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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
4c05b187 | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. |
32131a9c RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
ff2da9fc | 21 | #include <stdio.h> |
32131a9c RK |
22 | #include "config.h" |
23 | #include "rtl.h" | |
24 | #include "obstack.h" | |
25 | #include "insn-config.h" | |
26 | #include "insn-flags.h" | |
27 | #include "insn-codes.h" | |
28 | #include "flags.h" | |
29 | #include "expr.h" | |
30 | #include "regs.h" | |
31 | #include "hard-reg-set.h" | |
32 | #include "reload.h" | |
33 | #include "recog.h" | |
34 | #include "basic-block.h" | |
35 | #include "output.h" | |
32131a9c RK |
36 | |
37 | /* This file contains the reload pass of the compiler, which is | |
38 | run after register allocation has been done. It checks that | |
39 | each insn is valid (operands required to be in registers really | |
40 | are in registers of the proper class) and fixes up invalid ones | |
41 | by copying values temporarily into registers for the insns | |
42 | that need them. | |
43 | ||
44 | The results of register allocation are described by the vector | |
45 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
46 | can be used to find which hard reg, if any, a pseudo reg is in. | |
47 | ||
48 | The technique we always use is to free up a few hard regs that are | |
49 | called ``reload regs'', and for each place where a pseudo reg | |
50 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
51 | ||
52 | All the pseudos that were formerly allocated to the hard regs that | |
53 | are now in use as reload regs must be ``spilled''. This means | |
54 | that they go to other hard regs, or to stack slots if no other | |
55 | available hard regs can be found. Spilling can invalidate more | |
56 | insns, requiring additional need for reloads, so we must keep checking | |
57 | until the process stabilizes. | |
58 | ||
59 | For machines with different classes of registers, we must keep track | |
60 | of the register class needed for each reload, and make sure that | |
61 | we allocate enough reload registers of each class. | |
62 | ||
63 | The file reload.c contains the code that checks one insn for | |
64 | validity and reports the reloads that it needs. This file | |
65 | is in charge of scanning the entire rtl code, accumulating the | |
66 | reload needs, spilling, assigning reload registers to use for | |
67 | fixing up each insn, and generating the new insns to copy values | |
68 | into the reload registers. */ | |
546b63fb RK |
69 | |
70 | ||
71 | #ifndef REGISTER_MOVE_COST | |
72 | #define REGISTER_MOVE_COST(x, y) 2 | |
73 | #endif | |
74 | ||
75 | #ifndef MEMORY_MOVE_COST | |
76 | #define MEMORY_MOVE_COST(x) 4 | |
77 | #endif | |
32131a9c RK |
78 | \f |
79 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
d08ea79f | 80 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
81 | static rtx *reg_last_reload_reg; |
82 | ||
83 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
84 | for an output reload that stores into reg N. */ | |
85 | static char *reg_has_output_reload; | |
86 | ||
87 | /* Indicates which hard regs are reload-registers for an output reload | |
88 | in the current insn. */ | |
89 | static HARD_REG_SET reg_is_output_reload; | |
90 | ||
91 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
92 | or zero if pseudo reg N is not equivalent to a constant. | |
93 | find_reloads looks at this in order to replace pseudo reg N | |
94 | with the constant it stands for. */ | |
95 | rtx *reg_equiv_constant; | |
96 | ||
97 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
98 | prior to any register elimination (such as frame pointer to stack | |
99 | pointer). Depending on whether or not it is a valid address, this value | |
100 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 101 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
102 | |
103 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
104 | This is used when the address is not valid as a memory address | |
105 | (because its displacement is too big for the machine.) */ | |
106 | rtx *reg_equiv_address; | |
107 | ||
108 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
109 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
110 | rtx *reg_equiv_mem; | |
111 | ||
112 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
113 | static int *reg_max_ref_width; | |
114 | ||
115 | /* Element N is the insn that initialized reg N from its equivalent | |
116 | constant or memory slot. */ | |
117 | static rtx *reg_equiv_init; | |
118 | ||
119 | /* During reload_as_needed, element N contains the last pseudo regno | |
120 | reloaded into the Nth reload register. This vector is in parallel | |
121 | with spill_regs. If that pseudo reg occupied more than one register, | |
122 | reg_reloaded_contents points to that pseudo for each spill register in | |
123 | use; all of these must remain set for an inheritance to occur. */ | |
124 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
125 | ||
126 | /* During reload_as_needed, element N contains the insn for which | |
127 | the Nth reload register was last used. This vector is in parallel | |
128 | with spill_regs, and its contents are significant only when | |
129 | reg_reloaded_contents is significant. */ | |
130 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; | |
131 | ||
132 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ | |
133 | static int n_spills; | |
134 | ||
135 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
136 | Holds the last rtx used for any given reg, or 0 if it has never | |
137 | been used for spilling yet. This rtx is reused, provided it has | |
138 | the proper mode. */ | |
139 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
140 | ||
141 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
142 | that was stored after the last time it was used. | |
143 | The precise value is the insn generated to do the store. */ | |
144 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
145 | ||
146 | /* This table is the inverse mapping of spill_regs: | |
147 | indexed by hard reg number, | |
148 | it contains the position of that reg in spill_regs, | |
149 | or -1 for something that is not in spill_regs. */ | |
150 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; | |
151 | ||
152 | /* This reg set indicates registers that may not be used for retrying global | |
153 | allocation. The registers that may not be used include all spill registers | |
154 | and the frame pointer (if we are using one). */ | |
155 | HARD_REG_SET forbidden_regs; | |
156 | ||
157 | /* This reg set indicates registers that are not good for spill registers. | |
158 | They will not be used to complete groups of spill registers. This includes | |
546b63fb RK |
159 | all fixed registers, registers that may be eliminated, and, if |
160 | SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl. | |
32131a9c RK |
161 | |
162 | (spill_reg_order prevents these registers from being used to start a | |
163 | group.) */ | |
164 | static HARD_REG_SET bad_spill_regs; | |
165 | ||
166 | /* Describes order of use of registers for reloading | |
167 | of spilled pseudo-registers. `spills' is the number of | |
168 | elements that are actually valid; new ones are added at the end. */ | |
169 | static short spill_regs[FIRST_PSEUDO_REGISTER]; | |
170 | ||
171 | /* Describes order of preference for putting regs into spill_regs. | |
172 | Contains the numbers of all the hard regs, in order most preferred first. | |
173 | This order is different for each function. | |
174 | It is set up by order_regs_for_reload. | |
175 | Empty elements at the end contain -1. */ | |
176 | static short potential_reload_regs[FIRST_PSEUDO_REGISTER]; | |
177 | ||
178 | /* 1 for a hard register that appears explicitly in the rtl | |
179 | (for example, function value registers, special registers | |
180 | used by insns, structure value pointer registers). */ | |
181 | static char regs_explicitly_used[FIRST_PSEUDO_REGISTER]; | |
182 | ||
183 | /* Indicates if a register was counted against the need for | |
184 | groups. 0 means it can count against max_nongroup instead. */ | |
185 | static HARD_REG_SET counted_for_groups; | |
186 | ||
187 | /* Indicates if a register was counted against the need for | |
188 | non-groups. 0 means it can become part of a new group. | |
189 | During choose_reload_regs, 1 here means don't use this reg | |
190 | as part of a group, even if it seems to be otherwise ok. */ | |
191 | static HARD_REG_SET counted_for_nongroups; | |
192 | ||
193 | /* Nonzero if indirect addressing is supported on the machine; this means | |
194 | that spilling (REG n) does not require reloading it into a register in | |
195 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
196 | value indicates the level of indirect addressing supported, e.g., two | |
197 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
198 | a hard register. */ | |
199 | ||
200 | static char spill_indirect_levels; | |
201 | ||
202 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
203 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
204 | which these are valid is the same as spill_indirect_levels, above. */ | |
205 | ||
206 | char indirect_symref_ok; | |
207 | ||
208 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
209 | ||
210 | char double_reg_address_ok; | |
211 | ||
212 | /* Record the stack slot for each spilled hard register. */ | |
213 | ||
214 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; | |
215 | ||
216 | /* Width allocated so far for that stack slot. */ | |
217 | ||
218 | static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; | |
219 | ||
220 | /* Indexed by register class and basic block number, nonzero if there is | |
221 | any need for a spill register of that class in that basic block. | |
222 | The pointer is 0 if we did stupid allocation and don't know | |
223 | the structure of basic blocks. */ | |
224 | ||
225 | char *basic_block_needs[N_REG_CLASSES]; | |
226 | ||
227 | /* First uid used by insns created by reload in this function. | |
228 | Used in find_equiv_reg. */ | |
229 | int reload_first_uid; | |
230 | ||
231 | /* Flag set by local-alloc or global-alloc if anything is live in | |
232 | a call-clobbered reg across calls. */ | |
233 | ||
234 | int caller_save_needed; | |
235 | ||
236 | /* Set to 1 while reload_as_needed is operating. | |
237 | Required by some machines to handle any generated moves differently. */ | |
238 | ||
239 | int reload_in_progress = 0; | |
240 | ||
241 | /* These arrays record the insn_code of insns that may be needed to | |
242 | perform input and output reloads of special objects. They provide a | |
243 | place to pass a scratch register. */ | |
244 | ||
245 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; | |
246 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
247 | ||
d45cf215 | 248 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
249 | The allocated storage can be freed once find_reloads has processed the |
250 | insn. */ | |
251 | ||
252 | struct obstack reload_obstack; | |
253 | char *reload_firstobj; | |
254 | ||
255 | #define obstack_chunk_alloc xmalloc | |
256 | #define obstack_chunk_free free | |
257 | ||
32131a9c RK |
258 | /* List of labels that must never be deleted. */ |
259 | extern rtx forced_labels; | |
260 | \f | |
261 | /* This structure is used to record information about register eliminations. | |
262 | Each array entry describes one possible way of eliminating a register | |
263 | in favor of another. If there is more than one way of eliminating a | |
264 | particular register, the most preferred should be specified first. */ | |
265 | ||
266 | static struct elim_table | |
267 | { | |
268 | int from; /* Register number to be eliminated. */ | |
269 | int to; /* Register number used as replacement. */ | |
270 | int initial_offset; /* Initial difference between values. */ | |
271 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
272 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over | |
273 | insns made by reload. */ | |
274 | int offset; /* Current offset between the two regs. */ | |
a8efe40d | 275 | int max_offset; /* Maximum offset between the two regs. */ |
32131a9c RK |
276 | int previous_offset; /* Offset at end of previous insn. */ |
277 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
278 | rtx from_rtx; /* REG rtx for the register to be eliminated. | |
279 | We cannot simply compare the number since | |
280 | we might then spuriously replace a hard | |
281 | register corresponding to a pseudo | |
282 | assigned to the reg to be eliminated. */ | |
283 | rtx to_rtx; /* REG rtx for the replacement. */ | |
284 | } reg_eliminate[] = | |
285 | ||
286 | /* If a set of eliminable registers was specified, define the table from it. | |
287 | Otherwise, default to the normal case of the frame pointer being | |
288 | replaced by the stack pointer. */ | |
289 | ||
290 | #ifdef ELIMINABLE_REGS | |
291 | ELIMINABLE_REGS; | |
292 | #else | |
293 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
294 | #endif | |
295 | ||
296 | #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0]) | |
297 | ||
298 | /* Record the number of pending eliminations that have an offset not equal | |
299 | to their initial offset. If non-zero, we use a new copy of each | |
300 | replacement result in any insns encountered. */ | |
301 | static int num_not_at_initial_offset; | |
302 | ||
303 | /* Count the number of registers that we may be able to eliminate. */ | |
304 | static int num_eliminable; | |
305 | ||
306 | /* For each label, we record the offset of each elimination. If we reach | |
307 | a label by more than one path and an offset differs, we cannot do the | |
308 | elimination. This information is indexed by the number of the label. | |
309 | The first table is an array of flags that records whether we have yet | |
310 | encountered a label and the second table is an array of arrays, one | |
311 | entry in the latter array for each elimination. */ | |
312 | ||
313 | static char *offsets_known_at; | |
314 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
315 | ||
316 | /* Number of labels in the current function. */ | |
317 | ||
318 | static int num_labels; | |
546b63fb RK |
319 | |
320 | struct hard_reg_n_uses { int regno; int uses; }; | |
32131a9c | 321 | \f |
546b63fb RK |
322 | static int possible_group_p PROTO((int, int *)); |
323 | static void count_possible_groups PROTO((int *, enum machine_mode *, | |
324 | int *)); | |
325 | static int modes_equiv_for_class_p PROTO((enum machine_mode, | |
326 | enum machine_mode, | |
327 | enum reg_class)); | |
328 | static void spill_failure PROTO((rtx)); | |
329 | static int new_spill_reg PROTO((int, int, int *, int *, int, | |
330 | FILE *)); | |
331 | static void delete_dead_insn PROTO((rtx)); | |
332 | static void alter_reg PROTO((int, int)); | |
333 | static void set_label_offsets PROTO((rtx, rtx, int)); | |
334 | static int eliminate_regs_in_insn PROTO((rtx, int)); | |
335 | static void mark_not_eliminable PROTO((rtx, rtx)); | |
336 | static int spill_hard_reg PROTO((int, int, FILE *, int)); | |
337 | static void scan_paradoxical_subregs PROTO((rtx)); | |
338 | static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *, | |
339 | struct hard_reg_n_uses *)); | |
340 | static void order_regs_for_reload PROTO((void)); | |
341 | static void reload_as_needed PROTO((rtx, int)); | |
9a881562 | 342 | static void forget_old_reloads_1 PROTO((rtx, rtx)); |
546b63fb RK |
343 | static int reload_reg_class_lower PROTO((short *, short *)); |
344 | static void mark_reload_reg_in_use PROTO((int, int, enum reload_type, | |
345 | enum machine_mode)); | |
be7ae2a4 RK |
346 | static void clear_reload_reg_in_use PROTO((int, int, enum reload_type, |
347 | enum machine_mode)); | |
546b63fb RK |
348 | static int reload_reg_free_p PROTO((int, int, enum reload_type)); |
349 | static int reload_reg_free_before_p PROTO((int, int, enum reload_type)); | |
350 | static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type)); | |
351 | static int allocate_reload_reg PROTO((int, rtx, int, int)); | |
352 | static void choose_reload_regs PROTO((rtx, rtx)); | |
353 | static void merge_assigned_reloads PROTO((rtx)); | |
354 | static void emit_reload_insns PROTO((rtx)); | |
355 | static void delete_output_reload PROTO((rtx, int, rtx)); | |
356 | static void inc_for_reload PROTO((rtx, rtx, int)); | |
357 | static int constraint_accepts_reg_p PROTO((char *, rtx)); | |
358 | static int count_occurrences PROTO((rtx, rtx)); | |
32131a9c | 359 | \f |
546b63fb RK |
360 | /* Initialize the reload pass once per compilation. */ |
361 | ||
32131a9c RK |
362 | void |
363 | init_reload () | |
364 | { | |
365 | register int i; | |
366 | ||
367 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
368 | Set spill_indirect_levels to the number of levels such addressing is | |
369 | permitted, zero if it is not permitted at all. */ | |
370 | ||
371 | register rtx tem | |
372 | = gen_rtx (MEM, Pmode, | |
373 | gen_rtx (PLUS, Pmode, | |
374 | gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1), | |
fb3821f7 | 375 | GEN_INT (4))); |
32131a9c RK |
376 | spill_indirect_levels = 0; |
377 | ||
378 | while (memory_address_p (QImode, tem)) | |
379 | { | |
380 | spill_indirect_levels++; | |
381 | tem = gen_rtx (MEM, Pmode, tem); | |
382 | } | |
383 | ||
384 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
385 | ||
386 | tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo")); | |
387 | indirect_symref_ok = memory_address_p (QImode, tem); | |
388 | ||
389 | /* See if reg+reg is a valid (and offsettable) address. */ | |
390 | ||
65701fd2 | 391 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 RS |
392 | { |
393 | tem = gen_rtx (PLUS, Pmode, | |
394 | gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM), | |
395 | gen_rtx (REG, Pmode, i)); | |
396 | /* This way, we make sure that reg+reg is an offsettable address. */ | |
397 | tem = plus_constant (tem, 4); | |
398 | ||
399 | if (memory_address_p (QImode, tem)) | |
400 | { | |
401 | double_reg_address_ok = 1; | |
402 | break; | |
403 | } | |
404 | } | |
32131a9c RK |
405 | |
406 | /* Initialize obstack for our rtl allocation. */ | |
407 | gcc_obstack_init (&reload_obstack); | |
408 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
32131a9c RK |
409 | } |
410 | ||
546b63fb | 411 | /* Main entry point for the reload pass. |
32131a9c RK |
412 | |
413 | FIRST is the first insn of the function being compiled. | |
414 | ||
415 | GLOBAL nonzero means we were called from global_alloc | |
416 | and should attempt to reallocate any pseudoregs that we | |
417 | displace from hard regs we will use for reloads. | |
418 | If GLOBAL is zero, we do not have enough information to do that, | |
419 | so any pseudo reg that is spilled must go to the stack. | |
420 | ||
421 | DUMPFILE is the global-reg debugging dump file stream, or 0. | |
422 | If it is nonzero, messages are written to it to describe | |
423 | which registers are seized as reload regs, which pseudo regs | |
5352b11a | 424 | are spilled from them, and where the pseudo regs are reallocated to. |
32131a9c | 425 | |
5352b11a RS |
426 | Return value is nonzero if reload failed |
427 | and we must not do any more for this function. */ | |
428 | ||
429 | int | |
32131a9c RK |
430 | reload (first, global, dumpfile) |
431 | rtx first; | |
432 | int global; | |
433 | FILE *dumpfile; | |
434 | { | |
435 | register int class; | |
546b63fb | 436 | register int i, j; |
32131a9c RK |
437 | register rtx insn; |
438 | register struct elim_table *ep; | |
439 | ||
440 | int something_changed; | |
441 | int something_needs_reloads; | |
442 | int something_needs_elimination; | |
443 | int new_basic_block_needs; | |
a8efe40d RK |
444 | enum reg_class caller_save_spill_class = NO_REGS; |
445 | int caller_save_group_size = 1; | |
32131a9c | 446 | |
5352b11a RS |
447 | /* Nonzero means we couldn't get enough spill regs. */ |
448 | int failure = 0; | |
449 | ||
32131a9c RK |
450 | /* The basic block number currently being processed for INSN. */ |
451 | int this_block; | |
452 | ||
453 | /* Make sure even insns with volatile mem refs are recognizable. */ | |
454 | init_recog (); | |
455 | ||
456 | /* Enable find_equiv_reg to distinguish insns made by reload. */ | |
457 | reload_first_uid = get_max_uid (); | |
458 | ||
459 | for (i = 0; i < N_REG_CLASSES; i++) | |
460 | basic_block_needs[i] = 0; | |
461 | ||
0dadecf6 RK |
462 | #ifdef SECONDARY_MEMORY_NEEDED |
463 | /* Initialize the secondary memory table. */ | |
464 | clear_secondary_mem (); | |
465 | #endif | |
466 | ||
32131a9c RK |
467 | /* Remember which hard regs appear explicitly |
468 | before we merge into `regs_ever_live' the ones in which | |
469 | pseudo regs have been allocated. */ | |
470 | bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live); | |
471 | ||
472 | /* We don't have a stack slot for any spill reg yet. */ | |
473 | bzero (spill_stack_slot, sizeof spill_stack_slot); | |
474 | bzero (spill_stack_slot_width, sizeof spill_stack_slot_width); | |
475 | ||
a8efe40d RK |
476 | /* Initialize the save area information for caller-save, in case some |
477 | are needed. */ | |
478 | init_save_areas (); | |
a8fdc208 | 479 | |
32131a9c RK |
480 | /* Compute which hard registers are now in use |
481 | as homes for pseudo registers. | |
482 | This is done here rather than (eg) in global_alloc | |
483 | because this point is reached even if not optimizing. */ | |
484 | ||
485 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
486 | mark_home_live (i); | |
487 | ||
488 | /* Make sure that the last insn in the chain | |
489 | is not something that needs reloading. */ | |
fb3821f7 | 490 | emit_note (NULL_PTR, NOTE_INSN_DELETED); |
32131a9c RK |
491 | |
492 | /* Find all the pseudo registers that didn't get hard regs | |
493 | but do have known equivalent constants or memory slots. | |
494 | These include parameters (known equivalent to parameter slots) | |
495 | and cse'd or loop-moved constant memory addresses. | |
496 | ||
497 | Record constant equivalents in reg_equiv_constant | |
498 | so they will be substituted by find_reloads. | |
499 | Record memory equivalents in reg_mem_equiv so they can | |
500 | be substituted eventually by altering the REG-rtx's. */ | |
501 | ||
502 | reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx)); | |
503 | bzero (reg_equiv_constant, max_regno * sizeof (rtx)); | |
504 | reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx)); | |
505 | bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx)); | |
506 | reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx)); | |
507 | bzero (reg_equiv_mem, max_regno * sizeof (rtx)); | |
508 | reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx)); | |
509 | bzero (reg_equiv_init, max_regno * sizeof (rtx)); | |
510 | reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx)); | |
511 | bzero (reg_equiv_address, max_regno * sizeof (rtx)); | |
512 | reg_max_ref_width = (int *) alloca (max_regno * sizeof (int)); | |
513 | bzero (reg_max_ref_width, max_regno * sizeof (int)); | |
514 | ||
515 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. | |
516 | Also find all paradoxical subregs | |
517 | and find largest such for each pseudo. */ | |
518 | ||
519 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
520 | { | |
521 | rtx set = single_set (insn); | |
522 | ||
523 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) | |
524 | { | |
fb3821f7 | 525 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
526 | if (note |
527 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
a8fdc208 | 528 | && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic |
a8efe40d RK |
529 | || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) |
530 | #endif | |
531 | ) | |
32131a9c RK |
532 | { |
533 | rtx x = XEXP (note, 0); | |
534 | i = REGNO (SET_DEST (set)); | |
535 | if (i > LAST_VIRTUAL_REGISTER) | |
536 | { | |
537 | if (GET_CODE (x) == MEM) | |
538 | reg_equiv_memory_loc[i] = x; | |
539 | else if (CONSTANT_P (x)) | |
540 | { | |
541 | if (LEGITIMATE_CONSTANT_P (x)) | |
542 | reg_equiv_constant[i] = x; | |
543 | else | |
544 | reg_equiv_memory_loc[i] | |
d445b551 | 545 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
546 | } |
547 | else | |
548 | continue; | |
549 | ||
550 | /* If this register is being made equivalent to a MEM | |
551 | and the MEM is not SET_SRC, the equivalencing insn | |
552 | is one with the MEM as a SET_DEST and it occurs later. | |
553 | So don't mark this insn now. */ | |
554 | if (GET_CODE (x) != MEM | |
555 | || rtx_equal_p (SET_SRC (set), x)) | |
556 | reg_equiv_init[i] = insn; | |
557 | } | |
558 | } | |
559 | } | |
560 | ||
561 | /* If this insn is setting a MEM from a register equivalent to it, | |
562 | this is the equivalencing insn. */ | |
563 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
564 | && GET_CODE (SET_SRC (set)) == REG | |
565 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
566 | && rtx_equal_p (SET_DEST (set), | |
567 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
568 | reg_equiv_init[REGNO (SET_SRC (set))] = insn; | |
569 | ||
570 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
571 | scan_paradoxical_subregs (PATTERN (insn)); | |
572 | } | |
573 | ||
574 | /* Does this function require a frame pointer? */ | |
575 | ||
576 | frame_pointer_needed = (! flag_omit_frame_pointer | |
577 | #ifdef EXIT_IGNORE_STACK | |
578 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
579 | and restore sp for alloca. So we can't eliminate | |
580 | the frame pointer in that case. At some point, | |
581 | we should improve this by emitting the | |
582 | sp-adjusting insns for this case. */ | |
583 | || (current_function_calls_alloca | |
584 | && EXIT_IGNORE_STACK) | |
585 | #endif | |
586 | || FRAME_POINTER_REQUIRED); | |
587 | ||
588 | num_eliminable = 0; | |
589 | ||
590 | /* Initialize the table of registers to eliminate. The way we do this | |
591 | depends on how the eliminable registers were defined. */ | |
592 | #ifdef ELIMINABLE_REGS | |
593 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
594 | { | |
595 | ep->can_eliminate = ep->can_eliminate_previous | |
596 | = (CAN_ELIMINATE (ep->from, ep->to) | |
597 | && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed)); | |
598 | } | |
599 | #else | |
600 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous | |
601 | = ! frame_pointer_needed; | |
602 | #endif | |
603 | ||
604 | /* Count the number of eliminable registers and build the FROM and TO | |
a8fdc208 | 605 | REG rtx's. Note that code in gen_rtx will cause, e.g., |
32131a9c RK |
606 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. |
607 | We depend on this. */ | |
608 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
609 | { | |
610 | num_eliminable += ep->can_eliminate; | |
611 | ep->from_rtx = gen_rtx (REG, Pmode, ep->from); | |
612 | ep->to_rtx = gen_rtx (REG, Pmode, ep->to); | |
613 | } | |
614 | ||
615 | num_labels = max_label_num () - get_first_label_num (); | |
616 | ||
617 | /* Allocate the tables used to store offset information at labels. */ | |
618 | offsets_known_at = (char *) alloca (num_labels); | |
619 | offsets_at | |
620 | = (int (*)[NUM_ELIMINABLE_REGS]) | |
621 | alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); | |
622 | ||
623 | offsets_known_at -= get_first_label_num (); | |
624 | offsets_at -= get_first_label_num (); | |
625 | ||
626 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
627 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
628 | Do not touch virtual registers. */ | |
629 | ||
630 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
631 | alter_reg (i, -1); | |
632 | ||
633 | /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here | |
634 | because the stack size may be a part of the offset computation for | |
635 | register elimination. */ | |
636 | assign_stack_local (BLKmode, 0, 0); | |
637 | ||
638 | /* If we have some registers we think can be eliminated, scan all insns to | |
639 | see if there is an insn that sets one of these registers to something | |
640 | other than itself plus a constant. If so, the register cannot be | |
641 | eliminated. Doing this scan here eliminates an extra pass through the | |
642 | main reload loop in the most common case where register elimination | |
643 | cannot be done. */ | |
644 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
645 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
646 | || GET_CODE (insn) == CALL_INSN) | |
647 | note_stores (PATTERN (insn), mark_not_eliminable); | |
648 | ||
649 | #ifndef REGISTER_CONSTRAINTS | |
650 | /* If all the pseudo regs have hard regs, | |
651 | except for those that are never referenced, | |
652 | we know that no reloads are needed. */ | |
653 | /* But that is not true if there are register constraints, since | |
654 | in that case some pseudos might be in the wrong kind of hard reg. */ | |
655 | ||
656 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
657 | if (reg_renumber[i] == -1 && reg_n_refs[i] != 0) | |
658 | break; | |
659 | ||
b8093d02 | 660 | if (i == max_regno && num_eliminable == 0 && ! caller_save_needed) |
32131a9c RK |
661 | return; |
662 | #endif | |
663 | ||
664 | /* Compute the order of preference for hard registers to spill. | |
665 | Store them by decreasing preference in potential_reload_regs. */ | |
666 | ||
667 | order_regs_for_reload (); | |
668 | ||
669 | /* So far, no hard regs have been spilled. */ | |
670 | n_spills = 0; | |
671 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
672 | spill_reg_order[i] = -1; | |
673 | ||
674 | /* On most machines, we can't use any register explicitly used in the | |
675 | rtl as a spill register. But on some, we have to. Those will have | |
676 | taken care to keep the life of hard regs as short as possible. */ | |
677 | ||
678 | #ifdef SMALL_REGISTER_CLASSES | |
679 | CLEAR_HARD_REG_SET (forbidden_regs); | |
680 | #else | |
681 | COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs); | |
682 | #endif | |
683 | ||
684 | /* Spill any hard regs that we know we can't eliminate. */ | |
685 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
686 | if (! ep->can_eliminate) | |
687 | { | |
688 | spill_hard_reg (ep->from, global, dumpfile, 1); | |
689 | regs_ever_live[ep->from] = 1; | |
690 | } | |
691 | ||
692 | if (global) | |
693 | for (i = 0; i < N_REG_CLASSES; i++) | |
694 | { | |
695 | basic_block_needs[i] = (char *)alloca (n_basic_blocks); | |
696 | bzero (basic_block_needs[i], n_basic_blocks); | |
697 | } | |
698 | ||
b2f15f94 RK |
699 | /* From now on, we need to emit any moves without making new pseudos. */ |
700 | reload_in_progress = 1; | |
701 | ||
32131a9c RK |
702 | /* This loop scans the entire function each go-round |
703 | and repeats until one repetition spills no additional hard regs. */ | |
704 | ||
d45cf215 | 705 | /* This flag is set when a pseudo reg is spilled, |
32131a9c RK |
706 | to require another pass. Note that getting an additional reload |
707 | reg does not necessarily imply any pseudo reg was spilled; | |
708 | sometimes we find a reload reg that no pseudo reg was allocated in. */ | |
709 | something_changed = 1; | |
710 | /* This flag is set if there are any insns that require reloading. */ | |
711 | something_needs_reloads = 0; | |
712 | /* This flag is set if there are any insns that require register | |
713 | eliminations. */ | |
714 | something_needs_elimination = 0; | |
715 | while (something_changed) | |
716 | { | |
717 | rtx after_call = 0; | |
718 | ||
719 | /* For each class, number of reload regs needed in that class. | |
720 | This is the maximum over all insns of the needs in that class | |
721 | of the individual insn. */ | |
722 | int max_needs[N_REG_CLASSES]; | |
723 | /* For each class, size of group of consecutive regs | |
724 | that is needed for the reloads of this class. */ | |
725 | int group_size[N_REG_CLASSES]; | |
726 | /* For each class, max number of consecutive groups needed. | |
727 | (Each group contains group_size[CLASS] consecutive registers.) */ | |
728 | int max_groups[N_REG_CLASSES]; | |
729 | /* For each class, max number needed of regs that don't belong | |
730 | to any of the groups. */ | |
731 | int max_nongroups[N_REG_CLASSES]; | |
732 | /* For each class, the machine mode which requires consecutive | |
733 | groups of regs of that class. | |
734 | If two different modes ever require groups of one class, | |
735 | they must be the same size and equally restrictive for that class, | |
736 | otherwise we can't handle the complexity. */ | |
737 | enum machine_mode group_mode[N_REG_CLASSES]; | |
5352b11a RS |
738 | /* Record the insn where each maximum need is first found. */ |
739 | rtx max_needs_insn[N_REG_CLASSES]; | |
740 | rtx max_groups_insn[N_REG_CLASSES]; | |
741 | rtx max_nongroups_insn[N_REG_CLASSES]; | |
32131a9c | 742 | rtx x; |
0dadecf6 | 743 | int starting_frame_size = get_frame_size (); |
e404a39a | 744 | static char *reg_class_names[] = REG_CLASS_NAMES; |
32131a9c RK |
745 | |
746 | something_changed = 0; | |
747 | bzero (max_needs, sizeof max_needs); | |
748 | bzero (max_groups, sizeof max_groups); | |
749 | bzero (max_nongroups, sizeof max_nongroups); | |
5352b11a RS |
750 | bzero (max_needs_insn, sizeof max_needs_insn); |
751 | bzero (max_groups_insn, sizeof max_groups_insn); | |
752 | bzero (max_nongroups_insn, sizeof max_nongroups_insn); | |
32131a9c RK |
753 | bzero (group_size, sizeof group_size); |
754 | for (i = 0; i < N_REG_CLASSES; i++) | |
755 | group_mode[i] = VOIDmode; | |
756 | ||
757 | /* Keep track of which basic blocks are needing the reloads. */ | |
758 | this_block = 0; | |
759 | ||
760 | /* Remember whether any element of basic_block_needs | |
761 | changes from 0 to 1 in this pass. */ | |
762 | new_basic_block_needs = 0; | |
763 | ||
764 | /* Reset all offsets on eliminable registers to their initial values. */ | |
765 | #ifdef ELIMINABLE_REGS | |
766 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
767 | { | |
768 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
a8efe40d RK |
769 | ep->previous_offset = ep->offset |
770 | = ep->max_offset = ep->initial_offset; | |
32131a9c RK |
771 | } |
772 | #else | |
773 | #ifdef INITIAL_FRAME_POINTER_OFFSET | |
774 | INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); | |
775 | #else | |
776 | if (!FRAME_POINTER_REQUIRED) | |
777 | abort (); | |
778 | reg_eliminate[0].initial_offset = 0; | |
779 | #endif | |
a8efe40d | 780 | reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset |
32131a9c RK |
781 | = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; |
782 | #endif | |
783 | ||
784 | num_not_at_initial_offset = 0; | |
785 | ||
786 | bzero (&offsets_known_at[get_first_label_num ()], num_labels); | |
787 | ||
788 | /* Set a known offset for each forced label to be at the initial offset | |
789 | of each elimination. We do this because we assume that all | |
790 | computed jumps occur from a location where each elimination is | |
791 | at its initial offset. */ | |
792 | ||
793 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
794 | if (XEXP (x, 0)) | |
fb3821f7 | 795 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); |
32131a9c RK |
796 | |
797 | /* For each pseudo register that has an equivalent location defined, | |
798 | try to eliminate any eliminable registers (such as the frame pointer) | |
799 | assuming initial offsets for the replacement register, which | |
800 | is the normal case. | |
801 | ||
802 | If the resulting location is directly addressable, substitute | |
803 | the MEM we just got directly for the old REG. | |
804 | ||
805 | If it is not addressable but is a constant or the sum of a hard reg | |
806 | and constant, it is probably not addressable because the constant is | |
807 | out of range, in that case record the address; we will generate | |
808 | hairy code to compute the address in a register each time it is | |
a8fdc208 | 809 | needed. |
32131a9c RK |
810 | |
811 | If the location is not addressable, but does not have one of the | |
812 | above forms, assign a stack slot. We have to do this to avoid the | |
813 | potential of producing lots of reloads if, e.g., a location involves | |
814 | a pseudo that didn't get a hard register and has an equivalent memory | |
815 | location that also involves a pseudo that didn't get a hard register. | |
816 | ||
817 | Perhaps at some point we will improve reload_when_needed handling | |
818 | so this problem goes away. But that's very hairy. */ | |
819 | ||
820 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
821 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
822 | { | |
fb3821f7 | 823 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
824 | |
825 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
826 | XEXP (x, 0))) | |
827 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
828 | else if (CONSTANT_P (XEXP (x, 0)) | |
829 | || (GET_CODE (XEXP (x, 0)) == PLUS | |
830 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
831 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
832 | < FIRST_PSEUDO_REGISTER) | |
833 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
834 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
835 | else | |
836 | { | |
837 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 838 | changed so we go back and recompute offsets for |
32131a9c RK |
839 | eliminable registers because the allocation of memory |
840 | below might change some offset. reg_equiv_{mem,address} | |
841 | will be set up for this pseudo on the next pass around | |
842 | the loop. */ | |
843 | reg_equiv_memory_loc[i] = 0; | |
844 | reg_equiv_init[i] = 0; | |
845 | alter_reg (i, -1); | |
846 | something_changed = 1; | |
847 | } | |
848 | } | |
a8fdc208 | 849 | |
d45cf215 | 850 | /* If we allocated another pseudo to the stack, redo elimination |
32131a9c RK |
851 | bookkeeping. */ |
852 | if (something_changed) | |
853 | continue; | |
854 | ||
a8efe40d RK |
855 | /* If caller-saves needs a group, initialize the group to include |
856 | the size and mode required for caller-saves. */ | |
857 | ||
858 | if (caller_save_group_size > 1) | |
859 | { | |
860 | group_mode[(int) caller_save_spill_class] = Pmode; | |
861 | group_size[(int) caller_save_spill_class] = caller_save_group_size; | |
862 | } | |
863 | ||
32131a9c RK |
864 | /* Compute the most additional registers needed by any instruction. |
865 | Collect information separately for each class of regs. */ | |
866 | ||
867 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
868 | { | |
869 | if (global && this_block + 1 < n_basic_blocks | |
870 | && insn == basic_block_head[this_block+1]) | |
871 | ++this_block; | |
872 | ||
873 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which | |
874 | might include REG_LABEL), we need to see what effects this | |
875 | has on the known offsets at labels. */ | |
876 | ||
877 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
878 | || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
879 | && REG_NOTES (insn) != 0)) | |
880 | set_label_offsets (insn, insn, 0); | |
881 | ||
882 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
883 | { | |
884 | /* Nonzero means don't use a reload reg that overlaps | |
885 | the place where a function value can be returned. */ | |
886 | rtx avoid_return_reg = 0; | |
887 | ||
888 | rtx old_body = PATTERN (insn); | |
889 | int old_code = INSN_CODE (insn); | |
890 | rtx old_notes = REG_NOTES (insn); | |
891 | int did_elimination = 0; | |
546b63fb RK |
892 | int max_total_input_groups = 0, max_total_output_groups = 0; |
893 | ||
894 | /* To compute the number of reload registers of each class | |
895 | needed for an insn, we must similate what choose_reload_regs | |
896 | can do. We do this by splitting an insn into an "input" and | |
897 | an "output" part. RELOAD_OTHER reloads are used in both. | |
898 | The input part uses those reloads, RELOAD_FOR_INPUT reloads, | |
899 | which must be live over the entire input section of reloads, | |
900 | and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and | |
901 | RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the | |
902 | inputs. | |
903 | ||
904 | The registers needed for output are RELOAD_OTHER and | |
905 | RELOAD_FOR_OUTPUT, which are live for the entire output | |
906 | portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS | |
907 | reloads for each operand. | |
908 | ||
909 | The total number of registers needed is the maximum of the | |
910 | inputs and outputs. */ | |
911 | ||
912 | /* These just count RELOAD_OTHER. */ | |
32131a9c RK |
913 | int insn_needs[N_REG_CLASSES]; |
914 | int insn_groups[N_REG_CLASSES]; | |
915 | int insn_total_groups = 0; | |
916 | ||
546b63fb | 917 | /* Count RELOAD_FOR_INPUT reloads. */ |
32131a9c RK |
918 | int insn_needs_for_inputs[N_REG_CLASSES]; |
919 | int insn_groups_for_inputs[N_REG_CLASSES]; | |
920 | int insn_total_groups_for_inputs = 0; | |
921 | ||
546b63fb | 922 | /* Count RELOAD_FOR_OUTPUT reloads. */ |
32131a9c RK |
923 | int insn_needs_for_outputs[N_REG_CLASSES]; |
924 | int insn_groups_for_outputs[N_REG_CLASSES]; | |
925 | int insn_total_groups_for_outputs = 0; | |
926 | ||
546b63fb RK |
927 | /* Count RELOAD_FOR_INSN reloads. */ |
928 | int insn_needs_for_insn[N_REG_CLASSES]; | |
929 | int insn_groups_for_insn[N_REG_CLASSES]; | |
930 | int insn_total_groups_for_insn = 0; | |
931 | ||
932 | /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
933 | int insn_needs_for_other_addr[N_REG_CLASSES]; | |
934 | int insn_groups_for_other_addr[N_REG_CLASSES]; | |
935 | int insn_total_groups_for_other_addr = 0; | |
936 | ||
937 | /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */ | |
938 | int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; | |
939 | int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; | |
940 | int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS]; | |
941 | ||
942 | /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */ | |
943 | int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; | |
944 | int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES]; | |
945 | int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS]; | |
946 | ||
32131a9c | 947 | /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */ |
546b63fb RK |
948 | int insn_needs_for_op_addr[N_REG_CLASSES]; |
949 | int insn_groups_for_op_addr[N_REG_CLASSES]; | |
950 | int insn_total_groups_for_op_addr = 0; | |
32131a9c | 951 | |
32131a9c RK |
952 | #if 0 /* This wouldn't work nowadays, since optimize_bit_field |
953 | looks for non-strict memory addresses. */ | |
954 | /* Optimization: a bit-field instruction whose field | |
955 | happens to be a byte or halfword in memory | |
956 | can be changed to a move instruction. */ | |
957 | ||
958 | if (GET_CODE (PATTERN (insn)) == SET) | |
959 | { | |
960 | rtx dest = SET_DEST (PATTERN (insn)); | |
961 | rtx src = SET_SRC (PATTERN (insn)); | |
962 | ||
963 | if (GET_CODE (dest) == ZERO_EXTRACT | |
964 | || GET_CODE (dest) == SIGN_EXTRACT) | |
965 | optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); | |
966 | if (GET_CODE (src) == ZERO_EXTRACT | |
967 | || GET_CODE (src) == SIGN_EXTRACT) | |
968 | optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); | |
969 | } | |
970 | #endif | |
971 | ||
972 | /* If needed, eliminate any eliminable registers. */ | |
973 | if (num_eliminable) | |
974 | did_elimination = eliminate_regs_in_insn (insn, 0); | |
975 | ||
976 | #ifdef SMALL_REGISTER_CLASSES | |
977 | /* Set avoid_return_reg if this is an insn | |
978 | that might use the value of a function call. */ | |
979 | if (GET_CODE (insn) == CALL_INSN) | |
980 | { | |
981 | if (GET_CODE (PATTERN (insn)) == SET) | |
982 | after_call = SET_DEST (PATTERN (insn)); | |
983 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
984 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
985 | after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
986 | else | |
987 | after_call = 0; | |
988 | } | |
989 | else if (after_call != 0 | |
990 | && !(GET_CODE (PATTERN (insn)) == SET | |
991 | && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) | |
992 | { | |
993 | if (reg_mentioned_p (after_call, PATTERN (insn))) | |
994 | avoid_return_reg = after_call; | |
995 | after_call = 0; | |
996 | } | |
997 | #endif /* SMALL_REGISTER_CLASSES */ | |
998 | ||
999 | /* Analyze the instruction. */ | |
1000 | find_reloads (insn, 0, spill_indirect_levels, global, | |
1001 | spill_reg_order); | |
1002 | ||
1003 | /* Remember for later shortcuts which insns had any reloads or | |
1004 | register eliminations. | |
1005 | ||
1006 | One might think that it would be worthwhile to mark insns | |
1007 | that need register replacements but not reloads, but this is | |
1008 | not safe because find_reloads may do some manipulation of | |
1009 | the insn (such as swapping commutative operands), which would | |
1010 | be lost when we restore the old pattern after register | |
1011 | replacement. So the actions of find_reloads must be redone in | |
1012 | subsequent passes or in reload_as_needed. | |
1013 | ||
1014 | However, it is safe to mark insns that need reloads | |
1015 | but not register replacement. */ | |
1016 | ||
1017 | PUT_MODE (insn, (did_elimination ? QImode | |
1018 | : n_reloads ? HImode | |
546b63fb | 1019 | : GET_MODE (insn) == DImode ? DImode |
32131a9c RK |
1020 | : VOIDmode)); |
1021 | ||
1022 | /* Discard any register replacements done. */ | |
1023 | if (did_elimination) | |
1024 | { | |
1025 | obstack_free (&reload_obstack, reload_firstobj); | |
1026 | PATTERN (insn) = old_body; | |
1027 | INSN_CODE (insn) = old_code; | |
1028 | REG_NOTES (insn) = old_notes; | |
1029 | something_needs_elimination = 1; | |
1030 | } | |
1031 | ||
a8efe40d | 1032 | /* If this insn has no reloads, we need not do anything except |
a8fdc208 | 1033 | in the case of a CALL_INSN when we have caller-saves and |
a8efe40d RK |
1034 | caller-save needs reloads. */ |
1035 | ||
1036 | if (n_reloads == 0 | |
1037 | && ! (GET_CODE (insn) == CALL_INSN | |
1038 | && caller_save_spill_class != NO_REGS)) | |
32131a9c RK |
1039 | continue; |
1040 | ||
1041 | something_needs_reloads = 1; | |
1042 | ||
a8efe40d RK |
1043 | for (i = 0; i < N_REG_CLASSES; i++) |
1044 | { | |
1045 | insn_needs[i] = 0, insn_groups[i] = 0; | |
1046 | insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0; | |
1047 | insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0; | |
546b63fb RK |
1048 | insn_needs_for_insn[i] = 0, insn_groups_for_insn[i] = 0; |
1049 | insn_needs_for_op_addr[i] = 0, insn_groups_for_op_addr[i] = 0; | |
1050 | insn_needs_for_other_addr[i] = 0; | |
1051 | insn_groups_for_other_addr[i] = 0; | |
a8efe40d RK |
1052 | } |
1053 | ||
546b63fb RK |
1054 | for (i = 0; i < reload_n_operands; i++) |
1055 | { | |
1056 | insn_total_groups_for_in_addr[i] = 0; | |
1057 | insn_total_groups_for_out_addr[i] = 0; | |
1058 | ||
1059 | for (j = 0; j < N_REG_CLASSES; j++) | |
1060 | { | |
1061 | insn_needs_for_in_addr[i][j] = 0; | |
1062 | insn_needs_for_out_addr[i][j] = 0; | |
1063 | insn_groups_for_in_addr[i][j] = 0; | |
1064 | insn_groups_for_out_addr[i][j] = 0; | |
1065 | } | |
1066 | } | |
1067 | ||
32131a9c RK |
1068 | /* Count each reload once in every class |
1069 | containing the reload's own class. */ | |
1070 | ||
1071 | for (i = 0; i < n_reloads; i++) | |
1072 | { | |
1073 | register enum reg_class *p; | |
e85ddd99 | 1074 | enum reg_class class = reload_reg_class[i]; |
32131a9c RK |
1075 | int size; |
1076 | enum machine_mode mode; | |
1077 | int *this_groups; | |
1078 | int *this_needs; | |
1079 | int *this_total_groups; | |
1080 | ||
1081 | /* Don't count the dummy reloads, for which one of the | |
1082 | regs mentioned in the insn can be used for reloading. | |
1083 | Don't count optional reloads. | |
1084 | Don't count reloads that got combined with others. */ | |
1085 | if (reload_reg_rtx[i] != 0 | |
1086 | || reload_optional[i] != 0 | |
1087 | || (reload_out[i] == 0 && reload_in[i] == 0 | |
1088 | && ! reload_secondary_p[i])) | |
1089 | continue; | |
1090 | ||
e85ddd99 RK |
1091 | /* Show that a reload register of this class is needed |
1092 | in this basic block. We do not use insn_needs and | |
1093 | insn_groups because they are overly conservative for | |
1094 | this purpose. */ | |
1095 | if (global && ! basic_block_needs[(int) class][this_block]) | |
1096 | { | |
1097 | basic_block_needs[(int) class][this_block] = 1; | |
1098 | new_basic_block_needs = 1; | |
1099 | } | |
1100 | ||
32131a9c RK |
1101 | /* Decide which time-of-use to count this reload for. */ |
1102 | switch (reload_when_needed[i]) | |
1103 | { | |
1104 | case RELOAD_OTHER: | |
32131a9c RK |
1105 | this_needs = insn_needs; |
1106 | this_groups = insn_groups; | |
1107 | this_total_groups = &insn_total_groups; | |
1108 | break; | |
1109 | ||
546b63fb | 1110 | case RELOAD_FOR_INPUT: |
32131a9c RK |
1111 | this_needs = insn_needs_for_inputs; |
1112 | this_groups = insn_groups_for_inputs; | |
1113 | this_total_groups = &insn_total_groups_for_inputs; | |
1114 | break; | |
1115 | ||
546b63fb | 1116 | case RELOAD_FOR_OUTPUT: |
32131a9c RK |
1117 | this_needs = insn_needs_for_outputs; |
1118 | this_groups = insn_groups_for_outputs; | |
1119 | this_total_groups = &insn_total_groups_for_outputs; | |
1120 | break; | |
1121 | ||
546b63fb RK |
1122 | case RELOAD_FOR_INSN: |
1123 | this_needs = insn_needs_for_insn; | |
1124 | this_groups = insn_groups_for_outputs; | |
1125 | this_total_groups = &insn_total_groups_for_insn; | |
1126 | break; | |
1127 | ||
1128 | case RELOAD_FOR_OTHER_ADDRESS: | |
1129 | this_needs = insn_needs_for_other_addr; | |
1130 | this_groups = insn_groups_for_other_addr; | |
1131 | this_total_groups = &insn_total_groups_for_other_addr; | |
1132 | break; | |
1133 | ||
1134 | case RELOAD_FOR_INPUT_ADDRESS: | |
1135 | this_needs = insn_needs_for_in_addr[reload_opnum[i]]; | |
1136 | this_groups = insn_groups_for_in_addr[reload_opnum[i]]; | |
1137 | this_total_groups | |
1138 | = &insn_total_groups_for_in_addr[reload_opnum[i]]; | |
1139 | break; | |
1140 | ||
1141 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
1142 | this_needs = insn_needs_for_out_addr[reload_opnum[i]]; | |
1143 | this_groups = insn_groups_for_out_addr[reload_opnum[i]]; | |
1144 | this_total_groups | |
1145 | = &insn_total_groups_for_out_addr[reload_opnum[i]]; | |
1146 | break; | |
1147 | ||
32131a9c | 1148 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
1149 | this_needs = insn_needs_for_op_addr; |
1150 | this_groups = insn_groups_for_op_addr; | |
1151 | this_total_groups = &insn_total_groups_for_op_addr; | |
32131a9c RK |
1152 | break; |
1153 | } | |
1154 | ||
1155 | mode = reload_inmode[i]; | |
1156 | if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) | |
1157 | mode = reload_outmode[i]; | |
e85ddd99 | 1158 | size = CLASS_MAX_NREGS (class, mode); |
32131a9c RK |
1159 | if (size > 1) |
1160 | { | |
1161 | enum machine_mode other_mode, allocate_mode; | |
1162 | ||
1163 | /* Count number of groups needed separately from | |
1164 | number of individual regs needed. */ | |
e85ddd99 RK |
1165 | this_groups[(int) class]++; |
1166 | p = reg_class_superclasses[(int) class]; | |
32131a9c RK |
1167 | while (*p != LIM_REG_CLASSES) |
1168 | this_groups[(int) *p++]++; | |
1169 | (*this_total_groups)++; | |
1170 | ||
1171 | /* Record size and mode of a group of this class. */ | |
1172 | /* If more than one size group is needed, | |
1173 | make all groups the largest needed size. */ | |
e85ddd99 | 1174 | if (group_size[(int) class] < size) |
32131a9c | 1175 | { |
e85ddd99 | 1176 | other_mode = group_mode[(int) class]; |
32131a9c RK |
1177 | allocate_mode = mode; |
1178 | ||
e85ddd99 RK |
1179 | group_size[(int) class] = size; |
1180 | group_mode[(int) class] = mode; | |
32131a9c RK |
1181 | } |
1182 | else | |
1183 | { | |
1184 | other_mode = mode; | |
e85ddd99 | 1185 | allocate_mode = group_mode[(int) class]; |
32131a9c RK |
1186 | } |
1187 | ||
1188 | /* Crash if two dissimilar machine modes both need | |
1189 | groups of consecutive regs of the same class. */ | |
1190 | ||
1191 | if (other_mode != VOIDmode | |
1192 | && other_mode != allocate_mode | |
1193 | && ! modes_equiv_for_class_p (allocate_mode, | |
1194 | other_mode, | |
e85ddd99 | 1195 | class)) |
32131a9c RK |
1196 | abort (); |
1197 | } | |
1198 | else if (size == 1) | |
1199 | { | |
e85ddd99 RK |
1200 | this_needs[(int) class] += 1; |
1201 | p = reg_class_superclasses[(int) class]; | |
32131a9c RK |
1202 | while (*p != LIM_REG_CLASSES) |
1203 | this_needs[(int) *p++] += 1; | |
1204 | } | |
1205 | else | |
1206 | abort (); | |
1207 | } | |
1208 | ||
1209 | /* All reloads have been counted for this insn; | |
1210 | now merge the various times of use. | |
1211 | This sets insn_needs, etc., to the maximum total number | |
1212 | of registers needed at any point in this insn. */ | |
1213 | ||
1214 | for (i = 0; i < N_REG_CLASSES; i++) | |
1215 | { | |
546b63fb RK |
1216 | int in_max, out_max; |
1217 | ||
1218 | for (in_max = 0, out_max = 0, j = 0; | |
1219 | j < reload_n_operands; j++) | |
1220 | { | |
1221 | in_max = MAX (in_max, insn_needs_for_in_addr[j][i]); | |
1222 | out_max = MAX (out_max, insn_needs_for_out_addr[j][i]); | |
1223 | } | |
1224 | ||
1225 | /* RELOAD_FOR_INSN reloads conflict with inputs, outputs, | |
1226 | and operand addresses but not things used to reload them. | |
1227 | Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't | |
1228 | conflict with things needed to reload inputs or | |
1229 | outputs. */ | |
1230 | ||
1231 | in_max = MAX (in_max, insn_needs_for_op_addr[i]); | |
1232 | out_max = MAX (out_max, insn_needs_for_insn[i]); | |
1233 | ||
1234 | insn_needs_for_inputs[i] | |
1235 | = MAX (insn_needs_for_inputs[i] | |
1236 | + insn_needs_for_op_addr[i] | |
1237 | + insn_needs_for_insn[i], | |
1238 | in_max + insn_needs_for_inputs[i]); | |
1239 | ||
1240 | insn_needs_for_outputs[i] += out_max; | |
1241 | insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i], | |
1242 | insn_needs_for_outputs[i]), | |
1243 | insn_needs_for_other_addr[i]); | |
1244 | ||
1245 | for (in_max = 0, out_max = 0, j = 0; | |
1246 | j < reload_n_operands; j++) | |
1247 | { | |
1248 | in_max = MAX (in_max, insn_groups_for_in_addr[j][i]); | |
1249 | out_max = MAX (out_max, insn_groups_for_out_addr[j][i]); | |
1250 | } | |
1251 | ||
1252 | in_max = MAX (in_max, insn_groups_for_op_addr[i]); | |
1253 | out_max = MAX (out_max, insn_groups_for_insn[i]); | |
1254 | ||
1255 | insn_groups_for_inputs[i] | |
1256 | = MAX (insn_groups_for_inputs[i] | |
1257 | + insn_groups_for_op_addr[i] | |
1258 | + insn_groups_for_insn[i], | |
1259 | in_max + insn_groups_for_inputs[i]); | |
1260 | ||
1261 | insn_groups_for_outputs[i] += out_max; | |
1262 | insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i], | |
1263 | insn_groups_for_outputs[i]), | |
1264 | insn_groups_for_other_addr[i]); | |
1265 | } | |
1266 | ||
1267 | for (i = 0; i < reload_n_operands; i++) | |
1268 | { | |
1269 | max_total_input_groups | |
1270 | = MAX (max_total_input_groups, | |
1271 | insn_total_groups_for_in_addr[i]); | |
1272 | max_total_output_groups | |
1273 | = MAX (max_total_output_groups, | |
1274 | insn_total_groups_for_out_addr[i]); | |
32131a9c | 1275 | } |
a8efe40d | 1276 | |
546b63fb RK |
1277 | max_total_input_groups = MAX (max_total_input_groups, |
1278 | insn_total_groups_for_op_addr); | |
1279 | max_total_output_groups = MAX (max_total_output_groups, | |
1280 | insn_total_groups_for_insn); | |
1281 | ||
1282 | insn_total_groups_for_inputs | |
1283 | = MAX (max_total_input_groups + insn_total_groups_for_op_addr | |
1284 | + insn_total_groups_for_insn, | |
1285 | max_total_input_groups + insn_total_groups_for_inputs); | |
1286 | ||
1287 | insn_total_groups_for_outputs += max_total_output_groups; | |
1288 | ||
1289 | insn_total_groups += MAX (MAX (insn_total_groups_for_outputs, | |
1290 | insn_total_groups_for_inputs), | |
1291 | insn_total_groups_for_other_addr); | |
32131a9c | 1292 | |
a8efe40d RK |
1293 | /* If this is a CALL_INSN and caller-saves will need |
1294 | a spill register, act as if the spill register is | |
1295 | needed for this insn. However, the spill register | |
1296 | can be used by any reload of this insn, so we only | |
1297 | need do something if no need for that class has | |
a8fdc208 | 1298 | been recorded. |
a8efe40d RK |
1299 | |
1300 | The assumption that every CALL_INSN will trigger a | |
1301 | caller-save is highly conservative, however, the number | |
1302 | of cases where caller-saves will need a spill register but | |
1303 | a block containing a CALL_INSN won't need a spill register | |
1304 | of that class should be quite rare. | |
1305 | ||
1306 | If a group is needed, the size and mode of the group will | |
d45cf215 | 1307 | have been set up at the beginning of this loop. */ |
a8efe40d RK |
1308 | |
1309 | if (GET_CODE (insn) == CALL_INSN | |
1310 | && caller_save_spill_class != NO_REGS) | |
1311 | { | |
1312 | int *caller_save_needs | |
1313 | = (caller_save_group_size > 1 ? insn_groups : insn_needs); | |
1314 | ||
1315 | if (caller_save_needs[(int) caller_save_spill_class] == 0) | |
1316 | { | |
1317 | register enum reg_class *p | |
1318 | = reg_class_superclasses[(int) caller_save_spill_class]; | |
1319 | ||
1320 | caller_save_needs[(int) caller_save_spill_class]++; | |
1321 | ||
1322 | while (*p != LIM_REG_CLASSES) | |
0aaa6af8 | 1323 | caller_save_needs[(int) *p++] += 1; |
a8efe40d RK |
1324 | } |
1325 | ||
1326 | if (caller_save_group_size > 1) | |
1327 | insn_total_groups = MAX (insn_total_groups, 1); | |
d1c1397e RS |
1328 | |
1329 | ||
1330 | /* Show that this basic block will need a register of | |
1331 | this class. */ | |
1332 | ||
1333 | if (global | |
1334 | && ! (basic_block_needs[(int) caller_save_spill_class] | |
1335 | [this_block])) | |
1336 | { | |
1337 | basic_block_needs[(int) caller_save_spill_class] | |
1338 | [this_block] = 1; | |
1339 | new_basic_block_needs = 1; | |
1340 | } | |
a8efe40d RK |
1341 | } |
1342 | ||
32131a9c RK |
1343 | #ifdef SMALL_REGISTER_CLASSES |
1344 | /* If this insn stores the value of a function call, | |
1345 | and that value is in a register that has been spilled, | |
1346 | and if the insn needs a reload in a class | |
1347 | that might use that register as the reload register, | |
1348 | then add add an extra need in that class. | |
1349 | This makes sure we have a register available that does | |
1350 | not overlap the return value. */ | |
1351 | if (avoid_return_reg) | |
1352 | { | |
1353 | int regno = REGNO (avoid_return_reg); | |
1354 | int nregs | |
1355 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
1356 | int r; | |
546b63fb RK |
1357 | int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES]; |
1358 | ||
1359 | /* First compute the "basic needs", which counts a | |
1360 | need only in the smallest class in which it | |
1361 | is required. */ | |
1362 | ||
1363 | bcopy (insn_needs, basic_needs, sizeof basic_needs); | |
1364 | bcopy (insn_groups, basic_groups, sizeof basic_groups); | |
1365 | ||
1366 | for (i = 0; i < N_REG_CLASSES; i++) | |
1367 | { | |
1368 | enum reg_class *p; | |
1369 | ||
1370 | if (basic_needs[i] >= 0) | |
1371 | for (p = reg_class_superclasses[i]; | |
1372 | *p != LIM_REG_CLASSES; p++) | |
1373 | basic_needs[(int) *p] -= basic_needs[i]; | |
1374 | ||
1375 | if (basic_groups[i] >= 0) | |
1376 | for (p = reg_class_superclasses[i]; | |
1377 | *p != LIM_REG_CLASSES; p++) | |
1378 | basic_groups[(int) *p] -= basic_groups[i]; | |
1379 | } | |
1380 | ||
1381 | /* Now count extra regs if there might be a conflict with | |
1382 | the return value register. | |
1383 | ||
1384 | ??? This is not quite correct because we don't properly | |
1385 | handle the case of groups, but if we end up doing | |
1386 | something wrong, it either will end up not mattering or | |
1387 | we will abort elsewhere. */ | |
1388 | ||
32131a9c RK |
1389 | for (r = regno; r < regno + nregs; r++) |
1390 | if (spill_reg_order[r] >= 0) | |
1391 | for (i = 0; i < N_REG_CLASSES; i++) | |
1392 | if (TEST_HARD_REG_BIT (reg_class_contents[i], r)) | |
1393 | { | |
546b63fb RK |
1394 | if (basic_needs[i] > 0 || basic_groups[i] > 0) |
1395 | { | |
1396 | enum reg_class *p; | |
1397 | ||
1398 | insn_needs[i]++; | |
1399 | p = reg_class_superclasses[i]; | |
1400 | while (*p != LIM_REG_CLASSES) | |
1401 | insn_needs[(int) *p++]++; | |
1402 | } | |
32131a9c | 1403 | } |
32131a9c RK |
1404 | } |
1405 | #endif /* SMALL_REGISTER_CLASSES */ | |
1406 | ||
1407 | /* For each class, collect maximum need of any insn. */ | |
1408 | ||
1409 | for (i = 0; i < N_REG_CLASSES; i++) | |
1410 | { | |
1411 | if (max_needs[i] < insn_needs[i]) | |
5352b11a RS |
1412 | { |
1413 | max_needs[i] = insn_needs[i]; | |
1414 | max_needs_insn[i] = insn; | |
1415 | } | |
32131a9c | 1416 | if (max_groups[i] < insn_groups[i]) |
5352b11a RS |
1417 | { |
1418 | max_groups[i] = insn_groups[i]; | |
1419 | max_groups_insn[i] = insn; | |
1420 | } | |
32131a9c RK |
1421 | if (insn_total_groups > 0) |
1422 | if (max_nongroups[i] < insn_needs[i]) | |
5352b11a RS |
1423 | { |
1424 | max_nongroups[i] = insn_needs[i]; | |
1425 | max_nongroups_insn[i] = insn; | |
1426 | } | |
32131a9c RK |
1427 | } |
1428 | } | |
1429 | /* Note that there is a continue statement above. */ | |
1430 | } | |
1431 | ||
0dadecf6 RK |
1432 | /* If we allocated any new memory locations, make another pass |
1433 | since it might have changed elimination offsets. */ | |
1434 | if (starting_frame_size != get_frame_size ()) | |
1435 | something_changed = 1; | |
1436 | ||
e404a39a RK |
1437 | if (dumpfile) |
1438 | for (i = 0; i < N_REG_CLASSES; i++) | |
1439 | { | |
1440 | if (max_needs[i] > 0) | |
1441 | fprintf (dumpfile, | |
1442 | ";; Need %d reg%s of class %s (for insn %d).\n", | |
1443 | max_needs[i], max_needs[i] == 1 ? "" : "s", | |
1444 | reg_class_names[i], INSN_UID (max_needs_insn[i])); | |
1445 | if (max_nongroups[i] > 0) | |
1446 | fprintf (dumpfile, | |
1447 | ";; Need %d nongroup reg%s of class %s (for insn %d).\n", | |
1448 | max_nongroups[i], max_nongroups[i] == 1 ? "" : "s", | |
1449 | reg_class_names[i], INSN_UID (max_nongroups_insn[i])); | |
1450 | if (max_groups[i] > 0) | |
1451 | fprintf (dumpfile, | |
1452 | ";; Need %d group%s (%smode) of class %s (for insn %d).\n", | |
1453 | max_groups[i], max_groups[i] == 1 ? "" : "s", | |
1454 | mode_name[(int) group_mode[i]], | |
1455 | reg_class_names[i], INSN_UID (max_groups_insn[i])); | |
1456 | } | |
1457 | ||
d445b551 | 1458 | /* If we have caller-saves, set up the save areas and see if caller-save |
a8efe40d | 1459 | will need a spill register. */ |
32131a9c | 1460 | |
d445b551 | 1461 | if (caller_save_needed |
a8efe40d RK |
1462 | && ! setup_save_areas (&something_changed) |
1463 | && caller_save_spill_class == NO_REGS) | |
32131a9c | 1464 | { |
a8efe40d RK |
1465 | /* The class we will need depends on whether the machine |
1466 | supports the sum of two registers for an address; see | |
1467 | find_address_reloads for details. */ | |
1468 | ||
a8fdc208 | 1469 | caller_save_spill_class |
a8efe40d RK |
1470 | = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS; |
1471 | caller_save_group_size | |
1472 | = CLASS_MAX_NREGS (caller_save_spill_class, Pmode); | |
1473 | something_changed = 1; | |
32131a9c RK |
1474 | } |
1475 | ||
5c23c401 RK |
1476 | /* See if anything that happened changes which eliminations are valid. |
1477 | For example, on the Sparc, whether or not the frame pointer can | |
1478 | be eliminated can depend on what registers have been used. We need | |
1479 | not check some conditions again (such as flag_omit_frame_pointer) | |
1480 | since they can't have changed. */ | |
1481 | ||
1482 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1483 | if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
1484 | #ifdef ELIMINABLE_REGS | |
1485 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
1486 | #endif | |
1487 | ) | |
1488 | ep->can_eliminate = 0; | |
1489 | ||
32131a9c RK |
1490 | /* Look for the case where we have discovered that we can't replace |
1491 | register A with register B and that means that we will now be | |
1492 | trying to replace register A with register C. This means we can | |
1493 | no longer replace register C with register B and we need to disable | |
1494 | such an elimination, if it exists. This occurs often with A == ap, | |
1495 | B == sp, and C == fp. */ | |
a8fdc208 | 1496 | |
32131a9c RK |
1497 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
1498 | { | |
1499 | struct elim_table *op; | |
1500 | register int new_to = -1; | |
1501 | ||
1502 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
1503 | { | |
1504 | /* Find the current elimination for ep->from, if there is a | |
1505 | new one. */ | |
1506 | for (op = reg_eliminate; | |
1507 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
1508 | if (op->from == ep->from && op->can_eliminate) | |
1509 | { | |
1510 | new_to = op->to; | |
1511 | break; | |
1512 | } | |
1513 | ||
1514 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
1515 | disable it. */ | |
1516 | for (op = reg_eliminate; | |
1517 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
1518 | if (op->from == new_to && op->to == ep->to) | |
1519 | op->can_eliminate = 0; | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | /* See if any registers that we thought we could eliminate the previous | |
1524 | time are no longer eliminable. If so, something has changed and we | |
1525 | must spill the register. Also, recompute the number of eliminable | |
1526 | registers and see if the frame pointer is needed; it is if there is | |
1527 | no elimination of the frame pointer that we can perform. */ | |
1528 | ||
1529 | frame_pointer_needed = 1; | |
1530 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1531 | { | |
1532 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM) | |
1533 | frame_pointer_needed = 0; | |
1534 | ||
1535 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
1536 | { | |
1537 | ep->can_eliminate_previous = 0; | |
1538 | spill_hard_reg (ep->from, global, dumpfile, 1); | |
1539 | regs_ever_live[ep->from] = 1; | |
1540 | something_changed = 1; | |
1541 | num_eliminable--; | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | /* If all needs are met, we win. */ | |
1546 | ||
1547 | for (i = 0; i < N_REG_CLASSES; i++) | |
1548 | if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0) | |
1549 | break; | |
1550 | if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed) | |
1551 | break; | |
1552 | ||
546b63fb RK |
1553 | /* Not all needs are met; must spill some hard regs. */ |
1554 | ||
1555 | /* Put all registers spilled so far back in potential_reload_regs, but | |
1556 | put them at the front, since we've already spilled most of the | |
1557 | psuedos in them (we might have left some pseudos unspilled if they | |
1558 | were in a block that didn't need any spill registers of a conflicting | |
1559 | class. We used to try to mark off the need for those registers, | |
1560 | but doing so properly is very complex and reallocating them is the | |
1561 | simpler approach. First, "pack" potential_reload_regs by pushing | |
1562 | any nonnegative entries towards the end. That will leave room | |
1563 | for the registers we already spilled. | |
1564 | ||
1565 | Also, undo the marking of the spill registers from the last time | |
1566 | around in FORBIDDEN_REGS since we will be probably be allocating | |
1567 | them again below. | |
1568 | ||
1569 | ??? It is theoretically possible that we might end up not using one | |
1570 | of our previously-spilled registers in this allocation, even though | |
1571 | they are at the head of the list. It's not clear what to do about | |
1572 | this, but it was no better before, when we marked off the needs met | |
1573 | by the previously-spilled registers. With the current code, globals | |
1574 | can be allocated into these registers, but locals cannot. */ | |
1575 | ||
1576 | if (n_spills) | |
1577 | { | |
1578 | for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
1579 | if (potential_reload_regs[i] != -1) | |
1580 | potential_reload_regs[j--] = potential_reload_regs[i]; | |
32131a9c | 1581 | |
546b63fb RK |
1582 | for (i = 0; i < n_spills; i++) |
1583 | { | |
1584 | potential_reload_regs[i] = spill_regs[i]; | |
1585 | spill_reg_order[spill_regs[i]] = -1; | |
1586 | CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]); | |
1587 | } | |
32131a9c | 1588 | |
546b63fb RK |
1589 | n_spills = 0; |
1590 | } | |
32131a9c RK |
1591 | |
1592 | /* Now find more reload regs to satisfy the remaining need | |
1593 | Do it by ascending class number, since otherwise a reg | |
1594 | might be spilled for a big class and might fail to count | |
1595 | for a smaller class even though it belongs to that class. | |
1596 | ||
1597 | Count spilled regs in `spills', and add entries to | |
1598 | `spill_regs' and `spill_reg_order'. | |
1599 | ||
1600 | ??? Note there is a problem here. | |
1601 | When there is a need for a group in a high-numbered class, | |
1602 | and also need for non-group regs that come from a lower class, | |
1603 | the non-group regs are chosen first. If there aren't many regs, | |
1604 | they might leave no room for a group. | |
1605 | ||
1606 | This was happening on the 386. To fix it, we added the code | |
1607 | that calls possible_group_p, so that the lower class won't | |
1608 | break up the last possible group. | |
1609 | ||
1610 | Really fixing the problem would require changes above | |
1611 | in counting the regs already spilled, and in choose_reload_regs. | |
1612 | It might be hard to avoid introducing bugs there. */ | |
1613 | ||
546b63fb RK |
1614 | CLEAR_HARD_REG_SET (counted_for_groups); |
1615 | CLEAR_HARD_REG_SET (counted_for_nongroups); | |
1616 | ||
32131a9c RK |
1617 | for (class = 0; class < N_REG_CLASSES; class++) |
1618 | { | |
1619 | /* First get the groups of registers. | |
1620 | If we got single registers first, we might fragment | |
1621 | possible groups. */ | |
1622 | while (max_groups[class] > 0) | |
1623 | { | |
1624 | /* If any single spilled regs happen to form groups, | |
1625 | count them now. Maybe we don't really need | |
1626 | to spill another group. */ | |
1627 | count_possible_groups (group_size, group_mode, max_groups); | |
1628 | ||
93193ab5 RK |
1629 | if (max_groups[class] <= 0) |
1630 | break; | |
1631 | ||
32131a9c RK |
1632 | /* Groups of size 2 (the only groups used on most machines) |
1633 | are treated specially. */ | |
1634 | if (group_size[class] == 2) | |
1635 | { | |
1636 | /* First, look for a register that will complete a group. */ | |
1637 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1638 | { | |
32131a9c | 1639 | int other; |
546b63fb RK |
1640 | |
1641 | j = potential_reload_regs[i]; | |
32131a9c RK |
1642 | if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j) |
1643 | && | |
1644 | ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0) | |
1645 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
1646 | && TEST_HARD_REG_BIT (reg_class_contents[class], other) | |
1647 | && HARD_REGNO_MODE_OK (other, group_mode[class]) | |
1648 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
1649 | other) | |
1650 | /* We don't want one part of another group. | |
1651 | We could get "two groups" that overlap! */ | |
1652 | && ! TEST_HARD_REG_BIT (counted_for_groups, other)) | |
1653 | || | |
1654 | (j < FIRST_PSEUDO_REGISTER - 1 | |
1655 | && (other = j + 1, spill_reg_order[other] >= 0) | |
1656 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
1657 | && TEST_HARD_REG_BIT (reg_class_contents[class], other) | |
1658 | && HARD_REGNO_MODE_OK (j, group_mode[class]) | |
1659 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
1660 | other) | |
1661 | && ! TEST_HARD_REG_BIT (counted_for_groups, | |
1662 | other)))) | |
1663 | { | |
1664 | register enum reg_class *p; | |
1665 | ||
1666 | /* We have found one that will complete a group, | |
1667 | so count off one group as provided. */ | |
1668 | max_groups[class]--; | |
1669 | p = reg_class_superclasses[class]; | |
1670 | while (*p != LIM_REG_CLASSES) | |
1671 | max_groups[(int) *p++]--; | |
1672 | ||
1673 | /* Indicate both these regs are part of a group. */ | |
1674 | SET_HARD_REG_BIT (counted_for_groups, j); | |
1675 | SET_HARD_REG_BIT (counted_for_groups, other); | |
1676 | break; | |
1677 | } | |
1678 | } | |
1679 | /* We can't complete a group, so start one. */ | |
1680 | if (i == FIRST_PSEUDO_REGISTER) | |
1681 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1682 | { | |
57697575 | 1683 | int k; |
546b63fb | 1684 | j = potential_reload_regs[i]; |
57697575 RS |
1685 | /* Verify that J+1 is a potential reload reg. */ |
1686 | for (k = 0; k < FIRST_PSEUDO_REGISTER; k++) | |
1687 | if (potential_reload_regs[k] == j + 1) | |
1688 | break; | |
32131a9c | 1689 | if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER |
57697575 | 1690 | && k < FIRST_PSEUDO_REGISTER |
32131a9c RK |
1691 | && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0 |
1692 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
1693 | && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1) | |
1694 | && HARD_REGNO_MODE_OK (j, group_mode[class]) | |
1695 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
ee9f63c6 RS |
1696 | j + 1) |
1697 | && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)) | |
32131a9c RK |
1698 | break; |
1699 | } | |
1700 | ||
1701 | /* I should be the index in potential_reload_regs | |
1702 | of the new reload reg we have found. */ | |
1703 | ||
5352b11a RS |
1704 | if (i >= FIRST_PSEUDO_REGISTER) |
1705 | { | |
1706 | /* There are no groups left to spill. */ | |
1707 | spill_failure (max_groups_insn[class]); | |
1708 | failure = 1; | |
1709 | goto failed; | |
1710 | } | |
1711 | else | |
1712 | something_changed | |
fb3821f7 | 1713 | |= new_spill_reg (i, class, max_needs, NULL_PTR, |
5352b11a | 1714 | global, dumpfile); |
32131a9c RK |
1715 | } |
1716 | else | |
1717 | { | |
1718 | /* For groups of more than 2 registers, | |
1719 | look for a sufficient sequence of unspilled registers, | |
1720 | and spill them all at once. */ | |
1721 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1722 | { | |
32131a9c | 1723 | int k; |
546b63fb RK |
1724 | |
1725 | j = potential_reload_regs[i]; | |
9d1a4667 RS |
1726 | if (j >= 0 |
1727 | && j + group_size[class] <= FIRST_PSEUDO_REGISTER | |
32131a9c RK |
1728 | && HARD_REGNO_MODE_OK (j, group_mode[class])) |
1729 | { | |
1730 | /* Check each reg in the sequence. */ | |
1731 | for (k = 0; k < group_size[class]; k++) | |
1732 | if (! (spill_reg_order[j + k] < 0 | |
1733 | && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k) | |
1734 | && TEST_HARD_REG_BIT (reg_class_contents[class], j + k))) | |
1735 | break; | |
1736 | /* We got a full sequence, so spill them all. */ | |
1737 | if (k == group_size[class]) | |
1738 | { | |
1739 | register enum reg_class *p; | |
1740 | for (k = 0; k < group_size[class]; k++) | |
1741 | { | |
1742 | int idx; | |
1743 | SET_HARD_REG_BIT (counted_for_groups, j + k); | |
1744 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) | |
1745 | if (potential_reload_regs[idx] == j + k) | |
1746 | break; | |
9d1a4667 RS |
1747 | something_changed |
1748 | |= new_spill_reg (idx, class, | |
1749 | max_needs, NULL_PTR, | |
1750 | global, dumpfile); | |
32131a9c RK |
1751 | } |
1752 | ||
1753 | /* We have found one that will complete a group, | |
1754 | so count off one group as provided. */ | |
1755 | max_groups[class]--; | |
1756 | p = reg_class_superclasses[class]; | |
1757 | while (*p != LIM_REG_CLASSES) | |
1758 | max_groups[(int) *p++]--; | |
1759 | ||
1760 | break; | |
1761 | } | |
1762 | } | |
1763 | } | |
fa52261e | 1764 | /* We couldn't find any registers for this reload. |
9d1a4667 RS |
1765 | Avoid going into an infinite loop. */ |
1766 | if (i >= FIRST_PSEUDO_REGISTER) | |
1767 | { | |
1768 | /* There are no groups left. */ | |
1769 | spill_failure (max_groups_insn[class]); | |
1770 | failure = 1; | |
1771 | goto failed; | |
1772 | } | |
32131a9c RK |
1773 | } |
1774 | } | |
1775 | ||
1776 | /* Now similarly satisfy all need for single registers. */ | |
1777 | ||
1778 | while (max_needs[class] > 0 || max_nongroups[class] > 0) | |
1779 | { | |
1780 | /* Consider the potential reload regs that aren't | |
1781 | yet in use as reload regs, in order of preference. | |
1782 | Find the most preferred one that's in this class. */ | |
1783 | ||
1784 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1785 | if (potential_reload_regs[i] >= 0 | |
1786 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
1787 | potential_reload_regs[i]) | |
1788 | /* If this reg will not be available for groups, | |
1789 | pick one that does not foreclose possible groups. | |
1790 | This is a kludge, and not very general, | |
1791 | but it should be sufficient to make the 386 work, | |
1792 | and the problem should not occur on machines with | |
1793 | more registers. */ | |
1794 | && (max_nongroups[class] == 0 | |
1795 | || possible_group_p (potential_reload_regs[i], max_groups))) | |
1796 | break; | |
1797 | ||
e404a39a RK |
1798 | /* If we couldn't get a register, try to get one even if we |
1799 | might foreclose possible groups. This may cause problems | |
1800 | later, but that's better than aborting now, since it is | |
1801 | possible that we will, in fact, be able to form the needed | |
1802 | group even with this allocation. */ | |
1803 | ||
1804 | if (i >= FIRST_PSEUDO_REGISTER | |
1805 | && (asm_noperands (max_needs[class] > 0 | |
1806 | ? max_needs_insn[class] | |
1807 | : max_nongroups_insn[class]) | |
1808 | < 0)) | |
1809 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1810 | if (potential_reload_regs[i] >= 0 | |
1811 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
1812 | potential_reload_regs[i])) | |
1813 | break; | |
1814 | ||
32131a9c RK |
1815 | /* I should be the index in potential_reload_regs |
1816 | of the new reload reg we have found. */ | |
1817 | ||
5352b11a RS |
1818 | if (i >= FIRST_PSEUDO_REGISTER) |
1819 | { | |
1820 | /* There are no possible registers left to spill. */ | |
1821 | spill_failure (max_needs[class] > 0 ? max_needs_insn[class] | |
1822 | : max_nongroups_insn[class]); | |
1823 | failure = 1; | |
1824 | goto failed; | |
1825 | } | |
1826 | else | |
1827 | something_changed | |
1828 | |= new_spill_reg (i, class, max_needs, max_nongroups, | |
1829 | global, dumpfile); | |
32131a9c RK |
1830 | } |
1831 | } | |
1832 | } | |
1833 | ||
1834 | /* If global-alloc was run, notify it of any register eliminations we have | |
1835 | done. */ | |
1836 | if (global) | |
1837 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1838 | if (ep->can_eliminate) | |
1839 | mark_elimination (ep->from, ep->to); | |
1840 | ||
32131a9c | 1841 | /* Insert code to save and restore call-clobbered hard regs |
a8efe40d RK |
1842 | around calls. Tell if what mode to use so that we will process |
1843 | those insns in reload_as_needed if we have to. */ | |
32131a9c RK |
1844 | |
1845 | if (caller_save_needed) | |
a8efe40d RK |
1846 | save_call_clobbered_regs (num_eliminable ? QImode |
1847 | : caller_save_spill_class != NO_REGS ? HImode | |
1848 | : VOIDmode); | |
32131a9c RK |
1849 | |
1850 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. | |
1851 | If that insn didn't set the register (i.e., it copied the register to | |
1852 | memory), just delete that insn instead of the equivalencing insn plus | |
1853 | anything now dead. If we call delete_dead_insn on that insn, we may | |
1854 | delete the insn that actually sets the register if the register die | |
1855 | there and that is incorrect. */ | |
1856 | ||
1857 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1858 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0 | |
1859 | && GET_CODE (reg_equiv_init[i]) != NOTE) | |
1860 | { | |
1861 | if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i]))) | |
1862 | delete_dead_insn (reg_equiv_init[i]); | |
1863 | else | |
1864 | { | |
1865 | PUT_CODE (reg_equiv_init[i], NOTE); | |
1866 | NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0; | |
1867 | NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED; | |
1868 | } | |
1869 | } | |
1870 | ||
1871 | /* Use the reload registers where necessary | |
1872 | by generating move instructions to move the must-be-register | |
1873 | values into or out of the reload registers. */ | |
1874 | ||
a8efe40d RK |
1875 | if (something_needs_reloads || something_needs_elimination |
1876 | || (caller_save_needed && num_eliminable) | |
1877 | || caller_save_spill_class != NO_REGS) | |
32131a9c RK |
1878 | reload_as_needed (first, global); |
1879 | ||
2a1f8b6b | 1880 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1881 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1882 | virtue of being in a pseudo, that pseudo will be marked live |
1883 | and hence the frame pointer will be known to be live via that | |
1884 | pseudo. */ | |
1885 | ||
1886 | if (! frame_pointer_needed) | |
1887 | for (i = 0; i < n_basic_blocks; i++) | |
1888 | basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS] | |
1889 | &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS)); | |
1890 | ||
5352b11a RS |
1891 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1892 | and we decide not to abort about it. */ | |
1893 | failed: | |
1894 | ||
a3ec87a8 RS |
1895 | reload_in_progress = 0; |
1896 | ||
32131a9c RK |
1897 | /* Now eliminate all pseudo regs by modifying them into |
1898 | their equivalent memory references. | |
1899 | The REG-rtx's for the pseudos are modified in place, | |
1900 | so all insns that used to refer to them now refer to memory. | |
1901 | ||
1902 | For a reg that has a reg_equiv_address, all those insns | |
1903 | were changed by reloading so that no insns refer to it any longer; | |
1904 | but the DECL_RTL of a variable decl may refer to it, | |
1905 | and if so this causes the debugging info to mention the variable. */ | |
1906 | ||
1907 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1908 | { | |
1909 | rtx addr = 0; | |
ab1fd483 | 1910 | int in_struct = 0; |
32131a9c | 1911 | if (reg_equiv_mem[i]) |
ab1fd483 RS |
1912 | { |
1913 | addr = XEXP (reg_equiv_mem[i], 0); | |
1914 | in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]); | |
1915 | } | |
32131a9c RK |
1916 | if (reg_equiv_address[i]) |
1917 | addr = reg_equiv_address[i]; | |
1918 | if (addr) | |
1919 | { | |
1920 | if (reg_renumber[i] < 0) | |
1921 | { | |
1922 | rtx reg = regno_reg_rtx[i]; | |
1923 | XEXP (reg, 0) = addr; | |
1924 | REG_USERVAR_P (reg) = 0; | |
ab1fd483 | 1925 | MEM_IN_STRUCT_P (reg) = in_struct; |
32131a9c RK |
1926 | PUT_CODE (reg, MEM); |
1927 | } | |
1928 | else if (reg_equiv_mem[i]) | |
1929 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
1934 | /* Make a pass over all the insns and remove death notes for things that | |
1935 | are no longer registers or no longer die in the insn (e.g., an input | |
1936 | and output pseudo being tied). */ | |
1937 | ||
1938 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1939 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1940 | { | |
1941 | rtx note, next; | |
1942 | ||
1943 | for (note = REG_NOTES (insn); note; note = next) | |
1944 | { | |
1945 | next = XEXP (note, 1); | |
1946 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1947 | && (GET_CODE (XEXP (note, 0)) != REG | |
1948 | || reg_set_p (XEXP (note, 0), PATTERN (insn)))) | |
1949 | remove_note (insn, note); | |
1950 | } | |
1951 | } | |
1952 | #endif | |
1953 | ||
1954 | /* Indicate that we no longer have known memory locations or constants. */ | |
1955 | reg_equiv_constant = 0; | |
1956 | reg_equiv_memory_loc = 0; | |
5352b11a RS |
1957 | |
1958 | return failure; | |
32131a9c RK |
1959 | } |
1960 | \f | |
1961 | /* Nonzero if, after spilling reg REGNO for non-groups, | |
1962 | it will still be possible to find a group if we still need one. */ | |
1963 | ||
1964 | static int | |
1965 | possible_group_p (regno, max_groups) | |
1966 | int regno; | |
1967 | int *max_groups; | |
1968 | { | |
1969 | int i; | |
1970 | int class = (int) NO_REGS; | |
1971 | ||
1972 | for (i = 0; i < (int) N_REG_CLASSES; i++) | |
1973 | if (max_groups[i] > 0) | |
1974 | { | |
1975 | class = i; | |
1976 | break; | |
1977 | } | |
1978 | ||
1979 | if (class == (int) NO_REGS) | |
1980 | return 1; | |
1981 | ||
1982 | /* Consider each pair of consecutive registers. */ | |
1983 | for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++) | |
1984 | { | |
1985 | /* Ignore pairs that include reg REGNO. */ | |
1986 | if (i == regno || i + 1 == regno) | |
1987 | continue; | |
1988 | ||
1989 | /* Ignore pairs that are outside the class that needs the group. | |
1990 | ??? Here we fail to handle the case where two different classes | |
1991 | independently need groups. But this never happens with our | |
1992 | current machine descriptions. */ | |
1993 | if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i) | |
1994 | && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1))) | |
1995 | continue; | |
1996 | ||
1997 | /* A pair of consecutive regs we can still spill does the trick. */ | |
1998 | if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0 | |
1999 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i) | |
2000 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)) | |
2001 | return 1; | |
2002 | ||
2003 | /* A pair of one already spilled and one we can spill does it | |
2004 | provided the one already spilled is not otherwise reserved. */ | |
2005 | if (spill_reg_order[i] < 0 | |
2006 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i) | |
2007 | && spill_reg_order[i + 1] >= 0 | |
2008 | && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1) | |
2009 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1)) | |
2010 | return 1; | |
2011 | if (spill_reg_order[i + 1] < 0 | |
2012 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1) | |
2013 | && spill_reg_order[i] >= 0 | |
2014 | && ! TEST_HARD_REG_BIT (counted_for_groups, i) | |
2015 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, i)) | |
2016 | return 1; | |
2017 | } | |
2018 | ||
2019 | return 0; | |
2020 | } | |
2021 | \f | |
2022 | /* Count any groups that can be formed from the registers recently spilled. | |
2023 | This is done class by class, in order of ascending class number. */ | |
2024 | ||
2025 | static void | |
2026 | count_possible_groups (group_size, group_mode, max_groups) | |
546b63fb | 2027 | int *group_size; |
32131a9c | 2028 | enum machine_mode *group_mode; |
546b63fb | 2029 | int *max_groups; |
32131a9c RK |
2030 | { |
2031 | int i; | |
2032 | /* Now find all consecutive groups of spilled registers | |
2033 | and mark each group off against the need for such groups. | |
2034 | But don't count them against ordinary need, yet. */ | |
2035 | ||
2036 | for (i = 0; i < N_REG_CLASSES; i++) | |
2037 | if (group_size[i] > 1) | |
2038 | { | |
93193ab5 | 2039 | HARD_REG_SET new; |
32131a9c RK |
2040 | int j; |
2041 | ||
93193ab5 RK |
2042 | CLEAR_HARD_REG_SET (new); |
2043 | ||
32131a9c RK |
2044 | /* Make a mask of all the regs that are spill regs in class I. */ |
2045 | for (j = 0; j < n_spills; j++) | |
2046 | if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j]) | |
2047 | && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j]) | |
2048 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
2049 | spill_regs[j])) | |
93193ab5 RK |
2050 | SET_HARD_REG_BIT (new, spill_regs[j]); |
2051 | ||
32131a9c RK |
2052 | /* Find each consecutive group of them. */ |
2053 | for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++) | |
93193ab5 RK |
2054 | if (TEST_HARD_REG_BIT (new, j) |
2055 | && j + group_size[i] <= FIRST_PSEUDO_REGISTER | |
32131a9c RK |
2056 | /* Next line in case group-mode for this class |
2057 | demands an even-odd pair. */ | |
2058 | && HARD_REGNO_MODE_OK (j, group_mode[i])) | |
2059 | { | |
2060 | int k; | |
2061 | for (k = 1; k < group_size[i]; k++) | |
93193ab5 | 2062 | if (! TEST_HARD_REG_BIT (new, j + k)) |
32131a9c RK |
2063 | break; |
2064 | if (k == group_size[i]) | |
2065 | { | |
2066 | /* We found a group. Mark it off against this class's | |
2067 | need for groups, and against each superclass too. */ | |
2068 | register enum reg_class *p; | |
2069 | max_groups[i]--; | |
2070 | p = reg_class_superclasses[i]; | |
2071 | while (*p != LIM_REG_CLASSES) | |
2072 | max_groups[(int) *p++]--; | |
a8fdc208 | 2073 | /* Don't count these registers again. */ |
32131a9c RK |
2074 | for (k = 0; k < group_size[i]; k++) |
2075 | SET_HARD_REG_BIT (counted_for_groups, j + k); | |
2076 | } | |
fa52261e RS |
2077 | /* Skip to the last reg in this group. When j is incremented |
2078 | above, it will then point to the first reg of the next | |
2079 | possible group. */ | |
2080 | j += k - 1; | |
32131a9c RK |
2081 | } |
2082 | } | |
2083 | ||
2084 | } | |
2085 | \f | |
2086 | /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is | |
2087 | another mode that needs to be reloaded for the same register class CLASS. | |
2088 | If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail. | |
2089 | ALLOCATE_MODE will never be smaller than OTHER_MODE. | |
2090 | ||
2091 | This code used to also fail if any reg in CLASS allows OTHER_MODE but not | |
2092 | ALLOCATE_MODE. This test is unnecessary, because we will never try to put | |
2093 | something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this | |
2094 | causes unnecessary failures on machines requiring alignment of register | |
2095 | groups when the two modes are different sizes, because the larger mode has | |
2096 | more strict alignment rules than the smaller mode. */ | |
2097 | ||
2098 | static int | |
2099 | modes_equiv_for_class_p (allocate_mode, other_mode, class) | |
2100 | enum machine_mode allocate_mode, other_mode; | |
2101 | enum reg_class class; | |
2102 | { | |
2103 | register int regno; | |
2104 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
2105 | { | |
2106 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
2107 | && HARD_REGNO_MODE_OK (regno, allocate_mode) | |
2108 | && ! HARD_REGNO_MODE_OK (regno, other_mode)) | |
2109 | return 0; | |
2110 | } | |
2111 | return 1; | |
2112 | } | |
2113 | ||
5352b11a RS |
2114 | /* Handle the failure to find a register to spill. |
2115 | INSN should be one of the insns which needed this particular spill reg. */ | |
2116 | ||
2117 | static void | |
2118 | spill_failure (insn) | |
2119 | rtx insn; | |
2120 | { | |
2121 | if (asm_noperands (PATTERN (insn)) >= 0) | |
2122 | error_for_asm (insn, "`asm' needs too many reloads"); | |
2123 | else | |
2124 | abort (); | |
2125 | } | |
2126 | ||
32131a9c RK |
2127 | /* Add a new register to the tables of available spill-registers |
2128 | (as well as spilling all pseudos allocated to the register). | |
2129 | I is the index of this register in potential_reload_regs. | |
2130 | CLASS is the regclass whose need is being satisfied. | |
2131 | MAX_NEEDS and MAX_NONGROUPS are the vectors of needs, | |
2132 | so that this register can count off against them. | |
2133 | MAX_NONGROUPS is 0 if this register is part of a group. | |
2134 | GLOBAL and DUMPFILE are the same as the args that `reload' got. */ | |
2135 | ||
2136 | static int | |
2137 | new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile) | |
2138 | int i; | |
2139 | int class; | |
2140 | int *max_needs; | |
2141 | int *max_nongroups; | |
2142 | int global; | |
2143 | FILE *dumpfile; | |
2144 | { | |
2145 | register enum reg_class *p; | |
2146 | int val; | |
2147 | int regno = potential_reload_regs[i]; | |
2148 | ||
2149 | if (i >= FIRST_PSEUDO_REGISTER) | |
2150 | abort (); /* Caller failed to find any register. */ | |
2151 | ||
2152 | if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno)) | |
2153 | fatal ("fixed or forbidden register was spilled.\n\ | |
2154 | This may be due to a compiler bug or to impossible asm statements."); | |
2155 | ||
2156 | /* Make reg REGNO an additional reload reg. */ | |
2157 | ||
2158 | potential_reload_regs[i] = -1; | |
2159 | spill_regs[n_spills] = regno; | |
2160 | spill_reg_order[regno] = n_spills; | |
2161 | if (dumpfile) | |
2162 | fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]); | |
2163 | ||
2164 | /* Clear off the needs we just satisfied. */ | |
2165 | ||
2166 | max_needs[class]--; | |
2167 | p = reg_class_superclasses[class]; | |
2168 | while (*p != LIM_REG_CLASSES) | |
2169 | max_needs[(int) *p++]--; | |
2170 | ||
2171 | if (max_nongroups && max_nongroups[class] > 0) | |
2172 | { | |
2173 | SET_HARD_REG_BIT (counted_for_nongroups, regno); | |
2174 | max_nongroups[class]--; | |
2175 | p = reg_class_superclasses[class]; | |
2176 | while (*p != LIM_REG_CLASSES) | |
2177 | max_nongroups[(int) *p++]--; | |
2178 | } | |
2179 | ||
2180 | /* Spill every pseudo reg that was allocated to this reg | |
2181 | or to something that overlaps this reg. */ | |
2182 | ||
2183 | val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0); | |
2184 | ||
2185 | /* If there are some registers still to eliminate and this register | |
2186 | wasn't ever used before, additional stack space may have to be | |
2187 | allocated to store this register. Thus, we may have changed the offset | |
2188 | between the stack and frame pointers, so mark that something has changed. | |
2189 | (If new pseudos were spilled, thus requiring more space, VAL would have | |
2190 | been set non-zero by the call to spill_hard_reg above since additional | |
2191 | reloads may be needed in that case. | |
2192 | ||
2193 | One might think that we need only set VAL to 1 if this is a call-used | |
2194 | register. However, the set of registers that must be saved by the | |
2195 | prologue is not identical to the call-used set. For example, the | |
2196 | register used by the call insn for the return PC is a call-used register, | |
2197 | but must be saved by the prologue. */ | |
2198 | if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]]) | |
2199 | val = 1; | |
2200 | ||
2201 | regs_ever_live[spill_regs[n_spills]] = 1; | |
2202 | n_spills++; | |
2203 | ||
2204 | return val; | |
2205 | } | |
2206 | \f | |
2207 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
2208 | data that is dead in INSN. */ | |
2209 | ||
2210 | static void | |
2211 | delete_dead_insn (insn) | |
2212 | rtx insn; | |
2213 | { | |
2214 | rtx prev = prev_real_insn (insn); | |
2215 | rtx prev_dest; | |
2216 | ||
2217 | /* If the previous insn sets a register that dies in our insn, delete it | |
2218 | too. */ | |
2219 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
2220 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
2221 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
2222 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))) | |
2223 | delete_dead_insn (prev); | |
2224 | ||
2225 | PUT_CODE (insn, NOTE); | |
2226 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2227 | NOTE_SOURCE_FILE (insn) = 0; | |
2228 | } | |
2229 | ||
2230 | /* Modify the home of pseudo-reg I. | |
2231 | The new home is present in reg_renumber[I]. | |
2232 | ||
2233 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
2234 | or it may be -1, meaning there is none or it is not relevant. | |
2235 | This is used so that all pseudos spilled from a given hard reg | |
2236 | can share one stack slot. */ | |
2237 | ||
2238 | static void | |
2239 | alter_reg (i, from_reg) | |
2240 | register int i; | |
2241 | int from_reg; | |
2242 | { | |
2243 | /* When outputting an inline function, this can happen | |
2244 | for a reg that isn't actually used. */ | |
2245 | if (regno_reg_rtx[i] == 0) | |
2246 | return; | |
2247 | ||
2248 | /* If the reg got changed to a MEM at rtl-generation time, | |
2249 | ignore it. */ | |
2250 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
2251 | return; | |
2252 | ||
2253 | /* Modify the reg-rtx to contain the new hard reg | |
2254 | number or else to contain its pseudo reg number. */ | |
2255 | REGNO (regno_reg_rtx[i]) | |
2256 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
2257 | ||
2258 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
2259 | allocate a stack slot for it. */ | |
2260 | ||
2261 | if (reg_renumber[i] < 0 | |
2262 | && reg_n_refs[i] > 0 | |
2263 | && reg_equiv_constant[i] == 0 | |
2264 | && reg_equiv_memory_loc[i] == 0) | |
2265 | { | |
2266 | register rtx x; | |
2267 | int inherent_size = PSEUDO_REGNO_BYTES (i); | |
2268 | int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
2269 | int adjust = 0; | |
2270 | ||
2271 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
2272 | and a total size which provides room for paradoxical subregs | |
2273 | which refer to the pseudo reg in wider modes. | |
2274 | ||
2275 | We can use a slot already allocated if it provides both | |
2276 | enough inherent space and enough total space. | |
2277 | Otherwise, we allocate a new slot, making sure that it has no less | |
2278 | inherent space, and no less total space, then the previous slot. */ | |
2279 | if (from_reg == -1) | |
2280 | { | |
2281 | /* No known place to spill from => no slot to reuse. */ | |
2282 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1); | |
2283 | #if BYTES_BIG_ENDIAN | |
2284 | /* Cancel the big-endian correction done in assign_stack_local. | |
2285 | Get the address of the beginning of the slot. | |
2286 | This is so we can do a big-endian correction unconditionally | |
2287 | below. */ | |
2288 | adjust = inherent_size - total_size; | |
2289 | #endif | |
2290 | } | |
2291 | /* Reuse a stack slot if possible. */ | |
2292 | else if (spill_stack_slot[from_reg] != 0 | |
2293 | && spill_stack_slot_width[from_reg] >= total_size | |
2294 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2295 | >= inherent_size)) | |
2296 | x = spill_stack_slot[from_reg]; | |
2297 | /* Allocate a bigger slot. */ | |
2298 | else | |
2299 | { | |
2300 | /* Compute maximum size needed, both for inherent size | |
2301 | and for total size. */ | |
2302 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
2303 | if (spill_stack_slot[from_reg]) | |
2304 | { | |
2305 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2306 | > inherent_size) | |
2307 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2308 | if (spill_stack_slot_width[from_reg] > total_size) | |
2309 | total_size = spill_stack_slot_width[from_reg]; | |
2310 | } | |
2311 | /* Make a slot with that size. */ | |
2312 | x = assign_stack_local (mode, total_size, -1); | |
2313 | #if BYTES_BIG_ENDIAN | |
2314 | /* Cancel the big-endian correction done in assign_stack_local. | |
2315 | Get the address of the beginning of the slot. | |
2316 | This is so we can do a big-endian correction unconditionally | |
2317 | below. */ | |
2318 | adjust = GET_MODE_SIZE (mode) - total_size; | |
2319 | #endif | |
2320 | spill_stack_slot[from_reg] = x; | |
2321 | spill_stack_slot_width[from_reg] = total_size; | |
2322 | } | |
2323 | ||
2324 | #if BYTES_BIG_ENDIAN | |
2325 | /* On a big endian machine, the "address" of the slot | |
2326 | is the address of the low part that fits its inherent mode. */ | |
2327 | if (inherent_size < total_size) | |
2328 | adjust += (total_size - inherent_size); | |
2329 | #endif /* BYTES_BIG_ENDIAN */ | |
2330 | ||
2331 | /* If we have any adjustment to make, or if the stack slot is the | |
2332 | wrong mode, make a new stack slot. */ | |
2333 | if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) | |
2334 | { | |
2335 | x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]), | |
2336 | plus_constant (XEXP (x, 0), adjust)); | |
2337 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
2338 | } | |
2339 | ||
2340 | /* Save the stack slot for later. */ | |
2341 | reg_equiv_memory_loc[i] = x; | |
2342 | } | |
2343 | } | |
2344 | ||
2345 | /* Mark the slots in regs_ever_live for the hard regs | |
2346 | used by pseudo-reg number REGNO. */ | |
2347 | ||
2348 | void | |
2349 | mark_home_live (regno) | |
2350 | int regno; | |
2351 | { | |
2352 | register int i, lim; | |
2353 | i = reg_renumber[regno]; | |
2354 | if (i < 0) | |
2355 | return; | |
2356 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
2357 | while (i < lim) | |
2358 | regs_ever_live[i++] = 1; | |
2359 | } | |
2360 | \f | |
2361 | /* This function handles the tracking of elimination offsets around branches. | |
2362 | ||
2363 | X is a piece of RTL being scanned. | |
2364 | ||
2365 | INSN is the insn that it came from, if any. | |
2366 | ||
2367 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
2368 | offset and zero if we are setting the offset of the label to be the | |
2369 | current offset. */ | |
2370 | ||
2371 | static void | |
2372 | set_label_offsets (x, insn, initial_p) | |
2373 | rtx x; | |
2374 | rtx insn; | |
2375 | int initial_p; | |
2376 | { | |
2377 | enum rtx_code code = GET_CODE (x); | |
2378 | rtx tem; | |
2379 | int i; | |
2380 | struct elim_table *p; | |
2381 | ||
2382 | switch (code) | |
2383 | { | |
2384 | case LABEL_REF: | |
8be386d9 RS |
2385 | if (LABEL_REF_NONLOCAL_P (x)) |
2386 | return; | |
2387 | ||
32131a9c RK |
2388 | x = XEXP (x, 0); |
2389 | ||
2390 | /* ... fall through ... */ | |
2391 | ||
2392 | case CODE_LABEL: | |
2393 | /* If we know nothing about this label, set the desired offsets. Note | |
2394 | that this sets the offset at a label to be the offset before a label | |
2395 | if we don't know anything about the label. This is not correct for | |
2396 | the label after a BARRIER, but is the best guess we can make. If | |
2397 | we guessed wrong, we will suppress an elimination that might have | |
2398 | been possible had we been able to guess correctly. */ | |
2399 | ||
2400 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2401 | { | |
2402 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2403 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2404 | = (initial_p ? reg_eliminate[i].initial_offset | |
2405 | : reg_eliminate[i].offset); | |
2406 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2407 | } | |
2408 | ||
2409 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2410 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2411 | that label. */ |
2412 | ||
2413 | else if (x == insn | |
2414 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2415 | && GET_CODE (tem) == BARRIER) | |
2a4b5f3b RK |
2416 | { |
2417 | num_not_at_initial_offset = 0; | |
2418 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2419 | { | |
2420 | reg_eliminate[i].offset = reg_eliminate[i].previous_offset | |
2421 | = offsets_at[CODE_LABEL_NUMBER (x)][i]; | |
1d0d98f3 RK |
2422 | if (reg_eliminate[i].can_eliminate |
2423 | && (reg_eliminate[i].offset | |
2424 | != reg_eliminate[i].initial_offset)) | |
2a4b5f3b RK |
2425 | num_not_at_initial_offset++; |
2426 | } | |
2427 | } | |
32131a9c RK |
2428 | |
2429 | else | |
2430 | /* If neither of the above cases is true, compare each offset | |
2431 | with those previously recorded and suppress any eliminations | |
2432 | where the offsets disagree. */ | |
a8fdc208 | 2433 | |
32131a9c RK |
2434 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2435 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2436 | != (initial_p ? reg_eliminate[i].initial_offset | |
2437 | : reg_eliminate[i].offset)) | |
2438 | reg_eliminate[i].can_eliminate = 0; | |
2439 | ||
2440 | return; | |
2441 | ||
2442 | case JUMP_INSN: | |
2443 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2444 | ||
2445 | /* ... fall through ... */ | |
2446 | ||
2447 | case INSN: | |
2448 | case CALL_INSN: | |
2449 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2450 | and hence must have all eliminations at their initial offsets. */ | |
2451 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2452 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2453 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2454 | return; | |
2455 | ||
2456 | case ADDR_VEC: | |
2457 | case ADDR_DIFF_VEC: | |
2458 | /* Each of the labels in the address vector must be at their initial | |
2459 | offsets. We want the first first for ADDR_VEC and the second | |
2460 | field for ADDR_DIFF_VEC. */ | |
2461 | ||
2462 | for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++) | |
2463 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), | |
2464 | insn, initial_p); | |
2465 | return; | |
2466 | ||
2467 | case SET: | |
2468 | /* We only care about setting PC. If the source is not RETURN, | |
2469 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2470 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2471 | isn't one of those possibilities. For branches to a label, | |
2472 | call ourselves recursively. | |
2473 | ||
2474 | Note that this can disable elimination unnecessarily when we have | |
2475 | a non-local goto since it will look like a non-constant jump to | |
2476 | someplace in the current function. This isn't a significant | |
2477 | problem since such jumps will normally be when all elimination | |
2478 | pairs are back to their initial offsets. */ | |
2479 | ||
2480 | if (SET_DEST (x) != pc_rtx) | |
2481 | return; | |
2482 | ||
2483 | switch (GET_CODE (SET_SRC (x))) | |
2484 | { | |
2485 | case PC: | |
2486 | case RETURN: | |
2487 | return; | |
2488 | ||
2489 | case LABEL_REF: | |
2490 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2491 | return; | |
2492 | ||
2493 | case IF_THEN_ELSE: | |
2494 | tem = XEXP (SET_SRC (x), 1); | |
2495 | if (GET_CODE (tem) == LABEL_REF) | |
2496 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2497 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2498 | break; | |
2499 | ||
2500 | tem = XEXP (SET_SRC (x), 2); | |
2501 | if (GET_CODE (tem) == LABEL_REF) | |
2502 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2503 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2504 | break; | |
2505 | return; | |
2506 | } | |
2507 | ||
2508 | /* If we reach here, all eliminations must be at their initial | |
2509 | offset because we are doing a jump to a variable address. */ | |
2510 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2511 | if (p->offset != p->initial_offset) | |
2512 | p->can_eliminate = 0; | |
2513 | } | |
2514 | } | |
2515 | \f | |
2516 | /* Used for communication between the next two function to properly share | |
2517 | the vector for an ASM_OPERANDS. */ | |
2518 | ||
2519 | static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec; | |
2520 | ||
a8fdc208 | 2521 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2522 | replacement (such as sp), plus an offset. |
2523 | ||
2524 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2525 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2526 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2527 | with the register, which we cannot do outside a MEM. In addition, we need | |
2528 | to record the fact that a register is referenced outside a MEM. | |
2529 | ||
2530 | If INSN is nonzero, it is the insn containing X. If we replace a REG | |
2531 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a | |
2532 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
2533 | that the REG is being modified. | |
2534 | ||
2535 | If we see a modification to a register we know about, take the | |
2536 | appropriate action (see case SET, below). | |
2537 | ||
2538 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had | |
2539 | replacements done assuming all offsets are at their initial values. If | |
2540 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2541 | encounter, return the actual location so that find_reloads will do | |
2542 | the proper thing. */ | |
2543 | ||
2544 | rtx | |
2545 | eliminate_regs (x, mem_mode, insn) | |
2546 | rtx x; | |
2547 | enum machine_mode mem_mode; | |
2548 | rtx insn; | |
2549 | { | |
2550 | enum rtx_code code = GET_CODE (x); | |
2551 | struct elim_table *ep; | |
2552 | int regno; | |
2553 | rtx new; | |
2554 | int i, j; | |
2555 | char *fmt; | |
2556 | int copied = 0; | |
2557 | ||
2558 | switch (code) | |
2559 | { | |
2560 | case CONST_INT: | |
2561 | case CONST_DOUBLE: | |
2562 | case CONST: | |
2563 | case SYMBOL_REF: | |
2564 | case CODE_LABEL: | |
2565 | case PC: | |
2566 | case CC0: | |
2567 | case ASM_INPUT: | |
2568 | case ADDR_VEC: | |
2569 | case ADDR_DIFF_VEC: | |
2570 | case RETURN: | |
2571 | return x; | |
2572 | ||
2573 | case REG: | |
2574 | regno = REGNO (x); | |
2575 | ||
2576 | /* First handle the case where we encounter a bare register that | |
2577 | is eliminable. Replace it with a PLUS. */ | |
2578 | if (regno < FIRST_PSEUDO_REGISTER) | |
2579 | { | |
2580 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2581 | ep++) | |
2582 | if (ep->from_rtx == x && ep->can_eliminate) | |
2583 | { | |
2584 | if (! mem_mode) | |
2585 | ep->ref_outside_mem = 1; | |
2586 | return plus_constant (ep->to_rtx, ep->previous_offset); | |
2587 | } | |
2588 | ||
2589 | } | |
2590 | else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno] | |
2591 | && (reg_equiv_address[regno] || num_not_at_initial_offset)) | |
2592 | { | |
2593 | /* In this case, find_reloads would attempt to either use an | |
2594 | incorrect address (if something is not at its initial offset) | |
2595 | or substitute an replaced address into an insn (which loses | |
2596 | if the offset is changed by some later action). So we simply | |
2597 | return the replaced stack slot (assuming it is changed by | |
2598 | elimination) and ignore the fact that this is actually a | |
2599 | reference to the pseudo. Ensure we make a copy of the | |
2600 | address in case it is shared. */ | |
fb3821f7 CH |
2601 | new = eliminate_regs (reg_equiv_memory_loc[regno], |
2602 | mem_mode, NULL_RTX); | |
32131a9c RK |
2603 | if (new != reg_equiv_memory_loc[regno]) |
2604 | return copy_rtx (new); | |
2605 | } | |
2606 | return x; | |
2607 | ||
2608 | case PLUS: | |
2609 | /* If this is the sum of an eliminable register and a constant, rework | |
2610 | the sum. */ | |
2611 | if (GET_CODE (XEXP (x, 0)) == REG | |
2612 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2613 | && CONSTANT_P (XEXP (x, 1))) | |
2614 | { | |
2615 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2616 | ep++) | |
2617 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2618 | { | |
2619 | if (! mem_mode) | |
2620 | ep->ref_outside_mem = 1; | |
2621 | ||
2622 | /* The only time we want to replace a PLUS with a REG (this | |
2623 | occurs when the constant operand of the PLUS is the negative | |
2624 | of the offset) is when we are inside a MEM. We won't want | |
2625 | to do so at other times because that would change the | |
2626 | structure of the insn in a way that reload can't handle. | |
2627 | We special-case the commonest situation in | |
2628 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2629 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2630 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2631 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2632 | return ep->to_rtx; | |
2633 | else | |
2634 | return gen_rtx (PLUS, Pmode, ep->to_rtx, | |
2635 | plus_constant (XEXP (x, 1), | |
2636 | ep->previous_offset)); | |
2637 | } | |
2638 | ||
2639 | /* If the register is not eliminable, we are done since the other | |
2640 | operand is a constant. */ | |
2641 | return x; | |
2642 | } | |
2643 | ||
2644 | /* If this is part of an address, we want to bring any constant to the | |
2645 | outermost PLUS. We will do this by doing register replacement in | |
2646 | our operands and seeing if a constant shows up in one of them. | |
2647 | ||
2648 | We assume here this is part of an address (or a "load address" insn) | |
2649 | since an eliminable register is not likely to appear in any other | |
2650 | context. | |
2651 | ||
2652 | If we have (plus (eliminable) (reg)), we want to produce | |
2653 | (plus (plus (replacement) (reg) (const))). If this was part of a | |
2654 | normal add insn, (plus (replacement) (reg)) will be pushed as a | |
2655 | reload. This is the desired action. */ | |
2656 | ||
2657 | { | |
fb3821f7 CH |
2658 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
2659 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX); | |
32131a9c RK |
2660 | |
2661 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2662 | { | |
2663 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2664 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2665 | we must replace the constant here since it may no longer |
2666 | be in the position of any operand. */ | |
2667 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2668 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2669 | && reg_renumber[REGNO (new1)] < 0 | |
2670 | && reg_equiv_constant != 0 | |
2671 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2672 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2673 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2674 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2675 | && reg_renumber[REGNO (new0)] < 0 | |
2676 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2677 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2678 | ||
2679 | new = form_sum (new0, new1); | |
2680 | ||
2681 | /* As above, if we are not inside a MEM we do not want to | |
2682 | turn a PLUS into something else. We might try to do so here | |
2683 | for an addition of 0 if we aren't optimizing. */ | |
2684 | if (! mem_mode && GET_CODE (new) != PLUS) | |
2685 | return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx); | |
2686 | else | |
2687 | return new; | |
2688 | } | |
2689 | } | |
2690 | return x; | |
2691 | ||
2692 | case EXPR_LIST: | |
2693 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2694 | if (XEXP (x, 0)) | |
2695 | { | |
fb3821f7 | 2696 | new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
32131a9c RK |
2697 | if (new != XEXP (x, 0)) |
2698 | x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2699 | } | |
2700 | ||
2701 | /* ... fall through ... */ | |
2702 | ||
2703 | case INSN_LIST: | |
2704 | /* Now do eliminations in the rest of the chain. If this was | |
2705 | an EXPR_LIST, this might result in allocating more memory than is | |
2706 | strictly needed, but it simplifies the code. */ | |
2707 | if (XEXP (x, 1)) | |
2708 | { | |
fb3821f7 | 2709 | new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX); |
32131a9c RK |
2710 | if (new != XEXP (x, 1)) |
2711 | return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new); | |
2712 | } | |
2713 | return x; | |
2714 | ||
2715 | case CALL: | |
2716 | case COMPARE: | |
2717 | case MINUS: | |
2718 | case MULT: | |
2719 | case DIV: case UDIV: | |
2720 | case MOD: case UMOD: | |
2721 | case AND: case IOR: case XOR: | |
2722 | case LSHIFT: case ASHIFT: case ROTATE: | |
2723 | case ASHIFTRT: case LSHIFTRT: case ROTATERT: | |
2724 | case NE: case EQ: | |
2725 | case GE: case GT: case GEU: case GTU: | |
2726 | case LE: case LT: case LEU: case LTU: | |
2727 | { | |
fb3821f7 CH |
2728 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
2729 | rtx new1 | |
2730 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0; | |
32131a9c RK |
2731 | |
2732 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2733 | return gen_rtx (code, GET_MODE (x), new0, new1); | |
2734 | } | |
2735 | return x; | |
2736 | ||
2737 | case PRE_INC: | |
2738 | case POST_INC: | |
2739 | case PRE_DEC: | |
2740 | case POST_DEC: | |
2741 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2742 | if (ep->to_rtx == XEXP (x, 0)) | |
2743 | { | |
4c05b187 RK |
2744 | int size = GET_MODE_SIZE (mem_mode); |
2745 | ||
2746 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2747 | #ifdef PUSH_ROUNDING | |
2748 | if (ep->to_rtx == stack_pointer_rtx) | |
2749 | size = PUSH_ROUNDING (size); | |
2750 | #endif | |
32131a9c | 2751 | if (code == PRE_DEC || code == POST_DEC) |
4c05b187 | 2752 | ep->offset += size; |
32131a9c | 2753 | else |
4c05b187 | 2754 | ep->offset -= size; |
32131a9c RK |
2755 | } |
2756 | ||
2757 | /* Fall through to generic unary operation case. */ | |
2758 | case USE: | |
2759 | case STRICT_LOW_PART: | |
2760 | case NEG: case NOT: | |
2761 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2762 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2763 | case FLOAT: case FIX: | |
2764 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2765 | case ABS: | |
2766 | case SQRT: | |
2767 | case FFS: | |
fb3821f7 | 2768 | new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
32131a9c RK |
2769 | if (new != XEXP (x, 0)) |
2770 | return gen_rtx (code, GET_MODE (x), new); | |
2771 | return x; | |
2772 | ||
2773 | case SUBREG: | |
2774 | /* Similar to above processing, but preserve SUBREG_WORD. | |
2775 | Convert (subreg (mem)) to (mem) if not paradoxical. | |
2776 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2777 | pseudo didn't get a hard reg, we must replace this with the | |
2778 | eliminated version of the memory location because push_reloads | |
2779 | may do the replacement in certain circumstances. */ | |
2780 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2781 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2782 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2783 | && reg_equiv_memory_loc != 0 | |
2784 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2785 | { | |
2786 | new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))], | |
fb3821f7 | 2787 | mem_mode, NULL_RTX); |
32131a9c RK |
2788 | |
2789 | /* If we didn't change anything, we must retain the pseudo. */ | |
2790 | if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))]) | |
2791 | new = XEXP (x, 0); | |
2792 | else | |
2793 | /* Otherwise, ensure NEW isn't shared in case we have to reload | |
2794 | it. */ | |
2795 | new = copy_rtx (new); | |
2796 | } | |
2797 | else | |
fb3821f7 | 2798 | new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX); |
32131a9c RK |
2799 | |
2800 | if (new != XEXP (x, 0)) | |
2801 | { | |
2802 | if (GET_CODE (new) == MEM | |
2803 | && (GET_MODE_SIZE (GET_MODE (x)) | |
a3b75c07 RS |
2804 | <= GET_MODE_SIZE (GET_MODE (new))) |
2805 | #if defined(BYTES_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) | |
2806 | /* On these machines we will be reloading what is | |
2807 | inside the SUBREG if it originally was a pseudo and | |
2808 | the inner and outer modes are both a word or | |
2809 | smaller. So leave the SUBREG then. */ | |
2810 | && ! (GET_CODE (SUBREG_REG (x)) == REG | |
2811 | && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD | |
2812 | && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD) | |
2813 | #endif | |
2814 | ) | |
32131a9c RK |
2815 | { |
2816 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
2817 | enum machine_mode mode = GET_MODE (x); | |
2818 | ||
2819 | #if BYTES_BIG_ENDIAN | |
2820 | offset += (MIN (UNITS_PER_WORD, | |
2821 | GET_MODE_SIZE (GET_MODE (new))) | |
2822 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
2823 | #endif | |
2824 | ||
2825 | PUT_MODE (new, mode); | |
2826 | XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); | |
2827 | return new; | |
2828 | } | |
2829 | else | |
2830 | return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x)); | |
2831 | } | |
2832 | ||
2833 | return x; | |
2834 | ||
2835 | case CLOBBER: | |
2836 | /* If clobbering a register that is the replacement register for an | |
d45cf215 | 2837 | elimination we still think can be performed, note that it cannot |
32131a9c RK |
2838 | be performed. Otherwise, we need not be concerned about it. */ |
2839 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2840 | if (ep->to_rtx == XEXP (x, 0)) | |
2841 | ep->can_eliminate = 0; | |
2842 | ||
2045084c JVA |
2843 | new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
2844 | if (new != XEXP (x, 0)) | |
2845 | return gen_rtx (code, GET_MODE (x), new); | |
32131a9c RK |
2846 | return x; |
2847 | ||
2848 | case ASM_OPERANDS: | |
2849 | { | |
2850 | rtx *temp_vec; | |
2851 | /* Properly handle sharing input and constraint vectors. */ | |
2852 | if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec) | |
2853 | { | |
2854 | /* When we come to a new vector not seen before, | |
2855 | scan all its elements; keep the old vector if none | |
2856 | of them changes; otherwise, make a copy. */ | |
2857 | old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x); | |
2858 | temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx)); | |
2859 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) | |
2860 | temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i), | |
fb3821f7 | 2861 | mem_mode, NULL_RTX); |
32131a9c RK |
2862 | |
2863 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) | |
2864 | if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i)) | |
2865 | break; | |
2866 | ||
2867 | if (i == ASM_OPERANDS_INPUT_LENGTH (x)) | |
2868 | new_asm_operands_vec = old_asm_operands_vec; | |
2869 | else | |
2870 | new_asm_operands_vec | |
2871 | = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec); | |
2872 | } | |
2873 | ||
2874 | /* If we had to copy the vector, copy the entire ASM_OPERANDS. */ | |
2875 | if (new_asm_operands_vec == old_asm_operands_vec) | |
2876 | return x; | |
2877 | ||
2878 | new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x), | |
2879 | ASM_OPERANDS_OUTPUT_CONSTRAINT (x), | |
2880 | ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec, | |
2881 | ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x), | |
2882 | ASM_OPERANDS_SOURCE_FILE (x), | |
2883 | ASM_OPERANDS_SOURCE_LINE (x)); | |
2884 | new->volatil = x->volatil; | |
2885 | return new; | |
2886 | } | |
2887 | ||
2888 | case SET: | |
2889 | /* Check for setting a register that we know about. */ | |
2890 | if (GET_CODE (SET_DEST (x)) == REG) | |
2891 | { | |
2892 | /* See if this is setting the replacement register for an | |
a8fdc208 | 2893 | elimination. |
32131a9c RK |
2894 | |
2895 | If DEST is the frame pointer, we do nothing because we assume that | |
2896 | all assignments to the frame pointer are for non-local gotos and | |
2897 | are being done at a time when they are valid and do not disturb | |
2898 | anything else. Some machines want to eliminate a fake argument | |
2899 | pointer with either the frame or stack pointer. Assignments to | |
2900 | the frame pointer must not prevent this elimination. */ | |
2901 | ||
2902 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2903 | ep++) | |
2904 | if (ep->to_rtx == SET_DEST (x) | |
2905 | && SET_DEST (x) != frame_pointer_rtx) | |
2906 | { | |
6dc42e49 | 2907 | /* If it is being incremented, adjust the offset. Otherwise, |
32131a9c RK |
2908 | this elimination can't be done. */ |
2909 | rtx src = SET_SRC (x); | |
2910 | ||
2911 | if (GET_CODE (src) == PLUS | |
2912 | && XEXP (src, 0) == SET_DEST (x) | |
2913 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2914 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2915 | else | |
2916 | ep->can_eliminate = 0; | |
2917 | } | |
2918 | ||
2919 | /* Now check to see we are assigning to a register that can be | |
2920 | eliminated. If so, it must be as part of a PARALLEL, since we | |
2921 | will not have been called if this is a single SET. So indicate | |
2922 | that we can no longer eliminate this reg. */ | |
2923 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2924 | ep++) | |
2925 | if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate) | |
2926 | ep->can_eliminate = 0; | |
2927 | } | |
2928 | ||
2929 | /* Now avoid the loop below in this common case. */ | |
2930 | { | |
fb3821f7 CH |
2931 | rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX); |
2932 | rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX); | |
32131a9c RK |
2933 | |
2934 | /* If SET_DEST changed from a REG to a MEM and INSN is non-zero, | |
2935 | write a CLOBBER insn. */ | |
2936 | if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM | |
2937 | && insn != 0) | |
2938 | emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn); | |
2939 | ||
2940 | if (new0 != SET_DEST (x) || new1 != SET_SRC (x)) | |
2941 | return gen_rtx (SET, VOIDmode, new0, new1); | |
2942 | } | |
2943 | ||
2944 | return x; | |
2945 | ||
2946 | case MEM: | |
2947 | /* Our only special processing is to pass the mode of the MEM to our | |
2948 | recursive call and copy the flags. While we are here, handle this | |
2949 | case more efficiently. */ | |
fb3821f7 | 2950 | new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX); |
32131a9c RK |
2951 | if (new != XEXP (x, 0)) |
2952 | { | |
2953 | new = gen_rtx (MEM, GET_MODE (x), new); | |
2954 | new->volatil = x->volatil; | |
2955 | new->unchanging = x->unchanging; | |
2956 | new->in_struct = x->in_struct; | |
2957 | return new; | |
2958 | } | |
2959 | else | |
2960 | return x; | |
2961 | } | |
2962 | ||
2963 | /* Process each of our operands recursively. If any have changed, make a | |
2964 | copy of the rtx. */ | |
2965 | fmt = GET_RTX_FORMAT (code); | |
2966 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2967 | { | |
2968 | if (*fmt == 'e') | |
2969 | { | |
fb3821f7 | 2970 | new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX); |
32131a9c RK |
2971 | if (new != XEXP (x, i) && ! copied) |
2972 | { | |
2973 | rtx new_x = rtx_alloc (code); | |
2974 | bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld) | |
2975 | + (sizeof (new_x->fld[0]) | |
2976 | * GET_RTX_LENGTH (code)))); | |
2977 | x = new_x; | |
2978 | copied = 1; | |
2979 | } | |
2980 | XEXP (x, i) = new; | |
2981 | } | |
2982 | else if (*fmt == 'E') | |
2983 | { | |
2984 | int copied_vec = 0; | |
2985 | for (j = 0; j < XVECLEN (x, i); j++) | |
2986 | { | |
2987 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); | |
2988 | if (new != XVECEXP (x, i, j) && ! copied_vec) | |
2989 | { | |
2990 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), | |
2991 | &XVECEXP (x, i, 0)); | |
2992 | if (! copied) | |
2993 | { | |
2994 | rtx new_x = rtx_alloc (code); | |
2995 | bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld) | |
2996 | + (sizeof (new_x->fld[0]) | |
2997 | * GET_RTX_LENGTH (code)))); | |
2998 | x = new_x; | |
2999 | copied = 1; | |
3000 | } | |
3001 | XVEC (x, i) = new_v; | |
3002 | copied_vec = 1; | |
3003 | } | |
3004 | XVECEXP (x, i, j) = new; | |
3005 | } | |
3006 | } | |
3007 | } | |
3008 | ||
3009 | return x; | |
3010 | } | |
3011 | \f | |
3012 | /* Scan INSN and eliminate all eliminable registers in it. | |
3013 | ||
3014 | If REPLACE is nonzero, do the replacement destructively. Also | |
3015 | delete the insn as dead it if it is setting an eliminable register. | |
3016 | ||
3017 | If REPLACE is zero, do all our allocations in reload_obstack. | |
3018 | ||
3019 | If no eliminations were done and this insn doesn't require any elimination | |
3020 | processing (these are not identical conditions: it might be updating sp, | |
3021 | but not referencing fp; this needs to be seen during reload_as_needed so | |
3022 | that the offset between fp and sp can be taken into consideration), zero | |
3023 | is returned. Otherwise, 1 is returned. */ | |
3024 | ||
3025 | static int | |
3026 | eliminate_regs_in_insn (insn, replace) | |
3027 | rtx insn; | |
3028 | int replace; | |
3029 | { | |
3030 | rtx old_body = PATTERN (insn); | |
3031 | rtx new_body; | |
3032 | int val = 0; | |
3033 | struct elim_table *ep; | |
3034 | ||
3035 | if (! replace) | |
3036 | push_obstacks (&reload_obstack, &reload_obstack); | |
3037 | ||
3038 | if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG | |
3039 | && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER) | |
3040 | { | |
3041 | /* Check for setting an eliminable register. */ | |
3042 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3043 | if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate) | |
3044 | { | |
3045 | /* In this case this insn isn't serving a useful purpose. We | |
3046 | will delete it in reload_as_needed once we know that this | |
3047 | elimination is, in fact, being done. | |
3048 | ||
3049 | If REPLACE isn't set, we can't delete this insn, but neededn't | |
3050 | process it since it won't be used unless something changes. */ | |
3051 | if (replace) | |
3052 | delete_dead_insn (insn); | |
3053 | val = 1; | |
3054 | goto done; | |
3055 | } | |
3056 | ||
3057 | /* Check for (set (reg) (plus (reg from) (offset))) where the offset | |
3058 | in the insn is the negative of the offset in FROM. Substitute | |
3059 | (set (reg) (reg to)) for the insn and change its code. | |
3060 | ||
3061 | We have to do this here, rather than in eliminate_regs, do that we can | |
3062 | change the insn code. */ | |
3063 | ||
3064 | if (GET_CODE (SET_SRC (old_body)) == PLUS | |
3065 | && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG | |
3066 | && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT) | |
3067 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3068 | ep++) | |
3069 | if (ep->from_rtx == XEXP (SET_SRC (old_body), 0) | |
3070 | && ep->can_eliminate | |
3071 | && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1))) | |
3072 | { | |
3073 | PATTERN (insn) = gen_rtx (SET, VOIDmode, | |
3074 | SET_DEST (old_body), ep->to_rtx); | |
3075 | INSN_CODE (insn) = -1; | |
3076 | val = 1; | |
3077 | goto done; | |
3078 | } | |
3079 | } | |
3080 | ||
3081 | old_asm_operands_vec = 0; | |
3082 | ||
3083 | /* Replace the body of this insn with a substituted form. If we changed | |
3084 | something, return non-zero. If this is the final call for this | |
3085 | insn (REPLACE is non-zero), do the elimination in REG_NOTES as well. | |
3086 | ||
3087 | If we are replacing a body that was a (set X (plus Y Z)), try to | |
3088 | re-recognize the insn. We do this in case we had a simple addition | |
3089 | but now can do this as a load-address. This saves an insn in this | |
3090 | common case. */ | |
3091 | ||
fb3821f7 | 3092 | new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX); |
32131a9c RK |
3093 | if (new_body != old_body) |
3094 | { | |
7c791b13 RK |
3095 | /* If we aren't replacing things permanently and we changed something, |
3096 | make another copy to ensure that all the RTL is new. Otherwise | |
3097 | things can go wrong if find_reload swaps commutative operands | |
3098 | and one is inside RTL that has been copied while the other is not. */ | |
3099 | ||
4d411872 RS |
3100 | /* Don't copy an asm_operands because (1) there's no need and (2) |
3101 | copy_rtx can't do it properly when there are multiple outputs. */ | |
b84f9d9c | 3102 | if (! replace && asm_noperands (old_body) < 0) |
7c791b13 RK |
3103 | new_body = copy_rtx (new_body); |
3104 | ||
4a5d0fb5 | 3105 | /* If we had a move insn but now we don't, rerecognize it. */ |
0ba846c7 RS |
3106 | if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG |
3107 | && (GET_CODE (new_body) != SET | |
3108 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3109 | /* If this was an add insn before, rerecognize. */ | |
3110 | || | |
3111 | (GET_CODE (old_body) == SET | |
3112 | && GET_CODE (SET_SRC (old_body)) == PLUS)) | |
4a5d0fb5 RS |
3113 | { |
3114 | if (! validate_change (insn, &PATTERN (insn), new_body, 0)) | |
0ba846c7 RS |
3115 | /* If recognition fails, store the new body anyway. |
3116 | It's normal to have recognition failures here | |
3117 | due to bizarre memory addresses; reloading will fix them. */ | |
3118 | PATTERN (insn) = new_body; | |
4a5d0fb5 | 3119 | } |
0ba846c7 | 3120 | else |
32131a9c RK |
3121 | PATTERN (insn) = new_body; |
3122 | ||
3123 | if (replace && REG_NOTES (insn)) | |
fb3821f7 | 3124 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX); |
32131a9c RK |
3125 | val = 1; |
3126 | } | |
a8fdc208 | 3127 | |
32131a9c RK |
3128 | /* Loop through all elimination pairs. See if any have changed and |
3129 | recalculate the number not at initial offset. | |
3130 | ||
a8efe40d RK |
3131 | Compute the maximum offset (minimum offset if the stack does not |
3132 | grow downward) for each elimination pair. | |
3133 | ||
32131a9c RK |
3134 | We also detect a cases where register elimination cannot be done, |
3135 | namely, if a register would be both changed and referenced outside a MEM | |
3136 | in the resulting insn since such an insn is often undefined and, even if | |
3137 | not, we cannot know what meaning will be given to it. Note that it is | |
3138 | valid to have a register used in an address in an insn that changes it | |
3139 | (presumably with a pre- or post-increment or decrement). | |
3140 | ||
3141 | If anything changes, return nonzero. */ | |
3142 | ||
3143 | num_not_at_initial_offset = 0; | |
3144 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3145 | { | |
3146 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3147 | ep->can_eliminate = 0; | |
3148 | ||
3149 | ep->ref_outside_mem = 0; | |
3150 | ||
3151 | if (ep->previous_offset != ep->offset) | |
3152 | val = 1; | |
3153 | ||
3154 | ep->previous_offset = ep->offset; | |
3155 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3156 | num_not_at_initial_offset++; | |
a8efe40d RK |
3157 | |
3158 | #ifdef STACK_GROWS_DOWNWARD | |
3159 | ep->max_offset = MAX (ep->max_offset, ep->offset); | |
3160 | #else | |
3161 | ep->max_offset = MIN (ep->max_offset, ep->offset); | |
3162 | #endif | |
32131a9c RK |
3163 | } |
3164 | ||
3165 | done: | |
3166 | if (! replace) | |
3167 | pop_obstacks (); | |
3168 | ||
3169 | return val; | |
3170 | } | |
3171 | ||
3172 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register | |
3173 | replacement we currently believe is valid, mark it as not eliminable if X | |
3174 | modifies DEST in any way other than by adding a constant integer to it. | |
3175 | ||
3176 | If DEST is the frame pointer, we do nothing because we assume that | |
3177 | all assignments to the frame pointer are nonlocal gotos and are being done | |
3178 | at a time when they are valid and do not disturb anything else. | |
3179 | Some machines want to eliminate a fake argument pointer with either the | |
3180 | frame or stack pointer. Assignments to the frame pointer must not prevent | |
3181 | this elimination. | |
3182 | ||
3183 | Called via note_stores from reload before starting its passes to scan | |
3184 | the insns of the function. */ | |
3185 | ||
3186 | static void | |
3187 | mark_not_eliminable (dest, x) | |
3188 | rtx dest; | |
3189 | rtx x; | |
3190 | { | |
3191 | register int i; | |
3192 | ||
3193 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3194 | not see a SUBREG of an eliminable hard register, but check just in | |
3195 | case. */ | |
3196 | if (GET_CODE (dest) == SUBREG) | |
3197 | dest = SUBREG_REG (dest); | |
3198 | ||
3199 | if (dest == frame_pointer_rtx) | |
3200 | return; | |
3201 | ||
3202 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3203 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3204 | && (GET_CODE (x) != SET | |
3205 | || GET_CODE (SET_SRC (x)) != PLUS | |
3206 | || XEXP (SET_SRC (x), 0) != dest | |
3207 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3208 | { | |
3209 | reg_eliminate[i].can_eliminate_previous | |
3210 | = reg_eliminate[i].can_eliminate = 0; | |
3211 | num_eliminable--; | |
3212 | } | |
3213 | } | |
3214 | \f | |
3215 | /* Kick all pseudos out of hard register REGNO. | |
3216 | If GLOBAL is nonzero, try to find someplace else to put them. | |
3217 | If DUMPFILE is nonzero, log actions taken on that file. | |
3218 | ||
3219 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3220 | because we found we can't eliminate some register. In the case, no pseudos | |
3221 | are allowed to be in the register, even if they are only in a block that | |
3222 | doesn't require spill registers, unlike the case when we are spilling this | |
3223 | hard reg to produce another spill register. | |
3224 | ||
3225 | Return nonzero if any pseudos needed to be kicked out. */ | |
3226 | ||
3227 | static int | |
3228 | spill_hard_reg (regno, global, dumpfile, cant_eliminate) | |
3229 | register int regno; | |
3230 | int global; | |
3231 | FILE *dumpfile; | |
3232 | int cant_eliminate; | |
3233 | { | |
3234 | int something_changed = 0; | |
3235 | register int i; | |
3236 | ||
3237 | SET_HARD_REG_BIT (forbidden_regs, regno); | |
3238 | ||
3239 | /* Spill every pseudo reg that was allocated to this reg | |
3240 | or to something that overlaps this reg. */ | |
3241 | ||
3242 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3243 | if (reg_renumber[i] >= 0 | |
3244 | && reg_renumber[i] <= regno | |
a8fdc208 | 3245 | && (reg_renumber[i] |
32131a9c RK |
3246 | + HARD_REGNO_NREGS (reg_renumber[i], |
3247 | PSEUDO_REGNO_MODE (i)) | |
3248 | > regno)) | |
3249 | { | |
3250 | enum reg_class class = REGNO_REG_CLASS (regno); | |
3251 | ||
3252 | /* If this register belongs solely to a basic block which needed no | |
3253 | spilling of any class that this register is contained in, | |
3254 | leave it be, unless we are spilling this register because | |
3255 | it was a hard register that can't be eliminated. */ | |
3256 | ||
3257 | if (! cant_eliminate | |
3258 | && basic_block_needs[0] | |
3259 | && reg_basic_block[i] >= 0 | |
3260 | && basic_block_needs[(int) class][reg_basic_block[i]] == 0) | |
3261 | { | |
3262 | enum reg_class *p; | |
3263 | ||
3264 | for (p = reg_class_superclasses[(int) class]; | |
3265 | *p != LIM_REG_CLASSES; p++) | |
3266 | if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0) | |
3267 | break; | |
a8fdc208 | 3268 | |
32131a9c RK |
3269 | if (*p == LIM_REG_CLASSES) |
3270 | continue; | |
3271 | } | |
3272 | ||
3273 | /* Mark it as no longer having a hard register home. */ | |
3274 | reg_renumber[i] = -1; | |
3275 | /* We will need to scan everything again. */ | |
3276 | something_changed = 1; | |
3277 | if (global) | |
3278 | retry_global_alloc (i, forbidden_regs); | |
3279 | ||
3280 | alter_reg (i, regno); | |
3281 | if (dumpfile) | |
3282 | { | |
3283 | if (reg_renumber[i] == -1) | |
3284 | fprintf (dumpfile, " Register %d now on stack.\n\n", i); | |
3285 | else | |
3286 | fprintf (dumpfile, " Register %d now in %d.\n\n", | |
3287 | i, reg_renumber[i]); | |
3288 | } | |
3289 | } | |
3290 | ||
3291 | return something_changed; | |
3292 | } | |
3293 | \f | |
3294 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ | |
3295 | ||
3296 | static void | |
3297 | scan_paradoxical_subregs (x) | |
3298 | register rtx x; | |
3299 | { | |
3300 | register int i; | |
3301 | register char *fmt; | |
3302 | register enum rtx_code code = GET_CODE (x); | |
3303 | ||
3304 | switch (code) | |
3305 | { | |
3306 | case CONST_INT: | |
3307 | case CONST: | |
3308 | case SYMBOL_REF: | |
3309 | case LABEL_REF: | |
3310 | case CONST_DOUBLE: | |
3311 | case CC0: | |
3312 | case PC: | |
3313 | case REG: | |
3314 | case USE: | |
3315 | case CLOBBER: | |
3316 | return; | |
3317 | ||
3318 | case SUBREG: | |
3319 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3320 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3321 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3322 | = GET_MODE_SIZE (GET_MODE (x)); | |
3323 | return; | |
3324 | } | |
3325 | ||
3326 | fmt = GET_RTX_FORMAT (code); | |
3327 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3328 | { | |
3329 | if (fmt[i] == 'e') | |
3330 | scan_paradoxical_subregs (XEXP (x, i)); | |
3331 | else if (fmt[i] == 'E') | |
3332 | { | |
3333 | register int j; | |
3334 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
3335 | scan_paradoxical_subregs (XVECEXP (x, i, j)); | |
3336 | } | |
3337 | } | |
3338 | } | |
3339 | \f | |
32131a9c RK |
3340 | static int |
3341 | hard_reg_use_compare (p1, p2) | |
3342 | struct hard_reg_n_uses *p1, *p2; | |
3343 | { | |
3344 | int tem = p1->uses - p2->uses; | |
3345 | if (tem != 0) return tem; | |
3346 | /* If regs are equally good, sort by regno, | |
3347 | so that the results of qsort leave nothing to chance. */ | |
3348 | return p1->regno - p2->regno; | |
3349 | } | |
3350 | ||
3351 | /* Choose the order to consider regs for use as reload registers | |
3352 | based on how much trouble would be caused by spilling one. | |
3353 | Store them in order of decreasing preference in potential_reload_regs. */ | |
3354 | ||
3355 | static void | |
3356 | order_regs_for_reload () | |
3357 | { | |
3358 | register int i; | |
3359 | register int o = 0; | |
3360 | int large = 0; | |
3361 | ||
3362 | struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER]; | |
3363 | ||
3364 | CLEAR_HARD_REG_SET (bad_spill_regs); | |
3365 | ||
3366 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3367 | potential_reload_regs[i] = -1; | |
3368 | ||
3369 | /* Count number of uses of each hard reg by pseudo regs allocated to it | |
3370 | and then order them by decreasing use. */ | |
3371 | ||
3372 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3373 | { | |
3374 | hard_reg_n_uses[i].uses = 0; | |
3375 | hard_reg_n_uses[i].regno = i; | |
3376 | } | |
3377 | ||
3378 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3379 | { | |
3380 | int regno = reg_renumber[i]; | |
3381 | if (regno >= 0) | |
3382 | { | |
3383 | int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i)); | |
3384 | while (regno < lim) | |
3385 | hard_reg_n_uses[regno++].uses += reg_n_refs[i]; | |
3386 | } | |
3387 | large += reg_n_refs[i]; | |
3388 | } | |
3389 | ||
3390 | /* Now fixed registers (which cannot safely be used for reloading) | |
3391 | get a very high use count so they will be considered least desirable. | |
3392 | Registers used explicitly in the rtl code are almost as bad. */ | |
3393 | ||
3394 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3395 | { | |
3396 | if (fixed_regs[i]) | |
3397 | { | |
3398 | hard_reg_n_uses[i].uses += 2 * large + 2; | |
3399 | SET_HARD_REG_BIT (bad_spill_regs, i); | |
3400 | } | |
3401 | else if (regs_explicitly_used[i]) | |
3402 | { | |
3403 | hard_reg_n_uses[i].uses += large + 1; | |
546b63fb | 3404 | #ifndef SMALL_REGISTER_CLASSES |
32131a9c RK |
3405 | /* ??? We are doing this here because of the potential that |
3406 | bad code may be generated if a register explicitly used in | |
3407 | an insn was used as a spill register for that insn. But | |
3408 | not using these are spill registers may lose on some machine. | |
3409 | We'll have to see how this works out. */ | |
3410 | SET_HARD_REG_BIT (bad_spill_regs, i); | |
546b63fb | 3411 | #endif |
32131a9c RK |
3412 | } |
3413 | } | |
3414 | hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2; | |
3415 | SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM); | |
3416 | ||
3417 | #ifdef ELIMINABLE_REGS | |
3418 | /* If registers other than the frame pointer are eliminable, mark them as | |
3419 | poor choices. */ | |
3420 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3421 | { | |
3422 | hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2; | |
3423 | SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from); | |
3424 | } | |
3425 | #endif | |
3426 | ||
3427 | /* Prefer registers not so far used, for use in temporary loading. | |
3428 | Among them, if REG_ALLOC_ORDER is defined, use that order. | |
3429 | Otherwise, prefer registers not preserved by calls. */ | |
3430 | ||
3431 | #ifdef REG_ALLOC_ORDER | |
3432 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3433 | { | |
3434 | int regno = reg_alloc_order[i]; | |
3435 | ||
3436 | if (hard_reg_n_uses[regno].uses == 0) | |
3437 | potential_reload_regs[o++] = regno; | |
3438 | } | |
3439 | #else | |
3440 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3441 | { | |
3442 | if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]) | |
3443 | potential_reload_regs[o++] = i; | |
3444 | } | |
3445 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3446 | { | |
3447 | if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]) | |
3448 | potential_reload_regs[o++] = i; | |
3449 | } | |
3450 | #endif | |
3451 | ||
3452 | qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER, | |
3453 | sizeof hard_reg_n_uses[0], hard_reg_use_compare); | |
3454 | ||
3455 | /* Now add the regs that are already used, | |
3456 | preferring those used less often. The fixed and otherwise forbidden | |
3457 | registers will be at the end of this list. */ | |
3458 | ||
3459 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3460 | if (hard_reg_n_uses[i].uses != 0) | |
3461 | potential_reload_regs[o++] = hard_reg_n_uses[i].regno; | |
3462 | } | |
3463 | \f | |
3464 | /* Reload pseudo-registers into hard regs around each insn as needed. | |
3465 | Additional register load insns are output before the insn that needs it | |
3466 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3467 | ||
3468 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3469 | which registers are already available in reload registers. |
32131a9c RK |
3470 | We update these for the reloads that we perform, |
3471 | as the insns are scanned. */ | |
3472 | ||
3473 | static void | |
3474 | reload_as_needed (first, live_known) | |
3475 | rtx first; | |
3476 | int live_known; | |
3477 | { | |
3478 | register rtx insn; | |
3479 | register int i; | |
3480 | int this_block = 0; | |
3481 | rtx x; | |
3482 | rtx after_call = 0; | |
3483 | ||
3484 | bzero (spill_reg_rtx, sizeof spill_reg_rtx); | |
3485 | reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx)); | |
3486 | bzero (reg_last_reload_reg, max_regno * sizeof (rtx)); | |
3487 | reg_has_output_reload = (char *) alloca (max_regno); | |
3488 | for (i = 0; i < n_spills; i++) | |
3489 | { | |
3490 | reg_reloaded_contents[i] = -1; | |
3491 | reg_reloaded_insn[i] = 0; | |
3492 | } | |
3493 | ||
3494 | /* Reset all offsets on eliminable registers to their initial values. */ | |
3495 | #ifdef ELIMINABLE_REGS | |
3496 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3497 | { | |
3498 | INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to, | |
510dd77e | 3499 | reg_eliminate[i].initial_offset); |
32131a9c RK |
3500 | reg_eliminate[i].previous_offset |
3501 | = reg_eliminate[i].offset = reg_eliminate[i].initial_offset; | |
3502 | } | |
3503 | #else | |
3504 | INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); | |
3505 | reg_eliminate[0].previous_offset | |
3506 | = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; | |
3507 | #endif | |
3508 | ||
3509 | num_not_at_initial_offset = 0; | |
3510 | ||
3511 | for (insn = first; insn;) | |
3512 | { | |
3513 | register rtx next = NEXT_INSN (insn); | |
3514 | ||
3515 | /* Notice when we move to a new basic block. */ | |
aa2c50d6 | 3516 | if (live_known && this_block + 1 < n_basic_blocks |
32131a9c RK |
3517 | && insn == basic_block_head[this_block+1]) |
3518 | ++this_block; | |
3519 | ||
3520 | /* If we pass a label, copy the offsets from the label information | |
3521 | into the current offsets of each elimination. */ | |
3522 | if (GET_CODE (insn) == CODE_LABEL) | |
2a4b5f3b RK |
3523 | { |
3524 | num_not_at_initial_offset = 0; | |
3525 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3526 | { | |
3527 | reg_eliminate[i].offset = reg_eliminate[i].previous_offset | |
3528 | = offsets_at[CODE_LABEL_NUMBER (insn)][i]; | |
1d0d98f3 RK |
3529 | if (reg_eliminate[i].can_eliminate |
3530 | && (reg_eliminate[i].offset | |
3531 | != reg_eliminate[i].initial_offset)) | |
2a4b5f3b RK |
3532 | num_not_at_initial_offset++; |
3533 | } | |
3534 | } | |
32131a9c RK |
3535 | |
3536 | else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
3537 | { | |
3538 | rtx avoid_return_reg = 0; | |
3539 | ||
3540 | #ifdef SMALL_REGISTER_CLASSES | |
3541 | /* Set avoid_return_reg if this is an insn | |
3542 | that might use the value of a function call. */ | |
3543 | if (GET_CODE (insn) == CALL_INSN) | |
3544 | { | |
3545 | if (GET_CODE (PATTERN (insn)) == SET) | |
3546 | after_call = SET_DEST (PATTERN (insn)); | |
3547 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
3548 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
3549 | after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
3550 | else | |
3551 | after_call = 0; | |
3552 | } | |
3553 | else if (after_call != 0 | |
3554 | && !(GET_CODE (PATTERN (insn)) == SET | |
3555 | && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) | |
3556 | { | |
3557 | if (reg_mentioned_p (after_call, PATTERN (insn))) | |
3558 | avoid_return_reg = after_call; | |
3559 | after_call = 0; | |
3560 | } | |
3561 | #endif /* SMALL_REGISTER_CLASSES */ | |
3562 | ||
2758481d RS |
3563 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3564 | references to eliminable registers have been removed. */ | |
3565 | ||
3566 | if ((GET_CODE (PATTERN (insn)) == USE | |
3567 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3568 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3569 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3570 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
fb3821f7 | 3571 | GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX); |
2758481d | 3572 | |
32131a9c RK |
3573 | /* If we need to do register elimination processing, do so. |
3574 | This might delete the insn, in which case we are done. */ | |
3575 | if (num_eliminable && GET_MODE (insn) == QImode) | |
3576 | { | |
3577 | eliminate_regs_in_insn (insn, 1); | |
3578 | if (GET_CODE (insn) == NOTE) | |
3579 | { | |
3580 | insn = next; | |
3581 | continue; | |
3582 | } | |
3583 | } | |
3584 | ||
3585 | if (GET_MODE (insn) == VOIDmode) | |
3586 | n_reloads = 0; | |
3587 | /* First find the pseudo regs that must be reloaded for this insn. | |
3588 | This info is returned in the tables reload_... (see reload.h). | |
3589 | Also modify the body of INSN by substituting RELOAD | |
3590 | rtx's for those pseudo regs. */ | |
3591 | else | |
3592 | { | |
3593 | bzero (reg_has_output_reload, max_regno); | |
3594 | CLEAR_HARD_REG_SET (reg_is_output_reload); | |
3595 | ||
3596 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3597 | spill_reg_order); | |
3598 | } | |
3599 | ||
3600 | if (n_reloads > 0) | |
3601 | { | |
3c3eeea6 RK |
3602 | rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn); |
3603 | rtx p; | |
32131a9c RK |
3604 | int class; |
3605 | ||
3606 | /* If this block has not had spilling done for a | |
546b63fb RK |
3607 | particular clas and we have any non-optionals that need a |
3608 | spill reg in that class, abort. */ | |
32131a9c RK |
3609 | |
3610 | for (class = 0; class < N_REG_CLASSES; class++) | |
3611 | if (basic_block_needs[class] != 0 | |
3612 | && basic_block_needs[class][this_block] == 0) | |
3613 | for (i = 0; i < n_reloads; i++) | |
546b63fb RK |
3614 | if (class == (int) reload_reg_class[i] |
3615 | && reload_reg_rtx[i] == 0 | |
3616 | && ! reload_optional[i] | |
3617 | && (reload_in[i] != 0 || reload_out[i] != 0 | |
3618 | || reload_secondary_p[i] != 0)) | |
3619 | abort (); | |
32131a9c RK |
3620 | |
3621 | /* Now compute which reload regs to reload them into. Perhaps | |
3622 | reusing reload regs from previous insns, or else output | |
3623 | load insns to reload them. Maybe output store insns too. | |
3624 | Record the choices of reload reg in reload_reg_rtx. */ | |
3625 | choose_reload_regs (insn, avoid_return_reg); | |
3626 | ||
546b63fb RK |
3627 | #ifdef SMALL_REGISTER_CLASSES |
3628 | /* Merge any reloads that we didn't combine for fear of | |
3629 | increasing the number of spill registers needed but now | |
3630 | discover can be safely merged. */ | |
3631 | merge_assigned_reloads (insn); | |
3632 | #endif | |
3633 | ||
32131a9c RK |
3634 | /* Generate the insns to reload operands into or out of |
3635 | their reload regs. */ | |
3636 | emit_reload_insns (insn); | |
3637 | ||
3638 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3639 | into the insn's body (or perhaps into the bodies of other | |
3640 | load and store insn that we just made for reloading | |
3641 | and that we moved the structure into). */ | |
3642 | subst_reloads (); | |
3c3eeea6 RK |
3643 | |
3644 | /* If this was an ASM, make sure that all the reload insns | |
3645 | we have generated are valid. If not, give an error | |
3646 | and delete them. */ | |
3647 | ||
3648 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3649 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
3650 | if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
3651 | && (recog_memoized (p) < 0 | |
3652 | || (insn_extract (p), | |
3653 | ! constrain_operands (INSN_CODE (p), 1)))) | |
3654 | { | |
3655 | error_for_asm (insn, | |
3656 | "`asm' operand requires impossible reload"); | |
3657 | PUT_CODE (p, NOTE); | |
3658 | NOTE_SOURCE_FILE (p) = 0; | |
3659 | NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; | |
3660 | } | |
32131a9c RK |
3661 | } |
3662 | /* Any previously reloaded spilled pseudo reg, stored in this insn, | |
3663 | is no longer validly lying around to save a future reload. | |
3664 | Note that this does not detect pseudos that were reloaded | |
3665 | for this insn in order to be stored in | |
3666 | (obeying register constraints). That is correct; such reload | |
3667 | registers ARE still valid. */ | |
3668 | note_stores (PATTERN (insn), forget_old_reloads_1); | |
3669 | ||
3670 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3671 | between INSN and NEXT and use them to forget old reloads. */ | |
3672 | for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x)) | |
3673 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) | |
3674 | note_stores (PATTERN (x), forget_old_reloads_1); | |
3675 | ||
3676 | #ifdef AUTO_INC_DEC | |
3677 | /* Likewise for regs altered by auto-increment in this insn. | |
3678 | But note that the reg-notes are not changed by reloading: | |
3679 | they still contain the pseudo-regs, not the spill regs. */ | |
3680 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
3681 | if (REG_NOTE_KIND (x) == REG_INC) | |
3682 | { | |
3683 | /* See if this pseudo reg was reloaded in this insn. | |
3684 | If so, its last-reload info is still valid | |
3685 | because it is based on this insn's reload. */ | |
3686 | for (i = 0; i < n_reloads; i++) | |
3687 | if (reload_out[i] == XEXP (x, 0)) | |
3688 | break; | |
3689 | ||
08fb99fa | 3690 | if (i == n_reloads) |
9a881562 | 3691 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX); |
32131a9c RK |
3692 | } |
3693 | #endif | |
3694 | } | |
3695 | /* A reload reg's contents are unknown after a label. */ | |
3696 | if (GET_CODE (insn) == CODE_LABEL) | |
3697 | for (i = 0; i < n_spills; i++) | |
3698 | { | |
3699 | reg_reloaded_contents[i] = -1; | |
3700 | reg_reloaded_insn[i] = 0; | |
3701 | } | |
3702 | ||
3703 | /* Don't assume a reload reg is still good after a call insn | |
3704 | if it is a call-used reg. */ | |
546b63fb | 3705 | else if (GET_CODE (insn) == CALL_INSN) |
32131a9c RK |
3706 | for (i = 0; i < n_spills; i++) |
3707 | if (call_used_regs[spill_regs[i]]) | |
3708 | { | |
3709 | reg_reloaded_contents[i] = -1; | |
3710 | reg_reloaded_insn[i] = 0; | |
3711 | } | |
3712 | ||
3713 | /* In case registers overlap, allow certain insns to invalidate | |
3714 | particular hard registers. */ | |
3715 | ||
3716 | #ifdef INSN_CLOBBERS_REGNO_P | |
3717 | for (i = 0 ; i < n_spills ; i++) | |
3718 | if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i])) | |
3719 | { | |
3720 | reg_reloaded_contents[i] = -1; | |
3721 | reg_reloaded_insn[i] = 0; | |
3722 | } | |
3723 | #endif | |
3724 | ||
3725 | insn = next; | |
3726 | ||
3727 | #ifdef USE_C_ALLOCA | |
3728 | alloca (0); | |
3729 | #endif | |
3730 | } | |
3731 | } | |
3732 | ||
3733 | /* Discard all record of any value reloaded from X, | |
3734 | or reloaded in X from someplace else; | |
3735 | unless X is an output reload reg of the current insn. | |
3736 | ||
3737 | X may be a hard reg (the reload reg) | |
3738 | or it may be a pseudo reg that was reloaded from. */ | |
3739 | ||
3740 | static void | |
9a881562 | 3741 | forget_old_reloads_1 (x, ignored) |
32131a9c | 3742 | rtx x; |
9a881562 | 3743 | rtx ignored; |
32131a9c RK |
3744 | { |
3745 | register int regno; | |
3746 | int nr; | |
0a2e51a9 RS |
3747 | int offset = 0; |
3748 | ||
3749 | /* note_stores does give us subregs of hard regs. */ | |
3750 | while (GET_CODE (x) == SUBREG) | |
3751 | { | |
3752 | offset += SUBREG_WORD (x); | |
3753 | x = SUBREG_REG (x); | |
3754 | } | |
32131a9c RK |
3755 | |
3756 | if (GET_CODE (x) != REG) | |
3757 | return; | |
3758 | ||
0a2e51a9 | 3759 | regno = REGNO (x) + offset; |
32131a9c RK |
3760 | |
3761 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3762 | nr = 1; | |
3763 | else | |
3764 | { | |
3765 | int i; | |
3766 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3767 | /* Storing into a spilled-reg invalidates its contents. | |
3768 | This can happen if a block-local pseudo is allocated to that reg | |
3769 | and it wasn't spilled because this block's total need is 0. | |
3770 | Then some insn might have an optional reload and use this reg. */ | |
3771 | for (i = 0; i < nr; i++) | |
3772 | if (spill_reg_order[regno + i] >= 0 | |
3773 | /* But don't do this if the reg actually serves as an output | |
3774 | reload reg in the current instruction. */ | |
3775 | && (n_reloads == 0 | |
3776 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))) | |
3777 | { | |
3778 | reg_reloaded_contents[spill_reg_order[regno + i]] = -1; | |
3779 | reg_reloaded_insn[spill_reg_order[regno + i]] = 0; | |
3780 | } | |
3781 | } | |
3782 | ||
3783 | /* Since value of X has changed, | |
3784 | forget any value previously copied from it. */ | |
3785 | ||
3786 | while (nr-- > 0) | |
3787 | /* But don't forget a copy if this is the output reload | |
3788 | that establishes the copy's validity. */ | |
3789 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
3790 | reg_last_reload_reg[regno + nr] = 0; | |
3791 | } | |
3792 | \f | |
3793 | /* For each reload, the mode of the reload register. */ | |
3794 | static enum machine_mode reload_mode[MAX_RELOADS]; | |
3795 | ||
3796 | /* For each reload, the largest number of registers it will require. */ | |
3797 | static int reload_nregs[MAX_RELOADS]; | |
3798 | ||
3799 | /* Comparison function for qsort to decide which of two reloads | |
3800 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
3801 | ||
3802 | static int | |
3803 | reload_reg_class_lower (p1, p2) | |
3804 | short *p1, *p2; | |
3805 | { | |
3806 | register int r1 = *p1, r2 = *p2; | |
3807 | register int t; | |
a8fdc208 | 3808 | |
32131a9c RK |
3809 | /* Consider required reloads before optional ones. */ |
3810 | t = reload_optional[r1] - reload_optional[r2]; | |
3811 | if (t != 0) | |
3812 | return t; | |
3813 | ||
3814 | /* Count all solitary classes before non-solitary ones. */ | |
3815 | t = ((reg_class_size[(int) reload_reg_class[r2]] == 1) | |
3816 | - (reg_class_size[(int) reload_reg_class[r1]] == 1)); | |
3817 | if (t != 0) | |
3818 | return t; | |
3819 | ||
3820 | /* Aside from solitaires, consider all multi-reg groups first. */ | |
3821 | t = reload_nregs[r2] - reload_nregs[r1]; | |
3822 | if (t != 0) | |
3823 | return t; | |
3824 | ||
3825 | /* Consider reloads in order of increasing reg-class number. */ | |
3826 | t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2]; | |
3827 | if (t != 0) | |
3828 | return t; | |
3829 | ||
3830 | /* If reloads are equally urgent, sort by reload number, | |
3831 | so that the results of qsort leave nothing to chance. */ | |
3832 | return r1 - r2; | |
3833 | } | |
3834 | \f | |
3835 | /* The following HARD_REG_SETs indicate when each hard register is | |
3836 | used for a reload of various parts of the current insn. */ | |
3837 | ||
3838 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ | |
3839 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
3840 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
3841 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
3842 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ | |
3843 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
3844 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ | |
3845 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
3846 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
3847 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
3848 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
3849 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
546b63fb RK |
3850 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
3851 | static HARD_REG_SET reload_reg_used_in_insn; | |
3852 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
3853 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
3854 | |
3855 | /* If reg is in use as a reload reg for any sort of reload. */ | |
3856 | static HARD_REG_SET reload_reg_used_at_all; | |
3857 | ||
be7ae2a4 RK |
3858 | /* If reg is use as an inherited reload. We just mark the first register |
3859 | in the group. */ | |
3860 | static HARD_REG_SET reload_reg_used_for_inherit; | |
3861 | ||
546b63fb RK |
3862 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
3863 | TYPE. MODE is used to indicate how many consecutive regs are | |
3864 | actually used. */ | |
32131a9c RK |
3865 | |
3866 | static void | |
546b63fb | 3867 | mark_reload_reg_in_use (regno, opnum, type, mode) |
32131a9c | 3868 | int regno; |
546b63fb RK |
3869 | int opnum; |
3870 | enum reload_type type; | |
32131a9c RK |
3871 | enum machine_mode mode; |
3872 | { | |
3873 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
3874 | int i; | |
3875 | ||
3876 | for (i = regno; i < nregs + regno; i++) | |
3877 | { | |
546b63fb | 3878 | switch (type) |
32131a9c RK |
3879 | { |
3880 | case RELOAD_OTHER: | |
3881 | SET_HARD_REG_BIT (reload_reg_used, i); | |
3882 | break; | |
3883 | ||
546b63fb RK |
3884 | case RELOAD_FOR_INPUT_ADDRESS: |
3885 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
3886 | break; |
3887 | ||
546b63fb RK |
3888 | case RELOAD_FOR_OUTPUT_ADDRESS: |
3889 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
3890 | break; |
3891 | ||
3892 | case RELOAD_FOR_OPERAND_ADDRESS: | |
3893 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
3894 | break; | |
3895 | ||
546b63fb RK |
3896 | case RELOAD_FOR_OTHER_ADDRESS: |
3897 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
3898 | break; | |
3899 | ||
32131a9c | 3900 | case RELOAD_FOR_INPUT: |
546b63fb | 3901 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
3902 | break; |
3903 | ||
3904 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
3905 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
3906 | break; | |
3907 | ||
3908 | case RELOAD_FOR_INSN: | |
3909 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
3910 | break; |
3911 | } | |
3912 | ||
3913 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
3914 | } | |
3915 | } | |
3916 | ||
be7ae2a4 RK |
3917 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
3918 | ||
3919 | static void | |
3920 | clear_reload_reg_in_use (regno, opnum, type, mode) | |
3921 | int regno; | |
3922 | int opnum; | |
3923 | enum reload_type type; | |
3924 | enum machine_mode mode; | |
3925 | { | |
3926 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
3927 | int i; | |
3928 | ||
3929 | for (i = regno; i < nregs + regno; i++) | |
3930 | { | |
3931 | switch (type) | |
3932 | { | |
3933 | case RELOAD_OTHER: | |
3934 | CLEAR_HARD_REG_BIT (reload_reg_used, i); | |
3935 | break; | |
3936 | ||
3937 | case RELOAD_FOR_INPUT_ADDRESS: | |
3938 | CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
3939 | break; | |
3940 | ||
3941 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
3942 | CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
3943 | break; | |
3944 | ||
3945 | case RELOAD_FOR_OPERAND_ADDRESS: | |
3946 | CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
3947 | break; | |
3948 | ||
3949 | case RELOAD_FOR_OTHER_ADDRESS: | |
3950 | CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
3951 | break; | |
3952 | ||
3953 | case RELOAD_FOR_INPUT: | |
3954 | CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); | |
3955 | break; | |
3956 | ||
3957 | case RELOAD_FOR_OUTPUT: | |
3958 | CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); | |
3959 | break; | |
3960 | ||
3961 | case RELOAD_FOR_INSN: | |
3962 | CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
3963 | break; | |
3964 | } | |
3965 | } | |
3966 | } | |
3967 | ||
32131a9c | 3968 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 3969 | specified by OPNUM and TYPE. */ |
32131a9c RK |
3970 | |
3971 | static int | |
546b63fb | 3972 | reload_reg_free_p (regno, opnum, type) |
32131a9c | 3973 | int regno; |
546b63fb RK |
3974 | int opnum; |
3975 | enum reload_type type; | |
32131a9c | 3976 | { |
546b63fb RK |
3977 | int i; |
3978 | ||
3979 | /* In use for a RELOAD_OTHER means it's not available for anything except | |
3980 | RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known | |
3981 | to be used only for inputs. */ | |
3982 | ||
3983 | if (type != RELOAD_FOR_OTHER_ADDRESS | |
3984 | && TEST_HARD_REG_BIT (reload_reg_used, regno)) | |
32131a9c | 3985 | return 0; |
546b63fb RK |
3986 | |
3987 | switch (type) | |
32131a9c RK |
3988 | { |
3989 | case RELOAD_OTHER: | |
3990 | /* In use for anything means not available for a RELOAD_OTHER. */ | |
3991 | return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno); | |
3992 | ||
3993 | /* The other kinds of use can sometimes share a register. */ | |
3994 | case RELOAD_FOR_INPUT: | |
546b63fb RK |
3995 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
3996 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
3997 | return 0; | |
3998 | ||
3999 | /* If it is used for some other input, can't use it. */ | |
4000 | for (i = 0; i < reload_n_operands; i++) | |
4001 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4002 | return 0; | |
4003 | ||
4004 | /* If it is used in a later operand's address, can't use it. */ | |
4005 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4006 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) | |
4007 | return 0; | |
4008 | ||
4009 | return 1; | |
4010 | ||
4011 | case RELOAD_FOR_INPUT_ADDRESS: | |
4012 | /* Can't use a register if it is used for an input address for this | |
4013 | operand or used as an input in an earlier one. */ | |
4014 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)) | |
4015 | return 0; | |
4016 | ||
4017 | for (i = 0; i < opnum; i++) | |
4018 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4019 | return 0; | |
4020 | ||
4021 | return 1; | |
4022 | ||
4023 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4024 | /* Can't use a register if it is used for an output address for this | |
4025 | operand or used as an output in this or a later operand. */ | |
4026 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) | |
4027 | return 0; | |
4028 | ||
4029 | for (i = opnum; i < reload_n_operands; i++) | |
4030 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4031 | return 0; | |
4032 | ||
4033 | return 1; | |
4034 | ||
32131a9c | 4035 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4036 | for (i = 0; i < reload_n_operands; i++) |
4037 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4038 | return 0; | |
4039 | ||
4040 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4041 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4042 | ||
32131a9c | 4043 | case RELOAD_FOR_OUTPUT: |
546b63fb RK |
4044 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
4045 | outputs, or an operand address for this or an earlier output. */ | |
4046 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4047 | return 0; | |
4048 | ||
4049 | for (i = 0; i < reload_n_operands; i++) | |
4050 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4051 | return 0; | |
4052 | ||
4053 | for (i = 0; i <= opnum; i++) | |
4054 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)) | |
4055 | return 0; | |
4056 | ||
4057 | return 1; | |
4058 | ||
4059 | case RELOAD_FOR_INSN: | |
4060 | for (i = 0; i < reload_n_operands; i++) | |
4061 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4062 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4063 | return 0; | |
4064 | ||
4065 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4066 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4067 | ||
4068 | case RELOAD_FOR_OTHER_ADDRESS: | |
4069 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4070 | } |
4071 | abort (); | |
4072 | } | |
4073 | ||
4074 | /* Return 1 if the value in reload reg REGNO, as used by a reload | |
546b63fb | 4075 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4076 | is not in use for a reload in any prior part of the insn. |
4077 | ||
4078 | We can assume that the reload reg was already tested for availability | |
4079 | at the time it is needed, and we should not check this again, | |
4080 | in case the reg has already been marked in use. */ | |
4081 | ||
4082 | static int | |
546b63fb | 4083 | reload_reg_free_before_p (regno, opnum, type) |
32131a9c | 4084 | int regno; |
546b63fb RK |
4085 | int opnum; |
4086 | enum reload_type type; | |
32131a9c | 4087 | { |
546b63fb RK |
4088 | int i; |
4089 | ||
4090 | switch (type) | |
32131a9c | 4091 | { |
546b63fb RK |
4092 | case RELOAD_FOR_OTHER_ADDRESS: |
4093 | /* These always come first. */ | |
32131a9c RK |
4094 | return 1; |
4095 | ||
546b63fb RK |
4096 | case RELOAD_OTHER: |
4097 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
4098 | ||
32131a9c | 4099 | /* If this use is for part of the insn, |
546b63fb RK |
4100 | check the reg is not in use for any prior part. It is tempting |
4101 | to try to do this by falling through from objecs that occur | |
4102 | later in the insn to ones that occur earlier, but that will not | |
4103 | correctly take into account the fact that here we MUST ignore | |
4104 | things that would prevent the register from being allocated in | |
4105 | the first place, since we know that it was allocated. */ | |
4106 | ||
4107 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4108 | /* Earlier reloads are for earlier outputs or their addresses, | |
4109 | any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any | |
4110 | RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with | |
4111 | RELOAD_OTHER).. */ | |
4112 | for (i = 0; i < opnum; i++) | |
4113 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
4114 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4115 | return 0; | |
4116 | ||
4117 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
32131a9c | 4118 | return 0; |
546b63fb RK |
4119 | |
4120 | for (i = 0; i < reload_n_operands; i++) | |
4121 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
4122 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4123 | return 0; | |
4124 | ||
4125 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
4126 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4127 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4128 | ||
32131a9c | 4129 | case RELOAD_FOR_OUTPUT: |
546b63fb RK |
4130 | /* This can't be used in the output address for this operand and |
4131 | anything that can't be used for it, except that we've already | |
4132 | tested for RELOAD_FOR_INSN objects. */ | |
4133 | ||
4134 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) | |
32131a9c | 4135 | return 0; |
546b63fb RK |
4136 | |
4137 | for (i = 0; i < opnum; i++) | |
4138 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
4139 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4140 | return 0; | |
4141 | ||
4142 | for (i = 0; i < reload_n_operands; i++) | |
4143 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
4144 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4145 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4146 | return 0; | |
4147 | ||
4148 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
4149 | ||
32131a9c | 4150 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4151 | case RELOAD_FOR_INSN: |
4152 | /* These can't conflict with inputs, or each other, so all we have to | |
4153 | test is input addresses and the addresses of OTHER items. */ | |
4154 | ||
4155 | for (i = 0; i < reload_n_operands; i++) | |
4156 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) | |
4157 | return 0; | |
4158 | ||
4159 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
4160 | ||
32131a9c | 4161 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4162 | /* The only things earlier are the address for this and |
4163 | earlier inputs, other inputs (which we know we don't conflict | |
4164 | with), and addresses of RELOAD_OTHER objects. */ | |
4165 | ||
4166 | for (i = 0; i <= opnum; i++) | |
4167 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) | |
4168 | return 0; | |
4169 | ||
4170 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
4171 | ||
4172 | case RELOAD_FOR_INPUT_ADDRESS: | |
4173 | /* Similarly, all we have to check is for use in earlier inputs' | |
4174 | addresses. */ | |
4175 | for (i = 0; i < opnum; i++) | |
4176 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) | |
4177 | return 0; | |
4178 | ||
4179 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4180 | } |
4181 | abort (); | |
4182 | } | |
4183 | ||
4184 | /* Return 1 if the value in reload reg REGNO, as used by a reload | |
546b63fb | 4185 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4186 | is still available in REGNO at the end of the insn. |
4187 | ||
4188 | We can assume that the reload reg was already tested for availability | |
4189 | at the time it is needed, and we should not check this again, | |
4190 | in case the reg has already been marked in use. */ | |
4191 | ||
4192 | static int | |
546b63fb | 4193 | reload_reg_reaches_end_p (regno, opnum, type) |
32131a9c | 4194 | int regno; |
546b63fb RK |
4195 | int opnum; |
4196 | enum reload_type type; | |
32131a9c | 4197 | { |
546b63fb RK |
4198 | int i; |
4199 | ||
4200 | switch (type) | |
32131a9c RK |
4201 | { |
4202 | case RELOAD_OTHER: | |
4203 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4204 | its value must reach the end. */ | |
4205 | return 1; | |
4206 | ||
4207 | /* If this use is for part of the insn, | |
546b63fb RK |
4208 | its value reaches if no subsequent part uses the same register. |
4209 | Just like the above function, don't try to do this with lots | |
4210 | of fallthroughs. */ | |
4211 | ||
4212 | case RELOAD_FOR_OTHER_ADDRESS: | |
4213 | /* Here we check for everything else, since these don't conflict | |
4214 | with anything else and everything comes later. */ | |
4215 | ||
4216 | for (i = 0; i < reload_n_operands; i++) | |
4217 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
4218 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) | |
4219 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
4220 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4221 | return 0; | |
4222 | ||
4223 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4224 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4225 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4226 | ||
4227 | case RELOAD_FOR_INPUT_ADDRESS: | |
4228 | /* Similar, except that we check only for this and subsequent inputs | |
4229 | and the address of only subsequent inputs and we do not need | |
4230 | to check for RELOAD_OTHER objects since they are known not to | |
4231 | conflict. */ | |
4232 | ||
4233 | for (i = opnum; i < reload_n_operands; i++) | |
4234 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4235 | return 0; | |
4236 | ||
4237 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4238 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)) | |
4239 | return 0; | |
4240 | ||
4241 | for (i = 0; i < reload_n_operands; i++) | |
4242 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
4243 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4244 | return 0; | |
4245 | ||
4246 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4247 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); | |
4248 | ||
32131a9c | 4249 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4250 | /* Similar to input address, except we start at the next operand for |
4251 | both input and input address and we do not check for | |
4252 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these | |
4253 | would conflict. */ | |
4254 | ||
4255 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4256 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
4257 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4258 | return 0; | |
4259 | ||
4260 | /* ... fall through ... */ | |
4261 | ||
32131a9c | 4262 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4263 | /* Check outputs and their addresses. */ |
4264 | ||
4265 | for (i = 0; i < reload_n_operands; i++) | |
4266 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
4267 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4268 | return 0; | |
4269 | ||
4270 | return 1; | |
4271 | ||
4272 | case RELOAD_FOR_INSN: | |
4273 | /* These conflict with other outputs with with RELOAD_OTHER. So | |
4274 | we need only check for output addresses. */ | |
4275 | ||
4276 | opnum = -1; | |
4277 | ||
4278 | /* ... fall through ... */ | |
4279 | ||
32131a9c | 4280 | case RELOAD_FOR_OUTPUT: |
546b63fb RK |
4281 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4282 | /* We already know these can't conflict with a later output. So the | |
4283 | only thing to check are later output addresses. */ | |
4284 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4285 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)) | |
4286 | return 0; | |
4287 | ||
32131a9c RK |
4288 | return 1; |
4289 | } | |
546b63fb | 4290 | |
32131a9c RK |
4291 | abort (); |
4292 | } | |
4293 | \f | |
4294 | /* Vector of reload-numbers showing the order in which the reloads should | |
4295 | be processed. */ | |
4296 | short reload_order[MAX_RELOADS]; | |
4297 | ||
4298 | /* Indexed by reload number, 1 if incoming value | |
4299 | inherited from previous insns. */ | |
4300 | char reload_inherited[MAX_RELOADS]; | |
4301 | ||
4302 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4303 | if we know it. Otherwise, this is 0. */ | |
4304 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4305 | ||
4306 | /* If non-zero, this is a place to get the value of the reload, | |
4307 | rather than using reload_in. */ | |
4308 | rtx reload_override_in[MAX_RELOADS]; | |
4309 | ||
4310 | /* For each reload, the index in spill_regs of the spill register used, | |
4311 | or -1 if we did not need one of the spill registers for this reload. */ | |
4312 | int reload_spill_index[MAX_RELOADS]; | |
4313 | ||
4314 | /* Index of last register assigned as a spill register. We allocate in | |
4315 | a round-robin fashio. */ | |
4316 | ||
1d2310f3 | 4317 | static int last_spill_reg = 0; |
32131a9c RK |
4318 | |
4319 | /* Find a spill register to use as a reload register for reload R. | |
4320 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
4321 | processed. | |
4322 | ||
4323 | Set reload_reg_rtx[R] to the register allocated. | |
4324 | ||
4325 | If NOERROR is nonzero, we return 1 if successful, | |
4326 | or 0 if we couldn't find a spill reg and we didn't change anything. */ | |
4327 | ||
4328 | static int | |
4329 | allocate_reload_reg (r, insn, last_reload, noerror) | |
4330 | int r; | |
4331 | rtx insn; | |
4332 | int last_reload; | |
4333 | int noerror; | |
4334 | { | |
4335 | int i; | |
4336 | int pass; | |
4337 | int count; | |
4338 | rtx new; | |
4339 | int regno; | |
4340 | ||
4341 | /* If we put this reload ahead, thinking it is a group, | |
4342 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 4343 | reg that some other reload needs. |
32131a9c RK |
4344 | (That can happen when we have a 68000 DATA_OR_FP_REG |
4345 | which is a group of data regs or one fp reg.) | |
4346 | We need not be so restrictive if there are no more reloads | |
4347 | for this insn. | |
4348 | ||
4349 | ??? Really it would be nicer to have smarter handling | |
4350 | for that kind of reg class, where a problem like this is normal. | |
4351 | Perhaps those classes should be avoided for reloading | |
4352 | by use of more alternatives. */ | |
4353 | ||
4354 | int force_group = reload_nregs[r] > 1 && ! last_reload; | |
4355 | ||
4356 | /* If we want a single register and haven't yet found one, | |
4357 | take any reg in the right class and not in use. | |
4358 | If we want a consecutive group, here is where we look for it. | |
4359 | ||
4360 | We use two passes so we can first look for reload regs to | |
4361 | reuse, which are already in use for other reloads in this insn, | |
4362 | and only then use additional registers. | |
4363 | I think that maximizing reuse is needed to make sure we don't | |
4364 | run out of reload regs. Suppose we have three reloads, and | |
4365 | reloads A and B can share regs. These need two regs. | |
4366 | Suppose A and B are given different regs. | |
4367 | That leaves none for C. */ | |
4368 | for (pass = 0; pass < 2; pass++) | |
4369 | { | |
4370 | /* I is the index in spill_regs. | |
4371 | We advance it round-robin between insns to use all spill regs | |
4372 | equally, so that inherited reloads have a chance | |
4373 | of leapfrogging each other. */ | |
4374 | ||
4375 | for (count = 0, i = last_spill_reg; count < n_spills; count++) | |
4376 | { | |
4377 | int class = (int) reload_reg_class[r]; | |
4378 | ||
4379 | i = (i + 1) % n_spills; | |
4380 | ||
546b63fb RK |
4381 | if (reload_reg_free_p (spill_regs[i], reload_opnum[r], |
4382 | reload_when_needed[r]) | |
32131a9c RK |
4383 | && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i]) |
4384 | && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r]) | |
be7ae2a4 RK |
4385 | /* Look first for regs to share, then for unshared. But |
4386 | don't share regs used for inherited reloads; they are | |
4387 | the ones we want to preserve. */ | |
4388 | && (pass | |
4389 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
4390 | spill_regs[i]) | |
4391 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, | |
4392 | spill_regs[i])))) | |
32131a9c RK |
4393 | { |
4394 | int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); | |
4395 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG | |
4396 | (on 68000) got us two FP regs. If NR is 1, | |
4397 | we would reject both of them. */ | |
4398 | if (force_group) | |
4399 | nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]); | |
4400 | /* If we need only one reg, we have already won. */ | |
4401 | if (nr == 1) | |
4402 | { | |
4403 | /* But reject a single reg if we demand a group. */ | |
4404 | if (force_group) | |
4405 | continue; | |
4406 | break; | |
4407 | } | |
4408 | /* Otherwise check that as many consecutive regs as we need | |
4409 | are available here. | |
4410 | Also, don't use for a group registers that are | |
4411 | needed for nongroups. */ | |
4412 | if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i])) | |
4413 | while (nr > 1) | |
4414 | { | |
4415 | regno = spill_regs[i] + nr - 1; | |
4416 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
4417 | && spill_reg_order[regno] >= 0 | |
546b63fb RK |
4418 | && reload_reg_free_p (regno, reload_opnum[r], |
4419 | reload_when_needed[r]) | |
32131a9c RK |
4420 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, |
4421 | regno))) | |
4422 | break; | |
4423 | nr--; | |
4424 | } | |
4425 | if (nr == 1) | |
4426 | break; | |
4427 | } | |
4428 | } | |
4429 | ||
4430 | /* If we found something on pass 1, omit pass 2. */ | |
4431 | if (count < n_spills) | |
4432 | break; | |
4433 | } | |
4434 | ||
4435 | /* We should have found a spill register by now. */ | |
4436 | if (count == n_spills) | |
4437 | { | |
4438 | if (noerror) | |
4439 | return 0; | |
139fc12e | 4440 | goto failure; |
32131a9c RK |
4441 | } |
4442 | ||
be7ae2a4 RK |
4443 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
4444 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c RK |
4445 | |
4446 | new = spill_reg_rtx[i]; | |
4447 | ||
4448 | if (new == 0 || GET_MODE (new) != reload_mode[r]) | |
be7ae2a4 RK |
4449 | spill_reg_rtx[i] = new |
4450 | = gen_rtx (REG, reload_mode[r], spill_regs[i]); | |
4451 | ||
32131a9c RK |
4452 | regno = true_regnum (new); |
4453 | ||
4454 | /* Detect when the reload reg can't hold the reload mode. | |
4455 | This used to be one `if', but Sequent compiler can't handle that. */ | |
4456 | if (HARD_REGNO_MODE_OK (regno, reload_mode[r])) | |
4457 | { | |
4458 | enum machine_mode test_mode = VOIDmode; | |
4459 | if (reload_in[r]) | |
4460 | test_mode = GET_MODE (reload_in[r]); | |
4461 | /* If reload_in[r] has VOIDmode, it means we will load it | |
4462 | in whatever mode the reload reg has: to wit, reload_mode[r]. | |
4463 | We have already tested that for validity. */ | |
4464 | /* Aside from that, we need to test that the expressions | |
4465 | to reload from or into have modes which are valid for this | |
4466 | reload register. Otherwise the reload insns would be invalid. */ | |
4467 | if (! (reload_in[r] != 0 && test_mode != VOIDmode | |
4468 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
4469 | if (! (reload_out[r] != 0 | |
4470 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r])))) | |
be7ae2a4 RK |
4471 | { |
4472 | /* The reg is OK. */ | |
4473 | last_spill_reg = i; | |
4474 | ||
4475 | /* Mark as in use for this insn the reload regs we use | |
4476 | for this. */ | |
4477 | mark_reload_reg_in_use (spill_regs[i], reload_opnum[r], | |
4478 | reload_when_needed[r], reload_mode[r]); | |
4479 | ||
4480 | reload_reg_rtx[r] = new; | |
4481 | reload_spill_index[r] = i; | |
4482 | return 1; | |
4483 | } | |
32131a9c RK |
4484 | } |
4485 | ||
4486 | /* The reg is not OK. */ | |
4487 | if (noerror) | |
4488 | return 0; | |
4489 | ||
139fc12e | 4490 | failure: |
32131a9c RK |
4491 | if (asm_noperands (PATTERN (insn)) < 0) |
4492 | /* It's the compiler's fault. */ | |
4493 | abort (); | |
4494 | ||
4495 | /* It's the user's fault; the operand's mode and constraint | |
4496 | don't match. Disable this reload so we don't crash in final. */ | |
4497 | error_for_asm (insn, | |
4498 | "`asm' operand constraint incompatible with operand size"); | |
4499 | reload_in[r] = 0; | |
4500 | reload_out[r] = 0; | |
4501 | reload_reg_rtx[r] = 0; | |
4502 | reload_optional[r] = 1; | |
4503 | reload_secondary_p[r] = 1; | |
4504 | ||
4505 | return 1; | |
4506 | } | |
4507 | \f | |
4508 | /* Assign hard reg targets for the pseudo-registers we must reload | |
4509 | into hard regs for this insn. | |
4510 | Also output the instructions to copy them in and out of the hard regs. | |
4511 | ||
4512 | For machines with register classes, we are responsible for | |
4513 | finding a reload reg in the proper class. */ | |
4514 | ||
4515 | static void | |
4516 | choose_reload_regs (insn, avoid_return_reg) | |
4517 | rtx insn; | |
32131a9c RK |
4518 | rtx avoid_return_reg; |
4519 | { | |
4520 | register int i, j; | |
4521 | int max_group_size = 1; | |
4522 | enum reg_class group_class = NO_REGS; | |
4523 | int inheritance; | |
4524 | ||
4525 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
4526 | char save_reload_inherited[MAX_RELOADS]; | |
4527 | rtx save_reload_inheritance_insn[MAX_RELOADS]; | |
4528 | rtx save_reload_override_in[MAX_RELOADS]; | |
4529 | int save_reload_spill_index[MAX_RELOADS]; | |
4530 | HARD_REG_SET save_reload_reg_used; | |
546b63fb RK |
4531 | HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; |
4532 | HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
4533 | HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4534 | HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c | 4535 | HARD_REG_SET save_reload_reg_used_in_op_addr; |
546b63fb RK |
4536 | HARD_REG_SET save_reload_reg_used_in_insn; |
4537 | HARD_REG_SET save_reload_reg_used_in_other_addr; | |
32131a9c RK |
4538 | HARD_REG_SET save_reload_reg_used_at_all; |
4539 | ||
4540 | bzero (reload_inherited, MAX_RELOADS); | |
4541 | bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); | |
4542 | bzero (reload_override_in, MAX_RELOADS * sizeof (rtx)); | |
4543 | ||
4544 | CLEAR_HARD_REG_SET (reload_reg_used); | |
4545 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 4546 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
546b63fb RK |
4547 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
4548 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 4549 | |
546b63fb RK |
4550 | for (i = 0; i < reload_n_operands; i++) |
4551 | { | |
4552 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
4553 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
4554 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
4555 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); | |
4556 | } | |
32131a9c RK |
4557 | |
4558 | #ifdef SMALL_REGISTER_CLASSES | |
4559 | /* Don't bother with avoiding the return reg | |
4560 | if we have no mandatory reload that could use it. */ | |
4561 | if (avoid_return_reg) | |
4562 | { | |
4563 | int do_avoid = 0; | |
4564 | int regno = REGNO (avoid_return_reg); | |
4565 | int nregs | |
4566 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
4567 | int r; | |
4568 | ||
4569 | for (r = regno; r < regno + nregs; r++) | |
4570 | if (spill_reg_order[r] >= 0) | |
4571 | for (j = 0; j < n_reloads; j++) | |
4572 | if (!reload_optional[j] && reload_reg_rtx[j] == 0 | |
4573 | && (reload_in[j] != 0 || reload_out[j] != 0 | |
4574 | || reload_secondary_p[j]) | |
4575 | && | |
4576 | TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r)) | |
4577 | do_avoid = 1; | |
4578 | if (!do_avoid) | |
4579 | avoid_return_reg = 0; | |
4580 | } | |
4581 | #endif /* SMALL_REGISTER_CLASSES */ | |
4582 | ||
4583 | #if 0 /* Not needed, now that we can always retry without inheritance. */ | |
4584 | /* See if we have more mandatory reloads than spill regs. | |
4585 | If so, then we cannot risk optimizations that could prevent | |
a8fdc208 | 4586 | reloads from sharing one spill register. |
32131a9c RK |
4587 | |
4588 | Since we will try finding a better register than reload_reg_rtx | |
4589 | unless it is equal to reload_in or reload_out, count such reloads. */ | |
4590 | ||
4591 | { | |
4592 | int tem = 0; | |
4593 | #ifdef SMALL_REGISTER_CLASSES | |
4594 | int tem = (avoid_return_reg != 0); | |
a8fdc208 | 4595 | #endif |
32131a9c RK |
4596 | for (j = 0; j < n_reloads; j++) |
4597 | if (! reload_optional[j] | |
4598 | && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j]) | |
4599 | && (reload_reg_rtx[j] == 0 | |
4600 | || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j]) | |
4601 | && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j])))) | |
4602 | tem++; | |
4603 | if (tem > n_spills) | |
4604 | must_reuse = 1; | |
4605 | } | |
4606 | #endif | |
4607 | ||
4608 | #ifdef SMALL_REGISTER_CLASSES | |
4609 | /* Don't use the subroutine call return reg for a reload | |
4610 | if we are supposed to avoid it. */ | |
4611 | if (avoid_return_reg) | |
4612 | { | |
4613 | int regno = REGNO (avoid_return_reg); | |
4614 | int nregs | |
4615 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
4616 | int r; | |
4617 | ||
4618 | for (r = regno; r < regno + nregs; r++) | |
4619 | if (spill_reg_order[r] >= 0) | |
4620 | SET_HARD_REG_BIT (reload_reg_used, r); | |
4621 | } | |
4622 | #endif /* SMALL_REGISTER_CLASSES */ | |
4623 | ||
4624 | /* In order to be certain of getting the registers we need, | |
4625 | we must sort the reloads into order of increasing register class. | |
4626 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 4627 | that provided the reload registers. |
32131a9c RK |
4628 | |
4629 | Also note whether any of the reloads wants a consecutive group of regs. | |
4630 | If so, record the maximum size of the group desired and what | |
4631 | register class contains all the groups needed by this insn. */ | |
4632 | ||
4633 | for (j = 0; j < n_reloads; j++) | |
4634 | { | |
4635 | reload_order[j] = j; | |
4636 | reload_spill_index[j] = -1; | |
4637 | ||
4638 | reload_mode[j] | |
546b63fb RK |
4639 | = (reload_inmode[j] == VOIDmode |
4640 | || (GET_MODE_SIZE (reload_outmode[j]) | |
4641 | > GET_MODE_SIZE (reload_inmode[j]))) | |
4642 | ? reload_outmode[j] : reload_inmode[j]; | |
32131a9c RK |
4643 | |
4644 | reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]); | |
4645 | ||
4646 | if (reload_nregs[j] > 1) | |
4647 | { | |
4648 | max_group_size = MAX (reload_nregs[j], max_group_size); | |
4649 | group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class]; | |
4650 | } | |
4651 | ||
4652 | /* If we have already decided to use a certain register, | |
4653 | don't use it in another way. */ | |
4654 | if (reload_reg_rtx[j]) | |
546b63fb | 4655 | mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j], |
32131a9c RK |
4656 | reload_when_needed[j], reload_mode[j]); |
4657 | } | |
4658 | ||
4659 | if (n_reloads > 1) | |
4660 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
4661 | ||
4662 | bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx); | |
4663 | bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited); | |
4664 | bcopy (reload_inheritance_insn, save_reload_inheritance_insn, | |
4665 | sizeof reload_inheritance_insn); | |
4666 | bcopy (reload_override_in, save_reload_override_in, | |
4667 | sizeof reload_override_in); | |
4668 | bcopy (reload_spill_index, save_reload_spill_index, | |
4669 | sizeof reload_spill_index); | |
4670 | COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used); | |
4671 | COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all); | |
32131a9c RK |
4672 | COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr, |
4673 | reload_reg_used_in_op_addr); | |
546b63fb RK |
4674 | COPY_HARD_REG_SET (save_reload_reg_used_in_insn, |
4675 | reload_reg_used_in_insn); | |
4676 | COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr, | |
4677 | reload_reg_used_in_other_addr); | |
4678 | ||
4679 | for (i = 0; i < reload_n_operands; i++) | |
4680 | { | |
4681 | COPY_HARD_REG_SET (save_reload_reg_used_in_output[i], | |
4682 | reload_reg_used_in_output[i]); | |
4683 | COPY_HARD_REG_SET (save_reload_reg_used_in_input[i], | |
4684 | reload_reg_used_in_input[i]); | |
4685 | COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i], | |
4686 | reload_reg_used_in_input_addr[i]); | |
4687 | COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i], | |
4688 | reload_reg_used_in_output_addr[i]); | |
4689 | } | |
32131a9c | 4690 | |
58b1581b RS |
4691 | /* If -O, try first with inheritance, then turning it off. |
4692 | If not -O, don't do inheritance. | |
4693 | Using inheritance when not optimizing leads to paradoxes | |
4694 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
4695 | because one side of the comparison might be inherited. */ | |
32131a9c | 4696 | |
58b1581b | 4697 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c RK |
4698 | { |
4699 | /* Process the reloads in order of preference just found. | |
4700 | Beyond this point, subregs can be found in reload_reg_rtx. | |
4701 | ||
4702 | This used to look for an existing reloaded home for all | |
4703 | of the reloads, and only then perform any new reloads. | |
4704 | But that could lose if the reloads were done out of reg-class order | |
4705 | because a later reload with a looser constraint might have an old | |
4706 | home in a register needed by an earlier reload with a tighter constraint. | |
4707 | ||
4708 | To solve this, we make two passes over the reloads, in the order | |
4709 | described above. In the first pass we try to inherit a reload | |
4710 | from a previous insn. If there is a later reload that needs a | |
4711 | class that is a proper subset of the class being processed, we must | |
4712 | also allocate a spill register during the first pass. | |
4713 | ||
4714 | Then make a second pass over the reloads to allocate any reloads | |
4715 | that haven't been given registers yet. */ | |
4716 | ||
be7ae2a4 RK |
4717 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
4718 | ||
32131a9c RK |
4719 | for (j = 0; j < n_reloads; j++) |
4720 | { | |
4721 | register int r = reload_order[j]; | |
4722 | ||
4723 | /* Ignore reloads that got marked inoperative. */ | |
4724 | if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) | |
4725 | continue; | |
4726 | ||
4727 | /* If find_reloads chose a to use reload_in or reload_out as a reload | |
4728 | register, we don't need to chose one. Otherwise, try even if it found | |
4729 | one since we might save an insn if we find the value lying around. */ | |
4730 | if (reload_in[r] != 0 && reload_reg_rtx[r] != 0 | |
4731 | && (rtx_equal_p (reload_in[r], reload_reg_rtx[r]) | |
4732 | || rtx_equal_p (reload_out[r], reload_reg_rtx[r]))) | |
4733 | continue; | |
4734 | ||
4735 | #if 0 /* No longer needed for correct operation. | |
4736 | It might give better code, or might not; worth an experiment? */ | |
4737 | /* If this is an optional reload, we can't inherit from earlier insns | |
4738 | until we are sure that any non-optional reloads have been allocated. | |
4739 | The following code takes advantage of the fact that optional reloads | |
4740 | are at the end of reload_order. */ | |
4741 | if (reload_optional[r] != 0) | |
4742 | for (i = 0; i < j; i++) | |
4743 | if ((reload_out[reload_order[i]] != 0 | |
4744 | || reload_in[reload_order[i]] != 0 | |
4745 | || reload_secondary_p[reload_order[i]]) | |
4746 | && ! reload_optional[reload_order[i]] | |
4747 | && reload_reg_rtx[reload_order[i]] == 0) | |
4748 | allocate_reload_reg (reload_order[i], insn, 0, inheritance); | |
4749 | #endif | |
4750 | ||
4751 | /* First see if this pseudo is already available as reloaded | |
4752 | for a previous insn. We cannot try to inherit for reloads | |
4753 | that are smaller than the maximum number of registers needed | |
4754 | for groups unless the register we would allocate cannot be used | |
4755 | for the groups. | |
4756 | ||
4757 | We could check here to see if this is a secondary reload for | |
4758 | an object that is already in a register of the desired class. | |
4759 | This would avoid the need for the secondary reload register. | |
4760 | But this is complex because we can't easily determine what | |
4761 | objects might want to be loaded via this reload. So let a register | |
4762 | be allocated here. In `emit_reload_insns' we suppress one of the | |
4763 | loads in the case described above. */ | |
4764 | ||
4765 | if (inheritance) | |
4766 | { | |
4767 | register int regno = -1; | |
db660765 | 4768 | enum machine_mode mode; |
32131a9c RK |
4769 | |
4770 | if (reload_in[r] == 0) | |
4771 | ; | |
4772 | else if (GET_CODE (reload_in[r]) == REG) | |
db660765 TW |
4773 | { |
4774 | regno = REGNO (reload_in[r]); | |
4775 | mode = GET_MODE (reload_in[r]); | |
4776 | } | |
32131a9c | 4777 | else if (GET_CODE (reload_in_reg[r]) == REG) |
db660765 TW |
4778 | { |
4779 | regno = REGNO (reload_in_reg[r]); | |
4780 | mode = GET_MODE (reload_in_reg[r]); | |
4781 | } | |
32131a9c RK |
4782 | #if 0 |
4783 | /* This won't work, since REGNO can be a pseudo reg number. | |
4784 | Also, it takes much more hair to keep track of all the things | |
4785 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
4786 | else if (GET_CODE (reload_in[r]) == SUBREG | |
4787 | && GET_CODE (SUBREG_REG (reload_in[r])) == REG) | |
4788 | regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]); | |
4789 | #endif | |
4790 | ||
4791 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
4792 | { | |
4793 | i = spill_reg_order[REGNO (reg_last_reload_reg[regno])]; | |
4794 | ||
4795 | if (reg_reloaded_contents[i] == regno | |
db660765 TW |
4796 | && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])) |
4797 | >= GET_MODE_SIZE (mode)) | |
32131a9c RK |
4798 | && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r]) |
4799 | && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], | |
4800 | spill_regs[i]) | |
4801 | && (reload_nregs[r] == max_group_size | |
4802 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], | |
4803 | spill_regs[i])) | |
546b63fb RK |
4804 | && reload_reg_free_p (spill_regs[i], reload_opnum[r], |
4805 | reload_when_needed[r]) | |
32131a9c | 4806 | && reload_reg_free_before_p (spill_regs[i], |
546b63fb | 4807 | reload_opnum[r], |
32131a9c RK |
4808 | reload_when_needed[r])) |
4809 | { | |
4810 | /* If a group is needed, verify that all the subsequent | |
4811 | registers still have their values intact. */ | |
4812 | int nr | |
4813 | = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); | |
4814 | int k; | |
4815 | ||
4816 | for (k = 1; k < nr; k++) | |
4817 | if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] | |
4818 | != regno) | |
4819 | break; | |
4820 | ||
4821 | if (k == nr) | |
4822 | { | |
4823 | /* Mark the register as in use for this part of | |
4824 | the insn. */ | |
4825 | mark_reload_reg_in_use (spill_regs[i], | |
546b63fb | 4826 | reload_opnum[r], |
32131a9c RK |
4827 | reload_when_needed[r], |
4828 | reload_mode[r]); | |
4829 | reload_reg_rtx[r] = reg_last_reload_reg[regno]; | |
4830 | reload_inherited[r] = 1; | |
4831 | reload_inheritance_insn[r] = reg_reloaded_insn[i]; | |
4832 | reload_spill_index[r] = i; | |
be7ae2a4 RK |
4833 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
4834 | spill_regs[i]); | |
32131a9c RK |
4835 | } |
4836 | } | |
4837 | } | |
4838 | } | |
4839 | ||
4840 | /* Here's another way to see if the value is already lying around. */ | |
4841 | if (inheritance | |
4842 | && reload_in[r] != 0 | |
4843 | && ! reload_inherited[r] | |
4844 | && reload_out[r] == 0 | |
4845 | && (CONSTANT_P (reload_in[r]) | |
4846 | || GET_CODE (reload_in[r]) == PLUS | |
4847 | || GET_CODE (reload_in[r]) == REG | |
4848 | || GET_CODE (reload_in[r]) == MEM) | |
4849 | && (reload_nregs[r] == max_group_size | |
4850 | || ! reg_classes_intersect_p (reload_reg_class[r], group_class))) | |
4851 | { | |
4852 | register rtx equiv | |
4853 | = find_equiv_reg (reload_in[r], insn, reload_reg_class[r], | |
fb3821f7 | 4854 | -1, NULL_PTR, 0, reload_mode[r]); |
32131a9c RK |
4855 | int regno; |
4856 | ||
4857 | if (equiv != 0) | |
4858 | { | |
4859 | if (GET_CODE (equiv) == REG) | |
4860 | regno = REGNO (equiv); | |
4861 | else if (GET_CODE (equiv) == SUBREG) | |
4862 | { | |
4863 | regno = REGNO (SUBREG_REG (equiv)); | |
4864 | if (regno < FIRST_PSEUDO_REGISTER) | |
4865 | regno += SUBREG_WORD (equiv); | |
4866 | } | |
4867 | else | |
4868 | abort (); | |
4869 | } | |
4870 | ||
4871 | /* If we found a spill reg, reject it unless it is free | |
4872 | and of the desired class. */ | |
4873 | if (equiv != 0 | |
4874 | && ((spill_reg_order[regno] >= 0 | |
546b63fb | 4875 | && ! reload_reg_free_before_p (regno, reload_opnum[r], |
32131a9c RK |
4876 | reload_when_needed[r])) |
4877 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], | |
4878 | regno))) | |
4879 | equiv = 0; | |
4880 | ||
4881 | if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)) | |
4882 | equiv = 0; | |
4883 | ||
4884 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r])) | |
4885 | equiv = 0; | |
4886 | ||
4887 | /* We found a register that contains the value we need. | |
4888 | If this register is the same as an `earlyclobber' operand | |
4889 | of the current insn, just mark it as a place to reload from | |
4890 | since we can't use it as the reload register itself. */ | |
4891 | ||
4892 | if (equiv != 0) | |
4893 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
4894 | if (reg_overlap_mentioned_for_reload_p (equiv, |
4895 | reload_earlyclobbers[i])) | |
32131a9c RK |
4896 | { |
4897 | reload_override_in[r] = equiv; | |
4898 | equiv = 0; | |
4899 | break; | |
4900 | } | |
4901 | ||
4902 | /* JRV: If the equiv register we have found is explicitly | |
4903 | clobbered in the current insn, mark but don't use, as above. */ | |
4904 | ||
4905 | if (equiv != 0 && regno_clobbered_p (regno, insn)) | |
4906 | { | |
4907 | reload_override_in[r] = equiv; | |
4908 | equiv = 0; | |
4909 | } | |
4910 | ||
4911 | /* If we found an equivalent reg, say no code need be generated | |
4912 | to load it, and use it as our reload reg. */ | |
4913 | if (equiv != 0 && regno != FRAME_POINTER_REGNUM) | |
4914 | { | |
4915 | reload_reg_rtx[r] = equiv; | |
4916 | reload_inherited[r] = 1; | |
4917 | /* If it is a spill reg, | |
4918 | mark the spill reg as in use for this insn. */ | |
4919 | i = spill_reg_order[regno]; | |
4920 | if (i >= 0) | |
be7ae2a4 RK |
4921 | { |
4922 | mark_reload_reg_in_use (regno, reload_opnum[r], | |
4923 | reload_when_needed[r], | |
4924 | reload_mode[r]); | |
4925 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno); | |
4926 | } | |
32131a9c RK |
4927 | } |
4928 | } | |
4929 | ||
4930 | /* If we found a register to use already, or if this is an optional | |
4931 | reload, we are done. */ | |
4932 | if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0) | |
4933 | continue; | |
4934 | ||
4935 | #if 0 /* No longer needed for correct operation. Might or might not | |
4936 | give better code on the average. Want to experiment? */ | |
4937 | ||
4938 | /* See if there is a later reload that has a class different from our | |
4939 | class that intersects our class or that requires less register | |
4940 | than our reload. If so, we must allocate a register to this | |
4941 | reload now, since that reload might inherit a previous reload | |
4942 | and take the only available register in our class. Don't do this | |
4943 | for optional reloads since they will force all previous reloads | |
4944 | to be allocated. Also don't do this for reloads that have been | |
4945 | turned off. */ | |
4946 | ||
4947 | for (i = j + 1; i < n_reloads; i++) | |
4948 | { | |
4949 | int s = reload_order[i]; | |
4950 | ||
d45cf215 RS |
4951 | if ((reload_in[s] == 0 && reload_out[s] == 0 |
4952 | && ! reload_secondary_p[s]) | |
32131a9c RK |
4953 | || reload_optional[s]) |
4954 | continue; | |
4955 | ||
4956 | if ((reload_reg_class[s] != reload_reg_class[r] | |
4957 | && reg_classes_intersect_p (reload_reg_class[r], | |
4958 | reload_reg_class[s])) | |
4959 | || reload_nregs[s] < reload_nregs[r]) | |
4960 | break; | |
4961 | } | |
4962 | ||
4963 | if (i == n_reloads) | |
4964 | continue; | |
4965 | ||
4966 | allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance); | |
4967 | #endif | |
4968 | } | |
4969 | ||
4970 | /* Now allocate reload registers for anything non-optional that | |
4971 | didn't get one yet. */ | |
4972 | for (j = 0; j < n_reloads; j++) | |
4973 | { | |
4974 | register int r = reload_order[j]; | |
4975 | ||
4976 | /* Ignore reloads that got marked inoperative. */ | |
4977 | if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) | |
4978 | continue; | |
4979 | ||
4980 | /* Skip reloads that already have a register allocated or are | |
4981 | optional. */ | |
4982 | if (reload_reg_rtx[r] != 0 || reload_optional[r]) | |
4983 | continue; | |
4984 | ||
4985 | if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance)) | |
4986 | break; | |
4987 | } | |
4988 | ||
4989 | /* If that loop got all the way, we have won. */ | |
4990 | if (j == n_reloads) | |
4991 | break; | |
4992 | ||
4993 | fail: | |
4994 | /* Loop around and try without any inheritance. */ | |
4995 | /* First undo everything done by the failed attempt | |
4996 | to allocate with inheritance. */ | |
4997 | bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx); | |
4998 | bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited); | |
4999 | bcopy (save_reload_inheritance_insn, reload_inheritance_insn, | |
5000 | sizeof reload_inheritance_insn); | |
5001 | bcopy (save_reload_override_in, reload_override_in, | |
5002 | sizeof reload_override_in); | |
5003 | bcopy (save_reload_spill_index, reload_spill_index, | |
5004 | sizeof reload_spill_index); | |
5005 | COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used); | |
5006 | COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all); | |
32131a9c RK |
5007 | COPY_HARD_REG_SET (reload_reg_used_in_op_addr, |
5008 | save_reload_reg_used_in_op_addr); | |
546b63fb RK |
5009 | COPY_HARD_REG_SET (reload_reg_used_in_insn, |
5010 | save_reload_reg_used_in_insn); | |
5011 | COPY_HARD_REG_SET (reload_reg_used_in_other_addr, | |
5012 | save_reload_reg_used_in_other_addr); | |
5013 | ||
5014 | for (i = 0; i < reload_n_operands; i++) | |
5015 | { | |
5016 | COPY_HARD_REG_SET (reload_reg_used_in_input[i], | |
5017 | save_reload_reg_used_in_input[i]); | |
5018 | COPY_HARD_REG_SET (reload_reg_used_in_output[i], | |
5019 | save_reload_reg_used_in_output[i]); | |
5020 | COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i], | |
5021 | save_reload_reg_used_in_input_addr[i]); | |
5022 | COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i], | |
5023 | save_reload_reg_used_in_output_addr[i]); | |
5024 | } | |
32131a9c RK |
5025 | } |
5026 | ||
5027 | /* If we thought we could inherit a reload, because it seemed that | |
5028 | nothing else wanted the same reload register earlier in the insn, | |
5029 | verify that assumption, now that all reloads have been assigned. */ | |
5030 | ||
5031 | for (j = 0; j < n_reloads; j++) | |
5032 | { | |
5033 | register int r = reload_order[j]; | |
5034 | ||
5035 | if (reload_inherited[r] && reload_reg_rtx[r] != 0 | |
5036 | && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]), | |
546b63fb | 5037 | reload_opnum[r], |
32131a9c RK |
5038 | reload_when_needed[r])) |
5039 | reload_inherited[r] = 0; | |
5040 | ||
5041 | /* If we found a better place to reload from, | |
5042 | validate it in the same fashion, if it is a reload reg. */ | |
5043 | if (reload_override_in[r] | |
5044 | && (GET_CODE (reload_override_in[r]) == REG | |
5045 | || GET_CODE (reload_override_in[r]) == SUBREG)) | |
5046 | { | |
5047 | int regno = true_regnum (reload_override_in[r]); | |
5048 | if (spill_reg_order[regno] >= 0 | |
546b63fb RK |
5049 | && ! reload_reg_free_before_p (regno, reload_opnum[r], |
5050 | reload_when_needed[r])) | |
32131a9c RK |
5051 | reload_override_in[r] = 0; |
5052 | } | |
5053 | } | |
5054 | ||
5055 | /* Now that reload_override_in is known valid, | |
5056 | actually override reload_in. */ | |
5057 | for (j = 0; j < n_reloads; j++) | |
5058 | if (reload_override_in[j]) | |
5059 | reload_in[j] = reload_override_in[j]; | |
5060 | ||
5061 | /* If this reload won't be done because it has been cancelled or is | |
5062 | optional and not inherited, clear reload_reg_rtx so other | |
5063 | routines (such as subst_reloads) don't get confused. */ | |
5064 | for (j = 0; j < n_reloads; j++) | |
be7ae2a4 RK |
5065 | if (reload_reg_rtx[j] != 0 |
5066 | && ((reload_optional[j] && ! reload_inherited[j]) | |
5067 | || (reload_in[j] == 0 && reload_out[j] == 0 | |
5068 | && ! reload_secondary_p[j]))) | |
5069 | { | |
5070 | int regno = true_regnum (reload_reg_rtx[j]); | |
5071 | ||
5072 | if (spill_reg_order[regno] >= 0) | |
5073 | clear_reload_reg_in_use (regno, reload_opnum[j], | |
5074 | reload_when_needed[j], reload_mode[j]); | |
5075 | reload_reg_rtx[j] = 0; | |
5076 | } | |
32131a9c RK |
5077 | |
5078 | /* Record which pseudos and which spill regs have output reloads. */ | |
5079 | for (j = 0; j < n_reloads; j++) | |
5080 | { | |
5081 | register int r = reload_order[j]; | |
5082 | ||
5083 | i = reload_spill_index[r]; | |
5084 | ||
5085 | /* I is nonneg if this reload used one of the spill regs. | |
5086 | If reload_reg_rtx[r] is 0, this is an optional reload | |
5087 | that we opted to ignore. */ | |
5088 | if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG | |
5089 | && reload_reg_rtx[r] != 0) | |
5090 | { | |
5091 | register int nregno = REGNO (reload_out[r]); | |
372e033b RS |
5092 | int nr = 1; |
5093 | ||
5094 | if (nregno < FIRST_PSEUDO_REGISTER) | |
5095 | nr = HARD_REGNO_NREGS (nregno, reload_mode[r]); | |
32131a9c RK |
5096 | |
5097 | while (--nr >= 0) | |
372e033b RS |
5098 | reg_has_output_reload[nregno + nr] = 1; |
5099 | ||
5100 | if (i >= 0) | |
32131a9c | 5101 | { |
372e033b RS |
5102 | nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); |
5103 | while (--nr >= 0) | |
32131a9c RK |
5104 | SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr); |
5105 | } | |
5106 | ||
5107 | if (reload_when_needed[r] != RELOAD_OTHER | |
546b63fb RK |
5108 | && reload_when_needed[r] != RELOAD_FOR_OUTPUT |
5109 | && reload_when_needed[r] != RELOAD_FOR_INSN) | |
32131a9c RK |
5110 | abort (); |
5111 | } | |
5112 | } | |
5113 | } | |
5114 | \f | |
546b63fb RK |
5115 | /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two |
5116 | reloads of the same item for fear that we might not have enough reload | |
5117 | registers. However, normally they will get the same reload register | |
5118 | and hence actually need not be loaded twice. | |
5119 | ||
5120 | Here we check for the most common case of this phenomenon: when we have | |
5121 | a number of reloads for the same object, each of which were allocated | |
5122 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
5123 | reload, and is not modified in the insn itself. If we find such, | |
5124 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
5125 | This will not increase the number of spill registers needed and will | |
5126 | prevent redundant code. */ | |
5127 | ||
5128 | #ifdef SMALL_REGISTER_CLASSES | |
5129 | ||
5130 | static void | |
5131 | merge_assigned_reloads (insn) | |
5132 | rtx insn; | |
5133 | { | |
5134 | int i, j; | |
5135 | ||
5136 | /* Scan all the reloads looking for ones that only load values and | |
5137 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
5138 | assigned and not modified by INSN. */ | |
5139 | ||
5140 | for (i = 0; i < n_reloads; i++) | |
5141 | { | |
5142 | if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER | |
5143 | || reload_out[i] != 0 || reload_reg_rtx[i] == 0 | |
5144 | || reg_set_p (reload_reg_rtx[i], insn)) | |
5145 | continue; | |
5146 | ||
5147 | /* Look at all other reloads. Ensure that the only use of this | |
5148 | reload_reg_rtx is in a reload that just loads the same value | |
5149 | as we do. Note that any secondary reloads must be of the identical | |
5150 | class since the values, modes, and result registers are the | |
5151 | same, so we need not do anything with any secondary reloads. */ | |
5152 | ||
5153 | for (j = 0; j < n_reloads; j++) | |
5154 | { | |
5155 | if (i == j || reload_reg_rtx[j] == 0 | |
5156 | || ! reg_overlap_mentioned_p (reload_reg_rtx[j], | |
5157 | reload_reg_rtx[i])) | |
5158 | continue; | |
5159 | ||
5160 | /* If the reload regs aren't exactly the same (e.g, different modes) | |
5161 | or if the values are different, we can't merge anything with this | |
5162 | reload register. */ | |
5163 | ||
5164 | if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]) | |
5165 | || reload_out[j] != 0 || reload_in[j] == 0 | |
5166 | || ! rtx_equal_p (reload_in[i], reload_in[j])) | |
5167 | break; | |
5168 | } | |
5169 | ||
5170 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
5171 | we, in fact, found any matching reloads. */ | |
5172 | ||
5173 | if (j == n_reloads) | |
5174 | { | |
5175 | for (j = 0; j < n_reloads; j++) | |
5176 | if (i != j && reload_reg_rtx[j] != 0 | |
5177 | && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])) | |
5178 | { | |
5179 | reload_when_needed[i] = RELOAD_OTHER; | |
5180 | reload_in[j] = 0; | |
5181 | transfer_replacements (i, j); | |
5182 | } | |
5183 | ||
5184 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
5185 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
5186 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
5187 | this test is equivalent to looking for reloads for this operand | |
5188 | number. */ | |
5189 | ||
5190 | if (reload_when_needed[i] == RELOAD_OTHER) | |
5191 | for (j = 0; j < n_reloads; j++) | |
5192 | if (reload_in[j] != 0 | |
5193 | && reload_when_needed[i] != RELOAD_OTHER | |
5194 | && reg_overlap_mentioned_for_reload_p (reload_in[j], | |
5195 | reload_in[i])) | |
5196 | reload_when_needed[j] | |
5197 | = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
5198 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER; | |
5199 | } | |
5200 | } | |
5201 | } | |
5202 | #endif /* SMALL_RELOAD_CLASSES */ | |
5203 | \f | |
32131a9c RK |
5204 | /* Output insns to reload values in and out of the chosen reload regs. */ |
5205 | ||
5206 | static void | |
5207 | emit_reload_insns (insn) | |
5208 | rtx insn; | |
5209 | { | |
5210 | register int j; | |
546b63fb RK |
5211 | rtx input_reload_insns[MAX_RECOG_OPERANDS]; |
5212 | rtx other_input_address_reload_insns = 0; | |
5213 | rtx other_input_reload_insns = 0; | |
5214 | rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5215 | rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
5216 | rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5217 | rtx operand_reload_insns = 0; | |
32131a9c | 5218 | rtx following_insn = NEXT_INSN (insn); |
a8efe40d | 5219 | rtx before_insn = insn; |
32131a9c RK |
5220 | int special; |
5221 | /* Values to be put in spill_reg_store are put here first. */ | |
5222 | rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
5223 | ||
546b63fb RK |
5224 | for (j = 0; j < reload_n_operands; j++) |
5225 | input_reload_insns[j] = input_address_reload_insns[j] | |
5226 | = output_reload_insns[j] = output_address_reload_insns[j] = 0; | |
5227 | ||
d45cf215 | 5228 | /* If this is a CALL_INSN preceded by USE insns, any reload insns |
a8efe40d RK |
5229 | must go in front of the first USE insn, not in front of INSN. */ |
5230 | ||
5231 | if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN | |
5232 | && GET_CODE (PATTERN (PREV_INSN (insn))) == USE) | |
5233 | while (GET_CODE (PREV_INSN (before_insn)) == INSN | |
5234 | && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE) | |
546b63fb RK |
5235 | before_insn = PREV_INSN (before_insn); |
5236 | ||
a34a369b | 5237 | /* If INSN is followed by any CLOBBER insns made by find_reloads, |
546b63fb RK |
5238 | put our reloads after them since they may otherwise be |
5239 | misinterpreted. */ | |
5240 | ||
a34a369b DE |
5241 | while (GET_CODE (following_insn) == INSN |
5242 | && GET_MODE (following_insn) == DImode | |
5243 | && GET_CODE (PATTERN (following_insn)) == CLOBBER | |
5244 | && NEXT_INSN (following_insn) != 0) | |
546b63fb | 5245 | following_insn = NEXT_INSN (following_insn); |
a8efe40d | 5246 | |
32131a9c RK |
5247 | /* Now output the instructions to copy the data into and out of the |
5248 | reload registers. Do these in the order that the reloads were reported, | |
5249 | since reloads of base and index registers precede reloads of operands | |
5250 | and the operands may need the base and index registers reloaded. */ | |
5251 | ||
5252 | for (j = 0; j < n_reloads; j++) | |
5253 | { | |
5254 | register rtx old; | |
5255 | rtx oldequiv_reg = 0; | |
32131a9c RK |
5256 | rtx store_insn = 0; |
5257 | ||
5258 | old = reload_in[j]; | |
5259 | if (old != 0 && ! reload_inherited[j] | |
5260 | && ! rtx_equal_p (reload_reg_rtx[j], old) | |
5261 | && reload_reg_rtx[j] != 0) | |
5262 | { | |
5263 | register rtx reloadreg = reload_reg_rtx[j]; | |
5264 | rtx oldequiv = 0; | |
5265 | enum machine_mode mode; | |
546b63fb | 5266 | rtx *where; |
32131a9c RK |
5267 | |
5268 | /* Determine the mode to reload in. | |
5269 | This is very tricky because we have three to choose from. | |
5270 | There is the mode the insn operand wants (reload_inmode[J]). | |
5271 | There is the mode of the reload register RELOADREG. | |
5272 | There is the intrinsic mode of the operand, which we could find | |
5273 | by stripping some SUBREGs. | |
5274 | It turns out that RELOADREG's mode is irrelevant: | |
5275 | we can change that arbitrarily. | |
5276 | ||
5277 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
5278 | then the reload reg may not support QImode moves, so use SImode. | |
5279 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
5280 | because the QImode value is in the least significant part of a | |
5281 | slot big enough for a SImode. If foo is some other sort of | |
5282 | memory reference, then it is impossible to reload this case, | |
5283 | so previous passes had better make sure this never happens. | |
5284 | ||
5285 | Then consider a one-word union which has SImode and one of its | |
5286 | members is a float, being fetched as (SUBREG:SF union:SI). | |
5287 | We must fetch that as SFmode because we could be loading into | |
5288 | a float-only register. In this case OLD's mode is correct. | |
5289 | ||
5290 | Consider an immediate integer: it has VOIDmode. Here we need | |
5291 | to get a mode from something else. | |
5292 | ||
5293 | In some cases, there is a fourth mode, the operand's | |
5294 | containing mode. If the insn specifies a containing mode for | |
5295 | this operand, it overrides all others. | |
5296 | ||
5297 | I am not sure whether the algorithm here is always right, | |
5298 | but it does the right things in those cases. */ | |
5299 | ||
5300 | mode = GET_MODE (old); | |
5301 | if (mode == VOIDmode) | |
5302 | mode = reload_inmode[j]; | |
32131a9c RK |
5303 | |
5304 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5305 | /* If we need a secondary register for this operation, see if | |
5306 | the value is already in a register in that class. Don't | |
5307 | do this if the secondary register will be used as a scratch | |
5308 | register. */ | |
5309 | ||
5310 | if (reload_secondary_reload[j] >= 0 | |
58b1581b RS |
5311 | && reload_secondary_icode[j] == CODE_FOR_nothing |
5312 | && optimize) | |
32131a9c RK |
5313 | oldequiv |
5314 | = find_equiv_reg (old, insn, | |
5315 | reload_reg_class[reload_secondary_reload[j]], | |
fb3821f7 | 5316 | -1, NULL_PTR, 0, mode); |
32131a9c RK |
5317 | #endif |
5318 | ||
5319 | /* If reloading from memory, see if there is a register | |
5320 | that already holds the same value. If so, reload from there. | |
5321 | We can pass 0 as the reload_reg_p argument because | |
5322 | any other reload has either already been emitted, | |
5323 | in which case find_equiv_reg will see the reload-insn, | |
5324 | or has yet to be emitted, in which case it doesn't matter | |
5325 | because we will use this equiv reg right away. */ | |
5326 | ||
58b1581b | 5327 | if (oldequiv == 0 && optimize |
32131a9c RK |
5328 | && (GET_CODE (old) == MEM |
5329 | || (GET_CODE (old) == REG | |
5330 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
5331 | && reg_renumber[REGNO (old)] < 0))) | |
546b63fb | 5332 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, |
fb3821f7 | 5333 | -1, NULL_PTR, 0, mode); |
32131a9c RK |
5334 | |
5335 | if (oldequiv) | |
5336 | { | |
5337 | int regno = true_regnum (oldequiv); | |
5338 | ||
5339 | /* If OLDEQUIV is a spill register, don't use it for this | |
5340 | if any other reload needs it at an earlier stage of this insn | |
a8fdc208 | 5341 | or at this stage. */ |
32131a9c | 5342 | if (spill_reg_order[regno] >= 0 |
546b63fb RK |
5343 | && (! reload_reg_free_p (regno, reload_opnum[j], |
5344 | reload_when_needed[j]) | |
5345 | || ! reload_reg_free_before_p (regno, reload_opnum[j], | |
32131a9c RK |
5346 | reload_when_needed[j]))) |
5347 | oldequiv = 0; | |
5348 | ||
5349 | /* If OLDEQUIV is not a spill register, | |
5350 | don't use it if any other reload wants it. */ | |
5351 | if (spill_reg_order[regno] < 0) | |
5352 | { | |
5353 | int k; | |
5354 | for (k = 0; k < n_reloads; k++) | |
5355 | if (reload_reg_rtx[k] != 0 && k != j | |
bfa30b22 RK |
5356 | && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k], |
5357 | oldequiv)) | |
32131a9c RK |
5358 | { |
5359 | oldequiv = 0; | |
5360 | break; | |
5361 | } | |
5362 | } | |
546b63fb RK |
5363 | |
5364 | /* If it is no cheaper to copy from OLDEQUIV into the | |
5365 | reload register than it would be to move from memory, | |
5366 | don't use it. Likewise, if we need a secondary register | |
5367 | or memory. */ | |
5368 | ||
5369 | if (oldequiv != 0 | |
5370 | && ((REGNO_REG_CLASS (regno) != reload_reg_class[j] | |
5371 | && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno), | |
5372 | reload_reg_class[j]) | |
5373 | >= MEMORY_MOVE_COST (mode))) | |
5374 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5375 | || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], | |
5376 | mode, oldequiv) | |
5377 | != NO_REGS) | |
5378 | #endif | |
5379 | #ifdef SECONDARY_MEMORY_NEEDED | |
5380 | || SECONDARY_MEMORY_NEEDED (reload_reg_class[j], | |
5381 | REGNO_REG_CLASS (regno), | |
5382 | mode) | |
5383 | #endif | |
5384 | )) | |
5385 | oldequiv = 0; | |
32131a9c RK |
5386 | } |
5387 | ||
5388 | if (oldequiv == 0) | |
5389 | oldequiv = old; | |
5390 | else if (GET_CODE (oldequiv) == REG) | |
5391 | oldequiv_reg = oldequiv; | |
5392 | else if (GET_CODE (oldequiv) == SUBREG) | |
5393 | oldequiv_reg = SUBREG_REG (oldequiv); | |
5394 | ||
5395 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
5396 | then load RELOADREG from OLDEQUIV. */ | |
5397 | ||
5398 | if (GET_MODE (reloadreg) != mode) | |
b6983ae3 | 5399 | reloadreg = gen_lowpart_common (mode, reloadreg); |
32131a9c RK |
5400 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) |
5401 | oldequiv = SUBREG_REG (oldequiv); | |
5402 | if (GET_MODE (oldequiv) != VOIDmode | |
5403 | && mode != GET_MODE (oldequiv)) | |
5404 | oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0); | |
5405 | ||
546b63fb | 5406 | /* Switch to the right place to emit the reload insns. */ |
32131a9c RK |
5407 | switch (reload_when_needed[j]) |
5408 | { | |
32131a9c | 5409 | case RELOAD_OTHER: |
546b63fb RK |
5410 | where = &other_input_reload_insns; |
5411 | break; | |
5412 | case RELOAD_FOR_INPUT: | |
5413 | where = &input_reload_insns[reload_opnum[j]]; | |
32131a9c | 5414 | break; |
546b63fb RK |
5415 | case RELOAD_FOR_INPUT_ADDRESS: |
5416 | where = &input_address_reload_insns[reload_opnum[j]]; | |
32131a9c | 5417 | break; |
546b63fb RK |
5418 | case RELOAD_FOR_OUTPUT_ADDRESS: |
5419 | where = &output_address_reload_insns[reload_opnum[j]]; | |
32131a9c RK |
5420 | break; |
5421 | case RELOAD_FOR_OPERAND_ADDRESS: | |
546b63fb RK |
5422 | where = &operand_reload_insns; |
5423 | break; | |
5424 | case RELOAD_FOR_OTHER_ADDRESS: | |
5425 | where = &other_input_address_reload_insns; | |
5426 | break; | |
5427 | default: | |
5428 | abort (); | |
32131a9c RK |
5429 | } |
5430 | ||
546b63fb | 5431 | push_to_sequence (*where); |
32131a9c RK |
5432 | special = 0; |
5433 | ||
5434 | /* Auto-increment addresses must be reloaded in a special way. */ | |
5435 | if (GET_CODE (oldequiv) == POST_INC | |
5436 | || GET_CODE (oldequiv) == POST_DEC | |
5437 | || GET_CODE (oldequiv) == PRE_INC | |
5438 | || GET_CODE (oldequiv) == PRE_DEC) | |
5439 | { | |
5440 | /* We are not going to bother supporting the case where a | |
5441 | incremented register can't be copied directly from | |
5442 | OLDEQUIV since this seems highly unlikely. */ | |
5443 | if (reload_secondary_reload[j] >= 0) | |
5444 | abort (); | |
5445 | /* Prevent normal processing of this reload. */ | |
5446 | special = 1; | |
5447 | /* Output a special code sequence for this case. */ | |
546b63fb | 5448 | inc_for_reload (reloadreg, oldequiv, reload_inc[j]); |
32131a9c RK |
5449 | } |
5450 | ||
5451 | /* If we are reloading a pseudo-register that was set by the previous | |
5452 | insn, see if we can get rid of that pseudo-register entirely | |
5453 | by redirecting the previous insn into our reload register. */ | |
5454 | ||
5455 | else if (optimize && GET_CODE (old) == REG | |
5456 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
5457 | && dead_or_set_p (insn, old) | |
5458 | /* This is unsafe if some other reload | |
5459 | uses the same reg first. */ | |
546b63fb RK |
5460 | && reload_reg_free_before_p (REGNO (reloadreg), |
5461 | reload_opnum[j], | |
5462 | reload_when_needed[j])) | |
32131a9c RK |
5463 | { |
5464 | rtx temp = PREV_INSN (insn); | |
5465 | while (temp && GET_CODE (temp) == NOTE) | |
5466 | temp = PREV_INSN (temp); | |
5467 | if (temp | |
5468 | && GET_CODE (temp) == INSN | |
5469 | && GET_CODE (PATTERN (temp)) == SET | |
5470 | && SET_DEST (PATTERN (temp)) == old | |
5471 | /* Make sure we can access insn_operand_constraint. */ | |
5472 | && asm_noperands (PATTERN (temp)) < 0 | |
5473 | /* This is unsafe if prev insn rejects our reload reg. */ | |
5474 | && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0], | |
5475 | reloadreg) | |
5476 | /* This is unsafe if operand occurs more than once in current | |
5477 | insn. Perhaps some occurrences aren't reloaded. */ | |
5478 | && count_occurrences (PATTERN (insn), old) == 1 | |
5479 | /* Don't risk splitting a matching pair of operands. */ | |
5480 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
5481 | { | |
5482 | /* Store into the reload register instead of the pseudo. */ | |
5483 | SET_DEST (PATTERN (temp)) = reloadreg; | |
5484 | /* If these are the only uses of the pseudo reg, | |
5485 | pretend for GDB it lives in the reload reg we used. */ | |
5486 | if (reg_n_deaths[REGNO (old)] == 1 | |
5487 | && reg_n_sets[REGNO (old)] == 1) | |
5488 | { | |
5489 | reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]); | |
5490 | alter_reg (REGNO (old), -1); | |
5491 | } | |
5492 | special = 1; | |
5493 | } | |
5494 | } | |
5495 | ||
546b63fb RK |
5496 | /* We can't do that, so output an insn to load RELOADREG. */ |
5497 | ||
32131a9c RK |
5498 | if (! special) |
5499 | { | |
5500 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5501 | rtx second_reload_reg = 0; | |
5502 | enum insn_code icode; | |
5503 | ||
5504 | /* If we have a secondary reload, pick up the secondary register | |
d445b551 RK |
5505 | and icode, if any. If OLDEQUIV and OLD are different or |
5506 | if this is an in-out reload, recompute whether or not we | |
5507 | still need a secondary register and what the icode should | |
5508 | be. If we still need a secondary register and the class or | |
5509 | icode is different, go back to reloading from OLD if using | |
5510 | OLDEQUIV means that we got the wrong type of register. We | |
5511 | cannot have different class or icode due to an in-out reload | |
5512 | because we don't make such reloads when both the input and | |
5513 | output need secondary reload registers. */ | |
32131a9c RK |
5514 | |
5515 | if (reload_secondary_reload[j] >= 0) | |
5516 | { | |
5517 | int secondary_reload = reload_secondary_reload[j]; | |
1554c2c6 RK |
5518 | rtx real_oldequiv = oldequiv; |
5519 | rtx real_old = old; | |
5520 | ||
5521 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
5522 | and similarly for OLD. | |
5523 | See comments in find_secondary_reload in reload.c. */ | |
5524 | if (GET_CODE (oldequiv) == REG | |
5525 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
5526 | && reg_equiv_mem[REGNO (oldequiv)] != 0) | |
5527 | real_oldequiv = reg_equiv_mem[REGNO (oldequiv)]; | |
5528 | ||
5529 | if (GET_CODE (old) == REG | |
5530 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
5531 | && reg_equiv_mem[REGNO (old)] != 0) | |
5532 | real_old = reg_equiv_mem[REGNO (old)]; | |
5533 | ||
32131a9c RK |
5534 | second_reload_reg = reload_reg_rtx[secondary_reload]; |
5535 | icode = reload_secondary_icode[j]; | |
5536 | ||
d445b551 RK |
5537 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) |
5538 | || (reload_in[j] != 0 && reload_out[j] != 0)) | |
32131a9c RK |
5539 | { |
5540 | enum reg_class new_class | |
5541 | = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], | |
1554c2c6 | 5542 | mode, real_oldequiv); |
32131a9c RK |
5543 | |
5544 | if (new_class == NO_REGS) | |
5545 | second_reload_reg = 0; | |
5546 | else | |
5547 | { | |
5548 | enum insn_code new_icode; | |
5549 | enum machine_mode new_mode; | |
5550 | ||
5551 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
5552 | REGNO (second_reload_reg))) | |
1554c2c6 | 5553 | oldequiv = old, real_oldequiv = real_old; |
32131a9c RK |
5554 | else |
5555 | { | |
5556 | new_icode = reload_in_optab[(int) mode]; | |
5557 | if (new_icode != CODE_FOR_nothing | |
5558 | && ((insn_operand_predicate[(int) new_icode][0] | |
a8fdc208 | 5559 | && ! ((*insn_operand_predicate[(int) new_icode][0]) |
32131a9c | 5560 | (reloadreg, mode))) |
a8fdc208 RS |
5561 | || (insn_operand_predicate[(int) new_icode][1] |
5562 | && ! ((*insn_operand_predicate[(int) new_icode][1]) | |
1554c2c6 | 5563 | (real_oldequiv, mode))))) |
32131a9c RK |
5564 | new_icode = CODE_FOR_nothing; |
5565 | ||
5566 | if (new_icode == CODE_FOR_nothing) | |
5567 | new_mode = mode; | |
5568 | else | |
196ddf8a | 5569 | new_mode = insn_operand_mode[(int) new_icode][2]; |
32131a9c RK |
5570 | |
5571 | if (GET_MODE (second_reload_reg) != new_mode) | |
5572 | { | |
5573 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), | |
5574 | new_mode)) | |
1554c2c6 | 5575 | oldequiv = old, real_oldequiv = real_old; |
32131a9c RK |
5576 | else |
5577 | second_reload_reg | |
3aaa90c7 MM |
5578 | = gen_rtx (REG, new_mode, |
5579 | REGNO (second_reload_reg)); | |
32131a9c RK |
5580 | } |
5581 | } | |
5582 | } | |
5583 | } | |
5584 | ||
5585 | /* If we still need a secondary reload register, check | |
5586 | to see if it is being used as a scratch or intermediate | |
1554c2c6 RK |
5587 | register and generate code appropriately. If we need |
5588 | a scratch register, use REAL_OLDEQUIV since the form of | |
5589 | the insn may depend on the actual address if it is | |
5590 | a MEM. */ | |
32131a9c RK |
5591 | |
5592 | if (second_reload_reg) | |
5593 | { | |
5594 | if (icode != CODE_FOR_nothing) | |
5595 | { | |
546b63fb RK |
5596 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
5597 | second_reload_reg)); | |
32131a9c RK |
5598 | special = 1; |
5599 | } | |
5600 | else | |
5601 | { | |
5602 | /* See if we need a scratch register to load the | |
5603 | intermediate register (a tertiary reload). */ | |
5604 | enum insn_code tertiary_icode | |
5605 | = reload_secondary_icode[secondary_reload]; | |
5606 | ||
5607 | if (tertiary_icode != CODE_FOR_nothing) | |
5608 | { | |
5609 | rtx third_reload_reg | |
5610 | = reload_reg_rtx[reload_secondary_reload[secondary_reload]]; | |
5611 | ||
546b63fb RK |
5612 | emit_insn ((GEN_FCN (tertiary_icode) |
5613 | (second_reload_reg, real_oldequiv, | |
5614 | third_reload_reg))); | |
32131a9c RK |
5615 | } |
5616 | else | |
546b63fb RK |
5617 | gen_input_reload (second_reload_reg, oldequiv, |
5618 | reload_opnum[j], | |
5619 | reload_when_needed[j]); | |
5620 | ||
5621 | oldequiv = second_reload_reg; | |
32131a9c RK |
5622 | } |
5623 | } | |
5624 | } | |
5625 | #endif | |
5626 | ||
5627 | if (! special) | |
546b63fb RK |
5628 | gen_input_reload (reloadreg, oldequiv, reload_opnum[j], |
5629 | reload_when_needed[j]); | |
32131a9c RK |
5630 | |
5631 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P) | |
5632 | /* We may have to make a REG_DEAD note for the secondary reload | |
5633 | register in the insns we just made. Find the last insn that | |
5634 | mentioned the register. */ | |
5635 | if (! special && second_reload_reg | |
5636 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg))) | |
5637 | { | |
5638 | rtx prev; | |
5639 | ||
546b63fb | 5640 | for (prev = get_last_insn (); prev; |
32131a9c RK |
5641 | prev = PREV_INSN (prev)) |
5642 | if (GET_RTX_CLASS (GET_CODE (prev) == 'i') | |
bfa30b22 RK |
5643 | && reg_overlap_mentioned_for_reload_p (second_reload_reg, |
5644 | PATTERN (prev))) | |
32131a9c RK |
5645 | { |
5646 | REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD, | |
5647 | second_reload_reg, | |
5648 | REG_NOTES (prev)); | |
5649 | break; | |
5650 | } | |
5651 | } | |
5652 | #endif | |
5653 | } | |
5654 | ||
546b63fb RK |
5655 | /* End this sequence. */ |
5656 | *where = get_insns (); | |
5657 | end_sequence (); | |
32131a9c RK |
5658 | } |
5659 | ||
5660 | /* Add a note saying the input reload reg | |
5661 | dies in this insn, if anyone cares. */ | |
5662 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
5663 | if (old != 0 | |
5664 | && reload_reg_rtx[j] != old | |
5665 | && reload_reg_rtx[j] != 0 | |
5666 | && reload_out[j] == 0 | |
5667 | && ! reload_inherited[j] | |
5668 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))) | |
5669 | { | |
5670 | register rtx reloadreg = reload_reg_rtx[j]; | |
5671 | ||
a8fdc208 | 5672 | #if 0 |
32131a9c RK |
5673 | /* We can't abort here because we need to support this for sched.c. |
5674 | It's not terrible to miss a REG_DEAD note, but we should try | |
5675 | to figure out how to do this correctly. */ | |
5676 | /* The code below is incorrect for address-only reloads. */ | |
5677 | if (reload_when_needed[j] != RELOAD_OTHER | |
5678 | && reload_when_needed[j] != RELOAD_FOR_INPUT) | |
5679 | abort (); | |
5680 | #endif | |
5681 | ||
5682 | /* Add a death note to this insn, for an input reload. */ | |
5683 | ||
5684 | if ((reload_when_needed[j] == RELOAD_OTHER | |
5685 | || reload_when_needed[j] == RELOAD_FOR_INPUT) | |
5686 | && ! dead_or_set_p (insn, reloadreg)) | |
5687 | REG_NOTES (insn) | |
5688 | = gen_rtx (EXPR_LIST, REG_DEAD, | |
5689 | reloadreg, REG_NOTES (insn)); | |
5690 | } | |
5691 | ||
5692 | /* When we inherit a reload, the last marked death of the reload reg | |
5693 | may no longer really be a death. */ | |
5694 | if (reload_reg_rtx[j] != 0 | |
5695 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])) | |
5696 | && reload_inherited[j]) | |
5697 | { | |
5698 | /* Handle inheriting an output reload. | |
5699 | Remove the death note from the output reload insn. */ | |
5700 | if (reload_spill_index[j] >= 0 | |
5701 | && GET_CODE (reload_in[j]) == REG | |
5702 | && spill_reg_store[reload_spill_index[j]] != 0 | |
5703 | && find_regno_note (spill_reg_store[reload_spill_index[j]], | |
5704 | REG_DEAD, REGNO (reload_reg_rtx[j]))) | |
5705 | remove_death (REGNO (reload_reg_rtx[j]), | |
5706 | spill_reg_store[reload_spill_index[j]]); | |
5707 | /* Likewise for input reloads that were inherited. */ | |
5708 | else if (reload_spill_index[j] >= 0 | |
5709 | && GET_CODE (reload_in[j]) == REG | |
5710 | && spill_reg_store[reload_spill_index[j]] == 0 | |
5711 | && reload_inheritance_insn[j] != 0 | |
a8fdc208 | 5712 | && find_regno_note (reload_inheritance_insn[j], REG_DEAD, |
32131a9c RK |
5713 | REGNO (reload_reg_rtx[j]))) |
5714 | remove_death (REGNO (reload_reg_rtx[j]), | |
5715 | reload_inheritance_insn[j]); | |
5716 | else | |
5717 | { | |
5718 | rtx prev; | |
5719 | ||
5720 | /* We got this register from find_equiv_reg. | |
5721 | Search back for its last death note and get rid of it. | |
5722 | But don't search back too far. | |
5723 | Don't go past a place where this reg is set, | |
5724 | since a death note before that remains valid. */ | |
5725 | for (prev = PREV_INSN (insn); | |
5726 | prev && GET_CODE (prev) != CODE_LABEL; | |
5727 | prev = PREV_INSN (prev)) | |
5728 | if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' | |
5729 | && dead_or_set_p (prev, reload_reg_rtx[j])) | |
5730 | { | |
5731 | if (find_regno_note (prev, REG_DEAD, | |
5732 | REGNO (reload_reg_rtx[j]))) | |
5733 | remove_death (REGNO (reload_reg_rtx[j]), prev); | |
5734 | break; | |
5735 | } | |
5736 | } | |
5737 | } | |
5738 | ||
5739 | /* We might have used find_equiv_reg above to choose an alternate | |
5740 | place from which to reload. If so, and it died, we need to remove | |
5741 | that death and move it to one of the insns we just made. */ | |
5742 | ||
5743 | if (oldequiv_reg != 0 | |
5744 | && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg))) | |
5745 | { | |
5746 | rtx prev, prev1; | |
5747 | ||
5748 | for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL; | |
5749 | prev = PREV_INSN (prev)) | |
5750 | if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' | |
5751 | && dead_or_set_p (prev, oldequiv_reg)) | |
5752 | { | |
5753 | if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg))) | |
5754 | { | |
5755 | for (prev1 = this_reload_insn; | |
5756 | prev1; prev1 = PREV_INSN (prev1)) | |
5757 | if (GET_RTX_CLASS (GET_CODE (prev1) == 'i') | |
bfa30b22 RK |
5758 | && reg_overlap_mentioned_for_reload_p (oldequiv_reg, |
5759 | PATTERN (prev1))) | |
32131a9c RK |
5760 | { |
5761 | REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD, | |
5762 | oldequiv_reg, | |
5763 | REG_NOTES (prev1)); | |
5764 | break; | |
5765 | } | |
5766 | remove_death (REGNO (oldequiv_reg), prev); | |
5767 | } | |
5768 | break; | |
5769 | } | |
5770 | } | |
5771 | #endif | |
5772 | ||
5773 | /* If we are reloading a register that was recently stored in with an | |
5774 | output-reload, see if we can prove there was | |
5775 | actually no need to store the old value in it. */ | |
5776 | ||
5777 | if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0 | |
546b63fb | 5778 | && reload_in[j] != 0 |
32131a9c RK |
5779 | && GET_CODE (reload_in[j]) == REG |
5780 | #if 0 | |
5781 | /* There doesn't seem to be any reason to restrict this to pseudos | |
5782 | and doing so loses in the case where we are copying from a | |
5783 | register of the wrong class. */ | |
5784 | && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER | |
5785 | #endif | |
5786 | && spill_reg_store[reload_spill_index[j]] != 0 | |
546b63fb RK |
5787 | /* This is unsafe if some other reload uses the same reg first. */ |
5788 | && reload_reg_free_before_p (spill_regs[reload_spill_index[j]], | |
5789 | reload_opnum[j], reload_when_needed[j]) | |
32131a9c RK |
5790 | && dead_or_set_p (insn, reload_in[j]) |
5791 | /* This is unsafe if operand occurs more than once in current | |
5792 | insn. Perhaps some occurrences weren't reloaded. */ | |
5793 | && count_occurrences (PATTERN (insn), reload_in[j]) == 1) | |
5794 | delete_output_reload (insn, j, | |
5795 | spill_reg_store[reload_spill_index[j]]); | |
5796 | ||
5797 | /* Input-reloading is done. Now do output-reloading, | |
5798 | storing the value from the reload-register after the main insn | |
5799 | if reload_out[j] is nonzero. | |
5800 | ||
5801 | ??? At some point we need to support handling output reloads of | |
5802 | JUMP_INSNs or insns that set cc0. */ | |
5803 | old = reload_out[j]; | |
5804 | if (old != 0 | |
5805 | && reload_reg_rtx[j] != old | |
5806 | && reload_reg_rtx[j] != 0) | |
5807 | { | |
5808 | register rtx reloadreg = reload_reg_rtx[j]; | |
5809 | register rtx second_reloadreg = 0; | |
32131a9c RK |
5810 | rtx note, p; |
5811 | enum machine_mode mode; | |
5812 | int special = 0; | |
5813 | ||
5814 | /* An output operand that dies right away does need a reload, | |
5815 | but need not be copied from it. Show the new location in the | |
5816 | REG_UNUSED note. */ | |
5817 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
5818 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
5819 | { | |
5820 | XEXP (note, 0) = reload_reg_rtx[j]; | |
5821 | continue; | |
5822 | } | |
5823 | else if (GET_CODE (old) == SCRATCH) | |
5824 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
5825 | but we don't want to make an output reload. */ | |
5826 | continue; | |
5827 | ||
5828 | #if 0 | |
5829 | /* Strip off of OLD any size-increasing SUBREGs such as | |
5830 | (SUBREG:SI foo:QI 0). */ | |
5831 | ||
5832 | while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0 | |
5833 | && (GET_MODE_SIZE (GET_MODE (old)) | |
5834 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old))))) | |
5835 | old = SUBREG_REG (old); | |
5836 | #endif | |
5837 | ||
5838 | /* If is a JUMP_INSN, we can't support output reloads yet. */ | |
5839 | if (GET_CODE (insn) == JUMP_INSN) | |
5840 | abort (); | |
5841 | ||
546b63fb RK |
5842 | push_to_sequence (output_reload_insns[reload_opnum[j]]); |
5843 | ||
32131a9c RK |
5844 | /* Determine the mode to reload in. |
5845 | See comments above (for input reloading). */ | |
5846 | ||
5847 | mode = GET_MODE (old); | |
5848 | if (mode == VOIDmode) | |
79a365a7 RS |
5849 | { |
5850 | /* VOIDmode should never happen for an output. */ | |
5851 | if (asm_noperands (PATTERN (insn)) < 0) | |
5852 | /* It's the compiler's fault. */ | |
5853 | abort (); | |
5854 | error_for_asm (insn, "output operand is constant in `asm'"); | |
5855 | /* Prevent crash--use something we know is valid. */ | |
5856 | mode = word_mode; | |
5857 | old = gen_rtx (REG, mode, REGNO (reloadreg)); | |
5858 | } | |
32131a9c | 5859 | |
32131a9c | 5860 | if (GET_MODE (reloadreg) != mode) |
b6983ae3 | 5861 | reloadreg = gen_lowpart_common (mode, reloadreg); |
32131a9c RK |
5862 | |
5863 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
5864 | ||
5865 | /* If we need two reload regs, set RELOADREG to the intermediate | |
5866 | one, since it will be stored into OUT. We might need a secondary | |
5867 | register only for an input reload, so check again here. */ | |
5868 | ||
1554c2c6 | 5869 | if (reload_secondary_reload[j] >= 0) |
32131a9c | 5870 | { |
1554c2c6 | 5871 | rtx real_old = old; |
32131a9c | 5872 | |
1554c2c6 RK |
5873 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
5874 | && reg_equiv_mem[REGNO (old)] != 0) | |
5875 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 5876 | |
1554c2c6 RK |
5877 | if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j], |
5878 | mode, real_old) | |
5879 | != NO_REGS)) | |
5880 | { | |
5881 | second_reloadreg = reloadreg; | |
5882 | reloadreg = reload_reg_rtx[reload_secondary_reload[j]]; | |
32131a9c | 5883 | |
1554c2c6 RK |
5884 | /* See if RELOADREG is to be used as a scratch register |
5885 | or as an intermediate register. */ | |
5886 | if (reload_secondary_icode[j] != CODE_FOR_nothing) | |
32131a9c | 5887 | { |
546b63fb RK |
5888 | emit_insn ((GEN_FCN (reload_secondary_icode[j]) |
5889 | (real_old, second_reloadreg, reloadreg))); | |
1554c2c6 | 5890 | special = 1; |
32131a9c RK |
5891 | } |
5892 | else | |
1554c2c6 RK |
5893 | { |
5894 | /* See if we need both a scratch and intermediate reload | |
5895 | register. */ | |
5896 | int secondary_reload = reload_secondary_reload[j]; | |
5897 | enum insn_code tertiary_icode | |
5898 | = reload_secondary_icode[secondary_reload]; | |
5899 | rtx pat; | |
32131a9c | 5900 | |
1554c2c6 RK |
5901 | if (GET_MODE (reloadreg) != mode) |
5902 | reloadreg = gen_rtx (REG, mode, REGNO (reloadreg)); | |
5903 | ||
5904 | if (tertiary_icode != CODE_FOR_nothing) | |
5905 | { | |
5906 | rtx third_reloadreg | |
5907 | = reload_reg_rtx[reload_secondary_reload[secondary_reload]]; | |
5908 | pat = (GEN_FCN (tertiary_icode) | |
5909 | (reloadreg, second_reloadreg, third_reloadreg)); | |
5910 | } | |
9ad5f9f6 JW |
5911 | #ifdef SECONDARY_MEMORY_NEEDED |
5912 | /* If we need a memory location to do the move, do it that way. */ | |
5913 | else if (GET_CODE (reloadreg) == REG | |
5914 | && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER | |
5915 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)), | |
5916 | REGNO_REG_CLASS (REGNO (second_reloadreg)), | |
5917 | GET_MODE (second_reloadreg))) | |
5918 | { | |
5919 | /* Get the memory to use and rewrite both registers | |
5920 | to its mode. */ | |
546b63fb RK |
5921 | rtx loc |
5922 | = get_secondary_mem (reloadreg, | |
5923 | GET_MODE (second_reloadreg), | |
5924 | reload_opnum[j], | |
5925 | reload_when_needed[j]); | |
9ad5f9f6 JW |
5926 | rtx tmp_reloadreg; |
5927 | ||
5928 | if (GET_MODE (loc) != GET_MODE (second_reloadreg)) | |
5929 | second_reloadreg = gen_rtx (REG, GET_MODE (loc), | |
5930 | REGNO (second_reloadreg)); | |
5931 | ||
5932 | if (GET_MODE (loc) != GET_MODE (reloadreg)) | |
5933 | tmp_reloadreg = gen_rtx (REG, GET_MODE (loc), | |
5934 | REGNO (reloadreg)); | |
5935 | else | |
5936 | tmp_reloadreg = reloadreg; | |
5937 | ||
546b63fb | 5938 | emit_move_insn (loc, second_reloadreg); |
9ad5f9f6 JW |
5939 | pat = gen_move_insn (tmp_reloadreg, loc); |
5940 | } | |
5941 | #endif | |
1554c2c6 RK |
5942 | else |
5943 | pat = gen_move_insn (reloadreg, second_reloadreg); | |
5944 | ||
546b63fb | 5945 | emit_insn (pat); |
1554c2c6 | 5946 | } |
32131a9c RK |
5947 | } |
5948 | } | |
5949 | #endif | |
5950 | ||
5951 | /* Output the last reload insn. */ | |
5952 | if (! special) | |
0dadecf6 RK |
5953 | { |
5954 | #ifdef SECONDARY_MEMORY_NEEDED | |
5955 | /* If we need a memory location to do the move, do it that way. */ | |
5956 | if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER | |
5957 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)), | |
5958 | REGNO_REG_CLASS (REGNO (reloadreg)), | |
5959 | GET_MODE (reloadreg))) | |
5960 | { | |
5961 | /* Get the memory to use and rewrite both registers to | |
5962 | its mode. */ | |
546b63fb RK |
5963 | rtx loc = get_secondary_mem (old, GET_MODE (reloadreg), |
5964 | reload_opnum[j], | |
5965 | reload_when_needed[j]); | |
0dadecf6 RK |
5966 | |
5967 | if (GET_MODE (loc) != GET_MODE (reloadreg)) | |
5968 | reloadreg = gen_rtx (REG, GET_MODE (loc), | |
5969 | REGNO (reloadreg)); | |
5970 | ||
5971 | if (GET_MODE (loc) != GET_MODE (old)) | |
5972 | old = gen_rtx (REG, GET_MODE (loc), REGNO (old)); | |
5973 | ||
546b63fb RK |
5974 | emit_insn (gen_move_insn (loc, reloadreg)); |
5975 | emit_insn (gen_move_insn (old, loc)); | |
0dadecf6 RK |
5976 | } |
5977 | else | |
5978 | #endif | |
546b63fb | 5979 | emit_insn (gen_move_insn (old, reloadreg)); |
0dadecf6 | 5980 | } |
32131a9c RK |
5981 | |
5982 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
5983 | /* If final will look at death notes for this reg, | |
5984 | put one on the last output-reload insn to use it. Similarly | |
5985 | for any secondary register. */ | |
5986 | if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg))) | |
546b63fb | 5987 | for (p = get_last_insn (); p; p = PREV_INSN (p)) |
32131a9c | 5988 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i' |
bfa30b22 RK |
5989 | && reg_overlap_mentioned_for_reload_p (reloadreg, |
5990 | PATTERN (p))) | |
32131a9c RK |
5991 | REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD, |
5992 | reloadreg, REG_NOTES (p)); | |
5993 | ||
5994 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
5995 | if (! special | |
5996 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg))) | |
546b63fb | 5997 | for (p = get_last_insn (); p; p = PREV_INSN (p)) |
32131a9c | 5998 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i' |
bfa30b22 RK |
5999 | && reg_overlap_mentioned_for_reload_p (second_reloadreg, |
6000 | PATTERN (p))) | |
32131a9c RK |
6001 | REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD, |
6002 | second_reloadreg, REG_NOTES (p)); | |
6003 | #endif | |
6004 | #endif | |
6005 | /* Look at all insns we emitted, just to be safe. */ | |
546b63fb | 6006 | for (p = get_insns (); p; p = NEXT_INSN (p)) |
32131a9c RK |
6007 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') |
6008 | { | |
6009 | /* If this output reload doesn't come from a spill reg, | |
6010 | clear any memory of reloaded copies of the pseudo reg. | |
6011 | If this output reload comes from a spill reg, | |
6012 | reg_has_output_reload will make this do nothing. */ | |
6013 | note_stores (PATTERN (p), forget_old_reloads_1); | |
6014 | ||
6015 | if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))) | |
6016 | store_insn = p; | |
6017 | } | |
6018 | ||
546b63fb RK |
6019 | output_reload_insns[reload_opnum[j]] = get_insns (); |
6020 | end_sequence (); | |
6021 | ||
32131a9c RK |
6022 | } |
6023 | ||
6024 | if (reload_spill_index[j] >= 0) | |
6025 | new_spill_reg_store[reload_spill_index[j]] = store_insn; | |
6026 | } | |
6027 | ||
546b63fb RK |
6028 | /* Now write all the insns we made for reloads in the order expected by |
6029 | the allocation functions. Prior to the insn being reloaded, we write | |
6030 | the following reloads: | |
6031 | ||
6032 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
6033 | ||
6034 | RELOAD_OTHER reloads. | |
6035 | ||
6036 | For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by | |
6037 | the RELOAD_FOR_INPUT reload for the operand. | |
6038 | ||
6039 | RELOAD_FOR_OPERAND_ADDRESS reloads. | |
6040 | ||
6041 | After the insn being reloaded, we write the following: | |
6042 | ||
6043 | For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by | |
6044 | the RELOAD_FOR_OUTPUT reload for that operand. */ | |
6045 | ||
6046 | emit_insns_before (other_input_address_reload_insns, before_insn); | |
6047 | emit_insns_before (other_input_reload_insns, before_insn); | |
6048 | ||
6049 | for (j = 0; j < reload_n_operands; j++) | |
6050 | { | |
6051 | emit_insns_before (input_address_reload_insns[j], before_insn); | |
6052 | emit_insns_before (input_reload_insns[j], before_insn); | |
6053 | } | |
6054 | ||
6055 | emit_insns_before (operand_reload_insns, before_insn); | |
6056 | ||
6057 | for (j = 0; j < reload_n_operands; j++) | |
6058 | { | |
6059 | emit_insns_before (output_address_reload_insns[j], following_insn); | |
6060 | emit_insns_before (output_reload_insns[j], following_insn); | |
6061 | } | |
6062 | ||
32131a9c RK |
6063 | /* Move death notes from INSN |
6064 | to output-operand-address and output reload insns. */ | |
6065 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
6066 | { | |
6067 | rtx insn1; | |
6068 | /* Loop over those insns, last ones first. */ | |
6069 | for (insn1 = PREV_INSN (following_insn); insn1 != insn; | |
6070 | insn1 = PREV_INSN (insn1)) | |
6071 | if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET) | |
6072 | { | |
6073 | rtx source = SET_SRC (PATTERN (insn1)); | |
6074 | rtx dest = SET_DEST (PATTERN (insn1)); | |
6075 | ||
6076 | /* The note we will examine next. */ | |
6077 | rtx reg_notes = REG_NOTES (insn); | |
6078 | /* The place that pointed to this note. */ | |
6079 | rtx *prev_reg_note = ®_NOTES (insn); | |
6080 | ||
6081 | /* If the note is for something used in the source of this | |
6082 | reload insn, or in the output address, move the note. */ | |
6083 | while (reg_notes) | |
6084 | { | |
6085 | rtx next_reg_notes = XEXP (reg_notes, 1); | |
6086 | if (REG_NOTE_KIND (reg_notes) == REG_DEAD | |
6087 | && GET_CODE (XEXP (reg_notes, 0)) == REG | |
6088 | && ((GET_CODE (dest) != REG | |
bfa30b22 RK |
6089 | && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), |
6090 | dest)) | |
6091 | || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), | |
6092 | source))) | |
32131a9c RK |
6093 | { |
6094 | *prev_reg_note = next_reg_notes; | |
6095 | XEXP (reg_notes, 1) = REG_NOTES (insn1); | |
6096 | REG_NOTES (insn1) = reg_notes; | |
6097 | } | |
6098 | else | |
6099 | prev_reg_note = &XEXP (reg_notes, 1); | |
6100 | ||
6101 | reg_notes = next_reg_notes; | |
6102 | } | |
6103 | } | |
6104 | } | |
6105 | #endif | |
6106 | ||
6107 | /* For all the spill regs newly reloaded in this instruction, | |
6108 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
6109 | can inherit the reloads. |
6110 | ||
6111 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 6112 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
6113 | |
6114 | for (j = 0; j < n_reloads; j++) | |
6115 | { | |
6116 | register int r = reload_order[j]; | |
6117 | register int i = reload_spill_index[r]; | |
6118 | ||
6119 | /* I is nonneg if this reload used one of the spill regs. | |
6120 | If reload_reg_rtx[r] is 0, this is an optional reload | |
546b63fb RK |
6121 | that we opted to ignore. |
6122 | ||
6123 | Also ignore reloads that don't reach the end of the insn, | |
6124 | since we will eventually see the one that does. */ | |
d445b551 | 6125 | |
546b63fb RK |
6126 | if (i >= 0 && reload_reg_rtx[r] != 0 |
6127 | && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r], | |
6128 | reload_when_needed[r])) | |
32131a9c RK |
6129 | { |
6130 | /* First, clear out memory of what used to be in this spill reg. | |
6131 | If consecutive registers are used, clear them all. */ | |
6132 | int nr | |
6133 | = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r])); | |
6134 | int k; | |
6135 | ||
6136 | for (k = 0; k < nr; k++) | |
6137 | { | |
6138 | reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1; | |
6139 | reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0; | |
6140 | } | |
6141 | ||
6142 | /* Maybe the spill reg contains a copy of reload_out. */ | |
6143 | if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) | |
6144 | { | |
6145 | register int nregno = REGNO (reload_out[r]); | |
d08ea79f RK |
6146 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
6147 | : HARD_REGNO_NREGS (nregno, | |
6148 | GET_MODE (reload_reg_rtx[r]))); | |
d445b551 RK |
6149 | |
6150 | spill_reg_store[i] = new_spill_reg_store[i]; | |
32131a9c | 6151 | reg_last_reload_reg[nregno] = reload_reg_rtx[r]; |
d445b551 | 6152 | |
d08ea79f RK |
6153 | /* If NREGNO is a hard register, it may occupy more than |
6154 | one register. If it does, say what is in the | |
6155 | rest of the registers assuming that both registers | |
6156 | agree on how many words the object takes. If not, | |
6157 | invalidate the subsequent registers. */ | |
6158 | ||
6159 | if (nregno < FIRST_PSEUDO_REGISTER) | |
6160 | for (k = 1; k < nnr; k++) | |
6161 | reg_last_reload_reg[nregno + k] | |
6162 | = (nr == nnr ? gen_rtx (REG, word_mode, | |
6163 | REGNO (reload_reg_rtx[r]) + k) | |
6164 | : 0); | |
6165 | ||
6166 | /* Now do the inverse operation. */ | |
32131a9c RK |
6167 | for (k = 0; k < nr; k++) |
6168 | { | |
6169 | reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] | |
d08ea79f RK |
6170 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno |
6171 | : nregno + k); | |
32131a9c RK |
6172 | reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn; |
6173 | } | |
6174 | } | |
d445b551 | 6175 | |
2c9ce2ef RK |
6176 | /* Maybe the spill reg contains a copy of reload_in. Only do |
6177 | something if there will not be an output reload for | |
6178 | the register being reloaded. */ | |
32131a9c RK |
6179 | else if (reload_out[r] == 0 |
6180 | && reload_in[r] != 0 | |
2c9ce2ef RK |
6181 | && ((GET_CODE (reload_in[r]) == REG |
6182 | && ! reg_has_output_reload[REGNO (reload_in[r])] | |
6183 | || (GET_CODE (reload_in_reg[r]) == REG | |
6184 | && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))) | |
32131a9c RK |
6185 | { |
6186 | register int nregno; | |
d08ea79f RK |
6187 | int nnr; |
6188 | ||
32131a9c RK |
6189 | if (GET_CODE (reload_in[r]) == REG) |
6190 | nregno = REGNO (reload_in[r]); | |
6191 | else | |
6192 | nregno = REGNO (reload_in_reg[r]); | |
6193 | ||
d08ea79f RK |
6194 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
6195 | : HARD_REGNO_NREGS (nregno, | |
6196 | GET_MODE (reload_reg_rtx[r]))); | |
6197 | ||
546b63fb | 6198 | reg_last_reload_reg[nregno] = reload_reg_rtx[r]; |
d445b551 | 6199 | |
d08ea79f RK |
6200 | if (nregno < FIRST_PSEUDO_REGISTER) |
6201 | for (k = 1; k < nnr; k++) | |
6202 | reg_last_reload_reg[nregno + k] | |
6203 | = (nr == nnr ? gen_rtx (REG, word_mode, | |
6204 | REGNO (reload_reg_rtx[r]) + k) | |
6205 | : 0); | |
6206 | ||
546b63fb RK |
6207 | /* Unless we inherited this reload, show we haven't |
6208 | recently done a store. */ | |
6209 | if (! reload_inherited[r]) | |
6210 | spill_reg_store[i] = 0; | |
d445b551 | 6211 | |
546b63fb RK |
6212 | for (k = 0; k < nr; k++) |
6213 | { | |
6214 | reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] | |
d08ea79f RK |
6215 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno |
6216 | : nregno + k); | |
546b63fb RK |
6217 | reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] |
6218 | = insn; | |
32131a9c RK |
6219 | } |
6220 | } | |
6221 | } | |
6222 | ||
6223 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
6224 | It's reenabled in 1.35 because supposedly nothing else | |
6225 | deals with this problem. */ | |
6226 | ||
6227 | /* If a register gets output-reloaded from a non-spill register, | |
6228 | that invalidates any previous reloaded copy of it. | |
6229 | But forget_old_reloads_1 won't get to see it, because | |
6230 | it thinks only about the original insn. So invalidate it here. */ | |
6231 | if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) | |
6232 | { | |
6233 | register int nregno = REGNO (reload_out[r]); | |
6234 | reg_last_reload_reg[nregno] = 0; | |
6235 | } | |
6236 | } | |
6237 | } | |
6238 | \f | |
546b63fb RK |
6239 | /* Emit code to perform an input reload of IN to RELOADREG. IN is from |
6240 | operand OPNUM with reload type TYPE. | |
6241 | ||
3c3eeea6 | 6242 | Returns first insn emitted. */ |
32131a9c RK |
6243 | |
6244 | rtx | |
546b63fb | 6245 | gen_input_reload (reloadreg, in, opnum, type) |
32131a9c RK |
6246 | rtx reloadreg; |
6247 | rtx in; | |
546b63fb RK |
6248 | int opnum; |
6249 | enum reload_type type; | |
32131a9c | 6250 | { |
546b63fb | 6251 | rtx last = get_last_insn (); |
32131a9c | 6252 | |
a8fdc208 | 6253 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
6254 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
6255 | register that didn't get a hard register. In that case we can just | |
6256 | call emit_move_insn. | |
6257 | ||
3002e160 JW |
6258 | We can also be asked to reload a PLUS that adds either two registers, or |
6259 | a register and a constant or MEM, or a MEM and a constant. This can | |
6260 | occur during frame pointer elimination and while reloading addresses. | |
6261 | This case is handled by trying to emit a single insn | |
32131a9c RK |
6262 | to perform the add. If it is not valid, we use a two insn sequence. |
6263 | ||
6264 | Finally, we could be called to handle an 'o' constraint by putting | |
6265 | an address into a register. In that case, we first try to do this | |
6266 | with a named pattern of "reload_load_address". If no such pattern | |
6267 | exists, we just emit a SET insn and hope for the best (it will normally | |
6268 | be valid on machines that use 'o'). | |
6269 | ||
6270 | This entire process is made complex because reload will never | |
6271 | process the insns we generate here and so we must ensure that | |
6272 | they will fit their constraints and also by the fact that parts of | |
6273 | IN might be being reloaded separately and replaced with spill registers. | |
6274 | Because of this, we are, in some sense, just guessing the right approach | |
6275 | here. The one listed above seems to work. | |
6276 | ||
6277 | ??? At some point, this whole thing needs to be rethought. */ | |
6278 | ||
6279 | if (GET_CODE (in) == PLUS | |
3002e160 JW |
6280 | && ((GET_CODE (XEXP (in, 0)) == REG |
6281 | && (GET_CODE (XEXP (in, 1)) == REG | |
6282 | || CONSTANT_P (XEXP (in, 1)) | |
6283 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
6284 | || (GET_CODE (XEXP (in, 0)) == MEM | |
6285 | && CONSTANT_P (XEXP (in, 1))))) | |
32131a9c RK |
6286 | { |
6287 | /* We need to compute the sum of what is either a register and a | |
3002e160 JW |
6288 | constant, a register and memory, a hard register and a pseudo |
6289 | register, or memory and a constant and put it into the reload | |
6290 | register. The best possible way of doing this is if the machine | |
6291 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
6292 | |
6293 | The simplest approach is to try to generate such an insn and see if it | |
6294 | is recognized and matches its constraints. If so, it can be used. | |
6295 | ||
6296 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 6297 | but we need to pass the insn as an operand to `recog' and |
b36d7dd7 | 6298 | `insn_extract' and it is simpler to emit and then delete the insn if |
0009eff2 | 6299 | not valid than to dummy things up. */ |
a8fdc208 | 6300 | |
af929c62 | 6301 | rtx op0, op1, tem, insn; |
32131a9c | 6302 | int code; |
a8fdc208 | 6303 | |
af929c62 RK |
6304 | op0 = find_replacement (&XEXP (in, 0)); |
6305 | op1 = find_replacement (&XEXP (in, 1)); | |
6306 | ||
32131a9c RK |
6307 | /* Since constraint checking is strict, commutativity won't be |
6308 | checked, so we need to do that here to avoid spurious failure | |
6309 | if the add instruction is two-address and the second operand | |
6310 | of the add is the same as the reload reg, which is frequently | |
6311 | the case. If the insn would be A = B + A, rearrange it so | |
6312 | it will be A = A + B as constrain_operands expects. */ | |
a8fdc208 | 6313 | |
32131a9c RK |
6314 | if (GET_CODE (XEXP (in, 1)) == REG |
6315 | && REGNO (reloadreg) == REGNO (XEXP (in, 1))) | |
af929c62 RK |
6316 | tem = op0, op0 = op1, op1 = tem; |
6317 | ||
6318 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
6319 | in = gen_rtx (PLUS, GET_MODE (in), op0, op1); | |
32131a9c | 6320 | |
546b63fb | 6321 | insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in)); |
32131a9c RK |
6322 | code = recog_memoized (insn); |
6323 | ||
6324 | if (code >= 0) | |
6325 | { | |
6326 | insn_extract (insn); | |
6327 | /* We want constrain operands to treat this insn strictly in | |
6328 | its validity determination, i.e., the way it would after reload | |
6329 | has completed. */ | |
6330 | if (constrain_operands (code, 1)) | |
6331 | return insn; | |
6332 | } | |
6333 | ||
546b63fb | 6334 | delete_insns_since (last); |
32131a9c RK |
6335 | |
6336 | /* If that failed, we must use a conservative two-insn sequence. | |
6337 | use move to copy constant, MEM, or pseudo register to the reload | |
af929c62 RK |
6338 | register since "move" will be able to handle an arbitrary operand, |
6339 | unlike add which can't, in general. Then add the registers. | |
32131a9c RK |
6340 | |
6341 | If there is another way to do this for a specific machine, a | |
6342 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
6343 | we emit below. */ | |
6344 | ||
af929c62 RK |
6345 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM |
6346 | || (GET_CODE (op1) == REG | |
6347 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER)) | |
6348 | tem = op0, op0 = op1, op1 = tem; | |
32131a9c | 6349 | |
546b63fb | 6350 | emit_insn (gen_move_insn (reloadreg, op0)); |
39b56c2a RK |
6351 | |
6352 | /* If OP0 and OP1 are the same, we can use RELOADREG for OP1. | |
6353 | This fixes a problem on the 32K where the stack pointer cannot | |
6354 | be used as an operand of an add insn. */ | |
6355 | ||
6356 | if (rtx_equal_p (op0, op1)) | |
6357 | op1 = reloadreg; | |
6358 | ||
546b63fb | 6359 | emit_insn (gen_add2_insn (reloadreg, op1)); |
32131a9c RK |
6360 | } |
6361 | ||
0dadecf6 RK |
6362 | #ifdef SECONDARY_MEMORY_NEEDED |
6363 | /* If we need a memory location to do the move, do it that way. */ | |
6364 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
6365 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), | |
6366 | REGNO_REG_CLASS (REGNO (reloadreg)), | |
6367 | GET_MODE (reloadreg))) | |
6368 | { | |
6369 | /* Get the memory to use and rewrite both registers to its mode. */ | |
546b63fb | 6370 | rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type); |
0dadecf6 RK |
6371 | |
6372 | if (GET_MODE (loc) != GET_MODE (reloadreg)) | |
6373 | reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg)); | |
6374 | ||
6375 | if (GET_MODE (loc) != GET_MODE (in)) | |
6376 | in = gen_rtx (REG, GET_MODE (loc), REGNO (in)); | |
6377 | ||
546b63fb RK |
6378 | emit_insn (gen_move_insn (loc, in)); |
6379 | emit_insn (gen_move_insn (reloadreg, loc)); | |
0dadecf6 RK |
6380 | } |
6381 | #endif | |
6382 | ||
32131a9c RK |
6383 | /* If IN is a simple operand, use gen_move_insn. */ |
6384 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
546b63fb | 6385 | emit_insn (gen_move_insn (reloadreg, in)); |
32131a9c RK |
6386 | |
6387 | #ifdef HAVE_reload_load_address | |
6388 | else if (HAVE_reload_load_address) | |
546b63fb | 6389 | emit_insn (gen_reload_load_address (reloadreg, in)); |
32131a9c RK |
6390 | #endif |
6391 | ||
6392 | /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */ | |
6393 | else | |
546b63fb | 6394 | emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in)); |
32131a9c RK |
6395 | |
6396 | /* Return the first insn emitted. | |
546b63fb | 6397 | We can not just return get_last_insn, because there may have |
32131a9c RK |
6398 | been multiple instructions emitted. Also note that gen_move_insn may |
6399 | emit more than one insn itself, so we can not assume that there is one | |
6400 | insn emitted per emit_insn_before call. */ | |
6401 | ||
546b63fb | 6402 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
6403 | } |
6404 | \f | |
6405 | /* Delete a previously made output-reload | |
6406 | whose result we now believe is not needed. | |
6407 | First we double-check. | |
6408 | ||
6409 | INSN is the insn now being processed. | |
6410 | OUTPUT_RELOAD_INSN is the insn of the output reload. | |
6411 | J is the reload-number for this insn. */ | |
6412 | ||
6413 | static void | |
6414 | delete_output_reload (insn, j, output_reload_insn) | |
6415 | rtx insn; | |
6416 | int j; | |
6417 | rtx output_reload_insn; | |
6418 | { | |
6419 | register rtx i1; | |
6420 | ||
6421 | /* Get the raw pseudo-register referred to. */ | |
6422 | ||
6423 | rtx reg = reload_in[j]; | |
6424 | while (GET_CODE (reg) == SUBREG) | |
6425 | reg = SUBREG_REG (reg); | |
6426 | ||
6427 | /* If the pseudo-reg we are reloading is no longer referenced | |
6428 | anywhere between the store into it and here, | |
6429 | and no jumps or labels intervene, then the value can get | |
6430 | here through the reload reg alone. | |
6431 | Otherwise, give up--return. */ | |
6432 | for (i1 = NEXT_INSN (output_reload_insn); | |
6433 | i1 != insn; i1 = NEXT_INSN (i1)) | |
6434 | { | |
6435 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
6436 | return; | |
6437 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
6438 | && reg_mentioned_p (reg, PATTERN (i1))) | |
6439 | return; | |
6440 | } | |
6441 | ||
6442 | /* If this insn will store in the pseudo again, | |
6443 | the previous store can be removed. */ | |
6444 | if (reload_out[j] == reload_in[j]) | |
6445 | delete_insn (output_reload_insn); | |
6446 | ||
6447 | /* See if the pseudo reg has been completely replaced | |
6448 | with reload regs. If so, delete the store insn | |
6449 | and forget we had a stack slot for the pseudo. */ | |
6450 | else if (reg_n_deaths[REGNO (reg)] == 1 | |
6451 | && reg_basic_block[REGNO (reg)] >= 0 | |
6452 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
6453 | { | |
6454 | rtx i2; | |
6455 | ||
6456 | /* We know that it was used only between here | |
6457 | and the beginning of the current basic block. | |
6458 | (We also know that the last use before INSN was | |
6459 | the output reload we are thinking of deleting, but never mind that.) | |
6460 | Search that range; see if any ref remains. */ | |
6461 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
6462 | { | |
d445b551 RK |
6463 | rtx set = single_set (i2); |
6464 | ||
32131a9c RK |
6465 | /* Uses which just store in the pseudo don't count, |
6466 | since if they are the only uses, they are dead. */ | |
d445b551 | 6467 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
6468 | continue; |
6469 | if (GET_CODE (i2) == CODE_LABEL | |
6470 | || GET_CODE (i2) == JUMP_INSN) | |
6471 | break; | |
6472 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
6473 | && reg_mentioned_p (reg, PATTERN (i2))) | |
6474 | /* Some other ref remains; | |
6475 | we can't do anything. */ | |
6476 | return; | |
6477 | } | |
6478 | ||
6479 | /* Delete the now-dead stores into this pseudo. */ | |
6480 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
6481 | { | |
d445b551 RK |
6482 | rtx set = single_set (i2); |
6483 | ||
6484 | if (set != 0 && SET_DEST (set) == reg) | |
32131a9c RK |
6485 | delete_insn (i2); |
6486 | if (GET_CODE (i2) == CODE_LABEL | |
6487 | || GET_CODE (i2) == JUMP_INSN) | |
6488 | break; | |
6489 | } | |
6490 | ||
6491 | /* For the debugging info, | |
6492 | say the pseudo lives in this reload reg. */ | |
6493 | reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]); | |
6494 | alter_reg (REGNO (reg), -1); | |
6495 | } | |
6496 | } | |
32131a9c | 6497 | \f |
a8fdc208 | 6498 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 6499 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
6500 | is a register or memory location; |
6501 | so reloading involves incrementing that location. | |
6502 | ||
6503 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
546b63fb | 6504 | This cannot be deduced from VALUE. */ |
32131a9c | 6505 | |
546b63fb RK |
6506 | static void |
6507 | inc_for_reload (reloadreg, value, inc_amount) | |
32131a9c RK |
6508 | rtx reloadreg; |
6509 | rtx value; | |
6510 | int inc_amount; | |
32131a9c RK |
6511 | { |
6512 | /* REG or MEM to be copied and incremented. */ | |
6513 | rtx incloc = XEXP (value, 0); | |
6514 | /* Nonzero if increment after copying. */ | |
6515 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 6516 | rtx last; |
0009eff2 RK |
6517 | rtx inc; |
6518 | rtx add_insn; | |
6519 | int code; | |
32131a9c RK |
6520 | |
6521 | /* No hard register is equivalent to this register after | |
6522 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
6523 | we could inc/dec that register as well (maybe even using it for | |
6524 | the source), but I'm not sure it's worth worrying about. */ | |
6525 | if (GET_CODE (incloc) == REG) | |
6526 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
6527 | ||
6528 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
6529 | inc_amount = - inc_amount; | |
6530 | ||
fb3821f7 | 6531 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
6532 | |
6533 | /* If this is post-increment, first copy the location to the reload reg. */ | |
6534 | if (post) | |
546b63fb | 6535 | emit_insn (gen_move_insn (reloadreg, incloc)); |
0009eff2 RK |
6536 | |
6537 | /* See if we can directly increment INCLOC. Use a method similar to that | |
6538 | in gen_input_reload. */ | |
6539 | ||
546b63fb RK |
6540 | last = get_last_insn (); |
6541 | add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc, | |
6542 | gen_rtx (PLUS, GET_MODE (incloc), | |
6543 | incloc, inc))); | |
0009eff2 RK |
6544 | |
6545 | code = recog_memoized (add_insn); | |
6546 | if (code >= 0) | |
32131a9c | 6547 | { |
0009eff2 RK |
6548 | insn_extract (add_insn); |
6549 | if (constrain_operands (code, 1)) | |
32131a9c | 6550 | { |
0009eff2 RK |
6551 | /* If this is a pre-increment and we have incremented the value |
6552 | where it lives, copy the incremented value to RELOADREG to | |
6553 | be used as an address. */ | |
6554 | ||
6555 | if (! post) | |
546b63fb RK |
6556 | emit_insn (gen_move_insn (reloadreg, incloc)); |
6557 | ||
6558 | return; | |
32131a9c RK |
6559 | } |
6560 | } | |
0009eff2 | 6561 | |
546b63fb | 6562 | delete_insns_since (last); |
0009eff2 RK |
6563 | |
6564 | /* If couldn't do the increment directly, must increment in RELOADREG. | |
6565 | The way we do this depends on whether this is pre- or post-increment. | |
6566 | For pre-increment, copy INCLOC to the reload register, increment it | |
6567 | there, then save back. */ | |
6568 | ||
6569 | if (! post) | |
6570 | { | |
546b63fb RK |
6571 | emit_insn (gen_move_insn (reloadreg, incloc)); |
6572 | emit_insn (gen_add2_insn (reloadreg, inc)); | |
6573 | emit_insn (gen_move_insn (incloc, reloadreg)); | |
0009eff2 | 6574 | } |
32131a9c RK |
6575 | else |
6576 | { | |
0009eff2 RK |
6577 | /* Postincrement. |
6578 | Because this might be a jump insn or a compare, and because RELOADREG | |
6579 | may not be available after the insn in an input reload, we must do | |
6580 | the incrementation before the insn being reloaded for. | |
6581 | ||
6582 | We have already copied INCLOC to RELOADREG. Increment the copy in | |
6583 | RELOADREG, save that back, then decrement RELOADREG so it has | |
6584 | the original value. */ | |
6585 | ||
546b63fb RK |
6586 | emit_insn (gen_add2_insn (reloadreg, inc)); |
6587 | emit_insn (gen_move_insn (incloc, reloadreg)); | |
6588 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); | |
32131a9c | 6589 | } |
0009eff2 | 6590 | |
546b63fb | 6591 | return; |
32131a9c RK |
6592 | } |
6593 | \f | |
6594 | /* Return 1 if we are certain that the constraint-string STRING allows | |
6595 | the hard register REG. Return 0 if we can't be sure of this. */ | |
6596 | ||
6597 | static int | |
6598 | constraint_accepts_reg_p (string, reg) | |
6599 | char *string; | |
6600 | rtx reg; | |
6601 | { | |
6602 | int value = 0; | |
6603 | int regno = true_regnum (reg); | |
6604 | int c; | |
6605 | ||
6606 | /* Initialize for first alternative. */ | |
6607 | value = 0; | |
6608 | /* Check that each alternative contains `g' or `r'. */ | |
6609 | while (1) | |
6610 | switch (c = *string++) | |
6611 | { | |
6612 | case 0: | |
6613 | /* If an alternative lacks `g' or `r', we lose. */ | |
6614 | return value; | |
6615 | case ',': | |
6616 | /* If an alternative lacks `g' or `r', we lose. */ | |
6617 | if (value == 0) | |
6618 | return 0; | |
6619 | /* Initialize for next alternative. */ | |
6620 | value = 0; | |
6621 | break; | |
6622 | case 'g': | |
6623 | case 'r': | |
6624 | /* Any general reg wins for this alternative. */ | |
6625 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
6626 | value = 1; | |
6627 | break; | |
6628 | default: | |
6629 | /* Any reg in specified class wins for this alternative. */ | |
6630 | { | |
0009eff2 | 6631 | enum reg_class class = REG_CLASS_FROM_LETTER (c); |
32131a9c | 6632 | |
0009eff2 | 6633 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) |
32131a9c RK |
6634 | value = 1; |
6635 | } | |
6636 | } | |
6637 | } | |
6638 | \f | |
d445b551 RK |
6639 | /* Return the number of places FIND appears within X, but don't count |
6640 | an occurrence if some SET_DEST is FIND. */ | |
32131a9c RK |
6641 | |
6642 | static int | |
6643 | count_occurrences (x, find) | |
6644 | register rtx x, find; | |
6645 | { | |
6646 | register int i, j; | |
6647 | register enum rtx_code code; | |
6648 | register char *format_ptr; | |
6649 | int count; | |
6650 | ||
6651 | if (x == find) | |
6652 | return 1; | |
6653 | if (x == 0) | |
6654 | return 0; | |
6655 | ||
6656 | code = GET_CODE (x); | |
6657 | ||
6658 | switch (code) | |
6659 | { | |
6660 | case REG: | |
6661 | case QUEUED: | |
6662 | case CONST_INT: | |
6663 | case CONST_DOUBLE: | |
6664 | case SYMBOL_REF: | |
6665 | case CODE_LABEL: | |
6666 | case PC: | |
6667 | case CC0: | |
6668 | return 0; | |
d445b551 RK |
6669 | |
6670 | case SET: | |
6671 | if (SET_DEST (x) == find) | |
6672 | return count_occurrences (SET_SRC (x), find); | |
6673 | break; | |
32131a9c RK |
6674 | } |
6675 | ||
6676 | format_ptr = GET_RTX_FORMAT (code); | |
6677 | count = 0; | |
6678 | ||
6679 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
6680 | { | |
6681 | switch (*format_ptr++) | |
6682 | { | |
6683 | case 'e': | |
6684 | count += count_occurrences (XEXP (x, i), find); | |
6685 | break; | |
6686 | ||
6687 | case 'E': | |
6688 | if (XVEC (x, i) != NULL) | |
6689 | { | |
6690 | for (j = 0; j < XVECLEN (x, i); j++) | |
6691 | count += count_occurrences (XVECEXP (x, i, j), find); | |
6692 | } | |
6693 | break; | |
6694 | } | |
6695 | } | |
6696 | return count; | |
6697 | } |