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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
e56b4594 | 3 | 1999, 2000, 2001 Free Software Foundation, Inc. |
32131a9c | 4 | |
1322177d | 5 | This file is part of GCC. |
32131a9c | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
32131a9c | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
32131a9c RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
cab634f2 KG |
24 | |
25 | #include "machmode.h" | |
26 | #include "hard-reg-set.h" | |
32131a9c | 27 | #include "rtl.h" |
6baf1cc8 | 28 | #include "tm_p.h" |
32131a9c RK |
29 | #include "obstack.h" |
30 | #include "insn-config.h" | |
32131a9c | 31 | #include "flags.h" |
49ad7cfa | 32 | #include "function.h" |
32131a9c | 33 | #include "expr.h" |
e78d8e51 | 34 | #include "optabs.h" |
32131a9c | 35 | #include "regs.h" |
cad6f7d0 | 36 | #include "basic-block.h" |
32131a9c RK |
37 | #include "reload.h" |
38 | #include "recog.h" | |
32131a9c | 39 | #include "output.h" |
eab5c70a | 40 | #include "cselib.h" |
a9c366bf | 41 | #include "real.h" |
10f0ad3d | 42 | #include "toplev.h" |
39f95a2c | 43 | #include "except.h" |
32131a9c RK |
44 | |
45 | /* This file contains the reload pass of the compiler, which is | |
46 | run after register allocation has been done. It checks that | |
47 | each insn is valid (operands required to be in registers really | |
48 | are in registers of the proper class) and fixes up invalid ones | |
49 | by copying values temporarily into registers for the insns | |
50 | that need them. | |
51 | ||
52 | The results of register allocation are described by the vector | |
53 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
54 | can be used to find which hard reg, if any, a pseudo reg is in. | |
55 | ||
56 | The technique we always use is to free up a few hard regs that are | |
57 | called ``reload regs'', and for each place where a pseudo reg | |
58 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
59 | ||
03acd8f8 BS |
60 | Reload regs are allocated locally for every instruction that needs |
61 | reloads. When there are pseudos which are allocated to a register that | |
62 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
63 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
64 | available hard regs can be found. Spilling can invalidate more |
65 | insns, requiring additional need for reloads, so we must keep checking | |
66 | until the process stabilizes. | |
67 | ||
68 | For machines with different classes of registers, we must keep track | |
69 | of the register class needed for each reload, and make sure that | |
70 | we allocate enough reload registers of each class. | |
71 | ||
72 | The file reload.c contains the code that checks one insn for | |
73 | validity and reports the reloads that it needs. This file | |
74 | is in charge of scanning the entire rtl code, accumulating the | |
75 | reload needs, spilling, assigning reload registers to use for | |
76 | fixing up each insn, and generating the new insns to copy values | |
77 | into the reload registers. */ | |
546b63fb | 78 | |
546b63fb | 79 | #ifndef REGISTER_MOVE_COST |
e56b4594 | 80 | #define REGISTER_MOVE_COST(m, x, y) 2 |
546b63fb | 81 | #endif |
2a3e384f RH |
82 | |
83 | #ifndef LOCAL_REGNO | |
84 | #define LOCAL_REGNO(REGNO) 0 | |
85 | #endif | |
32131a9c RK |
86 | \f |
87 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 88 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
89 | static rtx *reg_last_reload_reg; |
90 | ||
91 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
92 | for an output reload that stores into reg N. */ | |
93 | static char *reg_has_output_reload; | |
94 | ||
95 | /* Indicates which hard regs are reload-registers for an output reload | |
96 | in the current insn. */ | |
97 | static HARD_REG_SET reg_is_output_reload; | |
98 | ||
99 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
100 | or zero if pseudo reg N is not equivalent to a constant. | |
101 | find_reloads looks at this in order to replace pseudo reg N | |
102 | with the constant it stands for. */ | |
103 | rtx *reg_equiv_constant; | |
104 | ||
105 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
106 | prior to any register elimination (such as frame pointer to stack | |
107 | pointer). Depending on whether or not it is a valid address, this value | |
108 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 109 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
110 | |
111 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
112 | This is used when the address is not valid as a memory address | |
113 | (because its displacement is too big for the machine.) */ | |
114 | rtx *reg_equiv_address; | |
115 | ||
116 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
117 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
118 | rtx *reg_equiv_mem; | |
119 | ||
120 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
770ae6cc | 121 | static unsigned int *reg_max_ref_width; |
32131a9c | 122 | |
135eb61c | 123 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c RK |
124 | constant or memory slot. */ |
125 | static rtx *reg_equiv_init; | |
126 | ||
03acd8f8 BS |
127 | /* Vector to remember old contents of reg_renumber before spilling. */ |
128 | static short *reg_old_renumber; | |
129 | ||
e6e52be0 | 130 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 131 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
132 | reg_reloaded_contents points to that pseudo for each spill register in |
133 | use; all of these must remain set for an inheritance to occur. */ | |
134 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
135 | ||
136 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
137 | hard register N was last used. Its contents are significant only |
138 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
139 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
140 | ||
e6e52be0 R |
141 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ |
142 | static HARD_REG_SET reg_reloaded_valid; | |
143 | /* Indicate if the register was dead at the end of the reload. | |
144 | This is only valid if reg_reloaded_contents is set and valid. */ | |
145 | static HARD_REG_SET reg_reloaded_dead; | |
146 | ||
32131a9c RK |
147 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
148 | static int n_spills; | |
149 | ||
150 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
151 | Holds the last rtx used for any given reg, or 0 if it has never | |
152 | been used for spilling yet. This rtx is reused, provided it has | |
153 | the proper mode. */ | |
154 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
155 | ||
156 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
157 | that was stored after the last time it was used. | |
158 | The precise value is the insn generated to do the store. */ | |
159 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
160 | ||
cb2afeb3 R |
161 | /* This is the register that was stored with spill_reg_store. This is a |
162 | copy of reload_out / reload_out_reg when the value was stored; if | |
163 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
164 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
165 | ||
32131a9c RK |
166 | /* This table is the inverse mapping of spill_regs: |
167 | indexed by hard reg number, | |
168 | it contains the position of that reg in spill_regs, | |
05d10675 | 169 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
170 | |
171 | ?!? This is no longer accurate. */ | |
32131a9c RK |
172 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
173 | ||
03acd8f8 BS |
174 | /* This reg set indicates registers that can't be used as spill registers for |
175 | the currently processed insn. These are the hard registers which are live | |
176 | during the insn, but not allocated to pseudos, as well as fixed | |
177 | registers. */ | |
32131a9c RK |
178 | static HARD_REG_SET bad_spill_regs; |
179 | ||
03acd8f8 BS |
180 | /* These are the hard registers that can't be used as spill register for any |
181 | insn. This includes registers used for user variables and registers that | |
182 | we can't eliminate. A register that appears in this set also can't be used | |
183 | to retry register allocation. */ | |
184 | static HARD_REG_SET bad_spill_regs_global; | |
185 | ||
32131a9c | 186 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
187 | of spilled pseudo-registers. `n_spills' is the number of |
188 | elements that are actually valid; new ones are added at the end. | |
189 | ||
190 | Both spill_regs and spill_reg_order are used on two occasions: | |
191 | once during find_reload_regs, where they keep track of the spill registers | |
192 | for a single insn, but also during reload_as_needed where they show all | |
193 | the registers ever used by reload. For the latter case, the information | |
194 | is calculated during finish_spills. */ | |
32131a9c RK |
195 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
196 | ||
03acd8f8 BS |
197 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
198 | may not be used for retrying global allocation because the register was | |
199 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
200 | a register that it was already allocated to, reload might not | |
201 | terminate. */ | |
202 | static HARD_REG_SET *pseudo_previous_regs; | |
203 | ||
204 | /* This vector of reg sets indicates, for each pseudo, which hard | |
205 | registers may not be used for retrying global allocation because they | |
206 | are used as spill registers during one of the insns in which the | |
207 | pseudo is live. */ | |
208 | static HARD_REG_SET *pseudo_forbidden_regs; | |
209 | ||
210 | /* All hard regs that have been used as spill registers for any insn are | |
211 | marked in this set. */ | |
212 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 213 | |
4079cd63 JW |
214 | /* Index of last register assigned as a spill register. We allocate in |
215 | a round-robin fashion. */ | |
4079cd63 JW |
216 | static int last_spill_reg; |
217 | ||
32131a9c RK |
218 | /* Nonzero if indirect addressing is supported on the machine; this means |
219 | that spilling (REG n) does not require reloading it into a register in | |
220 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
221 | value indicates the level of indirect addressing supported, e.g., two | |
222 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
223 | a hard register. */ | |
32131a9c RK |
224 | static char spill_indirect_levels; |
225 | ||
226 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
227 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
228 | which these are valid is the same as spill_indirect_levels, above. */ | |
32131a9c RK |
229 | char indirect_symref_ok; |
230 | ||
231 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
232 | char double_reg_address_ok; |
233 | ||
234 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
235 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
236 | ||
237 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 238 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 239 | |
7609e720 | 240 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
241 | static regset_head spilled_pseudos; |
242 | ||
243 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
244 | Used to avoid counting one pseudo twice. */ | |
245 | static regset_head pseudos_counted; | |
7609e720 | 246 | |
32131a9c RK |
247 | /* First uid used by insns created by reload in this function. |
248 | Used in find_equiv_reg. */ | |
249 | int reload_first_uid; | |
250 | ||
251 | /* Flag set by local-alloc or global-alloc if anything is live in | |
252 | a call-clobbered reg across calls. */ | |
32131a9c RK |
253 | int caller_save_needed; |
254 | ||
255 | /* Set to 1 while reload_as_needed is operating. | |
256 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
257 | int reload_in_progress = 0; |
258 | ||
259 | /* These arrays record the insn_code of insns that may be needed to | |
260 | perform input and output reloads of special objects. They provide a | |
261 | place to pass a scratch register. */ | |
32131a9c RK |
262 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
263 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
264 | ||
d45cf215 | 265 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
266 | The allocated storage can be freed once find_reloads has processed the |
267 | insn. */ | |
32131a9c | 268 | struct obstack reload_obstack; |
cad6f7d0 BS |
269 | |
270 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
271 | are allocated first. */ | |
272 | char *reload_startobj; | |
273 | ||
274 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 275 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
32131a9c RK |
276 | char *reload_firstobj; |
277 | ||
f5d8c9f4 BS |
278 | /* This points before all local rtl generated by register elimination. |
279 | Used to quickly free all memory after processing one insn. */ | |
280 | static char *reload_insn_firstobj; | |
281 | ||
32131a9c RK |
282 | #define obstack_chunk_alloc xmalloc |
283 | #define obstack_chunk_free free | |
284 | ||
cad6f7d0 BS |
285 | /* List of insn_chain instructions, one for every insn that reload needs to |
286 | examine. */ | |
287 | struct insn_chain *reload_insn_chain; | |
7609e720 | 288 | |
dfb7c80f JL |
289 | #ifdef TREE_CODE |
290 | extern tree current_function_decl; | |
291 | #else | |
122a860e | 292 | extern union tree_node *current_function_decl; |
dfb7c80f JL |
293 | #endif |
294 | ||
03acd8f8 | 295 | /* List of all insns needing reloads. */ |
7609e720 | 296 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
297 | \f |
298 | /* This structure is used to record information about register eliminations. | |
299 | Each array entry describes one possible way of eliminating a register | |
300 | in favor of another. If there is more than one way of eliminating a | |
301 | particular register, the most preferred should be specified first. */ | |
302 | ||
590cf94d | 303 | struct elim_table |
32131a9c | 304 | { |
0f41302f MS |
305 | int from; /* Register number to be eliminated. */ |
306 | int to; /* Register number used as replacement. */ | |
307 | int initial_offset; /* Initial difference between values. */ | |
308 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
32131a9c | 309 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f MS |
310 | insns made by reload. */ |
311 | int offset; /* Current offset between the two regs. */ | |
0f41302f MS |
312 | int previous_offset; /* Offset at end of previous insn. */ |
313 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
32131a9c RK |
314 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
315 | We cannot simply compare the number since | |
316 | we might then spuriously replace a hard | |
317 | register corresponding to a pseudo | |
0f41302f MS |
318 | assigned to the reg to be eliminated. */ |
319 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
320 | }; |
321 | ||
1d7254c5 | 322 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
323 | |
324 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 325 | exactly the members provided by ELIMINABLE_REGS. */ |
590cf94d KG |
326 | static struct elim_table_1 |
327 | { | |
328 | int from; | |
329 | int to; | |
330 | } reg_eliminate_1[] = | |
32131a9c RK |
331 | |
332 | /* If a set of eliminable registers was specified, define the table from it. | |
333 | Otherwise, default to the normal case of the frame pointer being | |
334 | replaced by the stack pointer. */ | |
335 | ||
336 | #ifdef ELIMINABLE_REGS | |
337 | ELIMINABLE_REGS; | |
338 | #else | |
339 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
340 | #endif | |
341 | ||
b6a1cbae | 342 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
343 | |
344 | /* Record the number of pending eliminations that have an offset not equal | |
345 | to their initial offset. If non-zero, we use a new copy of each | |
346 | replacement result in any insns encountered. */ | |
cb2afeb3 | 347 | int num_not_at_initial_offset; |
32131a9c RK |
348 | |
349 | /* Count the number of registers that we may be able to eliminate. */ | |
350 | static int num_eliminable; | |
2b49ee39 R |
351 | /* And the number of registers that are equivalent to a constant that |
352 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
353 | static int num_eliminable_invariants; | |
32131a9c RK |
354 | |
355 | /* For each label, we record the offset of each elimination. If we reach | |
356 | a label by more than one path and an offset differs, we cannot do the | |
357 | elimination. This information is indexed by the number of the label. | |
358 | The first table is an array of flags that records whether we have yet | |
359 | encountered a label and the second table is an array of arrays, one | |
360 | entry in the latter array for each elimination. */ | |
361 | ||
362 | static char *offsets_known_at; | |
363 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
364 | ||
365 | /* Number of labels in the current function. */ | |
366 | ||
367 | static int num_labels; | |
368 | \f | |
174fa2c4 AJ |
369 | static void replace_pseudos_in_call_usage PARAMS((rtx *, |
370 | enum machine_mode, | |
371 | rtx)); | |
cdadb1dd KG |
372 | static void maybe_fix_stack_asms PARAMS ((void)); |
373 | static void copy_reloads PARAMS ((struct insn_chain *)); | |
374 | static void calculate_needs_all_insns PARAMS ((int)); | |
e04ca094 JL |
375 | static int find_reg PARAMS ((struct insn_chain *, int)); |
376 | static void find_reload_regs PARAMS ((struct insn_chain *)); | |
377 | static void select_reload_regs PARAMS ((void)); | |
cdadb1dd KG |
378 | static void delete_caller_save_insns PARAMS ((void)); |
379 | ||
380 | static void spill_failure PARAMS ((rtx, enum reg_class)); | |
381 | static void count_spilled_pseudo PARAMS ((int, int, int)); | |
382 | static void delete_dead_insn PARAMS ((rtx)); | |
174fa2c4 | 383 | static void alter_reg PARAMS ((int, int)); |
cdadb1dd KG |
384 | static void set_label_offsets PARAMS ((rtx, rtx, int)); |
385 | static void check_eliminable_occurrences PARAMS ((rtx)); | |
386 | static void elimination_effects PARAMS ((rtx, enum machine_mode)); | |
387 | static int eliminate_regs_in_insn PARAMS ((rtx, int)); | |
388 | static void update_eliminable_offsets PARAMS ((void)); | |
389 | static void mark_not_eliminable PARAMS ((rtx, rtx, void *)); | |
390 | static void set_initial_elim_offsets PARAMS ((void)); | |
391 | static void verify_initial_elim_offsets PARAMS ((void)); | |
392 | static void set_initial_label_offsets PARAMS ((void)); | |
393 | static void set_offsets_for_label PARAMS ((rtx)); | |
394 | static void init_elim_table PARAMS ((void)); | |
395 | static void update_eliminables PARAMS ((HARD_REG_SET *)); | |
e04ca094 JL |
396 | static void spill_hard_reg PARAMS ((unsigned int, int)); |
397 | static int finish_spills PARAMS ((int)); | |
cdadb1dd KG |
398 | static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *)); |
399 | static void scan_paradoxical_subregs PARAMS ((rtx)); | |
400 | static void count_pseudo PARAMS ((int)); | |
401 | static void order_regs_for_reload PARAMS ((struct insn_chain *)); | |
e04ca094 | 402 | static void reload_as_needed PARAMS ((int)); |
cdadb1dd KG |
403 | static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *)); |
404 | static int reload_reg_class_lower PARAMS ((const PTR, const PTR)); | |
770ae6cc RK |
405 | static void mark_reload_reg_in_use PARAMS ((unsigned int, int, |
406 | enum reload_type, | |
407 | enum machine_mode)); | |
408 | static void clear_reload_reg_in_use PARAMS ((unsigned int, int, | |
409 | enum reload_type, | |
410 | enum machine_mode)); | |
411 | static int reload_reg_free_p PARAMS ((unsigned int, int, | |
412 | enum reload_type)); | |
304a22dd R |
413 | static int reload_reg_free_for_value_p PARAMS ((int, int, int, |
414 | enum reload_type, | |
770ae6cc | 415 | rtx, rtx, int, int)); |
c02cad8f BS |
416 | static int free_for_value_p PARAMS ((int, enum machine_mode, int, |
417 | enum reload_type, rtx, rtx, | |
418 | int, int)); | |
770ae6cc RK |
419 | static int reload_reg_reaches_end_p PARAMS ((unsigned int, int, |
420 | enum reload_type)); | |
421 | static int allocate_reload_reg PARAMS ((struct insn_chain *, int, | |
422 | int)); | |
ff6534ad | 423 | static int conflicts_with_override PARAMS ((rtx)); |
cdadb1dd KG |
424 | static void failed_reload PARAMS ((rtx, int)); |
425 | static int set_reload_reg PARAMS ((int, int)); | |
426 | static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *)); | |
427 | static void choose_reload_regs PARAMS ((struct insn_chain *)); | |
428 | static void merge_assigned_reloads PARAMS ((rtx)); | |
429 | static void emit_input_reload_insns PARAMS ((struct insn_chain *, | |
770ae6cc | 430 | struct reload *, rtx, int)); |
cdadb1dd | 431 | static void emit_output_reload_insns PARAMS ((struct insn_chain *, |
770ae6cc | 432 | struct reload *, int)); |
cdadb1dd | 433 | static void do_input_reload PARAMS ((struct insn_chain *, |
770ae6cc | 434 | struct reload *, int)); |
cdadb1dd | 435 | static void do_output_reload PARAMS ((struct insn_chain *, |
770ae6cc | 436 | struct reload *, int)); |
e04ca094 | 437 | static void emit_reload_insns PARAMS ((struct insn_chain *)); |
cdadb1dd KG |
438 | static void delete_output_reload PARAMS ((rtx, int, int)); |
439 | static void delete_address_reloads PARAMS ((rtx, rtx)); | |
440 | static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx)); | |
441 | static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int)); | |
442 | static int constraint_accepts_reg_p PARAMS ((const char *, rtx)); | |
443 | static void reload_cse_regs_1 PARAMS ((rtx)); | |
eab5c70a | 444 | static int reload_cse_noop_set_p PARAMS ((rtx)); |
cdadb1dd KG |
445 | static int reload_cse_simplify_set PARAMS ((rtx, rtx)); |
446 | static int reload_cse_simplify_operands PARAMS ((rtx)); | |
770ae6cc RK |
447 | static void reload_combine PARAMS ((void)); |
448 | static void reload_combine_note_use PARAMS ((rtx *, rtx)); | |
449 | static void reload_combine_note_store PARAMS ((rtx, rtx, void *)); | |
450 | static void reload_cse_move2add PARAMS ((rtx)); | |
451 | static void move2add_note_store PARAMS ((rtx, rtx, void *)); | |
2dfa9a87 | 452 | #ifdef AUTO_INC_DEC |
770ae6cc | 453 | static void add_auto_inc_notes PARAMS ((rtx, rtx)); |
2dfa9a87 | 454 | #endif |
94bd63e5 | 455 | static void copy_eh_notes PARAMS ((rtx, rtx)); |
61f5625b | 456 | static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode, |
770ae6cc | 457 | HOST_WIDE_INT)); |
cdadb1dd KG |
458 | static void failed_reload PARAMS ((rtx, int)); |
459 | static int set_reload_reg PARAMS ((int, int)); | |
e77d72cb KG |
460 | static void reload_cse_delete_noop_set PARAMS ((rtx, rtx)); |
461 | static void reload_cse_simplify PARAMS ((rtx)); | |
f1330226 | 462 | static void fixup_abnormal_edges PARAMS ((void)); |
e04ca094 | 463 | extern void dump_needs PARAMS ((struct insn_chain *)); |
32131a9c | 464 | \f |
546b63fb RK |
465 | /* Initialize the reload pass once per compilation. */ |
466 | ||
32131a9c RK |
467 | void |
468 | init_reload () | |
469 | { | |
470 | register int i; | |
471 | ||
472 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
473 | Set spill_indirect_levels to the number of levels such addressing is | |
474 | permitted, zero if it is not permitted at all. */ | |
475 | ||
476 | register rtx tem | |
38a448ca RH |
477 | = gen_rtx_MEM (Pmode, |
478 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
479 | gen_rtx_REG (Pmode, |
480 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 481 | GEN_INT (4))); |
32131a9c RK |
482 | spill_indirect_levels = 0; |
483 | ||
484 | while (memory_address_p (QImode, tem)) | |
485 | { | |
486 | spill_indirect_levels++; | |
38a448ca | 487 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
488 | } |
489 | ||
490 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
491 | ||
38a448ca | 492 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
493 | indirect_symref_ok = memory_address_p (QImode, tem); |
494 | ||
495 | /* See if reg+reg is a valid (and offsettable) address. */ | |
496 | ||
65701fd2 | 497 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 498 | { |
38a448ca RH |
499 | tem = gen_rtx_PLUS (Pmode, |
500 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
501 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 502 | |
57caa638 RS |
503 | /* This way, we make sure that reg+reg is an offsettable address. */ |
504 | tem = plus_constant (tem, 4); | |
505 | ||
506 | if (memory_address_p (QImode, tem)) | |
507 | { | |
508 | double_reg_address_ok = 1; | |
509 | break; | |
510 | } | |
511 | } | |
32131a9c | 512 | |
0f41302f | 513 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 514 | gcc_obstack_init (&reload_obstack); |
cad6f7d0 | 515 | reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
516 | |
517 | INIT_REG_SET (&spilled_pseudos); | |
518 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
519 | } |
520 | ||
cad6f7d0 BS |
521 | /* List of insn chains that are currently unused. */ |
522 | static struct insn_chain *unused_insn_chains = 0; | |
523 | ||
524 | /* Allocate an empty insn_chain structure. */ | |
525 | struct insn_chain * | |
526 | new_insn_chain () | |
527 | { | |
528 | struct insn_chain *c; | |
529 | ||
530 | if (unused_insn_chains == 0) | |
531 | { | |
8db99db2 KG |
532 | c = (struct insn_chain *) |
533 | obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); | |
239a0f5b BS |
534 | INIT_REG_SET (&c->live_throughout); |
535 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
536 | } |
537 | else | |
538 | { | |
539 | c = unused_insn_chains; | |
540 | unused_insn_chains = c->next; | |
541 | } | |
542 | c->is_caller_save_insn = 0; | |
03acd8f8 | 543 | c->need_operand_change = 0; |
cad6f7d0 BS |
544 | c->need_reload = 0; |
545 | c->need_elim = 0; | |
546 | return c; | |
547 | } | |
548 | ||
7609e720 BS |
549 | /* Small utility function to set all regs in hard reg set TO which are |
550 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 551 | |
7609e720 BS |
552 | void |
553 | compute_use_by_pseudos (to, from) | |
554 | HARD_REG_SET *to; | |
555 | regset from; | |
556 | { | |
770ae6cc RK |
557 | unsigned int regno; |
558 | ||
7609e720 BS |
559 | EXECUTE_IF_SET_IN_REG_SET |
560 | (from, FIRST_PSEUDO_REGISTER, regno, | |
561 | { | |
562 | int r = reg_renumber[regno]; | |
563 | int nregs; | |
770ae6cc | 564 | |
7609e720 | 565 | if (r < 0) |
404d95c4 R |
566 | { |
567 | /* reload_combine uses the information from | |
e881bb1b RH |
568 | BASIC_BLOCK->global_live_at_start, which might still |
569 | contain registers that have not actually been allocated | |
570 | since they have an equivalence. */ | |
404d95c4 R |
571 | if (! reload_completed) |
572 | abort (); | |
573 | } | |
574 | else | |
575 | { | |
576 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); | |
577 | while (nregs-- > 0) | |
578 | SET_HARD_REG_BIT (*to, r + nregs); | |
579 | } | |
7609e720 BS |
580 | }); |
581 | } | |
f474c6f8 AO |
582 | |
583 | /* Replace all pseudos found in LOC with their corresponding | |
584 | equivalences. */ | |
585 | ||
586 | static void | |
587 | replace_pseudos_in_call_usage (loc, mem_mode, usage) | |
588 | rtx *loc; | |
589 | enum machine_mode mem_mode; | |
590 | rtx usage; | |
591 | { | |
592 | rtx x = *loc; | |
593 | enum rtx_code code; | |
594 | const char *fmt; | |
595 | int i, j; | |
596 | ||
597 | if (! x) | |
598 | return; | |
174fa2c4 | 599 | |
f474c6f8 AO |
600 | code = GET_CODE (x); |
601 | if (code == REG) | |
602 | { | |
ae0ed63a | 603 | unsigned int regno = REGNO (x); |
086fef9e AO |
604 | |
605 | if (regno < FIRST_PSEUDO_REGISTER) | |
f474c6f8 AO |
606 | return; |
607 | ||
608 | x = eliminate_regs (x, mem_mode, usage); | |
609 | if (x != *loc) | |
610 | { | |
611 | *loc = x; | |
612 | replace_pseudos_in_call_usage (loc, mem_mode, usage); | |
613 | return; | |
614 | } | |
615 | ||
086fef9e AO |
616 | if (reg_equiv_constant[regno]) |
617 | *loc = reg_equiv_constant[regno]; | |
618 | else if (reg_equiv_mem[regno]) | |
619 | *loc = reg_equiv_mem[regno]; | |
620 | else if (reg_equiv_address[regno]) | |
621 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
622 | else if (GET_CODE (regno_reg_rtx[regno]) != REG | |
623 | || REGNO (regno_reg_rtx[regno]) != regno) | |
624 | *loc = regno_reg_rtx[regno]; | |
f474c6f8 AO |
625 | else |
626 | abort (); | |
627 | ||
628 | return; | |
629 | } | |
630 | else if (code == MEM) | |
631 | { | |
632 | replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage); | |
633 | return; | |
634 | } | |
174fa2c4 | 635 | |
f474c6f8 AO |
636 | /* Process each of our operands recursively. */ |
637 | fmt = GET_RTX_FORMAT (code); | |
638 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
639 | if (*fmt == 'e') | |
640 | replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage); | |
641 | else if (*fmt == 'E') | |
642 | for (j = 0; j < XVECLEN (x, i); j++) | |
643 | replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage); | |
644 | } | |
645 | ||
03acd8f8 | 646 | \f |
1e5bd841 BS |
647 | /* Global variables used by reload and its subroutines. */ |
648 | ||
1e5bd841 BS |
649 | /* Set during calculate_needs if an insn needs register elimination. */ |
650 | static int something_needs_elimination; | |
cb2afeb3 R |
651 | /* Set during calculate_needs if an insn needs an operand changed. */ |
652 | int something_needs_operands_changed; | |
1e5bd841 | 653 | |
1e5bd841 BS |
654 | /* Nonzero means we couldn't get enough spill regs. */ |
655 | static int failure; | |
656 | ||
546b63fb | 657 | /* Main entry point for the reload pass. |
32131a9c RK |
658 | |
659 | FIRST is the first insn of the function being compiled. | |
660 | ||
661 | GLOBAL nonzero means we were called from global_alloc | |
662 | and should attempt to reallocate any pseudoregs that we | |
663 | displace from hard regs we will use for reloads. | |
664 | If GLOBAL is zero, we do not have enough information to do that, | |
665 | so any pseudo reg that is spilled must go to the stack. | |
666 | ||
5352b11a RS |
667 | Return value is nonzero if reload failed |
668 | and we must not do any more for this function. */ | |
669 | ||
670 | int | |
e04ca094 | 671 | reload (first, global) |
32131a9c RK |
672 | rtx first; |
673 | int global; | |
32131a9c | 674 | { |
03acd8f8 | 675 | register int i; |
32131a9c RK |
676 | register rtx insn; |
677 | register struct elim_table *ep; | |
678 | ||
a68d4b75 BK |
679 | /* The two pointers used to track the true location of the memory used |
680 | for label offsets. */ | |
9714cf43 | 681 | char *real_known_ptr = NULL; |
a68d4b75 BK |
682 | int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; |
683 | ||
32131a9c RK |
684 | /* Make sure even insns with volatile mem refs are recognizable. */ |
685 | init_recog (); | |
686 | ||
1e5bd841 BS |
687 | failure = 0; |
688 | ||
cad6f7d0 BS |
689 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
690 | ||
437a710d BS |
691 | /* Make sure that the last insn in the chain |
692 | is not something that needs reloading. */ | |
6496a589 | 693 | emit_note (NULL, NOTE_INSN_DELETED); |
437a710d | 694 | |
32131a9c RK |
695 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
696 | reload_first_uid = get_max_uid (); | |
697 | ||
0dadecf6 RK |
698 | #ifdef SECONDARY_MEMORY_NEEDED |
699 | /* Initialize the secondary memory table. */ | |
700 | clear_secondary_mem (); | |
701 | #endif | |
702 | ||
32131a9c | 703 | /* We don't have a stack slot for any spill reg yet. */ |
961192e1 JM |
704 | memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot); |
705 | memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 706 | |
a8efe40d RK |
707 | /* Initialize the save area information for caller-save, in case some |
708 | are needed. */ | |
709 | init_save_areas (); | |
a8fdc208 | 710 | |
32131a9c RK |
711 | /* Compute which hard registers are now in use |
712 | as homes for pseudo registers. | |
713 | This is done here rather than (eg) in global_alloc | |
714 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
715 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
716 | mark_home_live (i); | |
717 | ||
8dddd002 RK |
718 | /* A function that receives a nonlocal goto must save all call-saved |
719 | registers. */ | |
720 | if (current_function_has_nonlocal_label) | |
721 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2a3e384f RH |
722 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
723 | regs_ever_live[i] = 1; | |
8dddd002 | 724 | |
32131a9c RK |
725 | /* Find all the pseudo registers that didn't get hard regs |
726 | but do have known equivalent constants or memory slots. | |
727 | These include parameters (known equivalent to parameter slots) | |
728 | and cse'd or loop-moved constant memory addresses. | |
729 | ||
730 | Record constant equivalents in reg_equiv_constant | |
731 | so they will be substituted by find_reloads. | |
732 | Record memory equivalents in reg_mem_equiv so they can | |
733 | be substituted eventually by altering the REG-rtx's. */ | |
734 | ||
ad85216e | 735 | reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
ad85216e KG |
736 | reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
737 | reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
738 | reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
f9e158c3 | 739 | reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int)); |
ad85216e | 740 | reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short)); |
4e135bdd | 741 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
03acd8f8 BS |
742 | pseudo_forbidden_regs |
743 | = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); | |
744 | pseudo_previous_regs | |
ad85216e | 745 | = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET)); |
32131a9c | 746 | |
03acd8f8 | 747 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 748 | |
32131a9c | 749 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. |
56f58d3a RK |
750 | Also find all paradoxical subregs and find largest such for each pseudo. |
751 | On machines with small register classes, record hard registers that | |
05d10675 | 752 | are used for user variables. These can never be used for spills. |
570a98eb | 753 | Also look for a "constant" REG_SETJMP. This means that all |
b453cb0b | 754 | caller-saved registers must be marked live. */ |
32131a9c | 755 | |
2b49ee39 | 756 | num_eliminable_invariants = 0; |
32131a9c RK |
757 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
758 | { | |
759 | rtx set = single_set (insn); | |
760 | ||
3d17d93d AO |
761 | /* We may introduce USEs that we want to remove at the end, so |
762 | we'll mark them with QImode. Make sure there are no | |
763 | previously-marked insns left by say regmove. */ | |
764 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
765 | && GET_MODE (insn) != VOIDmode) | |
766 | PUT_MODE (insn, VOIDmode); | |
767 | ||
19652adf ZW |
768 | if (GET_CODE (insn) == CALL_INSN |
769 | && find_reg_note (insn, REG_SETJMP, NULL)) | |
b453cb0b RK |
770 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
771 | if (! call_used_regs[i]) | |
772 | regs_ever_live[i] = 1; | |
773 | ||
32131a9c RK |
774 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) |
775 | { | |
fb3821f7 | 776 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
777 | if (note |
778 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2b49ee39 R |
779 | && (! function_invariant_p (XEXP (note, 0)) |
780 | || ! flag_pic | |
a8efe40d RK |
781 | || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) |
782 | #endif | |
783 | ) | |
32131a9c RK |
784 | { |
785 | rtx x = XEXP (note, 0); | |
786 | i = REGNO (SET_DEST (set)); | |
787 | if (i > LAST_VIRTUAL_REGISTER) | |
788 | { | |
789 | if (GET_CODE (x) == MEM) | |
956d6950 | 790 | { |
cf728d61 HPN |
791 | /* Always unshare the equivalence, so we can |
792 | substitute into this insn without touching the | |
2ba84f36 | 793 | equivalence. */ |
cf728d61 | 794 | reg_equiv_memory_loc[i] = copy_rtx (x); |
956d6950 | 795 | } |
2b49ee39 | 796 | else if (function_invariant_p (x)) |
32131a9c | 797 | { |
2b49ee39 R |
798 | if (GET_CODE (x) == PLUS) |
799 | { | |
800 | /* This is PLUS of frame pointer and a constant, | |
801 | and might be shared. Unshare it. */ | |
802 | reg_equiv_constant[i] = copy_rtx (x); | |
803 | num_eliminable_invariants++; | |
804 | } | |
805 | else if (x == frame_pointer_rtx | |
806 | || x == arg_pointer_rtx) | |
807 | { | |
808 | reg_equiv_constant[i] = x; | |
809 | num_eliminable_invariants++; | |
810 | } | |
811 | else if (LEGITIMATE_CONSTANT_P (x)) | |
32131a9c RK |
812 | reg_equiv_constant[i] = x; |
813 | else | |
814 | reg_equiv_memory_loc[i] | |
d445b551 | 815 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
816 | } |
817 | else | |
818 | continue; | |
819 | ||
820 | /* If this register is being made equivalent to a MEM | |
821 | and the MEM is not SET_SRC, the equivalencing insn | |
822 | is one with the MEM as a SET_DEST and it occurs later. | |
823 | So don't mark this insn now. */ | |
824 | if (GET_CODE (x) != MEM | |
825 | || rtx_equal_p (SET_SRC (set), x)) | |
135eb61c R |
826 | reg_equiv_init[i] |
827 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); | |
32131a9c RK |
828 | } |
829 | } | |
830 | } | |
831 | ||
832 | /* If this insn is setting a MEM from a register equivalent to it, | |
833 | this is the equivalencing insn. */ | |
834 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
835 | && GET_CODE (SET_SRC (set)) == REG | |
836 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
837 | && rtx_equal_p (SET_DEST (set), | |
838 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
135eb61c R |
839 | reg_equiv_init[REGNO (SET_SRC (set))] |
840 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
841 | reg_equiv_init[REGNO (SET_SRC (set))]); | |
32131a9c | 842 | |
2c3c49de | 843 | if (INSN_P (insn)) |
32131a9c RK |
844 | scan_paradoxical_subregs (PATTERN (insn)); |
845 | } | |
846 | ||
09dd1133 | 847 | init_elim_table (); |
32131a9c RK |
848 | |
849 | num_labels = max_label_num () - get_first_label_num (); | |
850 | ||
851 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
852 | /* We used to use alloca here, but the size of what it would try to |
853 | allocate would occasionally cause it to exceed the stack limit and | |
854 | cause a core dump. */ | |
855 | real_known_ptr = xmalloc (num_labels); | |
856 | real_at_ptr | |
32131a9c | 857 | = (int (*)[NUM_ELIMINABLE_REGS]) |
a68d4b75 | 858 | xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); |
32131a9c | 859 | |
a68d4b75 BK |
860 | offsets_known_at = real_known_ptr - get_first_label_num (); |
861 | offsets_at | |
862 | = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); | |
32131a9c RK |
863 | |
864 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
865 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
866 | Do not touch virtual registers. */ | |
867 | ||
868 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
869 | alter_reg (i, -1); | |
870 | ||
32131a9c RK |
871 | /* If we have some registers we think can be eliminated, scan all insns to |
872 | see if there is an insn that sets one of these registers to something | |
873 | other than itself plus a constant. If so, the register cannot be | |
874 | eliminated. Doing this scan here eliminates an extra pass through the | |
875 | main reload loop in the most common case where register elimination | |
876 | cannot be done. */ | |
877 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
878 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
879 | || GET_CODE (insn) == CALL_INSN) | |
84832317 | 880 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 881 | |
18a90182 BS |
882 | maybe_fix_stack_asms (); |
883 | ||
03acd8f8 BS |
884 | insns_need_reload = 0; |
885 | something_needs_elimination = 0; | |
05d10675 | 886 | |
4079cd63 JW |
887 | /* Initialize to -1, which means take the first spill register. */ |
888 | last_spill_reg = -1; | |
889 | ||
32131a9c | 890 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 891 | CLEAR_HARD_REG_SET (used_spill_regs); |
32131a9c RK |
892 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
893 | if (! ep->can_eliminate) | |
e04ca094 | 894 | spill_hard_reg (ep->from, 1); |
9ff3516a RK |
895 | |
896 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
897 | if (frame_pointer_needed) | |
e04ca094 | 898 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 899 | #endif |
e04ca094 | 900 | finish_spills (global); |
7609e720 | 901 | |
f1db3576 JL |
902 | /* From now on, we may need to generate moves differently. We may also |
903 | allow modifications of insns which cause them to not be recognized. | |
904 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
905 | reload_in_progress = 1; |
906 | ||
32131a9c RK |
907 | /* This loop scans the entire function each go-round |
908 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 909 | for (;;) |
32131a9c | 910 | { |
03acd8f8 BS |
911 | int something_changed; |
912 | int did_spill; | |
32131a9c | 913 | |
03acd8f8 | 914 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 915 | |
665792eb | 916 | /* Round size of stack frame to stack_alignment_needed. This must be done |
7657bf2f JW |
917 | here because the stack size may be a part of the offset computation |
918 | for register elimination, and there might have been new stack slots | |
919 | created in the last iteration of this loop. */ | |
665792eb JH |
920 | if (cfun->stack_alignment_needed) |
921 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
7657bf2f JW |
922 | |
923 | starting_frame_size = get_frame_size (); | |
924 | ||
09dd1133 | 925 | set_initial_elim_offsets (); |
1f3b1e1a | 926 | set_initial_label_offsets (); |
03acd8f8 | 927 | |
32131a9c RK |
928 | /* For each pseudo register that has an equivalent location defined, |
929 | try to eliminate any eliminable registers (such as the frame pointer) | |
930 | assuming initial offsets for the replacement register, which | |
931 | is the normal case. | |
932 | ||
933 | If the resulting location is directly addressable, substitute | |
934 | the MEM we just got directly for the old REG. | |
935 | ||
936 | If it is not addressable but is a constant or the sum of a hard reg | |
937 | and constant, it is probably not addressable because the constant is | |
938 | out of range, in that case record the address; we will generate | |
939 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
940 | needed. Similarly if it is a hard register, but one that is not |
941 | valid as an address register. | |
32131a9c RK |
942 | |
943 | If the location is not addressable, but does not have one of the | |
944 | above forms, assign a stack slot. We have to do this to avoid the | |
945 | potential of producing lots of reloads if, e.g., a location involves | |
946 | a pseudo that didn't get a hard register and has an equivalent memory | |
947 | location that also involves a pseudo that didn't get a hard register. | |
948 | ||
949 | Perhaps at some point we will improve reload_when_needed handling | |
950 | so this problem goes away. But that's very hairy. */ | |
951 | ||
952 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
953 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
954 | { | |
1914f5da | 955 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
956 | |
957 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
958 | XEXP (x, 0))) | |
959 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
960 | else if (CONSTANT_P (XEXP (x, 0)) | |
6491dbbb RK |
961 | || (GET_CODE (XEXP (x, 0)) == REG |
962 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
963 | || (GET_CODE (XEXP (x, 0)) == PLUS |
964 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
965 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
966 | < FIRST_PSEUDO_REGISTER) | |
967 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
968 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
969 | else | |
970 | { | |
971 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 972 | changed so we go back and recompute offsets for |
32131a9c RK |
973 | eliminable registers because the allocation of memory |
974 | below might change some offset. reg_equiv_{mem,address} | |
975 | will be set up for this pseudo on the next pass around | |
976 | the loop. */ | |
977 | reg_equiv_memory_loc[i] = 0; | |
978 | reg_equiv_init[i] = 0; | |
979 | alter_reg (i, -1); | |
32131a9c RK |
980 | } |
981 | } | |
a8fdc208 | 982 | |
437a710d BS |
983 | if (caller_save_needed) |
984 | setup_save_areas (); | |
985 | ||
03acd8f8 | 986 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 987 | if (starting_frame_size != get_frame_size ()) |
32131a9c RK |
988 | continue; |
989 | ||
437a710d | 990 | if (caller_save_needed) |
a8efe40d | 991 | { |
437a710d BS |
992 | save_call_clobbered_regs (); |
993 | /* That might have allocated new insn_chain structures. */ | |
994 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
a8efe40d RK |
995 | } |
996 | ||
03acd8f8 BS |
997 | calculate_needs_all_insns (global); |
998 | ||
f5d8c9f4 | 999 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
1000 | did_spill = 0; |
1001 | ||
1002 | something_changed = 0; | |
32131a9c | 1003 | |
0dadecf6 RK |
1004 | /* If we allocated any new memory locations, make another pass |
1005 | since it might have changed elimination offsets. */ | |
1006 | if (starting_frame_size != get_frame_size ()) | |
1007 | something_changed = 1; | |
1008 | ||
09dd1133 BS |
1009 | { |
1010 | HARD_REG_SET to_spill; | |
1011 | CLEAR_HARD_REG_SET (to_spill); | |
1012 | update_eliminables (&to_spill); | |
1013 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1014 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 1015 | { |
e04ca094 | 1016 | spill_hard_reg (i, 1); |
03acd8f8 | 1017 | did_spill = 1; |
8f5db3c1 JL |
1018 | |
1019 | /* Regardless of the state of spills, if we previously had | |
1020 | a register that we thought we could eliminate, but no can | |
1021 | not eliminate, we must run another pass. | |
1022 | ||
1023 | Consider pseudos which have an entry in reg_equiv_* which | |
1024 | reference an eliminable register. We must make another pass | |
1025 | to update reg_equiv_* so that we do not substitute in the | |
1026 | old value from when we thought the elimination could be | |
1027 | performed. */ | |
1028 | something_changed = 1; | |
32131a9c | 1029 | } |
09dd1133 | 1030 | } |
9ff3516a | 1031 | |
e04ca094 | 1032 | select_reload_regs (); |
e483bf9c BS |
1033 | if (failure) |
1034 | goto failed; | |
437a710d | 1035 | |
e483bf9c | 1036 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 1037 | something_changed |= finish_spills (global); |
7609e720 | 1038 | |
03acd8f8 BS |
1039 | if (! something_changed) |
1040 | break; | |
1041 | ||
1042 | if (caller_save_needed) | |
7609e720 | 1043 | delete_caller_save_insns (); |
f5d8c9f4 BS |
1044 | |
1045 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
1046 | } |
1047 | ||
1048 | /* If global-alloc was run, notify it of any register eliminations we have | |
1049 | done. */ | |
1050 | if (global) | |
1051 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1052 | if (ep->can_eliminate) | |
1053 | mark_elimination (ep->from, ep->to); | |
1054 | ||
32131a9c RK |
1055 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1056 | If that insn didn't set the register (i.e., it copied the register to | |
1057 | memory), just delete that insn instead of the equivalencing insn plus | |
1058 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 1059 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
1060 | there and that is incorrect. */ |
1061 | ||
1062 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
1063 | { |
1064 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1065 | { | |
1066 | rtx list; | |
1067 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1068 | { | |
1069 | rtx equiv_insn = XEXP (list, 0); | |
1070 | if (GET_CODE (equiv_insn) == NOTE) | |
1071 | continue; | |
1072 | if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
1073 | delete_dead_insn (equiv_insn); | |
1074 | else | |
1075 | { | |
1076 | PUT_CODE (equiv_insn, NOTE); | |
1077 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1078 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1079 | } | |
1080 | } | |
1081 | } | |
1082 | } | |
32131a9c RK |
1083 | |
1084 | /* Use the reload registers where necessary | |
1085 | by generating move instructions to move the must-be-register | |
1086 | values into or out of the reload registers. */ | |
1087 | ||
03acd8f8 BS |
1088 | if (insns_need_reload != 0 || something_needs_elimination |
1089 | || something_needs_operands_changed) | |
c47f5ea5 | 1090 | { |
102870fb | 1091 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1092 | |
e04ca094 | 1093 | reload_as_needed (global); |
c47f5ea5 BS |
1094 | |
1095 | if (old_frame_size != get_frame_size ()) | |
1096 | abort (); | |
1097 | ||
1098 | if (num_eliminable) | |
1099 | verify_initial_elim_offsets (); | |
1100 | } | |
32131a9c | 1101 | |
2a1f8b6b | 1102 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1103 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1104 | virtue of being in a pseudo, that pseudo will be marked live |
1105 | and hence the frame pointer will be known to be live via that | |
1106 | pseudo. */ | |
1107 | ||
1108 | if (! frame_pointer_needed) | |
1109 | for (i = 0; i < n_basic_blocks; i++) | |
e881bb1b | 1110 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start, |
8e08106d | 1111 | HARD_FRAME_POINTER_REGNUM); |
2a1f8b6b | 1112 | |
5352b11a RS |
1113 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1114 | and we decide not to abort about it. */ | |
1115 | failed: | |
1116 | ||
f5d8c9f4 | 1117 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1118 | reload_in_progress = 0; |
1119 | ||
32131a9c RK |
1120 | /* Now eliminate all pseudo regs by modifying them into |
1121 | their equivalent memory references. | |
1122 | The REG-rtx's for the pseudos are modified in place, | |
1123 | so all insns that used to refer to them now refer to memory. | |
1124 | ||
1125 | For a reg that has a reg_equiv_address, all those insns | |
1126 | were changed by reloading so that no insns refer to it any longer; | |
1127 | but the DECL_RTL of a variable decl may refer to it, | |
1128 | and if so this causes the debugging info to mention the variable. */ | |
1129 | ||
1130 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1131 | { | |
1132 | rtx addr = 0; | |
9ec36da5 JL |
1133 | |
1134 | if (reg_equiv_mem[i]) | |
1135 | addr = XEXP (reg_equiv_mem[i], 0); | |
1136 | ||
32131a9c RK |
1137 | if (reg_equiv_address[i]) |
1138 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1139 | |
32131a9c RK |
1140 | if (addr) |
1141 | { | |
1142 | if (reg_renumber[i] < 0) | |
1143 | { | |
1144 | rtx reg = regno_reg_rtx[i]; | |
173b24b9 | 1145 | |
ef178af3 | 1146 | PUT_CODE (reg, MEM); |
32131a9c RK |
1147 | XEXP (reg, 0) = addr; |
1148 | REG_USERVAR_P (reg) = 0; | |
173b24b9 RK |
1149 | if (reg_equiv_memory_loc[i]) |
1150 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1151 | else | |
1152 | { | |
1153 | RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg) | |
1154 | = MEM_SCALAR_P (reg) = 0; | |
1155 | MEM_ATTRS (reg) = 0; | |
1156 | } | |
32131a9c RK |
1157 | } |
1158 | else if (reg_equiv_mem[i]) | |
1159 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1160 | } | |
1161 | } | |
1162 | ||
2ae74651 JL |
1163 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1164 | below will re-recognize each insn and reload may have generated insns | |
1165 | which are only valid during and after reload. */ | |
1166 | reload_completed = 1; | |
1167 | ||
bd695e1e RH |
1168 | /* Make a pass over all the insns and delete all USEs which we inserted |
1169 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
1170 | notes. Delete all CLOBBER insns that don't refer to the return value | |
1171 | and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and | |
1172 | REG_LIBCALL notes since they are no longer useful or accurate. Strip | |
1173 | and regenerate REG_INC notes that may have been moved around. */ | |
32131a9c RK |
1174 | |
1175 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1176 | if (INSN_P (insn)) |
32131a9c | 1177 | { |
6764d250 | 1178 | rtx *pnote; |
32131a9c | 1179 | |
f474c6f8 AO |
1180 | if (GET_CODE (insn) == CALL_INSN) |
1181 | replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn), | |
1182 | VOIDmode, | |
1183 | CALL_INSN_FUNCTION_USAGE (insn)); | |
1184 | ||
0304f787 | 1185 | if ((GET_CODE (PATTERN (insn)) == USE |
3d17d93d AO |
1186 | /* We mark with QImode USEs introduced by reload itself. */ |
1187 | && (GET_MODE (insn) == QImode | |
1188 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
bd695e1e RH |
1189 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
1190 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG | |
1191 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
b60a8416 | 1192 | { |
e5eac8ef | 1193 | delete_insn (insn); |
b60a8416 R |
1194 | continue; |
1195 | } | |
6764d250 BS |
1196 | |
1197 | pnote = ®_NOTES (insn); | |
1198 | while (*pnote != 0) | |
32131a9c | 1199 | { |
6764d250 | 1200 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1201 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1202 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 NC |
1203 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
1204 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) | |
6764d250 BS |
1205 | *pnote = XEXP (*pnote, 1); |
1206 | else | |
1207 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1208 | } |
0304f787 | 1209 | |
2dfa9a87 MH |
1210 | #ifdef AUTO_INC_DEC |
1211 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1212 | #endif | |
1213 | ||
0304f787 JL |
1214 | /* And simplify (subreg (reg)) if it appears as an operand. */ |
1215 | cleanup_subreg_operands (insn); | |
b60a8416 | 1216 | } |
32131a9c | 1217 | |
ab87f8c8 JL |
1218 | /* If we are doing stack checking, give a warning if this function's |
1219 | frame size is larger than we expect. */ | |
1220 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1221 | { | |
1222 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1223 | static int verbose_warned = 0; |
1224 | ||
ab87f8c8 JL |
1225 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1226 | if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) | |
1227 | size += UNITS_PER_WORD; | |
1228 | ||
1229 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1230 | { |
ab87f8c8 JL |
1231 | warning ("frame size too large for reliable stack checking"); |
1232 | if (! verbose_warned) | |
1233 | { | |
1234 | warning ("try reducing the number of local variables"); | |
1235 | verbose_warned = 1; | |
1236 | } | |
1237 | } | |
1238 | } | |
1239 | ||
32131a9c | 1240 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1241 | if (reg_equiv_constant) |
1242 | free (reg_equiv_constant); | |
32131a9c | 1243 | reg_equiv_constant = 0; |
58d9f9d9 JL |
1244 | if (reg_equiv_memory_loc) |
1245 | free (reg_equiv_memory_loc); | |
32131a9c | 1246 | reg_equiv_memory_loc = 0; |
5352b11a | 1247 | |
a68d4b75 BK |
1248 | if (real_known_ptr) |
1249 | free (real_known_ptr); | |
1250 | if (real_at_ptr) | |
1251 | free (real_at_ptr); | |
1252 | ||
56a65848 DB |
1253 | free (reg_equiv_mem); |
1254 | free (reg_equiv_init); | |
1255 | free (reg_equiv_address); | |
1256 | free (reg_max_ref_width); | |
03acd8f8 BS |
1257 | free (reg_old_renumber); |
1258 | free (pseudo_previous_regs); | |
1259 | free (pseudo_forbidden_regs); | |
56a65848 | 1260 | |
8b4f9969 JW |
1261 | CLEAR_HARD_REG_SET (used_spill_regs); |
1262 | for (i = 0; i < n_spills; i++) | |
1263 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1264 | ||
7609e720 BS |
1265 | /* Free all the insn_chain structures at once. */ |
1266 | obstack_free (&reload_obstack, reload_startobj); | |
1267 | unused_insn_chains = 0; | |
f1330226 | 1268 | fixup_abnormal_edges (); |
7609e720 | 1269 | |
5352b11a | 1270 | return failure; |
32131a9c | 1271 | } |
1e5bd841 | 1272 | |
18a90182 BS |
1273 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1274 | write incorrect clobbers in asm statements. These clobbers must not | |
1275 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1276 | fatal_insn later. We clear the corresponding regnos in the live | |
1277 | register sets to avoid this. | |
1278 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1279 | |
18a90182 BS |
1280 | static void |
1281 | maybe_fix_stack_asms () | |
1282 | { | |
1283 | #ifdef STACK_REGS | |
392dccb7 | 1284 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1285 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1286 | struct insn_chain *chain; | |
1287 | ||
1288 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1289 | { | |
1290 | int i, noperands; | |
1291 | HARD_REG_SET clobbered, allowed; | |
1292 | rtx pat; | |
1293 | ||
2c3c49de | 1294 | if (! INSN_P (chain->insn) |
18a90182 BS |
1295 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1296 | continue; | |
1297 | pat = PATTERN (chain->insn); | |
1298 | if (GET_CODE (pat) != PARALLEL) | |
1299 | continue; | |
1300 | ||
1301 | CLEAR_HARD_REG_SET (clobbered); | |
1302 | CLEAR_HARD_REG_SET (allowed); | |
1303 | ||
1304 | /* First, make a mask of all stack regs that are clobbered. */ | |
1305 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1306 | { | |
1307 | rtx t = XVECEXP (pat, 0, i); | |
1308 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1309 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1310 | } | |
1311 | ||
1312 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1313 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
18a90182 BS |
1314 | constraints, operand_mode); |
1315 | ||
1316 | /* For every operand, see what registers are allowed. */ | |
1317 | for (i = 0; i < noperands; i++) | |
1318 | { | |
6b9c6f4f | 1319 | const char *p = constraints[i]; |
18a90182 BS |
1320 | /* For every alternative, we compute the class of registers allowed |
1321 | for reloading in CLS, and merge its contents into the reg set | |
1322 | ALLOWED. */ | |
1323 | int cls = (int) NO_REGS; | |
1324 | ||
1325 | for (;;) | |
1326 | { | |
1327 | char c = *p++; | |
1328 | ||
1329 | if (c == '\0' || c == ',' || c == '#') | |
1330 | { | |
1331 | /* End of one alternative - mark the regs in the current | |
1332 | class, and reset the class. */ | |
1333 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1334 | cls = NO_REGS; | |
1335 | if (c == '#') | |
1336 | do { | |
1337 | c = *p++; | |
1338 | } while (c != '\0' && c != ','); | |
1339 | if (c == '\0') | |
1340 | break; | |
1341 | continue; | |
1342 | } | |
1343 | ||
1344 | switch (c) | |
1345 | { | |
1346 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1347 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1348 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1349 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1350 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1351 | case 'P': | |
18a90182 BS |
1352 | break; |
1353 | ||
1354 | case 'p': | |
1355 | cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS]; | |
1356 | break; | |
1357 | ||
1358 | case 'g': | |
1359 | case 'r': | |
1360 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1361 | break; | |
1362 | ||
1363 | default: | |
1364 | cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)]; | |
05d10675 | 1365 | |
18a90182 BS |
1366 | } |
1367 | } | |
1368 | } | |
1369 | /* Those of the registers which are clobbered, but allowed by the | |
1370 | constraints, must be usable as reload registers. So clear them | |
1371 | out of the life information. */ | |
1372 | AND_HARD_REG_SET (allowed, clobbered); | |
1373 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1374 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1375 | { | |
239a0f5b BS |
1376 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1377 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1378 | } |
1379 | } | |
1380 | ||
1381 | #endif | |
1382 | } | |
03acd8f8 | 1383 | \f |
f5d8c9f4 BS |
1384 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1385 | of CHAIN. */ | |
1386 | static void | |
1387 | copy_reloads (chain) | |
1388 | struct insn_chain *chain; | |
1389 | { | |
1390 | chain->n_reloads = n_reloads; | |
1391 | chain->rld | |
1392 | = (struct reload *) obstack_alloc (&reload_obstack, | |
1393 | n_reloads * sizeof (struct reload)); | |
1394 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); | |
1395 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
1396 | } | |
1397 | ||
03acd8f8 BS |
1398 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1399 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1400 | set something_needs_elimination as appropriate. */ | |
1401 | static void | |
7609e720 | 1402 | calculate_needs_all_insns (global) |
1e5bd841 BS |
1403 | int global; |
1404 | { | |
7609e720 | 1405 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1406 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1407 | |
03acd8f8 BS |
1408 | something_needs_elimination = 0; |
1409 | ||
f5d8c9f4 | 1410 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
462561b7 | 1411 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1412 | { |
67e61fe7 | 1413 | rtx insn = chain->insn; |
03acd8f8 | 1414 | |
462561b7 JJ |
1415 | next = chain->next; |
1416 | ||
f5d8c9f4 BS |
1417 | /* Clear out the shortcuts. */ |
1418 | chain->n_reloads = 0; | |
67e61fe7 BS |
1419 | chain->need_elim = 0; |
1420 | chain->need_reload = 0; | |
1421 | chain->need_operand_change = 0; | |
1e5bd841 | 1422 | |
03acd8f8 BS |
1423 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1424 | include REG_LABEL), we need to see what effects this has on the | |
1425 | known offsets at labels. */ | |
1e5bd841 BS |
1426 | |
1427 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
2c3c49de | 1428 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1429 | set_label_offsets (insn, insn, 0); |
1430 | ||
2c3c49de | 1431 | if (INSN_P (insn)) |
1e5bd841 BS |
1432 | { |
1433 | rtx old_body = PATTERN (insn); | |
1434 | int old_code = INSN_CODE (insn); | |
1435 | rtx old_notes = REG_NOTES (insn); | |
1436 | int did_elimination = 0; | |
cb2afeb3 | 1437 | int operands_changed = 0; |
2b49ee39 R |
1438 | rtx set = single_set (insn); |
1439 | ||
1440 | /* Skip insns that only set an equivalence. */ | |
1441 | if (set && GET_CODE (SET_DEST (set)) == REG | |
1442 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1443 | && reg_equiv_constant[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1444 | continue; |
1e5bd841 | 1445 | |
1e5bd841 | 1446 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1447 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1448 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1449 | ||
1450 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1451 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1452 | global, spill_reg_order); | |
1453 | ||
1454 | /* If a no-op set needs more than one reload, this is likely | |
1455 | to be something that needs input address reloads. We | |
1456 | can't get rid of this cleanly later, and it is of no use | |
1457 | anyway, so discard it now. | |
1458 | We only do this when expensive_optimizations is enabled, | |
1459 | since this complements reload inheritance / output | |
1460 | reload deletion, and it can make debugging harder. */ | |
1461 | if (flag_expensive_optimizations && n_reloads > 1) | |
1462 | { | |
1463 | rtx set = single_set (insn); | |
1464 | if (set | |
1465 | && SET_SRC (set) == SET_DEST (set) | |
1466 | && GET_CODE (SET_SRC (set)) == REG | |
1467 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1468 | { | |
ca6c03ca | 1469 | delete_insn (insn); |
462561b7 JJ |
1470 | /* Delete it from the reload chain */ |
1471 | if (chain->prev) | |
1472 | chain->prev->next = next; | |
1473 | else | |
1474 | reload_insn_chain = next; | |
1475 | if (next) | |
1476 | next->prev = chain->prev; | |
1477 | chain->next = unused_insn_chains; | |
1478 | unused_insn_chains = chain; | |
cb2afeb3 R |
1479 | continue; |
1480 | } | |
1481 | } | |
1482 | if (num_eliminable) | |
1483 | update_eliminable_offsets (); | |
1e5bd841 BS |
1484 | |
1485 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1486 | register eliminations. */ |
1487 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1488 | chain->need_reload = n_reloads > 0; |
1489 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1490 | |
1491 | /* Discard any register replacements done. */ | |
1492 | if (did_elimination) | |
1493 | { | |
f5d8c9f4 | 1494 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1495 | PATTERN (insn) = old_body; |
1496 | INSN_CODE (insn) = old_code; | |
1497 | REG_NOTES (insn) = old_notes; | |
1498 | something_needs_elimination = 1; | |
1499 | } | |
1500 | ||
cb2afeb3 R |
1501 | something_needs_operands_changed |= operands_changed; |
1502 | ||
437a710d | 1503 | if (n_reloads != 0) |
7609e720 | 1504 | { |
f5d8c9f4 | 1505 | copy_reloads (chain); |
7609e720 BS |
1506 | *pprev_reload = chain; |
1507 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1508 | } |
1e5bd841 | 1509 | } |
1e5bd841 | 1510 | } |
7609e720 | 1511 | *pprev_reload = 0; |
1e5bd841 | 1512 | } |
f5d8c9f4 BS |
1513 | \f |
1514 | /* Comparison function for qsort to decide which of two reloads | |
1515 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1516 | |
f5d8c9f4 BS |
1517 | static int |
1518 | reload_reg_class_lower (r1p, r2p) | |
1519 | const PTR r1p; | |
1520 | const PTR r2p; | |
1e5bd841 | 1521 | { |
1d7254c5 | 1522 | register int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
f5d8c9f4 | 1523 | register int t; |
1e5bd841 | 1524 | |
f5d8c9f4 BS |
1525 | /* Consider required reloads before optional ones. */ |
1526 | t = rld[r1].optional - rld[r2].optional; | |
1527 | if (t != 0) | |
1528 | return t; | |
1e5bd841 | 1529 | |
f5d8c9f4 BS |
1530 | /* Count all solitary classes before non-solitary ones. */ |
1531 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1532 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1533 | if (t != 0) | |
1534 | return t; | |
1e5bd841 | 1535 | |
f5d8c9f4 BS |
1536 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1537 | t = rld[r2].nregs - rld[r1].nregs; | |
1538 | if (t != 0) | |
1539 | return t; | |
1e5bd841 | 1540 | |
f5d8c9f4 BS |
1541 | /* Consider reloads in order of increasing reg-class number. */ |
1542 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1543 | if (t != 0) | |
1544 | return t; | |
1e5bd841 | 1545 | |
f5d8c9f4 BS |
1546 | /* If reloads are equally urgent, sort by reload number, |
1547 | so that the results of qsort leave nothing to chance. */ | |
1548 | return r1 - r2; | |
1549 | } | |
1550 | \f | |
1551 | /* The cost of spilling each hard reg. */ | |
1552 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1553 | |
f5d8c9f4 BS |
1554 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1555 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1556 | only the first hard reg for a multi-reg pseudo. */ | |
1557 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1558 | |
f5d8c9f4 | 1559 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1560 | |
f5d8c9f4 BS |
1561 | static void |
1562 | count_pseudo (reg) | |
1563 | int reg; | |
1564 | { | |
b2aec5c0 | 1565 | int freq = REG_FREQ (reg); |
f5d8c9f4 BS |
1566 | int r = reg_renumber[reg]; |
1567 | int nregs; | |
1e5bd841 | 1568 | |
f5d8c9f4 BS |
1569 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1570 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1571 | return; | |
1e5bd841 | 1572 | |
f5d8c9f4 | 1573 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1574 | |
f5d8c9f4 BS |
1575 | if (r < 0) |
1576 | abort (); | |
1d7254c5 | 1577 | |
b2aec5c0 | 1578 | spill_add_cost[r] += freq; |
1e5bd841 | 1579 | |
f5d8c9f4 BS |
1580 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); |
1581 | while (nregs-- > 0) | |
b2aec5c0 | 1582 | spill_cost[r + nregs] += freq; |
f5d8c9f4 | 1583 | } |
1e5bd841 | 1584 | |
f5d8c9f4 BS |
1585 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1586 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1587 | |
f5d8c9f4 BS |
1588 | static void |
1589 | order_regs_for_reload (chain) | |
1590 | struct insn_chain *chain; | |
1591 | { | |
fbd40359 | 1592 | int i; |
efc9bd41 RK |
1593 | HARD_REG_SET used_by_pseudos; |
1594 | HARD_REG_SET used_by_pseudos2; | |
1e5bd841 | 1595 | |
efc9bd41 | 1596 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1597 | |
f5d8c9f4 BS |
1598 | memset (spill_cost, 0, sizeof spill_cost); |
1599 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1600 | |
f5d8c9f4 | 1601 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1602 | and then order them by decreasing use. First exclude hard registers |
1603 | that are live in or across this insn. */ | |
1604 | ||
1605 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1606 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1607 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1608 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1609 | |
f5d8c9f4 BS |
1610 | /* Now find out which pseudos are allocated to it, and update |
1611 | hard_reg_n_uses. */ | |
1612 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1613 | |
f5d8c9f4 | 1614 | EXECUTE_IF_SET_IN_REG_SET |
fbd40359 | 1615 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1616 | { |
fbd40359 | 1617 | count_pseudo (i); |
f5d8c9f4 BS |
1618 | }); |
1619 | EXECUTE_IF_SET_IN_REG_SET | |
fbd40359 | 1620 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1621 | { |
fbd40359 | 1622 | count_pseudo (i); |
f5d8c9f4 BS |
1623 | }); |
1624 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1625 | } |
03acd8f8 | 1626 | \f |
f5d8c9f4 BS |
1627 | /* Vector of reload-numbers showing the order in which the reloads should |
1628 | be processed. */ | |
1629 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1630 | |
f5d8c9f4 BS |
1631 | /* This is used to keep track of the spill regs used in one insn. */ |
1632 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1633 | |
f5d8c9f4 BS |
1634 | /* We decided to spill hard register SPILLED, which has a size of |
1635 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1636 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1637 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1638 | |
03acd8f8 | 1639 | static void |
f5d8c9f4 BS |
1640 | count_spilled_pseudo (spilled, spilled_nregs, reg) |
1641 | int spilled, spilled_nregs, reg; | |
1e5bd841 | 1642 | { |
f5d8c9f4 BS |
1643 | int r = reg_renumber[reg]; |
1644 | int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); | |
1e5bd841 | 1645 | |
f5d8c9f4 BS |
1646 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1647 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1648 | return; | |
1e5bd841 | 1649 | |
f5d8c9f4 | 1650 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1651 | |
b2aec5c0 | 1652 | spill_add_cost[r] -= REG_FREQ (reg); |
f5d8c9f4 | 1653 | while (nregs-- > 0) |
b2aec5c0 | 1654 | spill_cost[r + nregs] -= REG_FREQ (reg); |
1e5bd841 BS |
1655 | } |
1656 | ||
f5d8c9f4 | 1657 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1658 | |
f5d8c9f4 | 1659 | static int |
e04ca094 | 1660 | find_reg (chain, order) |
03acd8f8 | 1661 | struct insn_chain *chain; |
f5d8c9f4 | 1662 | int order; |
1e5bd841 | 1663 | { |
f5d8c9f4 BS |
1664 | int rnum = reload_order[order]; |
1665 | struct reload *rl = rld + rnum; | |
1666 | int best_cost = INT_MAX; | |
1667 | int best_reg = -1; | |
770ae6cc RK |
1668 | unsigned int i, j; |
1669 | int k; | |
f5d8c9f4 BS |
1670 | HARD_REG_SET not_usable; |
1671 | HARD_REG_SET used_by_other_reload; | |
1e5bd841 | 1672 | |
f5d8c9f4 BS |
1673 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1674 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1675 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1676 | ||
1677 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1678 | for (k = 0; k < order; k++) |
1e5bd841 | 1679 | { |
770ae6cc RK |
1680 | int other = reload_order[k]; |
1681 | ||
f5d8c9f4 BS |
1682 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1683 | for (j = 0; j < rld[other].nregs; j++) | |
1684 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1685 | } | |
1e5bd841 | 1686 | |
f5d8c9f4 BS |
1687 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1688 | { | |
770ae6cc RK |
1689 | unsigned int regno = i; |
1690 | ||
f5d8c9f4 BS |
1691 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1692 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1693 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1694 | { |
f5d8c9f4 BS |
1695 | int this_cost = spill_cost[regno]; |
1696 | int ok = 1; | |
770ae6cc | 1697 | unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); |
1e5bd841 | 1698 | |
f5d8c9f4 BS |
1699 | for (j = 1; j < this_nregs; j++) |
1700 | { | |
1701 | this_cost += spill_add_cost[regno + j]; | |
1702 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1703 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1704 | ok = 0; | |
1705 | } | |
1706 | if (! ok) | |
1707 | continue; | |
1708 | if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) | |
1709 | this_cost--; | |
1710 | if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) | |
1711 | this_cost--; | |
1712 | if (this_cost < best_cost | |
1713 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1714 | use REG_ALLOC_ORDER if it is defined. */ | |
1715 | || (this_cost == best_cost | |
1716 | #ifdef REG_ALLOC_ORDER | |
1717 | && (inv_reg_alloc_order[regno] | |
1718 | < inv_reg_alloc_order[best_reg]) | |
1719 | #else | |
1720 | && call_used_regs[regno] | |
1721 | && ! call_used_regs[best_reg] | |
1722 | #endif | |
1723 | )) | |
1724 | { | |
1725 | best_reg = regno; | |
1726 | best_cost = this_cost; | |
1e5bd841 BS |
1727 | } |
1728 | } | |
1729 | } | |
f5d8c9f4 BS |
1730 | if (best_reg == -1) |
1731 | return 0; | |
770ae6cc | 1732 | |
e04ca094 JL |
1733 | if (rtl_dump_file) |
1734 | fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1735 | |
f5d8c9f4 BS |
1736 | rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); |
1737 | rl->regno = best_reg; | |
1e5bd841 | 1738 | |
f5d8c9f4 | 1739 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1740 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1741 | { |
1742 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1743 | }); | |
770ae6cc | 1744 | |
f5d8c9f4 | 1745 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1746 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1747 | { |
1748 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1749 | }); | |
03acd8f8 | 1750 | |
f5d8c9f4 BS |
1751 | for (i = 0; i < rl->nregs; i++) |
1752 | { | |
1753 | if (spill_cost[best_reg + i] != 0 | |
1754 | || spill_add_cost[best_reg + i] != 0) | |
1755 | abort (); | |
1756 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); | |
1757 | } | |
1758 | return 1; | |
03acd8f8 BS |
1759 | } |
1760 | ||
1761 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1762 | is given by CHAIN. | |
1e5bd841 BS |
1763 | Do it by ascending class number, since otherwise a reg |
1764 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1765 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1766 | |
03acd8f8 | 1767 | static void |
e04ca094 | 1768 | find_reload_regs (chain) |
03acd8f8 | 1769 | struct insn_chain *chain; |
1e5bd841 | 1770 | { |
f5d8c9f4 | 1771 | int i; |
1e5bd841 | 1772 | |
f5d8c9f4 BS |
1773 | /* In order to be certain of getting the registers we need, |
1774 | we must sort the reloads into order of increasing register class. | |
1775 | Then our grabbing of reload registers will parallel the process | |
1776 | that provided the reload registers. */ | |
1777 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1778 | { |
f5d8c9f4 BS |
1779 | /* Show whether this reload already has a hard reg. */ |
1780 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1781 | { |
f5d8c9f4 BS |
1782 | int regno = REGNO (chain->rld[i].reg_rtx); |
1783 | chain->rld[i].regno = regno; | |
770ae6cc RK |
1784 | chain->rld[i].nregs |
1785 | = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); | |
1e5bd841 | 1786 | } |
f5d8c9f4 BS |
1787 | else |
1788 | chain->rld[i].regno = -1; | |
1789 | reload_order[i] = i; | |
1790 | } | |
1e5bd841 | 1791 | |
f5d8c9f4 BS |
1792 | n_reloads = chain->n_reloads; |
1793 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1794 | |
f5d8c9f4 | 1795 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1796 | |
e04ca094 JL |
1797 | if (rtl_dump_file) |
1798 | fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1799 | |
f5d8c9f4 | 1800 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1801 | |
f5d8c9f4 | 1802 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1803 | |
f5d8c9f4 | 1804 | order_regs_for_reload (chain); |
1e5bd841 | 1805 | |
f5d8c9f4 BS |
1806 | for (i = 0; i < n_reloads; i++) |
1807 | { | |
1808 | int r = reload_order[i]; | |
1e5bd841 | 1809 | |
f5d8c9f4 BS |
1810 | /* Ignore reloads that got marked inoperative. */ |
1811 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1812 | && ! rld[r].optional | |
1813 | && rld[r].regno == -1) | |
e04ca094 | 1814 | if (! find_reg (chain, i)) |
f5d8c9f4 | 1815 | { |
ecf3151a | 1816 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1817 | failure = 1; |
03acd8f8 | 1818 | return; |
f5d8c9f4 | 1819 | } |
1e5bd841 | 1820 | } |
05d10675 | 1821 | |
f5d8c9f4 BS |
1822 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1823 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1824 | |
f5d8c9f4 | 1825 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1826 | } |
1827 | ||
f5d8c9f4 | 1828 | static void |
e04ca094 | 1829 | select_reload_regs () |
09dd1133 | 1830 | { |
f5d8c9f4 | 1831 | struct insn_chain *chain; |
09dd1133 | 1832 | |
f5d8c9f4 BS |
1833 | /* Try to satisfy the needs for each insn. */ |
1834 | for (chain = insns_need_reload; chain != 0; | |
1835 | chain = chain->next_need_reload) | |
e04ca094 | 1836 | find_reload_regs (chain); |
09dd1133 | 1837 | } |
32131a9c | 1838 | \f |
437a710d BS |
1839 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1840 | this iteration. */ | |
1841 | static void | |
7609e720 | 1842 | delete_caller_save_insns () |
437a710d | 1843 | { |
7609e720 | 1844 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1845 | |
7609e720 | 1846 | while (c != 0) |
437a710d | 1847 | { |
7609e720 | 1848 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1849 | { |
7609e720 BS |
1850 | struct insn_chain *next = c->next; |
1851 | rtx insn = c->insn; | |
1852 | ||
7609e720 BS |
1853 | if (c == reload_insn_chain) |
1854 | reload_insn_chain = next; | |
ca6c03ca | 1855 | delete_insn (insn); |
7609e720 BS |
1856 | |
1857 | if (next) | |
1858 | next->prev = c->prev; | |
1859 | if (c->prev) | |
1860 | c->prev->next = next; | |
1861 | c->next = unused_insn_chains; | |
1862 | unused_insn_chains = c; | |
1863 | c = next; | |
437a710d | 1864 | } |
7609e720 BS |
1865 | if (c != 0) |
1866 | c = c->next; | |
437a710d BS |
1867 | } |
1868 | } | |
1869 | \f | |
5352b11a RS |
1870 | /* Handle the failure to find a register to spill. |
1871 | INSN should be one of the insns which needed this particular spill reg. */ | |
1872 | ||
1873 | static void | |
ecf3151a | 1874 | spill_failure (insn, class) |
5352b11a | 1875 | rtx insn; |
ecf3151a | 1876 | enum reg_class class; |
5352b11a | 1877 | { |
ecf3151a | 1878 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
5352b11a | 1879 | if (asm_noperands (PATTERN (insn)) >= 0) |
ecf3151a BS |
1880 | error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.", |
1881 | reg_class_names[class]); | |
5352b11a | 1882 | else |
ecf3151a BS |
1883 | { |
1884 | error ("Unable to find a register to spill in class `%s'.", | |
1885 | reg_class_names[class]); | |
1886 | fatal_insn ("This is the insn:", insn); | |
1887 | } | |
5352b11a | 1888 | } |
32131a9c RK |
1889 | \f |
1890 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
1891 | data that is dead in INSN. */ | |
1892 | ||
1893 | static void | |
1894 | delete_dead_insn (insn) | |
1895 | rtx insn; | |
1896 | { | |
1897 | rtx prev = prev_real_insn (insn); | |
1898 | rtx prev_dest; | |
1899 | ||
1900 | /* If the previous insn sets a register that dies in our insn, delete it | |
1901 | too. */ | |
1902 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
1903 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
1904 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
b294ca38 R |
1905 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
1906 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
1907 | delete_dead_insn (prev); |
1908 | ||
1909 | PUT_CODE (insn, NOTE); | |
1910 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1911 | NOTE_SOURCE_FILE (insn) = 0; | |
1912 | } | |
1913 | ||
1914 | /* Modify the home of pseudo-reg I. | |
1915 | The new home is present in reg_renumber[I]. | |
1916 | ||
1917 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1918 | or it may be -1, meaning there is none or it is not relevant. | |
1919 | This is used so that all pseudos spilled from a given hard reg | |
1920 | can share one stack slot. */ | |
1921 | ||
1922 | static void | |
1923 | alter_reg (i, from_reg) | |
1924 | register int i; | |
1925 | int from_reg; | |
1926 | { | |
1927 | /* When outputting an inline function, this can happen | |
1928 | for a reg that isn't actually used. */ | |
1929 | if (regno_reg_rtx[i] == 0) | |
1930 | return; | |
1931 | ||
1932 | /* If the reg got changed to a MEM at rtl-generation time, | |
1933 | ignore it. */ | |
1934 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1935 | return; | |
1936 | ||
1937 | /* Modify the reg-rtx to contain the new hard reg | |
1938 | number or else to contain its pseudo reg number. */ | |
1939 | REGNO (regno_reg_rtx[i]) | |
1940 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1941 | ||
1942 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1943 | allocate a stack slot for it. */ | |
1944 | ||
1945 | if (reg_renumber[i] < 0 | |
b1f21e0a | 1946 | && REG_N_REFS (i) > 0 |
32131a9c RK |
1947 | && reg_equiv_constant[i] == 0 |
1948 | && reg_equiv_memory_loc[i] == 0) | |
1949 | { | |
1950 | register rtx x; | |
770ae6cc RK |
1951 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
1952 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
32131a9c RK |
1953 | int adjust = 0; |
1954 | ||
1955 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1956 | and a total size which provides room for paradoxical subregs | |
1957 | which refer to the pseudo reg in wider modes. | |
1958 | ||
1959 | We can use a slot already allocated if it provides both | |
1960 | enough inherent space and enough total space. | |
1961 | Otherwise, we allocate a new slot, making sure that it has no less | |
1962 | inherent space, and no less total space, then the previous slot. */ | |
1963 | if (from_reg == -1) | |
1964 | { | |
1965 | /* No known place to spill from => no slot to reuse. */ | |
cabcf079 ILT |
1966 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, |
1967 | inherent_size == total_size ? 0 : -1); | |
f76b9db2 | 1968 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
1969 | /* Cancel the big-endian correction done in assign_stack_local. |
1970 | Get the address of the beginning of the slot. | |
1971 | This is so we can do a big-endian correction unconditionally | |
1972 | below. */ | |
1973 | adjust = inherent_size - total_size; | |
1974 | ||
1975 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
3bdf5ad1 RK |
1976 | |
1977 | /* Nothing can alias this slot except this pseudo. */ | |
ba4828e0 | 1978 | set_mem_alias_set (x, new_alias_set ()); |
32131a9c | 1979 | } |
3bdf5ad1 | 1980 | |
32131a9c RK |
1981 | /* Reuse a stack slot if possible. */ |
1982 | else if (spill_stack_slot[from_reg] != 0 | |
1983 | && spill_stack_slot_width[from_reg] >= total_size | |
1984 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1985 | >= inherent_size)) | |
1986 | x = spill_stack_slot[from_reg]; | |
3bdf5ad1 | 1987 | |
32131a9c RK |
1988 | /* Allocate a bigger slot. */ |
1989 | else | |
1990 | { | |
1991 | /* Compute maximum size needed, both for inherent size | |
1992 | and for total size. */ | |
1993 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
4f2d3674 | 1994 | rtx stack_slot; |
3bdf5ad1 | 1995 | |
32131a9c RK |
1996 | if (spill_stack_slot[from_reg]) |
1997 | { | |
1998 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1999 | > inherent_size) | |
2000 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2001 | if (spill_stack_slot_width[from_reg] > total_size) | |
2002 | total_size = spill_stack_slot_width[from_reg]; | |
2003 | } | |
3bdf5ad1 | 2004 | |
32131a9c | 2005 | /* Make a slot with that size. */ |
cabcf079 ILT |
2006 | x = assign_stack_local (mode, total_size, |
2007 | inherent_size == total_size ? 0 : -1); | |
4f2d3674 | 2008 | stack_slot = x; |
3bdf5ad1 RK |
2009 | |
2010 | /* All pseudos mapped to this slot can alias each other. */ | |
2011 | if (spill_stack_slot[from_reg]) | |
ba4828e0 | 2012 | set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg])); |
3bdf5ad1 | 2013 | else |
ba4828e0 | 2014 | set_mem_alias_set (x, new_alias_set ()); |
3bdf5ad1 | 2015 | |
f76b9db2 ILT |
2016 | if (BYTES_BIG_ENDIAN) |
2017 | { | |
2018 | /* Cancel the big-endian correction done in assign_stack_local. | |
2019 | Get the address of the beginning of the slot. | |
2020 | This is so we can do a big-endian correction unconditionally | |
2021 | below. */ | |
2022 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 2023 | if (adjust) |
38a448ca RH |
2024 | stack_slot = gen_rtx_MEM (mode_for_size (total_size |
2025 | * BITS_PER_UNIT, | |
2026 | MODE_INT, 1), | |
05d10675 | 2027 | plus_constant (XEXP (x, 0), adjust)); |
f76b9db2 | 2028 | } |
3bdf5ad1 | 2029 | |
4f2d3674 | 2030 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
2031 | spill_stack_slot_width[from_reg] = total_size; |
2032 | } | |
2033 | ||
32131a9c RK |
2034 | /* On a big endian machine, the "address" of the slot |
2035 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 2036 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 2037 | adjust += (total_size - inherent_size); |
32131a9c RK |
2038 | |
2039 | /* If we have any adjustment to make, or if the stack slot is the | |
2040 | wrong mode, make a new stack slot. */ | |
2041 | if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) | |
f1ec5147 | 2042 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
32131a9c RK |
2043 | |
2044 | /* Save the stack slot for later. */ | |
2045 | reg_equiv_memory_loc[i] = x; | |
2046 | } | |
2047 | } | |
2048 | ||
2049 | /* Mark the slots in regs_ever_live for the hard regs | |
2050 | used by pseudo-reg number REGNO. */ | |
2051 | ||
2052 | void | |
2053 | mark_home_live (regno) | |
2054 | int regno; | |
2055 | { | |
2056 | register int i, lim; | |
770ae6cc | 2057 | |
32131a9c RK |
2058 | i = reg_renumber[regno]; |
2059 | if (i < 0) | |
2060 | return; | |
2061 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
2062 | while (i < lim) | |
2063 | regs_ever_live[i++] = 1; | |
2064 | } | |
2065 | \f | |
2066 | /* This function handles the tracking of elimination offsets around branches. | |
2067 | ||
2068 | X is a piece of RTL being scanned. | |
2069 | ||
2070 | INSN is the insn that it came from, if any. | |
2071 | ||
2072 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
2073 | offset and zero if we are setting the offset of the label to be the | |
2074 | current offset. */ | |
2075 | ||
2076 | static void | |
2077 | set_label_offsets (x, insn, initial_p) | |
2078 | rtx x; | |
2079 | rtx insn; | |
2080 | int initial_p; | |
2081 | { | |
2082 | enum rtx_code code = GET_CODE (x); | |
2083 | rtx tem; | |
e51712db | 2084 | unsigned int i; |
32131a9c RK |
2085 | struct elim_table *p; |
2086 | ||
2087 | switch (code) | |
2088 | { | |
2089 | case LABEL_REF: | |
8be386d9 RS |
2090 | if (LABEL_REF_NONLOCAL_P (x)) |
2091 | return; | |
2092 | ||
32131a9c RK |
2093 | x = XEXP (x, 0); |
2094 | ||
0f41302f | 2095 | /* ... fall through ... */ |
32131a9c RK |
2096 | |
2097 | case CODE_LABEL: | |
2098 | /* If we know nothing about this label, set the desired offsets. Note | |
2099 | that this sets the offset at a label to be the offset before a label | |
2100 | if we don't know anything about the label. This is not correct for | |
2101 | the label after a BARRIER, but is the best guess we can make. If | |
2102 | we guessed wrong, we will suppress an elimination that might have | |
2103 | been possible had we been able to guess correctly. */ | |
2104 | ||
2105 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2106 | { | |
2107 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2108 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2109 | = (initial_p ? reg_eliminate[i].initial_offset | |
2110 | : reg_eliminate[i].offset); | |
2111 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2112 | } | |
2113 | ||
2114 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2115 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2116 | that label. */ |
2117 | ||
2118 | else if (x == insn | |
2119 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2120 | && GET_CODE (tem) == BARRIER) | |
1f3b1e1a | 2121 | set_offsets_for_label (insn); |
32131a9c RK |
2122 | else |
2123 | /* If neither of the above cases is true, compare each offset | |
2124 | with those previously recorded and suppress any eliminations | |
2125 | where the offsets disagree. */ | |
a8fdc208 | 2126 | |
32131a9c RK |
2127 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2128 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2129 | != (initial_p ? reg_eliminate[i].initial_offset | |
2130 | : reg_eliminate[i].offset)) | |
2131 | reg_eliminate[i].can_eliminate = 0; | |
2132 | ||
2133 | return; | |
2134 | ||
2135 | case JUMP_INSN: | |
2136 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2137 | ||
0f41302f | 2138 | /* ... fall through ... */ |
32131a9c RK |
2139 | |
2140 | case INSN: | |
2141 | case CALL_INSN: | |
2142 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2143 | and hence must have all eliminations at their initial offsets. */ | |
2144 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2145 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2146 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2147 | return; | |
2148 | ||
0c0ba09c | 2149 | case PARALLEL: |
32131a9c RK |
2150 | case ADDR_VEC: |
2151 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2152 | /* Each of the labels in the parallel or address vector must be |
2153 | at their initial offsets. We want the first field for PARALLEL | |
2154 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2155 | |
e51712db | 2156 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2157 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2158 | insn, initial_p); | |
2159 | return; | |
2160 | ||
2161 | case SET: | |
2162 | /* We only care about setting PC. If the source is not RETURN, | |
2163 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2164 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2165 | isn't one of those possibilities. For branches to a label, | |
2166 | call ourselves recursively. | |
2167 | ||
2168 | Note that this can disable elimination unnecessarily when we have | |
2169 | a non-local goto since it will look like a non-constant jump to | |
2170 | someplace in the current function. This isn't a significant | |
2171 | problem since such jumps will normally be when all elimination | |
2172 | pairs are back to their initial offsets. */ | |
2173 | ||
2174 | if (SET_DEST (x) != pc_rtx) | |
2175 | return; | |
2176 | ||
2177 | switch (GET_CODE (SET_SRC (x))) | |
2178 | { | |
2179 | case PC: | |
2180 | case RETURN: | |
2181 | return; | |
2182 | ||
2183 | case LABEL_REF: | |
2184 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2185 | return; | |
2186 | ||
2187 | case IF_THEN_ELSE: | |
2188 | tem = XEXP (SET_SRC (x), 1); | |
2189 | if (GET_CODE (tem) == LABEL_REF) | |
2190 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2191 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2192 | break; | |
2193 | ||
2194 | tem = XEXP (SET_SRC (x), 2); | |
2195 | if (GET_CODE (tem) == LABEL_REF) | |
2196 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2197 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2198 | break; | |
2199 | return; | |
e9a25f70 JL |
2200 | |
2201 | default: | |
2202 | break; | |
32131a9c RK |
2203 | } |
2204 | ||
2205 | /* If we reach here, all eliminations must be at their initial | |
2206 | offset because we are doing a jump to a variable address. */ | |
2207 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2208 | if (p->offset != p->initial_offset) | |
2209 | p->can_eliminate = 0; | |
e9a25f70 | 2210 | break; |
05d10675 | 2211 | |
e9a25f70 JL |
2212 | default: |
2213 | break; | |
32131a9c RK |
2214 | } |
2215 | } | |
2216 | \f | |
a8fdc208 | 2217 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2218 | replacement (such as sp), plus an offset. |
2219 | ||
2220 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2221 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2222 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2223 | with the register, which we cannot do outside a MEM. In addition, we need | |
2224 | to record the fact that a register is referenced outside a MEM. | |
2225 | ||
ff32812a | 2226 | If INSN is an insn, it is the insn containing X. If we replace a REG |
32131a9c RK |
2227 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a |
2228 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
38e01259 | 2229 | the REG is being modified. |
32131a9c | 2230 | |
ff32812a RS |
2231 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2232 | That's used when we eliminate in expressions stored in notes. | |
2233 | This means, do not set ref_outside_mem even if the reference | |
2234 | is outside of MEMs. | |
2235 | ||
32131a9c RK |
2236 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2237 | replacements done assuming all offsets are at their initial values. If | |
2238 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2239 | encounter, return the actual location so that find_reloads will do | |
2240 | the proper thing. */ | |
2241 | ||
2242 | rtx | |
1914f5da | 2243 | eliminate_regs (x, mem_mode, insn) |
32131a9c RK |
2244 | rtx x; |
2245 | enum machine_mode mem_mode; | |
2246 | rtx insn; | |
2247 | { | |
2248 | enum rtx_code code = GET_CODE (x); | |
2249 | struct elim_table *ep; | |
2250 | int regno; | |
2251 | rtx new; | |
2252 | int i, j; | |
6f7d635c | 2253 | const char *fmt; |
32131a9c RK |
2254 | int copied = 0; |
2255 | ||
d6633f01 NS |
2256 | if (! current_function_decl) |
2257 | return x; | |
9969bb2c | 2258 | |
32131a9c RK |
2259 | switch (code) |
2260 | { | |
2261 | case CONST_INT: | |
2262 | case CONST_DOUBLE: | |
2263 | case CONST: | |
2264 | case SYMBOL_REF: | |
2265 | case CODE_LABEL: | |
2266 | case PC: | |
2267 | case CC0: | |
2268 | case ASM_INPUT: | |
2269 | case ADDR_VEC: | |
2270 | case ADDR_DIFF_VEC: | |
2271 | case RETURN: | |
2272 | return x; | |
2273 | ||
e9a25f70 JL |
2274 | case ADDRESSOF: |
2275 | /* This is only for the benefit of the debugging backends, which call | |
2276 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2277 | removed after CSE. */ | |
1914f5da | 2278 | new = eliminate_regs (XEXP (x, 0), 0, insn); |
e9a25f70 JL |
2279 | if (GET_CODE (new) == MEM) |
2280 | return XEXP (new, 0); | |
2281 | return x; | |
2282 | ||
32131a9c RK |
2283 | case REG: |
2284 | regno = REGNO (x); | |
2285 | ||
2286 | /* First handle the case where we encounter a bare register that | |
2287 | is eliminable. Replace it with a PLUS. */ | |
2288 | if (regno < FIRST_PSEUDO_REGISTER) | |
2289 | { | |
2290 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2291 | ep++) | |
2292 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2293 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2294 | |
2295 | } | |
2b49ee39 R |
2296 | else if (reg_renumber[regno] < 0 && reg_equiv_constant |
2297 | && reg_equiv_constant[regno] | |
2298 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2299 | return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), | |
2300 | mem_mode, insn); | |
32131a9c RK |
2301 | return x; |
2302 | ||
c5c76735 JL |
2303 | /* You might think handling MINUS in a manner similar to PLUS is a |
2304 | good idea. It is not. It has been tried multiple times and every | |
2305 | time the change has had to have been reverted. | |
2306 | ||
2307 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2308 | and require special code to handle code a reloaded PLUS operand. | |
2309 | ||
2310 | Also consider backends where the flags register is clobbered by a | |
2311 | MINUS, but we can emit a PLUS that does not clobber flags (ia32, | |
2312 | lea instruction comes to mind). If we try to reload a MINUS, we | |
2313 | may kill the flags register that was holding a useful value. | |
2314 | ||
2315 | So, please before trying to handle MINUS, consider reload as a | |
2316 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2317 | case PLUS: |
2318 | /* If this is the sum of an eliminable register and a constant, rework | |
2319 | the sum. */ | |
2320 | if (GET_CODE (XEXP (x, 0)) == REG | |
2321 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2322 | && CONSTANT_P (XEXP (x, 1))) | |
2323 | { | |
2324 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2325 | ep++) | |
2326 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2327 | { | |
32131a9c RK |
2328 | /* The only time we want to replace a PLUS with a REG (this |
2329 | occurs when the constant operand of the PLUS is the negative | |
2330 | of the offset) is when we are inside a MEM. We won't want | |
2331 | to do so at other times because that would change the | |
2332 | structure of the insn in a way that reload can't handle. | |
2333 | We special-case the commonest situation in | |
2334 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2335 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2336 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2337 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2338 | return ep->to_rtx; | |
2339 | else | |
38a448ca RH |
2340 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2341 | plus_constant (XEXP (x, 1), | |
2342 | ep->previous_offset)); | |
32131a9c RK |
2343 | } |
2344 | ||
2345 | /* If the register is not eliminable, we are done since the other | |
2346 | operand is a constant. */ | |
2347 | return x; | |
2348 | } | |
2349 | ||
2350 | /* If this is part of an address, we want to bring any constant to the | |
2351 | outermost PLUS. We will do this by doing register replacement in | |
2352 | our operands and seeing if a constant shows up in one of them. | |
2353 | ||
dfac187e BS |
2354 | Note that there is no risk of modifying the structure of the insn, |
2355 | since we only get called for its operands, thus we are either | |
2356 | modifying the address inside a MEM, or something like an address | |
2357 | operand of a load-address insn. */ | |
32131a9c RK |
2358 | |
2359 | { | |
1914f5da RH |
2360 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
2361 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); | |
32131a9c RK |
2362 | |
2363 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2364 | { | |
2365 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2366 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2367 | we must replace the constant here since it may no longer |
2368 | be in the position of any operand. */ | |
2369 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2370 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2371 | && reg_renumber[REGNO (new1)] < 0 | |
2372 | && reg_equiv_constant != 0 | |
2373 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2374 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2375 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2376 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2377 | && reg_renumber[REGNO (new0)] < 0 | |
2378 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2379 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2380 | ||
2381 | new = form_sum (new0, new1); | |
2382 | ||
2383 | /* As above, if we are not inside a MEM we do not want to | |
2384 | turn a PLUS into something else. We might try to do so here | |
2385 | for an addition of 0 if we aren't optimizing. */ | |
2386 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2387 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2388 | else |
2389 | return new; | |
2390 | } | |
2391 | } | |
2392 | return x; | |
2393 | ||
981c7390 | 2394 | case MULT: |
05d10675 | 2395 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2396 | constant, apply the distribute law and move the constant out |
2397 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2398 | to keep load-address insns valid. This case is pathological. |
981c7390 RK |
2399 | We ignore the possibility of overflow here. */ |
2400 | if (GET_CODE (XEXP (x, 0)) == REG | |
2401 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2402 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2403 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2404 | ep++) | |
2405 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2406 | { | |
2407 | if (! mem_mode | |
2408 | /* Refs inside notes don't count for this purpose. */ | |
2409 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2410 | || GET_CODE (insn) == INSN_LIST))) | |
2411 | ep->ref_outside_mem = 1; | |
2412 | ||
2413 | return | |
38a448ca | 2414 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2415 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2416 | } | |
32131a9c | 2417 | |
0f41302f | 2418 | /* ... fall through ... */ |
32131a9c | 2419 | |
32131a9c RK |
2420 | case CALL: |
2421 | case COMPARE: | |
c5c76735 | 2422 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2423 | case MINUS: |
32131a9c RK |
2424 | case DIV: case UDIV: |
2425 | case MOD: case UMOD: | |
2426 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2427 | case ROTATERT: case ROTATE: |
2428 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2429 | case NE: case EQ: |
2430 | case GE: case GT: case GEU: case GTU: | |
2431 | case LE: case LT: case LEU: case LTU: | |
2432 | { | |
1914f5da | 2433 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
fb3821f7 | 2434 | rtx new1 |
1914f5da | 2435 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; |
32131a9c RK |
2436 | |
2437 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2438 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2439 | } |
2440 | return x; | |
2441 | ||
981c7390 RK |
2442 | case EXPR_LIST: |
2443 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2444 | if (XEXP (x, 0)) | |
2445 | { | |
1914f5da | 2446 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
981c7390 | 2447 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2448 | { |
2449 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2450 | Using the eliminated version could result in creating a | |
2451 | REG_DEAD note for the stack or frame pointer. */ | |
2452 | if (GET_MODE (x) == REG_DEAD) | |
2453 | return (XEXP (x, 1) | |
2454 | ? eliminate_regs (XEXP (x, 1), mem_mode, insn) | |
2455 | : NULL_RTX); | |
2456 | ||
2457 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2458 | } | |
981c7390 RK |
2459 | } |
2460 | ||
0f41302f | 2461 | /* ... fall through ... */ |
981c7390 RK |
2462 | |
2463 | case INSN_LIST: | |
2464 | /* Now do eliminations in the rest of the chain. If this was | |
2465 | an EXPR_LIST, this might result in allocating more memory than is | |
2466 | strictly needed, but it simplifies the code. */ | |
2467 | if (XEXP (x, 1)) | |
2468 | { | |
1914f5da | 2469 | new = eliminate_regs (XEXP (x, 1), mem_mode, insn); |
981c7390 | 2470 | if (new != XEXP (x, 1)) |
38a448ca | 2471 | return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); |
981c7390 RK |
2472 | } |
2473 | return x; | |
2474 | ||
32131a9c RK |
2475 | case PRE_INC: |
2476 | case POST_INC: | |
2477 | case PRE_DEC: | |
2478 | case POST_DEC: | |
32131a9c RK |
2479 | case STRICT_LOW_PART: |
2480 | case NEG: case NOT: | |
2481 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2482 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2483 | case FLOAT: case FIX: | |
2484 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2485 | case ABS: | |
2486 | case SQRT: | |
2487 | case FFS: | |
1914f5da | 2488 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
32131a9c | 2489 | if (new != XEXP (x, 0)) |
38a448ca | 2490 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2491 | return x; |
2492 | ||
2493 | case SUBREG: | |
ddef6bc7 | 2494 | /* Similar to above processing, but preserve SUBREG_BYTE. |
32131a9c RK |
2495 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2496 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2497 | pseudo didn't get a hard reg, we must replace this with the | |
2498 | eliminated version of the memory location because push_reloads | |
2499 | may do the replacement in certain circumstances. */ | |
2500 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2501 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2502 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2503 | && reg_equiv_memory_loc != 0 | |
2504 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2505 | { | |
cb2afeb3 | 2506 | new = SUBREG_REG (x); |
32131a9c RK |
2507 | } |
2508 | else | |
1914f5da | 2509 | new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); |
32131a9c | 2510 | |
ddef6bc7 | 2511 | if (new != SUBREG_REG (x)) |
32131a9c | 2512 | { |
29ae5012 RK |
2513 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2514 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2515 | ||
1914f5da | 2516 | if (GET_CODE (new) == MEM |
6d49a073 | 2517 | && ((x_size < new_size |
1914f5da | 2518 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2519 | /* On these machines, combine can create rtl of the form |
2520 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2521 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2522 | happen to the entire word. Moreover, it will use the |
2523 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2524 | So if the number of words is the same, preserve the |
6d49a073 | 2525 | subreg so that push_reloads can see it. */ |
5d9669fd RK |
2526 | && ! ((x_size - 1) / UNITS_PER_WORD |
2527 | == (new_size -1 ) / UNITS_PER_WORD) | |
1914f5da | 2528 | #endif |
6d49a073 | 2529 | ) |
5d9669fd | 2530 | || x_size == new_size) |
1914f5da | 2531 | ) |
32131a9c | 2532 | { |
ddef6bc7 | 2533 | int offset = SUBREG_BYTE (x); |
32131a9c RK |
2534 | enum machine_mode mode = GET_MODE (x); |
2535 | ||
32131a9c RK |
2536 | PUT_MODE (new, mode); |
2537 | XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); | |
2538 | return new; | |
2539 | } | |
2540 | else | |
ddef6bc7 | 2541 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); |
32131a9c RK |
2542 | } |
2543 | ||
2544 | return x; | |
2545 | ||
32131a9c | 2546 | case MEM: |
e9a25f70 JL |
2547 | /* This is only for the benefit of the debugging backends, which call |
2548 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2549 | removed after CSE. */ | |
2550 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
1914f5da | 2551 | return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); |
e9a25f70 | 2552 | |
32131a9c RK |
2553 | /* Our only special processing is to pass the mode of the MEM to our |
2554 | recursive call and copy the flags. While we are here, handle this | |
2555 | case more efficiently. */ | |
f1ec5147 RK |
2556 | return |
2557 | replace_equiv_address_nv (x, | |
2558 | eliminate_regs (XEXP (x, 0), | |
2559 | GET_MODE (x), insn)); | |
05d10675 | 2560 | |
dfac187e | 2561 | case USE: |
055c7759 JDA |
2562 | /* Handle insn_list USE that a call to a pure function may generate. */ |
2563 | new = eliminate_regs (XEXP (x, 0), 0, insn); | |
2564 | if (new != XEXP (x, 0)) | |
2565 | return gen_rtx_USE (GET_MODE (x), new); | |
2566 | return x; | |
2567 | ||
dfac187e BS |
2568 | case CLOBBER: |
2569 | case ASM_OPERANDS: | |
2570 | case SET: | |
2571 | abort (); | |
2572 | ||
e9a25f70 JL |
2573 | default: |
2574 | break; | |
32131a9c RK |
2575 | } |
2576 | ||
2577 | /* Process each of our operands recursively. If any have changed, make a | |
2578 | copy of the rtx. */ | |
2579 | fmt = GET_RTX_FORMAT (code); | |
2580 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2581 | { | |
2582 | if (*fmt == 'e') | |
2583 | { | |
1914f5da | 2584 | new = eliminate_regs (XEXP (x, i), mem_mode, insn); |
32131a9c RK |
2585 | if (new != XEXP (x, i) && ! copied) |
2586 | { | |
2587 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2588 | memcpy (new_x, x, |
2589 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2590 | + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); | |
32131a9c RK |
2591 | x = new_x; |
2592 | copied = 1; | |
2593 | } | |
2594 | XEXP (x, i) = new; | |
2595 | } | |
2596 | else if (*fmt == 'E') | |
2597 | { | |
2598 | int copied_vec = 0; | |
2599 | for (j = 0; j < XVECLEN (x, i); j++) | |
2600 | { | |
1914f5da | 2601 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); |
32131a9c RK |
2602 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2603 | { | |
8f985ec4 ZW |
2604 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2605 | XVEC (x, i)->elem); | |
32131a9c RK |
2606 | if (! copied) |
2607 | { | |
2608 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2609 | memcpy (new_x, x, |
2610 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2611 | + (sizeof (new_x->fld[0]) | |
2612 | * GET_RTX_LENGTH (code)))); | |
32131a9c RK |
2613 | x = new_x; |
2614 | copied = 1; | |
2615 | } | |
2616 | XVEC (x, i) = new_v; | |
2617 | copied_vec = 1; | |
2618 | } | |
2619 | XVECEXP (x, i, j) = new; | |
2620 | } | |
2621 | } | |
2622 | } | |
2623 | ||
2624 | return x; | |
2625 | } | |
dfac187e BS |
2626 | |
2627 | /* Scan rtx X for modifications of elimination target registers. Update | |
2628 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2629 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2630 | ||
2631 | static void | |
2632 | elimination_effects (x, mem_mode) | |
2633 | rtx x; | |
2634 | enum machine_mode mem_mode; | |
2635 | ||
2636 | { | |
2637 | enum rtx_code code = GET_CODE (x); | |
2638 | struct elim_table *ep; | |
2639 | int regno; | |
2640 | int i, j; | |
2641 | const char *fmt; | |
2642 | ||
2643 | switch (code) | |
2644 | { | |
2645 | case CONST_INT: | |
2646 | case CONST_DOUBLE: | |
2647 | case CONST: | |
2648 | case SYMBOL_REF: | |
2649 | case CODE_LABEL: | |
2650 | case PC: | |
2651 | case CC0: | |
2652 | case ASM_INPUT: | |
2653 | case ADDR_VEC: | |
2654 | case ADDR_DIFF_VEC: | |
2655 | case RETURN: | |
2656 | return; | |
2657 | ||
2658 | case ADDRESSOF: | |
2659 | abort (); | |
2660 | ||
2661 | case REG: | |
2662 | regno = REGNO (x); | |
2663 | ||
2664 | /* First handle the case where we encounter a bare register that | |
2665 | is eliminable. Replace it with a PLUS. */ | |
2666 | if (regno < FIRST_PSEUDO_REGISTER) | |
2667 | { | |
2668 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2669 | ep++) | |
2670 | if (ep->from_rtx == x && ep->can_eliminate) | |
2671 | { | |
2672 | if (! mem_mode) | |
2673 | ep->ref_outside_mem = 1; | |
2674 | return; | |
2675 | } | |
2676 | ||
2677 | } | |
2678 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2679 | && reg_equiv_constant[regno] | |
2680 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2681 | elimination_effects (reg_equiv_constant[regno], mem_mode); | |
2682 | return; | |
2683 | ||
2684 | case PRE_INC: | |
2685 | case POST_INC: | |
2686 | case PRE_DEC: | |
2687 | case POST_DEC: | |
4b983fdc RH |
2688 | case POST_MODIFY: |
2689 | case PRE_MODIFY: | |
dfac187e BS |
2690 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2691 | if (ep->to_rtx == XEXP (x, 0)) | |
2692 | { | |
2693 | int size = GET_MODE_SIZE (mem_mode); | |
2694 | ||
2695 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2696 | #ifdef PUSH_ROUNDING | |
2697 | if (ep->to_rtx == stack_pointer_rtx) | |
2698 | size = PUSH_ROUNDING (size); | |
2699 | #endif | |
2700 | if (code == PRE_DEC || code == POST_DEC) | |
2701 | ep->offset += size; | |
4b983fdc | 2702 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 2703 | ep->offset -= size; |
4b983fdc RH |
2704 | else if ((code == PRE_MODIFY || code == POST_MODIFY) |
2705 | && GET_CODE (XEXP (x, 1)) == PLUS | |
2706 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2707 | && CONSTANT_P (XEXP (XEXP (x, 1), 1))) | |
2708 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
dfac187e BS |
2709 | } |
2710 | ||
4b983fdc RH |
2711 | /* These two aren't unary operators. */ |
2712 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2713 | break; | |
2714 | ||
dfac187e BS |
2715 | /* Fall through to generic unary operation case. */ |
2716 | case STRICT_LOW_PART: | |
2717 | case NEG: case NOT: | |
2718 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2719 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2720 | case FLOAT: case FIX: | |
2721 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2722 | case ABS: | |
2723 | case SQRT: | |
2724 | case FFS: | |
2725 | elimination_effects (XEXP (x, 0), mem_mode); | |
2726 | return; | |
2727 | ||
2728 | case SUBREG: | |
2729 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2730 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2731 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2732 | && reg_equiv_memory_loc != 0 | |
2733 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2734 | return; | |
2735 | ||
2736 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2737 | return; | |
2738 | ||
2739 | case USE: | |
2740 | /* If using a register that is the source of an eliminate we still | |
2741 | think can be performed, note it cannot be performed since we don't | |
2742 | know how this register is used. */ | |
2743 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2744 | if (ep->from_rtx == XEXP (x, 0)) | |
2745 | ep->can_eliminate = 0; | |
2746 | ||
2747 | elimination_effects (XEXP (x, 0), mem_mode); | |
2748 | return; | |
2749 | ||
2750 | case CLOBBER: | |
2751 | /* If clobbering a register that is the replacement register for an | |
2752 | elimination we still think can be performed, note that it cannot | |
2753 | be performed. Otherwise, we need not be concerned about it. */ | |
2754 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2755 | if (ep->to_rtx == XEXP (x, 0)) | |
2756 | ep->can_eliminate = 0; | |
2757 | ||
2758 | elimination_effects (XEXP (x, 0), mem_mode); | |
2759 | return; | |
2760 | ||
2761 | case SET: | |
2762 | /* Check for setting a register that we know about. */ | |
2763 | if (GET_CODE (SET_DEST (x)) == REG) | |
2764 | { | |
2765 | /* See if this is setting the replacement register for an | |
2766 | elimination. | |
2767 | ||
2768 | If DEST is the hard frame pointer, we do nothing because we | |
2769 | assume that all assignments to the frame pointer are for | |
2770 | non-local gotos and are being done at a time when they are valid | |
2771 | and do not disturb anything else. Some machines want to | |
2772 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2773 | with either the real frame or the stack pointer. Assignments to | |
2774 | the hard frame pointer must not prevent this elimination. */ | |
2775 | ||
2776 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2777 | ep++) | |
2778 | if (ep->to_rtx == SET_DEST (x) | |
2779 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2780 | { | |
2781 | /* If it is being incremented, adjust the offset. Otherwise, | |
2782 | this elimination can't be done. */ | |
2783 | rtx src = SET_SRC (x); | |
2784 | ||
2785 | if (GET_CODE (src) == PLUS | |
2786 | && XEXP (src, 0) == SET_DEST (x) | |
2787 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2788 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2789 | else | |
2790 | ep->can_eliminate = 0; | |
2791 | } | |
2792 | } | |
2793 | ||
2794 | elimination_effects (SET_DEST (x), 0); | |
2795 | elimination_effects (SET_SRC (x), 0); | |
2796 | return; | |
2797 | ||
2798 | case MEM: | |
2799 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
2800 | abort (); | |
2801 | ||
2802 | /* Our only special processing is to pass the mode of the MEM to our | |
2803 | recursive call. */ | |
2804 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2805 | return; | |
2806 | ||
2807 | default: | |
2808 | break; | |
2809 | } | |
2810 | ||
2811 | fmt = GET_RTX_FORMAT (code); | |
2812 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2813 | { | |
2814 | if (*fmt == 'e') | |
2815 | elimination_effects (XEXP (x, i), mem_mode); | |
2816 | else if (*fmt == 'E') | |
2817 | for (j = 0; j < XVECLEN (x, i); j++) | |
2818 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | /* Descend through rtx X and verify that no references to eliminable registers | |
2823 | remain. If any do remain, mark the involved register as not | |
2824 | eliminable. */ | |
1d813780 | 2825 | |
dfac187e BS |
2826 | static void |
2827 | check_eliminable_occurrences (x) | |
2828 | rtx x; | |
2829 | { | |
2830 | const char *fmt; | |
2831 | int i; | |
2832 | enum rtx_code code; | |
2833 | ||
2834 | if (x == 0) | |
2835 | return; | |
1d7254c5 | 2836 | |
dfac187e BS |
2837 | code = GET_CODE (x); |
2838 | ||
2839 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
2840 | { | |
2841 | struct elim_table *ep; | |
2842 | ||
2843 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2844 | if (ep->from_rtx == x && ep->can_eliminate) | |
2845 | ep->can_eliminate = 0; | |
2846 | return; | |
2847 | } | |
1d7254c5 | 2848 | |
dfac187e BS |
2849 | fmt = GET_RTX_FORMAT (code); |
2850 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2851 | { | |
2852 | if (*fmt == 'e') | |
2853 | check_eliminable_occurrences (XEXP (x, i)); | |
2854 | else if (*fmt == 'E') | |
2855 | { | |
2856 | int j; | |
2857 | for (j = 0; j < XVECLEN (x, i); j++) | |
2858 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
2859 | } | |
2860 | } | |
2861 | } | |
32131a9c RK |
2862 | \f |
2863 | /* Scan INSN and eliminate all eliminable registers in it. | |
2864 | ||
2865 | If REPLACE is nonzero, do the replacement destructively. Also | |
2866 | delete the insn as dead it if it is setting an eliminable register. | |
2867 | ||
2868 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2869 | ||
2870 | If no eliminations were done and this insn doesn't require any elimination | |
2871 | processing (these are not identical conditions: it might be updating sp, | |
2872 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2873 | that the offset between fp and sp can be taken into consideration), zero | |
2874 | is returned. Otherwise, 1 is returned. */ | |
2875 | ||
2876 | static int | |
2877 | eliminate_regs_in_insn (insn, replace) | |
2878 | rtx insn; | |
2879 | int replace; | |
2880 | { | |
dfac187e | 2881 | int icode = recog_memoized (insn); |
32131a9c | 2882 | rtx old_body = PATTERN (insn); |
dfac187e | 2883 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 2884 | rtx old_set = single_set (insn); |
32131a9c RK |
2885 | rtx new_body; |
2886 | int val = 0; | |
dfac187e BS |
2887 | int i, any_changes; |
2888 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2889 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
2890 | struct elim_table *ep; |
2891 | ||
dfac187e BS |
2892 | if (! insn_is_asm && icode < 0) |
2893 | { | |
2894 | if (GET_CODE (PATTERN (insn)) == USE | |
2895 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
2896 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2897 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2898 | || GET_CODE (PATTERN (insn)) == ASM_INPUT) | |
2899 | return 0; | |
2900 | abort (); | |
2901 | } | |
2902 | ||
774672d2 RK |
2903 | if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG |
2904 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
2905 | { |
2906 | /* Check for setting an eliminable register. */ | |
2907 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 2908 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 2909 | { |
dd1eab0a RK |
2910 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
2911 | /* If this is setting the frame pointer register to the | |
2912 | hardware frame pointer register and this is an elimination | |
2913 | that will be done (tested above), this insn is really | |
2914 | adjusting the frame pointer downward to compensate for | |
2915 | the adjustment done before a nonlocal goto. */ | |
2916 | if (ep->from == FRAME_POINTER_REGNUM | |
2917 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
2918 | { | |
2919 | rtx src = SET_SRC (old_set); | |
973838fd | 2920 | int offset = 0, ok = 0; |
8026ebba | 2921 | rtx prev_insn, prev_set; |
dd1eab0a RK |
2922 | |
2923 | if (src == ep->to_rtx) | |
2924 | offset = 0, ok = 1; | |
2925 | else if (GET_CODE (src) == PLUS | |
bb22893c JW |
2926 | && GET_CODE (XEXP (src, 0)) == CONST_INT |
2927 | && XEXP (src, 1) == ep->to_rtx) | |
dd1eab0a | 2928 | offset = INTVAL (XEXP (src, 0)), ok = 1; |
bb22893c JW |
2929 | else if (GET_CODE (src) == PLUS |
2930 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2931 | && XEXP (src, 0) == ep->to_rtx) | |
2932 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
8026ebba ILT |
2933 | else if ((prev_insn = prev_nonnote_insn (insn)) != 0 |
2934 | && (prev_set = single_set (prev_insn)) != 0 | |
2935 | && rtx_equal_p (SET_DEST (prev_set), src)) | |
2936 | { | |
2937 | src = SET_SRC (prev_set); | |
2938 | if (src == ep->to_rtx) | |
2939 | offset = 0, ok = 1; | |
2940 | else if (GET_CODE (src) == PLUS | |
2941 | && GET_CODE (XEXP (src, 0)) == CONST_INT | |
2942 | && XEXP (src, 1) == ep->to_rtx) | |
2943 | offset = INTVAL (XEXP (src, 0)), ok = 1; | |
2944 | else if (GET_CODE (src) == PLUS | |
2945 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2946 | && XEXP (src, 0) == ep->to_rtx) | |
2947 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
2948 | } | |
dd1eab0a RK |
2949 | |
2950 | if (ok) | |
2951 | { | |
c77fbfbe GK |
2952 | rtx src |
2953 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
2954 | ||
2955 | new_body = old_body; | |
2956 | if (! replace) | |
2957 | { | |
2958 | new_body = copy_insn (old_body); | |
2959 | if (REG_NOTES (insn)) | |
2960 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
2961 | } | |
2962 | PATTERN (insn) = new_body; | |
2963 | old_set = single_set (insn); | |
2964 | ||
2965 | /* First see if this insn remains valid when we | |
2966 | make the change. If not, keep the INSN_CODE | |
2967 | the same and let reload fit it up. */ | |
2968 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
2969 | validate_change (insn, &SET_DEST (old_set), | |
2970 | ep->to_rtx, 1); | |
2971 | if (! apply_change_group ()) | |
dd1eab0a | 2972 | { |
c77fbfbe GK |
2973 | SET_SRC (old_set) = src; |
2974 | SET_DEST (old_set) = ep->to_rtx; | |
dd1eab0a RK |
2975 | } |
2976 | ||
2977 | val = 1; | |
2978 | goto done; | |
2979 | } | |
2980 | } | |
2981 | #endif | |
2982 | ||
32131a9c RK |
2983 | /* In this case this insn isn't serving a useful purpose. We |
2984 | will delete it in reload_as_needed once we know that this | |
2985 | elimination is, in fact, being done. | |
2986 | ||
abc95ed3 | 2987 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
2988 | process it since it won't be used unless something changes. */ |
2989 | if (replace) | |
8a34409d | 2990 | { |
1d7254c5 | 2991 | delete_dead_insn (insn); |
8a34409d RH |
2992 | return 1; |
2993 | } | |
32131a9c RK |
2994 | val = 1; |
2995 | goto done; | |
2996 | } | |
aa5524a9 | 2997 | } |
32131a9c | 2998 | |
aa5524a9 BS |
2999 | /* We allow one special case which happens to work on all machines we |
3000 | currently support: a single set with the source being a PLUS of an | |
3001 | eliminable register and a constant. */ | |
3002 | if (old_set | |
1abdf5e7 | 3003 | && GET_CODE (SET_DEST (old_set)) == REG |
aa5524a9 BS |
3004 | && GET_CODE (SET_SRC (old_set)) == PLUS |
3005 | && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG | |
3006 | && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT | |
3007 | && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) | |
3008 | { | |
3009 | rtx reg = XEXP (SET_SRC (old_set), 0); | |
3010 | int offset = INTVAL (XEXP (SET_SRC (old_set), 1)); | |
32131a9c | 3011 | |
aa5524a9 BS |
3012 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3013 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3014 | { | |
3015 | offset += ep->offset; | |
32131a9c | 3016 | |
aa5524a9 BS |
3017 | if (offset == 0) |
3018 | { | |
f34c06e5 R |
3019 | int num_clobbers; |
3020 | /* We assume here that if we need a PARALLEL with | |
3021 | CLOBBERs for this assignment, we can do with the | |
3022 | MATCH_SCRATCHes that add_clobbers allocates. | |
3023 | There's not much we can do if that doesn't work. */ | |
aa5524a9 BS |
3024 | PATTERN (insn) = gen_rtx_SET (VOIDmode, |
3025 | SET_DEST (old_set), | |
3026 | ep->to_rtx); | |
f34c06e5 R |
3027 | num_clobbers = 0; |
3028 | INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers); | |
3029 | if (num_clobbers) | |
3030 | { | |
3031 | rtvec vec = rtvec_alloc (num_clobbers + 1); | |
3032 | ||
3033 | vec->elem[0] = PATTERN (insn); | |
3034 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); | |
3035 | add_clobbers (PATTERN (insn), INSN_CODE (insn)); | |
3036 | } | |
aa5524a9 BS |
3037 | if (INSN_CODE (insn) < 0) |
3038 | abort (); | |
3039 | } | |
3040 | else | |
3041 | { | |
3042 | new_body = old_body; | |
3043 | if (! replace) | |
3044 | { | |
3045 | new_body = copy_insn (old_body); | |
3046 | if (REG_NOTES (insn)) | |
3047 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3048 | } | |
3049 | PATTERN (insn) = new_body; | |
3050 | old_set = single_set (insn); | |
922d9d40 | 3051 | |
aa5524a9 BS |
3052 | XEXP (SET_SRC (old_set), 0) = ep->to_rtx; |
3053 | XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); | |
3054 | } | |
3055 | val = 1; | |
3056 | /* This can't have an effect on elimination offsets, so skip right | |
3057 | to the end. */ | |
3058 | goto done; | |
3059 | } | |
32131a9c RK |
3060 | } |
3061 | ||
dfac187e BS |
3062 | /* Determine the effects of this insn on elimination offsets. */ |
3063 | elimination_effects (old_body, 0); | |
3064 | ||
3065 | /* Eliminate all eliminable registers occurring in operands that | |
3066 | can be handled by reload. */ | |
3067 | extract_insn (insn); | |
3068 | any_changes = 0; | |
3069 | for (i = 0; i < recog_data.n_operands; i++) | |
3070 | { | |
3071 | orig_operand[i] = recog_data.operand[i]; | |
3072 | substed_operand[i] = recog_data.operand[i]; | |
3073 | ||
3074 | /* For an asm statement, every operand is eliminable. */ | |
3075 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3076 | { | |
3077 | /* Check for setting a register that we know about. */ | |
3078 | if (recog_data.operand_type[i] != OP_IN | |
3079 | && GET_CODE (orig_operand[i]) == REG) | |
3080 | { | |
3081 | /* If we are assigning to a register that can be eliminated, it | |
3082 | must be as part of a PARALLEL, since the code above handles | |
3083 | single SETs. We must indicate that we can no longer | |
3084 | eliminate this reg. */ | |
3085 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3086 | ep++) | |
3087 | if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) | |
3088 | ep->can_eliminate = 0; | |
3089 | } | |
3090 | ||
3091 | substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, | |
3092 | replace ? insn : NULL_RTX); | |
3093 | if (substed_operand[i] != orig_operand[i]) | |
3094 | val = any_changes = 1; | |
3095 | /* Terminate the search in check_eliminable_occurrences at | |
3096 | this point. */ | |
3097 | *recog_data.operand_loc[i] = 0; | |
3098 | ||
3099 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3100 | insn, write a CLOBBER insn. */ | |
3101 | if (recog_data.operand_type[i] != OP_IN | |
3102 | && GET_CODE (orig_operand[i]) == REG | |
3103 | && GET_CODE (substed_operand[i]) == MEM | |
3104 | && replace) | |
3105 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3106 | insn); | |
3107 | } | |
3108 | } | |
3109 | ||
3110 | for (i = 0; i < recog_data.n_dups; i++) | |
3111 | *recog_data.dup_loc[i] | |
1d7254c5 | 3112 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3113 | |
3114 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3115 | check_eliminable_occurrences (old_body); | |
32131a9c | 3116 | |
dfac187e BS |
3117 | /* Substitute the operands; the new values are in the substed_operand |
3118 | array. */ | |
3119 | for (i = 0; i < recog_data.n_operands; i++) | |
3120 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3121 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3122 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3123 | |
dfac187e | 3124 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3125 | re-recognize the insn. We do this in case we had a simple addition |
3126 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3127 | common case. |
3128 | If re-recognition fails, the old insn code number will still be used, | |
3129 | and some register operands may have changed into PLUS expressions. | |
3130 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3131 | again. */ |
32131a9c | 3132 | |
dfac187e | 3133 | if (val) |
32131a9c | 3134 | { |
7c791b13 RK |
3135 | /* If we aren't replacing things permanently and we changed something, |
3136 | make another copy to ensure that all the RTL is new. Otherwise | |
3137 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3138 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3139 | new_body = old_body; |
3140 | if (! replace) | |
1b3b5765 BS |
3141 | { |
3142 | new_body = copy_insn (old_body); | |
3143 | if (REG_NOTES (insn)) | |
3144 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3145 | } | |
dfac187e | 3146 | PATTERN (insn) = new_body; |
7c791b13 | 3147 | |
774672d2 RK |
3148 | /* If we had a move insn but now we don't, rerecognize it. This will |
3149 | cause spurious re-recognition if the old move had a PARALLEL since | |
3150 | the new one still will, but we can't call single_set without | |
3151 | having put NEW_BODY into the insn and the re-recognition won't | |
3152 | hurt in this rare case. */ | |
dfac187e BS |
3153 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3154 | thing always? */ | |
3155 | if (! insn_is_asm | |
3156 | && old_set != 0 | |
774672d2 RK |
3157 | && ((GET_CODE (SET_SRC (old_set)) == REG |
3158 | && (GET_CODE (new_body) != SET | |
3159 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3160 | /* If this was a load from or store to memory, compare | |
1ccbefce RH |
3161 | the MEM in recog_data.operand to the one in the insn. |
3162 | If they are not equal, then rerecognize the insn. */ | |
774672d2 RK |
3163 | || (old_set != 0 |
3164 | && ((GET_CODE (SET_SRC (old_set)) == MEM | |
1ccbefce | 3165 | && SET_SRC (old_set) != recog_data.operand[1]) |
774672d2 | 3166 | || (GET_CODE (SET_DEST (old_set)) == MEM |
1ccbefce | 3167 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3168 | /* If this was an add insn before, rerecognize. */ |
3169 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3170 | { |
dfac187e BS |
3171 | int new_icode = recog (PATTERN (insn), insn, 0); |
3172 | if (new_icode < 0) | |
3173 | INSN_CODE (insn) = icode; | |
4a5d0fb5 | 3174 | } |
dfac187e | 3175 | } |
32131a9c | 3176 | |
dfac187e BS |
3177 | /* Restore the old body. If there were any changes to it, we made a copy |
3178 | of it while the changes were still in place, so we'll correctly return | |
3179 | a modified insn below. */ | |
3180 | if (! replace) | |
3181 | { | |
3182 | /* Restore the old body. */ | |
3183 | for (i = 0; i < recog_data.n_operands; i++) | |
3184 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3185 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3186 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3187 | } |
a8fdc208 | 3188 | |
dfac187e BS |
3189 | /* Update all elimination pairs to reflect the status after the current |
3190 | insn. The changes we make were determined by the earlier call to | |
3191 | elimination_effects. | |
a8efe40d | 3192 | |
32131a9c RK |
3193 | We also detect a cases where register elimination cannot be done, |
3194 | namely, if a register would be both changed and referenced outside a MEM | |
3195 | in the resulting insn since such an insn is often undefined and, even if | |
3196 | not, we cannot know what meaning will be given to it. Note that it is | |
3197 | valid to have a register used in an address in an insn that changes it | |
3198 | (presumably with a pre- or post-increment or decrement). | |
3199 | ||
3200 | If anything changes, return nonzero. */ | |
3201 | ||
32131a9c RK |
3202 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3203 | { | |
3204 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3205 | ep->can_eliminate = 0; | |
3206 | ||
3207 | ep->ref_outside_mem = 0; | |
3208 | ||
3209 | if (ep->previous_offset != ep->offset) | |
3210 | val = 1; | |
32131a9c RK |
3211 | } |
3212 | ||
3213 | done: | |
9faa82d8 | 3214 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3215 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3216 | to a register that we eliminate and could cause a different number | |
3217 | of spill registers to be needed in the final reload pass than in | |
3218 | the pre-passes. */ | |
20748cab | 3219 | if (val && REG_NOTES (insn) != 0) |
1914f5da | 3220 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); |
05b4c365 | 3221 | |
32131a9c RK |
3222 | return val; |
3223 | } | |
3224 | ||
cb2afeb3 R |
3225 | /* Loop through all elimination pairs. |
3226 | Recalculate the number not at initial offset. | |
3227 | ||
3228 | Compute the maximum offset (minimum offset if the stack does not | |
3229 | grow downward) for each elimination pair. */ | |
3230 | ||
3231 | static void | |
3232 | update_eliminable_offsets () | |
3233 | { | |
3234 | struct elim_table *ep; | |
3235 | ||
3236 | num_not_at_initial_offset = 0; | |
3237 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3238 | { | |
3239 | ep->previous_offset = ep->offset; | |
3240 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3241 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3242 | } |
3243 | } | |
3244 | ||
32131a9c RK |
3245 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3246 | replacement we currently believe is valid, mark it as not eliminable if X | |
3247 | modifies DEST in any way other than by adding a constant integer to it. | |
3248 | ||
3249 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3250 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3251 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3252 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3253 | frame or stack pointer. Assignments to the hard frame pointer must not |
3254 | prevent this elimination. | |
32131a9c RK |
3255 | |
3256 | Called via note_stores from reload before starting its passes to scan | |
3257 | the insns of the function. */ | |
3258 | ||
3259 | static void | |
84832317 | 3260 | mark_not_eliminable (dest, x, data) |
32131a9c RK |
3261 | rtx dest; |
3262 | rtx x; | |
84832317 | 3263 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 3264 | { |
e51712db | 3265 | register unsigned int i; |
32131a9c RK |
3266 | |
3267 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3268 | not see a SUBREG of an eliminable hard register, but check just in | |
3269 | case. */ | |
3270 | if (GET_CODE (dest) == SUBREG) | |
3271 | dest = SUBREG_REG (dest); | |
3272 | ||
3ec2ea3e | 3273 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3274 | return; |
3275 | ||
3276 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3277 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3278 | && (GET_CODE (x) != SET | |
3279 | || GET_CODE (SET_SRC (x)) != PLUS | |
3280 | || XEXP (SET_SRC (x), 0) != dest | |
3281 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3282 | { | |
3283 | reg_eliminate[i].can_eliminate_previous | |
3284 | = reg_eliminate[i].can_eliminate = 0; | |
3285 | num_eliminable--; | |
3286 | } | |
3287 | } | |
09dd1133 | 3288 | |
c47f5ea5 BS |
3289 | /* Verify that the initial elimination offsets did not change since the |
3290 | last call to set_initial_elim_offsets. This is used to catch cases | |
3291 | where something illegal happened during reload_as_needed that could | |
3292 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3293 | |
c47f5ea5 BS |
3294 | static void |
3295 | verify_initial_elim_offsets () | |
3296 | { | |
3297 | int t; | |
3298 | ||
3299 | #ifdef ELIMINABLE_REGS | |
3300 | struct elim_table *ep; | |
3301 | ||
3302 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3303 | { | |
3304 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3305 | if (t != ep->initial_offset) | |
3306 | abort (); | |
3307 | } | |
3308 | #else | |
3309 | INITIAL_FRAME_POINTER_OFFSET (t); | |
3310 | if (t != reg_eliminate[0].initial_offset) | |
3311 | abort (); | |
05d10675 | 3312 | #endif |
c47f5ea5 BS |
3313 | } |
3314 | ||
09dd1133 | 3315 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3316 | |
09dd1133 BS |
3317 | static void |
3318 | set_initial_elim_offsets () | |
3319 | { | |
1f3b1e1a | 3320 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3321 | |
3322 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3323 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3324 | { |
3325 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3326 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3327 | } |
3328 | #else | |
1f3b1e1a JL |
3329 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3330 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3331 | #endif |
3332 | ||
3333 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3334 | } |
09dd1133 | 3335 | |
1f3b1e1a JL |
3336 | /* Initialize the known label offsets. |
3337 | Set a known offset for each forced label to be at the initial offset | |
3338 | of each elimination. We do this because we assume that all | |
3339 | computed jumps occur from a location where each elimination is | |
3340 | at its initial offset. | |
3341 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3342 | |
1f3b1e1a JL |
3343 | static void |
3344 | set_initial_label_offsets () | |
3345 | { | |
3346 | rtx x; | |
961192e1 | 3347 | memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels); |
09dd1133 BS |
3348 | |
3349 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3350 | if (XEXP (x, 0)) | |
3351 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
3352 | } | |
3353 | ||
1f3b1e1a JL |
3354 | /* Set all elimination offsets to the known values for the code label given |
3355 | by INSN. */ | |
1d813780 | 3356 | |
1f3b1e1a JL |
3357 | static void |
3358 | set_offsets_for_label (insn) | |
3359 | rtx insn; | |
3360 | { | |
973838fd | 3361 | unsigned int i; |
1f3b1e1a JL |
3362 | int label_nr = CODE_LABEL_NUMBER (insn); |
3363 | struct elim_table *ep; | |
3364 | ||
3365 | num_not_at_initial_offset = 0; | |
3366 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3367 | { | |
3368 | ep->offset = ep->previous_offset = offsets_at[label_nr][i]; | |
3369 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3370 | num_not_at_initial_offset++; | |
3371 | } | |
3372 | } | |
3373 | ||
09dd1133 BS |
3374 | /* See if anything that happened changes which eliminations are valid. |
3375 | For example, on the Sparc, whether or not the frame pointer can | |
3376 | be eliminated can depend on what registers have been used. We need | |
3377 | not check some conditions again (such as flag_omit_frame_pointer) | |
3378 | since they can't have changed. */ | |
3379 | ||
3380 | static void | |
3381 | update_eliminables (pset) | |
3382 | HARD_REG_SET *pset; | |
3383 | { | |
3384 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3385 | int previous_frame_pointer_needed = frame_pointer_needed; | |
3386 | #endif | |
3387 | struct elim_table *ep; | |
3388 | ||
3389 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3390 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3391 | #ifdef ELIMINABLE_REGS | |
3392 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3393 | #endif | |
3394 | ) | |
3395 | ep->can_eliminate = 0; | |
3396 | ||
3397 | /* Look for the case where we have discovered that we can't replace | |
3398 | register A with register B and that means that we will now be | |
3399 | trying to replace register A with register C. This means we can | |
3400 | no longer replace register C with register B and we need to disable | |
3401 | such an elimination, if it exists. This occurs often with A == ap, | |
3402 | B == sp, and C == fp. */ | |
3403 | ||
3404 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3405 | { | |
3406 | struct elim_table *op; | |
3407 | register int new_to = -1; | |
3408 | ||
3409 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3410 | { | |
3411 | /* Find the current elimination for ep->from, if there is a | |
3412 | new one. */ | |
3413 | for (op = reg_eliminate; | |
3414 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3415 | if (op->from == ep->from && op->can_eliminate) | |
3416 | { | |
3417 | new_to = op->to; | |
3418 | break; | |
3419 | } | |
3420 | ||
3421 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3422 | disable it. */ | |
3423 | for (op = reg_eliminate; | |
3424 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3425 | if (op->from == new_to && op->to == ep->to) | |
3426 | op->can_eliminate = 0; | |
3427 | } | |
3428 | } | |
3429 | ||
3430 | /* See if any registers that we thought we could eliminate the previous | |
3431 | time are no longer eliminable. If so, something has changed and we | |
3432 | must spill the register. Also, recompute the number of eliminable | |
3433 | registers and see if the frame pointer is needed; it is if there is | |
3434 | no elimination of the frame pointer that we can perform. */ | |
3435 | ||
3436 | frame_pointer_needed = 1; | |
3437 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3438 | { | |
3439 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3440 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3441 | frame_pointer_needed = 0; | |
3442 | ||
3443 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3444 | { | |
3445 | ep->can_eliminate_previous = 0; | |
3446 | SET_HARD_REG_BIT (*pset, ep->from); | |
3447 | num_eliminable--; | |
3448 | } | |
3449 | } | |
3450 | ||
3451 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3452 | /* If we didn't need a frame pointer last time, but we do now, spill | |
3453 | the hard frame pointer. */ | |
3454 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3455 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
3456 | #endif | |
3457 | } | |
3458 | ||
3459 | /* Initialize the table of registers to eliminate. */ | |
1d813780 | 3460 | |
09dd1133 BS |
3461 | static void |
3462 | init_elim_table () | |
3463 | { | |
3464 | struct elim_table *ep; | |
590cf94d KG |
3465 | #ifdef ELIMINABLE_REGS |
3466 | struct elim_table_1 *ep1; | |
3467 | #endif | |
09dd1133 | 3468 | |
590cf94d | 3469 | if (!reg_eliminate) |
ad85216e | 3470 | reg_eliminate = (struct elim_table *) |
1d7254c5 | 3471 | xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); |
05d10675 | 3472 | |
09dd1133 BS |
3473 | /* Does this function require a frame pointer? */ |
3474 | ||
3475 | frame_pointer_needed = (! flag_omit_frame_pointer | |
3476 | #ifdef EXIT_IGNORE_STACK | |
3477 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
3478 | and restore sp for alloca. So we can't eliminate | |
3479 | the frame pointer in that case. At some point, | |
3480 | we should improve this by emitting the | |
3481 | sp-adjusting insns for this case. */ | |
3482 | || (current_function_calls_alloca | |
3483 | && EXIT_IGNORE_STACK) | |
3484 | #endif | |
3485 | || FRAME_POINTER_REQUIRED); | |
3486 | ||
3487 | num_eliminable = 0; | |
3488 | ||
3489 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3490 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3491 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3492 | { |
590cf94d KG |
3493 | ep->from = ep1->from; |
3494 | ep->to = ep1->to; | |
09dd1133 BS |
3495 | ep->can_eliminate = ep->can_eliminate_previous |
3496 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3497 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3498 | } | |
3499 | #else | |
590cf94d KG |
3500 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3501 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3502 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3503 | = ! frame_pointer_needed; | |
3504 | #endif | |
3505 | ||
3506 | /* Count the number of eliminable registers and build the FROM and TO | |
3507 | REG rtx's. Note that code in gen_rtx will cause, e.g., | |
3508 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. | |
3509 | We depend on this. */ | |
3510 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3511 | { | |
3512 | num_eliminable += ep->can_eliminate; | |
3513 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3514 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3515 | } | |
3516 | } | |
32131a9c RK |
3517 | \f |
3518 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3519 | |
3520 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3521 | because we found we can't eliminate some register. In the case, no pseudos | |
3522 | are allowed to be in the register, even if they are only in a block that | |
3523 | doesn't require spill registers, unlike the case when we are spilling this | |
3524 | hard reg to produce another spill register. | |
3525 | ||
3526 | Return nonzero if any pseudos needed to be kicked out. */ | |
3527 | ||
03acd8f8 | 3528 | static void |
e04ca094 | 3529 | spill_hard_reg (regno, cant_eliminate) |
770ae6cc | 3530 | unsigned int regno; |
32131a9c RK |
3531 | int cant_eliminate; |
3532 | { | |
32131a9c RK |
3533 | register int i; |
3534 | ||
9ff3516a | 3535 | if (cant_eliminate) |
03acd8f8 BS |
3536 | { |
3537 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3538 | regs_ever_live[regno] = 1; | |
3539 | } | |
9ff3516a | 3540 | |
32131a9c RK |
3541 | /* Spill every pseudo reg that was allocated to this reg |
3542 | or to something that overlaps this reg. */ | |
3543 | ||
3544 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3545 | if (reg_renumber[i] >= 0 | |
770ae6cc RK |
3546 | && (unsigned int) reg_renumber[i] <= regno |
3547 | && ((unsigned int) reg_renumber[i] | |
3548 | + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i], | |
32131a9c RK |
3549 | PSEUDO_REGNO_MODE (i)) |
3550 | > regno)) | |
f5d8c9f4 | 3551 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3552 | } |
32131a9c | 3553 | |
03acd8f8 BS |
3554 | /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET |
3555 | from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ | |
770ae6cc | 3556 | |
03acd8f8 BS |
3557 | static void |
3558 | ior_hard_reg_set (set1, set2) | |
3559 | HARD_REG_SET *set1, *set2; | |
3560 | { | |
3561 | IOR_HARD_REG_SET (*set1, *set2); | |
3562 | } | |
05d10675 | 3563 | |
03acd8f8 BS |
3564 | /* After find_reload_regs has been run for all insn that need reloads, |
3565 | and/or spill_hard_regs was called, this function is used to actually | |
3566 | spill pseudo registers and try to reallocate them. It also sets up the | |
3567 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3568 | |
03acd8f8 | 3569 | static int |
e04ca094 | 3570 | finish_spills (global) |
03acd8f8 | 3571 | int global; |
03acd8f8 BS |
3572 | { |
3573 | struct insn_chain *chain; | |
3574 | int something_changed = 0; | |
3575 | int i; | |
3576 | ||
3577 | /* Build the spill_regs array for the function. */ | |
3578 | /* If there are some registers still to eliminate and one of the spill regs | |
3579 | wasn't ever used before, additional stack space may have to be | |
3580 | allocated to store this register. Thus, we may have changed the offset | |
3581 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3582 | |
03acd8f8 BS |
3583 | One might think that we need only set VAL to 1 if this is a call-used |
3584 | register. However, the set of registers that must be saved by the | |
3585 | prologue is not identical to the call-used set. For example, the | |
3586 | register used by the call insn for the return PC is a call-used register, | |
3587 | but must be saved by the prologue. */ | |
3588 | ||
3589 | n_spills = 0; | |
3590 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3591 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3592 | { | |
3593 | spill_reg_order[i] = n_spills; | |
3594 | spill_regs[n_spills++] = i; | |
3595 | if (num_eliminable && ! regs_ever_live[i]) | |
3596 | something_changed = 1; | |
3597 | regs_ever_live[i] = 1; | |
3598 | } | |
3599 | else | |
3600 | spill_reg_order[i] = -1; | |
3601 | ||
efc9bd41 RK |
3602 | EXECUTE_IF_SET_IN_REG_SET |
3603 | (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, | |
3604 | { | |
3605 | /* Record the current hard register the pseudo is allocated to in | |
3606 | pseudo_previous_regs so we avoid reallocating it to the same | |
3607 | hard reg in a later pass. */ | |
3608 | if (reg_renumber[i] < 0) | |
3609 | abort (); | |
3610 | ||
3611 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3612 | /* Mark it as no longer having a hard register home. */ | |
3613 | reg_renumber[i] = -1; | |
3614 | /* We will need to scan everything again. */ | |
3615 | something_changed = 1; | |
3616 | }); | |
7609e720 | 3617 | |
03acd8f8 BS |
3618 | /* Retry global register allocation if possible. */ |
3619 | if (global) | |
3620 | { | |
961192e1 | 3621 | memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3622 | /* For every insn that needs reloads, set the registers used as spill |
3623 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3624 | insn. */ | |
3625 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3626 | { | |
3627 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3628 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3629 | { |
3630 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3631 | &chain->used_spill_regs); | |
3632 | }); | |
3633 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3634 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3635 | { |
3636 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3637 | &chain->used_spill_regs); | |
3638 | }); | |
3639 | } | |
7609e720 | 3640 | |
03acd8f8 BS |
3641 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3642 | various reg sets that indicate which hard regs can't be used, | |
3643 | and call retry_global_alloc. | |
05d10675 | 3644 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 BS |
3645 | get a new hard register. */ |
3646 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3647 | if (reg_old_renumber[i] != reg_renumber[i]) | |
32131a9c | 3648 | { |
03acd8f8 BS |
3649 | HARD_REG_SET forbidden; |
3650 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3651 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3652 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3653 | retry_global_alloc (i, forbidden); | |
3654 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3655 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3656 | } |
03acd8f8 | 3657 | } |
7609e720 | 3658 | |
03acd8f8 BS |
3659 | /* Fix up the register information in the insn chain. |
3660 | This involves deleting those of the spilled pseudos which did not get | |
3661 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3662 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3663 | { | |
03acd8f8 BS |
3664 | HARD_REG_SET used_by_pseudos; |
3665 | HARD_REG_SET used_by_pseudos2; | |
3666 | ||
239a0f5b BS |
3667 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3668 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3669 | |
3670 | /* Mark any unallocated hard regs as available for spills. That | |
3671 | makes inheritance work somewhat better. */ | |
3672 | if (chain->need_reload) | |
3673 | { | |
239a0f5b BS |
3674 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3675 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3676 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3677 | ||
3678 | /* Save the old value for the sanity test below. */ | |
3679 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3680 | ||
239a0f5b BS |
3681 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3682 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3683 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3684 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3685 | ||
3686 | /* Make sure we only enlarge the set. */ | |
3687 | GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); | |
3688 | abort (); | |
3689 | ok:; | |
3690 | } | |
7609e720 | 3691 | } |
03acd8f8 BS |
3692 | |
3693 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3694 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3695 | { | |
3696 | int regno = reg_renumber[i]; | |
3697 | if (reg_old_renumber[i] == regno) | |
3698 | continue; | |
05d10675 | 3699 | |
03acd8f8 BS |
3700 | alter_reg (i, reg_old_renumber[i]); |
3701 | reg_old_renumber[i] = regno; | |
e04ca094 | 3702 | if (rtl_dump_file) |
03acd8f8 BS |
3703 | { |
3704 | if (regno == -1) | |
e04ca094 | 3705 | fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 3706 | else |
e04ca094 | 3707 | fprintf (rtl_dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
3708 | i, reg_renumber[i]); |
3709 | } | |
3710 | } | |
3711 | ||
3712 | return something_changed; | |
7609e720 | 3713 | } |
32131a9c | 3714 | \f |
05d10675 | 3715 | /* Find all paradoxical subregs within X and update reg_max_ref_width. |
56f58d3a RK |
3716 | Also mark any hard registers used to store user variables as |
3717 | forbidden from being used for spill registers. */ | |
32131a9c RK |
3718 | |
3719 | static void | |
3720 | scan_paradoxical_subregs (x) | |
3721 | register rtx x; | |
3722 | { | |
3723 | register int i; | |
6f7d635c | 3724 | register const char *fmt; |
32131a9c RK |
3725 | register enum rtx_code code = GET_CODE (x); |
3726 | ||
3727 | switch (code) | |
3728 | { | |
56f58d3a | 3729 | case REG: |
03acd8f8 | 3730 | #if 0 |
e9a25f70 | 3731 | if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER |
f95182a4 | 3732 | && REG_USERVAR_P (x)) |
03acd8f8 BS |
3733 | SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); |
3734 | #endif | |
56f58d3a RK |
3735 | return; |
3736 | ||
32131a9c RK |
3737 | case CONST_INT: |
3738 | case CONST: | |
3739 | case SYMBOL_REF: | |
3740 | case LABEL_REF: | |
3741 | case CONST_DOUBLE: | |
3742 | case CC0: | |
3743 | case PC: | |
32131a9c RK |
3744 | case USE: |
3745 | case CLOBBER: | |
3746 | return; | |
3747 | ||
3748 | case SUBREG: | |
3749 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3750 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3751 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3752 | = GET_MODE_SIZE (GET_MODE (x)); | |
3753 | return; | |
05d10675 | 3754 | |
e9a25f70 JL |
3755 | default: |
3756 | break; | |
32131a9c RK |
3757 | } |
3758 | ||
3759 | fmt = GET_RTX_FORMAT (code); | |
3760 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3761 | { | |
3762 | if (fmt[i] == 'e') | |
3763 | scan_paradoxical_subregs (XEXP (x, i)); | |
3764 | else if (fmt[i] == 'E') | |
3765 | { | |
3766 | register int j; | |
1d7254c5 | 3767 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
3768 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
3769 | } | |
3770 | } | |
3771 | } | |
3772 | \f | |
32131a9c RK |
3773 | /* Reload pseudo-registers into hard regs around each insn as needed. |
3774 | Additional register load insns are output before the insn that needs it | |
3775 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3776 | ||
3777 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3778 | which registers are already available in reload registers. |
32131a9c RK |
3779 | We update these for the reloads that we perform, |
3780 | as the insns are scanned. */ | |
3781 | ||
3782 | static void | |
e04ca094 | 3783 | reload_as_needed (live_known) |
32131a9c RK |
3784 | int live_known; |
3785 | { | |
7609e720 | 3786 | struct insn_chain *chain; |
553687c9 | 3787 | #if defined (AUTO_INC_DEC) |
32131a9c | 3788 | register int i; |
973838fd | 3789 | #endif |
32131a9c | 3790 | rtx x; |
32131a9c | 3791 | |
961192e1 JM |
3792 | memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx); |
3793 | memset ((char *) spill_reg_store, 0, sizeof spill_reg_store); | |
ff154f78 MM |
3794 | reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
3795 | reg_has_output_reload = (char *) xmalloc (max_regno); | |
e6e52be0 | 3796 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c | 3797 | |
1f3b1e1a | 3798 | set_initial_elim_offsets (); |
32131a9c | 3799 | |
7609e720 | 3800 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 3801 | { |
03acd8f8 | 3802 | rtx prev; |
7609e720 BS |
3803 | rtx insn = chain->insn; |
3804 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
3805 | |
3806 | /* If we pass a label, copy the offsets from the label information | |
3807 | into the current offsets of each elimination. */ | |
3808 | if (GET_CODE (insn) == CODE_LABEL) | |
1f3b1e1a | 3809 | set_offsets_for_label (insn); |
32131a9c | 3810 | |
2c3c49de | 3811 | else if (INSN_P (insn)) |
32131a9c | 3812 | { |
0639444f | 3813 | rtx oldpat = PATTERN (insn); |
32131a9c | 3814 | |
2758481d RS |
3815 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3816 | references to eliminable registers have been removed. */ | |
3817 | ||
3818 | if ((GET_CODE (PATTERN (insn)) == USE | |
3819 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3820 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3821 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3822 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 3823 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 3824 | NULL_RTX); |
2758481d | 3825 | |
32131a9c RK |
3826 | /* If we need to do register elimination processing, do so. |
3827 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 3828 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
3829 | { |
3830 | eliminate_regs_in_insn (insn, 1); | |
3831 | if (GET_CODE (insn) == NOTE) | |
cb2afeb3 R |
3832 | { |
3833 | update_eliminable_offsets (); | |
3834 | continue; | |
3835 | } | |
32131a9c RK |
3836 | } |
3837 | ||
7609e720 BS |
3838 | /* If need_elim is nonzero but need_reload is zero, one might think |
3839 | that we could simply set n_reloads to 0. However, find_reloads | |
3840 | could have done some manipulation of the insn (such as swapping | |
3841 | commutative operands), and these manipulations are lost during | |
3842 | the first pass for every insn that needs register elimination. | |
3843 | So the actions of find_reloads must be redone here. */ | |
3844 | ||
03acd8f8 BS |
3845 | if (! chain->need_elim && ! chain->need_reload |
3846 | && ! chain->need_operand_change) | |
32131a9c RK |
3847 | n_reloads = 0; |
3848 | /* First find the pseudo regs that must be reloaded for this insn. | |
3849 | This info is returned in the tables reload_... (see reload.h). | |
3850 | Also modify the body of INSN by substituting RELOAD | |
3851 | rtx's for those pseudo regs. */ | |
3852 | else | |
3853 | { | |
961192e1 | 3854 | memset (reg_has_output_reload, 0, max_regno); |
32131a9c RK |
3855 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
3856 | ||
3857 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3858 | spill_reg_order); | |
3859 | } | |
3860 | ||
3861 | if (n_reloads > 0) | |
3862 | { | |
cb2afeb3 | 3863 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 3864 | rtx p; |
32131a9c | 3865 | |
cb2afeb3 R |
3866 | prev = PREV_INSN (insn); |
3867 | ||
32131a9c RK |
3868 | /* Now compute which reload regs to reload them into. Perhaps |
3869 | reusing reload regs from previous insns, or else output | |
3870 | load insns to reload them. Maybe output store insns too. | |
3871 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 3872 | choose_reload_regs (chain); |
32131a9c | 3873 | |
05d10675 | 3874 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
3875 | increasing the number of spill registers needed but now |
3876 | discover can be safely merged. */ | |
f95182a4 ILT |
3877 | if (SMALL_REGISTER_CLASSES) |
3878 | merge_assigned_reloads (insn); | |
546b63fb | 3879 | |
32131a9c RK |
3880 | /* Generate the insns to reload operands into or out of |
3881 | their reload regs. */ | |
e04ca094 | 3882 | emit_reload_insns (chain); |
32131a9c RK |
3883 | |
3884 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3885 | into the insn's body (or perhaps into the bodies of other | |
3886 | load and store insn that we just made for reloading | |
3887 | and that we moved the structure into). */ | |
f759eb8b | 3888 | subst_reloads (insn); |
3c3eeea6 RK |
3889 | |
3890 | /* If this was an ASM, make sure that all the reload insns | |
3891 | we have generated are valid. If not, give an error | |
3892 | and delete them. */ | |
3893 | ||
3894 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3895 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 3896 | if (p != insn && INSN_P (p) |
3c3eeea6 | 3897 | && (recog_memoized (p) < 0 |
0eadeb15 | 3898 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
3899 | { |
3900 | error_for_asm (insn, | |
3901 | "`asm' operand requires impossible reload"); | |
ca6c03ca | 3902 | delete_insn (p); |
3c3eeea6 | 3903 | } |
32131a9c | 3904 | } |
5d7ef82a BS |
3905 | |
3906 | if (num_eliminable && chain->need_elim) | |
3907 | update_eliminable_offsets (); | |
3908 | ||
32131a9c RK |
3909 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
3910 | is no longer validly lying around to save a future reload. | |
3911 | Note that this does not detect pseudos that were reloaded | |
3912 | for this insn in order to be stored in | |
3913 | (obeying register constraints). That is correct; such reload | |
3914 | registers ARE still valid. */ | |
84832317 | 3915 | note_stores (oldpat, forget_old_reloads_1, NULL); |
32131a9c RK |
3916 | |
3917 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3918 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 3919 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
32131a9c | 3920 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 3921 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
3922 | |
3923 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
3924 | /* Likewise for regs altered by auto-increment in this insn. |
3925 | REG_INC notes have been changed by reloading: | |
3926 | find_reloads_address_1 records substitutions for them, | |
3927 | which have been performed by subst_reloads above. */ | |
3928 | for (i = n_reloads - 1; i >= 0; i--) | |
3929 | { | |
eceef4c9 | 3930 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
3931 | if (in_reg) |
3932 | { | |
3933 | enum rtx_code code = GET_CODE (in_reg); | |
3934 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
3935 | with the same value as the stack slot, but that doesn't | |
3936 | hold true for POST_INC / POST_DEC. Either we have to | |
3937 | convert the memory access to a true POST_INC / POST_DEC, | |
3938 | or we can't use the reload register for inheritance. */ | |
3939 | if ((code == POST_INC || code == POST_DEC) | |
3940 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3941 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
3942 | /* Make sure it is the inc/dec pseudo, and not |
3943 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3944 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 3945 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 3946 | |
cb2afeb3 | 3947 | { |
eceef4c9 | 3948 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
3949 | enum machine_mode mode = GET_MODE (reload_reg); |
3950 | int n = 0; | |
3951 | rtx p; | |
3952 | ||
3953 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
3954 | { | |
3955 | /* We really want to ignore REG_INC notes here, so | |
3956 | use PATTERN (p) as argument to reg_set_p . */ | |
3957 | if (reg_set_p (reload_reg, PATTERN (p))) | |
3958 | break; | |
4b983fdc | 3959 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
3960 | if (! n) |
3961 | continue; | |
3962 | if (n == 1) | |
f67c2384 JL |
3963 | { |
3964 | n = validate_replace_rtx (reload_reg, | |
3965 | gen_rtx (code, mode, | |
3966 | reload_reg), | |
3967 | p); | |
3968 | ||
3969 | /* We must also verify that the constraints | |
3970 | are met after the replacement. */ | |
3971 | extract_insn (p); | |
3972 | if (n) | |
3973 | n = constrain_operands (1); | |
3974 | else | |
3975 | break; | |
3976 | ||
3977 | /* If the constraints were not met, then | |
3978 | undo the replacement. */ | |
3979 | if (!n) | |
3980 | { | |
3981 | validate_replace_rtx (gen_rtx (code, mode, | |
3982 | reload_reg), | |
3983 | reload_reg, p); | |
3984 | break; | |
3985 | } | |
05d10675 | 3986 | |
f67c2384 | 3987 | } |
cb2afeb3 R |
3988 | break; |
3989 | } | |
3990 | if (n == 1) | |
02eb1393 R |
3991 | { |
3992 | REG_NOTES (p) | |
3993 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
3994 | REG_NOTES (p)); | |
3995 | /* Mark this as having an output reload so that the | |
3996 | REG_INC processing code below won't invalidate | |
3997 | the reload for inheritance. */ | |
3998 | SET_HARD_REG_BIT (reg_is_output_reload, | |
3999 | REGNO (reload_reg)); | |
4000 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; | |
4001 | } | |
cb2afeb3 | 4002 | else |
1d7254c5 | 4003 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 4004 | NULL); |
cb2afeb3 | 4005 | } |
02eb1393 R |
4006 | else if ((code == PRE_INC || code == PRE_DEC) |
4007 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4008 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
4009 | /* Make sure it is the inc/dec pseudo, and not |
4010 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 4011 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
4012 | == REGNO (XEXP (in_reg, 0)))) |
4013 | { | |
4014 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 4015 | REGNO (rld[i].reg_rtx)); |
02eb1393 R |
4016 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; |
4017 | } | |
cb2afeb3 R |
4018 | } |
4019 | } | |
02eb1393 R |
4020 | /* If a pseudo that got a hard register is auto-incremented, |
4021 | we must purge records of copying it into pseudos without | |
4022 | hard registers. */ | |
32131a9c RK |
4023 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4024 | if (REG_NOTE_KIND (x) == REG_INC) | |
4025 | { | |
4026 | /* See if this pseudo reg was reloaded in this insn. | |
4027 | If so, its last-reload info is still valid | |
4028 | because it is based on this insn's reload. */ | |
4029 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 4030 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
4031 | break; |
4032 | ||
08fb99fa | 4033 | if (i == n_reloads) |
84832317 | 4034 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
4035 | } |
4036 | #endif | |
4037 | } | |
4038 | /* A reload reg's contents are unknown after a label. */ | |
4039 | if (GET_CODE (insn) == CODE_LABEL) | |
e6e52be0 | 4040 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
4041 | |
4042 | /* Don't assume a reload reg is still good after a call insn | |
4043 | if it is a call-used reg. */ | |
546b63fb | 4044 | else if (GET_CODE (insn) == CALL_INSN) |
e6e52be0 | 4045 | AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set); |
32131a9c | 4046 | } |
ff154f78 MM |
4047 | |
4048 | /* Clean up. */ | |
4049 | free (reg_last_reload_reg); | |
4050 | free (reg_has_output_reload); | |
32131a9c RK |
4051 | } |
4052 | ||
4053 | /* Discard all record of any value reloaded from X, | |
4054 | or reloaded in X from someplace else; | |
4055 | unless X is an output reload reg of the current insn. | |
4056 | ||
4057 | X may be a hard reg (the reload reg) | |
4058 | or it may be a pseudo reg that was reloaded from. */ | |
4059 | ||
4060 | static void | |
84832317 | 4061 | forget_old_reloads_1 (x, ignored, data) |
32131a9c | 4062 | rtx x; |
487a6e06 | 4063 | rtx ignored ATTRIBUTE_UNUSED; |
84832317 | 4064 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 4065 | { |
770ae6cc RK |
4066 | unsigned int regno; |
4067 | unsigned int nr; | |
0a2e51a9 RS |
4068 | int offset = 0; |
4069 | ||
ddef6bc7 JJ |
4070 | /* note_stores does give us subregs of hard regs, |
4071 | subreg_regno_offset will abort if it is not a hard reg. */ | |
0a2e51a9 RS |
4072 | while (GET_CODE (x) == SUBREG) |
4073 | { | |
ddef6bc7 JJ |
4074 | offset += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
4075 | GET_MODE (SUBREG_REG (x)), | |
4076 | SUBREG_BYTE (x), | |
4077 | GET_MODE (x)); | |
0a2e51a9 RS |
4078 | x = SUBREG_REG (x); |
4079 | } | |
32131a9c RK |
4080 | |
4081 | if (GET_CODE (x) != REG) | |
4082 | return; | |
4083 | ||
0a2e51a9 | 4084 | regno = REGNO (x) + offset; |
32131a9c RK |
4085 | |
4086 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4087 | nr = 1; | |
4088 | else | |
4089 | { | |
770ae6cc RK |
4090 | unsigned int i; |
4091 | ||
32131a9c RK |
4092 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
4093 | /* Storing into a spilled-reg invalidates its contents. | |
4094 | This can happen if a block-local pseudo is allocated to that reg | |
4095 | and it wasn't spilled because this block's total need is 0. | |
4096 | Then some insn might have an optional reload and use this reg. */ | |
4097 | for (i = 0; i < nr; i++) | |
e6e52be0 R |
4098 | /* But don't do this if the reg actually serves as an output |
4099 | reload reg in the current instruction. */ | |
4100 | if (n_reloads == 0 | |
4101 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
5d77a50c BS |
4102 | { |
4103 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
4104 | spill_reg_store[regno + i] = 0; | |
4105 | } | |
32131a9c RK |
4106 | } |
4107 | ||
4108 | /* Since value of X has changed, | |
4109 | forget any value previously copied from it. */ | |
4110 | ||
4111 | while (nr-- > 0) | |
4112 | /* But don't forget a copy if this is the output reload | |
4113 | that establishes the copy's validity. */ | |
4114 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
4115 | reg_last_reload_reg[regno + nr] = 0; | |
4116 | } | |
4117 | \f | |
32131a9c RK |
4118 | /* The following HARD_REG_SETs indicate when each hard register is |
4119 | used for a reload of various parts of the current insn. */ | |
4120 | ||
9e3a9cf2 BS |
4121 | /* If reg is unavailable for all reloads. */ |
4122 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4123 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4124 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4125 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4126 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4127 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4128 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4129 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4130 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4131 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4132 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4133 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4134 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4135 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4136 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4137 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4138 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4139 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4140 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4141 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4142 | static HARD_REG_SET reload_reg_used_in_insn; | |
4143 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4144 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4145 | |
4146 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4147 | static HARD_REG_SET reload_reg_used_at_all; | |
4148 | ||
be7ae2a4 RK |
4149 | /* If reg is use as an inherited reload. We just mark the first register |
4150 | in the group. */ | |
4151 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4152 | ||
f1db3576 JL |
4153 | /* Records which hard regs are used in any way, either as explicit use or |
4154 | by being allocated to a pseudo during any point of the current insn. */ | |
4155 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4156 | |
546b63fb RK |
4157 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4158 | TYPE. MODE is used to indicate how many consecutive regs are | |
4159 | actually used. */ | |
32131a9c RK |
4160 | |
4161 | static void | |
546b63fb | 4162 | mark_reload_reg_in_use (regno, opnum, type, mode) |
770ae6cc | 4163 | unsigned int regno; |
546b63fb RK |
4164 | int opnum; |
4165 | enum reload_type type; | |
32131a9c RK |
4166 | enum machine_mode mode; |
4167 | { | |
770ae6cc RK |
4168 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4169 | unsigned int i; | |
32131a9c RK |
4170 | |
4171 | for (i = regno; i < nregs + regno; i++) | |
4172 | { | |
546b63fb | 4173 | switch (type) |
32131a9c RK |
4174 | { |
4175 | case RELOAD_OTHER: | |
4176 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4177 | break; | |
4178 | ||
546b63fb RK |
4179 | case RELOAD_FOR_INPUT_ADDRESS: |
4180 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4181 | break; |
4182 | ||
47c8cf91 ILT |
4183 | case RELOAD_FOR_INPADDR_ADDRESS: |
4184 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4185 | break; | |
4186 | ||
546b63fb RK |
4187 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4188 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4189 | break; |
4190 | ||
47c8cf91 ILT |
4191 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4192 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4193 | break; | |
4194 | ||
32131a9c RK |
4195 | case RELOAD_FOR_OPERAND_ADDRESS: |
4196 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4197 | break; | |
4198 | ||
893bc853 RK |
4199 | case RELOAD_FOR_OPADDR_ADDR: |
4200 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4201 | break; | |
4202 | ||
546b63fb RK |
4203 | case RELOAD_FOR_OTHER_ADDRESS: |
4204 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4205 | break; | |
4206 | ||
32131a9c | 4207 | case RELOAD_FOR_INPUT: |
546b63fb | 4208 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4209 | break; |
4210 | ||
4211 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4212 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4213 | break; | |
4214 | ||
4215 | case RELOAD_FOR_INSN: | |
4216 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4217 | break; |
4218 | } | |
4219 | ||
4220 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4221 | } | |
4222 | } | |
4223 | ||
be7ae2a4 RK |
4224 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4225 | ||
4226 | static void | |
4227 | clear_reload_reg_in_use (regno, opnum, type, mode) | |
770ae6cc | 4228 | unsigned int regno; |
be7ae2a4 RK |
4229 | int opnum; |
4230 | enum reload_type type; | |
4231 | enum machine_mode mode; | |
4232 | { | |
770ae6cc RK |
4233 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4234 | unsigned int start_regno, end_regno, r; | |
be7ae2a4 | 4235 | int i; |
cb2afeb3 R |
4236 | /* A complication is that for some reload types, inheritance might |
4237 | allow multiple reloads of the same types to share a reload register. | |
4238 | We set check_opnum if we have to check only reloads with the same | |
4239 | operand number, and check_any if we have to check all reloads. */ | |
4240 | int check_opnum = 0; | |
4241 | int check_any = 0; | |
4242 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4243 | |
cb2afeb3 | 4244 | switch (type) |
be7ae2a4 | 4245 | { |
cb2afeb3 R |
4246 | case RELOAD_OTHER: |
4247 | used_in_set = &reload_reg_used; | |
4248 | break; | |
be7ae2a4 | 4249 | |
cb2afeb3 R |
4250 | case RELOAD_FOR_INPUT_ADDRESS: |
4251 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4252 | break; | |
be7ae2a4 | 4253 | |
cb2afeb3 R |
4254 | case RELOAD_FOR_INPADDR_ADDRESS: |
4255 | check_opnum = 1; | |
4256 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4257 | break; | |
47c8cf91 | 4258 | |
cb2afeb3 R |
4259 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4260 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4261 | break; | |
be7ae2a4 | 4262 | |
cb2afeb3 R |
4263 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4264 | check_opnum = 1; | |
4265 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4266 | break; | |
47c8cf91 | 4267 | |
cb2afeb3 R |
4268 | case RELOAD_FOR_OPERAND_ADDRESS: |
4269 | used_in_set = &reload_reg_used_in_op_addr; | |
4270 | break; | |
be7ae2a4 | 4271 | |
cb2afeb3 R |
4272 | case RELOAD_FOR_OPADDR_ADDR: |
4273 | check_any = 1; | |
4274 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4275 | break; | |
893bc853 | 4276 | |
cb2afeb3 R |
4277 | case RELOAD_FOR_OTHER_ADDRESS: |
4278 | used_in_set = &reload_reg_used_in_other_addr; | |
4279 | check_any = 1; | |
4280 | break; | |
be7ae2a4 | 4281 | |
cb2afeb3 R |
4282 | case RELOAD_FOR_INPUT: |
4283 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4284 | break; | |
be7ae2a4 | 4285 | |
cb2afeb3 R |
4286 | case RELOAD_FOR_OUTPUT: |
4287 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4288 | break; | |
be7ae2a4 | 4289 | |
cb2afeb3 R |
4290 | case RELOAD_FOR_INSN: |
4291 | used_in_set = &reload_reg_used_in_insn; | |
4292 | break; | |
4293 | default: | |
4294 | abort (); | |
4295 | } | |
4296 | /* We resolve conflicts with remaining reloads of the same type by | |
4297 | excluding the intervals of of reload registers by them from the | |
4298 | interval of freed reload registers. Since we only keep track of | |
4299 | one set of interval bounds, we might have to exclude somewhat | |
4300 | more then what would be necessary if we used a HARD_REG_SET here. | |
4301 | But this should only happen very infrequently, so there should | |
4302 | be no reason to worry about it. */ | |
05d10675 | 4303 | |
cb2afeb3 R |
4304 | start_regno = regno; |
4305 | end_regno = regno + nregs; | |
4306 | if (check_opnum || check_any) | |
4307 | { | |
4308 | for (i = n_reloads - 1; i >= 0; i--) | |
4309 | { | |
eceef4c9 BS |
4310 | if (rld[i].when_needed == type |
4311 | && (check_any || rld[i].opnum == opnum) | |
4312 | && rld[i].reg_rtx) | |
cb2afeb3 | 4313 | { |
770ae6cc RK |
4314 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4315 | unsigned int conflict_end | |
cb2afeb3 | 4316 | = (conflict_start |
8ec450a4 | 4317 | + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); |
cb2afeb3 R |
4318 | |
4319 | /* If there is an overlap with the first to-be-freed register, | |
4320 | adjust the interval start. */ | |
4321 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4322 | start_regno = conflict_end; | |
4323 | /* Otherwise, if there is a conflict with one of the other | |
4324 | to-be-freed registers, adjust the interval end. */ | |
4325 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4326 | end_regno = conflict_start; | |
4327 | } | |
be7ae2a4 RK |
4328 | } |
4329 | } | |
770ae6cc RK |
4330 | |
4331 | for (r = start_regno; r < end_regno; r++) | |
4332 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4333 | } |
4334 | ||
32131a9c | 4335 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4336 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4337 | |
4338 | static int | |
546b63fb | 4339 | reload_reg_free_p (regno, opnum, type) |
770ae6cc | 4340 | unsigned int regno; |
546b63fb RK |
4341 | int opnum; |
4342 | enum reload_type type; | |
32131a9c | 4343 | { |
546b63fb RK |
4344 | int i; |
4345 | ||
2edc8d65 | 4346 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4347 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4348 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4349 | return 0; |
546b63fb RK |
4350 | |
4351 | switch (type) | |
32131a9c RK |
4352 | { |
4353 | case RELOAD_OTHER: | |
2edc8d65 RK |
4354 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4355 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 RK |
4356 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4357 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4358 | return 0; | |
4359 | ||
4360 | for (i = 0; i < reload_n_operands; i++) | |
4361 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4362 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4363 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4364 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4365 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4366 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4367 | return 0; | |
4368 | ||
4369 | return 1; | |
32131a9c | 4370 | |
32131a9c | 4371 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4372 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4373 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4374 | return 0; | |
4375 | ||
893bc853 RK |
4376 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4377 | return 0; | |
4378 | ||
546b63fb RK |
4379 | /* If it is used for some other input, can't use it. */ |
4380 | for (i = 0; i < reload_n_operands; i++) | |
4381 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4382 | return 0; | |
4383 | ||
4384 | /* If it is used in a later operand's address, can't use it. */ | |
4385 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4386 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4387 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4388 | return 0; |
4389 | ||
4390 | return 1; | |
4391 | ||
4392 | case RELOAD_FOR_INPUT_ADDRESS: | |
4393 | /* Can't use a register if it is used for an input address for this | |
4394 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4395 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4396 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4397 | return 0; | |
4398 | ||
4399 | for (i = 0; i < opnum; i++) | |
4400 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4401 | return 0; | |
4402 | ||
4403 | return 1; | |
4404 | ||
4405 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4406 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4407 | for this operand or used as an input in an earlier |
4408 | one. */ | |
47c8cf91 | 4409 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4410 | return 0; |
4411 | ||
4412 | for (i = 0; i < opnum; i++) | |
4413 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4414 | return 0; | |
4415 | ||
4416 | return 1; | |
4417 | ||
4418 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4419 | /* Can't use a register if it is used for an output address for this | |
d1d18b46 DJ |
4420 | operand or used as an output in this or a later operand. Note |
4421 | that multiple output operands are emitted in reverse order, so | |
4422 | the conflicting ones are those with lower indices. */ | |
546b63fb RK |
4423 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4424 | return 0; | |
4425 | ||
d1d18b46 | 4426 | for (i = 0; i <= opnum; i++) |
546b63fb RK |
4427 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4428 | return 0; | |
4429 | ||
4430 | return 1; | |
4431 | ||
47c8cf91 ILT |
4432 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4433 | /* Can't use a register if it is used for an output address | |
05d10675 | 4434 | for this operand or used as an output in this or a |
d1d18b46 DJ |
4435 | later operand. Note that multiple output operands are |
4436 | emitted in reverse order, so the conflicting ones are | |
4437 | those with lower indices. */ | |
47c8cf91 ILT |
4438 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4439 | return 0; | |
4440 | ||
d1d18b46 | 4441 | for (i = 0; i <= opnum; i++) |
47c8cf91 ILT |
4442 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4443 | return 0; | |
4444 | ||
4445 | return 1; | |
4446 | ||
32131a9c | 4447 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4448 | for (i = 0; i < reload_n_operands; i++) |
4449 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4450 | return 0; | |
4451 | ||
4452 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4453 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4454 | ||
893bc853 RK |
4455 | case RELOAD_FOR_OPADDR_ADDR: |
4456 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4457 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4458 | return 0; | |
893bc853 | 4459 | |
a94ce333 | 4460 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4461 | |
32131a9c | 4462 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4463 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
d1d18b46 DJ |
4464 | outputs, or an operand address for this or an earlier output. |
4465 | Note that multiple output operands are emitted in reverse order, | |
4466 | so the conflicting ones are those with higher indices. */ | |
546b63fb RK |
4467 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4468 | return 0; | |
4469 | ||
4470 | for (i = 0; i < reload_n_operands; i++) | |
4471 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4472 | return 0; | |
4473 | ||
d1d18b46 | 4474 | for (i = opnum; i < reload_n_operands; i++) |
47c8cf91 ILT |
4475 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4476 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4477 | return 0; |
4478 | ||
4479 | return 1; | |
4480 | ||
4481 | case RELOAD_FOR_INSN: | |
4482 | for (i = 0; i < reload_n_operands; i++) | |
4483 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4484 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4485 | return 0; | |
4486 | ||
4487 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4488 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4489 | ||
4490 | case RELOAD_FOR_OTHER_ADDRESS: | |
4491 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4492 | } |
4493 | abort (); | |
4494 | } | |
4495 | ||
32131a9c | 4496 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4497 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4498 | is still available in REGNO at the end of the insn. |
4499 | ||
4500 | We can assume that the reload reg was already tested for availability | |
4501 | at the time it is needed, and we should not check this again, | |
4502 | in case the reg has already been marked in use. */ | |
4503 | ||
4504 | static int | |
546b63fb | 4505 | reload_reg_reaches_end_p (regno, opnum, type) |
770ae6cc | 4506 | unsigned int regno; |
546b63fb RK |
4507 | int opnum; |
4508 | enum reload_type type; | |
32131a9c | 4509 | { |
546b63fb RK |
4510 | int i; |
4511 | ||
4512 | switch (type) | |
32131a9c RK |
4513 | { |
4514 | case RELOAD_OTHER: | |
4515 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4516 | its value must reach the end. */ | |
4517 | return 1; | |
4518 | ||
4519 | /* If this use is for part of the insn, | |
05d10675 | 4520 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4521 | Just like the above function, don't try to do this with lots |
4522 | of fallthroughs. */ | |
4523 | ||
4524 | case RELOAD_FOR_OTHER_ADDRESS: | |
4525 | /* Here we check for everything else, since these don't conflict | |
4526 | with anything else and everything comes later. */ | |
4527 | ||
4528 | for (i = 0; i < reload_n_operands; i++) | |
4529 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4530 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4531 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4532 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4533 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4534 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4535 | return 0; | |
4536 | ||
4537 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4538 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4539 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4540 | ||
4541 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4542 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4543 | /* Similar, except that we check only for this and subsequent inputs |
4544 | and the address of only subsequent inputs and we do not need | |
4545 | to check for RELOAD_OTHER objects since they are known not to | |
4546 | conflict. */ | |
4547 | ||
4548 | for (i = opnum; i < reload_n_operands; i++) | |
4549 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4550 | return 0; | |
4551 | ||
4552 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4553 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4554 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4555 | return 0; |
4556 | ||
4557 | for (i = 0; i < reload_n_operands; i++) | |
4558 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4559 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4560 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4561 | return 0; | |
4562 | ||
893bc853 RK |
4563 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4564 | return 0; | |
4565 | ||
2af88768 GK |
4566 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4567 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4568 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 4569 | |
32131a9c | 4570 | case RELOAD_FOR_INPUT: |
546b63fb | 4571 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4572 | both input and input address and we do not check for |
546b63fb RK |
4573 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4574 | would conflict. */ | |
4575 | ||
4576 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4577 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4578 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4579 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4580 | return 0; | |
4581 | ||
0f41302f | 4582 | /* ... fall through ... */ |
546b63fb | 4583 | |
32131a9c | 4584 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4585 | /* Check outputs and their addresses. */ |
4586 | ||
4587 | for (i = 0; i < reload_n_operands; i++) | |
4588 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4589 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4590 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4591 | return 0; | |
4592 | ||
2af88768 | 4593 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 4594 | |
893bc853 RK |
4595 | case RELOAD_FOR_OPADDR_ADDR: |
4596 | for (i = 0; i < reload_n_operands; i++) | |
4597 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4598 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4599 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4600 | return 0; | |
4601 | ||
2af88768 GK |
4602 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4603 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4604 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 4605 | |
546b63fb | 4606 | case RELOAD_FOR_INSN: |
893bc853 | 4607 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4608 | we need only check for output addresses. */ |
4609 | ||
d1d18b46 | 4610 | opnum = reload_n_operands; |
546b63fb | 4611 | |
0f41302f | 4612 | /* ... fall through ... */ |
546b63fb | 4613 | |
32131a9c | 4614 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4615 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4616 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb | 4617 | /* We already know these can't conflict with a later output. So the |
d1d18b46 DJ |
4618 | only thing to check are later output addresses. |
4619 | Note that multiple output operands are emitted in reverse order, | |
4620 | so the conflicting ones are those with lower indices. */ | |
4621 | for (i = 0; i < opnum; i++) | |
47c8cf91 ILT |
4622 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4623 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4624 | return 0; |
4625 | ||
32131a9c RK |
4626 | return 1; |
4627 | } | |
546b63fb | 4628 | |
32131a9c RK |
4629 | abort (); |
4630 | } | |
4631 | \f | |
351aa1c1 RK |
4632 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4633 | Return 0 otherwise. | |
4634 | ||
4635 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4636 | ||
f5963e61 | 4637 | int |
351aa1c1 RK |
4638 | reloads_conflict (r1, r2) |
4639 | int r1, r2; | |
4640 | { | |
eceef4c9 BS |
4641 | enum reload_type r1_type = rld[r1].when_needed; |
4642 | enum reload_type r2_type = rld[r2].when_needed; | |
4643 | int r1_opnum = rld[r1].opnum; | |
4644 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4645 | |
2edc8d65 RK |
4646 | /* RELOAD_OTHER conflicts with everything. */ |
4647 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4648 | return 1; |
4649 | ||
4650 | /* Otherwise, check conflicts differently for each type. */ | |
4651 | ||
4652 | switch (r1_type) | |
4653 | { | |
4654 | case RELOAD_FOR_INPUT: | |
05d10675 | 4655 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4656 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4657 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4658 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4659 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4660 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4661 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4662 | |
4663 | case RELOAD_FOR_INPUT_ADDRESS: | |
4664 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
4665 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4666 | ||
47c8cf91 ILT |
4667 | case RELOAD_FOR_INPADDR_ADDRESS: |
4668 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
4669 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4670 | ||
351aa1c1 RK |
4671 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4672 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4673 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
351aa1c1 | 4674 | |
47c8cf91 ILT |
4675 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4676 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4677 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
47c8cf91 | 4678 | |
351aa1c1 RK |
4679 | case RELOAD_FOR_OPERAND_ADDRESS: |
4680 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a94ce333 | 4681 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); |
351aa1c1 | 4682 | |
893bc853 | 4683 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 4684 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 4685 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 4686 | |
351aa1c1 RK |
4687 | case RELOAD_FOR_OUTPUT: |
4688 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
4689 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
4690 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d1d18b46 | 4691 | && r2_opnum >= r1_opnum)); |
351aa1c1 RK |
4692 | |
4693 | case RELOAD_FOR_INSN: | |
4694 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
4695 | || r2_type == RELOAD_FOR_INSN | |
4696 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
4697 | ||
4698 | case RELOAD_FOR_OTHER_ADDRESS: | |
4699 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
4700 | ||
adab4fc5 | 4701 | case RELOAD_OTHER: |
2edc8d65 | 4702 | return 1; |
adab4fc5 | 4703 | |
351aa1c1 RK |
4704 | default: |
4705 | abort (); | |
4706 | } | |
4707 | } | |
4708 | \f | |
32131a9c RK |
4709 | /* Indexed by reload number, 1 if incoming value |
4710 | inherited from previous insns. */ | |
4711 | char reload_inherited[MAX_RELOADS]; | |
4712 | ||
4713 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4714 | if we know it. Otherwise, this is 0. */ | |
4715 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4716 | ||
4717 | /* If non-zero, this is a place to get the value of the reload, | |
4718 | rather than using reload_in. */ | |
4719 | rtx reload_override_in[MAX_RELOADS]; | |
4720 | ||
e6e52be0 R |
4721 | /* For each reload, the hard register number of the register used, |
4722 | or -1 if we did not need a register for this reload. */ | |
32131a9c RK |
4723 | int reload_spill_index[MAX_RELOADS]; |
4724 | ||
304a22dd R |
4725 | /* Subroutine of free_for_value_p, used to check a single register. |
4726 | START_REGNO is the starting regno of the full reload register | |
4727 | (possibly comprising multiple hard registers) that we are considering. */ | |
f5470689 | 4728 | |
6e684430 | 4729 | static int |
304a22dd R |
4730 | reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out, |
4731 | reloadnum, ignore_address_reloads) | |
4732 | int start_regno, regno; | |
6e684430 R |
4733 | int opnum; |
4734 | enum reload_type type; | |
f5470689 R |
4735 | rtx value, out; |
4736 | int reloadnum; | |
5828374f | 4737 | int ignore_address_reloads; |
6e684430 R |
4738 | { |
4739 | int time1; | |
09a308fe R |
4740 | /* Set if we see an input reload that must not share its reload register |
4741 | with any new earlyclobber, but might otherwise share the reload | |
4742 | register with an output or input-output reload. */ | |
4743 | int check_earlyclobber = 0; | |
6e684430 | 4744 | int i; |
dfe96118 R |
4745 | int copy = 0; |
4746 | ||
9e3a9cf2 | 4747 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
4748 | return 0; |
4749 | ||
dfe96118 R |
4750 | if (out == const0_rtx) |
4751 | { | |
4752 | copy = 1; | |
4753 | out = NULL_RTX; | |
4754 | } | |
6e684430 R |
4755 | |
4756 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
4757 | new register use would overlap with the one of a previous reload | |
4758 | that is not read-only or uses a different value. | |
4759 | The 'time' used doesn't have to be linear in any shape or form, just | |
4760 | monotonic. | |
4761 | Some reload types use different 'buckets' for each operand. | |
4762 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
4763 | such reload type. |
4764 | We compute TIME1 as the time when the register for the prospective | |
4765 | new reload ceases to be live, and TIME2 for each existing | |
4766 | reload as the time when that the reload register of that reload | |
4767 | becomes live. | |
4768 | Where there is little to be gained by exact lifetime calculations, | |
4769 | we just make conservative assumptions, i.e. a longer lifetime; | |
4770 | this is done in the 'default:' cases. */ | |
6e684430 R |
4771 | switch (type) |
4772 | { | |
4773 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 4774 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 4775 | time1 = copy ? 0 : 1; |
6e684430 | 4776 | break; |
dfe96118 R |
4777 | case RELOAD_OTHER: |
4778 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
4779 | break; | |
05d10675 BS |
4780 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
4781 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
4782 | respectively, to the time values for these, we get distinct time | |
4783 | values. To get distinct time values for each operand, we have to | |
4784 | multiply opnum by at least three. We round that up to four because | |
4785 | multiply by four is often cheaper. */ | |
6e684430 | 4786 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 4787 | time1 = opnum * 4 + 2; |
6e684430 R |
4788 | break; |
4789 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
4790 | time1 = opnum * 4 + 3; |
4791 | break; | |
4792 | case RELOAD_FOR_INPUT: | |
4793 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
4794 | executes (inclusive). */ | |
4795 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 4796 | break; |
cb2afeb3 | 4797 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
4798 | /* opnum * 4 + 4 |
4799 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
4800 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
4801 | break; | |
4802 | case RELOAD_FOR_OPERAND_ADDRESS: | |
4803 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
4804 | is executed. */ | |
dfe96118 R |
4805 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
4806 | break; | |
4807 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
4808 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 4809 | break; |
6e684430 | 4810 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 4811 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
4812 | break; |
4813 | default: | |
dfe96118 | 4814 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
4815 | } |
4816 | ||
4817 | for (i = 0; i < n_reloads; i++) | |
4818 | { | |
eceef4c9 | 4819 | rtx reg = rld[i].reg_rtx; |
6e684430 R |
4820 | if (reg && GET_CODE (reg) == REG |
4821 | && ((unsigned) regno - true_regnum (reg) | |
83e0821b | 4822 | <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1) |
f5470689 | 4823 | && i != reloadnum) |
6e684430 | 4824 | { |
304a22dd R |
4825 | rtx other_input = rld[i].in; |
4826 | ||
4827 | /* If the other reload loads the same input value, that | |
4828 | will not cause a conflict only if it's loading it into | |
4829 | the same register. */ | |
4830 | if (true_regnum (reg) != start_regno) | |
4831 | other_input = NULL_RTX; | |
4832 | if (! other_input || ! rtx_equal_p (other_input, value) | |
eceef4c9 | 4833 | || rld[i].out || out) |
6e684430 | 4834 | { |
09a308fe | 4835 | int time2; |
eceef4c9 | 4836 | switch (rld[i].when_needed) |
f5470689 R |
4837 | { |
4838 | case RELOAD_FOR_OTHER_ADDRESS: | |
4839 | time2 = 0; | |
4840 | break; | |
4841 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
4842 | /* find_reloads makes sure that a |
4843 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
4844 | by at most one - the first - | |
4845 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
4846 | address reload is inherited, the address address reload | |
4847 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
4848 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
4849 | && ignore_address_reloads | |
4850 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
4851 | Then the address address is still needed to store | |
4852 | back the new address. */ | |
eceef4c9 | 4853 | && ! rld[reloadnum].out) |
cb2afeb3 | 4854 | continue; |
dfe96118 R |
4855 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
4856 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
4857 | reloads go away. */ | |
eceef4c9 | 4858 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
4859 | && ignore_address_reloads |
4860 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 4861 | && ! rld[reloadnum].out) |
dfe96118 | 4862 | continue; |
eceef4c9 | 4863 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
4864 | break; |
4865 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4866 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 4867 | && ignore_address_reloads |
eceef4c9 | 4868 | && ! rld[reloadnum].out) |
dfe96118 | 4869 | continue; |
eceef4c9 | 4870 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
4871 | break; |
4872 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 4873 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 4874 | check_earlyclobber = 1; |
f5470689 | 4875 | break; |
eceef4c9 | 4876 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 4877 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 4878 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
4879 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
4880 | && ignore_address_reloads | |
eceef4c9 | 4881 | && ! rld[reloadnum].out) |
cb2afeb3 | 4882 | continue; |
dfe96118 | 4883 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
4884 | break; |
4885 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 4886 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 4887 | check_earlyclobber = 1; |
dfe96118 R |
4888 | break; |
4889 | case RELOAD_FOR_INSN: | |
4890 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 4891 | break; |
f5470689 | 4892 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
4893 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
4894 | instruction is executed. */ | |
dfe96118 | 4895 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 4896 | break; |
05d10675 BS |
4897 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
4898 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
4899 | value. */ | |
cb2afeb3 | 4900 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
4901 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
4902 | && ignore_address_reloads | |
eceef4c9 | 4903 | && ! rld[reloadnum].out) |
cb2afeb3 | 4904 | continue; |
eceef4c9 | 4905 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 4906 | break; |
f5470689 | 4907 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 4908 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
4909 | break; |
4910 | case RELOAD_OTHER: | |
dfe96118 R |
4911 | /* If there is no conflict in the input part, handle this |
4912 | like an output reload. */ | |
304a22dd | 4913 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
f5470689 | 4914 | { |
dfe96118 | 4915 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 4916 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
4917 | if (earlyclobber_operand_p (rld[i].out)) |
4918 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 4919 | |
f5470689 R |
4920 | break; |
4921 | } | |
dfe96118 R |
4922 | time2 = 1; |
4923 | /* RELOAD_OTHER might be live beyond instruction execution, | |
4924 | but this is not obvious when we set time2 = 1. So check | |
4925 | here if there might be a problem with the new reload | |
4926 | clobbering the register used by the RELOAD_OTHER. */ | |
4927 | if (out) | |
4928 | return 0; | |
4929 | break; | |
f5470689 | 4930 | default: |
dfe96118 | 4931 | return 0; |
f5470689 | 4932 | } |
25963977 | 4933 | if ((time1 >= time2 |
eceef4c9 | 4934 | && (! rld[i].in || rld[i].out |
304a22dd | 4935 | || ! rtx_equal_p (other_input, value))) |
eceef4c9 | 4936 | || (out && rld[reloadnum].out_reg |
701d55e8 | 4937 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 4938 | return 0; |
6e684430 | 4939 | } |
6e684430 R |
4940 | } |
4941 | } | |
09a308fe R |
4942 | |
4943 | /* Earlyclobbered outputs must conflict with inputs. */ | |
4944 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
4945 | return 0; | |
4946 | ||
6e684430 R |
4947 | return 1; |
4948 | } | |
4949 | ||
c02cad8f BS |
4950 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
4951 | needed for the part of the insn specified by OPNUM and TYPE, | |
4952 | may be used to load VALUE into it. | |
4953 | ||
4954 | MODE is the mode in which the register is used, this is needed to | |
4955 | determine how many hard regs to test. | |
4956 | ||
4957 | Other read-only reloads with the same value do not conflict | |
4958 | unless OUT is non-zero and these other reloads have to live while | |
4959 | output reloads live. | |
4960 | If OUT is CONST0_RTX, this is a special case: it means that the | |
4961 | test should not be for using register REGNO as reload register, but | |
4962 | for copying from register REGNO into the reload register. | |
4963 | ||
4964 | RELOADNUM is the number of the reload we want to load this value for; | |
4965 | a reload does not conflict with itself. | |
4966 | ||
4967 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
4968 | reloads that load an address for the very reload we are considering. | |
4969 | ||
4970 | The caller has to make sure that there is no conflict with the return | |
4971 | register. */ | |
4972 | ||
4973 | static int | |
4974 | free_for_value_p (regno, mode, opnum, type, value, out, reloadnum, | |
4975 | ignore_address_reloads) | |
4976 | int regno; | |
4977 | enum machine_mode mode; | |
4978 | int opnum; | |
4979 | enum reload_type type; | |
4980 | rtx value, out; | |
4981 | int reloadnum; | |
4982 | int ignore_address_reloads; | |
4983 | { | |
4984 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
4985 | while (nregs-- > 0) | |
304a22dd R |
4986 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
4987 | value, out, reloadnum, | |
4988 | ignore_address_reloads)) | |
c02cad8f BS |
4989 | return 0; |
4990 | return 1; | |
4991 | } | |
4992 | ||
ff6534ad BS |
4993 | /* Determine whether the reload reg X overlaps any rtx'es used for |
4994 | overriding inheritance. Return nonzero if so. */ | |
4995 | ||
4996 | static int | |
4997 | conflicts_with_override (x) | |
4998 | rtx x; | |
4999 | { | |
5000 | int i; | |
5001 | for (i = 0; i < n_reloads; i++) | |
5002 | if (reload_override_in[i] | |
5003 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
5004 | return 1; | |
5005 | return 0; | |
5006 | } | |
5007 | \f | |
67e61fe7 BS |
5008 | /* Give an error message saying we failed to find a reload for INSN, |
5009 | and clear out reload R. */ | |
5010 | static void | |
5011 | failed_reload (insn, r) | |
5012 | rtx insn; | |
5013 | int r; | |
5014 | { | |
5015 | if (asm_noperands (PATTERN (insn)) < 0) | |
5016 | /* It's the compiler's fault. */ | |
5017 | fatal_insn ("Could not find a spill register", insn); | |
5018 | ||
5019 | /* It's the user's fault; the operand's mode and constraint | |
5020 | don't match. Disable this reload so we don't crash in final. */ | |
5021 | error_for_asm (insn, | |
5022 | "`asm' operand constraint incompatible with operand size"); | |
5023 | rld[r].in = 0; | |
5024 | rld[r].out = 0; | |
5025 | rld[r].reg_rtx = 0; | |
5026 | rld[r].optional = 1; | |
5027 | rld[r].secondary_p = 1; | |
5028 | } | |
5029 | ||
5030 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5031 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5032 | successful. */ | |
5033 | static int | |
5034 | set_reload_reg (i, r) | |
5035 | int i, r; | |
5036 | { | |
5037 | int regno; | |
5038 | rtx reg = spill_reg_rtx[i]; | |
5039 | ||
5040 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5041 | spill_reg_rtx[i] = reg | |
5042 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5043 | ||
5044 | regno = true_regnum (reg); | |
5045 | ||
5046 | /* Detect when the reload reg can't hold the reload mode. | |
5047 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5048 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5049 | { | |
5050 | enum machine_mode test_mode = VOIDmode; | |
5051 | if (rld[r].in) | |
5052 | test_mode = GET_MODE (rld[r].in); | |
5053 | /* If rld[r].in has VOIDmode, it means we will load it | |
5054 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5055 | We have already tested that for validity. */ | |
5056 | /* Aside from that, we need to test that the expressions | |
5057 | to reload from or into have modes which are valid for this | |
5058 | reload register. Otherwise the reload insns would be invalid. */ | |
5059 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5060 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5061 | if (! (rld[r].out != 0 | |
5062 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5063 | { | |
5064 | /* The reg is OK. */ | |
5065 | last_spill_reg = i; | |
5066 | ||
5067 | /* Mark as in use for this insn the reload regs we use | |
5068 | for this. */ | |
5069 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5070 | rld[r].when_needed, rld[r].mode); | |
5071 | ||
5072 | rld[r].reg_rtx = reg; | |
5073 | reload_spill_index[r] = spill_regs[i]; | |
5074 | return 1; | |
5075 | } | |
5076 | } | |
5077 | return 0; | |
5078 | } | |
5079 | ||
32131a9c RK |
5080 | /* Find a spill register to use as a reload register for reload R. |
5081 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
5082 | processed. | |
5083 | ||
eceef4c9 | 5084 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5085 | |
f5d8c9f4 BS |
5086 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5087 | we didn't change anything. */ | |
32131a9c RK |
5088 | |
5089 | static int | |
f5d8c9f4 | 5090 | allocate_reload_reg (chain, r, last_reload) |
272df862 | 5091 | struct insn_chain *chain ATTRIBUTE_UNUSED; |
32131a9c | 5092 | int r; |
32131a9c | 5093 | int last_reload; |
32131a9c | 5094 | { |
67e61fe7 | 5095 | int i, pass, count; |
32131a9c RK |
5096 | |
5097 | /* If we put this reload ahead, thinking it is a group, | |
5098 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5099 | reg that some other reload needs. |
32131a9c RK |
5100 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5101 | which is a group of data regs or one fp reg.) | |
5102 | We need not be so restrictive if there are no more reloads | |
5103 | for this insn. | |
5104 | ||
5105 | ??? Really it would be nicer to have smarter handling | |
5106 | for that kind of reg class, where a problem like this is normal. | |
5107 | Perhaps those classes should be avoided for reloading | |
5108 | by use of more alternatives. */ | |
5109 | ||
8ec450a4 | 5110 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5111 | |
5112 | /* If we want a single register and haven't yet found one, | |
5113 | take any reg in the right class and not in use. | |
5114 | If we want a consecutive group, here is where we look for it. | |
5115 | ||
5116 | We use two passes so we can first look for reload regs to | |
5117 | reuse, which are already in use for other reloads in this insn, | |
5118 | and only then use additional registers. | |
5119 | I think that maximizing reuse is needed to make sure we don't | |
5120 | run out of reload regs. Suppose we have three reloads, and | |
5121 | reloads A and B can share regs. These need two regs. | |
5122 | Suppose A and B are given different regs. | |
5123 | That leaves none for C. */ | |
5124 | for (pass = 0; pass < 2; pass++) | |
5125 | { | |
5126 | /* I is the index in spill_regs. | |
5127 | We advance it round-robin between insns to use all spill regs | |
5128 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5129 | of leapfrogging each other. */ |
5130 | ||
5131 | i = last_spill_reg; | |
05d10675 | 5132 | |
a5339699 | 5133 | for (count = 0; count < n_spills; count++) |
32131a9c | 5134 | { |
eceef4c9 | 5135 | int class = (int) rld[r].class; |
03acd8f8 | 5136 | int regnum; |
32131a9c | 5137 | |
03acd8f8 BS |
5138 | i++; |
5139 | if (i >= n_spills) | |
5140 | i -= n_spills; | |
5141 | regnum = spill_regs[i]; | |
32131a9c | 5142 | |
eceef4c9 BS |
5143 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5144 | rld[r].when_needed) | |
5145 | || (rld[r].in | |
05d10675 BS |
5146 | /* We check reload_reg_used to make sure we |
5147 | don't clobber the return register. */ | |
03acd8f8 | 5148 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5149 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5150 | rld[r].when_needed, rld[r].in, | |
5151 | rld[r].out, r, 1))) | |
03acd8f8 | 5152 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 5153 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5154 | /* Look first for regs to share, then for unshared. But |
5155 | don't share regs used for inherited reloads; they are | |
5156 | the ones we want to preserve. */ | |
5157 | && (pass | |
5158 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5159 | regnum) |
be7ae2a4 | 5160 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5161 | regnum)))) |
32131a9c | 5162 | { |
8ec450a4 | 5163 | int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); |
32131a9c RK |
5164 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5165 | (on 68000) got us two FP regs. If NR is 1, | |
5166 | we would reject both of them. */ | |
5167 | if (force_group) | |
67e61fe7 | 5168 | nr = rld[r].nregs; |
32131a9c RK |
5169 | /* If we need only one reg, we have already won. */ |
5170 | if (nr == 1) | |
5171 | { | |
5172 | /* But reject a single reg if we demand a group. */ | |
5173 | if (force_group) | |
5174 | continue; | |
5175 | break; | |
5176 | } | |
5177 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5178 | are available here. */ |
5179 | while (nr > 1) | |
5180 | { | |
5181 | int regno = regnum + nr - 1; | |
5182 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5183 | && spill_reg_order[regno] >= 0 | |
5184 | && reload_reg_free_p (regno, rld[r].opnum, | |
5185 | rld[r].when_needed))) | |
5186 | break; | |
5187 | nr--; | |
5188 | } | |
32131a9c RK |
5189 | if (nr == 1) |
5190 | break; | |
5191 | } | |
5192 | } | |
5193 | ||
5194 | /* If we found something on pass 1, omit pass 2. */ | |
5195 | if (count < n_spills) | |
5196 | break; | |
5197 | } | |
1d7254c5 | 5198 | |
32131a9c | 5199 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5200 | if (count >= n_spills) |
32131a9c RK |
5201 | return 0; |
5202 | ||
f5d8c9f4 BS |
5203 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5204 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5205 | |
f5d8c9f4 | 5206 | return set_reload_reg (i, r); |
32131a9c RK |
5207 | } |
5208 | \f | |
67e61fe7 BS |
5209 | /* Initialize all the tables needed to allocate reload registers. |
5210 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5211 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5212 | |
32131a9c | 5213 | static void |
67e61fe7 | 5214 | choose_reload_regs_init (chain, save_reload_reg_rtx) |
7609e720 | 5215 | struct insn_chain *chain; |
67e61fe7 | 5216 | rtx *save_reload_reg_rtx; |
32131a9c | 5217 | { |
67e61fe7 | 5218 | int i; |
32131a9c | 5219 | |
67e61fe7 BS |
5220 | for (i = 0; i < n_reloads; i++) |
5221 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5222 | |
961192e1 JM |
5223 | memset (reload_inherited, 0, MAX_RELOADS); |
5224 | memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); | |
5225 | memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5226 | |
5227 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5228 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5229 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5230 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5231 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5232 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5233 | |
f1db3576 JL |
5234 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5235 | { | |
5236 | HARD_REG_SET tmp; | |
239a0f5b | 5237 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5238 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5239 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5240 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5241 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5242 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5243 | } |
efc9bd41 | 5244 | |
546b63fb RK |
5245 | for (i = 0; i < reload_n_operands; i++) |
5246 | { | |
5247 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5248 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5249 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5250 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5251 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5252 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5253 | } |
32131a9c | 5254 | |
9e3a9cf2 | 5255 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5256 | |
67e61fe7 | 5257 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5258 | |
67e61fe7 BS |
5259 | for (i = 0; i < n_reloads; i++) |
5260 | /* If we have already decided to use a certain register, | |
5261 | don't use it in another way. */ | |
5262 | if (rld[i].reg_rtx) | |
5263 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5264 | rld[i].when_needed, rld[i].mode); | |
5265 | } | |
32131a9c | 5266 | |
67e61fe7 BS |
5267 | /* Assign hard reg targets for the pseudo-registers we must reload |
5268 | into hard regs for this insn. | |
5269 | Also output the instructions to copy them in and out of the hard regs. | |
5270 | ||
5271 | For machines with register classes, we are responsible for | |
5272 | finding a reload reg in the proper class. */ | |
5273 | ||
5274 | static void | |
5275 | choose_reload_regs (chain) | |
5276 | struct insn_chain *chain; | |
5277 | { | |
5278 | rtx insn = chain->insn; | |
5279 | register int i, j; | |
770ae6cc | 5280 | unsigned int max_group_size = 1; |
67e61fe7 | 5281 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5282 | int pass, win, inheritance; |
67e61fe7 BS |
5283 | |
5284 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5285 | |
32131a9c RK |
5286 | /* In order to be certain of getting the registers we need, |
5287 | we must sort the reloads into order of increasing register class. | |
5288 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5289 | that provided the reload registers. |
32131a9c RK |
5290 | |
5291 | Also note whether any of the reloads wants a consecutive group of regs. | |
5292 | If so, record the maximum size of the group desired and what | |
5293 | register class contains all the groups needed by this insn. */ | |
5294 | ||
5295 | for (j = 0; j < n_reloads; j++) | |
5296 | { | |
5297 | reload_order[j] = j; | |
5298 | reload_spill_index[j] = -1; | |
5299 | ||
8ec450a4 | 5300 | if (rld[j].nregs > 1) |
32131a9c | 5301 | { |
8ec450a4 | 5302 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5303 | group_class |
1d7254c5 | 5304 | = reg_class_superunion[(int) rld[j].class][(int)group_class]; |
32131a9c RK |
5305 | } |
5306 | ||
eceef4c9 | 5307 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5308 | } |
5309 | ||
5310 | if (n_reloads > 1) | |
5311 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5312 | ||
58b1581b RS |
5313 | /* If -O, try first with inheritance, then turning it off. |
5314 | If not -O, don't do inheritance. | |
5315 | Using inheritance when not optimizing leads to paradoxes | |
5316 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5317 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5318 | win = 0; |
58b1581b | 5319 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5320 | { |
67e61fe7 BS |
5321 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5322 | ||
32131a9c RK |
5323 | /* Process the reloads in order of preference just found. |
5324 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5325 | ||
770ae6cc RK |
5326 | This used to look for an existing reloaded home for all of the |
5327 | reloads, and only then perform any new reloads. But that could lose | |
5328 | if the reloads were done out of reg-class order because a later | |
5329 | reload with a looser constraint might have an old home in a register | |
5330 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5331 | |
5332 | To solve this, we make two passes over the reloads, in the order | |
5333 | described above. In the first pass we try to inherit a reload | |
5334 | from a previous insn. If there is a later reload that needs a | |
5335 | class that is a proper subset of the class being processed, we must | |
5336 | also allocate a spill register during the first pass. | |
5337 | ||
5338 | Then make a second pass over the reloads to allocate any reloads | |
5339 | that haven't been given registers yet. */ | |
5340 | ||
5341 | for (j = 0; j < n_reloads; j++) | |
5342 | { | |
5343 | register int r = reload_order[j]; | |
8593b745 | 5344 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5345 | |
5346 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5347 | if (rld[r].out == 0 && rld[r].in == 0 |
5348 | && ! rld[r].secondary_p) | |
32131a9c RK |
5349 | continue; |
5350 | ||
b29514ee | 5351 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5352 | register, we don't need to chose one. Otherwise, try even if it |
5353 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5354 | around. |
5355 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5356 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5357 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5358 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
5359 | && GET_CODE (rld[r].in) != MEM | |
5360 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) | |
32131a9c RK |
5361 | continue; |
5362 | ||
5363 | #if 0 /* No longer needed for correct operation. | |
5364 | It might give better code, or might not; worth an experiment? */ | |
5365 | /* If this is an optional reload, we can't inherit from earlier insns | |
5366 | until we are sure that any non-optional reloads have been allocated. | |
5367 | The following code takes advantage of the fact that optional reloads | |
5368 | are at the end of reload_order. */ | |
eceef4c9 | 5369 | if (rld[r].optional != 0) |
32131a9c | 5370 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5371 | if ((rld[reload_order[i]].out != 0 |
5372 | || rld[reload_order[i]].in != 0 | |
5373 | || rld[reload_order[i]].secondary_p) | |
5374 | && ! rld[reload_order[i]].optional | |
5375 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5376 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5377 | #endif |
5378 | ||
5379 | /* First see if this pseudo is already available as reloaded | |
5380 | for a previous insn. We cannot try to inherit for reloads | |
5381 | that are smaller than the maximum number of registers needed | |
5382 | for groups unless the register we would allocate cannot be used | |
5383 | for the groups. | |
5384 | ||
5385 | We could check here to see if this is a secondary reload for | |
5386 | an object that is already in a register of the desired class. | |
5387 | This would avoid the need for the secondary reload register. | |
5388 | But this is complex because we can't easily determine what | |
b080c137 RK |
5389 | objects might want to be loaded via this reload. So let a |
5390 | register be allocated here. In `emit_reload_insns' we suppress | |
5391 | one of the loads in the case described above. */ | |
32131a9c RK |
5392 | |
5393 | if (inheritance) | |
5394 | { | |
ddef6bc7 | 5395 | int byte = 0; |
32131a9c | 5396 | register int regno = -1; |
6a651371 | 5397 | enum machine_mode mode = VOIDmode; |
32131a9c | 5398 | |
eceef4c9 | 5399 | if (rld[r].in == 0) |
32131a9c | 5400 | ; |
eceef4c9 | 5401 | else if (GET_CODE (rld[r].in) == REG) |
db660765 | 5402 | { |
eceef4c9 BS |
5403 | regno = REGNO (rld[r].in); |
5404 | mode = GET_MODE (rld[r].in); | |
db660765 | 5405 | } |
eceef4c9 | 5406 | else if (GET_CODE (rld[r].in_reg) == REG) |
db660765 | 5407 | { |
eceef4c9 BS |
5408 | regno = REGNO (rld[r].in_reg); |
5409 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5410 | } |
eceef4c9 BS |
5411 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
5412 | && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) | |
b60a8416 | 5413 | { |
ddef6bc7 | 5414 | byte = SUBREG_BYTE (rld[r].in_reg); |
eceef4c9 | 5415 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
cb2afeb3 | 5416 | if (regno < FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 5417 | regno = subreg_regno (rld[r].in_reg); |
eceef4c9 | 5418 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5419 | } |
5420 | #ifdef AUTO_INC_DEC | |
eceef4c9 BS |
5421 | else if ((GET_CODE (rld[r].in_reg) == PRE_INC |
5422 | || GET_CODE (rld[r].in_reg) == PRE_DEC | |
5423 | || GET_CODE (rld[r].in_reg) == POST_INC | |
5424 | || GET_CODE (rld[r].in_reg) == POST_DEC) | |
5425 | && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) | |
cb2afeb3 | 5426 | { |
eceef4c9 BS |
5427 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5428 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5429 | rld[r].out = rld[r].in; | |
b60a8416 | 5430 | } |
cb2afeb3 | 5431 | #endif |
32131a9c RK |
5432 | #if 0 |
5433 | /* This won't work, since REGNO can be a pseudo reg number. | |
5434 | Also, it takes much more hair to keep track of all the things | |
5435 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 BS |
5436 | else if (GET_CODE (rld[r].in) == SUBREG |
5437 | && GET_CODE (SUBREG_REG (rld[r].in)) == REG) | |
ddef6bc7 | 5438 | regno = subreg_regno (rld[r].in); |
32131a9c RK |
5439 | #endif |
5440 | ||
5441 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
5442 | { | |
eceef4c9 | 5443 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5444 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 5445 | enum machine_mode need_mode; |
05d10675 | 5446 | |
ddef6bc7 JJ |
5447 | i = REGNO (last_reg); |
5448 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
cb2afeb3 | 5449 | last_class = REGNO_REG_CLASS (i); |
02188693 | 5450 | |
ddef6bc7 | 5451 | if (byte == 0) |
ce701d1b BS |
5452 | need_mode = mode; |
5453 | else | |
5454 | need_mode | |
ddef6bc7 | 5455 | = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte, |
ce701d1b | 5456 | GET_MODE_CLASS (mode)); |
02188693 | 5457 | |
c9d8a813 | 5458 | if ( |
02188693 | 5459 | #ifdef CLASS_CANNOT_CHANGE_MODE |
c9d8a813 | 5460 | (TEST_HARD_REG_BIT |
02188693 | 5461 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i) |
1d7254c5 | 5462 | ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg), |
02188693 | 5463 | need_mode) |
c9d8a813 | 5464 | : (GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 5465 | >= GET_MODE_SIZE (need_mode))) |
c9d8a813 RH |
5466 | #else |
5467 | (GET_MODE_SIZE (GET_MODE (last_reg)) | |
02188693 | 5468 | >= GET_MODE_SIZE (need_mode)) |
c9d8a813 | 5469 | #endif |
cb2afeb3 | 5470 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 5471 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5472 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5473 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5474 | /* Even if we can't use this register as a reload | |
5475 | register, we might use it for reload_override_in, | |
5476 | if copying it to the desired class is cheap | |
5477 | enough. */ | |
e56b4594 | 5478 | || ((REGISTER_MOVE_COST (mode, last_class, class) |
cb2afeb3 R |
5479 | < MEMORY_MOVE_COST (mode, class, 1)) |
5480 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5481 | && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, | |
5482 | last_reg) | |
5483 | == NO_REGS) | |
5484 | #endif | |
5485 | #ifdef SECONDARY_MEMORY_NEEDED | |
5486 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5487 | mode) | |
5488 | #endif | |
5489 | )) | |
5490 | ||
8ec450a4 | 5491 | && (rld[r].nregs == max_group_size |
32131a9c | 5492 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5493 | i)) |
c02cad8f BS |
5494 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
5495 | rld[r].when_needed, rld[r].in, | |
5496 | const0_rtx, r, 1)) | |
32131a9c RK |
5497 | { |
5498 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5499 | registers still have their values intact. */ |
1d7254c5 | 5500 | int nr = HARD_REGNO_NREGS (i, rld[r].mode); |
32131a9c RK |
5501 | int k; |
5502 | ||
5503 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5504 | if (reg_reloaded_contents[i + k] != regno |
5505 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5506 | break; |
5507 | ||
5508 | if (k == nr) | |
5509 | { | |
c74fa651 | 5510 | int i1; |
eb4d554e | 5511 | int bad_for_class; |
c74fa651 | 5512 | |
cb2afeb3 R |
5513 | last_reg = (GET_MODE (last_reg) == mode |
5514 | ? last_reg : gen_rtx_REG (mode, i)); | |
5515 | ||
eb4d554e GK |
5516 | bad_for_class = 0; |
5517 | for (k = 0; k < nr; k++) | |
5518 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
5519 | i+k); | |
5520 | ||
c74fa651 RS |
5521 | /* We found a register that contains the |
5522 | value we need. If this register is the | |
5523 | same as an `earlyclobber' operand of the | |
5524 | current insn, just mark it as a place to | |
5525 | reload from since we can't use it as the | |
5526 | reload register itself. */ | |
5527 | ||
5528 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5529 | if (reg_overlap_mentioned_for_reload_p | |
5530 | (reg_last_reload_reg[regno], | |
5531 | reload_earlyclobbers[i1])) | |
5532 | break; | |
5533 | ||
8908158d | 5534 | if (i1 != n_earlyclobbers |
c02cad8f BS |
5535 | || ! (free_for_value_p (i, rld[r].mode, |
5536 | rld[r].opnum, | |
5537 | rld[r].when_needed, rld[r].in, | |
5538 | rld[r].out, r, 1)) | |
e6e52be0 | 5539 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5540 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5541 | && rld[r].out |
e6e52be0 | 5542 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5543 | /* Don't clobber the frame pointer. */ |
1d7254c5 KH |
5544 | || (i == HARD_FRAME_POINTER_REGNUM |
5545 | && rld[r].out) | |
8908158d RS |
5546 | /* Don't really use the inherited spill reg |
5547 | if we need it wider than we've got it. */ | |
8ec450a4 | 5548 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5549 | > GET_MODE_SIZE (mode)) |
eb4d554e | 5550 | || bad_for_class |
cb2afeb3 | 5551 | |
b29514ee R |
5552 | /* If find_reloads chose reload_out as reload |
5553 | register, stay with it - that leaves the | |
5554 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5555 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5556 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 5557 | { |
4c3a2649 BS |
5558 | if (! rld[r].optional) |
5559 | { | |
5560 | reload_override_in[r] = last_reg; | |
5561 | reload_inheritance_insn[r] | |
5562 | = reg_reloaded_insn[i]; | |
5563 | } | |
cb2afeb3 | 5564 | } |
c74fa651 RS |
5565 | else |
5566 | { | |
54c40e68 | 5567 | int k; |
c74fa651 RS |
5568 | /* We can use this as a reload reg. */ |
5569 | /* Mark the register as in use for this part of | |
5570 | the insn. */ | |
e6e52be0 | 5571 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5572 | rld[r].opnum, |
5573 | rld[r].when_needed, | |
8ec450a4 | 5574 | rld[r].mode); |
eceef4c9 | 5575 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5576 | reload_inherited[r] = 1; |
5577 | reload_inheritance_insn[r] | |
5578 | = reg_reloaded_insn[i]; | |
5579 | reload_spill_index[r] = i; | |
54c40e68 RS |
5580 | for (k = 0; k < nr; k++) |
5581 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5582 | i + k); |
c74fa651 | 5583 | } |
32131a9c RK |
5584 | } |
5585 | } | |
5586 | } | |
5587 | } | |
5588 | ||
5589 | /* Here's another way to see if the value is already lying around. */ | |
5590 | if (inheritance | |
eceef4c9 | 5591 | && rld[r].in != 0 |
32131a9c | 5592 | && ! reload_inherited[r] |
eceef4c9 BS |
5593 | && rld[r].out == 0 |
5594 | && (CONSTANT_P (rld[r].in) | |
5595 | || GET_CODE (rld[r].in) == PLUS | |
5596 | || GET_CODE (rld[r].in) == REG | |
5597 | || GET_CODE (rld[r].in) == MEM) | |
8ec450a4 | 5598 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5599 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5600 | search_equiv = rld[r].in; | |
8593b745 R |
5601 | /* If this is an output reload from a simple move insn, look |
5602 | if an equivalence for the input is available. */ | |
eceef4c9 | 5603 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5604 | { |
5605 | rtx set = single_set (insn); | |
5606 | ||
5607 | if (set | |
eceef4c9 | 5608 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5609 | && CONSTANT_P (SET_SRC (set))) |
5610 | search_equiv = SET_SRC (set); | |
5611 | } | |
5612 | ||
5613 | if (search_equiv) | |
32131a9c RK |
5614 | { |
5615 | register rtx equiv | |
eceef4c9 | 5616 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
9714cf43 | 5617 | -1, NULL, 0, rld[r].mode); |
f428f252 | 5618 | int regno = 0; |
32131a9c RK |
5619 | |
5620 | if (equiv != 0) | |
5621 | { | |
5622 | if (GET_CODE (equiv) == REG) | |
5623 | regno = REGNO (equiv); | |
5624 | else if (GET_CODE (equiv) == SUBREG) | |
5625 | { | |
f8a9e02b RK |
5626 | /* This must be a SUBREG of a hard register. |
5627 | Make a new REG since this might be used in an | |
5628 | address and not all machines support SUBREGs | |
5629 | there. */ | |
ddef6bc7 | 5630 | regno = subreg_regno (equiv); |
8ec450a4 | 5631 | equiv = gen_rtx_REG (rld[r].mode, regno); |
32131a9c RK |
5632 | } |
5633 | else | |
5634 | abort (); | |
5635 | } | |
5636 | ||
5637 | /* If we found a spill reg, reject it unless it is free | |
5638 | and of the desired class. */ | |
5639 | if (equiv != 0 | |
cb2afeb3 | 5640 | && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) |
c02cad8f BS |
5641 | && ! free_for_value_p (regno, rld[r].mode, |
5642 | rld[r].opnum, rld[r].when_needed, | |
5643 | rld[r].in, rld[r].out, r, 1)) | |
eceef4c9 | 5644 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
32131a9c RK |
5645 | regno))) |
5646 | equiv = 0; | |
5647 | ||
8ec450a4 | 5648 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
5649 | equiv = 0; |
5650 | ||
5651 | /* We found a register that contains the value we need. | |
5652 | If this register is the same as an `earlyclobber' operand | |
5653 | of the current insn, just mark it as a place to reload from | |
5654 | since we can't use it as the reload register itself. */ | |
5655 | ||
5656 | if (equiv != 0) | |
5657 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
5658 | if (reg_overlap_mentioned_for_reload_p (equiv, |
5659 | reload_earlyclobbers[i])) | |
32131a9c | 5660 | { |
4c3a2649 BS |
5661 | if (! rld[r].optional) |
5662 | reload_override_in[r] = equiv; | |
32131a9c RK |
5663 | equiv = 0; |
5664 | break; | |
5665 | } | |
5666 | ||
3c785e47 R |
5667 | /* If the equiv register we have found is explicitly clobbered |
5668 | in the current insn, it depends on the reload type if we | |
5669 | can use it, use it for reload_override_in, or not at all. | |
5670 | In particular, we then can't use EQUIV for a | |
5671 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 5672 | |
9532e31f | 5673 | if (equiv != 0) |
174fa2c4 | 5674 | { |
9532e31f BS |
5675 | if (regno_clobbered_p (regno, insn, rld[r].mode, 0)) |
5676 | switch (rld[r].when_needed) | |
5677 | { | |
5678 | case RELOAD_FOR_OTHER_ADDRESS: | |
5679 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5680 | case RELOAD_FOR_INPUT_ADDRESS: | |
5681 | case RELOAD_FOR_OPADDR_ADDR: | |
5682 | break; | |
5683 | case RELOAD_OTHER: | |
5684 | case RELOAD_FOR_INPUT: | |
5685 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5686 | if (! rld[r].optional) | |
5687 | reload_override_in[r] = equiv; | |
5688 | /* Fall through. */ | |
5689 | default: | |
5690 | equiv = 0; | |
5691 | break; | |
5692 | } | |
5693 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
5694 | switch (rld[r].when_needed) | |
5695 | { | |
5696 | case RELOAD_FOR_OTHER_ADDRESS: | |
5697 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5698 | case RELOAD_FOR_INPUT_ADDRESS: | |
5699 | case RELOAD_FOR_OPADDR_ADDR: | |
5700 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5701 | case RELOAD_FOR_INPUT: | |
5702 | break; | |
5703 | case RELOAD_OTHER: | |
5704 | if (! rld[r].optional) | |
5705 | reload_override_in[r] = equiv; | |
5706 | /* Fall through. */ | |
5707 | default: | |
5708 | equiv = 0; | |
5709 | break; | |
5710 | } | |
32131a9c RK |
5711 | } |
5712 | ||
5713 | /* If we found an equivalent reg, say no code need be generated | |
5714 | to load it, and use it as our reload reg. */ | |
3ec2ea3e | 5715 | if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM) |
32131a9c | 5716 | { |
8ec450a4 | 5717 | int nr = HARD_REGNO_NREGS (regno, rld[r].mode); |
100338df | 5718 | int k; |
eceef4c9 | 5719 | rld[r].reg_rtx = equiv; |
32131a9c | 5720 | reload_inherited[r] = 1; |
100338df | 5721 | |
91d7e7ac R |
5722 | /* If reg_reloaded_valid is not set for this register, |
5723 | there might be a stale spill_reg_store lying around. | |
5724 | We must clear it, since otherwise emit_reload_insns | |
5725 | might delete the store. */ | |
5726 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
5727 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
5728 | /* If any of the hard registers in EQUIV are spill |
5729 | registers, mark them as in use for this insn. */ | |
5730 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 5731 | { |
100338df JL |
5732 | i = spill_reg_order[regno + k]; |
5733 | if (i >= 0) | |
5734 | { | |
eceef4c9 BS |
5735 | mark_reload_reg_in_use (regno, rld[r].opnum, |
5736 | rld[r].when_needed, | |
8ec450a4 | 5737 | rld[r].mode); |
100338df JL |
5738 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
5739 | regno + k); | |
5740 | } | |
be7ae2a4 | 5741 | } |
32131a9c RK |
5742 | } |
5743 | } | |
5744 | ||
5745 | /* If we found a register to use already, or if this is an optional | |
5746 | reload, we are done. */ | |
eceef4c9 | 5747 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
5748 | continue; |
5749 | ||
1d7254c5 KH |
5750 | #if 0 |
5751 | /* No longer needed for correct operation. Might or might | |
5752 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
5753 | |
5754 | /* See if there is a later reload that has a class different from our | |
5755 | class that intersects our class or that requires less register | |
5756 | than our reload. If so, we must allocate a register to this | |
5757 | reload now, since that reload might inherit a previous reload | |
5758 | and take the only available register in our class. Don't do this | |
5759 | for optional reloads since they will force all previous reloads | |
5760 | to be allocated. Also don't do this for reloads that have been | |
5761 | turned off. */ | |
5762 | ||
5763 | for (i = j + 1; i < n_reloads; i++) | |
5764 | { | |
5765 | int s = reload_order[i]; | |
5766 | ||
eceef4c9 BS |
5767 | if ((rld[s].in == 0 && rld[s].out == 0 |
5768 | && ! rld[s].secondary_p) | |
5769 | || rld[s].optional) | |
32131a9c RK |
5770 | continue; |
5771 | ||
eceef4c9 BS |
5772 | if ((rld[s].class != rld[r].class |
5773 | && reg_classes_intersect_p (rld[r].class, | |
5774 | rld[s].class)) | |
8ec450a4 | 5775 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 5776 | break; |
32131a9c RK |
5777 | } |
5778 | ||
5779 | if (i == n_reloads) | |
5780 | continue; | |
5781 | ||
f5d8c9f4 | 5782 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
5783 | #endif |
5784 | } | |
5785 | ||
5786 | /* Now allocate reload registers for anything non-optional that | |
5787 | didn't get one yet. */ | |
5788 | for (j = 0; j < n_reloads; j++) | |
5789 | { | |
5790 | register int r = reload_order[j]; | |
5791 | ||
5792 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 5793 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
5794 | continue; |
5795 | ||
5796 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 5797 | optional. */ |
eceef4c9 | 5798 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
5799 | continue; |
5800 | ||
f5d8c9f4 | 5801 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
5802 | break; |
5803 | } | |
5804 | ||
5805 | /* If that loop got all the way, we have won. */ | |
5806 | if (j == n_reloads) | |
f5d8c9f4 BS |
5807 | { |
5808 | win = 1; | |
5809 | break; | |
5810 | } | |
32131a9c | 5811 | |
32131a9c | 5812 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
5813 | } |
5814 | ||
f5d8c9f4 BS |
5815 | if (! win) |
5816 | { | |
5817 | /* First undo everything done by the failed attempt | |
5818 | to allocate with inheritance. */ | |
5819 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
5820 | ||
5821 | /* Some sanity tests to verify that the reloads found in the first | |
5822 | pass are identical to the ones we have now. */ | |
5823 | if (chain->n_reloads != n_reloads) | |
5824 | abort (); | |
5825 | ||
5826 | for (i = 0; i < n_reloads; i++) | |
5827 | { | |
5828 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
5829 | continue; | |
5830 | if (chain->rld[i].when_needed != rld[i].when_needed) | |
5831 | abort (); | |
5832 | for (j = 0; j < n_spills; j++) | |
5833 | if (spill_regs[j] == chain->rld[i].regno) | |
5834 | if (! set_reload_reg (j, i)) | |
5835 | failed_reload (chain->insn, i); | |
5836 | } | |
5837 | } | |
5838 | ||
32131a9c RK |
5839 | /* If we thought we could inherit a reload, because it seemed that |
5840 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
5841 | verify that assumption, now that all reloads have been assigned. |
5842 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 5843 | |
cb2afeb3 R |
5844 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
5845 | cancel any inheritance, but removes reloads that have been needed only | |
5846 | for reloads that we know can be inherited. */ | |
5847 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 5848 | { |
cb2afeb3 | 5849 | for (j = 0; j < n_reloads; j++) |
029b38ff | 5850 | { |
cb2afeb3 R |
5851 | register int r = reload_order[j]; |
5852 | rtx check_reg; | |
eceef4c9 BS |
5853 | if (reload_inherited[r] && rld[r].reg_rtx) |
5854 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 R |
5855 | else if (reload_override_in[r] |
5856 | && (GET_CODE (reload_override_in[r]) == REG | |
05d10675 | 5857 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
5858 | check_reg = reload_override_in[r]; |
5859 | else | |
5860 | continue; | |
c02cad8f BS |
5861 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
5862 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
5863 | (reload_inherited[r] | |
5864 | ? rld[r].out : const0_rtx), | |
5865 | r, 1)) | |
029b38ff | 5866 | { |
cb2afeb3 R |
5867 | if (pass) |
5868 | continue; | |
5869 | reload_inherited[r] = 0; | |
5870 | reload_override_in[r] = 0; | |
029b38ff | 5871 | } |
cb2afeb3 R |
5872 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
5873 | reload_override_in, then we do not need its related | |
5874 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
5875 | likewise for other reload types. | |
5876 | We handle this by removing a reload when its only replacement | |
5877 | is mentioned in reload_in of the reload we are going to inherit. | |
5878 | A special case are auto_inc expressions; even if the input is | |
5879 | inherited, we still need the address for the output. We can | |
fe92fe26 | 5880 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
cb2afeb3 R |
5881 | If we suceeded removing some reload and we are doing a preliminary |
5882 | pass just to remove such reloads, make another pass, since the | |
5883 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
5884 | else if (rld[r].in |
5885 | && rld[r].out != rld[r].in | |
5886 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 5887 | pass = 2; |
32131a9c RK |
5888 | } |
5889 | } | |
5890 | ||
5891 | /* Now that reload_override_in is known valid, | |
5892 | actually override reload_in. */ | |
5893 | for (j = 0; j < n_reloads; j++) | |
5894 | if (reload_override_in[j]) | |
eceef4c9 | 5895 | rld[j].in = reload_override_in[j]; |
32131a9c RK |
5896 | |
5897 | /* If this reload won't be done because it has been cancelled or is | |
5898 | optional and not inherited, clear reload_reg_rtx so other | |
5899 | routines (such as subst_reloads) don't get confused. */ | |
5900 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5901 | if (rld[j].reg_rtx != 0 |
5902 | && ((rld[j].optional && ! reload_inherited[j]) | |
5903 | || (rld[j].in == 0 && rld[j].out == 0 | |
5904 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 5905 | { |
eceef4c9 | 5906 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
5907 | |
5908 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 5909 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 5910 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 5911 | rld[j].reg_rtx = 0; |
c0029be5 | 5912 | reload_spill_index[j] = -1; |
be7ae2a4 | 5913 | } |
32131a9c RK |
5914 | |
5915 | /* Record which pseudos and which spill regs have output reloads. */ | |
5916 | for (j = 0; j < n_reloads; j++) | |
5917 | { | |
5918 | register int r = reload_order[j]; | |
5919 | ||
5920 | i = reload_spill_index[r]; | |
5921 | ||
e6e52be0 | 5922 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 5923 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 5924 | that we opted to ignore. */ |
eceef4c9 BS |
5925 | if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG |
5926 | && rld[r].reg_rtx != 0) | |
32131a9c | 5927 | { |
eceef4c9 | 5928 | register int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
5929 | int nr = 1; |
5930 | ||
5931 | if (nregno < FIRST_PSEUDO_REGISTER) | |
8ec450a4 | 5932 | nr = HARD_REGNO_NREGS (nregno, rld[r].mode); |
32131a9c RK |
5933 | |
5934 | while (--nr >= 0) | |
372e033b RS |
5935 | reg_has_output_reload[nregno + nr] = 1; |
5936 | ||
5937 | if (i >= 0) | |
32131a9c | 5938 | { |
8ec450a4 | 5939 | nr = HARD_REGNO_NREGS (i, rld[r].mode); |
372e033b | 5940 | while (--nr >= 0) |
e6e52be0 | 5941 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
5942 | } |
5943 | ||
eceef4c9 BS |
5944 | if (rld[r].when_needed != RELOAD_OTHER |
5945 | && rld[r].when_needed != RELOAD_FOR_OUTPUT | |
5946 | && rld[r].when_needed != RELOAD_FOR_INSN) | |
32131a9c RK |
5947 | abort (); |
5948 | } | |
5949 | } | |
5950 | } | |
cb2afeb3 R |
5951 | |
5952 | /* Deallocate the reload register for reload R. This is called from | |
5953 | remove_address_replacements. */ | |
1d813780 | 5954 | |
cb2afeb3 R |
5955 | void |
5956 | deallocate_reload_reg (r) | |
5957 | int r; | |
5958 | { | |
5959 | int regno; | |
5960 | ||
eceef4c9 | 5961 | if (! rld[r].reg_rtx) |
cb2afeb3 | 5962 | return; |
eceef4c9 BS |
5963 | regno = true_regnum (rld[r].reg_rtx); |
5964 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 5965 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 5966 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 5967 | rld[r].mode); |
cb2afeb3 R |
5968 | reload_spill_index[r] = -1; |
5969 | } | |
32131a9c | 5970 | \f |
e9a25f70 | 5971 | /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two |
546b63fb RK |
5972 | reloads of the same item for fear that we might not have enough reload |
5973 | registers. However, normally they will get the same reload register | |
05d10675 | 5974 | and hence actually need not be loaded twice. |
546b63fb RK |
5975 | |
5976 | Here we check for the most common case of this phenomenon: when we have | |
5977 | a number of reloads for the same object, each of which were allocated | |
5978 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
5979 | reload, and is not modified in the insn itself. If we find such, | |
5980 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
5981 | This will not increase the number of spill registers needed and will | |
5982 | prevent redundant code. */ | |
5983 | ||
546b63fb RK |
5984 | static void |
5985 | merge_assigned_reloads (insn) | |
5986 | rtx insn; | |
5987 | { | |
5988 | int i, j; | |
5989 | ||
5990 | /* Scan all the reloads looking for ones that only load values and | |
5991 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
5992 | assigned and not modified by INSN. */ | |
5993 | ||
5994 | for (i = 0; i < n_reloads; i++) | |
5995 | { | |
d668e863 R |
5996 | int conflicting_input = 0; |
5997 | int max_input_address_opnum = -1; | |
5998 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
5999 | ||
eceef4c9 BS |
6000 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
6001 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
6002 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
6003 | continue; |
6004 | ||
6005 | /* Look at all other reloads. Ensure that the only use of this | |
6006 | reload_reg_rtx is in a reload that just loads the same value | |
6007 | as we do. Note that any secondary reloads must be of the identical | |
6008 | class since the values, modes, and result registers are the | |
6009 | same, so we need not do anything with any secondary reloads. */ | |
6010 | ||
6011 | for (j = 0; j < n_reloads; j++) | |
6012 | { | |
eceef4c9 BS |
6013 | if (i == j || rld[j].reg_rtx == 0 |
6014 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6015 | rld[i].reg_rtx)) | |
546b63fb RK |
6016 | continue; |
6017 | ||
eceef4c9 BS |
6018 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6019 | && rld[j].opnum > max_input_address_opnum) | |
6020 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 6021 | |
546b63fb | 6022 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
6023 | or if the values are different, we can't merge this reload. |
6024 | But if it is an input reload, we might still merge | |
6025 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 6026 | |
eceef4c9 BS |
6027 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6028 | || rld[j].out != 0 || rld[j].in == 0 | |
6029 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 6030 | { |
eceef4c9 BS |
6031 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6032 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6033 | || rld[i].opnum > rld[j].opnum) | |
6034 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
6035 | break; |
6036 | conflicting_input = 1; | |
eceef4c9 BS |
6037 | if (min_conflicting_input_opnum > rld[j].opnum) |
6038 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 6039 | } |
546b63fb RK |
6040 | } |
6041 | ||
6042 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6043 | we, in fact, found any matching reloads. */ | |
6044 | ||
d668e863 R |
6045 | if (j == n_reloads |
6046 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb RK |
6047 | { |
6048 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
6049 | if (i != j && rld[j].reg_rtx != 0 |
6050 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 6051 | && (! conflicting_input |
eceef4c9 BS |
6052 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6053 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 6054 | { |
eceef4c9 BS |
6055 | rld[i].when_needed = RELOAD_OTHER; |
6056 | rld[j].in = 0; | |
efdb3590 | 6057 | reload_spill_index[j] = -1; |
546b63fb RK |
6058 | transfer_replacements (i, j); |
6059 | } | |
6060 | ||
6061 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
6062 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
6063 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
6064 | this test is equivalent to looking for reloads for this operand | |
6065 | number. */ | |
6066 | ||
eceef4c9 | 6067 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 6068 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 6069 | if (rld[j].in != 0 |
91667711 | 6070 | && rld[j].when_needed != RELOAD_OTHER |
eceef4c9 BS |
6071 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6072 | rld[i].in)) | |
6073 | rld[j].when_needed | |
91667711 SC |
6074 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6075 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
47c8cf91 | 6076 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); |
546b63fb RK |
6077 | } |
6078 | } | |
05d10675 | 6079 | } |
546b63fb | 6080 | \f |
367b1cf5 BS |
6081 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6082 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6083 | static rtx other_input_address_reload_insns = 0; | |
6084 | static rtx other_input_reload_insns = 0; | |
6085 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6086 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6087 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6088 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6089 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6090 | static rtx operand_reload_insns = 0; | |
6091 | static rtx other_operand_reload_insns = 0; | |
6092 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6093 | ||
6094 | /* Values to be put in spill_reg_store are put here first. */ | |
6095 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6096 | static HARD_REG_SET reg_reloaded_died; | |
6097 | ||
6098 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and | |
6099 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6100 | |
32131a9c | 6101 | static void |
367b1cf5 | 6102 | emit_input_reload_insns (chain, rl, old, j) |
7609e720 | 6103 | struct insn_chain *chain; |
367b1cf5 BS |
6104 | struct reload *rl; |
6105 | rtx old; | |
6106 | int j; | |
32131a9c | 6107 | { |
7609e720 | 6108 | rtx insn = chain->insn; |
367b1cf5 BS |
6109 | register rtx reloadreg = rl->reg_rtx; |
6110 | rtx oldequiv_reg = 0; | |
6111 | rtx oldequiv = 0; | |
6112 | int special = 0; | |
6113 | enum machine_mode mode; | |
6114 | rtx *where; | |
6115 | ||
6116 | /* Determine the mode to reload in. | |
6117 | This is very tricky because we have three to choose from. | |
6118 | There is the mode the insn operand wants (rl->inmode). | |
6119 | There is the mode of the reload register RELOADREG. | |
6120 | There is the intrinsic mode of the operand, which we could find | |
6121 | by stripping some SUBREGs. | |
6122 | It turns out that RELOADREG's mode is irrelevant: | |
6123 | we can change that arbitrarily. | |
6124 | ||
6125 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
6126 | then the reload reg may not support QImode moves, so use SImode. | |
6127 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
6128 | because the QImode value is in the least significant part of a | |
6129 | slot big enough for a SImode. If foo is some other sort of | |
6130 | memory reference, then it is impossible to reload this case, | |
6131 | so previous passes had better make sure this never happens. | |
6132 | ||
6133 | Then consider a one-word union which has SImode and one of its | |
6134 | members is a float, being fetched as (SUBREG:SF union:SI). | |
6135 | We must fetch that as SFmode because we could be loading into | |
6136 | a float-only register. In this case OLD's mode is correct. | |
6137 | ||
6138 | Consider an immediate integer: it has VOIDmode. Here we need | |
6139 | to get a mode from something else. | |
6140 | ||
6141 | In some cases, there is a fourth mode, the operand's | |
6142 | containing mode. If the insn specifies a containing mode for | |
6143 | this operand, it overrides all others. | |
6144 | ||
6145 | I am not sure whether the algorithm here is always right, | |
6146 | but it does the right things in those cases. */ | |
6147 | ||
6148 | mode = GET_MODE (old); | |
6149 | if (mode == VOIDmode) | |
6150 | mode = rl->inmode; | |
7609e720 | 6151 | |
367b1cf5 BS |
6152 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6153 | /* If we need a secondary register for this operation, see if | |
6154 | the value is already in a register in that class. Don't | |
6155 | do this if the secondary register will be used as a scratch | |
6156 | register. */ | |
6157 | ||
6158 | if (rl->secondary_in_reload >= 0 | |
6159 | && rl->secondary_in_icode == CODE_FOR_nothing | |
6160 | && optimize) | |
6161 | oldequiv | |
6162 | = find_equiv_reg (old, insn, | |
6163 | rld[rl->secondary_in_reload].class, | |
9714cf43 | 6164 | -1, NULL, 0, mode); |
367b1cf5 | 6165 | #endif |
e6e52be0 | 6166 | |
367b1cf5 BS |
6167 | /* If reloading from memory, see if there is a register |
6168 | that already holds the same value. If so, reload from there. | |
6169 | We can pass 0 as the reload_reg_p argument because | |
6170 | any other reload has either already been emitted, | |
6171 | in which case find_equiv_reg will see the reload-insn, | |
6172 | or has yet to be emitted, in which case it doesn't matter | |
6173 | because we will use this equiv reg right away. */ | |
6174 | ||
6175 | if (oldequiv == 0 && optimize | |
6176 | && (GET_CODE (old) == MEM | |
6177 | || (GET_CODE (old) == REG | |
6178 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6179 | && reg_renumber[REGNO (old)] < 0))) | |
9714cf43 | 6180 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode); |
367b1cf5 BS |
6181 | |
6182 | if (oldequiv) | |
6183 | { | |
770ae6cc | 6184 | unsigned int regno = true_regnum (oldequiv); |
367b1cf5 BS |
6185 | |
6186 | /* Don't use OLDEQUIV if any other reload changes it at an | |
6187 | earlier stage of this insn or at this stage. */ | |
c02cad8f BS |
6188 | if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed, |
6189 | rl->in, const0_rtx, j, 0)) | |
367b1cf5 BS |
6190 | oldequiv = 0; |
6191 | ||
6192 | /* If it is no cheaper to copy from OLDEQUIV into the | |
6193 | reload register than it would be to move from memory, | |
6194 | don't use it. Likewise, if we need a secondary register | |
6195 | or memory. */ | |
6196 | ||
6197 | if (oldequiv != 0 | |
6198 | && ((REGNO_REG_CLASS (regno) != rl->class | |
e56b4594 | 6199 | && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno), |
367b1cf5 BS |
6200 | rl->class) |
6201 | >= MEMORY_MOVE_COST (mode, rl->class, 1))) | |
6202 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
6203 | || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6204 | mode, oldequiv) | |
6205 | != NO_REGS) | |
6206 | #endif | |
6207 | #ifdef SECONDARY_MEMORY_NEEDED | |
6208 | || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), | |
6209 | rl->class, | |
6210 | mode) | |
6211 | #endif | |
6212 | )) | |
6213 | oldequiv = 0; | |
6214 | } | |
32131a9c | 6215 | |
367b1cf5 BS |
6216 | /* delete_output_reload is only invoked properly if old contains |
6217 | the original pseudo register. Since this is replaced with a | |
6218 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6219 | find the pseudo in RELOAD_IN_REG. */ | |
6220 | if (oldequiv == 0 | |
6221 | && reload_override_in[j] | |
6222 | && GET_CODE (rl->in_reg) == REG) | |
6223 | { | |
6224 | oldequiv = old; | |
6225 | old = rl->in_reg; | |
6226 | } | |
6227 | if (oldequiv == 0) | |
6228 | oldequiv = old; | |
6229 | else if (GET_CODE (oldequiv) == REG) | |
6230 | oldequiv_reg = oldequiv; | |
6231 | else if (GET_CODE (oldequiv) == SUBREG) | |
6232 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6233 | ||
6234 | /* If we are reloading from a register that was recently stored in | |
6235 | with an output-reload, see if we can prove there was | |
6236 | actually no need to store the old value in it. */ | |
6237 | ||
6238 | if (optimize && GET_CODE (oldequiv) == REG | |
6239 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6240 | && spill_reg_store[REGNO (oldequiv)] | |
6241 | && GET_CODE (old) == REG | |
6242 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) | |
6243 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6244 | rl->out_reg))) | |
6245 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6246 | ||
6247 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6248 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6249 | gen_lowpart_common since it can do the wrong thing when | |
6250 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6251 | must always be a REG here. */ | |
6252 | ||
6253 | if (GET_MODE (reloadreg) != mode) | |
6254 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6255 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) | |
6256 | oldequiv = SUBREG_REG (oldequiv); | |
6257 | if (GET_MODE (oldequiv) != VOIDmode | |
6258 | && mode != GET_MODE (oldequiv)) | |
ddef6bc7 | 6259 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
367b1cf5 BS |
6260 | |
6261 | /* Switch to the right place to emit the reload insns. */ | |
6262 | switch (rl->when_needed) | |
6263 | { | |
6264 | case RELOAD_OTHER: | |
6265 | where = &other_input_reload_insns; | |
6266 | break; | |
6267 | case RELOAD_FOR_INPUT: | |
6268 | where = &input_reload_insns[rl->opnum]; | |
6269 | break; | |
6270 | case RELOAD_FOR_INPUT_ADDRESS: | |
6271 | where = &input_address_reload_insns[rl->opnum]; | |
6272 | break; | |
6273 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6274 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6275 | break; | |
6276 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6277 | where = &output_address_reload_insns[rl->opnum]; | |
6278 | break; | |
6279 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6280 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6281 | break; | |
6282 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6283 | where = &operand_reload_insns; | |
6284 | break; | |
6285 | case RELOAD_FOR_OPADDR_ADDR: | |
6286 | where = &other_operand_reload_insns; | |
6287 | break; | |
6288 | case RELOAD_FOR_OTHER_ADDRESS: | |
6289 | where = &other_input_address_reload_insns; | |
6290 | break; | |
6291 | default: | |
6292 | abort (); | |
6293 | } | |
546b63fb | 6294 | |
367b1cf5 | 6295 | push_to_sequence (*where); |
32131a9c | 6296 | |
367b1cf5 BS |
6297 | /* Auto-increment addresses must be reloaded in a special way. */ |
6298 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6299 | { |
367b1cf5 BS |
6300 | /* We are not going to bother supporting the case where a |
6301 | incremented register can't be copied directly from | |
6302 | OLDEQUIV since this seems highly unlikely. */ | |
6303 | if (rl->secondary_in_reload >= 0) | |
6304 | abort (); | |
32131a9c | 6305 | |
367b1cf5 BS |
6306 | if (reload_inherited[j]) |
6307 | oldequiv = reloadreg; | |
cb2afeb3 | 6308 | |
367b1cf5 | 6309 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6310 | |
367b1cf5 BS |
6311 | if (optimize && GET_CODE (oldequiv) == REG |
6312 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6313 | && spill_reg_store[REGNO (oldequiv)] | |
6314 | && GET_CODE (old) == REG | |
6315 | && (dead_or_set_p (insn, | |
6316 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6317 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6318 | old))) | |
6319 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6320 | ||
6321 | /* Prevent normal processing of this reload. */ | |
6322 | special = 1; | |
6323 | /* Output a special code sequence for this case. */ | |
6324 | new_spill_reg_store[REGNO (reloadreg)] | |
6325 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6326 | rl->inc); | |
6327 | } | |
32131a9c | 6328 | |
367b1cf5 BS |
6329 | /* If we are reloading a pseudo-register that was set by the previous |
6330 | insn, see if we can get rid of that pseudo-register entirely | |
6331 | by redirecting the previous insn into our reload register. */ | |
6332 | ||
6333 | else if (optimize && GET_CODE (old) == REG | |
6334 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6335 | && dead_or_set_p (insn, old) | |
6336 | /* This is unsafe if some other reload | |
6337 | uses the same reg first. */ | |
ff6534ad | 6338 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6339 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6340 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6341 | { |
6342 | rtx temp = PREV_INSN (insn); | |
6343 | while (temp && GET_CODE (temp) == NOTE) | |
6344 | temp = PREV_INSN (temp); | |
6345 | if (temp | |
6346 | && GET_CODE (temp) == INSN | |
6347 | && GET_CODE (PATTERN (temp)) == SET | |
6348 | && SET_DEST (PATTERN (temp)) == old | |
6349 | /* Make sure we can access insn_operand_constraint. */ | |
6350 | && asm_noperands (PATTERN (temp)) < 0 | |
6351 | /* This is unsafe if prev insn rejects our reload reg. */ | |
6352 | && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint, | |
6353 | reloadreg) | |
6354 | /* This is unsafe if operand occurs more than once in current | |
6355 | insn. Perhaps some occurrences aren't reloaded. */ | |
4b983fdc | 6356 | && count_occurrences (PATTERN (insn), old, 0) == 1 |
367b1cf5 BS |
6357 | /* Don't risk splitting a matching pair of operands. */ |
6358 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
6359 | { | |
6360 | /* Store into the reload register instead of the pseudo. */ | |
6361 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6362 | ||
6363 | /* If the previous insn is an output reload, the source is | |
6364 | a reload register, and its spill_reg_store entry will | |
6365 | contain the previous destination. This is now | |
6366 | invalid. */ | |
6367 | if (GET_CODE (SET_SRC (PATTERN (temp))) == REG | |
6368 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) | |
32131a9c | 6369 | { |
367b1cf5 BS |
6370 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; |
6371 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
32131a9c RK |
6372 | } |
6373 | ||
367b1cf5 BS |
6374 | /* If these are the only uses of the pseudo reg, |
6375 | pretend for GDB it lives in the reload reg we used. */ | |
6376 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6377 | && REG_N_SETS (REGNO (old)) == 1) | |
cb2afeb3 | 6378 | { |
367b1cf5 BS |
6379 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); |
6380 | alter_reg (REGNO (old), -1); | |
32131a9c | 6381 | } |
07875628 | 6382 | special = 1; |
367b1cf5 BS |
6383 | } |
6384 | } | |
32131a9c | 6385 | |
367b1cf5 | 6386 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6387 | |
367b1cf5 BS |
6388 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6389 | /* If we have a secondary reload, pick up the secondary register | |
6390 | and icode, if any. If OLDEQUIV and OLD are different or | |
6391 | if this is an in-out reload, recompute whether or not we | |
6392 | still need a secondary register and what the icode should | |
6393 | be. If we still need a secondary register and the class or | |
6394 | icode is different, go back to reloading from OLD if using | |
6395 | OLDEQUIV means that we got the wrong type of register. We | |
6396 | cannot have different class or icode due to an in-out reload | |
6397 | because we don't make such reloads when both the input and | |
6398 | output need secondary reload registers. */ | |
6399 | ||
07875628 | 6400 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6401 | { |
6402 | rtx second_reload_reg = 0; | |
6403 | int secondary_reload = rl->secondary_in_reload; | |
6404 | rtx real_oldequiv = oldequiv; | |
6405 | rtx real_old = old; | |
6406 | rtx tmp; | |
6407 | enum insn_code icode; | |
6408 | ||
6409 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6410 | and similarly for OLD. | |
6411 | See comments in get_secondary_reload in reload.c. */ | |
6412 | /* If it is a pseudo that cannot be replaced with its | |
6413 | equivalent MEM, we must fall back to reload_in, which | |
6414 | will have all the necessary substitutions registered. | |
6415 | Likewise for a pseudo that can't be replaced with its | |
6416 | equivalent constant. | |
6417 | ||
6418 | Take extra care for subregs of such pseudos. Note that | |
6419 | we cannot use reg_equiv_mem in this case because it is | |
6420 | not in the right mode. */ | |
6421 | ||
6422 | tmp = oldequiv; | |
6423 | if (GET_CODE (tmp) == SUBREG) | |
6424 | tmp = SUBREG_REG (tmp); | |
6425 | if (GET_CODE (tmp) == REG | |
6426 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6427 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6428 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6429 | { | |
6430 | if (! reg_equiv_mem[REGNO (tmp)] | |
6431 | || num_not_at_initial_offset | |
6432 | || GET_CODE (oldequiv) == SUBREG) | |
6433 | real_oldequiv = rl->in; | |
6434 | else | |
6435 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6436 | } | |
32131a9c | 6437 | |
367b1cf5 BS |
6438 | tmp = old; |
6439 | if (GET_CODE (tmp) == SUBREG) | |
6440 | tmp = SUBREG_REG (tmp); | |
6441 | if (GET_CODE (tmp) == REG | |
6442 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6443 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6444 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6445 | { | |
6446 | if (! reg_equiv_mem[REGNO (tmp)] | |
6447 | || num_not_at_initial_offset | |
6448 | || GET_CODE (old) == SUBREG) | |
6449 | real_old = rl->in; | |
6450 | else | |
6451 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6452 | } | |
6453 | ||
6454 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
6455 | icode = rl->secondary_in_icode; | |
6456 | ||
6457 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6458 | || (rl->in != 0 && rl->out != 0)) | |
6459 | { | |
6460 | enum reg_class new_class | |
6461 | = SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6462 | mode, real_oldequiv); | |
6463 | ||
6464 | if (new_class == NO_REGS) | |
6465 | second_reload_reg = 0; | |
6466 | else | |
32131a9c | 6467 | { |
367b1cf5 BS |
6468 | enum insn_code new_icode; |
6469 | enum machine_mode new_mode; | |
6470 | ||
6471 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
6472 | REGNO (second_reload_reg))) | |
6473 | oldequiv = old, real_oldequiv = real_old; | |
6474 | else | |
32131a9c | 6475 | { |
367b1cf5 BS |
6476 | new_icode = reload_in_optab[(int) mode]; |
6477 | if (new_icode != CODE_FOR_nothing | |
6478 | && ((insn_data[(int) new_icode].operand[0].predicate | |
6479 | && ! ((*insn_data[(int) new_icode].operand[0].predicate) | |
6480 | (reloadreg, mode))) | |
6481 | || (insn_data[(int) new_icode].operand[1].predicate | |
6482 | && ! ((*insn_data[(int) new_icode].operand[1].predicate) | |
6483 | (real_oldequiv, mode))))) | |
6484 | new_icode = CODE_FOR_nothing; | |
6485 | ||
6486 | if (new_icode == CODE_FOR_nothing) | |
6487 | new_mode = mode; | |
6488 | else | |
6489 | new_mode = insn_data[(int) new_icode].operand[2].mode; | |
d30e8ef0 | 6490 | |
367b1cf5 | 6491 | if (GET_MODE (second_reload_reg) != new_mode) |
32131a9c | 6492 | { |
367b1cf5 BS |
6493 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), |
6494 | new_mode)) | |
6495 | oldequiv = old, real_oldequiv = real_old; | |
6496 | else | |
6497 | second_reload_reg | |
6498 | = gen_rtx_REG (new_mode, | |
6499 | REGNO (second_reload_reg)); | |
32131a9c | 6500 | } |
32131a9c RK |
6501 | } |
6502 | } | |
367b1cf5 | 6503 | } |
32131a9c | 6504 | |
367b1cf5 BS |
6505 | /* If we still need a secondary reload register, check |
6506 | to see if it is being used as a scratch or intermediate | |
6507 | register and generate code appropriately. If we need | |
6508 | a scratch register, use REAL_OLDEQUIV since the form of | |
6509 | the insn may depend on the actual address if it is | |
6510 | a MEM. */ | |
546b63fb | 6511 | |
367b1cf5 BS |
6512 | if (second_reload_reg) |
6513 | { | |
6514 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6515 | { |
367b1cf5 BS |
6516 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6517 | second_reload_reg)); | |
07875628 | 6518 | special = 1; |
367b1cf5 BS |
6519 | } |
6520 | else | |
6521 | { | |
6522 | /* See if we need a scratch register to load the | |
6523 | intermediate register (a tertiary reload). */ | |
6524 | enum insn_code tertiary_icode | |
6525 | = rld[secondary_reload].secondary_in_icode; | |
1554c2c6 | 6526 | |
367b1cf5 BS |
6527 | if (tertiary_icode != CODE_FOR_nothing) |
6528 | { | |
6529 | rtx third_reload_reg | |
6530 | = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; | |
1554c2c6 | 6531 | |
367b1cf5 BS |
6532 | emit_insn ((GEN_FCN (tertiary_icode) |
6533 | (second_reload_reg, real_oldequiv, | |
6534 | third_reload_reg))); | |
6535 | } | |
6536 | else | |
6537 | gen_reload (second_reload_reg, real_oldequiv, | |
6538 | rl->opnum, | |
6539 | rl->when_needed); | |
32131a9c | 6540 | |
367b1cf5 BS |
6541 | oldequiv = second_reload_reg; |
6542 | } | |
6543 | } | |
6544 | } | |
6545 | #endif | |
32131a9c | 6546 | |
07875628 | 6547 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6548 | { |
6549 | rtx real_oldequiv = oldequiv; | |
6550 | ||
6551 | if ((GET_CODE (oldequiv) == REG | |
6552 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
6553 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6554 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6555 | || (GET_CODE (oldequiv) == SUBREG | |
6556 | && GET_CODE (SUBREG_REG (oldequiv)) == REG | |
6557 | && (REGNO (SUBREG_REG (oldequiv)) | |
6558 | >= FIRST_PSEUDO_REGISTER) | |
6559 | && ((reg_equiv_memory_loc | |
6560 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6561 | || (reg_equiv_constant | |
716120a7 JJ |
6562 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
6563 | || (CONSTANT_P (oldequiv) | |
6564 | && PREFERRED_RELOAD_CLASS (oldequiv, | |
6565 | REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS)) | |
367b1cf5 BS |
6566 | real_oldequiv = rl->in; |
6567 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6568 | rl->when_needed); | |
6569 | } | |
32131a9c | 6570 | |
94bd63e5 AH |
6571 | if (flag_non_call_exceptions) |
6572 | copy_eh_notes (insn, get_insns ()); | |
6573 | ||
367b1cf5 BS |
6574 | /* End this sequence. */ |
6575 | *where = get_insns (); | |
6576 | end_sequence (); | |
94bd63e5 | 6577 | |
367b1cf5 BS |
6578 | /* Update reload_override_in so that delete_address_reloads_1 |
6579 | can see the actual register usage. */ | |
6580 | if (oldequiv_reg) | |
6581 | reload_override_in[j] = oldequiv; | |
6582 | } | |
32131a9c | 6583 | |
367b1cf5 BS |
6584 | /* Generate insns to for the output reload RL, which is for the insn described |
6585 | by CHAIN and has the number J. */ | |
6586 | static void | |
6587 | emit_output_reload_insns (chain, rl, j) | |
6588 | struct insn_chain *chain; | |
6589 | struct reload *rl; | |
6590 | int j; | |
6591 | { | |
6592 | rtx reloadreg = rl->reg_rtx; | |
6593 | rtx insn = chain->insn; | |
6594 | int special = 0; | |
6595 | rtx old = rl->out; | |
6596 | enum machine_mode mode = GET_MODE (old); | |
6597 | rtx p; | |
32131a9c | 6598 | |
367b1cf5 BS |
6599 | if (rl->when_needed == RELOAD_OTHER) |
6600 | start_sequence (); | |
6601 | else | |
6602 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 6603 | |
367b1cf5 BS |
6604 | /* Determine the mode to reload in. |
6605 | See comments above (for input reloading). */ | |
32131a9c | 6606 | |
367b1cf5 BS |
6607 | if (mode == VOIDmode) |
6608 | { | |
6609 | /* VOIDmode should never happen for an output. */ | |
6610 | if (asm_noperands (PATTERN (insn)) < 0) | |
6611 | /* It's the compiler's fault. */ | |
6612 | fatal_insn ("VOIDmode on an output", insn); | |
6613 | error_for_asm (insn, "output operand is constant in `asm'"); | |
6614 | /* Prevent crash--use something we know is valid. */ | |
6615 | mode = word_mode; | |
6616 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6617 | } | |
546b63fb | 6618 | |
367b1cf5 BS |
6619 | if (GET_MODE (reloadreg) != mode) |
6620 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
32131a9c | 6621 | |
367b1cf5 | 6622 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
32131a9c | 6623 | |
367b1cf5 BS |
6624 | /* If we need two reload regs, set RELOADREG to the intermediate |
6625 | one, since it will be stored into OLD. We might need a secondary | |
6626 | register only for an input reload, so check again here. */ | |
32131a9c | 6627 | |
367b1cf5 BS |
6628 | if (rl->secondary_out_reload >= 0) |
6629 | { | |
6630 | rtx real_old = old; | |
cb2afeb3 | 6631 | |
367b1cf5 BS |
6632 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6633 | && reg_equiv_mem[REGNO (old)] != 0) | |
6634 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 6635 | |
367b1cf5 BS |
6636 | if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, |
6637 | mode, real_old) | |
6638 | != NO_REGS)) | |
b60a8416 | 6639 | { |
367b1cf5 BS |
6640 | rtx second_reloadreg = reloadreg; |
6641 | reloadreg = rld[rl->secondary_out_reload].reg_rtx; | |
32131a9c | 6642 | |
367b1cf5 BS |
6643 | /* See if RELOADREG is to be used as a scratch register |
6644 | or as an intermediate register. */ | |
6645 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
6646 | { | |
6647 | emit_insn ((GEN_FCN (rl->secondary_out_icode) | |
6648 | (real_old, second_reloadreg, reloadreg))); | |
6649 | special = 1; | |
6650 | } | |
6651 | else | |
6652 | { | |
6653 | /* See if we need both a scratch and intermediate reload | |
6654 | register. */ | |
32131a9c | 6655 | |
367b1cf5 BS |
6656 | int secondary_reload = rl->secondary_out_reload; |
6657 | enum insn_code tertiary_icode | |
6658 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 6659 | |
367b1cf5 BS |
6660 | if (GET_MODE (reloadreg) != mode) |
6661 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
cb2afeb3 | 6662 | |
367b1cf5 BS |
6663 | if (tertiary_icode != CODE_FOR_nothing) |
6664 | { | |
6665 | rtx third_reloadreg | |
6666 | = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; | |
6667 | rtx tem; | |
6668 | ||
6669 | /* Copy primary reload reg to secondary reload reg. | |
6670 | (Note that these have been swapped above, then | |
78adc5a0 | 6671 | secondary reload reg to OLD using our insn.) */ |
367b1cf5 BS |
6672 | |
6673 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
6674 | and try to put the opposite SUBREG on | |
6675 | RELOADREG. */ | |
6676 | if (GET_CODE (real_old) == SUBREG | |
6677 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
6678 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
6679 | && 0 != (tem = gen_lowpart_common | |
6680 | (GET_MODE (SUBREG_REG (real_old)), | |
6681 | reloadreg))) | |
6682 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
6683 | ||
6684 | gen_reload (reloadreg, second_reloadreg, | |
6685 | rl->opnum, rl->when_needed); | |
6686 | emit_insn ((GEN_FCN (tertiary_icode) | |
6687 | (real_old, reloadreg, third_reloadreg))); | |
6688 | special = 1; | |
6689 | } | |
05d10675 | 6690 | |
367b1cf5 BS |
6691 | else |
6692 | /* Copy between the reload regs here and then to | |
6693 | OUT later. */ | |
cb2afeb3 | 6694 | |
367b1cf5 BS |
6695 | gen_reload (reloadreg, second_reloadreg, |
6696 | rl->opnum, rl->when_needed); | |
a7911cd2 | 6697 | } |
367b1cf5 BS |
6698 | } |
6699 | } | |
32131a9c RK |
6700 | #endif |
6701 | ||
367b1cf5 BS |
6702 | /* Output the last reload insn. */ |
6703 | if (! special) | |
6704 | { | |
6705 | rtx set; | |
6706 | ||
6707 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 6708 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 BS |
6709 | if (! flag_expensive_optimizations |
6710 | || GET_CODE (old) != REG | |
6711 | || !(set = single_set (insn)) | |
6712 | || rtx_equal_p (old, SET_DEST (set)) | |
6713 | || !reg_mentioned_p (old, SET_SRC (set)) | |
9532e31f | 6714 | || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0)) |
367b1cf5 BS |
6715 | gen_reload (old, reloadreg, rl->opnum, |
6716 | rl->when_needed); | |
6717 | } | |
32131a9c | 6718 | |
367b1cf5 BS |
6719 | /* Look at all insns we emitted, just to be safe. */ |
6720 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 6721 | if (INSN_P (p)) |
367b1cf5 BS |
6722 | { |
6723 | rtx pat = PATTERN (p); | |
546b63fb | 6724 | |
367b1cf5 BS |
6725 | /* If this output reload doesn't come from a spill reg, |
6726 | clear any memory of reloaded copies of the pseudo reg. | |
6727 | If this output reload comes from a spill reg, | |
6728 | reg_has_output_reload will make this do nothing. */ | |
6729 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 6730 | |
367b1cf5 BS |
6731 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
6732 | { | |
6733 | rtx set = single_set (insn); | |
6734 | if (reload_spill_index[j] < 0 | |
6735 | && set | |
6736 | && SET_SRC (set) == rl->reg_rtx) | |
6737 | { | |
6738 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 6739 | |
367b1cf5 BS |
6740 | reload_spill_index[j] = src; |
6741 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
6742 | if (find_regno_note (insn, REG_DEAD, src)) | |
6743 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
6744 | } | |
6745 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6746 | { | |
6747 | int s = rl->secondary_out_reload; | |
6748 | set = single_set (p); | |
6749 | /* If this reload copies only to the secondary reload | |
6750 | register, the secondary reload does the actual | |
6751 | store. */ | |
6752 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
6753 | /* We can't tell what function the secondary reload |
6754 | has and where the actual store to the pseudo is | |
6755 | made; leave new_spill_reg_store alone. */ | |
6756 | ; | |
367b1cf5 BS |
6757 | else if (s >= 0 |
6758 | && SET_SRC (set) == rl->reg_rtx | |
6759 | && SET_DEST (set) == rld[s].reg_rtx) | |
6760 | { | |
6761 | /* Usually the next instruction will be the | |
6762 | secondary reload insn; if we can confirm | |
6763 | that it is, setting new_spill_reg_store to | |
6764 | that insn will allow an extra optimization. */ | |
6765 | rtx s_reg = rld[s].reg_rtx; | |
6766 | rtx next = NEXT_INSN (p); | |
6767 | rld[s].out = rl->out; | |
6768 | rld[s].out_reg = rl->out_reg; | |
6769 | set = single_set (next); | |
6770 | if (set && SET_SRC (set) == s_reg | |
6771 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
6772 | { | |
6773 | SET_HARD_REG_BIT (reg_is_output_reload, | |
6774 | REGNO (s_reg)); | |
6775 | new_spill_reg_store[REGNO (s_reg)] = next; | |
6776 | } | |
6777 | } | |
6778 | else | |
6779 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
6780 | } | |
6781 | } | |
6782 | } | |
32131a9c | 6783 | |
367b1cf5 BS |
6784 | if (rl->when_needed == RELOAD_OTHER) |
6785 | { | |
6786 | emit_insns (other_output_reload_insns[rl->opnum]); | |
6787 | other_output_reload_insns[rl->opnum] = get_insns (); | |
6788 | } | |
6789 | else | |
6790 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 6791 | |
94bd63e5 AH |
6792 | if (flag_non_call_exceptions) |
6793 | copy_eh_notes (insn, get_insns ()); | |
6794 | ||
1d7254c5 | 6795 | end_sequence (); |
367b1cf5 | 6796 | } |
32131a9c | 6797 | |
367b1cf5 BS |
6798 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
6799 | and has the number J. */ | |
6800 | static void | |
6801 | do_input_reload (chain, rl, j) | |
6802 | struct insn_chain *chain; | |
6803 | struct reload *rl; | |
6804 | int j; | |
6805 | { | |
6806 | int expect_occurrences = 1; | |
6807 | rtx insn = chain->insn; | |
6808 | rtx old = (rl->in && GET_CODE (rl->in) == MEM | |
6809 | ? rl->in_reg : rl->in); | |
6810 | ||
6811 | if (old != 0 | |
6812 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
6813 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
6814 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
6815 | && ! rtx_equal_p (rl->reg_rtx, old) | |
6816 | && rl->reg_rtx != 0) | |
1d813780 | 6817 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 6818 | |
367b1cf5 BS |
6819 | /* When inheriting a wider reload, we have a MEM in rl->in, |
6820 | e.g. inheriting a SImode output reload for | |
6821 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
6822 | if (optimize && reload_inherited[j] && rl->in | |
6823 | && GET_CODE (rl->in) == MEM | |
6824 | && GET_CODE (rl->in_reg) == MEM | |
6825 | && reload_spill_index[j] >= 0 | |
6826 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
6827 | { | |
6828 | expect_occurrences | |
4b983fdc | 6829 | = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1; |
1d7254c5 | 6830 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
367b1cf5 | 6831 | } |
32131a9c | 6832 | |
367b1cf5 BS |
6833 | /* If we are reloading a register that was recently stored in with an |
6834 | output-reload, see if we can prove there was | |
6835 | actually no need to store the old value in it. */ | |
32131a9c | 6836 | |
367b1cf5 BS |
6837 | if (optimize |
6838 | && (reload_inherited[j] || reload_override_in[j]) | |
6839 | && rl->reg_rtx | |
6840 | && GET_CODE (rl->reg_rtx) == REG | |
6841 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 | |
6842 | #if 0 | |
6843 | /* There doesn't seem to be any reason to restrict this to pseudos | |
6844 | and doing so loses in the case where we are copying from a | |
6845 | register of the wrong class. */ | |
6846 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6847 | >= FIRST_PSEUDO_REGISTER) | |
6848 | #endif | |
6849 | /* The insn might have already some references to stackslots | |
6850 | replaced by MEMs, while reload_out_reg still names the | |
6851 | original pseudo. */ | |
6852 | && (dead_or_set_p (insn, | |
6853 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6854 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
6855 | rl->out_reg))) | |
6856 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
6857 | } | |
32131a9c | 6858 | |
367b1cf5 BS |
6859 | /* Do output reloading for reload RL, which is for the insn described by |
6860 | CHAIN and has the number J. | |
6861 | ??? At some point we need to support handling output reloads of | |
6862 | JUMP_INSNs or insns that set cc0. */ | |
6863 | static void | |
6864 | do_output_reload (chain, rl, j) | |
6865 | struct insn_chain *chain; | |
6866 | struct reload *rl; | |
6867 | int j; | |
6868 | { | |
6869 | rtx note, old; | |
6870 | rtx insn = chain->insn; | |
6871 | /* If this is an output reload that stores something that is | |
6872 | not loaded in this same reload, see if we can eliminate a previous | |
6873 | store. */ | |
6874 | rtx pseudo = rl->out_reg; | |
6875 | ||
6876 | if (pseudo | |
6877 | && GET_CODE (pseudo) == REG | |
6878 | && ! rtx_equal_p (rl->in_reg, pseudo) | |
6879 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
6880 | && reg_last_reload_reg[REGNO (pseudo)]) | |
6881 | { | |
6882 | int pseudo_no = REGNO (pseudo); | |
6883 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
6884 | ||
6885 | /* We don't need to test full validity of last_regno for | |
6886 | inherit here; we only want to know if the store actually | |
6887 | matches the pseudo. */ | |
60ef417d GK |
6888 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
6889 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
6890 | && spill_reg_store[last_regno] |
6891 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
6892 | delete_output_reload (insn, j, last_regno); | |
6893 | } | |
5e03c156 | 6894 | |
367b1cf5 BS |
6895 | old = rl->out_reg; |
6896 | if (old == 0 | |
6897 | || rl->reg_rtx == old | |
6898 | || rl->reg_rtx == 0) | |
6899 | return; | |
32131a9c | 6900 | |
367b1cf5 BS |
6901 | /* An output operand that dies right away does need a reload, |
6902 | but need not be copied from it. Show the new location in the | |
6903 | REG_UNUSED note. */ | |
6904 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
6905 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
6906 | { | |
6907 | XEXP (note, 0) = rl->reg_rtx; | |
6908 | return; | |
6909 | } | |
6910 | /* Likewise for a SUBREG of an operand that dies. */ | |
6911 | else if (GET_CODE (old) == SUBREG | |
6912 | && GET_CODE (SUBREG_REG (old)) == REG | |
6913 | && 0 != (note = find_reg_note (insn, REG_UNUSED, | |
6914 | SUBREG_REG (old)))) | |
6915 | { | |
6916 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
6917 | rl->reg_rtx); | |
6918 | return; | |
6919 | } | |
6920 | else if (GET_CODE (old) == SCRATCH) | |
6921 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
6922 | but we don't want to make an output reload. */ | |
6923 | return; | |
1554c2c6 | 6924 | |
367b1cf5 BS |
6925 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
6926 | if (GET_CODE (insn) == JUMP_INSN) | |
6927 | abort (); | |
5e03c156 | 6928 | |
367b1cf5 BS |
6929 | emit_output_reload_insns (chain, rld + j, j); |
6930 | } | |
1554c2c6 | 6931 | |
367b1cf5 | 6932 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 6933 | |
367b1cf5 | 6934 | static void |
e04ca094 | 6935 | emit_reload_insns (chain) |
367b1cf5 BS |
6936 | struct insn_chain *chain; |
6937 | { | |
6938 | rtx insn = chain->insn; | |
32131a9c | 6939 | |
367b1cf5 | 6940 | register int j; |
e6e52be0 | 6941 | |
367b1cf5 | 6942 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 6943 | |
367b1cf5 BS |
6944 | for (j = 0; j < reload_n_operands; j++) |
6945 | input_reload_insns[j] = input_address_reload_insns[j] | |
6946 | = inpaddr_address_reload_insns[j] | |
6947 | = output_reload_insns[j] = output_address_reload_insns[j] | |
6948 | = outaddr_address_reload_insns[j] | |
6949 | = other_output_reload_insns[j] = 0; | |
6950 | other_input_address_reload_insns = 0; | |
6951 | other_input_reload_insns = 0; | |
6952 | operand_reload_insns = 0; | |
6953 | other_operand_reload_insns = 0; | |
32131a9c | 6954 | |
850aac53 | 6955 | /* Dump reloads into the dump file. */ |
e04ca094 | 6956 | if (rtl_dump_file) |
850aac53 | 6957 | { |
e04ca094 JL |
6958 | fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
6959 | debug_reload_to_stream (rtl_dump_file); | |
850aac53 JL |
6960 | } |
6961 | ||
367b1cf5 BS |
6962 | /* Now output the instructions to copy the data into and out of the |
6963 | reload registers. Do these in the order that the reloads were reported, | |
6964 | since reloads of base and index registers precede reloads of operands | |
6965 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 6966 | |
367b1cf5 BS |
6967 | for (j = 0; j < n_reloads; j++) |
6968 | { | |
6969 | if (rld[j].reg_rtx | |
6970 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6971 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 6972 | |
367b1cf5 BS |
6973 | do_input_reload (chain, rld + j, j); |
6974 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
6975 | } |
6976 | ||
546b63fb RK |
6977 | /* Now write all the insns we made for reloads in the order expected by |
6978 | the allocation functions. Prior to the insn being reloaded, we write | |
6979 | the following reloads: | |
6980 | ||
6981 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
6982 | ||
2edc8d65 | 6983 | RELOAD_OTHER reloads. |
546b63fb | 6984 | |
47c8cf91 ILT |
6985 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
6986 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
6987 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 6988 | |
893bc853 RK |
6989 | RELOAD_FOR_OPADDR_ADDRS reloads. |
6990 | ||
546b63fb RK |
6991 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
6992 | ||
6993 | After the insn being reloaded, we write the following: | |
6994 | ||
47c8cf91 ILT |
6995 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
6996 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
6997 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
6998 | reloads for the operand. The RELOAD_OTHER output reloads are | |
6999 | output in descending order by reload number. */ | |
546b63fb | 7000 | |
c93b03c2 RH |
7001 | emit_insns_before (other_input_address_reload_insns, insn); |
7002 | emit_insns_before (other_input_reload_insns, insn); | |
546b63fb RK |
7003 | |
7004 | for (j = 0; j < reload_n_operands; j++) | |
7005 | { | |
c93b03c2 RH |
7006 | emit_insns_before (inpaddr_address_reload_insns[j], insn); |
7007 | emit_insns_before (input_address_reload_insns[j], insn); | |
7008 | emit_insns_before (input_reload_insns[j], insn); | |
546b63fb RK |
7009 | } |
7010 | ||
c93b03c2 RH |
7011 | emit_insns_before (other_operand_reload_insns, insn); |
7012 | emit_insns_before (operand_reload_insns, insn); | |
546b63fb RK |
7013 | |
7014 | for (j = 0; j < reload_n_operands; j++) | |
7015 | { | |
ca6c03ca JH |
7016 | rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn); |
7017 | x = emit_insns_after (output_address_reload_insns[j], x); | |
7018 | x = emit_insns_after (output_reload_insns[j], x); | |
7019 | emit_insns_after (other_output_reload_insns[j], x); | |
546b63fb RK |
7020 | } |
7021 | ||
32131a9c RK |
7022 | /* For all the spill regs newly reloaded in this instruction, |
7023 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
7024 | can inherit the reloads. |
7025 | ||
7026 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 7027 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
7028 | |
7029 | for (j = 0; j < n_reloads; j++) | |
7030 | { | |
7031 | register int r = reload_order[j]; | |
7032 | register int i = reload_spill_index[r]; | |
7033 | ||
78a2bc08 | 7034 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
7035 | clear any memory of a previous store to the same pseudo. Only do |
7036 | something if there will not be an output reload for the pseudo | |
7037 | being reloaded. */ | |
eceef4c9 | 7038 | if (rld[r].in_reg != 0 |
05d10675 BS |
7039 | && ! (reload_inherited[r] || reload_override_in[r])) |
7040 | { | |
eceef4c9 | 7041 | rtx reg = rld[r].in_reg; |
78a2bc08 | 7042 | |
05d10675 | 7043 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 7044 | reg = SUBREG_REG (reg); |
05d10675 BS |
7045 | |
7046 | if (GET_CODE (reg) == REG | |
78a2bc08 R |
7047 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
7048 | && ! reg_has_output_reload[REGNO (reg)]) | |
7049 | { | |
7050 | int nregno = REGNO (reg); | |
7051 | ||
7052 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
7053 | { |
7054 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 7055 | |
05d10675 | 7056 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 7057 | spill_reg_store[last_regno] = 0; |
05d10675 | 7058 | } |
78a2bc08 R |
7059 | } |
7060 | } | |
05d10675 | 7061 | |
e6e52be0 | 7062 | /* I is nonneg if this reload used a register. |
eceef4c9 | 7063 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 7064 | that we opted to ignore. */ |
d445b551 | 7065 | |
eceef4c9 | 7066 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 7067 | { |
1d7254c5 | 7068 | int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); |
32131a9c | 7069 | int k; |
51f0c3b7 JW |
7070 | int part_reaches_end = 0; |
7071 | int all_reaches_end = 1; | |
32131a9c | 7072 | |
51f0c3b7 JW |
7073 | /* For a multi register reload, we need to check if all or part |
7074 | of the value lives to the end. */ | |
32131a9c RK |
7075 | for (k = 0; k < nr; k++) |
7076 | { | |
eceef4c9 BS |
7077 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7078 | rld[r].when_needed)) | |
51f0c3b7 JW |
7079 | part_reaches_end = 1; |
7080 | else | |
7081 | all_reaches_end = 0; | |
32131a9c RK |
7082 | } |
7083 | ||
51f0c3b7 JW |
7084 | /* Ignore reloads that don't reach the end of the insn in |
7085 | entirety. */ | |
7086 | if (all_reaches_end) | |
32131a9c | 7087 | { |
51f0c3b7 JW |
7088 | /* First, clear out memory of what used to be in this spill reg. |
7089 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 7090 | |
32131a9c | 7091 | for (k = 0; k < nr; k++) |
e6e52be0 | 7092 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
d08ea79f | 7093 | |
51f0c3b7 | 7094 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 BS |
7095 | if (rld[r].out != 0 |
7096 | && (GET_CODE (rld[r].out) == REG | |
cb2afeb3 | 7097 | #ifdef AUTO_INC_DEC |
eceef4c9 | 7098 | || ! rld[r].out_reg |
cb2afeb3 | 7099 | #endif |
eceef4c9 | 7100 | || GET_CODE (rld[r].out_reg) == REG)) |
51f0c3b7 | 7101 | { |
eceef4c9 BS |
7102 | rtx out = (GET_CODE (rld[r].out) == REG |
7103 | ? rld[r].out | |
7104 | : rld[r].out_reg | |
7105 | ? rld[r].out_reg | |
7106 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
cb2afeb3 | 7107 | register int nregno = REGNO (out); |
51f0c3b7 JW |
7108 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7109 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7110 | GET_MODE (rld[r].reg_rtx))); |
51f0c3b7 JW |
7111 | |
7112 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 7113 | spill_reg_stored_to[i] = out; |
eceef4c9 | 7114 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7115 | |
7116 | /* If NREGNO is a hard register, it may occupy more than | |
05d10675 | 7117 | one register. If it does, say what is in the |
51f0c3b7 JW |
7118 | rest of the registers assuming that both registers |
7119 | agree on how many words the object takes. If not, | |
7120 | invalidate the subsequent registers. */ | |
7121 | ||
7122 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7123 | for (k = 1; k < nnr; k++) | |
7124 | reg_last_reload_reg[nregno + k] | |
7125 | = (nr == nnr | |
eceef4c9 BS |
7126 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
7127 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
7128 | : 0); |
7129 | ||
7130 | /* Now do the inverse operation. */ | |
7131 | for (k = 0; k < nr; k++) | |
7132 | { | |
e6e52be0 R |
7133 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7134 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7135 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7136 | ? nregno | |
7137 | : nregno + k); | |
e6e52be0 R |
7138 | reg_reloaded_insn[i + k] = insn; |
7139 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7140 | } |
7141 | } | |
d08ea79f | 7142 | |
51f0c3b7 JW |
7143 | /* Maybe the spill reg contains a copy of reload_in. Only do |
7144 | something if there will not be an output reload for | |
7145 | the register being reloaded. */ | |
eceef4c9 BS |
7146 | else if (rld[r].out_reg == 0 |
7147 | && rld[r].in != 0 | |
7148 | && ((GET_CODE (rld[r].in) == REG | |
7149 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER | |
7150 | && ! reg_has_output_reload[REGNO (rld[r].in)]) | |
7151 | || (GET_CODE (rld[r].in_reg) == REG | |
7152 | && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) | |
7153 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) | |
51f0c3b7 JW |
7154 | { |
7155 | register int nregno; | |
7156 | int nnr; | |
d445b551 | 7157 | |
eceef4c9 BS |
7158 | if (GET_CODE (rld[r].in) == REG |
7159 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) | |
7160 | nregno = REGNO (rld[r].in); | |
7161 | else if (GET_CODE (rld[r].in_reg) == REG) | |
7162 | nregno = REGNO (rld[r].in_reg); | |
cb2afeb3 | 7163 | else |
eceef4c9 | 7164 | nregno = REGNO (XEXP (rld[r].in_reg, 0)); |
d08ea79f | 7165 | |
51f0c3b7 JW |
7166 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7167 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7168 | GET_MODE (rld[r].reg_rtx))); |
05d10675 | 7169 | |
eceef4c9 | 7170 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7171 | |
7172 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7173 | for (k = 1; k < nnr; k++) | |
7174 | reg_last_reload_reg[nregno + k] | |
7175 | = (nr == nnr | |
eceef4c9 BS |
7176 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
7177 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
7178 | : 0); |
7179 | ||
7180 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7181 | recently done a store. |
7182 | Previous stores of inherited auto_inc expressions | |
7183 | also have to be discarded. */ | |
7184 | if (! reload_inherited[r] | |
eceef4c9 | 7185 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
7186 | spill_reg_store[i] = 0; |
7187 | ||
7188 | for (k = 0; k < nr; k++) | |
7189 | { | |
e6e52be0 R |
7190 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7191 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7192 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7193 | ? nregno | |
7194 | : nregno + k); | |
e6e52be0 R |
7195 | reg_reloaded_insn[i + k] = insn; |
7196 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7197 | } |
7198 | } | |
7199 | } | |
d445b551 | 7200 | |
51f0c3b7 JW |
7201 | /* However, if part of the reload reaches the end, then we must |
7202 | invalidate the old info for the part that survives to the end. */ | |
7203 | else if (part_reaches_end) | |
7204 | { | |
546b63fb | 7205 | for (k = 0; k < nr; k++) |
e6e52be0 | 7206 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
7207 | rld[r].opnum, |
7208 | rld[r].when_needed)) | |
e6e52be0 | 7209 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
7210 | } |
7211 | } | |
7212 | ||
7213 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7214 | It's reenabled in 1.35 because supposedly nothing else | |
7215 | deals with this problem. */ | |
7216 | ||
7217 | /* If a register gets output-reloaded from a non-spill register, | |
7218 | that invalidates any previous reloaded copy of it. | |
7219 | But forget_old_reloads_1 won't get to see it, because | |
7220 | it thinks only about the original insn. So invalidate it here. */ | |
eceef4c9 BS |
7221 | if (i < 0 && rld[r].out != 0 |
7222 | && (GET_CODE (rld[r].out) == REG | |
7223 | || (GET_CODE (rld[r].out) == MEM | |
7224 | && GET_CODE (rld[r].out_reg) == REG))) | |
32131a9c | 7225 | { |
eceef4c9 BS |
7226 | rtx out = (GET_CODE (rld[r].out) == REG |
7227 | ? rld[r].out : rld[r].out_reg); | |
cb2afeb3 | 7228 | register int nregno = REGNO (out); |
c7093272 | 7229 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 7230 | { |
6a651371 | 7231 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
7232 | |
7233 | reg_last_reload_reg[nregno] = 0; | |
7234 | ||
7235 | /* If we can find a hard register that is stored, record | |
7236 | the storing insn so that we may delete this insn with | |
7237 | delete_output_reload. */ | |
eceef4c9 | 7238 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7239 | |
7240 | /* If this is an optional reload, try to find the source reg | |
7241 | from an input reload. */ | |
7242 | if (! src_reg) | |
7243 | { | |
7244 | rtx set = single_set (insn); | |
eceef4c9 | 7245 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7246 | { |
7247 | int k; | |
7248 | ||
7249 | src_reg = SET_SRC (set); | |
7250 | store_insn = insn; | |
7251 | for (k = 0; k < n_reloads; k++) | |
7252 | { | |
eceef4c9 | 7253 | if (rld[k].in == src_reg) |
cb2afeb3 | 7254 | { |
eceef4c9 | 7255 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7256 | break; |
7257 | } | |
7258 | } | |
7259 | } | |
7260 | } | |
7261 | else | |
7262 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
7263 | if (src_reg && GET_CODE (src_reg) == REG | |
7264 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) | |
7265 | { | |
7266 | int src_regno = REGNO (src_reg); | |
8ec450a4 | 7267 | int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); |
cb2afeb3 R |
7268 | /* The place where to find a death note varies with |
7269 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7270 | necessarily checked exactly in the code that moves | |
7271 | notes, so just check both locations. */ | |
7272 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
1558b970 | 7273 | if (! note && store_insn) |
cb2afeb3 R |
7274 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
7275 | while (nr-- > 0) | |
7276 | { | |
7277 | spill_reg_store[src_regno + nr] = store_insn; | |
7278 | spill_reg_stored_to[src_regno + nr] = out; | |
7279 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7280 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7281 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 R |
7282 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
7283 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); | |
7284 | if (note) | |
7285 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7286 | else | |
7287 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7288 | } | |
7289 | reg_last_reload_reg[nregno] = src_reg; | |
7290 | } | |
7291 | } | |
c7093272 RK |
7292 | else |
7293 | { | |
1d7254c5 | 7294 | int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out)); |
36281332 | 7295 | |
c7093272 RK |
7296 | while (num_regs-- > 0) |
7297 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7298 | } | |
32131a9c RK |
7299 | } |
7300 | } | |
e6e52be0 | 7301 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7302 | } |
7303 | \f | |
5e03c156 RK |
7304 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7305 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7306 | OPNUM with reload type TYPE. |
546b63fb | 7307 | |
3c3eeea6 | 7308 | Returns first insn emitted. */ |
32131a9c RK |
7309 | |
7310 | rtx | |
5e03c156 RK |
7311 | gen_reload (out, in, opnum, type) |
7312 | rtx out; | |
32131a9c | 7313 | rtx in; |
546b63fb RK |
7314 | int opnum; |
7315 | enum reload_type type; | |
32131a9c | 7316 | { |
546b63fb | 7317 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7318 | rtx tem; |
7319 | ||
7320 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7321 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7322 | if (GET_CODE (in) == SUBREG | |
7323 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7324 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7325 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7326 | in = SUBREG_REG (in), out = tem; | |
7327 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7328 | && (GET_MODE_SIZE (GET_MODE (out)) |
7329 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7330 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7331 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7332 | |
a8fdc208 | 7333 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7334 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7335 | register that didn't get a hard register. In that case we can just | |
7336 | call emit_move_insn. | |
7337 | ||
a7fd196c JW |
7338 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7339 | another register, constant or MEM. This can occur during frame pointer | |
7340 | elimination and while reloading addresses. This case is handled by | |
7341 | trying to emit a single insn to perform the add. If it is not valid, | |
7342 | we use a two insn sequence. | |
32131a9c RK |
7343 | |
7344 | Finally, we could be called to handle an 'o' constraint by putting | |
7345 | an address into a register. In that case, we first try to do this | |
7346 | with a named pattern of "reload_load_address". If no such pattern | |
7347 | exists, we just emit a SET insn and hope for the best (it will normally | |
7348 | be valid on machines that use 'o'). | |
7349 | ||
7350 | This entire process is made complex because reload will never | |
7351 | process the insns we generate here and so we must ensure that | |
7352 | they will fit their constraints and also by the fact that parts of | |
7353 | IN might be being reloaded separately and replaced with spill registers. | |
7354 | Because of this, we are, in some sense, just guessing the right approach | |
7355 | here. The one listed above seems to work. | |
7356 | ||
7357 | ??? At some point, this whole thing needs to be rethought. */ | |
7358 | ||
7359 | if (GET_CODE (in) == PLUS | |
a7fd196c | 7360 | && (GET_CODE (XEXP (in, 0)) == REG |
5c6b1bd2 | 7361 | || GET_CODE (XEXP (in, 0)) == SUBREG |
a7fd196c JW |
7362 | || GET_CODE (XEXP (in, 0)) == MEM) |
7363 | && (GET_CODE (XEXP (in, 1)) == REG | |
5c6b1bd2 | 7364 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c JW |
7365 | || CONSTANT_P (XEXP (in, 1)) |
7366 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
32131a9c | 7367 | { |
a7fd196c JW |
7368 | /* We need to compute the sum of a register or a MEM and another |
7369 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7370 | register. The best possible way of doing this is if the machine |
7371 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7372 | |
7373 | The simplest approach is to try to generate such an insn and see if it | |
7374 | is recognized and matches its constraints. If so, it can be used. | |
7375 | ||
7376 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7377 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7378 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7379 | not valid than to dummy things up. */ |
a8fdc208 | 7380 | |
af929c62 | 7381 | rtx op0, op1, tem, insn; |
32131a9c | 7382 | int code; |
a8fdc208 | 7383 | |
af929c62 RK |
7384 | op0 = find_replacement (&XEXP (in, 0)); |
7385 | op1 = find_replacement (&XEXP (in, 1)); | |
7386 | ||
32131a9c RK |
7387 | /* Since constraint checking is strict, commutativity won't be |
7388 | checked, so we need to do that here to avoid spurious failure | |
7389 | if the add instruction is two-address and the second operand | |
7390 | of the add is the same as the reload reg, which is frequently | |
7391 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7392 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7393 | |
32131a9c | 7394 | if (GET_CODE (XEXP (in, 1)) == REG |
5e03c156 | 7395 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7396 | tem = op0, op0 = op1, op1 = tem; |
7397 | ||
7398 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7399 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7400 | |
38a448ca | 7401 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7402 | code = recog_memoized (insn); |
7403 | ||
7404 | if (code >= 0) | |
7405 | { | |
0eadeb15 | 7406 | extract_insn (insn); |
32131a9c RK |
7407 | /* We want constrain operands to treat this insn strictly in |
7408 | its validity determination, i.e., the way it would after reload | |
7409 | has completed. */ | |
0eadeb15 | 7410 | if (constrain_operands (1)) |
32131a9c RK |
7411 | return insn; |
7412 | } | |
7413 | ||
546b63fb | 7414 | delete_insns_since (last); |
32131a9c RK |
7415 | |
7416 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7417 | |
7418 | Use a move to copy one operand into the reload register. Prefer | |
7419 | to reload a constant, MEM or pseudo since the move patterns can | |
7420 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7421 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7422 | reload OP1. | |
7423 | ||
7424 | After reloading one of the operands into the reload register, add | |
7425 | the reload register to the output register. | |
32131a9c RK |
7426 | |
7427 | If there is another way to do this for a specific machine, a | |
7428 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7429 | we emit below. */ | |
7430 | ||
09522f21 FS |
7431 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7432 | ||
5c6b1bd2 | 7433 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG |
af929c62 | 7434 | || (GET_CODE (op1) == REG |
09522f21 FS |
7435 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7436 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7437 | && ! ((*insn_data[code].operand[2].predicate) |
7438 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7439 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7440 | |
5c6b1bd2 | 7441 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7442 | |
5e03c156 | 7443 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7444 | This fixes a problem on the 32K where the stack pointer cannot |
7445 | be used as an operand of an add insn. */ | |
7446 | ||
7447 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7448 | op1 = out; |
39b56c2a | 7449 | |
5e03c156 | 7450 | insn = emit_insn (gen_add2_insn (out, op1)); |
c77c9766 RK |
7451 | |
7452 | /* If that failed, copy the address register to the reload register. | |
0f41302f | 7453 | Then add the constant to the reload register. */ |
c77c9766 RK |
7454 | |
7455 | code = recog_memoized (insn); | |
7456 | ||
7457 | if (code >= 0) | |
7458 | { | |
0eadeb15 | 7459 | extract_insn (insn); |
c77c9766 RK |
7460 | /* We want constrain operands to treat this insn strictly in |
7461 | its validity determination, i.e., the way it would after reload | |
7462 | has completed. */ | |
0eadeb15 | 7463 | if (constrain_operands (1)) |
4117a96b R |
7464 | { |
7465 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ | |
7466 | REG_NOTES (insn) | |
9e6a5703 | 7467 | = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
4117a96b R |
7468 | return insn; |
7469 | } | |
c77c9766 RK |
7470 | } |
7471 | ||
7472 | delete_insns_since (last); | |
7473 | ||
5c6b1bd2 | 7474 | gen_reload (out, op1, opnum, type); |
4117a96b | 7475 | insn = emit_insn (gen_add2_insn (out, op0)); |
9e6a5703 | 7476 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
32131a9c RK |
7477 | } |
7478 | ||
0dadecf6 RK |
7479 | #ifdef SECONDARY_MEMORY_NEEDED |
7480 | /* If we need a memory location to do the move, do it that way. */ | |
7481 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
5e03c156 | 7482 | && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER |
0dadecf6 | 7483 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), |
5e03c156 RK |
7484 | REGNO_REG_CLASS (REGNO (out)), |
7485 | GET_MODE (out))) | |
0dadecf6 RK |
7486 | { |
7487 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7488 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7489 | |
5e03c156 | 7490 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7491 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7492 | |
7493 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7494 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7495 | |
5c6b1bd2 RK |
7496 | gen_reload (loc, in, opnum, type); |
7497 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
7498 | } |
7499 | #endif | |
7500 | ||
32131a9c RK |
7501 | /* If IN is a simple operand, use gen_move_insn. */ |
7502 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
5e03c156 | 7503 | emit_insn (gen_move_insn (out, in)); |
32131a9c RK |
7504 | |
7505 | #ifdef HAVE_reload_load_address | |
7506 | else if (HAVE_reload_load_address) | |
5e03c156 | 7507 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
7508 | #endif |
7509 | ||
5e03c156 | 7510 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 7511 | else |
38a448ca | 7512 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7513 | |
7514 | /* Return the first insn emitted. | |
546b63fb | 7515 | We can not just return get_last_insn, because there may have |
32131a9c RK |
7516 | been multiple instructions emitted. Also note that gen_move_insn may |
7517 | emit more than one insn itself, so we can not assume that there is one | |
7518 | insn emitted per emit_insn_before call. */ | |
7519 | ||
546b63fb | 7520 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
7521 | } |
7522 | \f | |
7523 | /* Delete a previously made output-reload | |
7524 | whose result we now believe is not needed. | |
7525 | First we double-check. | |
7526 | ||
7527 | INSN is the insn now being processed. | |
cb2afeb3 R |
7528 | LAST_RELOAD_REG is the hard register number for which we want to delete |
7529 | the last output reload. | |
7530 | J is the reload-number that originally used REG. The caller has made | |
7531 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
7532 | |
7533 | static void | |
cb2afeb3 | 7534 | delete_output_reload (insn, j, last_reload_reg) |
32131a9c RK |
7535 | rtx insn; |
7536 | int j; | |
cb2afeb3 | 7537 | int last_reload_reg; |
32131a9c | 7538 | { |
cb2afeb3 R |
7539 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
7540 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
7541 | int k; | |
7542 | int n_occurrences; | |
7543 | int n_inherited = 0; | |
32131a9c | 7544 | register rtx i1; |
cb2afeb3 | 7545 | rtx substed; |
05d10675 | 7546 | |
32131a9c RK |
7547 | /* Get the raw pseudo-register referred to. */ |
7548 | ||
32131a9c RK |
7549 | while (GET_CODE (reg) == SUBREG) |
7550 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
7551 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
7552 | ||
7553 | /* This is unsafe if the operand occurs more often in the current | |
7554 | insn than it is inherited. */ | |
7555 | for (k = n_reloads - 1; k >= 0; k--) | |
7556 | { | |
eceef4c9 | 7557 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
7558 | if (! reg2) |
7559 | continue; | |
7560 | if (GET_CODE (reg2) == MEM || reload_override_in[k]) | |
eceef4c9 | 7561 | reg2 = rld[k].in_reg; |
cb2afeb3 | 7562 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
7563 | if (rld[k].out && ! rld[k].out_reg) |
7564 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
7565 | #endif |
7566 | while (GET_CODE (reg2) == SUBREG) | |
7567 | reg2 = SUBREG_REG (reg2); | |
7568 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
7569 | { |
7570 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
7571 | { | |
cb2afeb3 | 7572 | n_inherited++; |
eceef4c9 | 7573 | reg2 = rld[k].out_reg; |
2eb6dac7 AS |
7574 | if (! reg2) |
7575 | continue; | |
7576 | while (GET_CODE (reg2) == SUBREG) | |
7577 | reg2 = XEXP (reg2, 0); | |
7578 | if (rtx_equal_p (reg2, reg)) | |
7579 | n_inherited++; | |
7580 | } | |
7581 | else | |
7582 | return; | |
7583 | } | |
cb2afeb3 | 7584 | } |
4b983fdc | 7585 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
cb2afeb3 | 7586 | if (substed) |
5d7ef82a BS |
7587 | n_occurrences += count_occurrences (PATTERN (insn), |
7588 | eliminate_regs (substed, 0, | |
7589 | NULL_RTX), 0); | |
cb2afeb3 R |
7590 | if (n_occurrences > n_inherited) |
7591 | return; | |
32131a9c RK |
7592 | |
7593 | /* If the pseudo-reg we are reloading is no longer referenced | |
7594 | anywhere between the store into it and here, | |
7595 | and no jumps or labels intervene, then the value can get | |
7596 | here through the reload reg alone. | |
7597 | Otherwise, give up--return. */ | |
7598 | for (i1 = NEXT_INSN (output_reload_insn); | |
7599 | i1 != insn; i1 = NEXT_INSN (i1)) | |
7600 | { | |
7601 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
7602 | return; | |
7603 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
7604 | && reg_mentioned_p (reg, PATTERN (i1))) | |
aa6498c2 | 7605 | { |
cb2afeb3 R |
7606 | /* If this is USE in front of INSN, we only have to check that |
7607 | there are no more references than accounted for by inheritance. */ | |
7608 | while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) | |
aa6498c2 | 7609 | { |
cb2afeb3 | 7610 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
7611 | i1 = NEXT_INSN (i1); |
7612 | } | |
cb2afeb3 | 7613 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
7614 | break; |
7615 | return; | |
7616 | } | |
32131a9c RK |
7617 | } |
7618 | ||
aa6498c2 R |
7619 | /* The caller has already checked that REG dies or is set in INSN. |
7620 | It has also checked that we are optimizing, and thus some inaccurancies | |
7621 | in the debugging information are acceptable. | |
7622 | So we could just delete output_reload_insn. | |
7623 | But in some cases we can improve the debugging information without | |
7624 | sacrificing optimization - maybe even improving the code: | |
7625 | See if the pseudo reg has been completely replaced | |
32131a9c RK |
7626 | with reload regs. If so, delete the store insn |
7627 | and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 7628 | if (rld[j].out != rld[j].in |
aa6498c2 | 7629 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 7630 | && REG_N_SETS (REGNO (reg)) == 1 |
aa6498c2 R |
7631 | && REG_BASIC_BLOCK (REGNO (reg)) >= 0 |
7632 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
32131a9c RK |
7633 | { |
7634 | rtx i2; | |
7635 | ||
7636 | /* We know that it was used only between here | |
7637 | and the beginning of the current basic block. | |
7638 | (We also know that the last use before INSN was | |
7639 | the output reload we are thinking of deleting, but never mind that.) | |
7640 | Search that range; see if any ref remains. */ | |
7641 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7642 | { | |
d445b551 RK |
7643 | rtx set = single_set (i2); |
7644 | ||
32131a9c RK |
7645 | /* Uses which just store in the pseudo don't count, |
7646 | since if they are the only uses, they are dead. */ | |
d445b551 | 7647 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
7648 | continue; |
7649 | if (GET_CODE (i2) == CODE_LABEL | |
7650 | || GET_CODE (i2) == JUMP_INSN) | |
7651 | break; | |
7652 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
7653 | && reg_mentioned_p (reg, PATTERN (i2))) | |
aa6498c2 R |
7654 | { |
7655 | /* Some other ref remains; just delete the output reload we | |
7656 | know to be dead. */ | |
cb2afeb3 | 7657 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 7658 | delete_insn (output_reload_insn); |
aa6498c2 R |
7659 | return; |
7660 | } | |
32131a9c RK |
7661 | } |
7662 | ||
7663 | /* Delete the now-dead stores into this pseudo. */ | |
7664 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7665 | { | |
d445b551 RK |
7666 | rtx set = single_set (i2); |
7667 | ||
7668 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 7669 | { |
cb2afeb3 | 7670 | delete_address_reloads (i2, insn); |
5507b94b RK |
7671 | /* This might be a basic block head, |
7672 | thus don't use delete_insn. */ | |
ca6c03ca | 7673 | delete_insn (i2); |
5507b94b | 7674 | } |
32131a9c RK |
7675 | if (GET_CODE (i2) == CODE_LABEL |
7676 | || GET_CODE (i2) == JUMP_INSN) | |
7677 | break; | |
7678 | } | |
7679 | ||
7680 | /* For the debugging info, | |
7681 | say the pseudo lives in this reload reg. */ | |
eceef4c9 | 7682 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
7683 | alter_reg (REGNO (reg), -1); |
7684 | } | |
cb2afeb3 | 7685 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 7686 | delete_insn (output_reload_insn); |
cb2afeb3 R |
7687 | |
7688 | } | |
7689 | ||
7690 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
7691 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
7692 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
7693 | static void | |
7694 | delete_address_reloads (dead_insn, current_insn) | |
7695 | rtx dead_insn, current_insn; | |
7696 | { | |
7697 | rtx set = single_set (dead_insn); | |
7698 | rtx set2, dst, prev, next; | |
7699 | if (set) | |
7700 | { | |
7701 | rtx dst = SET_DEST (set); | |
7702 | if (GET_CODE (dst) == MEM) | |
7703 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); | |
7704 | } | |
7705 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
7706 | we can delete the matching adds. */ | |
7707 | prev = PREV_INSN (dead_insn); | |
7708 | next = NEXT_INSN (dead_insn); | |
7709 | if (! prev || ! next) | |
7710 | return; | |
7711 | set = single_set (next); | |
7712 | set2 = single_set (prev); | |
7713 | if (! set || ! set2 | |
7714 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
7715 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
7716 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
7717 | return; | |
7718 | dst = SET_DEST (set); | |
7719 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
7720 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
7721 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
7722 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 7723 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 | 7724 | return; |
53c17031 JH |
7725 | delete_related_insns (prev); |
7726 | delete_related_insns (next); | |
cb2afeb3 R |
7727 | } |
7728 | ||
7729 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
7730 | static void | |
7731 | delete_address_reloads_1 (dead_insn, x, current_insn) | |
7732 | rtx dead_insn, x, current_insn; | |
7733 | { | |
7734 | rtx prev, set, dst, i2; | |
7735 | int i, j; | |
7736 | enum rtx_code code = GET_CODE (x); | |
7737 | ||
7738 | if (code != REG) | |
7739 | { | |
1d7254c5 | 7740 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
7741 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7742 | { | |
7743 | if (fmt[i] == 'e') | |
7744 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
7745 | else if (fmt[i] == 'E') | |
7746 | { | |
1d7254c5 | 7747 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
7748 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
7749 | current_insn); | |
7750 | } | |
7751 | } | |
7752 | return; | |
7753 | } | |
7754 | ||
7755 | if (spill_reg_order[REGNO (x)] < 0) | |
7756 | return; | |
aa6498c2 | 7757 | |
cb2afeb3 R |
7758 | /* Scan backwards for the insn that sets x. This might be a way back due |
7759 | to inheritance. */ | |
7760 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
7761 | { | |
7762 | code = GET_CODE (prev); | |
7763 | if (code == CODE_LABEL || code == JUMP_INSN) | |
7764 | return; | |
7765 | if (GET_RTX_CLASS (code) != 'i') | |
7766 | continue; | |
7767 | if (reg_set_p (x, PATTERN (prev))) | |
7768 | break; | |
7769 | if (reg_referenced_p (x, PATTERN (prev))) | |
7770 | return; | |
7771 | } | |
7772 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
7773 | return; | |
7774 | /* Check that PREV only sets the reload register. */ | |
7775 | set = single_set (prev); | |
7776 | if (! set) | |
7777 | return; | |
7778 | dst = SET_DEST (set); | |
7779 | if (GET_CODE (dst) != REG | |
7780 | || ! rtx_equal_p (dst, x)) | |
7781 | return; | |
7782 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
7783 | { | |
7784 | /* Check if DST was used in a later insn - | |
7785 | it might have been inherited. */ | |
7786 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
7787 | { | |
7788 | if (GET_CODE (i2) == CODE_LABEL) | |
7789 | break; | |
2c3c49de | 7790 | if (! INSN_P (i2)) |
cb2afeb3 R |
7791 | continue; |
7792 | if (reg_referenced_p (dst, PATTERN (i2))) | |
7793 | { | |
7794 | /* If there is a reference to the register in the current insn, | |
7795 | it might be loaded in a non-inherited reload. If no other | |
7796 | reload uses it, that means the register is set before | |
7797 | referenced. */ | |
7798 | if (i2 == current_insn) | |
7799 | { | |
7800 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7801 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7802 | || reload_override_in[j] == dst) |
7803 | return; | |
7804 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7805 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
7806 | break; |
7807 | if (j >= 0) | |
7808 | break; | |
7809 | } | |
7810 | return; | |
7811 | } | |
7812 | if (GET_CODE (i2) == JUMP_INSN) | |
7813 | break; | |
cb2afeb3 | 7814 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
7815 | any reload. Note that even if CURRENT_INSN sets DST, we still |
7816 | have to check the reloads. */ | |
cb2afeb3 R |
7817 | if (i2 == current_insn) |
7818 | { | |
7819 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7820 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7821 | || reload_override_in[j] == dst) |
7822 | return; | |
7823 | /* ??? We can't finish the loop here, because dst might be | |
7824 | allocated to a pseudo in this block if no reload in this | |
7825 | block needs any of the clsses containing DST - see | |
7826 | spill_hard_reg. There is no easy way to tell this, so we | |
7827 | have to scan till the end of the basic block. */ | |
7828 | } | |
3900dc09 R |
7829 | if (reg_set_p (dst, PATTERN (i2))) |
7830 | break; | |
cb2afeb3 R |
7831 | } |
7832 | } | |
7833 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
7834 | reg_reloaded_contents[REGNO (dst)] = -1; | |
ca6c03ca | 7835 | delete_insn (prev); |
32131a9c | 7836 | } |
32131a9c | 7837 | \f |
a8fdc208 | 7838 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 7839 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
7840 | is a register or memory location; |
7841 | so reloading involves incrementing that location. | |
cb2afeb3 | 7842 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
7843 | |
7844 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 7845 | This cannot be deduced from VALUE. |
32131a9c | 7846 | |
cb2afeb3 R |
7847 | Return the instruction that stores into RELOADREG. */ |
7848 | ||
7849 | static rtx | |
7850 | inc_for_reload (reloadreg, in, value, inc_amount) | |
32131a9c | 7851 | rtx reloadreg; |
cb2afeb3 | 7852 | rtx in, value; |
32131a9c | 7853 | int inc_amount; |
32131a9c RK |
7854 | { |
7855 | /* REG or MEM to be copied and incremented. */ | |
7856 | rtx incloc = XEXP (value, 0); | |
7857 | /* Nonzero if increment after copying. */ | |
7858 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 7859 | rtx last; |
0009eff2 RK |
7860 | rtx inc; |
7861 | rtx add_insn; | |
7862 | int code; | |
cb2afeb3 R |
7863 | rtx store; |
7864 | rtx real_in = in == value ? XEXP (in, 0) : in; | |
32131a9c RK |
7865 | |
7866 | /* No hard register is equivalent to this register after | |
7867 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
7868 | we could inc/dec that register as well (maybe even using it for | |
7869 | the source), but I'm not sure it's worth worrying about. */ | |
7870 | if (GET_CODE (incloc) == REG) | |
7871 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
7872 | ||
7873 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
1d7254c5 | 7874 | inc_amount = -inc_amount; |
32131a9c | 7875 | |
fb3821f7 | 7876 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
7877 | |
7878 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
7879 | if (post && real_in != reloadreg) |
7880 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 7881 | |
cb2afeb3 R |
7882 | if (in == value) |
7883 | { | |
7884 | /* See if we can directly increment INCLOC. Use a method similar to | |
7885 | that in gen_reload. */ | |
0009eff2 | 7886 | |
cb2afeb3 R |
7887 | last = get_last_insn (); |
7888 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
7889 | gen_rtx_PLUS (GET_MODE (incloc), | |
7890 | incloc, inc))); | |
05d10675 | 7891 | |
cb2afeb3 R |
7892 | code = recog_memoized (add_insn); |
7893 | if (code >= 0) | |
32131a9c | 7894 | { |
0eadeb15 BS |
7895 | extract_insn (add_insn); |
7896 | if (constrain_operands (1)) | |
cb2afeb3 R |
7897 | { |
7898 | /* If this is a pre-increment and we have incremented the value | |
7899 | where it lives, copy the incremented value to RELOADREG to | |
7900 | be used as an address. */ | |
0009eff2 | 7901 | |
cb2afeb3 R |
7902 | if (! post) |
7903 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 7904 | |
cb2afeb3 R |
7905 | return add_insn; |
7906 | } | |
32131a9c | 7907 | } |
cb2afeb3 | 7908 | delete_insns_since (last); |
32131a9c | 7909 | } |
0009eff2 | 7910 | |
0009eff2 RK |
7911 | /* If couldn't do the increment directly, must increment in RELOADREG. |
7912 | The way we do this depends on whether this is pre- or post-increment. | |
7913 | For pre-increment, copy INCLOC to the reload register, increment it | |
7914 | there, then save back. */ | |
7915 | ||
7916 | if (! post) | |
7917 | { | |
cb2afeb3 R |
7918 | if (in != reloadreg) |
7919 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 7920 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7921 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 7922 | } |
32131a9c RK |
7923 | else |
7924 | { | |
0009eff2 RK |
7925 | /* Postincrement. |
7926 | Because this might be a jump insn or a compare, and because RELOADREG | |
7927 | may not be available after the insn in an input reload, we must do | |
7928 | the incrementation before the insn being reloaded for. | |
7929 | ||
cb2afeb3 | 7930 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
7931 | RELOADREG, save that back, then decrement RELOADREG so it has |
7932 | the original value. */ | |
7933 | ||
546b63fb | 7934 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7935 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
546b63fb | 7936 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); |
32131a9c | 7937 | } |
0009eff2 | 7938 | |
cb2afeb3 | 7939 | return store; |
32131a9c RK |
7940 | } |
7941 | \f | |
7942 | /* Return 1 if we are certain that the constraint-string STRING allows | |
7943 | the hard register REG. Return 0 if we can't be sure of this. */ | |
7944 | ||
7945 | static int | |
7946 | constraint_accepts_reg_p (string, reg) | |
9b3142b3 | 7947 | const char *string; |
32131a9c RK |
7948 | rtx reg; |
7949 | { | |
7950 | int value = 0; | |
7951 | int regno = true_regnum (reg); | |
7952 | int c; | |
7953 | ||
7954 | /* Initialize for first alternative. */ | |
7955 | value = 0; | |
7956 | /* Check that each alternative contains `g' or `r'. */ | |
7957 | while (1) | |
7958 | switch (c = *string++) | |
7959 | { | |
7960 | case 0: | |
7961 | /* If an alternative lacks `g' or `r', we lose. */ | |
7962 | return value; | |
7963 | case ',': | |
7964 | /* If an alternative lacks `g' or `r', we lose. */ | |
7965 | if (value == 0) | |
7966 | return 0; | |
7967 | /* Initialize for next alternative. */ | |
7968 | value = 0; | |
7969 | break; | |
7970 | case 'g': | |
7971 | case 'r': | |
7972 | /* Any general reg wins for this alternative. */ | |
7973 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
7974 | value = 1; | |
7975 | break; | |
7976 | default: | |
7977 | /* Any reg in specified class wins for this alternative. */ | |
7978 | { | |
0009eff2 | 7979 | enum reg_class class = REG_CLASS_FROM_LETTER (c); |
32131a9c | 7980 | |
0009eff2 | 7981 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) |
32131a9c RK |
7982 | value = 1; |
7983 | } | |
7984 | } | |
7985 | } | |
7986 | \f | |
eab5c70a BS |
7987 | /* INSN is a no-op; delete it. |
7988 | If this sets the return value of the function, we must keep a USE around, | |
7989 | in case this is in a different basic block than the final USE. Otherwise, | |
7990 | we could loose important register lifeness information on | |
7991 | SMALL_REGISTER_CLASSES machines, where return registers might be used as | |
7992 | spills: subsequent passes assume that spill registers are dead at the end | |
7993 | of a basic block. | |
7994 | VALUE must be the return value in such a case, NULL otherwise. */ | |
2a9fb548 | 7995 | static void |
eab5c70a BS |
7996 | reload_cse_delete_noop_set (insn, value) |
7997 | rtx insn, value; | |
2a9fb548 | 7998 | { |
eab5c70a | 7999 | if (value) |
2a9fb548 | 8000 | { |
eab5c70a BS |
8001 | PATTERN (insn) = gen_rtx_USE (VOIDmode, value); |
8002 | INSN_CODE (insn) = -1; | |
8003 | REG_NOTES (insn) = NULL_RTX; | |
2a9fb548 | 8004 | } |
eab5c70a | 8005 | else |
ca6c03ca | 8006 | delete_insn (insn); |
2a9fb548 ILT |
8007 | } |
8008 | ||
eab5c70a | 8009 | /* See whether a single set SET is a noop. */ |
2a9fb548 | 8010 | static int |
eab5c70a BS |
8011 | reload_cse_noop_set_p (set) |
8012 | rtx set; | |
2a9fb548 | 8013 | { |
eab5c70a BS |
8014 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); |
8015 | } | |
2a9fb548 | 8016 | |
eab5c70a BS |
8017 | /* Try to simplify INSN. */ |
8018 | static void | |
8019 | reload_cse_simplify (insn) | |
8020 | rtx insn; | |
8021 | { | |
8022 | rtx body = PATTERN (insn); | |
2a9fb548 | 8023 | |
eab5c70a | 8024 | if (GET_CODE (body) == SET) |
2a9fb548 | 8025 | { |
eab5c70a | 8026 | int count = 0; |
d5ae21aa AH |
8027 | |
8028 | /* Simplify even if we may think it is a no-op. | |
8029 | We may think a memory load of a value smaller than WORD_SIZE | |
8030 | is redundant because we haven't taken into account possible | |
8031 | implicit extension. reload_cse_simplify_set() will bring | |
8032 | this out, so it's safer to simplify before we delete. */ | |
8033 | count += reload_cse_simplify_set (body, insn); | |
8034 | ||
8035 | if (!count && reload_cse_noop_set_p (body)) | |
2a9fb548 | 8036 | { |
eab5c70a BS |
8037 | rtx value = SET_DEST (body); |
8038 | if (! REG_FUNCTION_VALUE_P (SET_DEST (body))) | |
8039 | value = 0; | |
8040 | reload_cse_delete_noop_set (insn, value); | |
8041 | return; | |
2a9fb548 | 8042 | } |
2a9fb548 | 8043 | |
eab5c70a BS |
8044 | if (count > 0) |
8045 | apply_change_group (); | |
8046 | else | |
8047 | reload_cse_simplify_operands (insn); | |
8048 | } | |
8049 | else if (GET_CODE (body) == PARALLEL) | |
2a9fb548 | 8050 | { |
eab5c70a BS |
8051 | int i; |
8052 | int count = 0; | |
8053 | rtx value = NULL_RTX; | |
2a9fb548 | 8054 | |
eab5c70a BS |
8055 | /* If every action in a PARALLEL is a noop, we can delete |
8056 | the entire PARALLEL. */ | |
8057 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
2a9fb548 | 8058 | { |
eab5c70a BS |
8059 | rtx part = XVECEXP (body, 0, i); |
8060 | if (GET_CODE (part) == SET) | |
2a9fb548 | 8061 | { |
eab5c70a BS |
8062 | if (! reload_cse_noop_set_p (part)) |
8063 | break; | |
8064 | if (REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
2a9fb548 | 8065 | { |
eab5c70a BS |
8066 | if (value) |
8067 | break; | |
8068 | value = SET_DEST (part); | |
2a9fb548 | 8069 | } |
2a9fb548 | 8070 | } |
eab5c70a BS |
8071 | else if (GET_CODE (part) != CLOBBER) |
8072 | break; | |
2a9fb548 | 8073 | } |
2a9fb548 | 8074 | |
eab5c70a BS |
8075 | if (i < 0) |
8076 | { | |
8077 | reload_cse_delete_noop_set (insn, value); | |
8078 | /* We're done with this insn. */ | |
8079 | return; | |
8080 | } | |
2a9fb548 | 8081 | |
eab5c70a BS |
8082 | /* It's not a no-op, but we can try to simplify it. */ |
8083 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
8084 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
8085 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
8086 | ||
8087 | if (count > 0) | |
8088 | apply_change_group (); | |
8089 | else | |
8090 | reload_cse_simplify_operands (insn); | |
8091 | } | |
2a9fb548 ILT |
8092 | } |
8093 | ||
8094 | /* Do a very simple CSE pass over the hard registers. | |
8095 | ||
8096 | This function detects no-op moves where we happened to assign two | |
8097 | different pseudo-registers to the same hard register, and then | |
8098 | copied one to the other. Reload will generate a useless | |
8099 | instruction copying a register to itself. | |
8100 | ||
8101 | This function also detects cases where we load a value from memory | |
8102 | into two different registers, and (if memory is more expensive than | |
8103 | registers) changes it to simply copy the first register into the | |
05d10675 | 8104 | second register. |
e9a25f70 JL |
8105 | |
8106 | Another optimization is performed that scans the operands of each | |
8107 | instruction to see whether the value is already available in a | |
8108 | hard register. It then replaces the operand with the hard register | |
8109 | if possible, much like an optional reload would. */ | |
2a9fb548 | 8110 | |
5adf6da0 R |
8111 | static void |
8112 | reload_cse_regs_1 (first) | |
2a9fb548 ILT |
8113 | rtx first; |
8114 | { | |
2a9fb548 ILT |
8115 | rtx insn; |
8116 | ||
1d7254c5 | 8117 | cselib_init (); |
cbfc3ad3 RK |
8118 | init_alias_analysis (); |
8119 | ||
2a9fb548 ILT |
8120 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
8121 | { | |
2c3c49de | 8122 | if (INSN_P (insn)) |
eab5c70a | 8123 | reload_cse_simplify (insn); |
2a9fb548 | 8124 | |
eab5c70a | 8125 | cselib_process_insn (insn); |
2a9fb548 ILT |
8126 | } |
8127 | ||
e05e2395 MM |
8128 | /* Clean up. */ |
8129 | end_alias_analysis (); | |
eab5c70a | 8130 | cselib_finish (); |
2a9fb548 ILT |
8131 | } |
8132 | ||
5adf6da0 R |
8133 | /* Call cse / combine like post-reload optimization phases. |
8134 | FIRST is the first instruction. */ | |
8135 | void | |
8136 | reload_cse_regs (first) | |
8137 | rtx first; | |
8138 | { | |
8139 | reload_cse_regs_1 (first); | |
8140 | reload_combine (); | |
8141 | reload_cse_move2add (first); | |
8142 | if (flag_expensive_optimizations) | |
8143 | reload_cse_regs_1 (first); | |
8144 | } | |
8145 | ||
2a9fb548 | 8146 | /* Try to simplify a single SET instruction. SET is the set pattern. |
e9a25f70 JL |
8147 | INSN is the instruction it came from. |
8148 | This function only handles one case: if we set a register to a value | |
8149 | which is not a register, we try to find that value in some other register | |
8150 | and change the set into a register copy. */ | |
2a9fb548 | 8151 | |
e9a25f70 | 8152 | static int |
2a9fb548 ILT |
8153 | reload_cse_simplify_set (set, insn) |
8154 | rtx set; | |
8155 | rtx insn; | |
8156 | { | |
eab5c70a | 8157 | int did_change = 0; |
2a9fb548 ILT |
8158 | int dreg; |
8159 | rtx src; | |
2a9fb548 | 8160 | enum reg_class dclass; |
eab5c70a BS |
8161 | int old_cost; |
8162 | cselib_val *val; | |
8163 | struct elt_loc_list *l; | |
78adc5a0 RH |
8164 | #ifdef LOAD_EXTEND_OP |
8165 | enum rtx_code extend_op = NIL; | |
8166 | #endif | |
2a9fb548 | 8167 | |
2a9fb548 ILT |
8168 | dreg = true_regnum (SET_DEST (set)); |
8169 | if (dreg < 0) | |
e9a25f70 | 8170 | return 0; |
2a9fb548 ILT |
8171 | |
8172 | src = SET_SRC (set); | |
8173 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
e9a25f70 | 8174 | return 0; |
2a9fb548 | 8175 | |
cbd5b9a2 KR |
8176 | dclass = REGNO_REG_CLASS (dreg); |
8177 | ||
78adc5a0 RH |
8178 | #ifdef LOAD_EXTEND_OP |
8179 | /* When replacing a memory with a register, we need to honor assumptions | |
8180 | that combine made wrt the contents of sign bits. We'll do this by | |
8181 | generating an extend instruction instead of a reg->reg copy. Thus | |
8182 | the destination must be a register that we can widen. */ | |
8183 | if (GET_CODE (src) == MEM | |
8184 | && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD | |
8185 | && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL | |
8186 | && GET_CODE (SET_DEST (set)) != REG) | |
8187 | return 0; | |
8188 | #endif | |
8189 | ||
33ab8de0 | 8190 | /* If memory loads are cheaper than register copies, don't change them. */ |
eab5c70a BS |
8191 | if (GET_CODE (src) == MEM) |
8192 | old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1); | |
8193 | else if (CONSTANT_P (src)) | |
8194 | old_cost = rtx_cost (src, SET); | |
8195 | else if (GET_CODE (src) == REG) | |
e56b4594 AO |
8196 | old_cost = REGISTER_MOVE_COST (GET_MODE (src), |
8197 | REGNO_REG_CLASS (REGNO (src)), dclass); | |
eab5c70a BS |
8198 | else |
8199 | /* ??? */ | |
8200 | old_cost = rtx_cost (src, SET); | |
2a9fb548 | 8201 | |
70bbeb8b | 8202 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0); |
eab5c70a | 8203 | if (! val) |
0254c561 | 8204 | return 0; |
eab5c70a | 8205 | for (l = val->locs; l; l = l->next) |
2a9fb548 | 8206 | { |
78adc5a0 | 8207 | rtx this_rtx = l->loc; |
eab5c70a | 8208 | int this_cost; |
78adc5a0 RH |
8209 | |
8210 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
8211 | { | |
8212 | #ifdef LOAD_EXTEND_OP | |
8213 | if (extend_op != NIL) | |
8214 | { | |
8215 | HOST_WIDE_INT this_val; | |
8216 | ||
8217 | /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other | |
8218 | constants, such as SYMBOL_REF, cannot be extended. */ | |
8219 | if (GET_CODE (this_rtx) != CONST_INT) | |
8220 | continue; | |
8221 | ||
8222 | this_val = INTVAL (this_rtx); | |
8223 | switch (extend_op) | |
8224 | { | |
8225 | case ZERO_EXTEND: | |
8226 | this_val &= GET_MODE_MASK (GET_MODE (src)); | |
8227 | break; | |
8228 | case SIGN_EXTEND: | |
8229 | /* ??? In theory we're already extended. */ | |
8230 | if (this_val == trunc_int_for_mode (this_val, GET_MODE (src))) | |
8231 | break; | |
8232 | default: | |
8233 | abort (); | |
8234 | } | |
5cada064 | 8235 | this_rtx = GEN_INT (this_val); |
78adc5a0 RH |
8236 | } |
8237 | #endif | |
8238 | this_cost = rtx_cost (this_rtx, SET); | |
8239 | } | |
8240 | else if (GET_CODE (this_rtx) == REG) | |
8241 | { | |
8242 | #ifdef LOAD_EXTEND_OP | |
8243 | if (extend_op != NIL) | |
8244 | { | |
8245 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
8246 | this_cost = rtx_cost (this_rtx, SET); | |
8247 | } | |
8248 | else | |
8249 | #endif | |
8250 | this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx), | |
8251 | REGNO_REG_CLASS (REGNO (this_rtx)), | |
8252 | dclass); | |
8253 | } | |
eab5c70a BS |
8254 | else |
8255 | continue; | |
78adc5a0 RH |
8256 | |
8257 | /* If equal costs, prefer registers over anything else. That | |
8258 | tends to lead to smaller instructions on some machines. */ | |
8259 | if (this_cost < old_cost | |
8260 | || (this_cost == old_cost | |
8261 | && GET_CODE (this_rtx) == REG | |
8262 | && GET_CODE (SET_SRC (set)) != REG)) | |
8263 | { | |
8264 | #ifdef LOAD_EXTEND_OP | |
b216e516 JL |
8265 | if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD |
8266 | && extend_op != NIL) | |
8267 | { | |
8268 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
8269 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
8270 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
8271 | } | |
78adc5a0 RH |
8272 | #endif |
8273 | ||
8274 | validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1); | |
8275 | old_cost = this_cost, did_change = 1; | |
8276 | } | |
e9a25f70 | 8277 | } |
eab5c70a BS |
8278 | |
8279 | return did_change; | |
e9a25f70 JL |
8280 | } |
8281 | ||
8282 | /* Try to replace operands in INSN with equivalent values that are already | |
05d10675 BS |
8283 | in registers. This can be viewed as optional reloading. |
8284 | ||
e9a25f70 JL |
8285 | For each non-register operand in the insn, see if any hard regs are |
8286 | known to be equivalent to that operand. Record the alternatives which | |
8287 | can accept these hard registers. Among all alternatives, select the | |
8288 | ones which are better or equal to the one currently matching, where | |
8289 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
8290 | alternatives, select the one which replaces most operands with | |
8291 | hard registers. */ | |
8292 | ||
8293 | static int | |
8294 | reload_cse_simplify_operands (insn) | |
8295 | rtx insn; | |
8296 | { | |
1d7254c5 | 8297 | int i, j; |
e9a25f70 | 8298 | |
eab5c70a BS |
8299 | /* For each operand, all registers that are equivalent to it. */ |
8300 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
8301 | ||
9b3142b3 | 8302 | const char *constraints[MAX_RECOG_OPERANDS]; |
05d10675 | 8303 | |
e9a25f70 JL |
8304 | /* Vector recording how bad an alternative is. */ |
8305 | int *alternative_reject; | |
8306 | /* Vector recording how many registers can be introduced by choosing | |
8307 | this alternative. */ | |
8308 | int *alternative_nregs; | |
8309 | /* Array of vectors recording, for each operand and each alternative, | |
8310 | which hard register to substitute, or -1 if the operand should be | |
8311 | left as it is. */ | |
8312 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
8313 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
8314 | int *alternative_order; | |
0254c561 | 8315 | rtx reg = gen_rtx_REG (VOIDmode, -1); |
05d10675 | 8316 | |
0eadeb15 | 8317 | extract_insn (insn); |
e9a25f70 | 8318 | |
1ccbefce | 8319 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) |
1d300e19 | 8320 | return 0; |
e9a25f70 JL |
8321 | |
8322 | /* Figure out which alternative currently matches. */ | |
0eadeb15 | 8323 | if (! constrain_operands (1)) |
b8705408 | 8324 | fatal_insn_not_found (insn); |
1d7254c5 | 8325 | |
1ccbefce RH |
8326 | alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8327 | alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8328 | alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
961192e1 JM |
8329 | memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
8330 | memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
e9a25f70 | 8331 | |
eab5c70a BS |
8332 | /* For each operand, find out which regs are equivalent. */ |
8333 | for (i = 0; i < recog_data.n_operands; i++) | |
8334 | { | |
8335 | cselib_val *v; | |
8336 | struct elt_loc_list *l; | |
8337 | ||
8338 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
8339 | ||
8340 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
70bbeb8b BS |
8341 | right, so avoid the problem here. Likewise if we have a constant |
8342 | and the insn pattern doesn't tell us the mode we need. */ | |
8343 | if (GET_CODE (recog_data.operand[i]) == CODE_LABEL | |
8344 | || (CONSTANT_P (recog_data.operand[i]) | |
8345 | && recog_data.operand_mode[i] == VOIDmode)) | |
eab5c70a BS |
8346 | continue; |
8347 | ||
8348 | v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0); | |
8349 | if (! v) | |
8350 | continue; | |
8351 | ||
8352 | for (l = v->locs; l; l = l->next) | |
8353 | if (GET_CODE (l->loc) == REG) | |
8354 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); | |
8355 | } | |
8356 | ||
1ccbefce | 8357 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 JL |
8358 | { |
8359 | enum machine_mode mode; | |
8360 | int regno; | |
9b3142b3 | 8361 | const char *p; |
e9a25f70 | 8362 | |
1ccbefce RH |
8363 | op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8364 | for (j = 0; j < recog_data.n_alternatives; j++) | |
e9a25f70 JL |
8365 | op_alt_regno[i][j] = -1; |
8366 | ||
1ccbefce RH |
8367 | p = constraints[i] = recog_data.constraints[i]; |
8368 | mode = recog_data.operand_mode[i]; | |
e9a25f70 JL |
8369 | |
8370 | /* Add the reject values for each alternative given by the constraints | |
8371 | for this operand. */ | |
8372 | j = 0; | |
8373 | while (*p != '\0') | |
8374 | { | |
8375 | char c = *p++; | |
8376 | if (c == ',') | |
8377 | j++; | |
8378 | else if (c == '?') | |
8379 | alternative_reject[j] += 3; | |
8380 | else if (c == '!') | |
8381 | alternative_reject[j] += 300; | |
8382 | } | |
8383 | ||
8384 | /* We won't change operands which are already registers. We | |
8385 | also don't want to modify output operands. */ | |
1ccbefce | 8386 | regno = true_regnum (recog_data.operand[i]); |
e9a25f70 JL |
8387 | if (regno >= 0 |
8388 | || constraints[i][0] == '=' | |
8389 | || constraints[i][0] == '+') | |
8390 | continue; | |
8391 | ||
8392 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
8393 | { | |
8394 | int class = (int) NO_REGS; | |
8395 | ||
eab5c70a | 8396 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) |
e9a25f70 JL |
8397 | continue; |
8398 | ||
0254c561 JC |
8399 | REGNO (reg) = regno; |
8400 | PUT_MODE (reg, mode); | |
8401 | ||
e9a25f70 JL |
8402 | /* We found a register equal to this operand. Now look for all |
8403 | alternatives that can accept this register and have not been | |
8404 | assigned a register they can use yet. */ | |
8405 | j = 0; | |
8406 | p = constraints[i]; | |
8407 | for (;;) | |
31418d35 | 8408 | { |
e9a25f70 | 8409 | char c = *p++; |
05d10675 | 8410 | |
e9a25f70 | 8411 | switch (c) |
31418d35 | 8412 | { |
e9a25f70 JL |
8413 | case '=': case '+': case '?': |
8414 | case '#': case '&': case '!': | |
05d10675 | 8415 | case '*': case '%': |
e9a25f70 | 8416 | case '0': case '1': case '2': case '3': case '4': |
c5c76735 | 8417 | case '5': case '6': case '7': case '8': case '9': |
e9a25f70 JL |
8418 | case 'm': case '<': case '>': case 'V': case 'o': |
8419 | case 'E': case 'F': case 'G': case 'H': | |
8420 | case 's': case 'i': case 'n': | |
8421 | case 'I': case 'J': case 'K': case 'L': | |
8422 | case 'M': case 'N': case 'O': case 'P': | |
e9a25f70 JL |
8423 | case 'p': case 'X': |
8424 | /* These don't say anything we care about. */ | |
8425 | break; | |
8426 | ||
8427 | case 'g': case 'r': | |
8428 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
8429 | break; | |
8430 | ||
8431 | default: | |
8432 | class | |
e51712db | 8433 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
e9a25f70 | 8434 | break; |
31418d35 | 8435 | |
e9a25f70 JL |
8436 | case ',': case '\0': |
8437 | /* See if REGNO fits this alternative, and set it up as the | |
8438 | replacement register if we don't have one for this | |
0254c561 | 8439 | alternative yet and the operand being replaced is not |
1d7254c5 | 8440 | a cheap CONST_INT. */ |
e9a25f70 | 8441 | if (op_alt_regno[i][j] == -1 |
0254c561 | 8442 | && reg_fits_class_p (reg, class, 0, mode) |
1ccbefce RH |
8443 | && (GET_CODE (recog_data.operand[i]) != CONST_INT |
8444 | || (rtx_cost (recog_data.operand[i], SET) | |
8445 | > rtx_cost (reg, SET)))) | |
31418d35 | 8446 | { |
e9a25f70 JL |
8447 | alternative_nregs[j]++; |
8448 | op_alt_regno[i][j] = regno; | |
31418d35 | 8449 | } |
e9a25f70 JL |
8450 | j++; |
8451 | break; | |
31418d35 ILT |
8452 | } |
8453 | ||
e9a25f70 JL |
8454 | if (c == '\0') |
8455 | break; | |
8456 | } | |
8457 | } | |
8458 | } | |
8459 | ||
8460 | /* Record all alternatives which are better or equal to the currently | |
8461 | matching one in the alternative_order array. */ | |
1ccbefce | 8462 | for (i = j = 0; i < recog_data.n_alternatives; i++) |
e9a25f70 JL |
8463 | if (alternative_reject[i] <= alternative_reject[which_alternative]) |
8464 | alternative_order[j++] = i; | |
1ccbefce | 8465 | recog_data.n_alternatives = j; |
e9a25f70 JL |
8466 | |
8467 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
8468 | won't hurt too much. */ | |
1ccbefce | 8469 | for (i = 0; i < recog_data.n_alternatives - 1; i++) |
e9a25f70 JL |
8470 | { |
8471 | int best = i; | |
8472 | int best_reject = alternative_reject[alternative_order[i]]; | |
8473 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
8474 | int tmp; | |
8475 | ||
1ccbefce | 8476 | for (j = i + 1; j < recog_data.n_alternatives; j++) |
e9a25f70 JL |
8477 | { |
8478 | int this_reject = alternative_reject[alternative_order[j]]; | |
8479 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
8480 | ||
8481 | if (this_reject < best_reject | |
8482 | || (this_reject == best_reject && this_nregs < best_nregs)) | |
8483 | { | |
8484 | best = j; | |
8485 | best_reject = this_reject; | |
8486 | best_nregs = this_nregs; | |
31418d35 | 8487 | } |
2a9fb548 | 8488 | } |
05d10675 | 8489 | |
e9a25f70 JL |
8490 | tmp = alternative_order[best]; |
8491 | alternative_order[best] = alternative_order[i]; | |
8492 | alternative_order[i] = tmp; | |
8493 | } | |
05d10675 | 8494 | |
e9a25f70 JL |
8495 | /* Substitute the operands as determined by op_alt_regno for the best |
8496 | alternative. */ | |
8497 | j = alternative_order[0]; | |
e9a25f70 | 8498 | |
1ccbefce | 8499 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 | 8500 | { |
1ccbefce | 8501 | enum machine_mode mode = recog_data.operand_mode[i]; |
e9a25f70 JL |
8502 | if (op_alt_regno[i][j] == -1) |
8503 | continue; | |
8504 | ||
1ccbefce | 8505 | validate_change (insn, recog_data.operand_loc[i], |
38a448ca | 8506 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); |
e9a25f70 JL |
8507 | } |
8508 | ||
1ccbefce | 8509 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
e9a25f70 | 8510 | { |
1ccbefce RH |
8511 | int op = recog_data.dup_num[i]; |
8512 | enum machine_mode mode = recog_data.operand_mode[op]; | |
e9a25f70 JL |
8513 | |
8514 | if (op_alt_regno[op][j] == -1) | |
8515 | continue; | |
8516 | ||
1ccbefce | 8517 | validate_change (insn, recog_data.dup_loc[i], |
38a448ca | 8518 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); |
2a9fb548 | 8519 | } |
e9a25f70 | 8520 | |
e9a25f70 | 8521 | return apply_change_group (); |
2a9fb548 | 8522 | } |
5adf6da0 R |
8523 | \f |
8524 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
8525 | addressing now. | |
8526 | This code might also be useful when reload gave up on reg+reg addresssing | |
8527 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
8528 | ||
8529 | /* The maximum number of uses of a register we can keep track of to | |
8530 | replace them with reg+reg addressing. */ | |
8531 | #define RELOAD_COMBINE_MAX_USES 6 | |
8532 | ||
8533 | /* INSN is the insn where a register has ben used, and USEP points to the | |
8534 | location of the register within the rtl. */ | |
8535 | struct reg_use { rtx insn, *usep; }; | |
8536 | ||
8537 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
8538 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
8539 | indicates where it becomes live again. | |
8540 | Otherwise, USE_INDEX is the index of the last encountered use of the | |
8541 | register (which is first among these we have seen since we scan backwards), | |
8542 | OFFSET contains the constant offset that is added to the register in | |
8543 | all encountered uses, and USE_RUID indicates the first encountered, i.e. | |
ed937a19 R |
8544 | last, of these uses. |
8545 | STORE_RUID is always meaningful if we only want to use a value in a | |
8546 | register in a different place: it denotes the next insn in the insn | |
8547 | stream (i.e. the last ecountered) that sets or clobbers the register. */ | |
5adf6da0 R |
8548 | static struct |
8549 | { | |
8550 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8551 | int use_index; | |
8552 | rtx offset; | |
8553 | int store_ruid; | |
8554 | int use_ruid; | |
8555 | } reg_state[FIRST_PSEUDO_REGISTER]; | |
8556 | ||
8557 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
8558 | the instructions from last to first. It is used to set last_label_ruid | |
8559 | and the store_ruid / use_ruid fields in reg_state. */ | |
8560 | static int reload_combine_ruid; | |
8561 | ||
b0634509 R |
8562 | #define LABEL_LIVE(LABEL) \ |
8563 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
8564 | ||
5adf6da0 R |
8565 | static void |
8566 | reload_combine () | |
8567 | { | |
8568 | rtx insn, set; | |
ae0ed63a JM |
8569 | int first_index_reg = -1; |
8570 | int last_index_reg = 0; | |
5adf6da0 | 8571 | int i; |
f8cd4126 | 8572 | unsigned int r; |
5adf6da0 | 8573 | int last_label_ruid; |
b0634509 R |
8574 | int min_labelno, n_labels; |
8575 | HARD_REG_SET ever_live_at_start, *label_live; | |
5adf6da0 R |
8576 | |
8577 | /* If reg+reg can be used in offsetable memory adresses, the main chunk of | |
8578 | reload has already used it where appropriate, so there is no use in | |
8579 | trying to generate it now. */ | |
03acd8f8 | 8580 | if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) |
5adf6da0 R |
8581 | return; |
8582 | ||
8583 | /* To avoid wasting too much time later searching for an index register, | |
8584 | determine the minimum and maximum index register numbers. */ | |
f8cd4126 RK |
8585 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8586 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
8587 | { | |
881a8969 | 8588 | if (first_index_reg == -1) |
4c3f1588 RK |
8589 | first_index_reg = r; |
8590 | ||
8591 | last_index_reg = r; | |
f8cd4126 RK |
8592 | } |
8593 | ||
5adf6da0 | 8594 | /* If no index register is available, we can quit now. */ |
881a8969 | 8595 | if (first_index_reg == -1) |
5adf6da0 R |
8596 | return; |
8597 | ||
b0634509 R |
8598 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
8599 | information is a bit fuzzy immediately after reload, but it's | |
8600 | still good enough to determine which registers are live at a jump | |
8601 | destination. */ | |
8602 | min_labelno = get_first_label_num (); | |
8603 | n_labels = max_label_num () - min_labelno; | |
8604 | label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); | |
8605 | CLEAR_HARD_REG_SET (ever_live_at_start); | |
f8cd4126 | 8606 | |
b0634509 R |
8607 | for (i = n_basic_blocks - 1; i >= 0; i--) |
8608 | { | |
3b413743 | 8609 | insn = BLOCK_HEAD (i); |
b0634509 R |
8610 | if (GET_CODE (insn) == CODE_LABEL) |
8611 | { | |
8612 | HARD_REG_SET live; | |
8613 | ||
f8cd4126 RK |
8614 | REG_SET_TO_HARD_REG_SET (live, |
8615 | BASIC_BLOCK (i)->global_live_at_start); | |
8616 | compute_use_by_pseudos (&live, | |
8617 | BASIC_BLOCK (i)->global_live_at_start); | |
b0634509 R |
8618 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
8619 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
8620 | } | |
8621 | } | |
8622 | ||
5adf6da0 R |
8623 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ |
8624 | last_label_ruid = reload_combine_ruid = 0; | |
f8cd4126 | 8625 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
5adf6da0 | 8626 | { |
f8cd4126 RK |
8627 | reg_state[r].store_ruid = reload_combine_ruid; |
8628 | if (fixed_regs[r]) | |
8629 | reg_state[r].use_index = -1; | |
5adf6da0 | 8630 | else |
f8cd4126 | 8631 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
5adf6da0 R |
8632 | } |
8633 | ||
8634 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
8635 | { | |
8636 | rtx note; | |
8637 | ||
8638 | /* We cannot do our optimization across labels. Invalidating all the use | |
8639 | information we have would be costly, so we just note where the label | |
05d10675 | 8640 | is and then later disable any optimization that would cross it. */ |
5adf6da0 R |
8641 | if (GET_CODE (insn) == CODE_LABEL) |
8642 | last_label_ruid = reload_combine_ruid; | |
f8cd4126 RK |
8643 | else if (GET_CODE (insn) == BARRIER) |
8644 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
8645 | if (! fixed_regs[r]) | |
8646 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8647 | ||
2c3c49de | 8648 | if (! INSN_P (insn)) |
5adf6da0 | 8649 | continue; |
f8cd4126 | 8650 | |
5adf6da0 R |
8651 | reload_combine_ruid++; |
8652 | ||
8653 | /* Look for (set (REGX) (CONST_INT)) | |
eceef4c9 BS |
8654 | (set (REGX) (PLUS (REGX) (REGY))) |
8655 | ... | |
8656 | ... (MEM (REGX)) ... | |
5adf6da0 | 8657 | and convert it to |
eceef4c9 BS |
8658 | (set (REGZ) (CONST_INT)) |
8659 | ... | |
8660 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
5adf6da0 R |
8661 | |
8662 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
8663 | and that we know all uses of REGX before it dies. */ | |
2abbc1bd R |
8664 | set = single_set (insn); |
8665 | if (set != NULL_RTX | |
5adf6da0 R |
8666 | && GET_CODE (SET_DEST (set)) == REG |
8667 | && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), | |
8668 | GET_MODE (SET_DEST (set))) | |
8669 | == 1) | |
8670 | && GET_CODE (SET_SRC (set)) == PLUS | |
8671 | && GET_CODE (XEXP (SET_SRC (set), 1)) == REG | |
8672 | && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | |
8673 | && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | |
8674 | { | |
8675 | rtx reg = SET_DEST (set); | |
8676 | rtx plus = SET_SRC (set); | |
8677 | rtx base = XEXP (plus, 1); | |
8678 | rtx prev = prev_nonnote_insn (insn); | |
8679 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; | |
f8cd4126 | 8680 | unsigned int regno = REGNO (reg); |
6a651371 | 8681 | rtx const_reg = NULL_RTX; |
5adf6da0 R |
8682 | rtx reg_sum = NULL_RTX; |
8683 | ||
8684 | /* Now, we need an index register. | |
8685 | We'll set index_reg to this index register, const_reg to the | |
8686 | register that is to be loaded with the constant | |
8687 | (denoted as REGZ in the substitution illustration above), | |
8688 | and reg_sum to the register-register that we want to use to | |
8689 | substitute uses of REG (typically in MEMs) with. | |
8690 | First check REG and BASE for being index registers; | |
8691 | we can use them even if they are not dead. */ | |
8692 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
8693 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
8694 | REGNO (base))) | |
8695 | { | |
8696 | const_reg = reg; | |
8697 | reg_sum = plus; | |
8698 | } | |
8699 | else | |
8700 | { | |
05d10675 BS |
8701 | /* Otherwise, look for a free index register. Since we have |
8702 | checked above that neiter REG nor BASE are index registers, | |
8703 | if we find anything at all, it will be different from these | |
8704 | two registers. */ | |
8705 | for (i = first_index_reg; i <= last_index_reg; i++) | |
5adf6da0 | 8706 | { |
f8cd4126 RK |
8707 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], |
8708 | i) | |
5adf6da0 R |
8709 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES |
8710 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
8711 | && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) | |
8712 | { | |
8713 | rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
f8cd4126 | 8714 | |
5adf6da0 R |
8715 | const_reg = index_reg; |
8716 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
8717 | break; | |
8718 | } | |
8719 | } | |
8720 | } | |
f8cd4126 | 8721 | |
ed937a19 R |
8722 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that |
8723 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
8724 | create. */ | |
f8cd4126 | 8725 | if (prev_set != 0 |
5adf6da0 R |
8726 | && GET_CODE (SET_SRC (prev_set)) == CONST_INT |
8727 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
8728 | && reg_state[regno].use_index >= 0 | |
f8cd4126 RK |
8729 | && (reg_state[REGNO (base)].store_ruid |
8730 | <= reg_state[regno].use_ruid) | |
8731 | && reg_sum != 0) | |
5adf6da0 R |
8732 | { |
8733 | int i; | |
8734 | ||
f8cd4126 | 8735 | /* Change destination register and, if necessary, the |
5adf6da0 R |
8736 | constant value in PREV, the constant loading instruction. */ |
8737 | validate_change (prev, &SET_DEST (prev_set), const_reg, 1); | |
8738 | if (reg_state[regno].offset != const0_rtx) | |
8739 | validate_change (prev, | |
8740 | &SET_SRC (prev_set), | |
8741 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
8742 | + INTVAL (reg_state[regno].offset)), | |
8743 | 1); | |
f8cd4126 | 8744 | |
5adf6da0 R |
8745 | /* Now for every use of REG that we have recorded, replace REG |
8746 | with REG_SUM. */ | |
8747 | for (i = reg_state[regno].use_index; | |
8748 | i < RELOAD_COMBINE_MAX_USES; i++) | |
8749 | validate_change (reg_state[regno].reg_use[i].insn, | |
8750 | reg_state[regno].reg_use[i].usep, | |
8751 | reg_sum, 1); | |
8752 | ||
8753 | if (apply_change_group ()) | |
8754 | { | |
8755 | rtx *np; | |
8756 | ||
8757 | /* Delete the reg-reg addition. */ | |
ca6c03ca | 8758 | delete_insn (insn); |
5adf6da0 R |
8759 | |
8760 | if (reg_state[regno].offset != const0_rtx) | |
f8cd4126 RK |
8761 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV |
8762 | are now invalid. */ | |
1d7254c5 | 8763 | for (np = ®_NOTES (prev); *np;) |
f8cd4126 RK |
8764 | { |
8765 | if (REG_NOTE_KIND (*np) == REG_EQUAL | |
8766 | || REG_NOTE_KIND (*np) == REG_EQUIV) | |
8767 | *np = XEXP (*np, 1); | |
8768 | else | |
8769 | np = &XEXP (*np, 1); | |
8770 | } | |
8771 | ||
5adf6da0 | 8772 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; |
f8cd4126 RK |
8773 | reg_state[REGNO (const_reg)].store_ruid |
8774 | = reload_combine_ruid; | |
5adf6da0 R |
8775 | continue; |
8776 | } | |
8777 | } | |
8778 | } | |
f8cd4126 | 8779 | |
1d7254c5 | 8780 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); |
f8cd4126 | 8781 | |
5adf6da0 R |
8782 | if (GET_CODE (insn) == CALL_INSN) |
8783 | { | |
8784 | rtx link; | |
8785 | ||
f8cd4126 RK |
8786 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8787 | if (call_used_regs[r]) | |
8788 | { | |
8789 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8790 | reg_state[r].store_ruid = reload_combine_ruid; | |
8791 | } | |
8792 | ||
5adf6da0 R |
8793 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; |
8794 | link = XEXP (link, 1)) | |
6a69653a CM |
8795 | { |
8796 | rtx usage_rtx = XEXP (XEXP (link, 0), 0); | |
8797 | if (GET_CODE (usage_rtx) == REG) | |
8798 | { | |
ae0ed63a | 8799 | unsigned int i; |
6a69653a CM |
8800 | unsigned int start_reg = REGNO (usage_rtx); |
8801 | unsigned int num_regs = | |
8802 | HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx)); | |
8803 | unsigned int end_reg = start_reg + num_regs - 1; | |
8804 | for (i = start_reg; i <= end_reg; i++) | |
8805 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
8806 | { | |
8807 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8808 | reg_state[i].store_ruid = reload_combine_ruid; | |
8809 | } | |
8810 | else | |
8811 | reg_state[i].use_index = -1; | |
8812 | } | |
8813 | } | |
f8cd4126 | 8814 | |
5adf6da0 | 8815 | } |
f8cd4126 RK |
8816 | else if (GET_CODE (insn) == JUMP_INSN |
8817 | && GET_CODE (PATTERN (insn)) != RETURN) | |
5adf6da0 R |
8818 | { |
8819 | /* Non-spill registers might be used at the call destination in | |
8820 | some unknown fashion, so we have to mark the unknown use. */ | |
b0634509 | 8821 | HARD_REG_SET *live; |
f8cd4126 | 8822 | |
b0634509 R |
8823 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) |
8824 | && JUMP_LABEL (insn)) | |
8825 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
8826 | else | |
8827 | live = &ever_live_at_start; | |
f8cd4126 | 8828 | |
5adf6da0 | 8829 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) |
f8cd4126 RK |
8830 | if (TEST_HARD_REG_BIT (*live, i)) |
8831 | reg_state[i].use_index = -1; | |
5adf6da0 | 8832 | } |
f8cd4126 | 8833 | |
5adf6da0 R |
8834 | reload_combine_note_use (&PATTERN (insn), insn); |
8835 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
8836 | { | |
8837 | if (REG_NOTE_KIND (note) == REG_INC | |
8838 | && GET_CODE (XEXP (note, 0)) == REG) | |
ed937a19 R |
8839 | { |
8840 | int regno = REGNO (XEXP (note, 0)); | |
8841 | ||
8842 | reg_state[regno].store_ruid = reload_combine_ruid; | |
8843 | reg_state[regno].use_index = -1; | |
8844 | } | |
5adf6da0 R |
8845 | } |
8846 | } | |
f8cd4126 | 8847 | |
b0634509 | 8848 | free (label_live); |
5adf6da0 R |
8849 | } |
8850 | ||
8851 | /* Check if DST is a register or a subreg of a register; if it is, | |
8852 | update reg_state[regno].store_ruid and reg_state[regno].use_index | |
f93233bb | 8853 | accordingly. Called via note_stores from reload_combine. */ |
f8cd4126 | 8854 | |
5adf6da0 | 8855 | static void |
84832317 | 8856 | reload_combine_note_store (dst, set, data) |
f93233bb | 8857 | rtx dst, set; |
84832317 | 8858 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 R |
8859 | { |
8860 | int regno = 0; | |
8861 | int i; | |
54ed0905 | 8862 | enum machine_mode mode = GET_MODE (dst); |
5adf6da0 R |
8863 | |
8864 | if (GET_CODE (dst) == SUBREG) | |
8865 | { | |
ddef6bc7 JJ |
8866 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
8867 | GET_MODE (SUBREG_REG (dst)), | |
8868 | SUBREG_BYTE (dst), | |
8869 | GET_MODE (dst)); | |
5adf6da0 R |
8870 | dst = SUBREG_REG (dst); |
8871 | } | |
8872 | if (GET_CODE (dst) != REG) | |
8873 | return; | |
8874 | regno += REGNO (dst); | |
54ca6ffa | 8875 | |
5adf6da0 | 8876 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be |
05d10675 | 8877 | careful with registers / register parts that are not full words. |
54ca6ffa JL |
8878 | |
8879 | Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ | |
8880 | if (GET_CODE (set) != SET | |
8881 | || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | |
8882 | || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT | |
8883 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
ed937a19 | 8884 | { |
54ed0905 | 8885 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
f93233bb JL |
8886 | { |
8887 | reg_state[i].use_index = -1; | |
8888 | reg_state[i].store_ruid = reload_combine_ruid; | |
8889 | } | |
ed937a19 | 8890 | } |
5adf6da0 R |
8891 | else |
8892 | { | |
54ed0905 | 8893 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
5adf6da0 R |
8894 | { |
8895 | reg_state[i].store_ruid = reload_combine_ruid; | |
8896 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8897 | } | |
8898 | } | |
8899 | } | |
8900 | ||
8901 | /* XP points to a piece of rtl that has to be checked for any uses of | |
8902 | registers. | |
8903 | *XP is the pattern of INSN, or a part of it. | |
8904 | Called from reload_combine, and recursively by itself. */ | |
8905 | static void | |
8906 | reload_combine_note_use (xp, insn) | |
8907 | rtx *xp, insn; | |
8908 | { | |
8909 | rtx x = *xp; | |
8910 | enum rtx_code code = x->code; | |
6f7d635c | 8911 | const char *fmt; |
5adf6da0 R |
8912 | int i, j; |
8913 | rtx offset = const0_rtx; /* For the REG case below. */ | |
8914 | ||
8915 | switch (code) | |
8916 | { | |
8917 | case SET: | |
8918 | if (GET_CODE (SET_DEST (x)) == REG) | |
8919 | { | |
8920 | reload_combine_note_use (&SET_SRC (x), insn); | |
8921 | return; | |
8922 | } | |
8923 | break; | |
8924 | ||
6ce7e0f9 R |
8925 | case USE: |
8926 | /* If this is the USE of a return value, we can't change it. */ | |
8927 | if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0))) | |
8928 | { | |
8929 | /* Mark the return register as used in an unknown fashion. */ | |
8930 | rtx reg = XEXP (x, 0); | |
8931 | int regno = REGNO (reg); | |
8932 | int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8933 | ||
8934 | while (--nregs >= 0) | |
8935 | reg_state[regno + nregs].use_index = -1; | |
8936 | return; | |
8937 | } | |
8938 | break; | |
8939 | ||
5adf6da0 R |
8940 | case CLOBBER: |
8941 | if (GET_CODE (SET_DEST (x)) == REG) | |
3d17d93d AO |
8942 | { |
8943 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
8944 | if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER) | |
8945 | abort (); | |
8946 | return; | |
8947 | } | |
5adf6da0 R |
8948 | break; |
8949 | ||
8950 | case PLUS: | |
8951 | /* We are interested in (plus (reg) (const_int)) . */ | |
1d7254c5 KH |
8952 | if (GET_CODE (XEXP (x, 0)) != REG |
8953 | || GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5adf6da0 R |
8954 | break; |
8955 | offset = XEXP (x, 1); | |
8956 | x = XEXP (x, 0); | |
05d10675 | 8957 | /* Fall through. */ |
5adf6da0 R |
8958 | case REG: |
8959 | { | |
8960 | int regno = REGNO (x); | |
8961 | int use_index; | |
6ce7e0f9 | 8962 | int nregs; |
5adf6da0 | 8963 | |
3d17d93d | 8964 | /* No spurious USEs of pseudo registers may remain. */ |
5adf6da0 | 8965 | if (regno >= FIRST_PSEUDO_REGISTER) |
3d17d93d | 8966 | abort (); |
5adf6da0 | 8967 | |
6ce7e0f9 R |
8968 | nregs = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
8969 | ||
8970 | /* We can't substitute into multi-hard-reg uses. */ | |
8971 | if (nregs > 1) | |
8972 | { | |
8973 | while (--nregs >= 0) | |
8974 | reg_state[regno + nregs].use_index = -1; | |
8975 | return; | |
8976 | } | |
8977 | ||
5adf6da0 R |
8978 | /* If this register is already used in some unknown fashion, we |
8979 | can't do anything. | |
8980 | If we decrement the index from zero to -1, we can't store more | |
8981 | uses, so this register becomes used in an unknown fashion. */ | |
8982 | use_index = --reg_state[regno].use_index; | |
8983 | if (use_index < 0) | |
8984 | return; | |
8985 | ||
8986 | if (use_index != RELOAD_COMBINE_MAX_USES - 1) | |
8987 | { | |
8988 | /* We have found another use for a register that is already | |
8989 | used later. Check if the offsets match; if not, mark the | |
8990 | register as used in an unknown fashion. */ | |
8991 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
8992 | { | |
8993 | reg_state[regno].use_index = -1; | |
8994 | return; | |
8995 | } | |
8996 | } | |
8997 | else | |
8998 | { | |
8999 | /* This is the first use of this register we have seen since we | |
9000 | marked it as dead. */ | |
9001 | reg_state[regno].offset = offset; | |
9002 | reg_state[regno].use_ruid = reload_combine_ruid; | |
9003 | } | |
9004 | reg_state[regno].reg_use[use_index].insn = insn; | |
9005 | reg_state[regno].reg_use[use_index].usep = xp; | |
9006 | return; | |
9007 | } | |
9008 | ||
9009 | default: | |
9010 | break; | |
9011 | } | |
9012 | ||
9013 | /* Recursively process the components of X. */ | |
9014 | fmt = GET_RTX_FORMAT (code); | |
9015 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9016 | { | |
9017 | if (fmt[i] == 'e') | |
9018 | reload_combine_note_use (&XEXP (x, i), insn); | |
9019 | else if (fmt[i] == 'E') | |
9020 | { | |
9021 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9022 | reload_combine_note_use (&XVECEXP (x, i, j), insn); | |
9023 | } | |
9024 | } | |
9025 | } | |
9026 | \f | |
61f5625b AO |
9027 | /* See if we can reduce the cost of a constant by replacing a move |
9028 | with an add. We track situations in which a register is set to a | |
9029 | constant or to a register plus a constant. */ | |
5adf6da0 R |
9030 | /* We cannot do our optimization across labels. Invalidating all the |
9031 | information about register contents we have would be costly, so we | |
61f5625b AO |
9032 | use move2add_last_label_luid to note where the label is and then |
9033 | later disable any optimization that would cross it. | |
5adf6da0 | 9034 | reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if |
61f5625b | 9035 | reg_set_luid[n] is greater than last_label_luid[n] . */ |
5adf6da0 | 9036 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
770ae6cc | 9037 | |
61f5625b AO |
9038 | /* If reg_base_reg[n] is negative, register n has been set to |
9039 | reg_offset[n] in mode reg_mode[n] . | |
9040 | If reg_base_reg[n] is non-negative, register n has been set to the | |
9041 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
dc297297 | 9042 | before reg_set_luid[n], calculated in mode reg_mode[n] . */ |
61f5625b | 9043 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
5adf6da0 R |
9044 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; |
9045 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; | |
770ae6cc | 9046 | |
5adf6da0 R |
9047 | /* move2add_luid is linearily increased while scanning the instructions |
9048 | from first to last. It is used to set reg_set_luid in | |
6764d250 | 9049 | reload_cse_move2add and move2add_note_store. */ |
5adf6da0 R |
9050 | static int move2add_luid; |
9051 | ||
61f5625b AO |
9052 | /* move2add_last_label_luid is set whenever a label is found. Labels |
9053 | invalidate all previously collected reg_offset data. */ | |
9054 | static int move2add_last_label_luid; | |
9055 | ||
ccc4ae07 | 9056 | /* Generate a CONST_INT and force it in the range of MODE. */ |
770ae6cc | 9057 | |
61f5625b AO |
9058 | static HOST_WIDE_INT |
9059 | sext_for_mode (mode, value) | |
ccc4ae07 AS |
9060 | enum machine_mode mode; |
9061 | HOST_WIDE_INT value; | |
9062 | { | |
9063 | HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); | |
9064 | int width = GET_MODE_BITSIZE (mode); | |
9065 | ||
9066 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, | |
9067 | sign extend it. */ | |
9068 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
9069 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
9070 | cval |= (HOST_WIDE_INT) -1 << width; | |
9071 | ||
61f5625b | 9072 | return cval; |
ccc4ae07 AS |
9073 | } |
9074 | ||
61f5625b AO |
9075 | /* ??? We don't know how zero / sign extension is handled, hence we |
9076 | can't go from a narrower to a wider mode. */ | |
9077 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
9078 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
9079 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
9080 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ | |
9081 | GET_MODE_BITSIZE (INMODE)))) | |
9082 | ||
5adf6da0 R |
9083 | static void |
9084 | reload_cse_move2add (first) | |
9085 | rtx first; | |
9086 | { | |
9087 | int i; | |
9088 | rtx insn; | |
5adf6da0 | 9089 | |
1d7254c5 | 9090 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
6764d250 BS |
9091 | reg_set_luid[i] = 0; |
9092 | ||
61f5625b AO |
9093 | move2add_last_label_luid = 0; |
9094 | move2add_luid = 2; | |
5adf6da0 R |
9095 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) |
9096 | { | |
9097 | rtx pat, note; | |
9098 | ||
9099 | if (GET_CODE (insn) == CODE_LABEL) | |
61f5625b AO |
9100 | { |
9101 | move2add_last_label_luid = move2add_luid; | |
9102 | /* We're going to increment move2add_luid twice after a | |
9103 | label, so that we can use move2add_last_label_luid + 1 as | |
9104 | the luid for constants. */ | |
9105 | move2add_luid++; | |
9106 | continue; | |
9107 | } | |
2c3c49de | 9108 | if (! INSN_P (insn)) |
5adf6da0 R |
9109 | continue; |
9110 | pat = PATTERN (insn); | |
9111 | /* For simplicity, we only perform this optimization on | |
9112 | straightforward SETs. */ | |
9113 | if (GET_CODE (pat) == SET | |
9114 | && GET_CODE (SET_DEST (pat)) == REG) | |
9115 | { | |
9116 | rtx reg = SET_DEST (pat); | |
9117 | int regno = REGNO (reg); | |
9118 | rtx src = SET_SRC (pat); | |
9119 | ||
9120 | /* Check if we have valid information on the contents of this | |
9121 | register in the mode of REG. */ | |
61f5625b AO |
9122 | if (reg_set_luid[regno] > move2add_last_label_luid |
9123 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])) | |
5adf6da0 R |
9124 | { |
9125 | /* Try to transform (set (REGX) (CONST_INT A)) | |
9126 | ... | |
9127 | (set (REGX) (CONST_INT B)) | |
9128 | to | |
9129 | (set (REGX) (CONST_INT A)) | |
9130 | ... | |
9131 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9132 | ||
9133 | if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) | |
9134 | { | |
9135 | int success = 0; | |
61f5625b AO |
9136 | rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), |
9137 | INTVAL (src) | |
9138 | - reg_offset[regno])); | |
5adf6da0 R |
9139 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
9140 | use (set (reg) (reg)) instead. | |
9141 | We don't delete this insn, nor do we convert it into a | |
9142 | note, to avoid losing register notes or the return | |
9143 | value flag. jump2 already knowns how to get rid of | |
9144 | no-op moves. */ | |
9145 | if (new_src == const0_rtx) | |
9146 | success = validate_change (insn, &SET_SRC (pat), reg, 0); | |
9147 | else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) | |
fb7e77d7 | 9148 | && have_add2_insn (reg, new_src)) |
5adf6da0 R |
9149 | success = validate_change (insn, &PATTERN (insn), |
9150 | gen_add2_insn (reg, new_src), 0); | |
5adf6da0 R |
9151 | reg_set_luid[regno] = move2add_luid; |
9152 | reg_mode[regno] = GET_MODE (reg); | |
61f5625b | 9153 | reg_offset[regno] = INTVAL (src); |
5adf6da0 R |
9154 | continue; |
9155 | } | |
9156 | ||
9157 | /* Try to transform (set (REGX) (REGY)) | |
9158 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9159 | ... | |
9160 | (set (REGX) (REGY)) | |
9161 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
9162 | to | |
9163 | (REGX) (REGY)) | |
9164 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9165 | ... | |
9166 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9167 | else if (GET_CODE (src) == REG | |
61f5625b AO |
9168 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
9169 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
9170 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), | |
9171 | reg_mode[REGNO (src)])) | |
5adf6da0 R |
9172 | { |
9173 | rtx next = next_nonnote_insn (insn); | |
6a651371 | 9174 | rtx set = NULL_RTX; |
5adf6da0 R |
9175 | if (next) |
9176 | set = single_set (next); | |
61f5625b | 9177 | if (set |
5adf6da0 R |
9178 | && SET_DEST (set) == reg |
9179 | && GET_CODE (SET_SRC (set)) == PLUS | |
9180 | && XEXP (SET_SRC (set), 0) == reg | |
9181 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
9182 | { | |
5adf6da0 | 9183 | rtx src3 = XEXP (SET_SRC (set), 1); |
61f5625b AO |
9184 | HOST_WIDE_INT added_offset = INTVAL (src3); |
9185 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; | |
9186 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
9187 | rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), | |
9188 | added_offset | |
9189 | + base_offset | |
9190 | - regno_offset)); | |
5adf6da0 R |
9191 | int success = 0; |
9192 | ||
9193 | if (new_src == const0_rtx) | |
9194 | /* See above why we create (set (reg) (reg)) here. */ | |
9195 | success | |
9196 | = validate_change (next, &SET_SRC (set), reg, 0); | |
9197 | else if ((rtx_cost (new_src, PLUS) | |
b437f1a7 | 9198 | < COSTS_N_INSNS (1) + rtx_cost (src3, SET)) |
fb7e77d7 | 9199 | && have_add2_insn (reg, new_src)) |
5adf6da0 R |
9200 | success |
9201 | = validate_change (next, &PATTERN (next), | |
9202 | gen_add2_insn (reg, new_src), 0); | |
9203 | if (success) | |
ca6c03ca | 9204 | delete_insn (insn); |
5adf6da0 | 9205 | insn = next; |
5adf6da0 | 9206 | reg_mode[regno] = GET_MODE (reg); |
61f5625b AO |
9207 | reg_offset[regno] = sext_for_mode (GET_MODE (reg), |
9208 | added_offset | |
9209 | + base_offset); | |
5adf6da0 R |
9210 | continue; |
9211 | } | |
9212 | } | |
9213 | } | |
9214 | } | |
9215 | ||
9216 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
9217 | { | |
9218 | if (REG_NOTE_KIND (note) == REG_INC | |
9219 | && GET_CODE (XEXP (note, 0)) == REG) | |
9220 | { | |
61f5625b | 9221 | /* Reset the information about this register. */ |
5adf6da0 R |
9222 | int regno = REGNO (XEXP (note, 0)); |
9223 | if (regno < FIRST_PSEUDO_REGISTER) | |
61f5625b | 9224 | reg_set_luid[regno] = 0; |
5adf6da0 | 9225 | } |
5adf6da0 | 9226 | } |
84832317 | 9227 | note_stores (PATTERN (insn), move2add_note_store, NULL); |
5adf6da0 R |
9228 | /* If this is a CALL_INSN, all call used registers are stored with |
9229 | unknown values. */ | |
9230 | if (GET_CODE (insn) == CALL_INSN) | |
9231 | { | |
1d7254c5 | 9232 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
5adf6da0 R |
9233 | { |
9234 | if (call_used_regs[i]) | |
61f5625b AO |
9235 | /* Reset the information about this register. */ |
9236 | reg_set_luid[i] = 0; | |
5adf6da0 R |
9237 | } |
9238 | } | |
9239 | } | |
9240 | } | |
9241 | ||
9242 | /* SET is a SET or CLOBBER that sets DST. | |
9243 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. | |
9244 | Called from reload_cse_move2add via note_stores. */ | |
770ae6cc | 9245 | |
5adf6da0 | 9246 | static void |
84832317 | 9247 | move2add_note_store (dst, set, data) |
5adf6da0 | 9248 | rtx dst, set; |
84832317 | 9249 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 | 9250 | { |
770ae6cc RK |
9251 | unsigned int regno = 0; |
9252 | unsigned int i; | |
5adf6da0 | 9253 | enum machine_mode mode = GET_MODE (dst); |
770ae6cc | 9254 | |
5adf6da0 R |
9255 | if (GET_CODE (dst) == SUBREG) |
9256 | { | |
ddef6bc7 JJ |
9257 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
9258 | GET_MODE (SUBREG_REG (dst)), | |
9259 | SUBREG_BYTE (dst), | |
9260 | GET_MODE (dst)); | |
5adf6da0 R |
9261 | dst = SUBREG_REG (dst); |
9262 | } | |
770ae6cc | 9263 | |
19ca869b JR |
9264 | /* Some targets do argument pushes without adding REG_INC notes. */ |
9265 | ||
9266 | if (GET_CODE (dst) == MEM) | |
9267 | { | |
9268 | dst = XEXP (dst, 0); | |
52fdbf26 | 9269 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC |
19ca869b | 9270 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) |
61f5625b | 9271 | reg_set_luid[REGNO (XEXP (dst, 0))] = 0; |
19ca869b | 9272 | return; |
174fa2c4 | 9273 | } |
5adf6da0 R |
9274 | if (GET_CODE (dst) != REG) |
9275 | return; | |
9276 | ||
9277 | regno += REGNO (dst); | |
9278 | ||
f93233bb JL |
9279 | if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET |
9280 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | |
9281 | && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT | |
9282 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | |
5adf6da0 R |
9283 | { |
9284 | rtx src = SET_SRC (set); | |
61f5625b AO |
9285 | rtx base_reg; |
9286 | HOST_WIDE_INT offset; | |
9287 | int base_regno; | |
9288 | /* This may be different from mode, if SET_DEST (set) is a | |
9289 | SUBREG. */ | |
9290 | enum machine_mode dst_mode = GET_MODE (dst); | |
5adf6da0 | 9291 | |
5adf6da0 R |
9292 | switch (GET_CODE (src)) |
9293 | { | |
9294 | case PLUS: | |
61f5625b AO |
9295 | if (GET_CODE (XEXP (src, 0)) == REG) |
9296 | { | |
9297 | base_reg = XEXP (src, 0); | |
9298 | ||
9299 | if (GET_CODE (XEXP (src, 1)) == CONST_INT) | |
9300 | offset = INTVAL (XEXP (src, 1)); | |
9301 | else if (GET_CODE (XEXP (src, 1)) == REG | |
9302 | && (reg_set_luid[REGNO (XEXP (src, 1))] | |
9303 | > move2add_last_label_luid) | |
9304 | && (MODES_OK_FOR_MOVE2ADD | |
9305 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) | |
9306 | { | |
9307 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0) | |
9308 | offset = reg_offset[REGNO (XEXP (src, 1))]; | |
9309 | /* Maybe the first register is known to be a | |
9310 | constant. */ | |
9311 | else if (reg_set_luid[REGNO (base_reg)] | |
9312 | > move2add_last_label_luid | |
9313 | && (MODES_OK_FOR_MOVE2ADD | |
9314 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))])) | |
9315 | && reg_base_reg[REGNO (base_reg)] < 0) | |
9316 | { | |
9317 | offset = reg_offset[REGNO (base_reg)]; | |
9318 | base_reg = XEXP (src, 1); | |
9319 | } | |
9320 | else | |
9321 | goto invalidate; | |
9322 | } | |
9323 | else | |
9324 | goto invalidate; | |
770ae6cc | 9325 | |
61f5625b AO |
9326 | break; |
9327 | } | |
770ae6cc | 9328 | |
61f5625b | 9329 | goto invalidate; |
5adf6da0 R |
9330 | |
9331 | case REG: | |
61f5625b AO |
9332 | base_reg = src; |
9333 | offset = 0; | |
5adf6da0 R |
9334 | break; |
9335 | ||
61f5625b AO |
9336 | case CONST_INT: |
9337 | /* Start tracking the register as a constant. */ | |
5adf6da0 | 9338 | reg_base_reg[regno] = -1; |
61f5625b AO |
9339 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
9340 | /* We assign the same luid to all registers set to constants. */ | |
9341 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
9342 | reg_mode[regno] = mode; | |
9343 | return; | |
9344 | ||
9345 | default: | |
9346 | invalidate: | |
9347 | /* Invalidate the contents of the register. */ | |
9348 | reg_set_luid[regno] = 0; | |
9349 | return; | |
5adf6da0 | 9350 | } |
61f5625b AO |
9351 | |
9352 | base_regno = REGNO (base_reg); | |
9353 | /* If information about the base register is not valid, set it | |
9354 | up as a new base register, pretending its value is known | |
9355 | starting from the current insn. */ | |
9356 | if (reg_set_luid[base_regno] <= move2add_last_label_luid) | |
9357 | { | |
9358 | reg_base_reg[base_regno] = base_regno; | |
9359 | reg_offset[base_regno] = 0; | |
9360 | reg_set_luid[base_regno] = move2add_luid; | |
9361 | reg_mode[base_regno] = mode; | |
9362 | } | |
9363 | else if (! MODES_OK_FOR_MOVE2ADD (dst_mode, | |
9364 | reg_mode[base_regno])) | |
9365 | goto invalidate; | |
9366 | ||
9367 | reg_mode[regno] = mode; | |
9368 | ||
9369 | /* Copy base information from our base register. */ | |
9370 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
9371 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
9372 | ||
9373 | /* Compute the sum of the offsets or constants. */ | |
9374 | reg_offset[regno] = sext_for_mode (dst_mode, | |
9375 | offset | |
9376 | + reg_offset[base_regno]); | |
5adf6da0 R |
9377 | } |
9378 | else | |
9379 | { | |
770ae6cc RK |
9380 | unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode); |
9381 | ||
9382 | for (i = regno; i < endregno; i++) | |
61f5625b AO |
9383 | /* Reset the information about this register. */ |
9384 | reg_set_luid[i] = 0; | |
5adf6da0 R |
9385 | } |
9386 | } | |
2dfa9a87 MH |
9387 | |
9388 | #ifdef AUTO_INC_DEC | |
9389 | static void | |
9390 | add_auto_inc_notes (insn, x) | |
9391 | rtx insn; | |
9392 | rtx x; | |
9393 | { | |
9394 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 9395 | const char *fmt; |
2dfa9a87 MH |
9396 | int i, j; |
9397 | ||
9398 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
9399 | { | |
9400 | REG_NOTES (insn) | |
9401 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
9402 | return; | |
9403 | } | |
9404 | ||
9405 | /* Scan all the operand sub-expressions. */ | |
9406 | fmt = GET_RTX_FORMAT (code); | |
9407 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9408 | { | |
9409 | if (fmt[i] == 'e') | |
9410 | add_auto_inc_notes (insn, XEXP (x, i)); | |
9411 | else if (fmt[i] == 'E') | |
9412 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9413 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
9414 | } | |
9415 | } | |
9416 | #endif | |
94bd63e5 AH |
9417 | |
9418 | /* Copy EH notes from an insn to its reloads. */ | |
9419 | static void | |
9420 | copy_eh_notes (insn, x) | |
9421 | rtx insn; | |
9422 | rtx x; | |
9423 | { | |
9424 | rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
9425 | if (eh_note) | |
9426 | { | |
9427 | for (; x != 0; x = NEXT_INSN (x)) | |
9428 | { | |
9429 | if (may_trap_p (PATTERN (x))) | |
9430 | REG_NOTES (x) | |
9431 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), | |
9432 | REG_NOTES (x)); | |
9433 | } | |
9434 | } | |
9435 | } | |
9436 | ||
f1330226 JH |
9437 | /* This is used by reload pass, that does emit some instructions after |
9438 | abnormal calls moving basic block end, but in fact it wants to emit | |
9439 | them on the edge. Looks for abnormal call edges, find backward the | |
9440 | proper call and fix the damage. | |
9441 | ||
9442 | Similar handle instructions throwing exceptions internally. */ | |
9443 | static void | |
9444 | fixup_abnormal_edges () | |
9445 | { | |
9446 | int i; | |
9447 | bool inserted = false; | |
9448 | ||
9449 | for (i = 0; i < n_basic_blocks; i++) | |
9450 | { | |
9451 | basic_block bb = BASIC_BLOCK (i); | |
9452 | edge e; | |
9453 | ||
9454 | /* Look for cases we are interested in - an calls or instructions causing | |
9455 | exceptions. */ | |
9456 | for (e = bb->succ; e; e = e->succ_next) | |
9457 | { | |
9458 | if (e->flags & EDGE_ABNORMAL_CALL) | |
9459 | break; | |
9460 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
9461 | == (EDGE_ABNORMAL | EDGE_EH)) | |
9462 | break; | |
9463 | } | |
9464 | if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end)) | |
9465 | { | |
0c4992b0 | 9466 | rtx insn = bb->end, stop = NEXT_INSN (bb->end); |
f1330226 JH |
9467 | rtx next; |
9468 | for (e = bb->succ; e; e = e->succ_next) | |
9469 | if (e->flags & EDGE_FALLTHRU) | |
9470 | break; | |
39f95a2c JH |
9471 | /* Get past the new insns generated. Allow notes, as the insns may |
9472 | be already deleted. */ | |
9473 | while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE) | |
9474 | && !can_throw_internal (insn) | |
9475 | && insn != bb->head) | |
f1330226 JH |
9476 | insn = PREV_INSN (insn); |
9477 | if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn)) | |
9478 | abort (); | |
9479 | bb->end = insn; | |
9480 | inserted = true; | |
9481 | insn = NEXT_INSN (insn); | |
0c4992b0 | 9482 | while (insn && insn != stop) |
f1330226 JH |
9483 | { |
9484 | next = NEXT_INSN (insn); | |
0c4992b0 JH |
9485 | if (INSN_P (insn)) |
9486 | { | |
9487 | insert_insn_on_edge (PATTERN (insn), e); | |
53c17031 | 9488 | delete_insn (insn); |
0c4992b0 | 9489 | } |
f1330226 JH |
9490 | insn = next; |
9491 | } | |
9492 | } | |
9493 | } | |
9494 | if (inserted) | |
9495 | commit_edge_insertions (); | |
9496 | } |