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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd JL |
2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
32131a9c RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
cab634f2 KG |
24 | |
25 | #include "machmode.h" | |
26 | #include "hard-reg-set.h" | |
32131a9c | 27 | #include "rtl.h" |
6baf1cc8 | 28 | #include "tm_p.h" |
32131a9c RK |
29 | #include "obstack.h" |
30 | #include "insn-config.h" | |
31 | #include "insn-flags.h" | |
32 | #include "insn-codes.h" | |
33 | #include "flags.h" | |
49ad7cfa | 34 | #include "function.h" |
32131a9c RK |
35 | #include "expr.h" |
36 | #include "regs.h" | |
cad6f7d0 | 37 | #include "basic-block.h" |
32131a9c RK |
38 | #include "reload.h" |
39 | #include "recog.h" | |
32131a9c | 40 | #include "output.h" |
eab5c70a | 41 | #include "cselib.h" |
a9c366bf | 42 | #include "real.h" |
10f0ad3d | 43 | #include "toplev.h" |
32131a9c | 44 | |
65954bd8 JL |
45 | #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY |
46 | #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY | |
47 | #endif | |
48 | ||
32131a9c RK |
49 | /* This file contains the reload pass of the compiler, which is |
50 | run after register allocation has been done. It checks that | |
51 | each insn is valid (operands required to be in registers really | |
52 | are in registers of the proper class) and fixes up invalid ones | |
53 | by copying values temporarily into registers for the insns | |
54 | that need them. | |
55 | ||
56 | The results of register allocation are described by the vector | |
57 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
58 | can be used to find which hard reg, if any, a pseudo reg is in. | |
59 | ||
60 | The technique we always use is to free up a few hard regs that are | |
61 | called ``reload regs'', and for each place where a pseudo reg | |
62 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
63 | ||
03acd8f8 BS |
64 | Reload regs are allocated locally for every instruction that needs |
65 | reloads. When there are pseudos which are allocated to a register that | |
66 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
67 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
68 | available hard regs can be found. Spilling can invalidate more |
69 | insns, requiring additional need for reloads, so we must keep checking | |
70 | until the process stabilizes. | |
71 | ||
72 | For machines with different classes of registers, we must keep track | |
73 | of the register class needed for each reload, and make sure that | |
74 | we allocate enough reload registers of each class. | |
75 | ||
76 | The file reload.c contains the code that checks one insn for | |
77 | validity and reports the reloads that it needs. This file | |
78 | is in charge of scanning the entire rtl code, accumulating the | |
79 | reload needs, spilling, assigning reload registers to use for | |
80 | fixing up each insn, and generating the new insns to copy values | |
81 | into the reload registers. */ | |
546b63fb | 82 | |
546b63fb RK |
83 | #ifndef REGISTER_MOVE_COST |
84 | #define REGISTER_MOVE_COST(x, y) 2 | |
85 | #endif | |
2a3e384f RH |
86 | |
87 | #ifndef LOCAL_REGNO | |
88 | #define LOCAL_REGNO(REGNO) 0 | |
89 | #endif | |
32131a9c RK |
90 | \f |
91 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 92 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
93 | static rtx *reg_last_reload_reg; |
94 | ||
95 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
96 | for an output reload that stores into reg N. */ | |
97 | static char *reg_has_output_reload; | |
98 | ||
99 | /* Indicates which hard regs are reload-registers for an output reload | |
100 | in the current insn. */ | |
101 | static HARD_REG_SET reg_is_output_reload; | |
102 | ||
103 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
104 | or zero if pseudo reg N is not equivalent to a constant. | |
105 | find_reloads looks at this in order to replace pseudo reg N | |
106 | with the constant it stands for. */ | |
107 | rtx *reg_equiv_constant; | |
108 | ||
109 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
110 | prior to any register elimination (such as frame pointer to stack | |
111 | pointer). Depending on whether or not it is a valid address, this value | |
112 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 113 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
114 | |
115 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
116 | This is used when the address is not valid as a memory address | |
117 | (because its displacement is too big for the machine.) */ | |
118 | rtx *reg_equiv_address; | |
119 | ||
120 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
121 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
122 | rtx *reg_equiv_mem; | |
123 | ||
124 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
770ae6cc | 125 | static unsigned int *reg_max_ref_width; |
32131a9c | 126 | |
135eb61c | 127 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c RK |
128 | constant or memory slot. */ |
129 | static rtx *reg_equiv_init; | |
130 | ||
03acd8f8 BS |
131 | /* Vector to remember old contents of reg_renumber before spilling. */ |
132 | static short *reg_old_renumber; | |
133 | ||
e6e52be0 | 134 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 135 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
136 | reg_reloaded_contents points to that pseudo for each spill register in |
137 | use; all of these must remain set for an inheritance to occur. */ | |
138 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
139 | ||
140 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
141 | hard register N was last used. Its contents are significant only |
142 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
143 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
144 | ||
e6e52be0 R |
145 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ |
146 | static HARD_REG_SET reg_reloaded_valid; | |
147 | /* Indicate if the register was dead at the end of the reload. | |
148 | This is only valid if reg_reloaded_contents is set and valid. */ | |
149 | static HARD_REG_SET reg_reloaded_dead; | |
150 | ||
32131a9c RK |
151 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
152 | static int n_spills; | |
153 | ||
154 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
155 | Holds the last rtx used for any given reg, or 0 if it has never | |
156 | been used for spilling yet. This rtx is reused, provided it has | |
157 | the proper mode. */ | |
158 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
159 | ||
160 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
161 | that was stored after the last time it was used. | |
162 | The precise value is the insn generated to do the store. */ | |
163 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
164 | ||
cb2afeb3 R |
165 | /* This is the register that was stored with spill_reg_store. This is a |
166 | copy of reload_out / reload_out_reg when the value was stored; if | |
167 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
168 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
169 | ||
32131a9c RK |
170 | /* This table is the inverse mapping of spill_regs: |
171 | indexed by hard reg number, | |
172 | it contains the position of that reg in spill_regs, | |
05d10675 | 173 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
174 | |
175 | ?!? This is no longer accurate. */ | |
32131a9c RK |
176 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
177 | ||
03acd8f8 BS |
178 | /* This reg set indicates registers that can't be used as spill registers for |
179 | the currently processed insn. These are the hard registers which are live | |
180 | during the insn, but not allocated to pseudos, as well as fixed | |
181 | registers. */ | |
32131a9c RK |
182 | static HARD_REG_SET bad_spill_regs; |
183 | ||
03acd8f8 BS |
184 | /* These are the hard registers that can't be used as spill register for any |
185 | insn. This includes registers used for user variables and registers that | |
186 | we can't eliminate. A register that appears in this set also can't be used | |
187 | to retry register allocation. */ | |
188 | static HARD_REG_SET bad_spill_regs_global; | |
189 | ||
32131a9c | 190 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
191 | of spilled pseudo-registers. `n_spills' is the number of |
192 | elements that are actually valid; new ones are added at the end. | |
193 | ||
194 | Both spill_regs and spill_reg_order are used on two occasions: | |
195 | once during find_reload_regs, where they keep track of the spill registers | |
196 | for a single insn, but also during reload_as_needed where they show all | |
197 | the registers ever used by reload. For the latter case, the information | |
198 | is calculated during finish_spills. */ | |
32131a9c RK |
199 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
200 | ||
03acd8f8 BS |
201 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
202 | may not be used for retrying global allocation because the register was | |
203 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
204 | a register that it was already allocated to, reload might not | |
205 | terminate. */ | |
206 | static HARD_REG_SET *pseudo_previous_regs; | |
207 | ||
208 | /* This vector of reg sets indicates, for each pseudo, which hard | |
209 | registers may not be used for retrying global allocation because they | |
210 | are used as spill registers during one of the insns in which the | |
211 | pseudo is live. */ | |
212 | static HARD_REG_SET *pseudo_forbidden_regs; | |
213 | ||
214 | /* All hard regs that have been used as spill registers for any insn are | |
215 | marked in this set. */ | |
216 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 217 | |
4079cd63 JW |
218 | /* Index of last register assigned as a spill register. We allocate in |
219 | a round-robin fashion. */ | |
4079cd63 JW |
220 | static int last_spill_reg; |
221 | ||
32131a9c RK |
222 | /* Nonzero if indirect addressing is supported on the machine; this means |
223 | that spilling (REG n) does not require reloading it into a register in | |
224 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
225 | value indicates the level of indirect addressing supported, e.g., two | |
226 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
227 | a hard register. */ | |
32131a9c RK |
228 | static char spill_indirect_levels; |
229 | ||
230 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
231 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
232 | which these are valid is the same as spill_indirect_levels, above. */ | |
32131a9c RK |
233 | char indirect_symref_ok; |
234 | ||
235 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
236 | char double_reg_address_ok; |
237 | ||
238 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
239 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
240 | ||
241 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 242 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 243 | |
7609e720 | 244 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
245 | static regset_head spilled_pseudos; |
246 | ||
247 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
248 | Used to avoid counting one pseudo twice. */ | |
249 | static regset_head pseudos_counted; | |
7609e720 | 250 | |
32131a9c RK |
251 | /* First uid used by insns created by reload in this function. |
252 | Used in find_equiv_reg. */ | |
253 | int reload_first_uid; | |
254 | ||
255 | /* Flag set by local-alloc or global-alloc if anything is live in | |
256 | a call-clobbered reg across calls. */ | |
32131a9c RK |
257 | int caller_save_needed; |
258 | ||
259 | /* Set to 1 while reload_as_needed is operating. | |
260 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
261 | int reload_in_progress = 0; |
262 | ||
263 | /* These arrays record the insn_code of insns that may be needed to | |
264 | perform input and output reloads of special objects. They provide a | |
265 | place to pass a scratch register. */ | |
32131a9c RK |
266 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
267 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
268 | ||
d45cf215 | 269 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
270 | The allocated storage can be freed once find_reloads has processed the |
271 | insn. */ | |
32131a9c | 272 | struct obstack reload_obstack; |
cad6f7d0 BS |
273 | |
274 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
275 | are allocated first. */ | |
276 | char *reload_startobj; | |
277 | ||
278 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 279 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
32131a9c RK |
280 | char *reload_firstobj; |
281 | ||
f5d8c9f4 BS |
282 | /* This points before all local rtl generated by register elimination. |
283 | Used to quickly free all memory after processing one insn. */ | |
284 | static char *reload_insn_firstobj; | |
285 | ||
32131a9c RK |
286 | #define obstack_chunk_alloc xmalloc |
287 | #define obstack_chunk_free free | |
288 | ||
cad6f7d0 BS |
289 | /* List of insn_chain instructions, one for every insn that reload needs to |
290 | examine. */ | |
291 | struct insn_chain *reload_insn_chain; | |
7609e720 | 292 | |
dfb7c80f JL |
293 | #ifdef TREE_CODE |
294 | extern tree current_function_decl; | |
295 | #else | |
122a860e | 296 | extern union tree_node *current_function_decl; |
dfb7c80f JL |
297 | #endif |
298 | ||
03acd8f8 | 299 | /* List of all insns needing reloads. */ |
7609e720 | 300 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
301 | \f |
302 | /* This structure is used to record information about register eliminations. | |
303 | Each array entry describes one possible way of eliminating a register | |
304 | in favor of another. If there is more than one way of eliminating a | |
305 | particular register, the most preferred should be specified first. */ | |
306 | ||
590cf94d | 307 | struct elim_table |
32131a9c | 308 | { |
0f41302f MS |
309 | int from; /* Register number to be eliminated. */ |
310 | int to; /* Register number used as replacement. */ | |
311 | int initial_offset; /* Initial difference between values. */ | |
312 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
32131a9c | 313 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f MS |
314 | insns made by reload. */ |
315 | int offset; /* Current offset between the two regs. */ | |
0f41302f MS |
316 | int previous_offset; /* Offset at end of previous insn. */ |
317 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
32131a9c RK |
318 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
319 | We cannot simply compare the number since | |
320 | we might then spuriously replace a hard | |
321 | register corresponding to a pseudo | |
0f41302f MS |
322 | assigned to the reg to be eliminated. */ |
323 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
324 | }; |
325 | ||
1d7254c5 | 326 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
327 | |
328 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 329 | exactly the members provided by ELIMINABLE_REGS. */ |
590cf94d KG |
330 | static struct elim_table_1 |
331 | { | |
332 | int from; | |
333 | int to; | |
334 | } reg_eliminate_1[] = | |
32131a9c RK |
335 | |
336 | /* If a set of eliminable registers was specified, define the table from it. | |
337 | Otherwise, default to the normal case of the frame pointer being | |
338 | replaced by the stack pointer. */ | |
339 | ||
340 | #ifdef ELIMINABLE_REGS | |
341 | ELIMINABLE_REGS; | |
342 | #else | |
343 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
344 | #endif | |
345 | ||
b6a1cbae | 346 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
347 | |
348 | /* Record the number of pending eliminations that have an offset not equal | |
349 | to their initial offset. If non-zero, we use a new copy of each | |
350 | replacement result in any insns encountered. */ | |
cb2afeb3 | 351 | int num_not_at_initial_offset; |
32131a9c RK |
352 | |
353 | /* Count the number of registers that we may be able to eliminate. */ | |
354 | static int num_eliminable; | |
2b49ee39 R |
355 | /* And the number of registers that are equivalent to a constant that |
356 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
357 | static int num_eliminable_invariants; | |
32131a9c RK |
358 | |
359 | /* For each label, we record the offset of each elimination. If we reach | |
360 | a label by more than one path and an offset differs, we cannot do the | |
361 | elimination. This information is indexed by the number of the label. | |
362 | The first table is an array of flags that records whether we have yet | |
363 | encountered a label and the second table is an array of arrays, one | |
364 | entry in the latter array for each elimination. */ | |
365 | ||
366 | static char *offsets_known_at; | |
367 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
368 | ||
369 | /* Number of labels in the current function. */ | |
370 | ||
371 | static int num_labels; | |
372 | \f | |
cdadb1dd KG |
373 | static void maybe_fix_stack_asms PARAMS ((void)); |
374 | static void copy_reloads PARAMS ((struct insn_chain *)); | |
375 | static void calculate_needs_all_insns PARAMS ((int)); | |
e04ca094 JL |
376 | static int find_reg PARAMS ((struct insn_chain *, int)); |
377 | static void find_reload_regs PARAMS ((struct insn_chain *)); | |
378 | static void select_reload_regs PARAMS ((void)); | |
cdadb1dd KG |
379 | static void delete_caller_save_insns PARAMS ((void)); |
380 | ||
381 | static void spill_failure PARAMS ((rtx, enum reg_class)); | |
382 | static void count_spilled_pseudo PARAMS ((int, int, int)); | |
383 | static void delete_dead_insn PARAMS ((rtx)); | |
384 | static void alter_reg PARAMS ((int, int)); | |
385 | static void set_label_offsets PARAMS ((rtx, rtx, int)); | |
386 | static void check_eliminable_occurrences PARAMS ((rtx)); | |
387 | static void elimination_effects PARAMS ((rtx, enum machine_mode)); | |
388 | static int eliminate_regs_in_insn PARAMS ((rtx, int)); | |
389 | static void update_eliminable_offsets PARAMS ((void)); | |
390 | static void mark_not_eliminable PARAMS ((rtx, rtx, void *)); | |
391 | static void set_initial_elim_offsets PARAMS ((void)); | |
392 | static void verify_initial_elim_offsets PARAMS ((void)); | |
393 | static void set_initial_label_offsets PARAMS ((void)); | |
394 | static void set_offsets_for_label PARAMS ((rtx)); | |
395 | static void init_elim_table PARAMS ((void)); | |
396 | static void update_eliminables PARAMS ((HARD_REG_SET *)); | |
e04ca094 JL |
397 | static void spill_hard_reg PARAMS ((unsigned int, int)); |
398 | static int finish_spills PARAMS ((int)); | |
cdadb1dd KG |
399 | static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *)); |
400 | static void scan_paradoxical_subregs PARAMS ((rtx)); | |
401 | static void count_pseudo PARAMS ((int)); | |
402 | static void order_regs_for_reload PARAMS ((struct insn_chain *)); | |
e04ca094 | 403 | static void reload_as_needed PARAMS ((int)); |
cdadb1dd KG |
404 | static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *)); |
405 | static int reload_reg_class_lower PARAMS ((const PTR, const PTR)); | |
770ae6cc RK |
406 | static void mark_reload_reg_in_use PARAMS ((unsigned int, int, |
407 | enum reload_type, | |
408 | enum machine_mode)); | |
409 | static void clear_reload_reg_in_use PARAMS ((unsigned int, int, | |
410 | enum reload_type, | |
411 | enum machine_mode)); | |
412 | static int reload_reg_free_p PARAMS ((unsigned int, int, | |
413 | enum reload_type)); | |
cdadb1dd | 414 | static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type, |
770ae6cc | 415 | rtx, rtx, int, int)); |
c02cad8f BS |
416 | static int free_for_value_p PARAMS ((int, enum machine_mode, int, |
417 | enum reload_type, rtx, rtx, | |
418 | int, int)); | |
770ae6cc RK |
419 | static int reload_reg_reaches_end_p PARAMS ((unsigned int, int, |
420 | enum reload_type)); | |
421 | static int allocate_reload_reg PARAMS ((struct insn_chain *, int, | |
422 | int)); | |
ff6534ad | 423 | static int conflicts_with_override PARAMS ((rtx)); |
cdadb1dd KG |
424 | static void failed_reload PARAMS ((rtx, int)); |
425 | static int set_reload_reg PARAMS ((int, int)); | |
426 | static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *)); | |
427 | static void choose_reload_regs PARAMS ((struct insn_chain *)); | |
428 | static void merge_assigned_reloads PARAMS ((rtx)); | |
429 | static void emit_input_reload_insns PARAMS ((struct insn_chain *, | |
770ae6cc | 430 | struct reload *, rtx, int)); |
cdadb1dd | 431 | static void emit_output_reload_insns PARAMS ((struct insn_chain *, |
770ae6cc | 432 | struct reload *, int)); |
cdadb1dd | 433 | static void do_input_reload PARAMS ((struct insn_chain *, |
770ae6cc | 434 | struct reload *, int)); |
cdadb1dd | 435 | static void do_output_reload PARAMS ((struct insn_chain *, |
770ae6cc | 436 | struct reload *, int)); |
e04ca094 | 437 | static void emit_reload_insns PARAMS ((struct insn_chain *)); |
cdadb1dd KG |
438 | static void delete_output_reload PARAMS ((rtx, int, int)); |
439 | static void delete_address_reloads PARAMS ((rtx, rtx)); | |
440 | static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx)); | |
441 | static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int)); | |
442 | static int constraint_accepts_reg_p PARAMS ((const char *, rtx)); | |
443 | static void reload_cse_regs_1 PARAMS ((rtx)); | |
eab5c70a | 444 | static int reload_cse_noop_set_p PARAMS ((rtx)); |
cdadb1dd KG |
445 | static int reload_cse_simplify_set PARAMS ((rtx, rtx)); |
446 | static int reload_cse_simplify_operands PARAMS ((rtx)); | |
770ae6cc RK |
447 | static void reload_combine PARAMS ((void)); |
448 | static void reload_combine_note_use PARAMS ((rtx *, rtx)); | |
449 | static void reload_combine_note_store PARAMS ((rtx, rtx, void *)); | |
450 | static void reload_cse_move2add PARAMS ((rtx)); | |
451 | static void move2add_note_store PARAMS ((rtx, rtx, void *)); | |
2dfa9a87 | 452 | #ifdef AUTO_INC_DEC |
770ae6cc | 453 | static void add_auto_inc_notes PARAMS ((rtx, rtx)); |
2dfa9a87 | 454 | #endif |
cdadb1dd | 455 | static rtx gen_mode_int PARAMS ((enum machine_mode, |
770ae6cc | 456 | HOST_WIDE_INT)); |
cdadb1dd KG |
457 | static void failed_reload PARAMS ((rtx, int)); |
458 | static int set_reload_reg PARAMS ((int, int)); | |
e77d72cb KG |
459 | static void reload_cse_delete_noop_set PARAMS ((rtx, rtx)); |
460 | static void reload_cse_simplify PARAMS ((rtx)); | |
e04ca094 | 461 | extern void dump_needs PARAMS ((struct insn_chain *)); |
32131a9c | 462 | \f |
546b63fb RK |
463 | /* Initialize the reload pass once per compilation. */ |
464 | ||
32131a9c RK |
465 | void |
466 | init_reload () | |
467 | { | |
468 | register int i; | |
469 | ||
470 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
471 | Set spill_indirect_levels to the number of levels such addressing is | |
472 | permitted, zero if it is not permitted at all. */ | |
473 | ||
474 | register rtx tem | |
38a448ca RH |
475 | = gen_rtx_MEM (Pmode, |
476 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
477 | gen_rtx_REG (Pmode, |
478 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 479 | GEN_INT (4))); |
32131a9c RK |
480 | spill_indirect_levels = 0; |
481 | ||
482 | while (memory_address_p (QImode, tem)) | |
483 | { | |
484 | spill_indirect_levels++; | |
38a448ca | 485 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
486 | } |
487 | ||
488 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
489 | ||
38a448ca | 490 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
491 | indirect_symref_ok = memory_address_p (QImode, tem); |
492 | ||
493 | /* See if reg+reg is a valid (and offsettable) address. */ | |
494 | ||
65701fd2 | 495 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 496 | { |
38a448ca RH |
497 | tem = gen_rtx_PLUS (Pmode, |
498 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
499 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 500 | |
57caa638 RS |
501 | /* This way, we make sure that reg+reg is an offsettable address. */ |
502 | tem = plus_constant (tem, 4); | |
503 | ||
504 | if (memory_address_p (QImode, tem)) | |
505 | { | |
506 | double_reg_address_ok = 1; | |
507 | break; | |
508 | } | |
509 | } | |
32131a9c | 510 | |
0f41302f | 511 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 512 | gcc_obstack_init (&reload_obstack); |
cad6f7d0 | 513 | reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
514 | |
515 | INIT_REG_SET (&spilled_pseudos); | |
516 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
517 | } |
518 | ||
cad6f7d0 BS |
519 | /* List of insn chains that are currently unused. */ |
520 | static struct insn_chain *unused_insn_chains = 0; | |
521 | ||
522 | /* Allocate an empty insn_chain structure. */ | |
523 | struct insn_chain * | |
524 | new_insn_chain () | |
525 | { | |
526 | struct insn_chain *c; | |
527 | ||
528 | if (unused_insn_chains == 0) | |
529 | { | |
8db99db2 KG |
530 | c = (struct insn_chain *) |
531 | obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); | |
239a0f5b BS |
532 | INIT_REG_SET (&c->live_throughout); |
533 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
534 | } |
535 | else | |
536 | { | |
537 | c = unused_insn_chains; | |
538 | unused_insn_chains = c->next; | |
539 | } | |
540 | c->is_caller_save_insn = 0; | |
03acd8f8 | 541 | c->need_operand_change = 0; |
cad6f7d0 BS |
542 | c->need_reload = 0; |
543 | c->need_elim = 0; | |
544 | return c; | |
545 | } | |
546 | ||
7609e720 BS |
547 | /* Small utility function to set all regs in hard reg set TO which are |
548 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 549 | |
7609e720 BS |
550 | void |
551 | compute_use_by_pseudos (to, from) | |
552 | HARD_REG_SET *to; | |
553 | regset from; | |
554 | { | |
770ae6cc RK |
555 | unsigned int regno; |
556 | ||
7609e720 BS |
557 | EXECUTE_IF_SET_IN_REG_SET |
558 | (from, FIRST_PSEUDO_REGISTER, regno, | |
559 | { | |
560 | int r = reg_renumber[regno]; | |
561 | int nregs; | |
770ae6cc | 562 | |
7609e720 | 563 | if (r < 0) |
404d95c4 R |
564 | { |
565 | /* reload_combine uses the information from | |
e881bb1b RH |
566 | BASIC_BLOCK->global_live_at_start, which might still |
567 | contain registers that have not actually been allocated | |
568 | since they have an equivalence. */ | |
404d95c4 R |
569 | if (! reload_completed) |
570 | abort (); | |
571 | } | |
572 | else | |
573 | { | |
574 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); | |
575 | while (nregs-- > 0) | |
576 | SET_HARD_REG_BIT (*to, r + nregs); | |
577 | } | |
7609e720 BS |
578 | }); |
579 | } | |
03acd8f8 | 580 | \f |
1e5bd841 BS |
581 | /* Global variables used by reload and its subroutines. */ |
582 | ||
1e5bd841 BS |
583 | /* Set during calculate_needs if an insn needs register elimination. */ |
584 | static int something_needs_elimination; | |
cb2afeb3 R |
585 | /* Set during calculate_needs if an insn needs an operand changed. */ |
586 | int something_needs_operands_changed; | |
1e5bd841 | 587 | |
1e5bd841 BS |
588 | /* Nonzero means we couldn't get enough spill regs. */ |
589 | static int failure; | |
590 | ||
546b63fb | 591 | /* Main entry point for the reload pass. |
32131a9c RK |
592 | |
593 | FIRST is the first insn of the function being compiled. | |
594 | ||
595 | GLOBAL nonzero means we were called from global_alloc | |
596 | and should attempt to reallocate any pseudoregs that we | |
597 | displace from hard regs we will use for reloads. | |
598 | If GLOBAL is zero, we do not have enough information to do that, | |
599 | so any pseudo reg that is spilled must go to the stack. | |
600 | ||
5352b11a RS |
601 | Return value is nonzero if reload failed |
602 | and we must not do any more for this function. */ | |
603 | ||
604 | int | |
e04ca094 | 605 | reload (first, global) |
32131a9c RK |
606 | rtx first; |
607 | int global; | |
32131a9c | 608 | { |
03acd8f8 | 609 | register int i; |
32131a9c RK |
610 | register rtx insn; |
611 | register struct elim_table *ep; | |
612 | ||
a68d4b75 BK |
613 | /* The two pointers used to track the true location of the memory used |
614 | for label offsets. */ | |
615 | char *real_known_ptr = NULL_PTR; | |
616 | int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; | |
617 | ||
32131a9c RK |
618 | /* Make sure even insns with volatile mem refs are recognizable. */ |
619 | init_recog (); | |
620 | ||
1e5bd841 BS |
621 | failure = 0; |
622 | ||
cad6f7d0 BS |
623 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
624 | ||
437a710d BS |
625 | /* Make sure that the last insn in the chain |
626 | is not something that needs reloading. */ | |
627 | emit_note (NULL_PTR, NOTE_INSN_DELETED); | |
628 | ||
32131a9c RK |
629 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
630 | reload_first_uid = get_max_uid (); | |
631 | ||
0dadecf6 RK |
632 | #ifdef SECONDARY_MEMORY_NEEDED |
633 | /* Initialize the secondary memory table. */ | |
634 | clear_secondary_mem (); | |
635 | #endif | |
636 | ||
32131a9c | 637 | /* We don't have a stack slot for any spill reg yet. */ |
961192e1 JM |
638 | memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot); |
639 | memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 640 | |
a8efe40d RK |
641 | /* Initialize the save area information for caller-save, in case some |
642 | are needed. */ | |
643 | init_save_areas (); | |
a8fdc208 | 644 | |
32131a9c RK |
645 | /* Compute which hard registers are now in use |
646 | as homes for pseudo registers. | |
647 | This is done here rather than (eg) in global_alloc | |
648 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
649 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
650 | mark_home_live (i); | |
651 | ||
8dddd002 RK |
652 | /* A function that receives a nonlocal goto must save all call-saved |
653 | registers. */ | |
654 | if (current_function_has_nonlocal_label) | |
655 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2a3e384f RH |
656 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
657 | regs_ever_live[i] = 1; | |
8dddd002 | 658 | |
32131a9c RK |
659 | /* Find all the pseudo registers that didn't get hard regs |
660 | but do have known equivalent constants or memory slots. | |
661 | These include parameters (known equivalent to parameter slots) | |
662 | and cse'd or loop-moved constant memory addresses. | |
663 | ||
664 | Record constant equivalents in reg_equiv_constant | |
665 | so they will be substituted by find_reloads. | |
666 | Record memory equivalents in reg_mem_equiv so they can | |
667 | be substituted eventually by altering the REG-rtx's. */ | |
668 | ||
ad85216e KG |
669 | reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
670 | reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
671 | reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
672 | reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
673 | reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
f9e158c3 | 674 | reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int)); |
ad85216e | 675 | reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short)); |
4e135bdd | 676 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
03acd8f8 BS |
677 | pseudo_forbidden_regs |
678 | = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); | |
679 | pseudo_previous_regs | |
ad85216e | 680 | = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET)); |
32131a9c | 681 | |
03acd8f8 | 682 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 683 | |
32131a9c | 684 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. |
56f58d3a RK |
685 | Also find all paradoxical subregs and find largest such for each pseudo. |
686 | On machines with small register classes, record hard registers that | |
05d10675 | 687 | are used for user variables. These can never be used for spills. |
b453cb0b RK |
688 | Also look for a "constant" NOTE_INSN_SETJMP. This means that all |
689 | caller-saved registers must be marked live. */ | |
32131a9c | 690 | |
2b49ee39 | 691 | num_eliminable_invariants = 0; |
32131a9c RK |
692 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
693 | { | |
694 | rtx set = single_set (insn); | |
695 | ||
b453cb0b RK |
696 | if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn) |
697 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) | |
698 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
699 | if (! call_used_regs[i]) | |
700 | regs_ever_live[i] = 1; | |
701 | ||
32131a9c RK |
702 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) |
703 | { | |
fb3821f7 | 704 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
705 | if (note |
706 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2b49ee39 R |
707 | && (! function_invariant_p (XEXP (note, 0)) |
708 | || ! flag_pic | |
a8efe40d RK |
709 | || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) |
710 | #endif | |
711 | ) | |
32131a9c RK |
712 | { |
713 | rtx x = XEXP (note, 0); | |
714 | i = REGNO (SET_DEST (set)); | |
715 | if (i > LAST_VIRTUAL_REGISTER) | |
716 | { | |
717 | if (GET_CODE (x) == MEM) | |
956d6950 JL |
718 | { |
719 | /* If the operand is a PLUS, the MEM may be shared, | |
720 | so make sure we have an unshared copy here. */ | |
721 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
722 | x = copy_rtx (x); | |
723 | ||
724 | reg_equiv_memory_loc[i] = x; | |
725 | } | |
2b49ee39 | 726 | else if (function_invariant_p (x)) |
32131a9c | 727 | { |
2b49ee39 R |
728 | if (GET_CODE (x) == PLUS) |
729 | { | |
730 | /* This is PLUS of frame pointer and a constant, | |
731 | and might be shared. Unshare it. */ | |
732 | reg_equiv_constant[i] = copy_rtx (x); | |
733 | num_eliminable_invariants++; | |
734 | } | |
735 | else if (x == frame_pointer_rtx | |
736 | || x == arg_pointer_rtx) | |
737 | { | |
738 | reg_equiv_constant[i] = x; | |
739 | num_eliminable_invariants++; | |
740 | } | |
741 | else if (LEGITIMATE_CONSTANT_P (x)) | |
32131a9c RK |
742 | reg_equiv_constant[i] = x; |
743 | else | |
744 | reg_equiv_memory_loc[i] | |
d445b551 | 745 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
746 | } |
747 | else | |
748 | continue; | |
749 | ||
750 | /* If this register is being made equivalent to a MEM | |
751 | and the MEM is not SET_SRC, the equivalencing insn | |
752 | is one with the MEM as a SET_DEST and it occurs later. | |
753 | So don't mark this insn now. */ | |
754 | if (GET_CODE (x) != MEM | |
755 | || rtx_equal_p (SET_SRC (set), x)) | |
135eb61c R |
756 | reg_equiv_init[i] |
757 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); | |
32131a9c RK |
758 | } |
759 | } | |
760 | } | |
761 | ||
762 | /* If this insn is setting a MEM from a register equivalent to it, | |
763 | this is the equivalencing insn. */ | |
764 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
765 | && GET_CODE (SET_SRC (set)) == REG | |
766 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
767 | && rtx_equal_p (SET_DEST (set), | |
768 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
135eb61c R |
769 | reg_equiv_init[REGNO (SET_SRC (set))] |
770 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
771 | reg_equiv_init[REGNO (SET_SRC (set))]); | |
32131a9c | 772 | |
2c3c49de | 773 | if (INSN_P (insn)) |
32131a9c RK |
774 | scan_paradoxical_subregs (PATTERN (insn)); |
775 | } | |
776 | ||
09dd1133 | 777 | init_elim_table (); |
32131a9c RK |
778 | |
779 | num_labels = max_label_num () - get_first_label_num (); | |
780 | ||
781 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
782 | /* We used to use alloca here, but the size of what it would try to |
783 | allocate would occasionally cause it to exceed the stack limit and | |
784 | cause a core dump. */ | |
785 | real_known_ptr = xmalloc (num_labels); | |
786 | real_at_ptr | |
32131a9c | 787 | = (int (*)[NUM_ELIMINABLE_REGS]) |
a68d4b75 | 788 | xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); |
32131a9c | 789 | |
a68d4b75 BK |
790 | offsets_known_at = real_known_ptr - get_first_label_num (); |
791 | offsets_at | |
792 | = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); | |
32131a9c RK |
793 | |
794 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
795 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
796 | Do not touch virtual registers. */ | |
797 | ||
798 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
799 | alter_reg (i, -1); | |
800 | ||
32131a9c RK |
801 | /* If we have some registers we think can be eliminated, scan all insns to |
802 | see if there is an insn that sets one of these registers to something | |
803 | other than itself plus a constant. If so, the register cannot be | |
804 | eliminated. Doing this scan here eliminates an extra pass through the | |
805 | main reload loop in the most common case where register elimination | |
806 | cannot be done. */ | |
807 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
808 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
809 | || GET_CODE (insn) == CALL_INSN) | |
84832317 | 810 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 811 | |
18a90182 BS |
812 | maybe_fix_stack_asms (); |
813 | ||
03acd8f8 BS |
814 | insns_need_reload = 0; |
815 | something_needs_elimination = 0; | |
05d10675 | 816 | |
4079cd63 JW |
817 | /* Initialize to -1, which means take the first spill register. */ |
818 | last_spill_reg = -1; | |
819 | ||
32131a9c | 820 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 821 | CLEAR_HARD_REG_SET (used_spill_regs); |
32131a9c RK |
822 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
823 | if (! ep->can_eliminate) | |
e04ca094 | 824 | spill_hard_reg (ep->from, 1); |
9ff3516a RK |
825 | |
826 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
827 | if (frame_pointer_needed) | |
e04ca094 | 828 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 829 | #endif |
e04ca094 | 830 | finish_spills (global); |
7609e720 | 831 | |
f1db3576 JL |
832 | /* From now on, we may need to generate moves differently. We may also |
833 | allow modifications of insns which cause them to not be recognized. | |
834 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
835 | reload_in_progress = 1; |
836 | ||
32131a9c RK |
837 | /* This loop scans the entire function each go-round |
838 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 839 | for (;;) |
32131a9c | 840 | { |
03acd8f8 BS |
841 | int something_changed; |
842 | int did_spill; | |
32131a9c | 843 | |
03acd8f8 | 844 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 845 | |
665792eb | 846 | /* Round size of stack frame to stack_alignment_needed. This must be done |
7657bf2f JW |
847 | here because the stack size may be a part of the offset computation |
848 | for register elimination, and there might have been new stack slots | |
849 | created in the last iteration of this loop. */ | |
665792eb JH |
850 | if (cfun->stack_alignment_needed) |
851 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
7657bf2f JW |
852 | |
853 | starting_frame_size = get_frame_size (); | |
854 | ||
09dd1133 | 855 | set_initial_elim_offsets (); |
1f3b1e1a | 856 | set_initial_label_offsets (); |
03acd8f8 | 857 | |
32131a9c RK |
858 | /* For each pseudo register that has an equivalent location defined, |
859 | try to eliminate any eliminable registers (such as the frame pointer) | |
860 | assuming initial offsets for the replacement register, which | |
861 | is the normal case. | |
862 | ||
863 | If the resulting location is directly addressable, substitute | |
864 | the MEM we just got directly for the old REG. | |
865 | ||
866 | If it is not addressable but is a constant or the sum of a hard reg | |
867 | and constant, it is probably not addressable because the constant is | |
868 | out of range, in that case record the address; we will generate | |
869 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
870 | needed. Similarly if it is a hard register, but one that is not |
871 | valid as an address register. | |
32131a9c RK |
872 | |
873 | If the location is not addressable, but does not have one of the | |
874 | above forms, assign a stack slot. We have to do this to avoid the | |
875 | potential of producing lots of reloads if, e.g., a location involves | |
876 | a pseudo that didn't get a hard register and has an equivalent memory | |
877 | location that also involves a pseudo that didn't get a hard register. | |
878 | ||
879 | Perhaps at some point we will improve reload_when_needed handling | |
880 | so this problem goes away. But that's very hairy. */ | |
881 | ||
882 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
883 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
884 | { | |
1914f5da | 885 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
886 | |
887 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
888 | XEXP (x, 0))) | |
889 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
890 | else if (CONSTANT_P (XEXP (x, 0)) | |
6491dbbb RK |
891 | || (GET_CODE (XEXP (x, 0)) == REG |
892 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
893 | || (GET_CODE (XEXP (x, 0)) == PLUS |
894 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
895 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
896 | < FIRST_PSEUDO_REGISTER) | |
897 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
898 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
899 | else | |
900 | { | |
901 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 902 | changed so we go back and recompute offsets for |
32131a9c RK |
903 | eliminable registers because the allocation of memory |
904 | below might change some offset. reg_equiv_{mem,address} | |
905 | will be set up for this pseudo on the next pass around | |
906 | the loop. */ | |
907 | reg_equiv_memory_loc[i] = 0; | |
908 | reg_equiv_init[i] = 0; | |
909 | alter_reg (i, -1); | |
32131a9c RK |
910 | } |
911 | } | |
a8fdc208 | 912 | |
437a710d BS |
913 | if (caller_save_needed) |
914 | setup_save_areas (); | |
915 | ||
03acd8f8 | 916 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 917 | if (starting_frame_size != get_frame_size ()) |
32131a9c RK |
918 | continue; |
919 | ||
437a710d | 920 | if (caller_save_needed) |
a8efe40d | 921 | { |
437a710d BS |
922 | save_call_clobbered_regs (); |
923 | /* That might have allocated new insn_chain structures. */ | |
924 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
a8efe40d RK |
925 | } |
926 | ||
03acd8f8 BS |
927 | calculate_needs_all_insns (global); |
928 | ||
f5d8c9f4 | 929 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
930 | did_spill = 0; |
931 | ||
932 | something_changed = 0; | |
32131a9c | 933 | |
0dadecf6 RK |
934 | /* If we allocated any new memory locations, make another pass |
935 | since it might have changed elimination offsets. */ | |
936 | if (starting_frame_size != get_frame_size ()) | |
937 | something_changed = 1; | |
938 | ||
09dd1133 BS |
939 | { |
940 | HARD_REG_SET to_spill; | |
941 | CLEAR_HARD_REG_SET (to_spill); | |
942 | update_eliminables (&to_spill); | |
943 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
944 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 945 | { |
e04ca094 | 946 | spill_hard_reg (i, 1); |
03acd8f8 | 947 | did_spill = 1; |
8f5db3c1 JL |
948 | |
949 | /* Regardless of the state of spills, if we previously had | |
950 | a register that we thought we could eliminate, but no can | |
951 | not eliminate, we must run another pass. | |
952 | ||
953 | Consider pseudos which have an entry in reg_equiv_* which | |
954 | reference an eliminable register. We must make another pass | |
955 | to update reg_equiv_* so that we do not substitute in the | |
956 | old value from when we thought the elimination could be | |
957 | performed. */ | |
958 | something_changed = 1; | |
32131a9c | 959 | } |
09dd1133 | 960 | } |
9ff3516a | 961 | |
e04ca094 | 962 | select_reload_regs (); |
e483bf9c BS |
963 | if (failure) |
964 | goto failed; | |
437a710d | 965 | |
e483bf9c | 966 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 967 | something_changed |= finish_spills (global); |
7609e720 | 968 | |
03acd8f8 BS |
969 | if (! something_changed) |
970 | break; | |
971 | ||
972 | if (caller_save_needed) | |
7609e720 | 973 | delete_caller_save_insns (); |
f5d8c9f4 BS |
974 | |
975 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
976 | } |
977 | ||
978 | /* If global-alloc was run, notify it of any register eliminations we have | |
979 | done. */ | |
980 | if (global) | |
981 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
982 | if (ep->can_eliminate) | |
983 | mark_elimination (ep->from, ep->to); | |
984 | ||
32131a9c RK |
985 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
986 | If that insn didn't set the register (i.e., it copied the register to | |
987 | memory), just delete that insn instead of the equivalencing insn plus | |
988 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 989 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
990 | there and that is incorrect. */ |
991 | ||
992 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
993 | { |
994 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
995 | { | |
996 | rtx list; | |
997 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
998 | { | |
999 | rtx equiv_insn = XEXP (list, 0); | |
1000 | if (GET_CODE (equiv_insn) == NOTE) | |
1001 | continue; | |
1002 | if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
1003 | delete_dead_insn (equiv_insn); | |
1004 | else | |
1005 | { | |
1006 | PUT_CODE (equiv_insn, NOTE); | |
1007 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1008 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1009 | } | |
1010 | } | |
1011 | } | |
1012 | } | |
32131a9c RK |
1013 | |
1014 | /* Use the reload registers where necessary | |
1015 | by generating move instructions to move the must-be-register | |
1016 | values into or out of the reload registers. */ | |
1017 | ||
03acd8f8 BS |
1018 | if (insns_need_reload != 0 || something_needs_elimination |
1019 | || something_needs_operands_changed) | |
c47f5ea5 | 1020 | { |
102870fb | 1021 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1022 | |
e04ca094 | 1023 | reload_as_needed (global); |
c47f5ea5 BS |
1024 | |
1025 | if (old_frame_size != get_frame_size ()) | |
1026 | abort (); | |
1027 | ||
1028 | if (num_eliminable) | |
1029 | verify_initial_elim_offsets (); | |
1030 | } | |
32131a9c | 1031 | |
2a1f8b6b | 1032 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1033 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1034 | virtue of being in a pseudo, that pseudo will be marked live |
1035 | and hence the frame pointer will be known to be live via that | |
1036 | pseudo. */ | |
1037 | ||
1038 | if (! frame_pointer_needed) | |
1039 | for (i = 0; i < n_basic_blocks; i++) | |
e881bb1b | 1040 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start, |
8e08106d | 1041 | HARD_FRAME_POINTER_REGNUM); |
2a1f8b6b | 1042 | |
5352b11a RS |
1043 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1044 | and we decide not to abort about it. */ | |
1045 | failed: | |
1046 | ||
f5d8c9f4 | 1047 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1048 | reload_in_progress = 0; |
1049 | ||
32131a9c RK |
1050 | /* Now eliminate all pseudo regs by modifying them into |
1051 | their equivalent memory references. | |
1052 | The REG-rtx's for the pseudos are modified in place, | |
1053 | so all insns that used to refer to them now refer to memory. | |
1054 | ||
1055 | For a reg that has a reg_equiv_address, all those insns | |
1056 | were changed by reloading so that no insns refer to it any longer; | |
1057 | but the DECL_RTL of a variable decl may refer to it, | |
1058 | and if so this causes the debugging info to mention the variable. */ | |
1059 | ||
1060 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1061 | { | |
1062 | rtx addr = 0; | |
ab1fd483 | 1063 | int in_struct = 0; |
6a651371 | 1064 | int is_scalar = 0; |
9ec36da5 JL |
1065 | int is_readonly = 0; |
1066 | ||
1067 | if (reg_equiv_memory_loc[i]) | |
ab1fd483 | 1068 | { |
9ec36da5 | 1069 | in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]); |
c6df88cb | 1070 | is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]); |
9ec36da5 | 1071 | is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]); |
ab1fd483 | 1072 | } |
9ec36da5 JL |
1073 | |
1074 | if (reg_equiv_mem[i]) | |
1075 | addr = XEXP (reg_equiv_mem[i], 0); | |
1076 | ||
32131a9c RK |
1077 | if (reg_equiv_address[i]) |
1078 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1079 | |
32131a9c RK |
1080 | if (addr) |
1081 | { | |
1082 | if (reg_renumber[i] < 0) | |
1083 | { | |
1084 | rtx reg = regno_reg_rtx[i]; | |
ef178af3 | 1085 | PUT_CODE (reg, MEM); |
32131a9c RK |
1086 | XEXP (reg, 0) = addr; |
1087 | REG_USERVAR_P (reg) = 0; | |
9ec36da5 | 1088 | RTX_UNCHANGING_P (reg) = is_readonly; |
ab1fd483 | 1089 | MEM_IN_STRUCT_P (reg) = in_struct; |
c6df88cb | 1090 | MEM_SCALAR_P (reg) = is_scalar; |
41472af8 MM |
1091 | /* We have no alias information about this newly created |
1092 | MEM. */ | |
1093 | MEM_ALIAS_SET (reg) = 0; | |
32131a9c RK |
1094 | } |
1095 | else if (reg_equiv_mem[i]) | |
1096 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1097 | } | |
1098 | } | |
1099 | ||
2ae74651 JL |
1100 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1101 | below will re-recognize each insn and reload may have generated insns | |
1102 | which are only valid during and after reload. */ | |
1103 | reload_completed = 1; | |
1104 | ||
bd695e1e RH |
1105 | /* Make a pass over all the insns and delete all USEs which we inserted |
1106 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
1107 | notes. Delete all CLOBBER insns that don't refer to the return value | |
1108 | and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and | |
1109 | REG_LIBCALL notes since they are no longer useful or accurate. Strip | |
1110 | and regenerate REG_INC notes that may have been moved around. */ | |
32131a9c RK |
1111 | |
1112 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1113 | if (INSN_P (insn)) |
32131a9c | 1114 | { |
6764d250 | 1115 | rtx *pnote; |
32131a9c | 1116 | |
0304f787 JL |
1117 | if ((GET_CODE (PATTERN (insn)) == USE |
1118 | && find_reg_note (insn, REG_EQUAL, NULL_RTX)) | |
bd695e1e RH |
1119 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
1120 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG | |
1121 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
b60a8416 R |
1122 | { |
1123 | PUT_CODE (insn, NOTE); | |
1124 | NOTE_SOURCE_FILE (insn) = 0; | |
1125 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1126 | continue; | |
1127 | } | |
6764d250 BS |
1128 | |
1129 | pnote = ®_NOTES (insn); | |
1130 | while (*pnote != 0) | |
32131a9c | 1131 | { |
6764d250 | 1132 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1133 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1134 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 NC |
1135 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
1136 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) | |
6764d250 BS |
1137 | *pnote = XEXP (*pnote, 1); |
1138 | else | |
1139 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1140 | } |
0304f787 | 1141 | |
2dfa9a87 MH |
1142 | #ifdef AUTO_INC_DEC |
1143 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1144 | #endif | |
1145 | ||
0304f787 JL |
1146 | /* And simplify (subreg (reg)) if it appears as an operand. */ |
1147 | cleanup_subreg_operands (insn); | |
b60a8416 | 1148 | } |
32131a9c | 1149 | |
ab87f8c8 JL |
1150 | /* If we are doing stack checking, give a warning if this function's |
1151 | frame size is larger than we expect. */ | |
1152 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1153 | { | |
1154 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1155 | static int verbose_warned = 0; |
1156 | ||
ab87f8c8 JL |
1157 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1158 | if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) | |
1159 | size += UNITS_PER_WORD; | |
1160 | ||
1161 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1162 | { |
ab87f8c8 JL |
1163 | warning ("frame size too large for reliable stack checking"); |
1164 | if (! verbose_warned) | |
1165 | { | |
1166 | warning ("try reducing the number of local variables"); | |
1167 | verbose_warned = 1; | |
1168 | } | |
1169 | } | |
1170 | } | |
1171 | ||
32131a9c | 1172 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1173 | if (reg_equiv_constant) |
1174 | free (reg_equiv_constant); | |
32131a9c | 1175 | reg_equiv_constant = 0; |
58d9f9d9 JL |
1176 | if (reg_equiv_memory_loc) |
1177 | free (reg_equiv_memory_loc); | |
32131a9c | 1178 | reg_equiv_memory_loc = 0; |
5352b11a | 1179 | |
a68d4b75 BK |
1180 | if (real_known_ptr) |
1181 | free (real_known_ptr); | |
1182 | if (real_at_ptr) | |
1183 | free (real_at_ptr); | |
1184 | ||
56a65848 DB |
1185 | free (reg_equiv_mem); |
1186 | free (reg_equiv_init); | |
1187 | free (reg_equiv_address); | |
1188 | free (reg_max_ref_width); | |
03acd8f8 BS |
1189 | free (reg_old_renumber); |
1190 | free (pseudo_previous_regs); | |
1191 | free (pseudo_forbidden_regs); | |
56a65848 | 1192 | |
8b4f9969 JW |
1193 | CLEAR_HARD_REG_SET (used_spill_regs); |
1194 | for (i = 0; i < n_spills; i++) | |
1195 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1196 | ||
7609e720 BS |
1197 | /* Free all the insn_chain structures at once. */ |
1198 | obstack_free (&reload_obstack, reload_startobj); | |
1199 | unused_insn_chains = 0; | |
1200 | ||
5352b11a | 1201 | return failure; |
32131a9c | 1202 | } |
1e5bd841 | 1203 | |
18a90182 BS |
1204 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1205 | write incorrect clobbers in asm statements. These clobbers must not | |
1206 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1207 | fatal_insn later. We clear the corresponding regnos in the live | |
1208 | register sets to avoid this. | |
1209 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1210 | |
18a90182 BS |
1211 | static void |
1212 | maybe_fix_stack_asms () | |
1213 | { | |
1214 | #ifdef STACK_REGS | |
392dccb7 | 1215 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1216 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1217 | struct insn_chain *chain; | |
1218 | ||
1219 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1220 | { | |
1221 | int i, noperands; | |
1222 | HARD_REG_SET clobbered, allowed; | |
1223 | rtx pat; | |
1224 | ||
2c3c49de | 1225 | if (! INSN_P (chain->insn) |
18a90182 BS |
1226 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1227 | continue; | |
1228 | pat = PATTERN (chain->insn); | |
1229 | if (GET_CODE (pat) != PARALLEL) | |
1230 | continue; | |
1231 | ||
1232 | CLEAR_HARD_REG_SET (clobbered); | |
1233 | CLEAR_HARD_REG_SET (allowed); | |
1234 | ||
1235 | /* First, make a mask of all stack regs that are clobbered. */ | |
1236 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1237 | { | |
1238 | rtx t = XVECEXP (pat, 0, i); | |
1239 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1240 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1241 | } | |
1242 | ||
1243 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1244 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
18a90182 BS |
1245 | constraints, operand_mode); |
1246 | ||
1247 | /* For every operand, see what registers are allowed. */ | |
1248 | for (i = 0; i < noperands; i++) | |
1249 | { | |
6b9c6f4f | 1250 | const char *p = constraints[i]; |
18a90182 BS |
1251 | /* For every alternative, we compute the class of registers allowed |
1252 | for reloading in CLS, and merge its contents into the reg set | |
1253 | ALLOWED. */ | |
1254 | int cls = (int) NO_REGS; | |
1255 | ||
1256 | for (;;) | |
1257 | { | |
1258 | char c = *p++; | |
1259 | ||
1260 | if (c == '\0' || c == ',' || c == '#') | |
1261 | { | |
1262 | /* End of one alternative - mark the regs in the current | |
1263 | class, and reset the class. */ | |
1264 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1265 | cls = NO_REGS; | |
1266 | if (c == '#') | |
1267 | do { | |
1268 | c = *p++; | |
1269 | } while (c != '\0' && c != ','); | |
1270 | if (c == '\0') | |
1271 | break; | |
1272 | continue; | |
1273 | } | |
1274 | ||
1275 | switch (c) | |
1276 | { | |
1277 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1278 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1279 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1280 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1281 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1282 | case 'P': | |
18a90182 BS |
1283 | break; |
1284 | ||
1285 | case 'p': | |
1286 | cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS]; | |
1287 | break; | |
1288 | ||
1289 | case 'g': | |
1290 | case 'r': | |
1291 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1292 | break; | |
1293 | ||
1294 | default: | |
1295 | cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)]; | |
05d10675 | 1296 | |
18a90182 BS |
1297 | } |
1298 | } | |
1299 | } | |
1300 | /* Those of the registers which are clobbered, but allowed by the | |
1301 | constraints, must be usable as reload registers. So clear them | |
1302 | out of the life information. */ | |
1303 | AND_HARD_REG_SET (allowed, clobbered); | |
1304 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1305 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1306 | { | |
239a0f5b BS |
1307 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1308 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1309 | } |
1310 | } | |
1311 | ||
1312 | #endif | |
1313 | } | |
03acd8f8 | 1314 | \f |
f5d8c9f4 BS |
1315 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1316 | of CHAIN. */ | |
1317 | static void | |
1318 | copy_reloads (chain) | |
1319 | struct insn_chain *chain; | |
1320 | { | |
1321 | chain->n_reloads = n_reloads; | |
1322 | chain->rld | |
1323 | = (struct reload *) obstack_alloc (&reload_obstack, | |
1324 | n_reloads * sizeof (struct reload)); | |
1325 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); | |
1326 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
1327 | } | |
1328 | ||
03acd8f8 BS |
1329 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1330 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1331 | set something_needs_elimination as appropriate. */ | |
1332 | static void | |
7609e720 | 1333 | calculate_needs_all_insns (global) |
1e5bd841 BS |
1334 | int global; |
1335 | { | |
7609e720 | 1336 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1337 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1338 | |
03acd8f8 BS |
1339 | something_needs_elimination = 0; |
1340 | ||
f5d8c9f4 | 1341 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
462561b7 | 1342 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1343 | { |
67e61fe7 | 1344 | rtx insn = chain->insn; |
03acd8f8 | 1345 | |
462561b7 JJ |
1346 | next = chain->next; |
1347 | ||
f5d8c9f4 BS |
1348 | /* Clear out the shortcuts. */ |
1349 | chain->n_reloads = 0; | |
67e61fe7 BS |
1350 | chain->need_elim = 0; |
1351 | chain->need_reload = 0; | |
1352 | chain->need_operand_change = 0; | |
1e5bd841 | 1353 | |
03acd8f8 BS |
1354 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1355 | include REG_LABEL), we need to see what effects this has on the | |
1356 | known offsets at labels. */ | |
1e5bd841 BS |
1357 | |
1358 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
2c3c49de | 1359 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1360 | set_label_offsets (insn, insn, 0); |
1361 | ||
2c3c49de | 1362 | if (INSN_P (insn)) |
1e5bd841 BS |
1363 | { |
1364 | rtx old_body = PATTERN (insn); | |
1365 | int old_code = INSN_CODE (insn); | |
1366 | rtx old_notes = REG_NOTES (insn); | |
1367 | int did_elimination = 0; | |
cb2afeb3 | 1368 | int operands_changed = 0; |
2b49ee39 R |
1369 | rtx set = single_set (insn); |
1370 | ||
1371 | /* Skip insns that only set an equivalence. */ | |
1372 | if (set && GET_CODE (SET_DEST (set)) == REG | |
1373 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1374 | && reg_equiv_constant[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1375 | continue; |
1e5bd841 | 1376 | |
1e5bd841 | 1377 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1378 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1379 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1380 | ||
1381 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1382 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1383 | global, spill_reg_order); | |
1384 | ||
1385 | /* If a no-op set needs more than one reload, this is likely | |
1386 | to be something that needs input address reloads. We | |
1387 | can't get rid of this cleanly later, and it is of no use | |
1388 | anyway, so discard it now. | |
1389 | We only do this when expensive_optimizations is enabled, | |
1390 | since this complements reload inheritance / output | |
1391 | reload deletion, and it can make debugging harder. */ | |
1392 | if (flag_expensive_optimizations && n_reloads > 1) | |
1393 | { | |
1394 | rtx set = single_set (insn); | |
1395 | if (set | |
1396 | && SET_SRC (set) == SET_DEST (set) | |
1397 | && GET_CODE (SET_SRC (set)) == REG | |
1398 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1399 | { | |
1400 | PUT_CODE (insn, NOTE); | |
1401 | NOTE_SOURCE_FILE (insn) = 0; | |
1402 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
462561b7 JJ |
1403 | /* Delete it from the reload chain */ |
1404 | if (chain->prev) | |
1405 | chain->prev->next = next; | |
1406 | else | |
1407 | reload_insn_chain = next; | |
1408 | if (next) | |
1409 | next->prev = chain->prev; | |
1410 | chain->next = unused_insn_chains; | |
1411 | unused_insn_chains = chain; | |
cb2afeb3 R |
1412 | continue; |
1413 | } | |
1414 | } | |
1415 | if (num_eliminable) | |
1416 | update_eliminable_offsets (); | |
1e5bd841 BS |
1417 | |
1418 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1419 | register eliminations. */ |
1420 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1421 | chain->need_reload = n_reloads > 0; |
1422 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1423 | |
1424 | /* Discard any register replacements done. */ | |
1425 | if (did_elimination) | |
1426 | { | |
f5d8c9f4 | 1427 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1428 | PATTERN (insn) = old_body; |
1429 | INSN_CODE (insn) = old_code; | |
1430 | REG_NOTES (insn) = old_notes; | |
1431 | something_needs_elimination = 1; | |
1432 | } | |
1433 | ||
cb2afeb3 R |
1434 | something_needs_operands_changed |= operands_changed; |
1435 | ||
437a710d | 1436 | if (n_reloads != 0) |
7609e720 | 1437 | { |
f5d8c9f4 | 1438 | copy_reloads (chain); |
7609e720 BS |
1439 | *pprev_reload = chain; |
1440 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1441 | } |
1e5bd841 | 1442 | } |
1e5bd841 | 1443 | } |
7609e720 | 1444 | *pprev_reload = 0; |
1e5bd841 | 1445 | } |
f5d8c9f4 BS |
1446 | \f |
1447 | /* Comparison function for qsort to decide which of two reloads | |
1448 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1449 | |
f5d8c9f4 BS |
1450 | static int |
1451 | reload_reg_class_lower (r1p, r2p) | |
1452 | const PTR r1p; | |
1453 | const PTR r2p; | |
1e5bd841 | 1454 | { |
1d7254c5 | 1455 | register int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
f5d8c9f4 | 1456 | register int t; |
1e5bd841 | 1457 | |
f5d8c9f4 BS |
1458 | /* Consider required reloads before optional ones. */ |
1459 | t = rld[r1].optional - rld[r2].optional; | |
1460 | if (t != 0) | |
1461 | return t; | |
1e5bd841 | 1462 | |
f5d8c9f4 BS |
1463 | /* Count all solitary classes before non-solitary ones. */ |
1464 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1465 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1466 | if (t != 0) | |
1467 | return t; | |
1e5bd841 | 1468 | |
f5d8c9f4 BS |
1469 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1470 | t = rld[r2].nregs - rld[r1].nregs; | |
1471 | if (t != 0) | |
1472 | return t; | |
1e5bd841 | 1473 | |
f5d8c9f4 BS |
1474 | /* Consider reloads in order of increasing reg-class number. */ |
1475 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1476 | if (t != 0) | |
1477 | return t; | |
1e5bd841 | 1478 | |
f5d8c9f4 BS |
1479 | /* If reloads are equally urgent, sort by reload number, |
1480 | so that the results of qsort leave nothing to chance. */ | |
1481 | return r1 - r2; | |
1482 | } | |
1483 | \f | |
1484 | /* The cost of spilling each hard reg. */ | |
1485 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1486 | |
f5d8c9f4 BS |
1487 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1488 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1489 | only the first hard reg for a multi-reg pseudo. */ | |
1490 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1491 | |
f5d8c9f4 | 1492 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1493 | |
f5d8c9f4 BS |
1494 | static void |
1495 | count_pseudo (reg) | |
1496 | int reg; | |
1497 | { | |
1498 | int n_refs = REG_N_REFS (reg); | |
1499 | int r = reg_renumber[reg]; | |
1500 | int nregs; | |
1e5bd841 | 1501 | |
f5d8c9f4 BS |
1502 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1503 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1504 | return; | |
1e5bd841 | 1505 | |
f5d8c9f4 | 1506 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1507 | |
f5d8c9f4 BS |
1508 | if (r < 0) |
1509 | abort (); | |
1d7254c5 | 1510 | |
f5d8c9f4 | 1511 | spill_add_cost[r] += n_refs; |
1e5bd841 | 1512 | |
f5d8c9f4 BS |
1513 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); |
1514 | while (nregs-- > 0) | |
1515 | spill_cost[r + nregs] += n_refs; | |
1516 | } | |
1e5bd841 | 1517 | |
f5d8c9f4 BS |
1518 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1519 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1520 | |
f5d8c9f4 BS |
1521 | static void |
1522 | order_regs_for_reload (chain) | |
1523 | struct insn_chain *chain; | |
1524 | { | |
fbd40359 | 1525 | int i; |
efc9bd41 RK |
1526 | HARD_REG_SET used_by_pseudos; |
1527 | HARD_REG_SET used_by_pseudos2; | |
1e5bd841 | 1528 | |
efc9bd41 | 1529 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1530 | |
f5d8c9f4 BS |
1531 | memset (spill_cost, 0, sizeof spill_cost); |
1532 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1533 | |
f5d8c9f4 | 1534 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1535 | and then order them by decreasing use. First exclude hard registers |
1536 | that are live in or across this insn. */ | |
1537 | ||
1538 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1539 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1540 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1541 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1542 | |
f5d8c9f4 BS |
1543 | /* Now find out which pseudos are allocated to it, and update |
1544 | hard_reg_n_uses. */ | |
1545 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1546 | |
f5d8c9f4 | 1547 | EXECUTE_IF_SET_IN_REG_SET |
fbd40359 | 1548 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1549 | { |
fbd40359 | 1550 | count_pseudo (i); |
f5d8c9f4 BS |
1551 | }); |
1552 | EXECUTE_IF_SET_IN_REG_SET | |
fbd40359 | 1553 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1554 | { |
fbd40359 | 1555 | count_pseudo (i); |
f5d8c9f4 BS |
1556 | }); |
1557 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1558 | } |
03acd8f8 | 1559 | \f |
f5d8c9f4 BS |
1560 | /* Vector of reload-numbers showing the order in which the reloads should |
1561 | be processed. */ | |
1562 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1563 | |
f5d8c9f4 BS |
1564 | /* This is used to keep track of the spill regs used in one insn. */ |
1565 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1566 | |
f5d8c9f4 BS |
1567 | /* We decided to spill hard register SPILLED, which has a size of |
1568 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1569 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1570 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1571 | |
03acd8f8 | 1572 | static void |
f5d8c9f4 BS |
1573 | count_spilled_pseudo (spilled, spilled_nregs, reg) |
1574 | int spilled, spilled_nregs, reg; | |
1e5bd841 | 1575 | { |
f5d8c9f4 BS |
1576 | int r = reg_renumber[reg]; |
1577 | int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); | |
1e5bd841 | 1578 | |
f5d8c9f4 BS |
1579 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1580 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1581 | return; | |
1e5bd841 | 1582 | |
f5d8c9f4 | 1583 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1584 | |
f5d8c9f4 BS |
1585 | spill_add_cost[r] -= REG_N_REFS (reg); |
1586 | while (nregs-- > 0) | |
1587 | spill_cost[r + nregs] -= REG_N_REFS (reg); | |
1e5bd841 BS |
1588 | } |
1589 | ||
f5d8c9f4 | 1590 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1591 | |
f5d8c9f4 | 1592 | static int |
e04ca094 | 1593 | find_reg (chain, order) |
03acd8f8 | 1594 | struct insn_chain *chain; |
f5d8c9f4 | 1595 | int order; |
1e5bd841 | 1596 | { |
f5d8c9f4 BS |
1597 | int rnum = reload_order[order]; |
1598 | struct reload *rl = rld + rnum; | |
1599 | int best_cost = INT_MAX; | |
1600 | int best_reg = -1; | |
770ae6cc RK |
1601 | unsigned int i, j; |
1602 | int k; | |
f5d8c9f4 BS |
1603 | HARD_REG_SET not_usable; |
1604 | HARD_REG_SET used_by_other_reload; | |
1e5bd841 | 1605 | |
f5d8c9f4 BS |
1606 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1607 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1608 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1609 | ||
1610 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1611 | for (k = 0; k < order; k++) |
1e5bd841 | 1612 | { |
770ae6cc RK |
1613 | int other = reload_order[k]; |
1614 | ||
f5d8c9f4 BS |
1615 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1616 | for (j = 0; j < rld[other].nregs; j++) | |
1617 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1618 | } | |
1e5bd841 | 1619 | |
f5d8c9f4 BS |
1620 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1621 | { | |
770ae6cc RK |
1622 | unsigned int regno = i; |
1623 | ||
f5d8c9f4 BS |
1624 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1625 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1626 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1627 | { |
f5d8c9f4 BS |
1628 | int this_cost = spill_cost[regno]; |
1629 | int ok = 1; | |
770ae6cc | 1630 | unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); |
1e5bd841 | 1631 | |
f5d8c9f4 BS |
1632 | for (j = 1; j < this_nregs; j++) |
1633 | { | |
1634 | this_cost += spill_add_cost[regno + j]; | |
1635 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1636 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1637 | ok = 0; | |
1638 | } | |
1639 | if (! ok) | |
1640 | continue; | |
1641 | if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) | |
1642 | this_cost--; | |
1643 | if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) | |
1644 | this_cost--; | |
1645 | if (this_cost < best_cost | |
1646 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1647 | use REG_ALLOC_ORDER if it is defined. */ | |
1648 | || (this_cost == best_cost | |
1649 | #ifdef REG_ALLOC_ORDER | |
1650 | && (inv_reg_alloc_order[regno] | |
1651 | < inv_reg_alloc_order[best_reg]) | |
1652 | #else | |
1653 | && call_used_regs[regno] | |
1654 | && ! call_used_regs[best_reg] | |
1655 | #endif | |
1656 | )) | |
1657 | { | |
1658 | best_reg = regno; | |
1659 | best_cost = this_cost; | |
1e5bd841 BS |
1660 | } |
1661 | } | |
1662 | } | |
f5d8c9f4 BS |
1663 | if (best_reg == -1) |
1664 | return 0; | |
770ae6cc | 1665 | |
e04ca094 JL |
1666 | if (rtl_dump_file) |
1667 | fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1668 | |
f5d8c9f4 BS |
1669 | rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); |
1670 | rl->regno = best_reg; | |
1e5bd841 | 1671 | |
f5d8c9f4 | 1672 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1673 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1674 | { |
1675 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1676 | }); | |
770ae6cc | 1677 | |
f5d8c9f4 | 1678 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1679 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1680 | { |
1681 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1682 | }); | |
03acd8f8 | 1683 | |
f5d8c9f4 BS |
1684 | for (i = 0; i < rl->nregs; i++) |
1685 | { | |
1686 | if (spill_cost[best_reg + i] != 0 | |
1687 | || spill_add_cost[best_reg + i] != 0) | |
1688 | abort (); | |
1689 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); | |
1690 | } | |
1691 | return 1; | |
03acd8f8 BS |
1692 | } |
1693 | ||
1694 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1695 | is given by CHAIN. | |
1e5bd841 BS |
1696 | Do it by ascending class number, since otherwise a reg |
1697 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1698 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1699 | |
03acd8f8 | 1700 | static void |
e04ca094 | 1701 | find_reload_regs (chain) |
03acd8f8 | 1702 | struct insn_chain *chain; |
1e5bd841 | 1703 | { |
f5d8c9f4 | 1704 | int i; |
1e5bd841 | 1705 | |
f5d8c9f4 BS |
1706 | /* In order to be certain of getting the registers we need, |
1707 | we must sort the reloads into order of increasing register class. | |
1708 | Then our grabbing of reload registers will parallel the process | |
1709 | that provided the reload registers. */ | |
1710 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1711 | { |
f5d8c9f4 BS |
1712 | /* Show whether this reload already has a hard reg. */ |
1713 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1714 | { |
f5d8c9f4 BS |
1715 | int regno = REGNO (chain->rld[i].reg_rtx); |
1716 | chain->rld[i].regno = regno; | |
770ae6cc RK |
1717 | chain->rld[i].nregs |
1718 | = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); | |
1e5bd841 | 1719 | } |
f5d8c9f4 BS |
1720 | else |
1721 | chain->rld[i].regno = -1; | |
1722 | reload_order[i] = i; | |
1723 | } | |
1e5bd841 | 1724 | |
f5d8c9f4 BS |
1725 | n_reloads = chain->n_reloads; |
1726 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1727 | |
f5d8c9f4 | 1728 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1729 | |
e04ca094 JL |
1730 | if (rtl_dump_file) |
1731 | fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1732 | |
f5d8c9f4 | 1733 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1734 | |
f5d8c9f4 | 1735 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1736 | |
f5d8c9f4 | 1737 | order_regs_for_reload (chain); |
1e5bd841 | 1738 | |
f5d8c9f4 BS |
1739 | for (i = 0; i < n_reloads; i++) |
1740 | { | |
1741 | int r = reload_order[i]; | |
1e5bd841 | 1742 | |
f5d8c9f4 BS |
1743 | /* Ignore reloads that got marked inoperative. */ |
1744 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1745 | && ! rld[r].optional | |
1746 | && rld[r].regno == -1) | |
e04ca094 | 1747 | if (! find_reg (chain, i)) |
f5d8c9f4 | 1748 | { |
ecf3151a | 1749 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1750 | failure = 1; |
03acd8f8 | 1751 | return; |
f5d8c9f4 | 1752 | } |
1e5bd841 | 1753 | } |
05d10675 | 1754 | |
f5d8c9f4 BS |
1755 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1756 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1757 | |
f5d8c9f4 | 1758 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1759 | } |
1760 | ||
f5d8c9f4 | 1761 | static void |
e04ca094 | 1762 | select_reload_regs () |
09dd1133 | 1763 | { |
f5d8c9f4 | 1764 | struct insn_chain *chain; |
09dd1133 | 1765 | |
f5d8c9f4 BS |
1766 | /* Try to satisfy the needs for each insn. */ |
1767 | for (chain = insns_need_reload; chain != 0; | |
1768 | chain = chain->next_need_reload) | |
e04ca094 | 1769 | find_reload_regs (chain); |
09dd1133 | 1770 | } |
32131a9c | 1771 | \f |
437a710d BS |
1772 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1773 | this iteration. */ | |
1774 | static void | |
7609e720 | 1775 | delete_caller_save_insns () |
437a710d | 1776 | { |
7609e720 | 1777 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1778 | |
7609e720 | 1779 | while (c != 0) |
437a710d | 1780 | { |
7609e720 | 1781 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1782 | { |
7609e720 BS |
1783 | struct insn_chain *next = c->next; |
1784 | rtx insn = c->insn; | |
1785 | ||
3b413743 RH |
1786 | if (insn == BLOCK_HEAD (c->block)) |
1787 | BLOCK_HEAD (c->block) = NEXT_INSN (insn); | |
1788 | if (insn == BLOCK_END (c->block)) | |
1789 | BLOCK_END (c->block) = PREV_INSN (insn); | |
7609e720 BS |
1790 | if (c == reload_insn_chain) |
1791 | reload_insn_chain = next; | |
1792 | ||
1793 | if (NEXT_INSN (insn) != 0) | |
1794 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
1795 | if (PREV_INSN (insn) != 0) | |
1796 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
1797 | ||
1798 | if (next) | |
1799 | next->prev = c->prev; | |
1800 | if (c->prev) | |
1801 | c->prev->next = next; | |
1802 | c->next = unused_insn_chains; | |
1803 | unused_insn_chains = c; | |
1804 | c = next; | |
437a710d | 1805 | } |
7609e720 BS |
1806 | if (c != 0) |
1807 | c = c->next; | |
437a710d BS |
1808 | } |
1809 | } | |
1810 | \f | |
5352b11a RS |
1811 | /* Handle the failure to find a register to spill. |
1812 | INSN should be one of the insns which needed this particular spill reg. */ | |
1813 | ||
1814 | static void | |
ecf3151a | 1815 | spill_failure (insn, class) |
5352b11a | 1816 | rtx insn; |
ecf3151a | 1817 | enum reg_class class; |
5352b11a | 1818 | { |
ecf3151a | 1819 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
5352b11a | 1820 | if (asm_noperands (PATTERN (insn)) >= 0) |
ecf3151a BS |
1821 | error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.", |
1822 | reg_class_names[class]); | |
5352b11a | 1823 | else |
ecf3151a BS |
1824 | { |
1825 | error ("Unable to find a register to spill in class `%s'.", | |
1826 | reg_class_names[class]); | |
1827 | fatal_insn ("This is the insn:", insn); | |
1828 | } | |
5352b11a | 1829 | } |
32131a9c RK |
1830 | \f |
1831 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
1832 | data that is dead in INSN. */ | |
1833 | ||
1834 | static void | |
1835 | delete_dead_insn (insn) | |
1836 | rtx insn; | |
1837 | { | |
1838 | rtx prev = prev_real_insn (insn); | |
1839 | rtx prev_dest; | |
1840 | ||
1841 | /* If the previous insn sets a register that dies in our insn, delete it | |
1842 | too. */ | |
1843 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
1844 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
1845 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
b294ca38 R |
1846 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
1847 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
1848 | delete_dead_insn (prev); |
1849 | ||
1850 | PUT_CODE (insn, NOTE); | |
1851 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1852 | NOTE_SOURCE_FILE (insn) = 0; | |
1853 | } | |
1854 | ||
1855 | /* Modify the home of pseudo-reg I. | |
1856 | The new home is present in reg_renumber[I]. | |
1857 | ||
1858 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1859 | or it may be -1, meaning there is none or it is not relevant. | |
1860 | This is used so that all pseudos spilled from a given hard reg | |
1861 | can share one stack slot. */ | |
1862 | ||
1863 | static void | |
1864 | alter_reg (i, from_reg) | |
1865 | register int i; | |
1866 | int from_reg; | |
1867 | { | |
1868 | /* When outputting an inline function, this can happen | |
1869 | for a reg that isn't actually used. */ | |
1870 | if (regno_reg_rtx[i] == 0) | |
1871 | return; | |
1872 | ||
1873 | /* If the reg got changed to a MEM at rtl-generation time, | |
1874 | ignore it. */ | |
1875 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1876 | return; | |
1877 | ||
1878 | /* Modify the reg-rtx to contain the new hard reg | |
1879 | number or else to contain its pseudo reg number. */ | |
1880 | REGNO (regno_reg_rtx[i]) | |
1881 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1882 | ||
1883 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1884 | allocate a stack slot for it. */ | |
1885 | ||
1886 | if (reg_renumber[i] < 0 | |
b1f21e0a | 1887 | && REG_N_REFS (i) > 0 |
32131a9c RK |
1888 | && reg_equiv_constant[i] == 0 |
1889 | && reg_equiv_memory_loc[i] == 0) | |
1890 | { | |
1891 | register rtx x; | |
770ae6cc RK |
1892 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
1893 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
32131a9c RK |
1894 | int adjust = 0; |
1895 | ||
1896 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1897 | and a total size which provides room for paradoxical subregs | |
1898 | which refer to the pseudo reg in wider modes. | |
1899 | ||
1900 | We can use a slot already allocated if it provides both | |
1901 | enough inherent space and enough total space. | |
1902 | Otherwise, we allocate a new slot, making sure that it has no less | |
1903 | inherent space, and no less total space, then the previous slot. */ | |
1904 | if (from_reg == -1) | |
1905 | { | |
1906 | /* No known place to spill from => no slot to reuse. */ | |
cabcf079 ILT |
1907 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, |
1908 | inherent_size == total_size ? 0 : -1); | |
f76b9db2 | 1909 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
1910 | /* Cancel the big-endian correction done in assign_stack_local. |
1911 | Get the address of the beginning of the slot. | |
1912 | This is so we can do a big-endian correction unconditionally | |
1913 | below. */ | |
1914 | adjust = inherent_size - total_size; | |
1915 | ||
1916 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
3bdf5ad1 RK |
1917 | |
1918 | /* Nothing can alias this slot except this pseudo. */ | |
1919 | MEM_ALIAS_SET (x) = new_alias_set (); | |
32131a9c | 1920 | } |
3bdf5ad1 | 1921 | |
32131a9c RK |
1922 | /* Reuse a stack slot if possible. */ |
1923 | else if (spill_stack_slot[from_reg] != 0 | |
1924 | && spill_stack_slot_width[from_reg] >= total_size | |
1925 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1926 | >= inherent_size)) | |
1927 | x = spill_stack_slot[from_reg]; | |
3bdf5ad1 | 1928 | |
32131a9c RK |
1929 | /* Allocate a bigger slot. */ |
1930 | else | |
1931 | { | |
1932 | /* Compute maximum size needed, both for inherent size | |
1933 | and for total size. */ | |
1934 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
4f2d3674 | 1935 | rtx stack_slot; |
3bdf5ad1 | 1936 | |
32131a9c RK |
1937 | if (spill_stack_slot[from_reg]) |
1938 | { | |
1939 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1940 | > inherent_size) | |
1941 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
1942 | if (spill_stack_slot_width[from_reg] > total_size) | |
1943 | total_size = spill_stack_slot_width[from_reg]; | |
1944 | } | |
3bdf5ad1 | 1945 | |
32131a9c | 1946 | /* Make a slot with that size. */ |
cabcf079 ILT |
1947 | x = assign_stack_local (mode, total_size, |
1948 | inherent_size == total_size ? 0 : -1); | |
4f2d3674 | 1949 | stack_slot = x; |
3bdf5ad1 RK |
1950 | |
1951 | /* All pseudos mapped to this slot can alias each other. */ | |
1952 | if (spill_stack_slot[from_reg]) | |
1953 | MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]); | |
1954 | else | |
1955 | MEM_ALIAS_SET (x) = new_alias_set (); | |
1956 | ||
f76b9db2 ILT |
1957 | if (BYTES_BIG_ENDIAN) |
1958 | { | |
1959 | /* Cancel the big-endian correction done in assign_stack_local. | |
1960 | Get the address of the beginning of the slot. | |
1961 | This is so we can do a big-endian correction unconditionally | |
1962 | below. */ | |
1963 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 1964 | if (adjust) |
38a448ca RH |
1965 | stack_slot = gen_rtx_MEM (mode_for_size (total_size |
1966 | * BITS_PER_UNIT, | |
1967 | MODE_INT, 1), | |
05d10675 | 1968 | plus_constant (XEXP (x, 0), adjust)); |
f76b9db2 | 1969 | } |
3bdf5ad1 | 1970 | |
4f2d3674 | 1971 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
1972 | spill_stack_slot_width[from_reg] = total_size; |
1973 | } | |
1974 | ||
32131a9c RK |
1975 | /* On a big endian machine, the "address" of the slot |
1976 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 1977 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 1978 | adjust += (total_size - inherent_size); |
32131a9c RK |
1979 | |
1980 | /* If we have any adjustment to make, or if the stack slot is the | |
1981 | wrong mode, make a new stack slot. */ | |
1982 | if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) | |
1983 | { | |
3bdf5ad1 RK |
1984 | rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]), |
1985 | plus_constant (XEXP (x, 0), adjust)); | |
9ec36da5 | 1986 | |
3bdf5ad1 RK |
1987 | MEM_COPY_ATTRIBUTES (new, x); |
1988 | x = new; | |
32131a9c RK |
1989 | } |
1990 | ||
1991 | /* Save the stack slot for later. */ | |
1992 | reg_equiv_memory_loc[i] = x; | |
1993 | } | |
1994 | } | |
1995 | ||
1996 | /* Mark the slots in regs_ever_live for the hard regs | |
1997 | used by pseudo-reg number REGNO. */ | |
1998 | ||
1999 | void | |
2000 | mark_home_live (regno) | |
2001 | int regno; | |
2002 | { | |
2003 | register int i, lim; | |
770ae6cc | 2004 | |
32131a9c RK |
2005 | i = reg_renumber[regno]; |
2006 | if (i < 0) | |
2007 | return; | |
2008 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
2009 | while (i < lim) | |
2010 | regs_ever_live[i++] = 1; | |
2011 | } | |
2012 | \f | |
2013 | /* This function handles the tracking of elimination offsets around branches. | |
2014 | ||
2015 | X is a piece of RTL being scanned. | |
2016 | ||
2017 | INSN is the insn that it came from, if any. | |
2018 | ||
2019 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
2020 | offset and zero if we are setting the offset of the label to be the | |
2021 | current offset. */ | |
2022 | ||
2023 | static void | |
2024 | set_label_offsets (x, insn, initial_p) | |
2025 | rtx x; | |
2026 | rtx insn; | |
2027 | int initial_p; | |
2028 | { | |
2029 | enum rtx_code code = GET_CODE (x); | |
2030 | rtx tem; | |
e51712db | 2031 | unsigned int i; |
32131a9c RK |
2032 | struct elim_table *p; |
2033 | ||
2034 | switch (code) | |
2035 | { | |
2036 | case LABEL_REF: | |
8be386d9 RS |
2037 | if (LABEL_REF_NONLOCAL_P (x)) |
2038 | return; | |
2039 | ||
32131a9c RK |
2040 | x = XEXP (x, 0); |
2041 | ||
0f41302f | 2042 | /* ... fall through ... */ |
32131a9c RK |
2043 | |
2044 | case CODE_LABEL: | |
2045 | /* If we know nothing about this label, set the desired offsets. Note | |
2046 | that this sets the offset at a label to be the offset before a label | |
2047 | if we don't know anything about the label. This is not correct for | |
2048 | the label after a BARRIER, but is the best guess we can make. If | |
2049 | we guessed wrong, we will suppress an elimination that might have | |
2050 | been possible had we been able to guess correctly. */ | |
2051 | ||
2052 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2053 | { | |
2054 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2055 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2056 | = (initial_p ? reg_eliminate[i].initial_offset | |
2057 | : reg_eliminate[i].offset); | |
2058 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2059 | } | |
2060 | ||
2061 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2062 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2063 | that label. */ |
2064 | ||
2065 | else if (x == insn | |
2066 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2067 | && GET_CODE (tem) == BARRIER) | |
1f3b1e1a | 2068 | set_offsets_for_label (insn); |
32131a9c RK |
2069 | else |
2070 | /* If neither of the above cases is true, compare each offset | |
2071 | with those previously recorded and suppress any eliminations | |
2072 | where the offsets disagree. */ | |
a8fdc208 | 2073 | |
32131a9c RK |
2074 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2075 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2076 | != (initial_p ? reg_eliminate[i].initial_offset | |
2077 | : reg_eliminate[i].offset)) | |
2078 | reg_eliminate[i].can_eliminate = 0; | |
2079 | ||
2080 | return; | |
2081 | ||
2082 | case JUMP_INSN: | |
2083 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2084 | ||
0f41302f | 2085 | /* ... fall through ... */ |
32131a9c RK |
2086 | |
2087 | case INSN: | |
2088 | case CALL_INSN: | |
2089 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2090 | and hence must have all eliminations at their initial offsets. */ | |
2091 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2092 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2093 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2094 | return; | |
2095 | ||
0c0ba09c | 2096 | case PARALLEL: |
32131a9c RK |
2097 | case ADDR_VEC: |
2098 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2099 | /* Each of the labels in the parallel or address vector must be |
2100 | at their initial offsets. We want the first field for PARALLEL | |
2101 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2102 | |
e51712db | 2103 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2104 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2105 | insn, initial_p); | |
2106 | return; | |
2107 | ||
2108 | case SET: | |
2109 | /* We only care about setting PC. If the source is not RETURN, | |
2110 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2111 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2112 | isn't one of those possibilities. For branches to a label, | |
2113 | call ourselves recursively. | |
2114 | ||
2115 | Note that this can disable elimination unnecessarily when we have | |
2116 | a non-local goto since it will look like a non-constant jump to | |
2117 | someplace in the current function. This isn't a significant | |
2118 | problem since such jumps will normally be when all elimination | |
2119 | pairs are back to their initial offsets. */ | |
2120 | ||
2121 | if (SET_DEST (x) != pc_rtx) | |
2122 | return; | |
2123 | ||
2124 | switch (GET_CODE (SET_SRC (x))) | |
2125 | { | |
2126 | case PC: | |
2127 | case RETURN: | |
2128 | return; | |
2129 | ||
2130 | case LABEL_REF: | |
2131 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2132 | return; | |
2133 | ||
2134 | case IF_THEN_ELSE: | |
2135 | tem = XEXP (SET_SRC (x), 1); | |
2136 | if (GET_CODE (tem) == LABEL_REF) | |
2137 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2138 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2139 | break; | |
2140 | ||
2141 | tem = XEXP (SET_SRC (x), 2); | |
2142 | if (GET_CODE (tem) == LABEL_REF) | |
2143 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2144 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2145 | break; | |
2146 | return; | |
e9a25f70 JL |
2147 | |
2148 | default: | |
2149 | break; | |
32131a9c RK |
2150 | } |
2151 | ||
2152 | /* If we reach here, all eliminations must be at their initial | |
2153 | offset because we are doing a jump to a variable address. */ | |
2154 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2155 | if (p->offset != p->initial_offset) | |
2156 | p->can_eliminate = 0; | |
e9a25f70 | 2157 | break; |
05d10675 | 2158 | |
e9a25f70 JL |
2159 | default: |
2160 | break; | |
32131a9c RK |
2161 | } |
2162 | } | |
2163 | \f | |
a8fdc208 | 2164 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2165 | replacement (such as sp), plus an offset. |
2166 | ||
2167 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2168 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2169 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2170 | with the register, which we cannot do outside a MEM. In addition, we need | |
2171 | to record the fact that a register is referenced outside a MEM. | |
2172 | ||
ff32812a | 2173 | If INSN is an insn, it is the insn containing X. If we replace a REG |
32131a9c RK |
2174 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a |
2175 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
38e01259 | 2176 | the REG is being modified. |
32131a9c | 2177 | |
ff32812a RS |
2178 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2179 | That's used when we eliminate in expressions stored in notes. | |
2180 | This means, do not set ref_outside_mem even if the reference | |
2181 | is outside of MEMs. | |
2182 | ||
32131a9c RK |
2183 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2184 | replacements done assuming all offsets are at their initial values. If | |
2185 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2186 | encounter, return the actual location so that find_reloads will do | |
2187 | the proper thing. */ | |
2188 | ||
2189 | rtx | |
1914f5da | 2190 | eliminate_regs (x, mem_mode, insn) |
32131a9c RK |
2191 | rtx x; |
2192 | enum machine_mode mem_mode; | |
2193 | rtx insn; | |
2194 | { | |
2195 | enum rtx_code code = GET_CODE (x); | |
2196 | struct elim_table *ep; | |
2197 | int regno; | |
2198 | rtx new; | |
2199 | int i, j; | |
6f7d635c | 2200 | const char *fmt; |
32131a9c RK |
2201 | int copied = 0; |
2202 | ||
d6633f01 NS |
2203 | if (! current_function_decl) |
2204 | return x; | |
9969bb2c | 2205 | |
32131a9c RK |
2206 | switch (code) |
2207 | { | |
2208 | case CONST_INT: | |
2209 | case CONST_DOUBLE: | |
2210 | case CONST: | |
2211 | case SYMBOL_REF: | |
2212 | case CODE_LABEL: | |
2213 | case PC: | |
2214 | case CC0: | |
2215 | case ASM_INPUT: | |
2216 | case ADDR_VEC: | |
2217 | case ADDR_DIFF_VEC: | |
2218 | case RETURN: | |
2219 | return x; | |
2220 | ||
e9a25f70 JL |
2221 | case ADDRESSOF: |
2222 | /* This is only for the benefit of the debugging backends, which call | |
2223 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2224 | removed after CSE. */ | |
1914f5da | 2225 | new = eliminate_regs (XEXP (x, 0), 0, insn); |
e9a25f70 JL |
2226 | if (GET_CODE (new) == MEM) |
2227 | return XEXP (new, 0); | |
2228 | return x; | |
2229 | ||
32131a9c RK |
2230 | case REG: |
2231 | regno = REGNO (x); | |
2232 | ||
2233 | /* First handle the case where we encounter a bare register that | |
2234 | is eliminable. Replace it with a PLUS. */ | |
2235 | if (regno < FIRST_PSEUDO_REGISTER) | |
2236 | { | |
2237 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2238 | ep++) | |
2239 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2240 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2241 | |
2242 | } | |
2b49ee39 R |
2243 | else if (reg_renumber[regno] < 0 && reg_equiv_constant |
2244 | && reg_equiv_constant[regno] | |
2245 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2246 | return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), | |
2247 | mem_mode, insn); | |
32131a9c RK |
2248 | return x; |
2249 | ||
c5c76735 JL |
2250 | /* You might think handling MINUS in a manner similar to PLUS is a |
2251 | good idea. It is not. It has been tried multiple times and every | |
2252 | time the change has had to have been reverted. | |
2253 | ||
2254 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2255 | and require special code to handle code a reloaded PLUS operand. | |
2256 | ||
2257 | Also consider backends where the flags register is clobbered by a | |
2258 | MINUS, but we can emit a PLUS that does not clobber flags (ia32, | |
2259 | lea instruction comes to mind). If we try to reload a MINUS, we | |
2260 | may kill the flags register that was holding a useful value. | |
2261 | ||
2262 | So, please before trying to handle MINUS, consider reload as a | |
2263 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2264 | case PLUS: |
2265 | /* If this is the sum of an eliminable register and a constant, rework | |
2266 | the sum. */ | |
2267 | if (GET_CODE (XEXP (x, 0)) == REG | |
2268 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2269 | && CONSTANT_P (XEXP (x, 1))) | |
2270 | { | |
2271 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2272 | ep++) | |
2273 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2274 | { | |
32131a9c RK |
2275 | /* The only time we want to replace a PLUS with a REG (this |
2276 | occurs when the constant operand of the PLUS is the negative | |
2277 | of the offset) is when we are inside a MEM. We won't want | |
2278 | to do so at other times because that would change the | |
2279 | structure of the insn in a way that reload can't handle. | |
2280 | We special-case the commonest situation in | |
2281 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2282 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2283 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2284 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2285 | return ep->to_rtx; | |
2286 | else | |
38a448ca RH |
2287 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2288 | plus_constant (XEXP (x, 1), | |
2289 | ep->previous_offset)); | |
32131a9c RK |
2290 | } |
2291 | ||
2292 | /* If the register is not eliminable, we are done since the other | |
2293 | operand is a constant. */ | |
2294 | return x; | |
2295 | } | |
2296 | ||
2297 | /* If this is part of an address, we want to bring any constant to the | |
2298 | outermost PLUS. We will do this by doing register replacement in | |
2299 | our operands and seeing if a constant shows up in one of them. | |
2300 | ||
dfac187e BS |
2301 | Note that there is no risk of modifying the structure of the insn, |
2302 | since we only get called for its operands, thus we are either | |
2303 | modifying the address inside a MEM, or something like an address | |
2304 | operand of a load-address insn. */ | |
32131a9c RK |
2305 | |
2306 | { | |
1914f5da RH |
2307 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
2308 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); | |
32131a9c RK |
2309 | |
2310 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2311 | { | |
2312 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2313 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2314 | we must replace the constant here since it may no longer |
2315 | be in the position of any operand. */ | |
2316 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2317 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2318 | && reg_renumber[REGNO (new1)] < 0 | |
2319 | && reg_equiv_constant != 0 | |
2320 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2321 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2322 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2323 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2324 | && reg_renumber[REGNO (new0)] < 0 | |
2325 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2326 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2327 | ||
2328 | new = form_sum (new0, new1); | |
2329 | ||
2330 | /* As above, if we are not inside a MEM we do not want to | |
2331 | turn a PLUS into something else. We might try to do so here | |
2332 | for an addition of 0 if we aren't optimizing. */ | |
2333 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2334 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2335 | else |
2336 | return new; | |
2337 | } | |
2338 | } | |
2339 | return x; | |
2340 | ||
981c7390 | 2341 | case MULT: |
05d10675 | 2342 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2343 | constant, apply the distribute law and move the constant out |
2344 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2345 | to keep load-address insns valid. This case is pathological. |
981c7390 RK |
2346 | We ignore the possibility of overflow here. */ |
2347 | if (GET_CODE (XEXP (x, 0)) == REG | |
2348 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2349 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2350 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2351 | ep++) | |
2352 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2353 | { | |
2354 | if (! mem_mode | |
2355 | /* Refs inside notes don't count for this purpose. */ | |
2356 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2357 | || GET_CODE (insn) == INSN_LIST))) | |
2358 | ep->ref_outside_mem = 1; | |
2359 | ||
2360 | return | |
38a448ca | 2361 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2362 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2363 | } | |
32131a9c | 2364 | |
0f41302f | 2365 | /* ... fall through ... */ |
32131a9c | 2366 | |
32131a9c RK |
2367 | case CALL: |
2368 | case COMPARE: | |
c5c76735 | 2369 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2370 | case MINUS: |
32131a9c RK |
2371 | case DIV: case UDIV: |
2372 | case MOD: case UMOD: | |
2373 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2374 | case ROTATERT: case ROTATE: |
2375 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2376 | case NE: case EQ: |
2377 | case GE: case GT: case GEU: case GTU: | |
2378 | case LE: case LT: case LEU: case LTU: | |
2379 | { | |
1914f5da | 2380 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
fb3821f7 | 2381 | rtx new1 |
1914f5da | 2382 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; |
32131a9c RK |
2383 | |
2384 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2385 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2386 | } |
2387 | return x; | |
2388 | ||
981c7390 RK |
2389 | case EXPR_LIST: |
2390 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2391 | if (XEXP (x, 0)) | |
2392 | { | |
1914f5da | 2393 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
981c7390 | 2394 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2395 | { |
2396 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2397 | Using the eliminated version could result in creating a | |
2398 | REG_DEAD note for the stack or frame pointer. */ | |
2399 | if (GET_MODE (x) == REG_DEAD) | |
2400 | return (XEXP (x, 1) | |
2401 | ? eliminate_regs (XEXP (x, 1), mem_mode, insn) | |
2402 | : NULL_RTX); | |
2403 | ||
2404 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2405 | } | |
981c7390 RK |
2406 | } |
2407 | ||
0f41302f | 2408 | /* ... fall through ... */ |
981c7390 RK |
2409 | |
2410 | case INSN_LIST: | |
2411 | /* Now do eliminations in the rest of the chain. If this was | |
2412 | an EXPR_LIST, this might result in allocating more memory than is | |
2413 | strictly needed, but it simplifies the code. */ | |
2414 | if (XEXP (x, 1)) | |
2415 | { | |
1914f5da | 2416 | new = eliminate_regs (XEXP (x, 1), mem_mode, insn); |
981c7390 | 2417 | if (new != XEXP (x, 1)) |
38a448ca | 2418 | return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); |
981c7390 RK |
2419 | } |
2420 | return x; | |
2421 | ||
32131a9c RK |
2422 | case PRE_INC: |
2423 | case POST_INC: | |
2424 | case PRE_DEC: | |
2425 | case POST_DEC: | |
32131a9c RK |
2426 | case STRICT_LOW_PART: |
2427 | case NEG: case NOT: | |
2428 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2429 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2430 | case FLOAT: case FIX: | |
2431 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2432 | case ABS: | |
2433 | case SQRT: | |
2434 | case FFS: | |
1914f5da | 2435 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
32131a9c | 2436 | if (new != XEXP (x, 0)) |
38a448ca | 2437 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2438 | return x; |
2439 | ||
2440 | case SUBREG: | |
2441 | /* Similar to above processing, but preserve SUBREG_WORD. | |
2442 | Convert (subreg (mem)) to (mem) if not paradoxical. | |
2443 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2444 | pseudo didn't get a hard reg, we must replace this with the | |
2445 | eliminated version of the memory location because push_reloads | |
2446 | may do the replacement in certain circumstances. */ | |
2447 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2448 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2449 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2450 | && reg_equiv_memory_loc != 0 | |
2451 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2452 | { | |
cb2afeb3 | 2453 | new = SUBREG_REG (x); |
32131a9c RK |
2454 | } |
2455 | else | |
1914f5da | 2456 | new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); |
32131a9c RK |
2457 | |
2458 | if (new != XEXP (x, 0)) | |
2459 | { | |
29ae5012 RK |
2460 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2461 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2462 | ||
1914f5da | 2463 | if (GET_CODE (new) == MEM |
6d49a073 | 2464 | && ((x_size < new_size |
1914f5da | 2465 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2466 | /* On these machines, combine can create rtl of the form |
2467 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2468 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2469 | happen to the entire word. Moreover, it will use the |
2470 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2471 | So if the number of words is the same, preserve the |
6d49a073 JW |
2472 | subreg so that push_reloads can see it. */ |
2473 | && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD) | |
1914f5da | 2474 | #endif |
6d49a073 JW |
2475 | ) |
2476 | || (x_size == new_size)) | |
1914f5da | 2477 | ) |
32131a9c RK |
2478 | { |
2479 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
2480 | enum machine_mode mode = GET_MODE (x); | |
2481 | ||
f76b9db2 ILT |
2482 | if (BYTES_BIG_ENDIAN) |
2483 | offset += (MIN (UNITS_PER_WORD, | |
2484 | GET_MODE_SIZE (GET_MODE (new))) | |
2485 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
32131a9c RK |
2486 | |
2487 | PUT_MODE (new, mode); | |
2488 | XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); | |
2489 | return new; | |
2490 | } | |
2491 | else | |
38a448ca | 2492 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x)); |
32131a9c RK |
2493 | } |
2494 | ||
2495 | return x; | |
2496 | ||
32131a9c | 2497 | case MEM: |
e9a25f70 JL |
2498 | /* This is only for the benefit of the debugging backends, which call |
2499 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2500 | removed after CSE. */ | |
2501 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
1914f5da | 2502 | return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); |
e9a25f70 | 2503 | |
32131a9c RK |
2504 | /* Our only special processing is to pass the mode of the MEM to our |
2505 | recursive call and copy the flags. While we are here, handle this | |
2506 | case more efficiently. */ | |
1914f5da | 2507 | new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn); |
32131a9c RK |
2508 | if (new != XEXP (x, 0)) |
2509 | { | |
38a448ca | 2510 | new = gen_rtx_MEM (GET_MODE (x), new); |
3bdf5ad1 | 2511 | MEM_COPY_ATTRIBUTES (new, x); |
32131a9c RK |
2512 | return new; |
2513 | } | |
2514 | else | |
2515 | return x; | |
05d10675 | 2516 | |
dfac187e BS |
2517 | case USE: |
2518 | case CLOBBER: | |
2519 | case ASM_OPERANDS: | |
2520 | case SET: | |
2521 | abort (); | |
2522 | ||
e9a25f70 JL |
2523 | default: |
2524 | break; | |
32131a9c RK |
2525 | } |
2526 | ||
2527 | /* Process each of our operands recursively. If any have changed, make a | |
2528 | copy of the rtx. */ | |
2529 | fmt = GET_RTX_FORMAT (code); | |
2530 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2531 | { | |
2532 | if (*fmt == 'e') | |
2533 | { | |
1914f5da | 2534 | new = eliminate_regs (XEXP (x, i), mem_mode, insn); |
32131a9c RK |
2535 | if (new != XEXP (x, i) && ! copied) |
2536 | { | |
2537 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2538 | memcpy (new_x, x, |
2539 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2540 | + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); | |
32131a9c RK |
2541 | x = new_x; |
2542 | copied = 1; | |
2543 | } | |
2544 | XEXP (x, i) = new; | |
2545 | } | |
2546 | else if (*fmt == 'E') | |
2547 | { | |
2548 | int copied_vec = 0; | |
2549 | for (j = 0; j < XVECLEN (x, i); j++) | |
2550 | { | |
1914f5da | 2551 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); |
32131a9c RK |
2552 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2553 | { | |
8f985ec4 ZW |
2554 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2555 | XVEC (x, i)->elem); | |
32131a9c RK |
2556 | if (! copied) |
2557 | { | |
2558 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2559 | memcpy (new_x, x, |
2560 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2561 | + (sizeof (new_x->fld[0]) | |
2562 | * GET_RTX_LENGTH (code)))); | |
32131a9c RK |
2563 | x = new_x; |
2564 | copied = 1; | |
2565 | } | |
2566 | XVEC (x, i) = new_v; | |
2567 | copied_vec = 1; | |
2568 | } | |
2569 | XVECEXP (x, i, j) = new; | |
2570 | } | |
2571 | } | |
2572 | } | |
2573 | ||
2574 | return x; | |
2575 | } | |
dfac187e BS |
2576 | |
2577 | /* Scan rtx X for modifications of elimination target registers. Update | |
2578 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2579 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2580 | ||
2581 | static void | |
2582 | elimination_effects (x, mem_mode) | |
2583 | rtx x; | |
2584 | enum machine_mode mem_mode; | |
2585 | ||
2586 | { | |
2587 | enum rtx_code code = GET_CODE (x); | |
2588 | struct elim_table *ep; | |
2589 | int regno; | |
2590 | int i, j; | |
2591 | const char *fmt; | |
2592 | ||
2593 | switch (code) | |
2594 | { | |
2595 | case CONST_INT: | |
2596 | case CONST_DOUBLE: | |
2597 | case CONST: | |
2598 | case SYMBOL_REF: | |
2599 | case CODE_LABEL: | |
2600 | case PC: | |
2601 | case CC0: | |
2602 | case ASM_INPUT: | |
2603 | case ADDR_VEC: | |
2604 | case ADDR_DIFF_VEC: | |
2605 | case RETURN: | |
2606 | return; | |
2607 | ||
2608 | case ADDRESSOF: | |
2609 | abort (); | |
2610 | ||
2611 | case REG: | |
2612 | regno = REGNO (x); | |
2613 | ||
2614 | /* First handle the case where we encounter a bare register that | |
2615 | is eliminable. Replace it with a PLUS. */ | |
2616 | if (regno < FIRST_PSEUDO_REGISTER) | |
2617 | { | |
2618 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2619 | ep++) | |
2620 | if (ep->from_rtx == x && ep->can_eliminate) | |
2621 | { | |
2622 | if (! mem_mode) | |
2623 | ep->ref_outside_mem = 1; | |
2624 | return; | |
2625 | } | |
2626 | ||
2627 | } | |
2628 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2629 | && reg_equiv_constant[regno] | |
2630 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2631 | elimination_effects (reg_equiv_constant[regno], mem_mode); | |
2632 | return; | |
2633 | ||
2634 | case PRE_INC: | |
2635 | case POST_INC: | |
2636 | case PRE_DEC: | |
2637 | case POST_DEC: | |
4b983fdc RH |
2638 | case POST_MODIFY: |
2639 | case PRE_MODIFY: | |
dfac187e BS |
2640 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2641 | if (ep->to_rtx == XEXP (x, 0)) | |
2642 | { | |
2643 | int size = GET_MODE_SIZE (mem_mode); | |
2644 | ||
2645 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2646 | #ifdef PUSH_ROUNDING | |
2647 | if (ep->to_rtx == stack_pointer_rtx) | |
2648 | size = PUSH_ROUNDING (size); | |
2649 | #endif | |
2650 | if (code == PRE_DEC || code == POST_DEC) | |
2651 | ep->offset += size; | |
4b983fdc | 2652 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 2653 | ep->offset -= size; |
4b983fdc RH |
2654 | else if ((code == PRE_MODIFY || code == POST_MODIFY) |
2655 | && GET_CODE (XEXP (x, 1)) == PLUS | |
2656 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2657 | && CONSTANT_P (XEXP (XEXP (x, 1), 1))) | |
2658 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
dfac187e BS |
2659 | } |
2660 | ||
4b983fdc RH |
2661 | /* These two aren't unary operators. */ |
2662 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2663 | break; | |
2664 | ||
dfac187e BS |
2665 | /* Fall through to generic unary operation case. */ |
2666 | case STRICT_LOW_PART: | |
2667 | case NEG: case NOT: | |
2668 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2669 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2670 | case FLOAT: case FIX: | |
2671 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2672 | case ABS: | |
2673 | case SQRT: | |
2674 | case FFS: | |
2675 | elimination_effects (XEXP (x, 0), mem_mode); | |
2676 | return; | |
2677 | ||
2678 | case SUBREG: | |
2679 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2680 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2681 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2682 | && reg_equiv_memory_loc != 0 | |
2683 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2684 | return; | |
2685 | ||
2686 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2687 | return; | |
2688 | ||
2689 | case USE: | |
2690 | /* If using a register that is the source of an eliminate we still | |
2691 | think can be performed, note it cannot be performed since we don't | |
2692 | know how this register is used. */ | |
2693 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2694 | if (ep->from_rtx == XEXP (x, 0)) | |
2695 | ep->can_eliminate = 0; | |
2696 | ||
2697 | elimination_effects (XEXP (x, 0), mem_mode); | |
2698 | return; | |
2699 | ||
2700 | case CLOBBER: | |
2701 | /* If clobbering a register that is the replacement register for an | |
2702 | elimination we still think can be performed, note that it cannot | |
2703 | be performed. Otherwise, we need not be concerned about it. */ | |
2704 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2705 | if (ep->to_rtx == XEXP (x, 0)) | |
2706 | ep->can_eliminate = 0; | |
2707 | ||
2708 | elimination_effects (XEXP (x, 0), mem_mode); | |
2709 | return; | |
2710 | ||
2711 | case SET: | |
2712 | /* Check for setting a register that we know about. */ | |
2713 | if (GET_CODE (SET_DEST (x)) == REG) | |
2714 | { | |
2715 | /* See if this is setting the replacement register for an | |
2716 | elimination. | |
2717 | ||
2718 | If DEST is the hard frame pointer, we do nothing because we | |
2719 | assume that all assignments to the frame pointer are for | |
2720 | non-local gotos and are being done at a time when they are valid | |
2721 | and do not disturb anything else. Some machines want to | |
2722 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2723 | with either the real frame or the stack pointer. Assignments to | |
2724 | the hard frame pointer must not prevent this elimination. */ | |
2725 | ||
2726 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2727 | ep++) | |
2728 | if (ep->to_rtx == SET_DEST (x) | |
2729 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2730 | { | |
2731 | /* If it is being incremented, adjust the offset. Otherwise, | |
2732 | this elimination can't be done. */ | |
2733 | rtx src = SET_SRC (x); | |
2734 | ||
2735 | if (GET_CODE (src) == PLUS | |
2736 | && XEXP (src, 0) == SET_DEST (x) | |
2737 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2738 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2739 | else | |
2740 | ep->can_eliminate = 0; | |
2741 | } | |
2742 | } | |
2743 | ||
2744 | elimination_effects (SET_DEST (x), 0); | |
2745 | elimination_effects (SET_SRC (x), 0); | |
2746 | return; | |
2747 | ||
2748 | case MEM: | |
2749 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
2750 | abort (); | |
2751 | ||
2752 | /* Our only special processing is to pass the mode of the MEM to our | |
2753 | recursive call. */ | |
2754 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2755 | return; | |
2756 | ||
2757 | default: | |
2758 | break; | |
2759 | } | |
2760 | ||
2761 | fmt = GET_RTX_FORMAT (code); | |
2762 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2763 | { | |
2764 | if (*fmt == 'e') | |
2765 | elimination_effects (XEXP (x, i), mem_mode); | |
2766 | else if (*fmt == 'E') | |
2767 | for (j = 0; j < XVECLEN (x, i); j++) | |
2768 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2769 | } | |
2770 | } | |
2771 | ||
2772 | /* Descend through rtx X and verify that no references to eliminable registers | |
2773 | remain. If any do remain, mark the involved register as not | |
2774 | eliminable. */ | |
1d813780 | 2775 | |
dfac187e BS |
2776 | static void |
2777 | check_eliminable_occurrences (x) | |
2778 | rtx x; | |
2779 | { | |
2780 | const char *fmt; | |
2781 | int i; | |
2782 | enum rtx_code code; | |
2783 | ||
2784 | if (x == 0) | |
2785 | return; | |
1d7254c5 | 2786 | |
dfac187e BS |
2787 | code = GET_CODE (x); |
2788 | ||
2789 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
2790 | { | |
2791 | struct elim_table *ep; | |
2792 | ||
2793 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2794 | if (ep->from_rtx == x && ep->can_eliminate) | |
2795 | ep->can_eliminate = 0; | |
2796 | return; | |
2797 | } | |
1d7254c5 | 2798 | |
dfac187e BS |
2799 | fmt = GET_RTX_FORMAT (code); |
2800 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2801 | { | |
2802 | if (*fmt == 'e') | |
2803 | check_eliminable_occurrences (XEXP (x, i)); | |
2804 | else if (*fmt == 'E') | |
2805 | { | |
2806 | int j; | |
2807 | for (j = 0; j < XVECLEN (x, i); j++) | |
2808 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
2809 | } | |
2810 | } | |
2811 | } | |
32131a9c RK |
2812 | \f |
2813 | /* Scan INSN and eliminate all eliminable registers in it. | |
2814 | ||
2815 | If REPLACE is nonzero, do the replacement destructively. Also | |
2816 | delete the insn as dead it if it is setting an eliminable register. | |
2817 | ||
2818 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2819 | ||
2820 | If no eliminations were done and this insn doesn't require any elimination | |
2821 | processing (these are not identical conditions: it might be updating sp, | |
2822 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2823 | that the offset between fp and sp can be taken into consideration), zero | |
2824 | is returned. Otherwise, 1 is returned. */ | |
2825 | ||
2826 | static int | |
2827 | eliminate_regs_in_insn (insn, replace) | |
2828 | rtx insn; | |
2829 | int replace; | |
2830 | { | |
dfac187e | 2831 | int icode = recog_memoized (insn); |
32131a9c | 2832 | rtx old_body = PATTERN (insn); |
dfac187e | 2833 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 2834 | rtx old_set = single_set (insn); |
32131a9c RK |
2835 | rtx new_body; |
2836 | int val = 0; | |
dfac187e BS |
2837 | int i, any_changes; |
2838 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2839 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
2840 | struct elim_table *ep; |
2841 | ||
dfac187e BS |
2842 | if (! insn_is_asm && icode < 0) |
2843 | { | |
2844 | if (GET_CODE (PATTERN (insn)) == USE | |
2845 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
2846 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2847 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2848 | || GET_CODE (PATTERN (insn)) == ASM_INPUT) | |
2849 | return 0; | |
2850 | abort (); | |
2851 | } | |
2852 | ||
774672d2 RK |
2853 | if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG |
2854 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
2855 | { |
2856 | /* Check for setting an eliminable register. */ | |
2857 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 2858 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 2859 | { |
dd1eab0a RK |
2860 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
2861 | /* If this is setting the frame pointer register to the | |
2862 | hardware frame pointer register and this is an elimination | |
2863 | that will be done (tested above), this insn is really | |
2864 | adjusting the frame pointer downward to compensate for | |
2865 | the adjustment done before a nonlocal goto. */ | |
2866 | if (ep->from == FRAME_POINTER_REGNUM | |
2867 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
2868 | { | |
2869 | rtx src = SET_SRC (old_set); | |
973838fd | 2870 | int offset = 0, ok = 0; |
8026ebba | 2871 | rtx prev_insn, prev_set; |
dd1eab0a RK |
2872 | |
2873 | if (src == ep->to_rtx) | |
2874 | offset = 0, ok = 1; | |
2875 | else if (GET_CODE (src) == PLUS | |
bb22893c JW |
2876 | && GET_CODE (XEXP (src, 0)) == CONST_INT |
2877 | && XEXP (src, 1) == ep->to_rtx) | |
dd1eab0a | 2878 | offset = INTVAL (XEXP (src, 0)), ok = 1; |
bb22893c JW |
2879 | else if (GET_CODE (src) == PLUS |
2880 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2881 | && XEXP (src, 0) == ep->to_rtx) | |
2882 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
8026ebba ILT |
2883 | else if ((prev_insn = prev_nonnote_insn (insn)) != 0 |
2884 | && (prev_set = single_set (prev_insn)) != 0 | |
2885 | && rtx_equal_p (SET_DEST (prev_set), src)) | |
2886 | { | |
2887 | src = SET_SRC (prev_set); | |
2888 | if (src == ep->to_rtx) | |
2889 | offset = 0, ok = 1; | |
2890 | else if (GET_CODE (src) == PLUS | |
2891 | && GET_CODE (XEXP (src, 0)) == CONST_INT | |
2892 | && XEXP (src, 1) == ep->to_rtx) | |
2893 | offset = INTVAL (XEXP (src, 0)), ok = 1; | |
2894 | else if (GET_CODE (src) == PLUS | |
2895 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2896 | && XEXP (src, 0) == ep->to_rtx) | |
2897 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
2898 | } | |
dd1eab0a RK |
2899 | |
2900 | if (ok) | |
2901 | { | |
2902 | if (replace) | |
2903 | { | |
2904 | rtx src | |
2905 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
2906 | ||
2907 | /* First see if this insn remains valid when we | |
2908 | make the change. If not, keep the INSN_CODE | |
2909 | the same and let reload fit it up. */ | |
2910 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
2911 | validate_change (insn, &SET_DEST (old_set), | |
2912 | ep->to_rtx, 1); | |
2913 | if (! apply_change_group ()) | |
2914 | { | |
2915 | SET_SRC (old_set) = src; | |
2916 | SET_DEST (old_set) = ep->to_rtx; | |
2917 | } | |
2918 | } | |
2919 | ||
2920 | val = 1; | |
2921 | goto done; | |
2922 | } | |
2923 | } | |
2924 | #endif | |
2925 | ||
32131a9c RK |
2926 | /* In this case this insn isn't serving a useful purpose. We |
2927 | will delete it in reload_as_needed once we know that this | |
2928 | elimination is, in fact, being done. | |
2929 | ||
abc95ed3 | 2930 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
2931 | process it since it won't be used unless something changes. */ |
2932 | if (replace) | |
8a34409d | 2933 | { |
1d7254c5 | 2934 | delete_dead_insn (insn); |
8a34409d RH |
2935 | return 1; |
2936 | } | |
32131a9c RK |
2937 | val = 1; |
2938 | goto done; | |
2939 | } | |
aa5524a9 | 2940 | } |
32131a9c | 2941 | |
aa5524a9 BS |
2942 | /* We allow one special case which happens to work on all machines we |
2943 | currently support: a single set with the source being a PLUS of an | |
2944 | eliminable register and a constant. */ | |
2945 | if (old_set | |
2946 | && GET_CODE (SET_SRC (old_set)) == PLUS | |
2947 | && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG | |
2948 | && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT | |
2949 | && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) | |
2950 | { | |
2951 | rtx reg = XEXP (SET_SRC (old_set), 0); | |
2952 | int offset = INTVAL (XEXP (SET_SRC (old_set), 1)); | |
32131a9c | 2953 | |
aa5524a9 BS |
2954 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2955 | if (ep->from_rtx == reg && ep->can_eliminate) | |
2956 | { | |
2957 | offset += ep->offset; | |
32131a9c | 2958 | |
aa5524a9 BS |
2959 | if (offset == 0) |
2960 | { | |
f34c06e5 R |
2961 | int num_clobbers; |
2962 | /* We assume here that if we need a PARALLEL with | |
2963 | CLOBBERs for this assignment, we can do with the | |
2964 | MATCH_SCRATCHes that add_clobbers allocates. | |
2965 | There's not much we can do if that doesn't work. */ | |
aa5524a9 BS |
2966 | PATTERN (insn) = gen_rtx_SET (VOIDmode, |
2967 | SET_DEST (old_set), | |
2968 | ep->to_rtx); | |
f34c06e5 R |
2969 | num_clobbers = 0; |
2970 | INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers); | |
2971 | if (num_clobbers) | |
2972 | { | |
2973 | rtvec vec = rtvec_alloc (num_clobbers + 1); | |
2974 | ||
2975 | vec->elem[0] = PATTERN (insn); | |
2976 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); | |
2977 | add_clobbers (PATTERN (insn), INSN_CODE (insn)); | |
2978 | } | |
aa5524a9 BS |
2979 | if (INSN_CODE (insn) < 0) |
2980 | abort (); | |
2981 | } | |
2982 | else | |
2983 | { | |
2984 | new_body = old_body; | |
2985 | if (! replace) | |
2986 | { | |
2987 | new_body = copy_insn (old_body); | |
2988 | if (REG_NOTES (insn)) | |
2989 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
2990 | } | |
2991 | PATTERN (insn) = new_body; | |
2992 | old_set = single_set (insn); | |
922d9d40 | 2993 | |
aa5524a9 BS |
2994 | XEXP (SET_SRC (old_set), 0) = ep->to_rtx; |
2995 | XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); | |
2996 | } | |
2997 | val = 1; | |
2998 | /* This can't have an effect on elimination offsets, so skip right | |
2999 | to the end. */ | |
3000 | goto done; | |
3001 | } | |
32131a9c RK |
3002 | } |
3003 | ||
dfac187e BS |
3004 | /* Determine the effects of this insn on elimination offsets. */ |
3005 | elimination_effects (old_body, 0); | |
3006 | ||
3007 | /* Eliminate all eliminable registers occurring in operands that | |
3008 | can be handled by reload. */ | |
3009 | extract_insn (insn); | |
3010 | any_changes = 0; | |
3011 | for (i = 0; i < recog_data.n_operands; i++) | |
3012 | { | |
3013 | orig_operand[i] = recog_data.operand[i]; | |
3014 | substed_operand[i] = recog_data.operand[i]; | |
3015 | ||
3016 | /* For an asm statement, every operand is eliminable. */ | |
3017 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3018 | { | |
3019 | /* Check for setting a register that we know about. */ | |
3020 | if (recog_data.operand_type[i] != OP_IN | |
3021 | && GET_CODE (orig_operand[i]) == REG) | |
3022 | { | |
3023 | /* If we are assigning to a register that can be eliminated, it | |
3024 | must be as part of a PARALLEL, since the code above handles | |
3025 | single SETs. We must indicate that we can no longer | |
3026 | eliminate this reg. */ | |
3027 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3028 | ep++) | |
3029 | if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) | |
3030 | ep->can_eliminate = 0; | |
3031 | } | |
3032 | ||
3033 | substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, | |
3034 | replace ? insn : NULL_RTX); | |
3035 | if (substed_operand[i] != orig_operand[i]) | |
3036 | val = any_changes = 1; | |
3037 | /* Terminate the search in check_eliminable_occurrences at | |
3038 | this point. */ | |
3039 | *recog_data.operand_loc[i] = 0; | |
3040 | ||
3041 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3042 | insn, write a CLOBBER insn. */ | |
3043 | if (recog_data.operand_type[i] != OP_IN | |
3044 | && GET_CODE (orig_operand[i]) == REG | |
3045 | && GET_CODE (substed_operand[i]) == MEM | |
3046 | && replace) | |
3047 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3048 | insn); | |
3049 | } | |
3050 | } | |
3051 | ||
3052 | for (i = 0; i < recog_data.n_dups; i++) | |
3053 | *recog_data.dup_loc[i] | |
1d7254c5 | 3054 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3055 | |
3056 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3057 | check_eliminable_occurrences (old_body); | |
32131a9c | 3058 | |
dfac187e BS |
3059 | /* Substitute the operands; the new values are in the substed_operand |
3060 | array. */ | |
3061 | for (i = 0; i < recog_data.n_operands; i++) | |
3062 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3063 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3064 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3065 | |
dfac187e | 3066 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3067 | re-recognize the insn. We do this in case we had a simple addition |
3068 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3069 | common case. |
3070 | If re-recognition fails, the old insn code number will still be used, | |
3071 | and some register operands may have changed into PLUS expressions. | |
3072 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3073 | again. */ |
32131a9c | 3074 | |
dfac187e | 3075 | if (val) |
32131a9c | 3076 | { |
7c791b13 RK |
3077 | /* If we aren't replacing things permanently and we changed something, |
3078 | make another copy to ensure that all the RTL is new. Otherwise | |
3079 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3080 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3081 | new_body = old_body; |
3082 | if (! replace) | |
1b3b5765 BS |
3083 | { |
3084 | new_body = copy_insn (old_body); | |
3085 | if (REG_NOTES (insn)) | |
3086 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3087 | } | |
dfac187e | 3088 | PATTERN (insn) = new_body; |
7c791b13 | 3089 | |
774672d2 RK |
3090 | /* If we had a move insn but now we don't, rerecognize it. This will |
3091 | cause spurious re-recognition if the old move had a PARALLEL since | |
3092 | the new one still will, but we can't call single_set without | |
3093 | having put NEW_BODY into the insn and the re-recognition won't | |
3094 | hurt in this rare case. */ | |
dfac187e BS |
3095 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3096 | thing always? */ | |
3097 | if (! insn_is_asm | |
3098 | && old_set != 0 | |
774672d2 RK |
3099 | && ((GET_CODE (SET_SRC (old_set)) == REG |
3100 | && (GET_CODE (new_body) != SET | |
3101 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3102 | /* If this was a load from or store to memory, compare | |
1ccbefce RH |
3103 | the MEM in recog_data.operand to the one in the insn. |
3104 | If they are not equal, then rerecognize the insn. */ | |
774672d2 RK |
3105 | || (old_set != 0 |
3106 | && ((GET_CODE (SET_SRC (old_set)) == MEM | |
1ccbefce | 3107 | && SET_SRC (old_set) != recog_data.operand[1]) |
774672d2 | 3108 | || (GET_CODE (SET_DEST (old_set)) == MEM |
1ccbefce | 3109 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3110 | /* If this was an add insn before, rerecognize. */ |
3111 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3112 | { |
dfac187e BS |
3113 | int new_icode = recog (PATTERN (insn), insn, 0); |
3114 | if (new_icode < 0) | |
3115 | INSN_CODE (insn) = icode; | |
4a5d0fb5 | 3116 | } |
dfac187e | 3117 | } |
32131a9c | 3118 | |
dfac187e BS |
3119 | /* Restore the old body. If there were any changes to it, we made a copy |
3120 | of it while the changes were still in place, so we'll correctly return | |
3121 | a modified insn below. */ | |
3122 | if (! replace) | |
3123 | { | |
3124 | /* Restore the old body. */ | |
3125 | for (i = 0; i < recog_data.n_operands; i++) | |
3126 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3127 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3128 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3129 | } |
a8fdc208 | 3130 | |
dfac187e BS |
3131 | /* Update all elimination pairs to reflect the status after the current |
3132 | insn. The changes we make were determined by the earlier call to | |
3133 | elimination_effects. | |
a8efe40d | 3134 | |
32131a9c RK |
3135 | We also detect a cases where register elimination cannot be done, |
3136 | namely, if a register would be both changed and referenced outside a MEM | |
3137 | in the resulting insn since such an insn is often undefined and, even if | |
3138 | not, we cannot know what meaning will be given to it. Note that it is | |
3139 | valid to have a register used in an address in an insn that changes it | |
3140 | (presumably with a pre- or post-increment or decrement). | |
3141 | ||
3142 | If anything changes, return nonzero. */ | |
3143 | ||
32131a9c RK |
3144 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3145 | { | |
3146 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3147 | ep->can_eliminate = 0; | |
3148 | ||
3149 | ep->ref_outside_mem = 0; | |
3150 | ||
3151 | if (ep->previous_offset != ep->offset) | |
3152 | val = 1; | |
32131a9c RK |
3153 | } |
3154 | ||
3155 | done: | |
9faa82d8 | 3156 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3157 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3158 | to a register that we eliminate and could cause a different number | |
3159 | of spill registers to be needed in the final reload pass than in | |
3160 | the pre-passes. */ | |
20748cab | 3161 | if (val && REG_NOTES (insn) != 0) |
1914f5da | 3162 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); |
05b4c365 | 3163 | |
32131a9c RK |
3164 | return val; |
3165 | } | |
3166 | ||
cb2afeb3 R |
3167 | /* Loop through all elimination pairs. |
3168 | Recalculate the number not at initial offset. | |
3169 | ||
3170 | Compute the maximum offset (minimum offset if the stack does not | |
3171 | grow downward) for each elimination pair. */ | |
3172 | ||
3173 | static void | |
3174 | update_eliminable_offsets () | |
3175 | { | |
3176 | struct elim_table *ep; | |
3177 | ||
3178 | num_not_at_initial_offset = 0; | |
3179 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3180 | { | |
3181 | ep->previous_offset = ep->offset; | |
3182 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3183 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3184 | } |
3185 | } | |
3186 | ||
32131a9c RK |
3187 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3188 | replacement we currently believe is valid, mark it as not eliminable if X | |
3189 | modifies DEST in any way other than by adding a constant integer to it. | |
3190 | ||
3191 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3192 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3193 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3194 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3195 | frame or stack pointer. Assignments to the hard frame pointer must not |
3196 | prevent this elimination. | |
32131a9c RK |
3197 | |
3198 | Called via note_stores from reload before starting its passes to scan | |
3199 | the insns of the function. */ | |
3200 | ||
3201 | static void | |
84832317 | 3202 | mark_not_eliminable (dest, x, data) |
32131a9c RK |
3203 | rtx dest; |
3204 | rtx x; | |
84832317 | 3205 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 3206 | { |
e51712db | 3207 | register unsigned int i; |
32131a9c RK |
3208 | |
3209 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3210 | not see a SUBREG of an eliminable hard register, but check just in | |
3211 | case. */ | |
3212 | if (GET_CODE (dest) == SUBREG) | |
3213 | dest = SUBREG_REG (dest); | |
3214 | ||
3ec2ea3e | 3215 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3216 | return; |
3217 | ||
3218 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3219 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3220 | && (GET_CODE (x) != SET | |
3221 | || GET_CODE (SET_SRC (x)) != PLUS | |
3222 | || XEXP (SET_SRC (x), 0) != dest | |
3223 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3224 | { | |
3225 | reg_eliminate[i].can_eliminate_previous | |
3226 | = reg_eliminate[i].can_eliminate = 0; | |
3227 | num_eliminable--; | |
3228 | } | |
3229 | } | |
09dd1133 | 3230 | |
c47f5ea5 BS |
3231 | /* Verify that the initial elimination offsets did not change since the |
3232 | last call to set_initial_elim_offsets. This is used to catch cases | |
3233 | where something illegal happened during reload_as_needed that could | |
3234 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3235 | |
c47f5ea5 BS |
3236 | static void |
3237 | verify_initial_elim_offsets () | |
3238 | { | |
3239 | int t; | |
3240 | ||
3241 | #ifdef ELIMINABLE_REGS | |
3242 | struct elim_table *ep; | |
3243 | ||
3244 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3245 | { | |
3246 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3247 | if (t != ep->initial_offset) | |
3248 | abort (); | |
3249 | } | |
3250 | #else | |
3251 | INITIAL_FRAME_POINTER_OFFSET (t); | |
3252 | if (t != reg_eliminate[0].initial_offset) | |
3253 | abort (); | |
05d10675 | 3254 | #endif |
c47f5ea5 BS |
3255 | } |
3256 | ||
09dd1133 | 3257 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3258 | |
09dd1133 BS |
3259 | static void |
3260 | set_initial_elim_offsets () | |
3261 | { | |
1f3b1e1a | 3262 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3263 | |
3264 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3265 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3266 | { |
3267 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3268 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3269 | } |
3270 | #else | |
1f3b1e1a JL |
3271 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3272 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3273 | #endif |
3274 | ||
3275 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3276 | } |
09dd1133 | 3277 | |
1f3b1e1a JL |
3278 | /* Initialize the known label offsets. |
3279 | Set a known offset for each forced label to be at the initial offset | |
3280 | of each elimination. We do this because we assume that all | |
3281 | computed jumps occur from a location where each elimination is | |
3282 | at its initial offset. | |
3283 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3284 | |
1f3b1e1a JL |
3285 | static void |
3286 | set_initial_label_offsets () | |
3287 | { | |
3288 | rtx x; | |
961192e1 | 3289 | memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels); |
09dd1133 BS |
3290 | |
3291 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3292 | if (XEXP (x, 0)) | |
3293 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
3294 | } | |
3295 | ||
1f3b1e1a JL |
3296 | /* Set all elimination offsets to the known values for the code label given |
3297 | by INSN. */ | |
1d813780 | 3298 | |
1f3b1e1a JL |
3299 | static void |
3300 | set_offsets_for_label (insn) | |
3301 | rtx insn; | |
3302 | { | |
973838fd | 3303 | unsigned int i; |
1f3b1e1a JL |
3304 | int label_nr = CODE_LABEL_NUMBER (insn); |
3305 | struct elim_table *ep; | |
3306 | ||
3307 | num_not_at_initial_offset = 0; | |
3308 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3309 | { | |
3310 | ep->offset = ep->previous_offset = offsets_at[label_nr][i]; | |
3311 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3312 | num_not_at_initial_offset++; | |
3313 | } | |
3314 | } | |
3315 | ||
09dd1133 BS |
3316 | /* See if anything that happened changes which eliminations are valid. |
3317 | For example, on the Sparc, whether or not the frame pointer can | |
3318 | be eliminated can depend on what registers have been used. We need | |
3319 | not check some conditions again (such as flag_omit_frame_pointer) | |
3320 | since they can't have changed. */ | |
3321 | ||
3322 | static void | |
3323 | update_eliminables (pset) | |
3324 | HARD_REG_SET *pset; | |
3325 | { | |
3326 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3327 | int previous_frame_pointer_needed = frame_pointer_needed; | |
3328 | #endif | |
3329 | struct elim_table *ep; | |
3330 | ||
3331 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3332 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3333 | #ifdef ELIMINABLE_REGS | |
3334 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3335 | #endif | |
3336 | ) | |
3337 | ep->can_eliminate = 0; | |
3338 | ||
3339 | /* Look for the case where we have discovered that we can't replace | |
3340 | register A with register B and that means that we will now be | |
3341 | trying to replace register A with register C. This means we can | |
3342 | no longer replace register C with register B and we need to disable | |
3343 | such an elimination, if it exists. This occurs often with A == ap, | |
3344 | B == sp, and C == fp. */ | |
3345 | ||
3346 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3347 | { | |
3348 | struct elim_table *op; | |
3349 | register int new_to = -1; | |
3350 | ||
3351 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3352 | { | |
3353 | /* Find the current elimination for ep->from, if there is a | |
3354 | new one. */ | |
3355 | for (op = reg_eliminate; | |
3356 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3357 | if (op->from == ep->from && op->can_eliminate) | |
3358 | { | |
3359 | new_to = op->to; | |
3360 | break; | |
3361 | } | |
3362 | ||
3363 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3364 | disable it. */ | |
3365 | for (op = reg_eliminate; | |
3366 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3367 | if (op->from == new_to && op->to == ep->to) | |
3368 | op->can_eliminate = 0; | |
3369 | } | |
3370 | } | |
3371 | ||
3372 | /* See if any registers that we thought we could eliminate the previous | |
3373 | time are no longer eliminable. If so, something has changed and we | |
3374 | must spill the register. Also, recompute the number of eliminable | |
3375 | registers and see if the frame pointer is needed; it is if there is | |
3376 | no elimination of the frame pointer that we can perform. */ | |
3377 | ||
3378 | frame_pointer_needed = 1; | |
3379 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3380 | { | |
3381 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3382 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3383 | frame_pointer_needed = 0; | |
3384 | ||
3385 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3386 | { | |
3387 | ep->can_eliminate_previous = 0; | |
3388 | SET_HARD_REG_BIT (*pset, ep->from); | |
3389 | num_eliminable--; | |
3390 | } | |
3391 | } | |
3392 | ||
3393 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3394 | /* If we didn't need a frame pointer last time, but we do now, spill | |
3395 | the hard frame pointer. */ | |
3396 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3397 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
3398 | #endif | |
3399 | } | |
3400 | ||
3401 | /* Initialize the table of registers to eliminate. */ | |
1d813780 | 3402 | |
09dd1133 BS |
3403 | static void |
3404 | init_elim_table () | |
3405 | { | |
3406 | struct elim_table *ep; | |
590cf94d KG |
3407 | #ifdef ELIMINABLE_REGS |
3408 | struct elim_table_1 *ep1; | |
3409 | #endif | |
09dd1133 | 3410 | |
590cf94d | 3411 | if (!reg_eliminate) |
ad85216e | 3412 | reg_eliminate = (struct elim_table *) |
1d7254c5 | 3413 | xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); |
05d10675 | 3414 | |
09dd1133 BS |
3415 | /* Does this function require a frame pointer? */ |
3416 | ||
3417 | frame_pointer_needed = (! flag_omit_frame_pointer | |
3418 | #ifdef EXIT_IGNORE_STACK | |
3419 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
3420 | and restore sp for alloca. So we can't eliminate | |
3421 | the frame pointer in that case. At some point, | |
3422 | we should improve this by emitting the | |
3423 | sp-adjusting insns for this case. */ | |
3424 | || (current_function_calls_alloca | |
3425 | && EXIT_IGNORE_STACK) | |
3426 | #endif | |
3427 | || FRAME_POINTER_REQUIRED); | |
3428 | ||
3429 | num_eliminable = 0; | |
3430 | ||
3431 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3432 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3433 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3434 | { |
590cf94d KG |
3435 | ep->from = ep1->from; |
3436 | ep->to = ep1->to; | |
09dd1133 BS |
3437 | ep->can_eliminate = ep->can_eliminate_previous |
3438 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3439 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3440 | } | |
3441 | #else | |
590cf94d KG |
3442 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3443 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3444 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3445 | = ! frame_pointer_needed; | |
3446 | #endif | |
3447 | ||
3448 | /* Count the number of eliminable registers and build the FROM and TO | |
3449 | REG rtx's. Note that code in gen_rtx will cause, e.g., | |
3450 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. | |
3451 | We depend on this. */ | |
3452 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3453 | { | |
3454 | num_eliminable += ep->can_eliminate; | |
3455 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3456 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3457 | } | |
3458 | } | |
32131a9c RK |
3459 | \f |
3460 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3461 | |
3462 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3463 | because we found we can't eliminate some register. In the case, no pseudos | |
3464 | are allowed to be in the register, even if they are only in a block that | |
3465 | doesn't require spill registers, unlike the case when we are spilling this | |
3466 | hard reg to produce another spill register. | |
3467 | ||
3468 | Return nonzero if any pseudos needed to be kicked out. */ | |
3469 | ||
03acd8f8 | 3470 | static void |
e04ca094 | 3471 | spill_hard_reg (regno, cant_eliminate) |
770ae6cc | 3472 | unsigned int regno; |
32131a9c RK |
3473 | int cant_eliminate; |
3474 | { | |
32131a9c RK |
3475 | register int i; |
3476 | ||
9ff3516a | 3477 | if (cant_eliminate) |
03acd8f8 BS |
3478 | { |
3479 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3480 | regs_ever_live[regno] = 1; | |
3481 | } | |
9ff3516a | 3482 | |
32131a9c RK |
3483 | /* Spill every pseudo reg that was allocated to this reg |
3484 | or to something that overlaps this reg. */ | |
3485 | ||
3486 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3487 | if (reg_renumber[i] >= 0 | |
770ae6cc RK |
3488 | && (unsigned int) reg_renumber[i] <= regno |
3489 | && ((unsigned int) reg_renumber[i] | |
3490 | + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i], | |
32131a9c RK |
3491 | PSEUDO_REGNO_MODE (i)) |
3492 | > regno)) | |
f5d8c9f4 | 3493 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3494 | } |
32131a9c | 3495 | |
03acd8f8 BS |
3496 | /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET |
3497 | from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ | |
770ae6cc | 3498 | |
03acd8f8 BS |
3499 | static void |
3500 | ior_hard_reg_set (set1, set2) | |
3501 | HARD_REG_SET *set1, *set2; | |
3502 | { | |
3503 | IOR_HARD_REG_SET (*set1, *set2); | |
3504 | } | |
05d10675 | 3505 | |
03acd8f8 BS |
3506 | /* After find_reload_regs has been run for all insn that need reloads, |
3507 | and/or spill_hard_regs was called, this function is used to actually | |
3508 | spill pseudo registers and try to reallocate them. It also sets up the | |
3509 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3510 | |
03acd8f8 | 3511 | static int |
e04ca094 | 3512 | finish_spills (global) |
03acd8f8 | 3513 | int global; |
03acd8f8 BS |
3514 | { |
3515 | struct insn_chain *chain; | |
3516 | int something_changed = 0; | |
3517 | int i; | |
3518 | ||
3519 | /* Build the spill_regs array for the function. */ | |
3520 | /* If there are some registers still to eliminate and one of the spill regs | |
3521 | wasn't ever used before, additional stack space may have to be | |
3522 | allocated to store this register. Thus, we may have changed the offset | |
3523 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3524 | |
03acd8f8 BS |
3525 | One might think that we need only set VAL to 1 if this is a call-used |
3526 | register. However, the set of registers that must be saved by the | |
3527 | prologue is not identical to the call-used set. For example, the | |
3528 | register used by the call insn for the return PC is a call-used register, | |
3529 | but must be saved by the prologue. */ | |
3530 | ||
3531 | n_spills = 0; | |
3532 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3533 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3534 | { | |
3535 | spill_reg_order[i] = n_spills; | |
3536 | spill_regs[n_spills++] = i; | |
3537 | if (num_eliminable && ! regs_ever_live[i]) | |
3538 | something_changed = 1; | |
3539 | regs_ever_live[i] = 1; | |
3540 | } | |
3541 | else | |
3542 | spill_reg_order[i] = -1; | |
3543 | ||
efc9bd41 RK |
3544 | EXECUTE_IF_SET_IN_REG_SET |
3545 | (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, | |
3546 | { | |
3547 | /* Record the current hard register the pseudo is allocated to in | |
3548 | pseudo_previous_regs so we avoid reallocating it to the same | |
3549 | hard reg in a later pass. */ | |
3550 | if (reg_renumber[i] < 0) | |
3551 | abort (); | |
3552 | ||
3553 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3554 | /* Mark it as no longer having a hard register home. */ | |
3555 | reg_renumber[i] = -1; | |
3556 | /* We will need to scan everything again. */ | |
3557 | something_changed = 1; | |
3558 | }); | |
7609e720 | 3559 | |
03acd8f8 BS |
3560 | /* Retry global register allocation if possible. */ |
3561 | if (global) | |
3562 | { | |
961192e1 | 3563 | memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3564 | /* For every insn that needs reloads, set the registers used as spill |
3565 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3566 | insn. */ | |
3567 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3568 | { | |
3569 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3570 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3571 | { |
3572 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3573 | &chain->used_spill_regs); | |
3574 | }); | |
3575 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3576 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3577 | { |
3578 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3579 | &chain->used_spill_regs); | |
3580 | }); | |
3581 | } | |
7609e720 | 3582 | |
03acd8f8 BS |
3583 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3584 | various reg sets that indicate which hard regs can't be used, | |
3585 | and call retry_global_alloc. | |
05d10675 | 3586 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 BS |
3587 | get a new hard register. */ |
3588 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3589 | if (reg_old_renumber[i] != reg_renumber[i]) | |
32131a9c | 3590 | { |
03acd8f8 BS |
3591 | HARD_REG_SET forbidden; |
3592 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3593 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3594 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3595 | retry_global_alloc (i, forbidden); | |
3596 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3597 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3598 | } |
03acd8f8 | 3599 | } |
7609e720 | 3600 | |
03acd8f8 BS |
3601 | /* Fix up the register information in the insn chain. |
3602 | This involves deleting those of the spilled pseudos which did not get | |
3603 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3604 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3605 | { | |
03acd8f8 BS |
3606 | HARD_REG_SET used_by_pseudos; |
3607 | HARD_REG_SET used_by_pseudos2; | |
3608 | ||
239a0f5b BS |
3609 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3610 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3611 | |
3612 | /* Mark any unallocated hard regs as available for spills. That | |
3613 | makes inheritance work somewhat better. */ | |
3614 | if (chain->need_reload) | |
3615 | { | |
239a0f5b BS |
3616 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3617 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3618 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3619 | ||
3620 | /* Save the old value for the sanity test below. */ | |
3621 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3622 | ||
239a0f5b BS |
3623 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3624 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3625 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3626 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3627 | ||
3628 | /* Make sure we only enlarge the set. */ | |
3629 | GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); | |
3630 | abort (); | |
3631 | ok:; | |
3632 | } | |
7609e720 | 3633 | } |
03acd8f8 BS |
3634 | |
3635 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3636 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3637 | { | |
3638 | int regno = reg_renumber[i]; | |
3639 | if (reg_old_renumber[i] == regno) | |
3640 | continue; | |
05d10675 | 3641 | |
03acd8f8 BS |
3642 | alter_reg (i, reg_old_renumber[i]); |
3643 | reg_old_renumber[i] = regno; | |
e04ca094 | 3644 | if (rtl_dump_file) |
03acd8f8 BS |
3645 | { |
3646 | if (regno == -1) | |
e04ca094 | 3647 | fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 3648 | else |
e04ca094 | 3649 | fprintf (rtl_dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
3650 | i, reg_renumber[i]); |
3651 | } | |
3652 | } | |
3653 | ||
3654 | return something_changed; | |
7609e720 | 3655 | } |
32131a9c | 3656 | \f |
05d10675 | 3657 | /* Find all paradoxical subregs within X and update reg_max_ref_width. |
56f58d3a RK |
3658 | Also mark any hard registers used to store user variables as |
3659 | forbidden from being used for spill registers. */ | |
32131a9c RK |
3660 | |
3661 | static void | |
3662 | scan_paradoxical_subregs (x) | |
3663 | register rtx x; | |
3664 | { | |
3665 | register int i; | |
6f7d635c | 3666 | register const char *fmt; |
32131a9c RK |
3667 | register enum rtx_code code = GET_CODE (x); |
3668 | ||
3669 | switch (code) | |
3670 | { | |
56f58d3a | 3671 | case REG: |
03acd8f8 | 3672 | #if 0 |
e9a25f70 | 3673 | if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER |
f95182a4 | 3674 | && REG_USERVAR_P (x)) |
03acd8f8 BS |
3675 | SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); |
3676 | #endif | |
56f58d3a RK |
3677 | return; |
3678 | ||
32131a9c RK |
3679 | case CONST_INT: |
3680 | case CONST: | |
3681 | case SYMBOL_REF: | |
3682 | case LABEL_REF: | |
3683 | case CONST_DOUBLE: | |
3684 | case CC0: | |
3685 | case PC: | |
32131a9c RK |
3686 | case USE: |
3687 | case CLOBBER: | |
3688 | return; | |
3689 | ||
3690 | case SUBREG: | |
3691 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3692 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3693 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3694 | = GET_MODE_SIZE (GET_MODE (x)); | |
3695 | return; | |
05d10675 | 3696 | |
e9a25f70 JL |
3697 | default: |
3698 | break; | |
32131a9c RK |
3699 | } |
3700 | ||
3701 | fmt = GET_RTX_FORMAT (code); | |
3702 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3703 | { | |
3704 | if (fmt[i] == 'e') | |
3705 | scan_paradoxical_subregs (XEXP (x, i)); | |
3706 | else if (fmt[i] == 'E') | |
3707 | { | |
3708 | register int j; | |
1d7254c5 | 3709 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
3710 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
3711 | } | |
3712 | } | |
3713 | } | |
3714 | \f | |
32131a9c RK |
3715 | /* Reload pseudo-registers into hard regs around each insn as needed. |
3716 | Additional register load insns are output before the insn that needs it | |
3717 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3718 | ||
3719 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3720 | which registers are already available in reload registers. |
32131a9c RK |
3721 | We update these for the reloads that we perform, |
3722 | as the insns are scanned. */ | |
3723 | ||
3724 | static void | |
e04ca094 | 3725 | reload_as_needed (live_known) |
32131a9c RK |
3726 | int live_known; |
3727 | { | |
7609e720 | 3728 | struct insn_chain *chain; |
553687c9 | 3729 | #if defined (AUTO_INC_DEC) |
32131a9c | 3730 | register int i; |
973838fd | 3731 | #endif |
32131a9c | 3732 | rtx x; |
32131a9c | 3733 | |
961192e1 JM |
3734 | memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx); |
3735 | memset ((char *) spill_reg_store, 0, sizeof spill_reg_store); | |
ff154f78 MM |
3736 | reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
3737 | reg_has_output_reload = (char *) xmalloc (max_regno); | |
e6e52be0 | 3738 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c | 3739 | |
1f3b1e1a | 3740 | set_initial_elim_offsets (); |
32131a9c | 3741 | |
7609e720 | 3742 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 3743 | { |
03acd8f8 | 3744 | rtx prev; |
7609e720 BS |
3745 | rtx insn = chain->insn; |
3746 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
3747 | |
3748 | /* If we pass a label, copy the offsets from the label information | |
3749 | into the current offsets of each elimination. */ | |
3750 | if (GET_CODE (insn) == CODE_LABEL) | |
1f3b1e1a | 3751 | set_offsets_for_label (insn); |
32131a9c | 3752 | |
2c3c49de | 3753 | else if (INSN_P (insn)) |
32131a9c | 3754 | { |
0639444f | 3755 | rtx oldpat = PATTERN (insn); |
32131a9c | 3756 | |
2758481d RS |
3757 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3758 | references to eliminable registers have been removed. */ | |
3759 | ||
3760 | if ((GET_CODE (PATTERN (insn)) == USE | |
3761 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3762 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3763 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3764 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 3765 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 3766 | NULL_RTX); |
2758481d | 3767 | |
32131a9c RK |
3768 | /* If we need to do register elimination processing, do so. |
3769 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 3770 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
3771 | { |
3772 | eliminate_regs_in_insn (insn, 1); | |
3773 | if (GET_CODE (insn) == NOTE) | |
cb2afeb3 R |
3774 | { |
3775 | update_eliminable_offsets (); | |
3776 | continue; | |
3777 | } | |
32131a9c RK |
3778 | } |
3779 | ||
7609e720 BS |
3780 | /* If need_elim is nonzero but need_reload is zero, one might think |
3781 | that we could simply set n_reloads to 0. However, find_reloads | |
3782 | could have done some manipulation of the insn (such as swapping | |
3783 | commutative operands), and these manipulations are lost during | |
3784 | the first pass for every insn that needs register elimination. | |
3785 | So the actions of find_reloads must be redone here. */ | |
3786 | ||
03acd8f8 BS |
3787 | if (! chain->need_elim && ! chain->need_reload |
3788 | && ! chain->need_operand_change) | |
32131a9c RK |
3789 | n_reloads = 0; |
3790 | /* First find the pseudo regs that must be reloaded for this insn. | |
3791 | This info is returned in the tables reload_... (see reload.h). | |
3792 | Also modify the body of INSN by substituting RELOAD | |
3793 | rtx's for those pseudo regs. */ | |
3794 | else | |
3795 | { | |
961192e1 | 3796 | memset (reg_has_output_reload, 0, max_regno); |
32131a9c RK |
3797 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
3798 | ||
3799 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3800 | spill_reg_order); | |
3801 | } | |
3802 | ||
dd6acd1b | 3803 | if (num_eliminable && chain->need_elim) |
cb2afeb3 R |
3804 | update_eliminable_offsets (); |
3805 | ||
32131a9c RK |
3806 | if (n_reloads > 0) |
3807 | { | |
cb2afeb3 | 3808 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 3809 | rtx p; |
32131a9c | 3810 | |
cb2afeb3 R |
3811 | prev = PREV_INSN (insn); |
3812 | ||
32131a9c RK |
3813 | /* Now compute which reload regs to reload them into. Perhaps |
3814 | reusing reload regs from previous insns, or else output | |
3815 | load insns to reload them. Maybe output store insns too. | |
3816 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 3817 | choose_reload_regs (chain); |
32131a9c | 3818 | |
05d10675 | 3819 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
3820 | increasing the number of spill registers needed but now |
3821 | discover can be safely merged. */ | |
f95182a4 ILT |
3822 | if (SMALL_REGISTER_CLASSES) |
3823 | merge_assigned_reloads (insn); | |
546b63fb | 3824 | |
32131a9c RK |
3825 | /* Generate the insns to reload operands into or out of |
3826 | their reload regs. */ | |
e04ca094 | 3827 | emit_reload_insns (chain); |
32131a9c RK |
3828 | |
3829 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3830 | into the insn's body (or perhaps into the bodies of other | |
3831 | load and store insn that we just made for reloading | |
3832 | and that we moved the structure into). */ | |
3833 | subst_reloads (); | |
3c3eeea6 RK |
3834 | |
3835 | /* If this was an ASM, make sure that all the reload insns | |
3836 | we have generated are valid. If not, give an error | |
3837 | and delete them. */ | |
3838 | ||
3839 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3840 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 3841 | if (p != insn && INSN_P (p) |
3c3eeea6 | 3842 | && (recog_memoized (p) < 0 |
0eadeb15 | 3843 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
3844 | { |
3845 | error_for_asm (insn, | |
3846 | "`asm' operand requires impossible reload"); | |
3847 | PUT_CODE (p, NOTE); | |
3848 | NOTE_SOURCE_FILE (p) = 0; | |
3849 | NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; | |
3850 | } | |
32131a9c RK |
3851 | } |
3852 | /* Any previously reloaded spilled pseudo reg, stored in this insn, | |
3853 | is no longer validly lying around to save a future reload. | |
3854 | Note that this does not detect pseudos that were reloaded | |
3855 | for this insn in order to be stored in | |
3856 | (obeying register constraints). That is correct; such reload | |
3857 | registers ARE still valid. */ | |
84832317 | 3858 | note_stores (oldpat, forget_old_reloads_1, NULL); |
32131a9c RK |
3859 | |
3860 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3861 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 3862 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
32131a9c | 3863 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 3864 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
3865 | |
3866 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
3867 | /* Likewise for regs altered by auto-increment in this insn. |
3868 | REG_INC notes have been changed by reloading: | |
3869 | find_reloads_address_1 records substitutions for them, | |
3870 | which have been performed by subst_reloads above. */ | |
3871 | for (i = n_reloads - 1; i >= 0; i--) | |
3872 | { | |
eceef4c9 | 3873 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
3874 | if (in_reg) |
3875 | { | |
3876 | enum rtx_code code = GET_CODE (in_reg); | |
3877 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
3878 | with the same value as the stack slot, but that doesn't | |
3879 | hold true for POST_INC / POST_DEC. Either we have to | |
3880 | convert the memory access to a true POST_INC / POST_DEC, | |
3881 | or we can't use the reload register for inheritance. */ | |
3882 | if ((code == POST_INC || code == POST_DEC) | |
3883 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3884 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
3885 | /* Make sure it is the inc/dec pseudo, and not |
3886 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3887 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 3888 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 3889 | |
cb2afeb3 | 3890 | { |
eceef4c9 | 3891 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
3892 | enum machine_mode mode = GET_MODE (reload_reg); |
3893 | int n = 0; | |
3894 | rtx p; | |
3895 | ||
3896 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
3897 | { | |
3898 | /* We really want to ignore REG_INC notes here, so | |
3899 | use PATTERN (p) as argument to reg_set_p . */ | |
3900 | if (reg_set_p (reload_reg, PATTERN (p))) | |
3901 | break; | |
4b983fdc | 3902 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
3903 | if (! n) |
3904 | continue; | |
3905 | if (n == 1) | |
f67c2384 JL |
3906 | { |
3907 | n = validate_replace_rtx (reload_reg, | |
3908 | gen_rtx (code, mode, | |
3909 | reload_reg), | |
3910 | p); | |
3911 | ||
3912 | /* We must also verify that the constraints | |
3913 | are met after the replacement. */ | |
3914 | extract_insn (p); | |
3915 | if (n) | |
3916 | n = constrain_operands (1); | |
3917 | else | |
3918 | break; | |
3919 | ||
3920 | /* If the constraints were not met, then | |
3921 | undo the replacement. */ | |
3922 | if (!n) | |
3923 | { | |
3924 | validate_replace_rtx (gen_rtx (code, mode, | |
3925 | reload_reg), | |
3926 | reload_reg, p); | |
3927 | break; | |
3928 | } | |
05d10675 | 3929 | |
f67c2384 | 3930 | } |
cb2afeb3 R |
3931 | break; |
3932 | } | |
3933 | if (n == 1) | |
02eb1393 R |
3934 | { |
3935 | REG_NOTES (p) | |
3936 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
3937 | REG_NOTES (p)); | |
3938 | /* Mark this as having an output reload so that the | |
3939 | REG_INC processing code below won't invalidate | |
3940 | the reload for inheritance. */ | |
3941 | SET_HARD_REG_BIT (reg_is_output_reload, | |
3942 | REGNO (reload_reg)); | |
3943 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; | |
3944 | } | |
cb2afeb3 | 3945 | else |
1d7254c5 | 3946 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 3947 | NULL); |
cb2afeb3 | 3948 | } |
02eb1393 R |
3949 | else if ((code == PRE_INC || code == PRE_DEC) |
3950 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3951 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
3952 | /* Make sure it is the inc/dec pseudo, and not |
3953 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3954 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
3955 | == REGNO (XEXP (in_reg, 0)))) |
3956 | { | |
3957 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 3958 | REGNO (rld[i].reg_rtx)); |
02eb1393 R |
3959 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; |
3960 | } | |
cb2afeb3 R |
3961 | } |
3962 | } | |
02eb1393 R |
3963 | /* If a pseudo that got a hard register is auto-incremented, |
3964 | we must purge records of copying it into pseudos without | |
3965 | hard registers. */ | |
32131a9c RK |
3966 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
3967 | if (REG_NOTE_KIND (x) == REG_INC) | |
3968 | { | |
3969 | /* See if this pseudo reg was reloaded in this insn. | |
3970 | If so, its last-reload info is still valid | |
3971 | because it is based on this insn's reload. */ | |
3972 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 3973 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
3974 | break; |
3975 | ||
08fb99fa | 3976 | if (i == n_reloads) |
84832317 | 3977 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
3978 | } |
3979 | #endif | |
3980 | } | |
3981 | /* A reload reg's contents are unknown after a label. */ | |
3982 | if (GET_CODE (insn) == CODE_LABEL) | |
e6e52be0 | 3983 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
3984 | |
3985 | /* Don't assume a reload reg is still good after a call insn | |
3986 | if it is a call-used reg. */ | |
546b63fb | 3987 | else if (GET_CODE (insn) == CALL_INSN) |
e6e52be0 | 3988 | AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set); |
32131a9c | 3989 | } |
ff154f78 MM |
3990 | |
3991 | /* Clean up. */ | |
3992 | free (reg_last_reload_reg); | |
3993 | free (reg_has_output_reload); | |
32131a9c RK |
3994 | } |
3995 | ||
3996 | /* Discard all record of any value reloaded from X, | |
3997 | or reloaded in X from someplace else; | |
3998 | unless X is an output reload reg of the current insn. | |
3999 | ||
4000 | X may be a hard reg (the reload reg) | |
4001 | or it may be a pseudo reg that was reloaded from. */ | |
4002 | ||
4003 | static void | |
84832317 | 4004 | forget_old_reloads_1 (x, ignored, data) |
32131a9c | 4005 | rtx x; |
487a6e06 | 4006 | rtx ignored ATTRIBUTE_UNUSED; |
84832317 | 4007 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 4008 | { |
770ae6cc RK |
4009 | unsigned int regno; |
4010 | unsigned int nr; | |
0a2e51a9 RS |
4011 | int offset = 0; |
4012 | ||
4013 | /* note_stores does give us subregs of hard regs. */ | |
4014 | while (GET_CODE (x) == SUBREG) | |
4015 | { | |
4016 | offset += SUBREG_WORD (x); | |
4017 | x = SUBREG_REG (x); | |
4018 | } | |
32131a9c RK |
4019 | |
4020 | if (GET_CODE (x) != REG) | |
4021 | return; | |
4022 | ||
0a2e51a9 | 4023 | regno = REGNO (x) + offset; |
32131a9c RK |
4024 | |
4025 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4026 | nr = 1; | |
4027 | else | |
4028 | { | |
770ae6cc RK |
4029 | unsigned int i; |
4030 | ||
32131a9c RK |
4031 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
4032 | /* Storing into a spilled-reg invalidates its contents. | |
4033 | This can happen if a block-local pseudo is allocated to that reg | |
4034 | and it wasn't spilled because this block's total need is 0. | |
4035 | Then some insn might have an optional reload and use this reg. */ | |
4036 | for (i = 0; i < nr; i++) | |
e6e52be0 R |
4037 | /* But don't do this if the reg actually serves as an output |
4038 | reload reg in the current instruction. */ | |
4039 | if (n_reloads == 0 | |
4040 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
5d77a50c BS |
4041 | { |
4042 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
4043 | spill_reg_store[regno + i] = 0; | |
4044 | } | |
32131a9c RK |
4045 | } |
4046 | ||
4047 | /* Since value of X has changed, | |
4048 | forget any value previously copied from it. */ | |
4049 | ||
4050 | while (nr-- > 0) | |
4051 | /* But don't forget a copy if this is the output reload | |
4052 | that establishes the copy's validity. */ | |
4053 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
4054 | reg_last_reload_reg[regno + nr] = 0; | |
4055 | } | |
4056 | \f | |
32131a9c RK |
4057 | /* The following HARD_REG_SETs indicate when each hard register is |
4058 | used for a reload of various parts of the current insn. */ | |
4059 | ||
9e3a9cf2 BS |
4060 | /* If reg is unavailable for all reloads. */ |
4061 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4062 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4063 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4064 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4065 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4066 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4067 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4068 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4069 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4070 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4071 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4072 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4073 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4074 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4075 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4076 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4077 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4078 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4079 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4080 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4081 | static HARD_REG_SET reload_reg_used_in_insn; | |
4082 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4083 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4084 | |
4085 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4086 | static HARD_REG_SET reload_reg_used_at_all; | |
4087 | ||
be7ae2a4 RK |
4088 | /* If reg is use as an inherited reload. We just mark the first register |
4089 | in the group. */ | |
4090 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4091 | ||
f1db3576 JL |
4092 | /* Records which hard regs are used in any way, either as explicit use or |
4093 | by being allocated to a pseudo during any point of the current insn. */ | |
4094 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4095 | |
546b63fb RK |
4096 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4097 | TYPE. MODE is used to indicate how many consecutive regs are | |
4098 | actually used. */ | |
32131a9c RK |
4099 | |
4100 | static void | |
546b63fb | 4101 | mark_reload_reg_in_use (regno, opnum, type, mode) |
770ae6cc | 4102 | unsigned int regno; |
546b63fb RK |
4103 | int opnum; |
4104 | enum reload_type type; | |
32131a9c RK |
4105 | enum machine_mode mode; |
4106 | { | |
770ae6cc RK |
4107 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4108 | unsigned int i; | |
32131a9c RK |
4109 | |
4110 | for (i = regno; i < nregs + regno; i++) | |
4111 | { | |
546b63fb | 4112 | switch (type) |
32131a9c RK |
4113 | { |
4114 | case RELOAD_OTHER: | |
4115 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4116 | break; | |
4117 | ||
546b63fb RK |
4118 | case RELOAD_FOR_INPUT_ADDRESS: |
4119 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4120 | break; |
4121 | ||
47c8cf91 ILT |
4122 | case RELOAD_FOR_INPADDR_ADDRESS: |
4123 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4124 | break; | |
4125 | ||
546b63fb RK |
4126 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4127 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4128 | break; |
4129 | ||
47c8cf91 ILT |
4130 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4131 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4132 | break; | |
4133 | ||
32131a9c RK |
4134 | case RELOAD_FOR_OPERAND_ADDRESS: |
4135 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4136 | break; | |
4137 | ||
893bc853 RK |
4138 | case RELOAD_FOR_OPADDR_ADDR: |
4139 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4140 | break; | |
4141 | ||
546b63fb RK |
4142 | case RELOAD_FOR_OTHER_ADDRESS: |
4143 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4144 | break; | |
4145 | ||
32131a9c | 4146 | case RELOAD_FOR_INPUT: |
546b63fb | 4147 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4148 | break; |
4149 | ||
4150 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4151 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4152 | break; | |
4153 | ||
4154 | case RELOAD_FOR_INSN: | |
4155 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4156 | break; |
4157 | } | |
4158 | ||
4159 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4160 | } | |
4161 | } | |
4162 | ||
be7ae2a4 RK |
4163 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4164 | ||
4165 | static void | |
4166 | clear_reload_reg_in_use (regno, opnum, type, mode) | |
770ae6cc | 4167 | unsigned int regno; |
be7ae2a4 RK |
4168 | int opnum; |
4169 | enum reload_type type; | |
4170 | enum machine_mode mode; | |
4171 | { | |
770ae6cc RK |
4172 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4173 | unsigned int start_regno, end_regno, r; | |
be7ae2a4 | 4174 | int i; |
cb2afeb3 R |
4175 | /* A complication is that for some reload types, inheritance might |
4176 | allow multiple reloads of the same types to share a reload register. | |
4177 | We set check_opnum if we have to check only reloads with the same | |
4178 | operand number, and check_any if we have to check all reloads. */ | |
4179 | int check_opnum = 0; | |
4180 | int check_any = 0; | |
4181 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4182 | |
cb2afeb3 | 4183 | switch (type) |
be7ae2a4 | 4184 | { |
cb2afeb3 R |
4185 | case RELOAD_OTHER: |
4186 | used_in_set = &reload_reg_used; | |
4187 | break; | |
be7ae2a4 | 4188 | |
cb2afeb3 R |
4189 | case RELOAD_FOR_INPUT_ADDRESS: |
4190 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4191 | break; | |
be7ae2a4 | 4192 | |
cb2afeb3 R |
4193 | case RELOAD_FOR_INPADDR_ADDRESS: |
4194 | check_opnum = 1; | |
4195 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4196 | break; | |
47c8cf91 | 4197 | |
cb2afeb3 R |
4198 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4199 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4200 | break; | |
be7ae2a4 | 4201 | |
cb2afeb3 R |
4202 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4203 | check_opnum = 1; | |
4204 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4205 | break; | |
47c8cf91 | 4206 | |
cb2afeb3 R |
4207 | case RELOAD_FOR_OPERAND_ADDRESS: |
4208 | used_in_set = &reload_reg_used_in_op_addr; | |
4209 | break; | |
be7ae2a4 | 4210 | |
cb2afeb3 R |
4211 | case RELOAD_FOR_OPADDR_ADDR: |
4212 | check_any = 1; | |
4213 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4214 | break; | |
893bc853 | 4215 | |
cb2afeb3 R |
4216 | case RELOAD_FOR_OTHER_ADDRESS: |
4217 | used_in_set = &reload_reg_used_in_other_addr; | |
4218 | check_any = 1; | |
4219 | break; | |
be7ae2a4 | 4220 | |
cb2afeb3 R |
4221 | case RELOAD_FOR_INPUT: |
4222 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4223 | break; | |
be7ae2a4 | 4224 | |
cb2afeb3 R |
4225 | case RELOAD_FOR_OUTPUT: |
4226 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4227 | break; | |
be7ae2a4 | 4228 | |
cb2afeb3 R |
4229 | case RELOAD_FOR_INSN: |
4230 | used_in_set = &reload_reg_used_in_insn; | |
4231 | break; | |
4232 | default: | |
4233 | abort (); | |
4234 | } | |
4235 | /* We resolve conflicts with remaining reloads of the same type by | |
4236 | excluding the intervals of of reload registers by them from the | |
4237 | interval of freed reload registers. Since we only keep track of | |
4238 | one set of interval bounds, we might have to exclude somewhat | |
4239 | more then what would be necessary if we used a HARD_REG_SET here. | |
4240 | But this should only happen very infrequently, so there should | |
4241 | be no reason to worry about it. */ | |
05d10675 | 4242 | |
cb2afeb3 R |
4243 | start_regno = regno; |
4244 | end_regno = regno + nregs; | |
4245 | if (check_opnum || check_any) | |
4246 | { | |
4247 | for (i = n_reloads - 1; i >= 0; i--) | |
4248 | { | |
eceef4c9 BS |
4249 | if (rld[i].when_needed == type |
4250 | && (check_any || rld[i].opnum == opnum) | |
4251 | && rld[i].reg_rtx) | |
cb2afeb3 | 4252 | { |
770ae6cc RK |
4253 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4254 | unsigned int conflict_end | |
cb2afeb3 | 4255 | = (conflict_start |
8ec450a4 | 4256 | + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); |
cb2afeb3 R |
4257 | |
4258 | /* If there is an overlap with the first to-be-freed register, | |
4259 | adjust the interval start. */ | |
4260 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4261 | start_regno = conflict_end; | |
4262 | /* Otherwise, if there is a conflict with one of the other | |
4263 | to-be-freed registers, adjust the interval end. */ | |
4264 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4265 | end_regno = conflict_start; | |
4266 | } | |
be7ae2a4 RK |
4267 | } |
4268 | } | |
770ae6cc RK |
4269 | |
4270 | for (r = start_regno; r < end_regno; r++) | |
4271 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4272 | } |
4273 | ||
32131a9c | 4274 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4275 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4276 | |
4277 | static int | |
546b63fb | 4278 | reload_reg_free_p (regno, opnum, type) |
770ae6cc | 4279 | unsigned int regno; |
546b63fb RK |
4280 | int opnum; |
4281 | enum reload_type type; | |
32131a9c | 4282 | { |
546b63fb RK |
4283 | int i; |
4284 | ||
2edc8d65 | 4285 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4286 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4287 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4288 | return 0; |
546b63fb RK |
4289 | |
4290 | switch (type) | |
32131a9c RK |
4291 | { |
4292 | case RELOAD_OTHER: | |
2edc8d65 RK |
4293 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4294 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 RK |
4295 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4296 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4297 | return 0; | |
4298 | ||
4299 | for (i = 0; i < reload_n_operands; i++) | |
4300 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4301 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4302 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4303 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4304 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4305 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4306 | return 0; | |
4307 | ||
4308 | return 1; | |
32131a9c | 4309 | |
32131a9c | 4310 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4311 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4312 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4313 | return 0; | |
4314 | ||
893bc853 RK |
4315 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4316 | return 0; | |
4317 | ||
546b63fb RK |
4318 | /* If it is used for some other input, can't use it. */ |
4319 | for (i = 0; i < reload_n_operands; i++) | |
4320 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4321 | return 0; | |
4322 | ||
4323 | /* If it is used in a later operand's address, can't use it. */ | |
4324 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4325 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4326 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4327 | return 0; |
4328 | ||
4329 | return 1; | |
4330 | ||
4331 | case RELOAD_FOR_INPUT_ADDRESS: | |
4332 | /* Can't use a register if it is used for an input address for this | |
4333 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4334 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4335 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4336 | return 0; | |
4337 | ||
4338 | for (i = 0; i < opnum; i++) | |
4339 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4340 | return 0; | |
4341 | ||
4342 | return 1; | |
4343 | ||
4344 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4345 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4346 | for this operand or used as an input in an earlier |
4347 | one. */ | |
47c8cf91 | 4348 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4349 | return 0; |
4350 | ||
4351 | for (i = 0; i < opnum; i++) | |
4352 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4353 | return 0; | |
4354 | ||
4355 | return 1; | |
4356 | ||
4357 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4358 | /* Can't use a register if it is used for an output address for this | |
4359 | operand or used as an output in this or a later operand. */ | |
4360 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) | |
4361 | return 0; | |
4362 | ||
4363 | for (i = opnum; i < reload_n_operands; i++) | |
4364 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4365 | return 0; | |
4366 | ||
4367 | return 1; | |
4368 | ||
47c8cf91 ILT |
4369 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4370 | /* Can't use a register if it is used for an output address | |
05d10675 BS |
4371 | for this operand or used as an output in this or a |
4372 | later operand. */ | |
47c8cf91 ILT |
4373 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4374 | return 0; | |
4375 | ||
4376 | for (i = opnum; i < reload_n_operands; i++) | |
4377 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4378 | return 0; | |
4379 | ||
4380 | return 1; | |
4381 | ||
32131a9c | 4382 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4383 | for (i = 0; i < reload_n_operands; i++) |
4384 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4385 | return 0; | |
4386 | ||
4387 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4388 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4389 | ||
893bc853 RK |
4390 | case RELOAD_FOR_OPADDR_ADDR: |
4391 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4392 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4393 | return 0; | |
893bc853 | 4394 | |
a94ce333 | 4395 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4396 | |
32131a9c | 4397 | case RELOAD_FOR_OUTPUT: |
546b63fb RK |
4398 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
4399 | outputs, or an operand address for this or an earlier output. */ | |
4400 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4401 | return 0; | |
4402 | ||
4403 | for (i = 0; i < reload_n_operands; i++) | |
4404 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4405 | return 0; | |
4406 | ||
4407 | for (i = 0; i <= opnum; i++) | |
47c8cf91 ILT |
4408 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4409 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4410 | return 0; |
4411 | ||
4412 | return 1; | |
4413 | ||
4414 | case RELOAD_FOR_INSN: | |
4415 | for (i = 0; i < reload_n_operands; i++) | |
4416 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4417 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4418 | return 0; | |
4419 | ||
4420 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4421 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4422 | ||
4423 | case RELOAD_FOR_OTHER_ADDRESS: | |
4424 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4425 | } |
4426 | abort (); | |
4427 | } | |
4428 | ||
32131a9c | 4429 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4430 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4431 | is still available in REGNO at the end of the insn. |
4432 | ||
4433 | We can assume that the reload reg was already tested for availability | |
4434 | at the time it is needed, and we should not check this again, | |
4435 | in case the reg has already been marked in use. */ | |
4436 | ||
4437 | static int | |
546b63fb | 4438 | reload_reg_reaches_end_p (regno, opnum, type) |
770ae6cc | 4439 | unsigned int regno; |
546b63fb RK |
4440 | int opnum; |
4441 | enum reload_type type; | |
32131a9c | 4442 | { |
546b63fb RK |
4443 | int i; |
4444 | ||
4445 | switch (type) | |
32131a9c RK |
4446 | { |
4447 | case RELOAD_OTHER: | |
4448 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4449 | its value must reach the end. */ | |
4450 | return 1; | |
4451 | ||
4452 | /* If this use is for part of the insn, | |
05d10675 | 4453 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4454 | Just like the above function, don't try to do this with lots |
4455 | of fallthroughs. */ | |
4456 | ||
4457 | case RELOAD_FOR_OTHER_ADDRESS: | |
4458 | /* Here we check for everything else, since these don't conflict | |
4459 | with anything else and everything comes later. */ | |
4460 | ||
4461 | for (i = 0; i < reload_n_operands; i++) | |
4462 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4463 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4464 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4465 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4466 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4467 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4468 | return 0; | |
4469 | ||
4470 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4471 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4472 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4473 | ||
4474 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4475 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4476 | /* Similar, except that we check only for this and subsequent inputs |
4477 | and the address of only subsequent inputs and we do not need | |
4478 | to check for RELOAD_OTHER objects since they are known not to | |
4479 | conflict. */ | |
4480 | ||
4481 | for (i = opnum; i < reload_n_operands; i++) | |
4482 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4483 | return 0; | |
4484 | ||
4485 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4486 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4487 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4488 | return 0; |
4489 | ||
4490 | for (i = 0; i < reload_n_operands; i++) | |
4491 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4492 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4493 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4494 | return 0; | |
4495 | ||
893bc853 RK |
4496 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4497 | return 0; | |
4498 | ||
2af88768 GK |
4499 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4500 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4501 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 4502 | |
32131a9c | 4503 | case RELOAD_FOR_INPUT: |
546b63fb | 4504 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4505 | both input and input address and we do not check for |
546b63fb RK |
4506 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4507 | would conflict. */ | |
4508 | ||
4509 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4510 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4511 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4512 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4513 | return 0; | |
4514 | ||
0f41302f | 4515 | /* ... fall through ... */ |
546b63fb | 4516 | |
32131a9c | 4517 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4518 | /* Check outputs and their addresses. */ |
4519 | ||
4520 | for (i = 0; i < reload_n_operands; i++) | |
4521 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4522 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4523 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4524 | return 0; | |
4525 | ||
2af88768 | 4526 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 4527 | |
893bc853 RK |
4528 | case RELOAD_FOR_OPADDR_ADDR: |
4529 | for (i = 0; i < reload_n_operands; i++) | |
4530 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4531 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4532 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4533 | return 0; | |
4534 | ||
2af88768 GK |
4535 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4536 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4537 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 4538 | |
546b63fb | 4539 | case RELOAD_FOR_INSN: |
893bc853 | 4540 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4541 | we need only check for output addresses. */ |
4542 | ||
4543 | opnum = -1; | |
4544 | ||
0f41302f | 4545 | /* ... fall through ... */ |
546b63fb | 4546 | |
32131a9c | 4547 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4548 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4549 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb RK |
4550 | /* We already know these can't conflict with a later output. So the |
4551 | only thing to check are later output addresses. */ | |
4552 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4553 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4554 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4555 | return 0; |
4556 | ||
32131a9c RK |
4557 | return 1; |
4558 | } | |
546b63fb | 4559 | |
32131a9c RK |
4560 | abort (); |
4561 | } | |
4562 | \f | |
351aa1c1 RK |
4563 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4564 | Return 0 otherwise. | |
4565 | ||
4566 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4567 | ||
f5963e61 | 4568 | int |
351aa1c1 RK |
4569 | reloads_conflict (r1, r2) |
4570 | int r1, r2; | |
4571 | { | |
eceef4c9 BS |
4572 | enum reload_type r1_type = rld[r1].when_needed; |
4573 | enum reload_type r2_type = rld[r2].when_needed; | |
4574 | int r1_opnum = rld[r1].opnum; | |
4575 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4576 | |
2edc8d65 RK |
4577 | /* RELOAD_OTHER conflicts with everything. */ |
4578 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4579 | return 1; |
4580 | ||
4581 | /* Otherwise, check conflicts differently for each type. */ | |
4582 | ||
4583 | switch (r1_type) | |
4584 | { | |
4585 | case RELOAD_FOR_INPUT: | |
05d10675 | 4586 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4587 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4588 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4589 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4590 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4591 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4592 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4593 | |
4594 | case RELOAD_FOR_INPUT_ADDRESS: | |
4595 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
4596 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4597 | ||
47c8cf91 ILT |
4598 | case RELOAD_FOR_INPADDR_ADDRESS: |
4599 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
4600 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4601 | ||
351aa1c1 RK |
4602 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4603 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
4604 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); | |
4605 | ||
47c8cf91 ILT |
4606 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4607 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
4608 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); | |
4609 | ||
351aa1c1 RK |
4610 | case RELOAD_FOR_OPERAND_ADDRESS: |
4611 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a94ce333 | 4612 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); |
351aa1c1 | 4613 | |
893bc853 | 4614 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 4615 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 4616 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 4617 | |
351aa1c1 RK |
4618 | case RELOAD_FOR_OUTPUT: |
4619 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
4620 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
4621 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
ca1a4af1 | 4622 | && r2_opnum <= r1_opnum)); |
351aa1c1 RK |
4623 | |
4624 | case RELOAD_FOR_INSN: | |
4625 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
4626 | || r2_type == RELOAD_FOR_INSN | |
4627 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
4628 | ||
4629 | case RELOAD_FOR_OTHER_ADDRESS: | |
4630 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
4631 | ||
adab4fc5 | 4632 | case RELOAD_OTHER: |
2edc8d65 | 4633 | return 1; |
adab4fc5 | 4634 | |
351aa1c1 RK |
4635 | default: |
4636 | abort (); | |
4637 | } | |
4638 | } | |
4639 | \f | |
32131a9c RK |
4640 | /* Indexed by reload number, 1 if incoming value |
4641 | inherited from previous insns. */ | |
4642 | char reload_inherited[MAX_RELOADS]; | |
4643 | ||
4644 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4645 | if we know it. Otherwise, this is 0. */ | |
4646 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4647 | ||
4648 | /* If non-zero, this is a place to get the value of the reload, | |
4649 | rather than using reload_in. */ | |
4650 | rtx reload_override_in[MAX_RELOADS]; | |
4651 | ||
e6e52be0 R |
4652 | /* For each reload, the hard register number of the register used, |
4653 | or -1 if we did not need a register for this reload. */ | |
32131a9c RK |
4654 | int reload_spill_index[MAX_RELOADS]; |
4655 | ||
c02cad8f | 4656 | /* Subroutine of free_for_value_p, used to check a single register. */ |
f5470689 | 4657 | |
6e684430 | 4658 | static int |
dfe96118 | 4659 | reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum, |
05d10675 | 4660 | ignore_address_reloads) |
6e684430 R |
4661 | int regno; |
4662 | int opnum; | |
4663 | enum reload_type type; | |
f5470689 R |
4664 | rtx value, out; |
4665 | int reloadnum; | |
5828374f | 4666 | int ignore_address_reloads; |
6e684430 R |
4667 | { |
4668 | int time1; | |
09a308fe R |
4669 | /* Set if we see an input reload that must not share its reload register |
4670 | with any new earlyclobber, but might otherwise share the reload | |
4671 | register with an output or input-output reload. */ | |
4672 | int check_earlyclobber = 0; | |
6e684430 | 4673 | int i; |
dfe96118 R |
4674 | int copy = 0; |
4675 | ||
9e3a9cf2 | 4676 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
4677 | return 0; |
4678 | ||
dfe96118 R |
4679 | if (out == const0_rtx) |
4680 | { | |
4681 | copy = 1; | |
4682 | out = NULL_RTX; | |
4683 | } | |
6e684430 R |
4684 | |
4685 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
4686 | new register use would overlap with the one of a previous reload | |
4687 | that is not read-only or uses a different value. | |
4688 | The 'time' used doesn't have to be linear in any shape or form, just | |
4689 | monotonic. | |
4690 | Some reload types use different 'buckets' for each operand. | |
4691 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
4692 | such reload type. |
4693 | We compute TIME1 as the time when the register for the prospective | |
4694 | new reload ceases to be live, and TIME2 for each existing | |
4695 | reload as the time when that the reload register of that reload | |
4696 | becomes live. | |
4697 | Where there is little to be gained by exact lifetime calculations, | |
4698 | we just make conservative assumptions, i.e. a longer lifetime; | |
4699 | this is done in the 'default:' cases. */ | |
6e684430 R |
4700 | switch (type) |
4701 | { | |
4702 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 4703 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 4704 | time1 = copy ? 0 : 1; |
6e684430 | 4705 | break; |
dfe96118 R |
4706 | case RELOAD_OTHER: |
4707 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
4708 | break; | |
05d10675 BS |
4709 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
4710 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
4711 | respectively, to the time values for these, we get distinct time | |
4712 | values. To get distinct time values for each operand, we have to | |
4713 | multiply opnum by at least three. We round that up to four because | |
4714 | multiply by four is often cheaper. */ | |
6e684430 | 4715 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 4716 | time1 = opnum * 4 + 2; |
6e684430 R |
4717 | break; |
4718 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
4719 | time1 = opnum * 4 + 3; |
4720 | break; | |
4721 | case RELOAD_FOR_INPUT: | |
4722 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
4723 | executes (inclusive). */ | |
4724 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 4725 | break; |
cb2afeb3 | 4726 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
4727 | /* opnum * 4 + 4 |
4728 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
4729 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
4730 | break; | |
4731 | case RELOAD_FOR_OPERAND_ADDRESS: | |
4732 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
4733 | is executed. */ | |
dfe96118 R |
4734 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
4735 | break; | |
4736 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
4737 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 4738 | break; |
6e684430 | 4739 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 4740 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
4741 | break; |
4742 | default: | |
dfe96118 | 4743 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
4744 | } |
4745 | ||
4746 | for (i = 0; i < n_reloads; i++) | |
4747 | { | |
eceef4c9 | 4748 | rtx reg = rld[i].reg_rtx; |
6e684430 R |
4749 | if (reg && GET_CODE (reg) == REG |
4750 | && ((unsigned) regno - true_regnum (reg) | |
83e0821b | 4751 | <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1) |
f5470689 | 4752 | && i != reloadnum) |
6e684430 | 4753 | { |
eceef4c9 BS |
4754 | if (! rld[i].in || ! rtx_equal_p (rld[i].in, value) |
4755 | || rld[i].out || out) | |
6e684430 | 4756 | { |
09a308fe | 4757 | int time2; |
eceef4c9 | 4758 | switch (rld[i].when_needed) |
f5470689 R |
4759 | { |
4760 | case RELOAD_FOR_OTHER_ADDRESS: | |
4761 | time2 = 0; | |
4762 | break; | |
4763 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
4764 | /* find_reloads makes sure that a |
4765 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
4766 | by at most one - the first - | |
4767 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
4768 | address reload is inherited, the address address reload | |
4769 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
4770 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
4771 | && ignore_address_reloads | |
4772 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
4773 | Then the address address is still needed to store | |
4774 | back the new address. */ | |
eceef4c9 | 4775 | && ! rld[reloadnum].out) |
cb2afeb3 | 4776 | continue; |
dfe96118 R |
4777 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
4778 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
4779 | reloads go away. */ | |
eceef4c9 | 4780 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
4781 | && ignore_address_reloads |
4782 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 4783 | && ! rld[reloadnum].out) |
dfe96118 | 4784 | continue; |
eceef4c9 | 4785 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
4786 | break; |
4787 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4788 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 4789 | && ignore_address_reloads |
eceef4c9 | 4790 | && ! rld[reloadnum].out) |
dfe96118 | 4791 | continue; |
eceef4c9 | 4792 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
4793 | break; |
4794 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 4795 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 4796 | check_earlyclobber = 1; |
f5470689 | 4797 | break; |
eceef4c9 | 4798 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 4799 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 4800 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
4801 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
4802 | && ignore_address_reloads | |
eceef4c9 | 4803 | && ! rld[reloadnum].out) |
cb2afeb3 | 4804 | continue; |
dfe96118 | 4805 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
4806 | break; |
4807 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 4808 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 4809 | check_earlyclobber = 1; |
dfe96118 R |
4810 | break; |
4811 | case RELOAD_FOR_INSN: | |
4812 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 4813 | break; |
f5470689 | 4814 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
4815 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
4816 | instruction is executed. */ | |
dfe96118 | 4817 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 4818 | break; |
05d10675 BS |
4819 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
4820 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
4821 | value. */ | |
cb2afeb3 | 4822 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
4823 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
4824 | && ignore_address_reloads | |
eceef4c9 | 4825 | && ! rld[reloadnum].out) |
cb2afeb3 | 4826 | continue; |
eceef4c9 | 4827 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 4828 | break; |
f5470689 | 4829 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 4830 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
4831 | break; |
4832 | case RELOAD_OTHER: | |
dfe96118 R |
4833 | /* If there is no conflict in the input part, handle this |
4834 | like an output reload. */ | |
eceef4c9 | 4835 | if (! rld[i].in || rtx_equal_p (rld[i].in, value)) |
f5470689 | 4836 | { |
dfe96118 | 4837 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 4838 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
4839 | if (earlyclobber_operand_p (rld[i].out)) |
4840 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 4841 | |
f5470689 R |
4842 | break; |
4843 | } | |
dfe96118 R |
4844 | time2 = 1; |
4845 | /* RELOAD_OTHER might be live beyond instruction execution, | |
4846 | but this is not obvious when we set time2 = 1. So check | |
4847 | here if there might be a problem with the new reload | |
4848 | clobbering the register used by the RELOAD_OTHER. */ | |
4849 | if (out) | |
4850 | return 0; | |
4851 | break; | |
f5470689 | 4852 | default: |
dfe96118 | 4853 | return 0; |
f5470689 | 4854 | } |
25963977 | 4855 | if ((time1 >= time2 |
eceef4c9 BS |
4856 | && (! rld[i].in || rld[i].out |
4857 | || ! rtx_equal_p (rld[i].in, value))) | |
4858 | || (out && rld[reloadnum].out_reg | |
701d55e8 | 4859 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 4860 | return 0; |
6e684430 | 4861 | } |
6e684430 R |
4862 | } |
4863 | } | |
09a308fe R |
4864 | |
4865 | /* Earlyclobbered outputs must conflict with inputs. */ | |
4866 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
4867 | return 0; | |
4868 | ||
6e684430 R |
4869 | return 1; |
4870 | } | |
4871 | ||
c02cad8f BS |
4872 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
4873 | needed for the part of the insn specified by OPNUM and TYPE, | |
4874 | may be used to load VALUE into it. | |
4875 | ||
4876 | MODE is the mode in which the register is used, this is needed to | |
4877 | determine how many hard regs to test. | |
4878 | ||
4879 | Other read-only reloads with the same value do not conflict | |
4880 | unless OUT is non-zero and these other reloads have to live while | |
4881 | output reloads live. | |
4882 | If OUT is CONST0_RTX, this is a special case: it means that the | |
4883 | test should not be for using register REGNO as reload register, but | |
4884 | for copying from register REGNO into the reload register. | |
4885 | ||
4886 | RELOADNUM is the number of the reload we want to load this value for; | |
4887 | a reload does not conflict with itself. | |
4888 | ||
4889 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
4890 | reloads that load an address for the very reload we are considering. | |
4891 | ||
4892 | The caller has to make sure that there is no conflict with the return | |
4893 | register. */ | |
4894 | ||
4895 | static int | |
4896 | free_for_value_p (regno, mode, opnum, type, value, out, reloadnum, | |
4897 | ignore_address_reloads) | |
4898 | int regno; | |
4899 | enum machine_mode mode; | |
4900 | int opnum; | |
4901 | enum reload_type type; | |
4902 | rtx value, out; | |
4903 | int reloadnum; | |
4904 | int ignore_address_reloads; | |
4905 | { | |
4906 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
4907 | while (nregs-- > 0) | |
4908 | if (! reload_reg_free_for_value_p (regno, opnum, type, value, out, | |
4909 | reloadnum, ignore_address_reloads)) | |
4910 | return 0; | |
4911 | return 1; | |
4912 | } | |
4913 | ||
ff6534ad BS |
4914 | /* Determine whether the reload reg X overlaps any rtx'es used for |
4915 | overriding inheritance. Return nonzero if so. */ | |
4916 | ||
4917 | static int | |
4918 | conflicts_with_override (x) | |
4919 | rtx x; | |
4920 | { | |
4921 | int i; | |
4922 | for (i = 0; i < n_reloads; i++) | |
4923 | if (reload_override_in[i] | |
4924 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
4925 | return 1; | |
4926 | return 0; | |
4927 | } | |
4928 | \f | |
67e61fe7 BS |
4929 | /* Give an error message saying we failed to find a reload for INSN, |
4930 | and clear out reload R. */ | |
4931 | static void | |
4932 | failed_reload (insn, r) | |
4933 | rtx insn; | |
4934 | int r; | |
4935 | { | |
4936 | if (asm_noperands (PATTERN (insn)) < 0) | |
4937 | /* It's the compiler's fault. */ | |
4938 | fatal_insn ("Could not find a spill register", insn); | |
4939 | ||
4940 | /* It's the user's fault; the operand's mode and constraint | |
4941 | don't match. Disable this reload so we don't crash in final. */ | |
4942 | error_for_asm (insn, | |
4943 | "`asm' operand constraint incompatible with operand size"); | |
4944 | rld[r].in = 0; | |
4945 | rld[r].out = 0; | |
4946 | rld[r].reg_rtx = 0; | |
4947 | rld[r].optional = 1; | |
4948 | rld[r].secondary_p = 1; | |
4949 | } | |
4950 | ||
4951 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
4952 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
4953 | successful. */ | |
4954 | static int | |
4955 | set_reload_reg (i, r) | |
4956 | int i, r; | |
4957 | { | |
4958 | int regno; | |
4959 | rtx reg = spill_reg_rtx[i]; | |
4960 | ||
4961 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
4962 | spill_reg_rtx[i] = reg | |
4963 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
4964 | ||
4965 | regno = true_regnum (reg); | |
4966 | ||
4967 | /* Detect when the reload reg can't hold the reload mode. | |
4968 | This used to be one `if', but Sequent compiler can't handle that. */ | |
4969 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
4970 | { | |
4971 | enum machine_mode test_mode = VOIDmode; | |
4972 | if (rld[r].in) | |
4973 | test_mode = GET_MODE (rld[r].in); | |
4974 | /* If rld[r].in has VOIDmode, it means we will load it | |
4975 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
4976 | We have already tested that for validity. */ | |
4977 | /* Aside from that, we need to test that the expressions | |
4978 | to reload from or into have modes which are valid for this | |
4979 | reload register. Otherwise the reload insns would be invalid. */ | |
4980 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
4981 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
4982 | if (! (rld[r].out != 0 | |
4983 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
4984 | { | |
4985 | /* The reg is OK. */ | |
4986 | last_spill_reg = i; | |
4987 | ||
4988 | /* Mark as in use for this insn the reload regs we use | |
4989 | for this. */ | |
4990 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
4991 | rld[r].when_needed, rld[r].mode); | |
4992 | ||
4993 | rld[r].reg_rtx = reg; | |
4994 | reload_spill_index[r] = spill_regs[i]; | |
4995 | return 1; | |
4996 | } | |
4997 | } | |
4998 | return 0; | |
4999 | } | |
5000 | ||
32131a9c RK |
5001 | /* Find a spill register to use as a reload register for reload R. |
5002 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
5003 | processed. | |
5004 | ||
eceef4c9 | 5005 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5006 | |
f5d8c9f4 BS |
5007 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5008 | we didn't change anything. */ | |
32131a9c RK |
5009 | |
5010 | static int | |
f5d8c9f4 | 5011 | allocate_reload_reg (chain, r, last_reload) |
272df862 | 5012 | struct insn_chain *chain ATTRIBUTE_UNUSED; |
32131a9c | 5013 | int r; |
32131a9c | 5014 | int last_reload; |
32131a9c | 5015 | { |
67e61fe7 | 5016 | int i, pass, count; |
32131a9c RK |
5017 | |
5018 | /* If we put this reload ahead, thinking it is a group, | |
5019 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5020 | reg that some other reload needs. |
32131a9c RK |
5021 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5022 | which is a group of data regs or one fp reg.) | |
5023 | We need not be so restrictive if there are no more reloads | |
5024 | for this insn. | |
5025 | ||
5026 | ??? Really it would be nicer to have smarter handling | |
5027 | for that kind of reg class, where a problem like this is normal. | |
5028 | Perhaps those classes should be avoided for reloading | |
5029 | by use of more alternatives. */ | |
5030 | ||
8ec450a4 | 5031 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5032 | |
5033 | /* If we want a single register and haven't yet found one, | |
5034 | take any reg in the right class and not in use. | |
5035 | If we want a consecutive group, here is where we look for it. | |
5036 | ||
5037 | We use two passes so we can first look for reload regs to | |
5038 | reuse, which are already in use for other reloads in this insn, | |
5039 | and only then use additional registers. | |
5040 | I think that maximizing reuse is needed to make sure we don't | |
5041 | run out of reload regs. Suppose we have three reloads, and | |
5042 | reloads A and B can share regs. These need two regs. | |
5043 | Suppose A and B are given different regs. | |
5044 | That leaves none for C. */ | |
5045 | for (pass = 0; pass < 2; pass++) | |
5046 | { | |
5047 | /* I is the index in spill_regs. | |
5048 | We advance it round-robin between insns to use all spill regs | |
5049 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5050 | of leapfrogging each other. */ |
5051 | ||
5052 | i = last_spill_reg; | |
05d10675 | 5053 | |
a5339699 | 5054 | for (count = 0; count < n_spills; count++) |
32131a9c | 5055 | { |
eceef4c9 | 5056 | int class = (int) rld[r].class; |
03acd8f8 | 5057 | int regnum; |
32131a9c | 5058 | |
03acd8f8 BS |
5059 | i++; |
5060 | if (i >= n_spills) | |
5061 | i -= n_spills; | |
5062 | regnum = spill_regs[i]; | |
32131a9c | 5063 | |
eceef4c9 BS |
5064 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5065 | rld[r].when_needed) | |
5066 | || (rld[r].in | |
05d10675 BS |
5067 | /* We check reload_reg_used to make sure we |
5068 | don't clobber the return register. */ | |
03acd8f8 | 5069 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5070 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5071 | rld[r].when_needed, rld[r].in, | |
5072 | rld[r].out, r, 1))) | |
03acd8f8 | 5073 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 5074 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5075 | /* Look first for regs to share, then for unshared. But |
5076 | don't share regs used for inherited reloads; they are | |
5077 | the ones we want to preserve. */ | |
5078 | && (pass | |
5079 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5080 | regnum) |
be7ae2a4 | 5081 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5082 | regnum)))) |
32131a9c | 5083 | { |
8ec450a4 | 5084 | int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); |
32131a9c RK |
5085 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5086 | (on 68000) got us two FP regs. If NR is 1, | |
5087 | we would reject both of them. */ | |
5088 | if (force_group) | |
67e61fe7 | 5089 | nr = rld[r].nregs; |
32131a9c RK |
5090 | /* If we need only one reg, we have already won. */ |
5091 | if (nr == 1) | |
5092 | { | |
5093 | /* But reject a single reg if we demand a group. */ | |
5094 | if (force_group) | |
5095 | continue; | |
5096 | break; | |
5097 | } | |
5098 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5099 | are available here. */ |
5100 | while (nr > 1) | |
5101 | { | |
5102 | int regno = regnum + nr - 1; | |
5103 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5104 | && spill_reg_order[regno] >= 0 | |
5105 | && reload_reg_free_p (regno, rld[r].opnum, | |
5106 | rld[r].when_needed))) | |
5107 | break; | |
5108 | nr--; | |
5109 | } | |
32131a9c RK |
5110 | if (nr == 1) |
5111 | break; | |
5112 | } | |
5113 | } | |
5114 | ||
5115 | /* If we found something on pass 1, omit pass 2. */ | |
5116 | if (count < n_spills) | |
5117 | break; | |
5118 | } | |
1d7254c5 | 5119 | |
32131a9c | 5120 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5121 | if (count >= n_spills) |
32131a9c RK |
5122 | return 0; |
5123 | ||
f5d8c9f4 BS |
5124 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5125 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5126 | |
f5d8c9f4 | 5127 | return set_reload_reg (i, r); |
32131a9c RK |
5128 | } |
5129 | \f | |
67e61fe7 BS |
5130 | /* Initialize all the tables needed to allocate reload registers. |
5131 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5132 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5133 | |
32131a9c | 5134 | static void |
67e61fe7 | 5135 | choose_reload_regs_init (chain, save_reload_reg_rtx) |
7609e720 | 5136 | struct insn_chain *chain; |
67e61fe7 | 5137 | rtx *save_reload_reg_rtx; |
32131a9c | 5138 | { |
67e61fe7 | 5139 | int i; |
32131a9c | 5140 | |
67e61fe7 BS |
5141 | for (i = 0; i < n_reloads; i++) |
5142 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5143 | |
961192e1 JM |
5144 | memset (reload_inherited, 0, MAX_RELOADS); |
5145 | memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); | |
5146 | memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5147 | |
5148 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5149 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5150 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5151 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5152 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5153 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5154 | |
f1db3576 JL |
5155 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5156 | { | |
5157 | HARD_REG_SET tmp; | |
239a0f5b | 5158 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5159 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5160 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5161 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5162 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5163 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5164 | } |
efc9bd41 | 5165 | |
546b63fb RK |
5166 | for (i = 0; i < reload_n_operands; i++) |
5167 | { | |
5168 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5169 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5170 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5171 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5172 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5173 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5174 | } |
32131a9c | 5175 | |
9e3a9cf2 | 5176 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5177 | |
67e61fe7 | 5178 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5179 | |
67e61fe7 BS |
5180 | for (i = 0; i < n_reloads; i++) |
5181 | /* If we have already decided to use a certain register, | |
5182 | don't use it in another way. */ | |
5183 | if (rld[i].reg_rtx) | |
5184 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5185 | rld[i].when_needed, rld[i].mode); | |
5186 | } | |
32131a9c | 5187 | |
67e61fe7 BS |
5188 | /* Assign hard reg targets for the pseudo-registers we must reload |
5189 | into hard regs for this insn. | |
5190 | Also output the instructions to copy them in and out of the hard regs. | |
5191 | ||
5192 | For machines with register classes, we are responsible for | |
5193 | finding a reload reg in the proper class. */ | |
5194 | ||
5195 | static void | |
5196 | choose_reload_regs (chain) | |
5197 | struct insn_chain *chain; | |
5198 | { | |
5199 | rtx insn = chain->insn; | |
5200 | register int i, j; | |
770ae6cc | 5201 | unsigned int max_group_size = 1; |
67e61fe7 | 5202 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5203 | int pass, win, inheritance; |
67e61fe7 BS |
5204 | |
5205 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5206 | |
32131a9c RK |
5207 | /* In order to be certain of getting the registers we need, |
5208 | we must sort the reloads into order of increasing register class. | |
5209 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5210 | that provided the reload registers. |
32131a9c RK |
5211 | |
5212 | Also note whether any of the reloads wants a consecutive group of regs. | |
5213 | If so, record the maximum size of the group desired and what | |
5214 | register class contains all the groups needed by this insn. */ | |
5215 | ||
5216 | for (j = 0; j < n_reloads; j++) | |
5217 | { | |
5218 | reload_order[j] = j; | |
5219 | reload_spill_index[j] = -1; | |
5220 | ||
8ec450a4 | 5221 | if (rld[j].nregs > 1) |
32131a9c | 5222 | { |
8ec450a4 | 5223 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5224 | group_class |
1d7254c5 | 5225 | = reg_class_superunion[(int) rld[j].class][(int)group_class]; |
32131a9c RK |
5226 | } |
5227 | ||
eceef4c9 | 5228 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5229 | } |
5230 | ||
5231 | if (n_reloads > 1) | |
5232 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5233 | ||
58b1581b RS |
5234 | /* If -O, try first with inheritance, then turning it off. |
5235 | If not -O, don't do inheritance. | |
5236 | Using inheritance when not optimizing leads to paradoxes | |
5237 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5238 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5239 | win = 0; |
58b1581b | 5240 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5241 | { |
67e61fe7 BS |
5242 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5243 | ||
32131a9c RK |
5244 | /* Process the reloads in order of preference just found. |
5245 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5246 | ||
770ae6cc RK |
5247 | This used to look for an existing reloaded home for all of the |
5248 | reloads, and only then perform any new reloads. But that could lose | |
5249 | if the reloads were done out of reg-class order because a later | |
5250 | reload with a looser constraint might have an old home in a register | |
5251 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5252 | |
5253 | To solve this, we make two passes over the reloads, in the order | |
5254 | described above. In the first pass we try to inherit a reload | |
5255 | from a previous insn. If there is a later reload that needs a | |
5256 | class that is a proper subset of the class being processed, we must | |
5257 | also allocate a spill register during the first pass. | |
5258 | ||
5259 | Then make a second pass over the reloads to allocate any reloads | |
5260 | that haven't been given registers yet. */ | |
5261 | ||
5262 | for (j = 0; j < n_reloads; j++) | |
5263 | { | |
5264 | register int r = reload_order[j]; | |
8593b745 | 5265 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5266 | |
5267 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5268 | if (rld[r].out == 0 && rld[r].in == 0 |
5269 | && ! rld[r].secondary_p) | |
32131a9c RK |
5270 | continue; |
5271 | ||
b29514ee | 5272 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5273 | register, we don't need to chose one. Otherwise, try even if it |
5274 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5275 | around. |
5276 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5277 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5278 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5279 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
5280 | && GET_CODE (rld[r].in) != MEM | |
5281 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) | |
32131a9c RK |
5282 | continue; |
5283 | ||
5284 | #if 0 /* No longer needed for correct operation. | |
5285 | It might give better code, or might not; worth an experiment? */ | |
5286 | /* If this is an optional reload, we can't inherit from earlier insns | |
5287 | until we are sure that any non-optional reloads have been allocated. | |
5288 | The following code takes advantage of the fact that optional reloads | |
5289 | are at the end of reload_order. */ | |
eceef4c9 | 5290 | if (rld[r].optional != 0) |
32131a9c | 5291 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5292 | if ((rld[reload_order[i]].out != 0 |
5293 | || rld[reload_order[i]].in != 0 | |
5294 | || rld[reload_order[i]].secondary_p) | |
5295 | && ! rld[reload_order[i]].optional | |
5296 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5297 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5298 | #endif |
5299 | ||
5300 | /* First see if this pseudo is already available as reloaded | |
5301 | for a previous insn. We cannot try to inherit for reloads | |
5302 | that are smaller than the maximum number of registers needed | |
5303 | for groups unless the register we would allocate cannot be used | |
5304 | for the groups. | |
5305 | ||
5306 | We could check here to see if this is a secondary reload for | |
5307 | an object that is already in a register of the desired class. | |
5308 | This would avoid the need for the secondary reload register. | |
5309 | But this is complex because we can't easily determine what | |
b080c137 RK |
5310 | objects might want to be loaded via this reload. So let a |
5311 | register be allocated here. In `emit_reload_insns' we suppress | |
5312 | one of the loads in the case described above. */ | |
32131a9c RK |
5313 | |
5314 | if (inheritance) | |
5315 | { | |
cb2afeb3 | 5316 | int word = 0; |
32131a9c | 5317 | register int regno = -1; |
6a651371 | 5318 | enum machine_mode mode = VOIDmode; |
32131a9c | 5319 | |
eceef4c9 | 5320 | if (rld[r].in == 0) |
32131a9c | 5321 | ; |
eceef4c9 | 5322 | else if (GET_CODE (rld[r].in) == REG) |
db660765 | 5323 | { |
eceef4c9 BS |
5324 | regno = REGNO (rld[r].in); |
5325 | mode = GET_MODE (rld[r].in); | |
db660765 | 5326 | } |
eceef4c9 | 5327 | else if (GET_CODE (rld[r].in_reg) == REG) |
db660765 | 5328 | { |
eceef4c9 BS |
5329 | regno = REGNO (rld[r].in_reg); |
5330 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5331 | } |
eceef4c9 BS |
5332 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
5333 | && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) | |
b60a8416 | 5334 | { |
eceef4c9 BS |
5335 | word = SUBREG_WORD (rld[r].in_reg); |
5336 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); | |
cb2afeb3 R |
5337 | if (regno < FIRST_PSEUDO_REGISTER) |
5338 | regno += word; | |
eceef4c9 | 5339 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5340 | } |
5341 | #ifdef AUTO_INC_DEC | |
eceef4c9 BS |
5342 | else if ((GET_CODE (rld[r].in_reg) == PRE_INC |
5343 | || GET_CODE (rld[r].in_reg) == PRE_DEC | |
5344 | || GET_CODE (rld[r].in_reg) == POST_INC | |
5345 | || GET_CODE (rld[r].in_reg) == POST_DEC) | |
5346 | && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) | |
cb2afeb3 | 5347 | { |
eceef4c9 BS |
5348 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5349 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5350 | rld[r].out = rld[r].in; | |
b60a8416 | 5351 | } |
cb2afeb3 | 5352 | #endif |
32131a9c RK |
5353 | #if 0 |
5354 | /* This won't work, since REGNO can be a pseudo reg number. | |
5355 | Also, it takes much more hair to keep track of all the things | |
5356 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 BS |
5357 | else if (GET_CODE (rld[r].in) == SUBREG |
5358 | && GET_CODE (SUBREG_REG (rld[r].in)) == REG) | |
5359 | regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in); | |
32131a9c RK |
5360 | #endif |
5361 | ||
5362 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
5363 | { | |
eceef4c9 | 5364 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5365 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 5366 | enum machine_mode need_mode; |
05d10675 | 5367 | |
cb2afeb3 R |
5368 | i = REGNO (last_reg) + word; |
5369 | last_class = REGNO_REG_CLASS (i); | |
02188693 | 5370 | |
ce701d1b BS |
5371 | if (word == 0) |
5372 | need_mode = mode; | |
5373 | else | |
5374 | need_mode | |
5375 | = smallest_mode_for_size (GET_MODE_SIZE (mode) | |
5376 | + word * UNITS_PER_WORD, | |
5377 | GET_MODE_CLASS (mode)); | |
02188693 | 5378 | |
c9d8a813 | 5379 | if ( |
02188693 | 5380 | #ifdef CLASS_CANNOT_CHANGE_MODE |
c9d8a813 | 5381 | (TEST_HARD_REG_BIT |
02188693 | 5382 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i) |
1d7254c5 | 5383 | ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg), |
02188693 | 5384 | need_mode) |
c9d8a813 | 5385 | : (GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 5386 | >= GET_MODE_SIZE (need_mode))) |
c9d8a813 RH |
5387 | #else |
5388 | (GET_MODE_SIZE (GET_MODE (last_reg)) | |
02188693 | 5389 | >= GET_MODE_SIZE (need_mode)) |
c9d8a813 | 5390 | #endif |
cb2afeb3 | 5391 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 5392 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5393 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5394 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5395 | /* Even if we can't use this register as a reload | |
5396 | register, we might use it for reload_override_in, | |
5397 | if copying it to the desired class is cheap | |
5398 | enough. */ | |
5399 | || ((REGISTER_MOVE_COST (last_class, class) | |
5400 | < MEMORY_MOVE_COST (mode, class, 1)) | |
5401 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5402 | && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, | |
5403 | last_reg) | |
5404 | == NO_REGS) | |
5405 | #endif | |
5406 | #ifdef SECONDARY_MEMORY_NEEDED | |
5407 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5408 | mode) | |
5409 | #endif | |
5410 | )) | |
5411 | ||
8ec450a4 | 5412 | && (rld[r].nregs == max_group_size |
32131a9c | 5413 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5414 | i)) |
c02cad8f BS |
5415 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
5416 | rld[r].when_needed, rld[r].in, | |
5417 | const0_rtx, r, 1)) | |
32131a9c RK |
5418 | { |
5419 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5420 | registers still have their values intact. */ |
1d7254c5 | 5421 | int nr = HARD_REGNO_NREGS (i, rld[r].mode); |
32131a9c RK |
5422 | int k; |
5423 | ||
5424 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5425 | if (reg_reloaded_contents[i + k] != regno |
5426 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5427 | break; |
5428 | ||
5429 | if (k == nr) | |
5430 | { | |
c74fa651 RS |
5431 | int i1; |
5432 | ||
cb2afeb3 R |
5433 | last_reg = (GET_MODE (last_reg) == mode |
5434 | ? last_reg : gen_rtx_REG (mode, i)); | |
5435 | ||
c74fa651 RS |
5436 | /* We found a register that contains the |
5437 | value we need. If this register is the | |
5438 | same as an `earlyclobber' operand of the | |
5439 | current insn, just mark it as a place to | |
5440 | reload from since we can't use it as the | |
5441 | reload register itself. */ | |
5442 | ||
5443 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5444 | if (reg_overlap_mentioned_for_reload_p | |
5445 | (reg_last_reload_reg[regno], | |
5446 | reload_earlyclobbers[i1])) | |
5447 | break; | |
5448 | ||
8908158d | 5449 | if (i1 != n_earlyclobbers |
c02cad8f BS |
5450 | || ! (free_for_value_p (i, rld[r].mode, |
5451 | rld[r].opnum, | |
5452 | rld[r].when_needed, rld[r].in, | |
5453 | rld[r].out, r, 1)) | |
e6e52be0 | 5454 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5455 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5456 | && rld[r].out |
e6e52be0 | 5457 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5458 | /* Don't clobber the frame pointer. */ |
1d7254c5 KH |
5459 | || (i == HARD_FRAME_POINTER_REGNUM |
5460 | && rld[r].out) | |
8908158d RS |
5461 | /* Don't really use the inherited spill reg |
5462 | if we need it wider than we've got it. */ | |
8ec450a4 | 5463 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5464 | > GET_MODE_SIZE (mode)) |
eceef4c9 | 5465 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
cb2afeb3 R |
5466 | i) |
5467 | ||
b29514ee R |
5468 | /* If find_reloads chose reload_out as reload |
5469 | register, stay with it - that leaves the | |
5470 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5471 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5472 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 5473 | { |
4c3a2649 BS |
5474 | if (! rld[r].optional) |
5475 | { | |
5476 | reload_override_in[r] = last_reg; | |
5477 | reload_inheritance_insn[r] | |
5478 | = reg_reloaded_insn[i]; | |
5479 | } | |
cb2afeb3 | 5480 | } |
c74fa651 RS |
5481 | else |
5482 | { | |
54c40e68 | 5483 | int k; |
c74fa651 RS |
5484 | /* We can use this as a reload reg. */ |
5485 | /* Mark the register as in use for this part of | |
5486 | the insn. */ | |
e6e52be0 | 5487 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5488 | rld[r].opnum, |
5489 | rld[r].when_needed, | |
8ec450a4 | 5490 | rld[r].mode); |
eceef4c9 | 5491 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5492 | reload_inherited[r] = 1; |
5493 | reload_inheritance_insn[r] | |
5494 | = reg_reloaded_insn[i]; | |
5495 | reload_spill_index[r] = i; | |
54c40e68 RS |
5496 | for (k = 0; k < nr; k++) |
5497 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5498 | i + k); |
c74fa651 | 5499 | } |
32131a9c RK |
5500 | } |
5501 | } | |
5502 | } | |
5503 | } | |
5504 | ||
5505 | /* Here's another way to see if the value is already lying around. */ | |
5506 | if (inheritance | |
eceef4c9 | 5507 | && rld[r].in != 0 |
32131a9c | 5508 | && ! reload_inherited[r] |
eceef4c9 BS |
5509 | && rld[r].out == 0 |
5510 | && (CONSTANT_P (rld[r].in) | |
5511 | || GET_CODE (rld[r].in) == PLUS | |
5512 | || GET_CODE (rld[r].in) == REG | |
5513 | || GET_CODE (rld[r].in) == MEM) | |
8ec450a4 | 5514 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5515 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5516 | search_equiv = rld[r].in; | |
8593b745 R |
5517 | /* If this is an output reload from a simple move insn, look |
5518 | if an equivalence for the input is available. */ | |
eceef4c9 | 5519 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5520 | { |
5521 | rtx set = single_set (insn); | |
5522 | ||
5523 | if (set | |
eceef4c9 | 5524 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5525 | && CONSTANT_P (SET_SRC (set))) |
5526 | search_equiv = SET_SRC (set); | |
5527 | } | |
5528 | ||
5529 | if (search_equiv) | |
32131a9c RK |
5530 | { |
5531 | register rtx equiv | |
eceef4c9 | 5532 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
8ec450a4 | 5533 | -1, NULL_PTR, 0, rld[r].mode); |
f428f252 | 5534 | int regno = 0; |
32131a9c RK |
5535 | |
5536 | if (equiv != 0) | |
5537 | { | |
5538 | if (GET_CODE (equiv) == REG) | |
5539 | regno = REGNO (equiv); | |
5540 | else if (GET_CODE (equiv) == SUBREG) | |
5541 | { | |
f8a9e02b RK |
5542 | /* This must be a SUBREG of a hard register. |
5543 | Make a new REG since this might be used in an | |
5544 | address and not all machines support SUBREGs | |
5545 | there. */ | |
5546 | regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv); | |
8ec450a4 | 5547 | equiv = gen_rtx_REG (rld[r].mode, regno); |
32131a9c RK |
5548 | } |
5549 | else | |
5550 | abort (); | |
5551 | } | |
5552 | ||
5553 | /* If we found a spill reg, reject it unless it is free | |
5554 | and of the desired class. */ | |
5555 | if (equiv != 0 | |
cb2afeb3 | 5556 | && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) |
c02cad8f BS |
5557 | && ! free_for_value_p (regno, rld[r].mode, |
5558 | rld[r].opnum, rld[r].when_needed, | |
5559 | rld[r].in, rld[r].out, r, 1)) | |
eceef4c9 | 5560 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
32131a9c RK |
5561 | regno))) |
5562 | equiv = 0; | |
5563 | ||
8ec450a4 | 5564 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
5565 | equiv = 0; |
5566 | ||
5567 | /* We found a register that contains the value we need. | |
5568 | If this register is the same as an `earlyclobber' operand | |
5569 | of the current insn, just mark it as a place to reload from | |
5570 | since we can't use it as the reload register itself. */ | |
5571 | ||
5572 | if (equiv != 0) | |
5573 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
5574 | if (reg_overlap_mentioned_for_reload_p (equiv, |
5575 | reload_earlyclobbers[i])) | |
32131a9c | 5576 | { |
4c3a2649 BS |
5577 | if (! rld[r].optional) |
5578 | reload_override_in[r] = equiv; | |
32131a9c RK |
5579 | equiv = 0; |
5580 | break; | |
5581 | } | |
5582 | ||
3c785e47 R |
5583 | /* If the equiv register we have found is explicitly clobbered |
5584 | in the current insn, it depends on the reload type if we | |
5585 | can use it, use it for reload_override_in, or not at all. | |
5586 | In particular, we then can't use EQUIV for a | |
5587 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 5588 | |
9532e31f BS |
5589 | if (equiv != 0) |
5590 | { | |
5591 | if (regno_clobbered_p (regno, insn, rld[r].mode, 0)) | |
5592 | switch (rld[r].when_needed) | |
5593 | { | |
5594 | case RELOAD_FOR_OTHER_ADDRESS: | |
5595 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5596 | case RELOAD_FOR_INPUT_ADDRESS: | |
5597 | case RELOAD_FOR_OPADDR_ADDR: | |
5598 | break; | |
5599 | case RELOAD_OTHER: | |
5600 | case RELOAD_FOR_INPUT: | |
5601 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5602 | if (! rld[r].optional) | |
5603 | reload_override_in[r] = equiv; | |
5604 | /* Fall through. */ | |
5605 | default: | |
5606 | equiv = 0; | |
5607 | break; | |
5608 | } | |
5609 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
5610 | switch (rld[r].when_needed) | |
5611 | { | |
5612 | case RELOAD_FOR_OTHER_ADDRESS: | |
5613 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5614 | case RELOAD_FOR_INPUT_ADDRESS: | |
5615 | case RELOAD_FOR_OPADDR_ADDR: | |
5616 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5617 | case RELOAD_FOR_INPUT: | |
5618 | break; | |
5619 | case RELOAD_OTHER: | |
5620 | if (! rld[r].optional) | |
5621 | reload_override_in[r] = equiv; | |
5622 | /* Fall through. */ | |
5623 | default: | |
5624 | equiv = 0; | |
5625 | break; | |
5626 | } | |
32131a9c RK |
5627 | } |
5628 | ||
5629 | /* If we found an equivalent reg, say no code need be generated | |
5630 | to load it, and use it as our reload reg. */ | |
3ec2ea3e | 5631 | if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM) |
32131a9c | 5632 | { |
8ec450a4 | 5633 | int nr = HARD_REGNO_NREGS (regno, rld[r].mode); |
100338df | 5634 | int k; |
eceef4c9 | 5635 | rld[r].reg_rtx = equiv; |
32131a9c | 5636 | reload_inherited[r] = 1; |
100338df | 5637 | |
91d7e7ac R |
5638 | /* If reg_reloaded_valid is not set for this register, |
5639 | there might be a stale spill_reg_store lying around. | |
5640 | We must clear it, since otherwise emit_reload_insns | |
5641 | might delete the store. */ | |
5642 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
5643 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
5644 | /* If any of the hard registers in EQUIV are spill |
5645 | registers, mark them as in use for this insn. */ | |
5646 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 5647 | { |
100338df JL |
5648 | i = spill_reg_order[regno + k]; |
5649 | if (i >= 0) | |
5650 | { | |
eceef4c9 BS |
5651 | mark_reload_reg_in_use (regno, rld[r].opnum, |
5652 | rld[r].when_needed, | |
8ec450a4 | 5653 | rld[r].mode); |
100338df JL |
5654 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
5655 | regno + k); | |
5656 | } | |
be7ae2a4 | 5657 | } |
32131a9c RK |
5658 | } |
5659 | } | |
5660 | ||
5661 | /* If we found a register to use already, or if this is an optional | |
5662 | reload, we are done. */ | |
eceef4c9 | 5663 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
5664 | continue; |
5665 | ||
1d7254c5 KH |
5666 | #if 0 |
5667 | /* No longer needed for correct operation. Might or might | |
5668 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
5669 | |
5670 | /* See if there is a later reload that has a class different from our | |
5671 | class that intersects our class or that requires less register | |
5672 | than our reload. If so, we must allocate a register to this | |
5673 | reload now, since that reload might inherit a previous reload | |
5674 | and take the only available register in our class. Don't do this | |
5675 | for optional reloads since they will force all previous reloads | |
5676 | to be allocated. Also don't do this for reloads that have been | |
5677 | turned off. */ | |
5678 | ||
5679 | for (i = j + 1; i < n_reloads; i++) | |
5680 | { | |
5681 | int s = reload_order[i]; | |
5682 | ||
eceef4c9 BS |
5683 | if ((rld[s].in == 0 && rld[s].out == 0 |
5684 | && ! rld[s].secondary_p) | |
5685 | || rld[s].optional) | |
32131a9c RK |
5686 | continue; |
5687 | ||
eceef4c9 BS |
5688 | if ((rld[s].class != rld[r].class |
5689 | && reg_classes_intersect_p (rld[r].class, | |
5690 | rld[s].class)) | |
8ec450a4 | 5691 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 5692 | break; |
32131a9c RK |
5693 | } |
5694 | ||
5695 | if (i == n_reloads) | |
5696 | continue; | |
5697 | ||
f5d8c9f4 | 5698 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
5699 | #endif |
5700 | } | |
5701 | ||
5702 | /* Now allocate reload registers for anything non-optional that | |
5703 | didn't get one yet. */ | |
5704 | for (j = 0; j < n_reloads; j++) | |
5705 | { | |
5706 | register int r = reload_order[j]; | |
5707 | ||
5708 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 5709 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
5710 | continue; |
5711 | ||
5712 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 5713 | optional. */ |
eceef4c9 | 5714 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
5715 | continue; |
5716 | ||
f5d8c9f4 | 5717 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
5718 | break; |
5719 | } | |
5720 | ||
5721 | /* If that loop got all the way, we have won. */ | |
5722 | if (j == n_reloads) | |
f5d8c9f4 BS |
5723 | { |
5724 | win = 1; | |
5725 | break; | |
5726 | } | |
32131a9c | 5727 | |
32131a9c | 5728 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
5729 | } |
5730 | ||
f5d8c9f4 BS |
5731 | if (! win) |
5732 | { | |
5733 | /* First undo everything done by the failed attempt | |
5734 | to allocate with inheritance. */ | |
5735 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
5736 | ||
5737 | /* Some sanity tests to verify that the reloads found in the first | |
5738 | pass are identical to the ones we have now. */ | |
5739 | if (chain->n_reloads != n_reloads) | |
5740 | abort (); | |
5741 | ||
5742 | for (i = 0; i < n_reloads; i++) | |
5743 | { | |
5744 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
5745 | continue; | |
5746 | if (chain->rld[i].when_needed != rld[i].when_needed) | |
5747 | abort (); | |
5748 | for (j = 0; j < n_spills; j++) | |
5749 | if (spill_regs[j] == chain->rld[i].regno) | |
5750 | if (! set_reload_reg (j, i)) | |
5751 | failed_reload (chain->insn, i); | |
5752 | } | |
5753 | } | |
5754 | ||
32131a9c RK |
5755 | /* If we thought we could inherit a reload, because it seemed that |
5756 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
5757 | verify that assumption, now that all reloads have been assigned. |
5758 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 5759 | |
cb2afeb3 R |
5760 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
5761 | cancel any inheritance, but removes reloads that have been needed only | |
5762 | for reloads that we know can be inherited. */ | |
5763 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 5764 | { |
cb2afeb3 | 5765 | for (j = 0; j < n_reloads; j++) |
029b38ff | 5766 | { |
cb2afeb3 R |
5767 | register int r = reload_order[j]; |
5768 | rtx check_reg; | |
eceef4c9 BS |
5769 | if (reload_inherited[r] && rld[r].reg_rtx) |
5770 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 R |
5771 | else if (reload_override_in[r] |
5772 | && (GET_CODE (reload_override_in[r]) == REG | |
05d10675 | 5773 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
5774 | check_reg = reload_override_in[r]; |
5775 | else | |
5776 | continue; | |
c02cad8f BS |
5777 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
5778 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
5779 | (reload_inherited[r] | |
5780 | ? rld[r].out : const0_rtx), | |
5781 | r, 1)) | |
029b38ff | 5782 | { |
cb2afeb3 R |
5783 | if (pass) |
5784 | continue; | |
5785 | reload_inherited[r] = 0; | |
5786 | reload_override_in[r] = 0; | |
029b38ff | 5787 | } |
cb2afeb3 R |
5788 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
5789 | reload_override_in, then we do not need its related | |
5790 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
5791 | likewise for other reload types. | |
5792 | We handle this by removing a reload when its only replacement | |
5793 | is mentioned in reload_in of the reload we are going to inherit. | |
5794 | A special case are auto_inc expressions; even if the input is | |
5795 | inherited, we still need the address for the output. We can | |
fe92fe26 | 5796 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
cb2afeb3 R |
5797 | If we suceeded removing some reload and we are doing a preliminary |
5798 | pass just to remove such reloads, make another pass, since the | |
5799 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
5800 | else if (rld[r].in |
5801 | && rld[r].out != rld[r].in | |
5802 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 5803 | pass = 2; |
32131a9c RK |
5804 | } |
5805 | } | |
5806 | ||
5807 | /* Now that reload_override_in is known valid, | |
5808 | actually override reload_in. */ | |
5809 | for (j = 0; j < n_reloads; j++) | |
5810 | if (reload_override_in[j]) | |
eceef4c9 | 5811 | rld[j].in = reload_override_in[j]; |
32131a9c RK |
5812 | |
5813 | /* If this reload won't be done because it has been cancelled or is | |
5814 | optional and not inherited, clear reload_reg_rtx so other | |
5815 | routines (such as subst_reloads) don't get confused. */ | |
5816 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5817 | if (rld[j].reg_rtx != 0 |
5818 | && ((rld[j].optional && ! reload_inherited[j]) | |
5819 | || (rld[j].in == 0 && rld[j].out == 0 | |
5820 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 5821 | { |
eceef4c9 | 5822 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
5823 | |
5824 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 5825 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 5826 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 5827 | rld[j].reg_rtx = 0; |
c0029be5 | 5828 | reload_spill_index[j] = -1; |
be7ae2a4 | 5829 | } |
32131a9c RK |
5830 | |
5831 | /* Record which pseudos and which spill regs have output reloads. */ | |
5832 | for (j = 0; j < n_reloads; j++) | |
5833 | { | |
5834 | register int r = reload_order[j]; | |
5835 | ||
5836 | i = reload_spill_index[r]; | |
5837 | ||
e6e52be0 | 5838 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 5839 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 5840 | that we opted to ignore. */ |
eceef4c9 BS |
5841 | if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG |
5842 | && rld[r].reg_rtx != 0) | |
32131a9c | 5843 | { |
eceef4c9 | 5844 | register int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
5845 | int nr = 1; |
5846 | ||
5847 | if (nregno < FIRST_PSEUDO_REGISTER) | |
8ec450a4 | 5848 | nr = HARD_REGNO_NREGS (nregno, rld[r].mode); |
32131a9c RK |
5849 | |
5850 | while (--nr >= 0) | |
372e033b RS |
5851 | reg_has_output_reload[nregno + nr] = 1; |
5852 | ||
5853 | if (i >= 0) | |
32131a9c | 5854 | { |
8ec450a4 | 5855 | nr = HARD_REGNO_NREGS (i, rld[r].mode); |
372e033b | 5856 | while (--nr >= 0) |
e6e52be0 | 5857 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
5858 | } |
5859 | ||
eceef4c9 BS |
5860 | if (rld[r].when_needed != RELOAD_OTHER |
5861 | && rld[r].when_needed != RELOAD_FOR_OUTPUT | |
5862 | && rld[r].when_needed != RELOAD_FOR_INSN) | |
32131a9c RK |
5863 | abort (); |
5864 | } | |
5865 | } | |
5866 | } | |
cb2afeb3 R |
5867 | |
5868 | /* Deallocate the reload register for reload R. This is called from | |
5869 | remove_address_replacements. */ | |
1d813780 | 5870 | |
cb2afeb3 R |
5871 | void |
5872 | deallocate_reload_reg (r) | |
5873 | int r; | |
5874 | { | |
5875 | int regno; | |
5876 | ||
eceef4c9 | 5877 | if (! rld[r].reg_rtx) |
cb2afeb3 | 5878 | return; |
eceef4c9 BS |
5879 | regno = true_regnum (rld[r].reg_rtx); |
5880 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 5881 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 5882 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 5883 | rld[r].mode); |
cb2afeb3 R |
5884 | reload_spill_index[r] = -1; |
5885 | } | |
32131a9c | 5886 | \f |
e9a25f70 | 5887 | /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two |
546b63fb RK |
5888 | reloads of the same item for fear that we might not have enough reload |
5889 | registers. However, normally they will get the same reload register | |
05d10675 | 5890 | and hence actually need not be loaded twice. |
546b63fb RK |
5891 | |
5892 | Here we check for the most common case of this phenomenon: when we have | |
5893 | a number of reloads for the same object, each of which were allocated | |
5894 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
5895 | reload, and is not modified in the insn itself. If we find such, | |
5896 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
5897 | This will not increase the number of spill registers needed and will | |
5898 | prevent redundant code. */ | |
5899 | ||
546b63fb RK |
5900 | static void |
5901 | merge_assigned_reloads (insn) | |
5902 | rtx insn; | |
5903 | { | |
5904 | int i, j; | |
5905 | ||
5906 | /* Scan all the reloads looking for ones that only load values and | |
5907 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
5908 | assigned and not modified by INSN. */ | |
5909 | ||
5910 | for (i = 0; i < n_reloads; i++) | |
5911 | { | |
d668e863 R |
5912 | int conflicting_input = 0; |
5913 | int max_input_address_opnum = -1; | |
5914 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
5915 | ||
eceef4c9 BS |
5916 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
5917 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
5918 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
5919 | continue; |
5920 | ||
5921 | /* Look at all other reloads. Ensure that the only use of this | |
5922 | reload_reg_rtx is in a reload that just loads the same value | |
5923 | as we do. Note that any secondary reloads must be of the identical | |
5924 | class since the values, modes, and result registers are the | |
5925 | same, so we need not do anything with any secondary reloads. */ | |
5926 | ||
5927 | for (j = 0; j < n_reloads; j++) | |
5928 | { | |
eceef4c9 BS |
5929 | if (i == j || rld[j].reg_rtx == 0 |
5930 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
5931 | rld[i].reg_rtx)) | |
546b63fb RK |
5932 | continue; |
5933 | ||
eceef4c9 BS |
5934 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
5935 | && rld[j].opnum > max_input_address_opnum) | |
5936 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 5937 | |
546b63fb | 5938 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
5939 | or if the values are different, we can't merge this reload. |
5940 | But if it is an input reload, we might still merge | |
5941 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 5942 | |
eceef4c9 BS |
5943 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
5944 | || rld[j].out != 0 || rld[j].in == 0 | |
5945 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 5946 | { |
eceef4c9 BS |
5947 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
5948 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
5949 | || rld[i].opnum > rld[j].opnum) | |
5950 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
5951 | break; |
5952 | conflicting_input = 1; | |
eceef4c9 BS |
5953 | if (min_conflicting_input_opnum > rld[j].opnum) |
5954 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 5955 | } |
546b63fb RK |
5956 | } |
5957 | ||
5958 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
5959 | we, in fact, found any matching reloads. */ | |
5960 | ||
d668e863 R |
5961 | if (j == n_reloads |
5962 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb RK |
5963 | { |
5964 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5965 | if (i != j && rld[j].reg_rtx != 0 |
5966 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 5967 | && (! conflicting_input |
eceef4c9 BS |
5968 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
5969 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 5970 | { |
eceef4c9 BS |
5971 | rld[i].when_needed = RELOAD_OTHER; |
5972 | rld[j].in = 0; | |
efdb3590 | 5973 | reload_spill_index[j] = -1; |
546b63fb RK |
5974 | transfer_replacements (i, j); |
5975 | } | |
5976 | ||
5977 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
5978 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
5979 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
5980 | this test is equivalent to looking for reloads for this operand | |
5981 | number. */ | |
5982 | ||
eceef4c9 | 5983 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 5984 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
5985 | if (rld[j].in != 0 |
5986 | && rld[i].when_needed != RELOAD_OTHER | |
5987 | && reg_overlap_mentioned_for_reload_p (rld[j].in, | |
5988 | rld[i].in)) | |
5989 | rld[j].when_needed | |
5990 | = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
5991 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
47c8cf91 | 5992 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); |
546b63fb RK |
5993 | } |
5994 | } | |
05d10675 | 5995 | } |
546b63fb | 5996 | \f |
367b1cf5 BS |
5997 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
5998 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
5999 | static rtx other_input_address_reload_insns = 0; | |
6000 | static rtx other_input_reload_insns = 0; | |
6001 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6002 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6003 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6004 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6005 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6006 | static rtx operand_reload_insns = 0; | |
6007 | static rtx other_operand_reload_insns = 0; | |
6008 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6009 | ||
6010 | /* Values to be put in spill_reg_store are put here first. */ | |
6011 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6012 | static HARD_REG_SET reg_reloaded_died; | |
6013 | ||
6014 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and | |
6015 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6016 | |
32131a9c | 6017 | static void |
367b1cf5 | 6018 | emit_input_reload_insns (chain, rl, old, j) |
7609e720 | 6019 | struct insn_chain *chain; |
367b1cf5 BS |
6020 | struct reload *rl; |
6021 | rtx old; | |
6022 | int j; | |
32131a9c | 6023 | { |
7609e720 | 6024 | rtx insn = chain->insn; |
367b1cf5 BS |
6025 | register rtx reloadreg = rl->reg_rtx; |
6026 | rtx oldequiv_reg = 0; | |
6027 | rtx oldequiv = 0; | |
6028 | int special = 0; | |
6029 | enum machine_mode mode; | |
6030 | rtx *where; | |
6031 | ||
6032 | /* Determine the mode to reload in. | |
6033 | This is very tricky because we have three to choose from. | |
6034 | There is the mode the insn operand wants (rl->inmode). | |
6035 | There is the mode of the reload register RELOADREG. | |
6036 | There is the intrinsic mode of the operand, which we could find | |
6037 | by stripping some SUBREGs. | |
6038 | It turns out that RELOADREG's mode is irrelevant: | |
6039 | we can change that arbitrarily. | |
6040 | ||
6041 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
6042 | then the reload reg may not support QImode moves, so use SImode. | |
6043 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
6044 | because the QImode value is in the least significant part of a | |
6045 | slot big enough for a SImode. If foo is some other sort of | |
6046 | memory reference, then it is impossible to reload this case, | |
6047 | so previous passes had better make sure this never happens. | |
6048 | ||
6049 | Then consider a one-word union which has SImode and one of its | |
6050 | members is a float, being fetched as (SUBREG:SF union:SI). | |
6051 | We must fetch that as SFmode because we could be loading into | |
6052 | a float-only register. In this case OLD's mode is correct. | |
6053 | ||
6054 | Consider an immediate integer: it has VOIDmode. Here we need | |
6055 | to get a mode from something else. | |
6056 | ||
6057 | In some cases, there is a fourth mode, the operand's | |
6058 | containing mode. If the insn specifies a containing mode for | |
6059 | this operand, it overrides all others. | |
6060 | ||
6061 | I am not sure whether the algorithm here is always right, | |
6062 | but it does the right things in those cases. */ | |
6063 | ||
6064 | mode = GET_MODE (old); | |
6065 | if (mode == VOIDmode) | |
6066 | mode = rl->inmode; | |
7609e720 | 6067 | |
367b1cf5 BS |
6068 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6069 | /* If we need a secondary register for this operation, see if | |
6070 | the value is already in a register in that class. Don't | |
6071 | do this if the secondary register will be used as a scratch | |
6072 | register. */ | |
6073 | ||
6074 | if (rl->secondary_in_reload >= 0 | |
6075 | && rl->secondary_in_icode == CODE_FOR_nothing | |
6076 | && optimize) | |
6077 | oldequiv | |
6078 | = find_equiv_reg (old, insn, | |
6079 | rld[rl->secondary_in_reload].class, | |
6080 | -1, NULL_PTR, 0, mode); | |
6081 | #endif | |
e6e52be0 | 6082 | |
367b1cf5 BS |
6083 | /* If reloading from memory, see if there is a register |
6084 | that already holds the same value. If so, reload from there. | |
6085 | We can pass 0 as the reload_reg_p argument because | |
6086 | any other reload has either already been emitted, | |
6087 | in which case find_equiv_reg will see the reload-insn, | |
6088 | or has yet to be emitted, in which case it doesn't matter | |
6089 | because we will use this equiv reg right away. */ | |
6090 | ||
6091 | if (oldequiv == 0 && optimize | |
6092 | && (GET_CODE (old) == MEM | |
6093 | || (GET_CODE (old) == REG | |
6094 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6095 | && reg_renumber[REGNO (old)] < 0))) | |
6096 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, | |
6097 | -1, NULL_PTR, 0, mode); | |
6098 | ||
6099 | if (oldequiv) | |
6100 | { | |
770ae6cc | 6101 | unsigned int regno = true_regnum (oldequiv); |
367b1cf5 BS |
6102 | |
6103 | /* Don't use OLDEQUIV if any other reload changes it at an | |
6104 | earlier stage of this insn or at this stage. */ | |
c02cad8f BS |
6105 | if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed, |
6106 | rl->in, const0_rtx, j, 0)) | |
367b1cf5 BS |
6107 | oldequiv = 0; |
6108 | ||
6109 | /* If it is no cheaper to copy from OLDEQUIV into the | |
6110 | reload register than it would be to move from memory, | |
6111 | don't use it. Likewise, if we need a secondary register | |
6112 | or memory. */ | |
6113 | ||
6114 | if (oldequiv != 0 | |
6115 | && ((REGNO_REG_CLASS (regno) != rl->class | |
6116 | && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno), | |
6117 | rl->class) | |
6118 | >= MEMORY_MOVE_COST (mode, rl->class, 1))) | |
6119 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
6120 | || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6121 | mode, oldequiv) | |
6122 | != NO_REGS) | |
6123 | #endif | |
6124 | #ifdef SECONDARY_MEMORY_NEEDED | |
6125 | || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), | |
6126 | rl->class, | |
6127 | mode) | |
6128 | #endif | |
6129 | )) | |
6130 | oldequiv = 0; | |
6131 | } | |
32131a9c | 6132 | |
367b1cf5 BS |
6133 | /* delete_output_reload is only invoked properly if old contains |
6134 | the original pseudo register. Since this is replaced with a | |
6135 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6136 | find the pseudo in RELOAD_IN_REG. */ | |
6137 | if (oldequiv == 0 | |
6138 | && reload_override_in[j] | |
6139 | && GET_CODE (rl->in_reg) == REG) | |
6140 | { | |
6141 | oldequiv = old; | |
6142 | old = rl->in_reg; | |
6143 | } | |
6144 | if (oldequiv == 0) | |
6145 | oldequiv = old; | |
6146 | else if (GET_CODE (oldequiv) == REG) | |
6147 | oldequiv_reg = oldequiv; | |
6148 | else if (GET_CODE (oldequiv) == SUBREG) | |
6149 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6150 | ||
6151 | /* If we are reloading from a register that was recently stored in | |
6152 | with an output-reload, see if we can prove there was | |
6153 | actually no need to store the old value in it. */ | |
6154 | ||
6155 | if (optimize && GET_CODE (oldequiv) == REG | |
6156 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6157 | && spill_reg_store[REGNO (oldequiv)] | |
6158 | && GET_CODE (old) == REG | |
6159 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) | |
6160 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6161 | rl->out_reg))) | |
6162 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6163 | ||
6164 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6165 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6166 | gen_lowpart_common since it can do the wrong thing when | |
6167 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6168 | must always be a REG here. */ | |
6169 | ||
6170 | if (GET_MODE (reloadreg) != mode) | |
6171 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6172 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) | |
6173 | oldequiv = SUBREG_REG (oldequiv); | |
6174 | if (GET_MODE (oldequiv) != VOIDmode | |
6175 | && mode != GET_MODE (oldequiv)) | |
6176 | oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0); | |
6177 | ||
6178 | /* Switch to the right place to emit the reload insns. */ | |
6179 | switch (rl->when_needed) | |
6180 | { | |
6181 | case RELOAD_OTHER: | |
6182 | where = &other_input_reload_insns; | |
6183 | break; | |
6184 | case RELOAD_FOR_INPUT: | |
6185 | where = &input_reload_insns[rl->opnum]; | |
6186 | break; | |
6187 | case RELOAD_FOR_INPUT_ADDRESS: | |
6188 | where = &input_address_reload_insns[rl->opnum]; | |
6189 | break; | |
6190 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6191 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6192 | break; | |
6193 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6194 | where = &output_address_reload_insns[rl->opnum]; | |
6195 | break; | |
6196 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6197 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6198 | break; | |
6199 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6200 | where = &operand_reload_insns; | |
6201 | break; | |
6202 | case RELOAD_FOR_OPADDR_ADDR: | |
6203 | where = &other_operand_reload_insns; | |
6204 | break; | |
6205 | case RELOAD_FOR_OTHER_ADDRESS: | |
6206 | where = &other_input_address_reload_insns; | |
6207 | break; | |
6208 | default: | |
6209 | abort (); | |
6210 | } | |
546b63fb | 6211 | |
367b1cf5 | 6212 | push_to_sequence (*where); |
32131a9c | 6213 | |
367b1cf5 BS |
6214 | /* Auto-increment addresses must be reloaded in a special way. */ |
6215 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6216 | { |
367b1cf5 BS |
6217 | /* We are not going to bother supporting the case where a |
6218 | incremented register can't be copied directly from | |
6219 | OLDEQUIV since this seems highly unlikely. */ | |
6220 | if (rl->secondary_in_reload >= 0) | |
6221 | abort (); | |
32131a9c | 6222 | |
367b1cf5 BS |
6223 | if (reload_inherited[j]) |
6224 | oldequiv = reloadreg; | |
cb2afeb3 | 6225 | |
367b1cf5 | 6226 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6227 | |
367b1cf5 BS |
6228 | if (optimize && GET_CODE (oldequiv) == REG |
6229 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6230 | && spill_reg_store[REGNO (oldequiv)] | |
6231 | && GET_CODE (old) == REG | |
6232 | && (dead_or_set_p (insn, | |
6233 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6234 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6235 | old))) | |
6236 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6237 | ||
6238 | /* Prevent normal processing of this reload. */ | |
6239 | special = 1; | |
6240 | /* Output a special code sequence for this case. */ | |
6241 | new_spill_reg_store[REGNO (reloadreg)] | |
6242 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6243 | rl->inc); | |
6244 | } | |
32131a9c | 6245 | |
367b1cf5 BS |
6246 | /* If we are reloading a pseudo-register that was set by the previous |
6247 | insn, see if we can get rid of that pseudo-register entirely | |
6248 | by redirecting the previous insn into our reload register. */ | |
6249 | ||
6250 | else if (optimize && GET_CODE (old) == REG | |
6251 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6252 | && dead_or_set_p (insn, old) | |
6253 | /* This is unsafe if some other reload | |
6254 | uses the same reg first. */ | |
ff6534ad | 6255 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6256 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6257 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6258 | { |
6259 | rtx temp = PREV_INSN (insn); | |
6260 | while (temp && GET_CODE (temp) == NOTE) | |
6261 | temp = PREV_INSN (temp); | |
6262 | if (temp | |
6263 | && GET_CODE (temp) == INSN | |
6264 | && GET_CODE (PATTERN (temp)) == SET | |
6265 | && SET_DEST (PATTERN (temp)) == old | |
6266 | /* Make sure we can access insn_operand_constraint. */ | |
6267 | && asm_noperands (PATTERN (temp)) < 0 | |
6268 | /* This is unsafe if prev insn rejects our reload reg. */ | |
6269 | && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint, | |
6270 | reloadreg) | |
6271 | /* This is unsafe if operand occurs more than once in current | |
6272 | insn. Perhaps some occurrences aren't reloaded. */ | |
4b983fdc | 6273 | && count_occurrences (PATTERN (insn), old, 0) == 1 |
367b1cf5 BS |
6274 | /* Don't risk splitting a matching pair of operands. */ |
6275 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
6276 | { | |
6277 | /* Store into the reload register instead of the pseudo. */ | |
6278 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6279 | ||
6280 | /* If the previous insn is an output reload, the source is | |
6281 | a reload register, and its spill_reg_store entry will | |
6282 | contain the previous destination. This is now | |
6283 | invalid. */ | |
6284 | if (GET_CODE (SET_SRC (PATTERN (temp))) == REG | |
6285 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) | |
32131a9c | 6286 | { |
367b1cf5 BS |
6287 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; |
6288 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
32131a9c RK |
6289 | } |
6290 | ||
367b1cf5 BS |
6291 | /* If these are the only uses of the pseudo reg, |
6292 | pretend for GDB it lives in the reload reg we used. */ | |
6293 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6294 | && REG_N_SETS (REGNO (old)) == 1) | |
cb2afeb3 | 6295 | { |
367b1cf5 BS |
6296 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); |
6297 | alter_reg (REGNO (old), -1); | |
32131a9c | 6298 | } |
07875628 | 6299 | special = 1; |
367b1cf5 BS |
6300 | } |
6301 | } | |
32131a9c | 6302 | |
367b1cf5 | 6303 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6304 | |
367b1cf5 BS |
6305 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6306 | /* If we have a secondary reload, pick up the secondary register | |
6307 | and icode, if any. If OLDEQUIV and OLD are different or | |
6308 | if this is an in-out reload, recompute whether or not we | |
6309 | still need a secondary register and what the icode should | |
6310 | be. If we still need a secondary register and the class or | |
6311 | icode is different, go back to reloading from OLD if using | |
6312 | OLDEQUIV means that we got the wrong type of register. We | |
6313 | cannot have different class or icode due to an in-out reload | |
6314 | because we don't make such reloads when both the input and | |
6315 | output need secondary reload registers. */ | |
6316 | ||
07875628 | 6317 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6318 | { |
6319 | rtx second_reload_reg = 0; | |
6320 | int secondary_reload = rl->secondary_in_reload; | |
6321 | rtx real_oldequiv = oldequiv; | |
6322 | rtx real_old = old; | |
6323 | rtx tmp; | |
6324 | enum insn_code icode; | |
6325 | ||
6326 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6327 | and similarly for OLD. | |
6328 | See comments in get_secondary_reload in reload.c. */ | |
6329 | /* If it is a pseudo that cannot be replaced with its | |
6330 | equivalent MEM, we must fall back to reload_in, which | |
6331 | will have all the necessary substitutions registered. | |
6332 | Likewise for a pseudo that can't be replaced with its | |
6333 | equivalent constant. | |
6334 | ||
6335 | Take extra care for subregs of such pseudos. Note that | |
6336 | we cannot use reg_equiv_mem in this case because it is | |
6337 | not in the right mode. */ | |
6338 | ||
6339 | tmp = oldequiv; | |
6340 | if (GET_CODE (tmp) == SUBREG) | |
6341 | tmp = SUBREG_REG (tmp); | |
6342 | if (GET_CODE (tmp) == REG | |
6343 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6344 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6345 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6346 | { | |
6347 | if (! reg_equiv_mem[REGNO (tmp)] | |
6348 | || num_not_at_initial_offset | |
6349 | || GET_CODE (oldequiv) == SUBREG) | |
6350 | real_oldequiv = rl->in; | |
6351 | else | |
6352 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6353 | } | |
32131a9c | 6354 | |
367b1cf5 BS |
6355 | tmp = old; |
6356 | if (GET_CODE (tmp) == SUBREG) | |
6357 | tmp = SUBREG_REG (tmp); | |
6358 | if (GET_CODE (tmp) == REG | |
6359 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6360 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6361 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6362 | { | |
6363 | if (! reg_equiv_mem[REGNO (tmp)] | |
6364 | || num_not_at_initial_offset | |
6365 | || GET_CODE (old) == SUBREG) | |
6366 | real_old = rl->in; | |
6367 | else | |
6368 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6369 | } | |
6370 | ||
6371 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
6372 | icode = rl->secondary_in_icode; | |
6373 | ||
6374 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6375 | || (rl->in != 0 && rl->out != 0)) | |
6376 | { | |
6377 | enum reg_class new_class | |
6378 | = SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6379 | mode, real_oldequiv); | |
6380 | ||
6381 | if (new_class == NO_REGS) | |
6382 | second_reload_reg = 0; | |
6383 | else | |
32131a9c | 6384 | { |
367b1cf5 BS |
6385 | enum insn_code new_icode; |
6386 | enum machine_mode new_mode; | |
6387 | ||
6388 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
6389 | REGNO (second_reload_reg))) | |
6390 | oldequiv = old, real_oldequiv = real_old; | |
6391 | else | |
32131a9c | 6392 | { |
367b1cf5 BS |
6393 | new_icode = reload_in_optab[(int) mode]; |
6394 | if (new_icode != CODE_FOR_nothing | |
6395 | && ((insn_data[(int) new_icode].operand[0].predicate | |
6396 | && ! ((*insn_data[(int) new_icode].operand[0].predicate) | |
6397 | (reloadreg, mode))) | |
6398 | || (insn_data[(int) new_icode].operand[1].predicate | |
6399 | && ! ((*insn_data[(int) new_icode].operand[1].predicate) | |
6400 | (real_oldequiv, mode))))) | |
6401 | new_icode = CODE_FOR_nothing; | |
6402 | ||
6403 | if (new_icode == CODE_FOR_nothing) | |
6404 | new_mode = mode; | |
6405 | else | |
6406 | new_mode = insn_data[(int) new_icode].operand[2].mode; | |
d30e8ef0 | 6407 | |
367b1cf5 | 6408 | if (GET_MODE (second_reload_reg) != new_mode) |
32131a9c | 6409 | { |
367b1cf5 BS |
6410 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), |
6411 | new_mode)) | |
6412 | oldequiv = old, real_oldequiv = real_old; | |
6413 | else | |
6414 | second_reload_reg | |
6415 | = gen_rtx_REG (new_mode, | |
6416 | REGNO (second_reload_reg)); | |
32131a9c | 6417 | } |
32131a9c RK |
6418 | } |
6419 | } | |
367b1cf5 | 6420 | } |
32131a9c | 6421 | |
367b1cf5 BS |
6422 | /* If we still need a secondary reload register, check |
6423 | to see if it is being used as a scratch or intermediate | |
6424 | register and generate code appropriately. If we need | |
6425 | a scratch register, use REAL_OLDEQUIV since the form of | |
6426 | the insn may depend on the actual address if it is | |
6427 | a MEM. */ | |
546b63fb | 6428 | |
367b1cf5 BS |
6429 | if (second_reload_reg) |
6430 | { | |
6431 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6432 | { |
367b1cf5 BS |
6433 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6434 | second_reload_reg)); | |
07875628 | 6435 | special = 1; |
367b1cf5 BS |
6436 | } |
6437 | else | |
6438 | { | |
6439 | /* See if we need a scratch register to load the | |
6440 | intermediate register (a tertiary reload). */ | |
6441 | enum insn_code tertiary_icode | |
6442 | = rld[secondary_reload].secondary_in_icode; | |
1554c2c6 | 6443 | |
367b1cf5 BS |
6444 | if (tertiary_icode != CODE_FOR_nothing) |
6445 | { | |
6446 | rtx third_reload_reg | |
6447 | = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; | |
1554c2c6 | 6448 | |
367b1cf5 BS |
6449 | emit_insn ((GEN_FCN (tertiary_icode) |
6450 | (second_reload_reg, real_oldequiv, | |
6451 | third_reload_reg))); | |
6452 | } | |
6453 | else | |
6454 | gen_reload (second_reload_reg, real_oldequiv, | |
6455 | rl->opnum, | |
6456 | rl->when_needed); | |
32131a9c | 6457 | |
367b1cf5 BS |
6458 | oldequiv = second_reload_reg; |
6459 | } | |
6460 | } | |
6461 | } | |
6462 | #endif | |
32131a9c | 6463 | |
07875628 | 6464 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6465 | { |
6466 | rtx real_oldequiv = oldequiv; | |
6467 | ||
6468 | if ((GET_CODE (oldequiv) == REG | |
6469 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
6470 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6471 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6472 | || (GET_CODE (oldequiv) == SUBREG | |
6473 | && GET_CODE (SUBREG_REG (oldequiv)) == REG | |
6474 | && (REGNO (SUBREG_REG (oldequiv)) | |
6475 | >= FIRST_PSEUDO_REGISTER) | |
6476 | && ((reg_equiv_memory_loc | |
6477 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6478 | || (reg_equiv_constant | |
716120a7 JJ |
6479 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
6480 | || (CONSTANT_P (oldequiv) | |
6481 | && PREFERRED_RELOAD_CLASS (oldequiv, | |
6482 | REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS)) | |
367b1cf5 BS |
6483 | real_oldequiv = rl->in; |
6484 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6485 | rl->when_needed); | |
6486 | } | |
32131a9c | 6487 | |
367b1cf5 BS |
6488 | /* End this sequence. */ |
6489 | *where = get_insns (); | |
6490 | end_sequence (); | |
32131a9c | 6491 | |
367b1cf5 BS |
6492 | /* Update reload_override_in so that delete_address_reloads_1 |
6493 | can see the actual register usage. */ | |
6494 | if (oldequiv_reg) | |
6495 | reload_override_in[j] = oldequiv; | |
6496 | } | |
32131a9c | 6497 | |
367b1cf5 BS |
6498 | /* Generate insns to for the output reload RL, which is for the insn described |
6499 | by CHAIN and has the number J. */ | |
6500 | static void | |
6501 | emit_output_reload_insns (chain, rl, j) | |
6502 | struct insn_chain *chain; | |
6503 | struct reload *rl; | |
6504 | int j; | |
6505 | { | |
6506 | rtx reloadreg = rl->reg_rtx; | |
6507 | rtx insn = chain->insn; | |
6508 | int special = 0; | |
6509 | rtx old = rl->out; | |
6510 | enum machine_mode mode = GET_MODE (old); | |
6511 | rtx p; | |
32131a9c | 6512 | |
367b1cf5 BS |
6513 | if (rl->when_needed == RELOAD_OTHER) |
6514 | start_sequence (); | |
6515 | else | |
6516 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 6517 | |
367b1cf5 BS |
6518 | /* Determine the mode to reload in. |
6519 | See comments above (for input reloading). */ | |
32131a9c | 6520 | |
367b1cf5 BS |
6521 | if (mode == VOIDmode) |
6522 | { | |
6523 | /* VOIDmode should never happen for an output. */ | |
6524 | if (asm_noperands (PATTERN (insn)) < 0) | |
6525 | /* It's the compiler's fault. */ | |
6526 | fatal_insn ("VOIDmode on an output", insn); | |
6527 | error_for_asm (insn, "output operand is constant in `asm'"); | |
6528 | /* Prevent crash--use something we know is valid. */ | |
6529 | mode = word_mode; | |
6530 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6531 | } | |
546b63fb | 6532 | |
367b1cf5 BS |
6533 | if (GET_MODE (reloadreg) != mode) |
6534 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
32131a9c | 6535 | |
367b1cf5 | 6536 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
32131a9c | 6537 | |
367b1cf5 BS |
6538 | /* If we need two reload regs, set RELOADREG to the intermediate |
6539 | one, since it will be stored into OLD. We might need a secondary | |
6540 | register only for an input reload, so check again here. */ | |
32131a9c | 6541 | |
367b1cf5 BS |
6542 | if (rl->secondary_out_reload >= 0) |
6543 | { | |
6544 | rtx real_old = old; | |
cb2afeb3 | 6545 | |
367b1cf5 BS |
6546 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6547 | && reg_equiv_mem[REGNO (old)] != 0) | |
6548 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 6549 | |
367b1cf5 BS |
6550 | if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, |
6551 | mode, real_old) | |
6552 | != NO_REGS)) | |
b60a8416 | 6553 | { |
367b1cf5 BS |
6554 | rtx second_reloadreg = reloadreg; |
6555 | reloadreg = rld[rl->secondary_out_reload].reg_rtx; | |
32131a9c | 6556 | |
367b1cf5 BS |
6557 | /* See if RELOADREG is to be used as a scratch register |
6558 | or as an intermediate register. */ | |
6559 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
6560 | { | |
6561 | emit_insn ((GEN_FCN (rl->secondary_out_icode) | |
6562 | (real_old, second_reloadreg, reloadreg))); | |
6563 | special = 1; | |
6564 | } | |
6565 | else | |
6566 | { | |
6567 | /* See if we need both a scratch and intermediate reload | |
6568 | register. */ | |
32131a9c | 6569 | |
367b1cf5 BS |
6570 | int secondary_reload = rl->secondary_out_reload; |
6571 | enum insn_code tertiary_icode | |
6572 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 6573 | |
367b1cf5 BS |
6574 | if (GET_MODE (reloadreg) != mode) |
6575 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
cb2afeb3 | 6576 | |
367b1cf5 BS |
6577 | if (tertiary_icode != CODE_FOR_nothing) |
6578 | { | |
6579 | rtx third_reloadreg | |
6580 | = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; | |
6581 | rtx tem; | |
6582 | ||
6583 | /* Copy primary reload reg to secondary reload reg. | |
6584 | (Note that these have been swapped above, then | |
6585 | secondary reload reg to OLD using our insn. */ | |
6586 | ||
6587 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
6588 | and try to put the opposite SUBREG on | |
6589 | RELOADREG. */ | |
6590 | if (GET_CODE (real_old) == SUBREG | |
6591 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
6592 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
6593 | && 0 != (tem = gen_lowpart_common | |
6594 | (GET_MODE (SUBREG_REG (real_old)), | |
6595 | reloadreg))) | |
6596 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
6597 | ||
6598 | gen_reload (reloadreg, second_reloadreg, | |
6599 | rl->opnum, rl->when_needed); | |
6600 | emit_insn ((GEN_FCN (tertiary_icode) | |
6601 | (real_old, reloadreg, third_reloadreg))); | |
6602 | special = 1; | |
6603 | } | |
05d10675 | 6604 | |
367b1cf5 BS |
6605 | else |
6606 | /* Copy between the reload regs here and then to | |
6607 | OUT later. */ | |
cb2afeb3 | 6608 | |
367b1cf5 BS |
6609 | gen_reload (reloadreg, second_reloadreg, |
6610 | rl->opnum, rl->when_needed); | |
a7911cd2 | 6611 | } |
367b1cf5 BS |
6612 | } |
6613 | } | |
32131a9c RK |
6614 | #endif |
6615 | ||
367b1cf5 BS |
6616 | /* Output the last reload insn. */ |
6617 | if (! special) | |
6618 | { | |
6619 | rtx set; | |
6620 | ||
6621 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 6622 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 BS |
6623 | if (! flag_expensive_optimizations |
6624 | || GET_CODE (old) != REG | |
6625 | || !(set = single_set (insn)) | |
6626 | || rtx_equal_p (old, SET_DEST (set)) | |
6627 | || !reg_mentioned_p (old, SET_SRC (set)) | |
9532e31f | 6628 | || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0)) |
367b1cf5 BS |
6629 | gen_reload (old, reloadreg, rl->opnum, |
6630 | rl->when_needed); | |
6631 | } | |
32131a9c | 6632 | |
367b1cf5 BS |
6633 | /* Look at all insns we emitted, just to be safe. */ |
6634 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 6635 | if (INSN_P (p)) |
367b1cf5 BS |
6636 | { |
6637 | rtx pat = PATTERN (p); | |
546b63fb | 6638 | |
367b1cf5 BS |
6639 | /* If this output reload doesn't come from a spill reg, |
6640 | clear any memory of reloaded copies of the pseudo reg. | |
6641 | If this output reload comes from a spill reg, | |
6642 | reg_has_output_reload will make this do nothing. */ | |
6643 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 6644 | |
367b1cf5 BS |
6645 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
6646 | { | |
6647 | rtx set = single_set (insn); | |
6648 | if (reload_spill_index[j] < 0 | |
6649 | && set | |
6650 | && SET_SRC (set) == rl->reg_rtx) | |
6651 | { | |
6652 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 6653 | |
367b1cf5 BS |
6654 | reload_spill_index[j] = src; |
6655 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
6656 | if (find_regno_note (insn, REG_DEAD, src)) | |
6657 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
6658 | } | |
6659 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6660 | { | |
6661 | int s = rl->secondary_out_reload; | |
6662 | set = single_set (p); | |
6663 | /* If this reload copies only to the secondary reload | |
6664 | register, the secondary reload does the actual | |
6665 | store. */ | |
6666 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
6667 | /* We can't tell what function the secondary reload |
6668 | has and where the actual store to the pseudo is | |
6669 | made; leave new_spill_reg_store alone. */ | |
6670 | ; | |
367b1cf5 BS |
6671 | else if (s >= 0 |
6672 | && SET_SRC (set) == rl->reg_rtx | |
6673 | && SET_DEST (set) == rld[s].reg_rtx) | |
6674 | { | |
6675 | /* Usually the next instruction will be the | |
6676 | secondary reload insn; if we can confirm | |
6677 | that it is, setting new_spill_reg_store to | |
6678 | that insn will allow an extra optimization. */ | |
6679 | rtx s_reg = rld[s].reg_rtx; | |
6680 | rtx next = NEXT_INSN (p); | |
6681 | rld[s].out = rl->out; | |
6682 | rld[s].out_reg = rl->out_reg; | |
6683 | set = single_set (next); | |
6684 | if (set && SET_SRC (set) == s_reg | |
6685 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
6686 | { | |
6687 | SET_HARD_REG_BIT (reg_is_output_reload, | |
6688 | REGNO (s_reg)); | |
6689 | new_spill_reg_store[REGNO (s_reg)] = next; | |
6690 | } | |
6691 | } | |
6692 | else | |
6693 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
6694 | } | |
6695 | } | |
6696 | } | |
32131a9c | 6697 | |
367b1cf5 BS |
6698 | if (rl->when_needed == RELOAD_OTHER) |
6699 | { | |
6700 | emit_insns (other_output_reload_insns[rl->opnum]); | |
6701 | other_output_reload_insns[rl->opnum] = get_insns (); | |
6702 | } | |
6703 | else | |
6704 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 6705 | |
1d7254c5 | 6706 | end_sequence (); |
367b1cf5 | 6707 | } |
32131a9c | 6708 | |
367b1cf5 BS |
6709 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
6710 | and has the number J. */ | |
6711 | static void | |
6712 | do_input_reload (chain, rl, j) | |
6713 | struct insn_chain *chain; | |
6714 | struct reload *rl; | |
6715 | int j; | |
6716 | { | |
6717 | int expect_occurrences = 1; | |
6718 | rtx insn = chain->insn; | |
6719 | rtx old = (rl->in && GET_CODE (rl->in) == MEM | |
6720 | ? rl->in_reg : rl->in); | |
6721 | ||
6722 | if (old != 0 | |
6723 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
6724 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
6725 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
6726 | && ! rtx_equal_p (rl->reg_rtx, old) | |
6727 | && rl->reg_rtx != 0) | |
1d813780 | 6728 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 6729 | |
367b1cf5 BS |
6730 | /* When inheriting a wider reload, we have a MEM in rl->in, |
6731 | e.g. inheriting a SImode output reload for | |
6732 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
6733 | if (optimize && reload_inherited[j] && rl->in | |
6734 | && GET_CODE (rl->in) == MEM | |
6735 | && GET_CODE (rl->in_reg) == MEM | |
6736 | && reload_spill_index[j] >= 0 | |
6737 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
6738 | { | |
6739 | expect_occurrences | |
4b983fdc | 6740 | = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1; |
1d7254c5 | 6741 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
367b1cf5 | 6742 | } |
32131a9c | 6743 | |
367b1cf5 BS |
6744 | /* If we are reloading a register that was recently stored in with an |
6745 | output-reload, see if we can prove there was | |
6746 | actually no need to store the old value in it. */ | |
32131a9c | 6747 | |
367b1cf5 BS |
6748 | if (optimize |
6749 | && (reload_inherited[j] || reload_override_in[j]) | |
6750 | && rl->reg_rtx | |
6751 | && GET_CODE (rl->reg_rtx) == REG | |
6752 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 | |
6753 | #if 0 | |
6754 | /* There doesn't seem to be any reason to restrict this to pseudos | |
6755 | and doing so loses in the case where we are copying from a | |
6756 | register of the wrong class. */ | |
6757 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6758 | >= FIRST_PSEUDO_REGISTER) | |
6759 | #endif | |
6760 | /* The insn might have already some references to stackslots | |
6761 | replaced by MEMs, while reload_out_reg still names the | |
6762 | original pseudo. */ | |
6763 | && (dead_or_set_p (insn, | |
6764 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6765 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
6766 | rl->out_reg))) | |
6767 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
6768 | } | |
32131a9c | 6769 | |
367b1cf5 BS |
6770 | /* Do output reloading for reload RL, which is for the insn described by |
6771 | CHAIN and has the number J. | |
6772 | ??? At some point we need to support handling output reloads of | |
6773 | JUMP_INSNs or insns that set cc0. */ | |
6774 | static void | |
6775 | do_output_reload (chain, rl, j) | |
6776 | struct insn_chain *chain; | |
6777 | struct reload *rl; | |
6778 | int j; | |
6779 | { | |
6780 | rtx note, old; | |
6781 | rtx insn = chain->insn; | |
6782 | /* If this is an output reload that stores something that is | |
6783 | not loaded in this same reload, see if we can eliminate a previous | |
6784 | store. */ | |
6785 | rtx pseudo = rl->out_reg; | |
6786 | ||
6787 | if (pseudo | |
6788 | && GET_CODE (pseudo) == REG | |
6789 | && ! rtx_equal_p (rl->in_reg, pseudo) | |
6790 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
6791 | && reg_last_reload_reg[REGNO (pseudo)]) | |
6792 | { | |
6793 | int pseudo_no = REGNO (pseudo); | |
6794 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
6795 | ||
6796 | /* We don't need to test full validity of last_regno for | |
6797 | inherit here; we only want to know if the store actually | |
6798 | matches the pseudo. */ | |
60ef417d GK |
6799 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
6800 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
6801 | && spill_reg_store[last_regno] |
6802 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
6803 | delete_output_reload (insn, j, last_regno); | |
6804 | } | |
5e03c156 | 6805 | |
367b1cf5 BS |
6806 | old = rl->out_reg; |
6807 | if (old == 0 | |
6808 | || rl->reg_rtx == old | |
6809 | || rl->reg_rtx == 0) | |
6810 | return; | |
32131a9c | 6811 | |
367b1cf5 BS |
6812 | /* An output operand that dies right away does need a reload, |
6813 | but need not be copied from it. Show the new location in the | |
6814 | REG_UNUSED note. */ | |
6815 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
6816 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
6817 | { | |
6818 | XEXP (note, 0) = rl->reg_rtx; | |
6819 | return; | |
6820 | } | |
6821 | /* Likewise for a SUBREG of an operand that dies. */ | |
6822 | else if (GET_CODE (old) == SUBREG | |
6823 | && GET_CODE (SUBREG_REG (old)) == REG | |
6824 | && 0 != (note = find_reg_note (insn, REG_UNUSED, | |
6825 | SUBREG_REG (old)))) | |
6826 | { | |
6827 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
6828 | rl->reg_rtx); | |
6829 | return; | |
6830 | } | |
6831 | else if (GET_CODE (old) == SCRATCH) | |
6832 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
6833 | but we don't want to make an output reload. */ | |
6834 | return; | |
1554c2c6 | 6835 | |
367b1cf5 BS |
6836 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
6837 | if (GET_CODE (insn) == JUMP_INSN) | |
6838 | abort (); | |
5e03c156 | 6839 | |
367b1cf5 BS |
6840 | emit_output_reload_insns (chain, rld + j, j); |
6841 | } | |
1554c2c6 | 6842 | |
367b1cf5 | 6843 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 6844 | |
367b1cf5 | 6845 | static void |
e04ca094 | 6846 | emit_reload_insns (chain) |
367b1cf5 BS |
6847 | struct insn_chain *chain; |
6848 | { | |
6849 | rtx insn = chain->insn; | |
32131a9c | 6850 | |
367b1cf5 BS |
6851 | register int j; |
6852 | rtx following_insn = NEXT_INSN (insn); | |
6853 | rtx before_insn = PREV_INSN (insn); | |
e6e52be0 | 6854 | |
367b1cf5 | 6855 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 6856 | |
367b1cf5 BS |
6857 | for (j = 0; j < reload_n_operands; j++) |
6858 | input_reload_insns[j] = input_address_reload_insns[j] | |
6859 | = inpaddr_address_reload_insns[j] | |
6860 | = output_reload_insns[j] = output_address_reload_insns[j] | |
6861 | = outaddr_address_reload_insns[j] | |
6862 | = other_output_reload_insns[j] = 0; | |
6863 | other_input_address_reload_insns = 0; | |
6864 | other_input_reload_insns = 0; | |
6865 | operand_reload_insns = 0; | |
6866 | other_operand_reload_insns = 0; | |
32131a9c | 6867 | |
850aac53 | 6868 | /* Dump reloads into the dump file. */ |
e04ca094 | 6869 | if (rtl_dump_file) |
850aac53 | 6870 | { |
e04ca094 JL |
6871 | fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
6872 | debug_reload_to_stream (rtl_dump_file); | |
850aac53 JL |
6873 | } |
6874 | ||
367b1cf5 BS |
6875 | /* Now output the instructions to copy the data into and out of the |
6876 | reload registers. Do these in the order that the reloads were reported, | |
6877 | since reloads of base and index registers precede reloads of operands | |
6878 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 6879 | |
367b1cf5 BS |
6880 | for (j = 0; j < n_reloads; j++) |
6881 | { | |
6882 | if (rld[j].reg_rtx | |
6883 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6884 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 6885 | |
367b1cf5 BS |
6886 | do_input_reload (chain, rld + j, j); |
6887 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
6888 | } |
6889 | ||
546b63fb RK |
6890 | /* Now write all the insns we made for reloads in the order expected by |
6891 | the allocation functions. Prior to the insn being reloaded, we write | |
6892 | the following reloads: | |
6893 | ||
6894 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
6895 | ||
2edc8d65 | 6896 | RELOAD_OTHER reloads. |
546b63fb | 6897 | |
47c8cf91 ILT |
6898 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
6899 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
6900 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 6901 | |
893bc853 RK |
6902 | RELOAD_FOR_OPADDR_ADDRS reloads. |
6903 | ||
546b63fb RK |
6904 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
6905 | ||
6906 | After the insn being reloaded, we write the following: | |
6907 | ||
47c8cf91 ILT |
6908 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
6909 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
6910 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
6911 | reloads for the operand. The RELOAD_OTHER output reloads are | |
6912 | output in descending order by reload number. */ | |
546b63fb | 6913 | |
c93b03c2 RH |
6914 | emit_insns_before (other_input_address_reload_insns, insn); |
6915 | emit_insns_before (other_input_reload_insns, insn); | |
546b63fb RK |
6916 | |
6917 | for (j = 0; j < reload_n_operands; j++) | |
6918 | { | |
c93b03c2 RH |
6919 | emit_insns_before (inpaddr_address_reload_insns[j], insn); |
6920 | emit_insns_before (input_address_reload_insns[j], insn); | |
6921 | emit_insns_before (input_reload_insns[j], insn); | |
546b63fb RK |
6922 | } |
6923 | ||
c93b03c2 RH |
6924 | emit_insns_before (other_operand_reload_insns, insn); |
6925 | emit_insns_before (operand_reload_insns, insn); | |
546b63fb RK |
6926 | |
6927 | for (j = 0; j < reload_n_operands; j++) | |
6928 | { | |
47c8cf91 | 6929 | emit_insns_before (outaddr_address_reload_insns[j], following_insn); |
546b63fb RK |
6930 | emit_insns_before (output_address_reload_insns[j], following_insn); |
6931 | emit_insns_before (output_reload_insns[j], following_insn); | |
befa01b9 | 6932 | emit_insns_before (other_output_reload_insns[j], following_insn); |
c93b03c2 RH |
6933 | } |
6934 | ||
6935 | /* Keep basic block info up to date. */ | |
6936 | if (n_basic_blocks) | |
6937 | { | |
3b413743 | 6938 | if (BLOCK_HEAD (chain->block) == insn) |
05d10675 | 6939 | BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn); |
3b413743 | 6940 | if (BLOCK_END (chain->block) == insn) |
05d10675 | 6941 | BLOCK_END (chain->block) = PREV_INSN (following_insn); |
546b63fb RK |
6942 | } |
6943 | ||
32131a9c RK |
6944 | /* For all the spill regs newly reloaded in this instruction, |
6945 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
6946 | can inherit the reloads. |
6947 | ||
6948 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 6949 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
6950 | |
6951 | for (j = 0; j < n_reloads; j++) | |
6952 | { | |
6953 | register int r = reload_order[j]; | |
6954 | register int i = reload_spill_index[r]; | |
6955 | ||
78a2bc08 | 6956 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
6957 | clear any memory of a previous store to the same pseudo. Only do |
6958 | something if there will not be an output reload for the pseudo | |
6959 | being reloaded. */ | |
eceef4c9 | 6960 | if (rld[r].in_reg != 0 |
05d10675 BS |
6961 | && ! (reload_inherited[r] || reload_override_in[r])) |
6962 | { | |
eceef4c9 | 6963 | rtx reg = rld[r].in_reg; |
78a2bc08 | 6964 | |
05d10675 | 6965 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 6966 | reg = SUBREG_REG (reg); |
05d10675 BS |
6967 | |
6968 | if (GET_CODE (reg) == REG | |
78a2bc08 R |
6969 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
6970 | && ! reg_has_output_reload[REGNO (reg)]) | |
6971 | { | |
6972 | int nregno = REGNO (reg); | |
6973 | ||
6974 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
6975 | { |
6976 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 6977 | |
05d10675 | 6978 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 6979 | spill_reg_store[last_regno] = 0; |
05d10675 | 6980 | } |
78a2bc08 R |
6981 | } |
6982 | } | |
05d10675 | 6983 | |
e6e52be0 | 6984 | /* I is nonneg if this reload used a register. |
eceef4c9 | 6985 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 6986 | that we opted to ignore. */ |
d445b551 | 6987 | |
eceef4c9 | 6988 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 6989 | { |
1d7254c5 | 6990 | int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); |
32131a9c | 6991 | int k; |
51f0c3b7 JW |
6992 | int part_reaches_end = 0; |
6993 | int all_reaches_end = 1; | |
32131a9c | 6994 | |
51f0c3b7 JW |
6995 | /* For a multi register reload, we need to check if all or part |
6996 | of the value lives to the end. */ | |
32131a9c RK |
6997 | for (k = 0; k < nr; k++) |
6998 | { | |
eceef4c9 BS |
6999 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7000 | rld[r].when_needed)) | |
51f0c3b7 JW |
7001 | part_reaches_end = 1; |
7002 | else | |
7003 | all_reaches_end = 0; | |
32131a9c RK |
7004 | } |
7005 | ||
51f0c3b7 JW |
7006 | /* Ignore reloads that don't reach the end of the insn in |
7007 | entirety. */ | |
7008 | if (all_reaches_end) | |
32131a9c | 7009 | { |
51f0c3b7 JW |
7010 | /* First, clear out memory of what used to be in this spill reg. |
7011 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 7012 | |
32131a9c | 7013 | for (k = 0; k < nr; k++) |
e6e52be0 | 7014 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
d08ea79f | 7015 | |
51f0c3b7 | 7016 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 BS |
7017 | if (rld[r].out != 0 |
7018 | && (GET_CODE (rld[r].out) == REG | |
cb2afeb3 | 7019 | #ifdef AUTO_INC_DEC |
eceef4c9 | 7020 | || ! rld[r].out_reg |
cb2afeb3 | 7021 | #endif |
eceef4c9 | 7022 | || GET_CODE (rld[r].out_reg) == REG)) |
51f0c3b7 | 7023 | { |
eceef4c9 BS |
7024 | rtx out = (GET_CODE (rld[r].out) == REG |
7025 | ? rld[r].out | |
7026 | : rld[r].out_reg | |
7027 | ? rld[r].out_reg | |
7028 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
cb2afeb3 | 7029 | register int nregno = REGNO (out); |
51f0c3b7 JW |
7030 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7031 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7032 | GET_MODE (rld[r].reg_rtx))); |
51f0c3b7 JW |
7033 | |
7034 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 7035 | spill_reg_stored_to[i] = out; |
eceef4c9 | 7036 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7037 | |
7038 | /* If NREGNO is a hard register, it may occupy more than | |
05d10675 | 7039 | one register. If it does, say what is in the |
51f0c3b7 JW |
7040 | rest of the registers assuming that both registers |
7041 | agree on how many words the object takes. If not, | |
7042 | invalidate the subsequent registers. */ | |
7043 | ||
7044 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7045 | for (k = 1; k < nnr; k++) | |
7046 | reg_last_reload_reg[nregno + k] | |
7047 | = (nr == nnr | |
eceef4c9 BS |
7048 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
7049 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
7050 | : 0); |
7051 | ||
7052 | /* Now do the inverse operation. */ | |
7053 | for (k = 0; k < nr; k++) | |
7054 | { | |
e6e52be0 R |
7055 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7056 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7057 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7058 | ? nregno | |
7059 | : nregno + k); | |
e6e52be0 R |
7060 | reg_reloaded_insn[i + k] = insn; |
7061 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7062 | } |
7063 | } | |
d08ea79f | 7064 | |
51f0c3b7 JW |
7065 | /* Maybe the spill reg contains a copy of reload_in. Only do |
7066 | something if there will not be an output reload for | |
7067 | the register being reloaded. */ | |
eceef4c9 BS |
7068 | else if (rld[r].out_reg == 0 |
7069 | && rld[r].in != 0 | |
7070 | && ((GET_CODE (rld[r].in) == REG | |
7071 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER | |
7072 | && ! reg_has_output_reload[REGNO (rld[r].in)]) | |
7073 | || (GET_CODE (rld[r].in_reg) == REG | |
7074 | && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) | |
7075 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) | |
51f0c3b7 JW |
7076 | { |
7077 | register int nregno; | |
7078 | int nnr; | |
d445b551 | 7079 | |
eceef4c9 BS |
7080 | if (GET_CODE (rld[r].in) == REG |
7081 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) | |
7082 | nregno = REGNO (rld[r].in); | |
7083 | else if (GET_CODE (rld[r].in_reg) == REG) | |
7084 | nregno = REGNO (rld[r].in_reg); | |
cb2afeb3 | 7085 | else |
eceef4c9 | 7086 | nregno = REGNO (XEXP (rld[r].in_reg, 0)); |
d08ea79f | 7087 | |
51f0c3b7 JW |
7088 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7089 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7090 | GET_MODE (rld[r].reg_rtx))); |
05d10675 | 7091 | |
eceef4c9 | 7092 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7093 | |
7094 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7095 | for (k = 1; k < nnr; k++) | |
7096 | reg_last_reload_reg[nregno + k] | |
7097 | = (nr == nnr | |
eceef4c9 BS |
7098 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
7099 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
7100 | : 0); |
7101 | ||
7102 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7103 | recently done a store. |
7104 | Previous stores of inherited auto_inc expressions | |
7105 | also have to be discarded. */ | |
7106 | if (! reload_inherited[r] | |
eceef4c9 | 7107 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
7108 | spill_reg_store[i] = 0; |
7109 | ||
7110 | for (k = 0; k < nr; k++) | |
7111 | { | |
e6e52be0 R |
7112 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7113 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7114 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7115 | ? nregno | |
7116 | : nregno + k); | |
e6e52be0 R |
7117 | reg_reloaded_insn[i + k] = insn; |
7118 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7119 | } |
7120 | } | |
7121 | } | |
d445b551 | 7122 | |
51f0c3b7 JW |
7123 | /* However, if part of the reload reaches the end, then we must |
7124 | invalidate the old info for the part that survives to the end. */ | |
7125 | else if (part_reaches_end) | |
7126 | { | |
546b63fb | 7127 | for (k = 0; k < nr; k++) |
e6e52be0 | 7128 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
7129 | rld[r].opnum, |
7130 | rld[r].when_needed)) | |
e6e52be0 | 7131 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
7132 | } |
7133 | } | |
7134 | ||
7135 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7136 | It's reenabled in 1.35 because supposedly nothing else | |
7137 | deals with this problem. */ | |
7138 | ||
7139 | /* If a register gets output-reloaded from a non-spill register, | |
7140 | that invalidates any previous reloaded copy of it. | |
7141 | But forget_old_reloads_1 won't get to see it, because | |
7142 | it thinks only about the original insn. So invalidate it here. */ | |
eceef4c9 BS |
7143 | if (i < 0 && rld[r].out != 0 |
7144 | && (GET_CODE (rld[r].out) == REG | |
7145 | || (GET_CODE (rld[r].out) == MEM | |
7146 | && GET_CODE (rld[r].out_reg) == REG))) | |
32131a9c | 7147 | { |
eceef4c9 BS |
7148 | rtx out = (GET_CODE (rld[r].out) == REG |
7149 | ? rld[r].out : rld[r].out_reg); | |
cb2afeb3 | 7150 | register int nregno = REGNO (out); |
c7093272 | 7151 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 7152 | { |
6a651371 | 7153 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
7154 | |
7155 | reg_last_reload_reg[nregno] = 0; | |
7156 | ||
7157 | /* If we can find a hard register that is stored, record | |
7158 | the storing insn so that we may delete this insn with | |
7159 | delete_output_reload. */ | |
eceef4c9 | 7160 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7161 | |
7162 | /* If this is an optional reload, try to find the source reg | |
7163 | from an input reload. */ | |
7164 | if (! src_reg) | |
7165 | { | |
7166 | rtx set = single_set (insn); | |
eceef4c9 | 7167 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7168 | { |
7169 | int k; | |
7170 | ||
7171 | src_reg = SET_SRC (set); | |
7172 | store_insn = insn; | |
7173 | for (k = 0; k < n_reloads; k++) | |
7174 | { | |
eceef4c9 | 7175 | if (rld[k].in == src_reg) |
cb2afeb3 | 7176 | { |
eceef4c9 | 7177 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7178 | break; |
7179 | } | |
7180 | } | |
7181 | } | |
7182 | } | |
7183 | else | |
7184 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
7185 | if (src_reg && GET_CODE (src_reg) == REG | |
7186 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) | |
7187 | { | |
7188 | int src_regno = REGNO (src_reg); | |
8ec450a4 | 7189 | int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); |
cb2afeb3 R |
7190 | /* The place where to find a death note varies with |
7191 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7192 | necessarily checked exactly in the code that moves | |
7193 | notes, so just check both locations. */ | |
7194 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
7195 | if (! note) | |
7196 | note = find_regno_note (store_insn, REG_DEAD, src_regno); | |
7197 | while (nr-- > 0) | |
7198 | { | |
7199 | spill_reg_store[src_regno + nr] = store_insn; | |
7200 | spill_reg_stored_to[src_regno + nr] = out; | |
7201 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7202 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7203 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 R |
7204 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
7205 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); | |
7206 | if (note) | |
7207 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7208 | else | |
7209 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7210 | } | |
7211 | reg_last_reload_reg[nregno] = src_reg; | |
7212 | } | |
7213 | } | |
c7093272 RK |
7214 | else |
7215 | { | |
1d7254c5 | 7216 | int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out)); |
36281332 | 7217 | |
c7093272 RK |
7218 | while (num_regs-- > 0) |
7219 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7220 | } | |
32131a9c RK |
7221 | } |
7222 | } | |
e6e52be0 | 7223 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7224 | } |
7225 | \f | |
5e03c156 RK |
7226 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7227 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7228 | OPNUM with reload type TYPE. |
546b63fb | 7229 | |
3c3eeea6 | 7230 | Returns first insn emitted. */ |
32131a9c RK |
7231 | |
7232 | rtx | |
5e03c156 RK |
7233 | gen_reload (out, in, opnum, type) |
7234 | rtx out; | |
32131a9c | 7235 | rtx in; |
546b63fb RK |
7236 | int opnum; |
7237 | enum reload_type type; | |
32131a9c | 7238 | { |
546b63fb | 7239 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7240 | rtx tem; |
7241 | ||
7242 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7243 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7244 | if (GET_CODE (in) == SUBREG | |
7245 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7246 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7247 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7248 | in = SUBREG_REG (in), out = tem; | |
7249 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7250 | && (GET_MODE_SIZE (GET_MODE (out)) |
7251 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7252 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7253 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7254 | |
a8fdc208 | 7255 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7256 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7257 | register that didn't get a hard register. In that case we can just | |
7258 | call emit_move_insn. | |
7259 | ||
a7fd196c JW |
7260 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7261 | another register, constant or MEM. This can occur during frame pointer | |
7262 | elimination and while reloading addresses. This case is handled by | |
7263 | trying to emit a single insn to perform the add. If it is not valid, | |
7264 | we use a two insn sequence. | |
32131a9c RK |
7265 | |
7266 | Finally, we could be called to handle an 'o' constraint by putting | |
7267 | an address into a register. In that case, we first try to do this | |
7268 | with a named pattern of "reload_load_address". If no such pattern | |
7269 | exists, we just emit a SET insn and hope for the best (it will normally | |
7270 | be valid on machines that use 'o'). | |
7271 | ||
7272 | This entire process is made complex because reload will never | |
7273 | process the insns we generate here and so we must ensure that | |
7274 | they will fit their constraints and also by the fact that parts of | |
7275 | IN might be being reloaded separately and replaced with spill registers. | |
7276 | Because of this, we are, in some sense, just guessing the right approach | |
7277 | here. The one listed above seems to work. | |
7278 | ||
7279 | ??? At some point, this whole thing needs to be rethought. */ | |
7280 | ||
7281 | if (GET_CODE (in) == PLUS | |
a7fd196c | 7282 | && (GET_CODE (XEXP (in, 0)) == REG |
5c6b1bd2 | 7283 | || GET_CODE (XEXP (in, 0)) == SUBREG |
a7fd196c JW |
7284 | || GET_CODE (XEXP (in, 0)) == MEM) |
7285 | && (GET_CODE (XEXP (in, 1)) == REG | |
5c6b1bd2 | 7286 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c JW |
7287 | || CONSTANT_P (XEXP (in, 1)) |
7288 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
32131a9c | 7289 | { |
a7fd196c JW |
7290 | /* We need to compute the sum of a register or a MEM and another |
7291 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7292 | register. The best possible way of doing this is if the machine |
7293 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7294 | |
7295 | The simplest approach is to try to generate such an insn and see if it | |
7296 | is recognized and matches its constraints. If so, it can be used. | |
7297 | ||
7298 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7299 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7300 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7301 | not valid than to dummy things up. */ |
a8fdc208 | 7302 | |
af929c62 | 7303 | rtx op0, op1, tem, insn; |
32131a9c | 7304 | int code; |
a8fdc208 | 7305 | |
af929c62 RK |
7306 | op0 = find_replacement (&XEXP (in, 0)); |
7307 | op1 = find_replacement (&XEXP (in, 1)); | |
7308 | ||
32131a9c RK |
7309 | /* Since constraint checking is strict, commutativity won't be |
7310 | checked, so we need to do that here to avoid spurious failure | |
7311 | if the add instruction is two-address and the second operand | |
7312 | of the add is the same as the reload reg, which is frequently | |
7313 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7314 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7315 | |
32131a9c | 7316 | if (GET_CODE (XEXP (in, 1)) == REG |
5e03c156 | 7317 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7318 | tem = op0, op0 = op1, op1 = tem; |
7319 | ||
7320 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7321 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7322 | |
38a448ca | 7323 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7324 | code = recog_memoized (insn); |
7325 | ||
7326 | if (code >= 0) | |
7327 | { | |
0eadeb15 | 7328 | extract_insn (insn); |
32131a9c RK |
7329 | /* We want constrain operands to treat this insn strictly in |
7330 | its validity determination, i.e., the way it would after reload | |
7331 | has completed. */ | |
0eadeb15 | 7332 | if (constrain_operands (1)) |
32131a9c RK |
7333 | return insn; |
7334 | } | |
7335 | ||
546b63fb | 7336 | delete_insns_since (last); |
32131a9c RK |
7337 | |
7338 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7339 | |
7340 | Use a move to copy one operand into the reload register. Prefer | |
7341 | to reload a constant, MEM or pseudo since the move patterns can | |
7342 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7343 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7344 | reload OP1. | |
7345 | ||
7346 | After reloading one of the operands into the reload register, add | |
7347 | the reload register to the output register. | |
32131a9c RK |
7348 | |
7349 | If there is another way to do this for a specific machine, a | |
7350 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7351 | we emit below. */ | |
7352 | ||
09522f21 FS |
7353 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7354 | ||
5c6b1bd2 | 7355 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG |
af929c62 | 7356 | || (GET_CODE (op1) == REG |
09522f21 FS |
7357 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7358 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7359 | && ! ((*insn_data[code].operand[2].predicate) |
7360 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7361 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7362 | |
5c6b1bd2 | 7363 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7364 | |
5e03c156 | 7365 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7366 | This fixes a problem on the 32K where the stack pointer cannot |
7367 | be used as an operand of an add insn. */ | |
7368 | ||
7369 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7370 | op1 = out; |
39b56c2a | 7371 | |
5e03c156 | 7372 | insn = emit_insn (gen_add2_insn (out, op1)); |
c77c9766 RK |
7373 | |
7374 | /* If that failed, copy the address register to the reload register. | |
0f41302f | 7375 | Then add the constant to the reload register. */ |
c77c9766 RK |
7376 | |
7377 | code = recog_memoized (insn); | |
7378 | ||
7379 | if (code >= 0) | |
7380 | { | |
0eadeb15 | 7381 | extract_insn (insn); |
c77c9766 RK |
7382 | /* We want constrain operands to treat this insn strictly in |
7383 | its validity determination, i.e., the way it would after reload | |
7384 | has completed. */ | |
0eadeb15 | 7385 | if (constrain_operands (1)) |
4117a96b R |
7386 | { |
7387 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ | |
7388 | REG_NOTES (insn) | |
9e6a5703 | 7389 | = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
4117a96b R |
7390 | return insn; |
7391 | } | |
c77c9766 RK |
7392 | } |
7393 | ||
7394 | delete_insns_since (last); | |
7395 | ||
5c6b1bd2 | 7396 | gen_reload (out, op1, opnum, type); |
4117a96b | 7397 | insn = emit_insn (gen_add2_insn (out, op0)); |
9e6a5703 | 7398 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
32131a9c RK |
7399 | } |
7400 | ||
0dadecf6 RK |
7401 | #ifdef SECONDARY_MEMORY_NEEDED |
7402 | /* If we need a memory location to do the move, do it that way. */ | |
7403 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
5e03c156 | 7404 | && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER |
0dadecf6 | 7405 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), |
5e03c156 RK |
7406 | REGNO_REG_CLASS (REGNO (out)), |
7407 | GET_MODE (out))) | |
0dadecf6 RK |
7408 | { |
7409 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7410 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7411 | |
5e03c156 | 7412 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7413 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7414 | |
7415 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7416 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7417 | |
5c6b1bd2 RK |
7418 | gen_reload (loc, in, opnum, type); |
7419 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
7420 | } |
7421 | #endif | |
7422 | ||
32131a9c RK |
7423 | /* If IN is a simple operand, use gen_move_insn. */ |
7424 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
5e03c156 | 7425 | emit_insn (gen_move_insn (out, in)); |
32131a9c RK |
7426 | |
7427 | #ifdef HAVE_reload_load_address | |
7428 | else if (HAVE_reload_load_address) | |
5e03c156 | 7429 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
7430 | #endif |
7431 | ||
5e03c156 | 7432 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 7433 | else |
38a448ca | 7434 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7435 | |
7436 | /* Return the first insn emitted. | |
546b63fb | 7437 | We can not just return get_last_insn, because there may have |
32131a9c RK |
7438 | been multiple instructions emitted. Also note that gen_move_insn may |
7439 | emit more than one insn itself, so we can not assume that there is one | |
7440 | insn emitted per emit_insn_before call. */ | |
7441 | ||
546b63fb | 7442 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
7443 | } |
7444 | \f | |
7445 | /* Delete a previously made output-reload | |
7446 | whose result we now believe is not needed. | |
7447 | First we double-check. | |
7448 | ||
7449 | INSN is the insn now being processed. | |
cb2afeb3 R |
7450 | LAST_RELOAD_REG is the hard register number for which we want to delete |
7451 | the last output reload. | |
7452 | J is the reload-number that originally used REG. The caller has made | |
7453 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
7454 | |
7455 | static void | |
cb2afeb3 | 7456 | delete_output_reload (insn, j, last_reload_reg) |
32131a9c RK |
7457 | rtx insn; |
7458 | int j; | |
cb2afeb3 | 7459 | int last_reload_reg; |
32131a9c | 7460 | { |
cb2afeb3 R |
7461 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
7462 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
7463 | int k; | |
7464 | int n_occurrences; | |
7465 | int n_inherited = 0; | |
32131a9c | 7466 | register rtx i1; |
cb2afeb3 | 7467 | rtx substed; |
05d10675 | 7468 | |
32131a9c RK |
7469 | /* Get the raw pseudo-register referred to. */ |
7470 | ||
32131a9c RK |
7471 | while (GET_CODE (reg) == SUBREG) |
7472 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
7473 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
7474 | ||
7475 | /* This is unsafe if the operand occurs more often in the current | |
7476 | insn than it is inherited. */ | |
7477 | for (k = n_reloads - 1; k >= 0; k--) | |
7478 | { | |
eceef4c9 | 7479 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
7480 | if (! reg2) |
7481 | continue; | |
7482 | if (GET_CODE (reg2) == MEM || reload_override_in[k]) | |
eceef4c9 | 7483 | reg2 = rld[k].in_reg; |
cb2afeb3 | 7484 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
7485 | if (rld[k].out && ! rld[k].out_reg) |
7486 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
7487 | #endif |
7488 | while (GET_CODE (reg2) == SUBREG) | |
7489 | reg2 = SUBREG_REG (reg2); | |
7490 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
7491 | { |
7492 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
7493 | { | |
cb2afeb3 | 7494 | n_inherited++; |
eceef4c9 | 7495 | reg2 = rld[k].out_reg; |
2eb6dac7 AS |
7496 | if (! reg2) |
7497 | continue; | |
7498 | while (GET_CODE (reg2) == SUBREG) | |
7499 | reg2 = XEXP (reg2, 0); | |
7500 | if (rtx_equal_p (reg2, reg)) | |
7501 | n_inherited++; | |
7502 | } | |
7503 | else | |
7504 | return; | |
7505 | } | |
cb2afeb3 | 7506 | } |
4b983fdc | 7507 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
cb2afeb3 | 7508 | if (substed) |
4b983fdc | 7509 | n_occurrences += count_occurrences (PATTERN (insn), substed, 0); |
cb2afeb3 R |
7510 | if (n_occurrences > n_inherited) |
7511 | return; | |
32131a9c RK |
7512 | |
7513 | /* If the pseudo-reg we are reloading is no longer referenced | |
7514 | anywhere between the store into it and here, | |
7515 | and no jumps or labels intervene, then the value can get | |
7516 | here through the reload reg alone. | |
7517 | Otherwise, give up--return. */ | |
7518 | for (i1 = NEXT_INSN (output_reload_insn); | |
7519 | i1 != insn; i1 = NEXT_INSN (i1)) | |
7520 | { | |
7521 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
7522 | return; | |
7523 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
7524 | && reg_mentioned_p (reg, PATTERN (i1))) | |
aa6498c2 | 7525 | { |
cb2afeb3 R |
7526 | /* If this is USE in front of INSN, we only have to check that |
7527 | there are no more references than accounted for by inheritance. */ | |
7528 | while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) | |
aa6498c2 | 7529 | { |
cb2afeb3 | 7530 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
7531 | i1 = NEXT_INSN (i1); |
7532 | } | |
cb2afeb3 | 7533 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
7534 | break; |
7535 | return; | |
7536 | } | |
32131a9c RK |
7537 | } |
7538 | ||
aa6498c2 R |
7539 | /* The caller has already checked that REG dies or is set in INSN. |
7540 | It has also checked that we are optimizing, and thus some inaccurancies | |
7541 | in the debugging information are acceptable. | |
7542 | So we could just delete output_reload_insn. | |
7543 | But in some cases we can improve the debugging information without | |
7544 | sacrificing optimization - maybe even improving the code: | |
7545 | See if the pseudo reg has been completely replaced | |
32131a9c RK |
7546 | with reload regs. If so, delete the store insn |
7547 | and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 7548 | if (rld[j].out != rld[j].in |
aa6498c2 | 7549 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 7550 | && REG_N_SETS (REGNO (reg)) == 1 |
aa6498c2 R |
7551 | && REG_BASIC_BLOCK (REGNO (reg)) >= 0 |
7552 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
32131a9c RK |
7553 | { |
7554 | rtx i2; | |
7555 | ||
7556 | /* We know that it was used only between here | |
7557 | and the beginning of the current basic block. | |
7558 | (We also know that the last use before INSN was | |
7559 | the output reload we are thinking of deleting, but never mind that.) | |
7560 | Search that range; see if any ref remains. */ | |
7561 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7562 | { | |
d445b551 RK |
7563 | rtx set = single_set (i2); |
7564 | ||
32131a9c RK |
7565 | /* Uses which just store in the pseudo don't count, |
7566 | since if they are the only uses, they are dead. */ | |
d445b551 | 7567 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
7568 | continue; |
7569 | if (GET_CODE (i2) == CODE_LABEL | |
7570 | || GET_CODE (i2) == JUMP_INSN) | |
7571 | break; | |
7572 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
7573 | && reg_mentioned_p (reg, PATTERN (i2))) | |
aa6498c2 R |
7574 | { |
7575 | /* Some other ref remains; just delete the output reload we | |
7576 | know to be dead. */ | |
cb2afeb3 R |
7577 | delete_address_reloads (output_reload_insn, insn); |
7578 | PUT_CODE (output_reload_insn, NOTE); | |
7579 | NOTE_SOURCE_FILE (output_reload_insn) = 0; | |
7580 | NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; | |
aa6498c2 R |
7581 | return; |
7582 | } | |
32131a9c RK |
7583 | } |
7584 | ||
7585 | /* Delete the now-dead stores into this pseudo. */ | |
7586 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7587 | { | |
d445b551 RK |
7588 | rtx set = single_set (i2); |
7589 | ||
7590 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 7591 | { |
cb2afeb3 | 7592 | delete_address_reloads (i2, insn); |
5507b94b RK |
7593 | /* This might be a basic block head, |
7594 | thus don't use delete_insn. */ | |
7595 | PUT_CODE (i2, NOTE); | |
7596 | NOTE_SOURCE_FILE (i2) = 0; | |
7597 | NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; | |
7598 | } | |
32131a9c RK |
7599 | if (GET_CODE (i2) == CODE_LABEL |
7600 | || GET_CODE (i2) == JUMP_INSN) | |
7601 | break; | |
7602 | } | |
7603 | ||
7604 | /* For the debugging info, | |
7605 | say the pseudo lives in this reload reg. */ | |
eceef4c9 | 7606 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
7607 | alter_reg (REGNO (reg), -1); |
7608 | } | |
cb2afeb3 R |
7609 | delete_address_reloads (output_reload_insn, insn); |
7610 | PUT_CODE (output_reload_insn, NOTE); | |
7611 | NOTE_SOURCE_FILE (output_reload_insn) = 0; | |
7612 | NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; | |
7613 | ||
7614 | } | |
7615 | ||
7616 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
7617 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
7618 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
7619 | static void | |
7620 | delete_address_reloads (dead_insn, current_insn) | |
7621 | rtx dead_insn, current_insn; | |
7622 | { | |
7623 | rtx set = single_set (dead_insn); | |
7624 | rtx set2, dst, prev, next; | |
7625 | if (set) | |
7626 | { | |
7627 | rtx dst = SET_DEST (set); | |
7628 | if (GET_CODE (dst) == MEM) | |
7629 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); | |
7630 | } | |
7631 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
7632 | we can delete the matching adds. */ | |
7633 | prev = PREV_INSN (dead_insn); | |
7634 | next = NEXT_INSN (dead_insn); | |
7635 | if (! prev || ! next) | |
7636 | return; | |
7637 | set = single_set (next); | |
7638 | set2 = single_set (prev); | |
7639 | if (! set || ! set2 | |
7640 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
7641 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
7642 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
7643 | return; | |
7644 | dst = SET_DEST (set); | |
7645 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
7646 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
7647 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
7648 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 7649 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 R |
7650 | return; |
7651 | delete_insn (prev); | |
7652 | delete_insn (next); | |
7653 | } | |
7654 | ||
7655 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
7656 | static void | |
7657 | delete_address_reloads_1 (dead_insn, x, current_insn) | |
7658 | rtx dead_insn, x, current_insn; | |
7659 | { | |
7660 | rtx prev, set, dst, i2; | |
7661 | int i, j; | |
7662 | enum rtx_code code = GET_CODE (x); | |
7663 | ||
7664 | if (code != REG) | |
7665 | { | |
1d7254c5 | 7666 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
7667 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7668 | { | |
7669 | if (fmt[i] == 'e') | |
7670 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
7671 | else if (fmt[i] == 'E') | |
7672 | { | |
1d7254c5 | 7673 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
7674 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
7675 | current_insn); | |
7676 | } | |
7677 | } | |
7678 | return; | |
7679 | } | |
7680 | ||
7681 | if (spill_reg_order[REGNO (x)] < 0) | |
7682 | return; | |
aa6498c2 | 7683 | |
cb2afeb3 R |
7684 | /* Scan backwards for the insn that sets x. This might be a way back due |
7685 | to inheritance. */ | |
7686 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
7687 | { | |
7688 | code = GET_CODE (prev); | |
7689 | if (code == CODE_LABEL || code == JUMP_INSN) | |
7690 | return; | |
7691 | if (GET_RTX_CLASS (code) != 'i') | |
7692 | continue; | |
7693 | if (reg_set_p (x, PATTERN (prev))) | |
7694 | break; | |
7695 | if (reg_referenced_p (x, PATTERN (prev))) | |
7696 | return; | |
7697 | } | |
7698 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
7699 | return; | |
7700 | /* Check that PREV only sets the reload register. */ | |
7701 | set = single_set (prev); | |
7702 | if (! set) | |
7703 | return; | |
7704 | dst = SET_DEST (set); | |
7705 | if (GET_CODE (dst) != REG | |
7706 | || ! rtx_equal_p (dst, x)) | |
7707 | return; | |
7708 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
7709 | { | |
7710 | /* Check if DST was used in a later insn - | |
7711 | it might have been inherited. */ | |
7712 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
7713 | { | |
7714 | if (GET_CODE (i2) == CODE_LABEL) | |
7715 | break; | |
2c3c49de | 7716 | if (! INSN_P (i2)) |
cb2afeb3 R |
7717 | continue; |
7718 | if (reg_referenced_p (dst, PATTERN (i2))) | |
7719 | { | |
7720 | /* If there is a reference to the register in the current insn, | |
7721 | it might be loaded in a non-inherited reload. If no other | |
7722 | reload uses it, that means the register is set before | |
7723 | referenced. */ | |
7724 | if (i2 == current_insn) | |
7725 | { | |
7726 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7727 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7728 | || reload_override_in[j] == dst) |
7729 | return; | |
7730 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7731 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
7732 | break; |
7733 | if (j >= 0) | |
7734 | break; | |
7735 | } | |
7736 | return; | |
7737 | } | |
7738 | if (GET_CODE (i2) == JUMP_INSN) | |
7739 | break; | |
cb2afeb3 | 7740 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
7741 | any reload. Note that even if CURRENT_INSN sets DST, we still |
7742 | have to check the reloads. */ | |
cb2afeb3 R |
7743 | if (i2 == current_insn) |
7744 | { | |
7745 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7746 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7747 | || reload_override_in[j] == dst) |
7748 | return; | |
7749 | /* ??? We can't finish the loop here, because dst might be | |
7750 | allocated to a pseudo in this block if no reload in this | |
7751 | block needs any of the clsses containing DST - see | |
7752 | spill_hard_reg. There is no easy way to tell this, so we | |
7753 | have to scan till the end of the basic block. */ | |
7754 | } | |
3900dc09 R |
7755 | if (reg_set_p (dst, PATTERN (i2))) |
7756 | break; | |
cb2afeb3 R |
7757 | } |
7758 | } | |
7759 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
7760 | reg_reloaded_contents[REGNO (dst)] = -1; | |
7761 | /* Can't use delete_insn here because PREV might be a basic block head. */ | |
7762 | PUT_CODE (prev, NOTE); | |
7763 | NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED; | |
7764 | NOTE_SOURCE_FILE (prev) = 0; | |
32131a9c | 7765 | } |
32131a9c | 7766 | \f |
a8fdc208 | 7767 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 7768 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
7769 | is a register or memory location; |
7770 | so reloading involves incrementing that location. | |
cb2afeb3 | 7771 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
7772 | |
7773 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 7774 | This cannot be deduced from VALUE. |
32131a9c | 7775 | |
cb2afeb3 R |
7776 | Return the instruction that stores into RELOADREG. */ |
7777 | ||
7778 | static rtx | |
7779 | inc_for_reload (reloadreg, in, value, inc_amount) | |
32131a9c | 7780 | rtx reloadreg; |
cb2afeb3 | 7781 | rtx in, value; |
32131a9c | 7782 | int inc_amount; |
32131a9c RK |
7783 | { |
7784 | /* REG or MEM to be copied and incremented. */ | |
7785 | rtx incloc = XEXP (value, 0); | |
7786 | /* Nonzero if increment after copying. */ | |
7787 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 7788 | rtx last; |
0009eff2 RK |
7789 | rtx inc; |
7790 | rtx add_insn; | |
7791 | int code; | |
cb2afeb3 R |
7792 | rtx store; |
7793 | rtx real_in = in == value ? XEXP (in, 0) : in; | |
32131a9c RK |
7794 | |
7795 | /* No hard register is equivalent to this register after | |
7796 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
7797 | we could inc/dec that register as well (maybe even using it for | |
7798 | the source), but I'm not sure it's worth worrying about. */ | |
7799 | if (GET_CODE (incloc) == REG) | |
7800 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
7801 | ||
7802 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
1d7254c5 | 7803 | inc_amount = -inc_amount; |
32131a9c | 7804 | |
fb3821f7 | 7805 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
7806 | |
7807 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
7808 | if (post && real_in != reloadreg) |
7809 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 7810 | |
cb2afeb3 R |
7811 | if (in == value) |
7812 | { | |
7813 | /* See if we can directly increment INCLOC. Use a method similar to | |
7814 | that in gen_reload. */ | |
0009eff2 | 7815 | |
cb2afeb3 R |
7816 | last = get_last_insn (); |
7817 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
7818 | gen_rtx_PLUS (GET_MODE (incloc), | |
7819 | incloc, inc))); | |
05d10675 | 7820 | |
cb2afeb3 R |
7821 | code = recog_memoized (add_insn); |
7822 | if (code >= 0) | |
32131a9c | 7823 | { |
0eadeb15 BS |
7824 | extract_insn (add_insn); |
7825 | if (constrain_operands (1)) | |
cb2afeb3 R |
7826 | { |
7827 | /* If this is a pre-increment and we have incremented the value | |
7828 | where it lives, copy the incremented value to RELOADREG to | |
7829 | be used as an address. */ | |
0009eff2 | 7830 | |
cb2afeb3 R |
7831 | if (! post) |
7832 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 7833 | |
cb2afeb3 R |
7834 | return add_insn; |
7835 | } | |
32131a9c | 7836 | } |
cb2afeb3 | 7837 | delete_insns_since (last); |
32131a9c | 7838 | } |
0009eff2 | 7839 | |
0009eff2 RK |
7840 | /* If couldn't do the increment directly, must increment in RELOADREG. |
7841 | The way we do this depends on whether this is pre- or post-increment. | |
7842 | For pre-increment, copy INCLOC to the reload register, increment it | |
7843 | there, then save back. */ | |
7844 | ||
7845 | if (! post) | |
7846 | { | |
cb2afeb3 R |
7847 | if (in != reloadreg) |
7848 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 7849 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7850 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 7851 | } |
32131a9c RK |
7852 | else |
7853 | { | |
0009eff2 RK |
7854 | /* Postincrement. |
7855 | Because this might be a jump insn or a compare, and because RELOADREG | |
7856 | may not be available after the insn in an input reload, we must do | |
7857 | the incrementation before the insn being reloaded for. | |
7858 | ||
cb2afeb3 | 7859 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
7860 | RELOADREG, save that back, then decrement RELOADREG so it has |
7861 | the original value. */ | |
7862 | ||
546b63fb | 7863 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7864 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
546b63fb | 7865 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); |
32131a9c | 7866 | } |
0009eff2 | 7867 | |
cb2afeb3 | 7868 | return store; |
32131a9c RK |
7869 | } |
7870 | \f | |
7871 | /* Return 1 if we are certain that the constraint-string STRING allows | |
7872 | the hard register REG. Return 0 if we can't be sure of this. */ | |
7873 | ||
7874 | static int | |
7875 | constraint_accepts_reg_p (string, reg) | |
9b3142b3 | 7876 | const char *string; |
32131a9c RK |
7877 | rtx reg; |
7878 | { | |
7879 | int value = 0; | |
7880 | int regno = true_regnum (reg); | |
7881 | int c; | |
7882 | ||
7883 | /* Initialize for first alternative. */ | |
7884 | value = 0; | |
7885 | /* Check that each alternative contains `g' or `r'. */ | |
7886 | while (1) | |
7887 | switch (c = *string++) | |
7888 | { | |
7889 | case 0: | |
7890 | /* If an alternative lacks `g' or `r', we lose. */ | |
7891 | return value; | |
7892 | case ',': | |
7893 | /* If an alternative lacks `g' or `r', we lose. */ | |
7894 | if (value == 0) | |
7895 | return 0; | |
7896 | /* Initialize for next alternative. */ | |
7897 | value = 0; | |
7898 | break; | |
7899 | case 'g': | |
7900 | case 'r': | |
7901 | /* Any general reg wins for this alternative. */ | |
7902 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
7903 | value = 1; | |
7904 | break; | |
7905 | default: | |
7906 | /* Any reg in specified class wins for this alternative. */ | |
7907 | { | |
0009eff2 | 7908 | enum reg_class class = REG_CLASS_FROM_LETTER (c); |
32131a9c | 7909 | |
0009eff2 | 7910 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) |
32131a9c RK |
7911 | value = 1; |
7912 | } | |
7913 | } | |
7914 | } | |
7915 | \f | |
eab5c70a BS |
7916 | /* INSN is a no-op; delete it. |
7917 | If this sets the return value of the function, we must keep a USE around, | |
7918 | in case this is in a different basic block than the final USE. Otherwise, | |
7919 | we could loose important register lifeness information on | |
7920 | SMALL_REGISTER_CLASSES machines, where return registers might be used as | |
7921 | spills: subsequent passes assume that spill registers are dead at the end | |
7922 | of a basic block. | |
7923 | VALUE must be the return value in such a case, NULL otherwise. */ | |
2a9fb548 | 7924 | static void |
eab5c70a BS |
7925 | reload_cse_delete_noop_set (insn, value) |
7926 | rtx insn, value; | |
2a9fb548 | 7927 | { |
eab5c70a | 7928 | if (value) |
2a9fb548 | 7929 | { |
eab5c70a BS |
7930 | PATTERN (insn) = gen_rtx_USE (VOIDmode, value); |
7931 | INSN_CODE (insn) = -1; | |
7932 | REG_NOTES (insn) = NULL_RTX; | |
2a9fb548 | 7933 | } |
eab5c70a | 7934 | else |
ba325eba | 7935 | { |
eab5c70a BS |
7936 | PUT_CODE (insn, NOTE); |
7937 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
7938 | NOTE_SOURCE_FILE (insn) = 0; | |
ba325eba | 7939 | } |
2a9fb548 ILT |
7940 | } |
7941 | ||
eab5c70a | 7942 | /* See whether a single set SET is a noop. */ |
2a9fb548 | 7943 | static int |
eab5c70a BS |
7944 | reload_cse_noop_set_p (set) |
7945 | rtx set; | |
2a9fb548 | 7946 | { |
eab5c70a BS |
7947 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); |
7948 | } | |
2a9fb548 | 7949 | |
eab5c70a BS |
7950 | /* Try to simplify INSN. */ |
7951 | static void | |
7952 | reload_cse_simplify (insn) | |
7953 | rtx insn; | |
7954 | { | |
7955 | rtx body = PATTERN (insn); | |
2a9fb548 | 7956 | |
eab5c70a | 7957 | if (GET_CODE (body) == SET) |
2a9fb548 | 7958 | { |
eab5c70a BS |
7959 | int count = 0; |
7960 | if (reload_cse_noop_set_p (body)) | |
2a9fb548 | 7961 | { |
eab5c70a BS |
7962 | rtx value = SET_DEST (body); |
7963 | if (! REG_FUNCTION_VALUE_P (SET_DEST (body))) | |
7964 | value = 0; | |
7965 | reload_cse_delete_noop_set (insn, value); | |
7966 | return; | |
2a9fb548 | 7967 | } |
2a9fb548 | 7968 | |
eab5c70a BS |
7969 | /* It's not a no-op, but we can try to simplify it. */ |
7970 | count += reload_cse_simplify_set (body, insn); | |
2a9fb548 | 7971 | |
eab5c70a BS |
7972 | if (count > 0) |
7973 | apply_change_group (); | |
7974 | else | |
7975 | reload_cse_simplify_operands (insn); | |
7976 | } | |
7977 | else if (GET_CODE (body) == PARALLEL) | |
2a9fb548 | 7978 | { |
eab5c70a BS |
7979 | int i; |
7980 | int count = 0; | |
7981 | rtx value = NULL_RTX; | |
2a9fb548 | 7982 | |
eab5c70a BS |
7983 | /* If every action in a PARALLEL is a noop, we can delete |
7984 | the entire PARALLEL. */ | |
7985 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
2a9fb548 | 7986 | { |
eab5c70a BS |
7987 | rtx part = XVECEXP (body, 0, i); |
7988 | if (GET_CODE (part) == SET) | |
2a9fb548 | 7989 | { |
eab5c70a BS |
7990 | if (! reload_cse_noop_set_p (part)) |
7991 | break; | |
7992 | if (REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
2a9fb548 | 7993 | { |
eab5c70a BS |
7994 | if (value) |
7995 | break; | |
7996 | value = SET_DEST (part); | |
2a9fb548 | 7997 | } |
2a9fb548 | 7998 | } |
eab5c70a BS |
7999 | else if (GET_CODE (part) != CLOBBER) |
8000 | break; | |
2a9fb548 | 8001 | } |
2a9fb548 | 8002 | |
eab5c70a BS |
8003 | if (i < 0) |
8004 | { | |
8005 | reload_cse_delete_noop_set (insn, value); | |
8006 | /* We're done with this insn. */ | |
8007 | return; | |
8008 | } | |
2a9fb548 | 8009 | |
eab5c70a BS |
8010 | /* It's not a no-op, but we can try to simplify it. */ |
8011 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
8012 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
8013 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
8014 | ||
8015 | if (count > 0) | |
8016 | apply_change_group (); | |
8017 | else | |
8018 | reload_cse_simplify_operands (insn); | |
8019 | } | |
2a9fb548 ILT |
8020 | } |
8021 | ||
8022 | /* Do a very simple CSE pass over the hard registers. | |
8023 | ||
8024 | This function detects no-op moves where we happened to assign two | |
8025 | different pseudo-registers to the same hard register, and then | |
8026 | copied one to the other. Reload will generate a useless | |
8027 | instruction copying a register to itself. | |
8028 | ||
8029 | This function also detects cases where we load a value from memory | |
8030 | into two different registers, and (if memory is more expensive than | |
8031 | registers) changes it to simply copy the first register into the | |
05d10675 | 8032 | second register. |
e9a25f70 JL |
8033 | |
8034 | Another optimization is performed that scans the operands of each | |
8035 | instruction to see whether the value is already available in a | |
8036 | hard register. It then replaces the operand with the hard register | |
8037 | if possible, much like an optional reload would. */ | |
2a9fb548 | 8038 | |
5adf6da0 R |
8039 | static void |
8040 | reload_cse_regs_1 (first) | |
2a9fb548 ILT |
8041 | rtx first; |
8042 | { | |
2a9fb548 ILT |
8043 | rtx insn; |
8044 | ||
1d7254c5 | 8045 | cselib_init (); |
cbfc3ad3 RK |
8046 | init_alias_analysis (); |
8047 | ||
2a9fb548 ILT |
8048 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
8049 | { | |
2c3c49de | 8050 | if (INSN_P (insn)) |
eab5c70a | 8051 | reload_cse_simplify (insn); |
2a9fb548 | 8052 | |
eab5c70a | 8053 | cselib_process_insn (insn); |
2a9fb548 ILT |
8054 | } |
8055 | ||
e05e2395 MM |
8056 | /* Clean up. */ |
8057 | end_alias_analysis (); | |
eab5c70a | 8058 | cselib_finish (); |
2a9fb548 ILT |
8059 | } |
8060 | ||
5adf6da0 R |
8061 | /* Call cse / combine like post-reload optimization phases. |
8062 | FIRST is the first instruction. */ | |
8063 | void | |
8064 | reload_cse_regs (first) | |
8065 | rtx first; | |
8066 | { | |
8067 | reload_cse_regs_1 (first); | |
8068 | reload_combine (); | |
8069 | reload_cse_move2add (first); | |
8070 | if (flag_expensive_optimizations) | |
8071 | reload_cse_regs_1 (first); | |
8072 | } | |
8073 | ||
2a9fb548 | 8074 | /* Try to simplify a single SET instruction. SET is the set pattern. |
e9a25f70 JL |
8075 | INSN is the instruction it came from. |
8076 | This function only handles one case: if we set a register to a value | |
8077 | which is not a register, we try to find that value in some other register | |
8078 | and change the set into a register copy. */ | |
2a9fb548 | 8079 | |
e9a25f70 | 8080 | static int |
2a9fb548 ILT |
8081 | reload_cse_simplify_set (set, insn) |
8082 | rtx set; | |
8083 | rtx insn; | |
8084 | { | |
eab5c70a | 8085 | int did_change = 0; |
2a9fb548 ILT |
8086 | int dreg; |
8087 | rtx src; | |
2a9fb548 | 8088 | enum reg_class dclass; |
eab5c70a BS |
8089 | int old_cost; |
8090 | cselib_val *val; | |
8091 | struct elt_loc_list *l; | |
2a9fb548 | 8092 | |
2a9fb548 ILT |
8093 | dreg = true_regnum (SET_DEST (set)); |
8094 | if (dreg < 0) | |
e9a25f70 | 8095 | return 0; |
2a9fb548 ILT |
8096 | |
8097 | src = SET_SRC (set); | |
8098 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
e9a25f70 | 8099 | return 0; |
2a9fb548 | 8100 | |
cbd5b9a2 KR |
8101 | dclass = REGNO_REG_CLASS (dreg); |
8102 | ||
33ab8de0 | 8103 | /* If memory loads are cheaper than register copies, don't change them. */ |
eab5c70a BS |
8104 | if (GET_CODE (src) == MEM) |
8105 | old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1); | |
8106 | else if (CONSTANT_P (src)) | |
8107 | old_cost = rtx_cost (src, SET); | |
8108 | else if (GET_CODE (src) == REG) | |
8109 | old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass); | |
8110 | else | |
8111 | /* ??? */ | |
8112 | old_cost = rtx_cost (src, SET); | |
2a9fb548 | 8113 | |
70bbeb8b | 8114 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0); |
eab5c70a | 8115 | if (! val) |
0254c561 | 8116 | return 0; |
eab5c70a | 8117 | for (l = val->locs; l; l = l->next) |
2a9fb548 | 8118 | { |
eab5c70a BS |
8119 | int this_cost; |
8120 | if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0)) | |
8121 | this_cost = rtx_cost (l->loc, SET); | |
8122 | else if (GET_CODE (l->loc) == REG) | |
8123 | this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)), | |
8124 | dclass); | |
8125 | else | |
8126 | continue; | |
8127 | /* If equal costs, prefer registers over anything else. That tends to | |
8128 | lead to smaller instructions on some machines. */ | |
8129 | if ((this_cost < old_cost | |
8130 | || (this_cost == old_cost | |
8131 | && GET_CODE (l->loc) == REG | |
8132 | && GET_CODE (SET_SRC (set)) != REG)) | |
1d7254c5 | 8133 | && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1)) |
eab5c70a | 8134 | old_cost = this_cost, did_change = 1; |
e9a25f70 | 8135 | } |
eab5c70a BS |
8136 | |
8137 | return did_change; | |
e9a25f70 JL |
8138 | } |
8139 | ||
8140 | /* Try to replace operands in INSN with equivalent values that are already | |
05d10675 BS |
8141 | in registers. This can be viewed as optional reloading. |
8142 | ||
e9a25f70 JL |
8143 | For each non-register operand in the insn, see if any hard regs are |
8144 | known to be equivalent to that operand. Record the alternatives which | |
8145 | can accept these hard registers. Among all alternatives, select the | |
8146 | ones which are better or equal to the one currently matching, where | |
8147 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
8148 | alternatives, select the one which replaces most operands with | |
8149 | hard registers. */ | |
8150 | ||
8151 | static int | |
8152 | reload_cse_simplify_operands (insn) | |
8153 | rtx insn; | |
8154 | { | |
1d7254c5 | 8155 | int i, j; |
e9a25f70 | 8156 | |
eab5c70a BS |
8157 | /* For each operand, all registers that are equivalent to it. */ |
8158 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
8159 | ||
9b3142b3 | 8160 | const char *constraints[MAX_RECOG_OPERANDS]; |
05d10675 | 8161 | |
e9a25f70 JL |
8162 | /* Vector recording how bad an alternative is. */ |
8163 | int *alternative_reject; | |
8164 | /* Vector recording how many registers can be introduced by choosing | |
8165 | this alternative. */ | |
8166 | int *alternative_nregs; | |
8167 | /* Array of vectors recording, for each operand and each alternative, | |
8168 | which hard register to substitute, or -1 if the operand should be | |
8169 | left as it is. */ | |
8170 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
8171 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
8172 | int *alternative_order; | |
0254c561 | 8173 | rtx reg = gen_rtx_REG (VOIDmode, -1); |
05d10675 | 8174 | |
0eadeb15 | 8175 | extract_insn (insn); |
e9a25f70 | 8176 | |
1ccbefce | 8177 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) |
1d300e19 | 8178 | return 0; |
e9a25f70 JL |
8179 | |
8180 | /* Figure out which alternative currently matches. */ | |
0eadeb15 | 8181 | if (! constrain_operands (1)) |
b8705408 | 8182 | fatal_insn_not_found (insn); |
1d7254c5 | 8183 | |
1ccbefce RH |
8184 | alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8185 | alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8186 | alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
961192e1 JM |
8187 | memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
8188 | memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
e9a25f70 | 8189 | |
eab5c70a BS |
8190 | /* For each operand, find out which regs are equivalent. */ |
8191 | for (i = 0; i < recog_data.n_operands; i++) | |
8192 | { | |
8193 | cselib_val *v; | |
8194 | struct elt_loc_list *l; | |
8195 | ||
8196 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
8197 | ||
8198 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
70bbeb8b BS |
8199 | right, so avoid the problem here. Likewise if we have a constant |
8200 | and the insn pattern doesn't tell us the mode we need. */ | |
8201 | if (GET_CODE (recog_data.operand[i]) == CODE_LABEL | |
8202 | || (CONSTANT_P (recog_data.operand[i]) | |
8203 | && recog_data.operand_mode[i] == VOIDmode)) | |
eab5c70a BS |
8204 | continue; |
8205 | ||
8206 | v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0); | |
8207 | if (! v) | |
8208 | continue; | |
8209 | ||
8210 | for (l = v->locs; l; l = l->next) | |
8211 | if (GET_CODE (l->loc) == REG) | |
8212 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); | |
8213 | } | |
8214 | ||
1ccbefce | 8215 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 JL |
8216 | { |
8217 | enum machine_mode mode; | |
8218 | int regno; | |
9b3142b3 | 8219 | const char *p; |
e9a25f70 | 8220 | |
1ccbefce RH |
8221 | op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8222 | for (j = 0; j < recog_data.n_alternatives; j++) | |
e9a25f70 JL |
8223 | op_alt_regno[i][j] = -1; |
8224 | ||
1ccbefce RH |
8225 | p = constraints[i] = recog_data.constraints[i]; |
8226 | mode = recog_data.operand_mode[i]; | |
e9a25f70 JL |
8227 | |
8228 | /* Add the reject values for each alternative given by the constraints | |
8229 | for this operand. */ | |
8230 | j = 0; | |
8231 | while (*p != '\0') | |
8232 | { | |
8233 | char c = *p++; | |
8234 | if (c == ',') | |
8235 | j++; | |
8236 | else if (c == '?') | |
8237 | alternative_reject[j] += 3; | |
8238 | else if (c == '!') | |
8239 | alternative_reject[j] += 300; | |
8240 | } | |
8241 | ||
8242 | /* We won't change operands which are already registers. We | |
8243 | also don't want to modify output operands. */ | |
1ccbefce | 8244 | regno = true_regnum (recog_data.operand[i]); |
e9a25f70 JL |
8245 | if (regno >= 0 |
8246 | || constraints[i][0] == '=' | |
8247 | || constraints[i][0] == '+') | |
8248 | continue; | |
8249 | ||
8250 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
8251 | { | |
8252 | int class = (int) NO_REGS; | |
8253 | ||
eab5c70a | 8254 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) |
e9a25f70 JL |
8255 | continue; |
8256 | ||
0254c561 JC |
8257 | REGNO (reg) = regno; |
8258 | PUT_MODE (reg, mode); | |
8259 | ||
e9a25f70 JL |
8260 | /* We found a register equal to this operand. Now look for all |
8261 | alternatives that can accept this register and have not been | |
8262 | assigned a register they can use yet. */ | |
8263 | j = 0; | |
8264 | p = constraints[i]; | |
8265 | for (;;) | |
31418d35 | 8266 | { |
e9a25f70 | 8267 | char c = *p++; |
05d10675 | 8268 | |
e9a25f70 | 8269 | switch (c) |
31418d35 | 8270 | { |
e9a25f70 JL |
8271 | case '=': case '+': case '?': |
8272 | case '#': case '&': case '!': | |
05d10675 | 8273 | case '*': case '%': |
e9a25f70 | 8274 | case '0': case '1': case '2': case '3': case '4': |
c5c76735 | 8275 | case '5': case '6': case '7': case '8': case '9': |
e9a25f70 JL |
8276 | case 'm': case '<': case '>': case 'V': case 'o': |
8277 | case 'E': case 'F': case 'G': case 'H': | |
8278 | case 's': case 'i': case 'n': | |
8279 | case 'I': case 'J': case 'K': case 'L': | |
8280 | case 'M': case 'N': case 'O': case 'P': | |
e9a25f70 JL |
8281 | case 'p': case 'X': |
8282 | /* These don't say anything we care about. */ | |
8283 | break; | |
8284 | ||
8285 | case 'g': case 'r': | |
8286 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
8287 | break; | |
8288 | ||
8289 | default: | |
8290 | class | |
e51712db | 8291 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
e9a25f70 | 8292 | break; |
31418d35 | 8293 | |
e9a25f70 JL |
8294 | case ',': case '\0': |
8295 | /* See if REGNO fits this alternative, and set it up as the | |
8296 | replacement register if we don't have one for this | |
0254c561 | 8297 | alternative yet and the operand being replaced is not |
1d7254c5 | 8298 | a cheap CONST_INT. */ |
e9a25f70 | 8299 | if (op_alt_regno[i][j] == -1 |
0254c561 | 8300 | && reg_fits_class_p (reg, class, 0, mode) |
1ccbefce RH |
8301 | && (GET_CODE (recog_data.operand[i]) != CONST_INT |
8302 | || (rtx_cost (recog_data.operand[i], SET) | |
8303 | > rtx_cost (reg, SET)))) | |
31418d35 | 8304 | { |
e9a25f70 JL |
8305 | alternative_nregs[j]++; |
8306 | op_alt_regno[i][j] = regno; | |
31418d35 | 8307 | } |
e9a25f70 JL |
8308 | j++; |
8309 | break; | |
31418d35 ILT |
8310 | } |
8311 | ||
e9a25f70 JL |
8312 | if (c == '\0') |
8313 | break; | |
8314 | } | |
8315 | } | |
8316 | } | |
8317 | ||
8318 | /* Record all alternatives which are better or equal to the currently | |
8319 | matching one in the alternative_order array. */ | |
1ccbefce | 8320 | for (i = j = 0; i < recog_data.n_alternatives; i++) |
e9a25f70 JL |
8321 | if (alternative_reject[i] <= alternative_reject[which_alternative]) |
8322 | alternative_order[j++] = i; | |
1ccbefce | 8323 | recog_data.n_alternatives = j; |
e9a25f70 JL |
8324 | |
8325 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
8326 | won't hurt too much. */ | |
1ccbefce | 8327 | for (i = 0; i < recog_data.n_alternatives - 1; i++) |
e9a25f70 JL |
8328 | { |
8329 | int best = i; | |
8330 | int best_reject = alternative_reject[alternative_order[i]]; | |
8331 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
8332 | int tmp; | |
8333 | ||
1ccbefce | 8334 | for (j = i + 1; j < recog_data.n_alternatives; j++) |
e9a25f70 JL |
8335 | { |
8336 | int this_reject = alternative_reject[alternative_order[j]]; | |
8337 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
8338 | ||
8339 | if (this_reject < best_reject | |
8340 | || (this_reject == best_reject && this_nregs < best_nregs)) | |
8341 | { | |
8342 | best = j; | |
8343 | best_reject = this_reject; | |
8344 | best_nregs = this_nregs; | |
31418d35 | 8345 | } |
2a9fb548 | 8346 | } |
05d10675 | 8347 | |
e9a25f70 JL |
8348 | tmp = alternative_order[best]; |
8349 | alternative_order[best] = alternative_order[i]; | |
8350 | alternative_order[i] = tmp; | |
8351 | } | |
05d10675 | 8352 | |
e9a25f70 JL |
8353 | /* Substitute the operands as determined by op_alt_regno for the best |
8354 | alternative. */ | |
8355 | j = alternative_order[0]; | |
e9a25f70 | 8356 | |
1ccbefce | 8357 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 | 8358 | { |
1ccbefce | 8359 | enum machine_mode mode = recog_data.operand_mode[i]; |
e9a25f70 JL |
8360 | if (op_alt_regno[i][j] == -1) |
8361 | continue; | |
8362 | ||
1ccbefce | 8363 | validate_change (insn, recog_data.operand_loc[i], |
38a448ca | 8364 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); |
e9a25f70 JL |
8365 | } |
8366 | ||
1ccbefce | 8367 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
e9a25f70 | 8368 | { |
1ccbefce RH |
8369 | int op = recog_data.dup_num[i]; |
8370 | enum machine_mode mode = recog_data.operand_mode[op]; | |
e9a25f70 JL |
8371 | |
8372 | if (op_alt_regno[op][j] == -1) | |
8373 | continue; | |
8374 | ||
1ccbefce | 8375 | validate_change (insn, recog_data.dup_loc[i], |
38a448ca | 8376 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); |
2a9fb548 | 8377 | } |
e9a25f70 | 8378 | |
e9a25f70 | 8379 | return apply_change_group (); |
2a9fb548 | 8380 | } |
5adf6da0 R |
8381 | \f |
8382 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
8383 | addressing now. | |
8384 | This code might also be useful when reload gave up on reg+reg addresssing | |
8385 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
8386 | ||
8387 | /* The maximum number of uses of a register we can keep track of to | |
8388 | replace them with reg+reg addressing. */ | |
8389 | #define RELOAD_COMBINE_MAX_USES 6 | |
8390 | ||
8391 | /* INSN is the insn where a register has ben used, and USEP points to the | |
8392 | location of the register within the rtl. */ | |
8393 | struct reg_use { rtx insn, *usep; }; | |
8394 | ||
8395 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
8396 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
8397 | indicates where it becomes live again. | |
8398 | Otherwise, USE_INDEX is the index of the last encountered use of the | |
8399 | register (which is first among these we have seen since we scan backwards), | |
8400 | OFFSET contains the constant offset that is added to the register in | |
8401 | all encountered uses, and USE_RUID indicates the first encountered, i.e. | |
ed937a19 R |
8402 | last, of these uses. |
8403 | STORE_RUID is always meaningful if we only want to use a value in a | |
8404 | register in a different place: it denotes the next insn in the insn | |
8405 | stream (i.e. the last ecountered) that sets or clobbers the register. */ | |
5adf6da0 R |
8406 | static struct |
8407 | { | |
8408 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8409 | int use_index; | |
8410 | rtx offset; | |
8411 | int store_ruid; | |
8412 | int use_ruid; | |
8413 | } reg_state[FIRST_PSEUDO_REGISTER]; | |
8414 | ||
8415 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
8416 | the instructions from last to first. It is used to set last_label_ruid | |
8417 | and the store_ruid / use_ruid fields in reg_state. */ | |
8418 | static int reload_combine_ruid; | |
8419 | ||
b0634509 R |
8420 | #define LABEL_LIVE(LABEL) \ |
8421 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
8422 | ||
5adf6da0 R |
8423 | static void |
8424 | reload_combine () | |
8425 | { | |
8426 | rtx insn, set; | |
881a8969 | 8427 | int first_index_reg = -1, last_index_reg; |
5adf6da0 | 8428 | int i; |
f8cd4126 | 8429 | unsigned int r; |
5adf6da0 | 8430 | int last_label_ruid; |
b0634509 R |
8431 | int min_labelno, n_labels; |
8432 | HARD_REG_SET ever_live_at_start, *label_live; | |
5adf6da0 R |
8433 | |
8434 | /* If reg+reg can be used in offsetable memory adresses, the main chunk of | |
8435 | reload has already used it where appropriate, so there is no use in | |
8436 | trying to generate it now. */ | |
03acd8f8 | 8437 | if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) |
5adf6da0 R |
8438 | return; |
8439 | ||
8440 | /* To avoid wasting too much time later searching for an index register, | |
8441 | determine the minimum and maximum index register numbers. */ | |
f8cd4126 RK |
8442 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8443 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
8444 | { | |
881a8969 | 8445 | if (first_index_reg == -1) |
4c3f1588 RK |
8446 | first_index_reg = r; |
8447 | ||
8448 | last_index_reg = r; | |
f8cd4126 RK |
8449 | } |
8450 | ||
5adf6da0 | 8451 | /* If no index register is available, we can quit now. */ |
881a8969 | 8452 | if (first_index_reg == -1) |
5adf6da0 R |
8453 | return; |
8454 | ||
b0634509 R |
8455 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
8456 | information is a bit fuzzy immediately after reload, but it's | |
8457 | still good enough to determine which registers are live at a jump | |
8458 | destination. */ | |
8459 | min_labelno = get_first_label_num (); | |
8460 | n_labels = max_label_num () - min_labelno; | |
8461 | label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); | |
8462 | CLEAR_HARD_REG_SET (ever_live_at_start); | |
f8cd4126 | 8463 | |
b0634509 R |
8464 | for (i = n_basic_blocks - 1; i >= 0; i--) |
8465 | { | |
3b413743 | 8466 | insn = BLOCK_HEAD (i); |
b0634509 R |
8467 | if (GET_CODE (insn) == CODE_LABEL) |
8468 | { | |
8469 | HARD_REG_SET live; | |
8470 | ||
f8cd4126 RK |
8471 | REG_SET_TO_HARD_REG_SET (live, |
8472 | BASIC_BLOCK (i)->global_live_at_start); | |
8473 | compute_use_by_pseudos (&live, | |
8474 | BASIC_BLOCK (i)->global_live_at_start); | |
b0634509 R |
8475 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
8476 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
8477 | } | |
8478 | } | |
8479 | ||
5adf6da0 R |
8480 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ |
8481 | last_label_ruid = reload_combine_ruid = 0; | |
f8cd4126 | 8482 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
5adf6da0 | 8483 | { |
f8cd4126 RK |
8484 | reg_state[r].store_ruid = reload_combine_ruid; |
8485 | if (fixed_regs[r]) | |
8486 | reg_state[r].use_index = -1; | |
5adf6da0 | 8487 | else |
f8cd4126 | 8488 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
5adf6da0 R |
8489 | } |
8490 | ||
8491 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
8492 | { | |
8493 | rtx note; | |
8494 | ||
8495 | /* We cannot do our optimization across labels. Invalidating all the use | |
8496 | information we have would be costly, so we just note where the label | |
05d10675 | 8497 | is and then later disable any optimization that would cross it. */ |
5adf6da0 R |
8498 | if (GET_CODE (insn) == CODE_LABEL) |
8499 | last_label_ruid = reload_combine_ruid; | |
f8cd4126 RK |
8500 | else if (GET_CODE (insn) == BARRIER) |
8501 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
8502 | if (! fixed_regs[r]) | |
8503 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8504 | ||
2c3c49de | 8505 | if (! INSN_P (insn)) |
5adf6da0 | 8506 | continue; |
f8cd4126 | 8507 | |
5adf6da0 R |
8508 | reload_combine_ruid++; |
8509 | ||
8510 | /* Look for (set (REGX) (CONST_INT)) | |
eceef4c9 BS |
8511 | (set (REGX) (PLUS (REGX) (REGY))) |
8512 | ... | |
8513 | ... (MEM (REGX)) ... | |
5adf6da0 | 8514 | and convert it to |
eceef4c9 BS |
8515 | (set (REGZ) (CONST_INT)) |
8516 | ... | |
8517 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
5adf6da0 R |
8518 | |
8519 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
8520 | and that we know all uses of REGX before it dies. */ | |
2abbc1bd R |
8521 | set = single_set (insn); |
8522 | if (set != NULL_RTX | |
5adf6da0 R |
8523 | && GET_CODE (SET_DEST (set)) == REG |
8524 | && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), | |
8525 | GET_MODE (SET_DEST (set))) | |
8526 | == 1) | |
8527 | && GET_CODE (SET_SRC (set)) == PLUS | |
8528 | && GET_CODE (XEXP (SET_SRC (set), 1)) == REG | |
8529 | && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | |
8530 | && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | |
8531 | { | |
8532 | rtx reg = SET_DEST (set); | |
8533 | rtx plus = SET_SRC (set); | |
8534 | rtx base = XEXP (plus, 1); | |
8535 | rtx prev = prev_nonnote_insn (insn); | |
8536 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; | |
f8cd4126 | 8537 | unsigned int regno = REGNO (reg); |
6a651371 | 8538 | rtx const_reg = NULL_RTX; |
5adf6da0 R |
8539 | rtx reg_sum = NULL_RTX; |
8540 | ||
8541 | /* Now, we need an index register. | |
8542 | We'll set index_reg to this index register, const_reg to the | |
8543 | register that is to be loaded with the constant | |
8544 | (denoted as REGZ in the substitution illustration above), | |
8545 | and reg_sum to the register-register that we want to use to | |
8546 | substitute uses of REG (typically in MEMs) with. | |
8547 | First check REG and BASE for being index registers; | |
8548 | we can use them even if they are not dead. */ | |
8549 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
8550 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
8551 | REGNO (base))) | |
8552 | { | |
8553 | const_reg = reg; | |
8554 | reg_sum = plus; | |
8555 | } | |
8556 | else | |
8557 | { | |
05d10675 BS |
8558 | /* Otherwise, look for a free index register. Since we have |
8559 | checked above that neiter REG nor BASE are index registers, | |
8560 | if we find anything at all, it will be different from these | |
8561 | two registers. */ | |
8562 | for (i = first_index_reg; i <= last_index_reg; i++) | |
5adf6da0 | 8563 | { |
f8cd4126 RK |
8564 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], |
8565 | i) | |
5adf6da0 R |
8566 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES |
8567 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
8568 | && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) | |
8569 | { | |
8570 | rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
f8cd4126 | 8571 | |
5adf6da0 R |
8572 | const_reg = index_reg; |
8573 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
8574 | break; | |
8575 | } | |
8576 | } | |
8577 | } | |
f8cd4126 | 8578 | |
ed937a19 R |
8579 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that |
8580 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
8581 | create. */ | |
f8cd4126 | 8582 | if (prev_set != 0 |
5adf6da0 R |
8583 | && GET_CODE (SET_SRC (prev_set)) == CONST_INT |
8584 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
8585 | && reg_state[regno].use_index >= 0 | |
f8cd4126 RK |
8586 | && (reg_state[REGNO (base)].store_ruid |
8587 | <= reg_state[regno].use_ruid) | |
8588 | && reg_sum != 0) | |
5adf6da0 R |
8589 | { |
8590 | int i; | |
8591 | ||
f8cd4126 | 8592 | /* Change destination register and, if necessary, the |
5adf6da0 R |
8593 | constant value in PREV, the constant loading instruction. */ |
8594 | validate_change (prev, &SET_DEST (prev_set), const_reg, 1); | |
8595 | if (reg_state[regno].offset != const0_rtx) | |
8596 | validate_change (prev, | |
8597 | &SET_SRC (prev_set), | |
8598 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
8599 | + INTVAL (reg_state[regno].offset)), | |
8600 | 1); | |
f8cd4126 | 8601 | |
5adf6da0 R |
8602 | /* Now for every use of REG that we have recorded, replace REG |
8603 | with REG_SUM. */ | |
8604 | for (i = reg_state[regno].use_index; | |
8605 | i < RELOAD_COMBINE_MAX_USES; i++) | |
8606 | validate_change (reg_state[regno].reg_use[i].insn, | |
8607 | reg_state[regno].reg_use[i].usep, | |
8608 | reg_sum, 1); | |
8609 | ||
8610 | if (apply_change_group ()) | |
8611 | { | |
8612 | rtx *np; | |
8613 | ||
8614 | /* Delete the reg-reg addition. */ | |
8615 | PUT_CODE (insn, NOTE); | |
8616 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
8617 | NOTE_SOURCE_FILE (insn) = 0; | |
8618 | ||
8619 | if (reg_state[regno].offset != const0_rtx) | |
f8cd4126 RK |
8620 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV |
8621 | are now invalid. */ | |
1d7254c5 | 8622 | for (np = ®_NOTES (prev); *np;) |
f8cd4126 RK |
8623 | { |
8624 | if (REG_NOTE_KIND (*np) == REG_EQUAL | |
8625 | || REG_NOTE_KIND (*np) == REG_EQUIV) | |
8626 | *np = XEXP (*np, 1); | |
8627 | else | |
8628 | np = &XEXP (*np, 1); | |
8629 | } | |
8630 | ||
5adf6da0 | 8631 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; |
f8cd4126 RK |
8632 | reg_state[REGNO (const_reg)].store_ruid |
8633 | = reload_combine_ruid; | |
5adf6da0 R |
8634 | continue; |
8635 | } | |
8636 | } | |
8637 | } | |
f8cd4126 | 8638 | |
1d7254c5 | 8639 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); |
f8cd4126 | 8640 | |
5adf6da0 R |
8641 | if (GET_CODE (insn) == CALL_INSN) |
8642 | { | |
8643 | rtx link; | |
8644 | ||
f8cd4126 RK |
8645 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8646 | if (call_used_regs[r]) | |
8647 | { | |
8648 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8649 | reg_state[r].store_ruid = reload_combine_ruid; | |
8650 | } | |
8651 | ||
5adf6da0 R |
8652 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; |
8653 | link = XEXP (link, 1)) | |
f8cd4126 RK |
8654 | if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG) |
8655 | { | |
8656 | unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
8657 | ||
8658 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
8659 | { | |
8660 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
8661 | reg_state[regno].store_ruid = reload_combine_ruid; | |
8662 | } | |
8663 | else | |
8664 | reg_state[regno].use_index = -1; | |
8665 | } | |
5adf6da0 | 8666 | } |
f8cd4126 RK |
8667 | |
8668 | else if (GET_CODE (insn) == JUMP_INSN | |
8669 | && GET_CODE (PATTERN (insn)) != RETURN) | |
5adf6da0 R |
8670 | { |
8671 | /* Non-spill registers might be used at the call destination in | |
8672 | some unknown fashion, so we have to mark the unknown use. */ | |
b0634509 | 8673 | HARD_REG_SET *live; |
f8cd4126 | 8674 | |
b0634509 R |
8675 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) |
8676 | && JUMP_LABEL (insn)) | |
8677 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
8678 | else | |
8679 | live = &ever_live_at_start; | |
f8cd4126 | 8680 | |
5adf6da0 | 8681 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) |
f8cd4126 RK |
8682 | if (TEST_HARD_REG_BIT (*live, i)) |
8683 | reg_state[i].use_index = -1; | |
5adf6da0 | 8684 | } |
f8cd4126 | 8685 | |
5adf6da0 R |
8686 | reload_combine_note_use (&PATTERN (insn), insn); |
8687 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
8688 | { | |
8689 | if (REG_NOTE_KIND (note) == REG_INC | |
8690 | && GET_CODE (XEXP (note, 0)) == REG) | |
ed937a19 R |
8691 | { |
8692 | int regno = REGNO (XEXP (note, 0)); | |
8693 | ||
8694 | reg_state[regno].store_ruid = reload_combine_ruid; | |
8695 | reg_state[regno].use_index = -1; | |
8696 | } | |
5adf6da0 R |
8697 | } |
8698 | } | |
f8cd4126 | 8699 | |
b0634509 | 8700 | free (label_live); |
5adf6da0 R |
8701 | } |
8702 | ||
8703 | /* Check if DST is a register or a subreg of a register; if it is, | |
8704 | update reg_state[regno].store_ruid and reg_state[regno].use_index | |
f93233bb | 8705 | accordingly. Called via note_stores from reload_combine. */ |
f8cd4126 | 8706 | |
5adf6da0 | 8707 | static void |
84832317 | 8708 | reload_combine_note_store (dst, set, data) |
f93233bb | 8709 | rtx dst, set; |
84832317 | 8710 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 R |
8711 | { |
8712 | int regno = 0; | |
8713 | int i; | |
54ed0905 | 8714 | enum machine_mode mode = GET_MODE (dst); |
5adf6da0 R |
8715 | |
8716 | if (GET_CODE (dst) == SUBREG) | |
8717 | { | |
8718 | regno = SUBREG_WORD (dst); | |
8719 | dst = SUBREG_REG (dst); | |
8720 | } | |
8721 | if (GET_CODE (dst) != REG) | |
8722 | return; | |
8723 | regno += REGNO (dst); | |
54ca6ffa | 8724 | |
5adf6da0 | 8725 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be |
05d10675 | 8726 | careful with registers / register parts that are not full words. |
54ca6ffa JL |
8727 | |
8728 | Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ | |
8729 | if (GET_CODE (set) != SET | |
8730 | || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | |
8731 | || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT | |
8732 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
ed937a19 | 8733 | { |
54ed0905 | 8734 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
f93233bb JL |
8735 | { |
8736 | reg_state[i].use_index = -1; | |
8737 | reg_state[i].store_ruid = reload_combine_ruid; | |
8738 | } | |
ed937a19 | 8739 | } |
5adf6da0 R |
8740 | else |
8741 | { | |
54ed0905 | 8742 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
5adf6da0 R |
8743 | { |
8744 | reg_state[i].store_ruid = reload_combine_ruid; | |
8745 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8746 | } | |
8747 | } | |
8748 | } | |
8749 | ||
8750 | /* XP points to a piece of rtl that has to be checked for any uses of | |
8751 | registers. | |
8752 | *XP is the pattern of INSN, or a part of it. | |
8753 | Called from reload_combine, and recursively by itself. */ | |
8754 | static void | |
8755 | reload_combine_note_use (xp, insn) | |
8756 | rtx *xp, insn; | |
8757 | { | |
8758 | rtx x = *xp; | |
8759 | enum rtx_code code = x->code; | |
6f7d635c | 8760 | const char *fmt; |
5adf6da0 R |
8761 | int i, j; |
8762 | rtx offset = const0_rtx; /* For the REG case below. */ | |
8763 | ||
8764 | switch (code) | |
8765 | { | |
8766 | case SET: | |
8767 | if (GET_CODE (SET_DEST (x)) == REG) | |
8768 | { | |
8769 | reload_combine_note_use (&SET_SRC (x), insn); | |
8770 | return; | |
8771 | } | |
8772 | break; | |
8773 | ||
6ce7e0f9 R |
8774 | case USE: |
8775 | /* If this is the USE of a return value, we can't change it. */ | |
8776 | if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0))) | |
8777 | { | |
8778 | /* Mark the return register as used in an unknown fashion. */ | |
8779 | rtx reg = XEXP (x, 0); | |
8780 | int regno = REGNO (reg); | |
8781 | int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8782 | ||
8783 | while (--nregs >= 0) | |
8784 | reg_state[regno + nregs].use_index = -1; | |
8785 | return; | |
8786 | } | |
8787 | break; | |
8788 | ||
5adf6da0 R |
8789 | case CLOBBER: |
8790 | if (GET_CODE (SET_DEST (x)) == REG) | |
8791 | return; | |
8792 | break; | |
8793 | ||
8794 | case PLUS: | |
8795 | /* We are interested in (plus (reg) (const_int)) . */ | |
1d7254c5 KH |
8796 | if (GET_CODE (XEXP (x, 0)) != REG |
8797 | || GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5adf6da0 R |
8798 | break; |
8799 | offset = XEXP (x, 1); | |
8800 | x = XEXP (x, 0); | |
05d10675 | 8801 | /* Fall through. */ |
5adf6da0 R |
8802 | case REG: |
8803 | { | |
8804 | int regno = REGNO (x); | |
8805 | int use_index; | |
6ce7e0f9 | 8806 | int nregs; |
5adf6da0 R |
8807 | |
8808 | /* Some spurious USEs of pseudo registers might remain. | |
8809 | Just ignore them. */ | |
8810 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8811 | return; | |
8812 | ||
6ce7e0f9 R |
8813 | nregs = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
8814 | ||
8815 | /* We can't substitute into multi-hard-reg uses. */ | |
8816 | if (nregs > 1) | |
8817 | { | |
8818 | while (--nregs >= 0) | |
8819 | reg_state[regno + nregs].use_index = -1; | |
8820 | return; | |
8821 | } | |
8822 | ||
5adf6da0 R |
8823 | /* If this register is already used in some unknown fashion, we |
8824 | can't do anything. | |
8825 | If we decrement the index from zero to -1, we can't store more | |
8826 | uses, so this register becomes used in an unknown fashion. */ | |
8827 | use_index = --reg_state[regno].use_index; | |
8828 | if (use_index < 0) | |
8829 | return; | |
8830 | ||
8831 | if (use_index != RELOAD_COMBINE_MAX_USES - 1) | |
8832 | { | |
8833 | /* We have found another use for a register that is already | |
8834 | used later. Check if the offsets match; if not, mark the | |
8835 | register as used in an unknown fashion. */ | |
8836 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
8837 | { | |
8838 | reg_state[regno].use_index = -1; | |
8839 | return; | |
8840 | } | |
8841 | } | |
8842 | else | |
8843 | { | |
8844 | /* This is the first use of this register we have seen since we | |
8845 | marked it as dead. */ | |
8846 | reg_state[regno].offset = offset; | |
8847 | reg_state[regno].use_ruid = reload_combine_ruid; | |
8848 | } | |
8849 | reg_state[regno].reg_use[use_index].insn = insn; | |
8850 | reg_state[regno].reg_use[use_index].usep = xp; | |
8851 | return; | |
8852 | } | |
8853 | ||
8854 | default: | |
8855 | break; | |
8856 | } | |
8857 | ||
8858 | /* Recursively process the components of X. */ | |
8859 | fmt = GET_RTX_FORMAT (code); | |
8860 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8861 | { | |
8862 | if (fmt[i] == 'e') | |
8863 | reload_combine_note_use (&XEXP (x, i), insn); | |
8864 | else if (fmt[i] == 'E') | |
8865 | { | |
8866 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8867 | reload_combine_note_use (&XVECEXP (x, i, j), insn); | |
8868 | } | |
8869 | } | |
8870 | } | |
8871 | \f | |
8872 | /* See if we can reduce the cost of a constant by replacing a move with | |
8873 | an add. */ | |
8874 | /* We cannot do our optimization across labels. Invalidating all the | |
8875 | information about register contents we have would be costly, so we | |
8876 | use last_label_luid (local variable of reload_cse_move2add) to note | |
8877 | where the label is and then later disable any optimization that would | |
8878 | cross it. | |
8879 | reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if | |
8880 | reg_set_luid[n] is larger than last_label_luid[n] . */ | |
8881 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; | |
770ae6cc | 8882 | |
5adf6da0 R |
8883 | /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] / |
8884 | reg_mode[n] to be valid. | |
8885 | If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n | |
8886 | has been set to reg_offset[n] in mode reg_mode[n] . | |
8887 | If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative, | |
8888 | register n has been set to the sum of reg_offset[n] and register | |
8889 | reg_base_reg[n], calculated in mode reg_mode[n] . */ | |
8890 | static rtx reg_offset[FIRST_PSEUDO_REGISTER]; | |
8891 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
8892 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; | |
770ae6cc | 8893 | |
5adf6da0 R |
8894 | /* move2add_luid is linearily increased while scanning the instructions |
8895 | from first to last. It is used to set reg_set_luid in | |
6764d250 | 8896 | reload_cse_move2add and move2add_note_store. */ |
5adf6da0 R |
8897 | static int move2add_luid; |
8898 | ||
ccc4ae07 | 8899 | /* Generate a CONST_INT and force it in the range of MODE. */ |
770ae6cc | 8900 | |
ccc4ae07 AS |
8901 | static rtx |
8902 | gen_mode_int (mode, value) | |
8903 | enum machine_mode mode; | |
8904 | HOST_WIDE_INT value; | |
8905 | { | |
8906 | HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); | |
8907 | int width = GET_MODE_BITSIZE (mode); | |
8908 | ||
8909 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, | |
8910 | sign extend it. */ | |
8911 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
8912 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
8913 | cval |= (HOST_WIDE_INT) -1 << width; | |
8914 | ||
8915 | return GEN_INT (cval); | |
8916 | } | |
8917 | ||
5adf6da0 R |
8918 | static void |
8919 | reload_cse_move2add (first) | |
8920 | rtx first; | |
8921 | { | |
8922 | int i; | |
8923 | rtx insn; | |
8924 | int last_label_luid; | |
5adf6da0 | 8925 | |
1d7254c5 | 8926 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
6764d250 BS |
8927 | reg_set_luid[i] = 0; |
8928 | ||
5adf6da0 R |
8929 | last_label_luid = 0; |
8930 | move2add_luid = 1; | |
8931 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
8932 | { | |
8933 | rtx pat, note; | |
8934 | ||
8935 | if (GET_CODE (insn) == CODE_LABEL) | |
8936 | last_label_luid = move2add_luid; | |
2c3c49de | 8937 | if (! INSN_P (insn)) |
5adf6da0 R |
8938 | continue; |
8939 | pat = PATTERN (insn); | |
8940 | /* For simplicity, we only perform this optimization on | |
8941 | straightforward SETs. */ | |
8942 | if (GET_CODE (pat) == SET | |
8943 | && GET_CODE (SET_DEST (pat)) == REG) | |
8944 | { | |
8945 | rtx reg = SET_DEST (pat); | |
8946 | int regno = REGNO (reg); | |
8947 | rtx src = SET_SRC (pat); | |
8948 | ||
8949 | /* Check if we have valid information on the contents of this | |
8950 | register in the mode of REG. */ | |
8951 | /* ??? We don't know how zero / sign extension is handled, hence | |
8952 | we can't go from a narrower to a wider mode. */ | |
8953 | if (reg_set_luid[regno] > last_label_luid | |
a3afe920 R |
8954 | && ((GET_MODE_SIZE (GET_MODE (reg)) |
8955 | == GET_MODE_SIZE (reg_mode[regno])) | |
8956 | || ((GET_MODE_SIZE (GET_MODE (reg)) | |
8957 | <= GET_MODE_SIZE (reg_mode[regno])) | |
8958 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)), | |
8959 | GET_MODE_BITSIZE (reg_mode[regno])))) | |
05d10675 | 8960 | && GET_CODE (reg_offset[regno]) == CONST_INT) |
5adf6da0 R |
8961 | { |
8962 | /* Try to transform (set (REGX) (CONST_INT A)) | |
8963 | ... | |
8964 | (set (REGX) (CONST_INT B)) | |
8965 | to | |
8966 | (set (REGX) (CONST_INT A)) | |
8967 | ... | |
8968 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
8969 | ||
8970 | if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) | |
8971 | { | |
8972 | int success = 0; | |
ccc4ae07 AS |
8973 | rtx new_src |
8974 | = gen_mode_int (GET_MODE (reg), | |
8975 | INTVAL (src) - INTVAL (reg_offset[regno])); | |
5adf6da0 R |
8976 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
8977 | use (set (reg) (reg)) instead. | |
8978 | We don't delete this insn, nor do we convert it into a | |
8979 | note, to avoid losing register notes or the return | |
8980 | value flag. jump2 already knowns how to get rid of | |
8981 | no-op moves. */ | |
8982 | if (new_src == const0_rtx) | |
8983 | success = validate_change (insn, &SET_SRC (pat), reg, 0); | |
8984 | else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) | |
8985 | && have_add2_insn (GET_MODE (reg))) | |
8986 | success = validate_change (insn, &PATTERN (insn), | |
8987 | gen_add2_insn (reg, new_src), 0); | |
5adf6da0 R |
8988 | reg_set_luid[regno] = move2add_luid; |
8989 | reg_mode[regno] = GET_MODE (reg); | |
8990 | reg_offset[regno] = src; | |
8991 | continue; | |
8992 | } | |
8993 | ||
8994 | /* Try to transform (set (REGX) (REGY)) | |
8995 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
8996 | ... | |
8997 | (set (REGX) (REGY)) | |
8998 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
8999 | to | |
9000 | (REGX) (REGY)) | |
9001 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9002 | ... | |
9003 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9004 | else if (GET_CODE (src) == REG | |
770ae6cc | 9005 | && reg_base_reg[regno] == (int) REGNO (src) |
5adf6da0 R |
9006 | && reg_set_luid[regno] > reg_set_luid[REGNO (src)]) |
9007 | { | |
9008 | rtx next = next_nonnote_insn (insn); | |
6a651371 | 9009 | rtx set = NULL_RTX; |
5adf6da0 R |
9010 | if (next) |
9011 | set = single_set (next); | |
9012 | if (next | |
9013 | && set | |
9014 | && SET_DEST (set) == reg | |
9015 | && GET_CODE (SET_SRC (set)) == PLUS | |
9016 | && XEXP (SET_SRC (set), 0) == reg | |
9017 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
9018 | { | |
5adf6da0 | 9019 | rtx src3 = XEXP (SET_SRC (set), 1); |
ccc4ae07 AS |
9020 | rtx new_src |
9021 | = gen_mode_int (GET_MODE (reg), | |
9022 | INTVAL (src3) | |
9023 | - INTVAL (reg_offset[regno])); | |
5adf6da0 R |
9024 | int success = 0; |
9025 | ||
9026 | if (new_src == const0_rtx) | |
9027 | /* See above why we create (set (reg) (reg)) here. */ | |
9028 | success | |
9029 | = validate_change (next, &SET_SRC (set), reg, 0); | |
9030 | else if ((rtx_cost (new_src, PLUS) | |
b437f1a7 | 9031 | < COSTS_N_INSNS (1) + rtx_cost (src3, SET)) |
5adf6da0 R |
9032 | && have_add2_insn (GET_MODE (reg))) |
9033 | success | |
9034 | = validate_change (next, &PATTERN (next), | |
9035 | gen_add2_insn (reg, new_src), 0); | |
9036 | if (success) | |
9037 | { | |
5adf6da0 R |
9038 | /* INSN might be the first insn in a basic block |
9039 | if the preceding insn is a conditional jump | |
9040 | or a possible-throwing call. */ | |
9041 | PUT_CODE (insn, NOTE); | |
9042 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
9043 | NOTE_SOURCE_FILE (insn) = 0; | |
9044 | } | |
9045 | insn = next; | |
9046 | reg_set_luid[regno] = move2add_luid; | |
9047 | reg_mode[regno] = GET_MODE (reg); | |
9048 | reg_offset[regno] = src3; | |
9049 | continue; | |
9050 | } | |
9051 | } | |
9052 | } | |
9053 | } | |
9054 | ||
9055 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
9056 | { | |
9057 | if (REG_NOTE_KIND (note) == REG_INC | |
9058 | && GET_CODE (XEXP (note, 0)) == REG) | |
9059 | { | |
9060 | /* Indicate that this register has been recently written to, | |
9061 | but the exact contents are not available. */ | |
9062 | int regno = REGNO (XEXP (note, 0)); | |
9063 | if (regno < FIRST_PSEUDO_REGISTER) | |
9064 | { | |
9065 | reg_set_luid[regno] = move2add_luid; | |
9066 | reg_offset[regno] = note; | |
9067 | } | |
9068 | } | |
5adf6da0 | 9069 | } |
84832317 | 9070 | note_stores (PATTERN (insn), move2add_note_store, NULL); |
5adf6da0 R |
9071 | /* If this is a CALL_INSN, all call used registers are stored with |
9072 | unknown values. */ | |
9073 | if (GET_CODE (insn) == CALL_INSN) | |
9074 | { | |
1d7254c5 | 9075 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
5adf6da0 R |
9076 | { |
9077 | if (call_used_regs[i]) | |
9078 | { | |
9079 | reg_set_luid[i] = move2add_luid; | |
9080 | reg_offset[i] = insn; /* Invalidate contents. */ | |
9081 | } | |
9082 | } | |
9083 | } | |
9084 | } | |
9085 | } | |
9086 | ||
9087 | /* SET is a SET or CLOBBER that sets DST. | |
9088 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. | |
9089 | Called from reload_cse_move2add via note_stores. */ | |
770ae6cc | 9090 | |
5adf6da0 | 9091 | static void |
84832317 | 9092 | move2add_note_store (dst, set, data) |
5adf6da0 | 9093 | rtx dst, set; |
84832317 | 9094 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 | 9095 | { |
770ae6cc RK |
9096 | unsigned int regno = 0; |
9097 | unsigned int i; | |
5adf6da0 | 9098 | enum machine_mode mode = GET_MODE (dst); |
770ae6cc | 9099 | |
5adf6da0 R |
9100 | if (GET_CODE (dst) == SUBREG) |
9101 | { | |
9102 | regno = SUBREG_WORD (dst); | |
9103 | dst = SUBREG_REG (dst); | |
9104 | } | |
770ae6cc | 9105 | |
19ca869b JR |
9106 | /* Some targets do argument pushes without adding REG_INC notes. */ |
9107 | ||
9108 | if (GET_CODE (dst) == MEM) | |
9109 | { | |
9110 | dst = XEXP (dst, 0); | |
9111 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC | |
9112 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) | |
9113 | { | |
9114 | regno = REGNO (XEXP (dst, 0)); | |
9115 | reg_set_luid[regno] = move2add_luid; | |
9116 | reg_offset[regno] = dst; | |
9117 | } | |
9118 | return; | |
9119 | } | |
5adf6da0 R |
9120 | if (GET_CODE (dst) != REG) |
9121 | return; | |
9122 | ||
9123 | regno += REGNO (dst); | |
9124 | ||
f93233bb JL |
9125 | if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET |
9126 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | |
9127 | && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT | |
9128 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | |
5adf6da0 R |
9129 | { |
9130 | rtx src = SET_SRC (set); | |
9131 | ||
9132 | reg_mode[regno] = mode; | |
9133 | switch (GET_CODE (src)) | |
9134 | { | |
9135 | case PLUS: | |
9136 | { | |
9137 | rtx src0 = XEXP (src, 0); | |
770ae6cc | 9138 | |
5adf6da0 R |
9139 | if (GET_CODE (src0) == REG) |
9140 | { | |
9141 | if (REGNO (src0) != regno | |
9142 | || reg_offset[regno] != const0_rtx) | |
9143 | { | |
9144 | reg_base_reg[regno] = REGNO (src0); | |
9145 | reg_set_luid[regno] = move2add_luid; | |
9146 | } | |
770ae6cc | 9147 | |
5adf6da0 R |
9148 | reg_offset[regno] = XEXP (src, 1); |
9149 | break; | |
9150 | } | |
770ae6cc | 9151 | |
5adf6da0 R |
9152 | reg_set_luid[regno] = move2add_luid; |
9153 | reg_offset[regno] = set; /* Invalidate contents. */ | |
9154 | break; | |
9155 | } | |
9156 | ||
9157 | case REG: | |
9158 | reg_base_reg[regno] = REGNO (SET_SRC (set)); | |
9159 | reg_offset[regno] = const0_rtx; | |
9160 | reg_set_luid[regno] = move2add_luid; | |
9161 | break; | |
9162 | ||
9163 | default: | |
9164 | reg_base_reg[regno] = -1; | |
9165 | reg_offset[regno] = SET_SRC (set); | |
9166 | reg_set_luid[regno] = move2add_luid; | |
9167 | break; | |
9168 | } | |
9169 | } | |
9170 | else | |
9171 | { | |
770ae6cc RK |
9172 | unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode); |
9173 | ||
9174 | for (i = regno; i < endregno; i++) | |
5adf6da0 R |
9175 | { |
9176 | /* Indicate that this register has been recently written to, | |
9177 | but the exact contents are not available. */ | |
9178 | reg_set_luid[i] = move2add_luid; | |
9179 | reg_offset[i] = dst; | |
9180 | } | |
9181 | } | |
9182 | } | |
2dfa9a87 MH |
9183 | |
9184 | #ifdef AUTO_INC_DEC | |
9185 | static void | |
9186 | add_auto_inc_notes (insn, x) | |
9187 | rtx insn; | |
9188 | rtx x; | |
9189 | { | |
9190 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 9191 | const char *fmt; |
2dfa9a87 MH |
9192 | int i, j; |
9193 | ||
9194 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
9195 | { | |
9196 | REG_NOTES (insn) | |
9197 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
9198 | return; | |
9199 | } | |
9200 | ||
9201 | /* Scan all the operand sub-expressions. */ | |
9202 | fmt = GET_RTX_FORMAT (code); | |
9203 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9204 | { | |
9205 | if (fmt[i] == 'e') | |
9206 | add_auto_inc_notes (insn, XEXP (x, i)); | |
9207 | else if (fmt[i] == 'E') | |
9208 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9209 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
9210 | } | |
9211 | } | |
9212 | #endif |