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eab89b90 | 1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
47c3ed98 | 2 | Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. |
eab89b90 RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
eab89b90 RK |
20 | |
21 | ||
22 | /* This file contains subroutines used only from the file reload1.c. | |
23 | It knows how to scan one insn for operands and values | |
24 | that need to be copied into registers to make valid code. | |
25 | It also finds other operands and values which are valid | |
26 | but for which equivalent values in registers exist and | |
27 | ought to be used instead. | |
28 | ||
29 | Before processing the first insn of the function, call `init_reload'. | |
30 | ||
31 | To scan an insn, call `find_reloads'. This does two things: | |
32 | 1. sets up tables describing which values must be reloaded | |
33 | for this insn, and what kind of hard regs they must be reloaded into; | |
34 | 2. optionally record the locations where those values appear in | |
35 | the data, so they can be replaced properly later. | |
36 | This is done only if the second arg to `find_reloads' is nonzero. | |
37 | ||
38 | The third arg to `find_reloads' specifies the number of levels | |
39 | of indirect addressing supported by the machine. If it is zero, | |
40 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
41 | is valid even if (REG n) did not get a hard register; if it is two, | |
42 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
43 | hard register, and similarly for higher values. | |
44 | ||
45 | Then you must choose the hard regs to reload those pseudo regs into, | |
46 | and generate appropriate load insns before this insn and perhaps | |
47 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
48 | to contain the REG rtx's for the registers you used. In some | |
49 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
50 | for certain reloads. Then that tells you which register to use, | |
51 | so you do not need to allocate one. But you still do need to add extra | |
52 | instructions to copy the value into and out of that register. | |
53 | ||
54 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
55 | into the locations already recorded. | |
56 | ||
57 | NOTE SIDE EFFECTS: | |
58 | ||
59 | find_reloads can alter the operands of the instruction it is called on. | |
60 | ||
61 | 1. Two operands of any sort may be interchanged, if they are in a | |
62 | commutative instruction. | |
63 | This happens only if find_reloads thinks the instruction will compile | |
64 | better that way. | |
65 | ||
66 | 2. Pseudo-registers that are equivalent to constants are replaced | |
67 | with those constants if they are not in hard registers. | |
68 | ||
69 | 1 happens every time find_reloads is called. | |
70 | 2 happens only when REPLACE is 1, which is only when | |
71 | actually doing the reloads, not when just counting them. | |
72 | ||
73 | ||
74 | Using a reload register for several reloads in one insn: | |
75 | ||
76 | When an insn has reloads, it is considered as having three parts: | |
77 | the input reloads, the insn itself after reloading, and the output reloads. | |
78 | Reloads of values used in memory addresses are often needed for only one part. | |
79 | ||
80 | When this is so, reload_when_needed records which part needs the reload. | |
81 | Two reloads for different parts of the insn can share the same reload | |
82 | register. | |
83 | ||
84 | When a reload is used for addresses in multiple parts, or when it is | |
85 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
86 | a register with any other reload. */ | |
87 | ||
88 | #define REG_OK_STRICT | |
89 | ||
90 | #include "config.h" | |
670ee920 | 91 | #include "system.h" |
eab89b90 | 92 | #include "rtl.h" |
6baf1cc8 | 93 | #include "tm_p.h" |
eab89b90 RK |
94 | #include "insn-config.h" |
95 | #include "insn-codes.h" | |
96 | #include "recog.h" | |
97 | #include "reload.h" | |
98 | #include "regs.h" | |
99 | #include "hard-reg-set.h" | |
100 | #include "flags.h" | |
101 | #include "real.h" | |
8a840ac9 | 102 | #include "output.h" |
49ad7cfa | 103 | #include "function.h" |
55c22565 | 104 | #include "expr.h" |
10f0ad3d | 105 | #include "toplev.h" |
eab89b90 RK |
106 | |
107 | #ifndef REGISTER_MOVE_COST | |
108 | #define REGISTER_MOVE_COST(x, y) 2 | |
109 | #endif | |
858c3c8c ILT |
110 | |
111 | #ifndef REGNO_MODE_OK_FOR_BASE_P | |
112 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO) | |
113 | #endif | |
114 | ||
115 | #ifndef REG_MODE_OK_FOR_BASE_P | |
116 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
117 | #endif | |
eab89b90 | 118 | \f |
eceef4c9 BS |
119 | /* All reloads of the current insn are recorded here. See reload.h for |
120 | comments. */ | |
eab89b90 | 121 | int n_reloads; |
eceef4c9 | 122 | struct reload rld[MAX_RELOADS]; |
eab89b90 RK |
123 | |
124 | /* All the "earlyclobber" operands of the current insn | |
125 | are recorded here. */ | |
126 | int n_earlyclobbers; | |
127 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
128 | ||
a8c9daeb RK |
129 | int reload_n_operands; |
130 | ||
eab89b90 RK |
131 | /* Replacing reloads. |
132 | ||
133 | If `replace_reloads' is nonzero, then as each reload is recorded | |
134 | an entry is made for it in the table `replacements'. | |
135 | Then later `subst_reloads' can look through that table and | |
136 | perform all the replacements needed. */ | |
137 | ||
138 | /* Nonzero means record the places to replace. */ | |
139 | static int replace_reloads; | |
140 | ||
141 | /* Each replacement is recorded with a structure like this. */ | |
142 | struct replacement | |
143 | { | |
144 | rtx *where; /* Location to store in */ | |
145 | rtx *subreg_loc; /* Location of SUBREG if WHERE is inside | |
146 | a SUBREG; 0 otherwise. */ | |
147 | int what; /* which reload this is for */ | |
148 | enum machine_mode mode; /* mode it must have */ | |
149 | }; | |
150 | ||
151 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
152 | ||
153 | /* Number of replacements currently recorded. */ | |
154 | static int n_replacements; | |
155 | ||
a8c9daeb RK |
156 | /* Used to track what is modified by an operand. */ |
157 | struct decomposition | |
158 | { | |
0f41302f MS |
159 | int reg_flag; /* Nonzero if referencing a register. */ |
160 | int safe; /* Nonzero if this can't conflict with anything. */ | |
161 | rtx base; /* Base address for MEM. */ | |
162 | HOST_WIDE_INT start; /* Starting offset or register number. */ | |
2a6d5ce0 | 163 | HOST_WIDE_INT end; /* Ending offset or register number. */ |
a8c9daeb RK |
164 | }; |
165 | ||
0dadecf6 RK |
166 | #ifdef SECONDARY_MEMORY_NEEDED |
167 | ||
168 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
05d10675 | 169 | is used per mode, but normally only one or two modes are ever used. |
0dadecf6 | 170 | |
05d10675 | 171 | We keep two versions, before and after register elimination. The one |
a8c9daeb RK |
172 | after register elimination is record separately for each operand. This |
173 | is done in case the address is not valid to be sure that we separately | |
174 | reload each. */ | |
0dadecf6 RK |
175 | |
176 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
77545d45 | 177 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; |
0dadecf6 RK |
178 | #endif |
179 | ||
eab89b90 RK |
180 | /* The instruction we are doing reloads for; |
181 | so we can test whether a register dies in it. */ | |
182 | static rtx this_insn; | |
183 | ||
184 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
185 | static int this_insn_is_asm; | |
186 | ||
187 | /* If hard_regs_live_known is nonzero, | |
188 | we can tell which hard regs are currently live, | |
189 | at least enough to succeed in choosing dummy reloads. */ | |
190 | static int hard_regs_live_known; | |
191 | ||
192 | /* Indexed by hard reg number, | |
956d6950 | 193 | element is nonnegative if hard reg has been spilled. |
eab89b90 RK |
194 | This vector is passed to `find_reloads' as an argument |
195 | and is not changed here. */ | |
196 | static short *static_reload_reg_p; | |
197 | ||
198 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
199 | static int subst_reg_equivs_changed; | |
200 | ||
201 | /* On return from push_reload, holds the reload-number for the OUT | |
202 | operand, which can be different for that from the input operand. */ | |
203 | static int output_reloadnum; | |
204 | ||
9ec7078b RK |
205 | /* Compare two RTX's. */ |
206 | #define MATCHES(x, y) \ | |
207 | (x == y || (x != 0 && (GET_CODE (x) == REG \ | |
208 | ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \ | |
209 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) | |
210 | ||
211 | /* Indicates if two reloads purposes are for similar enough things that we | |
212 | can merge their reloads. */ | |
213 | #define MERGABLE_RELOADS(when1, when2, op1, op2) \ | |
214 | ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ | |
215 | || ((when1) == (when2) && (op1) == (op2)) \ | |
216 | || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ | |
217 | || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
218 | && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ | |
219 | || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ | |
220 | && (when2) == RELOAD_FOR_OTHER_ADDRESS)) | |
221 | ||
222 | /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ | |
223 | #define MERGE_TO_OTHER(when1, when2, op1, op2) \ | |
224 | ((when1) != (when2) \ | |
225 | || ! ((op1) == (op2) \ | |
226 | || (when1) == RELOAD_FOR_INPUT \ | |
227 | || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
228 | || (when1) == RELOAD_FOR_OTHER_ADDRESS)) | |
229 | ||
47c8cf91 ILT |
230 | /* If we are going to reload an address, compute the reload type to |
231 | use. */ | |
232 | #define ADDR_TYPE(type) \ | |
233 | ((type) == RELOAD_FOR_INPUT_ADDRESS \ | |
234 | ? RELOAD_FOR_INPADDR_ADDRESS \ | |
235 | : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \ | |
236 | ? RELOAD_FOR_OUTADDR_ADDRESS \ | |
237 | : (type))) | |
238 | ||
56c5d8bf | 239 | #ifdef HAVE_SECONDARY_RELOADS |
9ec7078b RK |
240 | static int push_secondary_reload PROTO((int, rtx, int, int, enum reg_class, |
241 | enum machine_mode, enum reload_type, | |
242 | enum insn_code *)); | |
56c5d8bf | 243 | #endif |
c6716840 | 244 | static enum reg_class find_valid_class PROTO((enum machine_mode, int)); |
a8c9daeb RK |
245 | static int push_reload PROTO((rtx, rtx, rtx *, rtx *, enum reg_class, |
246 | enum machine_mode, enum machine_mode, | |
247 | int, int, int, enum reload_type)); | |
248 | static void push_replacement PROTO((rtx *, int, enum machine_mode)); | |
249 | static void combine_reloads PROTO((void)); | |
121315ea BS |
250 | static int find_reusable_reload PROTO((rtx *, rtx, enum reg_class, |
251 | enum reload_type, int, int)); | |
a8c9daeb | 252 | static rtx find_dummy_reload PROTO((rtx, rtx, rtx *, rtx *, |
36b50568 | 253 | enum machine_mode, enum machine_mode, |
189086f9 | 254 | enum reg_class, int, int)); |
4644aad4 | 255 | static int earlyclobber_operand_p PROTO((rtx)); |
a8c9daeb RK |
256 | static int hard_reg_set_here_p PROTO((int, int, rtx)); |
257 | static struct decomposition decompose PROTO((rtx)); | |
258 | static int immune_p PROTO((rtx, rtx, struct decomposition)); | |
9b3142b3 | 259 | static int alternative_allows_memconst PROTO((const char *, int)); |
cb2afeb3 | 260 | static rtx find_reloads_toplev PROTO((rtx, int, enum reload_type, int, int, rtx)); |
a8c9daeb RK |
261 | static rtx make_memloc PROTO((rtx, int)); |
262 | static int find_reloads_address PROTO((enum machine_mode, rtx *, rtx, rtx *, | |
55c22565 | 263 | int, enum reload_type, int, rtx)); |
cb2afeb3 | 264 | static rtx subst_reg_equivs PROTO((rtx, rtx)); |
a8c9daeb | 265 | static rtx subst_indexed_address PROTO((rtx)); |
858c3c8c | 266 | static int find_reloads_address_1 PROTO((enum machine_mode, rtx, int, rtx *, |
55c22565 | 267 | int, enum reload_type,int, rtx)); |
a8c9daeb RK |
268 | static void find_reloads_address_part PROTO((rtx, rtx *, enum reg_class, |
269 | enum machine_mode, int, | |
270 | enum reload_type, int)); | |
22505ad8 R |
271 | static rtx find_reloads_subreg_address PROTO((rtx, int, int, enum reload_type, |
272 | int, rtx)); | |
a8c9daeb | 273 | static int find_inc_amount PROTO((rtx, rtx)); |
cb2afeb3 | 274 | static int loc_mentioned_in_p PROTO((rtx *, rtx)); |
eab89b90 RK |
275 | \f |
276 | #ifdef HAVE_SECONDARY_RELOADS | |
277 | ||
278 | /* Determine if any secondary reloads are needed for loading (if IN_P is | |
279 | non-zero) or storing (if IN_P is zero) X to or from a reload register of | |
9ec7078b RK |
280 | register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads |
281 | are needed, push them. | |
282 | ||
283 | Return the reload number of the secondary reload we made, or -1 if | |
284 | we didn't need one. *PICODE is set to the insn_code to use if we do | |
285 | need a secondary reload. */ | |
286 | ||
287 | static int | |
288 | push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode, | |
289 | type, picode) | |
290 | int in_p; | |
eab89b90 | 291 | rtx x; |
9ec7078b RK |
292 | int opnum; |
293 | int optional; | |
eab89b90 RK |
294 | enum reg_class reload_class; |
295 | enum machine_mode reload_mode; | |
9ec7078b | 296 | enum reload_type type; |
eab89b90 | 297 | enum insn_code *picode; |
eab89b90 RK |
298 | { |
299 | enum reg_class class = NO_REGS; | |
300 | enum machine_mode mode = reload_mode; | |
301 | enum insn_code icode = CODE_FOR_nothing; | |
302 | enum reg_class t_class = NO_REGS; | |
303 | enum machine_mode t_mode = VOIDmode; | |
304 | enum insn_code t_icode = CODE_FOR_nothing; | |
d94d2abc | 305 | enum reload_type secondary_type; |
9ec7078b RK |
306 | int s_reload, t_reload = -1; |
307 | ||
47c8cf91 ILT |
308 | if (type == RELOAD_FOR_INPUT_ADDRESS |
309 | || type == RELOAD_FOR_OUTPUT_ADDRESS | |
310 | || type == RELOAD_FOR_INPADDR_ADDRESS | |
311 | || type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d94d2abc RK |
312 | secondary_type = type; |
313 | else | |
314 | secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS; | |
315 | ||
9ec7078b | 316 | *picode = CODE_FOR_nothing; |
eab89b90 | 317 | |
67340b03 RK |
318 | /* If X is a paradoxical SUBREG, use the inner value to determine both the |
319 | mode and object being reloaded. */ | |
320 | if (GET_CODE (x) == SUBREG | |
321 | && (GET_MODE_SIZE (GET_MODE (x)) | |
322 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
323 | { | |
324 | x = SUBREG_REG (x); | |
325 | reload_mode = GET_MODE (x); | |
326 | } | |
327 | ||
d45cf215 RS |
328 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
329 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
330 | but we don't want to assume that), use that equivalent when seeing if | |
331 | a secondary reload is needed since whether or not a reload is needed | |
332 | might be sensitive to the form of the MEM. */ | |
333 | ||
334 | if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
335 | && reg_equiv_mem[REGNO (x)] != 0) | |
336 | x = reg_equiv_mem[REGNO (x)]; | |
337 | ||
eab89b90 RK |
338 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
339 | if (in_p) | |
340 | class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
341 | #endif | |
342 | ||
343 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
344 | if (! in_p) | |
345 | class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
346 | #endif | |
347 | ||
9ec7078b | 348 | /* If we don't need any secondary registers, done. */ |
eab89b90 | 349 | if (class == NO_REGS) |
9ec7078b | 350 | return -1; |
eab89b90 RK |
351 | |
352 | /* Get a possible insn to use. If the predicate doesn't accept X, don't | |
353 | use the insn. */ | |
354 | ||
355 | icode = (in_p ? reload_in_optab[(int) reload_mode] | |
356 | : reload_out_optab[(int) reload_mode]); | |
357 | ||
358 | if (icode != CODE_FOR_nothing | |
a995e389 RH |
359 | && insn_data[(int) icode].operand[in_p].predicate |
360 | && (! (insn_data[(int) icode].operand[in_p].predicate) (x, reload_mode))) | |
eab89b90 RK |
361 | icode = CODE_FOR_nothing; |
362 | ||
363 | /* If we will be using an insn, see if it can directly handle the reload | |
364 | register we will be using. If it can, the secondary reload is for a | |
365 | scratch register. If it can't, we will use the secondary reload for | |
366 | an intermediate register and require a tertiary reload for the scratch | |
367 | register. */ | |
368 | ||
369 | if (icode != CODE_FOR_nothing) | |
370 | { | |
05d10675 | 371 | /* If IN_P is non-zero, the reload register will be the output in |
eab89b90 RK |
372 | operand 0. If IN_P is zero, the reload register will be the input |
373 | in operand 1. Outputs should have an initial "=", which we must | |
374 | skip. */ | |
375 | ||
a995e389 RH |
376 | char insn_letter |
377 | = insn_data[(int) icode].operand[!in_p].constraint[in_p]; | |
eab89b90 | 378 | enum reg_class insn_class |
d45cf215 | 379 | = (insn_letter == 'r' ? GENERAL_REGS |
e51712db | 380 | : REG_CLASS_FROM_LETTER ((unsigned char) insn_letter)); |
eab89b90 RK |
381 | |
382 | if (insn_class == NO_REGS | |
a995e389 RH |
383 | || (in_p |
384 | && insn_data[(int) icode].operand[!in_p].constraint[0] != '=') | |
eab89b90 | 385 | /* The scratch register's constraint must start with "=&". */ |
a995e389 RH |
386 | || insn_data[(int) icode].operand[2].constraint[0] != '=' |
387 | || insn_data[(int) icode].operand[2].constraint[1] != '&') | |
eab89b90 RK |
388 | abort (); |
389 | ||
390 | if (reg_class_subset_p (reload_class, insn_class)) | |
a995e389 | 391 | mode = insn_data[(int) icode].operand[2].mode; |
eab89b90 RK |
392 | else |
393 | { | |
a995e389 | 394 | char t_letter = insn_data[(int) icode].operand[2].constraint[2]; |
eab89b90 | 395 | class = insn_class; |
a995e389 | 396 | t_mode = insn_data[(int) icode].operand[2].mode; |
d45cf215 | 397 | t_class = (t_letter == 'r' ? GENERAL_REGS |
e51712db | 398 | : REG_CLASS_FROM_LETTER ((unsigned char) t_letter)); |
eab89b90 RK |
399 | t_icode = icode; |
400 | icode = CODE_FOR_nothing; | |
401 | } | |
402 | } | |
403 | ||
9ec7078b RK |
404 | /* This case isn't valid, so fail. Reload is allowed to use the same |
405 | register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but | |
406 | in the case of a secondary register, we actually need two different | |
407 | registers for correct code. We fail here to prevent the possibility of | |
408 | silently generating incorrect code later. | |
409 | ||
410 | The convention is that secondary input reloads are valid only if the | |
411 | secondary_class is different from class. If you have such a case, you | |
412 | can not use secondary reloads, you must work around the problem some | |
413 | other way. | |
414 | ||
415 | Allow this when MODE is not reload_mode and assume that the generated | |
416 | code handles this case (it does on the Alpha, which is the only place | |
417 | this currently happens). */ | |
418 | ||
419 | if (in_p && class == reload_class && mode == reload_mode) | |
420 | abort (); | |
421 | ||
422 | /* If we need a tertiary reload, see if we have one we can reuse or else | |
423 | make a new one. */ | |
424 | ||
425 | if (t_class != NO_REGS) | |
426 | { | |
427 | for (t_reload = 0; t_reload < n_reloads; t_reload++) | |
eceef4c9 BS |
428 | if (rld[t_reload].secondary_p |
429 | && (reg_class_subset_p (t_class, rld[t_reload].class) | |
430 | || reg_class_subset_p (rld[t_reload].class, t_class)) | |
431 | && ((in_p && rld[t_reload].inmode == t_mode) | |
432 | || (! in_p && rld[t_reload].outmode == t_mode)) | |
433 | && ((in_p && (rld[t_reload].secondary_in_icode | |
9ec7078b | 434 | == CODE_FOR_nothing)) |
eceef4c9 | 435 | || (! in_p &&(rld[t_reload].secondary_out_icode |
9ec7078b | 436 | == CODE_FOR_nothing))) |
e9a25f70 | 437 | && (reg_class_size[(int) t_class] == 1 || SMALL_REGISTER_CLASSES) |
9ec7078b | 438 | && MERGABLE_RELOADS (secondary_type, |
eceef4c9 BS |
439 | rld[t_reload].when_needed, |
440 | opnum, rld[t_reload].opnum)) | |
9ec7078b RK |
441 | { |
442 | if (in_p) | |
eceef4c9 | 443 | rld[t_reload].inmode = t_mode; |
9ec7078b | 444 | if (! in_p) |
eceef4c9 | 445 | rld[t_reload].outmode = t_mode; |
9ec7078b | 446 | |
eceef4c9 BS |
447 | if (reg_class_subset_p (t_class, rld[t_reload].class)) |
448 | rld[t_reload].class = t_class; | |
9ec7078b | 449 | |
eceef4c9 BS |
450 | rld[t_reload].opnum = MIN (rld[t_reload].opnum, opnum); |
451 | rld[t_reload].optional &= optional; | |
452 | rld[t_reload].secondary_p = 1; | |
453 | if (MERGE_TO_OTHER (secondary_type, rld[t_reload].when_needed, | |
454 | opnum, rld[t_reload].opnum)) | |
455 | rld[t_reload].when_needed = RELOAD_OTHER; | |
9ec7078b RK |
456 | } |
457 | ||
458 | if (t_reload == n_reloads) | |
459 | { | |
460 | /* We need to make a new tertiary reload for this register class. */ | |
eceef4c9 BS |
461 | rld[t_reload].in = rld[t_reload].out = 0; |
462 | rld[t_reload].class = t_class; | |
463 | rld[t_reload].inmode = in_p ? t_mode : VOIDmode; | |
464 | rld[t_reload].outmode = ! in_p ? t_mode : VOIDmode; | |
465 | rld[t_reload].reg_rtx = 0; | |
466 | rld[t_reload].optional = optional; | |
467 | rld[t_reload].nongroup = 0; | |
468 | rld[t_reload].inc = 0; | |
9ec7078b | 469 | /* Maybe we could combine these, but it seems too tricky. */ |
eceef4c9 BS |
470 | rld[t_reload].nocombine = 1; |
471 | rld[t_reload].in_reg = 0; | |
472 | rld[t_reload].out_reg = 0; | |
473 | rld[t_reload].opnum = opnum; | |
474 | rld[t_reload].when_needed = secondary_type; | |
475 | rld[t_reload].secondary_in_reload = -1; | |
476 | rld[t_reload].secondary_out_reload = -1; | |
477 | rld[t_reload].secondary_in_icode = CODE_FOR_nothing; | |
478 | rld[t_reload].secondary_out_icode = CODE_FOR_nothing; | |
479 | rld[t_reload].secondary_p = 1; | |
9ec7078b RK |
480 | |
481 | n_reloads++; | |
482 | } | |
483 | } | |
484 | ||
485 | /* See if we can reuse an existing secondary reload. */ | |
486 | for (s_reload = 0; s_reload < n_reloads; s_reload++) | |
eceef4c9 BS |
487 | if (rld[s_reload].secondary_p |
488 | && (reg_class_subset_p (class, rld[s_reload].class) | |
489 | || reg_class_subset_p (rld[s_reload].class, class)) | |
490 | && ((in_p && rld[s_reload].inmode == mode) | |
491 | || (! in_p && rld[s_reload].outmode == mode)) | |
492 | && ((in_p && rld[s_reload].secondary_in_reload == t_reload) | |
493 | || (! in_p && rld[s_reload].secondary_out_reload == t_reload)) | |
494 | && ((in_p && rld[s_reload].secondary_in_icode == t_icode) | |
495 | || (! in_p && rld[s_reload].secondary_out_icode == t_icode)) | |
e9a25f70 | 496 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
eceef4c9 BS |
497 | && MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed, |
498 | opnum, rld[s_reload].opnum)) | |
9ec7078b RK |
499 | { |
500 | if (in_p) | |
eceef4c9 | 501 | rld[s_reload].inmode = mode; |
9ec7078b | 502 | if (! in_p) |
eceef4c9 | 503 | rld[s_reload].outmode = mode; |
9ec7078b | 504 | |
eceef4c9 BS |
505 | if (reg_class_subset_p (class, rld[s_reload].class)) |
506 | rld[s_reload].class = class; | |
9ec7078b | 507 | |
eceef4c9 BS |
508 | rld[s_reload].opnum = MIN (rld[s_reload].opnum, opnum); |
509 | rld[s_reload].optional &= optional; | |
510 | rld[s_reload].secondary_p = 1; | |
511 | if (MERGE_TO_OTHER (secondary_type, rld[s_reload].when_needed, | |
512 | opnum, rld[s_reload].opnum)) | |
513 | rld[s_reload].when_needed = RELOAD_OTHER; | |
9ec7078b | 514 | } |
eab89b90 | 515 | |
9ec7078b RK |
516 | if (s_reload == n_reloads) |
517 | { | |
e9a25f70 JL |
518 | #ifdef SECONDARY_MEMORY_NEEDED |
519 | /* If we need a memory location to copy between the two reload regs, | |
520 | set it up now. Note that we do the input case before making | |
05d10675 | 521 | the reload and the output case after. This is due to the |
e9a25f70 JL |
522 | way reloads are output. */ |
523 | ||
524 | if (in_p && icode == CODE_FOR_nothing | |
525 | && SECONDARY_MEMORY_NEEDED (class, reload_class, mode)) | |
526 | get_secondary_mem (x, reload_mode, opnum, type); | |
527 | #endif | |
528 | ||
9ec7078b | 529 | /* We need to make a new secondary reload for this register class. */ |
eceef4c9 BS |
530 | rld[s_reload].in = rld[s_reload].out = 0; |
531 | rld[s_reload].class = class; | |
532 | ||
533 | rld[s_reload].inmode = in_p ? mode : VOIDmode; | |
534 | rld[s_reload].outmode = ! in_p ? mode : VOIDmode; | |
535 | rld[s_reload].reg_rtx = 0; | |
536 | rld[s_reload].optional = optional; | |
537 | rld[s_reload].nongroup = 0; | |
538 | rld[s_reload].inc = 0; | |
9ec7078b | 539 | /* Maybe we could combine these, but it seems too tricky. */ |
eceef4c9 BS |
540 | rld[s_reload].nocombine = 1; |
541 | rld[s_reload].in_reg = 0; | |
542 | rld[s_reload].out_reg = 0; | |
543 | rld[s_reload].opnum = opnum; | |
544 | rld[s_reload].when_needed = secondary_type; | |
545 | rld[s_reload].secondary_in_reload = in_p ? t_reload : -1; | |
546 | rld[s_reload].secondary_out_reload = ! in_p ? t_reload : -1; | |
547 | rld[s_reload].secondary_in_icode = in_p ? t_icode : CODE_FOR_nothing; | |
548 | rld[s_reload].secondary_out_icode | |
9ec7078b | 549 | = ! in_p ? t_icode : CODE_FOR_nothing; |
eceef4c9 | 550 | rld[s_reload].secondary_p = 1; |
9ec7078b RK |
551 | |
552 | n_reloads++; | |
553 | ||
554 | #ifdef SECONDARY_MEMORY_NEEDED | |
9ec7078b | 555 | if (! in_p && icode == CODE_FOR_nothing |
f49e4127 JW |
556 | && SECONDARY_MEMORY_NEEDED (reload_class, class, mode)) |
557 | get_secondary_mem (x, mode, opnum, type); | |
9ec7078b RK |
558 | #endif |
559 | } | |
560 | ||
561 | *picode = icode; | |
562 | return s_reload; | |
eab89b90 RK |
563 | } |
564 | #endif /* HAVE_SECONDARY_RELOADS */ | |
565 | \f | |
0dadecf6 RK |
566 | #ifdef SECONDARY_MEMORY_NEEDED |
567 | ||
05d10675 | 568 | /* Return a memory location that will be used to copy X in mode MODE. |
0dadecf6 RK |
569 | If we haven't already made a location for this mode in this insn, |
570 | call find_reloads_address on the location being returned. */ | |
571 | ||
572 | rtx | |
a8c9daeb | 573 | get_secondary_mem (x, mode, opnum, type) |
0dadecf6 RK |
574 | rtx x; |
575 | enum machine_mode mode; | |
a8c9daeb RK |
576 | int opnum; |
577 | enum reload_type type; | |
0dadecf6 RK |
578 | { |
579 | rtx loc; | |
580 | int mem_valid; | |
581 | ||
64609742 RK |
582 | /* By default, if MODE is narrower than a word, widen it to a word. |
583 | This is required because most machines that require these memory | |
584 | locations do not support short load and stores from all registers | |
585 | (e.g., FP registers). */ | |
586 | ||
587 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
588 | mode = SECONDARY_MEMORY_NEEDED_MODE (mode); | |
589 | #else | |
0dadecf6 RK |
590 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD) |
591 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); | |
64609742 | 592 | #endif |
0dadecf6 | 593 | |
77545d45 RK |
594 | /* If we already have made a MEM for this operand in MODE, return it. */ |
595 | if (secondary_memlocs_elim[(int) mode][opnum] != 0) | |
596 | return secondary_memlocs_elim[(int) mode][opnum]; | |
0dadecf6 | 597 | |
05d10675 | 598 | /* If this is the first time we've tried to get a MEM for this mode, |
0dadecf6 RK |
599 | allocate a new one. `something_changed' in reload will get set |
600 | by noticing that the frame size has changed. */ | |
601 | ||
602 | if (secondary_memlocs[(int) mode] == 0) | |
b24a53d5 JW |
603 | { |
604 | #ifdef SECONDARY_MEMORY_NEEDED_RTX | |
605 | secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); | |
606 | #else | |
607 | secondary_memlocs[(int) mode] | |
608 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
609 | #endif | |
610 | } | |
0dadecf6 RK |
611 | |
612 | /* Get a version of the address doing any eliminations needed. If that | |
613 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
614 | ||
1914f5da | 615 | loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); |
0dadecf6 RK |
616 | mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); |
617 | ||
618 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
619 | loc = copy_rtx (loc); | |
620 | ||
621 | /* The only time the call below will do anything is if the stack | |
622 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
a8c9daeb RK |
623 | can just pass a zero. Adjust the type to be the address of the |
624 | corresponding object. If the address was valid, save the eliminated | |
625 | address. If it wasn't valid, we need to make a reload each time, so | |
626 | don't save it. */ | |
0dadecf6 | 627 | |
a8c9daeb RK |
628 | if (! mem_valid) |
629 | { | |
630 | type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
631 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
632 | : RELOAD_OTHER); | |
8d618585 | 633 | |
a8c9daeb | 634 | find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), |
55c22565 | 635 | opnum, type, 0, 0); |
a8c9daeb | 636 | } |
0dadecf6 | 637 | |
77545d45 | 638 | secondary_memlocs_elim[(int) mode][opnum] = loc; |
0dadecf6 RK |
639 | return loc; |
640 | } | |
641 | ||
642 | /* Clear any secondary memory locations we've made. */ | |
643 | ||
644 | void | |
645 | clear_secondary_mem () | |
646 | { | |
4c9a05bc | 647 | bzero ((char *) secondary_memlocs, sizeof secondary_memlocs); |
0dadecf6 RK |
648 | } |
649 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
650 | \f | |
c6716840 RK |
651 | /* Find the largest class for which every register number plus N is valid in |
652 | M1 (if in range). Abort if no such class exists. */ | |
653 | ||
654 | static enum reg_class | |
655 | find_valid_class (m1, n) | |
656 | enum machine_mode m1; | |
657 | int n; | |
658 | { | |
659 | int class; | |
660 | int regno; | |
661 | enum reg_class best_class; | |
662 | int best_size = 0; | |
663 | ||
664 | for (class = 1; class < N_REG_CLASSES; class++) | |
665 | { | |
666 | int bad = 0; | |
667 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER && ! bad; regno++) | |
668 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
669 | && TEST_HARD_REG_BIT (reg_class_contents[class], regno + n) | |
670 | && ! HARD_REGNO_MODE_OK (regno + n, m1)) | |
671 | bad = 1; | |
672 | ||
673 | if (! bad && reg_class_size[class] > best_size) | |
674 | best_class = class, best_size = reg_class_size[class]; | |
675 | } | |
676 | ||
677 | if (best_size == 0) | |
678 | abort (); | |
679 | ||
680 | return best_class; | |
681 | } | |
682 | \f | |
121315ea BS |
683 | /* Return the number of a previously made reload that can be combined with |
684 | a new one, or n_reloads if none of the existing reloads can be used. | |
685 | OUT, CLASS, TYPE and OPNUM are the same arguments as passed to | |
686 | push_reload, they determine the kind of the new reload that we try to | |
687 | combine. P_IN points to the corresponding value of IN, which can be | |
688 | modified by this function. | |
689 | DONT_SHARE is nonzero if we can't share any input-only reload for IN. */ | |
690 | static int | |
691 | find_reusable_reload (p_in, out, class, type, opnum, dont_share) | |
692 | rtx *p_in, out; | |
693 | enum reg_class class; | |
694 | enum reload_type type; | |
695 | int opnum, dont_share; | |
696 | { | |
697 | rtx in = *p_in; | |
698 | int i; | |
699 | /* We can't merge two reloads if the output of either one is | |
700 | earlyclobbered. */ | |
701 | ||
702 | if (earlyclobber_operand_p (out)) | |
703 | return n_reloads; | |
704 | ||
705 | /* We can use an existing reload if the class is right | |
706 | and at least one of IN and OUT is a match | |
707 | and the other is at worst neutral. | |
05d10675 | 708 | (A zero compared against anything is neutral.) |
121315ea BS |
709 | |
710 | If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are | |
711 | for the same thing since that can cause us to need more reload registers | |
712 | than we otherwise would. */ | |
05d10675 | 713 | |
121315ea | 714 | for (i = 0; i < n_reloads; i++) |
eceef4c9 BS |
715 | if ((reg_class_subset_p (class, rld[i].class) |
716 | || reg_class_subset_p (rld[i].class, class)) | |
121315ea | 717 | /* If the existing reload has a register, it must fit our class. */ |
eceef4c9 | 718 | && (rld[i].reg_rtx == 0 |
121315ea | 719 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], |
eceef4c9 BS |
720 | true_regnum (rld[i].reg_rtx))) |
721 | && ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share | |
722 | && (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out))) | |
723 | || (out != 0 && MATCHES (rld[i].out, out) | |
724 | && (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in)))) | |
725 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) | |
121315ea | 726 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
eceef4c9 | 727 | && MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum)) |
121315ea BS |
728 | return i; |
729 | ||
730 | /* Reloading a plain reg for input can match a reload to postincrement | |
731 | that reg, since the postincrement's value is the right value. | |
732 | Likewise, it can match a preincrement reload, since we regard | |
733 | the preincrementation as happening before any ref in this insn | |
734 | to that register. */ | |
735 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
736 | if ((reg_class_subset_p (class, rld[i].class) |
737 | || reg_class_subset_p (rld[i].class, class)) | |
121315ea BS |
738 | /* If the existing reload has a register, it must fit our |
739 | class. */ | |
eceef4c9 | 740 | && (rld[i].reg_rtx == 0 |
121315ea | 741 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], |
eceef4c9 BS |
742 | true_regnum (rld[i].reg_rtx))) |
743 | && out == 0 && rld[i].out == 0 && rld[i].in != 0 | |
121315ea | 744 | && ((GET_CODE (in) == REG |
eceef4c9 BS |
745 | && (GET_CODE (rld[i].in) == POST_INC |
746 | || GET_CODE (rld[i].in) == POST_DEC | |
747 | || GET_CODE (rld[i].in) == PRE_INC | |
748 | || GET_CODE (rld[i].in) == PRE_DEC) | |
749 | && MATCHES (XEXP (rld[i].in, 0), in)) | |
121315ea | 750 | || |
eceef4c9 | 751 | (GET_CODE (rld[i].in) == REG |
121315ea BS |
752 | && (GET_CODE (in) == POST_INC |
753 | || GET_CODE (in) == POST_DEC | |
754 | || GET_CODE (in) == PRE_INC | |
755 | || GET_CODE (in) == PRE_DEC) | |
eceef4c9 BS |
756 | && MATCHES (XEXP (in, 0), rld[i].in))) |
757 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) | |
121315ea | 758 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
eceef4c9 BS |
759 | && MERGABLE_RELOADS (type, rld[i].when_needed, |
760 | opnum, rld[i].opnum)) | |
121315ea BS |
761 | { |
762 | /* Make sure reload_in ultimately has the increment, | |
763 | not the plain register. */ | |
764 | if (GET_CODE (in) == REG) | |
eceef4c9 | 765 | *p_in = rld[i].in; |
121315ea BS |
766 | return i; |
767 | } | |
768 | return n_reloads; | |
769 | } | |
770 | ||
a8c9daeb | 771 | /* Record one reload that needs to be performed. |
eab89b90 RK |
772 | IN is an rtx saying where the data are to be found before this instruction. |
773 | OUT says where they must be stored after the instruction. | |
774 | (IN is zero for data not read, and OUT is zero for data not written.) | |
775 | INLOC and OUTLOC point to the places in the instructions where | |
776 | IN and OUT were found. | |
a8c9daeb RK |
777 | If IN and OUT are both non-zero, it means the same register must be used |
778 | to reload both IN and OUT. | |
779 | ||
eab89b90 RK |
780 | CLASS is a register class required for the reloaded data. |
781 | INMODE is the machine mode that the instruction requires | |
782 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
783 | ||
784 | If IN is zero, then OUT's location and mode should be passed as | |
785 | INLOC and INMODE. | |
786 | ||
787 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
788 | ||
789 | OPTIONAL nonzero means this reload does not need to be performed: | |
790 | it can be discarded if that is more convenient. | |
791 | ||
a8c9daeb RK |
792 | OPNUM and TYPE say what the purpose of this reload is. |
793 | ||
eab89b90 RK |
794 | The return value is the reload-number for this reload. |
795 | ||
796 | If both IN and OUT are nonzero, in some rare cases we might | |
797 | want to make two separate reloads. (Actually we never do this now.) | |
798 | Therefore, the reload-number for OUT is stored in | |
799 | output_reloadnum when we return; the return value applies to IN. | |
800 | Usually (presently always), when IN and OUT are nonzero, | |
801 | the two reload-numbers are equal, but the caller should be careful to | |
802 | distinguish them. */ | |
803 | ||
804 | static int | |
805 | push_reload (in, out, inloc, outloc, class, | |
a8c9daeb | 806 | inmode, outmode, strict_low, optional, opnum, type) |
121315ea | 807 | rtx in, out; |
eab89b90 RK |
808 | rtx *inloc, *outloc; |
809 | enum reg_class class; | |
810 | enum machine_mode inmode, outmode; | |
811 | int strict_low; | |
812 | int optional; | |
a8c9daeb RK |
813 | int opnum; |
814 | enum reload_type type; | |
eab89b90 RK |
815 | { |
816 | register int i; | |
817 | int dont_share = 0; | |
74347d76 | 818 | int dont_remove_subreg = 0; |
eab89b90 | 819 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; |
9ec7078b | 820 | int secondary_in_reload = -1, secondary_out_reload = -1; |
a229128d RK |
821 | enum insn_code secondary_in_icode = CODE_FOR_nothing; |
822 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
a8c9daeb | 823 | |
eab89b90 RK |
824 | /* INMODE and/or OUTMODE could be VOIDmode if no mode |
825 | has been specified for the operand. In that case, | |
826 | use the operand's mode as the mode to reload. */ | |
827 | if (inmode == VOIDmode && in != 0) | |
828 | inmode = GET_MODE (in); | |
829 | if (outmode == VOIDmode && out != 0) | |
830 | outmode = GET_MODE (out); | |
831 | ||
05d10675 | 832 | /* If IN is a pseudo register everywhere-equivalent to a constant, and |
eab89b90 RK |
833 | it is not in a hard register, reload straight from the constant, |
834 | since we want to get rid of such pseudo registers. | |
835 | Often this is done earlier, but not always in find_reloads_address. */ | |
836 | if (in != 0 && GET_CODE (in) == REG) | |
837 | { | |
838 | register int regno = REGNO (in); | |
839 | ||
840 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
841 | && reg_equiv_constant[regno] != 0) | |
842 | in = reg_equiv_constant[regno]; | |
843 | } | |
844 | ||
845 | /* Likewise for OUT. Of course, OUT will never be equivalent to | |
846 | an actual constant, but it might be equivalent to a memory location | |
847 | (in the case of a parameter). */ | |
848 | if (out != 0 && GET_CODE (out) == REG) | |
849 | { | |
850 | register int regno = REGNO (out); | |
851 | ||
852 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
853 | && reg_equiv_constant[regno] != 0) | |
854 | out = reg_equiv_constant[regno]; | |
855 | } | |
856 | ||
857 | /* If we have a read-write operand with an address side-effect, | |
858 | change either IN or OUT so the side-effect happens only once. */ | |
859 | if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out)) | |
860 | { | |
861 | if (GET_CODE (XEXP (in, 0)) == POST_INC | |
862 | || GET_CODE (XEXP (in, 0)) == POST_DEC) | |
38a448ca | 863 | in = gen_rtx_MEM (GET_MODE (in), XEXP (XEXP (in, 0), 0)); |
eab89b90 RK |
864 | if (GET_CODE (XEXP (in, 0)) == PRE_INC |
865 | || GET_CODE (XEXP (in, 0)) == PRE_DEC) | |
38a448ca | 866 | out = gen_rtx_MEM (GET_MODE (out), XEXP (XEXP (out, 0), 0)); |
eab89b90 RK |
867 | } |
868 | ||
a61c98cf | 869 | /* If we are reloading a (SUBREG constant ...), really reload just the |
ca769828 | 870 | inside expression in its own mode. Similarly for (SUBREG (PLUS ...)). |
a61c98cf RK |
871 | If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still |
872 | a pseudo and hence will become a MEM) with M1 wider than M2 and the | |
873 | register is a pseudo, also reload the inside expression. | |
f72ccbe6 | 874 | For machines that extend byte loads, do this for any SUBREG of a pseudo |
486d8509 RK |
875 | where both M1 and M2 are a word or smaller, M1 is wider than M2, and |
876 | M2 is an integral mode that gets extended when loaded. | |
86c31b2d | 877 | Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
eab89b90 RK |
878 | either M1 is not valid for R or M2 is wider than a word but we only |
879 | need one word to store an M2-sized quantity in R. | |
86c31b2d RS |
880 | (However, if OUT is nonzero, we need to reload the reg *and* |
881 | the subreg, so do nothing here, and let following statement handle it.) | |
882 | ||
eab89b90 RK |
883 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; |
884 | we can't handle it here because CONST_INT does not indicate a mode. | |
885 | ||
886 | Similarly, we must reload the inside expression if we have a | |
df62f951 RK |
887 | STRICT_LOW_PART (presumably, in == out in the cas). |
888 | ||
889 | Also reload the inner expression if it does not require a secondary | |
486d8509 RK |
890 | reload but the SUBREG does. |
891 | ||
892 | Finally, reload the inner expression if it is a register that is in | |
893 | the class whose registers cannot be referenced in a different size | |
d030f4b2 RK |
894 | and M1 is not the same size as M2. If SUBREG_WORD is nonzero, we |
895 | cannot reload just the inside since we might end up with the wrong | |
ab87f8c8 JL |
896 | register class. But if it is inside a STRICT_LOW_PART, we have |
897 | no choice, so we hope we do get the right register class there. */ | |
eab89b90 | 898 | |
ab87f8c8 JL |
899 | if (in != 0 && GET_CODE (in) == SUBREG |
900 | && (SUBREG_WORD (in) == 0 || strict_low) | |
94bafba7 RK |
901 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
902 | && class != CLASS_CANNOT_CHANGE_SIZE | |
903 | #endif | |
a61c98cf | 904 | && (CONSTANT_P (SUBREG_REG (in)) |
ca769828 | 905 | || GET_CODE (SUBREG_REG (in)) == PLUS |
eab89b90 | 906 | || strict_low |
a61c98cf RK |
907 | || (((GET_CODE (SUBREG_REG (in)) == REG |
908 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER) | |
909 | || GET_CODE (SUBREG_REG (in)) == MEM) | |
03b72c86 RK |
910 | && ((GET_MODE_SIZE (inmode) |
911 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
09bf0250 | 912 | #ifdef LOAD_EXTEND_OP |
03b72c86 RK |
913 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
914 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
915 | <= UNITS_PER_WORD) | |
916 | && (GET_MODE_SIZE (inmode) | |
486d8509 RK |
917 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) |
918 | && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) | |
919 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != NIL) | |
d2c92f5a R |
920 | #endif |
921 | #ifdef WORD_REGISTER_OPERATIONS | |
922 | || ((GET_MODE_SIZE (inmode) | |
923 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
924 | && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == | |
925 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) | |
926 | / UNITS_PER_WORD))) | |
f72ccbe6 | 927 | #endif |
03b72c86 | 928 | )) |
a61c98cf RK |
929 | || (GET_CODE (SUBREG_REG (in)) == REG |
930 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
86c31b2d RS |
931 | /* The case where out is nonzero |
932 | is handled differently in the following statement. */ | |
933 | && (out == 0 || SUBREG_WORD (in) == 0) | |
f72ccbe6 RK |
934 | && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
935 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
936 | > UNITS_PER_WORD) | |
937 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
938 | / UNITS_PER_WORD) | |
939 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
940 | GET_MODE (SUBREG_REG (in))))) | |
941 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (in)) | |
942 | + SUBREG_WORD (in)), | |
943 | inmode))) | |
df62f951 RK |
944 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
945 | || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS | |
946 | && (SECONDARY_INPUT_RELOAD_CLASS (class, | |
947 | GET_MODE (SUBREG_REG (in)), | |
948 | SUBREG_REG (in)) | |
949 | == NO_REGS)) | |
486d8509 RK |
950 | #endif |
951 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
952 | || (GET_CODE (SUBREG_REG (in)) == REG | |
953 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
954 | && (TEST_HARD_REG_BIT | |
955 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
956 | REGNO (SUBREG_REG (in)))) | |
957 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
958 | != GET_MODE_SIZE (inmode))) | |
df62f951 RK |
959 | #endif |
960 | )) | |
eab89b90 RK |
961 | { |
962 | in_subreg_loc = inloc; | |
963 | inloc = &SUBREG_REG (in); | |
964 | in = *inloc; | |
d2c92f5a | 965 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
eab89b90 RK |
966 | if (GET_CODE (in) == MEM) |
967 | /* This is supposed to happen only for paradoxical subregs made by | |
968 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
969 | if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode)) | |
970 | abort (); | |
e05a9da8 | 971 | #endif |
eab89b90 RK |
972 | inmode = GET_MODE (in); |
973 | } | |
974 | ||
86c31b2d RS |
975 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
976 | either M1 is not valid for R or M2 is wider than a word but we only | |
977 | need one word to store an M2-sized quantity in R. | |
978 | ||
979 | However, we must reload the inner reg *as well as* the subreg in | |
980 | that case. */ | |
981 | ||
6fd5ac08 JW |
982 | /* Similar issue for (SUBREG constant ...) if it was not handled by the |
983 | code above. This can happen if SUBREG_WORD != 0. */ | |
984 | ||
86c31b2d | 985 | if (in != 0 && GET_CODE (in) == SUBREG |
6fd5ac08 JW |
986 | && (CONSTANT_P (SUBREG_REG (in)) |
987 | || (GET_CODE (SUBREG_REG (in)) == REG | |
988 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
989 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)) | |
990 | + SUBREG_WORD (in), | |
991 | inmode) | |
992 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD | |
993 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
994 | > UNITS_PER_WORD) | |
995 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
996 | / UNITS_PER_WORD) | |
997 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
998 | GET_MODE (SUBREG_REG (in))))))))) | |
86c31b2d | 999 | { |
c96d01ab RK |
1000 | /* This relies on the fact that emit_reload_insns outputs the |
1001 | instructions for input reloads of type RELOAD_OTHER in the same | |
1002 | order as the reloads. Thus if the outer reload is also of type | |
1003 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1004 | output before the outer reload. */ | |
86c31b2d | 1005 | push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), NULL_PTR, |
c6716840 RK |
1006 | find_valid_class (inmode, SUBREG_WORD (in)), |
1007 | VOIDmode, VOIDmode, 0, 0, opnum, type); | |
74347d76 | 1008 | dont_remove_subreg = 1; |
86c31b2d RS |
1009 | } |
1010 | ||
eab89b90 RK |
1011 | /* Similarly for paradoxical and problematical SUBREGs on the output. |
1012 | Note that there is no reason we need worry about the previous value | |
1013 | of SUBREG_REG (out); even if wider than out, | |
1014 | storing in a subreg is entitled to clobber it all | |
1015 | (except in the case of STRICT_LOW_PART, | |
1016 | and in that case the constraint should label it input-output.) */ | |
ab87f8c8 JL |
1017 | if (out != 0 && GET_CODE (out) == SUBREG |
1018 | && (SUBREG_WORD (out) == 0 || strict_low) | |
94bafba7 RK |
1019 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
1020 | && class != CLASS_CANNOT_CHANGE_SIZE | |
1021 | #endif | |
a61c98cf | 1022 | && (CONSTANT_P (SUBREG_REG (out)) |
eab89b90 | 1023 | || strict_low |
a61c98cf RK |
1024 | || (((GET_CODE (SUBREG_REG (out)) == REG |
1025 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER) | |
1026 | || GET_CODE (SUBREG_REG (out)) == MEM) | |
03b72c86 | 1027 | && ((GET_MODE_SIZE (outmode) |
1914f5da RH |
1028 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) |
1029 | #ifdef WORD_REGISTER_OPERATIONS | |
6d49a073 JW |
1030 | || ((GET_MODE_SIZE (outmode) |
1031 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
1032 | && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == | |
1033 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) | |
1034 | / UNITS_PER_WORD))) | |
1914f5da | 1035 | #endif |
05d10675 | 1036 | )) |
eab89b90 RK |
1037 | || (GET_CODE (SUBREG_REG (out)) == REG |
1038 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
1039 | && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1040 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1041 | > UNITS_PER_WORD) | |
1042 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1043 | / UNITS_PER_WORD) | |
1044 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
1045 | GET_MODE (SUBREG_REG (out))))) | |
1046 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (out)) | |
1047 | + SUBREG_WORD (out)), | |
1048 | outmode))) | |
df62f951 RK |
1049 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
1050 | || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS | |
1051 | && (SECONDARY_OUTPUT_RELOAD_CLASS (class, | |
1052 | GET_MODE (SUBREG_REG (out)), | |
1053 | SUBREG_REG (out)) | |
1054 | == NO_REGS)) | |
486d8509 RK |
1055 | #endif |
1056 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
1057 | || (GET_CODE (SUBREG_REG (out)) == REG | |
1058 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
1059 | && (TEST_HARD_REG_BIT | |
1060 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
1061 | REGNO (SUBREG_REG (out)))) | |
1062 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1063 | != GET_MODE_SIZE (outmode))) | |
df62f951 RK |
1064 | #endif |
1065 | )) | |
eab89b90 RK |
1066 | { |
1067 | out_subreg_loc = outloc; | |
1068 | outloc = &SUBREG_REG (out); | |
05d10675 | 1069 | out = *outloc; |
d2c92f5a | 1070 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
05d10675 | 1071 | if (GET_CODE (out) == MEM |
eab89b90 RK |
1072 | && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode)) |
1073 | abort (); | |
e05a9da8 | 1074 | #endif |
eab89b90 RK |
1075 | outmode = GET_MODE (out); |
1076 | } | |
1077 | ||
74347d76 RK |
1078 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
1079 | either M1 is not valid for R or M2 is wider than a word but we only | |
1080 | need one word to store an M2-sized quantity in R. | |
1081 | ||
1082 | However, we must reload the inner reg *as well as* the subreg in | |
1083 | that case. In this case, the inner reg is an in-out reload. */ | |
1084 | ||
1085 | if (out != 0 && GET_CODE (out) == SUBREG | |
1086 | && GET_CODE (SUBREG_REG (out)) == REG | |
1087 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
c6716840 RK |
1088 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)) + SUBREG_WORD (out), |
1089 | outmode) | |
74347d76 RK |
1090 | || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1091 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1092 | > UNITS_PER_WORD) | |
1093 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1094 | / UNITS_PER_WORD) | |
1095 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
1096 | GET_MODE (SUBREG_REG (out))))))) | |
1097 | { | |
c96d01ab RK |
1098 | /* This relies on the fact that emit_reload_insns outputs the |
1099 | instructions for output reloads of type RELOAD_OTHER in reverse | |
1100 | order of the reloads. Thus if the outer reload is also of type | |
1101 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1102 | output after the outer reload. */ | |
74347d76 RK |
1103 | dont_remove_subreg = 1; |
1104 | push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out), | |
c6716840 RK |
1105 | &SUBREG_REG (out), |
1106 | find_valid_class (outmode, SUBREG_WORD (out)), | |
1107 | VOIDmode, VOIDmode, 0, 0, | |
74347d76 RK |
1108 | opnum, RELOAD_OTHER); |
1109 | } | |
1110 | ||
eab89b90 RK |
1111 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ |
1112 | if (in != 0 && out != 0 && GET_CODE (out) == MEM | |
1113 | && (GET_CODE (in) == REG || GET_CODE (in) == MEM) | |
bfa30b22 | 1114 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
eab89b90 RK |
1115 | dont_share = 1; |
1116 | ||
0dadecf6 RK |
1117 | /* If IN is a SUBREG of a hard register, make a new REG. This |
1118 | simplifies some of the cases below. */ | |
1119 | ||
1120 | if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG | |
74347d76 RK |
1121 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
1122 | && ! dont_remove_subreg) | |
38a448ca RH |
1123 | in = gen_rtx_REG (GET_MODE (in), |
1124 | REGNO (SUBREG_REG (in)) + SUBREG_WORD (in)); | |
0dadecf6 RK |
1125 | |
1126 | /* Similarly for OUT. */ | |
1127 | if (out != 0 && GET_CODE (out) == SUBREG | |
1128 | && GET_CODE (SUBREG_REG (out)) == REG | |
74347d76 RK |
1129 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
1130 | && ! dont_remove_subreg) | |
38a448ca RH |
1131 | out = gen_rtx_REG (GET_MODE (out), |
1132 | REGNO (SUBREG_REG (out)) + SUBREG_WORD (out)); | |
0dadecf6 | 1133 | |
eab89b90 RK |
1134 | /* Narrow down the class of register wanted if that is |
1135 | desirable on this machine for efficiency. */ | |
1136 | if (in != 0) | |
1137 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1138 | ||
ac2a9454 | 1139 | /* Output reloads may need analogous treatment, different in detail. */ |
18a53b78 RS |
1140 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS |
1141 | if (out != 0) | |
1142 | class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class); | |
1143 | #endif | |
1144 | ||
eab89b90 RK |
1145 | /* Make sure we use a class that can handle the actual pseudo |
1146 | inside any subreg. For example, on the 386, QImode regs | |
1147 | can appear within SImode subregs. Although GENERAL_REGS | |
1148 | can handle SImode, QImode needs a smaller class. */ | |
1149 | #ifdef LIMIT_RELOAD_CLASS | |
1150 | if (in_subreg_loc) | |
1151 | class = LIMIT_RELOAD_CLASS (inmode, class); | |
1152 | else if (in != 0 && GET_CODE (in) == SUBREG) | |
1153 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); | |
1154 | ||
1155 | if (out_subreg_loc) | |
1156 | class = LIMIT_RELOAD_CLASS (outmode, class); | |
1157 | if (out != 0 && GET_CODE (out) == SUBREG) | |
1158 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); | |
1159 | #endif | |
1160 | ||
eab89b90 RK |
1161 | /* Verify that this class is at least possible for the mode that |
1162 | is specified. */ | |
1163 | if (this_insn_is_asm) | |
1164 | { | |
1165 | enum machine_mode mode; | |
1166 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
1167 | mode = inmode; | |
1168 | else | |
1169 | mode = outmode; | |
5488078f RS |
1170 | if (mode == VOIDmode) |
1171 | { | |
1172 | error_for_asm (this_insn, "cannot reload integer constant operand in `asm'"); | |
1173 | mode = word_mode; | |
1174 | if (in != 0) | |
1175 | inmode = word_mode; | |
1176 | if (out != 0) | |
1177 | outmode = word_mode; | |
1178 | } | |
eab89b90 RK |
1179 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1180 | if (HARD_REGNO_MODE_OK (i, mode) | |
1181 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)) | |
1182 | { | |
1183 | int nregs = HARD_REGNO_NREGS (i, mode); | |
1184 | ||
1185 | int j; | |
1186 | for (j = 1; j < nregs; j++) | |
1187 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j)) | |
1188 | break; | |
1189 | if (j == nregs) | |
1190 | break; | |
1191 | } | |
1192 | if (i == FIRST_PSEUDO_REGISTER) | |
1193 | { | |
1194 | error_for_asm (this_insn, "impossible register constraint in `asm'"); | |
1195 | class = ALL_REGS; | |
1196 | } | |
1197 | } | |
1198 | ||
cb2afeb3 R |
1199 | /* Optional output reloads are always OK even if we have no register class, |
1200 | since the function of these reloads is only to have spill_reg_store etc. | |
1201 | set, so that the storing insn can be deleted later. */ | |
1202 | if (class == NO_REGS | |
1203 | && (optional == 0 || type != RELOAD_FOR_OUTPUT)) | |
5488078f RS |
1204 | abort (); |
1205 | ||
121315ea | 1206 | i = find_reusable_reload (&in, out, class, type, opnum, dont_share); |
eab89b90 RK |
1207 | |
1208 | if (i == n_reloads) | |
1209 | { | |
9ec7078b RK |
1210 | /* See if we need a secondary reload register to move between CLASS |
1211 | and IN or CLASS and OUT. Get the icode and push any required reloads | |
1212 | needed for each of them if so. */ | |
eab89b90 RK |
1213 | |
1214 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1215 | if (in != 0) | |
9ec7078b RK |
1216 | secondary_in_reload |
1217 | = push_secondary_reload (1, in, opnum, optional, class, inmode, type, | |
1218 | &secondary_in_icode); | |
eab89b90 RK |
1219 | #endif |
1220 | ||
1221 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
1222 | if (out != 0 && GET_CODE (out) != SCRATCH) | |
9ec7078b RK |
1223 | secondary_out_reload |
1224 | = push_secondary_reload (0, out, opnum, optional, class, outmode, | |
1225 | type, &secondary_out_icode); | |
eab89b90 RK |
1226 | #endif |
1227 | ||
1228 | /* We found no existing reload suitable for re-use. | |
1229 | So add an additional reload. */ | |
1230 | ||
e9a25f70 JL |
1231 | #ifdef SECONDARY_MEMORY_NEEDED |
1232 | /* If a memory location is needed for the copy, make one. */ | |
1233 | if (in != 0 && GET_CODE (in) == REG | |
1234 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1235 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), | |
05d10675 | 1236 | class, inmode)) |
e9a25f70 JL |
1237 | get_secondary_mem (in, inmode, opnum, type); |
1238 | #endif | |
1239 | ||
9ec7078b | 1240 | i = n_reloads; |
eceef4c9 BS |
1241 | rld[i].in = in; |
1242 | rld[i].out = out; | |
1243 | rld[i].class = class; | |
1244 | rld[i].inmode = inmode; | |
1245 | rld[i].outmode = outmode; | |
1246 | rld[i].reg_rtx = 0; | |
1247 | rld[i].optional = optional; | |
1248 | rld[i].nongroup = 0; | |
1249 | rld[i].inc = 0; | |
1250 | rld[i].nocombine = 0; | |
1251 | rld[i].in_reg = inloc ? *inloc : 0; | |
1252 | rld[i].out_reg = outloc ? *outloc : 0; | |
1253 | rld[i].opnum = opnum; | |
1254 | rld[i].when_needed = type; | |
1255 | rld[i].secondary_in_reload = secondary_in_reload; | |
1256 | rld[i].secondary_out_reload = secondary_out_reload; | |
1257 | rld[i].secondary_in_icode = secondary_in_icode; | |
1258 | rld[i].secondary_out_icode = secondary_out_icode; | |
1259 | rld[i].secondary_p = 0; | |
eab89b90 RK |
1260 | |
1261 | n_reloads++; | |
0dadecf6 RK |
1262 | |
1263 | #ifdef SECONDARY_MEMORY_NEEDED | |
0dadecf6 RK |
1264 | if (out != 0 && GET_CODE (out) == REG |
1265 | && REGNO (out) < FIRST_PSEUDO_REGISTER | |
1266 | && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)), | |
1267 | outmode)) | |
a8c9daeb | 1268 | get_secondary_mem (out, outmode, opnum, type); |
0dadecf6 | 1269 | #endif |
eab89b90 RK |
1270 | } |
1271 | else | |
1272 | { | |
1273 | /* We are reusing an existing reload, | |
1274 | but we may have additional information for it. | |
1275 | For example, we may now have both IN and OUT | |
1276 | while the old one may have just one of them. */ | |
1277 | ||
6fd5ac08 JW |
1278 | /* The modes can be different. If they are, we want to reload in |
1279 | the larger mode, so that the value is valid for both modes. */ | |
1280 | if (inmode != VOIDmode | |
eceef4c9 BS |
1281 | && GET_MODE_SIZE (inmode) > GET_MODE_SIZE (rld[i].inmode)) |
1282 | rld[i].inmode = inmode; | |
6fd5ac08 | 1283 | if (outmode != VOIDmode |
eceef4c9 BS |
1284 | && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (rld[i].outmode)) |
1285 | rld[i].outmode = outmode; | |
eab89b90 | 1286 | if (in != 0) |
cb2afeb3 | 1287 | { |
506b3b3a | 1288 | rtx in_reg = inloc ? *inloc : 0; |
cb2afeb3 R |
1289 | /* If we merge reloads for two distinct rtl expressions that |
1290 | are identical in content, there might be duplicate address | |
1291 | reloads. Remove the extra set now, so that if we later find | |
1292 | that we can inherit this reload, we can get rid of the | |
b838974e JL |
1293 | address reloads altogether. |
1294 | ||
1295 | Do not do this if both reloads are optional since the result | |
1296 | would be an optional reload which could potentially leave | |
1297 | unresolved address replacements. | |
1298 | ||
1299 | It is not sufficient to call transfer_replacements since | |
1300 | choose_reload_regs will remove the replacements for address | |
1301 | reloads of inherited reloads which results in the same | |
1302 | problem. */ | |
eceef4c9 BS |
1303 | if (rld[i].in != in && rtx_equal_p (in, rld[i].in) |
1304 | && ! (rld[i].optional && optional)) | |
cb2afeb3 R |
1305 | { |
1306 | /* We must keep the address reload with the lower operand | |
1307 | number alive. */ | |
eceef4c9 | 1308 | if (opnum > rld[i].opnum) |
cb2afeb3 R |
1309 | { |
1310 | remove_address_replacements (in); | |
eceef4c9 BS |
1311 | in = rld[i].in; |
1312 | in_reg = rld[i].in_reg; | |
cb2afeb3 R |
1313 | } |
1314 | else | |
eceef4c9 | 1315 | remove_address_replacements (rld[i].in); |
cb2afeb3 | 1316 | } |
eceef4c9 BS |
1317 | rld[i].in = in; |
1318 | rld[i].in_reg = in_reg; | |
cb2afeb3 | 1319 | } |
eab89b90 | 1320 | if (out != 0) |
cb2afeb3 | 1321 | { |
eceef4c9 BS |
1322 | rld[i].out = out; |
1323 | rld[i].out_reg = outloc ? *outloc : 0; | |
cb2afeb3 | 1324 | } |
eceef4c9 BS |
1325 | if (reg_class_subset_p (class, rld[i].class)) |
1326 | rld[i].class = class; | |
1327 | rld[i].optional &= optional; | |
1328 | if (MERGE_TO_OTHER (type, rld[i].when_needed, | |
1329 | opnum, rld[i].opnum)) | |
1330 | rld[i].when_needed = RELOAD_OTHER; | |
1331 | rld[i].opnum = MIN (rld[i].opnum, opnum); | |
eab89b90 RK |
1332 | } |
1333 | ||
1334 | /* If the ostensible rtx being reload differs from the rtx found | |
1335 | in the location to substitute, this reload is not safe to combine | |
1336 | because we cannot reliably tell whether it appears in the insn. */ | |
1337 | ||
1338 | if (in != 0 && in != *inloc) | |
eceef4c9 | 1339 | rld[i].nocombine = 1; |
eab89b90 RK |
1340 | |
1341 | #if 0 | |
1342 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1343 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1344 | ||
1345 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1346 | it must be for an autoincrement. It doesn't work to store | |
1347 | the incremented value after the insn because that would clobber the CC. | |
1348 | So we must do the increment of the value reloaded from, | |
1349 | increment it, store it back, then decrement again. */ | |
1350 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1351 | { | |
1352 | out = 0; | |
eceef4c9 BS |
1353 | rld[i].out = 0; |
1354 | rld[i].inc = find_inc_amount (PATTERN (this_insn), in); | |
eab89b90 RK |
1355 | /* If we did not find a nonzero amount-to-increment-by, |
1356 | that contradicts the belief that IN is being incremented | |
1357 | in an address in this insn. */ | |
eceef4c9 | 1358 | if (rld[i].inc == 0) |
eab89b90 RK |
1359 | abort (); |
1360 | } | |
1361 | #endif | |
1362 | ||
1363 | /* If we will replace IN and OUT with the reload-reg, | |
1364 | record where they are located so that substitution need | |
1365 | not do a tree walk. */ | |
1366 | ||
1367 | if (replace_reloads) | |
1368 | { | |
1369 | if (inloc != 0) | |
1370 | { | |
1371 | register struct replacement *r = &replacements[n_replacements++]; | |
1372 | r->what = i; | |
1373 | r->subreg_loc = in_subreg_loc; | |
1374 | r->where = inloc; | |
1375 | r->mode = inmode; | |
1376 | } | |
1377 | if (outloc != 0 && outloc != inloc) | |
1378 | { | |
1379 | register struct replacement *r = &replacements[n_replacements++]; | |
1380 | r->what = i; | |
1381 | r->where = outloc; | |
1382 | r->subreg_loc = out_subreg_loc; | |
1383 | r->mode = outmode; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | /* If this reload is just being introduced and it has both | |
1388 | an incoming quantity and an outgoing quantity that are | |
1389 | supposed to be made to match, see if either one of the two | |
1390 | can serve as the place to reload into. | |
1391 | ||
eceef4c9 | 1392 | If one of them is acceptable, set rld[i].reg_rtx |
eab89b90 RK |
1393 | to that one. */ |
1394 | ||
eceef4c9 | 1395 | if (in != 0 && out != 0 && in != out && rld[i].reg_rtx == 0) |
eab89b90 | 1396 | { |
eceef4c9 BS |
1397 | rld[i].reg_rtx = find_dummy_reload (in, out, inloc, outloc, |
1398 | inmode, outmode, | |
1399 | rld[i].class, i, | |
1400 | earlyclobber_operand_p (out)); | |
eab89b90 RK |
1401 | |
1402 | /* If the outgoing register already contains the same value | |
1403 | as the incoming one, we can dispense with loading it. | |
1404 | The easiest way to tell the caller that is to give a phony | |
1405 | value for the incoming operand (same as outgoing one). */ | |
eceef4c9 | 1406 | if (rld[i].reg_rtx == out |
eab89b90 RK |
1407 | && (GET_CODE (in) == REG || CONSTANT_P (in)) |
1408 | && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), | |
1409 | static_reload_reg_p, i, inmode)) | |
eceef4c9 | 1410 | rld[i].in = out; |
eab89b90 RK |
1411 | } |
1412 | ||
1413 | /* If this is an input reload and the operand contains a register that | |
1414 | dies in this insn and is used nowhere else, see if it is the right class | |
1415 | to be used for this reload. Use it if so. (This occurs most commonly | |
1416 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1417 | this if it is also an output reload that mentions the register unless | |
1418 | the output is a SUBREG that clobbers an entire register. | |
1419 | ||
1420 | Note that the operand might be one of the spill regs, if it is a | |
1421 | pseudo reg and we are in a block where spilling has not taken place. | |
1422 | But if there is no spilling in this block, that is OK. | |
1423 | An explicitly used hard reg cannot be a spill reg. */ | |
1424 | ||
eceef4c9 | 1425 | if (rld[i].reg_rtx == 0 && in != 0) |
eab89b90 RK |
1426 | { |
1427 | rtx note; | |
1428 | int regno; | |
1429 | ||
1430 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1431 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1432 | && GET_CODE (XEXP (note, 0)) == REG | |
1433 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER | |
1434 | && reg_mentioned_p (XEXP (note, 0), in) | |
1435 | && ! refers_to_regno_for_reload_p (regno, | |
1436 | (regno | |
1437 | + HARD_REGNO_NREGS (regno, | |
1438 | inmode)), | |
1439 | PATTERN (this_insn), inloc) | |
05b4ec4f RS |
1440 | /* If this is also an output reload, IN cannot be used as |
1441 | the reload register if it is set in this insn unless IN | |
1442 | is also OUT. */ | |
1443 | && (out == 0 || in == out | |
1444 | || ! hard_reg_set_here_p (regno, | |
1445 | (regno | |
1446 | + HARD_REGNO_NREGS (regno, | |
1447 | inmode)), | |
1448 | PATTERN (this_insn))) | |
1449 | /* ??? Why is this code so different from the previous? | |
1450 | Is there any simple coherent way to describe the two together? | |
1451 | What's going on here. */ | |
eab89b90 RK |
1452 | && (in != out |
1453 | || (GET_CODE (in) == SUBREG | |
1454 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1455 | / UNITS_PER_WORD) | |
1456 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1457 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1458 | /* Make sure the operand fits in the reg that dies. */ | |
1459 | && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1460 | && HARD_REGNO_MODE_OK (regno, inmode) | |
1461 | && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1462 | && HARD_REGNO_MODE_OK (regno, outmode) | |
1463 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
1464 | && !fixed_regs[regno]) | |
1465 | { | |
eceef4c9 | 1466 | rld[i].reg_rtx = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
1467 | break; |
1468 | } | |
1469 | } | |
1470 | ||
1471 | if (out) | |
1472 | output_reloadnum = i; | |
1473 | ||
1474 | return i; | |
1475 | } | |
1476 | ||
1477 | /* Record an additional place we must replace a value | |
1478 | for which we have already recorded a reload. | |
1479 | RELOADNUM is the value returned by push_reload | |
1480 | when the reload was recorded. | |
1481 | This is used in insn patterns that use match_dup. */ | |
1482 | ||
1483 | static void | |
1484 | push_replacement (loc, reloadnum, mode) | |
1485 | rtx *loc; | |
1486 | int reloadnum; | |
1487 | enum machine_mode mode; | |
1488 | { | |
1489 | if (replace_reloads) | |
1490 | { | |
1491 | register struct replacement *r = &replacements[n_replacements++]; | |
1492 | r->what = reloadnum; | |
1493 | r->where = loc; | |
1494 | r->subreg_loc = 0; | |
1495 | r->mode = mode; | |
1496 | } | |
1497 | } | |
1498 | \f | |
a8c9daeb RK |
1499 | /* Transfer all replacements that used to be in reload FROM to be in |
1500 | reload TO. */ | |
1501 | ||
1502 | void | |
1503 | transfer_replacements (to, from) | |
1504 | int to, from; | |
1505 | { | |
1506 | int i; | |
1507 | ||
1508 | for (i = 0; i < n_replacements; i++) | |
1509 | if (replacements[i].what == from) | |
1510 | replacements[i].what = to; | |
1511 | } | |
1512 | \f | |
cb2afeb3 R |
1513 | /* IN_RTX is the value loaded by a reload that we now decided to inherit, |
1514 | or a subpart of it. If we have any replacements registered for IN_RTX, | |
1515 | cancel the reloads that were supposed to load them. | |
1516 | Return non-zero if we canceled any reloads. */ | |
1517 | int | |
1518 | remove_address_replacements (in_rtx) | |
1519 | rtx in_rtx; | |
029b38ff R |
1520 | { |
1521 | int i, j; | |
cb2afeb3 R |
1522 | char reload_flags[MAX_RELOADS]; |
1523 | int something_changed = 0; | |
029b38ff | 1524 | |
cb2afeb3 | 1525 | bzero (reload_flags, sizeof reload_flags); |
029b38ff R |
1526 | for (i = 0, j = 0; i < n_replacements; i++) |
1527 | { | |
cb2afeb3 R |
1528 | if (loc_mentioned_in_p (replacements[i].where, in_rtx)) |
1529 | reload_flags[replacements[i].what] |= 1; | |
1530 | else | |
1531 | { | |
1532 | replacements[j++] = replacements[i]; | |
1533 | reload_flags[replacements[i].what] |= 2; | |
1534 | } | |
1535 | } | |
1536 | /* Note that the following store must be done before the recursive calls. */ | |
1537 | n_replacements = j; | |
1538 | ||
1539 | for (i = n_reloads - 1; i >= 0; i--) | |
1540 | { | |
1541 | if (reload_flags[i] == 1) | |
1542 | { | |
1543 | deallocate_reload_reg (i); | |
eceef4c9 BS |
1544 | remove_address_replacements (rld[i].in); |
1545 | rld[i].in = 0; | |
cb2afeb3 R |
1546 | something_changed = 1; |
1547 | } | |
1548 | } | |
1549 | return something_changed; | |
1550 | } | |
1551 | ||
1552 | /* Return non-zero if IN contains a piece of rtl that has the address LOC */ | |
1553 | static int | |
1554 | loc_mentioned_in_p (loc, in) | |
1555 | rtx *loc, in; | |
1556 | { | |
1557 | enum rtx_code code = GET_CODE (in); | |
6f7d635c | 1558 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
1559 | int i, j; |
1560 | ||
1561 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1562 | { | |
ef178af3 | 1563 | if (loc == &in->fld[i].rtx) |
cb2afeb3 R |
1564 | return 1; |
1565 | if (fmt[i] == 'e') | |
05d10675 | 1566 | { |
7655071f GS |
1567 | if (loc_mentioned_in_p (loc, XEXP (in, i))) |
1568 | return 1; | |
05d10675 | 1569 | } |
cb2afeb3 R |
1570 | else if (fmt[i] == 'E') |
1571 | for (j = XVECLEN (in, i) - 1; i >= 0; i--) | |
1572 | if (loc_mentioned_in_p (loc, XVECEXP (in, i, j))) | |
1573 | return 1; | |
029b38ff | 1574 | } |
cb2afeb3 | 1575 | return 0; |
029b38ff R |
1576 | } |
1577 | \f | |
eab89b90 RK |
1578 | /* If there is only one output reload, and it is not for an earlyclobber |
1579 | operand, try to combine it with a (logically unrelated) input reload | |
1580 | to reduce the number of reload registers needed. | |
1581 | ||
1582 | This is safe if the input reload does not appear in | |
1583 | the value being output-reloaded, because this implies | |
1584 | it is not needed any more once the original insn completes. | |
1585 | ||
1586 | If that doesn't work, see we can use any of the registers that | |
1587 | die in this insn as a reload register. We can if it is of the right | |
1588 | class and does not appear in the value being output-reloaded. */ | |
1589 | ||
1590 | static void | |
1591 | combine_reloads () | |
1592 | { | |
1593 | int i; | |
1594 | int output_reload = -1; | |
8922eb5b | 1595 | int secondary_out = -1; |
eab89b90 RK |
1596 | rtx note; |
1597 | ||
1598 | /* Find the output reload; return unless there is exactly one | |
1599 | and that one is mandatory. */ | |
1600 | ||
1601 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 1602 | if (rld[i].out != 0) |
eab89b90 RK |
1603 | { |
1604 | if (output_reload >= 0) | |
1605 | return; | |
1606 | output_reload = i; | |
1607 | } | |
1608 | ||
eceef4c9 | 1609 | if (output_reload < 0 || rld[output_reload].optional) |
eab89b90 RK |
1610 | return; |
1611 | ||
1612 | /* An input-output reload isn't combinable. */ | |
1613 | ||
eceef4c9 | 1614 | if (rld[output_reload].in != 0) |
eab89b90 RK |
1615 | return; |
1616 | ||
6dc42e49 | 1617 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
eceef4c9 | 1618 | if (earlyclobber_operand_p (rld[output_reload].out)) |
4644aad4 | 1619 | return; |
eab89b90 RK |
1620 | |
1621 | /* Check each input reload; can we combine it? */ | |
1622 | ||
1623 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 1624 | if (rld[i].in && ! rld[i].optional && ! rld[i].nocombine |
eab89b90 | 1625 | /* Life span of this reload must not extend past main insn. */ |
eceef4c9 BS |
1626 | && rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
1627 | && rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS | |
1628 | && rld[i].when_needed != RELOAD_OTHER | |
1629 | && (CLASS_MAX_NREGS (rld[i].class, rld[i].inmode) | |
1630 | == CLASS_MAX_NREGS (rld[output_reload].class, | |
1631 | rld[output_reload].outmode)) | |
1632 | && rld[i].inc == 0 | |
1633 | && rld[i].reg_rtx == 0 | |
a8c9daeb | 1634 | #ifdef SECONDARY_MEMORY_NEEDED |
9ec7078b RK |
1635 | /* Don't combine two reloads with different secondary |
1636 | memory locations. */ | |
eceef4c9 BS |
1637 | && (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] == 0 |
1638 | || secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] == 0 | |
1639 | || rtx_equal_p (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum], | |
1640 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum])) | |
a8c9daeb | 1641 | #endif |
e9a25f70 | 1642 | && (SMALL_REGISTER_CLASSES |
eceef4c9 BS |
1643 | ? (rld[i].class == rld[output_reload].class) |
1644 | : (reg_class_subset_p (rld[i].class, | |
1645 | rld[output_reload].class) | |
1646 | || reg_class_subset_p (rld[output_reload].class, | |
1647 | rld[i].class))) | |
1648 | && (MATCHES (rld[i].in, rld[output_reload].out) | |
eab89b90 RK |
1649 | /* Args reversed because the first arg seems to be |
1650 | the one that we imagine being modified | |
1651 | while the second is the one that might be affected. */ | |
eceef4c9 BS |
1652 | || (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out, |
1653 | rld[i].in) | |
eab89b90 RK |
1654 | /* However, if the input is a register that appears inside |
1655 | the output, then we also can't share. | |
1656 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1657 | If the same reload reg is used for both reg 69 and the | |
1658 | result to be stored in memory, then that result | |
1659 | will clobber the address of the memory ref. */ | |
eceef4c9 BS |
1660 | && ! (GET_CODE (rld[i].in) == REG |
1661 | && reg_overlap_mentioned_for_reload_p (rld[i].in, | |
1662 | rld[output_reload].out)))) | |
1663 | && (reg_class_size[(int) rld[i].class] | |
e9a25f70 | 1664 | || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1665 | /* We will allow making things slightly worse by combining an |
1666 | input and an output, but no worse than that. */ | |
eceef4c9 BS |
1667 | && (rld[i].when_needed == RELOAD_FOR_INPUT |
1668 | || rld[i].when_needed == RELOAD_FOR_OUTPUT)) | |
eab89b90 RK |
1669 | { |
1670 | int j; | |
1671 | ||
1672 | /* We have found a reload to combine with! */ | |
eceef4c9 BS |
1673 | rld[i].out = rld[output_reload].out; |
1674 | rld[i].out_reg = rld[output_reload].out_reg; | |
1675 | rld[i].outmode = rld[output_reload].outmode; | |
eab89b90 | 1676 | /* Mark the old output reload as inoperative. */ |
eceef4c9 | 1677 | rld[output_reload].out = 0; |
eab89b90 | 1678 | /* The combined reload is needed for the entire insn. */ |
eceef4c9 | 1679 | rld[i].when_needed = RELOAD_OTHER; |
0f41302f | 1680 | /* If the output reload had a secondary reload, copy it. */ |
eceef4c9 | 1681 | if (rld[output_reload].secondary_out_reload != -1) |
9ec7078b | 1682 | { |
eceef4c9 BS |
1683 | rld[i].secondary_out_reload |
1684 | = rld[output_reload].secondary_out_reload; | |
1685 | rld[i].secondary_out_icode | |
1686 | = rld[output_reload].secondary_out_icode; | |
9ec7078b RK |
1687 | } |
1688 | ||
a8c9daeb RK |
1689 | #ifdef SECONDARY_MEMORY_NEEDED |
1690 | /* Copy any secondary MEM. */ | |
eceef4c9 BS |
1691 | if (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] != 0) |
1692 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] | |
1693 | = secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum]; | |
a8c9daeb | 1694 | #endif |
0f41302f | 1695 | /* If required, minimize the register class. */ |
eceef4c9 BS |
1696 | if (reg_class_subset_p (rld[output_reload].class, |
1697 | rld[i].class)) | |
1698 | rld[i].class = rld[output_reload].class; | |
eab89b90 RK |
1699 | |
1700 | /* Transfer all replacements from the old reload to the combined. */ | |
1701 | for (j = 0; j < n_replacements; j++) | |
1702 | if (replacements[j].what == output_reload) | |
1703 | replacements[j].what = i; | |
1704 | ||
1705 | return; | |
1706 | } | |
1707 | ||
1708 | /* If this insn has only one operand that is modified or written (assumed | |
1709 | to be the first), it must be the one corresponding to this reload. It | |
1710 | is safe to use anything that dies in this insn for that output provided | |
1711 | that it does not occur in the output (we already know it isn't an | |
1712 | earlyclobber. If this is an asm insn, give up. */ | |
1713 | ||
1714 | if (INSN_CODE (this_insn) == -1) | |
1715 | return; | |
1716 | ||
a995e389 RH |
1717 | for (i = 1; i < insn_data[INSN_CODE (this_insn)].n_operands; i++) |
1718 | if (insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '=' | |
1719 | || insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+') | |
eab89b90 RK |
1720 | return; |
1721 | ||
1722 | /* See if some hard register that dies in this insn and is not used in | |
1723 | the output is the right class. Only works if the register we pick | |
1724 | up can fully hold our output reload. */ | |
1725 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1726 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1727 | && GET_CODE (XEXP (note, 0)) == REG | |
bfa30b22 | 1728 | && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
eceef4c9 | 1729 | rld[output_reload].out) |
eab89b90 | 1730 | && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
eceef4c9 BS |
1731 | && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), rld[output_reload].outmode) |
1732 | && TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].class], | |
eab89b90 | 1733 | REGNO (XEXP (note, 0))) |
eceef4c9 | 1734 | && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), rld[output_reload].outmode) |
eab89b90 | 1735 | <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0)))) |
8922eb5b RK |
1736 | /* Ensure that a secondary or tertiary reload for this output |
1737 | won't want this register. */ | |
eceef4c9 | 1738 | && ((secondary_out = rld[output_reload].secondary_out_reload) == -1 |
05d10675 | 1739 | || (! (TEST_HARD_REG_BIT |
eceef4c9 | 1740 | (reg_class_contents[(int) rld[secondary_out].class], |
05d10675 | 1741 | REGNO (XEXP (note, 0)))) |
eceef4c9 | 1742 | && ((secondary_out = rld[secondary_out].secondary_out_reload) == -1 |
8922eb5b | 1743 | || ! (TEST_HARD_REG_BIT |
eceef4c9 | 1744 | (reg_class_contents[(int) rld[secondary_out].class], |
8922eb5b | 1745 | REGNO (XEXP (note, 0))))))) |
eab89b90 RK |
1746 | && ! fixed_regs[REGNO (XEXP (note, 0))]) |
1747 | { | |
eceef4c9 BS |
1748 | rld[output_reload].reg_rtx |
1749 | = gen_rtx_REG (rld[output_reload].outmode, | |
38a448ca | 1750 | REGNO (XEXP (note, 0))); |
eab89b90 RK |
1751 | return; |
1752 | } | |
1753 | } | |
1754 | \f | |
1755 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1756 | See if one of IN and OUT is a register that may be used; | |
1757 | this is desirable since a spill-register won't be needed. | |
1758 | If so, return the register rtx that proves acceptable. | |
1759 | ||
1760 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
1761 | CLASS is the register class required for the reload. | |
1762 | ||
1763 | If FOR_REAL is >= 0, it is the number of the reload, | |
1764 | and in some cases when it can be discovered that OUT doesn't need | |
eceef4c9 | 1765 | to be computed, clear out rld[FOR_REAL].out. |
eab89b90 RK |
1766 | |
1767 | If FOR_REAL is -1, this should not be done, because this call | |
189086f9 RK |
1768 | is just to see if a register can be found, not to find and install it. |
1769 | ||
1770 | EARLYCLOBBER is non-zero if OUT is an earlyclobber operand. This | |
1771 | puts an additional constraint on being able to use IN for OUT since | |
1772 | IN must not appear elsewhere in the insn (it is assumed that IN itself | |
1773 | is safe from the earlyclobber). */ | |
eab89b90 RK |
1774 | |
1775 | static rtx | |
36b50568 | 1776 | find_dummy_reload (real_in, real_out, inloc, outloc, |
189086f9 | 1777 | inmode, outmode, class, for_real, earlyclobber) |
eab89b90 RK |
1778 | rtx real_in, real_out; |
1779 | rtx *inloc, *outloc; | |
36b50568 | 1780 | enum machine_mode inmode, outmode; |
eab89b90 RK |
1781 | enum reg_class class; |
1782 | int for_real; | |
189086f9 | 1783 | int earlyclobber; |
eab89b90 RK |
1784 | { |
1785 | rtx in = real_in; | |
1786 | rtx out = real_out; | |
1787 | int in_offset = 0; | |
1788 | int out_offset = 0; | |
1789 | rtx value = 0; | |
1790 | ||
1791 | /* If operands exceed a word, we can't use either of them | |
1792 | unless they have the same size. */ | |
36b50568 RS |
1793 | if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode) |
1794 | && (GET_MODE_SIZE (outmode) > UNITS_PER_WORD | |
1795 | || GET_MODE_SIZE (inmode) > UNITS_PER_WORD)) | |
eab89b90 RK |
1796 | return 0; |
1797 | ||
1798 | /* Find the inside of any subregs. */ | |
1799 | while (GET_CODE (out) == SUBREG) | |
1800 | { | |
1801 | out_offset = SUBREG_WORD (out); | |
1802 | out = SUBREG_REG (out); | |
1803 | } | |
1804 | while (GET_CODE (in) == SUBREG) | |
1805 | { | |
1806 | in_offset = SUBREG_WORD (in); | |
1807 | in = SUBREG_REG (in); | |
1808 | } | |
1809 | ||
1810 | /* Narrow down the reg class, the same way push_reload will; | |
1811 | otherwise we might find a dummy now, but push_reload won't. */ | |
1812 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1813 | ||
1814 | /* See if OUT will do. */ | |
1815 | if (GET_CODE (out) == REG | |
1816 | && REGNO (out) < FIRST_PSEUDO_REGISTER) | |
1817 | { | |
1818 | register int regno = REGNO (out) + out_offset; | |
36b50568 | 1819 | int nwords = HARD_REGNO_NREGS (regno, outmode); |
d3b9996a | 1820 | rtx saved_rtx; |
eab89b90 RK |
1821 | |
1822 | /* When we consider whether the insn uses OUT, | |
1823 | ignore references within IN. They don't prevent us | |
1824 | from copying IN into OUT, because those refs would | |
1825 | move into the insn that reloads IN. | |
1826 | ||
1827 | However, we only ignore IN in its role as this reload. | |
1828 | If the insn uses IN elsewhere and it contains OUT, | |
1829 | that counts. We can't be sure it's the "same" operand | |
1830 | so it might not go through this reload. */ | |
d3b9996a | 1831 | saved_rtx = *inloc; |
eab89b90 RK |
1832 | *inloc = const0_rtx; |
1833 | ||
1834 | if (regno < FIRST_PSEUDO_REGISTER | |
1835 | /* A fixed reg that can overlap other regs better not be used | |
1836 | for reloading in any way. */ | |
1837 | #ifdef OVERLAPPING_REGNO_P | |
1838 | && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno)) | |
1839 | #endif | |
1840 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1841 | PATTERN (this_insn), outloc)) | |
1842 | { | |
1843 | int i; | |
1844 | for (i = 0; i < nwords; i++) | |
1845 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1846 | regno + i)) | |
1847 | break; | |
1848 | ||
1849 | if (i == nwords) | |
1850 | { | |
1851 | if (GET_CODE (real_out) == REG) | |
1852 | value = real_out; | |
1853 | else | |
38a448ca | 1854 | value = gen_rtx_REG (outmode, regno); |
eab89b90 RK |
1855 | } |
1856 | } | |
1857 | ||
d3b9996a | 1858 | *inloc = saved_rtx; |
eab89b90 RK |
1859 | } |
1860 | ||
1861 | /* Consider using IN if OUT was not acceptable | |
1862 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
1863 | We can't use IN unless it is dies in this insn, | |
1864 | which means we must know accurately which hard regs are live. | |
189086f9 RK |
1865 | Also, the result can't go in IN if IN is used within OUT, |
1866 | or if OUT is an earlyclobber and IN appears elsewhere in the insn. */ | |
eab89b90 RK |
1867 | if (hard_regs_live_known |
1868 | && GET_CODE (in) == REG | |
1869 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1870 | && (value == 0 | |
1871 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
1872 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
1873 | && !fixed_regs[REGNO (in)] | |
36b50568 RS |
1874 | && HARD_REGNO_MODE_OK (REGNO (in), |
1875 | /* The only case where out and real_out might | |
1876 | have different modes is where real_out | |
1877 | is a subreg, and in that case, out | |
1878 | has a real mode. */ | |
1879 | (GET_MODE (out) != VOIDmode | |
1880 | ? GET_MODE (out) : outmode))) | |
eab89b90 RK |
1881 | { |
1882 | register int regno = REGNO (in) + in_offset; | |
36b50568 | 1883 | int nwords = HARD_REGNO_NREGS (regno, inmode); |
eab89b90 | 1884 | |
fb3821f7 | 1885 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR) |
eab89b90 | 1886 | && ! hard_reg_set_here_p (regno, regno + nwords, |
189086f9 RK |
1887 | PATTERN (this_insn)) |
1888 | && (! earlyclobber | |
1889 | || ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1890 | PATTERN (this_insn), inloc))) | |
eab89b90 RK |
1891 | { |
1892 | int i; | |
1893 | for (i = 0; i < nwords; i++) | |
1894 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1895 | regno + i)) | |
1896 | break; | |
1897 | ||
1898 | if (i == nwords) | |
1899 | { | |
1900 | /* If we were going to use OUT as the reload reg | |
1901 | and changed our mind, it means OUT is a dummy that | |
1902 | dies here. So don't bother copying value to it. */ | |
1903 | if (for_real >= 0 && value == real_out) | |
eceef4c9 | 1904 | rld[for_real].out = 0; |
eab89b90 RK |
1905 | if (GET_CODE (real_in) == REG) |
1906 | value = real_in; | |
1907 | else | |
38a448ca | 1908 | value = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
1909 | } |
1910 | } | |
1911 | } | |
1912 | ||
1913 | return value; | |
1914 | } | |
1915 | \f | |
1916 | /* This page contains subroutines used mainly for determining | |
1917 | whether the IN or an OUT of a reload can serve as the | |
1918 | reload register. */ | |
1919 | ||
4644aad4 RK |
1920 | /* Return 1 if X is an operand of an insn that is being earlyclobbered. */ |
1921 | ||
1922 | static int | |
1923 | earlyclobber_operand_p (x) | |
1924 | rtx x; | |
1925 | { | |
1926 | int i; | |
1927 | ||
1928 | for (i = 0; i < n_earlyclobbers; i++) | |
1929 | if (reload_earlyclobbers[i] == x) | |
1930 | return 1; | |
1931 | ||
1932 | return 0; | |
1933 | } | |
1934 | ||
eab89b90 RK |
1935 | /* Return 1 if expression X alters a hard reg in the range |
1936 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
1937 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
1938 | X should be the body of an instruction. */ | |
1939 | ||
1940 | static int | |
1941 | hard_reg_set_here_p (beg_regno, end_regno, x) | |
1942 | register int beg_regno, end_regno; | |
1943 | rtx x; | |
1944 | { | |
1945 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
1946 | { | |
1947 | register rtx op0 = SET_DEST (x); | |
1948 | while (GET_CODE (op0) == SUBREG) | |
1949 | op0 = SUBREG_REG (op0); | |
1950 | if (GET_CODE (op0) == REG) | |
1951 | { | |
1952 | register int r = REGNO (op0); | |
1953 | /* See if this reg overlaps range under consideration. */ | |
1954 | if (r < end_regno | |
1955 | && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno) | |
1956 | return 1; | |
1957 | } | |
1958 | } | |
1959 | else if (GET_CODE (x) == PARALLEL) | |
1960 | { | |
1961 | register int i = XVECLEN (x, 0) - 1; | |
1962 | for (; i >= 0; i--) | |
1963 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
1964 | return 1; | |
1965 | } | |
1966 | ||
1967 | return 0; | |
1968 | } | |
1969 | ||
1970 | /* Return 1 if ADDR is a valid memory address for mode MODE, | |
1971 | and check that each pseudo reg has the proper kind of | |
1972 | hard reg. */ | |
1973 | ||
1974 | int | |
1975 | strict_memory_address_p (mode, addr) | |
1976 | enum machine_mode mode; | |
1977 | register rtx addr; | |
1978 | { | |
1979 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
1980 | return 0; | |
1981 | ||
1982 | win: | |
1983 | return 1; | |
1984 | } | |
eab89b90 RK |
1985 | \f |
1986 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
1987 | if they are the same hard reg, and has special hacks for | |
1988 | autoincrement and autodecrement. | |
1989 | This is specifically intended for find_reloads to use | |
1990 | in determining whether two operands match. | |
1991 | X is the operand whose number is the lower of the two. | |
1992 | ||
1993 | The value is 2 if Y contains a pre-increment that matches | |
1994 | a non-incrementing address in X. */ | |
1995 | ||
1996 | /* ??? To be completely correct, we should arrange to pass | |
1997 | for X the output operand and for Y the input operand. | |
1998 | For now, we assume that the output operand has the lower number | |
1999 | because that is natural in (SET output (... input ...)). */ | |
2000 | ||
2001 | int | |
2002 | operands_match_p (x, y) | |
2003 | register rtx x, y; | |
2004 | { | |
2005 | register int i; | |
2006 | register RTX_CODE code = GET_CODE (x); | |
6f7d635c | 2007 | register const char *fmt; |
eab89b90 | 2008 | int success_2; |
05d10675 | 2009 | |
eab89b90 RK |
2010 | if (x == y) |
2011 | return 1; | |
2012 | if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) | |
2013 | && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG | |
2014 | && GET_CODE (SUBREG_REG (y)) == REG))) | |
2015 | { | |
2016 | register int j; | |
2017 | ||
2018 | if (code == SUBREG) | |
2019 | { | |
2020 | i = REGNO (SUBREG_REG (x)); | |
2021 | if (i >= FIRST_PSEUDO_REGISTER) | |
2022 | goto slow; | |
2023 | i += SUBREG_WORD (x); | |
2024 | } | |
2025 | else | |
2026 | i = REGNO (x); | |
2027 | ||
2028 | if (GET_CODE (y) == SUBREG) | |
2029 | { | |
2030 | j = REGNO (SUBREG_REG (y)); | |
2031 | if (j >= FIRST_PSEUDO_REGISTER) | |
2032 | goto slow; | |
2033 | j += SUBREG_WORD (y); | |
2034 | } | |
2035 | else | |
2036 | j = REGNO (y); | |
2037 | ||
dca52d80 JW |
2038 | /* On a WORDS_BIG_ENDIAN machine, point to the last register of a |
2039 | multiple hard register group, so that for example (reg:DI 0) and | |
2040 | (reg:SI 1) will be considered the same register. */ | |
2041 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD | |
2042 | && i < FIRST_PSEUDO_REGISTER) | |
2043 | i += (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD) - 1; | |
2044 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD | |
2045 | && j < FIRST_PSEUDO_REGISTER) | |
2046 | j += (GET_MODE_SIZE (GET_MODE (y)) / UNITS_PER_WORD) - 1; | |
2047 | ||
eab89b90 RK |
2048 | return i == j; |
2049 | } | |
2050 | /* If two operands must match, because they are really a single | |
2051 | operand of an assembler insn, then two postincrements are invalid | |
2052 | because the assembler insn would increment only once. | |
2053 | On the other hand, an postincrement matches ordinary indexing | |
2054 | if the postincrement is the output operand. */ | |
2055 | if (code == POST_DEC || code == POST_INC) | |
2056 | return operands_match_p (XEXP (x, 0), y); | |
2057 | /* Two preincrements are invalid | |
2058 | because the assembler insn would increment only once. | |
2059 | On the other hand, an preincrement matches ordinary indexing | |
2060 | if the preincrement is the input operand. | |
2061 | In this case, return 2, since some callers need to do special | |
2062 | things when this happens. */ | |
2063 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC) | |
2064 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; | |
2065 | ||
2066 | slow: | |
2067 | ||
05d10675 | 2068 | /* Now we have disposed of all the cases |
eab89b90 RK |
2069 | in which different rtx codes can match. */ |
2070 | if (code != GET_CODE (y)) | |
2071 | return 0; | |
2072 | if (code == LABEL_REF) | |
2073 | return XEXP (x, 0) == XEXP (y, 0); | |
2074 | if (code == SYMBOL_REF) | |
2075 | return XSTR (x, 0) == XSTR (y, 0); | |
2076 | ||
2077 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
2078 | ||
2079 | if (GET_MODE (x) != GET_MODE (y)) | |
2080 | return 0; | |
2081 | ||
2082 | /* Compare the elements. If any pair of corresponding elements | |
2083 | fail to match, return 0 for the whole things. */ | |
2084 | ||
2085 | success_2 = 0; | |
2086 | fmt = GET_RTX_FORMAT (code); | |
2087 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2088 | { | |
91bb873f | 2089 | int val, j; |
eab89b90 RK |
2090 | switch (fmt[i]) |
2091 | { | |
fb3821f7 CH |
2092 | case 'w': |
2093 | if (XWINT (x, i) != XWINT (y, i)) | |
2094 | return 0; | |
2095 | break; | |
2096 | ||
eab89b90 RK |
2097 | case 'i': |
2098 | if (XINT (x, i) != XINT (y, i)) | |
2099 | return 0; | |
2100 | break; | |
2101 | ||
2102 | case 'e': | |
2103 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
2104 | if (val == 0) | |
2105 | return 0; | |
2106 | /* If any subexpression returns 2, | |
2107 | we should return 2 if we are successful. */ | |
2108 | if (val == 2) | |
2109 | success_2 = 1; | |
2110 | break; | |
2111 | ||
2112 | case '0': | |
2113 | break; | |
2114 | ||
91bb873f RH |
2115 | case 'E': |
2116 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
2117 | return 0; | |
2118 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
2119 | { | |
2120 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j)); | |
2121 | if (val == 0) | |
2122 | return 0; | |
2123 | if (val == 2) | |
2124 | success_2 = 1; | |
2125 | } | |
2126 | break; | |
2127 | ||
eab89b90 RK |
2128 | /* It is believed that rtx's at this level will never |
2129 | contain anything but integers and other rtx's, | |
2130 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
2131 | default: | |
2132 | abort (); | |
2133 | } | |
2134 | } | |
2135 | return 1 + success_2; | |
2136 | } | |
2137 | \f | |
eab89b90 | 2138 | /* Describe the range of registers or memory referenced by X. |
05d10675 | 2139 | If X is a register, set REG_FLAG and put the first register |
eab89b90 | 2140 | number into START and the last plus one into END. |
05d10675 | 2141 | If X is a memory reference, put a base address into BASE |
eab89b90 | 2142 | and a range of integer offsets into START and END. |
05d10675 | 2143 | If X is pushing on the stack, we can assume it causes no trouble, |
eab89b90 RK |
2144 | so we set the SAFE field. */ |
2145 | ||
2146 | static struct decomposition | |
2147 | decompose (x) | |
2148 | rtx x; | |
2149 | { | |
2150 | struct decomposition val; | |
2151 | int all_const = 0; | |
2152 | ||
2153 | val.reg_flag = 0; | |
2154 | val.safe = 0; | |
43984e29 | 2155 | val.base = 0; |
eab89b90 RK |
2156 | if (GET_CODE (x) == MEM) |
2157 | { | |
6a651371 | 2158 | rtx base = NULL_RTX, offset = 0; |
eab89b90 RK |
2159 | rtx addr = XEXP (x, 0); |
2160 | ||
2161 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC | |
2162 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
2163 | { | |
2164 | val.base = XEXP (addr, 0); | |
2165 | val.start = - GET_MODE_SIZE (GET_MODE (x)); | |
2166 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
2167 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2168 | return val; | |
2169 | } | |
2170 | ||
2171 | if (GET_CODE (addr) == CONST) | |
2172 | { | |
2173 | addr = XEXP (addr, 0); | |
2174 | all_const = 1; | |
2175 | } | |
2176 | if (GET_CODE (addr) == PLUS) | |
2177 | { | |
2178 | if (CONSTANT_P (XEXP (addr, 0))) | |
2179 | { | |
2180 | base = XEXP (addr, 1); | |
2181 | offset = XEXP (addr, 0); | |
2182 | } | |
2183 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2184 | { | |
2185 | base = XEXP (addr, 0); | |
2186 | offset = XEXP (addr, 1); | |
2187 | } | |
2188 | } | |
2189 | ||
2190 | if (offset == 0) | |
2191 | { | |
2192 | base = addr; | |
2193 | offset = const0_rtx; | |
05d10675 | 2194 | } |
eab89b90 RK |
2195 | if (GET_CODE (offset) == CONST) |
2196 | offset = XEXP (offset, 0); | |
2197 | if (GET_CODE (offset) == PLUS) | |
2198 | { | |
2199 | if (GET_CODE (XEXP (offset, 0)) == CONST_INT) | |
2200 | { | |
38a448ca | 2201 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1)); |
eab89b90 RK |
2202 | offset = XEXP (offset, 0); |
2203 | } | |
2204 | else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) | |
2205 | { | |
38a448ca | 2206 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0)); |
eab89b90 RK |
2207 | offset = XEXP (offset, 1); |
2208 | } | |
2209 | else | |
2210 | { | |
38a448ca | 2211 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); |
eab89b90 RK |
2212 | offset = const0_rtx; |
2213 | } | |
2214 | } | |
2215 | else if (GET_CODE (offset) != CONST_INT) | |
2216 | { | |
38a448ca | 2217 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); |
eab89b90 RK |
2218 | offset = const0_rtx; |
2219 | } | |
2220 | ||
2221 | if (all_const && GET_CODE (base) == PLUS) | |
38a448ca | 2222 | base = gen_rtx_CONST (GET_MODE (base), base); |
eab89b90 RK |
2223 | |
2224 | if (GET_CODE (offset) != CONST_INT) | |
2225 | abort (); | |
2226 | ||
2227 | val.start = INTVAL (offset); | |
2228 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
2229 | val.base = base; | |
2230 | return val; | |
2231 | } | |
2232 | else if (GET_CODE (x) == REG) | |
2233 | { | |
2234 | val.reg_flag = 1; | |
05d10675 | 2235 | val.start = true_regnum (x); |
eab89b90 RK |
2236 | if (val.start < 0) |
2237 | { | |
2238 | /* A pseudo with no hard reg. */ | |
2239 | val.start = REGNO (x); | |
2240 | val.end = val.start + 1; | |
2241 | } | |
2242 | else | |
2243 | /* A hard reg. */ | |
2244 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2245 | } | |
2246 | else if (GET_CODE (x) == SUBREG) | |
2247 | { | |
2248 | if (GET_CODE (SUBREG_REG (x)) != REG) | |
2249 | /* This could be more precise, but it's good enough. */ | |
2250 | return decompose (SUBREG_REG (x)); | |
2251 | val.reg_flag = 1; | |
05d10675 | 2252 | val.start = true_regnum (x); |
eab89b90 RK |
2253 | if (val.start < 0) |
2254 | return decompose (SUBREG_REG (x)); | |
2255 | else | |
2256 | /* A hard reg. */ | |
2257 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2258 | } | |
2259 | else if (CONSTANT_P (x) | |
2260 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
2261 | || GET_CODE (x) == SCRATCH) | |
2262 | val.safe = 1; | |
2263 | else | |
2264 | abort (); | |
2265 | return val; | |
2266 | } | |
2267 | ||
2268 | /* Return 1 if altering Y will not modify the value of X. | |
2269 | Y is also described by YDATA, which should be decompose (Y). */ | |
2270 | ||
2271 | static int | |
2272 | immune_p (x, y, ydata) | |
2273 | rtx x, y; | |
2274 | struct decomposition ydata; | |
2275 | { | |
2276 | struct decomposition xdata; | |
2277 | ||
2278 | if (ydata.reg_flag) | |
fb3821f7 | 2279 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR); |
eab89b90 RK |
2280 | if (ydata.safe) |
2281 | return 1; | |
2282 | ||
2283 | if (GET_CODE (y) != MEM) | |
2284 | abort (); | |
2285 | /* If Y is memory and X is not, Y can't affect X. */ | |
2286 | if (GET_CODE (x) != MEM) | |
2287 | return 1; | |
2288 | ||
2289 | xdata = decompose (x); | |
2290 | ||
2291 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
2292 | { | |
2293 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
2294 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
2295 | return 1; | |
2296 | /* Constants and stack slots never overlap. */ | |
2297 | if (CONSTANT_P (xdata.base) | |
2298 | && (ydata.base == frame_pointer_rtx | |
a36d4c62 | 2299 | || ydata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2300 | || ydata.base == stack_pointer_rtx)) |
2301 | return 1; | |
2302 | if (CONSTANT_P (ydata.base) | |
2303 | && (xdata.base == frame_pointer_rtx | |
a36d4c62 | 2304 | || xdata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2305 | || xdata.base == stack_pointer_rtx)) |
2306 | return 1; | |
2307 | /* If either base is variable, we don't know anything. */ | |
2308 | return 0; | |
2309 | } | |
2310 | ||
2311 | ||
2312 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); | |
2313 | } | |
44ace968 | 2314 | |
f72aed24 | 2315 | /* Similar, but calls decompose. */ |
44ace968 JW |
2316 | |
2317 | int | |
2318 | safe_from_earlyclobber (op, clobber) | |
2319 | rtx op, clobber; | |
2320 | { | |
2321 | struct decomposition early_data; | |
2322 | ||
2323 | early_data = decompose (clobber); | |
2324 | return immune_p (op, clobber, early_data); | |
2325 | } | |
eab89b90 RK |
2326 | \f |
2327 | /* Main entry point of this file: search the body of INSN | |
2328 | for values that need reloading and record them with push_reload. | |
2329 | REPLACE nonzero means record also where the values occur | |
2330 | so that subst_reloads can be used. | |
2331 | ||
2332 | IND_LEVELS says how many levels of indirection are supported by this | |
2333 | machine; a value of zero means that a memory reference is not a valid | |
2334 | memory address. | |
2335 | ||
2336 | LIVE_KNOWN says we have valid information about which hard | |
2337 | regs are live at each point in the program; this is true when | |
2338 | we are called from global_alloc but false when stupid register | |
2339 | allocation has been done. | |
2340 | ||
2341 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
2342 | which is nonnegative if the reg has been commandeered for reloading into. | |
2343 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
cb2afeb3 | 2344 | by various subroutines. |
eab89b90 | 2345 | |
cb2afeb3 R |
2346 | Return TRUE if some operands need to be changed, because of swapping |
2347 | commutative operands, reg_equiv_address substitution, or whatever. */ | |
2348 | ||
2349 | int | |
eab89b90 RK |
2350 | find_reloads (insn, replace, ind_levels, live_known, reload_reg_p) |
2351 | rtx insn; | |
2352 | int replace, ind_levels; | |
2353 | int live_known; | |
2354 | short *reload_reg_p; | |
2355 | { | |
eab89b90 RK |
2356 | #ifdef REGISTER_CONSTRAINTS |
2357 | ||
eab89b90 | 2358 | register int insn_code_number; |
a8c9daeb | 2359 | register int i, j; |
eab89b90 | 2360 | int noperands; |
eab89b90 RK |
2361 | /* These start out as the constraints for the insn |
2362 | and they are chewed up as we consider alternatives. */ | |
2363 | char *constraints[MAX_RECOG_OPERANDS]; | |
2364 | /* These are the preferred classes for an operand, or NO_REGS if it isn't | |
2365 | a register. */ | |
2366 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
2367 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
2368 | /* Nonzero for a MEM operand whose entire address needs a reload. */ | |
2369 | int address_reloaded[MAX_RECOG_OPERANDS]; | |
a8c9daeb RK |
2370 | /* Value of enum reload_type to use for operand. */ |
2371 | enum reload_type operand_type[MAX_RECOG_OPERANDS]; | |
2372 | /* Value of enum reload_type to use within address of operand. */ | |
2373 | enum reload_type address_type[MAX_RECOG_OPERANDS]; | |
2374 | /* Save the usage of each operand. */ | |
2375 | enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; | |
eab89b90 RK |
2376 | int no_input_reloads = 0, no_output_reloads = 0; |
2377 | int n_alternatives; | |
2378 | int this_alternative[MAX_RECOG_OPERANDS]; | |
2379 | char this_alternative_win[MAX_RECOG_OPERANDS]; | |
2380 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2381 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2382 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
2383 | int swapped; | |
2384 | int goal_alternative[MAX_RECOG_OPERANDS]; | |
2385 | int this_alternative_number; | |
2386 | int goal_alternative_number; | |
2387 | int operand_reloadnum[MAX_RECOG_OPERANDS]; | |
2388 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
2389 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
2390 | char goal_alternative_win[MAX_RECOG_OPERANDS]; | |
2391 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2392 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2393 | int goal_alternative_swapped; | |
eab89b90 RK |
2394 | int best; |
2395 | int commutative; | |
f5963e61 | 2396 | int changed; |
eab89b90 RK |
2397 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; |
2398 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2399 | rtx body = PATTERN (insn); | |
2400 | rtx set = single_set (insn); | |
2401 | int goal_earlyclobber, this_earlyclobber; | |
2402 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | |
cb2afeb3 | 2403 | int retval = 0; |
eab89b90 RK |
2404 | |
2405 | this_insn = insn; | |
eab89b90 RK |
2406 | n_reloads = 0; |
2407 | n_replacements = 0; | |
eab89b90 RK |
2408 | n_earlyclobbers = 0; |
2409 | replace_reloads = replace; | |
2410 | hard_regs_live_known = live_known; | |
2411 | static_reload_reg_p = reload_reg_p; | |
2412 | ||
2413 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
2414 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
2415 | to have any input reloads. */ | |
2416 | if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) | |
2417 | no_output_reloads = 1; | |
2418 | ||
2419 | #ifdef HAVE_cc0 | |
2420 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
2421 | no_input_reloads = 1; | |
2422 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
2423 | no_output_reloads = 1; | |
2424 | #endif | |
05d10675 | 2425 | |
0dadecf6 RK |
2426 | #ifdef SECONDARY_MEMORY_NEEDED |
2427 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
2428 | clear them out here. */ | |
2429 | ||
4c9a05bc | 2430 | bzero ((char *) secondary_memlocs_elim, sizeof secondary_memlocs_elim); |
0dadecf6 RK |
2431 | #endif |
2432 | ||
0a578fee BS |
2433 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it |
2434 | is cheap to move between them. If it is not, there may not be an insn | |
2435 | to do the copy, so we may need a reload. */ | |
2436 | if (GET_CODE (body) == SET | |
2437 | && GET_CODE (SET_DEST (body)) == REG | |
2438 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER | |
2439 | && GET_CODE (SET_SRC (body)) == REG | |
2440 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER | |
2441 | && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))), | |
2442 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) | |
2443 | return 0; | |
eab89b90 | 2444 | |
0a578fee | 2445 | extract_insn (insn); |
eab89b90 | 2446 | |
1ccbefce RH |
2447 | noperands = reload_n_operands = recog_data.n_operands; |
2448 | n_alternatives = recog_data.n_alternatives; | |
eab89b90 | 2449 | |
0a578fee BS |
2450 | /* Just return "no reloads" if insn has no operands with constraints. */ |
2451 | if (noperands == 0 || n_alternatives == 0) | |
2452 | return 0; | |
eab89b90 | 2453 | |
0a578fee BS |
2454 | insn_code_number = INSN_CODE (insn); |
2455 | this_insn_is_asm = insn_code_number < 0; | |
eab89b90 | 2456 | |
1ccbefce | 2457 | bcopy ((char *) recog_data.operand_mode, (char *) operand_mode, |
0a578fee | 2458 | noperands * sizeof (enum machine_mode)); |
1ccbefce | 2459 | bcopy ((char *) recog_data.constraints, (char *) constraints, |
0a578fee | 2460 | noperands * sizeof (char *)); |
eab89b90 RK |
2461 | |
2462 | commutative = -1; | |
2463 | ||
2464 | /* If we will need to know, later, whether some pair of operands | |
2465 | are the same, we must compare them now and save the result. | |
2466 | Reloading the base and index registers will clobber them | |
2467 | and afterward they will fail to match. */ | |
2468 | ||
2469 | for (i = 0; i < noperands; i++) | |
2470 | { | |
2471 | register char *p; | |
2472 | register int c; | |
2473 | ||
1ccbefce | 2474 | substed_operand[i] = recog_data.operand[i]; |
eab89b90 RK |
2475 | p = constraints[i]; |
2476 | ||
a8c9daeb RK |
2477 | modified[i] = RELOAD_READ; |
2478 | ||
05d10675 | 2479 | /* Scan this operand's constraint to see if it is an output operand, |
a8c9daeb | 2480 | an in-out operand, is commutative, or should match another. */ |
eab89b90 | 2481 | |
51723711 | 2482 | while ((c = *p++)) |
a8c9daeb RK |
2483 | { |
2484 | if (c == '=') | |
2485 | modified[i] = RELOAD_WRITE; | |
2486 | else if (c == '+') | |
2487 | modified[i] = RELOAD_READ_WRITE; | |
2488 | else if (c == '%') | |
2489 | { | |
2490 | /* The last operand should not be marked commutative. */ | |
2491 | if (i == noperands - 1) | |
2a230e9d BS |
2492 | abort (); |
2493 | ||
2494 | commutative = i; | |
a8c9daeb RK |
2495 | } |
2496 | else if (c >= '0' && c <= '9') | |
2497 | { | |
2498 | c -= '0'; | |
2499 | operands_match[c][i] | |
1ccbefce RH |
2500 | = operands_match_p (recog_data.operand[c], |
2501 | recog_data.operand[i]); | |
ea9c5b9e | 2502 | |
a8c9daeb RK |
2503 | /* An operand may not match itself. */ |
2504 | if (c == i) | |
2a230e9d | 2505 | abort (); |
ea9c5b9e | 2506 | |
a8c9daeb RK |
2507 | /* If C can be commuted with C+1, and C might need to match I, |
2508 | then C+1 might also need to match I. */ | |
2509 | if (commutative >= 0) | |
2510 | { | |
2511 | if (c == commutative || c == commutative + 1) | |
2512 | { | |
2513 | int other = c + (c == commutative ? 1 : -1); | |
2514 | operands_match[other][i] | |
1ccbefce RH |
2515 | = operands_match_p (recog_data.operand[other], |
2516 | recog_data.operand[i]); | |
a8c9daeb RK |
2517 | } |
2518 | if (i == commutative || i == commutative + 1) | |
2519 | { | |
2520 | int other = i + (i == commutative ? 1 : -1); | |
2521 | operands_match[c][other] | |
1ccbefce RH |
2522 | = operands_match_p (recog_data.operand[c], |
2523 | recog_data.operand[other]); | |
a8c9daeb RK |
2524 | } |
2525 | /* Note that C is supposed to be less than I. | |
2526 | No need to consider altering both C and I because in | |
2527 | that case we would alter one into the other. */ | |
2528 | } | |
2529 | } | |
2530 | } | |
eab89b90 RK |
2531 | } |
2532 | ||
2533 | /* Examine each operand that is a memory reference or memory address | |
2534 | and reload parts of the addresses into index registers. | |
eab89b90 RK |
2535 | Also here any references to pseudo regs that didn't get hard regs |
2536 | but are equivalent to constants get replaced in the insn itself | |
05d10675 | 2537 | with those constants. Nobody will ever see them again. |
eab89b90 RK |
2538 | |
2539 | Finally, set up the preferred classes of each operand. */ | |
2540 | ||
2541 | for (i = 0; i < noperands; i++) | |
2542 | { | |
1ccbefce | 2543 | register RTX_CODE code = GET_CODE (recog_data.operand[i]); |
a8c9daeb | 2544 | |
eab89b90 | 2545 | address_reloaded[i] = 0; |
a8c9daeb RK |
2546 | operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT |
2547 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT | |
2548 | : RELOAD_OTHER); | |
2549 | address_type[i] | |
2550 | = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS | |
2551 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS | |
2552 | : RELOAD_OTHER); | |
eab89b90 | 2553 | |
0d38001f RS |
2554 | if (*constraints[i] == 0) |
2555 | /* Ignore things like match_operator operands. */ | |
2556 | ; | |
2557 | else if (constraints[i][0] == 'p') | |
eab89b90 | 2558 | { |
fb3821f7 | 2559 | find_reloads_address (VOIDmode, NULL_PTR, |
1ccbefce RH |
2560 | recog_data.operand[i], |
2561 | recog_data.operand_loc[i], | |
55c22565 | 2562 | i, operand_type[i], ind_levels, insn); |
b685dbae | 2563 | |
05d10675 | 2564 | /* If we now have a simple operand where we used to have a |
b685dbae | 2565 | PLUS or MULT, re-recognize and try again. */ |
1ccbefce RH |
2566 | if ((GET_RTX_CLASS (GET_CODE (*recog_data.operand_loc[i])) == 'o' |
2567 | || GET_CODE (*recog_data.operand_loc[i]) == SUBREG) | |
2568 | && (GET_CODE (recog_data.operand[i]) == MULT | |
2569 | || GET_CODE (recog_data.operand[i]) == PLUS)) | |
b685dbae RK |
2570 | { |
2571 | INSN_CODE (insn) = -1; | |
cb2afeb3 R |
2572 | retval = find_reloads (insn, replace, ind_levels, live_known, |
2573 | reload_reg_p); | |
2574 | return retval; | |
b685dbae RK |
2575 | } |
2576 | ||
1ccbefce RH |
2577 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2578 | substed_operand[i] = recog_data.operand[i]; | |
eab89b90 RK |
2579 | } |
2580 | else if (code == MEM) | |
2581 | { | |
ab87f8c8 | 2582 | address_reloaded[i] |
1ccbefce RH |
2583 | = find_reloads_address (GET_MODE (recog_data.operand[i]), |
2584 | recog_data.operand_loc[i], | |
2585 | XEXP (recog_data.operand[i], 0), | |
2586 | &XEXP (recog_data.operand[i], 0), | |
ab87f8c8 | 2587 | i, address_type[i], ind_levels, insn); |
1ccbefce RH |
2588 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2589 | substed_operand[i] = recog_data.operand[i]; | |
eab89b90 RK |
2590 | } |
2591 | else if (code == SUBREG) | |
b60a8416 | 2592 | { |
1ccbefce | 2593 | rtx reg = SUBREG_REG (recog_data.operand[i]); |
b60a8416 | 2594 | rtx op |
1ccbefce | 2595 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], |
b60a8416 R |
2596 | ind_levels, |
2597 | set != 0 | |
1ccbefce | 2598 | && &SET_DEST (set) == recog_data.operand_loc[i], |
cb2afeb3 | 2599 | insn); |
b60a8416 R |
2600 | |
2601 | /* If we made a MEM to load (a part of) the stackslot of a pseudo | |
2602 | that didn't get a hard register, emit a USE with a REG_EQUAL | |
2603 | note in front so that we might inherit a previous, possibly | |
2604 | wider reload. */ | |
05d10675 | 2605 | |
cb2afeb3 R |
2606 | if (replace |
2607 | && GET_CODE (op) == MEM | |
b60a8416 R |
2608 | && GET_CODE (reg) == REG |
2609 | && (GET_MODE_SIZE (GET_MODE (reg)) | |
2610 | >= GET_MODE_SIZE (GET_MODE (op)))) | |
05d10675 BS |
2611 | REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, reg), insn)) |
2612 | = gen_rtx_EXPR_LIST (REG_EQUAL, | |
b60a8416 R |
2613 | reg_equiv_memory_loc[REGNO (reg)], NULL_RTX); |
2614 | ||
1ccbefce | 2615 | substed_operand[i] = recog_data.operand[i] = op; |
b60a8416 | 2616 | } |
ff428c90 ILT |
2617 | else if (code == PLUS || GET_RTX_CLASS (code) == '1') |
2618 | /* We can get a PLUS as an "operand" as a result of register | |
2619 | elimination. See eliminate_regs and gen_reload. We handle | |
2620 | a unary operator by reloading the operand. */ | |
1ccbefce RH |
2621 | substed_operand[i] = recog_data.operand[i] |
2622 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
cb2afeb3 | 2623 | ind_levels, 0, insn); |
eab89b90 RK |
2624 | else if (code == REG) |
2625 | { | |
2626 | /* This is equivalent to calling find_reloads_toplev. | |
2627 | The code is duplicated for speed. | |
2628 | When we find a pseudo always equivalent to a constant, | |
2629 | we replace it by the constant. We must be sure, however, | |
2630 | that we don't try to replace it in the insn in which it | |
2631 | is being set. */ | |
1ccbefce | 2632 | register int regno = REGNO (recog_data.operand[i]); |
eab89b90 | 2633 | if (reg_equiv_constant[regno] != 0 |
1ccbefce | 2634 | && (set == 0 || &SET_DEST (set) != recog_data.operand_loc[i])) |
726e2d54 JW |
2635 | { |
2636 | /* Record the existing mode so that the check if constants are | |
eceef4c9 | 2637 | allowed will work when operand_mode isn't specified. */ |
726e2d54 JW |
2638 | |
2639 | if (operand_mode[i] == VOIDmode) | |
1ccbefce | 2640 | operand_mode[i] = GET_MODE (recog_data.operand[i]); |
726e2d54 | 2641 | |
1ccbefce | 2642 | substed_operand[i] = recog_data.operand[i] |
05d10675 | 2643 | = reg_equiv_constant[regno]; |
726e2d54 | 2644 | } |
cb2afeb3 R |
2645 | if (reg_equiv_memory_loc[regno] != 0 |
2646 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
2647 | /* We need not give a valid is_set_dest argument since the case | |
2648 | of a constant equivalence was checked above. */ | |
1ccbefce RH |
2649 | substed_operand[i] = recog_data.operand[i] |
2650 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
cb2afeb3 | 2651 | ind_levels, 0, insn); |
eab89b90 | 2652 | } |
aaf9712e RS |
2653 | /* If the operand is still a register (we didn't replace it with an |
2654 | equivalent), get the preferred class to reload it into. */ | |
1ccbefce | 2655 | code = GET_CODE (recog_data.operand[i]); |
aaf9712e | 2656 | preferred_class[i] |
1ccbefce RH |
2657 | = ((code == REG && REGNO (recog_data.operand[i]) |
2658 | >= FIRST_PSEUDO_REGISTER) | |
2659 | ? reg_preferred_class (REGNO (recog_data.operand[i])) | |
2660 | : NO_REGS); | |
aaf9712e | 2661 | pref_or_nothing[i] |
1ccbefce RH |
2662 | = (code == REG |
2663 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER | |
2664 | && reg_alternate_class (REGNO (recog_data.operand[i])) == NO_REGS); | |
eab89b90 RK |
2665 | } |
2666 | ||
ab87f8c8 JL |
2667 | #ifdef HAVE_cc0 |
2668 | /* If we made any reloads for addresses, see if they violate a | |
2669 | "no input reloads" requirement for this insn. */ | |
2670 | if (no_input_reloads) | |
2671 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 2672 | if (rld[i].in != 0) |
ab87f8c8 JL |
2673 | abort (); |
2674 | #endif | |
2675 | ||
eab89b90 RK |
2676 | /* If this is simply a copy from operand 1 to operand 0, merge the |
2677 | preferred classes for the operands. */ | |
1ccbefce RH |
2678 | if (set != 0 && noperands >= 2 && recog_data.operand[0] == SET_DEST (set) |
2679 | && recog_data.operand[1] == SET_SRC (set)) | |
eab89b90 RK |
2680 | { |
2681 | preferred_class[0] = preferred_class[1] | |
2682 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2683 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2684 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2685 | } | |
2686 | ||
2687 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2688 | or got the wrong kind of hard reg. For this, we must consider | |
2689 | all the operands together against the register constraints. */ | |
2690 | ||
812f2051 | 2691 | best = MAX_RECOG_OPERANDS * 2 + 600; |
eab89b90 RK |
2692 | |
2693 | swapped = 0; | |
2694 | goal_alternative_swapped = 0; | |
2695 | try_swapped: | |
2696 | ||
2697 | /* The constraints are made of several alternatives. | |
2698 | Each operand's constraint looks like foo,bar,... with commas | |
2699 | separating the alternatives. The first alternatives for all | |
2700 | operands go together, the second alternatives go together, etc. | |
2701 | ||
2702 | First loop over alternatives. */ | |
2703 | ||
2704 | for (this_alternative_number = 0; | |
2705 | this_alternative_number < n_alternatives; | |
2706 | this_alternative_number++) | |
2707 | { | |
2708 | /* Loop over operands for one constraint alternative. */ | |
2709 | /* LOSERS counts those that don't fit this alternative | |
2710 | and would require loading. */ | |
2711 | int losers = 0; | |
2712 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2713 | even after reloading. */ | |
2714 | int bad = 0; | |
2715 | /* REJECT is a count of how undesirable this alternative says it is | |
2716 | if any reloading is required. If the alternative matches exactly | |
2717 | then REJECT is ignored, but otherwise it gets this much | |
05d10675 | 2718 | counted against it in addition to the reloading needed. Each |
eab89b90 RK |
2719 | ? counts three times here since we want the disparaging caused by |
2720 | a bad register class to only count 1/3 as much. */ | |
2721 | int reject = 0; | |
2722 | ||
2723 | this_earlyclobber = 0; | |
2724 | ||
2725 | for (i = 0; i < noperands; i++) | |
2726 | { | |
2727 | register char *p = constraints[i]; | |
2728 | register int win = 0; | |
2729 | /* 0 => this operand can be reloaded somehow for this alternative */ | |
2730 | int badop = 1; | |
2731 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2732 | int winreg = 0; | |
2733 | int c; | |
1ccbefce | 2734 | register rtx operand = recog_data.operand[i]; |
eab89b90 RK |
2735 | int offset = 0; |
2736 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2737 | regardless of what the constraint says. */ | |
2738 | int force_reload = 0; | |
2739 | int offmemok = 0; | |
9d926da5 RK |
2740 | /* Nonzero if a constant forced into memory would be OK for this |
2741 | operand. */ | |
2742 | int constmemok = 0; | |
eab89b90 RK |
2743 | int earlyclobber = 0; |
2744 | ||
ff428c90 | 2745 | /* If the predicate accepts a unary operator, it means that |
05d10675 | 2746 | we need to reload the operand, but do not do this for |
ad729076 JL |
2747 | match_operator and friends. */ |
2748 | if (GET_RTX_CLASS (GET_CODE (operand)) == '1' && *p != 0) | |
ff428c90 ILT |
2749 | operand = XEXP (operand, 0); |
2750 | ||
eab89b90 RK |
2751 | /* If the operand is a SUBREG, extract |
2752 | the REG or MEM (or maybe even a constant) within. | |
2753 | (Constants can occur as a result of reg_equiv_constant.) */ | |
2754 | ||
2755 | while (GET_CODE (operand) == SUBREG) | |
2756 | { | |
2757 | offset += SUBREG_WORD (operand); | |
2758 | operand = SUBREG_REG (operand); | |
38e01259 | 2759 | /* Force reload if this is a constant or PLUS or if there may |
a61c98cf RK |
2760 | be a problem accessing OPERAND in the outer mode. */ |
2761 | if (CONSTANT_P (operand) | |
ca769828 | 2762 | || GET_CODE (operand) == PLUS |
03b72c86 RK |
2763 | /* We must force a reload of paradoxical SUBREGs |
2764 | of a MEM because the alignment of the inner value | |
beb5a9b8 RK |
2765 | may not be enough to do the outer reference. On |
2766 | big-endian machines, it may also reference outside | |
2767 | the object. | |
03b72c86 RK |
2768 | |
2769 | On machines that extend byte operations and we have a | |
486d8509 RK |
2770 | SUBREG where both the inner and outer modes are no wider |
2771 | than a word and the inner mode is narrower, is integral, | |
2772 | and gets extended when loaded from memory, combine.c has | |
2773 | made assumptions about the behavior of the machine in such | |
03b72c86 RK |
2774 | register access. If the data is, in fact, in memory we |
2775 | must always load using the size assumed to be in the | |
05d10675 | 2776 | register and let the insn do the different-sized |
5ec105cd RH |
2777 | accesses. |
2778 | ||
05d10675 | 2779 | This is doubly true if WORD_REGISTER_OPERATIONS. In |
5ec105cd RH |
2780 | this case eliminate_regs has left non-paradoxical |
2781 | subregs for push_reloads to see. Make sure it does | |
2782 | by forcing the reload. | |
2783 | ||
2784 | ??? When is it right at this stage to have a subreg | |
2785 | of a mem that is _not_ to be handled specialy? IMO | |
2786 | those should have been reduced to just a mem. */ | |
a61c98cf RK |
2787 | || ((GET_CODE (operand) == MEM |
2788 | || (GET_CODE (operand)== REG | |
2789 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
5ec105cd | 2790 | #ifndef WORD_REGISTER_OPERATIONS |
03b72c86 RK |
2791 | && (((GET_MODE_BITSIZE (GET_MODE (operand)) |
2792 | < BIGGEST_ALIGNMENT) | |
2793 | && (GET_MODE_SIZE (operand_mode[i]) | |
2794 | > GET_MODE_SIZE (GET_MODE (operand)))) | |
beb5a9b8 | 2795 | || (GET_CODE (operand) == MEM && BYTES_BIG_ENDIAN) |
03b72c86 RK |
2796 | #ifdef LOAD_EXTEND_OP |
2797 | || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
2798 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2799 | <= UNITS_PER_WORD) | |
2800 | && (GET_MODE_SIZE (operand_mode[i]) | |
486d8509 RK |
2801 | > GET_MODE_SIZE (GET_MODE (operand))) |
2802 | && INTEGRAL_MODE_P (GET_MODE (operand)) | |
2803 | && LOAD_EXTEND_OP (GET_MODE (operand)) != NIL) | |
46da6b3a | 2804 | #endif |
5ec105cd RH |
2805 | ) |
2806 | #endif | |
2807 | ) | |
eab89b90 RK |
2808 | /* Subreg of a hard reg which can't handle the subreg's mode |
2809 | or which would handle that mode in the wrong number of | |
2810 | registers for subregging to work. */ | |
a61c98cf RK |
2811 | || (GET_CODE (operand) == REG |
2812 | && REGNO (operand) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
2813 | && ((GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
2814 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2815 | > UNITS_PER_WORD) | |
2816 | && ((GET_MODE_SIZE (GET_MODE (operand)) | |
2817 | / UNITS_PER_WORD) | |
2818 | != HARD_REGNO_NREGS (REGNO (operand), | |
2819 | GET_MODE (operand)))) | |
2820 | || ! HARD_REGNO_MODE_OK (REGNO (operand) + offset, | |
2821 | operand_mode[i])))) | |
eab89b90 RK |
2822 | force_reload = 1; |
2823 | } | |
2824 | ||
2825 | this_alternative[i] = (int) NO_REGS; | |
2826 | this_alternative_win[i] = 0; | |
2827 | this_alternative_offmemok[i] = 0; | |
2828 | this_alternative_earlyclobber[i] = 0; | |
2829 | this_alternative_matches[i] = -1; | |
2830 | ||
2831 | /* An empty constraint or empty alternative | |
2832 | allows anything which matched the pattern. */ | |
2833 | if (*p == 0 || *p == ',') | |
2834 | win = 1, badop = 0; | |
2835 | ||
2836 | /* Scan this alternative's specs for this operand; | |
2837 | set WIN if the operand fits any letter in this alternative. | |
2838 | Otherwise, clear BADOP if this operand could | |
2839 | fit some letter after reloads, | |
2840 | or set WINREG if this operand could fit after reloads | |
2841 | provided the constraint allows some registers. */ | |
2842 | ||
2843 | while (*p && (c = *p++) != ',') | |
2844 | switch (c) | |
2845 | { | |
c5c76735 | 2846 | case '=': case '+': case '*': |
eab89b90 RK |
2847 | break; |
2848 | ||
2849 | case '%': | |
42add480 TW |
2850 | /* The last operand should not be marked commutative. */ |
2851 | if (i != noperands - 1) | |
2852 | commutative = i; | |
eab89b90 RK |
2853 | break; |
2854 | ||
2855 | case '?': | |
812f2051 | 2856 | reject += 6; |
eab89b90 RK |
2857 | break; |
2858 | ||
2859 | case '!': | |
812f2051 | 2860 | reject = 600; |
eab89b90 RK |
2861 | break; |
2862 | ||
2863 | case '#': | |
2864 | /* Ignore rest of this alternative as far as | |
2865 | reloading is concerned. */ | |
2866 | while (*p && *p != ',') p++; | |
2867 | break; | |
2868 | ||
c5c76735 JL |
2869 | case '0': case '1': case '2': case '3': case '4': |
2870 | case '5': case '6': case '7': case '8': case '9': | |
2871 | ||
eab89b90 RK |
2872 | c -= '0'; |
2873 | this_alternative_matches[i] = c; | |
2874 | /* We are supposed to match a previous operand. | |
2875 | If we do, we win if that one did. | |
2876 | If we do not, count both of the operands as losers. | |
2877 | (This is too conservative, since most of the time | |
2878 | only a single reload insn will be needed to make | |
2879 | the two operands win. As a result, this alternative | |
2880 | may be rejected when it is actually desirable.) */ | |
2881 | if ((swapped && (c != commutative || i != commutative + 1)) | |
2882 | /* If we are matching as if two operands were swapped, | |
2883 | also pretend that operands_match had been computed | |
2884 | with swapped. | |
2885 | But if I is the second of those and C is the first, | |
2886 | don't exchange them, because operands_match is valid | |
2887 | only on one side of its diagonal. */ | |
2888 | ? (operands_match | |
05d10675 BS |
2889 | [(c == commutative || c == commutative + 1) |
2890 | ? 2*commutative + 1 - c : c] | |
2891 | [(i == commutative || i == commutative + 1) | |
2892 | ? 2*commutative + 1 - i : i]) | |
eab89b90 | 2893 | : operands_match[c][i]) |
fc79eafe JW |
2894 | { |
2895 | /* If we are matching a non-offsettable address where an | |
2896 | offsettable address was expected, then we must reject | |
2897 | this combination, because we can't reload it. */ | |
2898 | if (this_alternative_offmemok[c] | |
1ccbefce | 2899 | && GET_CODE (recog_data.operand[c]) == MEM |
fc79eafe JW |
2900 | && this_alternative[c] == (int) NO_REGS |
2901 | && ! this_alternative_win[c]) | |
2902 | bad = 1; | |
2903 | ||
2904 | win = this_alternative_win[c]; | |
2905 | } | |
eab89b90 RK |
2906 | else |
2907 | { | |
2908 | /* Operands don't match. */ | |
2909 | rtx value; | |
2910 | /* Retroactively mark the operand we had to match | |
2911 | as a loser, if it wasn't already. */ | |
2912 | if (this_alternative_win[c]) | |
2913 | losers++; | |
2914 | this_alternative_win[c] = 0; | |
2915 | if (this_alternative[c] == (int) NO_REGS) | |
2916 | bad = 1; | |
2917 | /* But count the pair only once in the total badness of | |
2918 | this alternative, if the pair can be a dummy reload. */ | |
2919 | value | |
1ccbefce RH |
2920 | = find_dummy_reload (recog_data.operand[i], |
2921 | recog_data.operand[c], | |
2922 | recog_data.operand_loc[i], | |
2923 | recog_data.operand_loc[c], | |
adb44af8 | 2924 | operand_mode[i], operand_mode[c], |
189086f9 RK |
2925 | this_alternative[c], -1, |
2926 | this_alternative_earlyclobber[c]); | |
eab89b90 RK |
2927 | |
2928 | if (value != 0) | |
2929 | losers--; | |
2930 | } | |
2931 | /* This can be fixed with reloads if the operand | |
2932 | we are supposed to match can be fixed with reloads. */ | |
2933 | badop = 0; | |
2934 | this_alternative[i] = this_alternative[c]; | |
e64c4f9e RK |
2935 | |
2936 | /* If we have to reload this operand and some previous | |
2937 | operand also had to match the same thing as this | |
2938 | operand, we don't know how to do that. So reject this | |
2939 | alternative. */ | |
2940 | if (! win || force_reload) | |
2941 | for (j = 0; j < i; j++) | |
2942 | if (this_alternative_matches[j] | |
2943 | == this_alternative_matches[i]) | |
2944 | badop = 1; | |
2945 | ||
eab89b90 RK |
2946 | break; |
2947 | ||
2948 | case 'p': | |
2949 | /* All necessary reloads for an address_operand | |
2950 | were handled in find_reloads_address. */ | |
5c73e847 | 2951 | this_alternative[i] = (int) BASE_REG_CLASS; |
eab89b90 RK |
2952 | win = 1; |
2953 | break; | |
2954 | ||
2955 | case 'm': | |
2956 | if (force_reload) | |
2957 | break; | |
2958 | if (GET_CODE (operand) == MEM | |
2959 | || (GET_CODE (operand) == REG | |
2960 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2961 | && reg_renumber[REGNO (operand)] < 0)) | |
2962 | win = 1; | |
3feffdfe JW |
2963 | if (CONSTANT_P (operand) |
2964 | /* force_const_mem does not accept HIGH. */ | |
2965 | && GET_CODE (operand) != HIGH) | |
eab89b90 | 2966 | badop = 0; |
9d926da5 | 2967 | constmemok = 1; |
eab89b90 RK |
2968 | break; |
2969 | ||
2970 | case '<': | |
2971 | if (GET_CODE (operand) == MEM | |
2972 | && ! address_reloaded[i] | |
2973 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
2974 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
2975 | win = 1; | |
2976 | break; | |
2977 | ||
2978 | case '>': | |
2979 | if (GET_CODE (operand) == MEM | |
2980 | && ! address_reloaded[i] | |
2981 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
2982 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
2983 | win = 1; | |
2984 | break; | |
2985 | ||
2986 | /* Memory operand whose address is not offsettable. */ | |
2987 | case 'V': | |
2988 | if (force_reload) | |
2989 | break; | |
2990 | if (GET_CODE (operand) == MEM | |
2991 | && ! (ind_levels ? offsettable_memref_p (operand) | |
2992 | : offsettable_nonstrict_memref_p (operand)) | |
2993 | /* Certain mem addresses will become offsettable | |
2994 | after they themselves are reloaded. This is important; | |
2995 | we don't want our own handling of unoffsettables | |
2996 | to override the handling of reg_equiv_address. */ | |
2997 | && !(GET_CODE (XEXP (operand, 0)) == REG | |
2998 | && (ind_levels == 0 | |
2999 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) | |
3000 | win = 1; | |
3001 | break; | |
3002 | ||
3003 | /* Memory operand whose address is offsettable. */ | |
3004 | case 'o': | |
3005 | if (force_reload) | |
3006 | break; | |
3007 | if ((GET_CODE (operand) == MEM | |
3008 | /* If IND_LEVELS, find_reloads_address won't reload a | |
3009 | pseudo that didn't get a hard reg, so we have to | |
3010 | reject that case. */ | |
ab87f8c8 JL |
3011 | && ((ind_levels ? offsettable_memref_p (operand) |
3012 | : offsettable_nonstrict_memref_p (operand)) | |
3013 | /* A reloaded address is offsettable because it is now | |
3014 | just a simple register indirect. */ | |
3015 | || address_reloaded[i])) | |
eab89b90 RK |
3016 | || (GET_CODE (operand) == REG |
3017 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3a322c50 RK |
3018 | && reg_renumber[REGNO (operand)] < 0 |
3019 | /* If reg_equiv_address is nonzero, we will be | |
3020 | loading it into a register; hence it will be | |
3021 | offsettable, but we cannot say that reg_equiv_mem | |
3022 | is offsettable without checking. */ | |
3023 | && ((reg_equiv_mem[REGNO (operand)] != 0 | |
3024 | && offsettable_memref_p (reg_equiv_mem[REGNO (operand)])) | |
3025 | || (reg_equiv_address[REGNO (operand)] != 0)))) | |
eab89b90 | 3026 | win = 1; |
3feffdfe JW |
3027 | /* force_const_mem does not accept HIGH. */ |
3028 | if ((CONSTANT_P (operand) && GET_CODE (operand) != HIGH) | |
3029 | || GET_CODE (operand) == MEM) | |
eab89b90 | 3030 | badop = 0; |
9d926da5 | 3031 | constmemok = 1; |
eab89b90 RK |
3032 | offmemok = 1; |
3033 | break; | |
3034 | ||
3035 | case '&': | |
3036 | /* Output operand that is stored before the need for the | |
3037 | input operands (and their index registers) is over. */ | |
3038 | earlyclobber = 1, this_earlyclobber = 1; | |
3039 | break; | |
3040 | ||
3041 | case 'E': | |
293166be | 3042 | #ifndef REAL_ARITHMETIC |
eab89b90 RK |
3043 | /* Match any floating double constant, but only if |
3044 | we can examine the bits of it reliably. */ | |
3045 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
fb3821f7 | 3046 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
eab89b90 RK |
3047 | && GET_MODE (operand) != VOIDmode && ! flag_pretend_float) |
3048 | break; | |
293166be | 3049 | #endif |
eab89b90 RK |
3050 | if (GET_CODE (operand) == CONST_DOUBLE) |
3051 | win = 1; | |
3052 | break; | |
3053 | ||
3054 | case 'F': | |
3055 | if (GET_CODE (operand) == CONST_DOUBLE) | |
3056 | win = 1; | |
3057 | break; | |
3058 | ||
3059 | case 'G': | |
3060 | case 'H': | |
3061 | if (GET_CODE (operand) == CONST_DOUBLE | |
3062 | && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c)) | |
3063 | win = 1; | |
3064 | break; | |
3065 | ||
3066 | case 's': | |
3067 | if (GET_CODE (operand) == CONST_INT | |
3068 | || (GET_CODE (operand) == CONST_DOUBLE | |
3069 | && GET_MODE (operand) == VOIDmode)) | |
3070 | break; | |
3071 | case 'i': | |
3072 | if (CONSTANT_P (operand) | |
3073 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
3074 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)) | |
3075 | #endif | |
3076 | ) | |
3077 | win = 1; | |
3078 | break; | |
3079 | ||
3080 | case 'n': | |
3081 | if (GET_CODE (operand) == CONST_INT | |
3082 | || (GET_CODE (operand) == CONST_DOUBLE | |
3083 | && GET_MODE (operand) == VOIDmode)) | |
3084 | win = 1; | |
3085 | break; | |
3086 | ||
3087 | case 'I': | |
3088 | case 'J': | |
3089 | case 'K': | |
3090 | case 'L': | |
3091 | case 'M': | |
3092 | case 'N': | |
3093 | case 'O': | |
3094 | case 'P': | |
3095 | if (GET_CODE (operand) == CONST_INT | |
3096 | && CONST_OK_FOR_LETTER_P (INTVAL (operand), c)) | |
3097 | win = 1; | |
3098 | break; | |
3099 | ||
3100 | case 'X': | |
3101 | win = 1; | |
3102 | break; | |
3103 | ||
3104 | case 'g': | |
3105 | if (! force_reload | |
3106 | /* A PLUS is never a valid operand, but reload can make | |
3107 | it from a register when eliminating registers. */ | |
3108 | && GET_CODE (operand) != PLUS | |
3109 | /* A SCRATCH is not a valid operand. */ | |
3110 | && GET_CODE (operand) != SCRATCH | |
3111 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
05d10675 BS |
3112 | && (! CONSTANT_P (operand) |
3113 | || ! flag_pic | |
eab89b90 RK |
3114 | || LEGITIMATE_PIC_OPERAND_P (operand)) |
3115 | #endif | |
3116 | && (GENERAL_REGS == ALL_REGS | |
3117 | || GET_CODE (operand) != REG | |
3118 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3119 | && reg_renumber[REGNO (operand)] < 0))) | |
3120 | win = 1; | |
3121 | /* Drop through into 'r' case */ | |
3122 | ||
3123 | case 'r': | |
3124 | this_alternative[i] | |
3125 | = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; | |
3126 | goto reg; | |
3127 | ||
3128 | #ifdef EXTRA_CONSTRAINT | |
05d10675 BS |
3129 | case 'Q': |
3130 | case 'R': | |
3131 | case 'S': | |
3132 | case 'T': | |
3133 | case 'U': | |
eab89b90 RK |
3134 | if (EXTRA_CONSTRAINT (operand, c)) |
3135 | win = 1; | |
3136 | break; | |
3137 | #endif | |
05d10675 | 3138 | |
eab89b90 RK |
3139 | default: |
3140 | this_alternative[i] | |
3141 | = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)]; | |
05d10675 | 3142 | |
eab89b90 RK |
3143 | reg: |
3144 | if (GET_MODE (operand) == BLKmode) | |
3145 | break; | |
3146 | winreg = 1; | |
3147 | if (GET_CODE (operand) == REG | |
3148 | && reg_fits_class_p (operand, this_alternative[i], | |
1ccbefce | 3149 | offset, GET_MODE (recog_data.operand[i]))) |
eab89b90 RK |
3150 | win = 1; |
3151 | break; | |
3152 | } | |
3153 | ||
3154 | constraints[i] = p; | |
3155 | ||
3156 | /* If this operand could be handled with a reg, | |
3157 | and some reg is allowed, then this operand can be handled. */ | |
3158 | if (winreg && this_alternative[i] != (int) NO_REGS) | |
3159 | badop = 0; | |
3160 | ||
3161 | /* Record which operands fit this alternative. */ | |
3162 | this_alternative_earlyclobber[i] = earlyclobber; | |
3163 | if (win && ! force_reload) | |
3164 | this_alternative_win[i] = 1; | |
3165 | else | |
3166 | { | |
9d926da5 RK |
3167 | int const_to_mem = 0; |
3168 | ||
eab89b90 RK |
3169 | this_alternative_offmemok[i] = offmemok; |
3170 | losers++; | |
3171 | if (badop) | |
3172 | bad = 1; | |
3173 | /* Alternative loses if it has no regs for a reg operand. */ | |
3174 | if (GET_CODE (operand) == REG | |
3175 | && this_alternative[i] == (int) NO_REGS | |
3176 | && this_alternative_matches[i] < 0) | |
3177 | bad = 1; | |
3178 | ||
3a322c50 RK |
3179 | /* If this is a constant that is reloaded into the desired |
3180 | class by copying it to memory first, count that as another | |
3181 | reload. This is consistent with other code and is | |
293166be | 3182 | required to avoid choosing another alternative when |
3a322c50 | 3183 | the constant is moved into memory by this function on |
05d10675 | 3184 | an early reload pass. Note that the test here is |
3a322c50 RK |
3185 | precisely the same as in the code below that calls |
3186 | force_const_mem. */ | |
3187 | if (CONSTANT_P (operand) | |
59f25cf9 RK |
3188 | /* force_const_mem does not accept HIGH. */ |
3189 | && GET_CODE (operand) != HIGH | |
e5e809f4 | 3190 | && ((PREFERRED_RELOAD_CLASS (operand, |
05d10675 | 3191 | (enum reg_class) this_alternative[i]) |
e5e809f4 JL |
3192 | == NO_REGS) |
3193 | || no_input_reloads) | |
3a322c50 | 3194 | && operand_mode[i] != VOIDmode) |
9d926da5 RK |
3195 | { |
3196 | const_to_mem = 1; | |
3197 | if (this_alternative[i] != (int) NO_REGS) | |
3198 | losers++; | |
3199 | } | |
3a322c50 | 3200 | |
5e6aa513 RK |
3201 | /* If we can't reload this value at all, reject this |
3202 | alternative. Note that we could also lose due to | |
3203 | LIMIT_RELOAD_RELOAD_CLASS, but we don't check that | |
3204 | here. */ | |
3205 | ||
3206 | if (! CONSTANT_P (operand) | |
73b236b5 | 3207 | && (enum reg_class) this_alternative[i] != NO_REGS |
5e6aa513 RK |
3208 | && (PREFERRED_RELOAD_CLASS (operand, |
3209 | (enum reg_class) this_alternative[i]) | |
3210 | == NO_REGS)) | |
3211 | bad = 1; | |
3212 | ||
e5e809f4 JL |
3213 | /* Alternative loses if it requires a type of reload not |
3214 | permitted for this insn. We can always reload SCRATCH | |
3215 | and objects with a REG_UNUSED note. */ | |
3216 | else if (GET_CODE (operand) != SCRATCH | |
05d10675 BS |
3217 | && modified[i] != RELOAD_READ && no_output_reloads |
3218 | && ! find_reg_note (insn, REG_UNUSED, operand)) | |
e5e809f4 JL |
3219 | bad = 1; |
3220 | else if (modified[i] != RELOAD_WRITE && no_input_reloads | |
3221 | && ! const_to_mem) | |
3222 | bad = 1; | |
3223 | ||
3224 | ||
eab89b90 RK |
3225 | /* We prefer to reload pseudos over reloading other things, |
3226 | since such reloads may be able to be eliminated later. | |
3227 | If we are reloading a SCRATCH, we won't be generating any | |
05d10675 | 3228 | insns, just using a register, so it is also preferred. |
9d926da5 RK |
3229 | So bump REJECT in other cases. Don't do this in the |
3230 | case where we are forcing a constant into memory and | |
3231 | it will then win since we don't want to have a different | |
3232 | alternative match then. */ | |
915bb763 RK |
3233 | if (! (GET_CODE (operand) == REG |
3234 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER) | |
9d926da5 RK |
3235 | && GET_CODE (operand) != SCRATCH |
3236 | && ! (const_to_mem && constmemok)) | |
812f2051 R |
3237 | reject += 2; |
3238 | ||
3239 | /* Input reloads can be inherited more often than output | |
3240 | reloads can be removed, so penalize output reloads. */ | |
7924156a JW |
3241 | if (operand_type[i] != RELOAD_FOR_INPUT |
3242 | && GET_CODE (operand) != SCRATCH) | |
eab89b90 RK |
3243 | reject++; |
3244 | } | |
3245 | ||
05d10675 | 3246 | /* If this operand is a pseudo register that didn't get a hard |
eab89b90 RK |
3247 | reg and this alternative accepts some register, see if the |
3248 | class that we want is a subset of the preferred class for this | |
3249 | register. If not, but it intersects that class, use the | |
3250 | preferred class instead. If it does not intersect the preferred | |
3251 | class, show that usage of this alternative should be discouraged; | |
3252 | it will be discouraged more still if the register is `preferred | |
3253 | or nothing'. We do this because it increases the chance of | |
3254 | reusing our spill register in a later insn and avoiding a pair | |
3255 | of memory stores and loads. | |
3256 | ||
3257 | Don't bother with this if this alternative will accept this | |
3258 | operand. | |
3259 | ||
a2d353e5 RK |
3260 | Don't do this for a multiword operand, since it is only a |
3261 | small win and has the risk of requiring more spill registers, | |
3262 | which could cause a large loss. | |
5aa14fee | 3263 | |
eab89b90 RK |
3264 | Don't do this if the preferred class has only one register |
3265 | because we might otherwise exhaust the class. */ | |
3266 | ||
3267 | ||
3268 | if (! win && this_alternative[i] != (int) NO_REGS | |
5aa14fee | 3269 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
eab89b90 RK |
3270 | && reg_class_size[(int) preferred_class[i]] > 1) |
3271 | { | |
3272 | if (! reg_class_subset_p (this_alternative[i], | |
3273 | preferred_class[i])) | |
3274 | { | |
3275 | /* Since we don't have a way of forming the intersection, | |
3276 | we just do something special if the preferred class | |
05d10675 | 3277 | is a subset of the class we have; that's the most |
eab89b90 RK |
3278 | common case anyway. */ |
3279 | if (reg_class_subset_p (preferred_class[i], | |
3280 | this_alternative[i])) | |
3281 | this_alternative[i] = (int) preferred_class[i]; | |
3282 | else | |
812f2051 | 3283 | reject += (2 + 2 * pref_or_nothing[i]); |
eab89b90 RK |
3284 | } |
3285 | } | |
3286 | } | |
3287 | ||
3288 | /* Now see if any output operands that are marked "earlyclobber" | |
3289 | in this alternative conflict with any input operands | |
3290 | or any memory addresses. */ | |
3291 | ||
3292 | for (i = 0; i < noperands; i++) | |
3293 | if (this_alternative_earlyclobber[i] | |
3294 | && this_alternative_win[i]) | |
3295 | { | |
05d10675 | 3296 | struct decomposition early_data; |
eab89b90 | 3297 | |
1ccbefce | 3298 | early_data = decompose (recog_data.operand[i]); |
eab89b90 RK |
3299 | |
3300 | if (modified[i] == RELOAD_READ) | |
2a230e9d | 3301 | abort (); |
05d10675 | 3302 | |
eab89b90 RK |
3303 | if (this_alternative[i] == NO_REGS) |
3304 | { | |
3305 | this_alternative_earlyclobber[i] = 0; | |
3306 | if (this_insn_is_asm) | |
3307 | error_for_asm (this_insn, | |
3308 | "`&' constraint used with no register class"); | |
3309 | else | |
3310 | abort (); | |
3311 | } | |
3312 | ||
3313 | for (j = 0; j < noperands; j++) | |
3314 | /* Is this an input operand or a memory ref? */ | |
1ccbefce | 3315 | if ((GET_CODE (recog_data.operand[j]) == MEM |
eab89b90 RK |
3316 | || modified[j] != RELOAD_WRITE) |
3317 | && j != i | |
3318 | /* Ignore things like match_operator operands. */ | |
1ccbefce | 3319 | && *recog_data.constraints[j] != 0 |
eab89b90 RK |
3320 | /* Don't count an input operand that is constrained to match |
3321 | the early clobber operand. */ | |
3322 | && ! (this_alternative_matches[j] == i | |
1ccbefce RH |
3323 | && rtx_equal_p (recog_data.operand[i], |
3324 | recog_data.operand[j])) | |
eab89b90 | 3325 | /* Is it altered by storing the earlyclobber operand? */ |
1ccbefce RH |
3326 | && !immune_p (recog_data.operand[j], recog_data.operand[i], |
3327 | early_data)) | |
eab89b90 RK |
3328 | { |
3329 | /* If the output is in a single-reg class, | |
3330 | it's costly to reload it, so reload the input instead. */ | |
3331 | if (reg_class_size[this_alternative[i]] == 1 | |
1ccbefce RH |
3332 | && (GET_CODE (recog_data.operand[j]) == REG |
3333 | || GET_CODE (recog_data.operand[j]) == SUBREG)) | |
eab89b90 RK |
3334 | { |
3335 | losers++; | |
3336 | this_alternative_win[j] = 0; | |
3337 | } | |
3338 | else | |
3339 | break; | |
3340 | } | |
3341 | /* If an earlyclobber operand conflicts with something, | |
3342 | it must be reloaded, so request this and count the cost. */ | |
3343 | if (j != noperands) | |
3344 | { | |
3345 | losers++; | |
3346 | this_alternative_win[i] = 0; | |
3347 | for (j = 0; j < noperands; j++) | |
3348 | if (this_alternative_matches[j] == i | |
3349 | && this_alternative_win[j]) | |
3350 | { | |
3351 | this_alternative_win[j] = 0; | |
3352 | losers++; | |
3353 | } | |
3354 | } | |
3355 | } | |
3356 | ||
3357 | /* If one alternative accepts all the operands, no reload required, | |
3358 | choose that alternative; don't consider the remaining ones. */ | |
3359 | if (losers == 0) | |
3360 | { | |
3361 | /* Unswap these so that they are never swapped at `finish'. */ | |
3362 | if (commutative >= 0) | |
3363 | { | |
1ccbefce RH |
3364 | recog_data.operand[commutative] = substed_operand[commutative]; |
3365 | recog_data.operand[commutative + 1] | |
eab89b90 RK |
3366 | = substed_operand[commutative + 1]; |
3367 | } | |
3368 | for (i = 0; i < noperands; i++) | |
3369 | { | |
3370 | goal_alternative_win[i] = 1; | |
3371 | goal_alternative[i] = this_alternative[i]; | |
3372 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3373 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3374 | goal_alternative_earlyclobber[i] | |
3375 | = this_alternative_earlyclobber[i]; | |
3376 | } | |
3377 | goal_alternative_number = this_alternative_number; | |
3378 | goal_alternative_swapped = swapped; | |
3379 | goal_earlyclobber = this_earlyclobber; | |
3380 | goto finish; | |
3381 | } | |
3382 | ||
3383 | /* REJECT, set by the ! and ? constraint characters and when a register | |
3384 | would be reloaded into a non-preferred class, discourages the use of | |
812f2051 R |
3385 | this alternative for a reload goal. REJECT is incremented by six |
3386 | for each ? and two for each non-preferred class. */ | |
3387 | losers = losers * 6 + reject; | |
eab89b90 RK |
3388 | |
3389 | /* If this alternative can be made to work by reloading, | |
3390 | and it needs less reloading than the others checked so far, | |
3391 | record it as the chosen goal for reloading. */ | |
3392 | if (! bad && best > losers) | |
3393 | { | |
3394 | for (i = 0; i < noperands; i++) | |
3395 | { | |
3396 | goal_alternative[i] = this_alternative[i]; | |
3397 | goal_alternative_win[i] = this_alternative_win[i]; | |
3398 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3399 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3400 | goal_alternative_earlyclobber[i] | |
3401 | = this_alternative_earlyclobber[i]; | |
3402 | } | |
3403 | goal_alternative_swapped = swapped; | |
3404 | best = losers; | |
3405 | goal_alternative_number = this_alternative_number; | |
3406 | goal_earlyclobber = this_earlyclobber; | |
3407 | } | |
3408 | } | |
3409 | ||
3410 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
3411 | then we need to try each alternative twice, | |
3412 | the second time matching those two operands | |
3413 | as if we had exchanged them. | |
3414 | To do this, really exchange them in operands. | |
3415 | ||
3416 | If we have just tried the alternatives the second time, | |
3417 | return operands to normal and drop through. */ | |
3418 | ||
3419 | if (commutative >= 0) | |
3420 | { | |
3421 | swapped = !swapped; | |
3422 | if (swapped) | |
3423 | { | |
3424 | register enum reg_class tclass; | |
3425 | register int t; | |
3426 | ||
1ccbefce RH |
3427 | recog_data.operand[commutative] = substed_operand[commutative + 1]; |
3428 | recog_data.operand[commutative + 1] = substed_operand[commutative]; | |
eab89b90 RK |
3429 | |
3430 | tclass = preferred_class[commutative]; | |
3431 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
3432 | preferred_class[commutative + 1] = tclass; | |
3433 | ||
3434 | t = pref_or_nothing[commutative]; | |
3435 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
3436 | pref_or_nothing[commutative + 1] = t; | |
3437 | ||
1ccbefce | 3438 | bcopy ((char *) recog_data.constraints, (char *) constraints, |
4c9a05bc | 3439 | noperands * sizeof (char *)); |
eab89b90 RK |
3440 | goto try_swapped; |
3441 | } | |
3442 | else | |
3443 | { | |
1ccbefce RH |
3444 | recog_data.operand[commutative] = substed_operand[commutative]; |
3445 | recog_data.operand[commutative + 1] | |
3446 | = substed_operand[commutative + 1]; | |
eab89b90 RK |
3447 | } |
3448 | } | |
3449 | ||
3450 | /* The operands don't meet the constraints. | |
3451 | goal_alternative describes the alternative | |
3452 | that we could reach by reloading the fewest operands. | |
3453 | Reload so as to fit it. */ | |
3454 | ||
c22eaf8a | 3455 | if (best == MAX_RECOG_OPERANDS * 2 + 600) |
eab89b90 RK |
3456 | { |
3457 | /* No alternative works with reloads?? */ | |
3458 | if (insn_code_number >= 0) | |
290b61f7 | 3459 | fatal_insn ("Unable to generate reloads for:", insn); |
eab89b90 RK |
3460 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); |
3461 | /* Avoid further trouble with this insn. */ | |
38a448ca | 3462 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 | 3463 | n_reloads = 0; |
cb2afeb3 | 3464 | return 0; |
eab89b90 RK |
3465 | } |
3466 | ||
3467 | /* Jump to `finish' from above if all operands are valid already. | |
3468 | In that case, goal_alternative_win is all 1. */ | |
3469 | finish: | |
3470 | ||
3471 | /* Right now, for any pair of operands I and J that are required to match, | |
3472 | with I < J, | |
3473 | goal_alternative_matches[J] is I. | |
3474 | Set up goal_alternative_matched as the inverse function: | |
3475 | goal_alternative_matched[I] = J. */ | |
3476 | ||
3477 | for (i = 0; i < noperands; i++) | |
3478 | goal_alternative_matched[i] = -1; | |
3479 | ||
3480 | for (i = 0; i < noperands; i++) | |
3481 | if (! goal_alternative_win[i] | |
3482 | && goal_alternative_matches[i] >= 0) | |
3483 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
3484 | ||
3485 | /* If the best alternative is with operands 1 and 2 swapped, | |
a8c9daeb RK |
3486 | consider them swapped before reporting the reloads. Update the |
3487 | operand numbers of any reloads already pushed. */ | |
eab89b90 RK |
3488 | |
3489 | if (goal_alternative_swapped) | |
3490 | { | |
3491 | register rtx tem; | |
3492 | ||
3493 | tem = substed_operand[commutative]; | |
3494 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
3495 | substed_operand[commutative + 1] = tem; | |
1ccbefce RH |
3496 | tem = recog_data.operand[commutative]; |
3497 | recog_data.operand[commutative] = recog_data.operand[commutative + 1]; | |
3498 | recog_data.operand[commutative + 1] = tem; | |
3499 | tem = *recog_data.operand_loc[commutative]; | |
3500 | *recog_data.operand_loc[commutative] | |
3501 | = *recog_data.operand_loc[commutative + 1]; | |
3502 | *recog_data.operand_loc[commutative+1] = tem; | |
a8c9daeb RK |
3503 | |
3504 | for (i = 0; i < n_reloads; i++) | |
3505 | { | |
eceef4c9 BS |
3506 | if (rld[i].opnum == commutative) |
3507 | rld[i].opnum = commutative + 1; | |
3508 | else if (rld[i].opnum == commutative + 1) | |
3509 | rld[i].opnum = commutative; | |
a8c9daeb | 3510 | } |
eab89b90 RK |
3511 | } |
3512 | ||
eab89b90 RK |
3513 | for (i = 0; i < noperands; i++) |
3514 | { | |
eab89b90 | 3515 | operand_reloadnum[i] = -1; |
a8c9daeb RK |
3516 | |
3517 | /* If this is an earlyclobber operand, we need to widen the scope. | |
3518 | The reload must remain valid from the start of the insn being | |
3519 | reloaded until after the operand is stored into its destination. | |
3520 | We approximate this with RELOAD_OTHER even though we know that we | |
3521 | do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. | |
3522 | ||
3523 | One special case that is worth checking is when we have an | |
3524 | output that is earlyclobber but isn't used past the insn (typically | |
05d10675 | 3525 | a SCRATCH). In this case, we only need have the reload live |
a8c9daeb | 3526 | through the insn itself, but not for any of our input or output |
05d10675 | 3527 | reloads. |
f9df0a1d R |
3528 | But we must not accidentally narrow the scope of an existing |
3529 | RELOAD_OTHER reload - leave these alone. | |
a8c9daeb RK |
3530 | |
3531 | In any case, anything needed to address this operand can remain | |
3532 | however they were previously categorized. */ | |
3533 | ||
f9df0a1d | 3534 | if (goal_alternative_earlyclobber[i] && operand_type[i] != RELOAD_OTHER) |
a8c9daeb | 3535 | operand_type[i] |
1ccbefce | 3536 | = (find_reg_note (insn, REG_UNUSED, recog_data.operand[i]) |
a8c9daeb | 3537 | ? RELOAD_FOR_INSN : RELOAD_OTHER); |
eab89b90 RK |
3538 | } |
3539 | ||
3540 | /* Any constants that aren't allowed and can't be reloaded | |
3541 | into registers are here changed into memory references. */ | |
3542 | for (i = 0; i < noperands; i++) | |
3543 | if (! goal_alternative_win[i] | |
1ccbefce | 3544 | && CONSTANT_P (recog_data.operand[i]) |
59f25cf9 | 3545 | /* force_const_mem does not accept HIGH. */ |
1ccbefce RH |
3546 | && GET_CODE (recog_data.operand[i]) != HIGH |
3547 | && ((PREFERRED_RELOAD_CLASS (recog_data.operand[i], | |
05d10675 | 3548 | (enum reg_class) goal_alternative[i]) |
e5e809f4 JL |
3549 | == NO_REGS) |
3550 | || no_input_reloads) | |
eab89b90 RK |
3551 | && operand_mode[i] != VOIDmode) |
3552 | { | |
1ccbefce | 3553 | substed_operand[i] = recog_data.operand[i] |
eab89b90 | 3554 | = find_reloads_toplev (force_const_mem (operand_mode[i], |
1ccbefce | 3555 | recog_data.operand[i]), |
cb2afeb3 | 3556 | i, address_type[i], ind_levels, 0, insn); |
1ccbefce | 3557 | if (alternative_allows_memconst (recog_data.constraints[i], |
eab89b90 RK |
3558 | goal_alternative_number)) |
3559 | goal_alternative_win[i] = 1; | |
3560 | } | |
3561 | ||
4644aad4 RK |
3562 | /* Record the values of the earlyclobber operands for the caller. */ |
3563 | if (goal_earlyclobber) | |
3564 | for (i = 0; i < noperands; i++) | |
3565 | if (goal_alternative_earlyclobber[i]) | |
1ccbefce | 3566 | reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i]; |
4644aad4 | 3567 | |
eab89b90 RK |
3568 | /* Now record reloads for all the operands that need them. */ |
3569 | for (i = 0; i < noperands; i++) | |
3570 | if (! goal_alternative_win[i]) | |
3571 | { | |
3572 | /* Operands that match previous ones have already been handled. */ | |
3573 | if (goal_alternative_matches[i] >= 0) | |
3574 | ; | |
3575 | /* Handle an operand with a nonoffsettable address | |
3576 | appearing where an offsettable address will do | |
3a322c50 RK |
3577 | by reloading the address into a base register. |
3578 | ||
3579 | ??? We can also do this when the operand is a register and | |
3580 | reg_equiv_mem is not offsettable, but this is a bit tricky, | |
3581 | so we don't bother with it. It may not be worth doing. */ | |
eab89b90 RK |
3582 | else if (goal_alternative_matched[i] == -1 |
3583 | && goal_alternative_offmemok[i] | |
1ccbefce | 3584 | && GET_CODE (recog_data.operand[i]) == MEM) |
eab89b90 RK |
3585 | { |
3586 | operand_reloadnum[i] | |
1ccbefce RH |
3587 | = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX, |
3588 | &XEXP (recog_data.operand[i], 0), NULL_PTR, | |
3589 | BASE_REG_CLASS, | |
3590 | GET_MODE (XEXP (recog_data.operand[i], 0)), | |
a8c9daeb | 3591 | VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); |
eceef4c9 | 3592 | rld[operand_reloadnum[i]].inc |
1ccbefce | 3593 | = GET_MODE_SIZE (GET_MODE (recog_data.operand[i])); |
a8c9daeb RK |
3594 | |
3595 | /* If this operand is an output, we will have made any | |
3596 | reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but | |
3597 | now we are treating part of the operand as an input, so | |
3598 | we must change these to RELOAD_FOR_INPUT_ADDRESS. */ | |
3599 | ||
2d55b7e8 | 3600 | if (modified[i] == RELOAD_WRITE) |
47c8cf91 ILT |
3601 | { |
3602 | for (j = 0; j < n_reloads; j++) | |
3603 | { | |
eceef4c9 | 3604 | if (rld[j].opnum == i) |
47c8cf91 | 3605 | { |
eceef4c9 BS |
3606 | if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS) |
3607 | rld[j].when_needed = RELOAD_FOR_INPUT_ADDRESS; | |
3608 | else if (rld[j].when_needed | |
47c8cf91 | 3609 | == RELOAD_FOR_OUTADDR_ADDRESS) |
eceef4c9 | 3610 | rld[j].when_needed = RELOAD_FOR_INPADDR_ADDRESS; |
47c8cf91 ILT |
3611 | } |
3612 | } | |
3613 | } | |
eab89b90 RK |
3614 | } |
3615 | else if (goal_alternative_matched[i] == -1) | |
9ec36da5 JL |
3616 | { |
3617 | operand_reloadnum[i] | |
3618 | = push_reload ((modified[i] != RELOAD_WRITE | |
1ccbefce RH |
3619 | ? recog_data.operand[i] : 0), |
3620 | (modified[i] != RELOAD_READ | |
3621 | ? recog_data.operand[i] : 0), | |
9ec36da5 | 3622 | (modified[i] != RELOAD_WRITE |
1ccbefce | 3623 | ? recog_data.operand_loc[i] : 0), |
9ec36da5 | 3624 | (modified[i] != RELOAD_READ |
1ccbefce | 3625 | ? recog_data.operand_loc[i] : 0), |
9ec36da5 JL |
3626 | (enum reg_class) goal_alternative[i], |
3627 | (modified[i] == RELOAD_WRITE | |
3628 | ? VOIDmode : operand_mode[i]), | |
3629 | (modified[i] == RELOAD_READ | |
3630 | ? VOIDmode : operand_mode[i]), | |
3631 | (insn_code_number < 0 ? 0 | |
a995e389 | 3632 | : insn_data[insn_code_number].operand[i].strict_low), |
9ec36da5 | 3633 | 0, i, operand_type[i]); |
9ec36da5 | 3634 | } |
eab89b90 RK |
3635 | /* In a matching pair of operands, one must be input only |
3636 | and the other must be output only. | |
3637 | Pass the input operand as IN and the other as OUT. */ | |
3638 | else if (modified[i] == RELOAD_READ | |
3639 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
3640 | { | |
3641 | operand_reloadnum[i] | |
1ccbefce RH |
3642 | = push_reload (recog_data.operand[i], |
3643 | recog_data.operand[goal_alternative_matched[i]], | |
3644 | recog_data.operand_loc[i], | |
3645 | recog_data.operand_loc[goal_alternative_matched[i]], | |
eab89b90 RK |
3646 | (enum reg_class) goal_alternative[i], |
3647 | operand_mode[i], | |
3648 | operand_mode[goal_alternative_matched[i]], | |
a8c9daeb | 3649 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3650 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
3651 | } | |
3652 | else if (modified[i] == RELOAD_WRITE | |
3653 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
3654 | { | |
3655 | operand_reloadnum[goal_alternative_matched[i]] | |
1ccbefce RH |
3656 | = push_reload (recog_data.operand[goal_alternative_matched[i]], |
3657 | recog_data.operand[i], | |
3658 | recog_data.operand_loc[goal_alternative_matched[i]], | |
3659 | recog_data.operand_loc[i], | |
eab89b90 RK |
3660 | (enum reg_class) goal_alternative[i], |
3661 | operand_mode[goal_alternative_matched[i]], | |
3662 | operand_mode[i], | |
a8c9daeb | 3663 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3664 | operand_reloadnum[i] = output_reloadnum; |
3665 | } | |
3666 | else if (insn_code_number >= 0) | |
3667 | abort (); | |
3668 | else | |
3669 | { | |
3670 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3671 | /* Avoid further trouble with this insn. */ | |
38a448ca | 3672 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 | 3673 | n_reloads = 0; |
cb2afeb3 | 3674 | return 0; |
eab89b90 RK |
3675 | } |
3676 | } | |
3677 | else if (goal_alternative_matched[i] < 0 | |
3678 | && goal_alternative_matches[i] < 0 | |
3679 | && optimize) | |
3680 | { | |
05d10675 | 3681 | /* For each non-matching operand that's a MEM or a pseudo-register |
eab89b90 RK |
3682 | that didn't get a hard register, make an optional reload. |
3683 | This may get done even if the insn needs no reloads otherwise. */ | |
a8c9daeb | 3684 | |
1ccbefce | 3685 | rtx operand = recog_data.operand[i]; |
a8c9daeb | 3686 | |
eab89b90 RK |
3687 | while (GET_CODE (operand) == SUBREG) |
3688 | operand = XEXP (operand, 0); | |
a8c9daeb RK |
3689 | if ((GET_CODE (operand) == MEM |
3690 | || (GET_CODE (operand) == REG | |
3691 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
cb2afeb3 R |
3692 | /* If this is only for an output, the optional reload would not |
3693 | actually cause us to use a register now, just note that | |
3694 | something is stored here. */ | |
3695 | && ((enum reg_class) goal_alternative[i] != NO_REGS | |
3696 | || modified[i] == RELOAD_WRITE) | |
a8c9daeb | 3697 | && ! no_input_reloads |
cb2afeb3 R |
3698 | /* An optional output reload might allow to delete INSN later. |
3699 | We mustn't make in-out reloads on insns that are not permitted | |
3700 | output reloads. | |
3701 | If this is an asm, we can't delete it; we must not even call | |
3702 | push_reload for an optional output reload in this case, | |
3703 | because we can't be sure that the constraint allows a register, | |
3704 | and push_reload verifies the constraints for asms. */ | |
eab89b90 | 3705 | && (modified[i] == RELOAD_READ |
cb2afeb3 | 3706 | || (! no_output_reloads && ! this_insn_is_asm))) |
eab89b90 | 3707 | operand_reloadnum[i] |
1ccbefce RH |
3708 | = push_reload ((modified[i] != RELOAD_WRITE |
3709 | ? recog_data.operand[i] : 0), | |
3710 | (modified[i] != RELOAD_READ | |
3711 | ? recog_data.operand[i] : 0), | |
a8c9daeb | 3712 | (modified[i] != RELOAD_WRITE |
1ccbefce | 3713 | ? recog_data.operand_loc[i] : 0), |
a8c9daeb | 3714 | (modified[i] != RELOAD_READ |
1ccbefce | 3715 | ? recog_data.operand_loc[i] : 0), |
eab89b90 | 3716 | (enum reg_class) goal_alternative[i], |
a8c9daeb RK |
3717 | (modified[i] == RELOAD_WRITE |
3718 | ? VOIDmode : operand_mode[i]), | |
3719 | (modified[i] == RELOAD_READ | |
3720 | ? VOIDmode : operand_mode[i]), | |
eab89b90 | 3721 | (insn_code_number < 0 ? 0 |
a995e389 | 3722 | : insn_data[insn_code_number].operand[i].strict_low), |
a8c9daeb | 3723 | 1, i, operand_type[i]); |
87afbee6 JL |
3724 | /* If a memory reference remains (either as a MEM or a pseudo that |
3725 | did not get a hard register), yet we can't make an optional | |
cb2afeb3 R |
3726 | reload, check if this is actually a pseudo register reference; |
3727 | we then need to emit a USE and/or a CLOBBER so that reload | |
3728 | inheritance will do the right thing. */ | |
87afbee6 JL |
3729 | else if (replace |
3730 | && (GET_CODE (operand) == MEM | |
3731 | || (GET_CODE (operand) == REG | |
3732 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3733 | && reg_renumber [REGNO (operand)] < 0))) | |
cb2afeb3 | 3734 | { |
1ccbefce | 3735 | operand = *recog_data.operand_loc[i]; |
cb2afeb3 R |
3736 | |
3737 | while (GET_CODE (operand) == SUBREG) | |
3738 | operand = XEXP (operand, 0); | |
3739 | if (GET_CODE (operand) == REG) | |
3740 | { | |
3741 | if (modified[i] != RELOAD_WRITE) | |
3742 | emit_insn_before (gen_rtx_USE (VOIDmode, operand), insn); | |
3743 | if (modified[i] != RELOAD_READ) | |
3744 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, operand), insn); | |
3745 | } | |
3746 | } | |
eab89b90 | 3747 | } |
a8c9daeb RK |
3748 | else if (goal_alternative_matches[i] >= 0 |
3749 | && goal_alternative_win[goal_alternative_matches[i]] | |
3750 | && modified[i] == RELOAD_READ | |
3751 | && modified[goal_alternative_matches[i]] == RELOAD_WRITE | |
3752 | && ! no_input_reloads && ! no_output_reloads | |
3753 | && optimize) | |
3754 | { | |
3755 | /* Similarly, make an optional reload for a pair of matching | |
3756 | objects that are in MEM or a pseudo that didn't get a hard reg. */ | |
eab89b90 | 3757 | |
1ccbefce | 3758 | rtx operand = recog_data.operand[i]; |
a8c9daeb RK |
3759 | |
3760 | while (GET_CODE (operand) == SUBREG) | |
3761 | operand = XEXP (operand, 0); | |
3762 | if ((GET_CODE (operand) == MEM | |
3763 | || (GET_CODE (operand) == REG | |
3764 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
3765 | && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] | |
3766 | != NO_REGS)) | |
3767 | operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] | |
1ccbefce RH |
3768 | = push_reload (recog_data.operand[goal_alternative_matches[i]], |
3769 | recog_data.operand[i], | |
3770 | recog_data.operand_loc[goal_alternative_matches[i]], | |
3771 | recog_data.operand_loc[i], | |
a8c9daeb RK |
3772 | (enum reg_class) goal_alternative[goal_alternative_matches[i]], |
3773 | operand_mode[goal_alternative_matches[i]], | |
3774 | operand_mode[i], | |
3775 | 0, 1, goal_alternative_matches[i], RELOAD_OTHER); | |
3776 | } | |
05d10675 | 3777 | |
cb2afeb3 R |
3778 | /* Perform whatever substitutions on the operands we are supposed |
3779 | to make due to commutativity or replacement of registers | |
3780 | with equivalent constants or memory slots. */ | |
3781 | ||
3782 | for (i = 0; i < noperands; i++) | |
3783 | { | |
3784 | /* We only do this on the last pass through reload, because it is | |
05d10675 BS |
3785 | possible for some data (like reg_equiv_address) to be changed during |
3786 | later passes. Moreover, we loose the opportunity to get a useful | |
3787 | reload_{in,out}_reg when we do these replacements. */ | |
cb2afeb3 R |
3788 | |
3789 | if (replace) | |
e54db24f MM |
3790 | { |
3791 | rtx substitution = substed_operand[i]; | |
3792 | ||
1ccbefce | 3793 | *recog_data.operand_loc[i] = substitution; |
e54db24f MM |
3794 | |
3795 | /* If we're replacing an operand with a LABEL_REF, we need | |
3796 | to make sure that there's a REG_LABEL note attached to | |
3797 | this instruction. */ | |
3798 | if (GET_CODE (insn) != JUMP_INSN | |
3799 | && GET_CODE (substitution) == LABEL_REF | |
3800 | && !find_reg_note (insn, REG_LABEL, XEXP (substitution, 0))) | |
3801 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_LABEL, | |
3802 | XEXP (substitution, 0), | |
3803 | REG_NOTES (insn)); | |
3804 | } | |
cb2afeb3 | 3805 | else |
1ccbefce | 3806 | retval |= (substed_operand[i] != *recog_data.operand_loc[i]); |
cb2afeb3 R |
3807 | } |
3808 | ||
eab89b90 RK |
3809 | /* If this insn pattern contains any MATCH_DUP's, make sure that |
3810 | they will be substituted if the operands they match are substituted. | |
3811 | Also do now any substitutions we already did on the operands. | |
3812 | ||
3813 | Don't do this if we aren't making replacements because we might be | |
3814 | propagating things allocated by frame pointer elimination into places | |
3815 | it doesn't expect. */ | |
3816 | ||
3817 | if (insn_code_number >= 0 && replace) | |
a995e389 | 3818 | for (i = insn_data[insn_code_number].n_dups - 1; i >= 0; i--) |
eab89b90 | 3819 | { |
1ccbefce RH |
3820 | int opno = recog_data.dup_num[i]; |
3821 | *recog_data.dup_loc[i] = *recog_data.operand_loc[opno]; | |
eab89b90 | 3822 | if (operand_reloadnum[opno] >= 0) |
1ccbefce | 3823 | push_replacement (recog_data.dup_loc[i], operand_reloadnum[opno], |
a995e389 | 3824 | insn_data[insn_code_number].operand[opno].mode); |
eab89b90 RK |
3825 | } |
3826 | ||
3827 | #if 0 | |
3828 | /* This loses because reloading of prior insns can invalidate the equivalence | |
3829 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
3830 | causing this insn to need more reload regs than it needed before. | |
3831 | It may be too late to make the reload regs available. | |
3832 | Now this optimization is done safely in choose_reload_regs. */ | |
3833 | ||
3834 | /* For each reload of a reg into some other class of reg, | |
3835 | search for an existing equivalent reg (same value now) in the right class. | |
3836 | We can use it as long as we don't need to change its contents. */ | |
3837 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
3838 | if (rld[i].reg_rtx == 0 |
3839 | && rld[i].in != 0 | |
3840 | && GET_CODE (rld[i].in) == REG | |
3841 | && rld[i].out == 0) | |
eab89b90 | 3842 | { |
eceef4c9 BS |
3843 | rld[i].reg_rtx |
3844 | = find_equiv_reg (rld[i].in, insn, rld[i].class, -1, | |
3845 | static_reload_reg_p, 0, rld[i].inmode); | |
eab89b90 RK |
3846 | /* Prevent generation of insn to load the value |
3847 | because the one we found already has the value. */ | |
eceef4c9 BS |
3848 | if (rld[i].reg_rtx) |
3849 | rld[i].in = rld[i].reg_rtx; | |
eab89b90 RK |
3850 | } |
3851 | #endif | |
3852 | ||
a8c9daeb RK |
3853 | /* Perhaps an output reload can be combined with another |
3854 | to reduce needs by one. */ | |
3855 | if (!goal_earlyclobber) | |
3856 | combine_reloads (); | |
3857 | ||
3858 | /* If we have a pair of reloads for parts of an address, they are reloading | |
3859 | the same object, the operands themselves were not reloaded, and they | |
3860 | are for two operands that are supposed to match, merge the reloads and | |
0f41302f | 3861 | change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ |
a8c9daeb RK |
3862 | |
3863 | for (i = 0; i < n_reloads; i++) | |
3864 | { | |
3865 | int k; | |
3866 | ||
3867 | for (j = i + 1; j < n_reloads; j++) | |
eceef4c9 BS |
3868 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
3869 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
3870 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
3871 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
3872 | && (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
3873 | || rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
3874 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
3875 | || rld[j].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
3876 | && rtx_equal_p (rld[i].in, rld[j].in) | |
3877 | && (operand_reloadnum[rld[i].opnum] < 0 | |
3878 | || rld[operand_reloadnum[rld[i].opnum]].optional) | |
3879 | && (operand_reloadnum[rld[j].opnum] < 0 | |
3880 | || rld[operand_reloadnum[rld[j].opnum]].optional) | |
3881 | && (goal_alternative_matches[rld[i].opnum] == rld[j].opnum | |
3882 | || (goal_alternative_matches[rld[j].opnum] | |
3883 | == rld[i].opnum))) | |
a8c9daeb RK |
3884 | { |
3885 | for (k = 0; k < n_replacements; k++) | |
3886 | if (replacements[k].what == j) | |
3887 | replacements[k].what = i; | |
3888 | ||
eceef4c9 BS |
3889 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
3890 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
3891 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
47c8cf91 | 3892 | else |
eceef4c9 BS |
3893 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
3894 | rld[j].in = 0; | |
a8c9daeb RK |
3895 | } |
3896 | } | |
3897 | ||
05d10675 | 3898 | /* Scan all the reloads and update their type. |
a8c9daeb RK |
3899 | If a reload is for the address of an operand and we didn't reload |
3900 | that operand, change the type. Similarly, change the operand number | |
3901 | of a reload when two operands match. If a reload is optional, treat it | |
3902 | as though the operand isn't reloaded. | |
3903 | ||
3904 | ??? This latter case is somewhat odd because if we do the optional | |
3905 | reload, it means the object is hanging around. Thus we need only | |
3906 | do the address reload if the optional reload was NOT done. | |
3907 | ||
3908 | Change secondary reloads to be the address type of their operand, not | |
3909 | the normal type. | |
3910 | ||
3911 | If an operand's reload is now RELOAD_OTHER, change any | |
3912 | RELOAD_FOR_INPUT_ADDRESS reloads of that operand to | |
3913 | RELOAD_FOR_OTHER_ADDRESS. */ | |
3914 | ||
3915 | for (i = 0; i < n_reloads; i++) | |
3916 | { | |
eceef4c9 BS |
3917 | if (rld[i].secondary_p |
3918 | && rld[i].when_needed == operand_type[rld[i].opnum]) | |
3919 | rld[i].when_needed = address_type[rld[i].opnum]; | |
3920 | ||
3921 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
3922 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
3923 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
3924 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
3925 | && (operand_reloadnum[rld[i].opnum] < 0 | |
3926 | || rld[operand_reloadnum[rld[i].opnum]].optional)) | |
f98bb7d3 RK |
3927 | { |
3928 | /* If we have a secondary reload to go along with this reload, | |
0f41302f | 3929 | change its type to RELOAD_FOR_OPADDR_ADDR. */ |
f98bb7d3 | 3930 | |
eceef4c9 BS |
3931 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
3932 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
3933 | && rld[i].secondary_in_reload != -1) | |
f98bb7d3 | 3934 | { |
eceef4c9 | 3935 | int secondary_in_reload = rld[i].secondary_in_reload; |
f98bb7d3 | 3936 | |
eceef4c9 | 3937 | rld[secondary_in_reload].when_needed |
db3cf6fb | 3938 | = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 3939 | |
0f41302f | 3940 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 | 3941 | if (secondary_in_reload > 0 |
eceef4c9 BS |
3942 | && rld[secondary_in_reload].secondary_in_reload != -1) |
3943 | rld[rld[secondary_in_reload].secondary_in_reload].when_needed | |
f98bb7d3 RK |
3944 | = RELOAD_FOR_OPADDR_ADDR; |
3945 | } | |
3946 | ||
eceef4c9 BS |
3947 | if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS |
3948 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
3949 | && rld[i].secondary_out_reload != -1) | |
f98bb7d3 | 3950 | { |
eceef4c9 | 3951 | int secondary_out_reload = rld[i].secondary_out_reload; |
f98bb7d3 | 3952 | |
eceef4c9 | 3953 | rld[secondary_out_reload].when_needed |
db3cf6fb | 3954 | = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 3955 | |
0f41302f | 3956 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 | 3957 | if (secondary_out_reload |
eceef4c9 BS |
3958 | && rld[secondary_out_reload].secondary_out_reload != -1) |
3959 | rld[rld[secondary_out_reload].secondary_out_reload].when_needed | |
f98bb7d3 RK |
3960 | = RELOAD_FOR_OPADDR_ADDR; |
3961 | } | |
e5e809f4 | 3962 | |
eceef4c9 BS |
3963 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
3964 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
3965 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
cb2afeb3 | 3966 | else |
eceef4c9 | 3967 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
f98bb7d3 | 3968 | } |
a8c9daeb | 3969 | |
eceef4c9 BS |
3970 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
3971 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
3972 | && operand_reloadnum[rld[i].opnum] >= 0 | |
3973 | && (rld[operand_reloadnum[rld[i].opnum]].when_needed | |
a8c9daeb | 3974 | == RELOAD_OTHER)) |
eceef4c9 | 3975 | rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS; |
a8c9daeb | 3976 | |
eceef4c9 BS |
3977 | if (goal_alternative_matches[rld[i].opnum] >= 0) |
3978 | rld[i].opnum = goal_alternative_matches[rld[i].opnum]; | |
a8c9daeb RK |
3979 | } |
3980 | ||
a94ce333 JW |
3981 | /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads. |
3982 | If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR | |
3983 | reloads to RELOAD_FOR_OPERAND_ADDRESS reloads. | |
3984 | ||
3985 | choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never | |
3986 | conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a | |
3987 | single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads. | |
3988 | However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload, | |
3989 | then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all | |
3990 | RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it. | |
3991 | This is complicated by the fact that a single operand can have more | |
3992 | than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix | |
3993 | choose_reload_regs without affecting code quality, and cases that | |
3994 | actually fail are extremely rare, so it turns out to be better to fix | |
3995 | the problem here by not generating cases that choose_reload_regs will | |
3996 | fail for. */ | |
d3adbeea | 3997 | /* There is a similar problem with RELOAD_FOR_INPUT_ADDRESS / |
826e3854 R |
3998 | RELOAD_FOR_OUTPUT_ADDRESS when there is more than one of a kind for |
3999 | a single operand. | |
4000 | We can reduce the register pressure by exploiting that a | |
4001 | RELOAD_FOR_X_ADDR_ADDR that precedes all RELOAD_FOR_X_ADDRESS reloads | |
c10638c9 R |
4002 | does not conflict with any of them, if it is only used for the first of |
4003 | the RELOAD_FOR_X_ADDRESS reloads. */ | |
a94ce333 | 4004 | { |
826e3854 R |
4005 | int first_op_addr_num = -2; |
4006 | int first_inpaddr_num[MAX_RECOG_OPERANDS]; | |
4007 | int first_outpaddr_num[MAX_RECOG_OPERANDS]; | |
4008 | int need_change= 0; | |
4009 | /* We use last_op_addr_reload and the contents of the above arrays | |
4010 | first as flags - -2 means no instance encountered, -1 means exactly | |
4011 | one instance encountered. | |
4012 | If more than one instance has been encountered, we store the reload | |
4013 | number of the first reload of the kind in question; reload numbers | |
4014 | are known to be non-negative. */ | |
4015 | for (i = 0; i < noperands; i++) | |
4016 | first_inpaddr_num[i] = first_outpaddr_num[i] = -2; | |
4017 | for (i = n_reloads - 1; i >= 0; i--) | |
4018 | { | |
eceef4c9 | 4019 | switch (rld[i].when_needed) |
826e3854 R |
4020 | { |
4021 | case RELOAD_FOR_OPERAND_ADDRESS: | |
c10638c9 | 4022 | if (++first_op_addr_num >= 0) |
826e3854 | 4023 | { |
c10638c9 | 4024 | first_op_addr_num = i; |
826e3854 R |
4025 | need_change = 1; |
4026 | } | |
4027 | break; | |
4028 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4029 | if (++first_inpaddr_num[rld[i].opnum] >= 0) |
826e3854 | 4030 | { |
eceef4c9 | 4031 | first_inpaddr_num[rld[i].opnum] = i; |
826e3854 R |
4032 | need_change = 1; |
4033 | } | |
4034 | break; | |
4035 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
eceef4c9 | 4036 | if (++first_outpaddr_num[rld[i].opnum] >= 0) |
826e3854 | 4037 | { |
eceef4c9 | 4038 | first_outpaddr_num[rld[i].opnum] = i; |
826e3854 R |
4039 | need_change = 1; |
4040 | } | |
4041 | break; | |
4042 | default: | |
4043 | break; | |
4044 | } | |
4045 | } | |
a94ce333 | 4046 | |
826e3854 R |
4047 | if (need_change) |
4048 | { | |
4049 | for (i = 0; i < n_reloads; i++) | |
4050 | { | |
4051 | int first_num, type; | |
4052 | ||
eceef4c9 | 4053 | switch (rld[i].when_needed) |
826e3854 R |
4054 | { |
4055 | case RELOAD_FOR_OPADDR_ADDR: | |
4056 | first_num = first_op_addr_num; | |
4057 | type = RELOAD_FOR_OPERAND_ADDRESS; | |
4058 | break; | |
4059 | case RELOAD_FOR_INPADDR_ADDRESS: | |
eceef4c9 | 4060 | first_num = first_inpaddr_num[rld[i].opnum]; |
826e3854 R |
4061 | type = RELOAD_FOR_INPUT_ADDRESS; |
4062 | break; | |
4063 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
eceef4c9 | 4064 | first_num = first_outpaddr_num[rld[i].opnum]; |
826e3854 R |
4065 | type = RELOAD_FOR_OUTPUT_ADDRESS; |
4066 | break; | |
4067 | default: | |
4068 | continue; | |
4069 | } | |
c10638c9 R |
4070 | if (first_num < 0) |
4071 | continue; | |
4072 | else if (i > first_num) | |
eceef4c9 | 4073 | rld[i].when_needed = type; |
c10638c9 R |
4074 | else |
4075 | { | |
4076 | /* Check if the only TYPE reload that uses reload I is | |
4077 | reload FIRST_NUM. */ | |
4078 | for (j = n_reloads - 1; j > first_num; j--) | |
4079 | { | |
eceef4c9 BS |
4080 | if (rld[j].when_needed == type |
4081 | && (rld[i].secondary_p | |
4082 | ? rld[j].secondary_in_reload == i | |
4083 | : reg_mentioned_p (rld[i].in, rld[j].in))) | |
c10638c9 | 4084 | { |
eceef4c9 | 4085 | rld[i].when_needed = type; |
c10638c9 R |
4086 | break; |
4087 | } | |
4088 | } | |
4089 | } | |
826e3854 R |
4090 | } |
4091 | } | |
a94ce333 JW |
4092 | } |
4093 | ||
a8c9daeb RK |
4094 | /* See if we have any reloads that are now allowed to be merged |
4095 | because we've changed when the reload is needed to | |
4096 | RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only | |
4097 | check for the most common cases. */ | |
4098 | ||
4099 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
4100 | if (rld[i].in != 0 && rld[i].out == 0 |
4101 | && (rld[i].when_needed == RELOAD_FOR_OPERAND_ADDRESS | |
4102 | || rld[i].when_needed == RELOAD_FOR_OPADDR_ADDR | |
4103 | || rld[i].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
a8c9daeb | 4104 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
4105 | if (i != j && rld[j].in != 0 && rld[j].out == 0 |
4106 | && rld[j].when_needed == rld[i].when_needed | |
4107 | && MATCHES (rld[i].in, rld[j].in) | |
4108 | && rld[i].class == rld[j].class | |
4109 | && !rld[i].nocombine && !rld[j].nocombine | |
4110 | && rld[i].reg_rtx == rld[j].reg_rtx) | |
a8c9daeb | 4111 | { |
eceef4c9 | 4112 | rld[i].opnum = MIN (rld[i].opnum, rld[j].opnum); |
a8c9daeb | 4113 | transfer_replacements (i, j); |
eceef4c9 | 4114 | rld[j].in = 0; |
a8c9daeb RK |
4115 | } |
4116 | ||
f5963e61 JL |
4117 | /* Set which reloads must use registers not used in any group. Start |
4118 | with those that conflict with a group and then include ones that | |
4119 | conflict with ones that are already known to conflict with a group. */ | |
4120 | ||
4121 | changed = 0; | |
4122 | for (i = 0; i < n_reloads; i++) | |
4123 | { | |
eceef4c9 BS |
4124 | enum machine_mode mode = rld[i].inmode; |
4125 | enum reg_class class = rld[i].class; | |
f5963e61 JL |
4126 | int size; |
4127 | ||
eceef4c9 BS |
4128 | if (GET_MODE_SIZE (rld[i].outmode) > GET_MODE_SIZE (mode)) |
4129 | mode = rld[i].outmode; | |
f5963e61 JL |
4130 | size = CLASS_MAX_NREGS (class, mode); |
4131 | ||
4132 | if (size == 1) | |
4133 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
4134 | if ((CLASS_MAX_NREGS (rld[j].class, |
4135 | (GET_MODE_SIZE (rld[j].outmode) | |
4136 | > GET_MODE_SIZE (rld[j].inmode)) | |
4137 | ? rld[j].outmode : rld[j].inmode) | |
f5963e61 | 4138 | > 1) |
eceef4c9 BS |
4139 | && !rld[j].optional |
4140 | && (rld[j].in != 0 || rld[j].out != 0 | |
4141 | || rld[j].secondary_p) | |
f5963e61 | 4142 | && reloads_conflict (i, j) |
eceef4c9 | 4143 | && reg_classes_intersect_p (class, rld[j].class)) |
f5963e61 | 4144 | { |
eceef4c9 | 4145 | rld[i].nongroup = 1; |
f5963e61 JL |
4146 | changed = 1; |
4147 | break; | |
4148 | } | |
4149 | } | |
4150 | ||
4151 | while (changed) | |
4152 | { | |
4153 | changed = 0; | |
4154 | ||
4155 | for (i = 0; i < n_reloads; i++) | |
4156 | { | |
eceef4c9 BS |
4157 | enum machine_mode mode = rld[i].inmode; |
4158 | enum reg_class class = rld[i].class; | |
f5963e61 JL |
4159 | int size; |
4160 | ||
eceef4c9 BS |
4161 | if (GET_MODE_SIZE (rld[i].outmode) > GET_MODE_SIZE (mode)) |
4162 | mode = rld[i].outmode; | |
f5963e61 JL |
4163 | size = CLASS_MAX_NREGS (class, mode); |
4164 | ||
eceef4c9 | 4165 | if (! rld[i].nongroup && size == 1) |
f5963e61 | 4166 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 4167 | if (rld[j].nongroup |
f5963e61 | 4168 | && reloads_conflict (i, j) |
eceef4c9 | 4169 | && reg_classes_intersect_p (class, rld[j].class)) |
f5963e61 | 4170 | { |
eceef4c9 | 4171 | rld[i].nongroup = 1; |
f5963e61 JL |
4172 | changed = 1; |
4173 | break; | |
4174 | } | |
4175 | } | |
4176 | } | |
4177 | ||
eab89b90 RK |
4178 | #else /* no REGISTER_CONSTRAINTS */ |
4179 | int noperands; | |
4180 | int insn_code_number; | |
4181 | int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */ | |
4182 | register int i; | |
4183 | rtx body = PATTERN (insn); | |
cb2afeb3 | 4184 | int retval = 0; |
eab89b90 RK |
4185 | |
4186 | n_reloads = 0; | |
4187 | n_replacements = 0; | |
4188 | n_earlyclobbers = 0; | |
4189 | replace_reloads = replace; | |
4190 | this_insn = insn; | |
4191 | ||
0a578fee | 4192 | extract_insn (insn); |
eab89b90 | 4193 | |
1ccbefce | 4194 | noperands = reload_n_operands = recog_data.n_operands; |
eab89b90 | 4195 | |
0a578fee | 4196 | /* Return if the insn needs no reload processing. */ |
eab89b90 RK |
4197 | if (noperands == 0) |
4198 | return; | |
4199 | ||
4200 | for (i = 0; i < noperands; i++) | |
4201 | { | |
1ccbefce | 4202 | register RTX_CODE code = GET_CODE (recog_data.operand[i]); |
eab89b90 RK |
4203 | int is_set_dest = GET_CODE (body) == SET && (i == 0); |
4204 | ||
4205 | if (insn_code_number >= 0) | |
a995e389 | 4206 | if (insn_data[insn_code_number].operand[i].address_p) |
fb3821f7 | 4207 | find_reloads_address (VOIDmode, NULL_PTR, |
1ccbefce RH |
4208 | recog_data.operand[i], |
4209 | recog_data.operand_loc[i], | |
55c22565 | 4210 | i, RELOAD_FOR_INPUT, ind_levels, insn); |
a8c9daeb RK |
4211 | |
4212 | /* In these cases, we can't tell if the operand is an input | |
4213 | or an output, so be conservative. In practice it won't be | |
4214 | problem. */ | |
4215 | ||
eab89b90 | 4216 | if (code == MEM) |
1ccbefce RH |
4217 | find_reloads_address (GET_MODE (recog_data.operand[i]), |
4218 | recog_data.operand_loc[i], | |
4219 | XEXP (recog_data.operand[i], 0), | |
4220 | &XEXP (recog_data.operand[i], 0), | |
55c22565 | 4221 | i, RELOAD_OTHER, ind_levels, insn); |
eab89b90 | 4222 | if (code == SUBREG) |
1ccbefce RH |
4223 | recog_data.operand[i] = *recog_data.operand_loc[i] |
4224 | = find_reloads_toplev (recog_data.operand[i], i, RELOAD_OTHER, | |
a8c9daeb | 4225 | ind_levels, is_set_dest); |
eab89b90 RK |
4226 | if (code == REG) |
4227 | { | |
1ccbefce | 4228 | register int regno = REGNO (recog_data.operand[i]); |
eab89b90 | 4229 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) |
1ccbefce | 4230 | recog_data.operand[i] = *recog_data.operand_loc[i] |
eab89b90 RK |
4231 | = reg_equiv_constant[regno]; |
4232 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
4233 | that feeds this insn. */ | |
4234 | if (reg_equiv_mem[regno] != 0) | |
1ccbefce | 4235 | recog_data.operand[i] = *recog_data.operand_loc[i] |
eab89b90 RK |
4236 | = reg_equiv_mem[regno]; |
4237 | #endif | |
4238 | } | |
eab89b90 RK |
4239 | } |
4240 | ||
4241 | /* Perhaps an output reload can be combined with another | |
4242 | to reduce needs by one. */ | |
4243 | if (!goal_earlyclobber) | |
4244 | combine_reloads (); | |
a8c9daeb | 4245 | #endif /* no REGISTER_CONSTRAINTS */ |
cb2afeb3 | 4246 | return retval; |
eab89b90 RK |
4247 | } |
4248 | ||
4249 | /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT | |
4250 | accepts a memory operand with constant address. */ | |
4251 | ||
4252 | static int | |
4253 | alternative_allows_memconst (constraint, altnum) | |
9b3142b3 | 4254 | const char *constraint; |
eab89b90 RK |
4255 | int altnum; |
4256 | { | |
4257 | register int c; | |
4258 | /* Skip alternatives before the one requested. */ | |
4259 | while (altnum > 0) | |
4260 | { | |
4261 | while (*constraint++ != ','); | |
4262 | altnum--; | |
4263 | } | |
4264 | /* Scan the requested alternative for 'm' or 'o'. | |
4265 | If one of them is present, this alternative accepts memory constants. */ | |
4266 | while ((c = *constraint++) && c != ',' && c != '#') | |
4267 | if (c == 'm' || c == 'o') | |
4268 | return 1; | |
4269 | return 0; | |
4270 | } | |
4271 | \f | |
4272 | /* Scan X for memory references and scan the addresses for reloading. | |
4273 | Also checks for references to "constant" regs that we want to eliminate | |
4274 | and replaces them with the values they stand for. | |
6dc42e49 | 4275 | We may alter X destructively if it contains a reference to such. |
eab89b90 RK |
4276 | If X is just a constant reg, we return the equivalent value |
4277 | instead of X. | |
4278 | ||
4279 | IND_LEVELS says how many levels of indirect addressing this machine | |
4280 | supports. | |
4281 | ||
a8c9daeb RK |
4282 | OPNUM and TYPE identify the purpose of the reload. |
4283 | ||
eab89b90 | 4284 | IS_SET_DEST is true if X is the destination of a SET, which is not |
cb2afeb3 R |
4285 | appropriate to be replaced by a constant. |
4286 | ||
4287 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
4288 | to determine if we may generate output reloads, and where to put USEs | |
4289 | for pseudos that we have to replace with stack slots. */ | |
eab89b90 RK |
4290 | |
4291 | static rtx | |
cb2afeb3 | 4292 | find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest, insn) |
eab89b90 | 4293 | rtx x; |
a8c9daeb RK |
4294 | int opnum; |
4295 | enum reload_type type; | |
eab89b90 RK |
4296 | int ind_levels; |
4297 | int is_set_dest; | |
cb2afeb3 | 4298 | rtx insn; |
eab89b90 RK |
4299 | { |
4300 | register RTX_CODE code = GET_CODE (x); | |
4301 | ||
6f7d635c | 4302 | register const char *fmt = GET_RTX_FORMAT (code); |
eab89b90 | 4303 | register int i; |
9f4749b1 | 4304 | int copied; |
eab89b90 RK |
4305 | |
4306 | if (code == REG) | |
4307 | { | |
4308 | /* This code is duplicated for speed in find_reloads. */ | |
4309 | register int regno = REGNO (x); | |
4310 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
4311 | x = reg_equiv_constant[regno]; | |
4312 | #if 0 | |
05d10675 BS |
4313 | /* This creates (subreg (mem...)) which would cause an unnecessary |
4314 | reload of the mem. */ | |
eab89b90 RK |
4315 | else if (reg_equiv_mem[regno] != 0) |
4316 | x = reg_equiv_mem[regno]; | |
4317 | #endif | |
cb2afeb3 R |
4318 | else if (reg_equiv_memory_loc[regno] |
4319 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
eab89b90 | 4320 | { |
cb2afeb3 R |
4321 | rtx mem = make_memloc (x, regno); |
4322 | if (reg_equiv_address[regno] | |
4323 | || ! rtx_equal_p (mem, reg_equiv_mem[regno])) | |
4324 | { | |
4325 | /* If this is not a toplevel operand, find_reloads doesn't see | |
4326 | this substitution. We have to emit a USE of the pseudo so | |
4327 | that delete_output_reload can see it. */ | |
1ccbefce | 4328 | if (replace_reloads && recog_data.operand[opnum] != x) |
cb2afeb3 R |
4329 | emit_insn_before (gen_rtx_USE (VOIDmode, x), insn); |
4330 | x = mem; | |
4331 | find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0), | |
4332 | opnum, type, ind_levels, insn); | |
4333 | } | |
eab89b90 RK |
4334 | } |
4335 | return x; | |
4336 | } | |
4337 | if (code == MEM) | |
4338 | { | |
4339 | rtx tem = x; | |
4340 | find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
cb2afeb3 | 4341 | opnum, type, ind_levels, insn); |
eab89b90 RK |
4342 | return tem; |
4343 | } | |
4344 | ||
4345 | if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG) | |
4346 | { | |
05d10675 | 4347 | /* Check for SUBREG containing a REG that's equivalent to a constant. |
eab89b90 RK |
4348 | If the constant has a known value, truncate it right now. |
4349 | Similarly if we are extracting a single-word of a multi-word | |
4350 | constant. If the constant is symbolic, allow it to be substituted | |
4351 | normally. push_reload will strip the subreg later. If the | |
4352 | constant is VOIDmode, abort because we will lose the mode of | |
4353 | the register (this should never happen because one of the cases | |
4354 | above should handle it). */ | |
4355 | ||
4356 | register int regno = REGNO (SUBREG_REG (x)); | |
4357 | rtx tem; | |
4358 | ||
4359 | if (subreg_lowpart_p (x) | |
4360 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4361 | && reg_equiv_constant[regno] != 0 | |
4362 | && (tem = gen_lowpart_common (GET_MODE (x), | |
4363 | reg_equiv_constant[regno])) != 0) | |
4364 | return tem; | |
4365 | ||
4366 | if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD | |
4367 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4368 | && reg_equiv_constant[regno] != 0 | |
4369 | && (tem = operand_subword (reg_equiv_constant[regno], | |
4370 | SUBREG_WORD (x), 0, | |
4371 | GET_MODE (SUBREG_REG (x)))) != 0) | |
0365438d JL |
4372 | { |
4373 | /* TEM is now a word sized constant for the bits from X that | |
4374 | we wanted. However, TEM may be the wrong representation. | |
4375 | ||
4376 | Use gen_lowpart_common to convert a CONST_INT into a | |
4377 | CONST_DOUBLE and vice versa as needed according to by the mode | |
4378 | of the SUBREG. */ | |
4379 | tem = gen_lowpart_common (GET_MODE (x), tem); | |
4380 | if (!tem) | |
4381 | abort (); | |
4382 | return tem; | |
4383 | } | |
eab89b90 | 4384 | |
2fd0af53 R |
4385 | /* If the SUBREG is wider than a word, the above test will fail. |
4386 | For example, we might have a SImode SUBREG of a DImode SUBREG_REG | |
4387 | for a 16 bit target, or a DImode SUBREG of a TImode SUBREG_REG for | |
4388 | a 32 bit target. We still can - and have to - handle this | |
4389 | for non-paradoxical subregs of CONST_INTs. */ | |
4390 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4391 | && reg_equiv_constant[regno] != 0 | |
4392 | && GET_CODE (reg_equiv_constant[regno]) == CONST_INT | |
4393 | && (GET_MODE_SIZE (GET_MODE (x)) | |
4394 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
05d10675 BS |
4395 | { |
4396 | int shift = SUBREG_WORD (x) * BITS_PER_WORD; | |
4397 | if (WORDS_BIG_ENDIAN) | |
4398 | shift = (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) | |
4399 | - GET_MODE_BITSIZE (GET_MODE (x)) | |
4400 | - shift); | |
4401 | /* Here we use the knowledge that CONST_INTs have a | |
4402 | HOST_WIDE_INT field. */ | |
4403 | if (shift >= HOST_BITS_PER_WIDE_INT) | |
4404 | shift = HOST_BITS_PER_WIDE_INT - 1; | |
4405 | return GEN_INT (INTVAL (reg_equiv_constant[regno]) >> shift); | |
4406 | } | |
2fd0af53 | 4407 | |
eab89b90 RK |
4408 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 |
4409 | && reg_equiv_constant[regno] != 0 | |
4410 | && GET_MODE (reg_equiv_constant[regno]) == VOIDmode) | |
4411 | abort (); | |
4412 | ||
4413 | /* If the subreg contains a reg that will be converted to a mem, | |
4414 | convert the subreg to a narrower memref now. | |
4415 | Otherwise, we would get (subreg (mem ...) ...), | |
4416 | which would force reload of the mem. | |
4417 | ||
4418 | We also need to do this if there is an equivalent MEM that is | |
4419 | not offsettable. In that case, alter_subreg would produce an | |
4420 | invalid address on big-endian machines. | |
4421 | ||
46da6b3a | 4422 | For machines that extend byte loads, we must not reload using |
eab89b90 RK |
4423 | a wider mode if we have a paradoxical SUBREG. find_reloads will |
4424 | force a reload in that case. So we should not do anything here. */ | |
4425 | ||
4426 | else if (regno >= FIRST_PSEUDO_REGISTER | |
fd72420f | 4427 | #ifdef LOAD_EXTEND_OP |
eab89b90 RK |
4428 | && (GET_MODE_SIZE (GET_MODE (x)) |
4429 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
4430 | #endif | |
4431 | && (reg_equiv_address[regno] != 0 | |
4432 | || (reg_equiv_mem[regno] != 0 | |
05d10675 | 4433 | && (! strict_memory_address_p (GET_MODE (x), |
f2fbfe92 | 4434 | XEXP (reg_equiv_mem[regno], 0)) |
cb2afeb3 R |
4435 | || ! offsettable_memref_p (reg_equiv_mem[regno]) |
4436 | || num_not_at_initial_offset)))) | |
22505ad8 R |
4437 | x = find_reloads_subreg_address (x, 1, opnum, type, ind_levels, |
4438 | insn); | |
eab89b90 RK |
4439 | } |
4440 | ||
9f4749b1 | 4441 | for (copied = 0, i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
eab89b90 RK |
4442 | { |
4443 | if (fmt[i] == 'e') | |
9f4749b1 R |
4444 | { |
4445 | rtx new_part = find_reloads_toplev (XEXP (x, i), opnum, type, | |
4446 | ind_levels, is_set_dest, insn); | |
4447 | /* If we have replaced a reg with it's equivalent memory loc - | |
4448 | that can still be handled here e.g. if it's in a paradoxical | |
4449 | subreg - we must make the change in a copy, rather than using | |
4450 | a destructive change. This way, find_reloads can still elect | |
4451 | not to do the change. */ | |
4452 | if (new_part != XEXP (x, i) && ! CONSTANT_P (new_part) && ! copied) | |
4453 | { | |
ce9d4c6d | 4454 | x = shallow_copy_rtx (x); |
9f4749b1 R |
4455 | copied = 1; |
4456 | } | |
4457 | XEXP (x, i) = new_part; | |
4458 | } | |
eab89b90 RK |
4459 | } |
4460 | return x; | |
4461 | } | |
4462 | ||
dbf85761 RS |
4463 | /* Return a mem ref for the memory equivalent of reg REGNO. |
4464 | This mem ref is not shared with anything. */ | |
4465 | ||
eab89b90 RK |
4466 | static rtx |
4467 | make_memloc (ad, regno) | |
4468 | rtx ad; | |
4469 | int regno; | |
4470 | { | |
4ffeab02 JW |
4471 | /* We must rerun eliminate_regs, in case the elimination |
4472 | offsets have changed. */ | |
cb2afeb3 R |
4473 | rtx tem |
4474 | = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, NULL_RTX), 0); | |
eab89b90 RK |
4475 | |
4476 | /* If TEM might contain a pseudo, we must copy it to avoid | |
4477 | modifying it when we do the substitution for the reload. */ | |
4478 | if (rtx_varies_p (tem)) | |
4479 | tem = copy_rtx (tem); | |
4480 | ||
38a448ca | 4481 | tem = gen_rtx_MEM (GET_MODE (ad), tem); |
eab89b90 | 4482 | RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); |
eab89b90 RK |
4483 | return tem; |
4484 | } | |
4485 | ||
4486 | /* Record all reloads needed for handling memory address AD | |
4487 | which appears in *LOC in a memory reference to mode MODE | |
4488 | which itself is found in location *MEMREFLOC. | |
4489 | Note that we take shortcuts assuming that no multi-reg machine mode | |
4490 | occurs as part of an address. | |
4491 | ||
a8c9daeb | 4492 | OPNUM and TYPE specify the purpose of this reload. |
eab89b90 RK |
4493 | |
4494 | IND_LEVELS says how many levels of indirect addressing this machine | |
4495 | supports. | |
4496 | ||
55c22565 | 4497 | INSN, if nonzero, is the insn in which we do the reload. It is used |
cb2afeb3 R |
4498 | to determine if we may generate output reloads, and where to put USEs |
4499 | for pseudos that we have to replace with stack slots. | |
55c22565 | 4500 | |
eab89b90 RK |
4501 | Value is nonzero if this address is reloaded or replaced as a whole. |
4502 | This is interesting to the caller if the address is an autoincrement. | |
4503 | ||
4504 | Note that there is no verification that the address will be valid after | |
4505 | this routine does its work. Instead, we rely on the fact that the address | |
4506 | was valid when reload started. So we need only undo things that reload | |
4507 | could have broken. These are wrong register types, pseudos not allocated | |
4508 | to a hard register, and frame pointer elimination. */ | |
4509 | ||
4510 | static int | |
55c22565 | 4511 | find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels, insn) |
eab89b90 RK |
4512 | enum machine_mode mode; |
4513 | rtx *memrefloc; | |
4514 | rtx ad; | |
4515 | rtx *loc; | |
a8c9daeb RK |
4516 | int opnum; |
4517 | enum reload_type type; | |
eab89b90 | 4518 | int ind_levels; |
55c22565 | 4519 | rtx insn; |
eab89b90 RK |
4520 | { |
4521 | register int regno; | |
ab87f8c8 | 4522 | int removed_and = 0; |
eab89b90 RK |
4523 | rtx tem; |
4524 | ||
4525 | /* If the address is a register, see if it is a legitimate address and | |
4526 | reload if not. We first handle the cases where we need not reload | |
4527 | or where we must reload in a non-standard way. */ | |
4528 | ||
4529 | if (GET_CODE (ad) == REG) | |
4530 | { | |
4531 | regno = REGNO (ad); | |
4532 | ||
4533 | if (reg_equiv_constant[regno] != 0 | |
4534 | && strict_memory_address_p (mode, reg_equiv_constant[regno])) | |
4535 | { | |
4536 | *loc = ad = reg_equiv_constant[regno]; | |
ab87f8c8 | 4537 | return 0; |
eab89b90 RK |
4538 | } |
4539 | ||
cb2afeb3 R |
4540 | tem = reg_equiv_memory_loc[regno]; |
4541 | if (tem != 0) | |
eab89b90 | 4542 | { |
cb2afeb3 R |
4543 | if (reg_equiv_address[regno] != 0 || num_not_at_initial_offset) |
4544 | { | |
4545 | tem = make_memloc (ad, regno); | |
4546 | if (! strict_memory_address_p (GET_MODE (tem), XEXP (tem, 0))) | |
4547 | { | |
4548 | find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0), | |
4549 | &XEXP (tem, 0), opnum, ADDR_TYPE (type), | |
4550 | ind_levels, insn); | |
4551 | } | |
4552 | /* We can avoid a reload if the register's equivalent memory | |
4553 | expression is valid as an indirect memory address. | |
4554 | But not all addresses are valid in a mem used as an indirect | |
4555 | address: only reg or reg+constant. */ | |
4556 | ||
4557 | if (ind_levels > 0 | |
4558 | && strict_memory_address_p (mode, tem) | |
4559 | && (GET_CODE (XEXP (tem, 0)) == REG | |
4560 | || (GET_CODE (XEXP (tem, 0)) == PLUS | |
4561 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG | |
4562 | && CONSTANT_P (XEXP (XEXP (tem, 0), 1))))) | |
4563 | { | |
4564 | /* TEM is not the same as what we'll be replacing the | |
4565 | pseudo with after reload, put a USE in front of INSN | |
4566 | in the final reload pass. */ | |
4567 | if (replace_reloads | |
4568 | && num_not_at_initial_offset | |
4569 | && ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
4570 | { | |
4571 | *loc = tem; | |
4572 | emit_insn_before (gen_rtx_USE (VOIDmode, ad), insn); | |
4573 | /* This doesn't really count as replacing the address | |
4574 | as a whole, since it is still a memory access. */ | |
4575 | } | |
4576 | return 0; | |
4577 | } | |
4578 | ad = tem; | |
4579 | } | |
eab89b90 RK |
4580 | } |
4581 | ||
eab89b90 RK |
4582 | /* The only remaining case where we can avoid a reload is if this is a |
4583 | hard register that is valid as a base register and which is not the | |
4584 | subject of a CLOBBER in this insn. */ | |
4585 | ||
858c3c8c ILT |
4586 | else if (regno < FIRST_PSEUDO_REGISTER |
4587 | && REGNO_MODE_OK_FOR_BASE_P (regno, mode) | |
eab89b90 RK |
4588 | && ! regno_clobbered_p (regno, this_insn)) |
4589 | return 0; | |
4590 | ||
4591 | /* If we do not have one of the cases above, we must do the reload. */ | |
03acd8f8 | 4592 | push_reload (ad, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, |
a8c9daeb | 4593 | GET_MODE (ad), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4594 | return 1; |
4595 | } | |
4596 | ||
4597 | if (strict_memory_address_p (mode, ad)) | |
4598 | { | |
4599 | /* The address appears valid, so reloads are not needed. | |
4600 | But the address may contain an eliminable register. | |
4601 | This can happen because a machine with indirect addressing | |
4602 | may consider a pseudo register by itself a valid address even when | |
4603 | it has failed to get a hard reg. | |
4604 | So do a tree-walk to find and eliminate all such regs. */ | |
4605 | ||
4606 | /* But first quickly dispose of a common case. */ | |
4607 | if (GET_CODE (ad) == PLUS | |
4608 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4609 | && GET_CODE (XEXP (ad, 0)) == REG | |
4610 | && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) | |
4611 | return 0; | |
4612 | ||
4613 | subst_reg_equivs_changed = 0; | |
cb2afeb3 | 4614 | *loc = subst_reg_equivs (ad, insn); |
eab89b90 RK |
4615 | |
4616 | if (! subst_reg_equivs_changed) | |
4617 | return 0; | |
4618 | ||
4619 | /* Check result for validity after substitution. */ | |
4620 | if (strict_memory_address_p (mode, ad)) | |
4621 | return 0; | |
4622 | } | |
4623 | ||
a9a2595b JR |
4624 | #ifdef LEGITIMIZE_RELOAD_ADDRESS |
4625 | do | |
4626 | { | |
4627 | if (memrefloc) | |
4628 | { | |
4629 | LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type, | |
4630 | ind_levels, win); | |
4631 | } | |
4632 | break; | |
4633 | win: | |
4634 | *memrefloc = copy_rtx (*memrefloc); | |
4635 | XEXP (*memrefloc, 0) = ad; | |
4636 | move_replacements (&ad, &XEXP (*memrefloc, 0)); | |
4637 | return 1; | |
4638 | } | |
4639 | while (0); | |
4640 | #endif | |
4641 | ||
ab87f8c8 JL |
4642 | /* The address is not valid. We have to figure out why. First see if |
4643 | we have an outer AND and remove it if so. Then analyze what's inside. */ | |
4644 | ||
4645 | if (GET_CODE (ad) == AND) | |
4646 | { | |
4647 | removed_and = 1; | |
4648 | loc = &XEXP (ad, 0); | |
4649 | ad = *loc; | |
4650 | } | |
4651 | ||
4652 | /* One possibility for why the address is invalid is that it is itself | |
4653 | a MEM. This can happen when the frame pointer is being eliminated, a | |
4654 | pseudo is not allocated to a hard register, and the offset between the | |
4655 | frame and stack pointers is not its initial value. In that case the | |
4656 | pseudo will have been replaced by a MEM referring to the | |
4657 | stack pointer. */ | |
eab89b90 RK |
4658 | if (GET_CODE (ad) == MEM) |
4659 | { | |
4660 | /* First ensure that the address in this MEM is valid. Then, unless | |
4661 | indirect addresses are valid, reload the MEM into a register. */ | |
4662 | tem = ad; | |
4663 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
47c8cf91 | 4664 | opnum, ADDR_TYPE (type), |
55c22565 | 4665 | ind_levels == 0 ? 0 : ind_levels - 1, insn); |
d2555454 RS |
4666 | |
4667 | /* If tem was changed, then we must create a new memory reference to | |
4668 | hold it and store it back into memrefloc. */ | |
4669 | if (tem != ad && memrefloc) | |
ca3e4a2f | 4670 | { |
ca3e4a2f | 4671 | *memrefloc = copy_rtx (*memrefloc); |
3c80f7ed | 4672 | copy_replacements (tem, XEXP (*memrefloc, 0)); |
ca3e4a2f | 4673 | loc = &XEXP (*memrefloc, 0); |
ab87f8c8 JL |
4674 | if (removed_and) |
4675 | loc = &XEXP (*loc, 0); | |
ca3e4a2f | 4676 | } |
d2555454 | 4677 | |
eab89b90 RK |
4678 | /* Check similar cases as for indirect addresses as above except |
4679 | that we can allow pseudos and a MEM since they should have been | |
4680 | taken care of above. */ | |
4681 | ||
4682 | if (ind_levels == 0 | |
4683 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
4684 | || GET_CODE (XEXP (tem, 0)) == MEM | |
4685 | || ! (GET_CODE (XEXP (tem, 0)) == REG | |
4686 | || (GET_CODE (XEXP (tem, 0)) == PLUS | |
4687 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG | |
4688 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) | |
4689 | { | |
4690 | /* Must use TEM here, not AD, since it is the one that will | |
4691 | have any subexpressions reloaded, if needed. */ | |
fb3821f7 | 4692 | push_reload (tem, NULL_RTX, loc, NULL_PTR, |
03acd8f8 | 4693 | BASE_REG_CLASS, GET_MODE (tem), |
1ba61f4e | 4694 | VOIDmode, 0, |
a8c9daeb | 4695 | 0, opnum, type); |
ab87f8c8 | 4696 | return ! removed_and; |
eab89b90 RK |
4697 | } |
4698 | else | |
4699 | return 0; | |
4700 | } | |
4701 | ||
1b4d2764 RK |
4702 | /* If we have address of a stack slot but it's not valid because the |
4703 | displacement is too large, compute the sum in a register. | |
4704 | Handle all base registers here, not just fp/ap/sp, because on some | |
4705 | targets (namely SH) we can also get too large displacements from | |
4706 | big-endian corrections. */ | |
eab89b90 | 4707 | else if (GET_CODE (ad) == PLUS |
1b4d2764 RK |
4708 | && GET_CODE (XEXP (ad, 0)) == REG |
4709 | && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER | |
858c3c8c | 4710 | && REG_MODE_OK_FOR_BASE_P (XEXP (ad, 0), mode) |
eab89b90 RK |
4711 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) |
4712 | { | |
4713 | /* Unshare the MEM rtx so we can safely alter it. */ | |
4714 | if (memrefloc) | |
4715 | { | |
eab89b90 RK |
4716 | *memrefloc = copy_rtx (*memrefloc); |
4717 | loc = &XEXP (*memrefloc, 0); | |
ab87f8c8 JL |
4718 | if (removed_and) |
4719 | loc = &XEXP (*loc, 0); | |
eab89b90 | 4720 | } |
ab87f8c8 | 4721 | |
eab89b90 RK |
4722 | if (double_reg_address_ok) |
4723 | { | |
4724 | /* Unshare the sum as well. */ | |
4725 | *loc = ad = copy_rtx (ad); | |
ab87f8c8 | 4726 | |
eab89b90 RK |
4727 | /* Reload the displacement into an index reg. |
4728 | We assume the frame pointer or arg pointer is a base reg. */ | |
4729 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
03acd8f8 BS |
4730 | INDEX_REG_CLASS, GET_MODE (ad), opnum, |
4731 | type, ind_levels); | |
ab87f8c8 | 4732 | return 0; |
eab89b90 RK |
4733 | } |
4734 | else | |
4735 | { | |
4736 | /* If the sum of two regs is not necessarily valid, | |
4737 | reload the sum into a base reg. | |
4738 | That will at least work. */ | |
03acd8f8 | 4739 | find_reloads_address_part (ad, loc, BASE_REG_CLASS, |
1ba61f4e | 4740 | Pmode, opnum, type, ind_levels); |
eab89b90 | 4741 | } |
ab87f8c8 | 4742 | return ! removed_and; |
eab89b90 RK |
4743 | } |
4744 | ||
4745 | /* If we have an indexed stack slot, there are three possible reasons why | |
4746 | it might be invalid: The index might need to be reloaded, the address | |
4747 | might have been made by frame pointer elimination and hence have a | |
05d10675 | 4748 | constant out of range, or both reasons might apply. |
eab89b90 RK |
4749 | |
4750 | We can easily check for an index needing reload, but even if that is the | |
4751 | case, we might also have an invalid constant. To avoid making the | |
4752 | conservative assumption and requiring two reloads, we see if this address | |
4753 | is valid when not interpreted strictly. If it is, the only problem is | |
4754 | that the index needs a reload and find_reloads_address_1 will take care | |
4755 | of it. | |
4756 | ||
4757 | There is still a case when we might generate an extra reload, | |
4758 | however. In certain cases eliminate_regs will return a MEM for a REG | |
4759 | (see the code there for details). In those cases, memory_address_p | |
4760 | applied to our address will return 0 so we will think that our offset | |
4761 | must be too large. But it might indeed be valid and the only problem | |
4762 | is that a MEM is present where a REG should be. This case should be | |
4763 | very rare and there doesn't seem to be any way to avoid it. | |
4764 | ||
4765 | If we decide to do something here, it must be that | |
4766 | `double_reg_address_ok' is true and that this address rtl was made by | |
4767 | eliminate_regs. We generate a reload of the fp/sp/ap + constant and | |
4768 | rework the sum so that the reload register will be added to the index. | |
4769 | This is safe because we know the address isn't shared. | |
4770 | ||
4771 | We check for fp/ap/sp as both the first and second operand of the | |
4772 | innermost PLUS. */ | |
4773 | ||
4774 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
f302eea3 | 4775 | && GET_CODE (XEXP (ad, 0)) == PLUS |
eab89b90 | 4776 | && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx |
a36d4c62 DE |
4777 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
4778 | || XEXP (XEXP (ad, 0), 0) == hard_frame_pointer_rtx | |
4779 | #endif | |
eab89b90 RK |
4780 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
4781 | || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx | |
4782 | #endif | |
4783 | || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx) | |
4784 | && ! memory_address_p (mode, ad)) | |
4785 | { | |
38a448ca RH |
4786 | *loc = ad = gen_rtx_PLUS (GET_MODE (ad), |
4787 | plus_constant (XEXP (XEXP (ad, 0), 0), | |
4788 | INTVAL (XEXP (ad, 1))), | |
05d10675 | 4789 | XEXP (XEXP (ad, 0), 1)); |
03acd8f8 | 4790 | find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, |
a8c9daeb | 4791 | GET_MODE (ad), opnum, type, ind_levels); |
858c3c8c | 4792 | find_reloads_address_1 (mode, XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, |
55c22565 | 4793 | type, 0, insn); |
eab89b90 | 4794 | |
ab87f8c8 | 4795 | return 0; |
eab89b90 | 4796 | } |
05d10675 | 4797 | |
eab89b90 RK |
4798 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT |
4799 | && GET_CODE (XEXP (ad, 0)) == PLUS | |
4800 | && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx | |
a36d4c62 DE |
4801 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
4802 | || XEXP (XEXP (ad, 0), 1) == hard_frame_pointer_rtx | |
4803 | #endif | |
eab89b90 RK |
4804 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
4805 | || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx | |
4806 | #endif | |
4807 | || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx) | |
4808 | && ! memory_address_p (mode, ad)) | |
4809 | { | |
38a448ca RH |
4810 | *loc = ad = gen_rtx_PLUS (GET_MODE (ad), |
4811 | XEXP (XEXP (ad, 0), 0), | |
4812 | plus_constant (XEXP (XEXP (ad, 0), 1), | |
4813 | INTVAL (XEXP (ad, 1)))); | |
03acd8f8 | 4814 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), BASE_REG_CLASS, |
a8c9daeb | 4815 | GET_MODE (ad), opnum, type, ind_levels); |
858c3c8c | 4816 | find_reloads_address_1 (mode, XEXP (ad, 0), 1, &XEXP (ad, 0), opnum, |
55c22565 | 4817 | type, 0, insn); |
eab89b90 | 4818 | |
ab87f8c8 | 4819 | return 0; |
eab89b90 | 4820 | } |
05d10675 | 4821 | |
eab89b90 RK |
4822 | /* See if address becomes valid when an eliminable register |
4823 | in a sum is replaced. */ | |
4824 | ||
4825 | tem = ad; | |
4826 | if (GET_CODE (ad) == PLUS) | |
4827 | tem = subst_indexed_address (ad); | |
4828 | if (tem != ad && strict_memory_address_p (mode, tem)) | |
4829 | { | |
4830 | /* Ok, we win that way. Replace any additional eliminable | |
4831 | registers. */ | |
4832 | ||
4833 | subst_reg_equivs_changed = 0; | |
cb2afeb3 | 4834 | tem = subst_reg_equivs (tem, insn); |
eab89b90 RK |
4835 | |
4836 | /* Make sure that didn't make the address invalid again. */ | |
4837 | ||
4838 | if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) | |
4839 | { | |
4840 | *loc = tem; | |
4841 | return 0; | |
4842 | } | |
4843 | } | |
4844 | ||
4845 | /* If constants aren't valid addresses, reload the constant address | |
4846 | into a register. */ | |
191b18e9 | 4847 | if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) |
eab89b90 RK |
4848 | { |
4849 | /* If AD is in address in the constant pool, the MEM rtx may be shared. | |
4850 | Unshare it so we can safely alter it. */ | |
4851 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
4852 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
4853 | { | |
eab89b90 RK |
4854 | *memrefloc = copy_rtx (*memrefloc); |
4855 | loc = &XEXP (*memrefloc, 0); | |
ab87f8c8 JL |
4856 | if (removed_and) |
4857 | loc = &XEXP (*loc, 0); | |
eab89b90 RK |
4858 | } |
4859 | ||
03acd8f8 | 4860 | find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, opnum, type, |
eab89b90 | 4861 | ind_levels); |
ab87f8c8 | 4862 | return ! removed_and; |
eab89b90 RK |
4863 | } |
4864 | ||
55c22565 RK |
4865 | return find_reloads_address_1 (mode, ad, 0, loc, opnum, type, ind_levels, |
4866 | insn); | |
eab89b90 RK |
4867 | } |
4868 | \f | |
4869 | /* Find all pseudo regs appearing in AD | |
4870 | that are eliminable in favor of equivalent values | |
cb2afeb3 R |
4871 | and do not have hard regs; replace them by their equivalents. |
4872 | INSN, if nonzero, is the insn in which we do the reload. We put USEs in | |
4873 | front of it for pseudos that we have to replace with stack slots. */ | |
eab89b90 RK |
4874 | |
4875 | static rtx | |
cb2afeb3 | 4876 | subst_reg_equivs (ad, insn) |
eab89b90 | 4877 | rtx ad; |
cb2afeb3 | 4878 | rtx insn; |
eab89b90 RK |
4879 | { |
4880 | register RTX_CODE code = GET_CODE (ad); | |
4881 | register int i; | |
6f7d635c | 4882 | register const char *fmt; |
eab89b90 RK |
4883 | |
4884 | switch (code) | |
4885 | { | |
4886 | case HIGH: | |
4887 | case CONST_INT: | |
4888 | case CONST: | |
4889 | case CONST_DOUBLE: | |
4890 | case SYMBOL_REF: | |
4891 | case LABEL_REF: | |
4892 | case PC: | |
4893 | case CC0: | |
4894 | return ad; | |
4895 | ||
4896 | case REG: | |
4897 | { | |
4898 | register int regno = REGNO (ad); | |
4899 | ||
4900 | if (reg_equiv_constant[regno] != 0) | |
4901 | { | |
4902 | subst_reg_equivs_changed = 1; | |
4903 | return reg_equiv_constant[regno]; | |
4904 | } | |
cb2afeb3 R |
4905 | if (reg_equiv_memory_loc[regno] && num_not_at_initial_offset) |
4906 | { | |
4907 | rtx mem = make_memloc (ad, regno); | |
4908 | if (! rtx_equal_p (mem, reg_equiv_mem[regno])) | |
4909 | { | |
4910 | subst_reg_equivs_changed = 1; | |
4911 | emit_insn_before (gen_rtx_USE (VOIDmode, ad), insn); | |
4912 | return mem; | |
4913 | } | |
4914 | } | |
eab89b90 RK |
4915 | } |
4916 | return ad; | |
4917 | ||
4918 | case PLUS: | |
4919 | /* Quickly dispose of a common case. */ | |
4920 | if (XEXP (ad, 0) == frame_pointer_rtx | |
4921 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
4922 | return ad; | |
e9a25f70 | 4923 | break; |
05d10675 | 4924 | |
e9a25f70 JL |
4925 | default: |
4926 | break; | |
eab89b90 RK |
4927 | } |
4928 | ||
4929 | fmt = GET_RTX_FORMAT (code); | |
4930 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4931 | if (fmt[i] == 'e') | |
cb2afeb3 | 4932 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i), insn); |
eab89b90 RK |
4933 | return ad; |
4934 | } | |
4935 | \f | |
4936 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
4937 | address, namely: sum constant integers, surround the sum of two | |
4938 | constants with a CONST, put the constant as the second operand, and | |
4939 | group the constant on the outermost sum. | |
4940 | ||
4941 | This routine assumes both inputs are already in canonical form. */ | |
4942 | ||
4943 | rtx | |
4944 | form_sum (x, y) | |
4945 | rtx x, y; | |
4946 | { | |
4947 | rtx tem; | |
2c0623e8 RK |
4948 | enum machine_mode mode = GET_MODE (x); |
4949 | ||
4950 | if (mode == VOIDmode) | |
4951 | mode = GET_MODE (y); | |
4952 | ||
4953 | if (mode == VOIDmode) | |
4954 | mode = Pmode; | |
eab89b90 RK |
4955 | |
4956 | if (GET_CODE (x) == CONST_INT) | |
4957 | return plus_constant (y, INTVAL (x)); | |
4958 | else if (GET_CODE (y) == CONST_INT) | |
4959 | return plus_constant (x, INTVAL (y)); | |
4960 | else if (CONSTANT_P (x)) | |
4961 | tem = x, x = y, y = tem; | |
4962 | ||
4963 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
4964 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
4965 | ||
4966 | /* Note that if the operands of Y are specified in the opposite | |
4967 | order in the recursive calls below, infinite recursion will occur. */ | |
d9771f62 | 4968 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) |
eab89b90 RK |
4969 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); |
4970 | ||
4971 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
4972 | constant will have been placed second. */ | |
4973 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
4974 | { | |
4975 | if (GET_CODE (x) == CONST) | |
4976 | x = XEXP (x, 0); | |
4977 | if (GET_CODE (y) == CONST) | |
4978 | y = XEXP (y, 0); | |
4979 | ||
38a448ca | 4980 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); |
eab89b90 RK |
4981 | } |
4982 | ||
38a448ca | 4983 | return gen_rtx_PLUS (mode, x, y); |
eab89b90 RK |
4984 | } |
4985 | \f | |
4986 | /* If ADDR is a sum containing a pseudo register that should be | |
4987 | replaced with a constant (from reg_equiv_constant), | |
4988 | return the result of doing so, and also apply the associative | |
4989 | law so that the result is more likely to be a valid address. | |
4990 | (But it is not guaranteed to be one.) | |
4991 | ||
4992 | Note that at most one register is replaced, even if more are | |
4993 | replaceable. Also, we try to put the result into a canonical form | |
4994 | so it is more likely to be a valid address. | |
4995 | ||
4996 | In all other cases, return ADDR. */ | |
4997 | ||
4998 | static rtx | |
4999 | subst_indexed_address (addr) | |
5000 | rtx addr; | |
5001 | { | |
5002 | rtx op0 = 0, op1 = 0, op2 = 0; | |
5003 | rtx tem; | |
5004 | int regno; | |
5005 | ||
5006 | if (GET_CODE (addr) == PLUS) | |
5007 | { | |
5008 | /* Try to find a register to replace. */ | |
5009 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
5010 | if (GET_CODE (op0) == REG | |
5011 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER | |
5012 | && reg_renumber[regno] < 0 | |
5013 | && reg_equiv_constant[regno] != 0) | |
5014 | op0 = reg_equiv_constant[regno]; | |
5015 | else if (GET_CODE (op1) == REG | |
05d10675 BS |
5016 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER |
5017 | && reg_renumber[regno] < 0 | |
5018 | && reg_equiv_constant[regno] != 0) | |
eab89b90 RK |
5019 | op1 = reg_equiv_constant[regno]; |
5020 | else if (GET_CODE (op0) == PLUS | |
5021 | && (tem = subst_indexed_address (op0)) != op0) | |
5022 | op0 = tem; | |
5023 | else if (GET_CODE (op1) == PLUS | |
5024 | && (tem = subst_indexed_address (op1)) != op1) | |
5025 | op1 = tem; | |
5026 | else | |
5027 | return addr; | |
5028 | ||
5029 | /* Pick out up to three things to add. */ | |
5030 | if (GET_CODE (op1) == PLUS) | |
5031 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
5032 | else if (GET_CODE (op0) == PLUS) | |
5033 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
5034 | ||
5035 | /* Compute the sum. */ | |
5036 | if (op2 != 0) | |
5037 | op1 = form_sum (op1, op2); | |
5038 | if (op1 != 0) | |
5039 | op0 = form_sum (op0, op1); | |
5040 | ||
5041 | return op0; | |
5042 | } | |
5043 | return addr; | |
5044 | } | |
5045 | \f | |
858c3c8c ILT |
5046 | /* Record the pseudo registers we must reload into hard registers in a |
5047 | subexpression of a would-be memory address, X referring to a value | |
5048 | in mode MODE. (This function is not called if the address we find | |
5049 | is strictly valid.) | |
5050 | ||
eab89b90 RK |
5051 | CONTEXT = 1 means we are considering regs as index regs, |
5052 | = 0 means we are considering them as base regs. | |
5053 | ||
a8c9daeb | 5054 | OPNUM and TYPE specify the purpose of any reloads made. |
eab89b90 RK |
5055 | |
5056 | IND_LEVELS says how many levels of indirect addressing are | |
5057 | supported at this point in the address. | |
5058 | ||
55c22565 RK |
5059 | INSN, if nonzero, is the insn in which we do the reload. It is used |
5060 | to determine if we may generate output reloads. | |
5061 | ||
eab89b90 RK |
5062 | We return nonzero if X, as a whole, is reloaded or replaced. */ |
5063 | ||
5064 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
5065 | occurs as part of an address. | |
5066 | Also, this is not fully machine-customizable; it works for machines | |
5067 | such as vaxes and 68000's and 32000's, but other possible machines | |
5068 | could have addressing modes that this does not handle right. */ | |
5069 | ||
5070 | static int | |
55c22565 | 5071 | find_reloads_address_1 (mode, x, context, loc, opnum, type, ind_levels, insn) |
858c3c8c | 5072 | enum machine_mode mode; |
eab89b90 RK |
5073 | rtx x; |
5074 | int context; | |
5075 | rtx *loc; | |
a8c9daeb RK |
5076 | int opnum; |
5077 | enum reload_type type; | |
eab89b90 | 5078 | int ind_levels; |
55c22565 | 5079 | rtx insn; |
eab89b90 RK |
5080 | { |
5081 | register RTX_CODE code = GET_CODE (x); | |
5082 | ||
a2d353e5 | 5083 | switch (code) |
eab89b90 | 5084 | { |
a2d353e5 RK |
5085 | case PLUS: |
5086 | { | |
5087 | register rtx orig_op0 = XEXP (x, 0); | |
5088 | register rtx orig_op1 = XEXP (x, 1); | |
5089 | register RTX_CODE code0 = GET_CODE (orig_op0); | |
5090 | register RTX_CODE code1 = GET_CODE (orig_op1); | |
5091 | register rtx op0 = orig_op0; | |
5092 | register rtx op1 = orig_op1; | |
5093 | ||
5094 | if (GET_CODE (op0) == SUBREG) | |
5095 | { | |
5096 | op0 = SUBREG_REG (op0); | |
5097 | code0 = GET_CODE (op0); | |
922db4bb | 5098 | if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER) |
38a448ca RH |
5099 | op0 = gen_rtx_REG (word_mode, |
5100 | REGNO (op0) + SUBREG_WORD (orig_op0)); | |
a2d353e5 | 5101 | } |
87935f60 | 5102 | |
a2d353e5 RK |
5103 | if (GET_CODE (op1) == SUBREG) |
5104 | { | |
5105 | op1 = SUBREG_REG (op1); | |
5106 | code1 = GET_CODE (op1); | |
922db4bb | 5107 | if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER) |
38a448ca RH |
5108 | op1 = gen_rtx_REG (GET_MODE (op1), |
5109 | REGNO (op1) + SUBREG_WORD (orig_op1)); | |
a2d353e5 RK |
5110 | } |
5111 | ||
05d10675 | 5112 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
5f8997b9 | 5113 | || code0 == ZERO_EXTEND || code1 == MEM) |
a2d353e5 | 5114 | { |
858c3c8c | 5115 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 5116 | type, ind_levels, insn); |
858c3c8c | 5117 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5118 | type, ind_levels, insn); |
a2d353e5 RK |
5119 | } |
5120 | ||
5f8997b9 SC |
5121 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE |
5122 | || code1 == ZERO_EXTEND || code0 == MEM) | |
a2d353e5 | 5123 | { |
858c3c8c | 5124 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 5125 | type, ind_levels, insn); |
858c3c8c | 5126 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, |
55c22565 | 5127 | type, ind_levels, insn); |
a2d353e5 RK |
5128 | } |
5129 | ||
5130 | else if (code0 == CONST_INT || code0 == CONST | |
5131 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
858c3c8c | 5132 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5133 | type, ind_levels, insn); |
a2d353e5 RK |
5134 | |
5135 | else if (code1 == CONST_INT || code1 == CONST | |
5136 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
858c3c8c | 5137 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 5138 | type, ind_levels, insn); |
a2d353e5 RK |
5139 | |
5140 | else if (code0 == REG && code1 == REG) | |
5141 | { | |
5142 | if (REG_OK_FOR_INDEX_P (op0) | |
858c3c8c | 5143 | && REG_MODE_OK_FOR_BASE_P (op1, mode)) |
a2d353e5 RK |
5144 | return 0; |
5145 | else if (REG_OK_FOR_INDEX_P (op1) | |
858c3c8c | 5146 | && REG_MODE_OK_FOR_BASE_P (op0, mode)) |
a2d353e5 | 5147 | return 0; |
858c3c8c ILT |
5148 | else if (REG_MODE_OK_FOR_BASE_P (op1, mode)) |
5149 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, | |
55c22565 | 5150 | type, ind_levels, insn); |
858c3c8c ILT |
5151 | else if (REG_MODE_OK_FOR_BASE_P (op0, mode)) |
5152 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, | |
55c22565 | 5153 | type, ind_levels, insn); |
a2d353e5 | 5154 | else if (REG_OK_FOR_INDEX_P (op1)) |
858c3c8c | 5155 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 5156 | type, ind_levels, insn); |
a2d353e5 | 5157 | else if (REG_OK_FOR_INDEX_P (op0)) |
858c3c8c | 5158 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5159 | type, ind_levels, insn); |
a2d353e5 RK |
5160 | else |
5161 | { | |
858c3c8c | 5162 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 5163 | type, ind_levels, insn); |
858c3c8c | 5164 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5165 | type, ind_levels, insn); |
a2d353e5 RK |
5166 | } |
5167 | } | |
5168 | ||
5169 | else if (code0 == REG) | |
5170 | { | |
858c3c8c | 5171 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 5172 | type, ind_levels, insn); |
858c3c8c | 5173 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5174 | type, ind_levels, insn); |
a2d353e5 RK |
5175 | } |
5176 | ||
5177 | else if (code1 == REG) | |
5178 | { | |
858c3c8c | 5179 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, |
55c22565 | 5180 | type, ind_levels, insn); |
858c3c8c | 5181 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 5182 | type, ind_levels, insn); |
a2d353e5 RK |
5183 | } |
5184 | } | |
5185 | ||
5186 | return 0; | |
5187 | ||
5188 | case POST_INC: | |
5189 | case POST_DEC: | |
5190 | case PRE_INC: | |
5191 | case PRE_DEC: | |
eab89b90 RK |
5192 | if (GET_CODE (XEXP (x, 0)) == REG) |
5193 | { | |
5194 | register int regno = REGNO (XEXP (x, 0)); | |
5195 | int value = 0; | |
5196 | rtx x_orig = x; | |
5197 | ||
5198 | /* A register that is incremented cannot be constant! */ | |
5199 | if (regno >= FIRST_PSEUDO_REGISTER | |
5200 | && reg_equiv_constant[regno] != 0) | |
5201 | abort (); | |
5202 | ||
5203 | /* Handle a register that is equivalent to a memory location | |
5204 | which cannot be addressed directly. */ | |
cb2afeb3 R |
5205 | if (reg_equiv_memory_loc[regno] != 0 |
5206 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
eab89b90 RK |
5207 | { |
5208 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
cb2afeb3 R |
5209 | if (reg_equiv_address[regno] |
5210 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5211 | { | |
5212 | /* First reload the memory location's address. | |
5213 | We can't use ADDR_TYPE (type) here, because we need to | |
5214 | write back the value after reading it, hence we actually | |
5215 | need two registers. */ | |
5216 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
5217 | &XEXP (tem, 0), opnum, type, | |
5218 | ind_levels, insn); | |
5219 | /* Put this inside a new increment-expression. */ | |
5220 | x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem); | |
5221 | /* Proceed to reload that, as if it contained a register. */ | |
5222 | } | |
eab89b90 RK |
5223 | } |
5224 | ||
5225 | /* If we have a hard register that is ok as an index, | |
5226 | don't make a reload. If an autoincrement of a nice register | |
5227 | isn't "valid", it must be that no autoincrement is "valid". | |
5228 | If that is true and something made an autoincrement anyway, | |
5229 | this must be a special context where one is allowed. | |
5230 | (For example, a "push" instruction.) | |
5231 | We can't improve this address, so leave it alone. */ | |
5232 | ||
5233 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
5234 | and record how much to increment by. */ | |
5235 | ||
5236 | if (reg_renumber[regno] >= 0) | |
5237 | regno = reg_renumber[regno]; | |
5238 | if ((regno >= FIRST_PSEUDO_REGISTER | |
5239 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
858c3c8c | 5240 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))) |
eab89b90 | 5241 | { |
29a82058 | 5242 | #ifdef AUTO_INC_DEC |
eab89b90 | 5243 | register rtx link; |
29a82058 | 5244 | #endif |
55c22565 RK |
5245 | int reloadnum; |
5246 | ||
5247 | /* If we can output the register afterwards, do so, this | |
5248 | saves the extra update. | |
5249 | We can do so if we have an INSN - i.e. no JUMP_INSN nor | |
5250 | CALL_INSN - and it does not set CC0. | |
5251 | But don't do this if we cannot directly address the | |
5252 | memory location, since this will make it harder to | |
956d6950 | 5253 | reuse address reloads, and increases register pressure. |
55c22565 | 5254 | Also don't do this if we can probably update x directly. */ |
cb2afeb3 R |
5255 | rtx equiv = (GET_CODE (XEXP (x, 0)) == MEM |
5256 | ? XEXP (x, 0) | |
5257 | : reg_equiv_mem[regno]); | |
55c22565 RK |
5258 | int icode = (int) add_optab->handlers[(int) Pmode].insn_code; |
5259 | if (insn && GET_CODE (insn) == INSN && equiv | |
cb2afeb3 | 5260 | && memory_operand (equiv, GET_MODE (equiv)) |
55c22565 RK |
5261 | #ifdef HAVE_cc0 |
5262 | && ! sets_cc0_p (PATTERN (insn)) | |
5263 | #endif | |
5264 | && ! (icode != CODE_FOR_nothing | |
a995e389 RH |
5265 | && ((*insn_data[icode].operand[0].predicate) |
5266 | (equiv, Pmode)) | |
5267 | && ((*insn_data[icode].operand[1].predicate) | |
5268 | (equiv, Pmode)))) | |
55c22565 RK |
5269 | { |
5270 | loc = &XEXP (x, 0); | |
5271 | x = XEXP (x, 0); | |
5272 | reloadnum | |
5273 | = push_reload (x, x, loc, loc, | |
03acd8f8 | 5274 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
05d10675 BS |
5275 | GET_MODE (x), GET_MODE (x), 0, 0, |
5276 | opnum, RELOAD_OTHER); | |
3520cdec JL |
5277 | |
5278 | /* If we created a new MEM based on reg_equiv_mem[REGNO], then | |
5279 | LOC above is part of the new MEM, not the MEM in INSN. | |
5280 | ||
5281 | We must also replace the address of the MEM in INSN. */ | |
5282 | if (&XEXP (x_orig, 0) != loc) | |
5283 | push_replacement (&XEXP (x_orig, 0), reloadnum, VOIDmode); | |
5284 | ||
55c22565 RK |
5285 | } |
5286 | else | |
5287 | { | |
5288 | reloadnum | |
5289 | = push_reload (x, NULL_RTX, loc, NULL_PTR, | |
03acd8f8 | 5290 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
e9a25f70 | 5291 | GET_MODE (x), GET_MODE (x), 0, 0, |
55c22565 | 5292 | opnum, type); |
eceef4c9 | 5293 | rld[reloadnum].inc |
55c22565 | 5294 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); |
05d10675 | 5295 | |
55c22565 RK |
5296 | value = 1; |
5297 | } | |
eab89b90 RK |
5298 | |
5299 | #ifdef AUTO_INC_DEC | |
5300 | /* Update the REG_INC notes. */ | |
5301 | ||
5302 | for (link = REG_NOTES (this_insn); | |
5303 | link; link = XEXP (link, 1)) | |
5304 | if (REG_NOTE_KIND (link) == REG_INC | |
5305 | && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0))) | |
5306 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
5307 | #endif | |
5308 | } | |
5309 | return value; | |
5310 | } | |
a2d353e5 | 5311 | |
eab89b90 RK |
5312 | else if (GET_CODE (XEXP (x, 0)) == MEM) |
5313 | { | |
5314 | /* This is probably the result of a substitution, by eliminate_regs, | |
5315 | of an equivalent address for a pseudo that was not allocated to a | |
5316 | hard register. Verify that the specified address is valid and | |
5317 | reload it into a register. */ | |
eceef4c9 | 5318 | /* Variable `tem' might or might not be used in FIND_REG_INC_NOTE. */ |
47c3ed98 | 5319 | rtx tem ATTRIBUTE_UNUSED = XEXP (x, 0); |
eab89b90 RK |
5320 | register rtx link; |
5321 | int reloadnum; | |
5322 | ||
5323 | /* Since we know we are going to reload this item, don't decrement | |
5324 | for the indirection level. | |
5325 | ||
5326 | Note that this is actually conservative: it would be slightly | |
5327 | more efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5328 | reload1.c here. */ | |
4757e6a4 JW |
5329 | /* We can't use ADDR_TYPE (type) here, because we need to |
5330 | write back the value after reading it, hence we actually | |
5331 | need two registers. */ | |
eab89b90 RK |
5332 | find_reloads_address (GET_MODE (x), &XEXP (x, 0), |
5333 | XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0), | |
55c22565 | 5334 | opnum, type, ind_levels, insn); |
eab89b90 | 5335 | |
fb3821f7 | 5336 | reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR, |
03acd8f8 | 5337 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
a8c9daeb | 5338 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eceef4c9 | 5339 | rld[reloadnum].inc |
eab89b90 RK |
5340 | = find_inc_amount (PATTERN (this_insn), XEXP (x, 0)); |
5341 | ||
5342 | link = FIND_REG_INC_NOTE (this_insn, tem); | |
5343 | if (link != 0) | |
5344 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
5345 | ||
5346 | return 1; | |
5347 | } | |
a2d353e5 RK |
5348 | return 0; |
5349 | ||
5350 | case MEM: | |
5351 | /* This is probably the result of a substitution, by eliminate_regs, of | |
5352 | an equivalent address for a pseudo that was not allocated to a hard | |
5353 | register. Verify that the specified address is valid and reload it | |
5354 | into a register. | |
eab89b90 | 5355 | |
a2d353e5 RK |
5356 | Since we know we are going to reload this item, don't decrement for |
5357 | the indirection level. | |
eab89b90 RK |
5358 | |
5359 | Note that this is actually conservative: it would be slightly more | |
5360 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5361 | reload1.c here. */ | |
5362 | ||
5363 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 5364 | opnum, ADDR_TYPE (type), ind_levels, insn); |
fb3821f7 | 5365 | push_reload (*loc, NULL_RTX, loc, NULL_PTR, |
03acd8f8 | 5366 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
a8c9daeb | 5367 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 | 5368 | return 1; |
eab89b90 | 5369 | |
a2d353e5 RK |
5370 | case REG: |
5371 | { | |
5372 | register int regno = REGNO (x); | |
5373 | ||
5374 | if (reg_equiv_constant[regno] != 0) | |
5375 | { | |
03acd8f8 BS |
5376 | find_reloads_address_part (reg_equiv_constant[regno], loc, |
5377 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), | |
a2d353e5 RK |
5378 | GET_MODE (x), opnum, type, ind_levels); |
5379 | return 1; | |
5380 | } | |
eab89b90 RK |
5381 | |
5382 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
5383 | that feeds this insn. */ | |
a2d353e5 RK |
5384 | if (reg_equiv_mem[regno] != 0) |
5385 | { | |
5386 | push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR, | |
03acd8f8 | 5387 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
a2d353e5 RK |
5388 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5389 | return 1; | |
5390 | } | |
eab89b90 | 5391 | #endif |
eab89b90 | 5392 | |
cb2afeb3 R |
5393 | if (reg_equiv_memory_loc[regno] |
5394 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
a2d353e5 | 5395 | { |
cb2afeb3 R |
5396 | rtx tem = make_memloc (x, regno); |
5397 | if (reg_equiv_address[regno] != 0 | |
5398 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5399 | { | |
5400 | x = tem; | |
5401 | find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), | |
5402 | &XEXP (x, 0), opnum, ADDR_TYPE (type), | |
5403 | ind_levels, insn); | |
5404 | } | |
a2d353e5 | 5405 | } |
eab89b90 | 5406 | |
a2d353e5 RK |
5407 | if (reg_renumber[regno] >= 0) |
5408 | regno = reg_renumber[regno]; | |
5409 | ||
5410 | if ((regno >= FIRST_PSEUDO_REGISTER | |
5411 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
858c3c8c | 5412 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))) |
a2d353e5 RK |
5413 | { |
5414 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
03acd8f8 | 5415 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
a2d353e5 RK |
5416 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5417 | return 1; | |
5418 | } | |
5419 | ||
5420 | /* If a register appearing in an address is the subject of a CLOBBER | |
5421 | in this insn, reload it into some other register to be safe. | |
5422 | The CLOBBER is supposed to make the register unavailable | |
5423 | from before this insn to after it. */ | |
5424 | if (regno_clobbered_p (regno, this_insn)) | |
5425 | { | |
5426 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
03acd8f8 | 5427 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
a2d353e5 RK |
5428 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5429 | return 1; | |
5430 | } | |
5431 | } | |
5432 | return 0; | |
5433 | ||
5434 | case SUBREG: | |
922db4bb | 5435 | if (GET_CODE (SUBREG_REG (x)) == REG) |
eab89b90 | 5436 | { |
922db4bb RK |
5437 | /* If this is a SUBREG of a hard register and the resulting register |
5438 | is of the wrong class, reload the whole SUBREG. This avoids | |
5439 | needless copies if SUBREG_REG is multi-word. */ | |
5440 | if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5441 | { | |
5442 | int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
a2d353e5 | 5443 | |
922db4bb | 5444 | if (! (context ? REGNO_OK_FOR_INDEX_P (regno) |
858c3c8c | 5445 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode))) |
922db4bb RK |
5446 | { |
5447 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
03acd8f8 | 5448 | (context ? INDEX_REG_CLASS : BASE_REG_CLASS), |
922db4bb RK |
5449 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5450 | return 1; | |
5451 | } | |
5452 | } | |
abc95ed3 | 5453 | /* If this is a SUBREG of a pseudo-register, and the pseudo-register |
922db4bb RK |
5454 | is larger than the class size, then reload the whole SUBREG. */ |
5455 | else | |
a2d353e5 | 5456 | { |
03acd8f8 BS |
5457 | enum reg_class class = (context ? INDEX_REG_CLASS |
5458 | : BASE_REG_CLASS); | |
922db4bb RK |
5459 | if (CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x))) |
5460 | > reg_class_size[class]) | |
5461 | { | |
22505ad8 R |
5462 | x = find_reloads_subreg_address (x, 0, opnum, type, |
5463 | ind_levels, insn); | |
922db4bb RK |
5464 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, |
5465 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
5466 | return 1; | |
5467 | } | |
a2d353e5 | 5468 | } |
eab89b90 | 5469 | } |
a2d353e5 | 5470 | break; |
05d10675 | 5471 | |
e9a25f70 JL |
5472 | default: |
5473 | break; | |
eab89b90 RK |
5474 | } |
5475 | ||
a2d353e5 | 5476 | { |
6f7d635c | 5477 | register const char *fmt = GET_RTX_FORMAT (code); |
a2d353e5 RK |
5478 | register int i; |
5479 | ||
5480 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5481 | { | |
5482 | if (fmt[i] == 'e') | |
858c3c8c | 5483 | find_reloads_address_1 (mode, XEXP (x, i), context, &XEXP (x, i), |
55c22565 | 5484 | opnum, type, ind_levels, insn); |
a2d353e5 RK |
5485 | } |
5486 | } | |
5487 | ||
eab89b90 RK |
5488 | return 0; |
5489 | } | |
5490 | \f | |
5491 | /* X, which is found at *LOC, is a part of an address that needs to be | |
5492 | reloaded into a register of class CLASS. If X is a constant, or if | |
5493 | X is a PLUS that contains a constant, check that the constant is a | |
5494 | legitimate operand and that we are supposed to be able to load | |
5495 | it into the register. | |
5496 | ||
5497 | If not, force the constant into memory and reload the MEM instead. | |
5498 | ||
5499 | MODE is the mode to use, in case X is an integer constant. | |
5500 | ||
a8c9daeb | 5501 | OPNUM and TYPE describe the purpose of any reloads made. |
eab89b90 RK |
5502 | |
5503 | IND_LEVELS says how many levels of indirect addressing this machine | |
5504 | supports. */ | |
5505 | ||
5506 | static void | |
a8c9daeb | 5507 | find_reloads_address_part (x, loc, class, mode, opnum, type, ind_levels) |
eab89b90 RK |
5508 | rtx x; |
5509 | rtx *loc; | |
5510 | enum reg_class class; | |
5511 | enum machine_mode mode; | |
a8c9daeb RK |
5512 | int opnum; |
5513 | enum reload_type type; | |
eab89b90 RK |
5514 | int ind_levels; |
5515 | { | |
5516 | if (CONSTANT_P (x) | |
5517 | && (! LEGITIMATE_CONSTANT_P (x) | |
5518 | || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) | |
5519 | { | |
ef18065c JW |
5520 | rtx tem; |
5521 | ||
5522 | /* If this is a CONST_INT, it could have been created by a | |
5523 | plus_constant call in eliminate_regs, which means it may be | |
5524 | on the reload_obstack. reload_obstack will be freed later, so | |
5525 | we can't allow such RTL to be put in the constant pool. There | |
5526 | is code in force_const_mem to check for this case, but it doesn't | |
5527 | work because we have already popped off the reload_obstack, so | |
5528 | rtl_obstack == saveable_obstack is true at this point. */ | |
5529 | if (GET_CODE (x) == CONST_INT) | |
5530 | tem = x = force_const_mem (mode, GEN_INT (INTVAL (x))); | |
5531 | else | |
5532 | tem = x = force_const_mem (mode, x); | |
5533 | ||
eab89b90 | 5534 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), |
55c22565 | 5535 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5536 | } |
5537 | ||
5538 | else if (GET_CODE (x) == PLUS | |
5539 | && CONSTANT_P (XEXP (x, 1)) | |
5540 | && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | |
5541 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) | |
5542 | { | |
ef18065c JW |
5543 | rtx tem; |
5544 | ||
5545 | /* See comment above. */ | |
5546 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5547 | tem = force_const_mem (GET_MODE (x), GEN_INT (INTVAL (XEXP (x, 1)))); | |
5548 | else | |
5549 | tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); | |
eab89b90 | 5550 | |
38a448ca | 5551 | x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem); |
eab89b90 | 5552 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), |
55c22565 | 5553 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5554 | } |
5555 | ||
fb3821f7 | 5556 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, |
a8c9daeb | 5557 | mode, VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
5558 | } |
5559 | \f | |
22505ad8 R |
5560 | /* X, a subreg of a pseudo, is a part of an address that needs to be |
5561 | reloaded. | |
5562 | ||
5563 | If the pseudo is equivalent to a memory location that cannot be directly | |
5564 | addressed, make the necessary address reloads. | |
5565 | ||
5566 | If address reloads have been necessary, or if the address is changed | |
5567 | by register elimination, return the rtx of the memory location; | |
5568 | otherwise, return X. | |
5569 | ||
5570 | If FORCE_REPLACE is nonzero, unconditionally replace the subreg with the | |
5571 | memory location. | |
5572 | ||
5573 | OPNUM and TYPE identify the purpose of the reload. | |
5574 | ||
5575 | IND_LEVELS says how many levels of indirect addressing are | |
5576 | supported at this point in the address. | |
5577 | ||
5578 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
5579 | to determine where to put USEs for pseudos that we have to replace with | |
5580 | stack slots. */ | |
5581 | ||
5582 | static rtx | |
5583 | find_reloads_subreg_address (x, force_replace, opnum, type, | |
5584 | ind_levels, insn) | |
5585 | rtx x; | |
5586 | int force_replace; | |
5587 | int opnum; | |
5588 | enum reload_type type; | |
5589 | int ind_levels; | |
5590 | rtx insn; | |
5591 | { | |
5592 | int regno = REGNO (SUBREG_REG (x)); | |
5593 | ||
5594 | if (reg_equiv_memory_loc[regno]) | |
5595 | { | |
5596 | /* If the address is not directly addressable, or if the address is not | |
5597 | offsettable, then it must be replaced. */ | |
5598 | if (! force_replace | |
5599 | && (reg_equiv_address[regno] | |
5600 | || ! offsettable_memref_p (reg_equiv_mem[regno]))) | |
5601 | force_replace = 1; | |
5602 | ||
5603 | if (force_replace || num_not_at_initial_offset) | |
5604 | { | |
5605 | rtx tem = make_memloc (SUBREG_REG (x), regno); | |
5606 | ||
5607 | /* If the address changes because of register elimination, then | |
dd074554 | 5608 | it must be replaced. */ |
22505ad8 R |
5609 | if (force_replace |
5610 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5611 | { | |
5612 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
5613 | ||
5614 | if (BYTES_BIG_ENDIAN) | |
5615 | { | |
5616 | int size; | |
5617 | ||
5618 | size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
5619 | offset += MIN (size, UNITS_PER_WORD); | |
5620 | size = GET_MODE_SIZE (GET_MODE (x)); | |
5621 | offset -= MIN (size, UNITS_PER_WORD); | |
5622 | } | |
5623 | XEXP (tem, 0) = plus_constant (XEXP (tem, 0), offset); | |
5624 | PUT_MODE (tem, GET_MODE (x)); | |
0ba9b9e6 R |
5625 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), |
5626 | &XEXP (tem, 0), opnum, ADDR_TYPE (type), | |
5627 | ind_levels, insn); | |
22505ad8 R |
5628 | /* If this is not a toplevel operand, find_reloads doesn't see |
5629 | this substitution. We have to emit a USE of the pseudo so | |
5630 | that delete_output_reload can see it. */ | |
1ccbefce | 5631 | if (replace_reloads && recog_data.operand[opnum] != x) |
22505ad8 | 5632 | emit_insn_before (gen_rtx_USE (VOIDmode, SUBREG_REG (x)), insn); |
0ba9b9e6 | 5633 | x = tem; |
22505ad8 R |
5634 | } |
5635 | } | |
5636 | } | |
5637 | return x; | |
5638 | } | |
5639 | \f | |
a8c9daeb | 5640 | /* Substitute into the current INSN the registers into which we have reloaded |
eab89b90 RK |
5641 | the things that need reloading. The array `replacements' |
5642 | says contains the locations of all pointers that must be changed | |
5643 | and says what to replace them with. | |
5644 | ||
5645 | Return the rtx that X translates into; usually X, but modified. */ | |
5646 | ||
5647 | void | |
5648 | subst_reloads () | |
5649 | { | |
5650 | register int i; | |
5651 | ||
5652 | for (i = 0; i < n_replacements; i++) | |
5653 | { | |
5654 | register struct replacement *r = &replacements[i]; | |
eceef4c9 | 5655 | register rtx reloadreg = rld[r->what].reg_rtx; |
eab89b90 RK |
5656 | if (reloadreg) |
5657 | { | |
5658 | /* Encapsulate RELOADREG so its machine mode matches what | |
26f1a00e RK |
5659 | used to be there. Note that gen_lowpart_common will |
5660 | do the wrong thing if RELOADREG is multi-word. RELOADREG | |
5661 | will always be a REG here. */ | |
eab89b90 | 5662 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) |
38a448ca | 5663 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
eab89b90 RK |
5664 | |
5665 | /* If we are putting this into a SUBREG and RELOADREG is a | |
5666 | SUBREG, we would be making nested SUBREGs, so we have to fix | |
5667 | this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ | |
5668 | ||
5669 | if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) | |
5670 | { | |
5671 | if (GET_MODE (*r->subreg_loc) | |
5672 | == GET_MODE (SUBREG_REG (reloadreg))) | |
5673 | *r->subreg_loc = SUBREG_REG (reloadreg); | |
5674 | else | |
5675 | { | |
5676 | *r->where = SUBREG_REG (reloadreg); | |
5677 | SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg); | |
5678 | } | |
5679 | } | |
5680 | else | |
5681 | *r->where = reloadreg; | |
5682 | } | |
5683 | /* If reload got no reg and isn't optional, something's wrong. */ | |
eceef4c9 | 5684 | else if (! rld[r->what].optional) |
eab89b90 RK |
5685 | abort (); |
5686 | } | |
5687 | } | |
5688 | \f | |
5689 | /* Make a copy of any replacements being done into X and move those copies | |
5690 | to locations in Y, a copy of X. We only look at the highest level of | |
5691 | the RTL. */ | |
5692 | ||
5693 | void | |
5694 | copy_replacements (x, y) | |
5695 | rtx x; | |
5696 | rtx y; | |
5697 | { | |
5698 | int i, j; | |
5699 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 5700 | const char *fmt = GET_RTX_FORMAT (code); |
eab89b90 RK |
5701 | struct replacement *r; |
5702 | ||
5703 | /* We can't support X being a SUBREG because we might then need to know its | |
5704 | location if something inside it was replaced. */ | |
5705 | if (code == SUBREG) | |
5706 | abort (); | |
5707 | ||
5708 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5709 | if (fmt[i] == 'e') | |
5710 | for (j = 0; j < n_replacements; j++) | |
5711 | { | |
5712 | if (replacements[j].subreg_loc == &XEXP (x, i)) | |
5713 | { | |
5714 | r = &replacements[n_replacements++]; | |
5715 | r->where = replacements[j].where; | |
5716 | r->subreg_loc = &XEXP (y, i); | |
5717 | r->what = replacements[j].what; | |
5718 | r->mode = replacements[j].mode; | |
5719 | } | |
5720 | else if (replacements[j].where == &XEXP (x, i)) | |
5721 | { | |
5722 | r = &replacements[n_replacements++]; | |
5723 | r->where = &XEXP (y, i); | |
5724 | r->subreg_loc = 0; | |
5725 | r->what = replacements[j].what; | |
5726 | r->mode = replacements[j].mode; | |
5727 | } | |
5728 | } | |
5729 | } | |
a9a2595b JR |
5730 | |
5731 | /* Change any replacements being done to *X to be done to *Y */ | |
5732 | ||
5733 | void | |
5734 | move_replacements (x, y) | |
5735 | rtx *x; | |
5736 | rtx *y; | |
5737 | { | |
5738 | int i; | |
5739 | ||
5740 | for (i = 0; i < n_replacements; i++) | |
5741 | if (replacements[i].subreg_loc == x) | |
5742 | replacements[i].subreg_loc = y; | |
5743 | else if (replacements[i].where == x) | |
5744 | { | |
5745 | replacements[i].where = y; | |
5746 | replacements[i].subreg_loc = 0; | |
5747 | } | |
5748 | } | |
eab89b90 | 5749 | \f |
af929c62 RK |
5750 | /* If LOC was scheduled to be replaced by something, return the replacement. |
5751 | Otherwise, return *LOC. */ | |
5752 | ||
5753 | rtx | |
5754 | find_replacement (loc) | |
5755 | rtx *loc; | |
5756 | { | |
5757 | struct replacement *r; | |
5758 | ||
5759 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
5760 | { | |
eceef4c9 | 5761 | rtx reloadreg = rld[r->what].reg_rtx; |
af929c62 RK |
5762 | |
5763 | if (reloadreg && r->where == loc) | |
5764 | { | |
5765 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
38a448ca | 5766 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
af929c62 RK |
5767 | |
5768 | return reloadreg; | |
5769 | } | |
5770 | else if (reloadreg && r->subreg_loc == loc) | |
5771 | { | |
5772 | /* RELOADREG must be either a REG or a SUBREG. | |
5773 | ||
5774 | ??? Is it actually still ever a SUBREG? If so, why? */ | |
5775 | ||
5776 | if (GET_CODE (reloadreg) == REG) | |
38a448ca RH |
5777 | return gen_rtx_REG (GET_MODE (*loc), |
5778 | REGNO (reloadreg) + SUBREG_WORD (*loc)); | |
af929c62 RK |
5779 | else if (GET_MODE (reloadreg) == GET_MODE (*loc)) |
5780 | return reloadreg; | |
5781 | else | |
38a448ca RH |
5782 | return gen_rtx_SUBREG (GET_MODE (*loc), SUBREG_REG (reloadreg), |
5783 | SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc)); | |
af929c62 RK |
5784 | } |
5785 | } | |
5786 | ||
956d6950 JL |
5787 | /* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for |
5788 | what's inside and make a new rtl if so. */ | |
5789 | if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS | |
5790 | || GET_CODE (*loc) == MULT) | |
5791 | { | |
5792 | rtx x = find_replacement (&XEXP (*loc, 0)); | |
5793 | rtx y = find_replacement (&XEXP (*loc, 1)); | |
5794 | ||
5795 | if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1)) | |
38a448ca | 5796 | return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y); |
956d6950 JL |
5797 | } |
5798 | ||
af929c62 RK |
5799 | return *loc; |
5800 | } | |
5801 | \f | |
eab89b90 RK |
5802 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
5803 | appears either explicitly or implicitly in X | |
4644aad4 | 5804 | other than being stored into (except for earlyclobber operands). |
eab89b90 RK |
5805 | |
5806 | References contained within the substructure at LOC do not count. | |
5807 | LOC may be zero, meaning don't ignore anything. | |
5808 | ||
5809 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
5810 | look at equivalences for pseudos that didn't get hard registers. */ | |
5811 | ||
5812 | int | |
5813 | refers_to_regno_for_reload_p (regno, endregno, x, loc) | |
5814 | int regno, endregno; | |
5815 | rtx x; | |
5816 | rtx *loc; | |
5817 | { | |
5818 | register int i; | |
5819 | register RTX_CODE code; | |
6f7d635c | 5820 | register const char *fmt; |
eab89b90 RK |
5821 | |
5822 | if (x == 0) | |
5823 | return 0; | |
5824 | ||
5825 | repeat: | |
5826 | code = GET_CODE (x); | |
5827 | ||
5828 | switch (code) | |
5829 | { | |
5830 | case REG: | |
5831 | i = REGNO (x); | |
5832 | ||
4803a34a RK |
5833 | /* If this is a pseudo, a hard register must not have been allocated. |
5834 | X must therefore either be a constant or be in memory. */ | |
5835 | if (i >= FIRST_PSEUDO_REGISTER) | |
5836 | { | |
5837 | if (reg_equiv_memory_loc[i]) | |
5838 | return refers_to_regno_for_reload_p (regno, endregno, | |
fb3821f7 CH |
5839 | reg_equiv_memory_loc[i], |
5840 | NULL_PTR); | |
4803a34a RK |
5841 | |
5842 | if (reg_equiv_constant[i]) | |
5843 | return 0; | |
5844 | ||
5845 | abort (); | |
5846 | } | |
eab89b90 RK |
5847 | |
5848 | return (endregno > i | |
05d10675 | 5849 | && regno < i + (i < FIRST_PSEUDO_REGISTER |
eab89b90 RK |
5850 | ? HARD_REGNO_NREGS (i, GET_MODE (x)) |
5851 | : 1)); | |
5852 | ||
5853 | case SUBREG: | |
5854 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
5855 | registers are being modified. Otherwise, handle normally. */ | |
5856 | if (GET_CODE (SUBREG_REG (x)) == REG | |
5857 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5858 | { | |
5859 | int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
5860 | int inner_endregno | |
5861 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER | |
5862 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
5863 | ||
5864 | return endregno > inner_regno && regno < inner_endregno; | |
5865 | } | |
5866 | break; | |
5867 | ||
5868 | case CLOBBER: | |
5869 | case SET: | |
5870 | if (&SET_DEST (x) != loc | |
5871 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
5872 | a pseudo but not for hard registers since we can | |
5873 | treat each word individually. */ | |
5874 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
5875 | && loc != &SUBREG_REG (SET_DEST (x)) | |
5876 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
5877 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER | |
5878 | && refers_to_regno_for_reload_p (regno, endregno, | |
5879 | SUBREG_REG (SET_DEST (x)), | |
5880 | loc)) | |
abc95ed3 | 5881 | /* If the output is an earlyclobber operand, this is |
4644aad4 RK |
5882 | a conflict. */ |
5883 | || ((GET_CODE (SET_DEST (x)) != REG | |
5884 | || earlyclobber_operand_p (SET_DEST (x))) | |
eab89b90 RK |
5885 | && refers_to_regno_for_reload_p (regno, endregno, |
5886 | SET_DEST (x), loc)))) | |
5887 | return 1; | |
5888 | ||
5889 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
5890 | return 0; | |
5891 | x = SET_SRC (x); | |
5892 | goto repeat; | |
05d10675 | 5893 | |
e9a25f70 JL |
5894 | default: |
5895 | break; | |
eab89b90 RK |
5896 | } |
5897 | ||
5898 | /* X does not match, so try its subexpressions. */ | |
5899 | ||
5900 | fmt = GET_RTX_FORMAT (code); | |
5901 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5902 | { | |
5903 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
5904 | { | |
5905 | if (i == 0) | |
5906 | { | |
5907 | x = XEXP (x, 0); | |
5908 | goto repeat; | |
5909 | } | |
5910 | else | |
5911 | if (refers_to_regno_for_reload_p (regno, endregno, | |
5912 | XEXP (x, i), loc)) | |
5913 | return 1; | |
5914 | } | |
5915 | else if (fmt[i] == 'E') | |
5916 | { | |
5917 | register int j; | |
5918 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
5919 | if (loc != &XVECEXP (x, i, j) | |
5920 | && refers_to_regno_for_reload_p (regno, endregno, | |
5921 | XVECEXP (x, i, j), loc)) | |
5922 | return 1; | |
5923 | } | |
5924 | } | |
5925 | return 0; | |
5926 | } | |
bfa30b22 RK |
5927 | |
5928 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
5929 | we check if any register number in X conflicts with the relevant register | |
5930 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
5931 | contains a MEM (we don't bother checking for memory addresses that can't | |
05d10675 | 5932 | conflict because we expect this to be a rare case. |
bfa30b22 RK |
5933 | |
5934 | This function is similar to reg_overlap_mention_p in rtlanal.c except | |
5935 | that we look at equivalences for pseudos that didn't get hard registers. */ | |
5936 | ||
5937 | int | |
5938 | reg_overlap_mentioned_for_reload_p (x, in) | |
5939 | rtx x, in; | |
5940 | { | |
5941 | int regno, endregno; | |
5942 | ||
b98b49ac JL |
5943 | /* Overly conservative. */ |
5944 | if (GET_CODE (x) == STRICT_LOW_PART) | |
5945 | x = XEXP (x, 0); | |
5946 | ||
5947 | /* If either argument is a constant, then modifying X can not affect IN. */ | |
5948 | if (CONSTANT_P (x) || CONSTANT_P (in)) | |
5949 | return 0; | |
5950 | else if (GET_CODE (x) == SUBREG) | |
bfa30b22 RK |
5951 | { |
5952 | regno = REGNO (SUBREG_REG (x)); | |
5953 | if (regno < FIRST_PSEUDO_REGISTER) | |
5954 | regno += SUBREG_WORD (x); | |
5955 | } | |
5956 | else if (GET_CODE (x) == REG) | |
5957 | { | |
5958 | regno = REGNO (x); | |
4803a34a RK |
5959 | |
5960 | /* If this is a pseudo, it must not have been assigned a hard register. | |
5961 | Therefore, it must either be in memory or be a constant. */ | |
5962 | ||
5963 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5964 | { | |
5965 | if (reg_equiv_memory_loc[regno]) | |
5966 | return refers_to_mem_for_reload_p (in); | |
5967 | else if (reg_equiv_constant[regno]) | |
5968 | return 0; | |
5969 | abort (); | |
5970 | } | |
bfa30b22 | 5971 | } |
bfa30b22 | 5972 | else if (GET_CODE (x) == MEM) |
4803a34a | 5973 | return refers_to_mem_for_reload_p (in); |
bfa30b22 RK |
5974 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
5975 | || GET_CODE (x) == CC0) | |
5976 | return reg_mentioned_p (x, in); | |
5977 | else | |
5978 | abort (); | |
5979 | ||
5980 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
5981 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
5982 | ||
fb3821f7 | 5983 | return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR); |
bfa30b22 | 5984 | } |
4803a34a RK |
5985 | |
5986 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
5987 | registers. */ | |
5988 | ||
5989 | int | |
5990 | refers_to_mem_for_reload_p (x) | |
5991 | rtx x; | |
5992 | { | |
6f7d635c | 5993 | const char *fmt; |
4803a34a RK |
5994 | int i; |
5995 | ||
5996 | if (GET_CODE (x) == MEM) | |
5997 | return 1; | |
5998 | ||
5999 | if (GET_CODE (x) == REG) | |
6000 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
6001 | && reg_equiv_memory_loc[REGNO (x)]); | |
05d10675 | 6002 | |
4803a34a RK |
6003 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
6004 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6005 | if (fmt[i] == 'e' | |
6006 | && (GET_CODE (XEXP (x, i)) == MEM | |
6007 | || refers_to_mem_for_reload_p (XEXP (x, i)))) | |
6008 | return 1; | |
05d10675 | 6009 | |
4803a34a RK |
6010 | return 0; |
6011 | } | |
eab89b90 | 6012 | \f |
eab89b90 RK |
6013 | /* Check the insns before INSN to see if there is a suitable register |
6014 | containing the same value as GOAL. | |
6015 | If OTHER is -1, look for a register in class CLASS. | |
6016 | Otherwise, just see if register number OTHER shares GOAL's value. | |
6017 | ||
6018 | Return an rtx for the register found, or zero if none is found. | |
6019 | ||
6020 | If RELOAD_REG_P is (short *)1, | |
6021 | we reject any hard reg that appears in reload_reg_rtx | |
6022 | because such a hard reg is also needed coming into this insn. | |
6023 | ||
6024 | If RELOAD_REG_P is any other nonzero value, | |
6025 | it is a vector indexed by hard reg number | |
6026 | and we reject any hard reg whose element in the vector is nonnegative | |
6027 | as well as any that appears in reload_reg_rtx. | |
6028 | ||
6029 | If GOAL is zero, then GOALREG is a register number; we look | |
6030 | for an equivalent for that register. | |
6031 | ||
6032 | MODE is the machine mode of the value we want an equivalence for. | |
6033 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
6034 | ||
6035 | This function is used by jump.c as well as in the reload pass. | |
6036 | ||
6037 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
6038 | as if it were a constant except that sp is required to be unchanging. */ | |
6039 | ||
6040 | rtx | |
6041 | find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode) | |
6042 | register rtx goal; | |
6043 | rtx insn; | |
6044 | enum reg_class class; | |
6045 | register int other; | |
6046 | short *reload_reg_p; | |
6047 | int goalreg; | |
6048 | enum machine_mode mode; | |
6049 | { | |
6050 | register rtx p = insn; | |
f55b1d97 | 6051 | rtx goaltry, valtry, value, where; |
eab89b90 RK |
6052 | register rtx pat; |
6053 | register int regno = -1; | |
6054 | int valueno; | |
6055 | int goal_mem = 0; | |
6056 | int goal_const = 0; | |
6057 | int goal_mem_addr_varies = 0; | |
6058 | int need_stable_sp = 0; | |
6059 | int nregs; | |
6060 | int valuenregs; | |
6061 | ||
6062 | if (goal == 0) | |
6063 | regno = goalreg; | |
6064 | else if (GET_CODE (goal) == REG) | |
6065 | regno = REGNO (goal); | |
6066 | else if (GET_CODE (goal) == MEM) | |
6067 | { | |
6068 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
6069 | if (MEM_VOLATILE_P (goal)) | |
6070 | return 0; | |
6071 | if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT) | |
6072 | return 0; | |
6073 | /* An address with side effects must be reexecuted. */ | |
6074 | switch (code) | |
6075 | { | |
6076 | case POST_INC: | |
6077 | case PRE_INC: | |
6078 | case POST_DEC: | |
6079 | case PRE_DEC: | |
6080 | return 0; | |
e9a25f70 JL |
6081 | default: |
6082 | break; | |
eab89b90 RK |
6083 | } |
6084 | goal_mem = 1; | |
6085 | } | |
6086 | else if (CONSTANT_P (goal)) | |
6087 | goal_const = 1; | |
6088 | else if (GET_CODE (goal) == PLUS | |
6089 | && XEXP (goal, 0) == stack_pointer_rtx | |
6090 | && CONSTANT_P (XEXP (goal, 1))) | |
6091 | goal_const = need_stable_sp = 1; | |
812f2051 R |
6092 | else if (GET_CODE (goal) == PLUS |
6093 | && XEXP (goal, 0) == frame_pointer_rtx | |
6094 | && CONSTANT_P (XEXP (goal, 1))) | |
6095 | goal_const = 1; | |
eab89b90 RK |
6096 | else |
6097 | return 0; | |
6098 | ||
6099 | /* On some machines, certain regs must always be rejected | |
6100 | because they don't behave the way ordinary registers do. */ | |
05d10675 | 6101 | |
eab89b90 | 6102 | #ifdef OVERLAPPING_REGNO_P |
05d10675 BS |
6103 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER |
6104 | && OVERLAPPING_REGNO_P (regno)) | |
6105 | return 0; | |
6106 | #endif | |
eab89b90 RK |
6107 | |
6108 | /* Scan insns back from INSN, looking for one that copies | |
6109 | a value into or out of GOAL. | |
6110 | Stop and give up if we reach a label. */ | |
6111 | ||
6112 | while (1) | |
6113 | { | |
6114 | p = PREV_INSN (p); | |
6115 | if (p == 0 || GET_CODE (p) == CODE_LABEL) | |
6116 | return 0; | |
6117 | if (GET_CODE (p) == INSN | |
0f41302f | 6118 | /* If we don't want spill regs ... */ |
a8c9daeb RK |
6119 | && (! (reload_reg_p != 0 |
6120 | && reload_reg_p != (short *) (HOST_WIDE_INT) 1) | |
05d10675 BS |
6121 | /* ... then ignore insns introduced by reload; they aren't useful |
6122 | and can cause results in reload_as_needed to be different | |
6123 | from what they were when calculating the need for spills. | |
6124 | If we notice an input-reload insn here, we will reject it below, | |
6125 | but it might hide a usable equivalent. That makes bad code. | |
6126 | It may even abort: perhaps no reg was spilled for this insn | |
6127 | because it was assumed we would find that equivalent. */ | |
eab89b90 RK |
6128 | || INSN_UID (p) < reload_first_uid)) |
6129 | { | |
e8094962 | 6130 | rtx tem; |
eab89b90 RK |
6131 | pat = single_set (p); |
6132 | /* First check for something that sets some reg equal to GOAL. */ | |
6133 | if (pat != 0 | |
6134 | && ((regno >= 0 | |
6135 | && true_regnum (SET_SRC (pat)) == regno | |
6136 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
6137 | || | |
6138 | (regno >= 0 | |
6139 | && true_regnum (SET_DEST (pat)) == regno | |
6140 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
6141 | || | |
6142 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
a5546290 R |
6143 | /* When looking for stack pointer + const, |
6144 | make sure we don't use a stack adjust. */ | |
6145 | && !reg_overlap_mentioned_for_reload_p (SET_DEST (pat), goal) | |
eab89b90 RK |
6146 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
6147 | || (goal_mem | |
6148 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
6149 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
6150 | || (goal_mem | |
6151 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
e8094962 RK |
6152 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
6153 | /* If we are looking for a constant, | |
6154 | and something equivalent to that constant was copied | |
6155 | into a reg, we can use that reg. */ | |
fb3821f7 CH |
6156 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
6157 | NULL_RTX)) | |
e8094962 | 6158 | && rtx_equal_p (XEXP (tem, 0), goal) |
95d3562b | 6159 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
fb3821f7 CH |
6160 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
6161 | NULL_RTX)) | |
e8094962 RK |
6162 | && GET_CODE (SET_DEST (pat)) == REG |
6163 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
6164 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
6165 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
6166 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 0, 0, |
6167 | VOIDmode)) | |
6168 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
6169 | && (valtry = operand_subword (SET_DEST (pat), 0, 0, |
6170 | VOIDmode)) | |
95d3562b | 6171 | && (valueno = true_regnum (valtry)) >= 0) |
fb3821f7 CH |
6172 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
6173 | NULL_RTX)) | |
e8094962 RK |
6174 | && GET_CODE (SET_DEST (pat)) == REG |
6175 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
6176 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
6177 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
6178 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, |
6179 | VOIDmode)) | |
6180 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
6181 | && (valtry |
6182 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
95d3562b | 6183 | && (valueno = true_regnum (valtry)) >= 0))) |
eab89b90 RK |
6184 | if (other >= 0 |
6185 | ? valueno == other | |
6186 | : ((unsigned) valueno < FIRST_PSEUDO_REGISTER | |
6187 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
6188 | valueno))) | |
6189 | { | |
6190 | value = valtry; | |
6191 | where = p; | |
6192 | break; | |
6193 | } | |
6194 | } | |
6195 | } | |
6196 | ||
6197 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
6198 | (or copying VALUE into GOAL, if GOAL is also a register). | |
6199 | Now verify that VALUE is really valid. */ | |
6200 | ||
6201 | /* VALUENO is the register number of VALUE; a hard register. */ | |
6202 | ||
6203 | /* Don't try to re-use something that is killed in this insn. We want | |
6204 | to be able to trust REG_UNUSED notes. */ | |
6205 | if (find_reg_note (where, REG_UNUSED, value)) | |
6206 | return 0; | |
6207 | ||
6208 | /* If we propose to get the value from the stack pointer or if GOAL is | |
6209 | a MEM based on the stack pointer, we need a stable SP. */ | |
d5a1d1c7 | 6210 | if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM |
bfa30b22 RK |
6211 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
6212 | goal))) | |
eab89b90 RK |
6213 | need_stable_sp = 1; |
6214 | ||
6215 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
6216 | if (GET_MODE (value) != mode) | |
6217 | return 0; | |
6218 | ||
6219 | /* Reject VALUE if it was loaded from GOAL | |
6220 | and is also a register that appears in the address of GOAL. */ | |
6221 | ||
bd5f6d44 | 6222 | if (goal_mem && value == SET_DEST (single_set (where)) |
bfa30b22 RK |
6223 | && refers_to_regno_for_reload_p (valueno, |
6224 | (valueno | |
6225 | + HARD_REGNO_NREGS (valueno, mode)), | |
fb3821f7 | 6226 | goal, NULL_PTR)) |
eab89b90 RK |
6227 | return 0; |
6228 | ||
6229 | /* Reject registers that overlap GOAL. */ | |
6230 | ||
6231 | if (!goal_mem && !goal_const | |
6232 | && regno + HARD_REGNO_NREGS (regno, mode) > valueno | |
6233 | && regno < valueno + HARD_REGNO_NREGS (valueno, mode)) | |
6234 | return 0; | |
6235 | ||
6236 | /* Reject VALUE if it is one of the regs reserved for reloads. | |
6237 | Reload1 knows how to reuse them anyway, and it would get | |
6238 | confused if we allocated one without its knowledge. | |
6239 | (Now that insns introduced by reload are ignored above, | |
6240 | this case shouldn't happen, but I'm not positive.) */ | |
6241 | ||
a8c9daeb | 6242 | if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1 |
eab89b90 RK |
6243 | && reload_reg_p[valueno] >= 0) |
6244 | return 0; | |
6245 | ||
6246 | /* On some machines, certain regs must always be rejected | |
6247 | because they don't behave the way ordinary registers do. */ | |
05d10675 | 6248 | |
eab89b90 RK |
6249 | #ifdef OVERLAPPING_REGNO_P |
6250 | if (OVERLAPPING_REGNO_P (valueno)) | |
6251 | return 0; | |
05d10675 | 6252 | #endif |
eab89b90 RK |
6253 | |
6254 | nregs = HARD_REGNO_NREGS (regno, mode); | |
6255 | valuenregs = HARD_REGNO_NREGS (valueno, mode); | |
6256 | ||
6257 | /* Reject VALUE if it is a register being used for an input reload | |
6258 | even if it is not one of those reserved. */ | |
6259 | ||
6260 | if (reload_reg_p != 0) | |
6261 | { | |
6262 | int i; | |
6263 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 6264 | if (rld[i].reg_rtx != 0 && rld[i].in) |
eab89b90 | 6265 | { |
eceef4c9 | 6266 | int regno1 = REGNO (rld[i].reg_rtx); |
eab89b90 | 6267 | int nregs1 = HARD_REGNO_NREGS (regno1, |
eceef4c9 | 6268 | GET_MODE (rld[i].reg_rtx)); |
eab89b90 RK |
6269 | if (regno1 < valueno + valuenregs |
6270 | && regno1 + nregs1 > valueno) | |
6271 | return 0; | |
6272 | } | |
6273 | } | |
6274 | ||
6275 | if (goal_mem) | |
54b5ffe9 RS |
6276 | /* We must treat frame pointer as varying here, |
6277 | since it can vary--in a nonlocal goto as generated by expand_goto. */ | |
6278 | goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); | |
eab89b90 RK |
6279 | |
6280 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
6281 | until INSN is reached. */ | |
6282 | ||
6283 | p = insn; | |
6284 | while (1) | |
6285 | { | |
6286 | p = PREV_INSN (p); | |
6287 | if (p == where) | |
6288 | return value; | |
6289 | ||
6290 | /* Don't trust the conversion past a function call | |
6291 | if either of the two is in a call-clobbered register, or memory. */ | |
6292 | if (GET_CODE (p) == CALL_INSN | |
6293 | && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
6294 | && call_used_regs[regno]) | |
6295 | || | |
6296 | (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
6297 | && call_used_regs[valueno]) | |
6298 | || | |
6299 | goal_mem | |
6300 | || need_stable_sp)) | |
6301 | return 0; | |
6302 | ||
05d10675 | 6303 | #ifdef NON_SAVING_SETJMP |
41fe17ab RK |
6304 | if (NON_SAVING_SETJMP && GET_CODE (p) == NOTE |
6305 | && NOTE_LINE_NUMBER (p) == NOTE_INSN_SETJMP) | |
6306 | return 0; | |
6307 | #endif | |
6308 | ||
eab89b90 RK |
6309 | #ifdef INSN_CLOBBERS_REGNO_P |
6310 | if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
05d10675 | 6311 | && INSN_CLOBBERS_REGNO_P (p, valueno)) |
eab89b90 | 6312 | || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER |
05d10675 | 6313 | && INSN_CLOBBERS_REGNO_P (p, regno))) |
eab89b90 RK |
6314 | return 0; |
6315 | #endif | |
6316 | ||
6317 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
6318 | { | |
8ec82f87 RH |
6319 | pat = PATTERN (p); |
6320 | ||
05d10675 BS |
6321 | /* Watch out for unspec_volatile, and volatile asms. */ |
6322 | if (volatile_insn_p (pat)) | |
8ec82f87 RH |
6323 | return 0; |
6324 | ||
eab89b90 RK |
6325 | /* If this insn P stores in either GOAL or VALUE, return 0. |
6326 | If GOAL is a memory ref and this insn writes memory, return 0. | |
6327 | If GOAL is a memory ref and its address is not constant, | |
6328 | and this insn P changes a register used in GOAL, return 0. */ | |
6329 | ||
eab89b90 RK |
6330 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) |
6331 | { | |
6332 | register rtx dest = SET_DEST (pat); | |
6333 | while (GET_CODE (dest) == SUBREG | |
6334 | || GET_CODE (dest) == ZERO_EXTRACT | |
6335 | || GET_CODE (dest) == SIGN_EXTRACT | |
6336 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6337 | dest = XEXP (dest, 0); | |
6338 | if (GET_CODE (dest) == REG) | |
6339 | { | |
6340 | register int xregno = REGNO (dest); | |
6341 | int xnregs; | |
6342 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
6343 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
6344 | else | |
6345 | xnregs = 1; | |
6346 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
6347 | return 0; | |
6348 | if (xregno < valueno + valuenregs | |
6349 | && xregno + xnregs > valueno) | |
6350 | return 0; | |
6351 | if (goal_mem_addr_varies | |
bfa30b22 | 6352 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
eab89b90 | 6353 | return 0; |
1b4d8b2b R |
6354 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
6355 | return 0; | |
eab89b90 RK |
6356 | } |
6357 | else if (goal_mem && GET_CODE (dest) == MEM | |
6358 | && ! push_operand (dest, GET_MODE (dest))) | |
6359 | return 0; | |
9fac9680 RK |
6360 | else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER |
6361 | && reg_equiv_memory_loc[regno] != 0) | |
6362 | return 0; | |
eab89b90 RK |
6363 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) |
6364 | return 0; | |
6365 | } | |
6366 | else if (GET_CODE (pat) == PARALLEL) | |
6367 | { | |
6368 | register int i; | |
6369 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
6370 | { | |
6371 | register rtx v1 = XVECEXP (pat, 0, i); | |
6372 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) | |
6373 | { | |
6374 | register rtx dest = SET_DEST (v1); | |
6375 | while (GET_CODE (dest) == SUBREG | |
6376 | || GET_CODE (dest) == ZERO_EXTRACT | |
6377 | || GET_CODE (dest) == SIGN_EXTRACT | |
6378 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6379 | dest = XEXP (dest, 0); | |
6380 | if (GET_CODE (dest) == REG) | |
6381 | { | |
6382 | register int xregno = REGNO (dest); | |
6383 | int xnregs; | |
6384 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
6385 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
6386 | else | |
6387 | xnregs = 1; | |
6388 | if (xregno < regno + nregs | |
6389 | && xregno + xnregs > regno) | |
6390 | return 0; | |
6391 | if (xregno < valueno + valuenregs | |
6392 | && xregno + xnregs > valueno) | |
6393 | return 0; | |
6394 | if (goal_mem_addr_varies | |
bfa30b22 RK |
6395 | && reg_overlap_mentioned_for_reload_p (dest, |
6396 | goal)) | |
eab89b90 | 6397 | return 0; |
930176e7 R |
6398 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
6399 | return 0; | |
eab89b90 RK |
6400 | } |
6401 | else if (goal_mem && GET_CODE (dest) == MEM | |
6402 | && ! push_operand (dest, GET_MODE (dest))) | |
6403 | return 0; | |
e9a25f70 JL |
6404 | else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER |
6405 | && reg_equiv_memory_loc[regno] != 0) | |
6406 | return 0; | |
369c7ab6 JW |
6407 | else if (need_stable_sp |
6408 | && push_operand (dest, GET_MODE (dest))) | |
6409 | return 0; | |
6410 | } | |
6411 | } | |
6412 | } | |
6413 | ||
6414 | if (GET_CODE (p) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (p)) | |
6415 | { | |
6416 | rtx link; | |
6417 | ||
6418 | for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0; | |
6419 | link = XEXP (link, 1)) | |
6420 | { | |
6421 | pat = XEXP (link, 0); | |
6422 | if (GET_CODE (pat) == CLOBBER) | |
6423 | { | |
6424 | register rtx dest = SET_DEST (pat); | |
6425 | while (GET_CODE (dest) == SUBREG | |
6426 | || GET_CODE (dest) == ZERO_EXTRACT | |
6427 | || GET_CODE (dest) == SIGN_EXTRACT | |
6428 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6429 | dest = XEXP (dest, 0); | |
6430 | if (GET_CODE (dest) == REG) | |
6431 | { | |
6432 | register int xregno = REGNO (dest); | |
6433 | int xnregs; | |
6434 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
6435 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
6436 | else | |
6437 | xnregs = 1; | |
6438 | if (xregno < regno + nregs | |
6439 | && xregno + xnregs > regno) | |
6440 | return 0; | |
6441 | if (xregno < valueno + valuenregs | |
6442 | && xregno + xnregs > valueno) | |
6443 | return 0; | |
6444 | if (goal_mem_addr_varies | |
6445 | && reg_overlap_mentioned_for_reload_p (dest, | |
6446 | goal)) | |
6447 | return 0; | |
6448 | } | |
6449 | else if (goal_mem && GET_CODE (dest) == MEM | |
6450 | && ! push_operand (dest, GET_MODE (dest))) | |
6451 | return 0; | |
eab89b90 RK |
6452 | else if (need_stable_sp |
6453 | && push_operand (dest, GET_MODE (dest))) | |
6454 | return 0; | |
6455 | } | |
6456 | } | |
6457 | } | |
6458 | ||
6459 | #ifdef AUTO_INC_DEC | |
6460 | /* If this insn auto-increments or auto-decrements | |
6461 | either regno or valueno, return 0 now. | |
6462 | If GOAL is a memory ref and its address is not constant, | |
6463 | and this insn P increments a register used in GOAL, return 0. */ | |
6464 | { | |
6465 | register rtx link; | |
6466 | ||
6467 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
6468 | if (REG_NOTE_KIND (link) == REG_INC | |
6469 | && GET_CODE (XEXP (link, 0)) == REG) | |
6470 | { | |
6471 | register int incno = REGNO (XEXP (link, 0)); | |
6472 | if (incno < regno + nregs && incno >= regno) | |
6473 | return 0; | |
6474 | if (incno < valueno + valuenregs && incno >= valueno) | |
6475 | return 0; | |
6476 | if (goal_mem_addr_varies | |
bfa30b22 RK |
6477 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
6478 | goal)) | |
eab89b90 RK |
6479 | return 0; |
6480 | } | |
6481 | } | |
6482 | #endif | |
6483 | } | |
6484 | } | |
6485 | } | |
6486 | \f | |
6487 | /* Find a place where INCED appears in an increment or decrement operator | |
6488 | within X, and return the amount INCED is incremented or decremented by. | |
6489 | The value is always positive. */ | |
6490 | ||
6491 | static int | |
6492 | find_inc_amount (x, inced) | |
6493 | rtx x, inced; | |
6494 | { | |
6495 | register enum rtx_code code = GET_CODE (x); | |
6f7d635c | 6496 | register const char *fmt; |
eab89b90 RK |
6497 | register int i; |
6498 | ||
6499 | if (code == MEM) | |
6500 | { | |
6501 | register rtx addr = XEXP (x, 0); | |
6502 | if ((GET_CODE (addr) == PRE_DEC | |
6503 | || GET_CODE (addr) == POST_DEC | |
6504 | || GET_CODE (addr) == PRE_INC | |
6505 | || GET_CODE (addr) == POST_INC) | |
6506 | && XEXP (addr, 0) == inced) | |
6507 | return GET_MODE_SIZE (GET_MODE (x)); | |
6508 | } | |
6509 | ||
6510 | fmt = GET_RTX_FORMAT (code); | |
6511 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6512 | { | |
6513 | if (fmt[i] == 'e') | |
6514 | { | |
6515 | register int tem = find_inc_amount (XEXP (x, i), inced); | |
6516 | if (tem != 0) | |
6517 | return tem; | |
6518 | } | |
6519 | if (fmt[i] == 'E') | |
6520 | { | |
6521 | register int j; | |
6522 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6523 | { | |
6524 | register int tem = find_inc_amount (XVECEXP (x, i, j), inced); | |
6525 | if (tem != 0) | |
6526 | return tem; | |
6527 | } | |
6528 | } | |
6529 | } | |
6530 | ||
6531 | return 0; | |
6532 | } | |
6533 | \f | |
6534 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ | |
6535 | ||
6536 | int | |
6537 | regno_clobbered_p (regno, insn) | |
6538 | int regno; | |
6539 | rtx insn; | |
6540 | { | |
6541 | if (GET_CODE (PATTERN (insn)) == CLOBBER | |
6542 | && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) | |
6543 | return REGNO (XEXP (PATTERN (insn), 0)) == regno; | |
6544 | ||
6545 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
6546 | { | |
6547 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
6548 | ||
6549 | for (; i >= 0; i--) | |
6550 | { | |
6551 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
6552 | if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG | |
6553 | && REGNO (XEXP (elt, 0)) == regno) | |
6554 | return 1; | |
6555 | } | |
6556 | } | |
6557 | ||
6558 | return 0; | |
6559 | } | |
10bcde0d | 6560 | |
6f7d635c | 6561 | static const char *reload_when_needed_name[] = |
10bcde0d | 6562 | { |
05d10675 BS |
6563 | "RELOAD_FOR_INPUT", |
6564 | "RELOAD_FOR_OUTPUT", | |
10bcde0d | 6565 | "RELOAD_FOR_INSN", |
47c8cf91 ILT |
6566 | "RELOAD_FOR_INPUT_ADDRESS", |
6567 | "RELOAD_FOR_INPADDR_ADDRESS", | |
10bcde0d | 6568 | "RELOAD_FOR_OUTPUT_ADDRESS", |
47c8cf91 | 6569 | "RELOAD_FOR_OUTADDR_ADDRESS", |
05d10675 | 6570 | "RELOAD_FOR_OPERAND_ADDRESS", |
10bcde0d | 6571 | "RELOAD_FOR_OPADDR_ADDR", |
05d10675 | 6572 | "RELOAD_OTHER", |
10bcde0d RK |
6573 | "RELOAD_FOR_OTHER_ADDRESS" |
6574 | }; | |
6575 | ||
6f7d635c | 6576 | static const char * const reg_class_names[] = REG_CLASS_NAMES; |
10bcde0d | 6577 | |
b8fb2d72 | 6578 | /* These functions are used to print the variables set by 'find_reloads' */ |
10bcde0d RK |
6579 | |
6580 | void | |
b8fb2d72 CI |
6581 | debug_reload_to_stream (f) |
6582 | FILE *f; | |
10bcde0d RK |
6583 | { |
6584 | int r; | |
6f7d635c | 6585 | const char *prefix; |
10bcde0d | 6586 | |
b8fb2d72 CI |
6587 | if (! f) |
6588 | f = stderr; | |
10bcde0d RK |
6589 | for (r = 0; r < n_reloads; r++) |
6590 | { | |
b8fb2d72 | 6591 | fprintf (f, "Reload %d: ", r); |
10bcde0d | 6592 | |
eceef4c9 | 6593 | if (rld[r].in != 0) |
10bcde0d | 6594 | { |
b8fb2d72 | 6595 | fprintf (f, "reload_in (%s) = ", |
eceef4c9 BS |
6596 | GET_MODE_NAME (rld[r].inmode)); |
6597 | print_inline_rtx (f, rld[r].in, 24); | |
b8fb2d72 | 6598 | fprintf (f, "\n\t"); |
10bcde0d RK |
6599 | } |
6600 | ||
eceef4c9 | 6601 | if (rld[r].out != 0) |
10bcde0d | 6602 | { |
b8fb2d72 | 6603 | fprintf (f, "reload_out (%s) = ", |
eceef4c9 BS |
6604 | GET_MODE_NAME (rld[r].outmode)); |
6605 | print_inline_rtx (f, rld[r].out, 24); | |
b8fb2d72 | 6606 | fprintf (f, "\n\t"); |
10bcde0d RK |
6607 | } |
6608 | ||
eceef4c9 | 6609 | fprintf (f, "%s, ", reg_class_names[(int) rld[r].class]); |
10bcde0d | 6610 | |
b8fb2d72 | 6611 | fprintf (f, "%s (opnum = %d)", |
eceef4c9 BS |
6612 | reload_when_needed_name[(int) rld[r].when_needed], |
6613 | rld[r].opnum); | |
10bcde0d | 6614 | |
eceef4c9 | 6615 | if (rld[r].optional) |
b8fb2d72 | 6616 | fprintf (f, ", optional"); |
10bcde0d | 6617 | |
eceef4c9 | 6618 | if (rld[r].nongroup) |
f5963e61 JL |
6619 | fprintf (stderr, ", nongroup"); |
6620 | ||
eceef4c9 BS |
6621 | if (rld[r].inc != 0) |
6622 | fprintf (f, ", inc by %d", rld[r].inc); | |
10bcde0d | 6623 | |
eceef4c9 | 6624 | if (rld[r].nocombine) |
b8fb2d72 | 6625 | fprintf (f, ", can't combine"); |
10bcde0d | 6626 | |
eceef4c9 | 6627 | if (rld[r].secondary_p) |
b8fb2d72 | 6628 | fprintf (f, ", secondary_reload_p"); |
10bcde0d | 6629 | |
eceef4c9 | 6630 | if (rld[r].in_reg != 0) |
10bcde0d | 6631 | { |
b8fb2d72 | 6632 | fprintf (f, "\n\treload_in_reg: "); |
eceef4c9 | 6633 | print_inline_rtx (f, rld[r].in_reg, 24); |
10bcde0d RK |
6634 | } |
6635 | ||
eceef4c9 | 6636 | if (rld[r].out_reg != 0) |
cb2afeb3 R |
6637 | { |
6638 | fprintf (f, "\n\treload_out_reg: "); | |
eceef4c9 | 6639 | print_inline_rtx (f, rld[r].out_reg, 24); |
cb2afeb3 R |
6640 | } |
6641 | ||
eceef4c9 | 6642 | if (rld[r].reg_rtx != 0) |
10bcde0d | 6643 | { |
b8fb2d72 | 6644 | fprintf (f, "\n\treload_reg_rtx: "); |
eceef4c9 | 6645 | print_inline_rtx (f, rld[r].reg_rtx, 24); |
10bcde0d RK |
6646 | } |
6647 | ||
505923a0 | 6648 | prefix = "\n\t"; |
eceef4c9 | 6649 | if (rld[r].secondary_in_reload != -1) |
10bcde0d | 6650 | { |
b8fb2d72 | 6651 | fprintf (f, "%ssecondary_in_reload = %d", |
eceef4c9 | 6652 | prefix, rld[r].secondary_in_reload); |
505923a0 | 6653 | prefix = ", "; |
10bcde0d RK |
6654 | } |
6655 | ||
eceef4c9 | 6656 | if (rld[r].secondary_out_reload != -1) |
b8fb2d72 | 6657 | fprintf (f, "%ssecondary_out_reload = %d\n", |
eceef4c9 | 6658 | prefix, rld[r].secondary_out_reload); |
10bcde0d | 6659 | |
505923a0 | 6660 | prefix = "\n\t"; |
eceef4c9 | 6661 | if (rld[r].secondary_in_icode != CODE_FOR_nothing) |
10bcde0d | 6662 | { |
e5e809f4 | 6663 | fprintf (stderr, "%ssecondary_in_icode = %s", prefix, |
eceef4c9 | 6664 | insn_data[rld[r].secondary_in_icode].name); |
505923a0 | 6665 | prefix = ", "; |
10bcde0d RK |
6666 | } |
6667 | ||
eceef4c9 | 6668 | if (rld[r].secondary_out_icode != CODE_FOR_nothing) |
e5e809f4 | 6669 | fprintf (stderr, "%ssecondary_out_icode = %s", prefix, |
eceef4c9 | 6670 | insn_data[rld[r].secondary_out_icode].name); |
10bcde0d | 6671 | |
b8fb2d72 | 6672 | fprintf (f, "\n"); |
10bcde0d | 6673 | } |
10bcde0d | 6674 | } |
b8fb2d72 CI |
6675 | |
6676 | void | |
6677 | debug_reload () | |
6678 | { | |
6679 | debug_reload_to_stream (stderr); | |
6680 | } |