]>
Commit | Line | Data |
---|---|---|
eab89b90 | 1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
2fd0af53 | 2 | Copyright (C) 1987, 88, 89, 92-7, 1998 Free Software Foundation, Inc. |
eab89b90 RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
eab89b90 RK |
20 | |
21 | ||
22 | /* This file contains subroutines used only from the file reload1.c. | |
23 | It knows how to scan one insn for operands and values | |
24 | that need to be copied into registers to make valid code. | |
25 | It also finds other operands and values which are valid | |
26 | but for which equivalent values in registers exist and | |
27 | ought to be used instead. | |
28 | ||
29 | Before processing the first insn of the function, call `init_reload'. | |
30 | ||
31 | To scan an insn, call `find_reloads'. This does two things: | |
32 | 1. sets up tables describing which values must be reloaded | |
33 | for this insn, and what kind of hard regs they must be reloaded into; | |
34 | 2. optionally record the locations where those values appear in | |
35 | the data, so they can be replaced properly later. | |
36 | This is done only if the second arg to `find_reloads' is nonzero. | |
37 | ||
38 | The third arg to `find_reloads' specifies the number of levels | |
39 | of indirect addressing supported by the machine. If it is zero, | |
40 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
41 | is valid even if (REG n) did not get a hard register; if it is two, | |
42 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
43 | hard register, and similarly for higher values. | |
44 | ||
45 | Then you must choose the hard regs to reload those pseudo regs into, | |
46 | and generate appropriate load insns before this insn and perhaps | |
47 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
48 | to contain the REG rtx's for the registers you used. In some | |
49 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
50 | for certain reloads. Then that tells you which register to use, | |
51 | so you do not need to allocate one. But you still do need to add extra | |
52 | instructions to copy the value into and out of that register. | |
53 | ||
54 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
55 | into the locations already recorded. | |
56 | ||
57 | NOTE SIDE EFFECTS: | |
58 | ||
59 | find_reloads can alter the operands of the instruction it is called on. | |
60 | ||
61 | 1. Two operands of any sort may be interchanged, if they are in a | |
62 | commutative instruction. | |
63 | This happens only if find_reloads thinks the instruction will compile | |
64 | better that way. | |
65 | ||
66 | 2. Pseudo-registers that are equivalent to constants are replaced | |
67 | with those constants if they are not in hard registers. | |
68 | ||
69 | 1 happens every time find_reloads is called. | |
70 | 2 happens only when REPLACE is 1, which is only when | |
71 | actually doing the reloads, not when just counting them. | |
72 | ||
73 | ||
74 | Using a reload register for several reloads in one insn: | |
75 | ||
76 | When an insn has reloads, it is considered as having three parts: | |
77 | the input reloads, the insn itself after reloading, and the output reloads. | |
78 | Reloads of values used in memory addresses are often needed for only one part. | |
79 | ||
80 | When this is so, reload_when_needed records which part needs the reload. | |
81 | Two reloads for different parts of the insn can share the same reload | |
82 | register. | |
83 | ||
84 | When a reload is used for addresses in multiple parts, or when it is | |
85 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
86 | a register with any other reload. */ | |
87 | ||
88 | #define REG_OK_STRICT | |
89 | ||
90 | #include "config.h" | |
e9a25f70 | 91 | #include <stdio.h> |
eab89b90 RK |
92 | #include "rtl.h" |
93 | #include "insn-config.h" | |
94 | #include "insn-codes.h" | |
95 | #include "recog.h" | |
96 | #include "reload.h" | |
97 | #include "regs.h" | |
98 | #include "hard-reg-set.h" | |
99 | #include "flags.h" | |
100 | #include "real.h" | |
8a840ac9 | 101 | #include "output.h" |
55c22565 | 102 | #include "expr.h" |
eab89b90 RK |
103 | |
104 | #ifndef REGISTER_MOVE_COST | |
105 | #define REGISTER_MOVE_COST(x, y) 2 | |
106 | #endif | |
858c3c8c ILT |
107 | |
108 | #ifndef REGNO_MODE_OK_FOR_BASE_P | |
109 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO) | |
110 | #endif | |
111 | ||
112 | #ifndef REG_MODE_OK_FOR_BASE_P | |
113 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
114 | #endif | |
eab89b90 RK |
115 | \f |
116 | /* The variables set up by `find_reloads' are: | |
117 | ||
118 | n_reloads number of distinct reloads needed; max reload # + 1 | |
119 | tables indexed by reload number | |
120 | reload_in rtx for value to reload from | |
121 | reload_out rtx for where to store reload-reg afterward if nec | |
122 | (often the same as reload_in) | |
123 | reload_reg_class enum reg_class, saying what regs to reload into | |
124 | reload_inmode enum machine_mode; mode this operand should have | |
125 | when reloaded, on input. | |
126 | reload_outmode enum machine_mode; mode this operand should have | |
127 | when reloaded, on output. | |
eab89b90 RK |
128 | reload_optional char, nonzero for an optional reload. |
129 | Optional reloads are ignored unless the | |
130 | value is already sitting in a register. | |
131 | reload_inc int, positive amount to increment or decrement by if | |
132 | reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC. | |
133 | Ignored otherwise (don't assume it is zero). | |
134 | reload_in_reg rtx. A reg for which reload_in is the equivalent. | |
135 | If reload_in is a symbol_ref which came from | |
136 | reg_equiv_constant, then this is the pseudo | |
137 | which has that symbol_ref as equivalent. | |
138 | reload_reg_rtx rtx. This is the register to reload into. | |
139 | If it is zero when `find_reloads' returns, | |
140 | you must find a suitable register in the class | |
141 | specified by reload_reg_class, and store here | |
142 | an rtx for that register with mode from | |
143 | reload_inmode or reload_outmode. | |
144 | reload_nocombine char, nonzero if this reload shouldn't be | |
145 | combined with another reload. | |
a8c9daeb RK |
146 | reload_opnum int, operand number being reloaded. This is |
147 | used to group related reloads and need not always | |
148 | be equal to the actual operand number in the insn, | |
149 | though it current will be; for in-out operands, it | |
150 | is one of the two operand numbers. | |
151 | reload_when_needed enum, classifies reload as needed either for | |
eab89b90 RK |
152 | addressing an input reload, addressing an output, |
153 | for addressing a non-reloaded mem ref, | |
154 | or for unspecified purposes (i.e., more than one | |
155 | of the above). | |
eab89b90 | 156 | reload_secondary_p int, 1 if this is a secondary register for one |
9ec7078b RK |
157 | or more reloads. |
158 | reload_secondary_in_reload | |
159 | reload_secondary_out_reload | |
160 | int, gives the reload number of a secondary | |
161 | reload, when needed; otherwise -1 | |
162 | reload_secondary_in_icode | |
163 | reload_secondary_out_icode | |
164 | enum insn_code, if a secondary reload is required, | |
eab89b90 RK |
165 | gives the INSN_CODE that uses the secondary |
166 | reload as a scratch register, or CODE_FOR_nothing | |
167 | if the secondary reload register is to be an | |
168 | intermediate register. */ | |
169 | int n_reloads; | |
170 | ||
171 | rtx reload_in[MAX_RELOADS]; | |
172 | rtx reload_out[MAX_RELOADS]; | |
173 | enum reg_class reload_reg_class[MAX_RELOADS]; | |
174 | enum machine_mode reload_inmode[MAX_RELOADS]; | |
175 | enum machine_mode reload_outmode[MAX_RELOADS]; | |
eab89b90 RK |
176 | rtx reload_reg_rtx[MAX_RELOADS]; |
177 | char reload_optional[MAX_RELOADS]; | |
178 | int reload_inc[MAX_RELOADS]; | |
179 | rtx reload_in_reg[MAX_RELOADS]; | |
180 | char reload_nocombine[MAX_RELOADS]; | |
a8c9daeb RK |
181 | int reload_opnum[MAX_RELOADS]; |
182 | enum reload_type reload_when_needed[MAX_RELOADS]; | |
eab89b90 | 183 | int reload_secondary_p[MAX_RELOADS]; |
9ec7078b RK |
184 | int reload_secondary_in_reload[MAX_RELOADS]; |
185 | int reload_secondary_out_reload[MAX_RELOADS]; | |
186 | enum insn_code reload_secondary_in_icode[MAX_RELOADS]; | |
187 | enum insn_code reload_secondary_out_icode[MAX_RELOADS]; | |
eab89b90 RK |
188 | |
189 | /* All the "earlyclobber" operands of the current insn | |
190 | are recorded here. */ | |
191 | int n_earlyclobbers; | |
192 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
193 | ||
a8c9daeb RK |
194 | int reload_n_operands; |
195 | ||
eab89b90 RK |
196 | /* Replacing reloads. |
197 | ||
198 | If `replace_reloads' is nonzero, then as each reload is recorded | |
199 | an entry is made for it in the table `replacements'. | |
200 | Then later `subst_reloads' can look through that table and | |
201 | perform all the replacements needed. */ | |
202 | ||
203 | /* Nonzero means record the places to replace. */ | |
204 | static int replace_reloads; | |
205 | ||
206 | /* Each replacement is recorded with a structure like this. */ | |
207 | struct replacement | |
208 | { | |
209 | rtx *where; /* Location to store in */ | |
210 | rtx *subreg_loc; /* Location of SUBREG if WHERE is inside | |
211 | a SUBREG; 0 otherwise. */ | |
212 | int what; /* which reload this is for */ | |
213 | enum machine_mode mode; /* mode it must have */ | |
214 | }; | |
215 | ||
216 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
217 | ||
218 | /* Number of replacements currently recorded. */ | |
219 | static int n_replacements; | |
220 | ||
a8c9daeb RK |
221 | /* Used to track what is modified by an operand. */ |
222 | struct decomposition | |
223 | { | |
0f41302f MS |
224 | int reg_flag; /* Nonzero if referencing a register. */ |
225 | int safe; /* Nonzero if this can't conflict with anything. */ | |
226 | rtx base; /* Base address for MEM. */ | |
227 | HOST_WIDE_INT start; /* Starting offset or register number. */ | |
2a6d5ce0 | 228 | HOST_WIDE_INT end; /* Ending offset or register number. */ |
a8c9daeb RK |
229 | }; |
230 | ||
eab89b90 RK |
231 | /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable; |
232 | (see reg_equiv_address). */ | |
233 | static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
234 | static int n_memlocs; | |
235 | ||
0dadecf6 RK |
236 | #ifdef SECONDARY_MEMORY_NEEDED |
237 | ||
238 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
239 | is used per mode, but normally only one or two modes are ever used. | |
240 | ||
a8c9daeb RK |
241 | We keep two versions, before and after register elimination. The one |
242 | after register elimination is record separately for each operand. This | |
243 | is done in case the address is not valid to be sure that we separately | |
244 | reload each. */ | |
0dadecf6 RK |
245 | |
246 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
77545d45 | 247 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; |
0dadecf6 RK |
248 | #endif |
249 | ||
eab89b90 RK |
250 | /* The instruction we are doing reloads for; |
251 | so we can test whether a register dies in it. */ | |
252 | static rtx this_insn; | |
253 | ||
254 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
255 | static int this_insn_is_asm; | |
256 | ||
257 | /* If hard_regs_live_known is nonzero, | |
258 | we can tell which hard regs are currently live, | |
259 | at least enough to succeed in choosing dummy reloads. */ | |
260 | static int hard_regs_live_known; | |
261 | ||
262 | /* Indexed by hard reg number, | |
956d6950 | 263 | element is nonnegative if hard reg has been spilled. |
eab89b90 RK |
264 | This vector is passed to `find_reloads' as an argument |
265 | and is not changed here. */ | |
266 | static short *static_reload_reg_p; | |
267 | ||
268 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
269 | static int subst_reg_equivs_changed; | |
270 | ||
271 | /* On return from push_reload, holds the reload-number for the OUT | |
272 | operand, which can be different for that from the input operand. */ | |
273 | static int output_reloadnum; | |
274 | ||
9ec7078b RK |
275 | /* Compare two RTX's. */ |
276 | #define MATCHES(x, y) \ | |
277 | (x == y || (x != 0 && (GET_CODE (x) == REG \ | |
278 | ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \ | |
279 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) | |
280 | ||
281 | /* Indicates if two reloads purposes are for similar enough things that we | |
282 | can merge their reloads. */ | |
283 | #define MERGABLE_RELOADS(when1, when2, op1, op2) \ | |
284 | ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ | |
285 | || ((when1) == (when2) && (op1) == (op2)) \ | |
286 | || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ | |
287 | || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
288 | && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ | |
289 | || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ | |
290 | && (when2) == RELOAD_FOR_OTHER_ADDRESS)) | |
291 | ||
292 | /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ | |
293 | #define MERGE_TO_OTHER(when1, when2, op1, op2) \ | |
294 | ((when1) != (when2) \ | |
295 | || ! ((op1) == (op2) \ | |
296 | || (when1) == RELOAD_FOR_INPUT \ | |
297 | || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
298 | || (when1) == RELOAD_FOR_OTHER_ADDRESS)) | |
299 | ||
47c8cf91 ILT |
300 | /* If we are going to reload an address, compute the reload type to |
301 | use. */ | |
302 | #define ADDR_TYPE(type) \ | |
303 | ((type) == RELOAD_FOR_INPUT_ADDRESS \ | |
304 | ? RELOAD_FOR_INPADDR_ADDRESS \ | |
305 | : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \ | |
306 | ? RELOAD_FOR_OUTADDR_ADDRESS \ | |
307 | : (type))) | |
308 | ||
9ec7078b RK |
309 | static int push_secondary_reload PROTO((int, rtx, int, int, enum reg_class, |
310 | enum machine_mode, enum reload_type, | |
311 | enum insn_code *)); | |
c6716840 | 312 | static enum reg_class find_valid_class PROTO((enum machine_mode, int)); |
a8c9daeb RK |
313 | static int push_reload PROTO((rtx, rtx, rtx *, rtx *, enum reg_class, |
314 | enum machine_mode, enum machine_mode, | |
315 | int, int, int, enum reload_type)); | |
316 | static void push_replacement PROTO((rtx *, int, enum machine_mode)); | |
317 | static void combine_reloads PROTO((void)); | |
318 | static rtx find_dummy_reload PROTO((rtx, rtx, rtx *, rtx *, | |
36b50568 | 319 | enum machine_mode, enum machine_mode, |
189086f9 | 320 | enum reg_class, int, int)); |
4644aad4 | 321 | static int earlyclobber_operand_p PROTO((rtx)); |
a8c9daeb RK |
322 | static int hard_reg_set_here_p PROTO((int, int, rtx)); |
323 | static struct decomposition decompose PROTO((rtx)); | |
324 | static int immune_p PROTO((rtx, rtx, struct decomposition)); | |
325 | static int alternative_allows_memconst PROTO((char *, int)); | |
326 | static rtx find_reloads_toplev PROTO((rtx, int, enum reload_type, int, int)); | |
327 | static rtx make_memloc PROTO((rtx, int)); | |
328 | static int find_reloads_address PROTO((enum machine_mode, rtx *, rtx, rtx *, | |
55c22565 | 329 | int, enum reload_type, int, rtx)); |
a8c9daeb RK |
330 | static rtx subst_reg_equivs PROTO((rtx)); |
331 | static rtx subst_indexed_address PROTO((rtx)); | |
858c3c8c | 332 | static int find_reloads_address_1 PROTO((enum machine_mode, rtx, int, rtx *, |
55c22565 | 333 | int, enum reload_type,int, rtx)); |
a8c9daeb RK |
334 | static void find_reloads_address_part PROTO((rtx, rtx *, enum reg_class, |
335 | enum machine_mode, int, | |
336 | enum reload_type, int)); | |
337 | static int find_inc_amount PROTO((rtx, rtx)); | |
eab89b90 RK |
338 | \f |
339 | #ifdef HAVE_SECONDARY_RELOADS | |
340 | ||
341 | /* Determine if any secondary reloads are needed for loading (if IN_P is | |
342 | non-zero) or storing (if IN_P is zero) X to or from a reload register of | |
9ec7078b RK |
343 | register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads |
344 | are needed, push them. | |
345 | ||
346 | Return the reload number of the secondary reload we made, or -1 if | |
347 | we didn't need one. *PICODE is set to the insn_code to use if we do | |
348 | need a secondary reload. */ | |
349 | ||
350 | static int | |
351 | push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode, | |
352 | type, picode) | |
353 | int in_p; | |
eab89b90 | 354 | rtx x; |
9ec7078b RK |
355 | int opnum; |
356 | int optional; | |
eab89b90 RK |
357 | enum reg_class reload_class; |
358 | enum machine_mode reload_mode; | |
9ec7078b | 359 | enum reload_type type; |
eab89b90 | 360 | enum insn_code *picode; |
eab89b90 RK |
361 | { |
362 | enum reg_class class = NO_REGS; | |
363 | enum machine_mode mode = reload_mode; | |
364 | enum insn_code icode = CODE_FOR_nothing; | |
365 | enum reg_class t_class = NO_REGS; | |
366 | enum machine_mode t_mode = VOIDmode; | |
367 | enum insn_code t_icode = CODE_FOR_nothing; | |
d94d2abc | 368 | enum reload_type secondary_type; |
9ec7078b RK |
369 | int s_reload, t_reload = -1; |
370 | ||
47c8cf91 ILT |
371 | if (type == RELOAD_FOR_INPUT_ADDRESS |
372 | || type == RELOAD_FOR_OUTPUT_ADDRESS | |
373 | || type == RELOAD_FOR_INPADDR_ADDRESS | |
374 | || type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d94d2abc RK |
375 | secondary_type = type; |
376 | else | |
377 | secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS; | |
378 | ||
9ec7078b | 379 | *picode = CODE_FOR_nothing; |
eab89b90 | 380 | |
67340b03 RK |
381 | /* If X is a paradoxical SUBREG, use the inner value to determine both the |
382 | mode and object being reloaded. */ | |
383 | if (GET_CODE (x) == SUBREG | |
384 | && (GET_MODE_SIZE (GET_MODE (x)) | |
385 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
386 | { | |
387 | x = SUBREG_REG (x); | |
388 | reload_mode = GET_MODE (x); | |
389 | } | |
390 | ||
d45cf215 RS |
391 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
392 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
393 | but we don't want to assume that), use that equivalent when seeing if | |
394 | a secondary reload is needed since whether or not a reload is needed | |
395 | might be sensitive to the form of the MEM. */ | |
396 | ||
397 | if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
398 | && reg_equiv_mem[REGNO (x)] != 0) | |
399 | x = reg_equiv_mem[REGNO (x)]; | |
400 | ||
eab89b90 RK |
401 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
402 | if (in_p) | |
403 | class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
404 | #endif | |
405 | ||
406 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
407 | if (! in_p) | |
408 | class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
409 | #endif | |
410 | ||
9ec7078b | 411 | /* If we don't need any secondary registers, done. */ |
eab89b90 | 412 | if (class == NO_REGS) |
9ec7078b | 413 | return -1; |
eab89b90 RK |
414 | |
415 | /* Get a possible insn to use. If the predicate doesn't accept X, don't | |
416 | use the insn. */ | |
417 | ||
418 | icode = (in_p ? reload_in_optab[(int) reload_mode] | |
419 | : reload_out_optab[(int) reload_mode]); | |
420 | ||
421 | if (icode != CODE_FOR_nothing | |
422 | && insn_operand_predicate[(int) icode][in_p] | |
423 | && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode))) | |
424 | icode = CODE_FOR_nothing; | |
425 | ||
426 | /* If we will be using an insn, see if it can directly handle the reload | |
427 | register we will be using. If it can, the secondary reload is for a | |
428 | scratch register. If it can't, we will use the secondary reload for | |
429 | an intermediate register and require a tertiary reload for the scratch | |
430 | register. */ | |
431 | ||
432 | if (icode != CODE_FOR_nothing) | |
433 | { | |
434 | /* If IN_P is non-zero, the reload register will be the output in | |
435 | operand 0. If IN_P is zero, the reload register will be the input | |
436 | in operand 1. Outputs should have an initial "=", which we must | |
437 | skip. */ | |
438 | ||
d45cf215 | 439 | char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p]; |
eab89b90 | 440 | enum reg_class insn_class |
d45cf215 RS |
441 | = (insn_letter == 'r' ? GENERAL_REGS |
442 | : REG_CLASS_FROM_LETTER (insn_letter)); | |
eab89b90 RK |
443 | |
444 | if (insn_class == NO_REGS | |
445 | || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=') | |
446 | /* The scratch register's constraint must start with "=&". */ | |
447 | || insn_operand_constraint[(int) icode][2][0] != '=' | |
448 | || insn_operand_constraint[(int) icode][2][1] != '&') | |
449 | abort (); | |
450 | ||
451 | if (reg_class_subset_p (reload_class, insn_class)) | |
452 | mode = insn_operand_mode[(int) icode][2]; | |
453 | else | |
454 | { | |
d45cf215 | 455 | char t_letter = insn_operand_constraint[(int) icode][2][2]; |
eab89b90 RK |
456 | class = insn_class; |
457 | t_mode = insn_operand_mode[(int) icode][2]; | |
d45cf215 RS |
458 | t_class = (t_letter == 'r' ? GENERAL_REGS |
459 | : REG_CLASS_FROM_LETTER (t_letter)); | |
eab89b90 RK |
460 | t_icode = icode; |
461 | icode = CODE_FOR_nothing; | |
462 | } | |
463 | } | |
464 | ||
9ec7078b RK |
465 | /* This case isn't valid, so fail. Reload is allowed to use the same |
466 | register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but | |
467 | in the case of a secondary register, we actually need two different | |
468 | registers for correct code. We fail here to prevent the possibility of | |
469 | silently generating incorrect code later. | |
470 | ||
471 | The convention is that secondary input reloads are valid only if the | |
472 | secondary_class is different from class. If you have such a case, you | |
473 | can not use secondary reloads, you must work around the problem some | |
474 | other way. | |
475 | ||
476 | Allow this when MODE is not reload_mode and assume that the generated | |
477 | code handles this case (it does on the Alpha, which is the only place | |
478 | this currently happens). */ | |
479 | ||
480 | if (in_p && class == reload_class && mode == reload_mode) | |
481 | abort (); | |
482 | ||
483 | /* If we need a tertiary reload, see if we have one we can reuse or else | |
484 | make a new one. */ | |
485 | ||
486 | if (t_class != NO_REGS) | |
487 | { | |
488 | for (t_reload = 0; t_reload < n_reloads; t_reload++) | |
489 | if (reload_secondary_p[t_reload] | |
490 | && (reg_class_subset_p (t_class, reload_reg_class[t_reload]) | |
491 | || reg_class_subset_p (reload_reg_class[t_reload], t_class)) | |
492 | && ((in_p && reload_inmode[t_reload] == t_mode) | |
493 | || (! in_p && reload_outmode[t_reload] == t_mode)) | |
494 | && ((in_p && (reload_secondary_in_icode[t_reload] | |
495 | == CODE_FOR_nothing)) | |
496 | || (! in_p &&(reload_secondary_out_icode[t_reload] | |
497 | == CODE_FOR_nothing))) | |
e9a25f70 | 498 | && (reg_class_size[(int) t_class] == 1 || SMALL_REGISTER_CLASSES) |
9ec7078b RK |
499 | && MERGABLE_RELOADS (secondary_type, |
500 | reload_when_needed[t_reload], | |
501 | opnum, reload_opnum[t_reload])) | |
502 | { | |
503 | if (in_p) | |
504 | reload_inmode[t_reload] = t_mode; | |
505 | if (! in_p) | |
506 | reload_outmode[t_reload] = t_mode; | |
507 | ||
508 | if (reg_class_subset_p (t_class, reload_reg_class[t_reload])) | |
509 | reload_reg_class[t_reload] = t_class; | |
510 | ||
511 | reload_opnum[t_reload] = MIN (reload_opnum[t_reload], opnum); | |
512 | reload_optional[t_reload] &= optional; | |
513 | reload_secondary_p[t_reload] = 1; | |
514 | if (MERGE_TO_OTHER (secondary_type, reload_when_needed[t_reload], | |
515 | opnum, reload_opnum[t_reload])) | |
516 | reload_when_needed[t_reload] = RELOAD_OTHER; | |
517 | } | |
518 | ||
519 | if (t_reload == n_reloads) | |
520 | { | |
521 | /* We need to make a new tertiary reload for this register class. */ | |
522 | reload_in[t_reload] = reload_out[t_reload] = 0; | |
523 | reload_reg_class[t_reload] = t_class; | |
524 | reload_inmode[t_reload] = in_p ? t_mode : VOIDmode; | |
525 | reload_outmode[t_reload] = ! in_p ? t_mode : VOIDmode; | |
526 | reload_reg_rtx[t_reload] = 0; | |
527 | reload_optional[t_reload] = optional; | |
528 | reload_inc[t_reload] = 0; | |
529 | /* Maybe we could combine these, but it seems too tricky. */ | |
530 | reload_nocombine[t_reload] = 1; | |
531 | reload_in_reg[t_reload] = 0; | |
532 | reload_opnum[t_reload] = opnum; | |
533 | reload_when_needed[t_reload] = secondary_type; | |
534 | reload_secondary_in_reload[t_reload] = -1; | |
535 | reload_secondary_out_reload[t_reload] = -1; | |
536 | reload_secondary_in_icode[t_reload] = CODE_FOR_nothing; | |
537 | reload_secondary_out_icode[t_reload] = CODE_FOR_nothing; | |
538 | reload_secondary_p[t_reload] = 1; | |
539 | ||
540 | n_reloads++; | |
541 | } | |
542 | } | |
543 | ||
544 | /* See if we can reuse an existing secondary reload. */ | |
545 | for (s_reload = 0; s_reload < n_reloads; s_reload++) | |
546 | if (reload_secondary_p[s_reload] | |
547 | && (reg_class_subset_p (class, reload_reg_class[s_reload]) | |
548 | || reg_class_subset_p (reload_reg_class[s_reload], class)) | |
549 | && ((in_p && reload_inmode[s_reload] == mode) | |
550 | || (! in_p && reload_outmode[s_reload] == mode)) | |
551 | && ((in_p && reload_secondary_in_reload[s_reload] == t_reload) | |
552 | || (! in_p && reload_secondary_out_reload[s_reload] == t_reload)) | |
553 | && ((in_p && reload_secondary_in_icode[s_reload] == t_icode) | |
554 | || (! in_p && reload_secondary_out_icode[s_reload] == t_icode)) | |
e9a25f70 | 555 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
9ec7078b RK |
556 | && MERGABLE_RELOADS (secondary_type, reload_when_needed[s_reload], |
557 | opnum, reload_opnum[s_reload])) | |
558 | { | |
559 | if (in_p) | |
560 | reload_inmode[s_reload] = mode; | |
561 | if (! in_p) | |
562 | reload_outmode[s_reload] = mode; | |
563 | ||
564 | if (reg_class_subset_p (class, reload_reg_class[s_reload])) | |
565 | reload_reg_class[s_reload] = class; | |
566 | ||
567 | reload_opnum[s_reload] = MIN (reload_opnum[s_reload], opnum); | |
568 | reload_optional[s_reload] &= optional; | |
569 | reload_secondary_p[s_reload] = 1; | |
570 | if (MERGE_TO_OTHER (secondary_type, reload_when_needed[s_reload], | |
571 | opnum, reload_opnum[s_reload])) | |
572 | reload_when_needed[s_reload] = RELOAD_OTHER; | |
573 | } | |
eab89b90 | 574 | |
9ec7078b RK |
575 | if (s_reload == n_reloads) |
576 | { | |
e9a25f70 JL |
577 | #ifdef SECONDARY_MEMORY_NEEDED |
578 | /* If we need a memory location to copy between the two reload regs, | |
579 | set it up now. Note that we do the input case before making | |
580 | the reload and the output case after. This is due to the | |
581 | way reloads are output. */ | |
582 | ||
583 | if (in_p && icode == CODE_FOR_nothing | |
584 | && SECONDARY_MEMORY_NEEDED (class, reload_class, mode)) | |
585 | get_secondary_mem (x, reload_mode, opnum, type); | |
586 | #endif | |
587 | ||
9ec7078b RK |
588 | /* We need to make a new secondary reload for this register class. */ |
589 | reload_in[s_reload] = reload_out[s_reload] = 0; | |
590 | reload_reg_class[s_reload] = class; | |
591 | ||
592 | reload_inmode[s_reload] = in_p ? mode : VOIDmode; | |
593 | reload_outmode[s_reload] = ! in_p ? mode : VOIDmode; | |
594 | reload_reg_rtx[s_reload] = 0; | |
595 | reload_optional[s_reload] = optional; | |
596 | reload_inc[s_reload] = 0; | |
597 | /* Maybe we could combine these, but it seems too tricky. */ | |
598 | reload_nocombine[s_reload] = 1; | |
599 | reload_in_reg[s_reload] = 0; | |
600 | reload_opnum[s_reload] = opnum; | |
601 | reload_when_needed[s_reload] = secondary_type; | |
602 | reload_secondary_in_reload[s_reload] = in_p ? t_reload : -1; | |
603 | reload_secondary_out_reload[s_reload] = ! in_p ? t_reload : -1; | |
604 | reload_secondary_in_icode[s_reload] = in_p ? t_icode : CODE_FOR_nothing; | |
605 | reload_secondary_out_icode[s_reload] | |
606 | = ! in_p ? t_icode : CODE_FOR_nothing; | |
607 | reload_secondary_p[s_reload] = 1; | |
608 | ||
609 | n_reloads++; | |
610 | ||
611 | #ifdef SECONDARY_MEMORY_NEEDED | |
9ec7078b | 612 | if (! in_p && icode == CODE_FOR_nothing |
f49e4127 JW |
613 | && SECONDARY_MEMORY_NEEDED (reload_class, class, mode)) |
614 | get_secondary_mem (x, mode, opnum, type); | |
9ec7078b RK |
615 | #endif |
616 | } | |
617 | ||
618 | *picode = icode; | |
619 | return s_reload; | |
eab89b90 RK |
620 | } |
621 | #endif /* HAVE_SECONDARY_RELOADS */ | |
622 | \f | |
0dadecf6 RK |
623 | #ifdef SECONDARY_MEMORY_NEEDED |
624 | ||
625 | /* Return a memory location that will be used to copy X in mode MODE. | |
626 | If we haven't already made a location for this mode in this insn, | |
627 | call find_reloads_address on the location being returned. */ | |
628 | ||
629 | rtx | |
a8c9daeb | 630 | get_secondary_mem (x, mode, opnum, type) |
0dadecf6 RK |
631 | rtx x; |
632 | enum machine_mode mode; | |
a8c9daeb RK |
633 | int opnum; |
634 | enum reload_type type; | |
0dadecf6 RK |
635 | { |
636 | rtx loc; | |
637 | int mem_valid; | |
638 | ||
64609742 RK |
639 | /* By default, if MODE is narrower than a word, widen it to a word. |
640 | This is required because most machines that require these memory | |
641 | locations do not support short load and stores from all registers | |
642 | (e.g., FP registers). */ | |
643 | ||
644 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
645 | mode = SECONDARY_MEMORY_NEEDED_MODE (mode); | |
646 | #else | |
0dadecf6 RK |
647 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD) |
648 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); | |
64609742 | 649 | #endif |
0dadecf6 | 650 | |
77545d45 RK |
651 | /* If we already have made a MEM for this operand in MODE, return it. */ |
652 | if (secondary_memlocs_elim[(int) mode][opnum] != 0) | |
653 | return secondary_memlocs_elim[(int) mode][opnum]; | |
0dadecf6 RK |
654 | |
655 | /* If this is the first time we've tried to get a MEM for this mode, | |
656 | allocate a new one. `something_changed' in reload will get set | |
657 | by noticing that the frame size has changed. */ | |
658 | ||
659 | if (secondary_memlocs[(int) mode] == 0) | |
b24a53d5 JW |
660 | { |
661 | #ifdef SECONDARY_MEMORY_NEEDED_RTX | |
662 | secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); | |
663 | #else | |
664 | secondary_memlocs[(int) mode] | |
665 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
666 | #endif | |
667 | } | |
0dadecf6 RK |
668 | |
669 | /* Get a version of the address doing any eliminations needed. If that | |
670 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
671 | ||
1914f5da | 672 | loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); |
0dadecf6 RK |
673 | mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); |
674 | ||
675 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
676 | loc = copy_rtx (loc); | |
677 | ||
678 | /* The only time the call below will do anything is if the stack | |
679 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
a8c9daeb RK |
680 | can just pass a zero. Adjust the type to be the address of the |
681 | corresponding object. If the address was valid, save the eliminated | |
682 | address. If it wasn't valid, we need to make a reload each time, so | |
683 | don't save it. */ | |
0dadecf6 | 684 | |
a8c9daeb RK |
685 | if (! mem_valid) |
686 | { | |
687 | type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
688 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
689 | : RELOAD_OTHER); | |
8d618585 | 690 | |
a8c9daeb | 691 | find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), |
55c22565 | 692 | opnum, type, 0, 0); |
a8c9daeb | 693 | } |
0dadecf6 | 694 | |
77545d45 | 695 | secondary_memlocs_elim[(int) mode][opnum] = loc; |
0dadecf6 RK |
696 | return loc; |
697 | } | |
698 | ||
699 | /* Clear any secondary memory locations we've made. */ | |
700 | ||
701 | void | |
702 | clear_secondary_mem () | |
703 | { | |
4c9a05bc | 704 | bzero ((char *) secondary_memlocs, sizeof secondary_memlocs); |
0dadecf6 RK |
705 | } |
706 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
707 | \f | |
c6716840 RK |
708 | /* Find the largest class for which every register number plus N is valid in |
709 | M1 (if in range). Abort if no such class exists. */ | |
710 | ||
711 | static enum reg_class | |
712 | find_valid_class (m1, n) | |
713 | enum machine_mode m1; | |
714 | int n; | |
715 | { | |
716 | int class; | |
717 | int regno; | |
718 | enum reg_class best_class; | |
719 | int best_size = 0; | |
720 | ||
721 | for (class = 1; class < N_REG_CLASSES; class++) | |
722 | { | |
723 | int bad = 0; | |
724 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER && ! bad; regno++) | |
725 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
726 | && TEST_HARD_REG_BIT (reg_class_contents[class], regno + n) | |
727 | && ! HARD_REGNO_MODE_OK (regno + n, m1)) | |
728 | bad = 1; | |
729 | ||
730 | if (! bad && reg_class_size[class] > best_size) | |
731 | best_class = class, best_size = reg_class_size[class]; | |
732 | } | |
733 | ||
734 | if (best_size == 0) | |
735 | abort (); | |
736 | ||
737 | return best_class; | |
738 | } | |
739 | \f | |
a8c9daeb | 740 | /* Record one reload that needs to be performed. |
eab89b90 RK |
741 | IN is an rtx saying where the data are to be found before this instruction. |
742 | OUT says where they must be stored after the instruction. | |
743 | (IN is zero for data not read, and OUT is zero for data not written.) | |
744 | INLOC and OUTLOC point to the places in the instructions where | |
745 | IN and OUT were found. | |
a8c9daeb RK |
746 | If IN and OUT are both non-zero, it means the same register must be used |
747 | to reload both IN and OUT. | |
748 | ||
eab89b90 RK |
749 | CLASS is a register class required for the reloaded data. |
750 | INMODE is the machine mode that the instruction requires | |
751 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
752 | ||
753 | If IN is zero, then OUT's location and mode should be passed as | |
754 | INLOC and INMODE. | |
755 | ||
756 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
757 | ||
758 | OPTIONAL nonzero means this reload does not need to be performed: | |
759 | it can be discarded if that is more convenient. | |
760 | ||
a8c9daeb RK |
761 | OPNUM and TYPE say what the purpose of this reload is. |
762 | ||
eab89b90 RK |
763 | The return value is the reload-number for this reload. |
764 | ||
765 | If both IN and OUT are nonzero, in some rare cases we might | |
766 | want to make two separate reloads. (Actually we never do this now.) | |
767 | Therefore, the reload-number for OUT is stored in | |
768 | output_reloadnum when we return; the return value applies to IN. | |
769 | Usually (presently always), when IN and OUT are nonzero, | |
770 | the two reload-numbers are equal, but the caller should be careful to | |
771 | distinguish them. */ | |
772 | ||
773 | static int | |
774 | push_reload (in, out, inloc, outloc, class, | |
a8c9daeb | 775 | inmode, outmode, strict_low, optional, opnum, type) |
eab89b90 RK |
776 | register rtx in, out; |
777 | rtx *inloc, *outloc; | |
778 | enum reg_class class; | |
779 | enum machine_mode inmode, outmode; | |
780 | int strict_low; | |
781 | int optional; | |
a8c9daeb RK |
782 | int opnum; |
783 | enum reload_type type; | |
eab89b90 RK |
784 | { |
785 | register int i; | |
786 | int dont_share = 0; | |
74347d76 | 787 | int dont_remove_subreg = 0; |
eab89b90 | 788 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; |
9ec7078b | 789 | int secondary_in_reload = -1, secondary_out_reload = -1; |
a229128d RK |
790 | enum insn_code secondary_in_icode = CODE_FOR_nothing; |
791 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
a8c9daeb | 792 | |
eab89b90 RK |
793 | /* INMODE and/or OUTMODE could be VOIDmode if no mode |
794 | has been specified for the operand. In that case, | |
795 | use the operand's mode as the mode to reload. */ | |
796 | if (inmode == VOIDmode && in != 0) | |
797 | inmode = GET_MODE (in); | |
798 | if (outmode == VOIDmode && out != 0) | |
799 | outmode = GET_MODE (out); | |
800 | ||
801 | /* If IN is a pseudo register everywhere-equivalent to a constant, and | |
802 | it is not in a hard register, reload straight from the constant, | |
803 | since we want to get rid of such pseudo registers. | |
804 | Often this is done earlier, but not always in find_reloads_address. */ | |
805 | if (in != 0 && GET_CODE (in) == REG) | |
806 | { | |
807 | register int regno = REGNO (in); | |
808 | ||
809 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
810 | && reg_equiv_constant[regno] != 0) | |
811 | in = reg_equiv_constant[regno]; | |
812 | } | |
813 | ||
814 | /* Likewise for OUT. Of course, OUT will never be equivalent to | |
815 | an actual constant, but it might be equivalent to a memory location | |
816 | (in the case of a parameter). */ | |
817 | if (out != 0 && GET_CODE (out) == REG) | |
818 | { | |
819 | register int regno = REGNO (out); | |
820 | ||
821 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
822 | && reg_equiv_constant[regno] != 0) | |
823 | out = reg_equiv_constant[regno]; | |
824 | } | |
825 | ||
826 | /* If we have a read-write operand with an address side-effect, | |
827 | change either IN or OUT so the side-effect happens only once. */ | |
828 | if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out)) | |
829 | { | |
830 | if (GET_CODE (XEXP (in, 0)) == POST_INC | |
831 | || GET_CODE (XEXP (in, 0)) == POST_DEC) | |
38a448ca | 832 | in = gen_rtx_MEM (GET_MODE (in), XEXP (XEXP (in, 0), 0)); |
eab89b90 RK |
833 | if (GET_CODE (XEXP (in, 0)) == PRE_INC |
834 | || GET_CODE (XEXP (in, 0)) == PRE_DEC) | |
38a448ca | 835 | out = gen_rtx_MEM (GET_MODE (out), XEXP (XEXP (out, 0), 0)); |
eab89b90 RK |
836 | } |
837 | ||
a61c98cf | 838 | /* If we are reloading a (SUBREG constant ...), really reload just the |
ca769828 | 839 | inside expression in its own mode. Similarly for (SUBREG (PLUS ...)). |
a61c98cf RK |
840 | If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still |
841 | a pseudo and hence will become a MEM) with M1 wider than M2 and the | |
842 | register is a pseudo, also reload the inside expression. | |
f72ccbe6 | 843 | For machines that extend byte loads, do this for any SUBREG of a pseudo |
486d8509 RK |
844 | where both M1 and M2 are a word or smaller, M1 is wider than M2, and |
845 | M2 is an integral mode that gets extended when loaded. | |
86c31b2d | 846 | Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
eab89b90 RK |
847 | either M1 is not valid for R or M2 is wider than a word but we only |
848 | need one word to store an M2-sized quantity in R. | |
86c31b2d RS |
849 | (However, if OUT is nonzero, we need to reload the reg *and* |
850 | the subreg, so do nothing here, and let following statement handle it.) | |
851 | ||
eab89b90 RK |
852 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; |
853 | we can't handle it here because CONST_INT does not indicate a mode. | |
854 | ||
855 | Similarly, we must reload the inside expression if we have a | |
df62f951 RK |
856 | STRICT_LOW_PART (presumably, in == out in the cas). |
857 | ||
858 | Also reload the inner expression if it does not require a secondary | |
486d8509 RK |
859 | reload but the SUBREG does. |
860 | ||
861 | Finally, reload the inner expression if it is a register that is in | |
862 | the class whose registers cannot be referenced in a different size | |
d030f4b2 RK |
863 | and M1 is not the same size as M2. If SUBREG_WORD is nonzero, we |
864 | cannot reload just the inside since we might end up with the wrong | |
0f41302f | 865 | register class. */ |
eab89b90 | 866 | |
d030f4b2 | 867 | if (in != 0 && GET_CODE (in) == SUBREG && SUBREG_WORD (in) == 0 |
94bafba7 RK |
868 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
869 | && class != CLASS_CANNOT_CHANGE_SIZE | |
870 | #endif | |
a61c98cf | 871 | && (CONSTANT_P (SUBREG_REG (in)) |
ca769828 | 872 | || GET_CODE (SUBREG_REG (in)) == PLUS |
eab89b90 | 873 | || strict_low |
a61c98cf RK |
874 | || (((GET_CODE (SUBREG_REG (in)) == REG |
875 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER) | |
876 | || GET_CODE (SUBREG_REG (in)) == MEM) | |
03b72c86 RK |
877 | && ((GET_MODE_SIZE (inmode) |
878 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
09bf0250 | 879 | #ifdef LOAD_EXTEND_OP |
03b72c86 RK |
880 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
881 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
882 | <= UNITS_PER_WORD) | |
883 | && (GET_MODE_SIZE (inmode) | |
486d8509 RK |
884 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) |
885 | && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) | |
886 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != NIL) | |
d2c92f5a R |
887 | #endif |
888 | #ifdef WORD_REGISTER_OPERATIONS | |
889 | || ((GET_MODE_SIZE (inmode) | |
890 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
891 | && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == | |
892 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) | |
893 | / UNITS_PER_WORD))) | |
f72ccbe6 | 894 | #endif |
03b72c86 | 895 | )) |
a61c98cf RK |
896 | || (GET_CODE (SUBREG_REG (in)) == REG |
897 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
86c31b2d RS |
898 | /* The case where out is nonzero |
899 | is handled differently in the following statement. */ | |
900 | && (out == 0 || SUBREG_WORD (in) == 0) | |
f72ccbe6 RK |
901 | && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
902 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
903 | > UNITS_PER_WORD) | |
904 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
905 | / UNITS_PER_WORD) | |
906 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
907 | GET_MODE (SUBREG_REG (in))))) | |
908 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (in)) | |
909 | + SUBREG_WORD (in)), | |
910 | inmode))) | |
df62f951 RK |
911 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
912 | || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS | |
913 | && (SECONDARY_INPUT_RELOAD_CLASS (class, | |
914 | GET_MODE (SUBREG_REG (in)), | |
915 | SUBREG_REG (in)) | |
916 | == NO_REGS)) | |
486d8509 RK |
917 | #endif |
918 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
919 | || (GET_CODE (SUBREG_REG (in)) == REG | |
920 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
921 | && (TEST_HARD_REG_BIT | |
922 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
923 | REGNO (SUBREG_REG (in)))) | |
924 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
925 | != GET_MODE_SIZE (inmode))) | |
df62f951 RK |
926 | #endif |
927 | )) | |
eab89b90 RK |
928 | { |
929 | in_subreg_loc = inloc; | |
930 | inloc = &SUBREG_REG (in); | |
931 | in = *inloc; | |
d2c92f5a | 932 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
eab89b90 RK |
933 | if (GET_CODE (in) == MEM) |
934 | /* This is supposed to happen only for paradoxical subregs made by | |
935 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
936 | if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode)) | |
937 | abort (); | |
e05a9da8 | 938 | #endif |
eab89b90 RK |
939 | inmode = GET_MODE (in); |
940 | } | |
941 | ||
86c31b2d RS |
942 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
943 | either M1 is not valid for R or M2 is wider than a word but we only | |
944 | need one word to store an M2-sized quantity in R. | |
945 | ||
946 | However, we must reload the inner reg *as well as* the subreg in | |
947 | that case. */ | |
948 | ||
6fd5ac08 JW |
949 | /* Similar issue for (SUBREG constant ...) if it was not handled by the |
950 | code above. This can happen if SUBREG_WORD != 0. */ | |
951 | ||
86c31b2d | 952 | if (in != 0 && GET_CODE (in) == SUBREG |
6fd5ac08 JW |
953 | && (CONSTANT_P (SUBREG_REG (in)) |
954 | || (GET_CODE (SUBREG_REG (in)) == REG | |
955 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
956 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)) | |
957 | + SUBREG_WORD (in), | |
958 | inmode) | |
959 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD | |
960 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
961 | > UNITS_PER_WORD) | |
962 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
963 | / UNITS_PER_WORD) | |
964 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
965 | GET_MODE (SUBREG_REG (in))))))))) | |
86c31b2d | 966 | { |
c96d01ab RK |
967 | /* This relies on the fact that emit_reload_insns outputs the |
968 | instructions for input reloads of type RELOAD_OTHER in the same | |
969 | order as the reloads. Thus if the outer reload is also of type | |
970 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
971 | output before the outer reload. */ | |
86c31b2d | 972 | push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), NULL_PTR, |
c6716840 RK |
973 | find_valid_class (inmode, SUBREG_WORD (in)), |
974 | VOIDmode, VOIDmode, 0, 0, opnum, type); | |
74347d76 | 975 | dont_remove_subreg = 1; |
86c31b2d RS |
976 | } |
977 | ||
eab89b90 RK |
978 | /* Similarly for paradoxical and problematical SUBREGs on the output. |
979 | Note that there is no reason we need worry about the previous value | |
980 | of SUBREG_REG (out); even if wider than out, | |
981 | storing in a subreg is entitled to clobber it all | |
982 | (except in the case of STRICT_LOW_PART, | |
983 | and in that case the constraint should label it input-output.) */ | |
d030f4b2 | 984 | if (out != 0 && GET_CODE (out) == SUBREG && SUBREG_WORD (out) == 0 |
94bafba7 RK |
985 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
986 | && class != CLASS_CANNOT_CHANGE_SIZE | |
987 | #endif | |
a61c98cf | 988 | && (CONSTANT_P (SUBREG_REG (out)) |
eab89b90 | 989 | || strict_low |
a61c98cf RK |
990 | || (((GET_CODE (SUBREG_REG (out)) == REG |
991 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER) | |
992 | || GET_CODE (SUBREG_REG (out)) == MEM) | |
03b72c86 | 993 | && ((GET_MODE_SIZE (outmode) |
1914f5da RH |
994 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) |
995 | #ifdef WORD_REGISTER_OPERATIONS | |
6d49a073 JW |
996 | || ((GET_MODE_SIZE (outmode) |
997 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
998 | && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == | |
999 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) | |
1000 | / UNITS_PER_WORD))) | |
1914f5da RH |
1001 | #endif |
1002 | )) | |
eab89b90 RK |
1003 | || (GET_CODE (SUBREG_REG (out)) == REG |
1004 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
1005 | && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1006 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1007 | > UNITS_PER_WORD) | |
1008 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1009 | / UNITS_PER_WORD) | |
1010 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
1011 | GET_MODE (SUBREG_REG (out))))) | |
1012 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (out)) | |
1013 | + SUBREG_WORD (out)), | |
1014 | outmode))) | |
df62f951 RK |
1015 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
1016 | || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS | |
1017 | && (SECONDARY_OUTPUT_RELOAD_CLASS (class, | |
1018 | GET_MODE (SUBREG_REG (out)), | |
1019 | SUBREG_REG (out)) | |
1020 | == NO_REGS)) | |
486d8509 RK |
1021 | #endif |
1022 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
1023 | || (GET_CODE (SUBREG_REG (out)) == REG | |
1024 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
1025 | && (TEST_HARD_REG_BIT | |
1026 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
1027 | REGNO (SUBREG_REG (out)))) | |
1028 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1029 | != GET_MODE_SIZE (outmode))) | |
df62f951 RK |
1030 | #endif |
1031 | )) | |
eab89b90 RK |
1032 | { |
1033 | out_subreg_loc = outloc; | |
1034 | outloc = &SUBREG_REG (out); | |
e05a9da8 | 1035 | out = *outloc; |
d2c92f5a | 1036 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
e05a9da8 | 1037 | if (GET_CODE (out) == MEM |
eab89b90 RK |
1038 | && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode)) |
1039 | abort (); | |
e05a9da8 | 1040 | #endif |
eab89b90 RK |
1041 | outmode = GET_MODE (out); |
1042 | } | |
1043 | ||
74347d76 RK |
1044 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
1045 | either M1 is not valid for R or M2 is wider than a word but we only | |
1046 | need one word to store an M2-sized quantity in R. | |
1047 | ||
1048 | However, we must reload the inner reg *as well as* the subreg in | |
1049 | that case. In this case, the inner reg is an in-out reload. */ | |
1050 | ||
1051 | if (out != 0 && GET_CODE (out) == SUBREG | |
1052 | && GET_CODE (SUBREG_REG (out)) == REG | |
1053 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
c6716840 RK |
1054 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)) + SUBREG_WORD (out), |
1055 | outmode) | |
74347d76 RK |
1056 | || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1057 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1058 | > UNITS_PER_WORD) | |
1059 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1060 | / UNITS_PER_WORD) | |
1061 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
1062 | GET_MODE (SUBREG_REG (out))))))) | |
1063 | { | |
c96d01ab RK |
1064 | /* This relies on the fact that emit_reload_insns outputs the |
1065 | instructions for output reloads of type RELOAD_OTHER in reverse | |
1066 | order of the reloads. Thus if the outer reload is also of type | |
1067 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1068 | output after the outer reload. */ | |
74347d76 RK |
1069 | dont_remove_subreg = 1; |
1070 | push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out), | |
c6716840 RK |
1071 | &SUBREG_REG (out), |
1072 | find_valid_class (outmode, SUBREG_WORD (out)), | |
1073 | VOIDmode, VOIDmode, 0, 0, | |
74347d76 RK |
1074 | opnum, RELOAD_OTHER); |
1075 | } | |
1076 | ||
eab89b90 RK |
1077 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ |
1078 | if (in != 0 && out != 0 && GET_CODE (out) == MEM | |
1079 | && (GET_CODE (in) == REG || GET_CODE (in) == MEM) | |
bfa30b22 | 1080 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
eab89b90 RK |
1081 | dont_share = 1; |
1082 | ||
0dadecf6 RK |
1083 | /* If IN is a SUBREG of a hard register, make a new REG. This |
1084 | simplifies some of the cases below. */ | |
1085 | ||
1086 | if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG | |
74347d76 RK |
1087 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
1088 | && ! dont_remove_subreg) | |
38a448ca RH |
1089 | in = gen_rtx_REG (GET_MODE (in), |
1090 | REGNO (SUBREG_REG (in)) + SUBREG_WORD (in)); | |
0dadecf6 RK |
1091 | |
1092 | /* Similarly for OUT. */ | |
1093 | if (out != 0 && GET_CODE (out) == SUBREG | |
1094 | && GET_CODE (SUBREG_REG (out)) == REG | |
74347d76 RK |
1095 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
1096 | && ! dont_remove_subreg) | |
38a448ca RH |
1097 | out = gen_rtx_REG (GET_MODE (out), |
1098 | REGNO (SUBREG_REG (out)) + SUBREG_WORD (out)); | |
0dadecf6 | 1099 | |
eab89b90 RK |
1100 | /* Narrow down the class of register wanted if that is |
1101 | desirable on this machine for efficiency. */ | |
1102 | if (in != 0) | |
1103 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1104 | ||
ac2a9454 | 1105 | /* Output reloads may need analogous treatment, different in detail. */ |
18a53b78 RS |
1106 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS |
1107 | if (out != 0) | |
1108 | class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class); | |
1109 | #endif | |
1110 | ||
eab89b90 RK |
1111 | /* Make sure we use a class that can handle the actual pseudo |
1112 | inside any subreg. For example, on the 386, QImode regs | |
1113 | can appear within SImode subregs. Although GENERAL_REGS | |
1114 | can handle SImode, QImode needs a smaller class. */ | |
1115 | #ifdef LIMIT_RELOAD_CLASS | |
1116 | if (in_subreg_loc) | |
1117 | class = LIMIT_RELOAD_CLASS (inmode, class); | |
1118 | else if (in != 0 && GET_CODE (in) == SUBREG) | |
1119 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); | |
1120 | ||
1121 | if (out_subreg_loc) | |
1122 | class = LIMIT_RELOAD_CLASS (outmode, class); | |
1123 | if (out != 0 && GET_CODE (out) == SUBREG) | |
1124 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); | |
1125 | #endif | |
1126 | ||
eab89b90 RK |
1127 | /* Verify that this class is at least possible for the mode that |
1128 | is specified. */ | |
1129 | if (this_insn_is_asm) | |
1130 | { | |
1131 | enum machine_mode mode; | |
1132 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
1133 | mode = inmode; | |
1134 | else | |
1135 | mode = outmode; | |
5488078f RS |
1136 | if (mode == VOIDmode) |
1137 | { | |
1138 | error_for_asm (this_insn, "cannot reload integer constant operand in `asm'"); | |
1139 | mode = word_mode; | |
1140 | if (in != 0) | |
1141 | inmode = word_mode; | |
1142 | if (out != 0) | |
1143 | outmode = word_mode; | |
1144 | } | |
eab89b90 RK |
1145 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1146 | if (HARD_REGNO_MODE_OK (i, mode) | |
1147 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)) | |
1148 | { | |
1149 | int nregs = HARD_REGNO_NREGS (i, mode); | |
1150 | ||
1151 | int j; | |
1152 | for (j = 1; j < nregs; j++) | |
1153 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j)) | |
1154 | break; | |
1155 | if (j == nregs) | |
1156 | break; | |
1157 | } | |
1158 | if (i == FIRST_PSEUDO_REGISTER) | |
1159 | { | |
1160 | error_for_asm (this_insn, "impossible register constraint in `asm'"); | |
1161 | class = ALL_REGS; | |
1162 | } | |
1163 | } | |
1164 | ||
5488078f RS |
1165 | if (class == NO_REGS) |
1166 | abort (); | |
1167 | ||
eab89b90 RK |
1168 | /* We can use an existing reload if the class is right |
1169 | and at least one of IN and OUT is a match | |
1170 | and the other is at worst neutral. | |
a8c9daeb RK |
1171 | (A zero compared against anything is neutral.) |
1172 | ||
1173 | If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are | |
1174 | for the same thing since that can cause us to need more reload registers | |
1175 | than we otherwise would. */ | |
1176 | ||
eab89b90 RK |
1177 | for (i = 0; i < n_reloads; i++) |
1178 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
1179 | || reg_class_subset_p (reload_reg_class[i], class)) | |
eab89b90 RK |
1180 | /* If the existing reload has a register, it must fit our class. */ |
1181 | && (reload_reg_rtx[i] == 0 | |
1182 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1183 | true_regnum (reload_reg_rtx[i]))) | |
1184 | && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share | |
1185 | && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out))) | |
1186 | || | |
1187 | (out != 0 && MATCHES (reload_out[i], out) | |
a8c9daeb | 1188 | && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))) |
e9a25f70 | 1189 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1190 | && MERGABLE_RELOADS (type, reload_when_needed[i], |
1191 | opnum, reload_opnum[i])) | |
eab89b90 RK |
1192 | break; |
1193 | ||
1194 | /* Reloading a plain reg for input can match a reload to postincrement | |
1195 | that reg, since the postincrement's value is the right value. | |
1196 | Likewise, it can match a preincrement reload, since we regard | |
1197 | the preincrementation as happening before any ref in this insn | |
1198 | to that register. */ | |
1199 | if (i == n_reloads) | |
1200 | for (i = 0; i < n_reloads; i++) | |
1201 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
1202 | || reg_class_subset_p (reload_reg_class[i], class)) | |
1203 | /* If the existing reload has a register, it must fit our class. */ | |
1204 | && (reload_reg_rtx[i] == 0 | |
1205 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1206 | true_regnum (reload_reg_rtx[i]))) | |
eab89b90 RK |
1207 | && out == 0 && reload_out[i] == 0 && reload_in[i] != 0 |
1208 | && ((GET_CODE (in) == REG | |
1209 | && (GET_CODE (reload_in[i]) == POST_INC | |
1210 | || GET_CODE (reload_in[i]) == POST_DEC | |
1211 | || GET_CODE (reload_in[i]) == PRE_INC | |
1212 | || GET_CODE (reload_in[i]) == PRE_DEC) | |
1213 | && MATCHES (XEXP (reload_in[i], 0), in)) | |
1214 | || | |
1215 | (GET_CODE (reload_in[i]) == REG | |
1216 | && (GET_CODE (in) == POST_INC | |
1217 | || GET_CODE (in) == POST_DEC | |
1218 | || GET_CODE (in) == PRE_INC | |
1219 | || GET_CODE (in) == PRE_DEC) | |
a8c9daeb | 1220 | && MATCHES (XEXP (in, 0), reload_in[i]))) |
e9a25f70 | 1221 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1222 | && MERGABLE_RELOADS (type, reload_when_needed[i], |
1223 | opnum, reload_opnum[i])) | |
eab89b90 RK |
1224 | { |
1225 | /* Make sure reload_in ultimately has the increment, | |
1226 | not the plain register. */ | |
1227 | if (GET_CODE (in) == REG) | |
1228 | in = reload_in[i]; | |
1229 | break; | |
1230 | } | |
1231 | ||
1232 | if (i == n_reloads) | |
1233 | { | |
9ec7078b RK |
1234 | /* See if we need a secondary reload register to move between CLASS |
1235 | and IN or CLASS and OUT. Get the icode and push any required reloads | |
1236 | needed for each of them if so. */ | |
eab89b90 RK |
1237 | |
1238 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1239 | if (in != 0) | |
9ec7078b RK |
1240 | secondary_in_reload |
1241 | = push_secondary_reload (1, in, opnum, optional, class, inmode, type, | |
1242 | &secondary_in_icode); | |
eab89b90 RK |
1243 | #endif |
1244 | ||
1245 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
1246 | if (out != 0 && GET_CODE (out) != SCRATCH) | |
9ec7078b RK |
1247 | secondary_out_reload |
1248 | = push_secondary_reload (0, out, opnum, optional, class, outmode, | |
1249 | type, &secondary_out_icode); | |
eab89b90 RK |
1250 | #endif |
1251 | ||
1252 | /* We found no existing reload suitable for re-use. | |
1253 | So add an additional reload. */ | |
1254 | ||
e9a25f70 JL |
1255 | #ifdef SECONDARY_MEMORY_NEEDED |
1256 | /* If a memory location is needed for the copy, make one. */ | |
1257 | if (in != 0 && GET_CODE (in) == REG | |
1258 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1259 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), | |
1260 | class, inmode)) | |
1261 | get_secondary_mem (in, inmode, opnum, type); | |
1262 | #endif | |
1263 | ||
9ec7078b | 1264 | i = n_reloads; |
eab89b90 RK |
1265 | reload_in[i] = in; |
1266 | reload_out[i] = out; | |
1267 | reload_reg_class[i] = class; | |
1268 | reload_inmode[i] = inmode; | |
1269 | reload_outmode[i] = outmode; | |
1270 | reload_reg_rtx[i] = 0; | |
1271 | reload_optional[i] = optional; | |
1272 | reload_inc[i] = 0; | |
eab89b90 RK |
1273 | reload_nocombine[i] = 0; |
1274 | reload_in_reg[i] = inloc ? *inloc : 0; | |
a8c9daeb RK |
1275 | reload_opnum[i] = opnum; |
1276 | reload_when_needed[i] = type; | |
9ec7078b RK |
1277 | reload_secondary_in_reload[i] = secondary_in_reload; |
1278 | reload_secondary_out_reload[i] = secondary_out_reload; | |
1279 | reload_secondary_in_icode[i] = secondary_in_icode; | |
1280 | reload_secondary_out_icode[i] = secondary_out_icode; | |
eab89b90 RK |
1281 | reload_secondary_p[i] = 0; |
1282 | ||
1283 | n_reloads++; | |
0dadecf6 RK |
1284 | |
1285 | #ifdef SECONDARY_MEMORY_NEEDED | |
0dadecf6 RK |
1286 | if (out != 0 && GET_CODE (out) == REG |
1287 | && REGNO (out) < FIRST_PSEUDO_REGISTER | |
1288 | && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)), | |
1289 | outmode)) | |
a8c9daeb | 1290 | get_secondary_mem (out, outmode, opnum, type); |
0dadecf6 | 1291 | #endif |
eab89b90 RK |
1292 | } |
1293 | else | |
1294 | { | |
1295 | /* We are reusing an existing reload, | |
1296 | but we may have additional information for it. | |
1297 | For example, we may now have both IN and OUT | |
1298 | while the old one may have just one of them. */ | |
1299 | ||
6fd5ac08 JW |
1300 | /* The modes can be different. If they are, we want to reload in |
1301 | the larger mode, so that the value is valid for both modes. */ | |
1302 | if (inmode != VOIDmode | |
1303 | && GET_MODE_SIZE (inmode) > GET_MODE_SIZE (reload_inmode[i])) | |
eab89b90 | 1304 | reload_inmode[i] = inmode; |
6fd5ac08 JW |
1305 | if (outmode != VOIDmode |
1306 | && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (reload_outmode[i])) | |
eab89b90 RK |
1307 | reload_outmode[i] = outmode; |
1308 | if (in != 0) | |
1309 | reload_in[i] = in; | |
1310 | if (out != 0) | |
1311 | reload_out[i] = out; | |
1312 | if (reg_class_subset_p (class, reload_reg_class[i])) | |
1313 | reload_reg_class[i] = class; | |
1314 | reload_optional[i] &= optional; | |
a8c9daeb RK |
1315 | if (MERGE_TO_OTHER (type, reload_when_needed[i], |
1316 | opnum, reload_opnum[i])) | |
1317 | reload_when_needed[i] = RELOAD_OTHER; | |
1318 | reload_opnum[i] = MIN (reload_opnum[i], opnum); | |
eab89b90 RK |
1319 | } |
1320 | ||
1321 | /* If the ostensible rtx being reload differs from the rtx found | |
1322 | in the location to substitute, this reload is not safe to combine | |
1323 | because we cannot reliably tell whether it appears in the insn. */ | |
1324 | ||
1325 | if (in != 0 && in != *inloc) | |
1326 | reload_nocombine[i] = 1; | |
1327 | ||
1328 | #if 0 | |
1329 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1330 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1331 | ||
1332 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1333 | it must be for an autoincrement. It doesn't work to store | |
1334 | the incremented value after the insn because that would clobber the CC. | |
1335 | So we must do the increment of the value reloaded from, | |
1336 | increment it, store it back, then decrement again. */ | |
1337 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1338 | { | |
1339 | out = 0; | |
1340 | reload_out[i] = 0; | |
1341 | reload_inc[i] = find_inc_amount (PATTERN (this_insn), in); | |
1342 | /* If we did not find a nonzero amount-to-increment-by, | |
1343 | that contradicts the belief that IN is being incremented | |
1344 | in an address in this insn. */ | |
1345 | if (reload_inc[i] == 0) | |
1346 | abort (); | |
1347 | } | |
1348 | #endif | |
1349 | ||
1350 | /* If we will replace IN and OUT with the reload-reg, | |
1351 | record where they are located so that substitution need | |
1352 | not do a tree walk. */ | |
1353 | ||
1354 | if (replace_reloads) | |
1355 | { | |
1356 | if (inloc != 0) | |
1357 | { | |
1358 | register struct replacement *r = &replacements[n_replacements++]; | |
1359 | r->what = i; | |
1360 | r->subreg_loc = in_subreg_loc; | |
1361 | r->where = inloc; | |
1362 | r->mode = inmode; | |
1363 | } | |
1364 | if (outloc != 0 && outloc != inloc) | |
1365 | { | |
1366 | register struct replacement *r = &replacements[n_replacements++]; | |
1367 | r->what = i; | |
1368 | r->where = outloc; | |
1369 | r->subreg_loc = out_subreg_loc; | |
1370 | r->mode = outmode; | |
1371 | } | |
1372 | } | |
1373 | ||
1374 | /* If this reload is just being introduced and it has both | |
1375 | an incoming quantity and an outgoing quantity that are | |
1376 | supposed to be made to match, see if either one of the two | |
1377 | can serve as the place to reload into. | |
1378 | ||
1379 | If one of them is acceptable, set reload_reg_rtx[i] | |
1380 | to that one. */ | |
1381 | ||
1382 | if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0) | |
1383 | { | |
1384 | reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc, | |
36b50568 | 1385 | inmode, outmode, |
189086f9 | 1386 | reload_reg_class[i], i, |
31c21e0c | 1387 | earlyclobber_operand_p (out)); |
eab89b90 RK |
1388 | |
1389 | /* If the outgoing register already contains the same value | |
1390 | as the incoming one, we can dispense with loading it. | |
1391 | The easiest way to tell the caller that is to give a phony | |
1392 | value for the incoming operand (same as outgoing one). */ | |
1393 | if (reload_reg_rtx[i] == out | |
1394 | && (GET_CODE (in) == REG || CONSTANT_P (in)) | |
1395 | && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), | |
1396 | static_reload_reg_p, i, inmode)) | |
1397 | reload_in[i] = out; | |
1398 | } | |
1399 | ||
1400 | /* If this is an input reload and the operand contains a register that | |
1401 | dies in this insn and is used nowhere else, see if it is the right class | |
1402 | to be used for this reload. Use it if so. (This occurs most commonly | |
1403 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1404 | this if it is also an output reload that mentions the register unless | |
1405 | the output is a SUBREG that clobbers an entire register. | |
1406 | ||
1407 | Note that the operand might be one of the spill regs, if it is a | |
1408 | pseudo reg and we are in a block where spilling has not taken place. | |
1409 | But if there is no spilling in this block, that is OK. | |
1410 | An explicitly used hard reg cannot be a spill reg. */ | |
1411 | ||
1412 | if (reload_reg_rtx[i] == 0 && in != 0) | |
1413 | { | |
1414 | rtx note; | |
1415 | int regno; | |
1416 | ||
1417 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1418 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1419 | && GET_CODE (XEXP (note, 0)) == REG | |
1420 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER | |
1421 | && reg_mentioned_p (XEXP (note, 0), in) | |
1422 | && ! refers_to_regno_for_reload_p (regno, | |
1423 | (regno | |
1424 | + HARD_REGNO_NREGS (regno, | |
1425 | inmode)), | |
1426 | PATTERN (this_insn), inloc) | |
05b4ec4f RS |
1427 | /* If this is also an output reload, IN cannot be used as |
1428 | the reload register if it is set in this insn unless IN | |
1429 | is also OUT. */ | |
1430 | && (out == 0 || in == out | |
1431 | || ! hard_reg_set_here_p (regno, | |
1432 | (regno | |
1433 | + HARD_REGNO_NREGS (regno, | |
1434 | inmode)), | |
1435 | PATTERN (this_insn))) | |
1436 | /* ??? Why is this code so different from the previous? | |
1437 | Is there any simple coherent way to describe the two together? | |
1438 | What's going on here. */ | |
eab89b90 RK |
1439 | && (in != out |
1440 | || (GET_CODE (in) == SUBREG | |
1441 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1442 | / UNITS_PER_WORD) | |
1443 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1444 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1445 | /* Make sure the operand fits in the reg that dies. */ | |
1446 | && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1447 | && HARD_REGNO_MODE_OK (regno, inmode) | |
1448 | && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1449 | && HARD_REGNO_MODE_OK (regno, outmode) | |
1450 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
1451 | && !fixed_regs[regno]) | |
1452 | { | |
38a448ca | 1453 | reload_reg_rtx[i] = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
1454 | break; |
1455 | } | |
1456 | } | |
1457 | ||
1458 | if (out) | |
1459 | output_reloadnum = i; | |
1460 | ||
1461 | return i; | |
1462 | } | |
1463 | ||
1464 | /* Record an additional place we must replace a value | |
1465 | for which we have already recorded a reload. | |
1466 | RELOADNUM is the value returned by push_reload | |
1467 | when the reload was recorded. | |
1468 | This is used in insn patterns that use match_dup. */ | |
1469 | ||
1470 | static void | |
1471 | push_replacement (loc, reloadnum, mode) | |
1472 | rtx *loc; | |
1473 | int reloadnum; | |
1474 | enum machine_mode mode; | |
1475 | { | |
1476 | if (replace_reloads) | |
1477 | { | |
1478 | register struct replacement *r = &replacements[n_replacements++]; | |
1479 | r->what = reloadnum; | |
1480 | r->where = loc; | |
1481 | r->subreg_loc = 0; | |
1482 | r->mode = mode; | |
1483 | } | |
1484 | } | |
1485 | \f | |
a8c9daeb RK |
1486 | /* Transfer all replacements that used to be in reload FROM to be in |
1487 | reload TO. */ | |
1488 | ||
1489 | void | |
1490 | transfer_replacements (to, from) | |
1491 | int to, from; | |
1492 | { | |
1493 | int i; | |
1494 | ||
1495 | for (i = 0; i < n_replacements; i++) | |
1496 | if (replacements[i].what == from) | |
1497 | replacements[i].what = to; | |
1498 | } | |
1499 | \f | |
eab89b90 RK |
1500 | /* If there is only one output reload, and it is not for an earlyclobber |
1501 | operand, try to combine it with a (logically unrelated) input reload | |
1502 | to reduce the number of reload registers needed. | |
1503 | ||
1504 | This is safe if the input reload does not appear in | |
1505 | the value being output-reloaded, because this implies | |
1506 | it is not needed any more once the original insn completes. | |
1507 | ||
1508 | If that doesn't work, see we can use any of the registers that | |
1509 | die in this insn as a reload register. We can if it is of the right | |
1510 | class and does not appear in the value being output-reloaded. */ | |
1511 | ||
1512 | static void | |
1513 | combine_reloads () | |
1514 | { | |
1515 | int i; | |
1516 | int output_reload = -1; | |
8922eb5b | 1517 | int secondary_out = -1; |
eab89b90 RK |
1518 | rtx note; |
1519 | ||
1520 | /* Find the output reload; return unless there is exactly one | |
1521 | and that one is mandatory. */ | |
1522 | ||
1523 | for (i = 0; i < n_reloads; i++) | |
1524 | if (reload_out[i] != 0) | |
1525 | { | |
1526 | if (output_reload >= 0) | |
1527 | return; | |
1528 | output_reload = i; | |
1529 | } | |
1530 | ||
1531 | if (output_reload < 0 || reload_optional[output_reload]) | |
1532 | return; | |
1533 | ||
1534 | /* An input-output reload isn't combinable. */ | |
1535 | ||
1536 | if (reload_in[output_reload] != 0) | |
1537 | return; | |
1538 | ||
6dc42e49 | 1539 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
4644aad4 RK |
1540 | if (earlyclobber_operand_p (reload_out[output_reload])) |
1541 | return; | |
eab89b90 RK |
1542 | |
1543 | /* Check each input reload; can we combine it? */ | |
1544 | ||
1545 | for (i = 0; i < n_reloads; i++) | |
1546 | if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i] | |
1547 | /* Life span of this reload must not extend past main insn. */ | |
a8c9daeb | 1548 | && reload_when_needed[i] != RELOAD_FOR_OUTPUT_ADDRESS |
47c8cf91 | 1549 | && reload_when_needed[i] != RELOAD_FOR_OUTADDR_ADDRESS |
a8c9daeb RK |
1550 | && reload_when_needed[i] != RELOAD_OTHER |
1551 | && (CLASS_MAX_NREGS (reload_reg_class[i], reload_inmode[i]) | |
1552 | == CLASS_MAX_NREGS (reload_reg_class[output_reload], | |
1553 | reload_outmode[output_reload])) | |
eab89b90 RK |
1554 | && reload_inc[i] == 0 |
1555 | && reload_reg_rtx[i] == 0 | |
a8c9daeb | 1556 | #ifdef SECONDARY_MEMORY_NEEDED |
9ec7078b RK |
1557 | /* Don't combine two reloads with different secondary |
1558 | memory locations. */ | |
77545d45 RK |
1559 | && (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] == 0 |
1560 | || secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] == 0 | |
1561 | || rtx_equal_p (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]], | |
1562 | secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]])) | |
a8c9daeb | 1563 | #endif |
e9a25f70 JL |
1564 | && (SMALL_REGISTER_CLASSES |
1565 | ? (reload_reg_class[i] == reload_reg_class[output_reload]) | |
1566 | : (reg_class_subset_p (reload_reg_class[i], | |
1567 | reload_reg_class[output_reload]) | |
1568 | || reg_class_subset_p (reload_reg_class[output_reload], | |
1569 | reload_reg_class[i]))) | |
eab89b90 RK |
1570 | && (MATCHES (reload_in[i], reload_out[output_reload]) |
1571 | /* Args reversed because the first arg seems to be | |
1572 | the one that we imagine being modified | |
1573 | while the second is the one that might be affected. */ | |
bfa30b22 RK |
1574 | || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload], |
1575 | reload_in[i]) | |
eab89b90 RK |
1576 | /* However, if the input is a register that appears inside |
1577 | the output, then we also can't share. | |
1578 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1579 | If the same reload reg is used for both reg 69 and the | |
1580 | result to be stored in memory, then that result | |
1581 | will clobber the address of the memory ref. */ | |
1582 | && ! (GET_CODE (reload_in[i]) == REG | |
bfa30b22 | 1583 | && reg_overlap_mentioned_for_reload_p (reload_in[i], |
a8c9daeb RK |
1584 | reload_out[output_reload])))) |
1585 | && (reg_class_size[(int) reload_reg_class[i]] | |
e9a25f70 | 1586 | || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1587 | /* We will allow making things slightly worse by combining an |
1588 | input and an output, but no worse than that. */ | |
1589 | && (reload_when_needed[i] == RELOAD_FOR_INPUT | |
1590 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT)) | |
eab89b90 RK |
1591 | { |
1592 | int j; | |
1593 | ||
1594 | /* We have found a reload to combine with! */ | |
1595 | reload_out[i] = reload_out[output_reload]; | |
1596 | reload_outmode[i] = reload_outmode[output_reload]; | |
1597 | /* Mark the old output reload as inoperative. */ | |
1598 | reload_out[output_reload] = 0; | |
1599 | /* The combined reload is needed for the entire insn. */ | |
eab89b90 | 1600 | reload_when_needed[i] = RELOAD_OTHER; |
0f41302f | 1601 | /* If the output reload had a secondary reload, copy it. */ |
9ec7078b RK |
1602 | if (reload_secondary_out_reload[output_reload] != -1) |
1603 | { | |
1604 | reload_secondary_out_reload[i] | |
1605 | = reload_secondary_out_reload[output_reload]; | |
1606 | reload_secondary_out_icode[i] | |
1607 | = reload_secondary_out_icode[output_reload]; | |
1608 | } | |
1609 | ||
a8c9daeb RK |
1610 | #ifdef SECONDARY_MEMORY_NEEDED |
1611 | /* Copy any secondary MEM. */ | |
77545d45 RK |
1612 | if (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] != 0) |
1613 | secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] | |
1614 | = secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]]; | |
a8c9daeb | 1615 | #endif |
0f41302f | 1616 | /* If required, minimize the register class. */ |
eab89b90 RK |
1617 | if (reg_class_subset_p (reload_reg_class[output_reload], |
1618 | reload_reg_class[i])) | |
1619 | reload_reg_class[i] = reload_reg_class[output_reload]; | |
1620 | ||
1621 | /* Transfer all replacements from the old reload to the combined. */ | |
1622 | for (j = 0; j < n_replacements; j++) | |
1623 | if (replacements[j].what == output_reload) | |
1624 | replacements[j].what = i; | |
1625 | ||
1626 | return; | |
1627 | } | |
1628 | ||
1629 | /* If this insn has only one operand that is modified or written (assumed | |
1630 | to be the first), it must be the one corresponding to this reload. It | |
1631 | is safe to use anything that dies in this insn for that output provided | |
1632 | that it does not occur in the output (we already know it isn't an | |
1633 | earlyclobber. If this is an asm insn, give up. */ | |
1634 | ||
1635 | if (INSN_CODE (this_insn) == -1) | |
1636 | return; | |
1637 | ||
1638 | for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++) | |
1639 | if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '=' | |
1640 | || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+') | |
1641 | return; | |
1642 | ||
1643 | /* See if some hard register that dies in this insn and is not used in | |
1644 | the output is the right class. Only works if the register we pick | |
1645 | up can fully hold our output reload. */ | |
1646 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1647 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1648 | && GET_CODE (XEXP (note, 0)) == REG | |
bfa30b22 RK |
1649 | && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
1650 | reload_out[output_reload]) | |
eab89b90 RK |
1651 | && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
1652 | && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1653 | && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]], | |
1654 | REGNO (XEXP (note, 0))) | |
1655 | && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1656 | <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0)))) | |
8922eb5b RK |
1657 | /* Ensure that a secondary or tertiary reload for this output |
1658 | won't want this register. */ | |
1659 | && ((secondary_out = reload_secondary_out_reload[output_reload]) == -1 | |
1660 | || (! (TEST_HARD_REG_BIT | |
1661 | (reg_class_contents[(int) reload_reg_class[secondary_out]], | |
1662 | REGNO (XEXP (note, 0)))) | |
1663 | && ((secondary_out = reload_secondary_out_reload[secondary_out]) == -1 | |
1664 | || ! (TEST_HARD_REG_BIT | |
1665 | (reg_class_contents[(int) reload_reg_class[secondary_out]], | |
1666 | REGNO (XEXP (note, 0))))))) | |
eab89b90 RK |
1667 | && ! fixed_regs[REGNO (XEXP (note, 0))]) |
1668 | { | |
38a448ca RH |
1669 | reload_reg_rtx[output_reload] |
1670 | = gen_rtx_REG (reload_outmode[output_reload], | |
1671 | REGNO (XEXP (note, 0))); | |
eab89b90 RK |
1672 | return; |
1673 | } | |
1674 | } | |
1675 | \f | |
1676 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1677 | See if one of IN and OUT is a register that may be used; | |
1678 | this is desirable since a spill-register won't be needed. | |
1679 | If so, return the register rtx that proves acceptable. | |
1680 | ||
1681 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
1682 | CLASS is the register class required for the reload. | |
1683 | ||
1684 | If FOR_REAL is >= 0, it is the number of the reload, | |
1685 | and in some cases when it can be discovered that OUT doesn't need | |
1686 | to be computed, clear out reload_out[FOR_REAL]. | |
1687 | ||
1688 | If FOR_REAL is -1, this should not be done, because this call | |
189086f9 RK |
1689 | is just to see if a register can be found, not to find and install it. |
1690 | ||
1691 | EARLYCLOBBER is non-zero if OUT is an earlyclobber operand. This | |
1692 | puts an additional constraint on being able to use IN for OUT since | |
1693 | IN must not appear elsewhere in the insn (it is assumed that IN itself | |
1694 | is safe from the earlyclobber). */ | |
eab89b90 RK |
1695 | |
1696 | static rtx | |
36b50568 | 1697 | find_dummy_reload (real_in, real_out, inloc, outloc, |
189086f9 | 1698 | inmode, outmode, class, for_real, earlyclobber) |
eab89b90 RK |
1699 | rtx real_in, real_out; |
1700 | rtx *inloc, *outloc; | |
36b50568 | 1701 | enum machine_mode inmode, outmode; |
eab89b90 RK |
1702 | enum reg_class class; |
1703 | int for_real; | |
189086f9 | 1704 | int earlyclobber; |
eab89b90 RK |
1705 | { |
1706 | rtx in = real_in; | |
1707 | rtx out = real_out; | |
1708 | int in_offset = 0; | |
1709 | int out_offset = 0; | |
1710 | rtx value = 0; | |
1711 | ||
1712 | /* If operands exceed a word, we can't use either of them | |
1713 | unless they have the same size. */ | |
36b50568 RS |
1714 | if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode) |
1715 | && (GET_MODE_SIZE (outmode) > UNITS_PER_WORD | |
1716 | || GET_MODE_SIZE (inmode) > UNITS_PER_WORD)) | |
eab89b90 RK |
1717 | return 0; |
1718 | ||
1719 | /* Find the inside of any subregs. */ | |
1720 | while (GET_CODE (out) == SUBREG) | |
1721 | { | |
1722 | out_offset = SUBREG_WORD (out); | |
1723 | out = SUBREG_REG (out); | |
1724 | } | |
1725 | while (GET_CODE (in) == SUBREG) | |
1726 | { | |
1727 | in_offset = SUBREG_WORD (in); | |
1728 | in = SUBREG_REG (in); | |
1729 | } | |
1730 | ||
1731 | /* Narrow down the reg class, the same way push_reload will; | |
1732 | otherwise we might find a dummy now, but push_reload won't. */ | |
1733 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1734 | ||
1735 | /* See if OUT will do. */ | |
1736 | if (GET_CODE (out) == REG | |
1737 | && REGNO (out) < FIRST_PSEUDO_REGISTER) | |
1738 | { | |
1739 | register int regno = REGNO (out) + out_offset; | |
36b50568 | 1740 | int nwords = HARD_REGNO_NREGS (regno, outmode); |
d3b9996a | 1741 | rtx saved_rtx; |
eab89b90 RK |
1742 | |
1743 | /* When we consider whether the insn uses OUT, | |
1744 | ignore references within IN. They don't prevent us | |
1745 | from copying IN into OUT, because those refs would | |
1746 | move into the insn that reloads IN. | |
1747 | ||
1748 | However, we only ignore IN in its role as this reload. | |
1749 | If the insn uses IN elsewhere and it contains OUT, | |
1750 | that counts. We can't be sure it's the "same" operand | |
1751 | so it might not go through this reload. */ | |
d3b9996a | 1752 | saved_rtx = *inloc; |
eab89b90 RK |
1753 | *inloc = const0_rtx; |
1754 | ||
1755 | if (regno < FIRST_PSEUDO_REGISTER | |
1756 | /* A fixed reg that can overlap other regs better not be used | |
1757 | for reloading in any way. */ | |
1758 | #ifdef OVERLAPPING_REGNO_P | |
1759 | && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno)) | |
1760 | #endif | |
1761 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1762 | PATTERN (this_insn), outloc)) | |
1763 | { | |
1764 | int i; | |
1765 | for (i = 0; i < nwords; i++) | |
1766 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1767 | regno + i)) | |
1768 | break; | |
1769 | ||
1770 | if (i == nwords) | |
1771 | { | |
1772 | if (GET_CODE (real_out) == REG) | |
1773 | value = real_out; | |
1774 | else | |
38a448ca | 1775 | value = gen_rtx_REG (outmode, regno); |
eab89b90 RK |
1776 | } |
1777 | } | |
1778 | ||
d3b9996a | 1779 | *inloc = saved_rtx; |
eab89b90 RK |
1780 | } |
1781 | ||
1782 | /* Consider using IN if OUT was not acceptable | |
1783 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
1784 | We can't use IN unless it is dies in this insn, | |
1785 | which means we must know accurately which hard regs are live. | |
189086f9 RK |
1786 | Also, the result can't go in IN if IN is used within OUT, |
1787 | or if OUT is an earlyclobber and IN appears elsewhere in the insn. */ | |
eab89b90 RK |
1788 | if (hard_regs_live_known |
1789 | && GET_CODE (in) == REG | |
1790 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1791 | && (value == 0 | |
1792 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
1793 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
1794 | && !fixed_regs[REGNO (in)] | |
36b50568 RS |
1795 | && HARD_REGNO_MODE_OK (REGNO (in), |
1796 | /* The only case where out and real_out might | |
1797 | have different modes is where real_out | |
1798 | is a subreg, and in that case, out | |
1799 | has a real mode. */ | |
1800 | (GET_MODE (out) != VOIDmode | |
1801 | ? GET_MODE (out) : outmode))) | |
eab89b90 RK |
1802 | { |
1803 | register int regno = REGNO (in) + in_offset; | |
36b50568 | 1804 | int nwords = HARD_REGNO_NREGS (regno, inmode); |
eab89b90 | 1805 | |
fb3821f7 | 1806 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR) |
eab89b90 | 1807 | && ! hard_reg_set_here_p (regno, regno + nwords, |
189086f9 RK |
1808 | PATTERN (this_insn)) |
1809 | && (! earlyclobber | |
1810 | || ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1811 | PATTERN (this_insn), inloc))) | |
eab89b90 RK |
1812 | { |
1813 | int i; | |
1814 | for (i = 0; i < nwords; i++) | |
1815 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1816 | regno + i)) | |
1817 | break; | |
1818 | ||
1819 | if (i == nwords) | |
1820 | { | |
1821 | /* If we were going to use OUT as the reload reg | |
1822 | and changed our mind, it means OUT is a dummy that | |
1823 | dies here. So don't bother copying value to it. */ | |
1824 | if (for_real >= 0 && value == real_out) | |
1825 | reload_out[for_real] = 0; | |
1826 | if (GET_CODE (real_in) == REG) | |
1827 | value = real_in; | |
1828 | else | |
38a448ca | 1829 | value = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
1830 | } |
1831 | } | |
1832 | } | |
1833 | ||
1834 | return value; | |
1835 | } | |
1836 | \f | |
1837 | /* This page contains subroutines used mainly for determining | |
1838 | whether the IN or an OUT of a reload can serve as the | |
1839 | reload register. */ | |
1840 | ||
4644aad4 RK |
1841 | /* Return 1 if X is an operand of an insn that is being earlyclobbered. */ |
1842 | ||
1843 | static int | |
1844 | earlyclobber_operand_p (x) | |
1845 | rtx x; | |
1846 | { | |
1847 | int i; | |
1848 | ||
1849 | for (i = 0; i < n_earlyclobbers; i++) | |
1850 | if (reload_earlyclobbers[i] == x) | |
1851 | return 1; | |
1852 | ||
1853 | return 0; | |
1854 | } | |
1855 | ||
eab89b90 RK |
1856 | /* Return 1 if expression X alters a hard reg in the range |
1857 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
1858 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
1859 | X should be the body of an instruction. */ | |
1860 | ||
1861 | static int | |
1862 | hard_reg_set_here_p (beg_regno, end_regno, x) | |
1863 | register int beg_regno, end_regno; | |
1864 | rtx x; | |
1865 | { | |
1866 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
1867 | { | |
1868 | register rtx op0 = SET_DEST (x); | |
1869 | while (GET_CODE (op0) == SUBREG) | |
1870 | op0 = SUBREG_REG (op0); | |
1871 | if (GET_CODE (op0) == REG) | |
1872 | { | |
1873 | register int r = REGNO (op0); | |
1874 | /* See if this reg overlaps range under consideration. */ | |
1875 | if (r < end_regno | |
1876 | && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno) | |
1877 | return 1; | |
1878 | } | |
1879 | } | |
1880 | else if (GET_CODE (x) == PARALLEL) | |
1881 | { | |
1882 | register int i = XVECLEN (x, 0) - 1; | |
1883 | for (; i >= 0; i--) | |
1884 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
1885 | return 1; | |
1886 | } | |
1887 | ||
1888 | return 0; | |
1889 | } | |
1890 | ||
1891 | /* Return 1 if ADDR is a valid memory address for mode MODE, | |
1892 | and check that each pseudo reg has the proper kind of | |
1893 | hard reg. */ | |
1894 | ||
1895 | int | |
1896 | strict_memory_address_p (mode, addr) | |
1897 | enum machine_mode mode; | |
1898 | register rtx addr; | |
1899 | { | |
1900 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
1901 | return 0; | |
1902 | ||
1903 | win: | |
1904 | return 1; | |
1905 | } | |
eab89b90 RK |
1906 | \f |
1907 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
1908 | if they are the same hard reg, and has special hacks for | |
1909 | autoincrement and autodecrement. | |
1910 | This is specifically intended for find_reloads to use | |
1911 | in determining whether two operands match. | |
1912 | X is the operand whose number is the lower of the two. | |
1913 | ||
1914 | The value is 2 if Y contains a pre-increment that matches | |
1915 | a non-incrementing address in X. */ | |
1916 | ||
1917 | /* ??? To be completely correct, we should arrange to pass | |
1918 | for X the output operand and for Y the input operand. | |
1919 | For now, we assume that the output operand has the lower number | |
1920 | because that is natural in (SET output (... input ...)). */ | |
1921 | ||
1922 | int | |
1923 | operands_match_p (x, y) | |
1924 | register rtx x, y; | |
1925 | { | |
1926 | register int i; | |
1927 | register RTX_CODE code = GET_CODE (x); | |
1928 | register char *fmt; | |
1929 | int success_2; | |
1930 | ||
1931 | if (x == y) | |
1932 | return 1; | |
1933 | if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) | |
1934 | && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG | |
1935 | && GET_CODE (SUBREG_REG (y)) == REG))) | |
1936 | { | |
1937 | register int j; | |
1938 | ||
1939 | if (code == SUBREG) | |
1940 | { | |
1941 | i = REGNO (SUBREG_REG (x)); | |
1942 | if (i >= FIRST_PSEUDO_REGISTER) | |
1943 | goto slow; | |
1944 | i += SUBREG_WORD (x); | |
1945 | } | |
1946 | else | |
1947 | i = REGNO (x); | |
1948 | ||
1949 | if (GET_CODE (y) == SUBREG) | |
1950 | { | |
1951 | j = REGNO (SUBREG_REG (y)); | |
1952 | if (j >= FIRST_PSEUDO_REGISTER) | |
1953 | goto slow; | |
1954 | j += SUBREG_WORD (y); | |
1955 | } | |
1956 | else | |
1957 | j = REGNO (y); | |
1958 | ||
dca52d80 JW |
1959 | /* On a WORDS_BIG_ENDIAN machine, point to the last register of a |
1960 | multiple hard register group, so that for example (reg:DI 0) and | |
1961 | (reg:SI 1) will be considered the same register. */ | |
1962 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD | |
1963 | && i < FIRST_PSEUDO_REGISTER) | |
1964 | i += (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD) - 1; | |
1965 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD | |
1966 | && j < FIRST_PSEUDO_REGISTER) | |
1967 | j += (GET_MODE_SIZE (GET_MODE (y)) / UNITS_PER_WORD) - 1; | |
1968 | ||
eab89b90 RK |
1969 | return i == j; |
1970 | } | |
1971 | /* If two operands must match, because they are really a single | |
1972 | operand of an assembler insn, then two postincrements are invalid | |
1973 | because the assembler insn would increment only once. | |
1974 | On the other hand, an postincrement matches ordinary indexing | |
1975 | if the postincrement is the output operand. */ | |
1976 | if (code == POST_DEC || code == POST_INC) | |
1977 | return operands_match_p (XEXP (x, 0), y); | |
1978 | /* Two preincrements are invalid | |
1979 | because the assembler insn would increment only once. | |
1980 | On the other hand, an preincrement matches ordinary indexing | |
1981 | if the preincrement is the input operand. | |
1982 | In this case, return 2, since some callers need to do special | |
1983 | things when this happens. */ | |
1984 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC) | |
1985 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; | |
1986 | ||
1987 | slow: | |
1988 | ||
1989 | /* Now we have disposed of all the cases | |
1990 | in which different rtx codes can match. */ | |
1991 | if (code != GET_CODE (y)) | |
1992 | return 0; | |
1993 | if (code == LABEL_REF) | |
1994 | return XEXP (x, 0) == XEXP (y, 0); | |
1995 | if (code == SYMBOL_REF) | |
1996 | return XSTR (x, 0) == XSTR (y, 0); | |
1997 | ||
1998 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
1999 | ||
2000 | if (GET_MODE (x) != GET_MODE (y)) | |
2001 | return 0; | |
2002 | ||
2003 | /* Compare the elements. If any pair of corresponding elements | |
2004 | fail to match, return 0 for the whole things. */ | |
2005 | ||
2006 | success_2 = 0; | |
2007 | fmt = GET_RTX_FORMAT (code); | |
2008 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2009 | { | |
2010 | int val; | |
2011 | switch (fmt[i]) | |
2012 | { | |
fb3821f7 CH |
2013 | case 'w': |
2014 | if (XWINT (x, i) != XWINT (y, i)) | |
2015 | return 0; | |
2016 | break; | |
2017 | ||
eab89b90 RK |
2018 | case 'i': |
2019 | if (XINT (x, i) != XINT (y, i)) | |
2020 | return 0; | |
2021 | break; | |
2022 | ||
2023 | case 'e': | |
2024 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
2025 | if (val == 0) | |
2026 | return 0; | |
2027 | /* If any subexpression returns 2, | |
2028 | we should return 2 if we are successful. */ | |
2029 | if (val == 2) | |
2030 | success_2 = 1; | |
2031 | break; | |
2032 | ||
2033 | case '0': | |
2034 | break; | |
2035 | ||
2036 | /* It is believed that rtx's at this level will never | |
2037 | contain anything but integers and other rtx's, | |
2038 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
2039 | default: | |
2040 | abort (); | |
2041 | } | |
2042 | } | |
2043 | return 1 + success_2; | |
2044 | } | |
2045 | \f | |
2046 | /* Return the number of times character C occurs in string S. */ | |
2047 | ||
e4600702 | 2048 | int |
eab89b90 | 2049 | n_occurrences (c, s) |
d149d5f5 | 2050 | int c; |
eab89b90 RK |
2051 | char *s; |
2052 | { | |
2053 | int n = 0; | |
2054 | while (*s) | |
2055 | n += (*s++ == c); | |
2056 | return n; | |
2057 | } | |
2058 | \f | |
eab89b90 RK |
2059 | /* Describe the range of registers or memory referenced by X. |
2060 | If X is a register, set REG_FLAG and put the first register | |
2061 | number into START and the last plus one into END. | |
2062 | If X is a memory reference, put a base address into BASE | |
2063 | and a range of integer offsets into START and END. | |
2064 | If X is pushing on the stack, we can assume it causes no trouble, | |
2065 | so we set the SAFE field. */ | |
2066 | ||
2067 | static struct decomposition | |
2068 | decompose (x) | |
2069 | rtx x; | |
2070 | { | |
2071 | struct decomposition val; | |
2072 | int all_const = 0; | |
2073 | ||
2074 | val.reg_flag = 0; | |
2075 | val.safe = 0; | |
43984e29 | 2076 | val.base = 0; |
eab89b90 RK |
2077 | if (GET_CODE (x) == MEM) |
2078 | { | |
2079 | rtx base, offset = 0; | |
2080 | rtx addr = XEXP (x, 0); | |
2081 | ||
2082 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC | |
2083 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
2084 | { | |
2085 | val.base = XEXP (addr, 0); | |
2086 | val.start = - GET_MODE_SIZE (GET_MODE (x)); | |
2087 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
2088 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2089 | return val; | |
2090 | } | |
2091 | ||
2092 | if (GET_CODE (addr) == CONST) | |
2093 | { | |
2094 | addr = XEXP (addr, 0); | |
2095 | all_const = 1; | |
2096 | } | |
2097 | if (GET_CODE (addr) == PLUS) | |
2098 | { | |
2099 | if (CONSTANT_P (XEXP (addr, 0))) | |
2100 | { | |
2101 | base = XEXP (addr, 1); | |
2102 | offset = XEXP (addr, 0); | |
2103 | } | |
2104 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2105 | { | |
2106 | base = XEXP (addr, 0); | |
2107 | offset = XEXP (addr, 1); | |
2108 | } | |
2109 | } | |
2110 | ||
2111 | if (offset == 0) | |
2112 | { | |
2113 | base = addr; | |
2114 | offset = const0_rtx; | |
2115 | } | |
2116 | if (GET_CODE (offset) == CONST) | |
2117 | offset = XEXP (offset, 0); | |
2118 | if (GET_CODE (offset) == PLUS) | |
2119 | { | |
2120 | if (GET_CODE (XEXP (offset, 0)) == CONST_INT) | |
2121 | { | |
38a448ca | 2122 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1)); |
eab89b90 RK |
2123 | offset = XEXP (offset, 0); |
2124 | } | |
2125 | else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) | |
2126 | { | |
38a448ca | 2127 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0)); |
eab89b90 RK |
2128 | offset = XEXP (offset, 1); |
2129 | } | |
2130 | else | |
2131 | { | |
38a448ca | 2132 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); |
eab89b90 RK |
2133 | offset = const0_rtx; |
2134 | } | |
2135 | } | |
2136 | else if (GET_CODE (offset) != CONST_INT) | |
2137 | { | |
38a448ca | 2138 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); |
eab89b90 RK |
2139 | offset = const0_rtx; |
2140 | } | |
2141 | ||
2142 | if (all_const && GET_CODE (base) == PLUS) | |
38a448ca | 2143 | base = gen_rtx_CONST (GET_MODE (base), base); |
eab89b90 RK |
2144 | |
2145 | if (GET_CODE (offset) != CONST_INT) | |
2146 | abort (); | |
2147 | ||
2148 | val.start = INTVAL (offset); | |
2149 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
2150 | val.base = base; | |
2151 | return val; | |
2152 | } | |
2153 | else if (GET_CODE (x) == REG) | |
2154 | { | |
2155 | val.reg_flag = 1; | |
2156 | val.start = true_regnum (x); | |
2157 | if (val.start < 0) | |
2158 | { | |
2159 | /* A pseudo with no hard reg. */ | |
2160 | val.start = REGNO (x); | |
2161 | val.end = val.start + 1; | |
2162 | } | |
2163 | else | |
2164 | /* A hard reg. */ | |
2165 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2166 | } | |
2167 | else if (GET_CODE (x) == SUBREG) | |
2168 | { | |
2169 | if (GET_CODE (SUBREG_REG (x)) != REG) | |
2170 | /* This could be more precise, but it's good enough. */ | |
2171 | return decompose (SUBREG_REG (x)); | |
2172 | val.reg_flag = 1; | |
2173 | val.start = true_regnum (x); | |
2174 | if (val.start < 0) | |
2175 | return decompose (SUBREG_REG (x)); | |
2176 | else | |
2177 | /* A hard reg. */ | |
2178 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2179 | } | |
2180 | else if (CONSTANT_P (x) | |
2181 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
2182 | || GET_CODE (x) == SCRATCH) | |
2183 | val.safe = 1; | |
2184 | else | |
2185 | abort (); | |
2186 | return val; | |
2187 | } | |
2188 | ||
2189 | /* Return 1 if altering Y will not modify the value of X. | |
2190 | Y is also described by YDATA, which should be decompose (Y). */ | |
2191 | ||
2192 | static int | |
2193 | immune_p (x, y, ydata) | |
2194 | rtx x, y; | |
2195 | struct decomposition ydata; | |
2196 | { | |
2197 | struct decomposition xdata; | |
2198 | ||
2199 | if (ydata.reg_flag) | |
fb3821f7 | 2200 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR); |
eab89b90 RK |
2201 | if (ydata.safe) |
2202 | return 1; | |
2203 | ||
2204 | if (GET_CODE (y) != MEM) | |
2205 | abort (); | |
2206 | /* If Y is memory and X is not, Y can't affect X. */ | |
2207 | if (GET_CODE (x) != MEM) | |
2208 | return 1; | |
2209 | ||
2210 | xdata = decompose (x); | |
2211 | ||
2212 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
2213 | { | |
2214 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
2215 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
2216 | return 1; | |
2217 | /* Constants and stack slots never overlap. */ | |
2218 | if (CONSTANT_P (xdata.base) | |
2219 | && (ydata.base == frame_pointer_rtx | |
a36d4c62 | 2220 | || ydata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2221 | || ydata.base == stack_pointer_rtx)) |
2222 | return 1; | |
2223 | if (CONSTANT_P (ydata.base) | |
2224 | && (xdata.base == frame_pointer_rtx | |
a36d4c62 | 2225 | || xdata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2226 | || xdata.base == stack_pointer_rtx)) |
2227 | return 1; | |
2228 | /* If either base is variable, we don't know anything. */ | |
2229 | return 0; | |
2230 | } | |
2231 | ||
2232 | ||
2233 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); | |
2234 | } | |
44ace968 | 2235 | |
f72aed24 | 2236 | /* Similar, but calls decompose. */ |
44ace968 JW |
2237 | |
2238 | int | |
2239 | safe_from_earlyclobber (op, clobber) | |
2240 | rtx op, clobber; | |
2241 | { | |
2242 | struct decomposition early_data; | |
2243 | ||
2244 | early_data = decompose (clobber); | |
2245 | return immune_p (op, clobber, early_data); | |
2246 | } | |
eab89b90 RK |
2247 | \f |
2248 | /* Main entry point of this file: search the body of INSN | |
2249 | for values that need reloading and record them with push_reload. | |
2250 | REPLACE nonzero means record also where the values occur | |
2251 | so that subst_reloads can be used. | |
2252 | ||
2253 | IND_LEVELS says how many levels of indirection are supported by this | |
2254 | machine; a value of zero means that a memory reference is not a valid | |
2255 | memory address. | |
2256 | ||
2257 | LIVE_KNOWN says we have valid information about which hard | |
2258 | regs are live at each point in the program; this is true when | |
2259 | we are called from global_alloc but false when stupid register | |
2260 | allocation has been done. | |
2261 | ||
2262 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
2263 | which is nonnegative if the reg has been commandeered for reloading into. | |
2264 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
2265 | by various subroutines. */ | |
2266 | ||
2267 | void | |
2268 | find_reloads (insn, replace, ind_levels, live_known, reload_reg_p) | |
2269 | rtx insn; | |
2270 | int replace, ind_levels; | |
2271 | int live_known; | |
2272 | short *reload_reg_p; | |
2273 | { | |
eab89b90 RK |
2274 | #ifdef REGISTER_CONSTRAINTS |
2275 | ||
eab89b90 | 2276 | register int insn_code_number; |
a8c9daeb | 2277 | register int i, j; |
eab89b90 RK |
2278 | int noperands; |
2279 | /* These are the constraints for the insn. We don't change them. */ | |
2280 | char *constraints1[MAX_RECOG_OPERANDS]; | |
2281 | /* These start out as the constraints for the insn | |
2282 | and they are chewed up as we consider alternatives. */ | |
2283 | char *constraints[MAX_RECOG_OPERANDS]; | |
2284 | /* These are the preferred classes for an operand, or NO_REGS if it isn't | |
2285 | a register. */ | |
2286 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
2287 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
2288 | /* Nonzero for a MEM operand whose entire address needs a reload. */ | |
2289 | int address_reloaded[MAX_RECOG_OPERANDS]; | |
a8c9daeb RK |
2290 | /* Value of enum reload_type to use for operand. */ |
2291 | enum reload_type operand_type[MAX_RECOG_OPERANDS]; | |
2292 | /* Value of enum reload_type to use within address of operand. */ | |
2293 | enum reload_type address_type[MAX_RECOG_OPERANDS]; | |
2294 | /* Save the usage of each operand. */ | |
2295 | enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; | |
eab89b90 RK |
2296 | int no_input_reloads = 0, no_output_reloads = 0; |
2297 | int n_alternatives; | |
2298 | int this_alternative[MAX_RECOG_OPERANDS]; | |
2299 | char this_alternative_win[MAX_RECOG_OPERANDS]; | |
2300 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2301 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2302 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
2303 | int swapped; | |
2304 | int goal_alternative[MAX_RECOG_OPERANDS]; | |
2305 | int this_alternative_number; | |
2306 | int goal_alternative_number; | |
2307 | int operand_reloadnum[MAX_RECOG_OPERANDS]; | |
2308 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
2309 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
2310 | char goal_alternative_win[MAX_RECOG_OPERANDS]; | |
2311 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2312 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2313 | int goal_alternative_swapped; | |
eab89b90 RK |
2314 | int best; |
2315 | int commutative; | |
2316 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
2317 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2318 | rtx body = PATTERN (insn); | |
2319 | rtx set = single_set (insn); | |
2320 | int goal_earlyclobber, this_earlyclobber; | |
2321 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | |
2322 | ||
2323 | this_insn = insn; | |
2324 | this_insn_is_asm = 0; /* Tentative. */ | |
2325 | n_reloads = 0; | |
2326 | n_replacements = 0; | |
2327 | n_memlocs = 0; | |
2328 | n_earlyclobbers = 0; | |
2329 | replace_reloads = replace; | |
2330 | hard_regs_live_known = live_known; | |
2331 | static_reload_reg_p = reload_reg_p; | |
2332 | ||
2333 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
2334 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
2335 | to have any input reloads. */ | |
2336 | if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) | |
2337 | no_output_reloads = 1; | |
2338 | ||
2339 | #ifdef HAVE_cc0 | |
2340 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
2341 | no_input_reloads = 1; | |
2342 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
2343 | no_output_reloads = 1; | |
2344 | #endif | |
2345 | ||
0dadecf6 RK |
2346 | #ifdef SECONDARY_MEMORY_NEEDED |
2347 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
2348 | clear them out here. */ | |
2349 | ||
4c9a05bc | 2350 | bzero ((char *) secondary_memlocs_elim, sizeof secondary_memlocs_elim); |
0dadecf6 RK |
2351 | #endif |
2352 | ||
eab89b90 RK |
2353 | /* Find what kind of insn this is. NOPERANDS gets number of operands. |
2354 | Make OPERANDS point to a vector of operand values. | |
2355 | Make OPERAND_LOCS point to a vector of pointers to | |
2356 | where the operands were found. | |
2357 | Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the | |
2358 | constraint-strings for this insn. | |
2359 | Return if the insn needs no reload processing. */ | |
2360 | ||
2361 | switch (GET_CODE (body)) | |
2362 | { | |
2363 | case USE: | |
2364 | case CLOBBER: | |
2365 | case ASM_INPUT: | |
2366 | case ADDR_VEC: | |
2367 | case ADDR_DIFF_VEC: | |
2368 | return; | |
2369 | ||
2370 | case SET: | |
2371 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it | |
2372 | is cheap to move between them. If it is not, there may not be an insn | |
2373 | to do the copy, so we may need a reload. */ | |
2374 | if (GET_CODE (SET_DEST (body)) == REG | |
2375 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER | |
2376 | && GET_CODE (SET_SRC (body)) == REG | |
2377 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER | |
2378 | && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))), | |
2379 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) | |
2380 | return; | |
2381 | case PARALLEL: | |
2382 | case ASM_OPERANDS: | |
a8c9daeb | 2383 | reload_n_operands = noperands = asm_noperands (body); |
eab89b90 RK |
2384 | if (noperands >= 0) |
2385 | { | |
2386 | /* This insn is an `asm' with operands. */ | |
2387 | ||
2388 | insn_code_number = -1; | |
2389 | this_insn_is_asm = 1; | |
2390 | ||
2391 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
2392 | if (noperands > MAX_RECOG_OPERANDS) | |
2393 | abort (); | |
2394 | ||
2395 | /* Now get the operand values and constraints out of the insn. */ | |
2396 | ||
2397 | decode_asm_operands (body, recog_operand, recog_operand_loc, | |
2398 | constraints, operand_mode); | |
2399 | if (noperands > 0) | |
2400 | { | |
4c9a05bc RK |
2401 | bcopy ((char *) constraints, (char *) constraints1, |
2402 | noperands * sizeof (char *)); | |
eab89b90 RK |
2403 | n_alternatives = n_occurrences (',', constraints[0]) + 1; |
2404 | for (i = 1; i < noperands; i++) | |
d45cf215 | 2405 | if (n_alternatives != n_occurrences (',', constraints[i]) + 1) |
eab89b90 RK |
2406 | { |
2407 | error_for_asm (insn, "operand constraints differ in number of alternatives"); | |
2408 | /* Avoid further trouble with this insn. */ | |
38a448ca | 2409 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 RK |
2410 | n_reloads = 0; |
2411 | return; | |
2412 | } | |
2413 | } | |
2414 | break; | |
2415 | } | |
2416 | ||
2417 | default: | |
2418 | /* Ordinary insn: recognize it, get the operands via insn_extract | |
2419 | and get the constraints. */ | |
2420 | ||
2421 | insn_code_number = recog_memoized (insn); | |
2422 | if (insn_code_number < 0) | |
2423 | fatal_insn_not_found (insn); | |
2424 | ||
a8c9daeb | 2425 | reload_n_operands = noperands = insn_n_operands[insn_code_number]; |
eab89b90 RK |
2426 | n_alternatives = insn_n_alternatives[insn_code_number]; |
2427 | /* Just return "no reloads" if insn has no operands with constraints. */ | |
2428 | if (n_alternatives == 0) | |
2429 | return; | |
2430 | insn_extract (insn); | |
2431 | for (i = 0; i < noperands; i++) | |
2432 | { | |
2433 | constraints[i] = constraints1[i] | |
2434 | = insn_operand_constraint[insn_code_number][i]; | |
2435 | operand_mode[i] = insn_operand_mode[insn_code_number][i]; | |
2436 | } | |
2437 | } | |
2438 | ||
2439 | if (noperands == 0) | |
2440 | return; | |
2441 | ||
2442 | commutative = -1; | |
2443 | ||
2444 | /* If we will need to know, later, whether some pair of operands | |
2445 | are the same, we must compare them now and save the result. | |
2446 | Reloading the base and index registers will clobber them | |
2447 | and afterward they will fail to match. */ | |
2448 | ||
2449 | for (i = 0; i < noperands; i++) | |
2450 | { | |
2451 | register char *p; | |
2452 | register int c; | |
2453 | ||
2454 | substed_operand[i] = recog_operand[i]; | |
2455 | p = constraints[i]; | |
2456 | ||
a8c9daeb RK |
2457 | modified[i] = RELOAD_READ; |
2458 | ||
2459 | /* Scan this operand's constraint to see if it is an output operand, | |
2460 | an in-out operand, is commutative, or should match another. */ | |
eab89b90 | 2461 | |
51723711 | 2462 | while ((c = *p++)) |
a8c9daeb RK |
2463 | { |
2464 | if (c == '=') | |
2465 | modified[i] = RELOAD_WRITE; | |
2466 | else if (c == '+') | |
2467 | modified[i] = RELOAD_READ_WRITE; | |
2468 | else if (c == '%') | |
2469 | { | |
2470 | /* The last operand should not be marked commutative. */ | |
2471 | if (i == noperands - 1) | |
2472 | { | |
2473 | if (this_insn_is_asm) | |
2474 | warning_for_asm (this_insn, | |
2475 | "`%%' constraint used with last operand"); | |
2476 | else | |
2477 | abort (); | |
2478 | } | |
2479 | else | |
2480 | commutative = i; | |
2481 | } | |
2482 | else if (c >= '0' && c <= '9') | |
2483 | { | |
2484 | c -= '0'; | |
2485 | operands_match[c][i] | |
2486 | = operands_match_p (recog_operand[c], recog_operand[i]); | |
ea9c5b9e | 2487 | |
a8c9daeb RK |
2488 | /* An operand may not match itself. */ |
2489 | if (c == i) | |
2490 | { | |
2491 | if (this_insn_is_asm) | |
2492 | warning_for_asm (this_insn, | |
2493 | "operand %d has constraint %d", i, c); | |
2494 | else | |
2495 | abort (); | |
2496 | } | |
ea9c5b9e | 2497 | |
a8c9daeb RK |
2498 | /* If C can be commuted with C+1, and C might need to match I, |
2499 | then C+1 might also need to match I. */ | |
2500 | if (commutative >= 0) | |
2501 | { | |
2502 | if (c == commutative || c == commutative + 1) | |
2503 | { | |
2504 | int other = c + (c == commutative ? 1 : -1); | |
2505 | operands_match[other][i] | |
2506 | = operands_match_p (recog_operand[other], recog_operand[i]); | |
2507 | } | |
2508 | if (i == commutative || i == commutative + 1) | |
2509 | { | |
2510 | int other = i + (i == commutative ? 1 : -1); | |
2511 | operands_match[c][other] | |
2512 | = operands_match_p (recog_operand[c], recog_operand[other]); | |
2513 | } | |
2514 | /* Note that C is supposed to be less than I. | |
2515 | No need to consider altering both C and I because in | |
2516 | that case we would alter one into the other. */ | |
2517 | } | |
2518 | } | |
2519 | } | |
eab89b90 RK |
2520 | } |
2521 | ||
2522 | /* Examine each operand that is a memory reference or memory address | |
2523 | and reload parts of the addresses into index registers. | |
eab89b90 RK |
2524 | Also here any references to pseudo regs that didn't get hard regs |
2525 | but are equivalent to constants get replaced in the insn itself | |
2526 | with those constants. Nobody will ever see them again. | |
2527 | ||
2528 | Finally, set up the preferred classes of each operand. */ | |
2529 | ||
2530 | for (i = 0; i < noperands; i++) | |
2531 | { | |
2532 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
a8c9daeb | 2533 | |
eab89b90 | 2534 | address_reloaded[i] = 0; |
a8c9daeb RK |
2535 | operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT |
2536 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT | |
2537 | : RELOAD_OTHER); | |
2538 | address_type[i] | |
2539 | = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS | |
2540 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS | |
2541 | : RELOAD_OTHER); | |
eab89b90 | 2542 | |
0d38001f RS |
2543 | if (*constraints[i] == 0) |
2544 | /* Ignore things like match_operator operands. */ | |
2545 | ; | |
2546 | else if (constraints[i][0] == 'p') | |
eab89b90 | 2547 | { |
fb3821f7 | 2548 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 | 2549 | recog_operand[i], recog_operand_loc[i], |
55c22565 | 2550 | i, operand_type[i], ind_levels, insn); |
b685dbae RK |
2551 | |
2552 | /* If we now have a simple operand where we used to have a | |
2553 | PLUS or MULT, re-recognize and try again. */ | |
2554 | if ((GET_RTX_CLASS (GET_CODE (*recog_operand_loc[i])) == 'o' | |
2555 | || GET_CODE (*recog_operand_loc[i]) == SUBREG) | |
2556 | && (GET_CODE (recog_operand[i]) == MULT | |
2557 | || GET_CODE (recog_operand[i]) == PLUS)) | |
2558 | { | |
2559 | INSN_CODE (insn) = -1; | |
2560 | find_reloads (insn, replace, ind_levels, live_known, | |
2561 | reload_reg_p); | |
2562 | return; | |
2563 | } | |
2564 | ||
eab89b90 RK |
2565 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; |
2566 | } | |
2567 | else if (code == MEM) | |
2568 | { | |
2569 | if (find_reloads_address (GET_MODE (recog_operand[i]), | |
2570 | recog_operand_loc[i], | |
2571 | XEXP (recog_operand[i], 0), | |
2572 | &XEXP (recog_operand[i], 0), | |
55c22565 | 2573 | i, address_type[i], ind_levels, insn)) |
eab89b90 RK |
2574 | address_reloaded[i] = 1; |
2575 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; | |
2576 | } | |
2577 | else if (code == SUBREG) | |
2578 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] | |
a8c9daeb RK |
2579 | = find_reloads_toplev (recog_operand[i], i, address_type[i], |
2580 | ind_levels, | |
eab89b90 RK |
2581 | set != 0 |
2582 | && &SET_DEST (set) == recog_operand_loc[i]); | |
ff428c90 ILT |
2583 | else if (code == PLUS || GET_RTX_CLASS (code) == '1') |
2584 | /* We can get a PLUS as an "operand" as a result of register | |
2585 | elimination. See eliminate_regs and gen_reload. We handle | |
2586 | a unary operator by reloading the operand. */ | |
944d7b14 RS |
2587 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] |
2588 | = find_reloads_toplev (recog_operand[i], i, address_type[i], | |
2589 | ind_levels, 0); | |
eab89b90 RK |
2590 | else if (code == REG) |
2591 | { | |
2592 | /* This is equivalent to calling find_reloads_toplev. | |
2593 | The code is duplicated for speed. | |
2594 | When we find a pseudo always equivalent to a constant, | |
2595 | we replace it by the constant. We must be sure, however, | |
2596 | that we don't try to replace it in the insn in which it | |
2597 | is being set. */ | |
2598 | register int regno = REGNO (recog_operand[i]); | |
2599 | if (reg_equiv_constant[regno] != 0 | |
2600 | && (set == 0 || &SET_DEST (set) != recog_operand_loc[i])) | |
2601 | substed_operand[i] = recog_operand[i] | |
2602 | = reg_equiv_constant[regno]; | |
2603 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
2604 | that feeds this insn. */ | |
2605 | if (reg_equiv_mem[regno] != 0) | |
2606 | substed_operand[i] = recog_operand[i] | |
2607 | = reg_equiv_mem[regno]; | |
2608 | #endif | |
2609 | if (reg_equiv_address[regno] != 0) | |
2610 | { | |
2611 | /* If reg_equiv_address is not a constant address, copy it, | |
2612 | since it may be shared. */ | |
4ffeab02 JW |
2613 | /* We must rerun eliminate_regs, in case the elimination |
2614 | offsets have changed. */ | |
2615 | rtx address = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], | |
1914f5da | 2616 | 0, NULL_RTX), |
4ffeab02 | 2617 | 0); |
eab89b90 RK |
2618 | |
2619 | if (rtx_varies_p (address)) | |
2620 | address = copy_rtx (address); | |
2621 | ||
2622 | /* If this is an output operand, we must output a CLOBBER | |
a8c9daeb RK |
2623 | after INSN so find_equiv_reg knows REGNO is being written. |
2624 | Mark this insn specially, do we can put our output reloads | |
2625 | after it. */ | |
2626 | ||
2627 | if (modified[i] != RELOAD_READ) | |
38a448ca RH |
2628 | PUT_MODE (emit_insn_after (gen_rtx_CLOBBER (VOIDmode, |
2629 | recog_operand[i]), | |
a8c9daeb RK |
2630 | insn), |
2631 | DImode); | |
eab89b90 RK |
2632 | |
2633 | *recog_operand_loc[i] = recog_operand[i] | |
38a448ca | 2634 | = gen_rtx_MEM (GET_MODE (recog_operand[i]), address); |
eab89b90 RK |
2635 | RTX_UNCHANGING_P (recog_operand[i]) |
2636 | = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
2637 | find_reloads_address (GET_MODE (recog_operand[i]), | |
130659a4 | 2638 | recog_operand_loc[i], |
eab89b90 RK |
2639 | XEXP (recog_operand[i], 0), |
2640 | &XEXP (recog_operand[i], 0), | |
55c22565 | 2641 | i, address_type[i], ind_levels, insn); |
eab89b90 RK |
2642 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; |
2643 | } | |
2644 | } | |
aaf9712e RS |
2645 | /* If the operand is still a register (we didn't replace it with an |
2646 | equivalent), get the preferred class to reload it into. */ | |
2647 | code = GET_CODE (recog_operand[i]); | |
2648 | preferred_class[i] | |
91f9a6ed | 2649 | = ((code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) |
aaf9712e RS |
2650 | ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS); |
2651 | pref_or_nothing[i] | |
91f9a6ed | 2652 | = (code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER |
e4600702 | 2653 | && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS); |
eab89b90 RK |
2654 | } |
2655 | ||
2656 | /* If this is simply a copy from operand 1 to operand 0, merge the | |
2657 | preferred classes for the operands. */ | |
2658 | if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set) | |
2659 | && recog_operand[1] == SET_SRC (set)) | |
2660 | { | |
2661 | preferred_class[0] = preferred_class[1] | |
2662 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2663 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2664 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2665 | } | |
2666 | ||
2667 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2668 | or got the wrong kind of hard reg. For this, we must consider | |
2669 | all the operands together against the register constraints. */ | |
2670 | ||
2671 | best = MAX_RECOG_OPERANDS + 300; | |
2672 | ||
2673 | swapped = 0; | |
2674 | goal_alternative_swapped = 0; | |
2675 | try_swapped: | |
2676 | ||
2677 | /* The constraints are made of several alternatives. | |
2678 | Each operand's constraint looks like foo,bar,... with commas | |
2679 | separating the alternatives. The first alternatives for all | |
2680 | operands go together, the second alternatives go together, etc. | |
2681 | ||
2682 | First loop over alternatives. */ | |
2683 | ||
2684 | for (this_alternative_number = 0; | |
2685 | this_alternative_number < n_alternatives; | |
2686 | this_alternative_number++) | |
2687 | { | |
2688 | /* Loop over operands for one constraint alternative. */ | |
2689 | /* LOSERS counts those that don't fit this alternative | |
2690 | and would require loading. */ | |
2691 | int losers = 0; | |
2692 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2693 | even after reloading. */ | |
2694 | int bad = 0; | |
2695 | /* REJECT is a count of how undesirable this alternative says it is | |
2696 | if any reloading is required. If the alternative matches exactly | |
2697 | then REJECT is ignored, but otherwise it gets this much | |
2698 | counted against it in addition to the reloading needed. Each | |
2699 | ? counts three times here since we want the disparaging caused by | |
2700 | a bad register class to only count 1/3 as much. */ | |
2701 | int reject = 0; | |
2702 | ||
2703 | this_earlyclobber = 0; | |
2704 | ||
2705 | for (i = 0; i < noperands; i++) | |
2706 | { | |
2707 | register char *p = constraints[i]; | |
2708 | register int win = 0; | |
2709 | /* 0 => this operand can be reloaded somehow for this alternative */ | |
2710 | int badop = 1; | |
2711 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2712 | int winreg = 0; | |
2713 | int c; | |
2714 | register rtx operand = recog_operand[i]; | |
2715 | int offset = 0; | |
2716 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2717 | regardless of what the constraint says. */ | |
2718 | int force_reload = 0; | |
2719 | int offmemok = 0; | |
9d926da5 RK |
2720 | /* Nonzero if a constant forced into memory would be OK for this |
2721 | operand. */ | |
2722 | int constmemok = 0; | |
eab89b90 RK |
2723 | int earlyclobber = 0; |
2724 | ||
ff428c90 ILT |
2725 | /* If the predicate accepts a unary operator, it means that |
2726 | we need to reload the operand. */ | |
2727 | if (GET_RTX_CLASS (GET_CODE (operand)) == '1') | |
2728 | operand = XEXP (operand, 0); | |
2729 | ||
eab89b90 RK |
2730 | /* If the operand is a SUBREG, extract |
2731 | the REG or MEM (or maybe even a constant) within. | |
2732 | (Constants can occur as a result of reg_equiv_constant.) */ | |
2733 | ||
2734 | while (GET_CODE (operand) == SUBREG) | |
2735 | { | |
2736 | offset += SUBREG_WORD (operand); | |
2737 | operand = SUBREG_REG (operand); | |
ca769828 | 2738 | /* Force reload if this is a constant or PLUS or if there may may |
a61c98cf RK |
2739 | be a problem accessing OPERAND in the outer mode. */ |
2740 | if (CONSTANT_P (operand) | |
ca769828 | 2741 | || GET_CODE (operand) == PLUS |
03b72c86 RK |
2742 | /* We must force a reload of paradoxical SUBREGs |
2743 | of a MEM because the alignment of the inner value | |
beb5a9b8 RK |
2744 | may not be enough to do the outer reference. On |
2745 | big-endian machines, it may also reference outside | |
2746 | the object. | |
03b72c86 RK |
2747 | |
2748 | On machines that extend byte operations and we have a | |
486d8509 RK |
2749 | SUBREG where both the inner and outer modes are no wider |
2750 | than a word and the inner mode is narrower, is integral, | |
2751 | and gets extended when loaded from memory, combine.c has | |
2752 | made assumptions about the behavior of the machine in such | |
03b72c86 RK |
2753 | register access. If the data is, in fact, in memory we |
2754 | must always load using the size assumed to be in the | |
2755 | register and let the insn do the different-sized | |
5ec105cd RH |
2756 | accesses. |
2757 | ||
2758 | This is doubly true if WORD_REGISTER_OPERATIONS. In | |
2759 | this case eliminate_regs has left non-paradoxical | |
2760 | subregs for push_reloads to see. Make sure it does | |
2761 | by forcing the reload. | |
2762 | ||
2763 | ??? When is it right at this stage to have a subreg | |
2764 | of a mem that is _not_ to be handled specialy? IMO | |
2765 | those should have been reduced to just a mem. */ | |
a61c98cf RK |
2766 | || ((GET_CODE (operand) == MEM |
2767 | || (GET_CODE (operand)== REG | |
2768 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
5ec105cd | 2769 | #ifndef WORD_REGISTER_OPERATIONS |
03b72c86 RK |
2770 | && (((GET_MODE_BITSIZE (GET_MODE (operand)) |
2771 | < BIGGEST_ALIGNMENT) | |
2772 | && (GET_MODE_SIZE (operand_mode[i]) | |
2773 | > GET_MODE_SIZE (GET_MODE (operand)))) | |
beb5a9b8 | 2774 | || (GET_CODE (operand) == MEM && BYTES_BIG_ENDIAN) |
03b72c86 RK |
2775 | #ifdef LOAD_EXTEND_OP |
2776 | || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
2777 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2778 | <= UNITS_PER_WORD) | |
2779 | && (GET_MODE_SIZE (operand_mode[i]) | |
486d8509 RK |
2780 | > GET_MODE_SIZE (GET_MODE (operand))) |
2781 | && INTEGRAL_MODE_P (GET_MODE (operand)) | |
2782 | && LOAD_EXTEND_OP (GET_MODE (operand)) != NIL) | |
46da6b3a | 2783 | #endif |
5ec105cd RH |
2784 | ) |
2785 | #endif | |
2786 | ) | |
eab89b90 RK |
2787 | /* Subreg of a hard reg which can't handle the subreg's mode |
2788 | or which would handle that mode in the wrong number of | |
2789 | registers for subregging to work. */ | |
a61c98cf RK |
2790 | || (GET_CODE (operand) == REG |
2791 | && REGNO (operand) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
2792 | && ((GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
2793 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2794 | > UNITS_PER_WORD) | |
2795 | && ((GET_MODE_SIZE (GET_MODE (operand)) | |
2796 | / UNITS_PER_WORD) | |
2797 | != HARD_REGNO_NREGS (REGNO (operand), | |
2798 | GET_MODE (operand)))) | |
2799 | || ! HARD_REGNO_MODE_OK (REGNO (operand) + offset, | |
2800 | operand_mode[i])))) | |
eab89b90 RK |
2801 | force_reload = 1; |
2802 | } | |
2803 | ||
2804 | this_alternative[i] = (int) NO_REGS; | |
2805 | this_alternative_win[i] = 0; | |
2806 | this_alternative_offmemok[i] = 0; | |
2807 | this_alternative_earlyclobber[i] = 0; | |
2808 | this_alternative_matches[i] = -1; | |
2809 | ||
2810 | /* An empty constraint or empty alternative | |
2811 | allows anything which matched the pattern. */ | |
2812 | if (*p == 0 || *p == ',') | |
2813 | win = 1, badop = 0; | |
2814 | ||
2815 | /* Scan this alternative's specs for this operand; | |
2816 | set WIN if the operand fits any letter in this alternative. | |
2817 | Otherwise, clear BADOP if this operand could | |
2818 | fit some letter after reloads, | |
2819 | or set WINREG if this operand could fit after reloads | |
2820 | provided the constraint allows some registers. */ | |
2821 | ||
2822 | while (*p && (c = *p++) != ',') | |
2823 | switch (c) | |
2824 | { | |
2825 | case '=': | |
eab89b90 | 2826 | case '+': |
eab89b90 RK |
2827 | case '*': |
2828 | break; | |
2829 | ||
2830 | case '%': | |
42add480 TW |
2831 | /* The last operand should not be marked commutative. */ |
2832 | if (i != noperands - 1) | |
2833 | commutative = i; | |
eab89b90 RK |
2834 | break; |
2835 | ||
2836 | case '?': | |
2837 | reject += 3; | |
2838 | break; | |
2839 | ||
2840 | case '!': | |
2841 | reject = 300; | |
2842 | break; | |
2843 | ||
2844 | case '#': | |
2845 | /* Ignore rest of this alternative as far as | |
2846 | reloading is concerned. */ | |
2847 | while (*p && *p != ',') p++; | |
2848 | break; | |
2849 | ||
2850 | case '0': | |
2851 | case '1': | |
2852 | case '2': | |
2853 | case '3': | |
2854 | case '4': | |
2855 | c -= '0'; | |
2856 | this_alternative_matches[i] = c; | |
2857 | /* We are supposed to match a previous operand. | |
2858 | If we do, we win if that one did. | |
2859 | If we do not, count both of the operands as losers. | |
2860 | (This is too conservative, since most of the time | |
2861 | only a single reload insn will be needed to make | |
2862 | the two operands win. As a result, this alternative | |
2863 | may be rejected when it is actually desirable.) */ | |
2864 | if ((swapped && (c != commutative || i != commutative + 1)) | |
2865 | /* If we are matching as if two operands were swapped, | |
2866 | also pretend that operands_match had been computed | |
2867 | with swapped. | |
2868 | But if I is the second of those and C is the first, | |
2869 | don't exchange them, because operands_match is valid | |
2870 | only on one side of its diagonal. */ | |
2871 | ? (operands_match | |
2872 | [(c == commutative || c == commutative + 1) | |
2873 | ? 2*commutative + 1 - c : c] | |
2874 | [(i == commutative || i == commutative + 1) | |
2875 | ? 2*commutative + 1 - i : i]) | |
2876 | : operands_match[c][i]) | |
fc79eafe JW |
2877 | { |
2878 | /* If we are matching a non-offsettable address where an | |
2879 | offsettable address was expected, then we must reject | |
2880 | this combination, because we can't reload it. */ | |
2881 | if (this_alternative_offmemok[c] | |
2882 | && GET_CODE (recog_operand[c]) == MEM | |
2883 | && this_alternative[c] == (int) NO_REGS | |
2884 | && ! this_alternative_win[c]) | |
2885 | bad = 1; | |
2886 | ||
2887 | win = this_alternative_win[c]; | |
2888 | } | |
eab89b90 RK |
2889 | else |
2890 | { | |
2891 | /* Operands don't match. */ | |
2892 | rtx value; | |
2893 | /* Retroactively mark the operand we had to match | |
2894 | as a loser, if it wasn't already. */ | |
2895 | if (this_alternative_win[c]) | |
2896 | losers++; | |
2897 | this_alternative_win[c] = 0; | |
2898 | if (this_alternative[c] == (int) NO_REGS) | |
2899 | bad = 1; | |
2900 | /* But count the pair only once in the total badness of | |
2901 | this alternative, if the pair can be a dummy reload. */ | |
2902 | value | |
2903 | = find_dummy_reload (recog_operand[i], recog_operand[c], | |
2904 | recog_operand_loc[i], recog_operand_loc[c], | |
adb44af8 | 2905 | operand_mode[i], operand_mode[c], |
189086f9 RK |
2906 | this_alternative[c], -1, |
2907 | this_alternative_earlyclobber[c]); | |
eab89b90 RK |
2908 | |
2909 | if (value != 0) | |
2910 | losers--; | |
2911 | } | |
2912 | /* This can be fixed with reloads if the operand | |
2913 | we are supposed to match can be fixed with reloads. */ | |
2914 | badop = 0; | |
2915 | this_alternative[i] = this_alternative[c]; | |
e64c4f9e RK |
2916 | |
2917 | /* If we have to reload this operand and some previous | |
2918 | operand also had to match the same thing as this | |
2919 | operand, we don't know how to do that. So reject this | |
2920 | alternative. */ | |
2921 | if (! win || force_reload) | |
2922 | for (j = 0; j < i; j++) | |
2923 | if (this_alternative_matches[j] | |
2924 | == this_alternative_matches[i]) | |
2925 | badop = 1; | |
2926 | ||
eab89b90 RK |
2927 | break; |
2928 | ||
2929 | case 'p': | |
2930 | /* All necessary reloads for an address_operand | |
2931 | were handled in find_reloads_address. */ | |
5c73e847 | 2932 | this_alternative[i] = (int) BASE_REG_CLASS; |
eab89b90 RK |
2933 | win = 1; |
2934 | break; | |
2935 | ||
2936 | case 'm': | |
2937 | if (force_reload) | |
2938 | break; | |
2939 | if (GET_CODE (operand) == MEM | |
2940 | || (GET_CODE (operand) == REG | |
2941 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2942 | && reg_renumber[REGNO (operand)] < 0)) | |
2943 | win = 1; | |
3feffdfe JW |
2944 | if (CONSTANT_P (operand) |
2945 | /* force_const_mem does not accept HIGH. */ | |
2946 | && GET_CODE (operand) != HIGH) | |
eab89b90 | 2947 | badop = 0; |
9d926da5 | 2948 | constmemok = 1; |
eab89b90 RK |
2949 | break; |
2950 | ||
2951 | case '<': | |
2952 | if (GET_CODE (operand) == MEM | |
2953 | && ! address_reloaded[i] | |
2954 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
2955 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
2956 | win = 1; | |
2957 | break; | |
2958 | ||
2959 | case '>': | |
2960 | if (GET_CODE (operand) == MEM | |
2961 | && ! address_reloaded[i] | |
2962 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
2963 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
2964 | win = 1; | |
2965 | break; | |
2966 | ||
2967 | /* Memory operand whose address is not offsettable. */ | |
2968 | case 'V': | |
2969 | if (force_reload) | |
2970 | break; | |
2971 | if (GET_CODE (operand) == MEM | |
2972 | && ! (ind_levels ? offsettable_memref_p (operand) | |
2973 | : offsettable_nonstrict_memref_p (operand)) | |
2974 | /* Certain mem addresses will become offsettable | |
2975 | after they themselves are reloaded. This is important; | |
2976 | we don't want our own handling of unoffsettables | |
2977 | to override the handling of reg_equiv_address. */ | |
2978 | && !(GET_CODE (XEXP (operand, 0)) == REG | |
2979 | && (ind_levels == 0 | |
2980 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) | |
2981 | win = 1; | |
2982 | break; | |
2983 | ||
2984 | /* Memory operand whose address is offsettable. */ | |
2985 | case 'o': | |
2986 | if (force_reload) | |
2987 | break; | |
2988 | if ((GET_CODE (operand) == MEM | |
2989 | /* If IND_LEVELS, find_reloads_address won't reload a | |
2990 | pseudo that didn't get a hard reg, so we have to | |
2991 | reject that case. */ | |
2992 | && (ind_levels ? offsettable_memref_p (operand) | |
2993 | : offsettable_nonstrict_memref_p (operand))) | |
26ba4aee JW |
2994 | /* A reloaded auto-increment address is offsettable, |
2995 | because it is now just a simple register indirect. */ | |
2996 | || (GET_CODE (operand) == MEM | |
2997 | && address_reloaded[i] | |
2998 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
2999 | || GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
3000 | || GET_CODE (XEXP (operand, 0)) == POST_INC | |
3001 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
eab89b90 RK |
3002 | /* Certain mem addresses will become offsettable |
3003 | after they themselves are reloaded. This is important; | |
3004 | we don't want our own handling of unoffsettables | |
3005 | to override the handling of reg_equiv_address. */ | |
3006 | || (GET_CODE (operand) == MEM | |
3007 | && GET_CODE (XEXP (operand, 0)) == REG | |
3008 | && (ind_levels == 0 | |
3009 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)) | |
3010 | || (GET_CODE (operand) == REG | |
3011 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3a322c50 RK |
3012 | && reg_renumber[REGNO (operand)] < 0 |
3013 | /* If reg_equiv_address is nonzero, we will be | |
3014 | loading it into a register; hence it will be | |
3015 | offsettable, but we cannot say that reg_equiv_mem | |
3016 | is offsettable without checking. */ | |
3017 | && ((reg_equiv_mem[REGNO (operand)] != 0 | |
3018 | && offsettable_memref_p (reg_equiv_mem[REGNO (operand)])) | |
3019 | || (reg_equiv_address[REGNO (operand)] != 0)))) | |
eab89b90 | 3020 | win = 1; |
3feffdfe JW |
3021 | /* force_const_mem does not accept HIGH. */ |
3022 | if ((CONSTANT_P (operand) && GET_CODE (operand) != HIGH) | |
3023 | || GET_CODE (operand) == MEM) | |
eab89b90 | 3024 | badop = 0; |
9d926da5 | 3025 | constmemok = 1; |
eab89b90 RK |
3026 | offmemok = 1; |
3027 | break; | |
3028 | ||
3029 | case '&': | |
3030 | /* Output operand that is stored before the need for the | |
3031 | input operands (and their index registers) is over. */ | |
3032 | earlyclobber = 1, this_earlyclobber = 1; | |
3033 | break; | |
3034 | ||
3035 | case 'E': | |
293166be | 3036 | #ifndef REAL_ARITHMETIC |
eab89b90 RK |
3037 | /* Match any floating double constant, but only if |
3038 | we can examine the bits of it reliably. */ | |
3039 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
fb3821f7 | 3040 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
eab89b90 RK |
3041 | && GET_MODE (operand) != VOIDmode && ! flag_pretend_float) |
3042 | break; | |
293166be | 3043 | #endif |
eab89b90 RK |
3044 | if (GET_CODE (operand) == CONST_DOUBLE) |
3045 | win = 1; | |
3046 | break; | |
3047 | ||
3048 | case 'F': | |
3049 | if (GET_CODE (operand) == CONST_DOUBLE) | |
3050 | win = 1; | |
3051 | break; | |
3052 | ||
3053 | case 'G': | |
3054 | case 'H': | |
3055 | if (GET_CODE (operand) == CONST_DOUBLE | |
3056 | && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c)) | |
3057 | win = 1; | |
3058 | break; | |
3059 | ||
3060 | case 's': | |
3061 | if (GET_CODE (operand) == CONST_INT | |
3062 | || (GET_CODE (operand) == CONST_DOUBLE | |
3063 | && GET_MODE (operand) == VOIDmode)) | |
3064 | break; | |
3065 | case 'i': | |
3066 | if (CONSTANT_P (operand) | |
3067 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
3068 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)) | |
3069 | #endif | |
3070 | ) | |
3071 | win = 1; | |
3072 | break; | |
3073 | ||
3074 | case 'n': | |
3075 | if (GET_CODE (operand) == CONST_INT | |
3076 | || (GET_CODE (operand) == CONST_DOUBLE | |
3077 | && GET_MODE (operand) == VOIDmode)) | |
3078 | win = 1; | |
3079 | break; | |
3080 | ||
3081 | case 'I': | |
3082 | case 'J': | |
3083 | case 'K': | |
3084 | case 'L': | |
3085 | case 'M': | |
3086 | case 'N': | |
3087 | case 'O': | |
3088 | case 'P': | |
3089 | if (GET_CODE (operand) == CONST_INT | |
3090 | && CONST_OK_FOR_LETTER_P (INTVAL (operand), c)) | |
3091 | win = 1; | |
3092 | break; | |
3093 | ||
3094 | case 'X': | |
3095 | win = 1; | |
3096 | break; | |
3097 | ||
3098 | case 'g': | |
3099 | if (! force_reload | |
3100 | /* A PLUS is never a valid operand, but reload can make | |
3101 | it from a register when eliminating registers. */ | |
3102 | && GET_CODE (operand) != PLUS | |
3103 | /* A SCRATCH is not a valid operand. */ | |
3104 | && GET_CODE (operand) != SCRATCH | |
3105 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
3106 | && (! CONSTANT_P (operand) | |
3107 | || ! flag_pic | |
3108 | || LEGITIMATE_PIC_OPERAND_P (operand)) | |
3109 | #endif | |
3110 | && (GENERAL_REGS == ALL_REGS | |
3111 | || GET_CODE (operand) != REG | |
3112 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3113 | && reg_renumber[REGNO (operand)] < 0))) | |
3114 | win = 1; | |
3115 | /* Drop through into 'r' case */ | |
3116 | ||
3117 | case 'r': | |
3118 | this_alternative[i] | |
3119 | = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; | |
3120 | goto reg; | |
3121 | ||
3122 | #ifdef EXTRA_CONSTRAINT | |
3123 | case 'Q': | |
3124 | case 'R': | |
3125 | case 'S': | |
3126 | case 'T': | |
3127 | case 'U': | |
3128 | if (EXTRA_CONSTRAINT (operand, c)) | |
3129 | win = 1; | |
3130 | break; | |
3131 | #endif | |
3132 | ||
3133 | default: | |
3134 | this_alternative[i] | |
3135 | = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)]; | |
3136 | ||
3137 | reg: | |
3138 | if (GET_MODE (operand) == BLKmode) | |
3139 | break; | |
3140 | winreg = 1; | |
3141 | if (GET_CODE (operand) == REG | |
3142 | && reg_fits_class_p (operand, this_alternative[i], | |
3143 | offset, GET_MODE (recog_operand[i]))) | |
3144 | win = 1; | |
3145 | break; | |
3146 | } | |
3147 | ||
3148 | constraints[i] = p; | |
3149 | ||
3150 | /* If this operand could be handled with a reg, | |
3151 | and some reg is allowed, then this operand can be handled. */ | |
3152 | if (winreg && this_alternative[i] != (int) NO_REGS) | |
3153 | badop = 0; | |
3154 | ||
3155 | /* Record which operands fit this alternative. */ | |
3156 | this_alternative_earlyclobber[i] = earlyclobber; | |
3157 | if (win && ! force_reload) | |
3158 | this_alternative_win[i] = 1; | |
3159 | else | |
3160 | { | |
9d926da5 RK |
3161 | int const_to_mem = 0; |
3162 | ||
eab89b90 RK |
3163 | this_alternative_offmemok[i] = offmemok; |
3164 | losers++; | |
3165 | if (badop) | |
3166 | bad = 1; | |
3167 | /* Alternative loses if it has no regs for a reg operand. */ | |
3168 | if (GET_CODE (operand) == REG | |
3169 | && this_alternative[i] == (int) NO_REGS | |
3170 | && this_alternative_matches[i] < 0) | |
3171 | bad = 1; | |
3172 | ||
3173 | /* Alternative loses if it requires a type of reload not | |
3174 | permitted for this insn. We can always reload SCRATCH | |
3175 | and objects with a REG_UNUSED note. */ | |
a8c9daeb RK |
3176 | if (GET_CODE (operand) != SCRATCH |
3177 | && modified[i] != RELOAD_READ && no_output_reloads | |
eab89b90 RK |
3178 | && ! find_reg_note (insn, REG_UNUSED, operand)) |
3179 | bad = 1; | |
3180 | else if (modified[i] != RELOAD_WRITE && no_input_reloads) | |
3181 | bad = 1; | |
3182 | ||
3a322c50 RK |
3183 | /* If this is a constant that is reloaded into the desired |
3184 | class by copying it to memory first, count that as another | |
3185 | reload. This is consistent with other code and is | |
293166be | 3186 | required to avoid choosing another alternative when |
3a322c50 RK |
3187 | the constant is moved into memory by this function on |
3188 | an early reload pass. Note that the test here is | |
3189 | precisely the same as in the code below that calls | |
3190 | force_const_mem. */ | |
3191 | if (CONSTANT_P (operand) | |
59f25cf9 RK |
3192 | /* force_const_mem does not accept HIGH. */ |
3193 | && GET_CODE (operand) != HIGH | |
3a322c50 RK |
3194 | && (PREFERRED_RELOAD_CLASS (operand, |
3195 | (enum reg_class) this_alternative[i]) | |
3196 | == NO_REGS) | |
3a322c50 | 3197 | && operand_mode[i] != VOIDmode) |
9d926da5 RK |
3198 | { |
3199 | const_to_mem = 1; | |
3200 | if (this_alternative[i] != (int) NO_REGS) | |
3201 | losers++; | |
3202 | } | |
3a322c50 | 3203 | |
5e6aa513 RK |
3204 | /* If we can't reload this value at all, reject this |
3205 | alternative. Note that we could also lose due to | |
3206 | LIMIT_RELOAD_RELOAD_CLASS, but we don't check that | |
3207 | here. */ | |
3208 | ||
3209 | if (! CONSTANT_P (operand) | |
73b236b5 | 3210 | && (enum reg_class) this_alternative[i] != NO_REGS |
5e6aa513 RK |
3211 | && (PREFERRED_RELOAD_CLASS (operand, |
3212 | (enum reg_class) this_alternative[i]) | |
3213 | == NO_REGS)) | |
3214 | bad = 1; | |
3215 | ||
eab89b90 RK |
3216 | /* We prefer to reload pseudos over reloading other things, |
3217 | since such reloads may be able to be eliminated later. | |
3218 | If we are reloading a SCRATCH, we won't be generating any | |
3219 | insns, just using a register, so it is also preferred. | |
9d926da5 RK |
3220 | So bump REJECT in other cases. Don't do this in the |
3221 | case where we are forcing a constant into memory and | |
3222 | it will then win since we don't want to have a different | |
3223 | alternative match then. */ | |
915bb763 RK |
3224 | if (! (GET_CODE (operand) == REG |
3225 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER) | |
9d926da5 RK |
3226 | && GET_CODE (operand) != SCRATCH |
3227 | && ! (const_to_mem && constmemok)) | |
eab89b90 RK |
3228 | reject++; |
3229 | } | |
3230 | ||
3231 | /* If this operand is a pseudo register that didn't get a hard | |
3232 | reg and this alternative accepts some register, see if the | |
3233 | class that we want is a subset of the preferred class for this | |
3234 | register. If not, but it intersects that class, use the | |
3235 | preferred class instead. If it does not intersect the preferred | |
3236 | class, show that usage of this alternative should be discouraged; | |
3237 | it will be discouraged more still if the register is `preferred | |
3238 | or nothing'. We do this because it increases the chance of | |
3239 | reusing our spill register in a later insn and avoiding a pair | |
3240 | of memory stores and loads. | |
3241 | ||
3242 | Don't bother with this if this alternative will accept this | |
3243 | operand. | |
3244 | ||
a2d353e5 RK |
3245 | Don't do this for a multiword operand, since it is only a |
3246 | small win and has the risk of requiring more spill registers, | |
3247 | which could cause a large loss. | |
5aa14fee | 3248 | |
eab89b90 RK |
3249 | Don't do this if the preferred class has only one register |
3250 | because we might otherwise exhaust the class. */ | |
3251 | ||
3252 | ||
3253 | if (! win && this_alternative[i] != (int) NO_REGS | |
5aa14fee | 3254 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
eab89b90 RK |
3255 | && reg_class_size[(int) preferred_class[i]] > 1) |
3256 | { | |
3257 | if (! reg_class_subset_p (this_alternative[i], | |
3258 | preferred_class[i])) | |
3259 | { | |
3260 | /* Since we don't have a way of forming the intersection, | |
3261 | we just do something special if the preferred class | |
3262 | is a subset of the class we have; that's the most | |
3263 | common case anyway. */ | |
3264 | if (reg_class_subset_p (preferred_class[i], | |
3265 | this_alternative[i])) | |
3266 | this_alternative[i] = (int) preferred_class[i]; | |
3267 | else | |
3268 | reject += (1 + pref_or_nothing[i]); | |
3269 | } | |
3270 | } | |
3271 | } | |
3272 | ||
3273 | /* Now see if any output operands that are marked "earlyclobber" | |
3274 | in this alternative conflict with any input operands | |
3275 | or any memory addresses. */ | |
3276 | ||
3277 | for (i = 0; i < noperands; i++) | |
3278 | if (this_alternative_earlyclobber[i] | |
3279 | && this_alternative_win[i]) | |
3280 | { | |
3281 | struct decomposition early_data; | |
eab89b90 RK |
3282 | |
3283 | early_data = decompose (recog_operand[i]); | |
3284 | ||
3285 | if (modified[i] == RELOAD_READ) | |
3286 | { | |
3287 | if (this_insn_is_asm) | |
3288 | warning_for_asm (this_insn, | |
3289 | "`&' constraint used with input operand"); | |
3290 | else | |
3291 | abort (); | |
3292 | continue; | |
3293 | } | |
3294 | ||
3295 | if (this_alternative[i] == NO_REGS) | |
3296 | { | |
3297 | this_alternative_earlyclobber[i] = 0; | |
3298 | if (this_insn_is_asm) | |
3299 | error_for_asm (this_insn, | |
3300 | "`&' constraint used with no register class"); | |
3301 | else | |
3302 | abort (); | |
3303 | } | |
3304 | ||
3305 | for (j = 0; j < noperands; j++) | |
3306 | /* Is this an input operand or a memory ref? */ | |
3307 | if ((GET_CODE (recog_operand[j]) == MEM | |
3308 | || modified[j] != RELOAD_WRITE) | |
3309 | && j != i | |
3310 | /* Ignore things like match_operator operands. */ | |
3311 | && *constraints1[j] != 0 | |
3312 | /* Don't count an input operand that is constrained to match | |
3313 | the early clobber operand. */ | |
3314 | && ! (this_alternative_matches[j] == i | |
3315 | && rtx_equal_p (recog_operand[i], recog_operand[j])) | |
3316 | /* Is it altered by storing the earlyclobber operand? */ | |
3317 | && !immune_p (recog_operand[j], recog_operand[i], early_data)) | |
3318 | { | |
3319 | /* If the output is in a single-reg class, | |
3320 | it's costly to reload it, so reload the input instead. */ | |
3321 | if (reg_class_size[this_alternative[i]] == 1 | |
3322 | && (GET_CODE (recog_operand[j]) == REG | |
3323 | || GET_CODE (recog_operand[j]) == SUBREG)) | |
3324 | { | |
3325 | losers++; | |
3326 | this_alternative_win[j] = 0; | |
3327 | } | |
3328 | else | |
3329 | break; | |
3330 | } | |
3331 | /* If an earlyclobber operand conflicts with something, | |
3332 | it must be reloaded, so request this and count the cost. */ | |
3333 | if (j != noperands) | |
3334 | { | |
3335 | losers++; | |
3336 | this_alternative_win[i] = 0; | |
3337 | for (j = 0; j < noperands; j++) | |
3338 | if (this_alternative_matches[j] == i | |
3339 | && this_alternative_win[j]) | |
3340 | { | |
3341 | this_alternative_win[j] = 0; | |
3342 | losers++; | |
3343 | } | |
3344 | } | |
3345 | } | |
3346 | ||
3347 | /* If one alternative accepts all the operands, no reload required, | |
3348 | choose that alternative; don't consider the remaining ones. */ | |
3349 | if (losers == 0) | |
3350 | { | |
3351 | /* Unswap these so that they are never swapped at `finish'. */ | |
3352 | if (commutative >= 0) | |
3353 | { | |
3354 | recog_operand[commutative] = substed_operand[commutative]; | |
3355 | recog_operand[commutative + 1] | |
3356 | = substed_operand[commutative + 1]; | |
3357 | } | |
3358 | for (i = 0; i < noperands; i++) | |
3359 | { | |
3360 | goal_alternative_win[i] = 1; | |
3361 | goal_alternative[i] = this_alternative[i]; | |
3362 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3363 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3364 | goal_alternative_earlyclobber[i] | |
3365 | = this_alternative_earlyclobber[i]; | |
3366 | } | |
3367 | goal_alternative_number = this_alternative_number; | |
3368 | goal_alternative_swapped = swapped; | |
3369 | goal_earlyclobber = this_earlyclobber; | |
3370 | goto finish; | |
3371 | } | |
3372 | ||
3373 | /* REJECT, set by the ! and ? constraint characters and when a register | |
3374 | would be reloaded into a non-preferred class, discourages the use of | |
3375 | this alternative for a reload goal. REJECT is incremented by three | |
3376 | for each ? and one for each non-preferred class. */ | |
3377 | losers = losers * 3 + reject; | |
3378 | ||
3379 | /* If this alternative can be made to work by reloading, | |
3380 | and it needs less reloading than the others checked so far, | |
3381 | record it as the chosen goal for reloading. */ | |
3382 | if (! bad && best > losers) | |
3383 | { | |
3384 | for (i = 0; i < noperands; i++) | |
3385 | { | |
3386 | goal_alternative[i] = this_alternative[i]; | |
3387 | goal_alternative_win[i] = this_alternative_win[i]; | |
3388 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3389 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3390 | goal_alternative_earlyclobber[i] | |
3391 | = this_alternative_earlyclobber[i]; | |
3392 | } | |
3393 | goal_alternative_swapped = swapped; | |
3394 | best = losers; | |
3395 | goal_alternative_number = this_alternative_number; | |
3396 | goal_earlyclobber = this_earlyclobber; | |
3397 | } | |
3398 | } | |
3399 | ||
3400 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
3401 | then we need to try each alternative twice, | |
3402 | the second time matching those two operands | |
3403 | as if we had exchanged them. | |
3404 | To do this, really exchange them in operands. | |
3405 | ||
3406 | If we have just tried the alternatives the second time, | |
3407 | return operands to normal and drop through. */ | |
3408 | ||
3409 | if (commutative >= 0) | |
3410 | { | |
3411 | swapped = !swapped; | |
3412 | if (swapped) | |
3413 | { | |
3414 | register enum reg_class tclass; | |
3415 | register int t; | |
3416 | ||
3417 | recog_operand[commutative] = substed_operand[commutative + 1]; | |
3418 | recog_operand[commutative + 1] = substed_operand[commutative]; | |
3419 | ||
3420 | tclass = preferred_class[commutative]; | |
3421 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
3422 | preferred_class[commutative + 1] = tclass; | |
3423 | ||
3424 | t = pref_or_nothing[commutative]; | |
3425 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
3426 | pref_or_nothing[commutative + 1] = t; | |
3427 | ||
4c9a05bc RK |
3428 | bcopy ((char *) constraints1, (char *) constraints, |
3429 | noperands * sizeof (char *)); | |
eab89b90 RK |
3430 | goto try_swapped; |
3431 | } | |
3432 | else | |
3433 | { | |
3434 | recog_operand[commutative] = substed_operand[commutative]; | |
3435 | recog_operand[commutative + 1] = substed_operand[commutative + 1]; | |
3436 | } | |
3437 | } | |
3438 | ||
3439 | /* The operands don't meet the constraints. | |
3440 | goal_alternative describes the alternative | |
3441 | that we could reach by reloading the fewest operands. | |
3442 | Reload so as to fit it. */ | |
3443 | ||
3444 | if (best == MAX_RECOG_OPERANDS + 300) | |
3445 | { | |
3446 | /* No alternative works with reloads?? */ | |
3447 | if (insn_code_number >= 0) | |
3448 | abort (); | |
3449 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3450 | /* Avoid further trouble with this insn. */ | |
38a448ca | 3451 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 RK |
3452 | n_reloads = 0; |
3453 | return; | |
3454 | } | |
3455 | ||
3456 | /* Jump to `finish' from above if all operands are valid already. | |
3457 | In that case, goal_alternative_win is all 1. */ | |
3458 | finish: | |
3459 | ||
3460 | /* Right now, for any pair of operands I and J that are required to match, | |
3461 | with I < J, | |
3462 | goal_alternative_matches[J] is I. | |
3463 | Set up goal_alternative_matched as the inverse function: | |
3464 | goal_alternative_matched[I] = J. */ | |
3465 | ||
3466 | for (i = 0; i < noperands; i++) | |
3467 | goal_alternative_matched[i] = -1; | |
3468 | ||
3469 | for (i = 0; i < noperands; i++) | |
3470 | if (! goal_alternative_win[i] | |
3471 | && goal_alternative_matches[i] >= 0) | |
3472 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
3473 | ||
3474 | /* If the best alternative is with operands 1 and 2 swapped, | |
a8c9daeb RK |
3475 | consider them swapped before reporting the reloads. Update the |
3476 | operand numbers of any reloads already pushed. */ | |
eab89b90 RK |
3477 | |
3478 | if (goal_alternative_swapped) | |
3479 | { | |
3480 | register rtx tem; | |
3481 | ||
3482 | tem = substed_operand[commutative]; | |
3483 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
3484 | substed_operand[commutative + 1] = tem; | |
3485 | tem = recog_operand[commutative]; | |
3486 | recog_operand[commutative] = recog_operand[commutative + 1]; | |
3487 | recog_operand[commutative + 1] = tem; | |
a8c9daeb RK |
3488 | |
3489 | for (i = 0; i < n_reloads; i++) | |
3490 | { | |
3491 | if (reload_opnum[i] == commutative) | |
3492 | reload_opnum[i] = commutative + 1; | |
3493 | else if (reload_opnum[i] == commutative + 1) | |
3494 | reload_opnum[i] = commutative; | |
3495 | } | |
eab89b90 RK |
3496 | } |
3497 | ||
3498 | /* Perform whatever substitutions on the operands we are supposed | |
3499 | to make due to commutativity or replacement of registers | |
3500 | with equivalent constants or memory slots. */ | |
3501 | ||
3502 | for (i = 0; i < noperands; i++) | |
3503 | { | |
3504 | *recog_operand_loc[i] = substed_operand[i]; | |
3505 | /* While we are looping on operands, initialize this. */ | |
3506 | operand_reloadnum[i] = -1; | |
a8c9daeb RK |
3507 | |
3508 | /* If this is an earlyclobber operand, we need to widen the scope. | |
3509 | The reload must remain valid from the start of the insn being | |
3510 | reloaded until after the operand is stored into its destination. | |
3511 | We approximate this with RELOAD_OTHER even though we know that we | |
3512 | do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. | |
3513 | ||
3514 | One special case that is worth checking is when we have an | |
3515 | output that is earlyclobber but isn't used past the insn (typically | |
3516 | a SCRATCH). In this case, we only need have the reload live | |
3517 | through the insn itself, but not for any of our input or output | |
3518 | reloads. | |
3519 | ||
3520 | In any case, anything needed to address this operand can remain | |
3521 | however they were previously categorized. */ | |
3522 | ||
3523 | if (goal_alternative_earlyclobber[i]) | |
3524 | operand_type[i] | |
3525 | = (find_reg_note (insn, REG_UNUSED, recog_operand[i]) | |
3526 | ? RELOAD_FOR_INSN : RELOAD_OTHER); | |
eab89b90 RK |
3527 | } |
3528 | ||
3529 | /* Any constants that aren't allowed and can't be reloaded | |
3530 | into registers are here changed into memory references. */ | |
3531 | for (i = 0; i < noperands; i++) | |
3532 | if (! goal_alternative_win[i] | |
3533 | && CONSTANT_P (recog_operand[i]) | |
59f25cf9 RK |
3534 | /* force_const_mem does not accept HIGH. */ |
3535 | && GET_CODE (recog_operand[i]) != HIGH | |
eab89b90 RK |
3536 | && (PREFERRED_RELOAD_CLASS (recog_operand[i], |
3537 | (enum reg_class) goal_alternative[i]) | |
3538 | == NO_REGS) | |
3539 | && operand_mode[i] != VOIDmode) | |
3540 | { | |
3541 | *recog_operand_loc[i] = recog_operand[i] | |
3542 | = find_reloads_toplev (force_const_mem (operand_mode[i], | |
3543 | recog_operand[i]), | |
a8c9daeb | 3544 | i, address_type[i], ind_levels, 0); |
eab89b90 RK |
3545 | if (alternative_allows_memconst (constraints1[i], |
3546 | goal_alternative_number)) | |
3547 | goal_alternative_win[i] = 1; | |
3548 | } | |
3549 | ||
4644aad4 RK |
3550 | /* Record the values of the earlyclobber operands for the caller. */ |
3551 | if (goal_earlyclobber) | |
3552 | for (i = 0; i < noperands; i++) | |
3553 | if (goal_alternative_earlyclobber[i]) | |
3554 | reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i]; | |
3555 | ||
eab89b90 RK |
3556 | /* Now record reloads for all the operands that need them. */ |
3557 | for (i = 0; i < noperands; i++) | |
3558 | if (! goal_alternative_win[i]) | |
3559 | { | |
3560 | /* Operands that match previous ones have already been handled. */ | |
3561 | if (goal_alternative_matches[i] >= 0) | |
3562 | ; | |
3563 | /* Handle an operand with a nonoffsettable address | |
3564 | appearing where an offsettable address will do | |
3a322c50 RK |
3565 | by reloading the address into a base register. |
3566 | ||
3567 | ??? We can also do this when the operand is a register and | |
3568 | reg_equiv_mem is not offsettable, but this is a bit tricky, | |
3569 | so we don't bother with it. It may not be worth doing. */ | |
eab89b90 RK |
3570 | else if (goal_alternative_matched[i] == -1 |
3571 | && goal_alternative_offmemok[i] | |
3572 | && GET_CODE (recog_operand[i]) == MEM) | |
3573 | { | |
3574 | operand_reloadnum[i] | |
fb3821f7 CH |
3575 | = push_reload (XEXP (recog_operand[i], 0), NULL_RTX, |
3576 | &XEXP (recog_operand[i], 0), NULL_PTR, | |
eab89b90 | 3577 | BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)), |
a8c9daeb | 3578 | VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); |
eab89b90 RK |
3579 | reload_inc[operand_reloadnum[i]] |
3580 | = GET_MODE_SIZE (GET_MODE (recog_operand[i])); | |
a8c9daeb RK |
3581 | |
3582 | /* If this operand is an output, we will have made any | |
3583 | reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but | |
3584 | now we are treating part of the operand as an input, so | |
3585 | we must change these to RELOAD_FOR_INPUT_ADDRESS. */ | |
3586 | ||
2d55b7e8 | 3587 | if (modified[i] == RELOAD_WRITE) |
47c8cf91 ILT |
3588 | { |
3589 | for (j = 0; j < n_reloads; j++) | |
3590 | { | |
3591 | if (reload_opnum[j] == i) | |
3592 | { | |
3593 | if (reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) | |
3594 | reload_when_needed[j] = RELOAD_FOR_INPUT_ADDRESS; | |
3595 | else if (reload_when_needed[j] | |
3596 | == RELOAD_FOR_OUTADDR_ADDRESS) | |
3597 | reload_when_needed[j] = RELOAD_FOR_INPADDR_ADDRESS; | |
3598 | } | |
3599 | } | |
3600 | } | |
eab89b90 RK |
3601 | } |
3602 | else if (goal_alternative_matched[i] == -1) | |
db3cf6fb MS |
3603 | operand_reloadnum[i] |
3604 | = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3605 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
3606 | (modified[i] != RELOAD_WRITE | |
3607 | ? recog_operand_loc[i] : 0), | |
3608 | modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, | |
3609 | (enum reg_class) goal_alternative[i], | |
3610 | (modified[i] == RELOAD_WRITE | |
3611 | ? VOIDmode : operand_mode[i]), | |
3612 | (modified[i] == RELOAD_READ | |
3613 | ? VOIDmode : operand_mode[i]), | |
3614 | (insn_code_number < 0 ? 0 | |
3615 | : insn_operand_strict_low[insn_code_number][i]), | |
3616 | 0, i, operand_type[i]); | |
eab89b90 RK |
3617 | /* In a matching pair of operands, one must be input only |
3618 | and the other must be output only. | |
3619 | Pass the input operand as IN and the other as OUT. */ | |
3620 | else if (modified[i] == RELOAD_READ | |
3621 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
3622 | { | |
3623 | operand_reloadnum[i] | |
3624 | = push_reload (recog_operand[i], | |
3625 | recog_operand[goal_alternative_matched[i]], | |
3626 | recog_operand_loc[i], | |
3627 | recog_operand_loc[goal_alternative_matched[i]], | |
3628 | (enum reg_class) goal_alternative[i], | |
3629 | operand_mode[i], | |
3630 | operand_mode[goal_alternative_matched[i]], | |
a8c9daeb | 3631 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3632 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
3633 | } | |
3634 | else if (modified[i] == RELOAD_WRITE | |
3635 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
3636 | { | |
3637 | operand_reloadnum[goal_alternative_matched[i]] | |
3638 | = push_reload (recog_operand[goal_alternative_matched[i]], | |
3639 | recog_operand[i], | |
3640 | recog_operand_loc[goal_alternative_matched[i]], | |
3641 | recog_operand_loc[i], | |
3642 | (enum reg_class) goal_alternative[i], | |
3643 | operand_mode[goal_alternative_matched[i]], | |
3644 | operand_mode[i], | |
a8c9daeb | 3645 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3646 | operand_reloadnum[i] = output_reloadnum; |
3647 | } | |
3648 | else if (insn_code_number >= 0) | |
3649 | abort (); | |
3650 | else | |
3651 | { | |
3652 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3653 | /* Avoid further trouble with this insn. */ | |
38a448ca | 3654 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 RK |
3655 | n_reloads = 0; |
3656 | return; | |
3657 | } | |
3658 | } | |
3659 | else if (goal_alternative_matched[i] < 0 | |
3660 | && goal_alternative_matches[i] < 0 | |
3661 | && optimize) | |
3662 | { | |
a8c9daeb | 3663 | /* For each non-matching operand that's a MEM or a pseudo-register |
eab89b90 RK |
3664 | that didn't get a hard register, make an optional reload. |
3665 | This may get done even if the insn needs no reloads otherwise. */ | |
a8c9daeb RK |
3666 | |
3667 | rtx operand = recog_operand[i]; | |
3668 | ||
eab89b90 RK |
3669 | while (GET_CODE (operand) == SUBREG) |
3670 | operand = XEXP (operand, 0); | |
a8c9daeb RK |
3671 | if ((GET_CODE (operand) == MEM |
3672 | || (GET_CODE (operand) == REG | |
3673 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
eab89b90 | 3674 | && (enum reg_class) goal_alternative[i] != NO_REGS |
a8c9daeb RK |
3675 | && ! no_input_reloads |
3676 | /* Optional output reloads don't do anything and we mustn't | |
3677 | make in-out reloads on insns that are not permitted output | |
3678 | reloads. */ | |
eab89b90 | 3679 | && (modified[i] == RELOAD_READ |
a8c9daeb | 3680 | || (modified[i] == RELOAD_READ_WRITE && ! no_output_reloads))) |
eab89b90 RK |
3681 | operand_reloadnum[i] |
3682 | = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3683 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
a8c9daeb RK |
3684 | (modified[i] != RELOAD_WRITE |
3685 | ? recog_operand_loc[i] : 0), | |
3686 | (modified[i] != RELOAD_READ | |
3687 | ? recog_operand_loc[i] : 0), | |
eab89b90 | 3688 | (enum reg_class) goal_alternative[i], |
a8c9daeb RK |
3689 | (modified[i] == RELOAD_WRITE |
3690 | ? VOIDmode : operand_mode[i]), | |
3691 | (modified[i] == RELOAD_READ | |
3692 | ? VOIDmode : operand_mode[i]), | |
eab89b90 RK |
3693 | (insn_code_number < 0 ? 0 |
3694 | : insn_operand_strict_low[insn_code_number][i]), | |
a8c9daeb | 3695 | 1, i, operand_type[i]); |
eab89b90 | 3696 | } |
a8c9daeb RK |
3697 | else if (goal_alternative_matches[i] >= 0 |
3698 | && goal_alternative_win[goal_alternative_matches[i]] | |
3699 | && modified[i] == RELOAD_READ | |
3700 | && modified[goal_alternative_matches[i]] == RELOAD_WRITE | |
3701 | && ! no_input_reloads && ! no_output_reloads | |
3702 | && optimize) | |
3703 | { | |
3704 | /* Similarly, make an optional reload for a pair of matching | |
3705 | objects that are in MEM or a pseudo that didn't get a hard reg. */ | |
eab89b90 | 3706 | |
a8c9daeb RK |
3707 | rtx operand = recog_operand[i]; |
3708 | ||
3709 | while (GET_CODE (operand) == SUBREG) | |
3710 | operand = XEXP (operand, 0); | |
3711 | if ((GET_CODE (operand) == MEM | |
3712 | || (GET_CODE (operand) == REG | |
3713 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
3714 | && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] | |
3715 | != NO_REGS)) | |
3716 | operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] | |
3717 | = push_reload (recog_operand[goal_alternative_matches[i]], | |
3718 | recog_operand[i], | |
3719 | recog_operand_loc[goal_alternative_matches[i]], | |
3720 | recog_operand_loc[i], | |
3721 | (enum reg_class) goal_alternative[goal_alternative_matches[i]], | |
3722 | operand_mode[goal_alternative_matches[i]], | |
3723 | operand_mode[i], | |
3724 | 0, 1, goal_alternative_matches[i], RELOAD_OTHER); | |
3725 | } | |
3726 | ||
eab89b90 RK |
3727 | /* If this insn pattern contains any MATCH_DUP's, make sure that |
3728 | they will be substituted if the operands they match are substituted. | |
3729 | Also do now any substitutions we already did on the operands. | |
3730 | ||
3731 | Don't do this if we aren't making replacements because we might be | |
3732 | propagating things allocated by frame pointer elimination into places | |
3733 | it doesn't expect. */ | |
3734 | ||
3735 | if (insn_code_number >= 0 && replace) | |
3736 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
3737 | { | |
3738 | int opno = recog_dup_num[i]; | |
3739 | *recog_dup_loc[i] = *recog_operand_loc[opno]; | |
3740 | if (operand_reloadnum[opno] >= 0) | |
3741 | push_replacement (recog_dup_loc[i], operand_reloadnum[opno], | |
3742 | insn_operand_mode[insn_code_number][opno]); | |
3743 | } | |
3744 | ||
3745 | #if 0 | |
3746 | /* This loses because reloading of prior insns can invalidate the equivalence | |
3747 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
3748 | causing this insn to need more reload regs than it needed before. | |
3749 | It may be too late to make the reload regs available. | |
3750 | Now this optimization is done safely in choose_reload_regs. */ | |
3751 | ||
3752 | /* For each reload of a reg into some other class of reg, | |
3753 | search for an existing equivalent reg (same value now) in the right class. | |
3754 | We can use it as long as we don't need to change its contents. */ | |
3755 | for (i = 0; i < n_reloads; i++) | |
3756 | if (reload_reg_rtx[i] == 0 | |
3757 | && reload_in[i] != 0 | |
3758 | && GET_CODE (reload_in[i]) == REG | |
3759 | && reload_out[i] == 0) | |
3760 | { | |
3761 | reload_reg_rtx[i] | |
3762 | = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1, | |
3763 | static_reload_reg_p, 0, reload_inmode[i]); | |
3764 | /* Prevent generation of insn to load the value | |
3765 | because the one we found already has the value. */ | |
3766 | if (reload_reg_rtx[i]) | |
3767 | reload_in[i] = reload_reg_rtx[i]; | |
3768 | } | |
3769 | #endif | |
3770 | ||
a8c9daeb RK |
3771 | /* Perhaps an output reload can be combined with another |
3772 | to reduce needs by one. */ | |
3773 | if (!goal_earlyclobber) | |
3774 | combine_reloads (); | |
3775 | ||
3776 | /* If we have a pair of reloads for parts of an address, they are reloading | |
3777 | the same object, the operands themselves were not reloaded, and they | |
3778 | are for two operands that are supposed to match, merge the reloads and | |
0f41302f | 3779 | change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ |
a8c9daeb RK |
3780 | |
3781 | for (i = 0; i < n_reloads; i++) | |
3782 | { | |
3783 | int k; | |
3784 | ||
3785 | for (j = i + 1; j < n_reloads; j++) | |
3786 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
47c8cf91 ILT |
3787 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS |
3788 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS | |
3789 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
a8c9daeb | 3790 | && (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS |
47c8cf91 ILT |
3791 | || reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS |
3792 | || reload_when_needed[j] == RELOAD_FOR_INPADDR_ADDRESS | |
3793 | || reload_when_needed[j] == RELOAD_FOR_OUTADDR_ADDRESS) | |
a8c9daeb RK |
3794 | && rtx_equal_p (reload_in[i], reload_in[j]) |
3795 | && (operand_reloadnum[reload_opnum[i]] < 0 | |
3796 | || reload_optional[operand_reloadnum[reload_opnum[i]]]) | |
3797 | && (operand_reloadnum[reload_opnum[j]] < 0 | |
3798 | || reload_optional[operand_reloadnum[reload_opnum[j]]]) | |
3799 | && (goal_alternative_matches[reload_opnum[i]] == reload_opnum[j] | |
3800 | || (goal_alternative_matches[reload_opnum[j]] | |
3801 | == reload_opnum[i]))) | |
3802 | { | |
3803 | for (k = 0; k < n_replacements; k++) | |
3804 | if (replacements[k].what == j) | |
3805 | replacements[k].what = i; | |
3806 | ||
47c8cf91 ILT |
3807 | if (reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS |
3808 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
3809 | reload_when_needed[i] = RELOAD_FOR_OPADDR_ADDR; | |
3810 | else | |
3811 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
a8c9daeb RK |
3812 | reload_in[j] = 0; |
3813 | } | |
3814 | } | |
3815 | ||
3816 | /* Scan all the reloads and update their type. | |
3817 | If a reload is for the address of an operand and we didn't reload | |
3818 | that operand, change the type. Similarly, change the operand number | |
3819 | of a reload when two operands match. If a reload is optional, treat it | |
3820 | as though the operand isn't reloaded. | |
3821 | ||
3822 | ??? This latter case is somewhat odd because if we do the optional | |
3823 | reload, it means the object is hanging around. Thus we need only | |
3824 | do the address reload if the optional reload was NOT done. | |
3825 | ||
3826 | Change secondary reloads to be the address type of their operand, not | |
3827 | the normal type. | |
3828 | ||
3829 | If an operand's reload is now RELOAD_OTHER, change any | |
3830 | RELOAD_FOR_INPUT_ADDRESS reloads of that operand to | |
3831 | RELOAD_FOR_OTHER_ADDRESS. */ | |
3832 | ||
3833 | for (i = 0; i < n_reloads; i++) | |
3834 | { | |
3835 | if (reload_secondary_p[i] | |
3836 | && reload_when_needed[i] == operand_type[reload_opnum[i]]) | |
3837 | reload_when_needed[i] = address_type[reload_opnum[i]]; | |
3838 | ||
3839 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
47c8cf91 ILT |
3840 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS |
3841 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS | |
3842 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
a8c9daeb | 3843 | && (operand_reloadnum[reload_opnum[i]] < 0 |
6ded3228 | 3844 | || reload_optional[operand_reloadnum[reload_opnum[i]]])) |
f98bb7d3 RK |
3845 | { |
3846 | /* If we have a secondary reload to go along with this reload, | |
0f41302f | 3847 | change its type to RELOAD_FOR_OPADDR_ADDR. */ |
f98bb7d3 | 3848 | |
47c8cf91 ILT |
3849 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS |
3850 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS) | |
f98bb7d3 RK |
3851 | && reload_secondary_in_reload[i] != -1) |
3852 | { | |
3853 | int secondary_in_reload = reload_secondary_in_reload[i]; | |
3854 | ||
db3cf6fb MS |
3855 | reload_when_needed[secondary_in_reload] |
3856 | = RELOAD_FOR_OPADDR_ADDR; | |
f98bb7d3 | 3857 | |
0f41302f | 3858 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 RK |
3859 | if (secondary_in_reload > 0 |
3860 | && reload_secondary_in_reload[secondary_in_reload] != -1) | |
3861 | reload_when_needed[reload_secondary_in_reload[secondary_in_reload]] | |
3862 | = RELOAD_FOR_OPADDR_ADDR; | |
3863 | } | |
3864 | ||
47c8cf91 ILT |
3865 | if ((reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS |
3866 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
f98bb7d3 RK |
3867 | && reload_secondary_out_reload[i] != -1) |
3868 | { | |
3869 | int secondary_out_reload = reload_secondary_out_reload[i]; | |
3870 | ||
db3cf6fb MS |
3871 | reload_when_needed[secondary_out_reload] |
3872 | = RELOAD_FOR_OPADDR_ADDR; | |
f98bb7d3 | 3873 | |
0f41302f | 3874 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 RK |
3875 | if (secondary_out_reload |
3876 | && reload_secondary_out_reload[secondary_out_reload] != -1) | |
3877 | reload_when_needed[reload_secondary_out_reload[secondary_out_reload]] | |
3878 | = RELOAD_FOR_OPADDR_ADDR; | |
3879 | } | |
47c8cf91 ILT |
3880 | if (reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS |
3881 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
3882 | reload_when_needed[i] = RELOAD_FOR_OPADDR_ADDR; | |
3883 | else | |
3884 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
f98bb7d3 | 3885 | } |
a8c9daeb | 3886 | |
47c8cf91 ILT |
3887 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS |
3888 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS) | |
a8c9daeb RK |
3889 | && operand_reloadnum[reload_opnum[i]] >= 0 |
3890 | && (reload_when_needed[operand_reloadnum[reload_opnum[i]]] | |
3891 | == RELOAD_OTHER)) | |
3892 | reload_when_needed[i] = RELOAD_FOR_OTHER_ADDRESS; | |
3893 | ||
3894 | if (goal_alternative_matches[reload_opnum[i]] >= 0) | |
3895 | reload_opnum[i] = goal_alternative_matches[reload_opnum[i]]; | |
3896 | } | |
3897 | ||
a94ce333 JW |
3898 | /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads. |
3899 | If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR | |
3900 | reloads to RELOAD_FOR_OPERAND_ADDRESS reloads. | |
3901 | ||
3902 | choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never | |
3903 | conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a | |
3904 | single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads. | |
3905 | However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload, | |
3906 | then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all | |
3907 | RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it. | |
3908 | This is complicated by the fact that a single operand can have more | |
3909 | than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix | |
3910 | choose_reload_regs without affecting code quality, and cases that | |
3911 | actually fail are extremely rare, so it turns out to be better to fix | |
3912 | the problem here by not generating cases that choose_reload_regs will | |
3913 | fail for. */ | |
3914 | ||
3915 | { | |
3916 | int op_addr_reloads = 0; | |
3917 | for (i = 0; i < n_reloads; i++) | |
3918 | if (reload_when_needed[i] == RELOAD_FOR_OPERAND_ADDRESS) | |
3919 | op_addr_reloads++; | |
3920 | ||
3921 | if (op_addr_reloads > 1) | |
3922 | for (i = 0; i < n_reloads; i++) | |
3923 | if (reload_when_needed[i] == RELOAD_FOR_OPADDR_ADDR) | |
3924 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
3925 | } | |
3926 | ||
a8c9daeb RK |
3927 | /* See if we have any reloads that are now allowed to be merged |
3928 | because we've changed when the reload is needed to | |
3929 | RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only | |
3930 | check for the most common cases. */ | |
3931 | ||
3932 | for (i = 0; i < n_reloads; i++) | |
3933 | if (reload_in[i] != 0 && reload_out[i] == 0 | |
3934 | && (reload_when_needed[i] == RELOAD_FOR_OPERAND_ADDRESS | |
47c8cf91 | 3935 | || reload_when_needed[i] == RELOAD_FOR_OPADDR_ADDR |
a8c9daeb RK |
3936 | || reload_when_needed[i] == RELOAD_FOR_OTHER_ADDRESS)) |
3937 | for (j = 0; j < n_reloads; j++) | |
3938 | if (i != j && reload_in[j] != 0 && reload_out[j] == 0 | |
3939 | && reload_when_needed[j] == reload_when_needed[i] | |
73f67895 RS |
3940 | && MATCHES (reload_in[i], reload_in[j]) |
3941 | && reload_reg_class[i] == reload_reg_class[j] | |
92b37691 RK |
3942 | && !reload_nocombine[i] && !reload_nocombine[j] |
3943 | && reload_reg_rtx[i] == reload_reg_rtx[j]) | |
a8c9daeb RK |
3944 | { |
3945 | reload_opnum[i] = MIN (reload_opnum[i], reload_opnum[j]); | |
3946 | transfer_replacements (i, j); | |
3947 | reload_in[j] = 0; | |
3948 | } | |
3949 | ||
eab89b90 RK |
3950 | #else /* no REGISTER_CONSTRAINTS */ |
3951 | int noperands; | |
3952 | int insn_code_number; | |
3953 | int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */ | |
3954 | register int i; | |
3955 | rtx body = PATTERN (insn); | |
3956 | ||
3957 | n_reloads = 0; | |
3958 | n_replacements = 0; | |
3959 | n_earlyclobbers = 0; | |
3960 | replace_reloads = replace; | |
3961 | this_insn = insn; | |
3962 | ||
3963 | /* Find what kind of insn this is. NOPERANDS gets number of operands. | |
3964 | Store the operand values in RECOG_OPERAND and the locations | |
3965 | of the words in the insn that point to them in RECOG_OPERAND_LOC. | |
3966 | Return if the insn needs no reload processing. */ | |
3967 | ||
3968 | switch (GET_CODE (body)) | |
3969 | { | |
3970 | case USE: | |
3971 | case CLOBBER: | |
3972 | case ASM_INPUT: | |
3973 | case ADDR_VEC: | |
3974 | case ADDR_DIFF_VEC: | |
3975 | return; | |
3976 | ||
3977 | case PARALLEL: | |
3978 | case SET: | |
3979 | noperands = asm_noperands (body); | |
3980 | if (noperands >= 0) | |
3981 | { | |
3982 | /* This insn is an `asm' with operands. | |
3983 | First, find out how many operands, and allocate space. */ | |
3984 | ||
3985 | insn_code_number = -1; | |
3986 | /* ??? This is a bug! ??? | |
3987 | Give up and delete this insn if it has too many operands. */ | |
3988 | if (noperands > MAX_RECOG_OPERANDS) | |
3989 | abort (); | |
3990 | ||
3991 | /* Now get the operand values out of the insn. */ | |
3992 | ||
fb3821f7 CH |
3993 | decode_asm_operands (body, recog_operand, recog_operand_loc, |
3994 | NULL_PTR, NULL_PTR); | |
eab89b90 RK |
3995 | break; |
3996 | } | |
3997 | ||
3998 | default: | |
3999 | /* Ordinary insn: recognize it, allocate space for operands and | |
4000 | constraints, and get them out via insn_extract. */ | |
4001 | ||
4002 | insn_code_number = recog_memoized (insn); | |
4003 | noperands = insn_n_operands[insn_code_number]; | |
4004 | insn_extract (insn); | |
4005 | } | |
4006 | ||
4007 | if (noperands == 0) | |
4008 | return; | |
4009 | ||
4010 | for (i = 0; i < noperands; i++) | |
4011 | { | |
4012 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
4013 | int is_set_dest = GET_CODE (body) == SET && (i == 0); | |
4014 | ||
4015 | if (insn_code_number >= 0) | |
4016 | if (insn_operand_address_p[insn_code_number][i]) | |
fb3821f7 | 4017 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 | 4018 | recog_operand[i], recog_operand_loc[i], |
55c22565 | 4019 | i, RELOAD_FOR_INPUT, ind_levels, insn); |
a8c9daeb RK |
4020 | |
4021 | /* In these cases, we can't tell if the operand is an input | |
4022 | or an output, so be conservative. In practice it won't be | |
4023 | problem. */ | |
4024 | ||
eab89b90 RK |
4025 | if (code == MEM) |
4026 | find_reloads_address (GET_MODE (recog_operand[i]), | |
4027 | recog_operand_loc[i], | |
4028 | XEXP (recog_operand[i], 0), | |
4029 | &XEXP (recog_operand[i], 0), | |
55c22565 | 4030 | i, RELOAD_OTHER, ind_levels, insn); |
eab89b90 RK |
4031 | if (code == SUBREG) |
4032 | recog_operand[i] = *recog_operand_loc[i] | |
a8c9daeb RK |
4033 | = find_reloads_toplev (recog_operand[i], i, RELOAD_OTHER, |
4034 | ind_levels, is_set_dest); | |
eab89b90 RK |
4035 | if (code == REG) |
4036 | { | |
4037 | register int regno = REGNO (recog_operand[i]); | |
4038 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
4039 | recog_operand[i] = *recog_operand_loc[i] | |
4040 | = reg_equiv_constant[regno]; | |
4041 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
4042 | that feeds this insn. */ | |
4043 | if (reg_equiv_mem[regno] != 0) | |
4044 | recog_operand[i] = *recog_operand_loc[i] | |
4045 | = reg_equiv_mem[regno]; | |
4046 | #endif | |
4047 | } | |
eab89b90 RK |
4048 | } |
4049 | ||
4050 | /* Perhaps an output reload can be combined with another | |
4051 | to reduce needs by one. */ | |
4052 | if (!goal_earlyclobber) | |
4053 | combine_reloads (); | |
a8c9daeb | 4054 | #endif /* no REGISTER_CONSTRAINTS */ |
eab89b90 RK |
4055 | } |
4056 | ||
4057 | /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT | |
4058 | accepts a memory operand with constant address. */ | |
4059 | ||
4060 | static int | |
4061 | alternative_allows_memconst (constraint, altnum) | |
4062 | char *constraint; | |
4063 | int altnum; | |
4064 | { | |
4065 | register int c; | |
4066 | /* Skip alternatives before the one requested. */ | |
4067 | while (altnum > 0) | |
4068 | { | |
4069 | while (*constraint++ != ','); | |
4070 | altnum--; | |
4071 | } | |
4072 | /* Scan the requested alternative for 'm' or 'o'. | |
4073 | If one of them is present, this alternative accepts memory constants. */ | |
4074 | while ((c = *constraint++) && c != ',' && c != '#') | |
4075 | if (c == 'm' || c == 'o') | |
4076 | return 1; | |
4077 | return 0; | |
4078 | } | |
4079 | \f | |
4080 | /* Scan X for memory references and scan the addresses for reloading. | |
4081 | Also checks for references to "constant" regs that we want to eliminate | |
4082 | and replaces them with the values they stand for. | |
6dc42e49 | 4083 | We may alter X destructively if it contains a reference to such. |
eab89b90 RK |
4084 | If X is just a constant reg, we return the equivalent value |
4085 | instead of X. | |
4086 | ||
4087 | IND_LEVELS says how many levels of indirect addressing this machine | |
4088 | supports. | |
4089 | ||
a8c9daeb RK |
4090 | OPNUM and TYPE identify the purpose of the reload. |
4091 | ||
eab89b90 RK |
4092 | IS_SET_DEST is true if X is the destination of a SET, which is not |
4093 | appropriate to be replaced by a constant. */ | |
4094 | ||
4095 | static rtx | |
a8c9daeb | 4096 | find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest) |
eab89b90 | 4097 | rtx x; |
a8c9daeb RK |
4098 | int opnum; |
4099 | enum reload_type type; | |
eab89b90 RK |
4100 | int ind_levels; |
4101 | int is_set_dest; | |
4102 | { | |
4103 | register RTX_CODE code = GET_CODE (x); | |
4104 | ||
4105 | register char *fmt = GET_RTX_FORMAT (code); | |
4106 | register int i; | |
4107 | ||
4108 | if (code == REG) | |
4109 | { | |
4110 | /* This code is duplicated for speed in find_reloads. */ | |
4111 | register int regno = REGNO (x); | |
4112 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
4113 | x = reg_equiv_constant[regno]; | |
4114 | #if 0 | |
4115 | /* This creates (subreg (mem...)) which would cause an unnecessary | |
4116 | reload of the mem. */ | |
4117 | else if (reg_equiv_mem[regno] != 0) | |
4118 | x = reg_equiv_mem[regno]; | |
4119 | #endif | |
4120 | else if (reg_equiv_address[regno] != 0) | |
4121 | { | |
4122 | /* If reg_equiv_address varies, it may be shared, so copy it. */ | |
4ffeab02 JW |
4123 | /* We must rerun eliminate_regs, in case the elimination |
4124 | offsets have changed. */ | |
4125 | rtx addr = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, | |
1914f5da | 4126 | NULL_RTX), |
4ffeab02 | 4127 | 0); |
eab89b90 RK |
4128 | |
4129 | if (rtx_varies_p (addr)) | |
4130 | addr = copy_rtx (addr); | |
4131 | ||
38a448ca | 4132 | x = gen_rtx_MEM (GET_MODE (x), addr); |
eab89b90 | 4133 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); |
fb3821f7 | 4134 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 | 4135 | XEXP (x, 0), |
55c22565 | 4136 | &XEXP (x, 0), opnum, type, ind_levels, 0); |
eab89b90 RK |
4137 | } |
4138 | return x; | |
4139 | } | |
4140 | if (code == MEM) | |
4141 | { | |
4142 | rtx tem = x; | |
4143 | find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 4144 | opnum, type, ind_levels, 0); |
eab89b90 RK |
4145 | return tem; |
4146 | } | |
4147 | ||
4148 | if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG) | |
4149 | { | |
4150 | /* Check for SUBREG containing a REG that's equivalent to a constant. | |
4151 | If the constant has a known value, truncate it right now. | |
4152 | Similarly if we are extracting a single-word of a multi-word | |
4153 | constant. If the constant is symbolic, allow it to be substituted | |
4154 | normally. push_reload will strip the subreg later. If the | |
4155 | constant is VOIDmode, abort because we will lose the mode of | |
4156 | the register (this should never happen because one of the cases | |
4157 | above should handle it). */ | |
4158 | ||
4159 | register int regno = REGNO (SUBREG_REG (x)); | |
4160 | rtx tem; | |
4161 | ||
4162 | if (subreg_lowpart_p (x) | |
4163 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4164 | && reg_equiv_constant[regno] != 0 | |
4165 | && (tem = gen_lowpart_common (GET_MODE (x), | |
4166 | reg_equiv_constant[regno])) != 0) | |
4167 | return tem; | |
4168 | ||
4169 | if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD | |
4170 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4171 | && reg_equiv_constant[regno] != 0 | |
4172 | && (tem = operand_subword (reg_equiv_constant[regno], | |
4173 | SUBREG_WORD (x), 0, | |
4174 | GET_MODE (SUBREG_REG (x)))) != 0) | |
4175 | return tem; | |
4176 | ||
2fd0af53 R |
4177 | /* If the SUBREG is wider than a word, the above test will fail. |
4178 | For example, we might have a SImode SUBREG of a DImode SUBREG_REG | |
4179 | for a 16 bit target, or a DImode SUBREG of a TImode SUBREG_REG for | |
4180 | a 32 bit target. We still can - and have to - handle this | |
4181 | for non-paradoxical subregs of CONST_INTs. */ | |
4182 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4183 | && reg_equiv_constant[regno] != 0 | |
4184 | && GET_CODE (reg_equiv_constant[regno]) == CONST_INT | |
4185 | && (GET_MODE_SIZE (GET_MODE (x)) | |
4186 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
4187 | { | |
4188 | int shift = SUBREG_WORD (x) * BITS_PER_WORD; | |
4189 | if (WORDS_BIG_ENDIAN) | |
4190 | shift = (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) | |
4191 | - GET_MODE_BITSIZE (GET_MODE (x)) | |
4192 | - shift); | |
4193 | /* Here we use the knowledge that CONST_INTs have a | |
4194 | HOST_WIDE_INT field. */ | |
4195 | if (shift >= HOST_BITS_PER_WIDE_INT) | |
4196 | shift = HOST_BITS_PER_WIDE_INT - 1; | |
4197 | return GEN_INT (INTVAL (reg_equiv_constant[regno]) >> shift); | |
4198 | } | |
4199 | ||
eab89b90 RK |
4200 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 |
4201 | && reg_equiv_constant[regno] != 0 | |
4202 | && GET_MODE (reg_equiv_constant[regno]) == VOIDmode) | |
4203 | abort (); | |
4204 | ||
4205 | /* If the subreg contains a reg that will be converted to a mem, | |
4206 | convert the subreg to a narrower memref now. | |
4207 | Otherwise, we would get (subreg (mem ...) ...), | |
4208 | which would force reload of the mem. | |
4209 | ||
4210 | We also need to do this if there is an equivalent MEM that is | |
4211 | not offsettable. In that case, alter_subreg would produce an | |
4212 | invalid address on big-endian machines. | |
4213 | ||
46da6b3a | 4214 | For machines that extend byte loads, we must not reload using |
eab89b90 RK |
4215 | a wider mode if we have a paradoxical SUBREG. find_reloads will |
4216 | force a reload in that case. So we should not do anything here. */ | |
4217 | ||
4218 | else if (regno >= FIRST_PSEUDO_REGISTER | |
fd72420f | 4219 | #ifdef LOAD_EXTEND_OP |
eab89b90 RK |
4220 | && (GET_MODE_SIZE (GET_MODE (x)) |
4221 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
4222 | #endif | |
4223 | && (reg_equiv_address[regno] != 0 | |
4224 | || (reg_equiv_mem[regno] != 0 | |
f2fbfe92 JL |
4225 | && (! strict_memory_address_p (GET_MODE (x), |
4226 | XEXP (reg_equiv_mem[regno], 0)) | |
4227 | || ! offsettable_memref_p (reg_equiv_mem[regno]))))) | |
eab89b90 RK |
4228 | { |
4229 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
4ffeab02 JW |
4230 | /* We must rerun eliminate_regs, in case the elimination |
4231 | offsets have changed. */ | |
4232 | rtx addr = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, | |
1914f5da | 4233 | NULL_RTX), |
4ffeab02 | 4234 | 0); |
f76b9db2 ILT |
4235 | if (BYTES_BIG_ENDIAN) |
4236 | { | |
4237 | int size; | |
4238 | size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
4239 | offset += MIN (size, UNITS_PER_WORD); | |
4240 | size = GET_MODE_SIZE (GET_MODE (x)); | |
4241 | offset -= MIN (size, UNITS_PER_WORD); | |
4242 | } | |
eab89b90 | 4243 | addr = plus_constant (addr, offset); |
38a448ca | 4244 | x = gen_rtx_MEM (GET_MODE (x), addr); |
eab89b90 | 4245 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); |
fb3821f7 | 4246 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 | 4247 | XEXP (x, 0), |
55c22565 | 4248 | &XEXP (x, 0), opnum, type, ind_levels, 0); |
eab89b90 RK |
4249 | } |
4250 | ||
4251 | } | |
4252 | ||
4253 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4254 | { | |
4255 | if (fmt[i] == 'e') | |
a8c9daeb | 4256 | XEXP (x, i) = find_reloads_toplev (XEXP (x, i), opnum, type, |
eab89b90 RK |
4257 | ind_levels, is_set_dest); |
4258 | } | |
4259 | return x; | |
4260 | } | |
4261 | ||
dbf85761 RS |
4262 | /* Return a mem ref for the memory equivalent of reg REGNO. |
4263 | This mem ref is not shared with anything. */ | |
4264 | ||
eab89b90 RK |
4265 | static rtx |
4266 | make_memloc (ad, regno) | |
4267 | rtx ad; | |
4268 | int regno; | |
4269 | { | |
29a82058 | 4270 | #if 0 |
eab89b90 | 4271 | register int i; |
29a82058 | 4272 | #endif |
4ffeab02 JW |
4273 | /* We must rerun eliminate_regs, in case the elimination |
4274 | offsets have changed. */ | |
1914f5da | 4275 | rtx tem = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, NULL_RTX), 0); |
dbf85761 RS |
4276 | |
4277 | #if 0 /* We cannot safely reuse a memloc made here; | |
4278 | if the pseudo appears twice, and its mem needs a reload, | |
4279 | it gets two separate reloads assigned, but it only | |
4280 | gets substituted with the second of them; | |
4281 | then it can get used before that reload reg gets loaded up. */ | |
eab89b90 RK |
4282 | for (i = 0; i < n_memlocs; i++) |
4283 | if (rtx_equal_p (tem, XEXP (memlocs[i], 0))) | |
4284 | return memlocs[i]; | |
dbf85761 | 4285 | #endif |
eab89b90 RK |
4286 | |
4287 | /* If TEM might contain a pseudo, we must copy it to avoid | |
4288 | modifying it when we do the substitution for the reload. */ | |
4289 | if (rtx_varies_p (tem)) | |
4290 | tem = copy_rtx (tem); | |
4291 | ||
38a448ca | 4292 | tem = gen_rtx_MEM (GET_MODE (ad), tem); |
eab89b90 RK |
4293 | RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); |
4294 | memlocs[n_memlocs++] = tem; | |
4295 | return tem; | |
4296 | } | |
4297 | ||
4298 | /* Record all reloads needed for handling memory address AD | |
4299 | which appears in *LOC in a memory reference to mode MODE | |
4300 | which itself is found in location *MEMREFLOC. | |
4301 | Note that we take shortcuts assuming that no multi-reg machine mode | |
4302 | occurs as part of an address. | |
4303 | ||
a8c9daeb | 4304 | OPNUM and TYPE specify the purpose of this reload. |
eab89b90 RK |
4305 | |
4306 | IND_LEVELS says how many levels of indirect addressing this machine | |
4307 | supports. | |
4308 | ||
55c22565 RK |
4309 | INSN, if nonzero, is the insn in which we do the reload. It is used |
4310 | to determine if we may generate output reloads. | |
4311 | ||
eab89b90 RK |
4312 | Value is nonzero if this address is reloaded or replaced as a whole. |
4313 | This is interesting to the caller if the address is an autoincrement. | |
4314 | ||
4315 | Note that there is no verification that the address will be valid after | |
4316 | this routine does its work. Instead, we rely on the fact that the address | |
4317 | was valid when reload started. So we need only undo things that reload | |
4318 | could have broken. These are wrong register types, pseudos not allocated | |
4319 | to a hard register, and frame pointer elimination. */ | |
4320 | ||
4321 | static int | |
55c22565 | 4322 | find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels, insn) |
eab89b90 RK |
4323 | enum machine_mode mode; |
4324 | rtx *memrefloc; | |
4325 | rtx ad; | |
4326 | rtx *loc; | |
a8c9daeb RK |
4327 | int opnum; |
4328 | enum reload_type type; | |
eab89b90 | 4329 | int ind_levels; |
55c22565 | 4330 | rtx insn; |
eab89b90 RK |
4331 | { |
4332 | register int regno; | |
4333 | rtx tem; | |
4334 | ||
4335 | /* If the address is a register, see if it is a legitimate address and | |
4336 | reload if not. We first handle the cases where we need not reload | |
4337 | or where we must reload in a non-standard way. */ | |
4338 | ||
4339 | if (GET_CODE (ad) == REG) | |
4340 | { | |
4341 | regno = REGNO (ad); | |
4342 | ||
4343 | if (reg_equiv_constant[regno] != 0 | |
4344 | && strict_memory_address_p (mode, reg_equiv_constant[regno])) | |
4345 | { | |
4346 | *loc = ad = reg_equiv_constant[regno]; | |
4347 | return 1; | |
4348 | } | |
4349 | ||
4350 | else if (reg_equiv_address[regno] != 0) | |
4351 | { | |
4352 | tem = make_memloc (ad, regno); | |
fb3821f7 | 4353 | find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0), |
47c8cf91 | 4354 | &XEXP (tem, 0), opnum, ADDR_TYPE (type), |
55c22565 | 4355 | ind_levels, insn); |
1ba61f4e ILT |
4356 | push_reload (tem, NULL_RTX, loc, NULL_PTR, |
4357 | reload_address_base_reg_class, | |
eab89b90 | 4358 | GET_MODE (ad), VOIDmode, 0, 0, |
a8c9daeb | 4359 | opnum, type); |
eab89b90 RK |
4360 | return 1; |
4361 | } | |
4362 | ||
b39555b4 | 4363 | /* We can avoid a reload if the register's equivalent memory expression |
c1875d66 RS |
4364 | is valid as an indirect memory address. |
4365 | But not all addresses are valid in a mem used as an indirect address: | |
4366 | only reg or reg+constant. */ | |
b39555b4 RS |
4367 | |
4368 | else if (reg_equiv_mem[regno] != 0 && ind_levels > 0 | |
c1875d66 RS |
4369 | && strict_memory_address_p (mode, reg_equiv_mem[regno]) |
4370 | && (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == REG | |
4371 | || (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == PLUS | |
4372 | && GET_CODE (XEXP (XEXP (reg_equiv_mem[regno], 0), 0)) == REG | |
75301d68 | 4373 | && CONSTANT_P (XEXP (XEXP (reg_equiv_mem[regno], 0), 1))))) |
b39555b4 | 4374 | return 0; |
eab89b90 RK |
4375 | |
4376 | /* The only remaining case where we can avoid a reload is if this is a | |
4377 | hard register that is valid as a base register and which is not the | |
4378 | subject of a CLOBBER in this insn. */ | |
4379 | ||
858c3c8c ILT |
4380 | else if (regno < FIRST_PSEUDO_REGISTER |
4381 | && REGNO_MODE_OK_FOR_BASE_P (regno, mode) | |
eab89b90 RK |
4382 | && ! regno_clobbered_p (regno, this_insn)) |
4383 | return 0; | |
4384 | ||
4385 | /* If we do not have one of the cases above, we must do the reload. */ | |
1ba61f4e | 4386 | push_reload (ad, NULL_RTX, loc, NULL_PTR, reload_address_base_reg_class, |
a8c9daeb | 4387 | GET_MODE (ad), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4388 | return 1; |
4389 | } | |
4390 | ||
4391 | if (strict_memory_address_p (mode, ad)) | |
4392 | { | |
4393 | /* The address appears valid, so reloads are not needed. | |
4394 | But the address may contain an eliminable register. | |
4395 | This can happen because a machine with indirect addressing | |
4396 | may consider a pseudo register by itself a valid address even when | |
4397 | it has failed to get a hard reg. | |
4398 | So do a tree-walk to find and eliminate all such regs. */ | |
4399 | ||
4400 | /* But first quickly dispose of a common case. */ | |
4401 | if (GET_CODE (ad) == PLUS | |
4402 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4403 | && GET_CODE (XEXP (ad, 0)) == REG | |
4404 | && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) | |
4405 | return 0; | |
4406 | ||
4407 | subst_reg_equivs_changed = 0; | |
4408 | *loc = subst_reg_equivs (ad); | |
4409 | ||
4410 | if (! subst_reg_equivs_changed) | |
4411 | return 0; | |
4412 | ||
4413 | /* Check result for validity after substitution. */ | |
4414 | if (strict_memory_address_p (mode, ad)) | |
4415 | return 0; | |
4416 | } | |
4417 | ||
4418 | /* The address is not valid. We have to figure out why. One possibility | |
4419 | is that it is itself a MEM. This can happen when the frame pointer is | |
4420 | being eliminated, a pseudo is not allocated to a hard register, and the | |
4421 | offset between the frame and stack pointers is not its initial value. | |
d45cf215 | 4422 | In that case the pseudo will have been replaced by a MEM referring to |
eab89b90 RK |
4423 | the stack pointer. */ |
4424 | if (GET_CODE (ad) == MEM) | |
4425 | { | |
4426 | /* First ensure that the address in this MEM is valid. Then, unless | |
4427 | indirect addresses are valid, reload the MEM into a register. */ | |
4428 | tem = ad; | |
4429 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
47c8cf91 | 4430 | opnum, ADDR_TYPE (type), |
55c22565 | 4431 | ind_levels == 0 ? 0 : ind_levels - 1, insn); |
d2555454 RS |
4432 | |
4433 | /* If tem was changed, then we must create a new memory reference to | |
4434 | hold it and store it back into memrefloc. */ | |
4435 | if (tem != ad && memrefloc) | |
ca3e4a2f | 4436 | { |
ca3e4a2f | 4437 | *memrefloc = copy_rtx (*memrefloc); |
3c80f7ed | 4438 | copy_replacements (tem, XEXP (*memrefloc, 0)); |
ca3e4a2f | 4439 | loc = &XEXP (*memrefloc, 0); |
ca3e4a2f | 4440 | } |
d2555454 | 4441 | |
eab89b90 RK |
4442 | /* Check similar cases as for indirect addresses as above except |
4443 | that we can allow pseudos and a MEM since they should have been | |
4444 | taken care of above. */ | |
4445 | ||
4446 | if (ind_levels == 0 | |
4447 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
4448 | || GET_CODE (XEXP (tem, 0)) == MEM | |
4449 | || ! (GET_CODE (XEXP (tem, 0)) == REG | |
4450 | || (GET_CODE (XEXP (tem, 0)) == PLUS | |
4451 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG | |
4452 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) | |
4453 | { | |
4454 | /* Must use TEM here, not AD, since it is the one that will | |
4455 | have any subexpressions reloaded, if needed. */ | |
fb3821f7 | 4456 | push_reload (tem, NULL_RTX, loc, NULL_PTR, |
1ba61f4e ILT |
4457 | reload_address_base_reg_class, GET_MODE (tem), |
4458 | VOIDmode, 0, | |
a8c9daeb | 4459 | 0, opnum, type); |
eab89b90 RK |
4460 | return 1; |
4461 | } | |
4462 | else | |
4463 | return 0; | |
4464 | } | |
4465 | ||
1b4d2764 RK |
4466 | /* If we have address of a stack slot but it's not valid because the |
4467 | displacement is too large, compute the sum in a register. | |
4468 | Handle all base registers here, not just fp/ap/sp, because on some | |
4469 | targets (namely SH) we can also get too large displacements from | |
4470 | big-endian corrections. */ | |
eab89b90 | 4471 | else if (GET_CODE (ad) == PLUS |
1b4d2764 RK |
4472 | && GET_CODE (XEXP (ad, 0)) == REG |
4473 | && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER | |
858c3c8c | 4474 | && REG_MODE_OK_FOR_BASE_P (XEXP (ad, 0), mode) |
eab89b90 RK |
4475 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) |
4476 | { | |
4477 | /* Unshare the MEM rtx so we can safely alter it. */ | |
4478 | if (memrefloc) | |
4479 | { | |
eab89b90 RK |
4480 | *memrefloc = copy_rtx (*memrefloc); |
4481 | loc = &XEXP (*memrefloc, 0); | |
eab89b90 RK |
4482 | } |
4483 | if (double_reg_address_ok) | |
4484 | { | |
4485 | /* Unshare the sum as well. */ | |
4486 | *loc = ad = copy_rtx (ad); | |
4487 | /* Reload the displacement into an index reg. | |
4488 | We assume the frame pointer or arg pointer is a base reg. */ | |
4489 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
1ba61f4e ILT |
4490 | reload_address_index_reg_class, |
4491 | GET_MODE (ad), opnum, type, ind_levels); | |
eab89b90 RK |
4492 | } |
4493 | else | |
4494 | { | |
4495 | /* If the sum of two regs is not necessarily valid, | |
4496 | reload the sum into a base reg. | |
4497 | That will at least work. */ | |
1ba61f4e ILT |
4498 | find_reloads_address_part (ad, loc, reload_address_base_reg_class, |
4499 | Pmode, opnum, type, ind_levels); | |
eab89b90 RK |
4500 | } |
4501 | return 1; | |
4502 | } | |
4503 | ||
4504 | /* If we have an indexed stack slot, there are three possible reasons why | |
4505 | it might be invalid: The index might need to be reloaded, the address | |
4506 | might have been made by frame pointer elimination and hence have a | |
f302eea3 | 4507 | constant out of range, or both reasons might apply. |
eab89b90 RK |
4508 | |
4509 | We can easily check for an index needing reload, but even if that is the | |
4510 | case, we might also have an invalid constant. To avoid making the | |
4511 | conservative assumption and requiring two reloads, we see if this address | |
4512 | is valid when not interpreted strictly. If it is, the only problem is | |
4513 | that the index needs a reload and find_reloads_address_1 will take care | |
4514 | of it. | |
4515 | ||
4516 | There is still a case when we might generate an extra reload, | |
4517 | however. In certain cases eliminate_regs will return a MEM for a REG | |
4518 | (see the code there for details). In those cases, memory_address_p | |
4519 | applied to our address will return 0 so we will think that our offset | |
4520 | must be too large. But it might indeed be valid and the only problem | |
4521 | is that a MEM is present where a REG should be. This case should be | |
4522 | very rare and there doesn't seem to be any way to avoid it. | |
4523 | ||
4524 | If we decide to do something here, it must be that | |
4525 | `double_reg_address_ok' is true and that this address rtl was made by | |
4526 | eliminate_regs. We generate a reload of the fp/sp/ap + constant and | |
4527 | rework the sum so that the reload register will be added to the index. | |
4528 | This is safe because we know the address isn't shared. | |
4529 | ||
4530 | We check for fp/ap/sp as both the first and second operand of the | |
4531 | innermost PLUS. */ | |
4532 | ||
4533 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
f302eea3 | 4534 | && GET_CODE (XEXP (ad, 0)) == PLUS |
eab89b90 | 4535 | && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx |
a36d4c62 DE |
4536 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
4537 | || XEXP (XEXP (ad, 0), 0) == hard_frame_pointer_rtx | |
4538 | #endif | |
eab89b90 RK |
4539 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
4540 | || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx | |
4541 | #endif | |
4542 | || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx) | |
4543 | && ! memory_address_p (mode, ad)) | |
4544 | { | |
38a448ca RH |
4545 | *loc = ad = gen_rtx_PLUS (GET_MODE (ad), |
4546 | plus_constant (XEXP (XEXP (ad, 0), 0), | |
4547 | INTVAL (XEXP (ad, 1))), | |
eab89b90 | 4548 | XEXP (XEXP (ad, 0), 1)); |
1ba61f4e ILT |
4549 | find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), |
4550 | reload_address_base_reg_class, | |
a8c9daeb | 4551 | GET_MODE (ad), opnum, type, ind_levels); |
858c3c8c | 4552 | find_reloads_address_1 (mode, XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, |
55c22565 | 4553 | type, 0, insn); |
eab89b90 RK |
4554 | |
4555 | return 1; | |
4556 | } | |
4557 | ||
4558 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4559 | && GET_CODE (XEXP (ad, 0)) == PLUS | |
4560 | && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx | |
a36d4c62 DE |
4561 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
4562 | || XEXP (XEXP (ad, 0), 1) == hard_frame_pointer_rtx | |
4563 | #endif | |
eab89b90 RK |
4564 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
4565 | || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx | |
4566 | #endif | |
4567 | || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx) | |
4568 | && ! memory_address_p (mode, ad)) | |
4569 | { | |
38a448ca RH |
4570 | *loc = ad = gen_rtx_PLUS (GET_MODE (ad), |
4571 | XEXP (XEXP (ad, 0), 0), | |
4572 | plus_constant (XEXP (XEXP (ad, 0), 1), | |
4573 | INTVAL (XEXP (ad, 1)))); | |
1ba61f4e ILT |
4574 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), |
4575 | reload_address_base_reg_class, | |
a8c9daeb | 4576 | GET_MODE (ad), opnum, type, ind_levels); |
858c3c8c | 4577 | find_reloads_address_1 (mode, XEXP (ad, 0), 1, &XEXP (ad, 0), opnum, |
55c22565 | 4578 | type, 0, insn); |
eab89b90 RK |
4579 | |
4580 | return 1; | |
4581 | } | |
4582 | ||
4583 | /* See if address becomes valid when an eliminable register | |
4584 | in a sum is replaced. */ | |
4585 | ||
4586 | tem = ad; | |
4587 | if (GET_CODE (ad) == PLUS) | |
4588 | tem = subst_indexed_address (ad); | |
4589 | if (tem != ad && strict_memory_address_p (mode, tem)) | |
4590 | { | |
4591 | /* Ok, we win that way. Replace any additional eliminable | |
4592 | registers. */ | |
4593 | ||
4594 | subst_reg_equivs_changed = 0; | |
4595 | tem = subst_reg_equivs (tem); | |
4596 | ||
4597 | /* Make sure that didn't make the address invalid again. */ | |
4598 | ||
4599 | if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) | |
4600 | { | |
4601 | *loc = tem; | |
4602 | return 0; | |
4603 | } | |
4604 | } | |
4605 | ||
4606 | /* If constants aren't valid addresses, reload the constant address | |
4607 | into a register. */ | |
191b18e9 | 4608 | if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) |
eab89b90 RK |
4609 | { |
4610 | /* If AD is in address in the constant pool, the MEM rtx may be shared. | |
4611 | Unshare it so we can safely alter it. */ | |
4612 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
4613 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
4614 | { | |
eab89b90 RK |
4615 | *memrefloc = copy_rtx (*memrefloc); |
4616 | loc = &XEXP (*memrefloc, 0); | |
eab89b90 RK |
4617 | } |
4618 | ||
1ba61f4e ILT |
4619 | find_reloads_address_part (ad, loc, reload_address_base_reg_class, |
4620 | Pmode, opnum, type, | |
eab89b90 RK |
4621 | ind_levels); |
4622 | return 1; | |
4623 | } | |
4624 | ||
55c22565 RK |
4625 | return find_reloads_address_1 (mode, ad, 0, loc, opnum, type, ind_levels, |
4626 | insn); | |
eab89b90 RK |
4627 | } |
4628 | \f | |
4629 | /* Find all pseudo regs appearing in AD | |
4630 | that are eliminable in favor of equivalent values | |
4631 | and do not have hard regs; replace them by their equivalents. */ | |
4632 | ||
4633 | static rtx | |
4634 | subst_reg_equivs (ad) | |
4635 | rtx ad; | |
4636 | { | |
4637 | register RTX_CODE code = GET_CODE (ad); | |
4638 | register int i; | |
4639 | register char *fmt; | |
4640 | ||
4641 | switch (code) | |
4642 | { | |
4643 | case HIGH: | |
4644 | case CONST_INT: | |
4645 | case CONST: | |
4646 | case CONST_DOUBLE: | |
4647 | case SYMBOL_REF: | |
4648 | case LABEL_REF: | |
4649 | case PC: | |
4650 | case CC0: | |
4651 | return ad; | |
4652 | ||
4653 | case REG: | |
4654 | { | |
4655 | register int regno = REGNO (ad); | |
4656 | ||
4657 | if (reg_equiv_constant[regno] != 0) | |
4658 | { | |
4659 | subst_reg_equivs_changed = 1; | |
4660 | return reg_equiv_constant[regno]; | |
4661 | } | |
4662 | } | |
4663 | return ad; | |
4664 | ||
4665 | case PLUS: | |
4666 | /* Quickly dispose of a common case. */ | |
4667 | if (XEXP (ad, 0) == frame_pointer_rtx | |
4668 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
4669 | return ad; | |
e9a25f70 JL |
4670 | break; |
4671 | ||
4672 | default: | |
4673 | break; | |
eab89b90 RK |
4674 | } |
4675 | ||
4676 | fmt = GET_RTX_FORMAT (code); | |
4677 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4678 | if (fmt[i] == 'e') | |
4679 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i)); | |
4680 | return ad; | |
4681 | } | |
4682 | \f | |
4683 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
4684 | address, namely: sum constant integers, surround the sum of two | |
4685 | constants with a CONST, put the constant as the second operand, and | |
4686 | group the constant on the outermost sum. | |
4687 | ||
4688 | This routine assumes both inputs are already in canonical form. */ | |
4689 | ||
4690 | rtx | |
4691 | form_sum (x, y) | |
4692 | rtx x, y; | |
4693 | { | |
4694 | rtx tem; | |
2c0623e8 RK |
4695 | enum machine_mode mode = GET_MODE (x); |
4696 | ||
4697 | if (mode == VOIDmode) | |
4698 | mode = GET_MODE (y); | |
4699 | ||
4700 | if (mode == VOIDmode) | |
4701 | mode = Pmode; | |
eab89b90 RK |
4702 | |
4703 | if (GET_CODE (x) == CONST_INT) | |
4704 | return plus_constant (y, INTVAL (x)); | |
4705 | else if (GET_CODE (y) == CONST_INT) | |
4706 | return plus_constant (x, INTVAL (y)); | |
4707 | else if (CONSTANT_P (x)) | |
4708 | tem = x, x = y, y = tem; | |
4709 | ||
4710 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
4711 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
4712 | ||
4713 | /* Note that if the operands of Y are specified in the opposite | |
4714 | order in the recursive calls below, infinite recursion will occur. */ | |
d9771f62 | 4715 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) |
eab89b90 RK |
4716 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); |
4717 | ||
4718 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
4719 | constant will have been placed second. */ | |
4720 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
4721 | { | |
4722 | if (GET_CODE (x) == CONST) | |
4723 | x = XEXP (x, 0); | |
4724 | if (GET_CODE (y) == CONST) | |
4725 | y = XEXP (y, 0); | |
4726 | ||
38a448ca | 4727 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); |
eab89b90 RK |
4728 | } |
4729 | ||
38a448ca | 4730 | return gen_rtx_PLUS (mode, x, y); |
eab89b90 RK |
4731 | } |
4732 | \f | |
4733 | /* If ADDR is a sum containing a pseudo register that should be | |
4734 | replaced with a constant (from reg_equiv_constant), | |
4735 | return the result of doing so, and also apply the associative | |
4736 | law so that the result is more likely to be a valid address. | |
4737 | (But it is not guaranteed to be one.) | |
4738 | ||
4739 | Note that at most one register is replaced, even if more are | |
4740 | replaceable. Also, we try to put the result into a canonical form | |
4741 | so it is more likely to be a valid address. | |
4742 | ||
4743 | In all other cases, return ADDR. */ | |
4744 | ||
4745 | static rtx | |
4746 | subst_indexed_address (addr) | |
4747 | rtx addr; | |
4748 | { | |
4749 | rtx op0 = 0, op1 = 0, op2 = 0; | |
4750 | rtx tem; | |
4751 | int regno; | |
4752 | ||
4753 | if (GET_CODE (addr) == PLUS) | |
4754 | { | |
4755 | /* Try to find a register to replace. */ | |
4756 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
4757 | if (GET_CODE (op0) == REG | |
4758 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER | |
4759 | && reg_renumber[regno] < 0 | |
4760 | && reg_equiv_constant[regno] != 0) | |
4761 | op0 = reg_equiv_constant[regno]; | |
4762 | else if (GET_CODE (op1) == REG | |
4763 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER | |
4764 | && reg_renumber[regno] < 0 | |
4765 | && reg_equiv_constant[regno] != 0) | |
4766 | op1 = reg_equiv_constant[regno]; | |
4767 | else if (GET_CODE (op0) == PLUS | |
4768 | && (tem = subst_indexed_address (op0)) != op0) | |
4769 | op0 = tem; | |
4770 | else if (GET_CODE (op1) == PLUS | |
4771 | && (tem = subst_indexed_address (op1)) != op1) | |
4772 | op1 = tem; | |
4773 | else | |
4774 | return addr; | |
4775 | ||
4776 | /* Pick out up to three things to add. */ | |
4777 | if (GET_CODE (op1) == PLUS) | |
4778 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
4779 | else if (GET_CODE (op0) == PLUS) | |
4780 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
4781 | ||
4782 | /* Compute the sum. */ | |
4783 | if (op2 != 0) | |
4784 | op1 = form_sum (op1, op2); | |
4785 | if (op1 != 0) | |
4786 | op0 = form_sum (op0, op1); | |
4787 | ||
4788 | return op0; | |
4789 | } | |
4790 | return addr; | |
4791 | } | |
4792 | \f | |
858c3c8c ILT |
4793 | /* Record the pseudo registers we must reload into hard registers in a |
4794 | subexpression of a would-be memory address, X referring to a value | |
4795 | in mode MODE. (This function is not called if the address we find | |
4796 | is strictly valid.) | |
4797 | ||
eab89b90 RK |
4798 | CONTEXT = 1 means we are considering regs as index regs, |
4799 | = 0 means we are considering them as base regs. | |
4800 | ||
a8c9daeb | 4801 | OPNUM and TYPE specify the purpose of any reloads made. |
eab89b90 RK |
4802 | |
4803 | IND_LEVELS says how many levels of indirect addressing are | |
4804 | supported at this point in the address. | |
4805 | ||
55c22565 RK |
4806 | INSN, if nonzero, is the insn in which we do the reload. It is used |
4807 | to determine if we may generate output reloads. | |
4808 | ||
eab89b90 RK |
4809 | We return nonzero if X, as a whole, is reloaded or replaced. */ |
4810 | ||
4811 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
4812 | occurs as part of an address. | |
4813 | Also, this is not fully machine-customizable; it works for machines | |
4814 | such as vaxes and 68000's and 32000's, but other possible machines | |
4815 | could have addressing modes that this does not handle right. */ | |
4816 | ||
4817 | static int | |
55c22565 | 4818 | find_reloads_address_1 (mode, x, context, loc, opnum, type, ind_levels, insn) |
858c3c8c | 4819 | enum machine_mode mode; |
eab89b90 RK |
4820 | rtx x; |
4821 | int context; | |
4822 | rtx *loc; | |
a8c9daeb RK |
4823 | int opnum; |
4824 | enum reload_type type; | |
eab89b90 | 4825 | int ind_levels; |
55c22565 | 4826 | rtx insn; |
eab89b90 RK |
4827 | { |
4828 | register RTX_CODE code = GET_CODE (x); | |
4829 | ||
a2d353e5 | 4830 | switch (code) |
eab89b90 | 4831 | { |
a2d353e5 RK |
4832 | case PLUS: |
4833 | { | |
4834 | register rtx orig_op0 = XEXP (x, 0); | |
4835 | register rtx orig_op1 = XEXP (x, 1); | |
4836 | register RTX_CODE code0 = GET_CODE (orig_op0); | |
4837 | register RTX_CODE code1 = GET_CODE (orig_op1); | |
4838 | register rtx op0 = orig_op0; | |
4839 | register rtx op1 = orig_op1; | |
4840 | ||
4841 | if (GET_CODE (op0) == SUBREG) | |
4842 | { | |
4843 | op0 = SUBREG_REG (op0); | |
4844 | code0 = GET_CODE (op0); | |
922db4bb | 4845 | if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER) |
38a448ca RH |
4846 | op0 = gen_rtx_REG (word_mode, |
4847 | REGNO (op0) + SUBREG_WORD (orig_op0)); | |
a2d353e5 | 4848 | } |
87935f60 | 4849 | |
a2d353e5 RK |
4850 | if (GET_CODE (op1) == SUBREG) |
4851 | { | |
4852 | op1 = SUBREG_REG (op1); | |
4853 | code1 = GET_CODE (op1); | |
922db4bb | 4854 | if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER) |
38a448ca RH |
4855 | op1 = gen_rtx_REG (GET_MODE (op1), |
4856 | REGNO (op1) + SUBREG_WORD (orig_op1)); | |
a2d353e5 RK |
4857 | } |
4858 | ||
5f8997b9 SC |
4859 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
4860 | || code0 == ZERO_EXTEND || code1 == MEM) | |
a2d353e5 | 4861 | { |
858c3c8c | 4862 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 4863 | type, ind_levels, insn); |
858c3c8c | 4864 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 4865 | type, ind_levels, insn); |
a2d353e5 RK |
4866 | } |
4867 | ||
5f8997b9 SC |
4868 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE |
4869 | || code1 == ZERO_EXTEND || code0 == MEM) | |
a2d353e5 | 4870 | { |
858c3c8c | 4871 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 4872 | type, ind_levels, insn); |
858c3c8c | 4873 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, |
55c22565 | 4874 | type, ind_levels, insn); |
a2d353e5 RK |
4875 | } |
4876 | ||
4877 | else if (code0 == CONST_INT || code0 == CONST | |
4878 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
858c3c8c | 4879 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 4880 | type, ind_levels, insn); |
a2d353e5 RK |
4881 | |
4882 | else if (code1 == CONST_INT || code1 == CONST | |
4883 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
858c3c8c | 4884 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 4885 | type, ind_levels, insn); |
a2d353e5 RK |
4886 | |
4887 | else if (code0 == REG && code1 == REG) | |
4888 | { | |
4889 | if (REG_OK_FOR_INDEX_P (op0) | |
858c3c8c | 4890 | && REG_MODE_OK_FOR_BASE_P (op1, mode)) |
a2d353e5 RK |
4891 | return 0; |
4892 | else if (REG_OK_FOR_INDEX_P (op1) | |
858c3c8c | 4893 | && REG_MODE_OK_FOR_BASE_P (op0, mode)) |
a2d353e5 | 4894 | return 0; |
858c3c8c ILT |
4895 | else if (REG_MODE_OK_FOR_BASE_P (op1, mode)) |
4896 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, | |
55c22565 | 4897 | type, ind_levels, insn); |
858c3c8c ILT |
4898 | else if (REG_MODE_OK_FOR_BASE_P (op0, mode)) |
4899 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, | |
55c22565 | 4900 | type, ind_levels, insn); |
a2d353e5 | 4901 | else if (REG_OK_FOR_INDEX_P (op1)) |
858c3c8c | 4902 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 4903 | type, ind_levels, insn); |
a2d353e5 | 4904 | else if (REG_OK_FOR_INDEX_P (op0)) |
858c3c8c | 4905 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 4906 | type, ind_levels, insn); |
a2d353e5 RK |
4907 | else |
4908 | { | |
858c3c8c | 4909 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 4910 | type, ind_levels, insn); |
858c3c8c | 4911 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 4912 | type, ind_levels, insn); |
a2d353e5 RK |
4913 | } |
4914 | } | |
4915 | ||
4916 | else if (code0 == REG) | |
4917 | { | |
858c3c8c | 4918 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 4919 | type, ind_levels, insn); |
858c3c8c | 4920 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 4921 | type, ind_levels, insn); |
a2d353e5 RK |
4922 | } |
4923 | ||
4924 | else if (code1 == REG) | |
4925 | { | |
858c3c8c | 4926 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, |
55c22565 | 4927 | type, ind_levels, insn); |
858c3c8c | 4928 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 4929 | type, ind_levels, insn); |
a2d353e5 RK |
4930 | } |
4931 | } | |
4932 | ||
4933 | return 0; | |
4934 | ||
4935 | case POST_INC: | |
4936 | case POST_DEC: | |
4937 | case PRE_INC: | |
4938 | case PRE_DEC: | |
eab89b90 RK |
4939 | if (GET_CODE (XEXP (x, 0)) == REG) |
4940 | { | |
4941 | register int regno = REGNO (XEXP (x, 0)); | |
4942 | int value = 0; | |
4943 | rtx x_orig = x; | |
4944 | ||
4945 | /* A register that is incremented cannot be constant! */ | |
4946 | if (regno >= FIRST_PSEUDO_REGISTER | |
4947 | && reg_equiv_constant[regno] != 0) | |
4948 | abort (); | |
4949 | ||
4950 | /* Handle a register that is equivalent to a memory location | |
4951 | which cannot be addressed directly. */ | |
4952 | if (reg_equiv_address[regno] != 0) | |
4953 | { | |
4954 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
4757e6a4 JW |
4955 | /* First reload the memory location's address. |
4956 | We can't use ADDR_TYPE (type) here, because we need to | |
4957 | write back the value after reading it, hence we actually | |
4958 | need two registers. */ | |
eab89b90 | 4959 | find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0), |
4757e6a4 | 4960 | &XEXP (tem, 0), opnum, type, |
55c22565 | 4961 | ind_levels, insn); |
eab89b90 | 4962 | /* Put this inside a new increment-expression. */ |
38a448ca | 4963 | x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem); |
eab89b90 RK |
4964 | /* Proceed to reload that, as if it contained a register. */ |
4965 | } | |
4966 | ||
4967 | /* If we have a hard register that is ok as an index, | |
4968 | don't make a reload. If an autoincrement of a nice register | |
4969 | isn't "valid", it must be that no autoincrement is "valid". | |
4970 | If that is true and something made an autoincrement anyway, | |
4971 | this must be a special context where one is allowed. | |
4972 | (For example, a "push" instruction.) | |
4973 | We can't improve this address, so leave it alone. */ | |
4974 | ||
4975 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
4976 | and record how much to increment by. */ | |
4977 | ||
4978 | if (reg_renumber[regno] >= 0) | |
4979 | regno = reg_renumber[regno]; | |
4980 | if ((regno >= FIRST_PSEUDO_REGISTER | |
4981 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
858c3c8c | 4982 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))) |
eab89b90 | 4983 | { |
29a82058 | 4984 | #ifdef AUTO_INC_DEC |
eab89b90 | 4985 | register rtx link; |
29a82058 | 4986 | #endif |
55c22565 RK |
4987 | int reloadnum; |
4988 | ||
4989 | /* If we can output the register afterwards, do so, this | |
4990 | saves the extra update. | |
4991 | We can do so if we have an INSN - i.e. no JUMP_INSN nor | |
4992 | CALL_INSN - and it does not set CC0. | |
4993 | But don't do this if we cannot directly address the | |
4994 | memory location, since this will make it harder to | |
956d6950 | 4995 | reuse address reloads, and increases register pressure. |
55c22565 RK |
4996 | Also don't do this if we can probably update x directly. */ |
4997 | rtx equiv = reg_equiv_mem[regno]; | |
4998 | int icode = (int) add_optab->handlers[(int) Pmode].insn_code; | |
4999 | if (insn && GET_CODE (insn) == INSN && equiv | |
5000 | #ifdef HAVE_cc0 | |
5001 | && ! sets_cc0_p (PATTERN (insn)) | |
5002 | #endif | |
5003 | && ! (icode != CODE_FOR_nothing | |
5004 | && (*insn_operand_predicate[icode][0]) (equiv, Pmode) | |
5005 | && (*insn_operand_predicate[icode][1]) (equiv, Pmode))) | |
5006 | { | |
5007 | loc = &XEXP (x, 0); | |
5008 | x = XEXP (x, 0); | |
5009 | reloadnum | |
5010 | = push_reload (x, x, loc, loc, | |
5011 | (context | |
5012 | ? reload_address_index_reg_class | |
5013 | : reload_address_base_reg_class), | |
e9a25f70 | 5014 | GET_MODE (x), GET_MODE (x), 0, 0, |
55c22565 RK |
5015 | opnum, RELOAD_OTHER); |
5016 | } | |
5017 | else | |
5018 | { | |
5019 | reloadnum | |
5020 | = push_reload (x, NULL_RTX, loc, NULL_PTR, | |
5021 | (context | |
5022 | ? reload_address_index_reg_class | |
5023 | : reload_address_base_reg_class), | |
e9a25f70 | 5024 | GET_MODE (x), GET_MODE (x), 0, 0, |
55c22565 RK |
5025 | opnum, type); |
5026 | reload_inc[reloadnum] | |
5027 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); | |
5028 | ||
5029 | value = 1; | |
5030 | } | |
eab89b90 RK |
5031 | |
5032 | #ifdef AUTO_INC_DEC | |
5033 | /* Update the REG_INC notes. */ | |
5034 | ||
5035 | for (link = REG_NOTES (this_insn); | |
5036 | link; link = XEXP (link, 1)) | |
5037 | if (REG_NOTE_KIND (link) == REG_INC | |
5038 | && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0))) | |
5039 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
5040 | #endif | |
5041 | } | |
5042 | return value; | |
5043 | } | |
a2d353e5 | 5044 | |
eab89b90 RK |
5045 | else if (GET_CODE (XEXP (x, 0)) == MEM) |
5046 | { | |
5047 | /* This is probably the result of a substitution, by eliminate_regs, | |
5048 | of an equivalent address for a pseudo that was not allocated to a | |
5049 | hard register. Verify that the specified address is valid and | |
5050 | reload it into a register. */ | |
5051 | rtx tem = XEXP (x, 0); | |
5052 | register rtx link; | |
5053 | int reloadnum; | |
5054 | ||
5055 | /* Since we know we are going to reload this item, don't decrement | |
5056 | for the indirection level. | |
5057 | ||
5058 | Note that this is actually conservative: it would be slightly | |
5059 | more efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5060 | reload1.c here. */ | |
4757e6a4 JW |
5061 | /* We can't use ADDR_TYPE (type) here, because we need to |
5062 | write back the value after reading it, hence we actually | |
5063 | need two registers. */ | |
eab89b90 RK |
5064 | find_reloads_address (GET_MODE (x), &XEXP (x, 0), |
5065 | XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0), | |
55c22565 | 5066 | opnum, type, ind_levels, insn); |
eab89b90 | 5067 | |
fb3821f7 | 5068 | reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR, |
1ba61f4e ILT |
5069 | (context |
5070 | ? reload_address_index_reg_class | |
5071 | : reload_address_base_reg_class), | |
a8c9daeb | 5072 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
5073 | reload_inc[reloadnum] |
5074 | = find_inc_amount (PATTERN (this_insn), XEXP (x, 0)); | |
5075 | ||
5076 | link = FIND_REG_INC_NOTE (this_insn, tem); | |
5077 | if (link != 0) | |
5078 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
5079 | ||
5080 | return 1; | |
5081 | } | |
a2d353e5 RK |
5082 | return 0; |
5083 | ||
5084 | case MEM: | |
5085 | /* This is probably the result of a substitution, by eliminate_regs, of | |
5086 | an equivalent address for a pseudo that was not allocated to a hard | |
5087 | register. Verify that the specified address is valid and reload it | |
5088 | into a register. | |
eab89b90 | 5089 | |
a2d353e5 RK |
5090 | Since we know we are going to reload this item, don't decrement for |
5091 | the indirection level. | |
eab89b90 RK |
5092 | |
5093 | Note that this is actually conservative: it would be slightly more | |
5094 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5095 | reload1.c here. */ | |
5096 | ||
5097 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 5098 | opnum, ADDR_TYPE (type), ind_levels, insn); |
fb3821f7 | 5099 | push_reload (*loc, NULL_RTX, loc, NULL_PTR, |
1ba61f4e ILT |
5100 | (context ? reload_address_index_reg_class |
5101 | : reload_address_base_reg_class), | |
a8c9daeb | 5102 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 | 5103 | return 1; |
eab89b90 | 5104 | |
a2d353e5 RK |
5105 | case REG: |
5106 | { | |
5107 | register int regno = REGNO (x); | |
5108 | ||
5109 | if (reg_equiv_constant[regno] != 0) | |
5110 | { | |
5111 | find_reloads_address_part (reg_equiv_constant[regno], loc, | |
1ba61f4e ILT |
5112 | (context |
5113 | ? reload_address_index_reg_class | |
5114 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5115 | GET_MODE (x), opnum, type, ind_levels); |
5116 | return 1; | |
5117 | } | |
eab89b90 RK |
5118 | |
5119 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
5120 | that feeds this insn. */ | |
a2d353e5 RK |
5121 | if (reg_equiv_mem[regno] != 0) |
5122 | { | |
5123 | push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5124 | (context |
5125 | ? reload_address_index_reg_class | |
5126 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5127 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5128 | return 1; | |
5129 | } | |
eab89b90 | 5130 | #endif |
eab89b90 | 5131 | |
a2d353e5 RK |
5132 | if (reg_equiv_address[regno] != 0) |
5133 | { | |
5134 | x = make_memloc (x, regno); | |
5135 | find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 5136 | opnum, ADDR_TYPE (type), ind_levels, insn); |
a2d353e5 | 5137 | } |
eab89b90 | 5138 | |
a2d353e5 RK |
5139 | if (reg_renumber[regno] >= 0) |
5140 | regno = reg_renumber[regno]; | |
5141 | ||
5142 | if ((regno >= FIRST_PSEUDO_REGISTER | |
5143 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
858c3c8c | 5144 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))) |
a2d353e5 RK |
5145 | { |
5146 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5147 | (context |
5148 | ? reload_address_index_reg_class | |
5149 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5150 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5151 | return 1; | |
5152 | } | |
5153 | ||
5154 | /* If a register appearing in an address is the subject of a CLOBBER | |
5155 | in this insn, reload it into some other register to be safe. | |
5156 | The CLOBBER is supposed to make the register unavailable | |
5157 | from before this insn to after it. */ | |
5158 | if (regno_clobbered_p (regno, this_insn)) | |
5159 | { | |
5160 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5161 | (context |
5162 | ? reload_address_index_reg_class | |
5163 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5164 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5165 | return 1; | |
5166 | } | |
5167 | } | |
5168 | return 0; | |
5169 | ||
5170 | case SUBREG: | |
922db4bb | 5171 | if (GET_CODE (SUBREG_REG (x)) == REG) |
eab89b90 | 5172 | { |
922db4bb RK |
5173 | /* If this is a SUBREG of a hard register and the resulting register |
5174 | is of the wrong class, reload the whole SUBREG. This avoids | |
5175 | needless copies if SUBREG_REG is multi-word. */ | |
5176 | if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5177 | { | |
5178 | int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
a2d353e5 | 5179 | |
922db4bb | 5180 | if (! (context ? REGNO_OK_FOR_INDEX_P (regno) |
858c3c8c | 5181 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode))) |
922db4bb RK |
5182 | { |
5183 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5184 | (context |
5185 | ? reload_address_index_reg_class | |
5186 | : reload_address_base_reg_class), | |
922db4bb RK |
5187 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5188 | return 1; | |
5189 | } | |
5190 | } | |
abc95ed3 | 5191 | /* If this is a SUBREG of a pseudo-register, and the pseudo-register |
922db4bb RK |
5192 | is larger than the class size, then reload the whole SUBREG. */ |
5193 | else | |
a2d353e5 | 5194 | { |
922db4bb | 5195 | enum reg_class class = (context |
1ba61f4e ILT |
5196 | ? reload_address_index_reg_class |
5197 | : reload_address_base_reg_class); | |
922db4bb RK |
5198 | if (CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x))) |
5199 | > reg_class_size[class]) | |
5200 | { | |
5201 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, | |
5202 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
5203 | return 1; | |
5204 | } | |
a2d353e5 | 5205 | } |
eab89b90 | 5206 | } |
a2d353e5 | 5207 | break; |
e9a25f70 JL |
5208 | |
5209 | default: | |
5210 | break; | |
eab89b90 RK |
5211 | } |
5212 | ||
a2d353e5 RK |
5213 | { |
5214 | register char *fmt = GET_RTX_FORMAT (code); | |
5215 | register int i; | |
5216 | ||
5217 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5218 | { | |
5219 | if (fmt[i] == 'e') | |
858c3c8c | 5220 | find_reloads_address_1 (mode, XEXP (x, i), context, &XEXP (x, i), |
55c22565 | 5221 | opnum, type, ind_levels, insn); |
a2d353e5 RK |
5222 | } |
5223 | } | |
5224 | ||
eab89b90 RK |
5225 | return 0; |
5226 | } | |
5227 | \f | |
5228 | /* X, which is found at *LOC, is a part of an address that needs to be | |
5229 | reloaded into a register of class CLASS. If X is a constant, or if | |
5230 | X is a PLUS that contains a constant, check that the constant is a | |
5231 | legitimate operand and that we are supposed to be able to load | |
5232 | it into the register. | |
5233 | ||
5234 | If not, force the constant into memory and reload the MEM instead. | |
5235 | ||
5236 | MODE is the mode to use, in case X is an integer constant. | |
5237 | ||
a8c9daeb | 5238 | OPNUM and TYPE describe the purpose of any reloads made. |
eab89b90 RK |
5239 | |
5240 | IND_LEVELS says how many levels of indirect addressing this machine | |
5241 | supports. */ | |
5242 | ||
5243 | static void | |
a8c9daeb | 5244 | find_reloads_address_part (x, loc, class, mode, opnum, type, ind_levels) |
eab89b90 RK |
5245 | rtx x; |
5246 | rtx *loc; | |
5247 | enum reg_class class; | |
5248 | enum machine_mode mode; | |
a8c9daeb RK |
5249 | int opnum; |
5250 | enum reload_type type; | |
eab89b90 RK |
5251 | int ind_levels; |
5252 | { | |
5253 | if (CONSTANT_P (x) | |
5254 | && (! LEGITIMATE_CONSTANT_P (x) | |
5255 | || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) | |
5256 | { | |
5257 | rtx tem = x = force_const_mem (mode, x); | |
5258 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), | |
55c22565 | 5259 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5260 | } |
5261 | ||
5262 | else if (GET_CODE (x) == PLUS | |
5263 | && CONSTANT_P (XEXP (x, 1)) | |
5264 | && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | |
5265 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) | |
5266 | { | |
5267 | rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); | |
5268 | ||
38a448ca | 5269 | x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem); |
eab89b90 | 5270 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), |
55c22565 | 5271 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5272 | } |
5273 | ||
fb3821f7 | 5274 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, |
a8c9daeb | 5275 | mode, VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
5276 | } |
5277 | \f | |
a8c9daeb | 5278 | /* Substitute into the current INSN the registers into which we have reloaded |
eab89b90 RK |
5279 | the things that need reloading. The array `replacements' |
5280 | says contains the locations of all pointers that must be changed | |
5281 | and says what to replace them with. | |
5282 | ||
5283 | Return the rtx that X translates into; usually X, but modified. */ | |
5284 | ||
5285 | void | |
5286 | subst_reloads () | |
5287 | { | |
5288 | register int i; | |
5289 | ||
5290 | for (i = 0; i < n_replacements; i++) | |
5291 | { | |
5292 | register struct replacement *r = &replacements[i]; | |
5293 | register rtx reloadreg = reload_reg_rtx[r->what]; | |
5294 | if (reloadreg) | |
5295 | { | |
5296 | /* Encapsulate RELOADREG so its machine mode matches what | |
26f1a00e RK |
5297 | used to be there. Note that gen_lowpart_common will |
5298 | do the wrong thing if RELOADREG is multi-word. RELOADREG | |
5299 | will always be a REG here. */ | |
eab89b90 | 5300 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) |
38a448ca | 5301 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
eab89b90 RK |
5302 | |
5303 | /* If we are putting this into a SUBREG and RELOADREG is a | |
5304 | SUBREG, we would be making nested SUBREGs, so we have to fix | |
5305 | this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ | |
5306 | ||
5307 | if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) | |
5308 | { | |
5309 | if (GET_MODE (*r->subreg_loc) | |
5310 | == GET_MODE (SUBREG_REG (reloadreg))) | |
5311 | *r->subreg_loc = SUBREG_REG (reloadreg); | |
5312 | else | |
5313 | { | |
5314 | *r->where = SUBREG_REG (reloadreg); | |
5315 | SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg); | |
5316 | } | |
5317 | } | |
5318 | else | |
5319 | *r->where = reloadreg; | |
5320 | } | |
5321 | /* If reload got no reg and isn't optional, something's wrong. */ | |
5322 | else if (! reload_optional[r->what]) | |
5323 | abort (); | |
5324 | } | |
5325 | } | |
5326 | \f | |
5327 | /* Make a copy of any replacements being done into X and move those copies | |
5328 | to locations in Y, a copy of X. We only look at the highest level of | |
5329 | the RTL. */ | |
5330 | ||
5331 | void | |
5332 | copy_replacements (x, y) | |
5333 | rtx x; | |
5334 | rtx y; | |
5335 | { | |
5336 | int i, j; | |
5337 | enum rtx_code code = GET_CODE (x); | |
5338 | char *fmt = GET_RTX_FORMAT (code); | |
5339 | struct replacement *r; | |
5340 | ||
5341 | /* We can't support X being a SUBREG because we might then need to know its | |
5342 | location if something inside it was replaced. */ | |
5343 | if (code == SUBREG) | |
5344 | abort (); | |
5345 | ||
5346 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5347 | if (fmt[i] == 'e') | |
5348 | for (j = 0; j < n_replacements; j++) | |
5349 | { | |
5350 | if (replacements[j].subreg_loc == &XEXP (x, i)) | |
5351 | { | |
5352 | r = &replacements[n_replacements++]; | |
5353 | r->where = replacements[j].where; | |
5354 | r->subreg_loc = &XEXP (y, i); | |
5355 | r->what = replacements[j].what; | |
5356 | r->mode = replacements[j].mode; | |
5357 | } | |
5358 | else if (replacements[j].where == &XEXP (x, i)) | |
5359 | { | |
5360 | r = &replacements[n_replacements++]; | |
5361 | r->where = &XEXP (y, i); | |
5362 | r->subreg_loc = 0; | |
5363 | r->what = replacements[j].what; | |
5364 | r->mode = replacements[j].mode; | |
5365 | } | |
5366 | } | |
5367 | } | |
5368 | \f | |
af929c62 RK |
5369 | /* If LOC was scheduled to be replaced by something, return the replacement. |
5370 | Otherwise, return *LOC. */ | |
5371 | ||
5372 | rtx | |
5373 | find_replacement (loc) | |
5374 | rtx *loc; | |
5375 | { | |
5376 | struct replacement *r; | |
5377 | ||
5378 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
5379 | { | |
5380 | rtx reloadreg = reload_reg_rtx[r->what]; | |
5381 | ||
5382 | if (reloadreg && r->where == loc) | |
5383 | { | |
5384 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
38a448ca | 5385 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
af929c62 RK |
5386 | |
5387 | return reloadreg; | |
5388 | } | |
5389 | else if (reloadreg && r->subreg_loc == loc) | |
5390 | { | |
5391 | /* RELOADREG must be either a REG or a SUBREG. | |
5392 | ||
5393 | ??? Is it actually still ever a SUBREG? If so, why? */ | |
5394 | ||
5395 | if (GET_CODE (reloadreg) == REG) | |
38a448ca RH |
5396 | return gen_rtx_REG (GET_MODE (*loc), |
5397 | REGNO (reloadreg) + SUBREG_WORD (*loc)); | |
af929c62 RK |
5398 | else if (GET_MODE (reloadreg) == GET_MODE (*loc)) |
5399 | return reloadreg; | |
5400 | else | |
38a448ca RH |
5401 | return gen_rtx_SUBREG (GET_MODE (*loc), SUBREG_REG (reloadreg), |
5402 | SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc)); | |
af929c62 RK |
5403 | } |
5404 | } | |
5405 | ||
956d6950 JL |
5406 | /* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for |
5407 | what's inside and make a new rtl if so. */ | |
5408 | if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS | |
5409 | || GET_CODE (*loc) == MULT) | |
5410 | { | |
5411 | rtx x = find_replacement (&XEXP (*loc, 0)); | |
5412 | rtx y = find_replacement (&XEXP (*loc, 1)); | |
5413 | ||
5414 | if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1)) | |
38a448ca | 5415 | return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y); |
956d6950 JL |
5416 | } |
5417 | ||
af929c62 RK |
5418 | return *loc; |
5419 | } | |
5420 | \f | |
eab89b90 RK |
5421 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
5422 | appears either explicitly or implicitly in X | |
4644aad4 | 5423 | other than being stored into (except for earlyclobber operands). |
eab89b90 RK |
5424 | |
5425 | References contained within the substructure at LOC do not count. | |
5426 | LOC may be zero, meaning don't ignore anything. | |
5427 | ||
5428 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
5429 | look at equivalences for pseudos that didn't get hard registers. */ | |
5430 | ||
5431 | int | |
5432 | refers_to_regno_for_reload_p (regno, endregno, x, loc) | |
5433 | int regno, endregno; | |
5434 | rtx x; | |
5435 | rtx *loc; | |
5436 | { | |
5437 | register int i; | |
5438 | register RTX_CODE code; | |
5439 | register char *fmt; | |
5440 | ||
5441 | if (x == 0) | |
5442 | return 0; | |
5443 | ||
5444 | repeat: | |
5445 | code = GET_CODE (x); | |
5446 | ||
5447 | switch (code) | |
5448 | { | |
5449 | case REG: | |
5450 | i = REGNO (x); | |
5451 | ||
4803a34a RK |
5452 | /* If this is a pseudo, a hard register must not have been allocated. |
5453 | X must therefore either be a constant or be in memory. */ | |
5454 | if (i >= FIRST_PSEUDO_REGISTER) | |
5455 | { | |
5456 | if (reg_equiv_memory_loc[i]) | |
5457 | return refers_to_regno_for_reload_p (regno, endregno, | |
fb3821f7 CH |
5458 | reg_equiv_memory_loc[i], |
5459 | NULL_PTR); | |
4803a34a RK |
5460 | |
5461 | if (reg_equiv_constant[i]) | |
5462 | return 0; | |
5463 | ||
5464 | abort (); | |
5465 | } | |
eab89b90 RK |
5466 | |
5467 | return (endregno > i | |
5468 | && regno < i + (i < FIRST_PSEUDO_REGISTER | |
5469 | ? HARD_REGNO_NREGS (i, GET_MODE (x)) | |
5470 | : 1)); | |
5471 | ||
5472 | case SUBREG: | |
5473 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
5474 | registers are being modified. Otherwise, handle normally. */ | |
5475 | if (GET_CODE (SUBREG_REG (x)) == REG | |
5476 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5477 | { | |
5478 | int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
5479 | int inner_endregno | |
5480 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER | |
5481 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
5482 | ||
5483 | return endregno > inner_regno && regno < inner_endregno; | |
5484 | } | |
5485 | break; | |
5486 | ||
5487 | case CLOBBER: | |
5488 | case SET: | |
5489 | if (&SET_DEST (x) != loc | |
5490 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
5491 | a pseudo but not for hard registers since we can | |
5492 | treat each word individually. */ | |
5493 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
5494 | && loc != &SUBREG_REG (SET_DEST (x)) | |
5495 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
5496 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER | |
5497 | && refers_to_regno_for_reload_p (regno, endregno, | |
5498 | SUBREG_REG (SET_DEST (x)), | |
5499 | loc)) | |
abc95ed3 | 5500 | /* If the output is an earlyclobber operand, this is |
4644aad4 RK |
5501 | a conflict. */ |
5502 | || ((GET_CODE (SET_DEST (x)) != REG | |
5503 | || earlyclobber_operand_p (SET_DEST (x))) | |
eab89b90 RK |
5504 | && refers_to_regno_for_reload_p (regno, endregno, |
5505 | SET_DEST (x), loc)))) | |
5506 | return 1; | |
5507 | ||
5508 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
5509 | return 0; | |
5510 | x = SET_SRC (x); | |
5511 | goto repeat; | |
e9a25f70 JL |
5512 | |
5513 | default: | |
5514 | break; | |
eab89b90 RK |
5515 | } |
5516 | ||
5517 | /* X does not match, so try its subexpressions. */ | |
5518 | ||
5519 | fmt = GET_RTX_FORMAT (code); | |
5520 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5521 | { | |
5522 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
5523 | { | |
5524 | if (i == 0) | |
5525 | { | |
5526 | x = XEXP (x, 0); | |
5527 | goto repeat; | |
5528 | } | |
5529 | else | |
5530 | if (refers_to_regno_for_reload_p (regno, endregno, | |
5531 | XEXP (x, i), loc)) | |
5532 | return 1; | |
5533 | } | |
5534 | else if (fmt[i] == 'E') | |
5535 | { | |
5536 | register int j; | |
5537 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
5538 | if (loc != &XVECEXP (x, i, j) | |
5539 | && refers_to_regno_for_reload_p (regno, endregno, | |
5540 | XVECEXP (x, i, j), loc)) | |
5541 | return 1; | |
5542 | } | |
5543 | } | |
5544 | return 0; | |
5545 | } | |
bfa30b22 RK |
5546 | |
5547 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
5548 | we check if any register number in X conflicts with the relevant register | |
5549 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
5550 | contains a MEM (we don't bother checking for memory addresses that can't | |
5551 | conflict because we expect this to be a rare case. | |
5552 | ||
5553 | This function is similar to reg_overlap_mention_p in rtlanal.c except | |
5554 | that we look at equivalences for pseudos that didn't get hard registers. */ | |
5555 | ||
5556 | int | |
5557 | reg_overlap_mentioned_for_reload_p (x, in) | |
5558 | rtx x, in; | |
5559 | { | |
5560 | int regno, endregno; | |
5561 | ||
5562 | if (GET_CODE (x) == SUBREG) | |
5563 | { | |
5564 | regno = REGNO (SUBREG_REG (x)); | |
5565 | if (regno < FIRST_PSEUDO_REGISTER) | |
5566 | regno += SUBREG_WORD (x); | |
5567 | } | |
5568 | else if (GET_CODE (x) == REG) | |
5569 | { | |
5570 | regno = REGNO (x); | |
4803a34a RK |
5571 | |
5572 | /* If this is a pseudo, it must not have been assigned a hard register. | |
5573 | Therefore, it must either be in memory or be a constant. */ | |
5574 | ||
5575 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5576 | { | |
5577 | if (reg_equiv_memory_loc[regno]) | |
5578 | return refers_to_mem_for_reload_p (in); | |
5579 | else if (reg_equiv_constant[regno]) | |
5580 | return 0; | |
5581 | abort (); | |
5582 | } | |
bfa30b22 RK |
5583 | } |
5584 | else if (CONSTANT_P (x)) | |
5585 | return 0; | |
5586 | else if (GET_CODE (x) == MEM) | |
4803a34a | 5587 | return refers_to_mem_for_reload_p (in); |
bfa30b22 RK |
5588 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
5589 | || GET_CODE (x) == CC0) | |
5590 | return reg_mentioned_p (x, in); | |
5591 | else | |
5592 | abort (); | |
5593 | ||
5594 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
5595 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
5596 | ||
fb3821f7 | 5597 | return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR); |
bfa30b22 | 5598 | } |
4803a34a RK |
5599 | |
5600 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
5601 | registers. */ | |
5602 | ||
5603 | int | |
5604 | refers_to_mem_for_reload_p (x) | |
5605 | rtx x; | |
5606 | { | |
5607 | char *fmt; | |
5608 | int i; | |
5609 | ||
5610 | if (GET_CODE (x) == MEM) | |
5611 | return 1; | |
5612 | ||
5613 | if (GET_CODE (x) == REG) | |
5614 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
5615 | && reg_equiv_memory_loc[REGNO (x)]); | |
5616 | ||
5617 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
5618 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
5619 | if (fmt[i] == 'e' | |
5620 | && (GET_CODE (XEXP (x, i)) == MEM | |
5621 | || refers_to_mem_for_reload_p (XEXP (x, i)))) | |
5622 | return 1; | |
5623 | ||
5624 | return 0; | |
5625 | } | |
eab89b90 | 5626 | \f |
eab89b90 RK |
5627 | /* Check the insns before INSN to see if there is a suitable register |
5628 | containing the same value as GOAL. | |
5629 | If OTHER is -1, look for a register in class CLASS. | |
5630 | Otherwise, just see if register number OTHER shares GOAL's value. | |
5631 | ||
5632 | Return an rtx for the register found, or zero if none is found. | |
5633 | ||
5634 | If RELOAD_REG_P is (short *)1, | |
5635 | we reject any hard reg that appears in reload_reg_rtx | |
5636 | because such a hard reg is also needed coming into this insn. | |
5637 | ||
5638 | If RELOAD_REG_P is any other nonzero value, | |
5639 | it is a vector indexed by hard reg number | |
5640 | and we reject any hard reg whose element in the vector is nonnegative | |
5641 | as well as any that appears in reload_reg_rtx. | |
5642 | ||
5643 | If GOAL is zero, then GOALREG is a register number; we look | |
5644 | for an equivalent for that register. | |
5645 | ||
5646 | MODE is the machine mode of the value we want an equivalence for. | |
5647 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
5648 | ||
5649 | This function is used by jump.c as well as in the reload pass. | |
5650 | ||
5651 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
5652 | as if it were a constant except that sp is required to be unchanging. */ | |
5653 | ||
5654 | rtx | |
5655 | find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode) | |
5656 | register rtx goal; | |
5657 | rtx insn; | |
5658 | enum reg_class class; | |
5659 | register int other; | |
5660 | short *reload_reg_p; | |
5661 | int goalreg; | |
5662 | enum machine_mode mode; | |
5663 | { | |
5664 | register rtx p = insn; | |
f55b1d97 | 5665 | rtx goaltry, valtry, value, where; |
eab89b90 RK |
5666 | register rtx pat; |
5667 | register int regno = -1; | |
5668 | int valueno; | |
5669 | int goal_mem = 0; | |
5670 | int goal_const = 0; | |
5671 | int goal_mem_addr_varies = 0; | |
5672 | int need_stable_sp = 0; | |
5673 | int nregs; | |
5674 | int valuenregs; | |
5675 | ||
5676 | if (goal == 0) | |
5677 | regno = goalreg; | |
5678 | else if (GET_CODE (goal) == REG) | |
5679 | regno = REGNO (goal); | |
5680 | else if (GET_CODE (goal) == MEM) | |
5681 | { | |
5682 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
5683 | if (MEM_VOLATILE_P (goal)) | |
5684 | return 0; | |
5685 | if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT) | |
5686 | return 0; | |
5687 | /* An address with side effects must be reexecuted. */ | |
5688 | switch (code) | |
5689 | { | |
5690 | case POST_INC: | |
5691 | case PRE_INC: | |
5692 | case POST_DEC: | |
5693 | case PRE_DEC: | |
5694 | return 0; | |
e9a25f70 JL |
5695 | default: |
5696 | break; | |
eab89b90 RK |
5697 | } |
5698 | goal_mem = 1; | |
5699 | } | |
5700 | else if (CONSTANT_P (goal)) | |
5701 | goal_const = 1; | |
5702 | else if (GET_CODE (goal) == PLUS | |
5703 | && XEXP (goal, 0) == stack_pointer_rtx | |
5704 | && CONSTANT_P (XEXP (goal, 1))) | |
5705 | goal_const = need_stable_sp = 1; | |
5706 | else | |
5707 | return 0; | |
5708 | ||
5709 | /* On some machines, certain regs must always be rejected | |
5710 | because they don't behave the way ordinary registers do. */ | |
5711 | ||
5712 | #ifdef OVERLAPPING_REGNO_P | |
5713 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5714 | && OVERLAPPING_REGNO_P (regno)) | |
5715 | return 0; | |
5716 | #endif | |
5717 | ||
5718 | /* Scan insns back from INSN, looking for one that copies | |
5719 | a value into or out of GOAL. | |
5720 | Stop and give up if we reach a label. */ | |
5721 | ||
5722 | while (1) | |
5723 | { | |
5724 | p = PREV_INSN (p); | |
5725 | if (p == 0 || GET_CODE (p) == CODE_LABEL) | |
5726 | return 0; | |
5727 | if (GET_CODE (p) == INSN | |
0f41302f | 5728 | /* If we don't want spill regs ... */ |
a8c9daeb RK |
5729 | && (! (reload_reg_p != 0 |
5730 | && reload_reg_p != (short *) (HOST_WIDE_INT) 1) | |
eab89b90 RK |
5731 | /* ... then ignore insns introduced by reload; they aren't useful |
5732 | and can cause results in reload_as_needed to be different | |
5733 | from what they were when calculating the need for spills. | |
5734 | If we notice an input-reload insn here, we will reject it below, | |
5735 | but it might hide a usable equivalent. That makes bad code. | |
5736 | It may even abort: perhaps no reg was spilled for this insn | |
5737 | because it was assumed we would find that equivalent. */ | |
5738 | || INSN_UID (p) < reload_first_uid)) | |
5739 | { | |
e8094962 | 5740 | rtx tem; |
eab89b90 RK |
5741 | pat = single_set (p); |
5742 | /* First check for something that sets some reg equal to GOAL. */ | |
5743 | if (pat != 0 | |
5744 | && ((regno >= 0 | |
5745 | && true_regnum (SET_SRC (pat)) == regno | |
5746 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
5747 | || | |
5748 | (regno >= 0 | |
5749 | && true_regnum (SET_DEST (pat)) == regno | |
5750 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
5751 | || | |
5752 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
5753 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
5754 | || (goal_mem | |
5755 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
5756 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
5757 | || (goal_mem | |
5758 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
e8094962 RK |
5759 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
5760 | /* If we are looking for a constant, | |
5761 | and something equivalent to that constant was copied | |
5762 | into a reg, we can use that reg. */ | |
fb3821f7 CH |
5763 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5764 | NULL_RTX)) | |
e8094962 | 5765 | && rtx_equal_p (XEXP (tem, 0), goal) |
95d3562b | 5766 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
fb3821f7 CH |
5767 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5768 | NULL_RTX)) | |
e8094962 RK |
5769 | && GET_CODE (SET_DEST (pat)) == REG |
5770 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
5771 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
5772 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
5773 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 0, 0, |
5774 | VOIDmode)) | |
5775 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
5776 | && (valtry = operand_subword (SET_DEST (pat), 0, 0, |
5777 | VOIDmode)) | |
95d3562b | 5778 | && (valueno = true_regnum (valtry)) >= 0) |
fb3821f7 CH |
5779 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5780 | NULL_RTX)) | |
e8094962 RK |
5781 | && GET_CODE (SET_DEST (pat)) == REG |
5782 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
5783 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
5784 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
5785 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, |
5786 | VOIDmode)) | |
5787 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
5788 | && (valtry |
5789 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
95d3562b | 5790 | && (valueno = true_regnum (valtry)) >= 0))) |
eab89b90 RK |
5791 | if (other >= 0 |
5792 | ? valueno == other | |
5793 | : ((unsigned) valueno < FIRST_PSEUDO_REGISTER | |
5794 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
5795 | valueno))) | |
5796 | { | |
5797 | value = valtry; | |
5798 | where = p; | |
5799 | break; | |
5800 | } | |
5801 | } | |
5802 | } | |
5803 | ||
5804 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
5805 | (or copying VALUE into GOAL, if GOAL is also a register). | |
5806 | Now verify that VALUE is really valid. */ | |
5807 | ||
5808 | /* VALUENO is the register number of VALUE; a hard register. */ | |
5809 | ||
5810 | /* Don't try to re-use something that is killed in this insn. We want | |
5811 | to be able to trust REG_UNUSED notes. */ | |
5812 | if (find_reg_note (where, REG_UNUSED, value)) | |
5813 | return 0; | |
5814 | ||
5815 | /* If we propose to get the value from the stack pointer or if GOAL is | |
5816 | a MEM based on the stack pointer, we need a stable SP. */ | |
d5a1d1c7 | 5817 | if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM |
bfa30b22 RK |
5818 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
5819 | goal))) | |
eab89b90 RK |
5820 | need_stable_sp = 1; |
5821 | ||
5822 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
5823 | if (GET_MODE (value) != mode) | |
5824 | return 0; | |
5825 | ||
5826 | /* Reject VALUE if it was loaded from GOAL | |
5827 | and is also a register that appears in the address of GOAL. */ | |
5828 | ||
bd5f6d44 | 5829 | if (goal_mem && value == SET_DEST (single_set (where)) |
bfa30b22 RK |
5830 | && refers_to_regno_for_reload_p (valueno, |
5831 | (valueno | |
5832 | + HARD_REGNO_NREGS (valueno, mode)), | |
fb3821f7 | 5833 | goal, NULL_PTR)) |
eab89b90 RK |
5834 | return 0; |
5835 | ||
5836 | /* Reject registers that overlap GOAL. */ | |
5837 | ||
5838 | if (!goal_mem && !goal_const | |
5839 | && regno + HARD_REGNO_NREGS (regno, mode) > valueno | |
5840 | && regno < valueno + HARD_REGNO_NREGS (valueno, mode)) | |
5841 | return 0; | |
5842 | ||
5843 | /* Reject VALUE if it is one of the regs reserved for reloads. | |
5844 | Reload1 knows how to reuse them anyway, and it would get | |
5845 | confused if we allocated one without its knowledge. | |
5846 | (Now that insns introduced by reload are ignored above, | |
5847 | this case shouldn't happen, but I'm not positive.) */ | |
5848 | ||
a8c9daeb | 5849 | if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1 |
eab89b90 RK |
5850 | && reload_reg_p[valueno] >= 0) |
5851 | return 0; | |
5852 | ||
5853 | /* On some machines, certain regs must always be rejected | |
5854 | because they don't behave the way ordinary registers do. */ | |
5855 | ||
5856 | #ifdef OVERLAPPING_REGNO_P | |
5857 | if (OVERLAPPING_REGNO_P (valueno)) | |
5858 | return 0; | |
5859 | #endif | |
5860 | ||
5861 | nregs = HARD_REGNO_NREGS (regno, mode); | |
5862 | valuenregs = HARD_REGNO_NREGS (valueno, mode); | |
5863 | ||
5864 | /* Reject VALUE if it is a register being used for an input reload | |
5865 | even if it is not one of those reserved. */ | |
5866 | ||
5867 | if (reload_reg_p != 0) | |
5868 | { | |
5869 | int i; | |
5870 | for (i = 0; i < n_reloads; i++) | |
5871 | if (reload_reg_rtx[i] != 0 && reload_in[i]) | |
5872 | { | |
5873 | int regno1 = REGNO (reload_reg_rtx[i]); | |
5874 | int nregs1 = HARD_REGNO_NREGS (regno1, | |
5875 | GET_MODE (reload_reg_rtx[i])); | |
5876 | if (regno1 < valueno + valuenregs | |
5877 | && regno1 + nregs1 > valueno) | |
5878 | return 0; | |
5879 | } | |
5880 | } | |
5881 | ||
5882 | if (goal_mem) | |
54b5ffe9 RS |
5883 | /* We must treat frame pointer as varying here, |
5884 | since it can vary--in a nonlocal goto as generated by expand_goto. */ | |
5885 | goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); | |
eab89b90 RK |
5886 | |
5887 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
5888 | until INSN is reached. */ | |
5889 | ||
5890 | p = insn; | |
5891 | while (1) | |
5892 | { | |
5893 | p = PREV_INSN (p); | |
5894 | if (p == where) | |
5895 | return value; | |
5896 | ||
5897 | /* Don't trust the conversion past a function call | |
5898 | if either of the two is in a call-clobbered register, or memory. */ | |
5899 | if (GET_CODE (p) == CALL_INSN | |
5900 | && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5901 | && call_used_regs[regno]) | |
5902 | || | |
5903 | (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
5904 | && call_used_regs[valueno]) | |
5905 | || | |
5906 | goal_mem | |
5907 | || need_stable_sp)) | |
5908 | return 0; | |
5909 | ||
41fe17ab RK |
5910 | #ifdef NON_SAVING_SETJMP |
5911 | if (NON_SAVING_SETJMP && GET_CODE (p) == NOTE | |
5912 | && NOTE_LINE_NUMBER (p) == NOTE_INSN_SETJMP) | |
5913 | return 0; | |
5914 | #endif | |
5915 | ||
eab89b90 RK |
5916 | #ifdef INSN_CLOBBERS_REGNO_P |
5917 | if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
5918 | && INSN_CLOBBERS_REGNO_P (p, valueno)) | |
5919 | || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5920 | && INSN_CLOBBERS_REGNO_P (p, regno))) | |
5921 | return 0; | |
5922 | #endif | |
5923 | ||
5924 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
5925 | { | |
5926 | /* If this insn P stores in either GOAL or VALUE, return 0. | |
5927 | If GOAL is a memory ref and this insn writes memory, return 0. | |
5928 | If GOAL is a memory ref and its address is not constant, | |
5929 | and this insn P changes a register used in GOAL, return 0. */ | |
5930 | ||
5931 | pat = PATTERN (p); | |
5932 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) | |
5933 | { | |
5934 | register rtx dest = SET_DEST (pat); | |
5935 | while (GET_CODE (dest) == SUBREG | |
5936 | || GET_CODE (dest) == ZERO_EXTRACT | |
5937 | || GET_CODE (dest) == SIGN_EXTRACT | |
5938 | || GET_CODE (dest) == STRICT_LOW_PART) | |
5939 | dest = XEXP (dest, 0); | |
5940 | if (GET_CODE (dest) == REG) | |
5941 | { | |
5942 | register int xregno = REGNO (dest); | |
5943 | int xnregs; | |
5944 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
5945 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
5946 | else | |
5947 | xnregs = 1; | |
5948 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
5949 | return 0; | |
5950 | if (xregno < valueno + valuenregs | |
5951 | && xregno + xnregs > valueno) | |
5952 | return 0; | |
5953 | if (goal_mem_addr_varies | |
bfa30b22 | 5954 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
eab89b90 RK |
5955 | return 0; |
5956 | } | |
5957 | else if (goal_mem && GET_CODE (dest) == MEM | |
5958 | && ! push_operand (dest, GET_MODE (dest))) | |
5959 | return 0; | |
9fac9680 RK |
5960 | else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER |
5961 | && reg_equiv_memory_loc[regno] != 0) | |
5962 | return 0; | |
eab89b90 RK |
5963 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) |
5964 | return 0; | |
5965 | } | |
5966 | else if (GET_CODE (pat) == PARALLEL) | |
5967 | { | |
5968 | register int i; | |
5969 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
5970 | { | |
5971 | register rtx v1 = XVECEXP (pat, 0, i); | |
5972 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) | |
5973 | { | |
5974 | register rtx dest = SET_DEST (v1); | |
5975 | while (GET_CODE (dest) == SUBREG | |
5976 | || GET_CODE (dest) == ZERO_EXTRACT | |
5977 | || GET_CODE (dest) == SIGN_EXTRACT | |
5978 | || GET_CODE (dest) == STRICT_LOW_PART) | |
5979 | dest = XEXP (dest, 0); | |
5980 | if (GET_CODE (dest) == REG) | |
5981 | { | |
5982 | register int xregno = REGNO (dest); | |
5983 | int xnregs; | |
5984 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
5985 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
5986 | else | |
5987 | xnregs = 1; | |
5988 | if (xregno < regno + nregs | |
5989 | && xregno + xnregs > regno) | |
5990 | return 0; | |
5991 | if (xregno < valueno + valuenregs | |
5992 | && xregno + xnregs > valueno) | |
5993 | return 0; | |
5994 | if (goal_mem_addr_varies | |
bfa30b22 RK |
5995 | && reg_overlap_mentioned_for_reload_p (dest, |
5996 | goal)) | |
eab89b90 RK |
5997 | return 0; |
5998 | } | |
5999 | else if (goal_mem && GET_CODE (dest) == MEM | |
6000 | && ! push_operand (dest, GET_MODE (dest))) | |
6001 | return 0; | |
e9a25f70 JL |
6002 | else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER |
6003 | && reg_equiv_memory_loc[regno] != 0) | |
6004 | return 0; | |
369c7ab6 JW |
6005 | else if (need_stable_sp |
6006 | && push_operand (dest, GET_MODE (dest))) | |
6007 | return 0; | |
6008 | } | |
6009 | } | |
6010 | } | |
6011 | ||
6012 | if (GET_CODE (p) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (p)) | |
6013 | { | |
6014 | rtx link; | |
6015 | ||
6016 | for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0; | |
6017 | link = XEXP (link, 1)) | |
6018 | { | |
6019 | pat = XEXP (link, 0); | |
6020 | if (GET_CODE (pat) == CLOBBER) | |
6021 | { | |
6022 | register rtx dest = SET_DEST (pat); | |
6023 | while (GET_CODE (dest) == SUBREG | |
6024 | || GET_CODE (dest) == ZERO_EXTRACT | |
6025 | || GET_CODE (dest) == SIGN_EXTRACT | |
6026 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6027 | dest = XEXP (dest, 0); | |
6028 | if (GET_CODE (dest) == REG) | |
6029 | { | |
6030 | register int xregno = REGNO (dest); | |
6031 | int xnregs; | |
6032 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
6033 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
6034 | else | |
6035 | xnregs = 1; | |
6036 | if (xregno < regno + nregs | |
6037 | && xregno + xnregs > regno) | |
6038 | return 0; | |
6039 | if (xregno < valueno + valuenregs | |
6040 | && xregno + xnregs > valueno) | |
6041 | return 0; | |
6042 | if (goal_mem_addr_varies | |
6043 | && reg_overlap_mentioned_for_reload_p (dest, | |
6044 | goal)) | |
6045 | return 0; | |
6046 | } | |
6047 | else if (goal_mem && GET_CODE (dest) == MEM | |
6048 | && ! push_operand (dest, GET_MODE (dest))) | |
6049 | return 0; | |
eab89b90 RK |
6050 | else if (need_stable_sp |
6051 | && push_operand (dest, GET_MODE (dest))) | |
6052 | return 0; | |
6053 | } | |
6054 | } | |
6055 | } | |
6056 | ||
6057 | #ifdef AUTO_INC_DEC | |
6058 | /* If this insn auto-increments or auto-decrements | |
6059 | either regno or valueno, return 0 now. | |
6060 | If GOAL is a memory ref and its address is not constant, | |
6061 | and this insn P increments a register used in GOAL, return 0. */ | |
6062 | { | |
6063 | register rtx link; | |
6064 | ||
6065 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
6066 | if (REG_NOTE_KIND (link) == REG_INC | |
6067 | && GET_CODE (XEXP (link, 0)) == REG) | |
6068 | { | |
6069 | register int incno = REGNO (XEXP (link, 0)); | |
6070 | if (incno < regno + nregs && incno >= regno) | |
6071 | return 0; | |
6072 | if (incno < valueno + valuenregs && incno >= valueno) | |
6073 | return 0; | |
6074 | if (goal_mem_addr_varies | |
bfa30b22 RK |
6075 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
6076 | goal)) | |
eab89b90 RK |
6077 | return 0; |
6078 | } | |
6079 | } | |
6080 | #endif | |
6081 | } | |
6082 | } | |
6083 | } | |
6084 | \f | |
6085 | /* Find a place where INCED appears in an increment or decrement operator | |
6086 | within X, and return the amount INCED is incremented or decremented by. | |
6087 | The value is always positive. */ | |
6088 | ||
6089 | static int | |
6090 | find_inc_amount (x, inced) | |
6091 | rtx x, inced; | |
6092 | { | |
6093 | register enum rtx_code code = GET_CODE (x); | |
6094 | register char *fmt; | |
6095 | register int i; | |
6096 | ||
6097 | if (code == MEM) | |
6098 | { | |
6099 | register rtx addr = XEXP (x, 0); | |
6100 | if ((GET_CODE (addr) == PRE_DEC | |
6101 | || GET_CODE (addr) == POST_DEC | |
6102 | || GET_CODE (addr) == PRE_INC | |
6103 | || GET_CODE (addr) == POST_INC) | |
6104 | && XEXP (addr, 0) == inced) | |
6105 | return GET_MODE_SIZE (GET_MODE (x)); | |
6106 | } | |
6107 | ||
6108 | fmt = GET_RTX_FORMAT (code); | |
6109 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6110 | { | |
6111 | if (fmt[i] == 'e') | |
6112 | { | |
6113 | register int tem = find_inc_amount (XEXP (x, i), inced); | |
6114 | if (tem != 0) | |
6115 | return tem; | |
6116 | } | |
6117 | if (fmt[i] == 'E') | |
6118 | { | |
6119 | register int j; | |
6120 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6121 | { | |
6122 | register int tem = find_inc_amount (XVECEXP (x, i, j), inced); | |
6123 | if (tem != 0) | |
6124 | return tem; | |
6125 | } | |
6126 | } | |
6127 | } | |
6128 | ||
6129 | return 0; | |
6130 | } | |
6131 | \f | |
6132 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ | |
6133 | ||
6134 | int | |
6135 | regno_clobbered_p (regno, insn) | |
6136 | int regno; | |
6137 | rtx insn; | |
6138 | { | |
6139 | if (GET_CODE (PATTERN (insn)) == CLOBBER | |
6140 | && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) | |
6141 | return REGNO (XEXP (PATTERN (insn), 0)) == regno; | |
6142 | ||
6143 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
6144 | { | |
6145 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
6146 | ||
6147 | for (; i >= 0; i--) | |
6148 | { | |
6149 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
6150 | if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG | |
6151 | && REGNO (XEXP (elt, 0)) == regno) | |
6152 | return 1; | |
6153 | } | |
6154 | } | |
6155 | ||
6156 | return 0; | |
6157 | } | |
10bcde0d RK |
6158 | |
6159 | static char *reload_when_needed_name[] = | |
6160 | { | |
6161 | "RELOAD_FOR_INPUT", | |
6162 | "RELOAD_FOR_OUTPUT", | |
6163 | "RELOAD_FOR_INSN", | |
47c8cf91 ILT |
6164 | "RELOAD_FOR_INPUT_ADDRESS", |
6165 | "RELOAD_FOR_INPADDR_ADDRESS", | |
10bcde0d | 6166 | "RELOAD_FOR_OUTPUT_ADDRESS", |
47c8cf91 | 6167 | "RELOAD_FOR_OUTADDR_ADDRESS", |
10bcde0d RK |
6168 | "RELOAD_FOR_OPERAND_ADDRESS", |
6169 | "RELOAD_FOR_OPADDR_ADDR", | |
6170 | "RELOAD_OTHER", | |
6171 | "RELOAD_FOR_OTHER_ADDRESS" | |
6172 | }; | |
6173 | ||
6174 | static char *reg_class_names[] = REG_CLASS_NAMES; | |
6175 | ||
b8fb2d72 | 6176 | /* These functions are used to print the variables set by 'find_reloads' */ |
10bcde0d RK |
6177 | |
6178 | void | |
b8fb2d72 CI |
6179 | debug_reload_to_stream (f) |
6180 | FILE *f; | |
10bcde0d RK |
6181 | { |
6182 | int r; | |
505923a0 | 6183 | char *prefix; |
10bcde0d | 6184 | |
b8fb2d72 CI |
6185 | if (! f) |
6186 | f = stderr; | |
10bcde0d RK |
6187 | for (r = 0; r < n_reloads; r++) |
6188 | { | |
b8fb2d72 | 6189 | fprintf (f, "Reload %d: ", r); |
10bcde0d | 6190 | |
505923a0 | 6191 | if (reload_in[r] != 0) |
10bcde0d | 6192 | { |
b8fb2d72 | 6193 | fprintf (f, "reload_in (%s) = ", |
f7393e85 | 6194 | GET_MODE_NAME (reload_inmode[r])); |
b8fb2d72 CI |
6195 | print_inline_rtx (f, reload_in[r], 24); |
6196 | fprintf (f, "\n\t"); | |
10bcde0d RK |
6197 | } |
6198 | ||
505923a0 | 6199 | if (reload_out[r] != 0) |
10bcde0d | 6200 | { |
b8fb2d72 | 6201 | fprintf (f, "reload_out (%s) = ", |
f7393e85 | 6202 | GET_MODE_NAME (reload_outmode[r])); |
b8fb2d72 CI |
6203 | print_inline_rtx (f, reload_out[r], 24); |
6204 | fprintf (f, "\n\t"); | |
10bcde0d RK |
6205 | } |
6206 | ||
b8fb2d72 | 6207 | fprintf (f, "%s, ", reg_class_names[(int) reload_reg_class[r]]); |
10bcde0d | 6208 | |
b8fb2d72 | 6209 | fprintf (f, "%s (opnum = %d)", |
505923a0 | 6210 | reload_when_needed_name[(int) reload_when_needed[r]], |
10bcde0d RK |
6211 | reload_opnum[r]); |
6212 | ||
6213 | if (reload_optional[r]) | |
b8fb2d72 | 6214 | fprintf (f, ", optional"); |
10bcde0d | 6215 | |
505923a0 | 6216 | if (reload_inc[r] != 0) |
b8fb2d72 | 6217 | fprintf (f, ", inc by %d", reload_inc[r]); |
10bcde0d RK |
6218 | |
6219 | if (reload_nocombine[r]) | |
b8fb2d72 | 6220 | fprintf (f, ", can't combine"); |
10bcde0d RK |
6221 | |
6222 | if (reload_secondary_p[r]) | |
b8fb2d72 | 6223 | fprintf (f, ", secondary_reload_p"); |
10bcde0d | 6224 | |
505923a0 | 6225 | if (reload_in_reg[r] != 0) |
10bcde0d | 6226 | { |
b8fb2d72 CI |
6227 | fprintf (f, "\n\treload_in_reg: "); |
6228 | print_inline_rtx (f, reload_in_reg[r], 24); | |
10bcde0d RK |
6229 | } |
6230 | ||
505923a0 | 6231 | if (reload_reg_rtx[r] != 0) |
10bcde0d | 6232 | { |
b8fb2d72 CI |
6233 | fprintf (f, "\n\treload_reg_rtx: "); |
6234 | print_inline_rtx (f, reload_reg_rtx[r], 24); | |
10bcde0d RK |
6235 | } |
6236 | ||
505923a0 | 6237 | prefix = "\n\t"; |
10bcde0d RK |
6238 | if (reload_secondary_in_reload[r] != -1) |
6239 | { | |
b8fb2d72 | 6240 | fprintf (f, "%ssecondary_in_reload = %d", |
505923a0 RK |
6241 | prefix, reload_secondary_in_reload[r]); |
6242 | prefix = ", "; | |
10bcde0d RK |
6243 | } |
6244 | ||
6245 | if (reload_secondary_out_reload[r] != -1) | |
b8fb2d72 | 6246 | fprintf (f, "%ssecondary_out_reload = %d\n", |
505923a0 | 6247 | prefix, reload_secondary_out_reload[r]); |
10bcde0d | 6248 | |
505923a0 | 6249 | prefix = "\n\t"; |
10bcde0d RK |
6250 | if (reload_secondary_in_icode[r] != CODE_FOR_nothing) |
6251 | { | |
b8fb2d72 | 6252 | fprintf (f, "%ssecondary_in_icode = %s", prefix, insn_name[r]); |
505923a0 | 6253 | prefix = ", "; |
10bcde0d RK |
6254 | } |
6255 | ||
6256 | if (reload_secondary_out_icode[r] != CODE_FOR_nothing) | |
b8fb2d72 | 6257 | fprintf (f, "%ssecondary_out_icode = %s", prefix, insn_name[r]); |
10bcde0d | 6258 | |
b8fb2d72 | 6259 | fprintf (f, "\n"); |
10bcde0d | 6260 | } |
10bcde0d | 6261 | } |
b8fb2d72 CI |
6262 | |
6263 | void | |
6264 | debug_reload () | |
6265 | { | |
6266 | debug_reload_to_stream (stderr); | |
6267 | } |