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eab89b90 | 1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
f55b1d97 | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. |
eab89b90 RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | /* This file contains subroutines used only from the file reload1.c. | |
22 | It knows how to scan one insn for operands and values | |
23 | that need to be copied into registers to make valid code. | |
24 | It also finds other operands and values which are valid | |
25 | but for which equivalent values in registers exist and | |
26 | ought to be used instead. | |
27 | ||
28 | Before processing the first insn of the function, call `init_reload'. | |
29 | ||
30 | To scan an insn, call `find_reloads'. This does two things: | |
31 | 1. sets up tables describing which values must be reloaded | |
32 | for this insn, and what kind of hard regs they must be reloaded into; | |
33 | 2. optionally record the locations where those values appear in | |
34 | the data, so they can be replaced properly later. | |
35 | This is done only if the second arg to `find_reloads' is nonzero. | |
36 | ||
37 | The third arg to `find_reloads' specifies the number of levels | |
38 | of indirect addressing supported by the machine. If it is zero, | |
39 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
40 | is valid even if (REG n) did not get a hard register; if it is two, | |
41 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
42 | hard register, and similarly for higher values. | |
43 | ||
44 | Then you must choose the hard regs to reload those pseudo regs into, | |
45 | and generate appropriate load insns before this insn and perhaps | |
46 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
47 | to contain the REG rtx's for the registers you used. In some | |
48 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
49 | for certain reloads. Then that tells you which register to use, | |
50 | so you do not need to allocate one. But you still do need to add extra | |
51 | instructions to copy the value into and out of that register. | |
52 | ||
53 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
54 | into the locations already recorded. | |
55 | ||
56 | NOTE SIDE EFFECTS: | |
57 | ||
58 | find_reloads can alter the operands of the instruction it is called on. | |
59 | ||
60 | 1. Two operands of any sort may be interchanged, if they are in a | |
61 | commutative instruction. | |
62 | This happens only if find_reloads thinks the instruction will compile | |
63 | better that way. | |
64 | ||
65 | 2. Pseudo-registers that are equivalent to constants are replaced | |
66 | with those constants if they are not in hard registers. | |
67 | ||
68 | 1 happens every time find_reloads is called. | |
69 | 2 happens only when REPLACE is 1, which is only when | |
70 | actually doing the reloads, not when just counting them. | |
71 | ||
72 | ||
73 | Using a reload register for several reloads in one insn: | |
74 | ||
75 | When an insn has reloads, it is considered as having three parts: | |
76 | the input reloads, the insn itself after reloading, and the output reloads. | |
77 | Reloads of values used in memory addresses are often needed for only one part. | |
78 | ||
79 | When this is so, reload_when_needed records which part needs the reload. | |
80 | Two reloads for different parts of the insn can share the same reload | |
81 | register. | |
82 | ||
83 | When a reload is used for addresses in multiple parts, or when it is | |
84 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
85 | a register with any other reload. */ | |
86 | ||
87 | #define REG_OK_STRICT | |
88 | ||
89 | #include "config.h" | |
90 | #include "rtl.h" | |
91 | #include "insn-config.h" | |
92 | #include "insn-codes.h" | |
93 | #include "recog.h" | |
94 | #include "reload.h" | |
95 | #include "regs.h" | |
96 | #include "hard-reg-set.h" | |
97 | #include "flags.h" | |
98 | #include "real.h" | |
99 | ||
100 | #ifndef REGISTER_MOVE_COST | |
101 | #define REGISTER_MOVE_COST(x, y) 2 | |
102 | #endif | |
103 | \f | |
104 | /* The variables set up by `find_reloads' are: | |
105 | ||
106 | n_reloads number of distinct reloads needed; max reload # + 1 | |
107 | tables indexed by reload number | |
108 | reload_in rtx for value to reload from | |
109 | reload_out rtx for where to store reload-reg afterward if nec | |
110 | (often the same as reload_in) | |
111 | reload_reg_class enum reg_class, saying what regs to reload into | |
112 | reload_inmode enum machine_mode; mode this operand should have | |
113 | when reloaded, on input. | |
114 | reload_outmode enum machine_mode; mode this operand should have | |
115 | when reloaded, on output. | |
eab89b90 RK |
116 | reload_optional char, nonzero for an optional reload. |
117 | Optional reloads are ignored unless the | |
118 | value is already sitting in a register. | |
119 | reload_inc int, positive amount to increment or decrement by if | |
120 | reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC. | |
121 | Ignored otherwise (don't assume it is zero). | |
122 | reload_in_reg rtx. A reg for which reload_in is the equivalent. | |
123 | If reload_in is a symbol_ref which came from | |
124 | reg_equiv_constant, then this is the pseudo | |
125 | which has that symbol_ref as equivalent. | |
126 | reload_reg_rtx rtx. This is the register to reload into. | |
127 | If it is zero when `find_reloads' returns, | |
128 | you must find a suitable register in the class | |
129 | specified by reload_reg_class, and store here | |
130 | an rtx for that register with mode from | |
131 | reload_inmode or reload_outmode. | |
132 | reload_nocombine char, nonzero if this reload shouldn't be | |
133 | combined with another reload. | |
a8c9daeb RK |
134 | reload_opnum int, operand number being reloaded. This is |
135 | used to group related reloads and need not always | |
136 | be equal to the actual operand number in the insn, | |
137 | though it current will be; for in-out operands, it | |
138 | is one of the two operand numbers. | |
139 | reload_when_needed enum, classifies reload as needed either for | |
eab89b90 RK |
140 | addressing an input reload, addressing an output, |
141 | for addressing a non-reloaded mem ref, | |
142 | or for unspecified purposes (i.e., more than one | |
143 | of the above). | |
144 | reload_secondary_reload int, gives the reload number of a secondary | |
145 | reload, when needed; otherwise -1 | |
146 | reload_secondary_p int, 1 if this is a secondary register for one | |
147 | or more reloads. | |
148 | reload_secondary_icode enum insn_code, if a secondary reload is required, | |
149 | gives the INSN_CODE that uses the secondary | |
150 | reload as a scratch register, or CODE_FOR_nothing | |
151 | if the secondary reload register is to be an | |
152 | intermediate register. */ | |
153 | int n_reloads; | |
154 | ||
155 | rtx reload_in[MAX_RELOADS]; | |
156 | rtx reload_out[MAX_RELOADS]; | |
157 | enum reg_class reload_reg_class[MAX_RELOADS]; | |
158 | enum machine_mode reload_inmode[MAX_RELOADS]; | |
159 | enum machine_mode reload_outmode[MAX_RELOADS]; | |
eab89b90 RK |
160 | rtx reload_reg_rtx[MAX_RELOADS]; |
161 | char reload_optional[MAX_RELOADS]; | |
162 | int reload_inc[MAX_RELOADS]; | |
163 | rtx reload_in_reg[MAX_RELOADS]; | |
164 | char reload_nocombine[MAX_RELOADS]; | |
a8c9daeb RK |
165 | int reload_opnum[MAX_RELOADS]; |
166 | enum reload_type reload_when_needed[MAX_RELOADS]; | |
eab89b90 RK |
167 | int reload_secondary_reload[MAX_RELOADS]; |
168 | int reload_secondary_p[MAX_RELOADS]; | |
169 | enum insn_code reload_secondary_icode[MAX_RELOADS]; | |
170 | ||
171 | /* All the "earlyclobber" operands of the current insn | |
172 | are recorded here. */ | |
173 | int n_earlyclobbers; | |
174 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
175 | ||
a8c9daeb RK |
176 | int reload_n_operands; |
177 | ||
eab89b90 RK |
178 | /* Replacing reloads. |
179 | ||
180 | If `replace_reloads' is nonzero, then as each reload is recorded | |
181 | an entry is made for it in the table `replacements'. | |
182 | Then later `subst_reloads' can look through that table and | |
183 | perform all the replacements needed. */ | |
184 | ||
185 | /* Nonzero means record the places to replace. */ | |
186 | static int replace_reloads; | |
187 | ||
188 | /* Each replacement is recorded with a structure like this. */ | |
189 | struct replacement | |
190 | { | |
191 | rtx *where; /* Location to store in */ | |
192 | rtx *subreg_loc; /* Location of SUBREG if WHERE is inside | |
193 | a SUBREG; 0 otherwise. */ | |
194 | int what; /* which reload this is for */ | |
195 | enum machine_mode mode; /* mode it must have */ | |
196 | }; | |
197 | ||
198 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
199 | ||
200 | /* Number of replacements currently recorded. */ | |
201 | static int n_replacements; | |
202 | ||
a8c9daeb RK |
203 | /* Used to track what is modified by an operand. */ |
204 | struct decomposition | |
205 | { | |
206 | int reg_flag; /* Nonzero if referencing a register. */ | |
207 | int safe; /* Nonzero if this can't conflict with anything. */ | |
208 | rtx base; /* Base adddress for MEM. */ | |
209 | HOST_WIDE_INT start; /* Starting offset or register number. */ | |
210 | HOST_WIDE_INT end; /* Endinf offset or register number. */ | |
211 | }; | |
212 | ||
eab89b90 RK |
213 | /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable; |
214 | (see reg_equiv_address). */ | |
215 | static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
216 | static int n_memlocs; | |
217 | ||
0dadecf6 RK |
218 | #ifdef SECONDARY_MEMORY_NEEDED |
219 | ||
220 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
221 | is used per mode, but normally only one or two modes are ever used. | |
222 | ||
a8c9daeb RK |
223 | We keep two versions, before and after register elimination. The one |
224 | after register elimination is record separately for each operand. This | |
225 | is done in case the address is not valid to be sure that we separately | |
226 | reload each. */ | |
0dadecf6 RK |
227 | |
228 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
77545d45 | 229 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; |
0dadecf6 RK |
230 | #endif |
231 | ||
eab89b90 RK |
232 | /* The instruction we are doing reloads for; |
233 | so we can test whether a register dies in it. */ | |
234 | static rtx this_insn; | |
235 | ||
236 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
237 | static int this_insn_is_asm; | |
238 | ||
239 | /* If hard_regs_live_known is nonzero, | |
240 | we can tell which hard regs are currently live, | |
241 | at least enough to succeed in choosing dummy reloads. */ | |
242 | static int hard_regs_live_known; | |
243 | ||
244 | /* Indexed by hard reg number, | |
245 | element is nonegative if hard reg has been spilled. | |
246 | This vector is passed to `find_reloads' as an argument | |
247 | and is not changed here. */ | |
248 | static short *static_reload_reg_p; | |
249 | ||
250 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
251 | static int subst_reg_equivs_changed; | |
252 | ||
253 | /* On return from push_reload, holds the reload-number for the OUT | |
254 | operand, which can be different for that from the input operand. */ | |
255 | static int output_reloadnum; | |
256 | ||
a8c9daeb RK |
257 | static enum reg_class find_secondary_reload PROTO((rtx, enum reg_class, |
258 | enum machine_mode, int, | |
259 | enum insn_code *, | |
260 | enum machine_mode *, | |
261 | enum reg_class *, | |
262 | enum insn_code *, | |
263 | enum machine_mode *)); | |
264 | static int push_reload PROTO((rtx, rtx, rtx *, rtx *, enum reg_class, | |
265 | enum machine_mode, enum machine_mode, | |
266 | int, int, int, enum reload_type)); | |
267 | static void push_replacement PROTO((rtx *, int, enum machine_mode)); | |
268 | static void combine_reloads PROTO((void)); | |
269 | static rtx find_dummy_reload PROTO((rtx, rtx, rtx *, rtx *, | |
270 | enum reg_class, int)); | |
271 | static int hard_reg_set_here_p PROTO((int, int, rtx)); | |
272 | static struct decomposition decompose PROTO((rtx)); | |
273 | static int immune_p PROTO((rtx, rtx, struct decomposition)); | |
274 | static int alternative_allows_memconst PROTO((char *, int)); | |
275 | static rtx find_reloads_toplev PROTO((rtx, int, enum reload_type, int, int)); | |
276 | static rtx make_memloc PROTO((rtx, int)); | |
277 | static int find_reloads_address PROTO((enum machine_mode, rtx *, rtx, rtx *, | |
278 | int, enum reload_type, int)); | |
279 | static rtx subst_reg_equivs PROTO((rtx)); | |
280 | static rtx subst_indexed_address PROTO((rtx)); | |
281 | static int find_reloads_address_1 PROTO((rtx, int, rtx *, int, | |
282 | enum reload_type,int)); | |
283 | static void find_reloads_address_part PROTO((rtx, rtx *, enum reg_class, | |
284 | enum machine_mode, int, | |
285 | enum reload_type, int)); | |
286 | static int find_inc_amount PROTO((rtx, rtx)); | |
eab89b90 RK |
287 | \f |
288 | #ifdef HAVE_SECONDARY_RELOADS | |
289 | ||
290 | /* Determine if any secondary reloads are needed for loading (if IN_P is | |
291 | non-zero) or storing (if IN_P is zero) X to or from a reload register of | |
292 | register class RELOAD_CLASS in mode RELOAD_MODE. | |
293 | ||
294 | Return the register class of a secondary reload register, or NO_REGS if | |
295 | none. *PMODE is set to the mode that the register is required in. | |
296 | If the reload register is needed as a scratch register instead of an | |
297 | intermediate register, *PICODE is set to the insn_code of the insn to be | |
298 | used to load or store the primary reload register; otherwise *PICODE | |
299 | is set to CODE_FOR_nothing. | |
300 | ||
301 | In some cases (such as storing MQ into an external memory location on | |
302 | the RT), both an intermediate register and a scratch register. In that | |
303 | case, *PICODE is set to CODE_FOR_nothing, the class for the intermediate | |
304 | register is returned, and the *PTERTIARY_... variables are set to describe | |
305 | the scratch register. */ | |
306 | ||
307 | static enum reg_class | |
308 | find_secondary_reload (x, reload_class, reload_mode, in_p, picode, pmode, | |
309 | ptertiary_class, ptertiary_icode, ptertiary_mode) | |
310 | rtx x; | |
311 | enum reg_class reload_class; | |
312 | enum machine_mode reload_mode; | |
313 | int in_p; | |
314 | enum insn_code *picode; | |
315 | enum machine_mode *pmode; | |
316 | enum reg_class *ptertiary_class; | |
317 | enum insn_code *ptertiary_icode; | |
318 | enum machine_mode *ptertiary_mode; | |
319 | { | |
320 | enum reg_class class = NO_REGS; | |
321 | enum machine_mode mode = reload_mode; | |
322 | enum insn_code icode = CODE_FOR_nothing; | |
323 | enum reg_class t_class = NO_REGS; | |
324 | enum machine_mode t_mode = VOIDmode; | |
325 | enum insn_code t_icode = CODE_FOR_nothing; | |
326 | ||
d45cf215 RS |
327 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
328 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
329 | but we don't want to assume that), use that equivalent when seeing if | |
330 | a secondary reload is needed since whether or not a reload is needed | |
331 | might be sensitive to the form of the MEM. */ | |
332 | ||
333 | if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
334 | && reg_equiv_mem[REGNO (x)] != 0) | |
335 | x = reg_equiv_mem[REGNO (x)]; | |
336 | ||
eab89b90 RK |
337 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
338 | if (in_p) | |
339 | class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
340 | #endif | |
341 | ||
342 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
343 | if (! in_p) | |
344 | class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
345 | #endif | |
346 | ||
347 | /* If we don't need any secondary registers, go away; the rest of the | |
348 | values won't be used. */ | |
349 | if (class == NO_REGS) | |
350 | return NO_REGS; | |
351 | ||
352 | /* Get a possible insn to use. If the predicate doesn't accept X, don't | |
353 | use the insn. */ | |
354 | ||
355 | icode = (in_p ? reload_in_optab[(int) reload_mode] | |
356 | : reload_out_optab[(int) reload_mode]); | |
357 | ||
358 | if (icode != CODE_FOR_nothing | |
359 | && insn_operand_predicate[(int) icode][in_p] | |
360 | && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode))) | |
361 | icode = CODE_FOR_nothing; | |
362 | ||
363 | /* If we will be using an insn, see if it can directly handle the reload | |
364 | register we will be using. If it can, the secondary reload is for a | |
365 | scratch register. If it can't, we will use the secondary reload for | |
366 | an intermediate register and require a tertiary reload for the scratch | |
367 | register. */ | |
368 | ||
369 | if (icode != CODE_FOR_nothing) | |
370 | { | |
371 | /* If IN_P is non-zero, the reload register will be the output in | |
372 | operand 0. If IN_P is zero, the reload register will be the input | |
373 | in operand 1. Outputs should have an initial "=", which we must | |
374 | skip. */ | |
375 | ||
d45cf215 | 376 | char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p]; |
eab89b90 | 377 | enum reg_class insn_class |
d45cf215 RS |
378 | = (insn_letter == 'r' ? GENERAL_REGS |
379 | : REG_CLASS_FROM_LETTER (insn_letter)); | |
eab89b90 RK |
380 | |
381 | if (insn_class == NO_REGS | |
382 | || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=') | |
383 | /* The scratch register's constraint must start with "=&". */ | |
384 | || insn_operand_constraint[(int) icode][2][0] != '=' | |
385 | || insn_operand_constraint[(int) icode][2][1] != '&') | |
386 | abort (); | |
387 | ||
388 | if (reg_class_subset_p (reload_class, insn_class)) | |
389 | mode = insn_operand_mode[(int) icode][2]; | |
390 | else | |
391 | { | |
d45cf215 | 392 | char t_letter = insn_operand_constraint[(int) icode][2][2]; |
eab89b90 RK |
393 | class = insn_class; |
394 | t_mode = insn_operand_mode[(int) icode][2]; | |
d45cf215 RS |
395 | t_class = (t_letter == 'r' ? GENERAL_REGS |
396 | : REG_CLASS_FROM_LETTER (t_letter)); | |
eab89b90 RK |
397 | t_icode = icode; |
398 | icode = CODE_FOR_nothing; | |
399 | } | |
400 | } | |
401 | ||
402 | *pmode = mode; | |
403 | *picode = icode; | |
404 | *ptertiary_class = t_class; | |
405 | *ptertiary_mode = t_mode; | |
406 | *ptertiary_icode = t_icode; | |
407 | ||
408 | return class; | |
409 | } | |
410 | #endif /* HAVE_SECONDARY_RELOADS */ | |
411 | \f | |
0dadecf6 RK |
412 | #ifdef SECONDARY_MEMORY_NEEDED |
413 | ||
414 | /* Return a memory location that will be used to copy X in mode MODE. | |
415 | If we haven't already made a location for this mode in this insn, | |
416 | call find_reloads_address on the location being returned. */ | |
417 | ||
418 | rtx | |
a8c9daeb | 419 | get_secondary_mem (x, mode, opnum, type) |
0dadecf6 RK |
420 | rtx x; |
421 | enum machine_mode mode; | |
a8c9daeb RK |
422 | int opnum; |
423 | enum reload_type type; | |
0dadecf6 RK |
424 | { |
425 | rtx loc; | |
426 | int mem_valid; | |
427 | ||
428 | /* If MODE is narrower than a word, widen it. This is required because | |
429 | most machines that require these memory locations do not support | |
430 | short load and stores from all registers (e.g., FP registers). We could | |
431 | possibly conditionalize this, but we lose nothing by doing the wider | |
432 | mode. */ | |
433 | ||
434 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD) | |
435 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); | |
436 | ||
77545d45 RK |
437 | /* If we already have made a MEM for this operand in MODE, return it. */ |
438 | if (secondary_memlocs_elim[(int) mode][opnum] != 0) | |
439 | return secondary_memlocs_elim[(int) mode][opnum]; | |
0dadecf6 RK |
440 | |
441 | /* If this is the first time we've tried to get a MEM for this mode, | |
442 | allocate a new one. `something_changed' in reload will get set | |
443 | by noticing that the frame size has changed. */ | |
444 | ||
445 | if (secondary_memlocs[(int) mode] == 0) | |
b24a53d5 JW |
446 | { |
447 | #ifdef SECONDARY_MEMORY_NEEDED_RTX | |
448 | secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); | |
449 | #else | |
450 | secondary_memlocs[(int) mode] | |
451 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
452 | #endif | |
453 | } | |
0dadecf6 RK |
454 | |
455 | /* Get a version of the address doing any eliminations needed. If that | |
456 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
457 | ||
a8c9daeb | 458 | loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); |
0dadecf6 RK |
459 | mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); |
460 | ||
461 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
462 | loc = copy_rtx (loc); | |
463 | ||
464 | /* The only time the call below will do anything is if the stack | |
465 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
a8c9daeb RK |
466 | can just pass a zero. Adjust the type to be the address of the |
467 | corresponding object. If the address was valid, save the eliminated | |
468 | address. If it wasn't valid, we need to make a reload each time, so | |
469 | don't save it. */ | |
0dadecf6 | 470 | |
a8c9daeb RK |
471 | if (! mem_valid) |
472 | { | |
473 | type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
474 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
475 | : RELOAD_OTHER); | |
8d618585 | 476 | |
a8c9daeb RK |
477 | find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), |
478 | opnum, type, 0); | |
479 | } | |
0dadecf6 | 480 | |
77545d45 | 481 | secondary_memlocs_elim[(int) mode][opnum] = loc; |
0dadecf6 RK |
482 | return loc; |
483 | } | |
484 | ||
485 | /* Clear any secondary memory locations we've made. */ | |
486 | ||
487 | void | |
488 | clear_secondary_mem () | |
489 | { | |
77545d45 | 490 | bzero (secondary_memlocs, sizeof secondary_memlocs); |
0dadecf6 RK |
491 | } |
492 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
493 | \f | |
a8c9daeb | 494 | /* Record one reload that needs to be performed. |
eab89b90 RK |
495 | IN is an rtx saying where the data are to be found before this instruction. |
496 | OUT says where they must be stored after the instruction. | |
497 | (IN is zero for data not read, and OUT is zero for data not written.) | |
498 | INLOC and OUTLOC point to the places in the instructions where | |
499 | IN and OUT were found. | |
a8c9daeb RK |
500 | If IN and OUT are both non-zero, it means the same register must be used |
501 | to reload both IN and OUT. | |
502 | ||
eab89b90 RK |
503 | CLASS is a register class required for the reloaded data. |
504 | INMODE is the machine mode that the instruction requires | |
505 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
506 | ||
507 | If IN is zero, then OUT's location and mode should be passed as | |
508 | INLOC and INMODE. | |
509 | ||
510 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
511 | ||
512 | OPTIONAL nonzero means this reload does not need to be performed: | |
513 | it can be discarded if that is more convenient. | |
514 | ||
a8c9daeb RK |
515 | OPNUM and TYPE say what the purpose of this reload is. |
516 | ||
eab89b90 RK |
517 | The return value is the reload-number for this reload. |
518 | ||
519 | If both IN and OUT are nonzero, in some rare cases we might | |
520 | want to make two separate reloads. (Actually we never do this now.) | |
521 | Therefore, the reload-number for OUT is stored in | |
522 | output_reloadnum when we return; the return value applies to IN. | |
523 | Usually (presently always), when IN and OUT are nonzero, | |
524 | the two reload-numbers are equal, but the caller should be careful to | |
525 | distinguish them. */ | |
526 | ||
527 | static int | |
528 | push_reload (in, out, inloc, outloc, class, | |
a8c9daeb | 529 | inmode, outmode, strict_low, optional, opnum, type) |
eab89b90 RK |
530 | register rtx in, out; |
531 | rtx *inloc, *outloc; | |
532 | enum reg_class class; | |
533 | enum machine_mode inmode, outmode; | |
534 | int strict_low; | |
535 | int optional; | |
a8c9daeb RK |
536 | int opnum; |
537 | enum reload_type type; | |
eab89b90 RK |
538 | { |
539 | register int i; | |
540 | int dont_share = 0; | |
541 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; | |
542 | int secondary_reload = -1; | |
543 | enum insn_code secondary_icode = CODE_FOR_nothing; | |
544 | ||
545 | /* Compare two RTX's. */ | |
546 | #define MATCHES(x, y) \ | |
547 | (x == y || (x != 0 && (GET_CODE (x) == REG \ | |
548 | ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \ | |
549 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) | |
550 | ||
a8c9daeb RK |
551 | /* Indicates if two reloads purposes are for similar enough things that we |
552 | can merge their reloads. */ | |
553 | #define MERGABLE_RELOADS(when1, when2, op1, op2) \ | |
554 | ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ | |
555 | || ((when1) == (when2) && (op1) == (op2)) \ | |
556 | || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ | |
557 | || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
558 | && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ | |
559 | || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ | |
560 | && (when2) == RELOAD_FOR_OTHER_ADDRESS)) | |
561 | ||
562 | /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ | |
563 | #define MERGE_TO_OTHER(when1, when2, op1, op2) \ | |
564 | ((when1) != (when2) \ | |
565 | || ! ((op1) == (op2) \ | |
566 | || (when1) == RELOAD_FOR_INPUT \ | |
567 | || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
568 | || (when1) == RELOAD_FOR_OTHER_ADDRESS)) | |
569 | ||
eab89b90 RK |
570 | /* INMODE and/or OUTMODE could be VOIDmode if no mode |
571 | has been specified for the operand. In that case, | |
572 | use the operand's mode as the mode to reload. */ | |
573 | if (inmode == VOIDmode && in != 0) | |
574 | inmode = GET_MODE (in); | |
575 | if (outmode == VOIDmode && out != 0) | |
576 | outmode = GET_MODE (out); | |
577 | ||
578 | /* If IN is a pseudo register everywhere-equivalent to a constant, and | |
579 | it is not in a hard register, reload straight from the constant, | |
580 | since we want to get rid of such pseudo registers. | |
581 | Often this is done earlier, but not always in find_reloads_address. */ | |
582 | if (in != 0 && GET_CODE (in) == REG) | |
583 | { | |
584 | register int regno = REGNO (in); | |
585 | ||
586 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
587 | && reg_equiv_constant[regno] != 0) | |
588 | in = reg_equiv_constant[regno]; | |
589 | } | |
590 | ||
591 | /* Likewise for OUT. Of course, OUT will never be equivalent to | |
592 | an actual constant, but it might be equivalent to a memory location | |
593 | (in the case of a parameter). */ | |
594 | if (out != 0 && GET_CODE (out) == REG) | |
595 | { | |
596 | register int regno = REGNO (out); | |
597 | ||
598 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
599 | && reg_equiv_constant[regno] != 0) | |
600 | out = reg_equiv_constant[regno]; | |
601 | } | |
602 | ||
603 | /* If we have a read-write operand with an address side-effect, | |
604 | change either IN or OUT so the side-effect happens only once. */ | |
605 | if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out)) | |
606 | { | |
607 | if (GET_CODE (XEXP (in, 0)) == POST_INC | |
608 | || GET_CODE (XEXP (in, 0)) == POST_DEC) | |
609 | in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0)); | |
610 | if (GET_CODE (XEXP (in, 0)) == PRE_INC | |
611 | || GET_CODE (XEXP (in, 0)) == PRE_DEC) | |
612 | out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0)); | |
613 | } | |
614 | ||
615 | /* If we are reloading a (SUBREG (MEM ...) ...) or (SUBREG constant ...), | |
616 | really reload just the inside expression in its own mode. | |
617 | If we have (SUBREG:M1 (REG:M2 ...) ...) with M1 wider than M2 and the | |
618 | register is a pseudo, this will become the same as the above case. | |
f72ccbe6 RK |
619 | For machines that extend byte loads, do this for any SUBREG of a pseudo |
620 | where both M1 and M2 are a word or smaller. | |
86c31b2d | 621 | Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
eab89b90 RK |
622 | either M1 is not valid for R or M2 is wider than a word but we only |
623 | need one word to store an M2-sized quantity in R. | |
86c31b2d RS |
624 | (However, if OUT is nonzero, we need to reload the reg *and* |
625 | the subreg, so do nothing here, and let following statement handle it.) | |
626 | ||
eab89b90 RK |
627 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; |
628 | we can't handle it here because CONST_INT does not indicate a mode. | |
629 | ||
630 | Similarly, we must reload the inside expression if we have a | |
df62f951 RK |
631 | STRICT_LOW_PART (presumably, in == out in the cas). |
632 | ||
633 | Also reload the inner expression if it does not require a secondary | |
634 | reload but the SUBREG does. */ | |
eab89b90 RK |
635 | |
636 | if (in != 0 && GET_CODE (in) == SUBREG | |
637 | && (GET_CODE (SUBREG_REG (in)) != REG | |
638 | || strict_low | |
639 | || (GET_CODE (SUBREG_REG (in)) == REG | |
640 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
641 | #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) |
642 | && GET_MODE_SIZE (inmode) <= UNITS_PER_WORD | |
643 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) <= UNITS_PER_WORD | |
644 | #else | |
eab89b90 | 645 | && (GET_MODE_SIZE (inmode) |
f72ccbe6 RK |
646 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) |
647 | #endif | |
648 | ) | |
86c31b2d RS |
649 | || (REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
650 | /* The case where out is nonzero | |
651 | is handled differently in the following statement. */ | |
652 | && (out == 0 || SUBREG_WORD (in) == 0) | |
f72ccbe6 RK |
653 | && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
654 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
655 | > UNITS_PER_WORD) | |
656 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
657 | / UNITS_PER_WORD) | |
658 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
659 | GET_MODE (SUBREG_REG (in))))) | |
660 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (in)) | |
661 | + SUBREG_WORD (in)), | |
662 | inmode))) | |
df62f951 RK |
663 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
664 | || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS | |
665 | && (SECONDARY_INPUT_RELOAD_CLASS (class, | |
666 | GET_MODE (SUBREG_REG (in)), | |
667 | SUBREG_REG (in)) | |
668 | == NO_REGS)) | |
669 | #endif | |
670 | )) | |
eab89b90 RK |
671 | { |
672 | in_subreg_loc = inloc; | |
673 | inloc = &SUBREG_REG (in); | |
674 | in = *inloc; | |
e05a9da8 | 675 | #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND) |
eab89b90 RK |
676 | if (GET_CODE (in) == MEM) |
677 | /* This is supposed to happen only for paradoxical subregs made by | |
678 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
679 | if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode)) | |
680 | abort (); | |
e05a9da8 | 681 | #endif |
eab89b90 RK |
682 | inmode = GET_MODE (in); |
683 | } | |
684 | ||
86c31b2d RS |
685 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
686 | either M1 is not valid for R or M2 is wider than a word but we only | |
687 | need one word to store an M2-sized quantity in R. | |
688 | ||
689 | However, we must reload the inner reg *as well as* the subreg in | |
690 | that case. */ | |
691 | ||
692 | if (in != 0 && GET_CODE (in) == SUBREG | |
693 | && GET_CODE (SUBREG_REG (in)) == REG | |
694 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
695 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode) | |
696 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD | |
697 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
698 | > UNITS_PER_WORD) | |
699 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
700 | / UNITS_PER_WORD) | |
701 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
702 | GET_MODE (SUBREG_REG (in))))))) | |
703 | { | |
704 | push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), NULL_PTR, | |
705 | GENERAL_REGS, VOIDmode, VOIDmode, 0, 0, opnum, type); | |
706 | } | |
707 | ||
708 | ||
eab89b90 RK |
709 | /* Similarly for paradoxical and problematical SUBREGs on the output. |
710 | Note that there is no reason we need worry about the previous value | |
711 | of SUBREG_REG (out); even if wider than out, | |
712 | storing in a subreg is entitled to clobber it all | |
713 | (except in the case of STRICT_LOW_PART, | |
714 | and in that case the constraint should label it input-output.) */ | |
715 | if (out != 0 && GET_CODE (out) == SUBREG | |
716 | && (GET_CODE (SUBREG_REG (out)) != REG | |
717 | || strict_low | |
718 | || (GET_CODE (SUBREG_REG (out)) == REG | |
719 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
720 | #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) |
721 | && GET_MODE_SIZE (outmode) <= UNITS_PER_WORD | |
722 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) <= UNITS_PER_WORD | |
723 | #else | |
eab89b90 | 724 | && (GET_MODE_SIZE (outmode) |
f72ccbe6 RK |
725 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) |
726 | #endif | |
727 | ) | |
eab89b90 RK |
728 | || (GET_CODE (SUBREG_REG (out)) == REG |
729 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
730 | && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
731 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
732 | > UNITS_PER_WORD) | |
733 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
734 | / UNITS_PER_WORD) | |
735 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
736 | GET_MODE (SUBREG_REG (out))))) | |
737 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (out)) | |
738 | + SUBREG_WORD (out)), | |
739 | outmode))) | |
df62f951 RK |
740 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
741 | || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS | |
742 | && (SECONDARY_OUTPUT_RELOAD_CLASS (class, | |
743 | GET_MODE (SUBREG_REG (out)), | |
744 | SUBREG_REG (out)) | |
745 | == NO_REGS)) | |
746 | #endif | |
747 | )) | |
eab89b90 RK |
748 | { |
749 | out_subreg_loc = outloc; | |
750 | outloc = &SUBREG_REG (out); | |
e05a9da8 RS |
751 | out = *outloc; |
752 | #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND) | |
753 | if (GET_CODE (out) == MEM | |
eab89b90 RK |
754 | && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode)) |
755 | abort (); | |
e05a9da8 | 756 | #endif |
eab89b90 RK |
757 | outmode = GET_MODE (out); |
758 | } | |
759 | ||
eab89b90 RK |
760 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ |
761 | if (in != 0 && out != 0 && GET_CODE (out) == MEM | |
762 | && (GET_CODE (in) == REG || GET_CODE (in) == MEM) | |
bfa30b22 | 763 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
eab89b90 RK |
764 | dont_share = 1; |
765 | ||
0dadecf6 RK |
766 | /* If IN is a SUBREG of a hard register, make a new REG. This |
767 | simplifies some of the cases below. */ | |
768 | ||
769 | if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG | |
770 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER) | |
771 | in = gen_rtx (REG, GET_MODE (in), | |
772 | REGNO (SUBREG_REG (in)) + SUBREG_WORD (in)); | |
773 | ||
774 | /* Similarly for OUT. */ | |
775 | if (out != 0 && GET_CODE (out) == SUBREG | |
776 | && GET_CODE (SUBREG_REG (out)) == REG | |
777 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER) | |
778 | out = gen_rtx (REG, GET_MODE (out), | |
779 | REGNO (SUBREG_REG (out)) + SUBREG_WORD (out)); | |
780 | ||
eab89b90 RK |
781 | /* Narrow down the class of register wanted if that is |
782 | desirable on this machine for efficiency. */ | |
783 | if (in != 0) | |
784 | class = PREFERRED_RELOAD_CLASS (in, class); | |
785 | ||
ac2a9454 | 786 | /* Output reloads may need analogous treatment, different in detail. */ |
18a53b78 RS |
787 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS |
788 | if (out != 0) | |
789 | class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class); | |
790 | #endif | |
791 | ||
eab89b90 RK |
792 | /* Make sure we use a class that can handle the actual pseudo |
793 | inside any subreg. For example, on the 386, QImode regs | |
794 | can appear within SImode subregs. Although GENERAL_REGS | |
795 | can handle SImode, QImode needs a smaller class. */ | |
796 | #ifdef LIMIT_RELOAD_CLASS | |
797 | if (in_subreg_loc) | |
798 | class = LIMIT_RELOAD_CLASS (inmode, class); | |
799 | else if (in != 0 && GET_CODE (in) == SUBREG) | |
800 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); | |
801 | ||
802 | if (out_subreg_loc) | |
803 | class = LIMIT_RELOAD_CLASS (outmode, class); | |
804 | if (out != 0 && GET_CODE (out) == SUBREG) | |
805 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); | |
806 | #endif | |
807 | ||
eab89b90 RK |
808 | /* Verify that this class is at least possible for the mode that |
809 | is specified. */ | |
810 | if (this_insn_is_asm) | |
811 | { | |
812 | enum machine_mode mode; | |
813 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
814 | mode = inmode; | |
815 | else | |
816 | mode = outmode; | |
5488078f RS |
817 | if (mode == VOIDmode) |
818 | { | |
819 | error_for_asm (this_insn, "cannot reload integer constant operand in `asm'"); | |
820 | mode = word_mode; | |
821 | if (in != 0) | |
822 | inmode = word_mode; | |
823 | if (out != 0) | |
824 | outmode = word_mode; | |
825 | } | |
eab89b90 RK |
826 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
827 | if (HARD_REGNO_MODE_OK (i, mode) | |
828 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)) | |
829 | { | |
830 | int nregs = HARD_REGNO_NREGS (i, mode); | |
831 | ||
832 | int j; | |
833 | for (j = 1; j < nregs; j++) | |
834 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j)) | |
835 | break; | |
836 | if (j == nregs) | |
837 | break; | |
838 | } | |
839 | if (i == FIRST_PSEUDO_REGISTER) | |
840 | { | |
841 | error_for_asm (this_insn, "impossible register constraint in `asm'"); | |
842 | class = ALL_REGS; | |
843 | } | |
844 | } | |
845 | ||
5488078f RS |
846 | if (class == NO_REGS) |
847 | abort (); | |
848 | ||
eab89b90 RK |
849 | /* We can use an existing reload if the class is right |
850 | and at least one of IN and OUT is a match | |
851 | and the other is at worst neutral. | |
a8c9daeb RK |
852 | (A zero compared against anything is neutral.) |
853 | ||
854 | If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are | |
855 | for the same thing since that can cause us to need more reload registers | |
856 | than we otherwise would. */ | |
857 | ||
eab89b90 RK |
858 | for (i = 0; i < n_reloads; i++) |
859 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
860 | || reg_class_subset_p (reload_reg_class[i], class)) | |
eab89b90 RK |
861 | /* If the existing reload has a register, it must fit our class. */ |
862 | && (reload_reg_rtx[i] == 0 | |
863 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
864 | true_regnum (reload_reg_rtx[i]))) | |
865 | && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share | |
866 | && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out))) | |
867 | || | |
868 | (out != 0 && MATCHES (reload_out[i], out) | |
a8c9daeb RK |
869 | && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))) |
870 | && (reg_class_size[(int) class] == 1 | |
871 | #ifdef SMALL_REGISTER_CLASSES | |
872 | || 1 | |
873 | #endif | |
874 | ) | |
875 | && MERGABLE_RELOADS (type, reload_when_needed[i], | |
876 | opnum, reload_opnum[i])) | |
eab89b90 RK |
877 | break; |
878 | ||
879 | /* Reloading a plain reg for input can match a reload to postincrement | |
880 | that reg, since the postincrement's value is the right value. | |
881 | Likewise, it can match a preincrement reload, since we regard | |
882 | the preincrementation as happening before any ref in this insn | |
883 | to that register. */ | |
884 | if (i == n_reloads) | |
885 | for (i = 0; i < n_reloads; i++) | |
886 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
887 | || reg_class_subset_p (reload_reg_class[i], class)) | |
888 | /* If the existing reload has a register, it must fit our class. */ | |
889 | && (reload_reg_rtx[i] == 0 | |
890 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
891 | true_regnum (reload_reg_rtx[i]))) | |
eab89b90 RK |
892 | && out == 0 && reload_out[i] == 0 && reload_in[i] != 0 |
893 | && ((GET_CODE (in) == REG | |
894 | && (GET_CODE (reload_in[i]) == POST_INC | |
895 | || GET_CODE (reload_in[i]) == POST_DEC | |
896 | || GET_CODE (reload_in[i]) == PRE_INC | |
897 | || GET_CODE (reload_in[i]) == PRE_DEC) | |
898 | && MATCHES (XEXP (reload_in[i], 0), in)) | |
899 | || | |
900 | (GET_CODE (reload_in[i]) == REG | |
901 | && (GET_CODE (in) == POST_INC | |
902 | || GET_CODE (in) == POST_DEC | |
903 | || GET_CODE (in) == PRE_INC | |
904 | || GET_CODE (in) == PRE_DEC) | |
a8c9daeb RK |
905 | && MATCHES (XEXP (in, 0), reload_in[i]))) |
906 | && (reg_class_size[(int) class] == 1 | |
907 | #ifdef SMALL_REGISTER_CLASSES | |
908 | || 1 | |
909 | #endif | |
910 | ) | |
911 | && MERGABLE_RELOADS (type, reload_when_needed[i], | |
912 | opnum, reload_opnum[i])) | |
eab89b90 RK |
913 | { |
914 | /* Make sure reload_in ultimately has the increment, | |
915 | not the plain register. */ | |
916 | if (GET_CODE (in) == REG) | |
917 | in = reload_in[i]; | |
918 | break; | |
919 | } | |
920 | ||
921 | if (i == n_reloads) | |
922 | { | |
923 | #ifdef HAVE_SECONDARY_RELOADS | |
924 | enum reg_class secondary_class = NO_REGS; | |
925 | enum reg_class secondary_out_class = NO_REGS; | |
926 | enum machine_mode secondary_mode = inmode; | |
927 | enum machine_mode secondary_out_mode = outmode; | |
928 | enum insn_code secondary_icode; | |
929 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
930 | enum reg_class tertiary_class = NO_REGS; | |
931 | enum reg_class tertiary_out_class = NO_REGS; | |
932 | enum machine_mode tertiary_mode; | |
933 | enum machine_mode tertiary_out_mode; | |
934 | enum insn_code tertiary_icode; | |
935 | enum insn_code tertiary_out_icode = CODE_FOR_nothing; | |
936 | int tertiary_reload = -1; | |
937 | ||
938 | /* See if we need a secondary reload register to move between | |
939 | CLASS and IN or CLASS and OUT. Get the modes and icodes to | |
940 | use for each of them if so. */ | |
941 | ||
942 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
943 | if (in != 0) | |
944 | secondary_class | |
945 | = find_secondary_reload (in, class, inmode, 1, &secondary_icode, | |
946 | &secondary_mode, &tertiary_class, | |
947 | &tertiary_icode, &tertiary_mode); | |
948 | #endif | |
949 | ||
950 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
951 | if (out != 0 && GET_CODE (out) != SCRATCH) | |
952 | secondary_out_class | |
953 | = find_secondary_reload (out, class, outmode, 0, | |
954 | &secondary_out_icode, &secondary_out_mode, | |
955 | &tertiary_out_class, &tertiary_out_icode, | |
956 | &tertiary_out_mode); | |
957 | #endif | |
958 | ||
959 | /* We can only record one secondary and one tertiary reload. If both | |
960 | IN and OUT need secondary reloads, we can only make an in-out | |
a8c9daeb RK |
961 | reload if neither need an insn and if the classes are compatible. |
962 | If they aren't, all we can do is abort since making two separate | |
963 | reloads is invalid. */ | |
eab89b90 RK |
964 | |
965 | if (secondary_class != NO_REGS && secondary_out_class != NO_REGS | |
966 | && reg_class_subset_p (secondary_out_class, secondary_class)) | |
967 | secondary_class = secondary_out_class; | |
968 | ||
969 | if (secondary_class != NO_REGS && secondary_out_class != NO_REGS | |
970 | && (! reg_class_subset_p (secondary_class, secondary_out_class) | |
971 | || secondary_icode != CODE_FOR_nothing | |
972 | || secondary_out_icode != CODE_FOR_nothing)) | |
a8c9daeb | 973 | abort (); |
eab89b90 RK |
974 | |
975 | /* If we need a secondary reload for OUT but not IN, copy the | |
976 | information. */ | |
977 | if (secondary_class == NO_REGS && secondary_out_class != NO_REGS) | |
978 | { | |
979 | secondary_class = secondary_out_class; | |
980 | secondary_icode = secondary_out_icode; | |
981 | tertiary_class = tertiary_out_class; | |
982 | tertiary_icode = tertiary_out_icode; | |
983 | tertiary_mode = tertiary_out_mode; | |
984 | } | |
985 | ||
986 | if (secondary_class != NO_REGS) | |
987 | { | |
a8c9daeb RK |
988 | /* Secondary reloads don't conflict as badly as the primary object |
989 | being reload. Specifically, we can always treat them as | |
990 | being for an input or output address and hence allowed to be | |
991 | reused in the same manner such address components could be | |
992 | reused. This is used as the reload_type for our secondary | |
993 | reloads. */ | |
994 | ||
995 | enum reload_type secondary_type | |
996 | = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
997 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
998 | : type); | |
999 | ||
eab89b90 RK |
1000 | /* If we need a tertiary reload, see if we have one we can reuse |
1001 | or else make one. */ | |
1002 | ||
1003 | if (tertiary_class != NO_REGS) | |
1004 | { | |
1005 | for (tertiary_reload = 0; tertiary_reload < n_reloads; | |
1006 | tertiary_reload++) | |
1007 | if (reload_secondary_p[tertiary_reload] | |
1008 | && (reg_class_subset_p (tertiary_class, | |
1009 | reload_reg_class[tertiary_reload]) | |
1010 | || reg_class_subset_p (reload_reg_class[tertiary_reload], | |
1011 | tertiary_class)) | |
1012 | && ((reload_inmode[tertiary_reload] == tertiary_mode) | |
1013 | || reload_inmode[tertiary_reload] == VOIDmode) | |
1014 | && ((reload_outmode[tertiary_reload] == tertiary_mode) | |
1015 | || reload_outmode[tertiary_reload] == VOIDmode) | |
1016 | && (reload_secondary_icode[tertiary_reload] | |
a8c9daeb RK |
1017 | == CODE_FOR_nothing) |
1018 | && (reg_class_size[(int) tertiary_class] == 1 | |
1019 | #ifdef SMALL_REGISTER_CLASSES | |
1020 | || 1 | |
1021 | #endif | |
1022 | ) | |
1023 | && MERGABLE_RELOADS (secondary_type, | |
1024 | reload_when_needed[tertiary_reload], | |
1025 | opnum, reload_opnum[tertiary_reload])) | |
eab89b90 RK |
1026 | { |
1027 | if (tertiary_mode != VOIDmode) | |
1028 | reload_inmode[tertiary_reload] = tertiary_mode; | |
1029 | if (tertiary_out_mode != VOIDmode) | |
1030 | reload_outmode[tertiary_reload] = tertiary_mode; | |
1031 | if (reg_class_subset_p (tertiary_class, | |
1032 | reload_reg_class[tertiary_reload])) | |
1033 | reload_reg_class[tertiary_reload] = tertiary_class; | |
a8c9daeb RK |
1034 | if (MERGE_TO_OTHER (secondary_type, |
1035 | reload_when_needed[tertiary_reload], | |
1036 | opnum, | |
1037 | reload_opnum[tertiary_reload])) | |
1038 | reload_when_needed[tertiary_reload] = RELOAD_OTHER; | |
1039 | reload_opnum[tertiary_reload] | |
1040 | = MIN (reload_opnum[tertiary_reload], opnum); | |
eab89b90 RK |
1041 | reload_optional[tertiary_reload] &= optional; |
1042 | reload_secondary_p[tertiary_reload] = 1; | |
1043 | } | |
1044 | ||
1045 | if (tertiary_reload == n_reloads) | |
1046 | { | |
1047 | /* We need to make a new tertiary reload for this register | |
1048 | class. */ | |
1049 | reload_in[tertiary_reload] = reload_out[tertiary_reload] = 0; | |
1050 | reload_reg_class[tertiary_reload] = tertiary_class; | |
1051 | reload_inmode[tertiary_reload] = tertiary_mode; | |
1052 | reload_outmode[tertiary_reload] = tertiary_mode; | |
1053 | reload_reg_rtx[tertiary_reload] = 0; | |
1054 | reload_optional[tertiary_reload] = optional; | |
1055 | reload_inc[tertiary_reload] = 0; | |
eab89b90 RK |
1056 | /* Maybe we could combine these, but it seems too tricky. */ |
1057 | reload_nocombine[tertiary_reload] = 1; | |
1058 | reload_in_reg[tertiary_reload] = 0; | |
a8c9daeb RK |
1059 | reload_opnum[tertiary_reload] = opnum; |
1060 | reload_when_needed[tertiary_reload] = secondary_type; | |
eab89b90 RK |
1061 | reload_secondary_reload[tertiary_reload] = -1; |
1062 | reload_secondary_icode[tertiary_reload] = CODE_FOR_nothing; | |
1063 | reload_secondary_p[tertiary_reload] = 1; | |
1064 | ||
1065 | n_reloads++; | |
1066 | i = n_reloads; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | /* See if we can reuse an existing secondary reload. */ | |
1071 | for (secondary_reload = 0; secondary_reload < n_reloads; | |
1072 | secondary_reload++) | |
1073 | if (reload_secondary_p[secondary_reload] | |
1074 | && (reg_class_subset_p (secondary_class, | |
1075 | reload_reg_class[secondary_reload]) | |
1076 | || reg_class_subset_p (reload_reg_class[secondary_reload], | |
1077 | secondary_class)) | |
1078 | && ((reload_inmode[secondary_reload] == secondary_mode) | |
1079 | || reload_inmode[secondary_reload] == VOIDmode) | |
1080 | && ((reload_outmode[secondary_reload] == secondary_out_mode) | |
1081 | || reload_outmode[secondary_reload] == VOIDmode) | |
1082 | && reload_secondary_reload[secondary_reload] == tertiary_reload | |
a8c9daeb RK |
1083 | && reload_secondary_icode[secondary_reload] == tertiary_icode |
1084 | && (reg_class_size[(int) secondary_class] == 1 | |
1085 | #ifdef SMALL_REGISTER_CLASSES | |
1086 | || 1 | |
1087 | #endif | |
1088 | ) | |
1089 | && MERGABLE_RELOADS (secondary_type, | |
1090 | reload_when_needed[secondary_reload], | |
1091 | opnum, reload_opnum[secondary_reload])) | |
eab89b90 RK |
1092 | { |
1093 | if (secondary_mode != VOIDmode) | |
1094 | reload_inmode[secondary_reload] = secondary_mode; | |
1095 | if (secondary_out_mode != VOIDmode) | |
1096 | reload_outmode[secondary_reload] = secondary_out_mode; | |
1097 | if (reg_class_subset_p (secondary_class, | |
1098 | reload_reg_class[secondary_reload])) | |
1099 | reload_reg_class[secondary_reload] = secondary_class; | |
a8c9daeb RK |
1100 | if (MERGE_TO_OTHER (secondary_type, |
1101 | reload_when_needed[secondary_reload], | |
1102 | opnum, reload_opnum[secondary_reload])) | |
1103 | reload_when_needed[secondary_reload] = RELOAD_OTHER; | |
1104 | reload_opnum[secondary_reload] | |
1105 | = MIN (reload_opnum[secondary_reload], opnum); | |
eab89b90 RK |
1106 | reload_optional[secondary_reload] &= optional; |
1107 | reload_secondary_p[secondary_reload] = 1; | |
1108 | } | |
1109 | ||
1110 | if (secondary_reload == n_reloads) | |
1111 | { | |
1112 | /* We need to make a new secondary reload for this register | |
1113 | class. */ | |
1114 | reload_in[secondary_reload] = reload_out[secondary_reload] = 0; | |
1115 | reload_reg_class[secondary_reload] = secondary_class; | |
1116 | reload_inmode[secondary_reload] = secondary_mode; | |
1117 | reload_outmode[secondary_reload] = secondary_out_mode; | |
1118 | reload_reg_rtx[secondary_reload] = 0; | |
1119 | reload_optional[secondary_reload] = optional; | |
1120 | reload_inc[secondary_reload] = 0; | |
eab89b90 RK |
1121 | /* Maybe we could combine these, but it seems too tricky. */ |
1122 | reload_nocombine[secondary_reload] = 1; | |
1123 | reload_in_reg[secondary_reload] = 0; | |
a8c9daeb RK |
1124 | reload_opnum[secondary_reload] = opnum; |
1125 | reload_when_needed[secondary_reload] = secondary_type; | |
eab89b90 RK |
1126 | reload_secondary_reload[secondary_reload] = tertiary_reload; |
1127 | reload_secondary_icode[secondary_reload] = tertiary_icode; | |
1128 | reload_secondary_p[secondary_reload] = 1; | |
1129 | ||
1130 | n_reloads++; | |
1131 | i = n_reloads; | |
0dadecf6 RK |
1132 | |
1133 | #ifdef SECONDARY_MEMORY_NEEDED | |
1134 | /* If we need a memory location to copy between the two | |
1135 | reload regs, set it up now. */ | |
1136 | ||
1137 | if (in != 0 && secondary_icode == CODE_FOR_nothing | |
1138 | && SECONDARY_MEMORY_NEEDED (secondary_class, class, inmode)) | |
a8c9daeb | 1139 | get_secondary_mem (in, inmode, opnum, type); |
0dadecf6 RK |
1140 | |
1141 | if (out != 0 && secondary_icode == CODE_FOR_nothing | |
1142 | && SECONDARY_MEMORY_NEEDED (class, secondary_class, outmode)) | |
a8c9daeb | 1143 | get_secondary_mem (out, outmode, opnum, type); |
0dadecf6 | 1144 | #endif |
eab89b90 RK |
1145 | } |
1146 | } | |
1147 | #endif | |
1148 | ||
1149 | /* We found no existing reload suitable for re-use. | |
1150 | So add an additional reload. */ | |
1151 | ||
1152 | reload_in[i] = in; | |
1153 | reload_out[i] = out; | |
1154 | reload_reg_class[i] = class; | |
1155 | reload_inmode[i] = inmode; | |
1156 | reload_outmode[i] = outmode; | |
1157 | reload_reg_rtx[i] = 0; | |
1158 | reload_optional[i] = optional; | |
1159 | reload_inc[i] = 0; | |
eab89b90 RK |
1160 | reload_nocombine[i] = 0; |
1161 | reload_in_reg[i] = inloc ? *inloc : 0; | |
a8c9daeb RK |
1162 | reload_opnum[i] = opnum; |
1163 | reload_when_needed[i] = type; | |
eab89b90 RK |
1164 | reload_secondary_reload[i] = secondary_reload; |
1165 | reload_secondary_icode[i] = secondary_icode; | |
1166 | reload_secondary_p[i] = 0; | |
1167 | ||
1168 | n_reloads++; | |
0dadecf6 RK |
1169 | |
1170 | #ifdef SECONDARY_MEMORY_NEEDED | |
1171 | /* If a memory location is needed for the copy, make one. */ | |
1172 | if (in != 0 && GET_CODE (in) == REG | |
1173 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1174 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), | |
1175 | class, inmode)) | |
a8c9daeb | 1176 | get_secondary_mem (in, inmode, opnum, type); |
0dadecf6 RK |
1177 | |
1178 | if (out != 0 && GET_CODE (out) == REG | |
1179 | && REGNO (out) < FIRST_PSEUDO_REGISTER | |
1180 | && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)), | |
1181 | outmode)) | |
a8c9daeb | 1182 | get_secondary_mem (out, outmode, opnum, type); |
0dadecf6 | 1183 | #endif |
eab89b90 RK |
1184 | } |
1185 | else | |
1186 | { | |
1187 | /* We are reusing an existing reload, | |
1188 | but we may have additional information for it. | |
1189 | For example, we may now have both IN and OUT | |
1190 | while the old one may have just one of them. */ | |
1191 | ||
1192 | if (inmode != VOIDmode) | |
1193 | reload_inmode[i] = inmode; | |
1194 | if (outmode != VOIDmode) | |
1195 | reload_outmode[i] = outmode; | |
1196 | if (in != 0) | |
1197 | reload_in[i] = in; | |
1198 | if (out != 0) | |
1199 | reload_out[i] = out; | |
1200 | if (reg_class_subset_p (class, reload_reg_class[i])) | |
1201 | reload_reg_class[i] = class; | |
1202 | reload_optional[i] &= optional; | |
a8c9daeb RK |
1203 | if (MERGE_TO_OTHER (type, reload_when_needed[i], |
1204 | opnum, reload_opnum[i])) | |
1205 | reload_when_needed[i] = RELOAD_OTHER; | |
1206 | reload_opnum[i] = MIN (reload_opnum[i], opnum); | |
eab89b90 RK |
1207 | } |
1208 | ||
1209 | /* If the ostensible rtx being reload differs from the rtx found | |
1210 | in the location to substitute, this reload is not safe to combine | |
1211 | because we cannot reliably tell whether it appears in the insn. */ | |
1212 | ||
1213 | if (in != 0 && in != *inloc) | |
1214 | reload_nocombine[i] = 1; | |
1215 | ||
1216 | #if 0 | |
1217 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1218 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1219 | ||
1220 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1221 | it must be for an autoincrement. It doesn't work to store | |
1222 | the incremented value after the insn because that would clobber the CC. | |
1223 | So we must do the increment of the value reloaded from, | |
1224 | increment it, store it back, then decrement again. */ | |
1225 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1226 | { | |
1227 | out = 0; | |
1228 | reload_out[i] = 0; | |
1229 | reload_inc[i] = find_inc_amount (PATTERN (this_insn), in); | |
1230 | /* If we did not find a nonzero amount-to-increment-by, | |
1231 | that contradicts the belief that IN is being incremented | |
1232 | in an address in this insn. */ | |
1233 | if (reload_inc[i] == 0) | |
1234 | abort (); | |
1235 | } | |
1236 | #endif | |
1237 | ||
1238 | /* If we will replace IN and OUT with the reload-reg, | |
1239 | record where they are located so that substitution need | |
1240 | not do a tree walk. */ | |
1241 | ||
1242 | if (replace_reloads) | |
1243 | { | |
1244 | if (inloc != 0) | |
1245 | { | |
1246 | register struct replacement *r = &replacements[n_replacements++]; | |
1247 | r->what = i; | |
1248 | r->subreg_loc = in_subreg_loc; | |
1249 | r->where = inloc; | |
1250 | r->mode = inmode; | |
1251 | } | |
1252 | if (outloc != 0 && outloc != inloc) | |
1253 | { | |
1254 | register struct replacement *r = &replacements[n_replacements++]; | |
1255 | r->what = i; | |
1256 | r->where = outloc; | |
1257 | r->subreg_loc = out_subreg_loc; | |
1258 | r->mode = outmode; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | /* If this reload is just being introduced and it has both | |
1263 | an incoming quantity and an outgoing quantity that are | |
1264 | supposed to be made to match, see if either one of the two | |
1265 | can serve as the place to reload into. | |
1266 | ||
1267 | If one of them is acceptable, set reload_reg_rtx[i] | |
1268 | to that one. */ | |
1269 | ||
1270 | if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0) | |
1271 | { | |
1272 | reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc, | |
1273 | reload_reg_class[i], i); | |
1274 | ||
1275 | /* If the outgoing register already contains the same value | |
1276 | as the incoming one, we can dispense with loading it. | |
1277 | The easiest way to tell the caller that is to give a phony | |
1278 | value for the incoming operand (same as outgoing one). */ | |
1279 | if (reload_reg_rtx[i] == out | |
1280 | && (GET_CODE (in) == REG || CONSTANT_P (in)) | |
1281 | && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), | |
1282 | static_reload_reg_p, i, inmode)) | |
1283 | reload_in[i] = out; | |
1284 | } | |
1285 | ||
1286 | /* If this is an input reload and the operand contains a register that | |
1287 | dies in this insn and is used nowhere else, see if it is the right class | |
1288 | to be used for this reload. Use it if so. (This occurs most commonly | |
1289 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1290 | this if it is also an output reload that mentions the register unless | |
1291 | the output is a SUBREG that clobbers an entire register. | |
1292 | ||
1293 | Note that the operand might be one of the spill regs, if it is a | |
1294 | pseudo reg and we are in a block where spilling has not taken place. | |
1295 | But if there is no spilling in this block, that is OK. | |
1296 | An explicitly used hard reg cannot be a spill reg. */ | |
1297 | ||
1298 | if (reload_reg_rtx[i] == 0 && in != 0) | |
1299 | { | |
1300 | rtx note; | |
1301 | int regno; | |
1302 | ||
1303 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1304 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1305 | && GET_CODE (XEXP (note, 0)) == REG | |
1306 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER | |
1307 | && reg_mentioned_p (XEXP (note, 0), in) | |
1308 | && ! refers_to_regno_for_reload_p (regno, | |
1309 | (regno | |
1310 | + HARD_REGNO_NREGS (regno, | |
1311 | inmode)), | |
1312 | PATTERN (this_insn), inloc) | |
05b4ec4f RS |
1313 | /* If this is also an output reload, IN cannot be used as |
1314 | the reload register if it is set in this insn unless IN | |
1315 | is also OUT. */ | |
1316 | && (out == 0 || in == out | |
1317 | || ! hard_reg_set_here_p (regno, | |
1318 | (regno | |
1319 | + HARD_REGNO_NREGS (regno, | |
1320 | inmode)), | |
1321 | PATTERN (this_insn))) | |
1322 | /* ??? Why is this code so different from the previous? | |
1323 | Is there any simple coherent way to describe the two together? | |
1324 | What's going on here. */ | |
eab89b90 RK |
1325 | && (in != out |
1326 | || (GET_CODE (in) == SUBREG | |
1327 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1328 | / UNITS_PER_WORD) | |
1329 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1330 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1331 | /* Make sure the operand fits in the reg that dies. */ | |
1332 | && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1333 | && HARD_REGNO_MODE_OK (regno, inmode) | |
1334 | && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1335 | && HARD_REGNO_MODE_OK (regno, outmode) | |
1336 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
1337 | && !fixed_regs[regno]) | |
1338 | { | |
1339 | reload_reg_rtx[i] = gen_rtx (REG, inmode, regno); | |
1340 | break; | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | if (out) | |
1345 | output_reloadnum = i; | |
1346 | ||
1347 | return i; | |
1348 | } | |
1349 | ||
1350 | /* Record an additional place we must replace a value | |
1351 | for which we have already recorded a reload. | |
1352 | RELOADNUM is the value returned by push_reload | |
1353 | when the reload was recorded. | |
1354 | This is used in insn patterns that use match_dup. */ | |
1355 | ||
1356 | static void | |
1357 | push_replacement (loc, reloadnum, mode) | |
1358 | rtx *loc; | |
1359 | int reloadnum; | |
1360 | enum machine_mode mode; | |
1361 | { | |
1362 | if (replace_reloads) | |
1363 | { | |
1364 | register struct replacement *r = &replacements[n_replacements++]; | |
1365 | r->what = reloadnum; | |
1366 | r->where = loc; | |
1367 | r->subreg_loc = 0; | |
1368 | r->mode = mode; | |
1369 | } | |
1370 | } | |
1371 | \f | |
a8c9daeb RK |
1372 | /* Transfer all replacements that used to be in reload FROM to be in |
1373 | reload TO. */ | |
1374 | ||
1375 | void | |
1376 | transfer_replacements (to, from) | |
1377 | int to, from; | |
1378 | { | |
1379 | int i; | |
1380 | ||
1381 | for (i = 0; i < n_replacements; i++) | |
1382 | if (replacements[i].what == from) | |
1383 | replacements[i].what = to; | |
1384 | } | |
1385 | \f | |
eab89b90 RK |
1386 | /* If there is only one output reload, and it is not for an earlyclobber |
1387 | operand, try to combine it with a (logically unrelated) input reload | |
1388 | to reduce the number of reload registers needed. | |
1389 | ||
1390 | This is safe if the input reload does not appear in | |
1391 | the value being output-reloaded, because this implies | |
1392 | it is not needed any more once the original insn completes. | |
1393 | ||
1394 | If that doesn't work, see we can use any of the registers that | |
1395 | die in this insn as a reload register. We can if it is of the right | |
1396 | class and does not appear in the value being output-reloaded. */ | |
1397 | ||
1398 | static void | |
1399 | combine_reloads () | |
1400 | { | |
1401 | int i; | |
1402 | int output_reload = -1; | |
1403 | rtx note; | |
1404 | ||
1405 | /* Find the output reload; return unless there is exactly one | |
1406 | and that one is mandatory. */ | |
1407 | ||
1408 | for (i = 0; i < n_reloads; i++) | |
1409 | if (reload_out[i] != 0) | |
1410 | { | |
1411 | if (output_reload >= 0) | |
1412 | return; | |
1413 | output_reload = i; | |
1414 | } | |
1415 | ||
1416 | if (output_reload < 0 || reload_optional[output_reload]) | |
1417 | return; | |
1418 | ||
1419 | /* An input-output reload isn't combinable. */ | |
1420 | ||
1421 | if (reload_in[output_reload] != 0) | |
1422 | return; | |
1423 | ||
6dc42e49 | 1424 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
eab89b90 RK |
1425 | |
1426 | for (i = 0; i < n_earlyclobbers; i++) | |
1427 | if (reload_out[output_reload] == reload_earlyclobbers[i]) | |
1428 | return; | |
1429 | ||
1430 | /* Check each input reload; can we combine it? */ | |
1431 | ||
1432 | for (i = 0; i < n_reloads; i++) | |
1433 | if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i] | |
1434 | /* Life span of this reload must not extend past main insn. */ | |
a8c9daeb RK |
1435 | && reload_when_needed[i] != RELOAD_FOR_OUTPUT_ADDRESS |
1436 | && reload_when_needed[i] != RELOAD_OTHER | |
1437 | && (CLASS_MAX_NREGS (reload_reg_class[i], reload_inmode[i]) | |
1438 | == CLASS_MAX_NREGS (reload_reg_class[output_reload], | |
1439 | reload_outmode[output_reload])) | |
eab89b90 RK |
1440 | && reload_inc[i] == 0 |
1441 | && reload_reg_rtx[i] == 0 | |
eab89b90 RK |
1442 | /* Don't combine two reloads with different secondary reloads. */ |
1443 | && (reload_secondary_reload[i] == reload_secondary_reload[output_reload] | |
1444 | || reload_secondary_reload[i] == -1 | |
1445 | || reload_secondary_reload[output_reload] == -1) | |
a8c9daeb RK |
1446 | #ifdef SECONDARY_MEMORY_NEEDED |
1447 | /* Likewise for different secondary memory locations. */ | |
77545d45 RK |
1448 | && (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] == 0 |
1449 | || secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] == 0 | |
1450 | || rtx_equal_p (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]], | |
1451 | secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]])) | |
a8c9daeb RK |
1452 | #endif |
1453 | #ifdef SMALL_REGISTER_CLASSES | |
1454 | && reload_reg_class[i] == reload_reg_class[output_reload] | |
1455 | #else | |
eab89b90 RK |
1456 | && (reg_class_subset_p (reload_reg_class[i], |
1457 | reload_reg_class[output_reload]) | |
1458 | || reg_class_subset_p (reload_reg_class[output_reload], | |
1459 | reload_reg_class[i])) | |
a8c9daeb | 1460 | #endif |
eab89b90 RK |
1461 | && (MATCHES (reload_in[i], reload_out[output_reload]) |
1462 | /* Args reversed because the first arg seems to be | |
1463 | the one that we imagine being modified | |
1464 | while the second is the one that might be affected. */ | |
bfa30b22 RK |
1465 | || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload], |
1466 | reload_in[i]) | |
eab89b90 RK |
1467 | /* However, if the input is a register that appears inside |
1468 | the output, then we also can't share. | |
1469 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1470 | If the same reload reg is used for both reg 69 and the | |
1471 | result to be stored in memory, then that result | |
1472 | will clobber the address of the memory ref. */ | |
1473 | && ! (GET_CODE (reload_in[i]) == REG | |
bfa30b22 | 1474 | && reg_overlap_mentioned_for_reload_p (reload_in[i], |
a8c9daeb RK |
1475 | reload_out[output_reload])))) |
1476 | && (reg_class_size[(int) reload_reg_class[i]] | |
1477 | #ifdef SMALL_REGISTER_CLASSES | |
1478 | || 1 | |
1479 | #endif | |
1480 | ) | |
1481 | /* We will allow making things slightly worse by combining an | |
1482 | input and an output, but no worse than that. */ | |
1483 | && (reload_when_needed[i] == RELOAD_FOR_INPUT | |
1484 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT)) | |
eab89b90 RK |
1485 | { |
1486 | int j; | |
1487 | ||
1488 | /* We have found a reload to combine with! */ | |
1489 | reload_out[i] = reload_out[output_reload]; | |
1490 | reload_outmode[i] = reload_outmode[output_reload]; | |
1491 | /* Mark the old output reload as inoperative. */ | |
1492 | reload_out[output_reload] = 0; | |
1493 | /* The combined reload is needed for the entire insn. */ | |
eab89b90 RK |
1494 | reload_when_needed[i] = RELOAD_OTHER; |
1495 | /* If the output reload had a secondary reload, copy it. */ | |
1496 | if (reload_secondary_reload[output_reload] != -1) | |
1497 | reload_secondary_reload[i] = reload_secondary_reload[output_reload]; | |
a8c9daeb RK |
1498 | #ifdef SECONDARY_MEMORY_NEEDED |
1499 | /* Copy any secondary MEM. */ | |
77545d45 RK |
1500 | if (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] != 0) |
1501 | secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] | |
1502 | = secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]]; | |
a8c9daeb | 1503 | #endif |
eab89b90 RK |
1504 | /* If required, minimize the register class. */ |
1505 | if (reg_class_subset_p (reload_reg_class[output_reload], | |
1506 | reload_reg_class[i])) | |
1507 | reload_reg_class[i] = reload_reg_class[output_reload]; | |
1508 | ||
1509 | /* Transfer all replacements from the old reload to the combined. */ | |
1510 | for (j = 0; j < n_replacements; j++) | |
1511 | if (replacements[j].what == output_reload) | |
1512 | replacements[j].what = i; | |
1513 | ||
1514 | return; | |
1515 | } | |
1516 | ||
1517 | /* If this insn has only one operand that is modified or written (assumed | |
1518 | to be the first), it must be the one corresponding to this reload. It | |
1519 | is safe to use anything that dies in this insn for that output provided | |
1520 | that it does not occur in the output (we already know it isn't an | |
1521 | earlyclobber. If this is an asm insn, give up. */ | |
1522 | ||
1523 | if (INSN_CODE (this_insn) == -1) | |
1524 | return; | |
1525 | ||
1526 | for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++) | |
1527 | if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '=' | |
1528 | || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+') | |
1529 | return; | |
1530 | ||
1531 | /* See if some hard register that dies in this insn and is not used in | |
1532 | the output is the right class. Only works if the register we pick | |
1533 | up can fully hold our output reload. */ | |
1534 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1535 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1536 | && GET_CODE (XEXP (note, 0)) == REG | |
bfa30b22 RK |
1537 | && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
1538 | reload_out[output_reload]) | |
eab89b90 RK |
1539 | && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
1540 | && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1541 | && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]], | |
1542 | REGNO (XEXP (note, 0))) | |
1543 | && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1544 | <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0)))) | |
1545 | && ! fixed_regs[REGNO (XEXP (note, 0))]) | |
1546 | { | |
1547 | reload_reg_rtx[output_reload] = gen_rtx (REG, | |
1548 | reload_outmode[output_reload], | |
1549 | REGNO (XEXP (note, 0))); | |
1550 | return; | |
1551 | } | |
1552 | } | |
1553 | \f | |
1554 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1555 | See if one of IN and OUT is a register that may be used; | |
1556 | this is desirable since a spill-register won't be needed. | |
1557 | If so, return the register rtx that proves acceptable. | |
1558 | ||
1559 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
1560 | CLASS is the register class required for the reload. | |
1561 | ||
1562 | If FOR_REAL is >= 0, it is the number of the reload, | |
1563 | and in some cases when it can be discovered that OUT doesn't need | |
1564 | to be computed, clear out reload_out[FOR_REAL]. | |
1565 | ||
1566 | If FOR_REAL is -1, this should not be done, because this call | |
1567 | is just to see if a register can be found, not to find and install it. */ | |
1568 | ||
1569 | static rtx | |
1570 | find_dummy_reload (real_in, real_out, inloc, outloc, class, for_real) | |
1571 | rtx real_in, real_out; | |
1572 | rtx *inloc, *outloc; | |
1573 | enum reg_class class; | |
1574 | int for_real; | |
1575 | { | |
1576 | rtx in = real_in; | |
1577 | rtx out = real_out; | |
1578 | int in_offset = 0; | |
1579 | int out_offset = 0; | |
1580 | rtx value = 0; | |
1581 | ||
1582 | /* If operands exceed a word, we can't use either of them | |
1583 | unless they have the same size. */ | |
1584 | if (GET_MODE_SIZE (GET_MODE (real_out)) != GET_MODE_SIZE (GET_MODE (real_in)) | |
1585 | && (GET_MODE_SIZE (GET_MODE (real_out)) > UNITS_PER_WORD | |
1586 | || GET_MODE_SIZE (GET_MODE (real_in)) > UNITS_PER_WORD)) | |
1587 | return 0; | |
1588 | ||
1589 | /* Find the inside of any subregs. */ | |
1590 | while (GET_CODE (out) == SUBREG) | |
1591 | { | |
1592 | out_offset = SUBREG_WORD (out); | |
1593 | out = SUBREG_REG (out); | |
1594 | } | |
1595 | while (GET_CODE (in) == SUBREG) | |
1596 | { | |
1597 | in_offset = SUBREG_WORD (in); | |
1598 | in = SUBREG_REG (in); | |
1599 | } | |
1600 | ||
1601 | /* Narrow down the reg class, the same way push_reload will; | |
1602 | otherwise we might find a dummy now, but push_reload won't. */ | |
1603 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1604 | ||
1605 | /* See if OUT will do. */ | |
1606 | if (GET_CODE (out) == REG | |
1607 | && REGNO (out) < FIRST_PSEUDO_REGISTER) | |
1608 | { | |
1609 | register int regno = REGNO (out) + out_offset; | |
1610 | int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_out)); | |
d3b9996a | 1611 | rtx saved_rtx; |
eab89b90 RK |
1612 | |
1613 | /* When we consider whether the insn uses OUT, | |
1614 | ignore references within IN. They don't prevent us | |
1615 | from copying IN into OUT, because those refs would | |
1616 | move into the insn that reloads IN. | |
1617 | ||
1618 | However, we only ignore IN in its role as this reload. | |
1619 | If the insn uses IN elsewhere and it contains OUT, | |
1620 | that counts. We can't be sure it's the "same" operand | |
1621 | so it might not go through this reload. */ | |
d3b9996a | 1622 | saved_rtx = *inloc; |
eab89b90 RK |
1623 | *inloc = const0_rtx; |
1624 | ||
1625 | if (regno < FIRST_PSEUDO_REGISTER | |
1626 | /* A fixed reg that can overlap other regs better not be used | |
1627 | for reloading in any way. */ | |
1628 | #ifdef OVERLAPPING_REGNO_P | |
1629 | && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno)) | |
1630 | #endif | |
1631 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1632 | PATTERN (this_insn), outloc)) | |
1633 | { | |
1634 | int i; | |
1635 | for (i = 0; i < nwords; i++) | |
1636 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1637 | regno + i)) | |
1638 | break; | |
1639 | ||
1640 | if (i == nwords) | |
1641 | { | |
1642 | if (GET_CODE (real_out) == REG) | |
1643 | value = real_out; | |
1644 | else | |
1645 | value = gen_rtx (REG, GET_MODE (real_out), regno); | |
1646 | } | |
1647 | } | |
1648 | ||
d3b9996a | 1649 | *inloc = saved_rtx; |
eab89b90 RK |
1650 | } |
1651 | ||
1652 | /* Consider using IN if OUT was not acceptable | |
1653 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
1654 | We can't use IN unless it is dies in this insn, | |
1655 | which means we must know accurately which hard regs are live. | |
1656 | Also, the result can't go in IN if IN is used within OUT. */ | |
1657 | if (hard_regs_live_known | |
1658 | && GET_CODE (in) == REG | |
1659 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1660 | && (value == 0 | |
1661 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
1662 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
1663 | && !fixed_regs[REGNO (in)] | |
1664 | && HARD_REGNO_MODE_OK (REGNO (in), GET_MODE (out))) | |
1665 | { | |
1666 | register int regno = REGNO (in) + in_offset; | |
1667 | int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_in)); | |
1668 | ||
fb3821f7 | 1669 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR) |
eab89b90 RK |
1670 | && ! hard_reg_set_here_p (regno, regno + nwords, |
1671 | PATTERN (this_insn))) | |
1672 | { | |
1673 | int i; | |
1674 | for (i = 0; i < nwords; i++) | |
1675 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1676 | regno + i)) | |
1677 | break; | |
1678 | ||
1679 | if (i == nwords) | |
1680 | { | |
1681 | /* If we were going to use OUT as the reload reg | |
1682 | and changed our mind, it means OUT is a dummy that | |
1683 | dies here. So don't bother copying value to it. */ | |
1684 | if (for_real >= 0 && value == real_out) | |
1685 | reload_out[for_real] = 0; | |
1686 | if (GET_CODE (real_in) == REG) | |
1687 | value = real_in; | |
1688 | else | |
1689 | value = gen_rtx (REG, GET_MODE (real_in), regno); | |
1690 | } | |
1691 | } | |
1692 | } | |
1693 | ||
1694 | return value; | |
1695 | } | |
1696 | \f | |
1697 | /* This page contains subroutines used mainly for determining | |
1698 | whether the IN or an OUT of a reload can serve as the | |
1699 | reload register. */ | |
1700 | ||
1701 | /* Return 1 if expression X alters a hard reg in the range | |
1702 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
1703 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
1704 | X should be the body of an instruction. */ | |
1705 | ||
1706 | static int | |
1707 | hard_reg_set_here_p (beg_regno, end_regno, x) | |
1708 | register int beg_regno, end_regno; | |
1709 | rtx x; | |
1710 | { | |
1711 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
1712 | { | |
1713 | register rtx op0 = SET_DEST (x); | |
1714 | while (GET_CODE (op0) == SUBREG) | |
1715 | op0 = SUBREG_REG (op0); | |
1716 | if (GET_CODE (op0) == REG) | |
1717 | { | |
1718 | register int r = REGNO (op0); | |
1719 | /* See if this reg overlaps range under consideration. */ | |
1720 | if (r < end_regno | |
1721 | && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno) | |
1722 | return 1; | |
1723 | } | |
1724 | } | |
1725 | else if (GET_CODE (x) == PARALLEL) | |
1726 | { | |
1727 | register int i = XVECLEN (x, 0) - 1; | |
1728 | for (; i >= 0; i--) | |
1729 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
1730 | return 1; | |
1731 | } | |
1732 | ||
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | /* Return 1 if ADDR is a valid memory address for mode MODE, | |
1737 | and check that each pseudo reg has the proper kind of | |
1738 | hard reg. */ | |
1739 | ||
1740 | int | |
1741 | strict_memory_address_p (mode, addr) | |
1742 | enum machine_mode mode; | |
1743 | register rtx addr; | |
1744 | { | |
1745 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
1746 | return 0; | |
1747 | ||
1748 | win: | |
1749 | return 1; | |
1750 | } | |
eab89b90 RK |
1751 | \f |
1752 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
1753 | if they are the same hard reg, and has special hacks for | |
1754 | autoincrement and autodecrement. | |
1755 | This is specifically intended for find_reloads to use | |
1756 | in determining whether two operands match. | |
1757 | X is the operand whose number is the lower of the two. | |
1758 | ||
1759 | The value is 2 if Y contains a pre-increment that matches | |
1760 | a non-incrementing address in X. */ | |
1761 | ||
1762 | /* ??? To be completely correct, we should arrange to pass | |
1763 | for X the output operand and for Y the input operand. | |
1764 | For now, we assume that the output operand has the lower number | |
1765 | because that is natural in (SET output (... input ...)). */ | |
1766 | ||
1767 | int | |
1768 | operands_match_p (x, y) | |
1769 | register rtx x, y; | |
1770 | { | |
1771 | register int i; | |
1772 | register RTX_CODE code = GET_CODE (x); | |
1773 | register char *fmt; | |
1774 | int success_2; | |
1775 | ||
1776 | if (x == y) | |
1777 | return 1; | |
1778 | if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) | |
1779 | && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG | |
1780 | && GET_CODE (SUBREG_REG (y)) == REG))) | |
1781 | { | |
1782 | register int j; | |
1783 | ||
1784 | if (code == SUBREG) | |
1785 | { | |
1786 | i = REGNO (SUBREG_REG (x)); | |
1787 | if (i >= FIRST_PSEUDO_REGISTER) | |
1788 | goto slow; | |
1789 | i += SUBREG_WORD (x); | |
1790 | } | |
1791 | else | |
1792 | i = REGNO (x); | |
1793 | ||
1794 | if (GET_CODE (y) == SUBREG) | |
1795 | { | |
1796 | j = REGNO (SUBREG_REG (y)); | |
1797 | if (j >= FIRST_PSEUDO_REGISTER) | |
1798 | goto slow; | |
1799 | j += SUBREG_WORD (y); | |
1800 | } | |
1801 | else | |
1802 | j = REGNO (y); | |
1803 | ||
dca52d80 JW |
1804 | /* On a WORDS_BIG_ENDIAN machine, point to the last register of a |
1805 | multiple hard register group, so that for example (reg:DI 0) and | |
1806 | (reg:SI 1) will be considered the same register. */ | |
1807 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD | |
1808 | && i < FIRST_PSEUDO_REGISTER) | |
1809 | i += (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD) - 1; | |
1810 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD | |
1811 | && j < FIRST_PSEUDO_REGISTER) | |
1812 | j += (GET_MODE_SIZE (GET_MODE (y)) / UNITS_PER_WORD) - 1; | |
1813 | ||
eab89b90 RK |
1814 | return i == j; |
1815 | } | |
1816 | /* If two operands must match, because they are really a single | |
1817 | operand of an assembler insn, then two postincrements are invalid | |
1818 | because the assembler insn would increment only once. | |
1819 | On the other hand, an postincrement matches ordinary indexing | |
1820 | if the postincrement is the output operand. */ | |
1821 | if (code == POST_DEC || code == POST_INC) | |
1822 | return operands_match_p (XEXP (x, 0), y); | |
1823 | /* Two preincrements are invalid | |
1824 | because the assembler insn would increment only once. | |
1825 | On the other hand, an preincrement matches ordinary indexing | |
1826 | if the preincrement is the input operand. | |
1827 | In this case, return 2, since some callers need to do special | |
1828 | things when this happens. */ | |
1829 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC) | |
1830 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; | |
1831 | ||
1832 | slow: | |
1833 | ||
1834 | /* Now we have disposed of all the cases | |
1835 | in which different rtx codes can match. */ | |
1836 | if (code != GET_CODE (y)) | |
1837 | return 0; | |
1838 | if (code == LABEL_REF) | |
1839 | return XEXP (x, 0) == XEXP (y, 0); | |
1840 | if (code == SYMBOL_REF) | |
1841 | return XSTR (x, 0) == XSTR (y, 0); | |
1842 | ||
1843 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
1844 | ||
1845 | if (GET_MODE (x) != GET_MODE (y)) | |
1846 | return 0; | |
1847 | ||
1848 | /* Compare the elements. If any pair of corresponding elements | |
1849 | fail to match, return 0 for the whole things. */ | |
1850 | ||
1851 | success_2 = 0; | |
1852 | fmt = GET_RTX_FORMAT (code); | |
1853 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1854 | { | |
1855 | int val; | |
1856 | switch (fmt[i]) | |
1857 | { | |
fb3821f7 CH |
1858 | case 'w': |
1859 | if (XWINT (x, i) != XWINT (y, i)) | |
1860 | return 0; | |
1861 | break; | |
1862 | ||
eab89b90 RK |
1863 | case 'i': |
1864 | if (XINT (x, i) != XINT (y, i)) | |
1865 | return 0; | |
1866 | break; | |
1867 | ||
1868 | case 'e': | |
1869 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
1870 | if (val == 0) | |
1871 | return 0; | |
1872 | /* If any subexpression returns 2, | |
1873 | we should return 2 if we are successful. */ | |
1874 | if (val == 2) | |
1875 | success_2 = 1; | |
1876 | break; | |
1877 | ||
1878 | case '0': | |
1879 | break; | |
1880 | ||
1881 | /* It is believed that rtx's at this level will never | |
1882 | contain anything but integers and other rtx's, | |
1883 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
1884 | default: | |
1885 | abort (); | |
1886 | } | |
1887 | } | |
1888 | return 1 + success_2; | |
1889 | } | |
1890 | \f | |
1891 | /* Return the number of times character C occurs in string S. */ | |
1892 | ||
e4600702 | 1893 | int |
eab89b90 RK |
1894 | n_occurrences (c, s) |
1895 | char c; | |
1896 | char *s; | |
1897 | { | |
1898 | int n = 0; | |
1899 | while (*s) | |
1900 | n += (*s++ == c); | |
1901 | return n; | |
1902 | } | |
1903 | \f | |
eab89b90 RK |
1904 | /* Describe the range of registers or memory referenced by X. |
1905 | If X is a register, set REG_FLAG and put the first register | |
1906 | number into START and the last plus one into END. | |
1907 | If X is a memory reference, put a base address into BASE | |
1908 | and a range of integer offsets into START and END. | |
1909 | If X is pushing on the stack, we can assume it causes no trouble, | |
1910 | so we set the SAFE field. */ | |
1911 | ||
1912 | static struct decomposition | |
1913 | decompose (x) | |
1914 | rtx x; | |
1915 | { | |
1916 | struct decomposition val; | |
1917 | int all_const = 0; | |
1918 | ||
1919 | val.reg_flag = 0; | |
1920 | val.safe = 0; | |
1921 | if (GET_CODE (x) == MEM) | |
1922 | { | |
1923 | rtx base, offset = 0; | |
1924 | rtx addr = XEXP (x, 0); | |
1925 | ||
1926 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC | |
1927 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
1928 | { | |
1929 | val.base = XEXP (addr, 0); | |
1930 | val.start = - GET_MODE_SIZE (GET_MODE (x)); | |
1931 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
1932 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
1933 | return val; | |
1934 | } | |
1935 | ||
1936 | if (GET_CODE (addr) == CONST) | |
1937 | { | |
1938 | addr = XEXP (addr, 0); | |
1939 | all_const = 1; | |
1940 | } | |
1941 | if (GET_CODE (addr) == PLUS) | |
1942 | { | |
1943 | if (CONSTANT_P (XEXP (addr, 0))) | |
1944 | { | |
1945 | base = XEXP (addr, 1); | |
1946 | offset = XEXP (addr, 0); | |
1947 | } | |
1948 | else if (CONSTANT_P (XEXP (addr, 1))) | |
1949 | { | |
1950 | base = XEXP (addr, 0); | |
1951 | offset = XEXP (addr, 1); | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | if (offset == 0) | |
1956 | { | |
1957 | base = addr; | |
1958 | offset = const0_rtx; | |
1959 | } | |
1960 | if (GET_CODE (offset) == CONST) | |
1961 | offset = XEXP (offset, 0); | |
1962 | if (GET_CODE (offset) == PLUS) | |
1963 | { | |
1964 | if (GET_CODE (XEXP (offset, 0)) == CONST_INT) | |
1965 | { | |
1966 | base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1)); | |
1967 | offset = XEXP (offset, 0); | |
1968 | } | |
1969 | else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) | |
1970 | { | |
1971 | base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0)); | |
1972 | offset = XEXP (offset, 1); | |
1973 | } | |
1974 | else | |
1975 | { | |
1976 | base = gen_rtx (PLUS, GET_MODE (base), base, offset); | |
1977 | offset = const0_rtx; | |
1978 | } | |
1979 | } | |
1980 | else if (GET_CODE (offset) != CONST_INT) | |
1981 | { | |
1982 | base = gen_rtx (PLUS, GET_MODE (base), base, offset); | |
1983 | offset = const0_rtx; | |
1984 | } | |
1985 | ||
1986 | if (all_const && GET_CODE (base) == PLUS) | |
1987 | base = gen_rtx (CONST, GET_MODE (base), base); | |
1988 | ||
1989 | if (GET_CODE (offset) != CONST_INT) | |
1990 | abort (); | |
1991 | ||
1992 | val.start = INTVAL (offset); | |
1993 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
1994 | val.base = base; | |
1995 | return val; | |
1996 | } | |
1997 | else if (GET_CODE (x) == REG) | |
1998 | { | |
1999 | val.reg_flag = 1; | |
2000 | val.start = true_regnum (x); | |
2001 | if (val.start < 0) | |
2002 | { | |
2003 | /* A pseudo with no hard reg. */ | |
2004 | val.start = REGNO (x); | |
2005 | val.end = val.start + 1; | |
2006 | } | |
2007 | else | |
2008 | /* A hard reg. */ | |
2009 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2010 | } | |
2011 | else if (GET_CODE (x) == SUBREG) | |
2012 | { | |
2013 | if (GET_CODE (SUBREG_REG (x)) != REG) | |
2014 | /* This could be more precise, but it's good enough. */ | |
2015 | return decompose (SUBREG_REG (x)); | |
2016 | val.reg_flag = 1; | |
2017 | val.start = true_regnum (x); | |
2018 | if (val.start < 0) | |
2019 | return decompose (SUBREG_REG (x)); | |
2020 | else | |
2021 | /* A hard reg. */ | |
2022 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2023 | } | |
2024 | else if (CONSTANT_P (x) | |
2025 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
2026 | || GET_CODE (x) == SCRATCH) | |
2027 | val.safe = 1; | |
2028 | else | |
2029 | abort (); | |
2030 | return val; | |
2031 | } | |
2032 | ||
2033 | /* Return 1 if altering Y will not modify the value of X. | |
2034 | Y is also described by YDATA, which should be decompose (Y). */ | |
2035 | ||
2036 | static int | |
2037 | immune_p (x, y, ydata) | |
2038 | rtx x, y; | |
2039 | struct decomposition ydata; | |
2040 | { | |
2041 | struct decomposition xdata; | |
2042 | ||
2043 | if (ydata.reg_flag) | |
fb3821f7 | 2044 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR); |
eab89b90 RK |
2045 | if (ydata.safe) |
2046 | return 1; | |
2047 | ||
2048 | if (GET_CODE (y) != MEM) | |
2049 | abort (); | |
2050 | /* If Y is memory and X is not, Y can't affect X. */ | |
2051 | if (GET_CODE (x) != MEM) | |
2052 | return 1; | |
2053 | ||
2054 | xdata = decompose (x); | |
2055 | ||
2056 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
2057 | { | |
2058 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
2059 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
2060 | return 1; | |
2061 | /* Constants and stack slots never overlap. */ | |
2062 | if (CONSTANT_P (xdata.base) | |
2063 | && (ydata.base == frame_pointer_rtx | |
2064 | || ydata.base == stack_pointer_rtx)) | |
2065 | return 1; | |
2066 | if (CONSTANT_P (ydata.base) | |
2067 | && (xdata.base == frame_pointer_rtx | |
2068 | || xdata.base == stack_pointer_rtx)) | |
2069 | return 1; | |
2070 | /* If either base is variable, we don't know anything. */ | |
2071 | return 0; | |
2072 | } | |
2073 | ||
2074 | ||
2075 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); | |
2076 | } | |
44ace968 | 2077 | |
f72aed24 | 2078 | /* Similar, but calls decompose. */ |
44ace968 JW |
2079 | |
2080 | int | |
2081 | safe_from_earlyclobber (op, clobber) | |
2082 | rtx op, clobber; | |
2083 | { | |
2084 | struct decomposition early_data; | |
2085 | ||
2086 | early_data = decompose (clobber); | |
2087 | return immune_p (op, clobber, early_data); | |
2088 | } | |
eab89b90 RK |
2089 | \f |
2090 | /* Main entry point of this file: search the body of INSN | |
2091 | for values that need reloading and record them with push_reload. | |
2092 | REPLACE nonzero means record also where the values occur | |
2093 | so that subst_reloads can be used. | |
2094 | ||
2095 | IND_LEVELS says how many levels of indirection are supported by this | |
2096 | machine; a value of zero means that a memory reference is not a valid | |
2097 | memory address. | |
2098 | ||
2099 | LIVE_KNOWN says we have valid information about which hard | |
2100 | regs are live at each point in the program; this is true when | |
2101 | we are called from global_alloc but false when stupid register | |
2102 | allocation has been done. | |
2103 | ||
2104 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
2105 | which is nonnegative if the reg has been commandeered for reloading into. | |
2106 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
2107 | by various subroutines. */ | |
2108 | ||
2109 | void | |
2110 | find_reloads (insn, replace, ind_levels, live_known, reload_reg_p) | |
2111 | rtx insn; | |
2112 | int replace, ind_levels; | |
2113 | int live_known; | |
2114 | short *reload_reg_p; | |
2115 | { | |
eab89b90 RK |
2116 | #ifdef REGISTER_CONSTRAINTS |
2117 | ||
eab89b90 | 2118 | register int insn_code_number; |
a8c9daeb | 2119 | register int i, j; |
eab89b90 RK |
2120 | int noperands; |
2121 | /* These are the constraints for the insn. We don't change them. */ | |
2122 | char *constraints1[MAX_RECOG_OPERANDS]; | |
2123 | /* These start out as the constraints for the insn | |
2124 | and they are chewed up as we consider alternatives. */ | |
2125 | char *constraints[MAX_RECOG_OPERANDS]; | |
2126 | /* These are the preferred classes for an operand, or NO_REGS if it isn't | |
2127 | a register. */ | |
2128 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
2129 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
2130 | /* Nonzero for a MEM operand whose entire address needs a reload. */ | |
2131 | int address_reloaded[MAX_RECOG_OPERANDS]; | |
a8c9daeb RK |
2132 | /* Value of enum reload_type to use for operand. */ |
2133 | enum reload_type operand_type[MAX_RECOG_OPERANDS]; | |
2134 | /* Value of enum reload_type to use within address of operand. */ | |
2135 | enum reload_type address_type[MAX_RECOG_OPERANDS]; | |
2136 | /* Save the usage of each operand. */ | |
2137 | enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; | |
eab89b90 RK |
2138 | int no_input_reloads = 0, no_output_reloads = 0; |
2139 | int n_alternatives; | |
2140 | int this_alternative[MAX_RECOG_OPERANDS]; | |
2141 | char this_alternative_win[MAX_RECOG_OPERANDS]; | |
2142 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2143 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2144 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
2145 | int swapped; | |
2146 | int goal_alternative[MAX_RECOG_OPERANDS]; | |
2147 | int this_alternative_number; | |
2148 | int goal_alternative_number; | |
2149 | int operand_reloadnum[MAX_RECOG_OPERANDS]; | |
2150 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
2151 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
2152 | char goal_alternative_win[MAX_RECOG_OPERANDS]; | |
2153 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2154 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2155 | int goal_alternative_swapped; | |
eab89b90 RK |
2156 | int best; |
2157 | int commutative; | |
2158 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
2159 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2160 | rtx body = PATTERN (insn); | |
2161 | rtx set = single_set (insn); | |
2162 | int goal_earlyclobber, this_earlyclobber; | |
2163 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | |
2164 | ||
2165 | this_insn = insn; | |
2166 | this_insn_is_asm = 0; /* Tentative. */ | |
2167 | n_reloads = 0; | |
2168 | n_replacements = 0; | |
2169 | n_memlocs = 0; | |
2170 | n_earlyclobbers = 0; | |
2171 | replace_reloads = replace; | |
2172 | hard_regs_live_known = live_known; | |
2173 | static_reload_reg_p = reload_reg_p; | |
2174 | ||
2175 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
2176 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
2177 | to have any input reloads. */ | |
2178 | if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) | |
2179 | no_output_reloads = 1; | |
2180 | ||
2181 | #ifdef HAVE_cc0 | |
2182 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
2183 | no_input_reloads = 1; | |
2184 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
2185 | no_output_reloads = 1; | |
2186 | #endif | |
2187 | ||
0dadecf6 RK |
2188 | #ifdef SECONDARY_MEMORY_NEEDED |
2189 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
2190 | clear them out here. */ | |
2191 | ||
2192 | bzero (secondary_memlocs_elim, sizeof secondary_memlocs_elim); | |
2193 | #endif | |
2194 | ||
eab89b90 RK |
2195 | /* Find what kind of insn this is. NOPERANDS gets number of operands. |
2196 | Make OPERANDS point to a vector of operand values. | |
2197 | Make OPERAND_LOCS point to a vector of pointers to | |
2198 | where the operands were found. | |
2199 | Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the | |
2200 | constraint-strings for this insn. | |
2201 | Return if the insn needs no reload processing. */ | |
2202 | ||
2203 | switch (GET_CODE (body)) | |
2204 | { | |
2205 | case USE: | |
2206 | case CLOBBER: | |
2207 | case ASM_INPUT: | |
2208 | case ADDR_VEC: | |
2209 | case ADDR_DIFF_VEC: | |
2210 | return; | |
2211 | ||
2212 | case SET: | |
2213 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it | |
2214 | is cheap to move between them. If it is not, there may not be an insn | |
2215 | to do the copy, so we may need a reload. */ | |
2216 | if (GET_CODE (SET_DEST (body)) == REG | |
2217 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER | |
2218 | && GET_CODE (SET_SRC (body)) == REG | |
2219 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER | |
2220 | && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))), | |
2221 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) | |
2222 | return; | |
2223 | case PARALLEL: | |
2224 | case ASM_OPERANDS: | |
a8c9daeb | 2225 | reload_n_operands = noperands = asm_noperands (body); |
eab89b90 RK |
2226 | if (noperands >= 0) |
2227 | { | |
2228 | /* This insn is an `asm' with operands. */ | |
2229 | ||
2230 | insn_code_number = -1; | |
2231 | this_insn_is_asm = 1; | |
2232 | ||
2233 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
2234 | if (noperands > MAX_RECOG_OPERANDS) | |
2235 | abort (); | |
2236 | ||
2237 | /* Now get the operand values and constraints out of the insn. */ | |
2238 | ||
2239 | decode_asm_operands (body, recog_operand, recog_operand_loc, | |
2240 | constraints, operand_mode); | |
2241 | if (noperands > 0) | |
2242 | { | |
2243 | bcopy (constraints, constraints1, noperands * sizeof (char *)); | |
2244 | n_alternatives = n_occurrences (',', constraints[0]) + 1; | |
2245 | for (i = 1; i < noperands; i++) | |
d45cf215 | 2246 | if (n_alternatives != n_occurrences (',', constraints[i]) + 1) |
eab89b90 RK |
2247 | { |
2248 | error_for_asm (insn, "operand constraints differ in number of alternatives"); | |
2249 | /* Avoid further trouble with this insn. */ | |
2250 | PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); | |
2251 | n_reloads = 0; | |
2252 | return; | |
2253 | } | |
2254 | } | |
2255 | break; | |
2256 | } | |
2257 | ||
2258 | default: | |
2259 | /* Ordinary insn: recognize it, get the operands via insn_extract | |
2260 | and get the constraints. */ | |
2261 | ||
2262 | insn_code_number = recog_memoized (insn); | |
2263 | if (insn_code_number < 0) | |
2264 | fatal_insn_not_found (insn); | |
2265 | ||
a8c9daeb | 2266 | reload_n_operands = noperands = insn_n_operands[insn_code_number]; |
eab89b90 RK |
2267 | n_alternatives = insn_n_alternatives[insn_code_number]; |
2268 | /* Just return "no reloads" if insn has no operands with constraints. */ | |
2269 | if (n_alternatives == 0) | |
2270 | return; | |
2271 | insn_extract (insn); | |
2272 | for (i = 0; i < noperands; i++) | |
2273 | { | |
2274 | constraints[i] = constraints1[i] | |
2275 | = insn_operand_constraint[insn_code_number][i]; | |
2276 | operand_mode[i] = insn_operand_mode[insn_code_number][i]; | |
2277 | } | |
2278 | } | |
2279 | ||
2280 | if (noperands == 0) | |
2281 | return; | |
2282 | ||
2283 | commutative = -1; | |
2284 | ||
2285 | /* If we will need to know, later, whether some pair of operands | |
2286 | are the same, we must compare them now and save the result. | |
2287 | Reloading the base and index registers will clobber them | |
2288 | and afterward they will fail to match. */ | |
2289 | ||
2290 | for (i = 0; i < noperands; i++) | |
2291 | { | |
2292 | register char *p; | |
2293 | register int c; | |
2294 | ||
2295 | substed_operand[i] = recog_operand[i]; | |
2296 | p = constraints[i]; | |
2297 | ||
a8c9daeb RK |
2298 | modified[i] = RELOAD_READ; |
2299 | ||
2300 | /* Scan this operand's constraint to see if it is an output operand, | |
2301 | an in-out operand, is commutative, or should match another. */ | |
eab89b90 RK |
2302 | |
2303 | while (c = *p++) | |
a8c9daeb RK |
2304 | { |
2305 | if (c == '=') | |
2306 | modified[i] = RELOAD_WRITE; | |
2307 | else if (c == '+') | |
2308 | modified[i] = RELOAD_READ_WRITE; | |
2309 | else if (c == '%') | |
2310 | { | |
2311 | /* The last operand should not be marked commutative. */ | |
2312 | if (i == noperands - 1) | |
2313 | { | |
2314 | if (this_insn_is_asm) | |
2315 | warning_for_asm (this_insn, | |
2316 | "`%%' constraint used with last operand"); | |
2317 | else | |
2318 | abort (); | |
2319 | } | |
2320 | else | |
2321 | commutative = i; | |
2322 | } | |
2323 | else if (c >= '0' && c <= '9') | |
2324 | { | |
2325 | c -= '0'; | |
2326 | operands_match[c][i] | |
2327 | = operands_match_p (recog_operand[c], recog_operand[i]); | |
ea9c5b9e | 2328 | |
a8c9daeb RK |
2329 | /* An operand may not match itself. */ |
2330 | if (c == i) | |
2331 | { | |
2332 | if (this_insn_is_asm) | |
2333 | warning_for_asm (this_insn, | |
2334 | "operand %d has constraint %d", i, c); | |
2335 | else | |
2336 | abort (); | |
2337 | } | |
ea9c5b9e | 2338 | |
a8c9daeb RK |
2339 | /* If C can be commuted with C+1, and C might need to match I, |
2340 | then C+1 might also need to match I. */ | |
2341 | if (commutative >= 0) | |
2342 | { | |
2343 | if (c == commutative || c == commutative + 1) | |
2344 | { | |
2345 | int other = c + (c == commutative ? 1 : -1); | |
2346 | operands_match[other][i] | |
2347 | = operands_match_p (recog_operand[other], recog_operand[i]); | |
2348 | } | |
2349 | if (i == commutative || i == commutative + 1) | |
2350 | { | |
2351 | int other = i + (i == commutative ? 1 : -1); | |
2352 | operands_match[c][other] | |
2353 | = operands_match_p (recog_operand[c], recog_operand[other]); | |
2354 | } | |
2355 | /* Note that C is supposed to be less than I. | |
2356 | No need to consider altering both C and I because in | |
2357 | that case we would alter one into the other. */ | |
2358 | } | |
2359 | } | |
2360 | } | |
eab89b90 RK |
2361 | } |
2362 | ||
2363 | /* Examine each operand that is a memory reference or memory address | |
2364 | and reload parts of the addresses into index registers. | |
eab89b90 RK |
2365 | Also here any references to pseudo regs that didn't get hard regs |
2366 | but are equivalent to constants get replaced in the insn itself | |
2367 | with those constants. Nobody will ever see them again. | |
2368 | ||
2369 | Finally, set up the preferred classes of each operand. */ | |
2370 | ||
2371 | for (i = 0; i < noperands; i++) | |
2372 | { | |
2373 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
a8c9daeb | 2374 | |
eab89b90 | 2375 | address_reloaded[i] = 0; |
a8c9daeb RK |
2376 | operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT |
2377 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT | |
2378 | : RELOAD_OTHER); | |
2379 | address_type[i] | |
2380 | = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS | |
2381 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS | |
2382 | : RELOAD_OTHER); | |
eab89b90 RK |
2383 | |
2384 | if (constraints[i][0] == 'p') | |
2385 | { | |
fb3821f7 | 2386 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 | 2387 | recog_operand[i], recog_operand_loc[i], |
a8c9daeb | 2388 | i, operand_type[i], ind_levels); |
eab89b90 RK |
2389 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; |
2390 | } | |
2391 | else if (code == MEM) | |
2392 | { | |
2393 | if (find_reloads_address (GET_MODE (recog_operand[i]), | |
2394 | recog_operand_loc[i], | |
2395 | XEXP (recog_operand[i], 0), | |
2396 | &XEXP (recog_operand[i], 0), | |
a8c9daeb | 2397 | i, address_type[i], ind_levels)) |
eab89b90 RK |
2398 | address_reloaded[i] = 1; |
2399 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; | |
2400 | } | |
2401 | else if (code == SUBREG) | |
2402 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] | |
a8c9daeb RK |
2403 | = find_reloads_toplev (recog_operand[i], i, address_type[i], |
2404 | ind_levels, | |
eab89b90 RK |
2405 | set != 0 |
2406 | && &SET_DEST (set) == recog_operand_loc[i]); | |
2407 | else if (code == REG) | |
2408 | { | |
2409 | /* This is equivalent to calling find_reloads_toplev. | |
2410 | The code is duplicated for speed. | |
2411 | When we find a pseudo always equivalent to a constant, | |
2412 | we replace it by the constant. We must be sure, however, | |
2413 | that we don't try to replace it in the insn in which it | |
2414 | is being set. */ | |
2415 | register int regno = REGNO (recog_operand[i]); | |
2416 | if (reg_equiv_constant[regno] != 0 | |
2417 | && (set == 0 || &SET_DEST (set) != recog_operand_loc[i])) | |
2418 | substed_operand[i] = recog_operand[i] | |
2419 | = reg_equiv_constant[regno]; | |
2420 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
2421 | that feeds this insn. */ | |
2422 | if (reg_equiv_mem[regno] != 0) | |
2423 | substed_operand[i] = recog_operand[i] | |
2424 | = reg_equiv_mem[regno]; | |
2425 | #endif | |
2426 | if (reg_equiv_address[regno] != 0) | |
2427 | { | |
2428 | /* If reg_equiv_address is not a constant address, copy it, | |
2429 | since it may be shared. */ | |
2430 | rtx address = reg_equiv_address[regno]; | |
2431 | ||
2432 | if (rtx_varies_p (address)) | |
2433 | address = copy_rtx (address); | |
2434 | ||
2435 | /* If this is an output operand, we must output a CLOBBER | |
a8c9daeb RK |
2436 | after INSN so find_equiv_reg knows REGNO is being written. |
2437 | Mark this insn specially, do we can put our output reloads | |
2438 | after it. */ | |
2439 | ||
2440 | if (modified[i] != RELOAD_READ) | |
2441 | PUT_MODE (emit_insn_after (gen_rtx (CLOBBER, VOIDmode, | |
2442 | recog_operand[i]), | |
2443 | insn), | |
2444 | DImode); | |
eab89b90 RK |
2445 | |
2446 | *recog_operand_loc[i] = recog_operand[i] | |
2447 | = gen_rtx (MEM, GET_MODE (recog_operand[i]), address); | |
2448 | RTX_UNCHANGING_P (recog_operand[i]) | |
2449 | = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
2450 | find_reloads_address (GET_MODE (recog_operand[i]), | |
130659a4 | 2451 | recog_operand_loc[i], |
eab89b90 RK |
2452 | XEXP (recog_operand[i], 0), |
2453 | &XEXP (recog_operand[i], 0), | |
a8c9daeb | 2454 | i, address_type[i], ind_levels); |
eab89b90 RK |
2455 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; |
2456 | } | |
2457 | } | |
aaf9712e RS |
2458 | /* If the operand is still a register (we didn't replace it with an |
2459 | equivalent), get the preferred class to reload it into. */ | |
2460 | code = GET_CODE (recog_operand[i]); | |
2461 | preferred_class[i] | |
91f9a6ed | 2462 | = ((code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) |
aaf9712e RS |
2463 | ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS); |
2464 | pref_or_nothing[i] | |
91f9a6ed | 2465 | = (code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER |
e4600702 | 2466 | && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS); |
eab89b90 RK |
2467 | } |
2468 | ||
2469 | /* If this is simply a copy from operand 1 to operand 0, merge the | |
2470 | preferred classes for the operands. */ | |
2471 | if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set) | |
2472 | && recog_operand[1] == SET_SRC (set)) | |
2473 | { | |
2474 | preferred_class[0] = preferred_class[1] | |
2475 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2476 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2477 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2478 | } | |
2479 | ||
2480 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2481 | or got the wrong kind of hard reg. For this, we must consider | |
2482 | all the operands together against the register constraints. */ | |
2483 | ||
2484 | best = MAX_RECOG_OPERANDS + 300; | |
2485 | ||
2486 | swapped = 0; | |
2487 | goal_alternative_swapped = 0; | |
2488 | try_swapped: | |
2489 | ||
2490 | /* The constraints are made of several alternatives. | |
2491 | Each operand's constraint looks like foo,bar,... with commas | |
2492 | separating the alternatives. The first alternatives for all | |
2493 | operands go together, the second alternatives go together, etc. | |
2494 | ||
2495 | First loop over alternatives. */ | |
2496 | ||
2497 | for (this_alternative_number = 0; | |
2498 | this_alternative_number < n_alternatives; | |
2499 | this_alternative_number++) | |
2500 | { | |
2501 | /* Loop over operands for one constraint alternative. */ | |
2502 | /* LOSERS counts those that don't fit this alternative | |
2503 | and would require loading. */ | |
2504 | int losers = 0; | |
2505 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2506 | even after reloading. */ | |
2507 | int bad = 0; | |
2508 | /* REJECT is a count of how undesirable this alternative says it is | |
2509 | if any reloading is required. If the alternative matches exactly | |
2510 | then REJECT is ignored, but otherwise it gets this much | |
2511 | counted against it in addition to the reloading needed. Each | |
2512 | ? counts three times here since we want the disparaging caused by | |
2513 | a bad register class to only count 1/3 as much. */ | |
2514 | int reject = 0; | |
2515 | ||
2516 | this_earlyclobber = 0; | |
2517 | ||
2518 | for (i = 0; i < noperands; i++) | |
2519 | { | |
2520 | register char *p = constraints[i]; | |
2521 | register int win = 0; | |
2522 | /* 0 => this operand can be reloaded somehow for this alternative */ | |
2523 | int badop = 1; | |
2524 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2525 | int winreg = 0; | |
2526 | int c; | |
2527 | register rtx operand = recog_operand[i]; | |
2528 | int offset = 0; | |
2529 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2530 | regardless of what the constraint says. */ | |
2531 | int force_reload = 0; | |
2532 | int offmemok = 0; | |
2533 | int earlyclobber = 0; | |
2534 | ||
2535 | /* If the operand is a SUBREG, extract | |
2536 | the REG or MEM (or maybe even a constant) within. | |
2537 | (Constants can occur as a result of reg_equiv_constant.) */ | |
2538 | ||
2539 | while (GET_CODE (operand) == SUBREG) | |
2540 | { | |
2541 | offset += SUBREG_WORD (operand); | |
2542 | operand = SUBREG_REG (operand); | |
2543 | /* Force reload if this is not a register or if there may may | |
2544 | be a problem accessing the register in the outer mode. */ | |
2545 | if (GET_CODE (operand) != REG | |
46da6b3a | 2546 | #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) |
f72ccbe6 RK |
2547 | /* If we have a SUBREG where both the inner and outer |
2548 | modes are different but no wider than a word, combine.c | |
2549 | has made assumptions about the behavior of the machine | |
2550 | in such register access. If the data is, in fact, in | |
2551 | memory we must always load using the size assumed to | |
2552 | be in the register and let the insn do the different-sized | |
2553 | accesses. */ | |
2554 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2555 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
2556 | && GET_MODE_SIZE (GET_MODE (operand)) <= UNITS_PER_WORD) | |
46da6b3a | 2557 | #endif |
eab89b90 RK |
2558 | /* Subreg of a hard reg which can't handle the subreg's mode |
2559 | or which would handle that mode in the wrong number of | |
2560 | registers for subregging to work. */ | |
2561 | || (REGNO (operand) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
2562 | && ((GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
2563 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2564 | > UNITS_PER_WORD) | |
2565 | && ((GET_MODE_SIZE (GET_MODE (operand)) | |
2566 | / UNITS_PER_WORD) | |
2567 | != HARD_REGNO_NREGS (REGNO (operand), | |
2568 | GET_MODE (operand)))) | |
2569 | || ! HARD_REGNO_MODE_OK (REGNO (operand) + offset, | |
2570 | operand_mode[i])))) | |
eab89b90 RK |
2571 | force_reload = 1; |
2572 | } | |
2573 | ||
2574 | this_alternative[i] = (int) NO_REGS; | |
2575 | this_alternative_win[i] = 0; | |
2576 | this_alternative_offmemok[i] = 0; | |
2577 | this_alternative_earlyclobber[i] = 0; | |
2578 | this_alternative_matches[i] = -1; | |
2579 | ||
2580 | /* An empty constraint or empty alternative | |
2581 | allows anything which matched the pattern. */ | |
2582 | if (*p == 0 || *p == ',') | |
2583 | win = 1, badop = 0; | |
2584 | ||
2585 | /* Scan this alternative's specs for this operand; | |
2586 | set WIN if the operand fits any letter in this alternative. | |
2587 | Otherwise, clear BADOP if this operand could | |
2588 | fit some letter after reloads, | |
2589 | or set WINREG if this operand could fit after reloads | |
2590 | provided the constraint allows some registers. */ | |
2591 | ||
2592 | while (*p && (c = *p++) != ',') | |
2593 | switch (c) | |
2594 | { | |
2595 | case '=': | |
eab89b90 | 2596 | case '+': |
eab89b90 RK |
2597 | case '*': |
2598 | break; | |
2599 | ||
2600 | case '%': | |
42add480 TW |
2601 | /* The last operand should not be marked commutative. */ |
2602 | if (i != noperands - 1) | |
2603 | commutative = i; | |
eab89b90 RK |
2604 | break; |
2605 | ||
2606 | case '?': | |
2607 | reject += 3; | |
2608 | break; | |
2609 | ||
2610 | case '!': | |
2611 | reject = 300; | |
2612 | break; | |
2613 | ||
2614 | case '#': | |
2615 | /* Ignore rest of this alternative as far as | |
2616 | reloading is concerned. */ | |
2617 | while (*p && *p != ',') p++; | |
2618 | break; | |
2619 | ||
2620 | case '0': | |
2621 | case '1': | |
2622 | case '2': | |
2623 | case '3': | |
2624 | case '4': | |
2625 | c -= '0'; | |
2626 | this_alternative_matches[i] = c; | |
2627 | /* We are supposed to match a previous operand. | |
2628 | If we do, we win if that one did. | |
2629 | If we do not, count both of the operands as losers. | |
2630 | (This is too conservative, since most of the time | |
2631 | only a single reload insn will be needed to make | |
2632 | the two operands win. As a result, this alternative | |
2633 | may be rejected when it is actually desirable.) */ | |
2634 | if ((swapped && (c != commutative || i != commutative + 1)) | |
2635 | /* If we are matching as if two operands were swapped, | |
2636 | also pretend that operands_match had been computed | |
2637 | with swapped. | |
2638 | But if I is the second of those and C is the first, | |
2639 | don't exchange them, because operands_match is valid | |
2640 | only on one side of its diagonal. */ | |
2641 | ? (operands_match | |
2642 | [(c == commutative || c == commutative + 1) | |
2643 | ? 2*commutative + 1 - c : c] | |
2644 | [(i == commutative || i == commutative + 1) | |
2645 | ? 2*commutative + 1 - i : i]) | |
2646 | : operands_match[c][i]) | |
2647 | win = this_alternative_win[c]; | |
2648 | else | |
2649 | { | |
2650 | /* Operands don't match. */ | |
2651 | rtx value; | |
2652 | /* Retroactively mark the operand we had to match | |
2653 | as a loser, if it wasn't already. */ | |
2654 | if (this_alternative_win[c]) | |
2655 | losers++; | |
2656 | this_alternative_win[c] = 0; | |
2657 | if (this_alternative[c] == (int) NO_REGS) | |
2658 | bad = 1; | |
2659 | /* But count the pair only once in the total badness of | |
2660 | this alternative, if the pair can be a dummy reload. */ | |
2661 | value | |
2662 | = find_dummy_reload (recog_operand[i], recog_operand[c], | |
2663 | recog_operand_loc[i], recog_operand_loc[c], | |
2664 | this_alternative[c], -1); | |
2665 | ||
2666 | if (value != 0) | |
2667 | losers--; | |
2668 | } | |
2669 | /* This can be fixed with reloads if the operand | |
2670 | we are supposed to match can be fixed with reloads. */ | |
2671 | badop = 0; | |
2672 | this_alternative[i] = this_alternative[c]; | |
2673 | break; | |
2674 | ||
2675 | case 'p': | |
2676 | /* All necessary reloads for an address_operand | |
2677 | were handled in find_reloads_address. */ | |
2678 | this_alternative[i] = (int) ALL_REGS; | |
2679 | win = 1; | |
2680 | break; | |
2681 | ||
2682 | case 'm': | |
2683 | if (force_reload) | |
2684 | break; | |
2685 | if (GET_CODE (operand) == MEM | |
2686 | || (GET_CODE (operand) == REG | |
2687 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2688 | && reg_renumber[REGNO (operand)] < 0)) | |
2689 | win = 1; | |
2690 | if (CONSTANT_P (operand)) | |
2691 | badop = 0; | |
2692 | break; | |
2693 | ||
2694 | case '<': | |
2695 | if (GET_CODE (operand) == MEM | |
2696 | && ! address_reloaded[i] | |
2697 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
2698 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
2699 | win = 1; | |
2700 | break; | |
2701 | ||
2702 | case '>': | |
2703 | if (GET_CODE (operand) == MEM | |
2704 | && ! address_reloaded[i] | |
2705 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
2706 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
2707 | win = 1; | |
2708 | break; | |
2709 | ||
2710 | /* Memory operand whose address is not offsettable. */ | |
2711 | case 'V': | |
2712 | if (force_reload) | |
2713 | break; | |
2714 | if (GET_CODE (operand) == MEM | |
2715 | && ! (ind_levels ? offsettable_memref_p (operand) | |
2716 | : offsettable_nonstrict_memref_p (operand)) | |
2717 | /* Certain mem addresses will become offsettable | |
2718 | after they themselves are reloaded. This is important; | |
2719 | we don't want our own handling of unoffsettables | |
2720 | to override the handling of reg_equiv_address. */ | |
2721 | && !(GET_CODE (XEXP (operand, 0)) == REG | |
2722 | && (ind_levels == 0 | |
2723 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) | |
2724 | win = 1; | |
2725 | break; | |
2726 | ||
2727 | /* Memory operand whose address is offsettable. */ | |
2728 | case 'o': | |
2729 | if (force_reload) | |
2730 | break; | |
2731 | if ((GET_CODE (operand) == MEM | |
2732 | /* If IND_LEVELS, find_reloads_address won't reload a | |
2733 | pseudo that didn't get a hard reg, so we have to | |
2734 | reject that case. */ | |
2735 | && (ind_levels ? offsettable_memref_p (operand) | |
2736 | : offsettable_nonstrict_memref_p (operand))) | |
2737 | /* Certain mem addresses will become offsettable | |
2738 | after they themselves are reloaded. This is important; | |
2739 | we don't want our own handling of unoffsettables | |
2740 | to override the handling of reg_equiv_address. */ | |
2741 | || (GET_CODE (operand) == MEM | |
2742 | && GET_CODE (XEXP (operand, 0)) == REG | |
2743 | && (ind_levels == 0 | |
2744 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)) | |
2745 | || (GET_CODE (operand) == REG | |
2746 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2747 | && reg_renumber[REGNO (operand)] < 0)) | |
2748 | win = 1; | |
2749 | if (CONSTANT_P (operand) || GET_CODE (operand) == MEM) | |
2750 | badop = 0; | |
2751 | offmemok = 1; | |
2752 | break; | |
2753 | ||
2754 | case '&': | |
2755 | /* Output operand that is stored before the need for the | |
2756 | input operands (and their index registers) is over. */ | |
2757 | earlyclobber = 1, this_earlyclobber = 1; | |
2758 | break; | |
2759 | ||
2760 | case 'E': | |
2761 | /* Match any floating double constant, but only if | |
2762 | we can examine the bits of it reliably. */ | |
2763 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
fb3821f7 | 2764 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
eab89b90 RK |
2765 | && GET_MODE (operand) != VOIDmode && ! flag_pretend_float) |
2766 | break; | |
2767 | if (GET_CODE (operand) == CONST_DOUBLE) | |
2768 | win = 1; | |
2769 | break; | |
2770 | ||
2771 | case 'F': | |
2772 | if (GET_CODE (operand) == CONST_DOUBLE) | |
2773 | win = 1; | |
2774 | break; | |
2775 | ||
2776 | case 'G': | |
2777 | case 'H': | |
2778 | if (GET_CODE (operand) == CONST_DOUBLE | |
2779 | && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c)) | |
2780 | win = 1; | |
2781 | break; | |
2782 | ||
2783 | case 's': | |
2784 | if (GET_CODE (operand) == CONST_INT | |
2785 | || (GET_CODE (operand) == CONST_DOUBLE | |
2786 | && GET_MODE (operand) == VOIDmode)) | |
2787 | break; | |
2788 | case 'i': | |
2789 | if (CONSTANT_P (operand) | |
2790 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2791 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)) | |
2792 | #endif | |
2793 | ) | |
2794 | win = 1; | |
2795 | break; | |
2796 | ||
2797 | case 'n': | |
2798 | if (GET_CODE (operand) == CONST_INT | |
2799 | || (GET_CODE (operand) == CONST_DOUBLE | |
2800 | && GET_MODE (operand) == VOIDmode)) | |
2801 | win = 1; | |
2802 | break; | |
2803 | ||
2804 | case 'I': | |
2805 | case 'J': | |
2806 | case 'K': | |
2807 | case 'L': | |
2808 | case 'M': | |
2809 | case 'N': | |
2810 | case 'O': | |
2811 | case 'P': | |
2812 | if (GET_CODE (operand) == CONST_INT | |
2813 | && CONST_OK_FOR_LETTER_P (INTVAL (operand), c)) | |
2814 | win = 1; | |
2815 | break; | |
2816 | ||
2817 | case 'X': | |
2818 | win = 1; | |
2819 | break; | |
2820 | ||
2821 | case 'g': | |
2822 | if (! force_reload | |
2823 | /* A PLUS is never a valid operand, but reload can make | |
2824 | it from a register when eliminating registers. */ | |
2825 | && GET_CODE (operand) != PLUS | |
2826 | /* A SCRATCH is not a valid operand. */ | |
2827 | && GET_CODE (operand) != SCRATCH | |
2828 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2829 | && (! CONSTANT_P (operand) | |
2830 | || ! flag_pic | |
2831 | || LEGITIMATE_PIC_OPERAND_P (operand)) | |
2832 | #endif | |
2833 | && (GENERAL_REGS == ALL_REGS | |
2834 | || GET_CODE (operand) != REG | |
2835 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2836 | && reg_renumber[REGNO (operand)] < 0))) | |
2837 | win = 1; | |
2838 | /* Drop through into 'r' case */ | |
2839 | ||
2840 | case 'r': | |
2841 | this_alternative[i] | |
2842 | = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; | |
2843 | goto reg; | |
2844 | ||
2845 | #ifdef EXTRA_CONSTRAINT | |
2846 | case 'Q': | |
2847 | case 'R': | |
2848 | case 'S': | |
2849 | case 'T': | |
2850 | case 'U': | |
2851 | if (EXTRA_CONSTRAINT (operand, c)) | |
2852 | win = 1; | |
2853 | break; | |
2854 | #endif | |
2855 | ||
2856 | default: | |
2857 | this_alternative[i] | |
2858 | = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)]; | |
2859 | ||
2860 | reg: | |
2861 | if (GET_MODE (operand) == BLKmode) | |
2862 | break; | |
2863 | winreg = 1; | |
2864 | if (GET_CODE (operand) == REG | |
2865 | && reg_fits_class_p (operand, this_alternative[i], | |
2866 | offset, GET_MODE (recog_operand[i]))) | |
2867 | win = 1; | |
2868 | break; | |
2869 | } | |
2870 | ||
2871 | constraints[i] = p; | |
2872 | ||
2873 | /* If this operand could be handled with a reg, | |
2874 | and some reg is allowed, then this operand can be handled. */ | |
2875 | if (winreg && this_alternative[i] != (int) NO_REGS) | |
2876 | badop = 0; | |
2877 | ||
2878 | /* Record which operands fit this alternative. */ | |
2879 | this_alternative_earlyclobber[i] = earlyclobber; | |
2880 | if (win && ! force_reload) | |
2881 | this_alternative_win[i] = 1; | |
2882 | else | |
2883 | { | |
2884 | this_alternative_offmemok[i] = offmemok; | |
2885 | losers++; | |
2886 | if (badop) | |
2887 | bad = 1; | |
2888 | /* Alternative loses if it has no regs for a reg operand. */ | |
2889 | if (GET_CODE (operand) == REG | |
2890 | && this_alternative[i] == (int) NO_REGS | |
2891 | && this_alternative_matches[i] < 0) | |
2892 | bad = 1; | |
2893 | ||
2894 | /* Alternative loses if it requires a type of reload not | |
2895 | permitted for this insn. We can always reload SCRATCH | |
2896 | and objects with a REG_UNUSED note. */ | |
a8c9daeb RK |
2897 | if (GET_CODE (operand) != SCRATCH |
2898 | && modified[i] != RELOAD_READ && no_output_reloads | |
eab89b90 RK |
2899 | && ! find_reg_note (insn, REG_UNUSED, operand)) |
2900 | bad = 1; | |
2901 | else if (modified[i] != RELOAD_WRITE && no_input_reloads) | |
2902 | bad = 1; | |
2903 | ||
2904 | /* We prefer to reload pseudos over reloading other things, | |
2905 | since such reloads may be able to be eliminated later. | |
2906 | If we are reloading a SCRATCH, we won't be generating any | |
2907 | insns, just using a register, so it is also preferred. | |
2908 | So bump REJECT in other cases. */ | |
2909 | if (GET_CODE (operand) != REG && GET_CODE (operand) != SCRATCH) | |
2910 | reject++; | |
2911 | } | |
2912 | ||
2913 | /* If this operand is a pseudo register that didn't get a hard | |
2914 | reg and this alternative accepts some register, see if the | |
2915 | class that we want is a subset of the preferred class for this | |
2916 | register. If not, but it intersects that class, use the | |
2917 | preferred class instead. If it does not intersect the preferred | |
2918 | class, show that usage of this alternative should be discouraged; | |
2919 | it will be discouraged more still if the register is `preferred | |
2920 | or nothing'. We do this because it increases the chance of | |
2921 | reusing our spill register in a later insn and avoiding a pair | |
2922 | of memory stores and loads. | |
2923 | ||
2924 | Don't bother with this if this alternative will accept this | |
2925 | operand. | |
2926 | ||
5aa14fee RS |
2927 | Don't do this for a multiword operand, if |
2928 | we have to worry about small classes, because making reg groups | |
2929 | harder to allocate is asking for trouble. | |
2930 | ||
eab89b90 RK |
2931 | Don't do this if the preferred class has only one register |
2932 | because we might otherwise exhaust the class. */ | |
2933 | ||
2934 | ||
2935 | if (! win && this_alternative[i] != (int) NO_REGS | |
5aa14fee RS |
2936 | #ifdef SMALL_REGISTER_CLASSES |
2937 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
2938 | #endif | |
eab89b90 RK |
2939 | && reg_class_size[(int) preferred_class[i]] > 1) |
2940 | { | |
2941 | if (! reg_class_subset_p (this_alternative[i], | |
2942 | preferred_class[i])) | |
2943 | { | |
2944 | /* Since we don't have a way of forming the intersection, | |
2945 | we just do something special if the preferred class | |
2946 | is a subset of the class we have; that's the most | |
2947 | common case anyway. */ | |
2948 | if (reg_class_subset_p (preferred_class[i], | |
2949 | this_alternative[i])) | |
2950 | this_alternative[i] = (int) preferred_class[i]; | |
2951 | else | |
2952 | reject += (1 + pref_or_nothing[i]); | |
2953 | } | |
2954 | } | |
2955 | } | |
2956 | ||
2957 | /* Now see if any output operands that are marked "earlyclobber" | |
2958 | in this alternative conflict with any input operands | |
2959 | or any memory addresses. */ | |
2960 | ||
2961 | for (i = 0; i < noperands; i++) | |
2962 | if (this_alternative_earlyclobber[i] | |
2963 | && this_alternative_win[i]) | |
2964 | { | |
2965 | struct decomposition early_data; | |
eab89b90 RK |
2966 | |
2967 | early_data = decompose (recog_operand[i]); | |
2968 | ||
2969 | if (modified[i] == RELOAD_READ) | |
2970 | { | |
2971 | if (this_insn_is_asm) | |
2972 | warning_for_asm (this_insn, | |
2973 | "`&' constraint used with input operand"); | |
2974 | else | |
2975 | abort (); | |
2976 | continue; | |
2977 | } | |
2978 | ||
2979 | if (this_alternative[i] == NO_REGS) | |
2980 | { | |
2981 | this_alternative_earlyclobber[i] = 0; | |
2982 | if (this_insn_is_asm) | |
2983 | error_for_asm (this_insn, | |
2984 | "`&' constraint used with no register class"); | |
2985 | else | |
2986 | abort (); | |
2987 | } | |
2988 | ||
2989 | for (j = 0; j < noperands; j++) | |
2990 | /* Is this an input operand or a memory ref? */ | |
2991 | if ((GET_CODE (recog_operand[j]) == MEM | |
2992 | || modified[j] != RELOAD_WRITE) | |
2993 | && j != i | |
2994 | /* Ignore things like match_operator operands. */ | |
2995 | && *constraints1[j] != 0 | |
2996 | /* Don't count an input operand that is constrained to match | |
2997 | the early clobber operand. */ | |
2998 | && ! (this_alternative_matches[j] == i | |
2999 | && rtx_equal_p (recog_operand[i], recog_operand[j])) | |
3000 | /* Is it altered by storing the earlyclobber operand? */ | |
3001 | && !immune_p (recog_operand[j], recog_operand[i], early_data)) | |
3002 | { | |
3003 | /* If the output is in a single-reg class, | |
3004 | it's costly to reload it, so reload the input instead. */ | |
3005 | if (reg_class_size[this_alternative[i]] == 1 | |
3006 | && (GET_CODE (recog_operand[j]) == REG | |
3007 | || GET_CODE (recog_operand[j]) == SUBREG)) | |
3008 | { | |
3009 | losers++; | |
3010 | this_alternative_win[j] = 0; | |
3011 | } | |
3012 | else | |
3013 | break; | |
3014 | } | |
3015 | /* If an earlyclobber operand conflicts with something, | |
3016 | it must be reloaded, so request this and count the cost. */ | |
3017 | if (j != noperands) | |
3018 | { | |
3019 | losers++; | |
3020 | this_alternative_win[i] = 0; | |
3021 | for (j = 0; j < noperands; j++) | |
3022 | if (this_alternative_matches[j] == i | |
3023 | && this_alternative_win[j]) | |
3024 | { | |
3025 | this_alternative_win[j] = 0; | |
3026 | losers++; | |
3027 | } | |
3028 | } | |
3029 | } | |
3030 | ||
3031 | /* If one alternative accepts all the operands, no reload required, | |
3032 | choose that alternative; don't consider the remaining ones. */ | |
3033 | if (losers == 0) | |
3034 | { | |
3035 | /* Unswap these so that they are never swapped at `finish'. */ | |
3036 | if (commutative >= 0) | |
3037 | { | |
3038 | recog_operand[commutative] = substed_operand[commutative]; | |
3039 | recog_operand[commutative + 1] | |
3040 | = substed_operand[commutative + 1]; | |
3041 | } | |
3042 | for (i = 0; i < noperands; i++) | |
3043 | { | |
3044 | goal_alternative_win[i] = 1; | |
3045 | goal_alternative[i] = this_alternative[i]; | |
3046 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3047 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3048 | goal_alternative_earlyclobber[i] | |
3049 | = this_alternative_earlyclobber[i]; | |
3050 | } | |
3051 | goal_alternative_number = this_alternative_number; | |
3052 | goal_alternative_swapped = swapped; | |
3053 | goal_earlyclobber = this_earlyclobber; | |
3054 | goto finish; | |
3055 | } | |
3056 | ||
3057 | /* REJECT, set by the ! and ? constraint characters and when a register | |
3058 | would be reloaded into a non-preferred class, discourages the use of | |
3059 | this alternative for a reload goal. REJECT is incremented by three | |
3060 | for each ? and one for each non-preferred class. */ | |
3061 | losers = losers * 3 + reject; | |
3062 | ||
3063 | /* If this alternative can be made to work by reloading, | |
3064 | and it needs less reloading than the others checked so far, | |
3065 | record it as the chosen goal for reloading. */ | |
3066 | if (! bad && best > losers) | |
3067 | { | |
3068 | for (i = 0; i < noperands; i++) | |
3069 | { | |
3070 | goal_alternative[i] = this_alternative[i]; | |
3071 | goal_alternative_win[i] = this_alternative_win[i]; | |
3072 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3073 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3074 | goal_alternative_earlyclobber[i] | |
3075 | = this_alternative_earlyclobber[i]; | |
3076 | } | |
3077 | goal_alternative_swapped = swapped; | |
3078 | best = losers; | |
3079 | goal_alternative_number = this_alternative_number; | |
3080 | goal_earlyclobber = this_earlyclobber; | |
3081 | } | |
3082 | } | |
3083 | ||
3084 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
3085 | then we need to try each alternative twice, | |
3086 | the second time matching those two operands | |
3087 | as if we had exchanged them. | |
3088 | To do this, really exchange them in operands. | |
3089 | ||
3090 | If we have just tried the alternatives the second time, | |
3091 | return operands to normal and drop through. */ | |
3092 | ||
3093 | if (commutative >= 0) | |
3094 | { | |
3095 | swapped = !swapped; | |
3096 | if (swapped) | |
3097 | { | |
3098 | register enum reg_class tclass; | |
3099 | register int t; | |
3100 | ||
3101 | recog_operand[commutative] = substed_operand[commutative + 1]; | |
3102 | recog_operand[commutative + 1] = substed_operand[commutative]; | |
3103 | ||
3104 | tclass = preferred_class[commutative]; | |
3105 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
3106 | preferred_class[commutative + 1] = tclass; | |
3107 | ||
3108 | t = pref_or_nothing[commutative]; | |
3109 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
3110 | pref_or_nothing[commutative + 1] = t; | |
3111 | ||
3112 | bcopy (constraints1, constraints, noperands * sizeof (char *)); | |
3113 | goto try_swapped; | |
3114 | } | |
3115 | else | |
3116 | { | |
3117 | recog_operand[commutative] = substed_operand[commutative]; | |
3118 | recog_operand[commutative + 1] = substed_operand[commutative + 1]; | |
3119 | } | |
3120 | } | |
3121 | ||
3122 | /* The operands don't meet the constraints. | |
3123 | goal_alternative describes the alternative | |
3124 | that we could reach by reloading the fewest operands. | |
3125 | Reload so as to fit it. */ | |
3126 | ||
3127 | if (best == MAX_RECOG_OPERANDS + 300) | |
3128 | { | |
3129 | /* No alternative works with reloads?? */ | |
3130 | if (insn_code_number >= 0) | |
3131 | abort (); | |
3132 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3133 | /* Avoid further trouble with this insn. */ | |
3134 | PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); | |
3135 | n_reloads = 0; | |
3136 | return; | |
3137 | } | |
3138 | ||
3139 | /* Jump to `finish' from above if all operands are valid already. | |
3140 | In that case, goal_alternative_win is all 1. */ | |
3141 | finish: | |
3142 | ||
3143 | /* Right now, for any pair of operands I and J that are required to match, | |
3144 | with I < J, | |
3145 | goal_alternative_matches[J] is I. | |
3146 | Set up goal_alternative_matched as the inverse function: | |
3147 | goal_alternative_matched[I] = J. */ | |
3148 | ||
3149 | for (i = 0; i < noperands; i++) | |
3150 | goal_alternative_matched[i] = -1; | |
3151 | ||
3152 | for (i = 0; i < noperands; i++) | |
3153 | if (! goal_alternative_win[i] | |
3154 | && goal_alternative_matches[i] >= 0) | |
3155 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
3156 | ||
3157 | /* If the best alternative is with operands 1 and 2 swapped, | |
a8c9daeb RK |
3158 | consider them swapped before reporting the reloads. Update the |
3159 | operand numbers of any reloads already pushed. */ | |
eab89b90 RK |
3160 | |
3161 | if (goal_alternative_swapped) | |
3162 | { | |
3163 | register rtx tem; | |
3164 | ||
3165 | tem = substed_operand[commutative]; | |
3166 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
3167 | substed_operand[commutative + 1] = tem; | |
3168 | tem = recog_operand[commutative]; | |
3169 | recog_operand[commutative] = recog_operand[commutative + 1]; | |
3170 | recog_operand[commutative + 1] = tem; | |
a8c9daeb RK |
3171 | |
3172 | for (i = 0; i < n_reloads; i++) | |
3173 | { | |
3174 | if (reload_opnum[i] == commutative) | |
3175 | reload_opnum[i] = commutative + 1; | |
3176 | else if (reload_opnum[i] == commutative + 1) | |
3177 | reload_opnum[i] = commutative; | |
3178 | } | |
eab89b90 RK |
3179 | } |
3180 | ||
3181 | /* Perform whatever substitutions on the operands we are supposed | |
3182 | to make due to commutativity or replacement of registers | |
3183 | with equivalent constants or memory slots. */ | |
3184 | ||
3185 | for (i = 0; i < noperands; i++) | |
3186 | { | |
3187 | *recog_operand_loc[i] = substed_operand[i]; | |
3188 | /* While we are looping on operands, initialize this. */ | |
3189 | operand_reloadnum[i] = -1; | |
a8c9daeb RK |
3190 | |
3191 | /* If this is an earlyclobber operand, we need to widen the scope. | |
3192 | The reload must remain valid from the start of the insn being | |
3193 | reloaded until after the operand is stored into its destination. | |
3194 | We approximate this with RELOAD_OTHER even though we know that we | |
3195 | do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. | |
3196 | ||
3197 | One special case that is worth checking is when we have an | |
3198 | output that is earlyclobber but isn't used past the insn (typically | |
3199 | a SCRATCH). In this case, we only need have the reload live | |
3200 | through the insn itself, but not for any of our input or output | |
3201 | reloads. | |
3202 | ||
3203 | In any case, anything needed to address this operand can remain | |
3204 | however they were previously categorized. */ | |
3205 | ||
3206 | if (goal_alternative_earlyclobber[i]) | |
3207 | operand_type[i] | |
3208 | = (find_reg_note (insn, REG_UNUSED, recog_operand[i]) | |
3209 | ? RELOAD_FOR_INSN : RELOAD_OTHER); | |
eab89b90 RK |
3210 | } |
3211 | ||
3212 | /* Any constants that aren't allowed and can't be reloaded | |
3213 | into registers are here changed into memory references. */ | |
3214 | for (i = 0; i < noperands; i++) | |
3215 | if (! goal_alternative_win[i] | |
3216 | && CONSTANT_P (recog_operand[i]) | |
3217 | && (PREFERRED_RELOAD_CLASS (recog_operand[i], | |
3218 | (enum reg_class) goal_alternative[i]) | |
3219 | == NO_REGS) | |
3220 | && operand_mode[i] != VOIDmode) | |
3221 | { | |
3222 | *recog_operand_loc[i] = recog_operand[i] | |
3223 | = find_reloads_toplev (force_const_mem (operand_mode[i], | |
3224 | recog_operand[i]), | |
a8c9daeb | 3225 | i, address_type[i], ind_levels, 0); |
eab89b90 RK |
3226 | if (alternative_allows_memconst (constraints1[i], |
3227 | goal_alternative_number)) | |
3228 | goal_alternative_win[i] = 1; | |
3229 | } | |
3230 | ||
3231 | /* Now record reloads for all the operands that need them. */ | |
3232 | for (i = 0; i < noperands; i++) | |
3233 | if (! goal_alternative_win[i]) | |
3234 | { | |
3235 | /* Operands that match previous ones have already been handled. */ | |
3236 | if (goal_alternative_matches[i] >= 0) | |
3237 | ; | |
3238 | /* Handle an operand with a nonoffsettable address | |
3239 | appearing where an offsettable address will do | |
3240 | by reloading the address into a base register. */ | |
3241 | else if (goal_alternative_matched[i] == -1 | |
3242 | && goal_alternative_offmemok[i] | |
3243 | && GET_CODE (recog_operand[i]) == MEM) | |
3244 | { | |
3245 | operand_reloadnum[i] | |
fb3821f7 CH |
3246 | = push_reload (XEXP (recog_operand[i], 0), NULL_RTX, |
3247 | &XEXP (recog_operand[i], 0), NULL_PTR, | |
eab89b90 | 3248 | BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)), |
a8c9daeb | 3249 | VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); |
eab89b90 RK |
3250 | reload_inc[operand_reloadnum[i]] |
3251 | = GET_MODE_SIZE (GET_MODE (recog_operand[i])); | |
a8c9daeb RK |
3252 | |
3253 | /* If this operand is an output, we will have made any | |
3254 | reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but | |
3255 | now we are treating part of the operand as an input, so | |
3256 | we must change these to RELOAD_FOR_INPUT_ADDRESS. */ | |
3257 | ||
3258 | if (operand_type[i] == RELOAD_FOR_OUTPUT) | |
3259 | for (j = 0; j < n_reloads; j++) | |
3260 | if (reload_opnum[j] == i | |
3261 | && reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) | |
3262 | reload_when_needed[j] = RELOAD_FOR_INPUT_ADDRESS; | |
eab89b90 RK |
3263 | } |
3264 | else if (goal_alternative_matched[i] == -1) | |
3265 | operand_reloadnum[i] = | |
3266 | push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3267 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
a8c9daeb RK |
3268 | (modified[i] != RELOAD_WRITE ? |
3269 | recog_operand_loc[i] : 0), | |
eab89b90 RK |
3270 | modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, |
3271 | (enum reg_class) goal_alternative[i], | |
a8c9daeb RK |
3272 | (modified[i] == RELOAD_WRITE |
3273 | ? VOIDmode : operand_mode[i]), | |
3274 | (modified[i] == RELOAD_READ | |
3275 | ? VOIDmode : operand_mode[i]), | |
eab89b90 RK |
3276 | (insn_code_number < 0 ? 0 |
3277 | : insn_operand_strict_low[insn_code_number][i]), | |
a8c9daeb | 3278 | 0, i, operand_type[i]); |
eab89b90 RK |
3279 | /* In a matching pair of operands, one must be input only |
3280 | and the other must be output only. | |
3281 | Pass the input operand as IN and the other as OUT. */ | |
3282 | else if (modified[i] == RELOAD_READ | |
3283 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
3284 | { | |
3285 | operand_reloadnum[i] | |
3286 | = push_reload (recog_operand[i], | |
3287 | recog_operand[goal_alternative_matched[i]], | |
3288 | recog_operand_loc[i], | |
3289 | recog_operand_loc[goal_alternative_matched[i]], | |
3290 | (enum reg_class) goal_alternative[i], | |
3291 | operand_mode[i], | |
3292 | operand_mode[goal_alternative_matched[i]], | |
a8c9daeb | 3293 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3294 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
3295 | } | |
3296 | else if (modified[i] == RELOAD_WRITE | |
3297 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
3298 | { | |
3299 | operand_reloadnum[goal_alternative_matched[i]] | |
3300 | = push_reload (recog_operand[goal_alternative_matched[i]], | |
3301 | recog_operand[i], | |
3302 | recog_operand_loc[goal_alternative_matched[i]], | |
3303 | recog_operand_loc[i], | |
3304 | (enum reg_class) goal_alternative[i], | |
3305 | operand_mode[goal_alternative_matched[i]], | |
3306 | operand_mode[i], | |
a8c9daeb | 3307 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3308 | operand_reloadnum[i] = output_reloadnum; |
3309 | } | |
3310 | else if (insn_code_number >= 0) | |
3311 | abort (); | |
3312 | else | |
3313 | { | |
3314 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3315 | /* Avoid further trouble with this insn. */ | |
3316 | PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); | |
3317 | n_reloads = 0; | |
3318 | return; | |
3319 | } | |
3320 | } | |
3321 | else if (goal_alternative_matched[i] < 0 | |
3322 | && goal_alternative_matches[i] < 0 | |
3323 | && optimize) | |
3324 | { | |
a8c9daeb | 3325 | /* For each non-matching operand that's a MEM or a pseudo-register |
eab89b90 RK |
3326 | that didn't get a hard register, make an optional reload. |
3327 | This may get done even if the insn needs no reloads otherwise. */ | |
a8c9daeb RK |
3328 | |
3329 | rtx operand = recog_operand[i]; | |
3330 | ||
eab89b90 RK |
3331 | while (GET_CODE (operand) == SUBREG) |
3332 | operand = XEXP (operand, 0); | |
a8c9daeb RK |
3333 | if ((GET_CODE (operand) == MEM |
3334 | || (GET_CODE (operand) == REG | |
3335 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
eab89b90 | 3336 | && (enum reg_class) goal_alternative[i] != NO_REGS |
a8c9daeb RK |
3337 | && ! no_input_reloads |
3338 | /* Optional output reloads don't do anything and we mustn't | |
3339 | make in-out reloads on insns that are not permitted output | |
3340 | reloads. */ | |
eab89b90 | 3341 | && (modified[i] == RELOAD_READ |
a8c9daeb | 3342 | || (modified[i] == RELOAD_READ_WRITE && ! no_output_reloads))) |
eab89b90 RK |
3343 | operand_reloadnum[i] |
3344 | = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3345 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
a8c9daeb RK |
3346 | (modified[i] != RELOAD_WRITE |
3347 | ? recog_operand_loc[i] : 0), | |
3348 | (modified[i] != RELOAD_READ | |
3349 | ? recog_operand_loc[i] : 0), | |
eab89b90 | 3350 | (enum reg_class) goal_alternative[i], |
a8c9daeb RK |
3351 | (modified[i] == RELOAD_WRITE |
3352 | ? VOIDmode : operand_mode[i]), | |
3353 | (modified[i] == RELOAD_READ | |
3354 | ? VOIDmode : operand_mode[i]), | |
eab89b90 RK |
3355 | (insn_code_number < 0 ? 0 |
3356 | : insn_operand_strict_low[insn_code_number][i]), | |
a8c9daeb | 3357 | 1, i, operand_type[i]); |
eab89b90 | 3358 | } |
a8c9daeb RK |
3359 | else if (goal_alternative_matches[i] >= 0 |
3360 | && goal_alternative_win[goal_alternative_matches[i]] | |
3361 | && modified[i] == RELOAD_READ | |
3362 | && modified[goal_alternative_matches[i]] == RELOAD_WRITE | |
3363 | && ! no_input_reloads && ! no_output_reloads | |
3364 | && optimize) | |
3365 | { | |
3366 | /* Similarly, make an optional reload for a pair of matching | |
3367 | objects that are in MEM or a pseudo that didn't get a hard reg. */ | |
eab89b90 | 3368 | |
a8c9daeb RK |
3369 | rtx operand = recog_operand[i]; |
3370 | ||
3371 | while (GET_CODE (operand) == SUBREG) | |
3372 | operand = XEXP (operand, 0); | |
3373 | if ((GET_CODE (operand) == MEM | |
3374 | || (GET_CODE (operand) == REG | |
3375 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
3376 | && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] | |
3377 | != NO_REGS)) | |
3378 | operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] | |
3379 | = push_reload (recog_operand[goal_alternative_matches[i]], | |
3380 | recog_operand[i], | |
3381 | recog_operand_loc[goal_alternative_matches[i]], | |
3382 | recog_operand_loc[i], | |
3383 | (enum reg_class) goal_alternative[goal_alternative_matches[i]], | |
3384 | operand_mode[goal_alternative_matches[i]], | |
3385 | operand_mode[i], | |
3386 | 0, 1, goal_alternative_matches[i], RELOAD_OTHER); | |
3387 | } | |
3388 | ||
eab89b90 RK |
3389 | /* Record the values of the earlyclobber operands for the caller. */ |
3390 | if (goal_earlyclobber) | |
3391 | for (i = 0; i < noperands; i++) | |
3392 | if (goal_alternative_earlyclobber[i]) | |
3393 | reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i]; | |
3394 | ||
3395 | /* If this insn pattern contains any MATCH_DUP's, make sure that | |
3396 | they will be substituted if the operands they match are substituted. | |
3397 | Also do now any substitutions we already did on the operands. | |
3398 | ||
3399 | Don't do this if we aren't making replacements because we might be | |
3400 | propagating things allocated by frame pointer elimination into places | |
3401 | it doesn't expect. */ | |
3402 | ||
3403 | if (insn_code_number >= 0 && replace) | |
3404 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
3405 | { | |
3406 | int opno = recog_dup_num[i]; | |
3407 | *recog_dup_loc[i] = *recog_operand_loc[opno]; | |
3408 | if (operand_reloadnum[opno] >= 0) | |
3409 | push_replacement (recog_dup_loc[i], operand_reloadnum[opno], | |
3410 | insn_operand_mode[insn_code_number][opno]); | |
3411 | } | |
3412 | ||
3413 | #if 0 | |
3414 | /* This loses because reloading of prior insns can invalidate the equivalence | |
3415 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
3416 | causing this insn to need more reload regs than it needed before. | |
3417 | It may be too late to make the reload regs available. | |
3418 | Now this optimization is done safely in choose_reload_regs. */ | |
3419 | ||
3420 | /* For each reload of a reg into some other class of reg, | |
3421 | search for an existing equivalent reg (same value now) in the right class. | |
3422 | We can use it as long as we don't need to change its contents. */ | |
3423 | for (i = 0; i < n_reloads; i++) | |
3424 | if (reload_reg_rtx[i] == 0 | |
3425 | && reload_in[i] != 0 | |
3426 | && GET_CODE (reload_in[i]) == REG | |
3427 | && reload_out[i] == 0) | |
3428 | { | |
3429 | reload_reg_rtx[i] | |
3430 | = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1, | |
3431 | static_reload_reg_p, 0, reload_inmode[i]); | |
3432 | /* Prevent generation of insn to load the value | |
3433 | because the one we found already has the value. */ | |
3434 | if (reload_reg_rtx[i]) | |
3435 | reload_in[i] = reload_reg_rtx[i]; | |
3436 | } | |
3437 | #endif | |
3438 | ||
a8c9daeb RK |
3439 | /* Perhaps an output reload can be combined with another |
3440 | to reduce needs by one. */ | |
3441 | if (!goal_earlyclobber) | |
3442 | combine_reloads (); | |
3443 | ||
3444 | /* If we have a pair of reloads for parts of an address, they are reloading | |
3445 | the same object, the operands themselves were not reloaded, and they | |
3446 | are for two operands that are supposed to match, merge the reloads and | |
3447 | change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ | |
3448 | ||
3449 | for (i = 0; i < n_reloads; i++) | |
3450 | { | |
3451 | int k; | |
3452 | ||
3453 | for (j = i + 1; j < n_reloads; j++) | |
3454 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
3455 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS) | |
3456 | && (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS | |
3457 | || reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) | |
3458 | && rtx_equal_p (reload_in[i], reload_in[j]) | |
3459 | && (operand_reloadnum[reload_opnum[i]] < 0 | |
3460 | || reload_optional[operand_reloadnum[reload_opnum[i]]]) | |
3461 | && (operand_reloadnum[reload_opnum[j]] < 0 | |
3462 | || reload_optional[operand_reloadnum[reload_opnum[j]]]) | |
3463 | && (goal_alternative_matches[reload_opnum[i]] == reload_opnum[j] | |
3464 | || (goal_alternative_matches[reload_opnum[j]] | |
3465 | == reload_opnum[i]))) | |
3466 | { | |
3467 | for (k = 0; k < n_replacements; k++) | |
3468 | if (replacements[k].what == j) | |
3469 | replacements[k].what = i; | |
3470 | ||
3471 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
3472 | reload_in[j] = 0; | |
3473 | } | |
3474 | } | |
3475 | ||
3476 | /* Scan all the reloads and update their type. | |
3477 | If a reload is for the address of an operand and we didn't reload | |
3478 | that operand, change the type. Similarly, change the operand number | |
3479 | of a reload when two operands match. If a reload is optional, treat it | |
3480 | as though the operand isn't reloaded. | |
3481 | ||
3482 | ??? This latter case is somewhat odd because if we do the optional | |
3483 | reload, it means the object is hanging around. Thus we need only | |
3484 | do the address reload if the optional reload was NOT done. | |
3485 | ||
3486 | Change secondary reloads to be the address type of their operand, not | |
3487 | the normal type. | |
3488 | ||
3489 | If an operand's reload is now RELOAD_OTHER, change any | |
3490 | RELOAD_FOR_INPUT_ADDRESS reloads of that operand to | |
3491 | RELOAD_FOR_OTHER_ADDRESS. */ | |
3492 | ||
3493 | for (i = 0; i < n_reloads; i++) | |
3494 | { | |
3495 | if (reload_secondary_p[i] | |
3496 | && reload_when_needed[i] == operand_type[reload_opnum[i]]) | |
3497 | reload_when_needed[i] = address_type[reload_opnum[i]]; | |
3498 | ||
3499 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
3500 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS) | |
3501 | && (operand_reloadnum[reload_opnum[i]] < 0 | |
3502 | || reload_optional[operand_reloadnum[reload_opnum[i]]])) | |
3503 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
3504 | ||
3505 | if (reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
3506 | && operand_reloadnum[reload_opnum[i]] >= 0 | |
3507 | && (reload_when_needed[operand_reloadnum[reload_opnum[i]]] | |
3508 | == RELOAD_OTHER)) | |
3509 | reload_when_needed[i] = RELOAD_FOR_OTHER_ADDRESS; | |
3510 | ||
3511 | if (goal_alternative_matches[reload_opnum[i]] >= 0) | |
3512 | reload_opnum[i] = goal_alternative_matches[reload_opnum[i]]; | |
3513 | } | |
3514 | ||
3515 | /* See if we have any reloads that are now allowed to be merged | |
3516 | because we've changed when the reload is needed to | |
3517 | RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only | |
3518 | check for the most common cases. */ | |
3519 | ||
3520 | for (i = 0; i < n_reloads; i++) | |
3521 | if (reload_in[i] != 0 && reload_out[i] == 0 | |
3522 | && (reload_when_needed[i] == RELOAD_FOR_OPERAND_ADDRESS | |
3523 | || reload_when_needed[i] == RELOAD_FOR_OTHER_ADDRESS)) | |
3524 | for (j = 0; j < n_reloads; j++) | |
3525 | if (i != j && reload_in[j] != 0 && reload_out[j] == 0 | |
3526 | && reload_when_needed[j] == reload_when_needed[i] | |
73f67895 RS |
3527 | && MATCHES (reload_in[i], reload_in[j]) |
3528 | && reload_reg_class[i] == reload_reg_class[j] | |
3529 | && !reload_nocombine[i] && !reload_nocombine[j]) | |
a8c9daeb RK |
3530 | { |
3531 | reload_opnum[i] = MIN (reload_opnum[i], reload_opnum[j]); | |
3532 | transfer_replacements (i, j); | |
3533 | reload_in[j] = 0; | |
3534 | } | |
3535 | ||
eab89b90 RK |
3536 | #else /* no REGISTER_CONSTRAINTS */ |
3537 | int noperands; | |
3538 | int insn_code_number; | |
3539 | int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */ | |
3540 | register int i; | |
3541 | rtx body = PATTERN (insn); | |
3542 | ||
3543 | n_reloads = 0; | |
3544 | n_replacements = 0; | |
3545 | n_earlyclobbers = 0; | |
3546 | replace_reloads = replace; | |
3547 | this_insn = insn; | |
3548 | ||
3549 | /* Find what kind of insn this is. NOPERANDS gets number of operands. | |
3550 | Store the operand values in RECOG_OPERAND and the locations | |
3551 | of the words in the insn that point to them in RECOG_OPERAND_LOC. | |
3552 | Return if the insn needs no reload processing. */ | |
3553 | ||
3554 | switch (GET_CODE (body)) | |
3555 | { | |
3556 | case USE: | |
3557 | case CLOBBER: | |
3558 | case ASM_INPUT: | |
3559 | case ADDR_VEC: | |
3560 | case ADDR_DIFF_VEC: | |
3561 | return; | |
3562 | ||
3563 | case PARALLEL: | |
3564 | case SET: | |
3565 | noperands = asm_noperands (body); | |
3566 | if (noperands >= 0) | |
3567 | { | |
3568 | /* This insn is an `asm' with operands. | |
3569 | First, find out how many operands, and allocate space. */ | |
3570 | ||
3571 | insn_code_number = -1; | |
3572 | /* ??? This is a bug! ??? | |
3573 | Give up and delete this insn if it has too many operands. */ | |
3574 | if (noperands > MAX_RECOG_OPERANDS) | |
3575 | abort (); | |
3576 | ||
3577 | /* Now get the operand values out of the insn. */ | |
3578 | ||
fb3821f7 CH |
3579 | decode_asm_operands (body, recog_operand, recog_operand_loc, |
3580 | NULL_PTR, NULL_PTR); | |
eab89b90 RK |
3581 | break; |
3582 | } | |
3583 | ||
3584 | default: | |
3585 | /* Ordinary insn: recognize it, allocate space for operands and | |
3586 | constraints, and get them out via insn_extract. */ | |
3587 | ||
3588 | insn_code_number = recog_memoized (insn); | |
3589 | noperands = insn_n_operands[insn_code_number]; | |
3590 | insn_extract (insn); | |
3591 | } | |
3592 | ||
3593 | if (noperands == 0) | |
3594 | return; | |
3595 | ||
3596 | for (i = 0; i < noperands; i++) | |
3597 | { | |
3598 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
3599 | int is_set_dest = GET_CODE (body) == SET && (i == 0); | |
3600 | ||
3601 | if (insn_code_number >= 0) | |
3602 | if (insn_operand_address_p[insn_code_number][i]) | |
fb3821f7 | 3603 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 | 3604 | recog_operand[i], recog_operand_loc[i], |
a8c9daeb RK |
3605 | i, RELOAD_FOR_INPUT, ind_levels); |
3606 | ||
3607 | /* In these cases, we can't tell if the operand is an input | |
3608 | or an output, so be conservative. In practice it won't be | |
3609 | problem. */ | |
3610 | ||
eab89b90 RK |
3611 | if (code == MEM) |
3612 | find_reloads_address (GET_MODE (recog_operand[i]), | |
3613 | recog_operand_loc[i], | |
3614 | XEXP (recog_operand[i], 0), | |
3615 | &XEXP (recog_operand[i], 0), | |
a8c9daeb | 3616 | i, RELOAD_OTHER, ind_levels); |
eab89b90 RK |
3617 | if (code == SUBREG) |
3618 | recog_operand[i] = *recog_operand_loc[i] | |
a8c9daeb RK |
3619 | = find_reloads_toplev (recog_operand[i], i, RELOAD_OTHER, |
3620 | ind_levels, is_set_dest); | |
eab89b90 RK |
3621 | if (code == REG) |
3622 | { | |
3623 | register int regno = REGNO (recog_operand[i]); | |
3624 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
3625 | recog_operand[i] = *recog_operand_loc[i] | |
3626 | = reg_equiv_constant[regno]; | |
3627 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
3628 | that feeds this insn. */ | |
3629 | if (reg_equiv_mem[regno] != 0) | |
3630 | recog_operand[i] = *recog_operand_loc[i] | |
3631 | = reg_equiv_mem[regno]; | |
3632 | #endif | |
3633 | } | |
eab89b90 RK |
3634 | } |
3635 | ||
3636 | /* Perhaps an output reload can be combined with another | |
3637 | to reduce needs by one. */ | |
3638 | if (!goal_earlyclobber) | |
3639 | combine_reloads (); | |
a8c9daeb | 3640 | #endif /* no REGISTER_CONSTRAINTS */ |
eab89b90 RK |
3641 | } |
3642 | ||
3643 | /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT | |
3644 | accepts a memory operand with constant address. */ | |
3645 | ||
3646 | static int | |
3647 | alternative_allows_memconst (constraint, altnum) | |
3648 | char *constraint; | |
3649 | int altnum; | |
3650 | { | |
3651 | register int c; | |
3652 | /* Skip alternatives before the one requested. */ | |
3653 | while (altnum > 0) | |
3654 | { | |
3655 | while (*constraint++ != ','); | |
3656 | altnum--; | |
3657 | } | |
3658 | /* Scan the requested alternative for 'm' or 'o'. | |
3659 | If one of them is present, this alternative accepts memory constants. */ | |
3660 | while ((c = *constraint++) && c != ',' && c != '#') | |
3661 | if (c == 'm' || c == 'o') | |
3662 | return 1; | |
3663 | return 0; | |
3664 | } | |
3665 | \f | |
3666 | /* Scan X for memory references and scan the addresses for reloading. | |
3667 | Also checks for references to "constant" regs that we want to eliminate | |
3668 | and replaces them with the values they stand for. | |
6dc42e49 | 3669 | We may alter X destructively if it contains a reference to such. |
eab89b90 RK |
3670 | If X is just a constant reg, we return the equivalent value |
3671 | instead of X. | |
3672 | ||
3673 | IND_LEVELS says how many levels of indirect addressing this machine | |
3674 | supports. | |
3675 | ||
a8c9daeb RK |
3676 | OPNUM and TYPE identify the purpose of the reload. |
3677 | ||
eab89b90 RK |
3678 | IS_SET_DEST is true if X is the destination of a SET, which is not |
3679 | appropriate to be replaced by a constant. */ | |
3680 | ||
3681 | static rtx | |
a8c9daeb | 3682 | find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest) |
eab89b90 | 3683 | rtx x; |
a8c9daeb RK |
3684 | int opnum; |
3685 | enum reload_type type; | |
eab89b90 RK |
3686 | int ind_levels; |
3687 | int is_set_dest; | |
3688 | { | |
3689 | register RTX_CODE code = GET_CODE (x); | |
3690 | ||
3691 | register char *fmt = GET_RTX_FORMAT (code); | |
3692 | register int i; | |
3693 | ||
3694 | if (code == REG) | |
3695 | { | |
3696 | /* This code is duplicated for speed in find_reloads. */ | |
3697 | register int regno = REGNO (x); | |
3698 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
3699 | x = reg_equiv_constant[regno]; | |
3700 | #if 0 | |
3701 | /* This creates (subreg (mem...)) which would cause an unnecessary | |
3702 | reload of the mem. */ | |
3703 | else if (reg_equiv_mem[regno] != 0) | |
3704 | x = reg_equiv_mem[regno]; | |
3705 | #endif | |
3706 | else if (reg_equiv_address[regno] != 0) | |
3707 | { | |
3708 | /* If reg_equiv_address varies, it may be shared, so copy it. */ | |
3709 | rtx addr = reg_equiv_address[regno]; | |
3710 | ||
3711 | if (rtx_varies_p (addr)) | |
3712 | addr = copy_rtx (addr); | |
3713 | ||
3714 | x = gen_rtx (MEM, GET_MODE (x), addr); | |
3715 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
fb3821f7 | 3716 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 | 3717 | XEXP (x, 0), |
a8c9daeb | 3718 | &XEXP (x, 0), opnum, type, ind_levels); |
eab89b90 RK |
3719 | } |
3720 | return x; | |
3721 | } | |
3722 | if (code == MEM) | |
3723 | { | |
3724 | rtx tem = x; | |
3725 | find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
a8c9daeb | 3726 | opnum, type, ind_levels); |
eab89b90 RK |
3727 | return tem; |
3728 | } | |
3729 | ||
3730 | if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG) | |
3731 | { | |
3732 | /* Check for SUBREG containing a REG that's equivalent to a constant. | |
3733 | If the constant has a known value, truncate it right now. | |
3734 | Similarly if we are extracting a single-word of a multi-word | |
3735 | constant. If the constant is symbolic, allow it to be substituted | |
3736 | normally. push_reload will strip the subreg later. If the | |
3737 | constant is VOIDmode, abort because we will lose the mode of | |
3738 | the register (this should never happen because one of the cases | |
3739 | above should handle it). */ | |
3740 | ||
3741 | register int regno = REGNO (SUBREG_REG (x)); | |
3742 | rtx tem; | |
3743 | ||
3744 | if (subreg_lowpart_p (x) | |
3745 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
3746 | && reg_equiv_constant[regno] != 0 | |
3747 | && (tem = gen_lowpart_common (GET_MODE (x), | |
3748 | reg_equiv_constant[regno])) != 0) | |
3749 | return tem; | |
3750 | ||
3751 | if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD | |
3752 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
3753 | && reg_equiv_constant[regno] != 0 | |
3754 | && (tem = operand_subword (reg_equiv_constant[regno], | |
3755 | SUBREG_WORD (x), 0, | |
3756 | GET_MODE (SUBREG_REG (x)))) != 0) | |
3757 | return tem; | |
3758 | ||
3759 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
3760 | && reg_equiv_constant[regno] != 0 | |
3761 | && GET_MODE (reg_equiv_constant[regno]) == VOIDmode) | |
3762 | abort (); | |
3763 | ||
3764 | /* If the subreg contains a reg that will be converted to a mem, | |
3765 | convert the subreg to a narrower memref now. | |
3766 | Otherwise, we would get (subreg (mem ...) ...), | |
3767 | which would force reload of the mem. | |
3768 | ||
3769 | We also need to do this if there is an equivalent MEM that is | |
3770 | not offsettable. In that case, alter_subreg would produce an | |
3771 | invalid address on big-endian machines. | |
3772 | ||
46da6b3a | 3773 | For machines that extend byte loads, we must not reload using |
eab89b90 RK |
3774 | a wider mode if we have a paradoxical SUBREG. find_reloads will |
3775 | force a reload in that case. So we should not do anything here. */ | |
3776 | ||
3777 | else if (regno >= FIRST_PSEUDO_REGISTER | |
46da6b3a | 3778 | #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND) |
eab89b90 RK |
3779 | && (GET_MODE_SIZE (GET_MODE (x)) |
3780 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3781 | #endif | |
3782 | && (reg_equiv_address[regno] != 0 | |
3783 | || (reg_equiv_mem[regno] != 0 | |
f2fbfe92 JL |
3784 | && (! strict_memory_address_p (GET_MODE (x), |
3785 | XEXP (reg_equiv_mem[regno], 0)) | |
3786 | || ! offsettable_memref_p (reg_equiv_mem[regno]))))) | |
eab89b90 RK |
3787 | { |
3788 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
3789 | rtx addr = (reg_equiv_address[regno] ? reg_equiv_address[regno] | |
3790 | : XEXP (reg_equiv_mem[regno], 0)); | |
3791 | #if BYTES_BIG_ENDIAN | |
3792 | int size; | |
3793 | size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
3794 | offset += MIN (size, UNITS_PER_WORD); | |
3795 | size = GET_MODE_SIZE (GET_MODE (x)); | |
3796 | offset -= MIN (size, UNITS_PER_WORD); | |
3797 | #endif | |
3798 | addr = plus_constant (addr, offset); | |
3799 | x = gen_rtx (MEM, GET_MODE (x), addr); | |
3800 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
fb3821f7 | 3801 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 | 3802 | XEXP (x, 0), |
a8c9daeb | 3803 | &XEXP (x, 0), opnum, type, ind_levels); |
eab89b90 RK |
3804 | } |
3805 | ||
3806 | } | |
3807 | ||
3808 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3809 | { | |
3810 | if (fmt[i] == 'e') | |
a8c9daeb | 3811 | XEXP (x, i) = find_reloads_toplev (XEXP (x, i), opnum, type, |
eab89b90 RK |
3812 | ind_levels, is_set_dest); |
3813 | } | |
3814 | return x; | |
3815 | } | |
3816 | ||
dbf85761 RS |
3817 | /* Return a mem ref for the memory equivalent of reg REGNO. |
3818 | This mem ref is not shared with anything. */ | |
3819 | ||
eab89b90 RK |
3820 | static rtx |
3821 | make_memloc (ad, regno) | |
3822 | rtx ad; | |
3823 | int regno; | |
3824 | { | |
3825 | register int i; | |
3826 | rtx tem = reg_equiv_address[regno]; | |
dbf85761 RS |
3827 | |
3828 | #if 0 /* We cannot safely reuse a memloc made here; | |
3829 | if the pseudo appears twice, and its mem needs a reload, | |
3830 | it gets two separate reloads assigned, but it only | |
3831 | gets substituted with the second of them; | |
3832 | then it can get used before that reload reg gets loaded up. */ | |
eab89b90 RK |
3833 | for (i = 0; i < n_memlocs; i++) |
3834 | if (rtx_equal_p (tem, XEXP (memlocs[i], 0))) | |
3835 | return memlocs[i]; | |
dbf85761 | 3836 | #endif |
eab89b90 RK |
3837 | |
3838 | /* If TEM might contain a pseudo, we must copy it to avoid | |
3839 | modifying it when we do the substitution for the reload. */ | |
3840 | if (rtx_varies_p (tem)) | |
3841 | tem = copy_rtx (tem); | |
3842 | ||
3843 | tem = gen_rtx (MEM, GET_MODE (ad), tem); | |
3844 | RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
3845 | memlocs[n_memlocs++] = tem; | |
3846 | return tem; | |
3847 | } | |
3848 | ||
3849 | /* Record all reloads needed for handling memory address AD | |
3850 | which appears in *LOC in a memory reference to mode MODE | |
3851 | which itself is found in location *MEMREFLOC. | |
3852 | Note that we take shortcuts assuming that no multi-reg machine mode | |
3853 | occurs as part of an address. | |
3854 | ||
a8c9daeb | 3855 | OPNUM and TYPE specify the purpose of this reload. |
eab89b90 RK |
3856 | |
3857 | IND_LEVELS says how many levels of indirect addressing this machine | |
3858 | supports. | |
3859 | ||
3860 | Value is nonzero if this address is reloaded or replaced as a whole. | |
3861 | This is interesting to the caller if the address is an autoincrement. | |
3862 | ||
3863 | Note that there is no verification that the address will be valid after | |
3864 | this routine does its work. Instead, we rely on the fact that the address | |
3865 | was valid when reload started. So we need only undo things that reload | |
3866 | could have broken. These are wrong register types, pseudos not allocated | |
3867 | to a hard register, and frame pointer elimination. */ | |
3868 | ||
3869 | static int | |
a8c9daeb | 3870 | find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels) |
eab89b90 RK |
3871 | enum machine_mode mode; |
3872 | rtx *memrefloc; | |
3873 | rtx ad; | |
3874 | rtx *loc; | |
a8c9daeb RK |
3875 | int opnum; |
3876 | enum reload_type type; | |
eab89b90 RK |
3877 | int ind_levels; |
3878 | { | |
3879 | register int regno; | |
3880 | rtx tem; | |
3881 | ||
3882 | /* If the address is a register, see if it is a legitimate address and | |
3883 | reload if not. We first handle the cases where we need not reload | |
3884 | or where we must reload in a non-standard way. */ | |
3885 | ||
3886 | if (GET_CODE (ad) == REG) | |
3887 | { | |
3888 | regno = REGNO (ad); | |
3889 | ||
3890 | if (reg_equiv_constant[regno] != 0 | |
3891 | && strict_memory_address_p (mode, reg_equiv_constant[regno])) | |
3892 | { | |
3893 | *loc = ad = reg_equiv_constant[regno]; | |
3894 | return 1; | |
3895 | } | |
3896 | ||
3897 | else if (reg_equiv_address[regno] != 0) | |
3898 | { | |
3899 | tem = make_memloc (ad, regno); | |
fb3821f7 | 3900 | find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0), |
a8c9daeb | 3901 | &XEXP (tem, 0), opnum, type, ind_levels); |
fb3821f7 | 3902 | push_reload (tem, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, |
eab89b90 | 3903 | GET_MODE (ad), VOIDmode, 0, 0, |
a8c9daeb | 3904 | opnum, type); |
eab89b90 RK |
3905 | return 1; |
3906 | } | |
3907 | ||
b39555b4 | 3908 | /* We can avoid a reload if the register's equivalent memory expression |
c1875d66 RS |
3909 | is valid as an indirect memory address. |
3910 | But not all addresses are valid in a mem used as an indirect address: | |
3911 | only reg or reg+constant. */ | |
b39555b4 RS |
3912 | |
3913 | else if (reg_equiv_mem[regno] != 0 && ind_levels > 0 | |
c1875d66 RS |
3914 | && strict_memory_address_p (mode, reg_equiv_mem[regno]) |
3915 | && (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == REG | |
3916 | || (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == PLUS | |
3917 | && GET_CODE (XEXP (XEXP (reg_equiv_mem[regno], 0), 0)) == REG | |
3918 | && CONSTANT_P (XEXP (XEXP (reg_equiv_mem[regno], 0), 0))))) | |
b39555b4 | 3919 | return 0; |
eab89b90 RK |
3920 | |
3921 | /* The only remaining case where we can avoid a reload is if this is a | |
3922 | hard register that is valid as a base register and which is not the | |
3923 | subject of a CLOBBER in this insn. */ | |
3924 | ||
3925 | else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno) | |
3926 | && ! regno_clobbered_p (regno, this_insn)) | |
3927 | return 0; | |
3928 | ||
3929 | /* If we do not have one of the cases above, we must do the reload. */ | |
fb3821f7 | 3930 | push_reload (ad, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, |
a8c9daeb | 3931 | GET_MODE (ad), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
3932 | return 1; |
3933 | } | |
3934 | ||
3935 | if (strict_memory_address_p (mode, ad)) | |
3936 | { | |
3937 | /* The address appears valid, so reloads are not needed. | |
3938 | But the address may contain an eliminable register. | |
3939 | This can happen because a machine with indirect addressing | |
3940 | may consider a pseudo register by itself a valid address even when | |
3941 | it has failed to get a hard reg. | |
3942 | So do a tree-walk to find and eliminate all such regs. */ | |
3943 | ||
3944 | /* But first quickly dispose of a common case. */ | |
3945 | if (GET_CODE (ad) == PLUS | |
3946 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
3947 | && GET_CODE (XEXP (ad, 0)) == REG | |
3948 | && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) | |
3949 | return 0; | |
3950 | ||
3951 | subst_reg_equivs_changed = 0; | |
3952 | *loc = subst_reg_equivs (ad); | |
3953 | ||
3954 | if (! subst_reg_equivs_changed) | |
3955 | return 0; | |
3956 | ||
3957 | /* Check result for validity after substitution. */ | |
3958 | if (strict_memory_address_p (mode, ad)) | |
3959 | return 0; | |
3960 | } | |
3961 | ||
3962 | /* The address is not valid. We have to figure out why. One possibility | |
3963 | is that it is itself a MEM. This can happen when the frame pointer is | |
3964 | being eliminated, a pseudo is not allocated to a hard register, and the | |
3965 | offset between the frame and stack pointers is not its initial value. | |
d45cf215 | 3966 | In that case the pseudo will have been replaced by a MEM referring to |
eab89b90 RK |
3967 | the stack pointer. */ |
3968 | if (GET_CODE (ad) == MEM) | |
3969 | { | |
3970 | /* First ensure that the address in this MEM is valid. Then, unless | |
3971 | indirect addresses are valid, reload the MEM into a register. */ | |
3972 | tem = ad; | |
3973 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
a8c9daeb | 3974 | opnum, type, ind_levels == 0 ? 0 : ind_levels - 1); |
d2555454 RS |
3975 | |
3976 | /* If tem was changed, then we must create a new memory reference to | |
3977 | hold it and store it back into memrefloc. */ | |
3978 | if (tem != ad && memrefloc) | |
ca3e4a2f | 3979 | { |
ca3e4a2f | 3980 | *memrefloc = copy_rtx (*memrefloc); |
3c80f7ed | 3981 | copy_replacements (tem, XEXP (*memrefloc, 0)); |
ca3e4a2f | 3982 | loc = &XEXP (*memrefloc, 0); |
ca3e4a2f | 3983 | } |
d2555454 | 3984 | |
eab89b90 RK |
3985 | /* Check similar cases as for indirect addresses as above except |
3986 | that we can allow pseudos and a MEM since they should have been | |
3987 | taken care of above. */ | |
3988 | ||
3989 | if (ind_levels == 0 | |
3990 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
3991 | || GET_CODE (XEXP (tem, 0)) == MEM | |
3992 | || ! (GET_CODE (XEXP (tem, 0)) == REG | |
3993 | || (GET_CODE (XEXP (tem, 0)) == PLUS | |
3994 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG | |
3995 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) | |
3996 | { | |
3997 | /* Must use TEM here, not AD, since it is the one that will | |
3998 | have any subexpressions reloaded, if needed. */ | |
fb3821f7 | 3999 | push_reload (tem, NULL_RTX, loc, NULL_PTR, |
eab89b90 | 4000 | BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0, |
a8c9daeb | 4001 | 0, opnum, type); |
eab89b90 RK |
4002 | return 1; |
4003 | } | |
4004 | else | |
4005 | return 0; | |
4006 | } | |
4007 | ||
4008 | /* If we have address of a stack slot but it's not valid | |
4009 | (displacement is too large), compute the sum in a register. */ | |
4010 | else if (GET_CODE (ad) == PLUS | |
4011 | && (XEXP (ad, 0) == frame_pointer_rtx | |
4012 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
4013 | || XEXP (ad, 0) == arg_pointer_rtx | |
4014 | #endif | |
4015 | || XEXP (ad, 0) == stack_pointer_rtx) | |
4016 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
4017 | { | |
4018 | /* Unshare the MEM rtx so we can safely alter it. */ | |
4019 | if (memrefloc) | |
4020 | { | |
4021 | rtx oldref = *memrefloc; | |
4022 | *memrefloc = copy_rtx (*memrefloc); | |
4023 | loc = &XEXP (*memrefloc, 0); | |
eab89b90 RK |
4024 | } |
4025 | if (double_reg_address_ok) | |
4026 | { | |
4027 | /* Unshare the sum as well. */ | |
4028 | *loc = ad = copy_rtx (ad); | |
4029 | /* Reload the displacement into an index reg. | |
4030 | We assume the frame pointer or arg pointer is a base reg. */ | |
4031 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
a8c9daeb RK |
4032 | INDEX_REG_CLASS, GET_MODE (ad), opnum, |
4033 | type, ind_levels); | |
eab89b90 RK |
4034 | } |
4035 | else | |
4036 | { | |
4037 | /* If the sum of two regs is not necessarily valid, | |
4038 | reload the sum into a base reg. | |
4039 | That will at least work. */ | |
4040 | find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, | |
a8c9daeb | 4041 | opnum, type, ind_levels); |
eab89b90 RK |
4042 | } |
4043 | return 1; | |
4044 | } | |
4045 | ||
4046 | /* If we have an indexed stack slot, there are three possible reasons why | |
4047 | it might be invalid: The index might need to be reloaded, the address | |
4048 | might have been made by frame pointer elimination and hence have a | |
4049 | constant out of range, or both reasons might apply. | |
4050 | ||
4051 | We can easily check for an index needing reload, but even if that is the | |
4052 | case, we might also have an invalid constant. To avoid making the | |
4053 | conservative assumption and requiring two reloads, we see if this address | |
4054 | is valid when not interpreted strictly. If it is, the only problem is | |
4055 | that the index needs a reload and find_reloads_address_1 will take care | |
4056 | of it. | |
4057 | ||
4058 | There is still a case when we might generate an extra reload, | |
4059 | however. In certain cases eliminate_regs will return a MEM for a REG | |
4060 | (see the code there for details). In those cases, memory_address_p | |
4061 | applied to our address will return 0 so we will think that our offset | |
4062 | must be too large. But it might indeed be valid and the only problem | |
4063 | is that a MEM is present where a REG should be. This case should be | |
4064 | very rare and there doesn't seem to be any way to avoid it. | |
4065 | ||
4066 | If we decide to do something here, it must be that | |
4067 | `double_reg_address_ok' is true and that this address rtl was made by | |
4068 | eliminate_regs. We generate a reload of the fp/sp/ap + constant and | |
4069 | rework the sum so that the reload register will be added to the index. | |
4070 | This is safe because we know the address isn't shared. | |
4071 | ||
4072 | We check for fp/ap/sp as both the first and second operand of the | |
4073 | innermost PLUS. */ | |
4074 | ||
4075 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4076 | && GET_CODE (XEXP (ad, 0)) == PLUS | |
4077 | && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx | |
4078 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
4079 | || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx | |
4080 | #endif | |
4081 | || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx) | |
4082 | && ! memory_address_p (mode, ad)) | |
4083 | { | |
4084 | *loc = ad = gen_rtx (PLUS, GET_MODE (ad), | |
4085 | plus_constant (XEXP (XEXP (ad, 0), 0), | |
4086 | INTVAL (XEXP (ad, 1))), | |
4087 | XEXP (XEXP (ad, 0), 1)); | |
4088 | find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, | |
a8c9daeb RK |
4089 | GET_MODE (ad), opnum, type, ind_levels); |
4090 | find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, type, 0); | |
eab89b90 RK |
4091 | |
4092 | return 1; | |
4093 | } | |
4094 | ||
4095 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4096 | && GET_CODE (XEXP (ad, 0)) == PLUS | |
4097 | && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx | |
4098 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
4099 | || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx | |
4100 | #endif | |
4101 | || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx) | |
4102 | && ! memory_address_p (mode, ad)) | |
4103 | { | |
4104 | *loc = ad = gen_rtx (PLUS, GET_MODE (ad), | |
4105 | plus_constant (XEXP (XEXP (ad, 0), 1), | |
4106 | INTVAL (XEXP (ad, 1))), | |
4107 | XEXP (XEXP (ad, 0), 0)); | |
4108 | find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, | |
a8c9daeb RK |
4109 | GET_MODE (ad), opnum, type, ind_levels); |
4110 | find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, type, 0); | |
eab89b90 RK |
4111 | |
4112 | return 1; | |
4113 | } | |
4114 | ||
4115 | /* See if address becomes valid when an eliminable register | |
4116 | in a sum is replaced. */ | |
4117 | ||
4118 | tem = ad; | |
4119 | if (GET_CODE (ad) == PLUS) | |
4120 | tem = subst_indexed_address (ad); | |
4121 | if (tem != ad && strict_memory_address_p (mode, tem)) | |
4122 | { | |
4123 | /* Ok, we win that way. Replace any additional eliminable | |
4124 | registers. */ | |
4125 | ||
4126 | subst_reg_equivs_changed = 0; | |
4127 | tem = subst_reg_equivs (tem); | |
4128 | ||
4129 | /* Make sure that didn't make the address invalid again. */ | |
4130 | ||
4131 | if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) | |
4132 | { | |
4133 | *loc = tem; | |
4134 | return 0; | |
4135 | } | |
4136 | } | |
4137 | ||
4138 | /* If constants aren't valid addresses, reload the constant address | |
4139 | into a register. */ | |
191b18e9 | 4140 | if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) |
eab89b90 RK |
4141 | { |
4142 | /* If AD is in address in the constant pool, the MEM rtx may be shared. | |
4143 | Unshare it so we can safely alter it. */ | |
4144 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
4145 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
4146 | { | |
4147 | rtx oldref = *memrefloc; | |
4148 | *memrefloc = copy_rtx (*memrefloc); | |
4149 | loc = &XEXP (*memrefloc, 0); | |
eab89b90 RK |
4150 | } |
4151 | ||
a8c9daeb | 4152 | find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, opnum, type, |
eab89b90 RK |
4153 | ind_levels); |
4154 | return 1; | |
4155 | } | |
4156 | ||
a8c9daeb | 4157 | return find_reloads_address_1 (ad, 0, loc, opnum, type, ind_levels); |
eab89b90 RK |
4158 | } |
4159 | \f | |
4160 | /* Find all pseudo regs appearing in AD | |
4161 | that are eliminable in favor of equivalent values | |
4162 | and do not have hard regs; replace them by their equivalents. */ | |
4163 | ||
4164 | static rtx | |
4165 | subst_reg_equivs (ad) | |
4166 | rtx ad; | |
4167 | { | |
4168 | register RTX_CODE code = GET_CODE (ad); | |
4169 | register int i; | |
4170 | register char *fmt; | |
4171 | ||
4172 | switch (code) | |
4173 | { | |
4174 | case HIGH: | |
4175 | case CONST_INT: | |
4176 | case CONST: | |
4177 | case CONST_DOUBLE: | |
4178 | case SYMBOL_REF: | |
4179 | case LABEL_REF: | |
4180 | case PC: | |
4181 | case CC0: | |
4182 | return ad; | |
4183 | ||
4184 | case REG: | |
4185 | { | |
4186 | register int regno = REGNO (ad); | |
4187 | ||
4188 | if (reg_equiv_constant[regno] != 0) | |
4189 | { | |
4190 | subst_reg_equivs_changed = 1; | |
4191 | return reg_equiv_constant[regno]; | |
4192 | } | |
4193 | } | |
4194 | return ad; | |
4195 | ||
4196 | case PLUS: | |
4197 | /* Quickly dispose of a common case. */ | |
4198 | if (XEXP (ad, 0) == frame_pointer_rtx | |
4199 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
4200 | return ad; | |
4201 | } | |
4202 | ||
4203 | fmt = GET_RTX_FORMAT (code); | |
4204 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4205 | if (fmt[i] == 'e') | |
4206 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i)); | |
4207 | return ad; | |
4208 | } | |
4209 | \f | |
4210 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
4211 | address, namely: sum constant integers, surround the sum of two | |
4212 | constants with a CONST, put the constant as the second operand, and | |
4213 | group the constant on the outermost sum. | |
4214 | ||
4215 | This routine assumes both inputs are already in canonical form. */ | |
4216 | ||
4217 | rtx | |
4218 | form_sum (x, y) | |
4219 | rtx x, y; | |
4220 | { | |
4221 | rtx tem; | |
2c0623e8 RK |
4222 | enum machine_mode mode = GET_MODE (x); |
4223 | ||
4224 | if (mode == VOIDmode) | |
4225 | mode = GET_MODE (y); | |
4226 | ||
4227 | if (mode == VOIDmode) | |
4228 | mode = Pmode; | |
eab89b90 RK |
4229 | |
4230 | if (GET_CODE (x) == CONST_INT) | |
4231 | return plus_constant (y, INTVAL (x)); | |
4232 | else if (GET_CODE (y) == CONST_INT) | |
4233 | return plus_constant (x, INTVAL (y)); | |
4234 | else if (CONSTANT_P (x)) | |
4235 | tem = x, x = y, y = tem; | |
4236 | ||
4237 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
4238 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
4239 | ||
4240 | /* Note that if the operands of Y are specified in the opposite | |
4241 | order in the recursive calls below, infinite recursion will occur. */ | |
4242 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) | |
4243 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); | |
4244 | ||
4245 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
4246 | constant will have been placed second. */ | |
4247 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
4248 | { | |
4249 | if (GET_CODE (x) == CONST) | |
4250 | x = XEXP (x, 0); | |
4251 | if (GET_CODE (y) == CONST) | |
4252 | y = XEXP (y, 0); | |
4253 | ||
2c0623e8 | 4254 | return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, mode, x, y)); |
eab89b90 RK |
4255 | } |
4256 | ||
2c0623e8 | 4257 | return gen_rtx (PLUS, mode, x, y); |
eab89b90 RK |
4258 | } |
4259 | \f | |
4260 | /* If ADDR is a sum containing a pseudo register that should be | |
4261 | replaced with a constant (from reg_equiv_constant), | |
4262 | return the result of doing so, and also apply the associative | |
4263 | law so that the result is more likely to be a valid address. | |
4264 | (But it is not guaranteed to be one.) | |
4265 | ||
4266 | Note that at most one register is replaced, even if more are | |
4267 | replaceable. Also, we try to put the result into a canonical form | |
4268 | so it is more likely to be a valid address. | |
4269 | ||
4270 | In all other cases, return ADDR. */ | |
4271 | ||
4272 | static rtx | |
4273 | subst_indexed_address (addr) | |
4274 | rtx addr; | |
4275 | { | |
4276 | rtx op0 = 0, op1 = 0, op2 = 0; | |
4277 | rtx tem; | |
4278 | int regno; | |
4279 | ||
4280 | if (GET_CODE (addr) == PLUS) | |
4281 | { | |
4282 | /* Try to find a register to replace. */ | |
4283 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
4284 | if (GET_CODE (op0) == REG | |
4285 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER | |
4286 | && reg_renumber[regno] < 0 | |
4287 | && reg_equiv_constant[regno] != 0) | |
4288 | op0 = reg_equiv_constant[regno]; | |
4289 | else if (GET_CODE (op1) == REG | |
4290 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER | |
4291 | && reg_renumber[regno] < 0 | |
4292 | && reg_equiv_constant[regno] != 0) | |
4293 | op1 = reg_equiv_constant[regno]; | |
4294 | else if (GET_CODE (op0) == PLUS | |
4295 | && (tem = subst_indexed_address (op0)) != op0) | |
4296 | op0 = tem; | |
4297 | else if (GET_CODE (op1) == PLUS | |
4298 | && (tem = subst_indexed_address (op1)) != op1) | |
4299 | op1 = tem; | |
4300 | else | |
4301 | return addr; | |
4302 | ||
4303 | /* Pick out up to three things to add. */ | |
4304 | if (GET_CODE (op1) == PLUS) | |
4305 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
4306 | else if (GET_CODE (op0) == PLUS) | |
4307 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
4308 | ||
4309 | /* Compute the sum. */ | |
4310 | if (op2 != 0) | |
4311 | op1 = form_sum (op1, op2); | |
4312 | if (op1 != 0) | |
4313 | op0 = form_sum (op0, op1); | |
4314 | ||
4315 | return op0; | |
4316 | } | |
4317 | return addr; | |
4318 | } | |
4319 | \f | |
4320 | /* Record the pseudo registers we must reload into hard registers | |
4321 | in a subexpression of a would-be memory address, X. | |
4322 | (This function is not called if the address we find is strictly valid.) | |
4323 | CONTEXT = 1 means we are considering regs as index regs, | |
4324 | = 0 means we are considering them as base regs. | |
4325 | ||
a8c9daeb | 4326 | OPNUM and TYPE specify the purpose of any reloads made. |
eab89b90 RK |
4327 | |
4328 | IND_LEVELS says how many levels of indirect addressing are | |
4329 | supported at this point in the address. | |
4330 | ||
4331 | We return nonzero if X, as a whole, is reloaded or replaced. */ | |
4332 | ||
4333 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
4334 | occurs as part of an address. | |
4335 | Also, this is not fully machine-customizable; it works for machines | |
4336 | such as vaxes and 68000's and 32000's, but other possible machines | |
4337 | could have addressing modes that this does not handle right. */ | |
4338 | ||
4339 | static int | |
a8c9daeb | 4340 | find_reloads_address_1 (x, context, loc, opnum, type, ind_levels) |
eab89b90 RK |
4341 | rtx x; |
4342 | int context; | |
4343 | rtx *loc; | |
a8c9daeb RK |
4344 | int opnum; |
4345 | enum reload_type type; | |
eab89b90 RK |
4346 | int ind_levels; |
4347 | { | |
4348 | register RTX_CODE code = GET_CODE (x); | |
4349 | ||
4350 | if (code == PLUS) | |
4351 | { | |
4352 | register rtx op0 = XEXP (x, 0); | |
4353 | register rtx op1 = XEXP (x, 1); | |
4354 | register RTX_CODE code0 = GET_CODE (op0); | |
4355 | register RTX_CODE code1 = GET_CODE (op1); | |
4356 | if (code0 == MULT || code0 == SIGN_EXTEND || code1 == MEM) | |
4357 | { | |
a8c9daeb RK |
4358 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, |
4359 | ind_levels); | |
4360 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, | |
4361 | ind_levels); | |
eab89b90 RK |
4362 | } |
4363 | else if (code1 == MULT || code1 == SIGN_EXTEND || code0 == MEM) | |
4364 | { | |
a8c9daeb RK |
4365 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, |
4366 | ind_levels); | |
4367 | find_reloads_address_1 (op1, 1, &XEXP (x, 1), opnum, type, | |
4368 | ind_levels); | |
eab89b90 RK |
4369 | } |
4370 | else if (code0 == CONST_INT || code0 == CONST | |
4371 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
a8c9daeb | 4372 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, ind_levels); |
eab89b90 RK |
4373 | else if (code1 == CONST_INT || code1 == CONST |
4374 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
a8c9daeb | 4375 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, ind_levels); |
eab89b90 RK |
4376 | else if (code0 == REG && code1 == REG) |
4377 | { | |
4378 | if (REG_OK_FOR_INDEX_P (op0) | |
4379 | && REG_OK_FOR_BASE_P (op1)) | |
4380 | return 0; | |
4381 | else if (REG_OK_FOR_INDEX_P (op1) | |
4382 | && REG_OK_FOR_BASE_P (op0)) | |
4383 | return 0; | |
4384 | else if (REG_OK_FOR_BASE_P (op1)) | |
a8c9daeb RK |
4385 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, |
4386 | ind_levels); | |
eab89b90 | 4387 | else if (REG_OK_FOR_BASE_P (op0)) |
a8c9daeb RK |
4388 | find_reloads_address_1 (op1, 1, &XEXP (x, 1), opnum, type, |
4389 | ind_levels); | |
eab89b90 | 4390 | else if (REG_OK_FOR_INDEX_P (op1)) |
a8c9daeb RK |
4391 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, |
4392 | ind_levels); | |
eab89b90 | 4393 | else if (REG_OK_FOR_INDEX_P (op0)) |
a8c9daeb RK |
4394 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, |
4395 | ind_levels); | |
eab89b90 RK |
4396 | else |
4397 | { | |
a8c9daeb | 4398 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, |
eab89b90 | 4399 | ind_levels); |
a8c9daeb | 4400 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, |
eab89b90 RK |
4401 | ind_levels); |
4402 | } | |
4403 | } | |
4404 | else if (code0 == REG) | |
4405 | { | |
a8c9daeb RK |
4406 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), opnum, type, |
4407 | ind_levels); | |
4408 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), opnum, type, | |
4409 | ind_levels); | |
eab89b90 RK |
4410 | } |
4411 | else if (code1 == REG) | |
4412 | { | |
a8c9daeb RK |
4413 | find_reloads_address_1 (op1, 1, &XEXP (x, 1), opnum, type, |
4414 | ind_levels); | |
4415 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), opnum, type, | |
4416 | ind_levels); | |
eab89b90 RK |
4417 | } |
4418 | } | |
4419 | else if (code == POST_INC || code == POST_DEC | |
4420 | || code == PRE_INC || code == PRE_DEC) | |
4421 | { | |
4422 | if (GET_CODE (XEXP (x, 0)) == REG) | |
4423 | { | |
4424 | register int regno = REGNO (XEXP (x, 0)); | |
4425 | int value = 0; | |
4426 | rtx x_orig = x; | |
4427 | ||
4428 | /* A register that is incremented cannot be constant! */ | |
4429 | if (regno >= FIRST_PSEUDO_REGISTER | |
4430 | && reg_equiv_constant[regno] != 0) | |
4431 | abort (); | |
4432 | ||
4433 | /* Handle a register that is equivalent to a memory location | |
4434 | which cannot be addressed directly. */ | |
4435 | if (reg_equiv_address[regno] != 0) | |
4436 | { | |
4437 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
4438 | /* First reload the memory location's address. */ | |
4439 | find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0), | |
a8c9daeb | 4440 | &XEXP (tem, 0), opnum, type, ind_levels); |
eab89b90 RK |
4441 | /* Put this inside a new increment-expression. */ |
4442 | x = gen_rtx (GET_CODE (x), GET_MODE (x), tem); | |
4443 | /* Proceed to reload that, as if it contained a register. */ | |
4444 | } | |
4445 | ||
4446 | /* If we have a hard register that is ok as an index, | |
4447 | don't make a reload. If an autoincrement of a nice register | |
4448 | isn't "valid", it must be that no autoincrement is "valid". | |
4449 | If that is true and something made an autoincrement anyway, | |
4450 | this must be a special context where one is allowed. | |
4451 | (For example, a "push" instruction.) | |
4452 | We can't improve this address, so leave it alone. */ | |
4453 | ||
4454 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
4455 | and record how much to increment by. */ | |
4456 | ||
4457 | if (reg_renumber[regno] >= 0) | |
4458 | regno = reg_renumber[regno]; | |
4459 | if ((regno >= FIRST_PSEUDO_REGISTER | |
4460 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
4461 | : REGNO_OK_FOR_BASE_P (regno)))) | |
4462 | { | |
4463 | register rtx link; | |
4464 | ||
4465 | int reloadnum | |
fb3821f7 | 4466 | = push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 | 4467 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
a8c9daeb RK |
4468 | GET_MODE (x), GET_MODE (x), VOIDmode, 0, |
4469 | opnum, type); | |
eab89b90 RK |
4470 | reload_inc[reloadnum] |
4471 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); | |
4472 | ||
4473 | value = 1; | |
4474 | ||
4475 | #ifdef AUTO_INC_DEC | |
4476 | /* Update the REG_INC notes. */ | |
4477 | ||
4478 | for (link = REG_NOTES (this_insn); | |
4479 | link; link = XEXP (link, 1)) | |
4480 | if (REG_NOTE_KIND (link) == REG_INC | |
4481 | && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0))) | |
4482 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
4483 | #endif | |
4484 | } | |
4485 | return value; | |
4486 | } | |
4487 | else if (GET_CODE (XEXP (x, 0)) == MEM) | |
4488 | { | |
4489 | /* This is probably the result of a substitution, by eliminate_regs, | |
4490 | of an equivalent address for a pseudo that was not allocated to a | |
4491 | hard register. Verify that the specified address is valid and | |
4492 | reload it into a register. */ | |
4493 | rtx tem = XEXP (x, 0); | |
4494 | register rtx link; | |
4495 | int reloadnum; | |
4496 | ||
4497 | /* Since we know we are going to reload this item, don't decrement | |
4498 | for the indirection level. | |
4499 | ||
4500 | Note that this is actually conservative: it would be slightly | |
4501 | more efficient to use the value of SPILL_INDIRECT_LEVELS from | |
4502 | reload1.c here. */ | |
4503 | find_reloads_address (GET_MODE (x), &XEXP (x, 0), | |
4504 | XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0), | |
a8c9daeb | 4505 | opnum, type, ind_levels); |
eab89b90 | 4506 | |
fb3821f7 | 4507 | reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 | 4508 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
a8c9daeb | 4509 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4510 | reload_inc[reloadnum] |
4511 | = find_inc_amount (PATTERN (this_insn), XEXP (x, 0)); | |
4512 | ||
4513 | link = FIND_REG_INC_NOTE (this_insn, tem); | |
4514 | if (link != 0) | |
4515 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
4516 | ||
4517 | return 1; | |
4518 | } | |
4519 | } | |
4520 | else if (code == MEM) | |
4521 | { | |
4522 | /* This is probably the result of a substitution, by eliminate_regs, | |
4523 | of an equivalent address for a pseudo that was not allocated to a | |
4524 | hard register. Verify that the specified address is valid and reload | |
4525 | it into a register. | |
4526 | ||
4527 | Since we know we are going to reload this item, don't decrement | |
4528 | for the indirection level. | |
4529 | ||
4530 | Note that this is actually conservative: it would be slightly more | |
4531 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
4532 | reload1.c here. */ | |
4533 | ||
4534 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
a8c9daeb | 4535 | opnum, type, ind_levels); |
eab89b90 | 4536 | |
fb3821f7 | 4537 | push_reload (*loc, NULL_RTX, loc, NULL_PTR, |
eab89b90 | 4538 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
a8c9daeb | 4539 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4540 | return 1; |
4541 | } | |
4542 | else if (code == REG) | |
4543 | { | |
4544 | register int regno = REGNO (x); | |
4545 | ||
4546 | if (reg_equiv_constant[regno] != 0) | |
4547 | { | |
58c8c593 RK |
4548 | find_reloads_address_part (reg_equiv_constant[regno], loc, |
4549 | (context ? INDEX_REG_CLASS | |
4550 | : BASE_REG_CLASS), | |
a8c9daeb | 4551 | GET_MODE (x), opnum, type, ind_levels); |
eab89b90 RK |
4552 | return 1; |
4553 | } | |
4554 | ||
4555 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
4556 | that feeds this insn. */ | |
4557 | if (reg_equiv_mem[regno] != 0) | |
4558 | { | |
fb3821f7 | 4559 | push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR, |
eab89b90 | 4560 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
a8c9daeb | 4561 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4562 | return 1; |
4563 | } | |
4564 | #endif | |
4565 | if (reg_equiv_address[regno] != 0) | |
4566 | { | |
4567 | x = make_memloc (x, regno); | |
4568 | find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0), | |
a8c9daeb | 4569 | opnum, type, ind_levels); |
eab89b90 RK |
4570 | } |
4571 | ||
4572 | if (reg_renumber[regno] >= 0) | |
4573 | regno = reg_renumber[regno]; | |
4574 | if ((regno >= FIRST_PSEUDO_REGISTER | |
4575 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
4576 | : REGNO_OK_FOR_BASE_P (regno)))) | |
4577 | { | |
fb3821f7 | 4578 | push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 | 4579 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
a8c9daeb | 4580 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4581 | return 1; |
4582 | } | |
4583 | ||
4584 | /* If a register appearing in an address is the subject of a CLOBBER | |
4585 | in this insn, reload it into some other register to be safe. | |
4586 | The CLOBBER is supposed to make the register unavailable | |
4587 | from before this insn to after it. */ | |
4588 | if (regno_clobbered_p (regno, this_insn)) | |
4589 | { | |
fb3821f7 | 4590 | push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 | 4591 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
a8c9daeb | 4592 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4593 | return 1; |
4594 | } | |
4595 | } | |
4596 | else | |
4597 | { | |
4598 | register char *fmt = GET_RTX_FORMAT (code); | |
4599 | register int i; | |
4600 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4601 | { | |
4602 | if (fmt[i] == 'e') | |
4603 | find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i), | |
a8c9daeb | 4604 | opnum, type, ind_levels); |
eab89b90 RK |
4605 | } |
4606 | } | |
4607 | ||
4608 | return 0; | |
4609 | } | |
4610 | \f | |
4611 | /* X, which is found at *LOC, is a part of an address that needs to be | |
4612 | reloaded into a register of class CLASS. If X is a constant, or if | |
4613 | X is a PLUS that contains a constant, check that the constant is a | |
4614 | legitimate operand and that we are supposed to be able to load | |
4615 | it into the register. | |
4616 | ||
4617 | If not, force the constant into memory and reload the MEM instead. | |
4618 | ||
4619 | MODE is the mode to use, in case X is an integer constant. | |
4620 | ||
a8c9daeb | 4621 | OPNUM and TYPE describe the purpose of any reloads made. |
eab89b90 RK |
4622 | |
4623 | IND_LEVELS says how many levels of indirect addressing this machine | |
4624 | supports. */ | |
4625 | ||
4626 | static void | |
a8c9daeb | 4627 | find_reloads_address_part (x, loc, class, mode, opnum, type, ind_levels) |
eab89b90 RK |
4628 | rtx x; |
4629 | rtx *loc; | |
4630 | enum reg_class class; | |
4631 | enum machine_mode mode; | |
a8c9daeb RK |
4632 | int opnum; |
4633 | enum reload_type type; | |
eab89b90 RK |
4634 | int ind_levels; |
4635 | { | |
4636 | if (CONSTANT_P (x) | |
4637 | && (! LEGITIMATE_CONSTANT_P (x) | |
4638 | || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) | |
4639 | { | |
4640 | rtx tem = x = force_const_mem (mode, x); | |
4641 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), | |
a8c9daeb | 4642 | opnum, type, ind_levels); |
eab89b90 RK |
4643 | } |
4644 | ||
4645 | else if (GET_CODE (x) == PLUS | |
4646 | && CONSTANT_P (XEXP (x, 1)) | |
4647 | && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | |
4648 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) | |
4649 | { | |
4650 | rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); | |
4651 | ||
4652 | x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem); | |
4653 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), | |
a8c9daeb | 4654 | opnum, type, ind_levels); |
eab89b90 RK |
4655 | } |
4656 | ||
fb3821f7 | 4657 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, |
a8c9daeb | 4658 | mode, VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4659 | } |
4660 | \f | |
a8c9daeb | 4661 | /* Substitute into the current INSN the registers into which we have reloaded |
eab89b90 RK |
4662 | the things that need reloading. The array `replacements' |
4663 | says contains the locations of all pointers that must be changed | |
4664 | and says what to replace them with. | |
4665 | ||
4666 | Return the rtx that X translates into; usually X, but modified. */ | |
4667 | ||
4668 | void | |
4669 | subst_reloads () | |
4670 | { | |
4671 | register int i; | |
4672 | ||
4673 | for (i = 0; i < n_replacements; i++) | |
4674 | { | |
4675 | register struct replacement *r = &replacements[i]; | |
4676 | register rtx reloadreg = reload_reg_rtx[r->what]; | |
4677 | if (reloadreg) | |
4678 | { | |
4679 | /* Encapsulate RELOADREG so its machine mode matches what | |
26f1a00e RK |
4680 | used to be there. Note that gen_lowpart_common will |
4681 | do the wrong thing if RELOADREG is multi-word. RELOADREG | |
4682 | will always be a REG here. */ | |
eab89b90 | 4683 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) |
26f1a00e | 4684 | reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg)); |
eab89b90 RK |
4685 | |
4686 | /* If we are putting this into a SUBREG and RELOADREG is a | |
4687 | SUBREG, we would be making nested SUBREGs, so we have to fix | |
4688 | this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ | |
4689 | ||
4690 | if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) | |
4691 | { | |
4692 | if (GET_MODE (*r->subreg_loc) | |
4693 | == GET_MODE (SUBREG_REG (reloadreg))) | |
4694 | *r->subreg_loc = SUBREG_REG (reloadreg); | |
4695 | else | |
4696 | { | |
4697 | *r->where = SUBREG_REG (reloadreg); | |
4698 | SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg); | |
4699 | } | |
4700 | } | |
4701 | else | |
4702 | *r->where = reloadreg; | |
4703 | } | |
4704 | /* If reload got no reg and isn't optional, something's wrong. */ | |
4705 | else if (! reload_optional[r->what]) | |
4706 | abort (); | |
4707 | } | |
4708 | } | |
4709 | \f | |
4710 | /* Make a copy of any replacements being done into X and move those copies | |
4711 | to locations in Y, a copy of X. We only look at the highest level of | |
4712 | the RTL. */ | |
4713 | ||
4714 | void | |
4715 | copy_replacements (x, y) | |
4716 | rtx x; | |
4717 | rtx y; | |
4718 | { | |
4719 | int i, j; | |
4720 | enum rtx_code code = GET_CODE (x); | |
4721 | char *fmt = GET_RTX_FORMAT (code); | |
4722 | struct replacement *r; | |
4723 | ||
4724 | /* We can't support X being a SUBREG because we might then need to know its | |
4725 | location if something inside it was replaced. */ | |
4726 | if (code == SUBREG) | |
4727 | abort (); | |
4728 | ||
4729 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4730 | if (fmt[i] == 'e') | |
4731 | for (j = 0; j < n_replacements; j++) | |
4732 | { | |
4733 | if (replacements[j].subreg_loc == &XEXP (x, i)) | |
4734 | { | |
4735 | r = &replacements[n_replacements++]; | |
4736 | r->where = replacements[j].where; | |
4737 | r->subreg_loc = &XEXP (y, i); | |
4738 | r->what = replacements[j].what; | |
4739 | r->mode = replacements[j].mode; | |
4740 | } | |
4741 | else if (replacements[j].where == &XEXP (x, i)) | |
4742 | { | |
4743 | r = &replacements[n_replacements++]; | |
4744 | r->where = &XEXP (y, i); | |
4745 | r->subreg_loc = 0; | |
4746 | r->what = replacements[j].what; | |
4747 | r->mode = replacements[j].mode; | |
4748 | } | |
4749 | } | |
4750 | } | |
4751 | \f | |
af929c62 RK |
4752 | /* If LOC was scheduled to be replaced by something, return the replacement. |
4753 | Otherwise, return *LOC. */ | |
4754 | ||
4755 | rtx | |
4756 | find_replacement (loc) | |
4757 | rtx *loc; | |
4758 | { | |
4759 | struct replacement *r; | |
4760 | ||
4761 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
4762 | { | |
4763 | rtx reloadreg = reload_reg_rtx[r->what]; | |
4764 | ||
4765 | if (reloadreg && r->where == loc) | |
4766 | { | |
4767 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
4768 | reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg)); | |
4769 | ||
4770 | return reloadreg; | |
4771 | } | |
4772 | else if (reloadreg && r->subreg_loc == loc) | |
4773 | { | |
4774 | /* RELOADREG must be either a REG or a SUBREG. | |
4775 | ||
4776 | ??? Is it actually still ever a SUBREG? If so, why? */ | |
4777 | ||
4778 | if (GET_CODE (reloadreg) == REG) | |
4779 | return gen_rtx (REG, GET_MODE (*loc), | |
4780 | REGNO (reloadreg) + SUBREG_WORD (*loc)); | |
4781 | else if (GET_MODE (reloadreg) == GET_MODE (*loc)) | |
4782 | return reloadreg; | |
4783 | else | |
4784 | return gen_rtx (SUBREG, GET_MODE (*loc), SUBREG_REG (reloadreg), | |
4785 | SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc)); | |
4786 | } | |
4787 | } | |
4788 | ||
4789 | return *loc; | |
4790 | } | |
4791 | \f | |
eab89b90 RK |
4792 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
4793 | appears either explicitly or implicitly in X | |
4794 | other than being stored into. | |
4795 | ||
4796 | References contained within the substructure at LOC do not count. | |
4797 | LOC may be zero, meaning don't ignore anything. | |
4798 | ||
4799 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
4800 | look at equivalences for pseudos that didn't get hard registers. */ | |
4801 | ||
4802 | int | |
4803 | refers_to_regno_for_reload_p (regno, endregno, x, loc) | |
4804 | int regno, endregno; | |
4805 | rtx x; | |
4806 | rtx *loc; | |
4807 | { | |
4808 | register int i; | |
4809 | register RTX_CODE code; | |
4810 | register char *fmt; | |
4811 | ||
4812 | if (x == 0) | |
4813 | return 0; | |
4814 | ||
4815 | repeat: | |
4816 | code = GET_CODE (x); | |
4817 | ||
4818 | switch (code) | |
4819 | { | |
4820 | case REG: | |
4821 | i = REGNO (x); | |
4822 | ||
4803a34a RK |
4823 | /* If this is a pseudo, a hard register must not have been allocated. |
4824 | X must therefore either be a constant or be in memory. */ | |
4825 | if (i >= FIRST_PSEUDO_REGISTER) | |
4826 | { | |
4827 | if (reg_equiv_memory_loc[i]) | |
4828 | return refers_to_regno_for_reload_p (regno, endregno, | |
fb3821f7 CH |
4829 | reg_equiv_memory_loc[i], |
4830 | NULL_PTR); | |
4803a34a RK |
4831 | |
4832 | if (reg_equiv_constant[i]) | |
4833 | return 0; | |
4834 | ||
4835 | abort (); | |
4836 | } | |
eab89b90 RK |
4837 | |
4838 | return (endregno > i | |
4839 | && regno < i + (i < FIRST_PSEUDO_REGISTER | |
4840 | ? HARD_REGNO_NREGS (i, GET_MODE (x)) | |
4841 | : 1)); | |
4842 | ||
4843 | case SUBREG: | |
4844 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
4845 | registers are being modified. Otherwise, handle normally. */ | |
4846 | if (GET_CODE (SUBREG_REG (x)) == REG | |
4847 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
4848 | { | |
4849 | int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
4850 | int inner_endregno | |
4851 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER | |
4852 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
4853 | ||
4854 | return endregno > inner_regno && regno < inner_endregno; | |
4855 | } | |
4856 | break; | |
4857 | ||
4858 | case CLOBBER: | |
4859 | case SET: | |
4860 | if (&SET_DEST (x) != loc | |
4861 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
4862 | a pseudo but not for hard registers since we can | |
4863 | treat each word individually. */ | |
4864 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
4865 | && loc != &SUBREG_REG (SET_DEST (x)) | |
4866 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
4867 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER | |
4868 | && refers_to_regno_for_reload_p (regno, endregno, | |
4869 | SUBREG_REG (SET_DEST (x)), | |
4870 | loc)) | |
4871 | || (GET_CODE (SET_DEST (x)) != REG | |
4872 | && refers_to_regno_for_reload_p (regno, endregno, | |
4873 | SET_DEST (x), loc)))) | |
4874 | return 1; | |
4875 | ||
4876 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
4877 | return 0; | |
4878 | x = SET_SRC (x); | |
4879 | goto repeat; | |
4880 | } | |
4881 | ||
4882 | /* X does not match, so try its subexpressions. */ | |
4883 | ||
4884 | fmt = GET_RTX_FORMAT (code); | |
4885 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4886 | { | |
4887 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
4888 | { | |
4889 | if (i == 0) | |
4890 | { | |
4891 | x = XEXP (x, 0); | |
4892 | goto repeat; | |
4893 | } | |
4894 | else | |
4895 | if (refers_to_regno_for_reload_p (regno, endregno, | |
4896 | XEXP (x, i), loc)) | |
4897 | return 1; | |
4898 | } | |
4899 | else if (fmt[i] == 'E') | |
4900 | { | |
4901 | register int j; | |
4902 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
4903 | if (loc != &XVECEXP (x, i, j) | |
4904 | && refers_to_regno_for_reload_p (regno, endregno, | |
4905 | XVECEXP (x, i, j), loc)) | |
4906 | return 1; | |
4907 | } | |
4908 | } | |
4909 | return 0; | |
4910 | } | |
bfa30b22 RK |
4911 | |
4912 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
4913 | we check if any register number in X conflicts with the relevant register | |
4914 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
4915 | contains a MEM (we don't bother checking for memory addresses that can't | |
4916 | conflict because we expect this to be a rare case. | |
4917 | ||
4918 | This function is similar to reg_overlap_mention_p in rtlanal.c except | |
4919 | that we look at equivalences for pseudos that didn't get hard registers. */ | |
4920 | ||
4921 | int | |
4922 | reg_overlap_mentioned_for_reload_p (x, in) | |
4923 | rtx x, in; | |
4924 | { | |
4925 | int regno, endregno; | |
4926 | ||
4927 | if (GET_CODE (x) == SUBREG) | |
4928 | { | |
4929 | regno = REGNO (SUBREG_REG (x)); | |
4930 | if (regno < FIRST_PSEUDO_REGISTER) | |
4931 | regno += SUBREG_WORD (x); | |
4932 | } | |
4933 | else if (GET_CODE (x) == REG) | |
4934 | { | |
4935 | regno = REGNO (x); | |
4803a34a RK |
4936 | |
4937 | /* If this is a pseudo, it must not have been assigned a hard register. | |
4938 | Therefore, it must either be in memory or be a constant. */ | |
4939 | ||
4940 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4941 | { | |
4942 | if (reg_equiv_memory_loc[regno]) | |
4943 | return refers_to_mem_for_reload_p (in); | |
4944 | else if (reg_equiv_constant[regno]) | |
4945 | return 0; | |
4946 | abort (); | |
4947 | } | |
bfa30b22 RK |
4948 | } |
4949 | else if (CONSTANT_P (x)) | |
4950 | return 0; | |
4951 | else if (GET_CODE (x) == MEM) | |
4803a34a | 4952 | return refers_to_mem_for_reload_p (in); |
bfa30b22 RK |
4953 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
4954 | || GET_CODE (x) == CC0) | |
4955 | return reg_mentioned_p (x, in); | |
4956 | else | |
4957 | abort (); | |
4958 | ||
4959 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
4960 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
4961 | ||
fb3821f7 | 4962 | return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR); |
bfa30b22 | 4963 | } |
4803a34a RK |
4964 | |
4965 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
4966 | registers. */ | |
4967 | ||
4968 | int | |
4969 | refers_to_mem_for_reload_p (x) | |
4970 | rtx x; | |
4971 | { | |
4972 | char *fmt; | |
4973 | int i; | |
4974 | ||
4975 | if (GET_CODE (x) == MEM) | |
4976 | return 1; | |
4977 | ||
4978 | if (GET_CODE (x) == REG) | |
4979 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
4980 | && reg_equiv_memory_loc[REGNO (x)]); | |
4981 | ||
4982 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
4983 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
4984 | if (fmt[i] == 'e' | |
4985 | && (GET_CODE (XEXP (x, i)) == MEM | |
4986 | || refers_to_mem_for_reload_p (XEXP (x, i)))) | |
4987 | return 1; | |
4988 | ||
4989 | return 0; | |
4990 | } | |
eab89b90 | 4991 | \f |
eab89b90 RK |
4992 | /* Check the insns before INSN to see if there is a suitable register |
4993 | containing the same value as GOAL. | |
4994 | If OTHER is -1, look for a register in class CLASS. | |
4995 | Otherwise, just see if register number OTHER shares GOAL's value. | |
4996 | ||
4997 | Return an rtx for the register found, or zero if none is found. | |
4998 | ||
4999 | If RELOAD_REG_P is (short *)1, | |
5000 | we reject any hard reg that appears in reload_reg_rtx | |
5001 | because such a hard reg is also needed coming into this insn. | |
5002 | ||
5003 | If RELOAD_REG_P is any other nonzero value, | |
5004 | it is a vector indexed by hard reg number | |
5005 | and we reject any hard reg whose element in the vector is nonnegative | |
5006 | as well as any that appears in reload_reg_rtx. | |
5007 | ||
5008 | If GOAL is zero, then GOALREG is a register number; we look | |
5009 | for an equivalent for that register. | |
5010 | ||
5011 | MODE is the machine mode of the value we want an equivalence for. | |
5012 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
5013 | ||
5014 | This function is used by jump.c as well as in the reload pass. | |
5015 | ||
5016 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
5017 | as if it were a constant except that sp is required to be unchanging. */ | |
5018 | ||
5019 | rtx | |
5020 | find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode) | |
5021 | register rtx goal; | |
5022 | rtx insn; | |
5023 | enum reg_class class; | |
5024 | register int other; | |
5025 | short *reload_reg_p; | |
5026 | int goalreg; | |
5027 | enum machine_mode mode; | |
5028 | { | |
5029 | register rtx p = insn; | |
f55b1d97 | 5030 | rtx goaltry, valtry, value, where; |
eab89b90 RK |
5031 | register rtx pat; |
5032 | register int regno = -1; | |
5033 | int valueno; | |
5034 | int goal_mem = 0; | |
5035 | int goal_const = 0; | |
5036 | int goal_mem_addr_varies = 0; | |
5037 | int need_stable_sp = 0; | |
5038 | int nregs; | |
5039 | int valuenregs; | |
5040 | ||
5041 | if (goal == 0) | |
5042 | regno = goalreg; | |
5043 | else if (GET_CODE (goal) == REG) | |
5044 | regno = REGNO (goal); | |
5045 | else if (GET_CODE (goal) == MEM) | |
5046 | { | |
5047 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
5048 | if (MEM_VOLATILE_P (goal)) | |
5049 | return 0; | |
5050 | if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT) | |
5051 | return 0; | |
5052 | /* An address with side effects must be reexecuted. */ | |
5053 | switch (code) | |
5054 | { | |
5055 | case POST_INC: | |
5056 | case PRE_INC: | |
5057 | case POST_DEC: | |
5058 | case PRE_DEC: | |
5059 | return 0; | |
5060 | } | |
5061 | goal_mem = 1; | |
5062 | } | |
5063 | else if (CONSTANT_P (goal)) | |
5064 | goal_const = 1; | |
5065 | else if (GET_CODE (goal) == PLUS | |
5066 | && XEXP (goal, 0) == stack_pointer_rtx | |
5067 | && CONSTANT_P (XEXP (goal, 1))) | |
5068 | goal_const = need_stable_sp = 1; | |
5069 | else | |
5070 | return 0; | |
5071 | ||
5072 | /* On some machines, certain regs must always be rejected | |
5073 | because they don't behave the way ordinary registers do. */ | |
5074 | ||
5075 | #ifdef OVERLAPPING_REGNO_P | |
5076 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5077 | && OVERLAPPING_REGNO_P (regno)) | |
5078 | return 0; | |
5079 | #endif | |
5080 | ||
5081 | /* Scan insns back from INSN, looking for one that copies | |
5082 | a value into or out of GOAL. | |
5083 | Stop and give up if we reach a label. */ | |
5084 | ||
5085 | while (1) | |
5086 | { | |
5087 | p = PREV_INSN (p); | |
5088 | if (p == 0 || GET_CODE (p) == CODE_LABEL) | |
5089 | return 0; | |
5090 | if (GET_CODE (p) == INSN | |
5091 | /* If we don't want spill regs ... */ | |
a8c9daeb RK |
5092 | && (! (reload_reg_p != 0 |
5093 | && reload_reg_p != (short *) (HOST_WIDE_INT) 1) | |
eab89b90 RK |
5094 | /* ... then ignore insns introduced by reload; they aren't useful |
5095 | and can cause results in reload_as_needed to be different | |
5096 | from what they were when calculating the need for spills. | |
5097 | If we notice an input-reload insn here, we will reject it below, | |
5098 | but it might hide a usable equivalent. That makes bad code. | |
5099 | It may even abort: perhaps no reg was spilled for this insn | |
5100 | because it was assumed we would find that equivalent. */ | |
5101 | || INSN_UID (p) < reload_first_uid)) | |
5102 | { | |
e8094962 | 5103 | rtx tem; |
eab89b90 RK |
5104 | pat = single_set (p); |
5105 | /* First check for something that sets some reg equal to GOAL. */ | |
5106 | if (pat != 0 | |
5107 | && ((regno >= 0 | |
5108 | && true_regnum (SET_SRC (pat)) == regno | |
5109 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
5110 | || | |
5111 | (regno >= 0 | |
5112 | && true_regnum (SET_DEST (pat)) == regno | |
5113 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
5114 | || | |
5115 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
5116 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
5117 | || (goal_mem | |
5118 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
5119 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
5120 | || (goal_mem | |
5121 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
e8094962 RK |
5122 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
5123 | /* If we are looking for a constant, | |
5124 | and something equivalent to that constant was copied | |
5125 | into a reg, we can use that reg. */ | |
fb3821f7 CH |
5126 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5127 | NULL_RTX)) | |
e8094962 | 5128 | && rtx_equal_p (XEXP (tem, 0), goal) |
95d3562b | 5129 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
fb3821f7 CH |
5130 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5131 | NULL_RTX)) | |
e8094962 RK |
5132 | && GET_CODE (SET_DEST (pat)) == REG |
5133 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
5134 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
5135 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
5136 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 0, 0, |
5137 | VOIDmode)) | |
5138 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
5139 | && (valtry = operand_subword (SET_DEST (pat), 0, 0, |
5140 | VOIDmode)) | |
95d3562b | 5141 | && (valueno = true_regnum (valtry)) >= 0) |
fb3821f7 CH |
5142 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5143 | NULL_RTX)) | |
e8094962 RK |
5144 | && GET_CODE (SET_DEST (pat)) == REG |
5145 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
5146 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
5147 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
5148 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, |
5149 | VOIDmode)) | |
5150 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
5151 | && (valtry |
5152 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
95d3562b | 5153 | && (valueno = true_regnum (valtry)) >= 0))) |
eab89b90 RK |
5154 | if (other >= 0 |
5155 | ? valueno == other | |
5156 | : ((unsigned) valueno < FIRST_PSEUDO_REGISTER | |
5157 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
5158 | valueno))) | |
5159 | { | |
5160 | value = valtry; | |
5161 | where = p; | |
5162 | break; | |
5163 | } | |
5164 | } | |
5165 | } | |
5166 | ||
5167 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
5168 | (or copying VALUE into GOAL, if GOAL is also a register). | |
5169 | Now verify that VALUE is really valid. */ | |
5170 | ||
5171 | /* VALUENO is the register number of VALUE; a hard register. */ | |
5172 | ||
5173 | /* Don't try to re-use something that is killed in this insn. We want | |
5174 | to be able to trust REG_UNUSED notes. */ | |
5175 | if (find_reg_note (where, REG_UNUSED, value)) | |
5176 | return 0; | |
5177 | ||
5178 | /* If we propose to get the value from the stack pointer or if GOAL is | |
5179 | a MEM based on the stack pointer, we need a stable SP. */ | |
5180 | if (valueno == STACK_POINTER_REGNUM | |
bfa30b22 RK |
5181 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
5182 | goal))) | |
eab89b90 RK |
5183 | need_stable_sp = 1; |
5184 | ||
5185 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
5186 | if (GET_MODE (value) != mode) | |
5187 | return 0; | |
5188 | ||
5189 | /* Reject VALUE if it was loaded from GOAL | |
5190 | and is also a register that appears in the address of GOAL. */ | |
5191 | ||
5192 | if (goal_mem && value == SET_DEST (PATTERN (where)) | |
bfa30b22 RK |
5193 | && refers_to_regno_for_reload_p (valueno, |
5194 | (valueno | |
5195 | + HARD_REGNO_NREGS (valueno, mode)), | |
fb3821f7 | 5196 | goal, NULL_PTR)) |
eab89b90 RK |
5197 | return 0; |
5198 | ||
5199 | /* Reject registers that overlap GOAL. */ | |
5200 | ||
5201 | if (!goal_mem && !goal_const | |
5202 | && regno + HARD_REGNO_NREGS (regno, mode) > valueno | |
5203 | && regno < valueno + HARD_REGNO_NREGS (valueno, mode)) | |
5204 | return 0; | |
5205 | ||
5206 | /* Reject VALUE if it is one of the regs reserved for reloads. | |
5207 | Reload1 knows how to reuse them anyway, and it would get | |
5208 | confused if we allocated one without its knowledge. | |
5209 | (Now that insns introduced by reload are ignored above, | |
5210 | this case shouldn't happen, but I'm not positive.) */ | |
5211 | ||
a8c9daeb | 5212 | if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1 |
eab89b90 RK |
5213 | && reload_reg_p[valueno] >= 0) |
5214 | return 0; | |
5215 | ||
5216 | /* On some machines, certain regs must always be rejected | |
5217 | because they don't behave the way ordinary registers do. */ | |
5218 | ||
5219 | #ifdef OVERLAPPING_REGNO_P | |
5220 | if (OVERLAPPING_REGNO_P (valueno)) | |
5221 | return 0; | |
5222 | #endif | |
5223 | ||
5224 | nregs = HARD_REGNO_NREGS (regno, mode); | |
5225 | valuenregs = HARD_REGNO_NREGS (valueno, mode); | |
5226 | ||
5227 | /* Reject VALUE if it is a register being used for an input reload | |
5228 | even if it is not one of those reserved. */ | |
5229 | ||
5230 | if (reload_reg_p != 0) | |
5231 | { | |
5232 | int i; | |
5233 | for (i = 0; i < n_reloads; i++) | |
5234 | if (reload_reg_rtx[i] != 0 && reload_in[i]) | |
5235 | { | |
5236 | int regno1 = REGNO (reload_reg_rtx[i]); | |
5237 | int nregs1 = HARD_REGNO_NREGS (regno1, | |
5238 | GET_MODE (reload_reg_rtx[i])); | |
5239 | if (regno1 < valueno + valuenregs | |
5240 | && regno1 + nregs1 > valueno) | |
5241 | return 0; | |
5242 | } | |
5243 | } | |
5244 | ||
5245 | if (goal_mem) | |
54b5ffe9 RS |
5246 | /* We must treat frame pointer as varying here, |
5247 | since it can vary--in a nonlocal goto as generated by expand_goto. */ | |
5248 | goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); | |
eab89b90 RK |
5249 | |
5250 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
5251 | until INSN is reached. */ | |
5252 | ||
5253 | p = insn; | |
5254 | while (1) | |
5255 | { | |
5256 | p = PREV_INSN (p); | |
5257 | if (p == where) | |
5258 | return value; | |
5259 | ||
5260 | /* Don't trust the conversion past a function call | |
5261 | if either of the two is in a call-clobbered register, or memory. */ | |
5262 | if (GET_CODE (p) == CALL_INSN | |
5263 | && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5264 | && call_used_regs[regno]) | |
5265 | || | |
5266 | (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
5267 | && call_used_regs[valueno]) | |
5268 | || | |
5269 | goal_mem | |
5270 | || need_stable_sp)) | |
5271 | return 0; | |
5272 | ||
5273 | #ifdef INSN_CLOBBERS_REGNO_P | |
5274 | if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
5275 | && INSN_CLOBBERS_REGNO_P (p, valueno)) | |
5276 | || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5277 | && INSN_CLOBBERS_REGNO_P (p, regno))) | |
5278 | return 0; | |
5279 | #endif | |
5280 | ||
5281 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
5282 | { | |
5283 | /* If this insn P stores in either GOAL or VALUE, return 0. | |
5284 | If GOAL is a memory ref and this insn writes memory, return 0. | |
5285 | If GOAL is a memory ref and its address is not constant, | |
5286 | and this insn P changes a register used in GOAL, return 0. */ | |
5287 | ||
5288 | pat = PATTERN (p); | |
5289 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) | |
5290 | { | |
5291 | register rtx dest = SET_DEST (pat); | |
5292 | while (GET_CODE (dest) == SUBREG | |
5293 | || GET_CODE (dest) == ZERO_EXTRACT | |
5294 | || GET_CODE (dest) == SIGN_EXTRACT | |
5295 | || GET_CODE (dest) == STRICT_LOW_PART) | |
5296 | dest = XEXP (dest, 0); | |
5297 | if (GET_CODE (dest) == REG) | |
5298 | { | |
5299 | register int xregno = REGNO (dest); | |
5300 | int xnregs; | |
5301 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
5302 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
5303 | else | |
5304 | xnregs = 1; | |
5305 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
5306 | return 0; | |
5307 | if (xregno < valueno + valuenregs | |
5308 | && xregno + xnregs > valueno) | |
5309 | return 0; | |
5310 | if (goal_mem_addr_varies | |
bfa30b22 | 5311 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
eab89b90 RK |
5312 | return 0; |
5313 | } | |
5314 | else if (goal_mem && GET_CODE (dest) == MEM | |
5315 | && ! push_operand (dest, GET_MODE (dest))) | |
5316 | return 0; | |
5317 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) | |
5318 | return 0; | |
5319 | } | |
5320 | else if (GET_CODE (pat) == PARALLEL) | |
5321 | { | |
5322 | register int i; | |
5323 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
5324 | { | |
5325 | register rtx v1 = XVECEXP (pat, 0, i); | |
5326 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) | |
5327 | { | |
5328 | register rtx dest = SET_DEST (v1); | |
5329 | while (GET_CODE (dest) == SUBREG | |
5330 | || GET_CODE (dest) == ZERO_EXTRACT | |
5331 | || GET_CODE (dest) == SIGN_EXTRACT | |
5332 | || GET_CODE (dest) == STRICT_LOW_PART) | |
5333 | dest = XEXP (dest, 0); | |
5334 | if (GET_CODE (dest) == REG) | |
5335 | { | |
5336 | register int xregno = REGNO (dest); | |
5337 | int xnregs; | |
5338 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
5339 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
5340 | else | |
5341 | xnregs = 1; | |
5342 | if (xregno < regno + nregs | |
5343 | && xregno + xnregs > regno) | |
5344 | return 0; | |
5345 | if (xregno < valueno + valuenregs | |
5346 | && xregno + xnregs > valueno) | |
5347 | return 0; | |
5348 | if (goal_mem_addr_varies | |
bfa30b22 RK |
5349 | && reg_overlap_mentioned_for_reload_p (dest, |
5350 | goal)) | |
eab89b90 RK |
5351 | return 0; |
5352 | } | |
5353 | else if (goal_mem && GET_CODE (dest) == MEM | |
5354 | && ! push_operand (dest, GET_MODE (dest))) | |
5355 | return 0; | |
5356 | else if (need_stable_sp | |
5357 | && push_operand (dest, GET_MODE (dest))) | |
5358 | return 0; | |
5359 | } | |
5360 | } | |
5361 | } | |
5362 | ||
5363 | #ifdef AUTO_INC_DEC | |
5364 | /* If this insn auto-increments or auto-decrements | |
5365 | either regno or valueno, return 0 now. | |
5366 | If GOAL is a memory ref and its address is not constant, | |
5367 | and this insn P increments a register used in GOAL, return 0. */ | |
5368 | { | |
5369 | register rtx link; | |
5370 | ||
5371 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
5372 | if (REG_NOTE_KIND (link) == REG_INC | |
5373 | && GET_CODE (XEXP (link, 0)) == REG) | |
5374 | { | |
5375 | register int incno = REGNO (XEXP (link, 0)); | |
5376 | if (incno < regno + nregs && incno >= regno) | |
5377 | return 0; | |
5378 | if (incno < valueno + valuenregs && incno >= valueno) | |
5379 | return 0; | |
5380 | if (goal_mem_addr_varies | |
bfa30b22 RK |
5381 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
5382 | goal)) | |
eab89b90 RK |
5383 | return 0; |
5384 | } | |
5385 | } | |
5386 | #endif | |
5387 | } | |
5388 | } | |
5389 | } | |
5390 | \f | |
5391 | /* Find a place where INCED appears in an increment or decrement operator | |
5392 | within X, and return the amount INCED is incremented or decremented by. | |
5393 | The value is always positive. */ | |
5394 | ||
5395 | static int | |
5396 | find_inc_amount (x, inced) | |
5397 | rtx x, inced; | |
5398 | { | |
5399 | register enum rtx_code code = GET_CODE (x); | |
5400 | register char *fmt; | |
5401 | register int i; | |
5402 | ||
5403 | if (code == MEM) | |
5404 | { | |
5405 | register rtx addr = XEXP (x, 0); | |
5406 | if ((GET_CODE (addr) == PRE_DEC | |
5407 | || GET_CODE (addr) == POST_DEC | |
5408 | || GET_CODE (addr) == PRE_INC | |
5409 | || GET_CODE (addr) == POST_INC) | |
5410 | && XEXP (addr, 0) == inced) | |
5411 | return GET_MODE_SIZE (GET_MODE (x)); | |
5412 | } | |
5413 | ||
5414 | fmt = GET_RTX_FORMAT (code); | |
5415 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5416 | { | |
5417 | if (fmt[i] == 'e') | |
5418 | { | |
5419 | register int tem = find_inc_amount (XEXP (x, i), inced); | |
5420 | if (tem != 0) | |
5421 | return tem; | |
5422 | } | |
5423 | if (fmt[i] == 'E') | |
5424 | { | |
5425 | register int j; | |
5426 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5427 | { | |
5428 | register int tem = find_inc_amount (XVECEXP (x, i, j), inced); | |
5429 | if (tem != 0) | |
5430 | return tem; | |
5431 | } | |
5432 | } | |
5433 | } | |
5434 | ||
5435 | return 0; | |
5436 | } | |
5437 | \f | |
5438 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ | |
5439 | ||
5440 | int | |
5441 | regno_clobbered_p (regno, insn) | |
5442 | int regno; | |
5443 | rtx insn; | |
5444 | { | |
5445 | if (GET_CODE (PATTERN (insn)) == CLOBBER | |
5446 | && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) | |
5447 | return REGNO (XEXP (PATTERN (insn), 0)) == regno; | |
5448 | ||
5449 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
5450 | { | |
5451 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
5452 | ||
5453 | for (; i >= 0; i--) | |
5454 | { | |
5455 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
5456 | if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG | |
5457 | && REGNO (XEXP (elt, 0)) == regno) | |
5458 | return 1; | |
5459 | } | |
5460 | } | |
5461 | ||
5462 | return 0; | |
5463 | } |