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eab89b90 RK |
1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
2 | Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | /* This file contains subroutines used only from the file reload1.c. | |
22 | It knows how to scan one insn for operands and values | |
23 | that need to be copied into registers to make valid code. | |
24 | It also finds other operands and values which are valid | |
25 | but for which equivalent values in registers exist and | |
26 | ought to be used instead. | |
27 | ||
28 | Before processing the first insn of the function, call `init_reload'. | |
29 | ||
30 | To scan an insn, call `find_reloads'. This does two things: | |
31 | 1. sets up tables describing which values must be reloaded | |
32 | for this insn, and what kind of hard regs they must be reloaded into; | |
33 | 2. optionally record the locations where those values appear in | |
34 | the data, so they can be replaced properly later. | |
35 | This is done only if the second arg to `find_reloads' is nonzero. | |
36 | ||
37 | The third arg to `find_reloads' specifies the number of levels | |
38 | of indirect addressing supported by the machine. If it is zero, | |
39 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
40 | is valid even if (REG n) did not get a hard register; if it is two, | |
41 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
42 | hard register, and similarly for higher values. | |
43 | ||
44 | Then you must choose the hard regs to reload those pseudo regs into, | |
45 | and generate appropriate load insns before this insn and perhaps | |
46 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
47 | to contain the REG rtx's for the registers you used. In some | |
48 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
49 | for certain reloads. Then that tells you which register to use, | |
50 | so you do not need to allocate one. But you still do need to add extra | |
51 | instructions to copy the value into and out of that register. | |
52 | ||
53 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
54 | into the locations already recorded. | |
55 | ||
56 | NOTE SIDE EFFECTS: | |
57 | ||
58 | find_reloads can alter the operands of the instruction it is called on. | |
59 | ||
60 | 1. Two operands of any sort may be interchanged, if they are in a | |
61 | commutative instruction. | |
62 | This happens only if find_reloads thinks the instruction will compile | |
63 | better that way. | |
64 | ||
65 | 2. Pseudo-registers that are equivalent to constants are replaced | |
66 | with those constants if they are not in hard registers. | |
67 | ||
68 | 1 happens every time find_reloads is called. | |
69 | 2 happens only when REPLACE is 1, which is only when | |
70 | actually doing the reloads, not when just counting them. | |
71 | ||
72 | ||
73 | Using a reload register for several reloads in one insn: | |
74 | ||
75 | When an insn has reloads, it is considered as having three parts: | |
76 | the input reloads, the insn itself after reloading, and the output reloads. | |
77 | Reloads of values used in memory addresses are often needed for only one part. | |
78 | ||
79 | When this is so, reload_when_needed records which part needs the reload. | |
80 | Two reloads for different parts of the insn can share the same reload | |
81 | register. | |
82 | ||
83 | When a reload is used for addresses in multiple parts, or when it is | |
84 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
85 | a register with any other reload. */ | |
86 | ||
87 | #define REG_OK_STRICT | |
88 | ||
89 | #include "config.h" | |
90 | #include "rtl.h" | |
91 | #include "insn-config.h" | |
92 | #include "insn-codes.h" | |
93 | #include "recog.h" | |
94 | #include "reload.h" | |
95 | #include "regs.h" | |
96 | #include "hard-reg-set.h" | |
97 | #include "flags.h" | |
98 | #include "real.h" | |
99 | ||
100 | #ifndef REGISTER_MOVE_COST | |
101 | #define REGISTER_MOVE_COST(x, y) 2 | |
102 | #endif | |
103 | \f | |
104 | /* The variables set up by `find_reloads' are: | |
105 | ||
106 | n_reloads number of distinct reloads needed; max reload # + 1 | |
107 | tables indexed by reload number | |
108 | reload_in rtx for value to reload from | |
109 | reload_out rtx for where to store reload-reg afterward if nec | |
110 | (often the same as reload_in) | |
111 | reload_reg_class enum reg_class, saying what regs to reload into | |
112 | reload_inmode enum machine_mode; mode this operand should have | |
113 | when reloaded, on input. | |
114 | reload_outmode enum machine_mode; mode this operand should have | |
115 | when reloaded, on output. | |
116 | reload_strict_low char; currently always zero; used to mean that this | |
117 | reload is inside a STRICT_LOW_PART, but we don't | |
118 | need to know this anymore. | |
119 | reload_optional char, nonzero for an optional reload. | |
120 | Optional reloads are ignored unless the | |
121 | value is already sitting in a register. | |
122 | reload_inc int, positive amount to increment or decrement by if | |
123 | reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC. | |
124 | Ignored otherwise (don't assume it is zero). | |
125 | reload_in_reg rtx. A reg for which reload_in is the equivalent. | |
126 | If reload_in is a symbol_ref which came from | |
127 | reg_equiv_constant, then this is the pseudo | |
128 | which has that symbol_ref as equivalent. | |
129 | reload_reg_rtx rtx. This is the register to reload into. | |
130 | If it is zero when `find_reloads' returns, | |
131 | you must find a suitable register in the class | |
132 | specified by reload_reg_class, and store here | |
133 | an rtx for that register with mode from | |
134 | reload_inmode or reload_outmode. | |
135 | reload_nocombine char, nonzero if this reload shouldn't be | |
136 | combined with another reload. | |
137 | reload_needed_for rtx, operand this reload is needed for address of. | |
138 | 0 means it isn't needed for addressing. | |
139 | reload_needed_for_multiple | |
140 | int, 1 if this reload needed for more than one thing. | |
141 | reload_when_needed enum, classifies reload as needed either for | |
142 | addressing an input reload, addressing an output, | |
143 | for addressing a non-reloaded mem ref, | |
144 | or for unspecified purposes (i.e., more than one | |
145 | of the above). | |
146 | reload_secondary_reload int, gives the reload number of a secondary | |
147 | reload, when needed; otherwise -1 | |
148 | reload_secondary_p int, 1 if this is a secondary register for one | |
149 | or more reloads. | |
150 | reload_secondary_icode enum insn_code, if a secondary reload is required, | |
151 | gives the INSN_CODE that uses the secondary | |
152 | reload as a scratch register, or CODE_FOR_nothing | |
153 | if the secondary reload register is to be an | |
154 | intermediate register. */ | |
155 | int n_reloads; | |
156 | ||
157 | rtx reload_in[MAX_RELOADS]; | |
158 | rtx reload_out[MAX_RELOADS]; | |
159 | enum reg_class reload_reg_class[MAX_RELOADS]; | |
160 | enum machine_mode reload_inmode[MAX_RELOADS]; | |
161 | enum machine_mode reload_outmode[MAX_RELOADS]; | |
162 | char reload_strict_low[MAX_RELOADS]; | |
163 | rtx reload_reg_rtx[MAX_RELOADS]; | |
164 | char reload_optional[MAX_RELOADS]; | |
165 | int reload_inc[MAX_RELOADS]; | |
166 | rtx reload_in_reg[MAX_RELOADS]; | |
167 | char reload_nocombine[MAX_RELOADS]; | |
168 | int reload_needed_for_multiple[MAX_RELOADS]; | |
169 | rtx reload_needed_for[MAX_RELOADS]; | |
170 | enum reload_when_needed reload_when_needed[MAX_RELOADS]; | |
171 | int reload_secondary_reload[MAX_RELOADS]; | |
172 | int reload_secondary_p[MAX_RELOADS]; | |
173 | enum insn_code reload_secondary_icode[MAX_RELOADS]; | |
174 | ||
175 | /* All the "earlyclobber" operands of the current insn | |
176 | are recorded here. */ | |
177 | int n_earlyclobbers; | |
178 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
179 | ||
180 | /* Replacing reloads. | |
181 | ||
182 | If `replace_reloads' is nonzero, then as each reload is recorded | |
183 | an entry is made for it in the table `replacements'. | |
184 | Then later `subst_reloads' can look through that table and | |
185 | perform all the replacements needed. */ | |
186 | ||
187 | /* Nonzero means record the places to replace. */ | |
188 | static int replace_reloads; | |
189 | ||
190 | /* Each replacement is recorded with a structure like this. */ | |
191 | struct replacement | |
192 | { | |
193 | rtx *where; /* Location to store in */ | |
194 | rtx *subreg_loc; /* Location of SUBREG if WHERE is inside | |
195 | a SUBREG; 0 otherwise. */ | |
196 | int what; /* which reload this is for */ | |
197 | enum machine_mode mode; /* mode it must have */ | |
198 | }; | |
199 | ||
200 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
201 | ||
202 | /* Number of replacements currently recorded. */ | |
203 | static int n_replacements; | |
204 | ||
205 | /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable; | |
206 | (see reg_equiv_address). */ | |
207 | static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
208 | static int n_memlocs; | |
209 | ||
0dadecf6 RK |
210 | #ifdef SECONDARY_MEMORY_NEEDED |
211 | ||
212 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
213 | is used per mode, but normally only one or two modes are ever used. | |
214 | ||
215 | We keep two versions, before and after register elimination. */ | |
216 | ||
217 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
218 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES]; | |
219 | #endif | |
220 | ||
eab89b90 RK |
221 | /* The instruction we are doing reloads for; |
222 | so we can test whether a register dies in it. */ | |
223 | static rtx this_insn; | |
224 | ||
225 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
226 | static int this_insn_is_asm; | |
227 | ||
228 | /* If hard_regs_live_known is nonzero, | |
229 | we can tell which hard regs are currently live, | |
230 | at least enough to succeed in choosing dummy reloads. */ | |
231 | static int hard_regs_live_known; | |
232 | ||
233 | /* Indexed by hard reg number, | |
234 | element is nonegative if hard reg has been spilled. | |
235 | This vector is passed to `find_reloads' as an argument | |
236 | and is not changed here. */ | |
237 | static short *static_reload_reg_p; | |
238 | ||
239 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
240 | static int subst_reg_equivs_changed; | |
241 | ||
242 | /* On return from push_reload, holds the reload-number for the OUT | |
243 | operand, which can be different for that from the input operand. */ | |
244 | static int output_reloadnum; | |
245 | ||
246 | static int alternative_allows_memconst (); | |
247 | static rtx find_dummy_reload (); | |
248 | static rtx find_reloads_toplev (); | |
249 | static int find_reloads_address (); | |
250 | static int find_reloads_address_1 (); | |
251 | static void find_reloads_address_part (); | |
252 | static int hard_reg_set_here_p (); | |
253 | /* static rtx forget_volatility (); */ | |
254 | static rtx subst_reg_equivs (); | |
255 | static rtx subst_indexed_address (); | |
256 | rtx find_equiv_reg (); | |
257 | static int find_inc_amount (); | |
258 | \f | |
259 | #ifdef HAVE_SECONDARY_RELOADS | |
260 | ||
261 | /* Determine if any secondary reloads are needed for loading (if IN_P is | |
262 | non-zero) or storing (if IN_P is zero) X to or from a reload register of | |
263 | register class RELOAD_CLASS in mode RELOAD_MODE. | |
264 | ||
265 | Return the register class of a secondary reload register, or NO_REGS if | |
266 | none. *PMODE is set to the mode that the register is required in. | |
267 | If the reload register is needed as a scratch register instead of an | |
268 | intermediate register, *PICODE is set to the insn_code of the insn to be | |
269 | used to load or store the primary reload register; otherwise *PICODE | |
270 | is set to CODE_FOR_nothing. | |
271 | ||
272 | In some cases (such as storing MQ into an external memory location on | |
273 | the RT), both an intermediate register and a scratch register. In that | |
274 | case, *PICODE is set to CODE_FOR_nothing, the class for the intermediate | |
275 | register is returned, and the *PTERTIARY_... variables are set to describe | |
276 | the scratch register. */ | |
277 | ||
278 | static enum reg_class | |
279 | find_secondary_reload (x, reload_class, reload_mode, in_p, picode, pmode, | |
280 | ptertiary_class, ptertiary_icode, ptertiary_mode) | |
281 | rtx x; | |
282 | enum reg_class reload_class; | |
283 | enum machine_mode reload_mode; | |
284 | int in_p; | |
285 | enum insn_code *picode; | |
286 | enum machine_mode *pmode; | |
287 | enum reg_class *ptertiary_class; | |
288 | enum insn_code *ptertiary_icode; | |
289 | enum machine_mode *ptertiary_mode; | |
290 | { | |
291 | enum reg_class class = NO_REGS; | |
292 | enum machine_mode mode = reload_mode; | |
293 | enum insn_code icode = CODE_FOR_nothing; | |
294 | enum reg_class t_class = NO_REGS; | |
295 | enum machine_mode t_mode = VOIDmode; | |
296 | enum insn_code t_icode = CODE_FOR_nothing; | |
297 | ||
d45cf215 RS |
298 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
299 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
300 | but we don't want to assume that), use that equivalent when seeing if | |
301 | a secondary reload is needed since whether or not a reload is needed | |
302 | might be sensitive to the form of the MEM. */ | |
303 | ||
304 | if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
305 | && reg_equiv_mem[REGNO (x)] != 0) | |
306 | x = reg_equiv_mem[REGNO (x)]; | |
307 | ||
eab89b90 RK |
308 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
309 | if (in_p) | |
310 | class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
311 | #endif | |
312 | ||
313 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
314 | if (! in_p) | |
315 | class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
316 | #endif | |
317 | ||
318 | /* If we don't need any secondary registers, go away; the rest of the | |
319 | values won't be used. */ | |
320 | if (class == NO_REGS) | |
321 | return NO_REGS; | |
322 | ||
323 | /* Get a possible insn to use. If the predicate doesn't accept X, don't | |
324 | use the insn. */ | |
325 | ||
326 | icode = (in_p ? reload_in_optab[(int) reload_mode] | |
327 | : reload_out_optab[(int) reload_mode]); | |
328 | ||
329 | if (icode != CODE_FOR_nothing | |
330 | && insn_operand_predicate[(int) icode][in_p] | |
331 | && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode))) | |
332 | icode = CODE_FOR_nothing; | |
333 | ||
334 | /* If we will be using an insn, see if it can directly handle the reload | |
335 | register we will be using. If it can, the secondary reload is for a | |
336 | scratch register. If it can't, we will use the secondary reload for | |
337 | an intermediate register and require a tertiary reload for the scratch | |
338 | register. */ | |
339 | ||
340 | if (icode != CODE_FOR_nothing) | |
341 | { | |
342 | /* If IN_P is non-zero, the reload register will be the output in | |
343 | operand 0. If IN_P is zero, the reload register will be the input | |
344 | in operand 1. Outputs should have an initial "=", which we must | |
345 | skip. */ | |
346 | ||
d45cf215 | 347 | char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p]; |
eab89b90 | 348 | enum reg_class insn_class |
d45cf215 RS |
349 | = (insn_letter == 'r' ? GENERAL_REGS |
350 | : REG_CLASS_FROM_LETTER (insn_letter)); | |
eab89b90 RK |
351 | |
352 | if (insn_class == NO_REGS | |
353 | || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=') | |
354 | /* The scratch register's constraint must start with "=&". */ | |
355 | || insn_operand_constraint[(int) icode][2][0] != '=' | |
356 | || insn_operand_constraint[(int) icode][2][1] != '&') | |
357 | abort (); | |
358 | ||
359 | if (reg_class_subset_p (reload_class, insn_class)) | |
360 | mode = insn_operand_mode[(int) icode][2]; | |
361 | else | |
362 | { | |
d45cf215 | 363 | char t_letter = insn_operand_constraint[(int) icode][2][2]; |
eab89b90 RK |
364 | class = insn_class; |
365 | t_mode = insn_operand_mode[(int) icode][2]; | |
d45cf215 RS |
366 | t_class = (t_letter == 'r' ? GENERAL_REGS |
367 | : REG_CLASS_FROM_LETTER (t_letter)); | |
eab89b90 RK |
368 | t_icode = icode; |
369 | icode = CODE_FOR_nothing; | |
370 | } | |
371 | } | |
372 | ||
373 | *pmode = mode; | |
374 | *picode = icode; | |
375 | *ptertiary_class = t_class; | |
376 | *ptertiary_mode = t_mode; | |
377 | *ptertiary_icode = t_icode; | |
378 | ||
379 | return class; | |
380 | } | |
381 | #endif /* HAVE_SECONDARY_RELOADS */ | |
382 | \f | |
0dadecf6 RK |
383 | #ifdef SECONDARY_MEMORY_NEEDED |
384 | ||
385 | /* Return a memory location that will be used to copy X in mode MODE. | |
386 | If we haven't already made a location for this mode in this insn, | |
387 | call find_reloads_address on the location being returned. */ | |
388 | ||
389 | rtx | |
390 | get_secondary_mem (x, mode) | |
391 | rtx x; | |
392 | enum machine_mode mode; | |
393 | { | |
394 | rtx loc; | |
395 | int mem_valid; | |
396 | ||
397 | /* If MODE is narrower than a word, widen it. This is required because | |
398 | most machines that require these memory locations do not support | |
399 | short load and stores from all registers (e.g., FP registers). We could | |
400 | possibly conditionalize this, but we lose nothing by doing the wider | |
401 | mode. */ | |
402 | ||
403 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD) | |
404 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); | |
405 | ||
406 | /* If we already have made a MEM for this insn, return it. */ | |
407 | if (secondary_memlocs_elim[(int) mode] != 0) | |
408 | return secondary_memlocs_elim[(int) mode]; | |
409 | ||
410 | /* If this is the first time we've tried to get a MEM for this mode, | |
411 | allocate a new one. `something_changed' in reload will get set | |
412 | by noticing that the frame size has changed. */ | |
413 | ||
414 | if (secondary_memlocs[(int) mode] == 0) | |
415 | secondary_memlocs[(int) mode] | |
416 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
417 | ||
418 | /* Get a version of the address doing any eliminations needed. If that | |
419 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
420 | ||
421 | loc = eliminate_regs (secondary_memlocs[(int) mode], 0, NULL_RTX); | |
422 | mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); | |
423 | ||
424 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
425 | loc = copy_rtx (loc); | |
426 | ||
427 | /* The only time the call below will do anything is if the stack | |
428 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
429 | can just pass a zero. */ | |
430 | if (! mem_valid) | |
431 | find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), x, 0); | |
432 | ||
433 | secondary_memlocs_elim[(int) mode] = loc; | |
434 | ||
435 | return loc; | |
436 | } | |
437 | ||
438 | /* Clear any secondary memory locations we've made. */ | |
439 | ||
440 | void | |
441 | clear_secondary_mem () | |
442 | { | |
443 | int i; | |
444 | ||
445 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
446 | secondary_memlocs[i] = 0; | |
447 | } | |
448 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
449 | \f | |
eab89b90 RK |
450 | /* Record one (sometimes two) reload that needs to be performed. |
451 | IN is an rtx saying where the data are to be found before this instruction. | |
452 | OUT says where they must be stored after the instruction. | |
453 | (IN is zero for data not read, and OUT is zero for data not written.) | |
454 | INLOC and OUTLOC point to the places in the instructions where | |
455 | IN and OUT were found. | |
456 | CLASS is a register class required for the reloaded data. | |
457 | INMODE is the machine mode that the instruction requires | |
458 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
459 | ||
460 | If IN is zero, then OUT's location and mode should be passed as | |
461 | INLOC and INMODE. | |
462 | ||
463 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
464 | ||
465 | OPTIONAL nonzero means this reload does not need to be performed: | |
466 | it can be discarded if that is more convenient. | |
467 | ||
468 | The return value is the reload-number for this reload. | |
469 | ||
470 | If both IN and OUT are nonzero, in some rare cases we might | |
471 | want to make two separate reloads. (Actually we never do this now.) | |
472 | Therefore, the reload-number for OUT is stored in | |
473 | output_reloadnum when we return; the return value applies to IN. | |
474 | Usually (presently always), when IN and OUT are nonzero, | |
475 | the two reload-numbers are equal, but the caller should be careful to | |
476 | distinguish them. */ | |
477 | ||
478 | static int | |
479 | push_reload (in, out, inloc, outloc, class, | |
480 | inmode, outmode, strict_low, optional, needed_for) | |
481 | register rtx in, out; | |
482 | rtx *inloc, *outloc; | |
483 | enum reg_class class; | |
484 | enum machine_mode inmode, outmode; | |
485 | int strict_low; | |
486 | int optional; | |
487 | rtx needed_for; | |
488 | { | |
489 | register int i; | |
490 | int dont_share = 0; | |
491 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; | |
492 | int secondary_reload = -1; | |
493 | enum insn_code secondary_icode = CODE_FOR_nothing; | |
494 | ||
495 | /* Compare two RTX's. */ | |
496 | #define MATCHES(x, y) \ | |
497 | (x == y || (x != 0 && (GET_CODE (x) == REG \ | |
498 | ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \ | |
499 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) | |
500 | ||
501 | /* INMODE and/or OUTMODE could be VOIDmode if no mode | |
502 | has been specified for the operand. In that case, | |
503 | use the operand's mode as the mode to reload. */ | |
504 | if (inmode == VOIDmode && in != 0) | |
505 | inmode = GET_MODE (in); | |
506 | if (outmode == VOIDmode && out != 0) | |
507 | outmode = GET_MODE (out); | |
508 | ||
509 | /* If IN is a pseudo register everywhere-equivalent to a constant, and | |
510 | it is not in a hard register, reload straight from the constant, | |
511 | since we want to get rid of such pseudo registers. | |
512 | Often this is done earlier, but not always in find_reloads_address. */ | |
513 | if (in != 0 && GET_CODE (in) == REG) | |
514 | { | |
515 | register int regno = REGNO (in); | |
516 | ||
517 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
518 | && reg_equiv_constant[regno] != 0) | |
519 | in = reg_equiv_constant[regno]; | |
520 | } | |
521 | ||
522 | /* Likewise for OUT. Of course, OUT will never be equivalent to | |
523 | an actual constant, but it might be equivalent to a memory location | |
524 | (in the case of a parameter). */ | |
525 | if (out != 0 && GET_CODE (out) == REG) | |
526 | { | |
527 | register int regno = REGNO (out); | |
528 | ||
529 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
530 | && reg_equiv_constant[regno] != 0) | |
531 | out = reg_equiv_constant[regno]; | |
532 | } | |
533 | ||
534 | /* If we have a read-write operand with an address side-effect, | |
535 | change either IN or OUT so the side-effect happens only once. */ | |
536 | if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out)) | |
537 | { | |
538 | if (GET_CODE (XEXP (in, 0)) == POST_INC | |
539 | || GET_CODE (XEXP (in, 0)) == POST_DEC) | |
540 | in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0)); | |
541 | if (GET_CODE (XEXP (in, 0)) == PRE_INC | |
542 | || GET_CODE (XEXP (in, 0)) == PRE_DEC) | |
543 | out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0)); | |
544 | } | |
545 | ||
546 | /* If we are reloading a (SUBREG (MEM ...) ...) or (SUBREG constant ...), | |
547 | really reload just the inside expression in its own mode. | |
548 | If we have (SUBREG:M1 (REG:M2 ...) ...) with M1 wider than M2 and the | |
549 | register is a pseudo, this will become the same as the above case. | |
550 | Do the same for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where | |
551 | either M1 is not valid for R or M2 is wider than a word but we only | |
552 | need one word to store an M2-sized quantity in R. | |
553 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; | |
554 | we can't handle it here because CONST_INT does not indicate a mode. | |
555 | ||
556 | Similarly, we must reload the inside expression if we have a | |
df62f951 RK |
557 | STRICT_LOW_PART (presumably, in == out in the cas). |
558 | ||
559 | Also reload the inner expression if it does not require a secondary | |
560 | reload but the SUBREG does. */ | |
eab89b90 RK |
561 | |
562 | if (in != 0 && GET_CODE (in) == SUBREG | |
563 | && (GET_CODE (SUBREG_REG (in)) != REG | |
564 | || strict_low | |
565 | || (GET_CODE (SUBREG_REG (in)) == REG | |
566 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER | |
567 | && (GET_MODE_SIZE (inmode) | |
568 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))) | |
569 | || (GET_CODE (SUBREG_REG (in)) == REG | |
570 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
571 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode) | |
572 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD | |
573 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
574 | > UNITS_PER_WORD) | |
575 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
576 | / UNITS_PER_WORD) | |
577 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
df62f951 RK |
578 | GET_MODE (SUBREG_REG (in))))))) |
579 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
580 | || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS | |
581 | && (SECONDARY_INPUT_RELOAD_CLASS (class, | |
582 | GET_MODE (SUBREG_REG (in)), | |
583 | SUBREG_REG (in)) | |
584 | == NO_REGS)) | |
585 | #endif | |
586 | )) | |
eab89b90 RK |
587 | { |
588 | in_subreg_loc = inloc; | |
589 | inloc = &SUBREG_REG (in); | |
590 | in = *inloc; | |
591 | if (GET_CODE (in) == MEM) | |
592 | /* This is supposed to happen only for paradoxical subregs made by | |
593 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
594 | if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode)) | |
595 | abort (); | |
596 | inmode = GET_MODE (in); | |
597 | } | |
598 | ||
599 | /* Similarly for paradoxical and problematical SUBREGs on the output. | |
600 | Note that there is no reason we need worry about the previous value | |
601 | of SUBREG_REG (out); even if wider than out, | |
602 | storing in a subreg is entitled to clobber it all | |
603 | (except in the case of STRICT_LOW_PART, | |
604 | and in that case the constraint should label it input-output.) */ | |
605 | if (out != 0 && GET_CODE (out) == SUBREG | |
606 | && (GET_CODE (SUBREG_REG (out)) != REG | |
607 | || strict_low | |
608 | || (GET_CODE (SUBREG_REG (out)) == REG | |
609 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER | |
610 | && (GET_MODE_SIZE (outmode) | |
611 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))) | |
612 | || (GET_CODE (SUBREG_REG (out)) == REG | |
613 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
614 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)), outmode) | |
615 | || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD | |
616 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
617 | > UNITS_PER_WORD) | |
618 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
619 | / UNITS_PER_WORD) | |
620 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
df62f951 RK |
621 | GET_MODE (SUBREG_REG (out))))))) |
622 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
623 | || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS | |
624 | && (SECONDARY_OUTPUT_RELOAD_CLASS (class, | |
625 | GET_MODE (SUBREG_REG (out)), | |
626 | SUBREG_REG (out)) | |
627 | == NO_REGS)) | |
628 | #endif | |
629 | )) | |
eab89b90 RK |
630 | { |
631 | out_subreg_loc = outloc; | |
632 | outloc = &SUBREG_REG (out); | |
633 | out = *outloc; | |
634 | if (GET_CODE (out) == MEM | |
635 | && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode)) | |
636 | abort (); | |
637 | outmode = GET_MODE (out); | |
638 | } | |
639 | ||
640 | /* That's all we use STRICT_LOW for, so clear it. At some point, | |
641 | we may want to get rid of reload_strict_low. */ | |
642 | strict_low = 0; | |
643 | ||
644 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ | |
645 | if (in != 0 && out != 0 && GET_CODE (out) == MEM | |
646 | && (GET_CODE (in) == REG || GET_CODE (in) == MEM) | |
bfa30b22 | 647 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
eab89b90 RK |
648 | dont_share = 1; |
649 | ||
0dadecf6 RK |
650 | /* If IN is a SUBREG of a hard register, make a new REG. This |
651 | simplifies some of the cases below. */ | |
652 | ||
653 | if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG | |
654 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER) | |
655 | in = gen_rtx (REG, GET_MODE (in), | |
656 | REGNO (SUBREG_REG (in)) + SUBREG_WORD (in)); | |
657 | ||
658 | /* Similarly for OUT. */ | |
659 | if (out != 0 && GET_CODE (out) == SUBREG | |
660 | && GET_CODE (SUBREG_REG (out)) == REG | |
661 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER) | |
662 | out = gen_rtx (REG, GET_MODE (out), | |
663 | REGNO (SUBREG_REG (out)) + SUBREG_WORD (out)); | |
664 | ||
eab89b90 RK |
665 | /* Narrow down the class of register wanted if that is |
666 | desirable on this machine for efficiency. */ | |
667 | if (in != 0) | |
668 | class = PREFERRED_RELOAD_CLASS (in, class); | |
669 | ||
18a53b78 RS |
670 | /* Output reloads may need analagous treatment, different in detail. */ |
671 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS | |
672 | if (out != 0) | |
673 | class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class); | |
674 | #endif | |
675 | ||
eab89b90 RK |
676 | /* Make sure we use a class that can handle the actual pseudo |
677 | inside any subreg. For example, on the 386, QImode regs | |
678 | can appear within SImode subregs. Although GENERAL_REGS | |
679 | can handle SImode, QImode needs a smaller class. */ | |
680 | #ifdef LIMIT_RELOAD_CLASS | |
681 | if (in_subreg_loc) | |
682 | class = LIMIT_RELOAD_CLASS (inmode, class); | |
683 | else if (in != 0 && GET_CODE (in) == SUBREG) | |
684 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); | |
685 | ||
686 | if (out_subreg_loc) | |
687 | class = LIMIT_RELOAD_CLASS (outmode, class); | |
688 | if (out != 0 && GET_CODE (out) == SUBREG) | |
689 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); | |
690 | #endif | |
691 | ||
692 | if (class == NO_REGS) | |
693 | abort (); | |
694 | ||
695 | /* Verify that this class is at least possible for the mode that | |
696 | is specified. */ | |
697 | if (this_insn_is_asm) | |
698 | { | |
699 | enum machine_mode mode; | |
700 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
701 | mode = inmode; | |
702 | else | |
703 | mode = outmode; | |
704 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
705 | if (HARD_REGNO_MODE_OK (i, mode) | |
706 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)) | |
707 | { | |
708 | int nregs = HARD_REGNO_NREGS (i, mode); | |
709 | ||
710 | int j; | |
711 | for (j = 1; j < nregs; j++) | |
712 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j)) | |
713 | break; | |
714 | if (j == nregs) | |
715 | break; | |
716 | } | |
717 | if (i == FIRST_PSEUDO_REGISTER) | |
718 | { | |
719 | error_for_asm (this_insn, "impossible register constraint in `asm'"); | |
720 | class = ALL_REGS; | |
721 | } | |
722 | } | |
723 | ||
724 | /* We can use an existing reload if the class is right | |
725 | and at least one of IN and OUT is a match | |
726 | and the other is at worst neutral. | |
727 | (A zero compared against anything is neutral.) */ | |
728 | for (i = 0; i < n_reloads; i++) | |
729 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
730 | || reg_class_subset_p (reload_reg_class[i], class)) | |
731 | && reload_strict_low[i] == strict_low | |
732 | /* If the existing reload has a register, it must fit our class. */ | |
733 | && (reload_reg_rtx[i] == 0 | |
734 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
735 | true_regnum (reload_reg_rtx[i]))) | |
736 | && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share | |
737 | && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out))) | |
738 | || | |
739 | (out != 0 && MATCHES (reload_out[i], out) | |
740 | && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in))))) | |
741 | break; | |
742 | ||
743 | /* Reloading a plain reg for input can match a reload to postincrement | |
744 | that reg, since the postincrement's value is the right value. | |
745 | Likewise, it can match a preincrement reload, since we regard | |
746 | the preincrementation as happening before any ref in this insn | |
747 | to that register. */ | |
748 | if (i == n_reloads) | |
749 | for (i = 0; i < n_reloads; i++) | |
750 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
751 | || reg_class_subset_p (reload_reg_class[i], class)) | |
752 | /* If the existing reload has a register, it must fit our class. */ | |
753 | && (reload_reg_rtx[i] == 0 | |
754 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
755 | true_regnum (reload_reg_rtx[i]))) | |
756 | && reload_strict_low[i] == strict_low | |
757 | && out == 0 && reload_out[i] == 0 && reload_in[i] != 0 | |
758 | && ((GET_CODE (in) == REG | |
759 | && (GET_CODE (reload_in[i]) == POST_INC | |
760 | || GET_CODE (reload_in[i]) == POST_DEC | |
761 | || GET_CODE (reload_in[i]) == PRE_INC | |
762 | || GET_CODE (reload_in[i]) == PRE_DEC) | |
763 | && MATCHES (XEXP (reload_in[i], 0), in)) | |
764 | || | |
765 | (GET_CODE (reload_in[i]) == REG | |
766 | && (GET_CODE (in) == POST_INC | |
767 | || GET_CODE (in) == POST_DEC | |
768 | || GET_CODE (in) == PRE_INC | |
769 | || GET_CODE (in) == PRE_DEC) | |
770 | && MATCHES (XEXP (in, 0), reload_in[i])))) | |
771 | { | |
772 | /* Make sure reload_in ultimately has the increment, | |
773 | not the plain register. */ | |
774 | if (GET_CODE (in) == REG) | |
775 | in = reload_in[i]; | |
776 | break; | |
777 | } | |
778 | ||
779 | if (i == n_reloads) | |
780 | { | |
781 | #ifdef HAVE_SECONDARY_RELOADS | |
782 | enum reg_class secondary_class = NO_REGS; | |
783 | enum reg_class secondary_out_class = NO_REGS; | |
784 | enum machine_mode secondary_mode = inmode; | |
785 | enum machine_mode secondary_out_mode = outmode; | |
786 | enum insn_code secondary_icode; | |
787 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
788 | enum reg_class tertiary_class = NO_REGS; | |
789 | enum reg_class tertiary_out_class = NO_REGS; | |
790 | enum machine_mode tertiary_mode; | |
791 | enum machine_mode tertiary_out_mode; | |
792 | enum insn_code tertiary_icode; | |
793 | enum insn_code tertiary_out_icode = CODE_FOR_nothing; | |
794 | int tertiary_reload = -1; | |
795 | ||
796 | /* See if we need a secondary reload register to move between | |
797 | CLASS and IN or CLASS and OUT. Get the modes and icodes to | |
798 | use for each of them if so. */ | |
799 | ||
800 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
801 | if (in != 0) | |
802 | secondary_class | |
803 | = find_secondary_reload (in, class, inmode, 1, &secondary_icode, | |
804 | &secondary_mode, &tertiary_class, | |
805 | &tertiary_icode, &tertiary_mode); | |
806 | #endif | |
807 | ||
808 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
809 | if (out != 0 && GET_CODE (out) != SCRATCH) | |
810 | secondary_out_class | |
811 | = find_secondary_reload (out, class, outmode, 0, | |
812 | &secondary_out_icode, &secondary_out_mode, | |
813 | &tertiary_out_class, &tertiary_out_icode, | |
814 | &tertiary_out_mode); | |
815 | #endif | |
816 | ||
817 | /* We can only record one secondary and one tertiary reload. If both | |
818 | IN and OUT need secondary reloads, we can only make an in-out | |
819 | reload if neither need an insn and if the classes are compatible. */ | |
820 | ||
821 | if (secondary_class != NO_REGS && secondary_out_class != NO_REGS | |
822 | && reg_class_subset_p (secondary_out_class, secondary_class)) | |
823 | secondary_class = secondary_out_class; | |
824 | ||
825 | if (secondary_class != NO_REGS && secondary_out_class != NO_REGS | |
826 | && (! reg_class_subset_p (secondary_class, secondary_out_class) | |
827 | || secondary_icode != CODE_FOR_nothing | |
828 | || secondary_out_icode != CODE_FOR_nothing)) | |
829 | { | |
fb3821f7 CH |
830 | push_reload (NULL_RTX, out, NULL_PTR, outloc, class, |
831 | VOIDmode, outmode, strict_low, optional, needed_for); | |
eab89b90 RK |
832 | out = 0; |
833 | outloc = 0; | |
834 | outmode = VOIDmode; | |
835 | } | |
836 | ||
837 | /* If we need a secondary reload for OUT but not IN, copy the | |
838 | information. */ | |
839 | if (secondary_class == NO_REGS && secondary_out_class != NO_REGS) | |
840 | { | |
841 | secondary_class = secondary_out_class; | |
842 | secondary_icode = secondary_out_icode; | |
843 | tertiary_class = tertiary_out_class; | |
844 | tertiary_icode = tertiary_out_icode; | |
845 | tertiary_mode = tertiary_out_mode; | |
846 | } | |
847 | ||
848 | if (secondary_class != NO_REGS) | |
849 | { | |
850 | /* If we need a tertiary reload, see if we have one we can reuse | |
851 | or else make one. */ | |
852 | ||
853 | if (tertiary_class != NO_REGS) | |
854 | { | |
855 | for (tertiary_reload = 0; tertiary_reload < n_reloads; | |
856 | tertiary_reload++) | |
857 | if (reload_secondary_p[tertiary_reload] | |
858 | && (reg_class_subset_p (tertiary_class, | |
859 | reload_reg_class[tertiary_reload]) | |
860 | || reg_class_subset_p (reload_reg_class[tertiary_reload], | |
861 | tertiary_class)) | |
862 | && ((reload_inmode[tertiary_reload] == tertiary_mode) | |
863 | || reload_inmode[tertiary_reload] == VOIDmode) | |
864 | && ((reload_outmode[tertiary_reload] == tertiary_mode) | |
865 | || reload_outmode[tertiary_reload] == VOIDmode) | |
866 | && (reload_secondary_icode[tertiary_reload] | |
867 | == CODE_FOR_nothing)) | |
868 | ||
869 | { | |
870 | if (tertiary_mode != VOIDmode) | |
871 | reload_inmode[tertiary_reload] = tertiary_mode; | |
872 | if (tertiary_out_mode != VOIDmode) | |
873 | reload_outmode[tertiary_reload] = tertiary_mode; | |
874 | if (reg_class_subset_p (tertiary_class, | |
875 | reload_reg_class[tertiary_reload])) | |
876 | reload_reg_class[tertiary_reload] = tertiary_class; | |
877 | if (reload_needed_for[tertiary_reload] != needed_for) | |
878 | reload_needed_for_multiple[tertiary_reload] = 1; | |
879 | reload_optional[tertiary_reload] &= optional; | |
880 | reload_secondary_p[tertiary_reload] = 1; | |
881 | } | |
882 | ||
883 | if (tertiary_reload == n_reloads) | |
884 | { | |
885 | /* We need to make a new tertiary reload for this register | |
886 | class. */ | |
887 | reload_in[tertiary_reload] = reload_out[tertiary_reload] = 0; | |
888 | reload_reg_class[tertiary_reload] = tertiary_class; | |
889 | reload_inmode[tertiary_reload] = tertiary_mode; | |
890 | reload_outmode[tertiary_reload] = tertiary_mode; | |
891 | reload_reg_rtx[tertiary_reload] = 0; | |
892 | reload_optional[tertiary_reload] = optional; | |
893 | reload_inc[tertiary_reload] = 0; | |
894 | reload_strict_low[tertiary_reload] = 0; | |
895 | /* Maybe we could combine these, but it seems too tricky. */ | |
896 | reload_nocombine[tertiary_reload] = 1; | |
897 | reload_in_reg[tertiary_reload] = 0; | |
898 | reload_needed_for[tertiary_reload] = needed_for; | |
899 | reload_needed_for_multiple[tertiary_reload] = 0; | |
900 | reload_secondary_reload[tertiary_reload] = -1; | |
901 | reload_secondary_icode[tertiary_reload] = CODE_FOR_nothing; | |
902 | reload_secondary_p[tertiary_reload] = 1; | |
903 | ||
904 | n_reloads++; | |
905 | i = n_reloads; | |
906 | } | |
907 | } | |
908 | ||
909 | /* See if we can reuse an existing secondary reload. */ | |
910 | for (secondary_reload = 0; secondary_reload < n_reloads; | |
911 | secondary_reload++) | |
912 | if (reload_secondary_p[secondary_reload] | |
913 | && (reg_class_subset_p (secondary_class, | |
914 | reload_reg_class[secondary_reload]) | |
915 | || reg_class_subset_p (reload_reg_class[secondary_reload], | |
916 | secondary_class)) | |
917 | && ((reload_inmode[secondary_reload] == secondary_mode) | |
918 | || reload_inmode[secondary_reload] == VOIDmode) | |
919 | && ((reload_outmode[secondary_reload] == secondary_out_mode) | |
920 | || reload_outmode[secondary_reload] == VOIDmode) | |
921 | && reload_secondary_reload[secondary_reload] == tertiary_reload | |
922 | && reload_secondary_icode[secondary_reload] == tertiary_icode) | |
923 | { | |
924 | if (secondary_mode != VOIDmode) | |
925 | reload_inmode[secondary_reload] = secondary_mode; | |
926 | if (secondary_out_mode != VOIDmode) | |
927 | reload_outmode[secondary_reload] = secondary_out_mode; | |
928 | if (reg_class_subset_p (secondary_class, | |
929 | reload_reg_class[secondary_reload])) | |
930 | reload_reg_class[secondary_reload] = secondary_class; | |
931 | if (reload_needed_for[secondary_reload] != needed_for) | |
932 | reload_needed_for_multiple[secondary_reload] = 1; | |
933 | reload_optional[secondary_reload] &= optional; | |
934 | reload_secondary_p[secondary_reload] = 1; | |
935 | } | |
936 | ||
937 | if (secondary_reload == n_reloads) | |
938 | { | |
939 | /* We need to make a new secondary reload for this register | |
940 | class. */ | |
941 | reload_in[secondary_reload] = reload_out[secondary_reload] = 0; | |
942 | reload_reg_class[secondary_reload] = secondary_class; | |
943 | reload_inmode[secondary_reload] = secondary_mode; | |
944 | reload_outmode[secondary_reload] = secondary_out_mode; | |
945 | reload_reg_rtx[secondary_reload] = 0; | |
946 | reload_optional[secondary_reload] = optional; | |
947 | reload_inc[secondary_reload] = 0; | |
948 | reload_strict_low[secondary_reload] = 0; | |
949 | /* Maybe we could combine these, but it seems too tricky. */ | |
950 | reload_nocombine[secondary_reload] = 1; | |
951 | reload_in_reg[secondary_reload] = 0; | |
952 | reload_needed_for[secondary_reload] = needed_for; | |
953 | reload_needed_for_multiple[secondary_reload] = 0; | |
954 | reload_secondary_reload[secondary_reload] = tertiary_reload; | |
955 | reload_secondary_icode[secondary_reload] = tertiary_icode; | |
956 | reload_secondary_p[secondary_reload] = 1; | |
957 | ||
958 | n_reloads++; | |
959 | i = n_reloads; | |
0dadecf6 RK |
960 | |
961 | #ifdef SECONDARY_MEMORY_NEEDED | |
962 | /* If we need a memory location to copy between the two | |
963 | reload regs, set it up now. */ | |
964 | ||
965 | if (in != 0 && secondary_icode == CODE_FOR_nothing | |
966 | && SECONDARY_MEMORY_NEEDED (secondary_class, class, inmode)) | |
967 | get_secondary_mem (in, inmode); | |
968 | ||
969 | if (out != 0 && secondary_icode == CODE_FOR_nothing | |
970 | && SECONDARY_MEMORY_NEEDED (class, secondary_class, outmode)) | |
971 | get_secondary_mem (out, outmode); | |
972 | #endif | |
eab89b90 RK |
973 | } |
974 | } | |
975 | #endif | |
976 | ||
977 | /* We found no existing reload suitable for re-use. | |
978 | So add an additional reload. */ | |
979 | ||
980 | reload_in[i] = in; | |
981 | reload_out[i] = out; | |
982 | reload_reg_class[i] = class; | |
983 | reload_inmode[i] = inmode; | |
984 | reload_outmode[i] = outmode; | |
985 | reload_reg_rtx[i] = 0; | |
986 | reload_optional[i] = optional; | |
987 | reload_inc[i] = 0; | |
988 | reload_strict_low[i] = strict_low; | |
989 | reload_nocombine[i] = 0; | |
990 | reload_in_reg[i] = inloc ? *inloc : 0; | |
991 | reload_needed_for[i] = needed_for; | |
992 | reload_needed_for_multiple[i] = 0; | |
993 | reload_secondary_reload[i] = secondary_reload; | |
994 | reload_secondary_icode[i] = secondary_icode; | |
995 | reload_secondary_p[i] = 0; | |
996 | ||
997 | n_reloads++; | |
0dadecf6 RK |
998 | |
999 | #ifdef SECONDARY_MEMORY_NEEDED | |
1000 | /* If a memory location is needed for the copy, make one. */ | |
1001 | if (in != 0 && GET_CODE (in) == REG | |
1002 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1003 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), | |
1004 | class, inmode)) | |
1005 | get_secondary_mem (in, inmode); | |
1006 | ||
1007 | if (out != 0 && GET_CODE (out) == REG | |
1008 | && REGNO (out) < FIRST_PSEUDO_REGISTER | |
1009 | && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)), | |
1010 | outmode)) | |
1011 | get_secondary_mem (out, outmode); | |
1012 | #endif | |
eab89b90 RK |
1013 | } |
1014 | else | |
1015 | { | |
1016 | /* We are reusing an existing reload, | |
1017 | but we may have additional information for it. | |
1018 | For example, we may now have both IN and OUT | |
1019 | while the old one may have just one of them. */ | |
1020 | ||
1021 | if (inmode != VOIDmode) | |
1022 | reload_inmode[i] = inmode; | |
1023 | if (outmode != VOIDmode) | |
1024 | reload_outmode[i] = outmode; | |
1025 | if (in != 0) | |
1026 | reload_in[i] = in; | |
1027 | if (out != 0) | |
1028 | reload_out[i] = out; | |
1029 | if (reg_class_subset_p (class, reload_reg_class[i])) | |
1030 | reload_reg_class[i] = class; | |
1031 | reload_optional[i] &= optional; | |
1032 | if (reload_needed_for[i] != needed_for) | |
1033 | reload_needed_for_multiple[i] = 1; | |
1034 | } | |
1035 | ||
1036 | /* If the ostensible rtx being reload differs from the rtx found | |
1037 | in the location to substitute, this reload is not safe to combine | |
1038 | because we cannot reliably tell whether it appears in the insn. */ | |
1039 | ||
1040 | if (in != 0 && in != *inloc) | |
1041 | reload_nocombine[i] = 1; | |
1042 | ||
1043 | #if 0 | |
1044 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1045 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1046 | ||
1047 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1048 | it must be for an autoincrement. It doesn't work to store | |
1049 | the incremented value after the insn because that would clobber the CC. | |
1050 | So we must do the increment of the value reloaded from, | |
1051 | increment it, store it back, then decrement again. */ | |
1052 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1053 | { | |
1054 | out = 0; | |
1055 | reload_out[i] = 0; | |
1056 | reload_inc[i] = find_inc_amount (PATTERN (this_insn), in); | |
1057 | /* If we did not find a nonzero amount-to-increment-by, | |
1058 | that contradicts the belief that IN is being incremented | |
1059 | in an address in this insn. */ | |
1060 | if (reload_inc[i] == 0) | |
1061 | abort (); | |
1062 | } | |
1063 | #endif | |
1064 | ||
1065 | /* If we will replace IN and OUT with the reload-reg, | |
1066 | record where they are located so that substitution need | |
1067 | not do a tree walk. */ | |
1068 | ||
1069 | if (replace_reloads) | |
1070 | { | |
1071 | if (inloc != 0) | |
1072 | { | |
1073 | register struct replacement *r = &replacements[n_replacements++]; | |
1074 | r->what = i; | |
1075 | r->subreg_loc = in_subreg_loc; | |
1076 | r->where = inloc; | |
1077 | r->mode = inmode; | |
1078 | } | |
1079 | if (outloc != 0 && outloc != inloc) | |
1080 | { | |
1081 | register struct replacement *r = &replacements[n_replacements++]; | |
1082 | r->what = i; | |
1083 | r->where = outloc; | |
1084 | r->subreg_loc = out_subreg_loc; | |
1085 | r->mode = outmode; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | /* If this reload is just being introduced and it has both | |
1090 | an incoming quantity and an outgoing quantity that are | |
1091 | supposed to be made to match, see if either one of the two | |
1092 | can serve as the place to reload into. | |
1093 | ||
1094 | If one of them is acceptable, set reload_reg_rtx[i] | |
1095 | to that one. */ | |
1096 | ||
1097 | if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0) | |
1098 | { | |
1099 | reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc, | |
1100 | reload_reg_class[i], i); | |
1101 | ||
1102 | /* If the outgoing register already contains the same value | |
1103 | as the incoming one, we can dispense with loading it. | |
1104 | The easiest way to tell the caller that is to give a phony | |
1105 | value for the incoming operand (same as outgoing one). */ | |
1106 | if (reload_reg_rtx[i] == out | |
1107 | && (GET_CODE (in) == REG || CONSTANT_P (in)) | |
1108 | && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), | |
1109 | static_reload_reg_p, i, inmode)) | |
1110 | reload_in[i] = out; | |
1111 | } | |
1112 | ||
1113 | /* If this is an input reload and the operand contains a register that | |
1114 | dies in this insn and is used nowhere else, see if it is the right class | |
1115 | to be used for this reload. Use it if so. (This occurs most commonly | |
1116 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1117 | this if it is also an output reload that mentions the register unless | |
1118 | the output is a SUBREG that clobbers an entire register. | |
1119 | ||
1120 | Note that the operand might be one of the spill regs, if it is a | |
1121 | pseudo reg and we are in a block where spilling has not taken place. | |
1122 | But if there is no spilling in this block, that is OK. | |
1123 | An explicitly used hard reg cannot be a spill reg. */ | |
1124 | ||
1125 | if (reload_reg_rtx[i] == 0 && in != 0) | |
1126 | { | |
1127 | rtx note; | |
1128 | int regno; | |
1129 | ||
1130 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1131 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1132 | && GET_CODE (XEXP (note, 0)) == REG | |
1133 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER | |
1134 | && reg_mentioned_p (XEXP (note, 0), in) | |
1135 | && ! refers_to_regno_for_reload_p (regno, | |
1136 | (regno | |
1137 | + HARD_REGNO_NREGS (regno, | |
1138 | inmode)), | |
1139 | PATTERN (this_insn), inloc) | |
1140 | && (in != out | |
1141 | || (GET_CODE (in) == SUBREG | |
1142 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1143 | / UNITS_PER_WORD) | |
1144 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1145 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1146 | /* Make sure the operand fits in the reg that dies. */ | |
1147 | && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1148 | && HARD_REGNO_MODE_OK (regno, inmode) | |
1149 | && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1150 | && HARD_REGNO_MODE_OK (regno, outmode) | |
1151 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
1152 | && !fixed_regs[regno]) | |
1153 | { | |
1154 | reload_reg_rtx[i] = gen_rtx (REG, inmode, regno); | |
1155 | break; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | if (out) | |
1160 | output_reloadnum = i; | |
1161 | ||
1162 | return i; | |
1163 | } | |
1164 | ||
1165 | /* Record an additional place we must replace a value | |
1166 | for which we have already recorded a reload. | |
1167 | RELOADNUM is the value returned by push_reload | |
1168 | when the reload was recorded. | |
1169 | This is used in insn patterns that use match_dup. */ | |
1170 | ||
1171 | static void | |
1172 | push_replacement (loc, reloadnum, mode) | |
1173 | rtx *loc; | |
1174 | int reloadnum; | |
1175 | enum machine_mode mode; | |
1176 | { | |
1177 | if (replace_reloads) | |
1178 | { | |
1179 | register struct replacement *r = &replacements[n_replacements++]; | |
1180 | r->what = reloadnum; | |
1181 | r->where = loc; | |
1182 | r->subreg_loc = 0; | |
1183 | r->mode = mode; | |
1184 | } | |
1185 | } | |
1186 | \f | |
1187 | /* If there is only one output reload, and it is not for an earlyclobber | |
1188 | operand, try to combine it with a (logically unrelated) input reload | |
1189 | to reduce the number of reload registers needed. | |
1190 | ||
1191 | This is safe if the input reload does not appear in | |
1192 | the value being output-reloaded, because this implies | |
1193 | it is not needed any more once the original insn completes. | |
1194 | ||
1195 | If that doesn't work, see we can use any of the registers that | |
1196 | die in this insn as a reload register. We can if it is of the right | |
1197 | class and does not appear in the value being output-reloaded. */ | |
1198 | ||
1199 | static void | |
1200 | combine_reloads () | |
1201 | { | |
1202 | int i; | |
1203 | int output_reload = -1; | |
1204 | rtx note; | |
1205 | ||
1206 | /* Find the output reload; return unless there is exactly one | |
1207 | and that one is mandatory. */ | |
1208 | ||
1209 | for (i = 0; i < n_reloads; i++) | |
1210 | if (reload_out[i] != 0) | |
1211 | { | |
1212 | if (output_reload >= 0) | |
1213 | return; | |
1214 | output_reload = i; | |
1215 | } | |
1216 | ||
1217 | if (output_reload < 0 || reload_optional[output_reload]) | |
1218 | return; | |
1219 | ||
1220 | /* An input-output reload isn't combinable. */ | |
1221 | ||
1222 | if (reload_in[output_reload] != 0) | |
1223 | return; | |
1224 | ||
6dc42e49 | 1225 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
eab89b90 RK |
1226 | |
1227 | for (i = 0; i < n_earlyclobbers; i++) | |
1228 | if (reload_out[output_reload] == reload_earlyclobbers[i]) | |
1229 | return; | |
1230 | ||
1231 | /* Check each input reload; can we combine it? */ | |
1232 | ||
1233 | for (i = 0; i < n_reloads; i++) | |
1234 | if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i] | |
1235 | /* Life span of this reload must not extend past main insn. */ | |
1236 | && reload_when_needed[i] != RELOAD_FOR_OUTPUT_RELOAD_ADDRESS | |
1237 | && reload_inmode[i] == reload_outmode[output_reload] | |
1238 | && reload_inc[i] == 0 | |
1239 | && reload_reg_rtx[i] == 0 | |
1240 | && reload_strict_low[i] == 0 | |
1241 | /* Don't combine two reloads with different secondary reloads. */ | |
1242 | && (reload_secondary_reload[i] == reload_secondary_reload[output_reload] | |
1243 | || reload_secondary_reload[i] == -1 | |
1244 | || reload_secondary_reload[output_reload] == -1) | |
1245 | && (reg_class_subset_p (reload_reg_class[i], | |
1246 | reload_reg_class[output_reload]) | |
1247 | || reg_class_subset_p (reload_reg_class[output_reload], | |
1248 | reload_reg_class[i])) | |
1249 | && (MATCHES (reload_in[i], reload_out[output_reload]) | |
1250 | /* Args reversed because the first arg seems to be | |
1251 | the one that we imagine being modified | |
1252 | while the second is the one that might be affected. */ | |
bfa30b22 RK |
1253 | || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload], |
1254 | reload_in[i]) | |
eab89b90 RK |
1255 | /* However, if the input is a register that appears inside |
1256 | the output, then we also can't share. | |
1257 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1258 | If the same reload reg is used for both reg 69 and the | |
1259 | result to be stored in memory, then that result | |
1260 | will clobber the address of the memory ref. */ | |
1261 | && ! (GET_CODE (reload_in[i]) == REG | |
bfa30b22 RK |
1262 | && reg_overlap_mentioned_for_reload_p (reload_in[i], |
1263 | reload_out[output_reload]))))) | |
eab89b90 RK |
1264 | { |
1265 | int j; | |
1266 | ||
1267 | /* We have found a reload to combine with! */ | |
1268 | reload_out[i] = reload_out[output_reload]; | |
1269 | reload_outmode[i] = reload_outmode[output_reload]; | |
1270 | /* Mark the old output reload as inoperative. */ | |
1271 | reload_out[output_reload] = 0; | |
1272 | /* The combined reload is needed for the entire insn. */ | |
1273 | reload_needed_for_multiple[i] = 1; | |
1274 | reload_when_needed[i] = RELOAD_OTHER; | |
1275 | /* If the output reload had a secondary reload, copy it. */ | |
1276 | if (reload_secondary_reload[output_reload] != -1) | |
1277 | reload_secondary_reload[i] = reload_secondary_reload[output_reload]; | |
1278 | /* If required, minimize the register class. */ | |
1279 | if (reg_class_subset_p (reload_reg_class[output_reload], | |
1280 | reload_reg_class[i])) | |
1281 | reload_reg_class[i] = reload_reg_class[output_reload]; | |
1282 | ||
1283 | /* Transfer all replacements from the old reload to the combined. */ | |
1284 | for (j = 0; j < n_replacements; j++) | |
1285 | if (replacements[j].what == output_reload) | |
1286 | replacements[j].what = i; | |
1287 | ||
1288 | return; | |
1289 | } | |
1290 | ||
1291 | /* If this insn has only one operand that is modified or written (assumed | |
1292 | to be the first), it must be the one corresponding to this reload. It | |
1293 | is safe to use anything that dies in this insn for that output provided | |
1294 | that it does not occur in the output (we already know it isn't an | |
1295 | earlyclobber. If this is an asm insn, give up. */ | |
1296 | ||
1297 | if (INSN_CODE (this_insn) == -1) | |
1298 | return; | |
1299 | ||
1300 | for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++) | |
1301 | if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '=' | |
1302 | || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+') | |
1303 | return; | |
1304 | ||
1305 | /* See if some hard register that dies in this insn and is not used in | |
1306 | the output is the right class. Only works if the register we pick | |
1307 | up can fully hold our output reload. */ | |
1308 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1309 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1310 | && GET_CODE (XEXP (note, 0)) == REG | |
bfa30b22 RK |
1311 | && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
1312 | reload_out[output_reload]) | |
eab89b90 RK |
1313 | && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
1314 | && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1315 | && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]], | |
1316 | REGNO (XEXP (note, 0))) | |
1317 | && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1318 | <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0)))) | |
1319 | && ! fixed_regs[REGNO (XEXP (note, 0))]) | |
1320 | { | |
1321 | reload_reg_rtx[output_reload] = gen_rtx (REG, | |
1322 | reload_outmode[output_reload], | |
1323 | REGNO (XEXP (note, 0))); | |
1324 | return; | |
1325 | } | |
1326 | } | |
1327 | \f | |
1328 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1329 | See if one of IN and OUT is a register that may be used; | |
1330 | this is desirable since a spill-register won't be needed. | |
1331 | If so, return the register rtx that proves acceptable. | |
1332 | ||
1333 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
1334 | CLASS is the register class required for the reload. | |
1335 | ||
1336 | If FOR_REAL is >= 0, it is the number of the reload, | |
1337 | and in some cases when it can be discovered that OUT doesn't need | |
1338 | to be computed, clear out reload_out[FOR_REAL]. | |
1339 | ||
1340 | If FOR_REAL is -1, this should not be done, because this call | |
1341 | is just to see if a register can be found, not to find and install it. */ | |
1342 | ||
1343 | static rtx | |
1344 | find_dummy_reload (real_in, real_out, inloc, outloc, class, for_real) | |
1345 | rtx real_in, real_out; | |
1346 | rtx *inloc, *outloc; | |
1347 | enum reg_class class; | |
1348 | int for_real; | |
1349 | { | |
1350 | rtx in = real_in; | |
1351 | rtx out = real_out; | |
1352 | int in_offset = 0; | |
1353 | int out_offset = 0; | |
1354 | rtx value = 0; | |
1355 | ||
1356 | /* If operands exceed a word, we can't use either of them | |
1357 | unless they have the same size. */ | |
1358 | if (GET_MODE_SIZE (GET_MODE (real_out)) != GET_MODE_SIZE (GET_MODE (real_in)) | |
1359 | && (GET_MODE_SIZE (GET_MODE (real_out)) > UNITS_PER_WORD | |
1360 | || GET_MODE_SIZE (GET_MODE (real_in)) > UNITS_PER_WORD)) | |
1361 | return 0; | |
1362 | ||
1363 | /* Find the inside of any subregs. */ | |
1364 | while (GET_CODE (out) == SUBREG) | |
1365 | { | |
1366 | out_offset = SUBREG_WORD (out); | |
1367 | out = SUBREG_REG (out); | |
1368 | } | |
1369 | while (GET_CODE (in) == SUBREG) | |
1370 | { | |
1371 | in_offset = SUBREG_WORD (in); | |
1372 | in = SUBREG_REG (in); | |
1373 | } | |
1374 | ||
1375 | /* Narrow down the reg class, the same way push_reload will; | |
1376 | otherwise we might find a dummy now, but push_reload won't. */ | |
1377 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1378 | ||
1379 | /* See if OUT will do. */ | |
1380 | if (GET_CODE (out) == REG | |
1381 | && REGNO (out) < FIRST_PSEUDO_REGISTER) | |
1382 | { | |
1383 | register int regno = REGNO (out) + out_offset; | |
1384 | int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_out)); | |
d3b9996a | 1385 | rtx saved_rtx; |
eab89b90 RK |
1386 | |
1387 | /* When we consider whether the insn uses OUT, | |
1388 | ignore references within IN. They don't prevent us | |
1389 | from copying IN into OUT, because those refs would | |
1390 | move into the insn that reloads IN. | |
1391 | ||
1392 | However, we only ignore IN in its role as this reload. | |
1393 | If the insn uses IN elsewhere and it contains OUT, | |
1394 | that counts. We can't be sure it's the "same" operand | |
1395 | so it might not go through this reload. */ | |
d3b9996a | 1396 | saved_rtx = *inloc; |
eab89b90 RK |
1397 | *inloc = const0_rtx; |
1398 | ||
1399 | if (regno < FIRST_PSEUDO_REGISTER | |
1400 | /* A fixed reg that can overlap other regs better not be used | |
1401 | for reloading in any way. */ | |
1402 | #ifdef OVERLAPPING_REGNO_P | |
1403 | && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno)) | |
1404 | #endif | |
1405 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1406 | PATTERN (this_insn), outloc)) | |
1407 | { | |
1408 | int i; | |
1409 | for (i = 0; i < nwords; i++) | |
1410 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1411 | regno + i)) | |
1412 | break; | |
1413 | ||
1414 | if (i == nwords) | |
1415 | { | |
1416 | if (GET_CODE (real_out) == REG) | |
1417 | value = real_out; | |
1418 | else | |
1419 | value = gen_rtx (REG, GET_MODE (real_out), regno); | |
1420 | } | |
1421 | } | |
1422 | ||
d3b9996a | 1423 | *inloc = saved_rtx; |
eab89b90 RK |
1424 | } |
1425 | ||
1426 | /* Consider using IN if OUT was not acceptable | |
1427 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
1428 | We can't use IN unless it is dies in this insn, | |
1429 | which means we must know accurately which hard regs are live. | |
1430 | Also, the result can't go in IN if IN is used within OUT. */ | |
1431 | if (hard_regs_live_known | |
1432 | && GET_CODE (in) == REG | |
1433 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1434 | && (value == 0 | |
1435 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
1436 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
1437 | && !fixed_regs[REGNO (in)] | |
1438 | && HARD_REGNO_MODE_OK (REGNO (in), GET_MODE (out))) | |
1439 | { | |
1440 | register int regno = REGNO (in) + in_offset; | |
1441 | int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_in)); | |
1442 | ||
fb3821f7 | 1443 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR) |
eab89b90 RK |
1444 | && ! hard_reg_set_here_p (regno, regno + nwords, |
1445 | PATTERN (this_insn))) | |
1446 | { | |
1447 | int i; | |
1448 | for (i = 0; i < nwords; i++) | |
1449 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1450 | regno + i)) | |
1451 | break; | |
1452 | ||
1453 | if (i == nwords) | |
1454 | { | |
1455 | /* If we were going to use OUT as the reload reg | |
1456 | and changed our mind, it means OUT is a dummy that | |
1457 | dies here. So don't bother copying value to it. */ | |
1458 | if (for_real >= 0 && value == real_out) | |
1459 | reload_out[for_real] = 0; | |
1460 | if (GET_CODE (real_in) == REG) | |
1461 | value = real_in; | |
1462 | else | |
1463 | value = gen_rtx (REG, GET_MODE (real_in), regno); | |
1464 | } | |
1465 | } | |
1466 | } | |
1467 | ||
1468 | return value; | |
1469 | } | |
1470 | \f | |
1471 | /* This page contains subroutines used mainly for determining | |
1472 | whether the IN or an OUT of a reload can serve as the | |
1473 | reload register. */ | |
1474 | ||
1475 | /* Return 1 if expression X alters a hard reg in the range | |
1476 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
1477 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
1478 | X should be the body of an instruction. */ | |
1479 | ||
1480 | static int | |
1481 | hard_reg_set_here_p (beg_regno, end_regno, x) | |
1482 | register int beg_regno, end_regno; | |
1483 | rtx x; | |
1484 | { | |
1485 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
1486 | { | |
1487 | register rtx op0 = SET_DEST (x); | |
1488 | while (GET_CODE (op0) == SUBREG) | |
1489 | op0 = SUBREG_REG (op0); | |
1490 | if (GET_CODE (op0) == REG) | |
1491 | { | |
1492 | register int r = REGNO (op0); | |
1493 | /* See if this reg overlaps range under consideration. */ | |
1494 | if (r < end_regno | |
1495 | && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno) | |
1496 | return 1; | |
1497 | } | |
1498 | } | |
1499 | else if (GET_CODE (x) == PARALLEL) | |
1500 | { | |
1501 | register int i = XVECLEN (x, 0) - 1; | |
1502 | for (; i >= 0; i--) | |
1503 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
1504 | return 1; | |
1505 | } | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | /* Return 1 if ADDR is a valid memory address for mode MODE, | |
1511 | and check that each pseudo reg has the proper kind of | |
1512 | hard reg. */ | |
1513 | ||
1514 | int | |
1515 | strict_memory_address_p (mode, addr) | |
1516 | enum machine_mode mode; | |
1517 | register rtx addr; | |
1518 | { | |
1519 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
1520 | return 0; | |
1521 | ||
1522 | win: | |
1523 | return 1; | |
1524 | } | |
1525 | ||
1526 | \f | |
1527 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
1528 | if they are the same hard reg, and has special hacks for | |
1529 | autoincrement and autodecrement. | |
1530 | This is specifically intended for find_reloads to use | |
1531 | in determining whether two operands match. | |
1532 | X is the operand whose number is the lower of the two. | |
1533 | ||
1534 | The value is 2 if Y contains a pre-increment that matches | |
1535 | a non-incrementing address in X. */ | |
1536 | ||
1537 | /* ??? To be completely correct, we should arrange to pass | |
1538 | for X the output operand and for Y the input operand. | |
1539 | For now, we assume that the output operand has the lower number | |
1540 | because that is natural in (SET output (... input ...)). */ | |
1541 | ||
1542 | int | |
1543 | operands_match_p (x, y) | |
1544 | register rtx x, y; | |
1545 | { | |
1546 | register int i; | |
1547 | register RTX_CODE code = GET_CODE (x); | |
1548 | register char *fmt; | |
1549 | int success_2; | |
1550 | ||
1551 | if (x == y) | |
1552 | return 1; | |
1553 | if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) | |
1554 | && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG | |
1555 | && GET_CODE (SUBREG_REG (y)) == REG))) | |
1556 | { | |
1557 | register int j; | |
1558 | ||
1559 | if (code == SUBREG) | |
1560 | { | |
1561 | i = REGNO (SUBREG_REG (x)); | |
1562 | if (i >= FIRST_PSEUDO_REGISTER) | |
1563 | goto slow; | |
1564 | i += SUBREG_WORD (x); | |
1565 | } | |
1566 | else | |
1567 | i = REGNO (x); | |
1568 | ||
1569 | if (GET_CODE (y) == SUBREG) | |
1570 | { | |
1571 | j = REGNO (SUBREG_REG (y)); | |
1572 | if (j >= FIRST_PSEUDO_REGISTER) | |
1573 | goto slow; | |
1574 | j += SUBREG_WORD (y); | |
1575 | } | |
1576 | else | |
1577 | j = REGNO (y); | |
1578 | ||
1579 | return i == j; | |
1580 | } | |
1581 | /* If two operands must match, because they are really a single | |
1582 | operand of an assembler insn, then two postincrements are invalid | |
1583 | because the assembler insn would increment only once. | |
1584 | On the other hand, an postincrement matches ordinary indexing | |
1585 | if the postincrement is the output operand. */ | |
1586 | if (code == POST_DEC || code == POST_INC) | |
1587 | return operands_match_p (XEXP (x, 0), y); | |
1588 | /* Two preincrements are invalid | |
1589 | because the assembler insn would increment only once. | |
1590 | On the other hand, an preincrement matches ordinary indexing | |
1591 | if the preincrement is the input operand. | |
1592 | In this case, return 2, since some callers need to do special | |
1593 | things when this happens. */ | |
1594 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC) | |
1595 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; | |
1596 | ||
1597 | slow: | |
1598 | ||
1599 | /* Now we have disposed of all the cases | |
1600 | in which different rtx codes can match. */ | |
1601 | if (code != GET_CODE (y)) | |
1602 | return 0; | |
1603 | if (code == LABEL_REF) | |
1604 | return XEXP (x, 0) == XEXP (y, 0); | |
1605 | if (code == SYMBOL_REF) | |
1606 | return XSTR (x, 0) == XSTR (y, 0); | |
1607 | ||
1608 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
1609 | ||
1610 | if (GET_MODE (x) != GET_MODE (y)) | |
1611 | return 0; | |
1612 | ||
1613 | /* Compare the elements. If any pair of corresponding elements | |
1614 | fail to match, return 0 for the whole things. */ | |
1615 | ||
1616 | success_2 = 0; | |
1617 | fmt = GET_RTX_FORMAT (code); | |
1618 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1619 | { | |
1620 | int val; | |
1621 | switch (fmt[i]) | |
1622 | { | |
fb3821f7 CH |
1623 | case 'w': |
1624 | if (XWINT (x, i) != XWINT (y, i)) | |
1625 | return 0; | |
1626 | break; | |
1627 | ||
eab89b90 RK |
1628 | case 'i': |
1629 | if (XINT (x, i) != XINT (y, i)) | |
1630 | return 0; | |
1631 | break; | |
1632 | ||
1633 | case 'e': | |
1634 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
1635 | if (val == 0) | |
1636 | return 0; | |
1637 | /* If any subexpression returns 2, | |
1638 | we should return 2 if we are successful. */ | |
1639 | if (val == 2) | |
1640 | success_2 = 1; | |
1641 | break; | |
1642 | ||
1643 | case '0': | |
1644 | break; | |
1645 | ||
1646 | /* It is believed that rtx's at this level will never | |
1647 | contain anything but integers and other rtx's, | |
1648 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
1649 | default: | |
1650 | abort (); | |
1651 | } | |
1652 | } | |
1653 | return 1 + success_2; | |
1654 | } | |
1655 | \f | |
1656 | /* Return the number of times character C occurs in string S. */ | |
1657 | ||
e4600702 | 1658 | int |
eab89b90 RK |
1659 | n_occurrences (c, s) |
1660 | char c; | |
1661 | char *s; | |
1662 | { | |
1663 | int n = 0; | |
1664 | while (*s) | |
1665 | n += (*s++ == c); | |
1666 | return n; | |
1667 | } | |
1668 | \f | |
1669 | struct decomposition | |
1670 | { | |
1671 | int reg_flag; | |
1672 | int safe; | |
1673 | rtx base; | |
fb3821f7 CH |
1674 | HOST_WIDE_INT start; |
1675 | HOST_WIDE_INT end; | |
eab89b90 RK |
1676 | }; |
1677 | ||
1678 | /* Describe the range of registers or memory referenced by X. | |
1679 | If X is a register, set REG_FLAG and put the first register | |
1680 | number into START and the last plus one into END. | |
1681 | If X is a memory reference, put a base address into BASE | |
1682 | and a range of integer offsets into START and END. | |
1683 | If X is pushing on the stack, we can assume it causes no trouble, | |
1684 | so we set the SAFE field. */ | |
1685 | ||
1686 | static struct decomposition | |
1687 | decompose (x) | |
1688 | rtx x; | |
1689 | { | |
1690 | struct decomposition val; | |
1691 | int all_const = 0; | |
1692 | ||
1693 | val.reg_flag = 0; | |
1694 | val.safe = 0; | |
1695 | if (GET_CODE (x) == MEM) | |
1696 | { | |
1697 | rtx base, offset = 0; | |
1698 | rtx addr = XEXP (x, 0); | |
1699 | ||
1700 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC | |
1701 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
1702 | { | |
1703 | val.base = XEXP (addr, 0); | |
1704 | val.start = - GET_MODE_SIZE (GET_MODE (x)); | |
1705 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
1706 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
1707 | return val; | |
1708 | } | |
1709 | ||
1710 | if (GET_CODE (addr) == CONST) | |
1711 | { | |
1712 | addr = XEXP (addr, 0); | |
1713 | all_const = 1; | |
1714 | } | |
1715 | if (GET_CODE (addr) == PLUS) | |
1716 | { | |
1717 | if (CONSTANT_P (XEXP (addr, 0))) | |
1718 | { | |
1719 | base = XEXP (addr, 1); | |
1720 | offset = XEXP (addr, 0); | |
1721 | } | |
1722 | else if (CONSTANT_P (XEXP (addr, 1))) | |
1723 | { | |
1724 | base = XEXP (addr, 0); | |
1725 | offset = XEXP (addr, 1); | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | if (offset == 0) | |
1730 | { | |
1731 | base = addr; | |
1732 | offset = const0_rtx; | |
1733 | } | |
1734 | if (GET_CODE (offset) == CONST) | |
1735 | offset = XEXP (offset, 0); | |
1736 | if (GET_CODE (offset) == PLUS) | |
1737 | { | |
1738 | if (GET_CODE (XEXP (offset, 0)) == CONST_INT) | |
1739 | { | |
1740 | base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1)); | |
1741 | offset = XEXP (offset, 0); | |
1742 | } | |
1743 | else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) | |
1744 | { | |
1745 | base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0)); | |
1746 | offset = XEXP (offset, 1); | |
1747 | } | |
1748 | else | |
1749 | { | |
1750 | base = gen_rtx (PLUS, GET_MODE (base), base, offset); | |
1751 | offset = const0_rtx; | |
1752 | } | |
1753 | } | |
1754 | else if (GET_CODE (offset) != CONST_INT) | |
1755 | { | |
1756 | base = gen_rtx (PLUS, GET_MODE (base), base, offset); | |
1757 | offset = const0_rtx; | |
1758 | } | |
1759 | ||
1760 | if (all_const && GET_CODE (base) == PLUS) | |
1761 | base = gen_rtx (CONST, GET_MODE (base), base); | |
1762 | ||
1763 | if (GET_CODE (offset) != CONST_INT) | |
1764 | abort (); | |
1765 | ||
1766 | val.start = INTVAL (offset); | |
1767 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
1768 | val.base = base; | |
1769 | return val; | |
1770 | } | |
1771 | else if (GET_CODE (x) == REG) | |
1772 | { | |
1773 | val.reg_flag = 1; | |
1774 | val.start = true_regnum (x); | |
1775 | if (val.start < 0) | |
1776 | { | |
1777 | /* A pseudo with no hard reg. */ | |
1778 | val.start = REGNO (x); | |
1779 | val.end = val.start + 1; | |
1780 | } | |
1781 | else | |
1782 | /* A hard reg. */ | |
1783 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
1784 | } | |
1785 | else if (GET_CODE (x) == SUBREG) | |
1786 | { | |
1787 | if (GET_CODE (SUBREG_REG (x)) != REG) | |
1788 | /* This could be more precise, but it's good enough. */ | |
1789 | return decompose (SUBREG_REG (x)); | |
1790 | val.reg_flag = 1; | |
1791 | val.start = true_regnum (x); | |
1792 | if (val.start < 0) | |
1793 | return decompose (SUBREG_REG (x)); | |
1794 | else | |
1795 | /* A hard reg. */ | |
1796 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
1797 | } | |
1798 | else if (CONSTANT_P (x) | |
1799 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
1800 | || GET_CODE (x) == SCRATCH) | |
1801 | val.safe = 1; | |
1802 | else | |
1803 | abort (); | |
1804 | return val; | |
1805 | } | |
1806 | ||
1807 | /* Return 1 if altering Y will not modify the value of X. | |
1808 | Y is also described by YDATA, which should be decompose (Y). */ | |
1809 | ||
1810 | static int | |
1811 | immune_p (x, y, ydata) | |
1812 | rtx x, y; | |
1813 | struct decomposition ydata; | |
1814 | { | |
1815 | struct decomposition xdata; | |
1816 | ||
1817 | if (ydata.reg_flag) | |
fb3821f7 | 1818 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR); |
eab89b90 RK |
1819 | if (ydata.safe) |
1820 | return 1; | |
1821 | ||
1822 | if (GET_CODE (y) != MEM) | |
1823 | abort (); | |
1824 | /* If Y is memory and X is not, Y can't affect X. */ | |
1825 | if (GET_CODE (x) != MEM) | |
1826 | return 1; | |
1827 | ||
1828 | xdata = decompose (x); | |
1829 | ||
1830 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
1831 | { | |
1832 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
1833 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
1834 | return 1; | |
1835 | /* Constants and stack slots never overlap. */ | |
1836 | if (CONSTANT_P (xdata.base) | |
1837 | && (ydata.base == frame_pointer_rtx | |
1838 | || ydata.base == stack_pointer_rtx)) | |
1839 | return 1; | |
1840 | if (CONSTANT_P (ydata.base) | |
1841 | && (xdata.base == frame_pointer_rtx | |
1842 | || xdata.base == stack_pointer_rtx)) | |
1843 | return 1; | |
1844 | /* If either base is variable, we don't know anything. */ | |
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | ||
1849 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); | |
1850 | } | |
44ace968 | 1851 | |
f72aed24 | 1852 | /* Similar, but calls decompose. */ |
44ace968 JW |
1853 | |
1854 | int | |
1855 | safe_from_earlyclobber (op, clobber) | |
1856 | rtx op, clobber; | |
1857 | { | |
1858 | struct decomposition early_data; | |
1859 | ||
1860 | early_data = decompose (clobber); | |
1861 | return immune_p (op, clobber, early_data); | |
1862 | } | |
eab89b90 RK |
1863 | \f |
1864 | /* Main entry point of this file: search the body of INSN | |
1865 | for values that need reloading and record them with push_reload. | |
1866 | REPLACE nonzero means record also where the values occur | |
1867 | so that subst_reloads can be used. | |
1868 | ||
1869 | IND_LEVELS says how many levels of indirection are supported by this | |
1870 | machine; a value of zero means that a memory reference is not a valid | |
1871 | memory address. | |
1872 | ||
1873 | LIVE_KNOWN says we have valid information about which hard | |
1874 | regs are live at each point in the program; this is true when | |
1875 | we are called from global_alloc but false when stupid register | |
1876 | allocation has been done. | |
1877 | ||
1878 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
1879 | which is nonnegative if the reg has been commandeered for reloading into. | |
1880 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
1881 | by various subroutines. */ | |
1882 | ||
1883 | void | |
1884 | find_reloads (insn, replace, ind_levels, live_known, reload_reg_p) | |
1885 | rtx insn; | |
1886 | int replace, ind_levels; | |
1887 | int live_known; | |
1888 | short *reload_reg_p; | |
1889 | { | |
1890 | rtx non_reloaded_operands[MAX_RECOG_OPERANDS]; | |
1891 | int n_non_reloaded_operands = 0; | |
1892 | #ifdef REGISTER_CONSTRAINTS | |
1893 | ||
1894 | enum reload_modified { RELOAD_NOTHING, RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE }; | |
1895 | ||
1896 | register int insn_code_number; | |
1897 | register int i; | |
1898 | int noperands; | |
1899 | /* These are the constraints for the insn. We don't change them. */ | |
1900 | char *constraints1[MAX_RECOG_OPERANDS]; | |
1901 | /* These start out as the constraints for the insn | |
1902 | and they are chewed up as we consider alternatives. */ | |
1903 | char *constraints[MAX_RECOG_OPERANDS]; | |
1904 | /* These are the preferred classes for an operand, or NO_REGS if it isn't | |
1905 | a register. */ | |
1906 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
1907 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
1908 | /* Nonzero for a MEM operand whose entire address needs a reload. */ | |
1909 | int address_reloaded[MAX_RECOG_OPERANDS]; | |
1910 | int no_input_reloads = 0, no_output_reloads = 0; | |
1911 | int n_alternatives; | |
1912 | int this_alternative[MAX_RECOG_OPERANDS]; | |
1913 | char this_alternative_win[MAX_RECOG_OPERANDS]; | |
1914 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
1915 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
1916 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
1917 | int swapped; | |
1918 | int goal_alternative[MAX_RECOG_OPERANDS]; | |
1919 | int this_alternative_number; | |
1920 | int goal_alternative_number; | |
1921 | int operand_reloadnum[MAX_RECOG_OPERANDS]; | |
1922 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
1923 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
1924 | char goal_alternative_win[MAX_RECOG_OPERANDS]; | |
1925 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
1926 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
1927 | int goal_alternative_swapped; | |
1928 | enum reload_modified modified[MAX_RECOG_OPERANDS]; | |
1929 | int best; | |
1930 | int commutative; | |
1931 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
1932 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
1933 | rtx body = PATTERN (insn); | |
1934 | rtx set = single_set (insn); | |
1935 | int goal_earlyclobber, this_earlyclobber; | |
1936 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | |
1937 | ||
1938 | this_insn = insn; | |
1939 | this_insn_is_asm = 0; /* Tentative. */ | |
1940 | n_reloads = 0; | |
1941 | n_replacements = 0; | |
1942 | n_memlocs = 0; | |
1943 | n_earlyclobbers = 0; | |
1944 | replace_reloads = replace; | |
1945 | hard_regs_live_known = live_known; | |
1946 | static_reload_reg_p = reload_reg_p; | |
1947 | ||
1948 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
1949 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
1950 | to have any input reloads. */ | |
1951 | if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) | |
1952 | no_output_reloads = 1; | |
1953 | ||
1954 | #ifdef HAVE_cc0 | |
1955 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
1956 | no_input_reloads = 1; | |
1957 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
1958 | no_output_reloads = 1; | |
1959 | #endif | |
1960 | ||
0dadecf6 RK |
1961 | #ifdef SECONDARY_MEMORY_NEEDED |
1962 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
1963 | clear them out here. */ | |
1964 | ||
1965 | bzero (secondary_memlocs_elim, sizeof secondary_memlocs_elim); | |
1966 | #endif | |
1967 | ||
eab89b90 RK |
1968 | /* Find what kind of insn this is. NOPERANDS gets number of operands. |
1969 | Make OPERANDS point to a vector of operand values. | |
1970 | Make OPERAND_LOCS point to a vector of pointers to | |
1971 | where the operands were found. | |
1972 | Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the | |
1973 | constraint-strings for this insn. | |
1974 | Return if the insn needs no reload processing. */ | |
1975 | ||
1976 | switch (GET_CODE (body)) | |
1977 | { | |
1978 | case USE: | |
1979 | case CLOBBER: | |
1980 | case ASM_INPUT: | |
1981 | case ADDR_VEC: | |
1982 | case ADDR_DIFF_VEC: | |
1983 | return; | |
1984 | ||
1985 | case SET: | |
1986 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it | |
1987 | is cheap to move between them. If it is not, there may not be an insn | |
1988 | to do the copy, so we may need a reload. */ | |
1989 | if (GET_CODE (SET_DEST (body)) == REG | |
1990 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER | |
1991 | && GET_CODE (SET_SRC (body)) == REG | |
1992 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER | |
1993 | && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))), | |
1994 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) | |
1995 | return; | |
1996 | case PARALLEL: | |
1997 | case ASM_OPERANDS: | |
1998 | noperands = asm_noperands (body); | |
1999 | if (noperands >= 0) | |
2000 | { | |
2001 | /* This insn is an `asm' with operands. */ | |
2002 | ||
2003 | insn_code_number = -1; | |
2004 | this_insn_is_asm = 1; | |
2005 | ||
2006 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
2007 | if (noperands > MAX_RECOG_OPERANDS) | |
2008 | abort (); | |
2009 | ||
2010 | /* Now get the operand values and constraints out of the insn. */ | |
2011 | ||
2012 | decode_asm_operands (body, recog_operand, recog_operand_loc, | |
2013 | constraints, operand_mode); | |
2014 | if (noperands > 0) | |
2015 | { | |
2016 | bcopy (constraints, constraints1, noperands * sizeof (char *)); | |
2017 | n_alternatives = n_occurrences (',', constraints[0]) + 1; | |
2018 | for (i = 1; i < noperands; i++) | |
d45cf215 | 2019 | if (n_alternatives != n_occurrences (',', constraints[i]) + 1) |
eab89b90 RK |
2020 | { |
2021 | error_for_asm (insn, "operand constraints differ in number of alternatives"); | |
2022 | /* Avoid further trouble with this insn. */ | |
2023 | PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); | |
2024 | n_reloads = 0; | |
2025 | return; | |
2026 | } | |
2027 | } | |
2028 | break; | |
2029 | } | |
2030 | ||
2031 | default: | |
2032 | /* Ordinary insn: recognize it, get the operands via insn_extract | |
2033 | and get the constraints. */ | |
2034 | ||
2035 | insn_code_number = recog_memoized (insn); | |
2036 | if (insn_code_number < 0) | |
2037 | fatal_insn_not_found (insn); | |
2038 | ||
2039 | noperands = insn_n_operands[insn_code_number]; | |
2040 | n_alternatives = insn_n_alternatives[insn_code_number]; | |
2041 | /* Just return "no reloads" if insn has no operands with constraints. */ | |
2042 | if (n_alternatives == 0) | |
2043 | return; | |
2044 | insn_extract (insn); | |
2045 | for (i = 0; i < noperands; i++) | |
2046 | { | |
2047 | constraints[i] = constraints1[i] | |
2048 | = insn_operand_constraint[insn_code_number][i]; | |
2049 | operand_mode[i] = insn_operand_mode[insn_code_number][i]; | |
2050 | } | |
2051 | } | |
2052 | ||
2053 | if (noperands == 0) | |
2054 | return; | |
2055 | ||
2056 | commutative = -1; | |
2057 | ||
2058 | /* If we will need to know, later, whether some pair of operands | |
2059 | are the same, we must compare them now and save the result. | |
2060 | Reloading the base and index registers will clobber them | |
2061 | and afterward they will fail to match. */ | |
2062 | ||
2063 | for (i = 0; i < noperands; i++) | |
2064 | { | |
2065 | register char *p; | |
2066 | register int c; | |
2067 | ||
2068 | substed_operand[i] = recog_operand[i]; | |
2069 | p = constraints[i]; | |
2070 | ||
2071 | /* Scan this operand's constraint to see if it should match another. */ | |
2072 | ||
2073 | while (c = *p++) | |
2074 | if (c == '%') | |
2075 | { | |
e53c841d | 2076 | /* The last operand should not be marked commutative. */ |
eab89b90 | 2077 | if (i == noperands - 1) |
e53c841d RS |
2078 | { |
2079 | if (this_insn_is_asm) | |
2080 | warning_for_asm (this_insn, | |
6bcd21bb | 2081 | "`%%' constraint used with last operand"); |
e53c841d RS |
2082 | else |
2083 | abort (); | |
2084 | } | |
2085 | else | |
2086 | commutative = i; | |
eab89b90 RK |
2087 | } |
2088 | else if (c >= '0' && c <= '9') | |
2089 | { | |
2090 | c -= '0'; | |
2091 | operands_match[c][i] | |
2092 | = operands_match_p (recog_operand[c], recog_operand[i]); | |
2093 | /* If C can be commuted with C+1, and C might need to match I, | |
2094 | then C+1 might also need to match I. */ | |
2095 | if (commutative >= 0) | |
2096 | { | |
2097 | if (c == commutative || c == commutative + 1) | |
2098 | { | |
2099 | int other = c + (c == commutative ? 1 : -1); | |
2100 | operands_match[other][i] | |
2101 | = operands_match_p (recog_operand[other], recog_operand[i]); | |
2102 | } | |
2103 | if (i == commutative || i == commutative + 1) | |
2104 | { | |
2105 | int other = i + (i == commutative ? 1 : -1); | |
2106 | operands_match[c][other] | |
2107 | = operands_match_p (recog_operand[c], recog_operand[other]); | |
2108 | } | |
2109 | /* Note that C is supposed to be less than I. | |
2110 | No need to consider altering both C and I | |
2111 | because in that case we would alter one into the other. */ | |
2112 | } | |
2113 | } | |
2114 | } | |
2115 | ||
2116 | /* Examine each operand that is a memory reference or memory address | |
2117 | and reload parts of the addresses into index registers. | |
2118 | While we are at it, initialize the array `modified'. | |
2119 | Also here any references to pseudo regs that didn't get hard regs | |
2120 | but are equivalent to constants get replaced in the insn itself | |
2121 | with those constants. Nobody will ever see them again. | |
2122 | ||
2123 | Finally, set up the preferred classes of each operand. */ | |
2124 | ||
2125 | for (i = 0; i < noperands; i++) | |
2126 | { | |
2127 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
2128 | modified[i] = RELOAD_READ; | |
2129 | address_reloaded[i] = 0; | |
eab89b90 RK |
2130 | |
2131 | if (constraints[i][0] == 'p') | |
2132 | { | |
fb3821f7 | 2133 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 RK |
2134 | recog_operand[i], recog_operand_loc[i], |
2135 | recog_operand[i], ind_levels); | |
2136 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; | |
2137 | } | |
2138 | else if (code == MEM) | |
2139 | { | |
2140 | if (find_reloads_address (GET_MODE (recog_operand[i]), | |
2141 | recog_operand_loc[i], | |
2142 | XEXP (recog_operand[i], 0), | |
2143 | &XEXP (recog_operand[i], 0), | |
2144 | recog_operand[i], ind_levels)) | |
2145 | address_reloaded[i] = 1; | |
2146 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; | |
2147 | } | |
2148 | else if (code == SUBREG) | |
2149 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] | |
2150 | = find_reloads_toplev (recog_operand[i], ind_levels, | |
2151 | set != 0 | |
2152 | && &SET_DEST (set) == recog_operand_loc[i]); | |
2153 | else if (code == REG) | |
2154 | { | |
2155 | /* This is equivalent to calling find_reloads_toplev. | |
2156 | The code is duplicated for speed. | |
2157 | When we find a pseudo always equivalent to a constant, | |
2158 | we replace it by the constant. We must be sure, however, | |
2159 | that we don't try to replace it in the insn in which it | |
2160 | is being set. */ | |
2161 | register int regno = REGNO (recog_operand[i]); | |
2162 | if (reg_equiv_constant[regno] != 0 | |
2163 | && (set == 0 || &SET_DEST (set) != recog_operand_loc[i])) | |
2164 | substed_operand[i] = recog_operand[i] | |
2165 | = reg_equiv_constant[regno]; | |
2166 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
2167 | that feeds this insn. */ | |
2168 | if (reg_equiv_mem[regno] != 0) | |
2169 | substed_operand[i] = recog_operand[i] | |
2170 | = reg_equiv_mem[regno]; | |
2171 | #endif | |
2172 | if (reg_equiv_address[regno] != 0) | |
2173 | { | |
2174 | /* If reg_equiv_address is not a constant address, copy it, | |
2175 | since it may be shared. */ | |
2176 | rtx address = reg_equiv_address[regno]; | |
2177 | ||
2178 | if (rtx_varies_p (address)) | |
2179 | address = copy_rtx (address); | |
2180 | ||
2181 | /* If this is an output operand, we must output a CLOBBER | |
2182 | after INSN so find_equiv_reg knows REGNO is being written. */ | |
2183 | if (constraints[i][0] == '=' | |
2184 | || constraints[i][0] == '+') | |
2185 | emit_insn_after (gen_rtx (CLOBBER, VOIDmode, recog_operand[i]), | |
2186 | insn); | |
2187 | ||
2188 | *recog_operand_loc[i] = recog_operand[i] | |
2189 | = gen_rtx (MEM, GET_MODE (recog_operand[i]), address); | |
2190 | RTX_UNCHANGING_P (recog_operand[i]) | |
2191 | = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
2192 | find_reloads_address (GET_MODE (recog_operand[i]), | |
130659a4 | 2193 | recog_operand_loc[i], |
eab89b90 RK |
2194 | XEXP (recog_operand[i], 0), |
2195 | &XEXP (recog_operand[i], 0), | |
2196 | recog_operand[i], ind_levels); | |
2197 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; | |
2198 | } | |
2199 | } | |
aaf9712e RS |
2200 | /* If the operand is still a register (we didn't replace it with an |
2201 | equivalent), get the preferred class to reload it into. */ | |
2202 | code = GET_CODE (recog_operand[i]); | |
2203 | preferred_class[i] | |
2204 | = ((code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER) | |
2205 | ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS); | |
2206 | pref_or_nothing[i] | |
2207 | = (code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER | |
e4600702 | 2208 | && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS); |
eab89b90 RK |
2209 | } |
2210 | ||
2211 | /* If this is simply a copy from operand 1 to operand 0, merge the | |
2212 | preferred classes for the operands. */ | |
2213 | if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set) | |
2214 | && recog_operand[1] == SET_SRC (set)) | |
2215 | { | |
2216 | preferred_class[0] = preferred_class[1] | |
2217 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2218 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2219 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2220 | } | |
2221 | ||
2222 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2223 | or got the wrong kind of hard reg. For this, we must consider | |
2224 | all the operands together against the register constraints. */ | |
2225 | ||
2226 | best = MAX_RECOG_OPERANDS + 300; | |
2227 | ||
2228 | swapped = 0; | |
2229 | goal_alternative_swapped = 0; | |
2230 | try_swapped: | |
2231 | ||
2232 | /* The constraints are made of several alternatives. | |
2233 | Each operand's constraint looks like foo,bar,... with commas | |
2234 | separating the alternatives. The first alternatives for all | |
2235 | operands go together, the second alternatives go together, etc. | |
2236 | ||
2237 | First loop over alternatives. */ | |
2238 | ||
2239 | for (this_alternative_number = 0; | |
2240 | this_alternative_number < n_alternatives; | |
2241 | this_alternative_number++) | |
2242 | { | |
2243 | /* Loop over operands for one constraint alternative. */ | |
2244 | /* LOSERS counts those that don't fit this alternative | |
2245 | and would require loading. */ | |
2246 | int losers = 0; | |
2247 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2248 | even after reloading. */ | |
2249 | int bad = 0; | |
2250 | /* REJECT is a count of how undesirable this alternative says it is | |
2251 | if any reloading is required. If the alternative matches exactly | |
2252 | then REJECT is ignored, but otherwise it gets this much | |
2253 | counted against it in addition to the reloading needed. Each | |
2254 | ? counts three times here since we want the disparaging caused by | |
2255 | a bad register class to only count 1/3 as much. */ | |
2256 | int reject = 0; | |
2257 | ||
2258 | this_earlyclobber = 0; | |
2259 | ||
2260 | for (i = 0; i < noperands; i++) | |
2261 | { | |
2262 | register char *p = constraints[i]; | |
2263 | register int win = 0; | |
2264 | /* 0 => this operand can be reloaded somehow for this alternative */ | |
2265 | int badop = 1; | |
2266 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2267 | int winreg = 0; | |
2268 | int c; | |
2269 | register rtx operand = recog_operand[i]; | |
2270 | int offset = 0; | |
2271 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2272 | regardless of what the constraint says. */ | |
2273 | int force_reload = 0; | |
2274 | int offmemok = 0; | |
2275 | int earlyclobber = 0; | |
2276 | ||
2277 | /* If the operand is a SUBREG, extract | |
2278 | the REG or MEM (or maybe even a constant) within. | |
2279 | (Constants can occur as a result of reg_equiv_constant.) */ | |
2280 | ||
2281 | while (GET_CODE (operand) == SUBREG) | |
2282 | { | |
2283 | offset += SUBREG_WORD (operand); | |
2284 | operand = SUBREG_REG (operand); | |
2285 | /* Force reload if this is not a register or if there may may | |
2286 | be a problem accessing the register in the outer mode. */ | |
2287 | if (GET_CODE (operand) != REG | |
2288 | #ifdef BYTE_LOADS_ZERO_EXTEND | |
2289 | /* Nonparadoxical subreg of a pseudoreg. | |
2290 | Don't to load the full width if on this machine | |
2291 | we expected the fetch to zero-extend. */ | |
2292 | || ((GET_MODE_SIZE (operand_mode[i]) | |
2293 | > GET_MODE_SIZE (GET_MODE (operand))) | |
2294 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER) | |
2295 | #endif /* BYTE_LOADS_ZERO_EXTEND */ | |
2296 | /* Subreg of a hard reg which can't handle the subreg's mode | |
2297 | or which would handle that mode in the wrong number of | |
2298 | registers for subregging to work. */ | |
2299 | || (REGNO (operand) < FIRST_PSEUDO_REGISTER | |
2300 | && (! HARD_REGNO_MODE_OK (REGNO (operand), | |
2301 | operand_mode[i]) | |
2302 | || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
2303 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2304 | > UNITS_PER_WORD) | |
2305 | && ((GET_MODE_SIZE (GET_MODE (operand)) | |
2306 | / UNITS_PER_WORD) | |
2307 | != HARD_REGNO_NREGS (REGNO (operand), | |
2308 | GET_MODE (operand))))))) | |
2309 | force_reload = 1; | |
2310 | } | |
2311 | ||
2312 | this_alternative[i] = (int) NO_REGS; | |
2313 | this_alternative_win[i] = 0; | |
2314 | this_alternative_offmemok[i] = 0; | |
2315 | this_alternative_earlyclobber[i] = 0; | |
2316 | this_alternative_matches[i] = -1; | |
2317 | ||
2318 | /* An empty constraint or empty alternative | |
2319 | allows anything which matched the pattern. */ | |
2320 | if (*p == 0 || *p == ',') | |
2321 | win = 1, badop = 0; | |
2322 | ||
2323 | /* Scan this alternative's specs for this operand; | |
2324 | set WIN if the operand fits any letter in this alternative. | |
2325 | Otherwise, clear BADOP if this operand could | |
2326 | fit some letter after reloads, | |
2327 | or set WINREG if this operand could fit after reloads | |
2328 | provided the constraint allows some registers. */ | |
2329 | ||
2330 | while (*p && (c = *p++) != ',') | |
2331 | switch (c) | |
2332 | { | |
2333 | case '=': | |
2334 | modified[i] = RELOAD_WRITE; | |
2335 | break; | |
2336 | ||
2337 | case '+': | |
2338 | modified[i] = RELOAD_READ_WRITE; | |
2339 | break; | |
2340 | ||
2341 | case '*': | |
2342 | break; | |
2343 | ||
2344 | case '%': | |
42add480 TW |
2345 | /* The last operand should not be marked commutative. */ |
2346 | if (i != noperands - 1) | |
2347 | commutative = i; | |
eab89b90 RK |
2348 | break; |
2349 | ||
2350 | case '?': | |
2351 | reject += 3; | |
2352 | break; | |
2353 | ||
2354 | case '!': | |
2355 | reject = 300; | |
2356 | break; | |
2357 | ||
2358 | case '#': | |
2359 | /* Ignore rest of this alternative as far as | |
2360 | reloading is concerned. */ | |
2361 | while (*p && *p != ',') p++; | |
2362 | break; | |
2363 | ||
2364 | case '0': | |
2365 | case '1': | |
2366 | case '2': | |
2367 | case '3': | |
2368 | case '4': | |
2369 | c -= '0'; | |
2370 | this_alternative_matches[i] = c; | |
2371 | /* We are supposed to match a previous operand. | |
2372 | If we do, we win if that one did. | |
2373 | If we do not, count both of the operands as losers. | |
2374 | (This is too conservative, since most of the time | |
2375 | only a single reload insn will be needed to make | |
2376 | the two operands win. As a result, this alternative | |
2377 | may be rejected when it is actually desirable.) */ | |
2378 | if ((swapped && (c != commutative || i != commutative + 1)) | |
2379 | /* If we are matching as if two operands were swapped, | |
2380 | also pretend that operands_match had been computed | |
2381 | with swapped. | |
2382 | But if I is the second of those and C is the first, | |
2383 | don't exchange them, because operands_match is valid | |
2384 | only on one side of its diagonal. */ | |
2385 | ? (operands_match | |
2386 | [(c == commutative || c == commutative + 1) | |
2387 | ? 2*commutative + 1 - c : c] | |
2388 | [(i == commutative || i == commutative + 1) | |
2389 | ? 2*commutative + 1 - i : i]) | |
2390 | : operands_match[c][i]) | |
2391 | win = this_alternative_win[c]; | |
2392 | else | |
2393 | { | |
2394 | /* Operands don't match. */ | |
2395 | rtx value; | |
2396 | /* Retroactively mark the operand we had to match | |
2397 | as a loser, if it wasn't already. */ | |
2398 | if (this_alternative_win[c]) | |
2399 | losers++; | |
2400 | this_alternative_win[c] = 0; | |
2401 | if (this_alternative[c] == (int) NO_REGS) | |
2402 | bad = 1; | |
2403 | /* But count the pair only once in the total badness of | |
2404 | this alternative, if the pair can be a dummy reload. */ | |
2405 | value | |
2406 | = find_dummy_reload (recog_operand[i], recog_operand[c], | |
2407 | recog_operand_loc[i], recog_operand_loc[c], | |
2408 | this_alternative[c], -1); | |
2409 | ||
2410 | if (value != 0) | |
2411 | losers--; | |
2412 | } | |
2413 | /* This can be fixed with reloads if the operand | |
2414 | we are supposed to match can be fixed with reloads. */ | |
2415 | badop = 0; | |
2416 | this_alternative[i] = this_alternative[c]; | |
2417 | break; | |
2418 | ||
2419 | case 'p': | |
2420 | /* All necessary reloads for an address_operand | |
2421 | were handled in find_reloads_address. */ | |
2422 | this_alternative[i] = (int) ALL_REGS; | |
2423 | win = 1; | |
2424 | break; | |
2425 | ||
2426 | case 'm': | |
2427 | if (force_reload) | |
2428 | break; | |
2429 | if (GET_CODE (operand) == MEM | |
2430 | || (GET_CODE (operand) == REG | |
2431 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2432 | && reg_renumber[REGNO (operand)] < 0)) | |
2433 | win = 1; | |
2434 | if (CONSTANT_P (operand)) | |
2435 | badop = 0; | |
2436 | break; | |
2437 | ||
2438 | case '<': | |
2439 | if (GET_CODE (operand) == MEM | |
2440 | && ! address_reloaded[i] | |
2441 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
2442 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
2443 | win = 1; | |
2444 | break; | |
2445 | ||
2446 | case '>': | |
2447 | if (GET_CODE (operand) == MEM | |
2448 | && ! address_reloaded[i] | |
2449 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
2450 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
2451 | win = 1; | |
2452 | break; | |
2453 | ||
2454 | /* Memory operand whose address is not offsettable. */ | |
2455 | case 'V': | |
2456 | if (force_reload) | |
2457 | break; | |
2458 | if (GET_CODE (operand) == MEM | |
2459 | && ! (ind_levels ? offsettable_memref_p (operand) | |
2460 | : offsettable_nonstrict_memref_p (operand)) | |
2461 | /* Certain mem addresses will become offsettable | |
2462 | after they themselves are reloaded. This is important; | |
2463 | we don't want our own handling of unoffsettables | |
2464 | to override the handling of reg_equiv_address. */ | |
2465 | && !(GET_CODE (XEXP (operand, 0)) == REG | |
2466 | && (ind_levels == 0 | |
2467 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) | |
2468 | win = 1; | |
2469 | break; | |
2470 | ||
2471 | /* Memory operand whose address is offsettable. */ | |
2472 | case 'o': | |
2473 | if (force_reload) | |
2474 | break; | |
2475 | if ((GET_CODE (operand) == MEM | |
2476 | /* If IND_LEVELS, find_reloads_address won't reload a | |
2477 | pseudo that didn't get a hard reg, so we have to | |
2478 | reject that case. */ | |
2479 | && (ind_levels ? offsettable_memref_p (operand) | |
2480 | : offsettable_nonstrict_memref_p (operand))) | |
2481 | /* Certain mem addresses will become offsettable | |
2482 | after they themselves are reloaded. This is important; | |
2483 | we don't want our own handling of unoffsettables | |
2484 | to override the handling of reg_equiv_address. */ | |
2485 | || (GET_CODE (operand) == MEM | |
2486 | && GET_CODE (XEXP (operand, 0)) == REG | |
2487 | && (ind_levels == 0 | |
2488 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)) | |
2489 | || (GET_CODE (operand) == REG | |
2490 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2491 | && reg_renumber[REGNO (operand)] < 0)) | |
2492 | win = 1; | |
2493 | if (CONSTANT_P (operand) || GET_CODE (operand) == MEM) | |
2494 | badop = 0; | |
2495 | offmemok = 1; | |
2496 | break; | |
2497 | ||
2498 | case '&': | |
2499 | /* Output operand that is stored before the need for the | |
2500 | input operands (and their index registers) is over. */ | |
2501 | earlyclobber = 1, this_earlyclobber = 1; | |
2502 | break; | |
2503 | ||
2504 | case 'E': | |
2505 | /* Match any floating double constant, but only if | |
2506 | we can examine the bits of it reliably. */ | |
2507 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
fb3821f7 | 2508 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
eab89b90 RK |
2509 | && GET_MODE (operand) != VOIDmode && ! flag_pretend_float) |
2510 | break; | |
2511 | if (GET_CODE (operand) == CONST_DOUBLE) | |
2512 | win = 1; | |
2513 | break; | |
2514 | ||
2515 | case 'F': | |
2516 | if (GET_CODE (operand) == CONST_DOUBLE) | |
2517 | win = 1; | |
2518 | break; | |
2519 | ||
2520 | case 'G': | |
2521 | case 'H': | |
2522 | if (GET_CODE (operand) == CONST_DOUBLE | |
2523 | && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c)) | |
2524 | win = 1; | |
2525 | break; | |
2526 | ||
2527 | case 's': | |
2528 | if (GET_CODE (operand) == CONST_INT | |
2529 | || (GET_CODE (operand) == CONST_DOUBLE | |
2530 | && GET_MODE (operand) == VOIDmode)) | |
2531 | break; | |
2532 | case 'i': | |
2533 | if (CONSTANT_P (operand) | |
2534 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2535 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)) | |
2536 | #endif | |
2537 | ) | |
2538 | win = 1; | |
2539 | break; | |
2540 | ||
2541 | case 'n': | |
2542 | if (GET_CODE (operand) == CONST_INT | |
2543 | || (GET_CODE (operand) == CONST_DOUBLE | |
2544 | && GET_MODE (operand) == VOIDmode)) | |
2545 | win = 1; | |
2546 | break; | |
2547 | ||
2548 | case 'I': | |
2549 | case 'J': | |
2550 | case 'K': | |
2551 | case 'L': | |
2552 | case 'M': | |
2553 | case 'N': | |
2554 | case 'O': | |
2555 | case 'P': | |
2556 | if (GET_CODE (operand) == CONST_INT | |
2557 | && CONST_OK_FOR_LETTER_P (INTVAL (operand), c)) | |
2558 | win = 1; | |
2559 | break; | |
2560 | ||
2561 | case 'X': | |
2562 | win = 1; | |
2563 | break; | |
2564 | ||
2565 | case 'g': | |
2566 | if (! force_reload | |
2567 | /* A PLUS is never a valid operand, but reload can make | |
2568 | it from a register when eliminating registers. */ | |
2569 | && GET_CODE (operand) != PLUS | |
2570 | /* A SCRATCH is not a valid operand. */ | |
2571 | && GET_CODE (operand) != SCRATCH | |
2572 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2573 | && (! CONSTANT_P (operand) | |
2574 | || ! flag_pic | |
2575 | || LEGITIMATE_PIC_OPERAND_P (operand)) | |
2576 | #endif | |
2577 | && (GENERAL_REGS == ALL_REGS | |
2578 | || GET_CODE (operand) != REG | |
2579 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2580 | && reg_renumber[REGNO (operand)] < 0))) | |
2581 | win = 1; | |
2582 | /* Drop through into 'r' case */ | |
2583 | ||
2584 | case 'r': | |
2585 | this_alternative[i] | |
2586 | = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; | |
2587 | goto reg; | |
2588 | ||
2589 | #ifdef EXTRA_CONSTRAINT | |
2590 | case 'Q': | |
2591 | case 'R': | |
2592 | case 'S': | |
2593 | case 'T': | |
2594 | case 'U': | |
2595 | if (EXTRA_CONSTRAINT (operand, c)) | |
2596 | win = 1; | |
2597 | break; | |
2598 | #endif | |
2599 | ||
2600 | default: | |
2601 | this_alternative[i] | |
2602 | = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)]; | |
2603 | ||
2604 | reg: | |
2605 | if (GET_MODE (operand) == BLKmode) | |
2606 | break; | |
2607 | winreg = 1; | |
2608 | if (GET_CODE (operand) == REG | |
2609 | && reg_fits_class_p (operand, this_alternative[i], | |
2610 | offset, GET_MODE (recog_operand[i]))) | |
2611 | win = 1; | |
2612 | break; | |
2613 | } | |
2614 | ||
2615 | constraints[i] = p; | |
2616 | ||
2617 | /* If this operand could be handled with a reg, | |
2618 | and some reg is allowed, then this operand can be handled. */ | |
2619 | if (winreg && this_alternative[i] != (int) NO_REGS) | |
2620 | badop = 0; | |
2621 | ||
2622 | /* Record which operands fit this alternative. */ | |
2623 | this_alternative_earlyclobber[i] = earlyclobber; | |
2624 | if (win && ! force_reload) | |
2625 | this_alternative_win[i] = 1; | |
2626 | else | |
2627 | { | |
2628 | this_alternative_offmemok[i] = offmemok; | |
2629 | losers++; | |
2630 | if (badop) | |
2631 | bad = 1; | |
2632 | /* Alternative loses if it has no regs for a reg operand. */ | |
2633 | if (GET_CODE (operand) == REG | |
2634 | && this_alternative[i] == (int) NO_REGS | |
2635 | && this_alternative_matches[i] < 0) | |
2636 | bad = 1; | |
2637 | ||
2638 | /* Alternative loses if it requires a type of reload not | |
2639 | permitted for this insn. We can always reload SCRATCH | |
2640 | and objects with a REG_UNUSED note. */ | |
2641 | if (GET_CODE (operand) != SCRATCH && modified[i] != RELOAD_READ | |
2642 | && no_output_reloads | |
2643 | && ! find_reg_note (insn, REG_UNUSED, operand)) | |
2644 | bad = 1; | |
2645 | else if (modified[i] != RELOAD_WRITE && no_input_reloads) | |
2646 | bad = 1; | |
2647 | ||
2648 | /* We prefer to reload pseudos over reloading other things, | |
2649 | since such reloads may be able to be eliminated later. | |
2650 | If we are reloading a SCRATCH, we won't be generating any | |
2651 | insns, just using a register, so it is also preferred. | |
2652 | So bump REJECT in other cases. */ | |
2653 | if (GET_CODE (operand) != REG && GET_CODE (operand) != SCRATCH) | |
2654 | reject++; | |
2655 | } | |
2656 | ||
2657 | /* If this operand is a pseudo register that didn't get a hard | |
2658 | reg and this alternative accepts some register, see if the | |
2659 | class that we want is a subset of the preferred class for this | |
2660 | register. If not, but it intersects that class, use the | |
2661 | preferred class instead. If it does not intersect the preferred | |
2662 | class, show that usage of this alternative should be discouraged; | |
2663 | it will be discouraged more still if the register is `preferred | |
2664 | or nothing'. We do this because it increases the chance of | |
2665 | reusing our spill register in a later insn and avoiding a pair | |
2666 | of memory stores and loads. | |
2667 | ||
2668 | Don't bother with this if this alternative will accept this | |
2669 | operand. | |
2670 | ||
2671 | Don't do this if the preferred class has only one register | |
2672 | because we might otherwise exhaust the class. */ | |
2673 | ||
2674 | ||
2675 | if (! win && this_alternative[i] != (int) NO_REGS | |
2676 | && reg_class_size[(int) preferred_class[i]] > 1) | |
2677 | { | |
2678 | if (! reg_class_subset_p (this_alternative[i], | |
2679 | preferred_class[i])) | |
2680 | { | |
2681 | /* Since we don't have a way of forming the intersection, | |
2682 | we just do something special if the preferred class | |
2683 | is a subset of the class we have; that's the most | |
2684 | common case anyway. */ | |
2685 | if (reg_class_subset_p (preferred_class[i], | |
2686 | this_alternative[i])) | |
2687 | this_alternative[i] = (int) preferred_class[i]; | |
2688 | else | |
2689 | reject += (1 + pref_or_nothing[i]); | |
2690 | } | |
2691 | } | |
2692 | } | |
2693 | ||
2694 | /* Now see if any output operands that are marked "earlyclobber" | |
2695 | in this alternative conflict with any input operands | |
2696 | or any memory addresses. */ | |
2697 | ||
2698 | for (i = 0; i < noperands; i++) | |
2699 | if (this_alternative_earlyclobber[i] | |
2700 | && this_alternative_win[i]) | |
2701 | { | |
2702 | struct decomposition early_data; | |
2703 | int j; | |
2704 | ||
2705 | early_data = decompose (recog_operand[i]); | |
2706 | ||
2707 | if (modified[i] == RELOAD_READ) | |
2708 | { | |
2709 | if (this_insn_is_asm) | |
2710 | warning_for_asm (this_insn, | |
2711 | "`&' constraint used with input operand"); | |
2712 | else | |
2713 | abort (); | |
2714 | continue; | |
2715 | } | |
2716 | ||
2717 | if (this_alternative[i] == NO_REGS) | |
2718 | { | |
2719 | this_alternative_earlyclobber[i] = 0; | |
2720 | if (this_insn_is_asm) | |
2721 | error_for_asm (this_insn, | |
2722 | "`&' constraint used with no register class"); | |
2723 | else | |
2724 | abort (); | |
2725 | } | |
2726 | ||
2727 | for (j = 0; j < noperands; j++) | |
2728 | /* Is this an input operand or a memory ref? */ | |
2729 | if ((GET_CODE (recog_operand[j]) == MEM | |
2730 | || modified[j] != RELOAD_WRITE) | |
2731 | && j != i | |
2732 | /* Ignore things like match_operator operands. */ | |
2733 | && *constraints1[j] != 0 | |
2734 | /* Don't count an input operand that is constrained to match | |
2735 | the early clobber operand. */ | |
2736 | && ! (this_alternative_matches[j] == i | |
2737 | && rtx_equal_p (recog_operand[i], recog_operand[j])) | |
2738 | /* Is it altered by storing the earlyclobber operand? */ | |
2739 | && !immune_p (recog_operand[j], recog_operand[i], early_data)) | |
2740 | { | |
2741 | /* If the output is in a single-reg class, | |
2742 | it's costly to reload it, so reload the input instead. */ | |
2743 | if (reg_class_size[this_alternative[i]] == 1 | |
2744 | && (GET_CODE (recog_operand[j]) == REG | |
2745 | || GET_CODE (recog_operand[j]) == SUBREG)) | |
2746 | { | |
2747 | losers++; | |
2748 | this_alternative_win[j] = 0; | |
2749 | } | |
2750 | else | |
2751 | break; | |
2752 | } | |
2753 | /* If an earlyclobber operand conflicts with something, | |
2754 | it must be reloaded, so request this and count the cost. */ | |
2755 | if (j != noperands) | |
2756 | { | |
2757 | losers++; | |
2758 | this_alternative_win[i] = 0; | |
2759 | for (j = 0; j < noperands; j++) | |
2760 | if (this_alternative_matches[j] == i | |
2761 | && this_alternative_win[j]) | |
2762 | { | |
2763 | this_alternative_win[j] = 0; | |
2764 | losers++; | |
2765 | } | |
2766 | } | |
2767 | } | |
2768 | ||
2769 | /* If one alternative accepts all the operands, no reload required, | |
2770 | choose that alternative; don't consider the remaining ones. */ | |
2771 | if (losers == 0) | |
2772 | { | |
2773 | /* Unswap these so that they are never swapped at `finish'. */ | |
2774 | if (commutative >= 0) | |
2775 | { | |
2776 | recog_operand[commutative] = substed_operand[commutative]; | |
2777 | recog_operand[commutative + 1] | |
2778 | = substed_operand[commutative + 1]; | |
2779 | } | |
2780 | for (i = 0; i < noperands; i++) | |
2781 | { | |
2782 | goal_alternative_win[i] = 1; | |
2783 | goal_alternative[i] = this_alternative[i]; | |
2784 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
2785 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
2786 | goal_alternative_earlyclobber[i] | |
2787 | = this_alternative_earlyclobber[i]; | |
2788 | } | |
2789 | goal_alternative_number = this_alternative_number; | |
2790 | goal_alternative_swapped = swapped; | |
2791 | goal_earlyclobber = this_earlyclobber; | |
2792 | goto finish; | |
2793 | } | |
2794 | ||
2795 | /* REJECT, set by the ! and ? constraint characters and when a register | |
2796 | would be reloaded into a non-preferred class, discourages the use of | |
2797 | this alternative for a reload goal. REJECT is incremented by three | |
2798 | for each ? and one for each non-preferred class. */ | |
2799 | losers = losers * 3 + reject; | |
2800 | ||
2801 | /* If this alternative can be made to work by reloading, | |
2802 | and it needs less reloading than the others checked so far, | |
2803 | record it as the chosen goal for reloading. */ | |
2804 | if (! bad && best > losers) | |
2805 | { | |
2806 | for (i = 0; i < noperands; i++) | |
2807 | { | |
2808 | goal_alternative[i] = this_alternative[i]; | |
2809 | goal_alternative_win[i] = this_alternative_win[i]; | |
2810 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
2811 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
2812 | goal_alternative_earlyclobber[i] | |
2813 | = this_alternative_earlyclobber[i]; | |
2814 | } | |
2815 | goal_alternative_swapped = swapped; | |
2816 | best = losers; | |
2817 | goal_alternative_number = this_alternative_number; | |
2818 | goal_earlyclobber = this_earlyclobber; | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
2823 | then we need to try each alternative twice, | |
2824 | the second time matching those two operands | |
2825 | as if we had exchanged them. | |
2826 | To do this, really exchange them in operands. | |
2827 | ||
2828 | If we have just tried the alternatives the second time, | |
2829 | return operands to normal and drop through. */ | |
2830 | ||
2831 | if (commutative >= 0) | |
2832 | { | |
2833 | swapped = !swapped; | |
2834 | if (swapped) | |
2835 | { | |
2836 | register enum reg_class tclass; | |
2837 | register int t; | |
2838 | ||
2839 | recog_operand[commutative] = substed_operand[commutative + 1]; | |
2840 | recog_operand[commutative + 1] = substed_operand[commutative]; | |
2841 | ||
2842 | tclass = preferred_class[commutative]; | |
2843 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
2844 | preferred_class[commutative + 1] = tclass; | |
2845 | ||
2846 | t = pref_or_nothing[commutative]; | |
2847 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
2848 | pref_or_nothing[commutative + 1] = t; | |
2849 | ||
2850 | bcopy (constraints1, constraints, noperands * sizeof (char *)); | |
2851 | goto try_swapped; | |
2852 | } | |
2853 | else | |
2854 | { | |
2855 | recog_operand[commutative] = substed_operand[commutative]; | |
2856 | recog_operand[commutative + 1] = substed_operand[commutative + 1]; | |
2857 | } | |
2858 | } | |
2859 | ||
2860 | /* The operands don't meet the constraints. | |
2861 | goal_alternative describes the alternative | |
2862 | that we could reach by reloading the fewest operands. | |
2863 | Reload so as to fit it. */ | |
2864 | ||
2865 | if (best == MAX_RECOG_OPERANDS + 300) | |
2866 | { | |
2867 | /* No alternative works with reloads?? */ | |
2868 | if (insn_code_number >= 0) | |
2869 | abort (); | |
2870 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
2871 | /* Avoid further trouble with this insn. */ | |
2872 | PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); | |
2873 | n_reloads = 0; | |
2874 | return; | |
2875 | } | |
2876 | ||
2877 | /* Jump to `finish' from above if all operands are valid already. | |
2878 | In that case, goal_alternative_win is all 1. */ | |
2879 | finish: | |
2880 | ||
2881 | /* Right now, for any pair of operands I and J that are required to match, | |
2882 | with I < J, | |
2883 | goal_alternative_matches[J] is I. | |
2884 | Set up goal_alternative_matched as the inverse function: | |
2885 | goal_alternative_matched[I] = J. */ | |
2886 | ||
2887 | for (i = 0; i < noperands; i++) | |
2888 | goal_alternative_matched[i] = -1; | |
2889 | ||
2890 | for (i = 0; i < noperands; i++) | |
2891 | if (! goal_alternative_win[i] | |
2892 | && goal_alternative_matches[i] >= 0) | |
2893 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
2894 | ||
2895 | /* If the best alternative is with operands 1 and 2 swapped, | |
2896 | consider them swapped before reporting the reloads. */ | |
2897 | ||
2898 | if (goal_alternative_swapped) | |
2899 | { | |
2900 | register rtx tem; | |
2901 | ||
2902 | tem = substed_operand[commutative]; | |
2903 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
2904 | substed_operand[commutative + 1] = tem; | |
2905 | tem = recog_operand[commutative]; | |
2906 | recog_operand[commutative] = recog_operand[commutative + 1]; | |
2907 | recog_operand[commutative + 1] = tem; | |
2908 | } | |
2909 | ||
2910 | /* Perform whatever substitutions on the operands we are supposed | |
2911 | to make due to commutativity or replacement of registers | |
2912 | with equivalent constants or memory slots. */ | |
2913 | ||
2914 | for (i = 0; i < noperands; i++) | |
2915 | { | |
2916 | *recog_operand_loc[i] = substed_operand[i]; | |
2917 | /* While we are looping on operands, initialize this. */ | |
2918 | operand_reloadnum[i] = -1; | |
2919 | } | |
2920 | ||
2921 | /* Any constants that aren't allowed and can't be reloaded | |
2922 | into registers are here changed into memory references. */ | |
2923 | for (i = 0; i < noperands; i++) | |
2924 | if (! goal_alternative_win[i] | |
2925 | && CONSTANT_P (recog_operand[i]) | |
2926 | && (PREFERRED_RELOAD_CLASS (recog_operand[i], | |
2927 | (enum reg_class) goal_alternative[i]) | |
2928 | == NO_REGS) | |
2929 | && operand_mode[i] != VOIDmode) | |
2930 | { | |
2931 | *recog_operand_loc[i] = recog_operand[i] | |
2932 | = find_reloads_toplev (force_const_mem (operand_mode[i], | |
2933 | recog_operand[i]), | |
2934 | ind_levels, 0); | |
2935 | if (alternative_allows_memconst (constraints1[i], | |
2936 | goal_alternative_number)) | |
2937 | goal_alternative_win[i] = 1; | |
2938 | } | |
2939 | ||
2940 | /* Now record reloads for all the operands that need them. */ | |
2941 | for (i = 0; i < noperands; i++) | |
2942 | if (! goal_alternative_win[i]) | |
2943 | { | |
2944 | /* Operands that match previous ones have already been handled. */ | |
2945 | if (goal_alternative_matches[i] >= 0) | |
2946 | ; | |
2947 | /* Handle an operand with a nonoffsettable address | |
2948 | appearing where an offsettable address will do | |
2949 | by reloading the address into a base register. */ | |
2950 | else if (goal_alternative_matched[i] == -1 | |
2951 | && goal_alternative_offmemok[i] | |
2952 | && GET_CODE (recog_operand[i]) == MEM) | |
2953 | { | |
2954 | operand_reloadnum[i] | |
fb3821f7 CH |
2955 | = push_reload (XEXP (recog_operand[i], 0), NULL_RTX, |
2956 | &XEXP (recog_operand[i], 0), NULL_PTR, | |
eab89b90 | 2957 | BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)), |
fb3821f7 | 2958 | VOIDmode, 0, 0, NULL_RTX); |
eab89b90 RK |
2959 | reload_inc[operand_reloadnum[i]] |
2960 | = GET_MODE_SIZE (GET_MODE (recog_operand[i])); | |
2961 | } | |
2962 | else if (goal_alternative_matched[i] == -1) | |
2963 | operand_reloadnum[i] = | |
2964 | push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
2965 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
2966 | modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0, | |
2967 | modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, | |
2968 | (enum reg_class) goal_alternative[i], | |
2969 | (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]), | |
2970 | (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]), | |
2971 | (insn_code_number < 0 ? 0 | |
2972 | : insn_operand_strict_low[insn_code_number][i]), | |
fb3821f7 | 2973 | 0, NULL_RTX); |
eab89b90 RK |
2974 | /* In a matching pair of operands, one must be input only |
2975 | and the other must be output only. | |
2976 | Pass the input operand as IN and the other as OUT. */ | |
2977 | else if (modified[i] == RELOAD_READ | |
2978 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
2979 | { | |
2980 | operand_reloadnum[i] | |
2981 | = push_reload (recog_operand[i], | |
2982 | recog_operand[goal_alternative_matched[i]], | |
2983 | recog_operand_loc[i], | |
2984 | recog_operand_loc[goal_alternative_matched[i]], | |
2985 | (enum reg_class) goal_alternative[i], | |
2986 | operand_mode[i], | |
2987 | operand_mode[goal_alternative_matched[i]], | |
fb3821f7 | 2988 | 0, 0, NULL_RTX); |
eab89b90 RK |
2989 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
2990 | } | |
2991 | else if (modified[i] == RELOAD_WRITE | |
2992 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
2993 | { | |
2994 | operand_reloadnum[goal_alternative_matched[i]] | |
2995 | = push_reload (recog_operand[goal_alternative_matched[i]], | |
2996 | recog_operand[i], | |
2997 | recog_operand_loc[goal_alternative_matched[i]], | |
2998 | recog_operand_loc[i], | |
2999 | (enum reg_class) goal_alternative[i], | |
3000 | operand_mode[goal_alternative_matched[i]], | |
3001 | operand_mode[i], | |
fb3821f7 | 3002 | 0, 0, NULL_RTX); |
eab89b90 RK |
3003 | operand_reloadnum[i] = output_reloadnum; |
3004 | } | |
3005 | else if (insn_code_number >= 0) | |
3006 | abort (); | |
3007 | else | |
3008 | { | |
3009 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3010 | /* Avoid further trouble with this insn. */ | |
3011 | PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); | |
3012 | n_reloads = 0; | |
3013 | return; | |
3014 | } | |
3015 | } | |
3016 | else if (goal_alternative_matched[i] < 0 | |
3017 | && goal_alternative_matches[i] < 0 | |
3018 | && optimize) | |
3019 | { | |
3020 | rtx operand = recog_operand[i]; | |
3021 | /* For each non-matching operand that's a pseudo-register | |
3022 | that didn't get a hard register, make an optional reload. | |
3023 | This may get done even if the insn needs no reloads otherwise. */ | |
3024 | /* (It would be safe to make an optional reload for a matching pair | |
3025 | of operands, but we don't bother yet.) */ | |
3026 | while (GET_CODE (operand) == SUBREG) | |
3027 | operand = XEXP (operand, 0); | |
3028 | if (GET_CODE (operand) == REG | |
3029 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3030 | && reg_renumber[REGNO (operand)] < 0 | |
3031 | && (enum reg_class) goal_alternative[i] != NO_REGS | |
3032 | /* Don't make optional output reloads for jump insns | |
3033 | (such as aobjeq on the vax). */ | |
3034 | && (modified[i] == RELOAD_READ | |
3035 | || GET_CODE (insn) != JUMP_INSN)) | |
3036 | operand_reloadnum[i] | |
3037 | = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3038 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
3039 | modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0, | |
3040 | modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, | |
3041 | (enum reg_class) goal_alternative[i], | |
3042 | (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]), | |
3043 | (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]), | |
3044 | (insn_code_number < 0 ? 0 | |
3045 | : insn_operand_strict_low[insn_code_number][i]), | |
fb3821f7 | 3046 | 1, NULL_RTX); |
eab89b90 RK |
3047 | /* Make an optional reload for an explicit mem ref. */ |
3048 | else if (GET_CODE (operand) == MEM | |
3049 | && (enum reg_class) goal_alternative[i] != NO_REGS | |
3050 | /* Don't make optional output reloads for jump insns | |
3051 | (such as aobjeq on the vax). */ | |
3052 | && (modified[i] == RELOAD_READ | |
3053 | || GET_CODE (insn) != JUMP_INSN)) | |
3054 | operand_reloadnum[i] | |
3055 | = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3056 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
3057 | modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0, | |
3058 | modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, | |
3059 | (enum reg_class) goal_alternative[i], | |
3060 | (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]), | |
3061 | (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]), | |
3062 | (insn_code_number < 0 ? 0 | |
3063 | : insn_operand_strict_low[insn_code_number][i]), | |
fb3821f7 | 3064 | 1, NULL_RTX); |
eab89b90 RK |
3065 | else |
3066 | non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i]; | |
3067 | } | |
3068 | else if (goal_alternative_matched[i] < 0 | |
3069 | && goal_alternative_matches[i] < 0) | |
3070 | non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i]; | |
3071 | ||
3072 | /* Record the values of the earlyclobber operands for the caller. */ | |
3073 | if (goal_earlyclobber) | |
3074 | for (i = 0; i < noperands; i++) | |
3075 | if (goal_alternative_earlyclobber[i]) | |
3076 | reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i]; | |
3077 | ||
3078 | /* If this insn pattern contains any MATCH_DUP's, make sure that | |
3079 | they will be substituted if the operands they match are substituted. | |
3080 | Also do now any substitutions we already did on the operands. | |
3081 | ||
3082 | Don't do this if we aren't making replacements because we might be | |
3083 | propagating things allocated by frame pointer elimination into places | |
3084 | it doesn't expect. */ | |
3085 | ||
3086 | if (insn_code_number >= 0 && replace) | |
3087 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
3088 | { | |
3089 | int opno = recog_dup_num[i]; | |
3090 | *recog_dup_loc[i] = *recog_operand_loc[opno]; | |
3091 | if (operand_reloadnum[opno] >= 0) | |
3092 | push_replacement (recog_dup_loc[i], operand_reloadnum[opno], | |
3093 | insn_operand_mode[insn_code_number][opno]); | |
3094 | } | |
3095 | ||
3096 | #if 0 | |
3097 | /* This loses because reloading of prior insns can invalidate the equivalence | |
3098 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
3099 | causing this insn to need more reload regs than it needed before. | |
3100 | It may be too late to make the reload regs available. | |
3101 | Now this optimization is done safely in choose_reload_regs. */ | |
3102 | ||
3103 | /* For each reload of a reg into some other class of reg, | |
3104 | search for an existing equivalent reg (same value now) in the right class. | |
3105 | We can use it as long as we don't need to change its contents. */ | |
3106 | for (i = 0; i < n_reloads; i++) | |
3107 | if (reload_reg_rtx[i] == 0 | |
3108 | && reload_in[i] != 0 | |
3109 | && GET_CODE (reload_in[i]) == REG | |
3110 | && reload_out[i] == 0) | |
3111 | { | |
3112 | reload_reg_rtx[i] | |
3113 | = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1, | |
3114 | static_reload_reg_p, 0, reload_inmode[i]); | |
3115 | /* Prevent generation of insn to load the value | |
3116 | because the one we found already has the value. */ | |
3117 | if (reload_reg_rtx[i]) | |
3118 | reload_in[i] = reload_reg_rtx[i]; | |
3119 | } | |
3120 | #endif | |
3121 | ||
3122 | #else /* no REGISTER_CONSTRAINTS */ | |
3123 | int noperands; | |
3124 | int insn_code_number; | |
3125 | int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */ | |
3126 | register int i; | |
3127 | rtx body = PATTERN (insn); | |
3128 | ||
3129 | n_reloads = 0; | |
3130 | n_replacements = 0; | |
3131 | n_earlyclobbers = 0; | |
3132 | replace_reloads = replace; | |
3133 | this_insn = insn; | |
3134 | ||
3135 | /* Find what kind of insn this is. NOPERANDS gets number of operands. | |
3136 | Store the operand values in RECOG_OPERAND and the locations | |
3137 | of the words in the insn that point to them in RECOG_OPERAND_LOC. | |
3138 | Return if the insn needs no reload processing. */ | |
3139 | ||
3140 | switch (GET_CODE (body)) | |
3141 | { | |
3142 | case USE: | |
3143 | case CLOBBER: | |
3144 | case ASM_INPUT: | |
3145 | case ADDR_VEC: | |
3146 | case ADDR_DIFF_VEC: | |
3147 | return; | |
3148 | ||
3149 | case PARALLEL: | |
3150 | case SET: | |
3151 | noperands = asm_noperands (body); | |
3152 | if (noperands >= 0) | |
3153 | { | |
3154 | /* This insn is an `asm' with operands. | |
3155 | First, find out how many operands, and allocate space. */ | |
3156 | ||
3157 | insn_code_number = -1; | |
3158 | /* ??? This is a bug! ??? | |
3159 | Give up and delete this insn if it has too many operands. */ | |
3160 | if (noperands > MAX_RECOG_OPERANDS) | |
3161 | abort (); | |
3162 | ||
3163 | /* Now get the operand values out of the insn. */ | |
3164 | ||
fb3821f7 CH |
3165 | decode_asm_operands (body, recog_operand, recog_operand_loc, |
3166 | NULL_PTR, NULL_PTR); | |
eab89b90 RK |
3167 | break; |
3168 | } | |
3169 | ||
3170 | default: | |
3171 | /* Ordinary insn: recognize it, allocate space for operands and | |
3172 | constraints, and get them out via insn_extract. */ | |
3173 | ||
3174 | insn_code_number = recog_memoized (insn); | |
3175 | noperands = insn_n_operands[insn_code_number]; | |
3176 | insn_extract (insn); | |
3177 | } | |
3178 | ||
3179 | if (noperands == 0) | |
3180 | return; | |
3181 | ||
3182 | for (i = 0; i < noperands; i++) | |
3183 | { | |
3184 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
3185 | int is_set_dest = GET_CODE (body) == SET && (i == 0); | |
3186 | ||
3187 | if (insn_code_number >= 0) | |
3188 | if (insn_operand_address_p[insn_code_number][i]) | |
fb3821f7 | 3189 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 RK |
3190 | recog_operand[i], recog_operand_loc[i], |
3191 | recog_operand[i], ind_levels); | |
3192 | if (code == MEM) | |
3193 | find_reloads_address (GET_MODE (recog_operand[i]), | |
3194 | recog_operand_loc[i], | |
3195 | XEXP (recog_operand[i], 0), | |
3196 | &XEXP (recog_operand[i], 0), | |
3197 | recog_operand[i], ind_levels); | |
3198 | if (code == SUBREG) | |
3199 | recog_operand[i] = *recog_operand_loc[i] | |
3200 | = find_reloads_toplev (recog_operand[i], ind_levels, is_set_dest); | |
3201 | if (code == REG) | |
3202 | { | |
3203 | register int regno = REGNO (recog_operand[i]); | |
3204 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
3205 | recog_operand[i] = *recog_operand_loc[i] | |
3206 | = reg_equiv_constant[regno]; | |
3207 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
3208 | that feeds this insn. */ | |
3209 | if (reg_equiv_mem[regno] != 0) | |
3210 | recog_operand[i] = *recog_operand_loc[i] | |
3211 | = reg_equiv_mem[regno]; | |
3212 | #endif | |
3213 | } | |
3214 | /* All operands are non-reloaded. */ | |
3215 | non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i]; | |
3216 | } | |
3217 | #endif /* no REGISTER_CONSTRAINTS */ | |
3218 | ||
3219 | /* Determine which part of the insn each reload is needed for, | |
3220 | based on which operand the reload is needed for. | |
3221 | Reloads of entire operands are classified as RELOAD_OTHER. | |
3222 | So are reloads for which a unique purpose is not known. */ | |
3223 | ||
3224 | for (i = 0; i < n_reloads; i++) | |
3225 | { | |
3226 | reload_when_needed[i] = RELOAD_OTHER; | |
3227 | ||
3228 | if (reload_needed_for[i] != 0 && ! reload_needed_for_multiple[i]) | |
3229 | { | |
3230 | int j; | |
3231 | int output_address = 0; | |
3232 | int input_address = 0; | |
3233 | int operand_address = 0; | |
3234 | ||
3235 | /* This reload is needed only for the address of something. | |
3236 | Determine whether it is needed for addressing an operand | |
3237 | being reloaded for input, whether it is needed for an | |
3238 | operand being reloaded for output, and whether it is needed | |
3239 | for addressing an operand that won't really be reloaded. | |
3240 | ||
3241 | Note that we know that this reload is needed in only one address, | |
3242 | but we have not yet checked for the case where that same address | |
3243 | is used in both input and output reloads. | |
3244 | The following code detects this case. */ | |
3245 | ||
3246 | for (j = 0; j < n_reloads; j++) | |
3247 | if (reload_needed_for[i] == reload_in[j] | |
3248 | || reload_needed_for[i] == reload_out[j]) | |
3249 | { | |
3250 | if (reload_optional[j]) | |
3251 | operand_address = 1; | |
3252 | else | |
3253 | { | |
3254 | if (reload_needed_for[i] == reload_in[j]) | |
3255 | input_address = 1; | |
3256 | if (reload_needed_for[i] == reload_out[j]) | |
3257 | output_address = 1; | |
3258 | } | |
3259 | } | |
3260 | /* Don't ignore memrefs without optional reloads. */ | |
3261 | for (j = 0; j < n_non_reloaded_operands; j++) | |
3262 | if (reload_needed_for[i] == non_reloaded_operands[j]) | |
3263 | operand_address = 1; | |
3264 | ||
3265 | /* If it is needed for only one of those, record which one. */ | |
3266 | ||
3267 | if (input_address && ! output_address && ! operand_address) | |
3268 | reload_when_needed[i] = RELOAD_FOR_INPUT_RELOAD_ADDRESS; | |
3269 | if (output_address && ! input_address && ! operand_address) | |
3270 | reload_when_needed[i] = RELOAD_FOR_OUTPUT_RELOAD_ADDRESS; | |
3271 | if (operand_address && ! input_address && ! output_address) | |
3272 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
3273 | ||
3274 | /* Indicate those RELOAD_OTHER reloads which, though they have | |
3275 | 0 for reload_output, still cannot overlap an output reload. */ | |
3276 | ||
3277 | if (output_address && reload_when_needed[i] == RELOAD_OTHER) | |
3278 | reload_needed_for_multiple[i] = 1; | |
3279 | } | |
3280 | } | |
3281 | ||
3282 | /* Perhaps an output reload can be combined with another | |
3283 | to reduce needs by one. */ | |
3284 | if (!goal_earlyclobber) | |
3285 | combine_reloads (); | |
3286 | } | |
3287 | ||
3288 | /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT | |
3289 | accepts a memory operand with constant address. */ | |
3290 | ||
3291 | static int | |
3292 | alternative_allows_memconst (constraint, altnum) | |
3293 | char *constraint; | |
3294 | int altnum; | |
3295 | { | |
3296 | register int c; | |
3297 | /* Skip alternatives before the one requested. */ | |
3298 | while (altnum > 0) | |
3299 | { | |
3300 | while (*constraint++ != ','); | |
3301 | altnum--; | |
3302 | } | |
3303 | /* Scan the requested alternative for 'm' or 'o'. | |
3304 | If one of them is present, this alternative accepts memory constants. */ | |
3305 | while ((c = *constraint++) && c != ',' && c != '#') | |
3306 | if (c == 'm' || c == 'o') | |
3307 | return 1; | |
3308 | return 0; | |
3309 | } | |
3310 | \f | |
3311 | /* Scan X for memory references and scan the addresses for reloading. | |
3312 | Also checks for references to "constant" regs that we want to eliminate | |
3313 | and replaces them with the values they stand for. | |
6dc42e49 | 3314 | We may alter X destructively if it contains a reference to such. |
eab89b90 RK |
3315 | If X is just a constant reg, we return the equivalent value |
3316 | instead of X. | |
3317 | ||
3318 | IND_LEVELS says how many levels of indirect addressing this machine | |
3319 | supports. | |
3320 | ||
3321 | IS_SET_DEST is true if X is the destination of a SET, which is not | |
3322 | appropriate to be replaced by a constant. */ | |
3323 | ||
3324 | static rtx | |
3325 | find_reloads_toplev (x, ind_levels, is_set_dest) | |
3326 | rtx x; | |
3327 | int ind_levels; | |
3328 | int is_set_dest; | |
3329 | { | |
3330 | register RTX_CODE code = GET_CODE (x); | |
3331 | ||
3332 | register char *fmt = GET_RTX_FORMAT (code); | |
3333 | register int i; | |
3334 | ||
3335 | if (code == REG) | |
3336 | { | |
3337 | /* This code is duplicated for speed in find_reloads. */ | |
3338 | register int regno = REGNO (x); | |
3339 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
3340 | x = reg_equiv_constant[regno]; | |
3341 | #if 0 | |
3342 | /* This creates (subreg (mem...)) which would cause an unnecessary | |
3343 | reload of the mem. */ | |
3344 | else if (reg_equiv_mem[regno] != 0) | |
3345 | x = reg_equiv_mem[regno]; | |
3346 | #endif | |
3347 | else if (reg_equiv_address[regno] != 0) | |
3348 | { | |
3349 | /* If reg_equiv_address varies, it may be shared, so copy it. */ | |
3350 | rtx addr = reg_equiv_address[regno]; | |
3351 | ||
3352 | if (rtx_varies_p (addr)) | |
3353 | addr = copy_rtx (addr); | |
3354 | ||
3355 | x = gen_rtx (MEM, GET_MODE (x), addr); | |
3356 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
fb3821f7 | 3357 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 RK |
3358 | XEXP (x, 0), |
3359 | &XEXP (x, 0), x, ind_levels); | |
3360 | } | |
3361 | return x; | |
3362 | } | |
3363 | if (code == MEM) | |
3364 | { | |
3365 | rtx tem = x; | |
3366 | find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
3367 | x, ind_levels); | |
3368 | return tem; | |
3369 | } | |
3370 | ||
3371 | if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG) | |
3372 | { | |
3373 | /* Check for SUBREG containing a REG that's equivalent to a constant. | |
3374 | If the constant has a known value, truncate it right now. | |
3375 | Similarly if we are extracting a single-word of a multi-word | |
3376 | constant. If the constant is symbolic, allow it to be substituted | |
3377 | normally. push_reload will strip the subreg later. If the | |
3378 | constant is VOIDmode, abort because we will lose the mode of | |
3379 | the register (this should never happen because one of the cases | |
3380 | above should handle it). */ | |
3381 | ||
3382 | register int regno = REGNO (SUBREG_REG (x)); | |
3383 | rtx tem; | |
3384 | ||
3385 | if (subreg_lowpart_p (x) | |
3386 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
3387 | && reg_equiv_constant[regno] != 0 | |
3388 | && (tem = gen_lowpart_common (GET_MODE (x), | |
3389 | reg_equiv_constant[regno])) != 0) | |
3390 | return tem; | |
3391 | ||
3392 | if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD | |
3393 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
3394 | && reg_equiv_constant[regno] != 0 | |
3395 | && (tem = operand_subword (reg_equiv_constant[regno], | |
3396 | SUBREG_WORD (x), 0, | |
3397 | GET_MODE (SUBREG_REG (x)))) != 0) | |
3398 | return tem; | |
3399 | ||
3400 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
3401 | && reg_equiv_constant[regno] != 0 | |
3402 | && GET_MODE (reg_equiv_constant[regno]) == VOIDmode) | |
3403 | abort (); | |
3404 | ||
3405 | /* If the subreg contains a reg that will be converted to a mem, | |
3406 | convert the subreg to a narrower memref now. | |
3407 | Otherwise, we would get (subreg (mem ...) ...), | |
3408 | which would force reload of the mem. | |
3409 | ||
3410 | We also need to do this if there is an equivalent MEM that is | |
3411 | not offsettable. In that case, alter_subreg would produce an | |
3412 | invalid address on big-endian machines. | |
3413 | ||
3414 | For machines that zero-extend byte loads, we must not reload using | |
3415 | a wider mode if we have a paradoxical SUBREG. find_reloads will | |
3416 | force a reload in that case. So we should not do anything here. */ | |
3417 | ||
3418 | else if (regno >= FIRST_PSEUDO_REGISTER | |
3419 | #ifdef BYTE_LOADS_ZERO_EXTEND | |
3420 | && (GET_MODE_SIZE (GET_MODE (x)) | |
3421 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3422 | #endif | |
3423 | && (reg_equiv_address[regno] != 0 | |
3424 | || (reg_equiv_mem[regno] != 0 | |
3425 | && ! offsettable_memref_p (reg_equiv_mem[regno])))) | |
3426 | { | |
3427 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
3428 | rtx addr = (reg_equiv_address[regno] ? reg_equiv_address[regno] | |
3429 | : XEXP (reg_equiv_mem[regno], 0)); | |
3430 | #if BYTES_BIG_ENDIAN | |
3431 | int size; | |
3432 | size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
3433 | offset += MIN (size, UNITS_PER_WORD); | |
3434 | size = GET_MODE_SIZE (GET_MODE (x)); | |
3435 | offset -= MIN (size, UNITS_PER_WORD); | |
3436 | #endif | |
3437 | addr = plus_constant (addr, offset); | |
3438 | x = gen_rtx (MEM, GET_MODE (x), addr); | |
3439 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
fb3821f7 | 3440 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 RK |
3441 | XEXP (x, 0), |
3442 | &XEXP (x, 0), x, ind_levels); | |
3443 | } | |
3444 | ||
3445 | } | |
3446 | ||
3447 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3448 | { | |
3449 | if (fmt[i] == 'e') | |
3450 | XEXP (x, i) = find_reloads_toplev (XEXP (x, i), | |
3451 | ind_levels, is_set_dest); | |
3452 | } | |
3453 | return x; | |
3454 | } | |
3455 | ||
3456 | static rtx | |
3457 | make_memloc (ad, regno) | |
3458 | rtx ad; | |
3459 | int regno; | |
3460 | { | |
3461 | register int i; | |
3462 | rtx tem = reg_equiv_address[regno]; | |
3463 | for (i = 0; i < n_memlocs; i++) | |
3464 | if (rtx_equal_p (tem, XEXP (memlocs[i], 0))) | |
3465 | return memlocs[i]; | |
3466 | ||
3467 | /* If TEM might contain a pseudo, we must copy it to avoid | |
3468 | modifying it when we do the substitution for the reload. */ | |
3469 | if (rtx_varies_p (tem)) | |
3470 | tem = copy_rtx (tem); | |
3471 | ||
3472 | tem = gen_rtx (MEM, GET_MODE (ad), tem); | |
3473 | RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
3474 | memlocs[n_memlocs++] = tem; | |
3475 | return tem; | |
3476 | } | |
3477 | ||
3478 | /* Record all reloads needed for handling memory address AD | |
3479 | which appears in *LOC in a memory reference to mode MODE | |
3480 | which itself is found in location *MEMREFLOC. | |
3481 | Note that we take shortcuts assuming that no multi-reg machine mode | |
3482 | occurs as part of an address. | |
3483 | ||
3484 | OPERAND is the operand of the insn within which this address appears. | |
3485 | ||
3486 | IND_LEVELS says how many levels of indirect addressing this machine | |
3487 | supports. | |
3488 | ||
3489 | Value is nonzero if this address is reloaded or replaced as a whole. | |
3490 | This is interesting to the caller if the address is an autoincrement. | |
3491 | ||
3492 | Note that there is no verification that the address will be valid after | |
3493 | this routine does its work. Instead, we rely on the fact that the address | |
3494 | was valid when reload started. So we need only undo things that reload | |
3495 | could have broken. These are wrong register types, pseudos not allocated | |
3496 | to a hard register, and frame pointer elimination. */ | |
3497 | ||
3498 | static int | |
3499 | find_reloads_address (mode, memrefloc, ad, loc, operand, ind_levels) | |
3500 | enum machine_mode mode; | |
3501 | rtx *memrefloc; | |
3502 | rtx ad; | |
3503 | rtx *loc; | |
3504 | rtx operand; | |
3505 | int ind_levels; | |
3506 | { | |
3507 | register int regno; | |
3508 | rtx tem; | |
3509 | ||
3510 | /* If the address is a register, see if it is a legitimate address and | |
3511 | reload if not. We first handle the cases where we need not reload | |
3512 | or where we must reload in a non-standard way. */ | |
3513 | ||
3514 | if (GET_CODE (ad) == REG) | |
3515 | { | |
3516 | regno = REGNO (ad); | |
3517 | ||
3518 | if (reg_equiv_constant[regno] != 0 | |
3519 | && strict_memory_address_p (mode, reg_equiv_constant[regno])) | |
3520 | { | |
3521 | *loc = ad = reg_equiv_constant[regno]; | |
3522 | return 1; | |
3523 | } | |
3524 | ||
3525 | else if (reg_equiv_address[regno] != 0) | |
3526 | { | |
3527 | tem = make_memloc (ad, regno); | |
fb3821f7 | 3528 | find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0), |
eab89b90 | 3529 | &XEXP (tem, 0), operand, ind_levels); |
fb3821f7 | 3530 | push_reload (tem, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, |
eab89b90 RK |
3531 | GET_MODE (ad), VOIDmode, 0, 0, |
3532 | operand); | |
3533 | return 1; | |
3534 | } | |
3535 | ||
3536 | else if (reg_equiv_mem[regno] != 0) | |
3537 | { | |
3538 | tem = XEXP (reg_equiv_mem[regno], 0); | |
3539 | ||
3540 | /* If we can't indirect any more, a pseudo must be reloaded. | |
3541 | If the pseudo's address in its MEM is a SYMBOL_REF, it | |
3542 | must be reloaded unless indirect_symref_ok. Otherwise, it | |
3543 | can be reloaded if the address is REG or REG + CONST_INT. */ | |
3544 | ||
3545 | if (ind_levels > 0 | |
3546 | && ! (GET_CODE (tem) == SYMBOL_REF && ! indirect_symref_ok) | |
3547 | && ((GET_CODE (tem) == REG | |
3548 | && REGNO (tem) < FIRST_PSEUDO_REGISTER) | |
3549 | || (GET_CODE (tem) == PLUS | |
3550 | && GET_CODE (XEXP (tem, 0)) == REG | |
3551 | && REGNO (XEXP (tem, 0)) < FIRST_PSEUDO_REGISTER | |
3552 | && GET_CODE (XEXP (tem, 1)) == CONST_INT))) | |
3553 | return 0; | |
3554 | } | |
3555 | ||
3556 | /* The only remaining case where we can avoid a reload is if this is a | |
3557 | hard register that is valid as a base register and which is not the | |
3558 | subject of a CLOBBER in this insn. */ | |
3559 | ||
3560 | else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno) | |
3561 | && ! regno_clobbered_p (regno, this_insn)) | |
3562 | return 0; | |
3563 | ||
3564 | /* If we do not have one of the cases above, we must do the reload. */ | |
fb3821f7 | 3565 | push_reload (ad, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, |
eab89b90 RK |
3566 | GET_MODE (ad), VOIDmode, 0, 0, operand); |
3567 | return 1; | |
3568 | } | |
3569 | ||
3570 | if (strict_memory_address_p (mode, ad)) | |
3571 | { | |
3572 | /* The address appears valid, so reloads are not needed. | |
3573 | But the address may contain an eliminable register. | |
3574 | This can happen because a machine with indirect addressing | |
3575 | may consider a pseudo register by itself a valid address even when | |
3576 | it has failed to get a hard reg. | |
3577 | So do a tree-walk to find and eliminate all such regs. */ | |
3578 | ||
3579 | /* But first quickly dispose of a common case. */ | |
3580 | if (GET_CODE (ad) == PLUS | |
3581 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
3582 | && GET_CODE (XEXP (ad, 0)) == REG | |
3583 | && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) | |
3584 | return 0; | |
3585 | ||
3586 | subst_reg_equivs_changed = 0; | |
3587 | *loc = subst_reg_equivs (ad); | |
3588 | ||
3589 | if (! subst_reg_equivs_changed) | |
3590 | return 0; | |
3591 | ||
3592 | /* Check result for validity after substitution. */ | |
3593 | if (strict_memory_address_p (mode, ad)) | |
3594 | return 0; | |
3595 | } | |
3596 | ||
3597 | /* The address is not valid. We have to figure out why. One possibility | |
3598 | is that it is itself a MEM. This can happen when the frame pointer is | |
3599 | being eliminated, a pseudo is not allocated to a hard register, and the | |
3600 | offset between the frame and stack pointers is not its initial value. | |
d45cf215 | 3601 | In that case the pseudo will have been replaced by a MEM referring to |
eab89b90 RK |
3602 | the stack pointer. */ |
3603 | if (GET_CODE (ad) == MEM) | |
3604 | { | |
3605 | /* First ensure that the address in this MEM is valid. Then, unless | |
3606 | indirect addresses are valid, reload the MEM into a register. */ | |
3607 | tem = ad; | |
3608 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
3609 | operand, ind_levels == 0 ? 0 : ind_levels - 1); | |
3610 | /* Check similar cases as for indirect addresses as above except | |
3611 | that we can allow pseudos and a MEM since they should have been | |
3612 | taken care of above. */ | |
3613 | ||
3614 | if (ind_levels == 0 | |
3615 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
3616 | || GET_CODE (XEXP (tem, 0)) == MEM | |
3617 | || ! (GET_CODE (XEXP (tem, 0)) == REG | |
3618 | || (GET_CODE (XEXP (tem, 0)) == PLUS | |
3619 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG | |
3620 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) | |
3621 | { | |
3622 | /* Must use TEM here, not AD, since it is the one that will | |
3623 | have any subexpressions reloaded, if needed. */ | |
fb3821f7 | 3624 | push_reload (tem, NULL_RTX, loc, NULL_PTR, |
eab89b90 RK |
3625 | BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0, |
3626 | 0, operand); | |
3627 | return 1; | |
3628 | } | |
3629 | else | |
3630 | return 0; | |
3631 | } | |
3632 | ||
3633 | /* If we have address of a stack slot but it's not valid | |
3634 | (displacement is too large), compute the sum in a register. */ | |
3635 | else if (GET_CODE (ad) == PLUS | |
3636 | && (XEXP (ad, 0) == frame_pointer_rtx | |
3637 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
3638 | || XEXP (ad, 0) == arg_pointer_rtx | |
3639 | #endif | |
3640 | || XEXP (ad, 0) == stack_pointer_rtx) | |
3641 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
3642 | { | |
3643 | /* Unshare the MEM rtx so we can safely alter it. */ | |
3644 | if (memrefloc) | |
3645 | { | |
3646 | rtx oldref = *memrefloc; | |
3647 | *memrefloc = copy_rtx (*memrefloc); | |
3648 | loc = &XEXP (*memrefloc, 0); | |
3649 | if (operand == oldref) | |
3650 | operand = *memrefloc; | |
3651 | } | |
3652 | if (double_reg_address_ok) | |
3653 | { | |
3654 | /* Unshare the sum as well. */ | |
3655 | *loc = ad = copy_rtx (ad); | |
3656 | /* Reload the displacement into an index reg. | |
3657 | We assume the frame pointer or arg pointer is a base reg. */ | |
3658 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
3659 | INDEX_REG_CLASS, GET_MODE (ad), operand, | |
3660 | ind_levels); | |
3661 | } | |
3662 | else | |
3663 | { | |
3664 | /* If the sum of two regs is not necessarily valid, | |
3665 | reload the sum into a base reg. | |
3666 | That will at least work. */ | |
3667 | find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, | |
3668 | operand, ind_levels); | |
3669 | } | |
3670 | return 1; | |
3671 | } | |
3672 | ||
3673 | /* If we have an indexed stack slot, there are three possible reasons why | |
3674 | it might be invalid: The index might need to be reloaded, the address | |
3675 | might have been made by frame pointer elimination and hence have a | |
3676 | constant out of range, or both reasons might apply. | |
3677 | ||
3678 | We can easily check for an index needing reload, but even if that is the | |
3679 | case, we might also have an invalid constant. To avoid making the | |
3680 | conservative assumption and requiring two reloads, we see if this address | |
3681 | is valid when not interpreted strictly. If it is, the only problem is | |
3682 | that the index needs a reload and find_reloads_address_1 will take care | |
3683 | of it. | |
3684 | ||
3685 | There is still a case when we might generate an extra reload, | |
3686 | however. In certain cases eliminate_regs will return a MEM for a REG | |
3687 | (see the code there for details). In those cases, memory_address_p | |
3688 | applied to our address will return 0 so we will think that our offset | |
3689 | must be too large. But it might indeed be valid and the only problem | |
3690 | is that a MEM is present where a REG should be. This case should be | |
3691 | very rare and there doesn't seem to be any way to avoid it. | |
3692 | ||
3693 | If we decide to do something here, it must be that | |
3694 | `double_reg_address_ok' is true and that this address rtl was made by | |
3695 | eliminate_regs. We generate a reload of the fp/sp/ap + constant and | |
3696 | rework the sum so that the reload register will be added to the index. | |
3697 | This is safe because we know the address isn't shared. | |
3698 | ||
3699 | We check for fp/ap/sp as both the first and second operand of the | |
3700 | innermost PLUS. */ | |
3701 | ||
3702 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
3703 | && GET_CODE (XEXP (ad, 0)) == PLUS | |
3704 | && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx | |
3705 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
3706 | || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx | |
3707 | #endif | |
3708 | || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx) | |
3709 | && ! memory_address_p (mode, ad)) | |
3710 | { | |
3711 | *loc = ad = gen_rtx (PLUS, GET_MODE (ad), | |
3712 | plus_constant (XEXP (XEXP (ad, 0), 0), | |
3713 | INTVAL (XEXP (ad, 1))), | |
3714 | XEXP (XEXP (ad, 0), 1)); | |
3715 | find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, | |
3716 | GET_MODE (ad), operand, ind_levels); | |
3717 | find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0); | |
3718 | ||
3719 | return 1; | |
3720 | } | |
3721 | ||
3722 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
3723 | && GET_CODE (XEXP (ad, 0)) == PLUS | |
3724 | && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx | |
3725 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
3726 | || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx | |
3727 | #endif | |
3728 | || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx) | |
3729 | && ! memory_address_p (mode, ad)) | |
3730 | { | |
3731 | *loc = ad = gen_rtx (PLUS, GET_MODE (ad), | |
3732 | plus_constant (XEXP (XEXP (ad, 0), 1), | |
3733 | INTVAL (XEXP (ad, 1))), | |
3734 | XEXP (XEXP (ad, 0), 0)); | |
3735 | find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, | |
3736 | GET_MODE (ad), operand, ind_levels); | |
3737 | find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0); | |
3738 | ||
3739 | return 1; | |
3740 | } | |
3741 | ||
3742 | /* See if address becomes valid when an eliminable register | |
3743 | in a sum is replaced. */ | |
3744 | ||
3745 | tem = ad; | |
3746 | if (GET_CODE (ad) == PLUS) | |
3747 | tem = subst_indexed_address (ad); | |
3748 | if (tem != ad && strict_memory_address_p (mode, tem)) | |
3749 | { | |
3750 | /* Ok, we win that way. Replace any additional eliminable | |
3751 | registers. */ | |
3752 | ||
3753 | subst_reg_equivs_changed = 0; | |
3754 | tem = subst_reg_equivs (tem); | |
3755 | ||
3756 | /* Make sure that didn't make the address invalid again. */ | |
3757 | ||
3758 | if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) | |
3759 | { | |
3760 | *loc = tem; | |
3761 | return 0; | |
3762 | } | |
3763 | } | |
3764 | ||
3765 | /* If constants aren't valid addresses, reload the constant address | |
3766 | into a register. */ | |
3767 | if (CONSTANT_ADDRESS_P (ad) && ! strict_memory_address_p (mode, ad)) | |
3768 | { | |
3769 | /* If AD is in address in the constant pool, the MEM rtx may be shared. | |
3770 | Unshare it so we can safely alter it. */ | |
3771 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
3772 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
3773 | { | |
3774 | rtx oldref = *memrefloc; | |
3775 | *memrefloc = copy_rtx (*memrefloc); | |
3776 | loc = &XEXP (*memrefloc, 0); | |
3777 | if (operand == oldref) | |
3778 | operand = *memrefloc; | |
3779 | } | |
3780 | ||
3781 | find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, operand, | |
3782 | ind_levels); | |
3783 | return 1; | |
3784 | } | |
3785 | ||
3786 | return find_reloads_address_1 (ad, 0, loc, operand, ind_levels); | |
3787 | } | |
3788 | \f | |
3789 | /* Find all pseudo regs appearing in AD | |
3790 | that are eliminable in favor of equivalent values | |
3791 | and do not have hard regs; replace them by their equivalents. */ | |
3792 | ||
3793 | static rtx | |
3794 | subst_reg_equivs (ad) | |
3795 | rtx ad; | |
3796 | { | |
3797 | register RTX_CODE code = GET_CODE (ad); | |
3798 | register int i; | |
3799 | register char *fmt; | |
3800 | ||
3801 | switch (code) | |
3802 | { | |
3803 | case HIGH: | |
3804 | case CONST_INT: | |
3805 | case CONST: | |
3806 | case CONST_DOUBLE: | |
3807 | case SYMBOL_REF: | |
3808 | case LABEL_REF: | |
3809 | case PC: | |
3810 | case CC0: | |
3811 | return ad; | |
3812 | ||
3813 | case REG: | |
3814 | { | |
3815 | register int regno = REGNO (ad); | |
3816 | ||
3817 | if (reg_equiv_constant[regno] != 0) | |
3818 | { | |
3819 | subst_reg_equivs_changed = 1; | |
3820 | return reg_equiv_constant[regno]; | |
3821 | } | |
3822 | } | |
3823 | return ad; | |
3824 | ||
3825 | case PLUS: | |
3826 | /* Quickly dispose of a common case. */ | |
3827 | if (XEXP (ad, 0) == frame_pointer_rtx | |
3828 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
3829 | return ad; | |
3830 | } | |
3831 | ||
3832 | fmt = GET_RTX_FORMAT (code); | |
3833 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3834 | if (fmt[i] == 'e') | |
3835 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i)); | |
3836 | return ad; | |
3837 | } | |
3838 | \f | |
3839 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
3840 | address, namely: sum constant integers, surround the sum of two | |
3841 | constants with a CONST, put the constant as the second operand, and | |
3842 | group the constant on the outermost sum. | |
3843 | ||
3844 | This routine assumes both inputs are already in canonical form. */ | |
3845 | ||
3846 | rtx | |
3847 | form_sum (x, y) | |
3848 | rtx x, y; | |
3849 | { | |
3850 | rtx tem; | |
3851 | ||
3852 | if (GET_CODE (x) == CONST_INT) | |
3853 | return plus_constant (y, INTVAL (x)); | |
3854 | else if (GET_CODE (y) == CONST_INT) | |
3855 | return plus_constant (x, INTVAL (y)); | |
3856 | else if (CONSTANT_P (x)) | |
3857 | tem = x, x = y, y = tem; | |
3858 | ||
3859 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
3860 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
3861 | ||
3862 | /* Note that if the operands of Y are specified in the opposite | |
3863 | order in the recursive calls below, infinite recursion will occur. */ | |
3864 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) | |
3865 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); | |
3866 | ||
3867 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
3868 | constant will have been placed second. */ | |
3869 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
3870 | { | |
3871 | if (GET_CODE (x) == CONST) | |
3872 | x = XEXP (x, 0); | |
3873 | if (GET_CODE (y) == CONST) | |
3874 | y = XEXP (y, 0); | |
3875 | ||
3876 | return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, Pmode, x, y)); | |
3877 | } | |
3878 | ||
3879 | return gen_rtx (PLUS, Pmode, x, y); | |
3880 | } | |
3881 | \f | |
3882 | /* If ADDR is a sum containing a pseudo register that should be | |
3883 | replaced with a constant (from reg_equiv_constant), | |
3884 | return the result of doing so, and also apply the associative | |
3885 | law so that the result is more likely to be a valid address. | |
3886 | (But it is not guaranteed to be one.) | |
3887 | ||
3888 | Note that at most one register is replaced, even if more are | |
3889 | replaceable. Also, we try to put the result into a canonical form | |
3890 | so it is more likely to be a valid address. | |
3891 | ||
3892 | In all other cases, return ADDR. */ | |
3893 | ||
3894 | static rtx | |
3895 | subst_indexed_address (addr) | |
3896 | rtx addr; | |
3897 | { | |
3898 | rtx op0 = 0, op1 = 0, op2 = 0; | |
3899 | rtx tem; | |
3900 | int regno; | |
3901 | ||
3902 | if (GET_CODE (addr) == PLUS) | |
3903 | { | |
3904 | /* Try to find a register to replace. */ | |
3905 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
3906 | if (GET_CODE (op0) == REG | |
3907 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER | |
3908 | && reg_renumber[regno] < 0 | |
3909 | && reg_equiv_constant[regno] != 0) | |
3910 | op0 = reg_equiv_constant[regno]; | |
3911 | else if (GET_CODE (op1) == REG | |
3912 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER | |
3913 | && reg_renumber[regno] < 0 | |
3914 | && reg_equiv_constant[regno] != 0) | |
3915 | op1 = reg_equiv_constant[regno]; | |
3916 | else if (GET_CODE (op0) == PLUS | |
3917 | && (tem = subst_indexed_address (op0)) != op0) | |
3918 | op0 = tem; | |
3919 | else if (GET_CODE (op1) == PLUS | |
3920 | && (tem = subst_indexed_address (op1)) != op1) | |
3921 | op1 = tem; | |
3922 | else | |
3923 | return addr; | |
3924 | ||
3925 | /* Pick out up to three things to add. */ | |
3926 | if (GET_CODE (op1) == PLUS) | |
3927 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
3928 | else if (GET_CODE (op0) == PLUS) | |
3929 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
3930 | ||
3931 | /* Compute the sum. */ | |
3932 | if (op2 != 0) | |
3933 | op1 = form_sum (op1, op2); | |
3934 | if (op1 != 0) | |
3935 | op0 = form_sum (op0, op1); | |
3936 | ||
3937 | return op0; | |
3938 | } | |
3939 | return addr; | |
3940 | } | |
3941 | \f | |
3942 | /* Record the pseudo registers we must reload into hard registers | |
3943 | in a subexpression of a would-be memory address, X. | |
3944 | (This function is not called if the address we find is strictly valid.) | |
3945 | CONTEXT = 1 means we are considering regs as index regs, | |
3946 | = 0 means we are considering them as base regs. | |
3947 | ||
3948 | OPERAND is the operand of the insn within which this address appears. | |
3949 | ||
3950 | IND_LEVELS says how many levels of indirect addressing are | |
3951 | supported at this point in the address. | |
3952 | ||
3953 | We return nonzero if X, as a whole, is reloaded or replaced. */ | |
3954 | ||
3955 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
3956 | occurs as part of an address. | |
3957 | Also, this is not fully machine-customizable; it works for machines | |
3958 | such as vaxes and 68000's and 32000's, but other possible machines | |
3959 | could have addressing modes that this does not handle right. */ | |
3960 | ||
3961 | static int | |
3962 | find_reloads_address_1 (x, context, loc, operand, ind_levels) | |
3963 | rtx x; | |
3964 | int context; | |
3965 | rtx *loc; | |
3966 | rtx operand; | |
3967 | int ind_levels; | |
3968 | { | |
3969 | register RTX_CODE code = GET_CODE (x); | |
3970 | ||
3971 | if (code == PLUS) | |
3972 | { | |
3973 | register rtx op0 = XEXP (x, 0); | |
3974 | register rtx op1 = XEXP (x, 1); | |
3975 | register RTX_CODE code0 = GET_CODE (op0); | |
3976 | register RTX_CODE code1 = GET_CODE (op1); | |
3977 | if (code0 == MULT || code0 == SIGN_EXTEND || code1 == MEM) | |
3978 | { | |
3979 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels); | |
3980 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels); | |
3981 | } | |
3982 | else if (code1 == MULT || code1 == SIGN_EXTEND || code0 == MEM) | |
3983 | { | |
3984 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels); | |
3985 | find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels); | |
3986 | } | |
3987 | else if (code0 == CONST_INT || code0 == CONST | |
3988 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
3989 | { | |
3990 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels); | |
3991 | } | |
3992 | else if (code1 == CONST_INT || code1 == CONST | |
3993 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
3994 | { | |
3995 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels); | |
3996 | } | |
3997 | else if (code0 == REG && code1 == REG) | |
3998 | { | |
3999 | if (REG_OK_FOR_INDEX_P (op0) | |
4000 | && REG_OK_FOR_BASE_P (op1)) | |
4001 | return 0; | |
4002 | else if (REG_OK_FOR_INDEX_P (op1) | |
4003 | && REG_OK_FOR_BASE_P (op0)) | |
4004 | return 0; | |
4005 | else if (REG_OK_FOR_BASE_P (op1)) | |
4006 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels); | |
4007 | else if (REG_OK_FOR_BASE_P (op0)) | |
4008 | find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels); | |
4009 | else if (REG_OK_FOR_INDEX_P (op1)) | |
4010 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels); | |
4011 | else if (REG_OK_FOR_INDEX_P (op0)) | |
4012 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels); | |
4013 | else | |
4014 | { | |
4015 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, | |
4016 | ind_levels); | |
4017 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, | |
4018 | ind_levels); | |
4019 | } | |
4020 | } | |
4021 | else if (code0 == REG) | |
4022 | { | |
4023 | find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels); | |
4024 | find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels); | |
4025 | } | |
4026 | else if (code1 == REG) | |
4027 | { | |
4028 | find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels); | |
4029 | find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels); | |
4030 | } | |
4031 | } | |
4032 | else if (code == POST_INC || code == POST_DEC | |
4033 | || code == PRE_INC || code == PRE_DEC) | |
4034 | { | |
4035 | if (GET_CODE (XEXP (x, 0)) == REG) | |
4036 | { | |
4037 | register int regno = REGNO (XEXP (x, 0)); | |
4038 | int value = 0; | |
4039 | rtx x_orig = x; | |
4040 | ||
4041 | /* A register that is incremented cannot be constant! */ | |
4042 | if (regno >= FIRST_PSEUDO_REGISTER | |
4043 | && reg_equiv_constant[regno] != 0) | |
4044 | abort (); | |
4045 | ||
4046 | /* Handle a register that is equivalent to a memory location | |
4047 | which cannot be addressed directly. */ | |
4048 | if (reg_equiv_address[regno] != 0) | |
4049 | { | |
4050 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
4051 | /* First reload the memory location's address. */ | |
4052 | find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0), | |
4053 | &XEXP (tem, 0), operand, ind_levels); | |
4054 | /* Put this inside a new increment-expression. */ | |
4055 | x = gen_rtx (GET_CODE (x), GET_MODE (x), tem); | |
4056 | /* Proceed to reload that, as if it contained a register. */ | |
4057 | } | |
4058 | ||
4059 | /* If we have a hard register that is ok as an index, | |
4060 | don't make a reload. If an autoincrement of a nice register | |
4061 | isn't "valid", it must be that no autoincrement is "valid". | |
4062 | If that is true and something made an autoincrement anyway, | |
4063 | this must be a special context where one is allowed. | |
4064 | (For example, a "push" instruction.) | |
4065 | We can't improve this address, so leave it alone. */ | |
4066 | ||
4067 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
4068 | and record how much to increment by. */ | |
4069 | ||
4070 | if (reg_renumber[regno] >= 0) | |
4071 | regno = reg_renumber[regno]; | |
4072 | if ((regno >= FIRST_PSEUDO_REGISTER | |
4073 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
4074 | : REGNO_OK_FOR_BASE_P (regno)))) | |
4075 | { | |
4076 | register rtx link; | |
4077 | ||
4078 | int reloadnum | |
fb3821f7 | 4079 | = push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 RK |
4080 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
4081 | GET_MODE (x), GET_MODE (x), VOIDmode, 0, operand); | |
4082 | reload_inc[reloadnum] | |
4083 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); | |
4084 | ||
4085 | value = 1; | |
4086 | ||
4087 | #ifdef AUTO_INC_DEC | |
4088 | /* Update the REG_INC notes. */ | |
4089 | ||
4090 | for (link = REG_NOTES (this_insn); | |
4091 | link; link = XEXP (link, 1)) | |
4092 | if (REG_NOTE_KIND (link) == REG_INC | |
4093 | && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0))) | |
4094 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
4095 | #endif | |
4096 | } | |
4097 | return value; | |
4098 | } | |
4099 | else if (GET_CODE (XEXP (x, 0)) == MEM) | |
4100 | { | |
4101 | /* This is probably the result of a substitution, by eliminate_regs, | |
4102 | of an equivalent address for a pseudo that was not allocated to a | |
4103 | hard register. Verify that the specified address is valid and | |
4104 | reload it into a register. */ | |
4105 | rtx tem = XEXP (x, 0); | |
4106 | register rtx link; | |
4107 | int reloadnum; | |
4108 | ||
4109 | /* Since we know we are going to reload this item, don't decrement | |
4110 | for the indirection level. | |
4111 | ||
4112 | Note that this is actually conservative: it would be slightly | |
4113 | more efficient to use the value of SPILL_INDIRECT_LEVELS from | |
4114 | reload1.c here. */ | |
4115 | find_reloads_address (GET_MODE (x), &XEXP (x, 0), | |
4116 | XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0), | |
4117 | operand, ind_levels); | |
4118 | ||
fb3821f7 | 4119 | reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 RK |
4120 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
4121 | GET_MODE (x), VOIDmode, 0, 0, operand); | |
4122 | reload_inc[reloadnum] | |
4123 | = find_inc_amount (PATTERN (this_insn), XEXP (x, 0)); | |
4124 | ||
4125 | link = FIND_REG_INC_NOTE (this_insn, tem); | |
4126 | if (link != 0) | |
4127 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
4128 | ||
4129 | return 1; | |
4130 | } | |
4131 | } | |
4132 | else if (code == MEM) | |
4133 | { | |
4134 | /* This is probably the result of a substitution, by eliminate_regs, | |
4135 | of an equivalent address for a pseudo that was not allocated to a | |
4136 | hard register. Verify that the specified address is valid and reload | |
4137 | it into a register. | |
4138 | ||
4139 | Since we know we are going to reload this item, don't decrement | |
4140 | for the indirection level. | |
4141 | ||
4142 | Note that this is actually conservative: it would be slightly more | |
4143 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
4144 | reload1.c here. */ | |
4145 | ||
4146 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
4147 | operand, ind_levels); | |
4148 | ||
fb3821f7 | 4149 | push_reload (*loc, NULL_RTX, loc, NULL_PTR, |
eab89b90 RK |
4150 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
4151 | GET_MODE (x), VOIDmode, 0, 0, operand); | |
4152 | return 1; | |
4153 | } | |
4154 | else if (code == REG) | |
4155 | { | |
4156 | register int regno = REGNO (x); | |
4157 | ||
4158 | if (reg_equiv_constant[regno] != 0) | |
4159 | { | |
58c8c593 RK |
4160 | find_reloads_address_part (reg_equiv_constant[regno], loc, |
4161 | (context ? INDEX_REG_CLASS | |
4162 | : BASE_REG_CLASS), | |
4163 | GET_MODE (x), operand, ind_levels); | |
eab89b90 RK |
4164 | return 1; |
4165 | } | |
4166 | ||
4167 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
4168 | that feeds this insn. */ | |
4169 | if (reg_equiv_mem[regno] != 0) | |
4170 | { | |
fb3821f7 | 4171 | push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR, |
eab89b90 RK |
4172 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
4173 | GET_MODE (x), VOIDmode, 0, 0, operand); | |
4174 | return 1; | |
4175 | } | |
4176 | #endif | |
4177 | if (reg_equiv_address[regno] != 0) | |
4178 | { | |
4179 | x = make_memloc (x, regno); | |
4180 | find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0), | |
4181 | operand, ind_levels); | |
4182 | } | |
4183 | ||
4184 | if (reg_renumber[regno] >= 0) | |
4185 | regno = reg_renumber[regno]; | |
4186 | if ((regno >= FIRST_PSEUDO_REGISTER | |
4187 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
4188 | : REGNO_OK_FOR_BASE_P (regno)))) | |
4189 | { | |
fb3821f7 | 4190 | push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 RK |
4191 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
4192 | GET_MODE (x), VOIDmode, 0, 0, operand); | |
4193 | return 1; | |
4194 | } | |
4195 | ||
4196 | /* If a register appearing in an address is the subject of a CLOBBER | |
4197 | in this insn, reload it into some other register to be safe. | |
4198 | The CLOBBER is supposed to make the register unavailable | |
4199 | from before this insn to after it. */ | |
4200 | if (regno_clobbered_p (regno, this_insn)) | |
4201 | { | |
fb3821f7 | 4202 | push_reload (x, NULL_RTX, loc, NULL_PTR, |
eab89b90 RK |
4203 | context ? INDEX_REG_CLASS : BASE_REG_CLASS, |
4204 | GET_MODE (x), VOIDmode, 0, 0, operand); | |
4205 | return 1; | |
4206 | } | |
4207 | } | |
4208 | else | |
4209 | { | |
4210 | register char *fmt = GET_RTX_FORMAT (code); | |
4211 | register int i; | |
4212 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4213 | { | |
4214 | if (fmt[i] == 'e') | |
4215 | find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i), | |
4216 | operand, ind_levels); | |
4217 | } | |
4218 | } | |
4219 | ||
4220 | return 0; | |
4221 | } | |
4222 | \f | |
4223 | /* X, which is found at *LOC, is a part of an address that needs to be | |
4224 | reloaded into a register of class CLASS. If X is a constant, or if | |
4225 | X is a PLUS that contains a constant, check that the constant is a | |
4226 | legitimate operand and that we are supposed to be able to load | |
4227 | it into the register. | |
4228 | ||
4229 | If not, force the constant into memory and reload the MEM instead. | |
4230 | ||
4231 | MODE is the mode to use, in case X is an integer constant. | |
4232 | ||
4233 | NEEDED_FOR says which operand this reload is needed for. | |
4234 | ||
4235 | IND_LEVELS says how many levels of indirect addressing this machine | |
4236 | supports. */ | |
4237 | ||
4238 | static void | |
4239 | find_reloads_address_part (x, loc, class, mode, needed_for, ind_levels) | |
4240 | rtx x; | |
4241 | rtx *loc; | |
4242 | enum reg_class class; | |
4243 | enum machine_mode mode; | |
4244 | rtx needed_for; | |
4245 | int ind_levels; | |
4246 | { | |
4247 | if (CONSTANT_P (x) | |
4248 | && (! LEGITIMATE_CONSTANT_P (x) | |
4249 | || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) | |
4250 | { | |
4251 | rtx tem = x = force_const_mem (mode, x); | |
4252 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), | |
4253 | needed_for, ind_levels); | |
4254 | } | |
4255 | ||
4256 | else if (GET_CODE (x) == PLUS | |
4257 | && CONSTANT_P (XEXP (x, 1)) | |
4258 | && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | |
4259 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) | |
4260 | { | |
4261 | rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); | |
4262 | ||
4263 | x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem); | |
4264 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), | |
4265 | needed_for, ind_levels); | |
4266 | } | |
4267 | ||
fb3821f7 CH |
4268 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, |
4269 | mode, VOIDmode, 0, 0, needed_for); | |
eab89b90 RK |
4270 | } |
4271 | \f | |
4272 | /* Substitute into X the registers into which we have reloaded | |
4273 | the things that need reloading. The array `replacements' | |
4274 | says contains the locations of all pointers that must be changed | |
4275 | and says what to replace them with. | |
4276 | ||
4277 | Return the rtx that X translates into; usually X, but modified. */ | |
4278 | ||
4279 | void | |
4280 | subst_reloads () | |
4281 | { | |
4282 | register int i; | |
4283 | ||
4284 | for (i = 0; i < n_replacements; i++) | |
4285 | { | |
4286 | register struct replacement *r = &replacements[i]; | |
4287 | register rtx reloadreg = reload_reg_rtx[r->what]; | |
4288 | if (reloadreg) | |
4289 | { | |
4290 | /* Encapsulate RELOADREG so its machine mode matches what | |
4291 | used to be there. */ | |
4292 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) | |
4293 | reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg)); | |
4294 | ||
4295 | /* If we are putting this into a SUBREG and RELOADREG is a | |
4296 | SUBREG, we would be making nested SUBREGs, so we have to fix | |
4297 | this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ | |
4298 | ||
4299 | if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) | |
4300 | { | |
4301 | if (GET_MODE (*r->subreg_loc) | |
4302 | == GET_MODE (SUBREG_REG (reloadreg))) | |
4303 | *r->subreg_loc = SUBREG_REG (reloadreg); | |
4304 | else | |
4305 | { | |
4306 | *r->where = SUBREG_REG (reloadreg); | |
4307 | SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg); | |
4308 | } | |
4309 | } | |
4310 | else | |
4311 | *r->where = reloadreg; | |
4312 | } | |
4313 | /* If reload got no reg and isn't optional, something's wrong. */ | |
4314 | else if (! reload_optional[r->what]) | |
4315 | abort (); | |
4316 | } | |
4317 | } | |
4318 | \f | |
4319 | /* Make a copy of any replacements being done into X and move those copies | |
4320 | to locations in Y, a copy of X. We only look at the highest level of | |
4321 | the RTL. */ | |
4322 | ||
4323 | void | |
4324 | copy_replacements (x, y) | |
4325 | rtx x; | |
4326 | rtx y; | |
4327 | { | |
4328 | int i, j; | |
4329 | enum rtx_code code = GET_CODE (x); | |
4330 | char *fmt = GET_RTX_FORMAT (code); | |
4331 | struct replacement *r; | |
4332 | ||
4333 | /* We can't support X being a SUBREG because we might then need to know its | |
4334 | location if something inside it was replaced. */ | |
4335 | if (code == SUBREG) | |
4336 | abort (); | |
4337 | ||
4338 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4339 | if (fmt[i] == 'e') | |
4340 | for (j = 0; j < n_replacements; j++) | |
4341 | { | |
4342 | if (replacements[j].subreg_loc == &XEXP (x, i)) | |
4343 | { | |
4344 | r = &replacements[n_replacements++]; | |
4345 | r->where = replacements[j].where; | |
4346 | r->subreg_loc = &XEXP (y, i); | |
4347 | r->what = replacements[j].what; | |
4348 | r->mode = replacements[j].mode; | |
4349 | } | |
4350 | else if (replacements[j].where == &XEXP (x, i)) | |
4351 | { | |
4352 | r = &replacements[n_replacements++]; | |
4353 | r->where = &XEXP (y, i); | |
4354 | r->subreg_loc = 0; | |
4355 | r->what = replacements[j].what; | |
4356 | r->mode = replacements[j].mode; | |
4357 | } | |
4358 | } | |
4359 | } | |
4360 | \f | |
af929c62 RK |
4361 | /* If LOC was scheduled to be replaced by something, return the replacement. |
4362 | Otherwise, return *LOC. */ | |
4363 | ||
4364 | rtx | |
4365 | find_replacement (loc) | |
4366 | rtx *loc; | |
4367 | { | |
4368 | struct replacement *r; | |
4369 | ||
4370 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
4371 | { | |
4372 | rtx reloadreg = reload_reg_rtx[r->what]; | |
4373 | ||
4374 | if (reloadreg && r->where == loc) | |
4375 | { | |
4376 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
4377 | reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg)); | |
4378 | ||
4379 | return reloadreg; | |
4380 | } | |
4381 | else if (reloadreg && r->subreg_loc == loc) | |
4382 | { | |
4383 | /* RELOADREG must be either a REG or a SUBREG. | |
4384 | ||
4385 | ??? Is it actually still ever a SUBREG? If so, why? */ | |
4386 | ||
4387 | if (GET_CODE (reloadreg) == REG) | |
4388 | return gen_rtx (REG, GET_MODE (*loc), | |
4389 | REGNO (reloadreg) + SUBREG_WORD (*loc)); | |
4390 | else if (GET_MODE (reloadreg) == GET_MODE (*loc)) | |
4391 | return reloadreg; | |
4392 | else | |
4393 | return gen_rtx (SUBREG, GET_MODE (*loc), SUBREG_REG (reloadreg), | |
4394 | SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc)); | |
4395 | } | |
4396 | } | |
4397 | ||
4398 | return *loc; | |
4399 | } | |
4400 | \f | |
eab89b90 RK |
4401 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
4402 | appears either explicitly or implicitly in X | |
4403 | other than being stored into. | |
4404 | ||
4405 | References contained within the substructure at LOC do not count. | |
4406 | LOC may be zero, meaning don't ignore anything. | |
4407 | ||
4408 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
4409 | look at equivalences for pseudos that didn't get hard registers. */ | |
4410 | ||
4411 | int | |
4412 | refers_to_regno_for_reload_p (regno, endregno, x, loc) | |
4413 | int regno, endregno; | |
4414 | rtx x; | |
4415 | rtx *loc; | |
4416 | { | |
4417 | register int i; | |
4418 | register RTX_CODE code; | |
4419 | register char *fmt; | |
4420 | ||
4421 | if (x == 0) | |
4422 | return 0; | |
4423 | ||
4424 | repeat: | |
4425 | code = GET_CODE (x); | |
4426 | ||
4427 | switch (code) | |
4428 | { | |
4429 | case REG: | |
4430 | i = REGNO (x); | |
4431 | ||
4803a34a RK |
4432 | /* If this is a pseudo, a hard register must not have been allocated. |
4433 | X must therefore either be a constant or be in memory. */ | |
4434 | if (i >= FIRST_PSEUDO_REGISTER) | |
4435 | { | |
4436 | if (reg_equiv_memory_loc[i]) | |
4437 | return refers_to_regno_for_reload_p (regno, endregno, | |
fb3821f7 CH |
4438 | reg_equiv_memory_loc[i], |
4439 | NULL_PTR); | |
4803a34a RK |
4440 | |
4441 | if (reg_equiv_constant[i]) | |
4442 | return 0; | |
4443 | ||
4444 | abort (); | |
4445 | } | |
eab89b90 RK |
4446 | |
4447 | return (endregno > i | |
4448 | && regno < i + (i < FIRST_PSEUDO_REGISTER | |
4449 | ? HARD_REGNO_NREGS (i, GET_MODE (x)) | |
4450 | : 1)); | |
4451 | ||
4452 | case SUBREG: | |
4453 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
4454 | registers are being modified. Otherwise, handle normally. */ | |
4455 | if (GET_CODE (SUBREG_REG (x)) == REG | |
4456 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
4457 | { | |
4458 | int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
4459 | int inner_endregno | |
4460 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER | |
4461 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
4462 | ||
4463 | return endregno > inner_regno && regno < inner_endregno; | |
4464 | } | |
4465 | break; | |
4466 | ||
4467 | case CLOBBER: | |
4468 | case SET: | |
4469 | if (&SET_DEST (x) != loc | |
4470 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
4471 | a pseudo but not for hard registers since we can | |
4472 | treat each word individually. */ | |
4473 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
4474 | && loc != &SUBREG_REG (SET_DEST (x)) | |
4475 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
4476 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER | |
4477 | && refers_to_regno_for_reload_p (regno, endregno, | |
4478 | SUBREG_REG (SET_DEST (x)), | |
4479 | loc)) | |
4480 | || (GET_CODE (SET_DEST (x)) != REG | |
4481 | && refers_to_regno_for_reload_p (regno, endregno, | |
4482 | SET_DEST (x), loc)))) | |
4483 | return 1; | |
4484 | ||
4485 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
4486 | return 0; | |
4487 | x = SET_SRC (x); | |
4488 | goto repeat; | |
4489 | } | |
4490 | ||
4491 | /* X does not match, so try its subexpressions. */ | |
4492 | ||
4493 | fmt = GET_RTX_FORMAT (code); | |
4494 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4495 | { | |
4496 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
4497 | { | |
4498 | if (i == 0) | |
4499 | { | |
4500 | x = XEXP (x, 0); | |
4501 | goto repeat; | |
4502 | } | |
4503 | else | |
4504 | if (refers_to_regno_for_reload_p (regno, endregno, | |
4505 | XEXP (x, i), loc)) | |
4506 | return 1; | |
4507 | } | |
4508 | else if (fmt[i] == 'E') | |
4509 | { | |
4510 | register int j; | |
4511 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
4512 | if (loc != &XVECEXP (x, i, j) | |
4513 | && refers_to_regno_for_reload_p (regno, endregno, | |
4514 | XVECEXP (x, i, j), loc)) | |
4515 | return 1; | |
4516 | } | |
4517 | } | |
4518 | return 0; | |
4519 | } | |
bfa30b22 RK |
4520 | |
4521 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
4522 | we check if any register number in X conflicts with the relevant register | |
4523 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
4524 | contains a MEM (we don't bother checking for memory addresses that can't | |
4525 | conflict because we expect this to be a rare case. | |
4526 | ||
4527 | This function is similar to reg_overlap_mention_p in rtlanal.c except | |
4528 | that we look at equivalences for pseudos that didn't get hard registers. */ | |
4529 | ||
4530 | int | |
4531 | reg_overlap_mentioned_for_reload_p (x, in) | |
4532 | rtx x, in; | |
4533 | { | |
4534 | int regno, endregno; | |
4535 | ||
4536 | if (GET_CODE (x) == SUBREG) | |
4537 | { | |
4538 | regno = REGNO (SUBREG_REG (x)); | |
4539 | if (regno < FIRST_PSEUDO_REGISTER) | |
4540 | regno += SUBREG_WORD (x); | |
4541 | } | |
4542 | else if (GET_CODE (x) == REG) | |
4543 | { | |
4544 | regno = REGNO (x); | |
4803a34a RK |
4545 | |
4546 | /* If this is a pseudo, it must not have been assigned a hard register. | |
4547 | Therefore, it must either be in memory or be a constant. */ | |
4548 | ||
4549 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4550 | { | |
4551 | if (reg_equiv_memory_loc[regno]) | |
4552 | return refers_to_mem_for_reload_p (in); | |
4553 | else if (reg_equiv_constant[regno]) | |
4554 | return 0; | |
4555 | abort (); | |
4556 | } | |
bfa30b22 RK |
4557 | } |
4558 | else if (CONSTANT_P (x)) | |
4559 | return 0; | |
4560 | else if (GET_CODE (x) == MEM) | |
4803a34a | 4561 | return refers_to_mem_for_reload_p (in); |
bfa30b22 RK |
4562 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
4563 | || GET_CODE (x) == CC0) | |
4564 | return reg_mentioned_p (x, in); | |
4565 | else | |
4566 | abort (); | |
4567 | ||
4568 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
4569 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
4570 | ||
fb3821f7 | 4571 | return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR); |
bfa30b22 | 4572 | } |
4803a34a RK |
4573 | |
4574 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
4575 | registers. */ | |
4576 | ||
4577 | int | |
4578 | refers_to_mem_for_reload_p (x) | |
4579 | rtx x; | |
4580 | { | |
4581 | char *fmt; | |
4582 | int i; | |
4583 | ||
4584 | if (GET_CODE (x) == MEM) | |
4585 | return 1; | |
4586 | ||
4587 | if (GET_CODE (x) == REG) | |
4588 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
4589 | && reg_equiv_memory_loc[REGNO (x)]); | |
4590 | ||
4591 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
4592 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
4593 | if (fmt[i] == 'e' | |
4594 | && (GET_CODE (XEXP (x, i)) == MEM | |
4595 | || refers_to_mem_for_reload_p (XEXP (x, i)))) | |
4596 | return 1; | |
4597 | ||
4598 | return 0; | |
4599 | } | |
eab89b90 RK |
4600 | \f |
4601 | #if 0 | |
4602 | ||
4603 | /* [[This function is currently obsolete, now that volatility | |
4604 | is represented by a special bit `volatil' so VOLATILE is never used; | |
4605 | and UNCHANGING has never been brought into use.]] | |
4606 | ||
4607 | Alter X by eliminating all VOLATILE and UNCHANGING expressions. | |
4608 | Each of them is replaced by its operand. | |
4609 | Thus, (PLUS (VOLATILE (MEM (REG 5))) (CONST_INT 4)) | |
4610 | becomes (PLUS (MEM (REG 5)) (CONST_INT 4)). | |
4611 | ||
4612 | If X is itself a VOLATILE expression, | |
4613 | we return the expression that should replace it | |
4614 | but we do not modify X. */ | |
4615 | ||
4616 | static rtx | |
4617 | forget_volatility (x) | |
4618 | register rtx x; | |
4619 | { | |
4620 | enum rtx_code code = GET_CODE (x); | |
4621 | register char *fmt; | |
4622 | register int i; | |
4623 | register rtx value = 0; | |
4624 | ||
4625 | switch (code) | |
4626 | { | |
4627 | case LABEL_REF: | |
4628 | case SYMBOL_REF: | |
4629 | case CONST_INT: | |
4630 | case CONST_DOUBLE: | |
4631 | case CONST: | |
4632 | case REG: | |
4633 | case CC0: | |
4634 | case PC: | |
4635 | return x; | |
4636 | ||
4637 | case VOLATILE: | |
4638 | case UNCHANGING: | |
4639 | return XEXP (x, 0); | |
4640 | } | |
4641 | ||
4642 | fmt = GET_RTX_FORMAT (code); | |
4643 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4644 | { | |
4645 | if (fmt[i] == 'e') | |
4646 | XEXP (x, i) = forget_volatility (XEXP (x, i)); | |
4647 | if (fmt[i] == 'E') | |
4648 | { | |
4649 | register int j; | |
4650 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4651 | XVECEXP (x, i, j) = forget_volatility (XVECEXP (x, i, j)); | |
4652 | } | |
4653 | } | |
4654 | ||
4655 | return x; | |
4656 | } | |
4657 | ||
4658 | #endif | |
4659 | \f | |
4660 | /* Check the insns before INSN to see if there is a suitable register | |
4661 | containing the same value as GOAL. | |
4662 | If OTHER is -1, look for a register in class CLASS. | |
4663 | Otherwise, just see if register number OTHER shares GOAL's value. | |
4664 | ||
4665 | Return an rtx for the register found, or zero if none is found. | |
4666 | ||
4667 | If RELOAD_REG_P is (short *)1, | |
4668 | we reject any hard reg that appears in reload_reg_rtx | |
4669 | because such a hard reg is also needed coming into this insn. | |
4670 | ||
4671 | If RELOAD_REG_P is any other nonzero value, | |
4672 | it is a vector indexed by hard reg number | |
4673 | and we reject any hard reg whose element in the vector is nonnegative | |
4674 | as well as any that appears in reload_reg_rtx. | |
4675 | ||
4676 | If GOAL is zero, then GOALREG is a register number; we look | |
4677 | for an equivalent for that register. | |
4678 | ||
4679 | MODE is the machine mode of the value we want an equivalence for. | |
4680 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
4681 | ||
4682 | This function is used by jump.c as well as in the reload pass. | |
4683 | ||
4684 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
4685 | as if it were a constant except that sp is required to be unchanging. */ | |
4686 | ||
4687 | rtx | |
4688 | find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode) | |
4689 | register rtx goal; | |
4690 | rtx insn; | |
4691 | enum reg_class class; | |
4692 | register int other; | |
4693 | short *reload_reg_p; | |
4694 | int goalreg; | |
4695 | enum machine_mode mode; | |
4696 | { | |
4697 | register rtx p = insn; | |
4698 | rtx valtry, value, where; | |
4699 | register rtx pat; | |
4700 | register int regno = -1; | |
4701 | int valueno; | |
4702 | int goal_mem = 0; | |
4703 | int goal_const = 0; | |
4704 | int goal_mem_addr_varies = 0; | |
4705 | int need_stable_sp = 0; | |
4706 | int nregs; | |
4707 | int valuenregs; | |
4708 | ||
4709 | if (goal == 0) | |
4710 | regno = goalreg; | |
4711 | else if (GET_CODE (goal) == REG) | |
4712 | regno = REGNO (goal); | |
4713 | else if (GET_CODE (goal) == MEM) | |
4714 | { | |
4715 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
4716 | if (MEM_VOLATILE_P (goal)) | |
4717 | return 0; | |
4718 | if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT) | |
4719 | return 0; | |
4720 | /* An address with side effects must be reexecuted. */ | |
4721 | switch (code) | |
4722 | { | |
4723 | case POST_INC: | |
4724 | case PRE_INC: | |
4725 | case POST_DEC: | |
4726 | case PRE_DEC: | |
4727 | return 0; | |
4728 | } | |
4729 | goal_mem = 1; | |
4730 | } | |
4731 | else if (CONSTANT_P (goal)) | |
4732 | goal_const = 1; | |
4733 | else if (GET_CODE (goal) == PLUS | |
4734 | && XEXP (goal, 0) == stack_pointer_rtx | |
4735 | && CONSTANT_P (XEXP (goal, 1))) | |
4736 | goal_const = need_stable_sp = 1; | |
4737 | else | |
4738 | return 0; | |
4739 | ||
4740 | /* On some machines, certain regs must always be rejected | |
4741 | because they don't behave the way ordinary registers do. */ | |
4742 | ||
4743 | #ifdef OVERLAPPING_REGNO_P | |
4744 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
4745 | && OVERLAPPING_REGNO_P (regno)) | |
4746 | return 0; | |
4747 | #endif | |
4748 | ||
4749 | /* Scan insns back from INSN, looking for one that copies | |
4750 | a value into or out of GOAL. | |
4751 | Stop and give up if we reach a label. */ | |
4752 | ||
4753 | while (1) | |
4754 | { | |
4755 | p = PREV_INSN (p); | |
4756 | if (p == 0 || GET_CODE (p) == CODE_LABEL) | |
4757 | return 0; | |
4758 | if (GET_CODE (p) == INSN | |
4759 | /* If we don't want spill regs ... */ | |
4760 | && (! (reload_reg_p != 0 && reload_reg_p != (short *)1) | |
4761 | /* ... then ignore insns introduced by reload; they aren't useful | |
4762 | and can cause results in reload_as_needed to be different | |
4763 | from what they were when calculating the need for spills. | |
4764 | If we notice an input-reload insn here, we will reject it below, | |
4765 | but it might hide a usable equivalent. That makes bad code. | |
4766 | It may even abort: perhaps no reg was spilled for this insn | |
4767 | because it was assumed we would find that equivalent. */ | |
4768 | || INSN_UID (p) < reload_first_uid)) | |
4769 | { | |
e8094962 | 4770 | rtx tem; |
eab89b90 RK |
4771 | pat = single_set (p); |
4772 | /* First check for something that sets some reg equal to GOAL. */ | |
4773 | if (pat != 0 | |
4774 | && ((regno >= 0 | |
4775 | && true_regnum (SET_SRC (pat)) == regno | |
4776 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
4777 | || | |
4778 | (regno >= 0 | |
4779 | && true_regnum (SET_DEST (pat)) == regno | |
4780 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
4781 | || | |
4782 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
4783 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
4784 | || (goal_mem | |
4785 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
4786 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
4787 | || (goal_mem | |
4788 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
e8094962 RK |
4789 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
4790 | /* If we are looking for a constant, | |
4791 | and something equivalent to that constant was copied | |
4792 | into a reg, we can use that reg. */ | |
fb3821f7 CH |
4793 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
4794 | NULL_RTX)) | |
e8094962 | 4795 | && rtx_equal_p (XEXP (tem, 0), goal) |
95d3562b | 4796 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
fb3821f7 CH |
4797 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
4798 | NULL_RTX)) | |
e8094962 RK |
4799 | && GET_CODE (SET_DEST (pat)) == REG |
4800 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
4801 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
4802 | && GET_CODE (goal) == CONST_INT | |
4803 | && INTVAL (goal) == CONST_DOUBLE_LOW (XEXP (tem, 0)) | |
4804 | && (valtry = operand_subword (SET_DEST (pat), 0, 0, | |
4805 | VOIDmode)) | |
95d3562b | 4806 | && (valueno = true_regnum (valtry)) >= 0) |
fb3821f7 CH |
4807 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
4808 | NULL_RTX)) | |
e8094962 RK |
4809 | && GET_CODE (SET_DEST (pat)) == REG |
4810 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
4811 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
4812 | && GET_CODE (goal) == CONST_INT | |
4813 | && INTVAL (goal) == CONST_DOUBLE_HIGH (XEXP (tem, 0)) | |
4814 | && (valtry | |
4815 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
95d3562b | 4816 | && (valueno = true_regnum (valtry)) >= 0))) |
eab89b90 RK |
4817 | if (other >= 0 |
4818 | ? valueno == other | |
4819 | : ((unsigned) valueno < FIRST_PSEUDO_REGISTER | |
4820 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
4821 | valueno))) | |
4822 | { | |
4823 | value = valtry; | |
4824 | where = p; | |
4825 | break; | |
4826 | } | |
4827 | } | |
4828 | } | |
4829 | ||
4830 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
4831 | (or copying VALUE into GOAL, if GOAL is also a register). | |
4832 | Now verify that VALUE is really valid. */ | |
4833 | ||
4834 | /* VALUENO is the register number of VALUE; a hard register. */ | |
4835 | ||
4836 | /* Don't try to re-use something that is killed in this insn. We want | |
4837 | to be able to trust REG_UNUSED notes. */ | |
4838 | if (find_reg_note (where, REG_UNUSED, value)) | |
4839 | return 0; | |
4840 | ||
4841 | /* If we propose to get the value from the stack pointer or if GOAL is | |
4842 | a MEM based on the stack pointer, we need a stable SP. */ | |
4843 | if (valueno == STACK_POINTER_REGNUM | |
bfa30b22 RK |
4844 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
4845 | goal))) | |
eab89b90 RK |
4846 | need_stable_sp = 1; |
4847 | ||
4848 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
4849 | if (GET_MODE (value) != mode) | |
4850 | return 0; | |
4851 | ||
4852 | /* Reject VALUE if it was loaded from GOAL | |
4853 | and is also a register that appears in the address of GOAL. */ | |
4854 | ||
4855 | if (goal_mem && value == SET_DEST (PATTERN (where)) | |
bfa30b22 RK |
4856 | && refers_to_regno_for_reload_p (valueno, |
4857 | (valueno | |
4858 | + HARD_REGNO_NREGS (valueno, mode)), | |
fb3821f7 | 4859 | goal, NULL_PTR)) |
eab89b90 RK |
4860 | return 0; |
4861 | ||
4862 | /* Reject registers that overlap GOAL. */ | |
4863 | ||
4864 | if (!goal_mem && !goal_const | |
4865 | && regno + HARD_REGNO_NREGS (regno, mode) > valueno | |
4866 | && regno < valueno + HARD_REGNO_NREGS (valueno, mode)) | |
4867 | return 0; | |
4868 | ||
4869 | /* Reject VALUE if it is one of the regs reserved for reloads. | |
4870 | Reload1 knows how to reuse them anyway, and it would get | |
4871 | confused if we allocated one without its knowledge. | |
4872 | (Now that insns introduced by reload are ignored above, | |
4873 | this case shouldn't happen, but I'm not positive.) */ | |
4874 | ||
4875 | if (reload_reg_p != 0 && reload_reg_p != (short *)1 | |
4876 | && reload_reg_p[valueno] >= 0) | |
4877 | return 0; | |
4878 | ||
4879 | /* On some machines, certain regs must always be rejected | |
4880 | because they don't behave the way ordinary registers do. */ | |
4881 | ||
4882 | #ifdef OVERLAPPING_REGNO_P | |
4883 | if (OVERLAPPING_REGNO_P (valueno)) | |
4884 | return 0; | |
4885 | #endif | |
4886 | ||
4887 | nregs = HARD_REGNO_NREGS (regno, mode); | |
4888 | valuenregs = HARD_REGNO_NREGS (valueno, mode); | |
4889 | ||
4890 | /* Reject VALUE if it is a register being used for an input reload | |
4891 | even if it is not one of those reserved. */ | |
4892 | ||
4893 | if (reload_reg_p != 0) | |
4894 | { | |
4895 | int i; | |
4896 | for (i = 0; i < n_reloads; i++) | |
4897 | if (reload_reg_rtx[i] != 0 && reload_in[i]) | |
4898 | { | |
4899 | int regno1 = REGNO (reload_reg_rtx[i]); | |
4900 | int nregs1 = HARD_REGNO_NREGS (regno1, | |
4901 | GET_MODE (reload_reg_rtx[i])); | |
4902 | if (regno1 < valueno + valuenregs | |
4903 | && regno1 + nregs1 > valueno) | |
4904 | return 0; | |
4905 | } | |
4906 | } | |
4907 | ||
4908 | if (goal_mem) | |
4909 | goal_mem_addr_varies = rtx_addr_varies_p (goal); | |
4910 | ||
4911 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
4912 | until INSN is reached. */ | |
4913 | ||
4914 | p = insn; | |
4915 | while (1) | |
4916 | { | |
4917 | p = PREV_INSN (p); | |
4918 | if (p == where) | |
4919 | return value; | |
4920 | ||
4921 | /* Don't trust the conversion past a function call | |
4922 | if either of the two is in a call-clobbered register, or memory. */ | |
4923 | if (GET_CODE (p) == CALL_INSN | |
4924 | && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
4925 | && call_used_regs[regno]) | |
4926 | || | |
4927 | (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
4928 | && call_used_regs[valueno]) | |
4929 | || | |
4930 | goal_mem | |
4931 | || need_stable_sp)) | |
4932 | return 0; | |
4933 | ||
4934 | #ifdef INSN_CLOBBERS_REGNO_P | |
4935 | if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
4936 | && INSN_CLOBBERS_REGNO_P (p, valueno)) | |
4937 | || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
4938 | && INSN_CLOBBERS_REGNO_P (p, regno))) | |
4939 | return 0; | |
4940 | #endif | |
4941 | ||
4942 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
4943 | { | |
4944 | /* If this insn P stores in either GOAL or VALUE, return 0. | |
4945 | If GOAL is a memory ref and this insn writes memory, return 0. | |
4946 | If GOAL is a memory ref and its address is not constant, | |
4947 | and this insn P changes a register used in GOAL, return 0. */ | |
4948 | ||
4949 | pat = PATTERN (p); | |
4950 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) | |
4951 | { | |
4952 | register rtx dest = SET_DEST (pat); | |
4953 | while (GET_CODE (dest) == SUBREG | |
4954 | || GET_CODE (dest) == ZERO_EXTRACT | |
4955 | || GET_CODE (dest) == SIGN_EXTRACT | |
4956 | || GET_CODE (dest) == STRICT_LOW_PART) | |
4957 | dest = XEXP (dest, 0); | |
4958 | if (GET_CODE (dest) == REG) | |
4959 | { | |
4960 | register int xregno = REGNO (dest); | |
4961 | int xnregs; | |
4962 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
4963 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
4964 | else | |
4965 | xnregs = 1; | |
4966 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
4967 | return 0; | |
4968 | if (xregno < valueno + valuenregs | |
4969 | && xregno + xnregs > valueno) | |
4970 | return 0; | |
4971 | if (goal_mem_addr_varies | |
bfa30b22 | 4972 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
eab89b90 RK |
4973 | return 0; |
4974 | } | |
4975 | else if (goal_mem && GET_CODE (dest) == MEM | |
4976 | && ! push_operand (dest, GET_MODE (dest))) | |
4977 | return 0; | |
4978 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) | |
4979 | return 0; | |
4980 | } | |
4981 | else if (GET_CODE (pat) == PARALLEL) | |
4982 | { | |
4983 | register int i; | |
4984 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
4985 | { | |
4986 | register rtx v1 = XVECEXP (pat, 0, i); | |
4987 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) | |
4988 | { | |
4989 | register rtx dest = SET_DEST (v1); | |
4990 | while (GET_CODE (dest) == SUBREG | |
4991 | || GET_CODE (dest) == ZERO_EXTRACT | |
4992 | || GET_CODE (dest) == SIGN_EXTRACT | |
4993 | || GET_CODE (dest) == STRICT_LOW_PART) | |
4994 | dest = XEXP (dest, 0); | |
4995 | if (GET_CODE (dest) == REG) | |
4996 | { | |
4997 | register int xregno = REGNO (dest); | |
4998 | int xnregs; | |
4999 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
5000 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
5001 | else | |
5002 | xnregs = 1; | |
5003 | if (xregno < regno + nregs | |
5004 | && xregno + xnregs > regno) | |
5005 | return 0; | |
5006 | if (xregno < valueno + valuenregs | |
5007 | && xregno + xnregs > valueno) | |
5008 | return 0; | |
5009 | if (goal_mem_addr_varies | |
bfa30b22 RK |
5010 | && reg_overlap_mentioned_for_reload_p (dest, |
5011 | goal)) | |
eab89b90 RK |
5012 | return 0; |
5013 | } | |
5014 | else if (goal_mem && GET_CODE (dest) == MEM | |
5015 | && ! push_operand (dest, GET_MODE (dest))) | |
5016 | return 0; | |
5017 | else if (need_stable_sp | |
5018 | && push_operand (dest, GET_MODE (dest))) | |
5019 | return 0; | |
5020 | } | |
5021 | } | |
5022 | } | |
5023 | ||
5024 | #ifdef AUTO_INC_DEC | |
5025 | /* If this insn auto-increments or auto-decrements | |
5026 | either regno or valueno, return 0 now. | |
5027 | If GOAL is a memory ref and its address is not constant, | |
5028 | and this insn P increments a register used in GOAL, return 0. */ | |
5029 | { | |
5030 | register rtx link; | |
5031 | ||
5032 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
5033 | if (REG_NOTE_KIND (link) == REG_INC | |
5034 | && GET_CODE (XEXP (link, 0)) == REG) | |
5035 | { | |
5036 | register int incno = REGNO (XEXP (link, 0)); | |
5037 | if (incno < regno + nregs && incno >= regno) | |
5038 | return 0; | |
5039 | if (incno < valueno + valuenregs && incno >= valueno) | |
5040 | return 0; | |
5041 | if (goal_mem_addr_varies | |
bfa30b22 RK |
5042 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
5043 | goal)) | |
eab89b90 RK |
5044 | return 0; |
5045 | } | |
5046 | } | |
5047 | #endif | |
5048 | } | |
5049 | } | |
5050 | } | |
5051 | \f | |
5052 | /* Find a place where INCED appears in an increment or decrement operator | |
5053 | within X, and return the amount INCED is incremented or decremented by. | |
5054 | The value is always positive. */ | |
5055 | ||
5056 | static int | |
5057 | find_inc_amount (x, inced) | |
5058 | rtx x, inced; | |
5059 | { | |
5060 | register enum rtx_code code = GET_CODE (x); | |
5061 | register char *fmt; | |
5062 | register int i; | |
5063 | ||
5064 | if (code == MEM) | |
5065 | { | |
5066 | register rtx addr = XEXP (x, 0); | |
5067 | if ((GET_CODE (addr) == PRE_DEC | |
5068 | || GET_CODE (addr) == POST_DEC | |
5069 | || GET_CODE (addr) == PRE_INC | |
5070 | || GET_CODE (addr) == POST_INC) | |
5071 | && XEXP (addr, 0) == inced) | |
5072 | return GET_MODE_SIZE (GET_MODE (x)); | |
5073 | } | |
5074 | ||
5075 | fmt = GET_RTX_FORMAT (code); | |
5076 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5077 | { | |
5078 | if (fmt[i] == 'e') | |
5079 | { | |
5080 | register int tem = find_inc_amount (XEXP (x, i), inced); | |
5081 | if (tem != 0) | |
5082 | return tem; | |
5083 | } | |
5084 | if (fmt[i] == 'E') | |
5085 | { | |
5086 | register int j; | |
5087 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5088 | { | |
5089 | register int tem = find_inc_amount (XVECEXP (x, i, j), inced); | |
5090 | if (tem != 0) | |
5091 | return tem; | |
5092 | } | |
5093 | } | |
5094 | } | |
5095 | ||
5096 | return 0; | |
5097 | } | |
5098 | \f | |
5099 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ | |
5100 | ||
5101 | int | |
5102 | regno_clobbered_p (regno, insn) | |
5103 | int regno; | |
5104 | rtx insn; | |
5105 | { | |
5106 | if (GET_CODE (PATTERN (insn)) == CLOBBER | |
5107 | && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) | |
5108 | return REGNO (XEXP (PATTERN (insn), 0)) == regno; | |
5109 | ||
5110 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
5111 | { | |
5112 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
5113 | ||
5114 | for (; i >= 0; i--) | |
5115 | { | |
5116 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
5117 | if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG | |
5118 | && REGNO (XEXP (elt, 0)) == regno) | |
5119 | return 1; | |
5120 | } | |
5121 | } | |
5122 | ||
5123 | return 0; | |
5124 | } |