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8c660648 1/* Move registers around to reduce number of move instructions needed.
184bb750 2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
8c660648
JL
3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
18the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19
20
21/* This module looks for cases where matching constraints would force
22 an instruction to need a reload, and this reload would be a register
23 to register move. It then attempts to change the registers used by the
24 instruction to avoid the move instruction. */
25
26#include "config.h"
27#ifdef __STDC__
28#include <stdarg.h>
29#else
30#include <varargs.h>
31#endif
32
670ee920
KG
33/* stdio.h must precede rtl.h for FFS. */
34#include "system.h"
8c660648
JL
35
36#include "rtl.h"
37#include "insn-config.h"
38#include "recog.h"
39#include "output.h"
40#include "reload.h"
41#include "regs.h"
184bb750
R
42#include "hard-reg-set.h"
43#include "flags.h"
44#include "expr.h"
45#include "insn-flags.h"
ddc8bed2 46#include "basic-block.h"
2e107e9e 47#include "toplev.h"
184bb750 48
1230327b
R
49static int optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
50static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
184bb750 51static void optimize_reg_copy_3 PROTO((rtx, rtx, rtx));
1a29f703 52static rtx gen_add3_insn PROTO((rtx, rtx, rtx));
ddc8bed2
MM
53static void copy_src_to_dest PROTO((rtx, rtx, rtx, int));
54static int *regmove_bb_head;
8c660648 55
184bb750
R
56struct match {
57 int with[MAX_RECOG_OPERANDS];
58 enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS];
59 int commutative[MAX_RECOG_OPERANDS];
60 int early_clobber[MAX_RECOG_OPERANDS];
61};
62
d06eab0d 63#ifdef AUTO_INC_DEC
0e05e8ea 64static int try_auto_increment PROTO((rtx, rtx, rtx, rtx, HOST_WIDE_INT, int));
d06eab0d 65#endif
184bb750
R
66static int find_matches PROTO((rtx, struct match *));
67static int fixup_match_1 PROTO((rtx, rtx, rtx, rtx, rtx, int, int, int, FILE *))
68;
69static int reg_is_remote_constant_p PROTO((rtx, rtx, rtx));
8c660648 70static int stable_but_for_p PROTO((rtx, rtx, rtx));
184bb750 71static int loop_depth;
8c660648 72
1a29f703
R
73/* Generate and return an insn body to add r1 and c,
74 storing the result in r0. */
75static rtx
76gen_add3_insn (r0, r1, c)
77 rtx r0, r1, c;
78{
79 int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code;
80
81 if (icode == CODE_FOR_nothing
82 || ! (*insn_operand_predicate[icode][0]) (r0, insn_operand_mode[icode][0])
83 || ! (*insn_operand_predicate[icode][1]) (r1, insn_operand_mode[icode][1])
84 || ! (*insn_operand_predicate[icode][2]) (c, insn_operand_mode[icode][2]))
85 return NULL_RTX;
86
87 return (GEN_FCN (icode) (r0, r1, c));
88}
89
184bb750 90#ifdef AUTO_INC_DEC
8c660648
JL
91
92/* INC_INSN is an instruction that adds INCREMENT to REG.
93 Try to fold INC_INSN as a post/pre in/decrement into INSN.
94 Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src.
95 Return nonzero for success. */
96static int
97try_auto_increment (insn, inc_insn, inc_insn_set, reg, increment, pre)
98 rtx reg, insn, inc_insn ,inc_insn_set;
99 HOST_WIDE_INT increment;
100 int pre;
101{
102 enum rtx_code inc_code;
103
104 rtx pset = single_set (insn);
105 if (pset)
106 {
107 /* Can't use the size of SET_SRC, we might have something like
108 (sign_extend:SI (mem:QI ... */
109 rtx use = find_use_as_address (pset, reg, 0);
110 if (use != 0 && use != (rtx) 1)
111 {
112 int size = GET_MODE_SIZE (GET_MODE (use));
113 if (0
114#ifdef HAVE_POST_INCREMENT
115 || (pre == 0 && (inc_code = POST_INC, increment == size))
116#endif
117#ifdef HAVE_PRE_INCREMENT
118 || (pre == 1 && (inc_code = PRE_INC, increment == size))
119#endif
120#ifdef HAVE_POST_DECREMENT
121 || (pre == 0 && (inc_code = POST_DEC, increment == -size))
122#endif
123#ifdef HAVE_PRE_DECREMENT
124 || (pre == 1 && (inc_code = PRE_DEC, increment == -size))
125#endif
184bb750
R
126 )
127 {
128 if (inc_insn_set)
129 validate_change
130 (inc_insn,
131 &SET_SRC (inc_insn_set),
8c660648 132 XEXP (SET_SRC (inc_insn_set), 0), 1);
184bb750 133 validate_change (insn, &XEXP (use, 0),
38a448ca 134 gen_rtx_fmt_e (inc_code, Pmode, reg), 1);
184bb750
R
135 if (apply_change_group ())
136 {
137 REG_NOTES (insn)
38a448ca
RH
138 = gen_rtx_EXPR_LIST (REG_INC,
139 reg, REG_NOTES (insn));
184bb750
R
140 if (! inc_insn_set)
141 {
142 PUT_CODE (inc_insn, NOTE);
143 NOTE_LINE_NUMBER (inc_insn) = NOTE_INSN_DELETED;
144 NOTE_SOURCE_FILE (inc_insn) = 0;
145 }
8c660648 146 return 1;
184bb750
R
147 }
148 }
149 }
150 }
151 return 0;
152}
153#endif /* AUTO_INC_DEC */
154
155static int *regno_src_regno;
156
157/* Indicate how good a choice REG (which appears as a source) is to replace
158 a destination register with. The higher the returned value, the better
159 the choice. The main objective is to avoid using a register that is
160 a candidate for tying to a hard register, since the output might in
161 turn be a candidate to be tied to a different hard register. */
162int
163replacement_quality(reg)
164 rtx reg;
165{
166 int src_regno;
167
168 /* Bad if this isn't a register at all. */
169 if (GET_CODE (reg) != REG)
170 return 0;
171
172 /* If this register is not meant to get a hard register,
173 it is a poor choice. */
174 if (REG_LIVE_LENGTH (REGNO (reg)) < 0)
175 return 0;
176
177 src_regno = regno_src_regno[REGNO (reg)];
178
179 /* If it was not copied from another register, it is fine. */
180 if (src_regno < 0)
181 return 3;
182
183 /* Copied from a hard register? */
184 if (src_regno < FIRST_PSEUDO_REGISTER)
185 return 1;
186
187 /* Copied from a pseudo register - not as bad as from a hard register,
188 yet still cumbersome, since the register live length will be lengthened
189 when the registers get tied. */
190 return 2;
191}
192
1230327b
R
193/* INSN is a copy from SRC to DEST, both registers, and SRC does not die
194 in INSN.
195
196 Search forward to see if SRC dies before either it or DEST is modified,
197 but don't scan past the end of a basic block. If so, we can replace SRC
198 with DEST and let SRC die in INSN.
199
200 This will reduce the number of registers live in that range and may enable
201 DEST to be tied to SRC, thus often saving one register in addition to a
202 register-register copy. */
203
204static int
205optimize_reg_copy_1 (insn, dest, src)
206 rtx insn;
207 rtx dest;
208 rtx src;
209{
210 rtx p, q;
211 rtx note;
212 rtx dest_death = 0;
213 int sregno = REGNO (src);
214 int dregno = REGNO (dest);
215
216 /* We don't want to mess with hard regs if register classes are small. */
217 if (sregno == dregno
218 || (SMALL_REGISTER_CLASSES
219 && (sregno < FIRST_PSEUDO_REGISTER
220 || dregno < FIRST_PSEUDO_REGISTER))
221 /* We don't see all updates to SP if they are in an auto-inc memory
222 reference, so we must disallow this optimization on them. */
223 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
224 return 0;
225
226 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
227 {
228 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
229 || (GET_CODE (p) == NOTE
230 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
231 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
232 break;
233
7bf825d2
JW
234 /* ??? We can't scan past the end of a basic block without updating
235 the register lifetime info (REG_DEAD/basic_block_live_at_start).
236 A CALL_INSN might be the last insn of a basic block, if it is inside
237 an EH region. There is no easy way to tell, so we just always break
238 when we see a CALL_INSN if flag_exceptions is nonzero. */
239 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
240 break;
241
1230327b
R
242 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
243 continue;
244
245 if (reg_set_p (src, p) || reg_set_p (dest, p)
246 /* Don't change a USE of a register. */
247 || (GET_CODE (PATTERN (p)) == USE
248 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
249 break;
250
251 /* See if all of SRC dies in P. This test is slightly more
252 conservative than it needs to be. */
253 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
254 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
255 {
256 int failed = 0;
257 int length = 0;
258 int d_length = 0;
259 int n_calls = 0;
260 int d_n_calls = 0;
261
262 /* We can do the optimization. Scan forward from INSN again,
263 replacing regs as we go. Set FAILED if a replacement can't
264 be done. In that case, we can't move the death note for SRC.
265 This should be rare. */
266
267 /* Set to stop at next insn. */
268 for (q = next_real_insn (insn);
269 q != next_real_insn (p);
270 q = next_real_insn (q))
271 {
272 if (reg_overlap_mentioned_p (src, PATTERN (q)))
273 {
274 /* If SRC is a hard register, we might miss some
275 overlapping registers with validate_replace_rtx,
276 so we would have to undo it. We can't if DEST is
277 present in the insn, so fail in that combination
278 of cases. */
279 if (sregno < FIRST_PSEUDO_REGISTER
280 && reg_mentioned_p (dest, PATTERN (q)))
281 failed = 1;
282
283 /* Replace all uses and make sure that the register
284 isn't still present. */
285 else if (validate_replace_rtx (src, dest, q)
286 && (sregno >= FIRST_PSEUDO_REGISTER
287 || ! reg_overlap_mentioned_p (src,
288 PATTERN (q))))
289 {
290 /* We assume that a register is used exactly once per
7b31b7d9
JL
291 insn in the REG_N_REFS updates below. If this is not
292 correct, no great harm is done.
293
294
295 We do not undo this substitution if something later
296 fails. Therefore, we must update the other REG_N_*
297 counters now to keep them accurate. */
1230327b 298 if (sregno >= FIRST_PSEUDO_REGISTER)
7b31b7d9
JL
299 {
300 REG_N_REFS (sregno) -= loop_depth;
301
302 if (REG_LIVE_LENGTH (sregno) >= 0)
303 {
304 REG_LIVE_LENGTH (sregno) -= length;
305 /* REG_LIVE_LENGTH is only an approximation after
306 combine if sched is not run, so make sure that
307 we still have a reasonable value. */
308 if (REG_LIVE_LENGTH (sregno) < 2)
309 REG_LIVE_LENGTH (sregno) = 2;
310 }
311
312 REG_N_CALLS_CROSSED (sregno) -= n_calls;
313 }
314
1230327b 315 if (dregno >= FIRST_PSEUDO_REGISTER)
7b31b7d9
JL
316 {
317 REG_N_REFS (dregno) += loop_depth;
318
319 if (REG_LIVE_LENGTH (dregno) >= 0)
320 REG_LIVE_LENGTH (dregno) += d_length;
321
322 REG_N_CALLS_CROSSED (dregno) += d_n_calls;
323 }
324
325 /* We've done a substitution, clear the counters. */
326 length = 0;
327 d_length = 0;
328 n_calls = 0;
329 d_n_calls = 0;
1230327b
R
330 }
331 else
332 {
333 validate_replace_rtx (dest, src, q);
334 failed = 1;
335 }
336 }
337
338 /* Count the insns and CALL_INSNs passed. If we passed the
339 death note of DEST, show increased live length. */
340 length++;
341 if (dest_death)
342 d_length++;
343
344 /* If the insn in which SRC dies is a CALL_INSN, don't count it
345 as a call that has been crossed. Otherwise, count it. */
346 if (q != p && GET_CODE (q) == CALL_INSN)
347 {
348 n_calls++;
349 if (dest_death)
350 d_n_calls++;
351 }
352
353 /* If DEST dies here, remove the death note and save it for
354 later. Make sure ALL of DEST dies here; again, this is
355 overly conservative. */
356 if (dest_death == 0
357 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0)
358 {
359 if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest))
360 failed = 1, dest_death = 0;
361 else
362 remove_note (q, dest_death);
363 }
364 }
365
366 if (! failed)
367 {
368 if (sregno >= FIRST_PSEUDO_REGISTER)
369 {
370 if (REG_LIVE_LENGTH (sregno) >= 0)
371 {
372 REG_LIVE_LENGTH (sregno) -= length;
373 /* REG_LIVE_LENGTH is only an approximation after
374 combine if sched is not run, so make sure that we
375 still have a reasonable value. */
376 if (REG_LIVE_LENGTH (sregno) < 2)
377 REG_LIVE_LENGTH (sregno) = 2;
378 }
379
380 REG_N_CALLS_CROSSED (sregno) -= n_calls;
381 }
382
383 if (dregno >= FIRST_PSEUDO_REGISTER)
384 {
385 if (REG_LIVE_LENGTH (dregno) >= 0)
386 REG_LIVE_LENGTH (dregno) += d_length;
387
388 REG_N_CALLS_CROSSED (dregno) += d_n_calls;
389 }
390
391 /* Move death note of SRC from P to INSN. */
392 remove_note (p, note);
393 XEXP (note, 1) = REG_NOTES (insn);
394 REG_NOTES (insn) = note;
395 }
396
397 /* Put death note of DEST on P if we saw it die. */
398 if (dest_death)
399 {
400 XEXP (dest_death, 1) = REG_NOTES (p);
401 REG_NOTES (p) = dest_death;
402 }
403
404 return ! failed;
405 }
406
407 /* If SRC is a hard register which is set or killed in some other
408 way, we can't do this optimization. */
409 else if (sregno < FIRST_PSEUDO_REGISTER
410 && dead_or_set_p (p, src))
411 break;
412 }
413 return 0;
414}
415\f
416/* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
417 a sequence of insns that modify DEST followed by an insn that sets
418 SRC to DEST in which DEST dies, with no prior modification of DEST.
419 (There is no need to check if the insns in between actually modify
420 DEST. We should not have cases where DEST is not modified, but
421 the optimization is safe if no such modification is detected.)
422 In that case, we can replace all uses of DEST, starting with INSN and
423 ending with the set of SRC to DEST, with SRC. We do not do this
424 optimization if a CALL_INSN is crossed unless SRC already crosses a
425 call or if DEST dies before the copy back to SRC.
426
427 It is assumed that DEST and SRC are pseudos; it is too complicated to do
428 this for hard registers since the substitutions we may make might fail. */
429
430static void
431optimize_reg_copy_2 (insn, dest, src)
432 rtx insn;
433 rtx dest;
434 rtx src;
435{
436 rtx p, q;
437 rtx set;
438 int sregno = REGNO (src);
439 int dregno = REGNO (dest);
440
441 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
442 {
443 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
444 || (GET_CODE (p) == NOTE
445 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
446 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
447 break;
448
7bf825d2
JW
449 /* ??? We can't scan past the end of a basic block without updating
450 the register lifetime info (REG_DEAD/basic_block_live_at_start).
451 A CALL_INSN might be the last insn of a basic block, if it is inside
452 an EH region. There is no easy way to tell, so we just always break
453 when we see a CALL_INSN if flag_exceptions is nonzero. */
454 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
455 break;
456
1230327b
R
457 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
458 continue;
459
460 set = single_set (p);
461 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
462 && find_reg_note (p, REG_DEAD, dest))
463 {
464 /* We can do the optimization. Scan forward from INSN again,
465 replacing regs as we go. */
466
467 /* Set to stop at next insn. */
468 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
469 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
470 {
471 if (reg_mentioned_p (dest, PATTERN (q)))
472 {
473 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
474
475 /* We assume that a register is used exactly once per
476 insn in the updates below. If this is not correct,
477 no great harm is done. */
478 REG_N_REFS (dregno) -= loop_depth;
479 REG_N_REFS (sregno) += loop_depth;
480 }
481
482
483 if (GET_CODE (q) == CALL_INSN)
484 {
485 REG_N_CALLS_CROSSED (dregno)--;
486 REG_N_CALLS_CROSSED (sregno)++;
487 }
488 }
489
490 remove_note (p, find_reg_note (p, REG_DEAD, dest));
491 REG_N_DEATHS (dregno)--;
492 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
493 REG_N_DEATHS (sregno)--;
494 return;
495 }
496
497 if (reg_set_p (src, p)
498 || find_reg_note (p, REG_DEAD, dest)
499 || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0))
500 break;
501 }
502}
184bb750
R
503/* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST.
504 Look if SRC dies there, and if it is only set once, by loading
505 it from memory. If so, try to encorporate the zero/sign extension
506 into the memory read, change SRC to the mode of DEST, and alter
507 the remaining accesses to use the appropriate SUBREG. This allows
508 SRC and DEST to be tied later. */
509static void
510optimize_reg_copy_3 (insn, dest, src)
511 rtx insn;
512 rtx dest;
513 rtx src;
514{
515 rtx src_reg = XEXP (src, 0);
516 int src_no = REGNO (src_reg);
517 int dst_no = REGNO (dest);
518 rtx p, set, subreg;
519 enum machine_mode old_mode;
520
521 if (src_no < FIRST_PSEUDO_REGISTER
522 || dst_no < FIRST_PSEUDO_REGISTER
523 || ! find_reg_note (insn, REG_DEAD, src_reg)
524 || REG_N_SETS (src_no) != 1)
525 return;
526 for (p = PREV_INSN (insn); ! reg_set_p (src_reg, p); p = PREV_INSN (p))
527 {
7bf825d2
JW
528 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
529 || (GET_CODE (p) == NOTE
530 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
531 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
532 return;
533
534 /* ??? We can't scan past the end of a basic block without updating
535 the register lifetime info (REG_DEAD/basic_block_live_at_start).
536 A CALL_INSN might be the last insn of a basic block, if it is inside
537 an EH region. There is no easy way to tell, so we just always break
538 when we see a CALL_INSN if flag_exceptions is nonzero. */
539 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
540 return;
541
184bb750
R
542 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
543 continue;
184bb750
R
544 }
545 if (! (set = single_set (p))
546 || GET_CODE (SET_SRC (set)) != MEM
547 || SET_DEST (set) != src_reg)
548 return;
549 old_mode = GET_MODE (src_reg);
550 PUT_MODE (src_reg, GET_MODE (src));
551 XEXP (src, 0) = SET_SRC (set);
e757da5e
JL
552
553 /* Include this change in the group so that it's easily undone if
554 one of the changes in the group is invalid. */
555 validate_change (p, &SET_SRC (set), src, 1);
556
557 /* Now walk forward making additional replacements. We want to be able
558 to undo all the changes if a later substitution fails. */
38a448ca 559 subreg = gen_rtx_SUBREG (old_mode, src_reg, 0);
184bb750
R
560 while (p = NEXT_INSN (p), p != insn)
561 {
562 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
563 continue;
e757da5e
JL
564
565 /* Make a tenative change. */
566 validate_replace_rtx_group (src_reg, subreg, p);
567 }
568
569 validate_replace_rtx_group (src, src_reg, insn);
570
571 /* Now see if all the changes are valid. */
572 if (! apply_change_group ())
573 {
574 /* One or more changes were no good. Back out everything. */
575 PUT_MODE (src_reg, old_mode);
576 XEXP (src, 0) = src_reg;
184bb750 577 }
184bb750
R
578}
579
ddc8bed2
MM
580\f
581/* If we were not able to update the users of src to use dest directly, try
582 instead moving the value to dest directly before the operation. */
583
cab634f2 584static void
ddc8bed2
MM
585copy_src_to_dest (insn, src, dest, loop_depth)
586 rtx insn;
587 rtx src;
588 rtx dest;
29a4c5ed 589 int loop_depth;
ddc8bed2
MM
590{
591 rtx seq;
592 rtx link;
593 rtx next;
594 rtx set;
595 rtx move_insn;
596 rtx *p_insn_notes;
597 rtx *p_move_notes;
ddc8bed2
MM
598 int src_regno;
599 int dest_regno;
600 int bb;
601 int insn_uid;
602 int move_uid;
603
604 /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant
605 or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is
606 parameter when there is no frame pointer that is not allocated a register.
607 For now, we just reject them, rather than incrementing the live length. */
608
3ac3da71
MM
609 if (GET_CODE (src) == REG
610 && REG_LIVE_LENGTH (REGNO (src)) > 0
611 && GET_CODE (dest) == REG
612 && REG_LIVE_LENGTH (REGNO (dest)) > 0
ddc8bed2
MM
613 && (set = single_set (insn)) != NULL_RTX
614 && !reg_mentioned_p (dest, SET_SRC (set))
ddc8bed2
MM
615 && validate_replace_rtx (src, dest, insn))
616 {
617 /* Generate the src->dest move. */
618 start_sequence ();
619 emit_move_insn (dest, src);
620 seq = gen_sequence ();
621 end_sequence ();
622 emit_insn_before (seq, insn);
623 move_insn = PREV_INSN (insn);
624 p_move_notes = &REG_NOTES (move_insn);
625 p_insn_notes = &REG_NOTES (insn);
626
627 /* Move any notes mentioning src to the move instruction */
628 for (link = REG_NOTES (insn); link != NULL_RTX; link = next)
629 {
630 next = XEXP (link, 1);
631 if (XEXP (link, 0) == src)
632 {
633 *p_move_notes = link;
634 p_move_notes = &XEXP (link, 1);
635 }
636 else
637 {
638 *p_insn_notes = link;
639 p_insn_notes = &XEXP (link, 1);
640 }
641 }
642
643 *p_move_notes = NULL_RTX;
644 *p_insn_notes = NULL_RTX;
645
646 /* Is the insn the head of a basic block? If so extend it */
647 insn_uid = INSN_UID (insn);
648 move_uid = INSN_UID (move_insn);
649 bb = regmove_bb_head[insn_uid];
650 if (bb >= 0)
651 {
652 basic_block_head[bb] = move_insn;
653 regmove_bb_head[insn_uid] = -1;
654 }
655
656 /* Update the various register tables. */
657 dest_regno = REGNO (dest);
658 REG_N_SETS (dest_regno) += loop_depth;
659 REG_N_REFS (dest_regno) += loop_depth;
660 REG_LIVE_LENGTH (dest_regno)++;
661 if (REGNO_FIRST_UID (dest_regno) == insn_uid)
662 REGNO_FIRST_UID (dest_regno) = move_uid;
663
664 src_regno = REGNO (src);
665 if (! find_reg_note (move_insn, REG_DEAD, src))
666 REG_LIVE_LENGTH (src_regno)++;
667
668 if (REGNO_FIRST_UID (src_regno) == insn_uid)
669 REGNO_FIRST_UID (src_regno) = move_uid;
670
671 if (REGNO_LAST_UID (src_regno) == insn_uid)
672 REGNO_LAST_UID (src_regno) = move_uid;
673
674 if (REGNO_LAST_NOTE_UID (src_regno) == insn_uid)
675 REGNO_LAST_NOTE_UID (src_regno) = move_uid;
676 }
677}
678
679\f
184bb750
R
680/* Return whether REG is set in only one location, and is set to a
681 constant, but is set in a different basic block from INSN (an
682 instructions which uses REG). In this case REG is equivalent to a
683 constant, and we don't want to break that equivalence, because that
684 may increase register pressure and make reload harder. If REG is
685 set in the same basic block as INSN, we don't worry about it,
686 because we'll probably need a register anyhow (??? but what if REG
687 is used in a different basic block as well as this one?). FIRST is
688 the first insn in the function. */
689
690static int
691reg_is_remote_constant_p (reg, insn, first)
692 rtx reg;
693 rtx insn;
694 rtx first;
695{
696 register rtx p;
697
698 if (REG_N_SETS (REGNO (reg)) != 1)
699 return 0;
700
701 /* Look for the set. */
702 for (p = LOG_LINKS (insn); p; p = XEXP (p, 1))
703 {
704 rtx s;
705
706 if (REG_NOTE_KIND (p) != 0)
707 continue;
708 s = single_set (XEXP (p, 0));
709 if (s != 0
710 && GET_CODE (SET_DEST (s)) == REG
711 && REGNO (SET_DEST (s)) == REGNO (reg))
712 {
713 /* The register is set in the same basic block. */
714 return 0;
715 }
716 }
717
718 for (p = first; p && p != insn; p = NEXT_INSN (p))
719 {
720 rtx s;
721
722 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
723 continue;
724 s = single_set (p);
725 if (s != 0
726 && GET_CODE (SET_DEST (s)) == REG
727 && REGNO (SET_DEST (s)) == REGNO (reg))
728 {
729 /* This is the instruction which sets REG. If there is a
730 REG_EQUAL note, then REG is equivalent to a constant. */
731 if (find_reg_note (p, REG_EQUAL, NULL_RTX))
732 return 1;
733 return 0;
734 }
735 }
736
737 return 0;
738}
739
b1a7d591
JW
740/* INSN is adding a CONST_INT to a REG. We search backwards looking for
741 another add immediate instruction with the same source and dest registers,
742 and if we find one, we change INSN to an increment, and return 1. If
743 no changes are made, we return 0.
744
745 This changes
746 (set (reg100) (plus reg1 offset1))
747 ...
748 (set (reg100) (plus reg1 offset2))
749 to
750 (set (reg100) (plus reg1 offset1))
751 ...
752 (set (reg100) (plus reg100 offset2-offset1)) */
753
754/* ??? What does this comment mean? */
184bb750
R
755/* cse disrupts preincrement / postdecrement squences when it finds a
756 hard register as ultimate source, like the frame pointer. */
b1a7d591 757
7bf825d2
JW
758int
759fixup_match_2 (insn, dst, src, offset, regmove_dump_file)
184bb750
R
760 rtx insn, dst, src, offset;
761 FILE *regmove_dump_file;
762{
763 rtx p, dst_death = 0;
764 int length, num_calls = 0;
765
766 /* If SRC dies in INSN, we'd have to move the death note. This is
767 considered to be very unlikely, so we just skip the optimization
768 in this case. */
769 if (find_regno_note (insn, REG_DEAD, REGNO (src)))
770 return 0;
771
772 /* Scan backward to find the first instruction that sets DST. */
773
774 for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p))
775 {
776 rtx pset;
777
778 if (GET_CODE (p) == CODE_LABEL
779 || GET_CODE (p) == JUMP_INSN
780 || (GET_CODE (p) == NOTE
781 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
782 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
783 break;
784
7bf825d2
JW
785 /* ??? We can't scan past the end of a basic block without updating
786 the register lifetime info (REG_DEAD/basic_block_live_at_start).
787 A CALL_INSN might be the last insn of a basic block, if it is inside
788 an EH region. There is no easy way to tell, so we just always break
789 when we see a CALL_INSN if flag_exceptions is nonzero. */
790 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
791 break;
792
184bb750
R
793 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
794 continue;
795
7bf825d2
JW
796 if (find_regno_note (p, REG_DEAD, REGNO (dst)))
797 dst_death = p;
798 if (! dst_death)
799 length++;
184bb750
R
800
801 pset = single_set (p);
802 if (pset && SET_DEST (pset) == dst
803 && GET_CODE (SET_SRC (pset)) == PLUS
804 && XEXP (SET_SRC (pset), 0) == src
805 && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT)
806 {
807 HOST_WIDE_INT newconst
808 = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1));
1a29f703
R
809 rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst));
810
811 if (add && validate_change (insn, &PATTERN (insn), add, 0))
184bb750
R
812 {
813 /* Remove the death note for DST from DST_DEATH. */
814 if (dst_death)
815 {
816 remove_death (REGNO (dst), dst_death);
817 REG_LIVE_LENGTH (REGNO (dst)) += length;
818 REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls;
819 }
820
821 REG_N_REFS (REGNO (dst)) += loop_depth;
822 REG_N_REFS (REGNO (src)) -= loop_depth;
823
824 if (regmove_dump_file)
825 fprintf (regmove_dump_file,
826 "Fixed operand of insn %d.\n",
827 INSN_UID (insn));
828
829#ifdef AUTO_INC_DEC
830 for (p = PREV_INSN (insn); p; p = PREV_INSN (p))
831 {
832 if (GET_CODE (p) == CODE_LABEL
833 || GET_CODE (p) == JUMP_INSN
834 || (GET_CODE (p) == NOTE
835 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
836 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
837 break;
e27a5106
JL
838 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
839 continue;
184bb750
R
840 if (reg_overlap_mentioned_p (dst, PATTERN (p)))
841 {
842 if (try_auto_increment (p, insn, 0, dst, newconst, 0))
843 return 1;
844 break;
845 }
846 }
847 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
848 {
849 if (GET_CODE (p) == CODE_LABEL
850 || GET_CODE (p) == JUMP_INSN
851 || (GET_CODE (p) == NOTE
852 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
853 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
854 break;
8543c01e
R
855 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
856 continue;
184bb750
R
857 if (reg_overlap_mentioned_p (dst, PATTERN (p)))
858 {
859 try_auto_increment (p, insn, 0, dst, newconst, 1);
860 break;
861 }
862 }
863#endif
864 return 1;
865 }
8c660648 866 }
184bb750
R
867
868 if (reg_set_p (dst, PATTERN (p)))
869 break;
870
871 /* If we have passed a call instruction, and the
872 pseudo-reg SRC is not already live across a call,
873 then don't perform the optimization. */
874 /* reg_set_p is overly conservative for CALL_INSNS, thinks that all
875 hard regs are clobbered. Thus, we only use it for src for
876 non-call insns. */
877 if (GET_CODE (p) == CALL_INSN)
878 {
879 if (! dst_death)
880 num_calls++;
881
882 if (REG_N_CALLS_CROSSED (REGNO (src)) == 0)
883 break;
884
885 if (call_used_regs [REGNO (dst)]
886 || find_reg_fusage (p, CLOBBER, dst))
887 break;
888 }
889 else if (reg_set_p (src, PATTERN (p)))
890 break;
8c660648 891 }
184bb750 892
8c660648
JL
893 return 0;
894}
8c660648
JL
895
896void
897regmove_optimize (f, nregs, regmove_dump_file)
898 rtx f;
899 int nregs;
900 FILE *regmove_dump_file;
901{
8c660648 902 rtx insn;
184bb750 903 struct match match;
8c660648 904 int pass;
184bb750 905 int maxregnum = max_reg_num (), i;
ddc8bed2 906 rtx copy_src, copy_dst;
184bb750
R
907
908 regno_src_regno = (int *)alloca (sizeof *regno_src_regno * maxregnum);
909 for (i = maxregnum; --i >= 0; ) regno_src_regno[i] = -1;
8c660648 910
ddc8bed2 911 regmove_bb_head = (int *)alloca (sizeof (int) * (get_max_uid () + 1));
9616dd8d 912 for (i = get_max_uid (); i >= 0; i--) regmove_bb_head[i] = -1;
ddc8bed2
MM
913 for (i = 0; i < n_basic_blocks; i++)
914 regmove_bb_head[INSN_UID (basic_block_head[i])] = i;
915
8c660648
JL
916 /* A forward/backward pass. Replace output operands with input operands. */
917
184bb750
R
918 loop_depth = 1;
919
920 for (pass = 0; pass <= 2; pass++)
8c660648 921 {
184bb750
R
922 if (! flag_regmove && pass >= flag_expensive_optimizations)
923 return;
924
8c660648
JL
925 if (regmove_dump_file)
926 fprintf (regmove_dump_file, "Starting %s pass...\n",
927 pass ? "backward" : "forward");
928
929 for (insn = pass ? get_last_insn () : f; insn;
930 insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn))
931 {
184bb750
R
932 rtx set;
933 int insn_code_number;
934 int operand_number, match_number;
935
936 if (GET_CODE (insn) == NOTE)
8c660648 937 {
184bb750
R
938 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
939 loop_depth++;
940 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
941 loop_depth--;
942 }
8c660648 943
184bb750
R
944 set = single_set (insn);
945 if (! set)
946 continue;
8c660648 947
184bb750
R
948 if (flag_expensive_optimizations && ! pass
949 && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND
950 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND)
951 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
952 && GET_CODE (SET_DEST(set)) == REG)
953 optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set));
954
955 if (flag_expensive_optimizations && ! pass
956 && GET_CODE (SET_SRC (set)) == REG
957 && GET_CODE (SET_DEST(set)) == REG)
958 {
959 /* If this is a register-register copy where SRC is not dead,
960 see if we can optimize it. If this optimization succeeds,
961 it will become a copy where SRC is dead. */
962 if ((find_reg_note (insn, REG_DEAD, SET_SRC (set))
963 || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set)))
964 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER)
8c660648 965 {
184bb750
R
966 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
967 if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
968 optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set));
969 if (regno_src_regno[REGNO (SET_DEST (set))] < 0
970 && SET_SRC (set) != SET_DEST (set))
8c660648 971 {
184bb750
R
972 int srcregno = REGNO (SET_SRC(set));
973 if (regno_src_regno[srcregno] >= 0)
974 srcregno = regno_src_regno[srcregno];
975 regno_src_regno[REGNO (SET_DEST (set))] = srcregno;
8c660648
JL
976 }
977 }
184bb750
R
978 }
979#ifdef REGISTER_CONSTRAINTS
980 insn_code_number
981 = find_matches (insn, &match);
982
983 if (insn_code_number < 0)
984 continue;
985
986 /* Now scan through the operands looking for a source operand
987 which is supposed to match the destination operand.
988 Then scan forward for an instruction which uses the dest
989 operand.
990 If it dies there, then replace the dest in both operands with
991 the source operand. */
992
993 for (operand_number = 0;
994 operand_number < insn_n_operands[insn_code_number];
995 operand_number++)
996 {
5e9defae 997 rtx src, dst, src_subreg;
184bb750
R
998 enum reg_class src_class, dst_class;
999
1000 match_number = match.with[operand_number];
1001
1002 /* Nothing to do if the two operands aren't supposed to match. */
1003 if (match_number < 0)
1004 continue;
1005
1006 src = recog_operand[operand_number];
1007 dst = recog_operand[match_number];
1008
1009 if (GET_CODE (src) != REG)
1010 continue;
1011
1012 src_subreg = src;
1013 if (GET_CODE (dst) == SUBREG
1014 && GET_MODE_SIZE (GET_MODE (dst))
1015 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst))))
1016 {
1017 src_subreg
38a448ca
RH
1018 = gen_rtx_SUBREG (GET_MODE (SUBREG_REG (dst)),
1019 src, SUBREG_WORD (dst));
184bb750
R
1020 dst = SUBREG_REG (dst);
1021 }
1022 if (GET_CODE (dst) != REG
1023 || REGNO (dst) < FIRST_PSEUDO_REGISTER)
1024 continue;
1025
1026 if (REGNO (src) < FIRST_PSEUDO_REGISTER)
1027 {
1028 if (match.commutative[operand_number] < operand_number)
1029 regno_src_regno[REGNO (dst)] = REGNO (src);
1030 continue;
1031 }
1032
1033 if (REG_LIVE_LENGTH (REGNO (src)) < 0)
1034 continue;
1035
1036 /* operand_number/src must be a read-only operand, and
1037 match_operand/dst must be a write-only operand. */
1038 if (match.use[operand_number] != READ
1039 || match.use[match_number] != WRITE)
1040 continue;
1041
1042 if (match.early_clobber[match_number]
1043 && count_occurrences (PATTERN (insn), src) > 1)
1044 continue;
1045
1046 /* Make sure match_operand is the destination. */
1047 if (recog_operand[match_number] != SET_DEST (set))
1048 continue;
1049
1050 /* If the operands already match, then there is nothing to do. */
1051 /* But in the commutative case, we might find a better match. */
1052 if (operands_match_p (src, dst)
1053 || (match.commutative[operand_number] >= 0
1054 && operands_match_p (recog_operand[match.commutative
1055 [operand_number]], dst)
1056 && (replacement_quality (recog_operand[match.commutative
1057 [operand_number]])
1058 >= replacement_quality (src))))
1059 continue;
1060
1061 src_class = reg_preferred_class (REGNO (src));
1062 dst_class = reg_preferred_class (REGNO (dst));
1063 if (src_class != dst_class
1064 && (! reg_class_subset_p (src_class, dst_class)
1065 || CLASS_LIKELY_SPILLED_P (src_class))
1066 && (! reg_class_subset_p (dst_class, src_class)
1067 || CLASS_LIKELY_SPILLED_P (dst_class)))
1068 continue;
1069
1070 if (fixup_match_1 (insn, set, src, src_subreg, dst, pass,
1071 operand_number, match_number,
1072 regmove_dump_file))
1073 break;
8c660648
JL
1074 }
1075 }
1076 }
1077
1078 /* A backward pass. Replace input operands with output operands. */
1079
1080 if (regmove_dump_file)
1081 fprintf (regmove_dump_file, "Starting backward pass...\n");
1082
184bb750
R
1083 loop_depth = 1;
1084
8c660648
JL
1085 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
1086 {
184bb750
R
1087 if (GET_CODE (insn) == NOTE)
1088 {
1089 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1090 loop_depth++;
1091 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1092 loop_depth--;
1093 }
8c660648
JL
1094 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1095 {
184bb750 1096 int insn_code_number = find_matches (insn, &match);
8c660648 1097 int operand_number, match_number;
ddc8bed2 1098 int success = 0;
8c660648
JL
1099
1100 if (insn_code_number < 0)
1101 continue;
1102
8c660648
JL
1103 /* Now scan through the operands looking for a destination operand
1104 which is supposed to match a source operand.
1105 Then scan backward for an instruction which sets the source
1106 operand. If safe, then replace the source operand with the
1107 dest operand in both instructions. */
1108
ddc8bed2
MM
1109 copy_src = NULL_RTX;
1110 copy_dst = NULL_RTX;
8c660648
JL
1111 for (operand_number = 0;
1112 operand_number < insn_n_operands[insn_code_number];
1113 operand_number++)
1114 {
184bb750
R
1115 rtx set, p, src, dst;
1116 rtx src_note, dst_note;
184bb750
R
1117 int num_calls = 0;
1118 enum reg_class src_class, dst_class;
1119 int length;
8c660648 1120
184bb750 1121 match_number = match.with[operand_number];
8c660648 1122
184bb750
R
1123 /* Nothing to do if the two operands aren't supposed to match. */
1124 if (match_number < 0)
1125 continue;
8c660648 1126
184bb750
R
1127 dst = recog_operand[match_number];
1128 src = recog_operand[operand_number];
8c660648 1129
184bb750
R
1130 if (GET_CODE (src) != REG)
1131 continue;
8c660648 1132
184bb750
R
1133 if (GET_CODE (dst) != REG
1134 || REGNO (dst) < FIRST_PSEUDO_REGISTER
1135 || REG_LIVE_LENGTH (REGNO (dst)) < 0)
1136 continue;
8c660648 1137
184bb750
R
1138 /* If the operands already match, then there is nothing to do. */
1139 if (operands_match_p (src, dst)
1140 || (match.commutative[operand_number] >= 0
1141 && operands_match_p (recog_operand[match.commutative[operand_number]], dst)))
1142 continue;
8c660648 1143
184bb750
R
1144 set = single_set (insn);
1145 if (! set)
1146 continue;
8c660648 1147
184bb750
R
1148 /* match_number/dst must be a write-only operand, and
1149 operand_operand/src must be a read-only operand. */
1150 if (match.use[operand_number] != READ
1151 || match.use[match_number] != WRITE)
1152 continue;
8c660648 1153
184bb750
R
1154 if (match.early_clobber[match_number]
1155 && count_occurrences (PATTERN (insn), src) > 1)
1156 continue;
8c660648 1157
184bb750
R
1158 /* Make sure match_number is the destination. */
1159 if (recog_operand[match_number] != SET_DEST (set))
1160 continue;
8c660648 1161
184bb750
R
1162 if (REGNO (src) < FIRST_PSEUDO_REGISTER)
1163 {
1164 if (GET_CODE (SET_SRC (set)) == PLUS
1165 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT
1166 && XEXP (SET_SRC (set), 0) == src
1167 && fixup_match_2 (insn, dst, src,
1168 XEXP (SET_SRC (set), 1),
1169 regmove_dump_file))
1170 break;
1171 continue;
1172 }
1173 src_class = reg_preferred_class (REGNO (src));
1174 dst_class = reg_preferred_class (REGNO (dst));
1175 if (src_class != dst_class
1176 && (! reg_class_subset_p (src_class, dst_class)
1177 || CLASS_LIKELY_SPILLED_P (src_class))
1178 && (! reg_class_subset_p (dst_class, src_class)
1179 || CLASS_LIKELY_SPILLED_P (dst_class)))
ddc8bed2
MM
1180 {
1181 if (!copy_src)
1182 {
1183 copy_src = src;
1184 copy_dst = dst;
1185 }
1186 continue;
1187 }
8c660648 1188
184bb750
R
1189 /* Can not modify an earlier insn to set dst if this insn
1190 uses an old value in the source. */
1191 if (reg_overlap_mentioned_p (dst, SET_SRC (set)))
ddc8bed2
MM
1192 {
1193 if (!copy_src)
1194 {
1195 copy_src = src;
1196 copy_dst = dst;
1197 }
1198 continue;
1199 }
1200
1201 if (! (src_note = find_reg_note (insn, REG_DEAD, src)))
1202 {
1203 if (!copy_src)
1204 {
1205 copy_src = src;
1206 copy_dst = dst;
1207 }
1208 continue;
1209 }
8c660648 1210
8c660648 1211
184bb750
R
1212 /* If src is set once in a different basic block,
1213 and is set equal to a constant, then do not use
1214 it for this optimization, as this would make it
1215 no longer equivalent to a constant. */
ddc8bed2
MM
1216
1217 if (reg_is_remote_constant_p (src, insn, f))
1218 {
1219 if (!copy_src)
1220 {
1221 copy_src = src;
1222 copy_dst = dst;
1223 }
1224 continue;
1225 }
1226
1227
1228 if (regmove_dump_file)
1229 fprintf (regmove_dump_file,
1230 "Could fix operand %d of insn %d matching operand %d.\n",
1231 operand_number, INSN_UID (insn), match_number);
8c660648 1232
184bb750
R
1233 /* Scan backward to find the first instruction that uses
1234 the input operand. If the operand is set here, then
1235 replace it in both instructions with match_number. */
1236
1237 for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p))
1238 {
1239 rtx pset;
1240
1241 if (GET_CODE (p) == CODE_LABEL
1242 || GET_CODE (p) == JUMP_INSN
1243 || (GET_CODE (p) == NOTE
1244 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
1245 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
1246 break;
1247
7bf825d2
JW
1248 /* ??? We can't scan past the end of a basic block without
1249 updating the register lifetime info
1250 (REG_DEAD/basic_block_live_at_start).
1251 A CALL_INSN might be the last insn of a basic block, if
1252 it is inside an EH region. There is no easy way to tell,
1253 so we just always break when we see a CALL_INSN if
1254 flag_exceptions is nonzero. */
1255 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
1256 break;
1257
184bb750
R
1258 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
1259 continue;
8c660648 1260
184bb750 1261 length++;
8c660648 1262
184bb750
R
1263 /* ??? See if all of SRC is set in P. This test is much
1264 more conservative than it needs to be. */
1265 pset = single_set (p);
1266 if (pset && SET_DEST (pset) == src)
1267 {
1268 /* We use validate_replace_rtx, in case there
1269 are multiple identical source operands. All of
1270 them have to be changed at the same time. */
1271 if (validate_replace_rtx (src, dst, insn))
8c660648 1272 {
184bb750
R
1273 if (validate_change (p, &SET_DEST (pset),
1274 dst, 0))
1275 success = 1;
1276 else
8c660648 1277 {
184bb750
R
1278 /* Change all source operands back.
1279 This modifies the dst as a side-effect. */
1280 validate_replace_rtx (dst, src, insn);
1281 /* Now make sure the dst is right. */
1282 validate_change (insn,
1283 recog_operand_loc[match_number],
1284 dst, 0);
8c660648 1285 }
8c660648 1286 }
184bb750
R
1287 break;
1288 }
1289
1290 if (reg_overlap_mentioned_p (src, PATTERN (p))
1291 || reg_overlap_mentioned_p (dst, PATTERN (p)))
1292 break;
8c660648 1293
184bb750
R
1294 /* If we have passed a call instruction, and the
1295 pseudo-reg DST is not already live across a call,
1296 then don't perform the optimization. */
1297 if (GET_CODE (p) == CALL_INSN)
1298 {
1299 num_calls++;
1300
1301 if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0)
8c660648 1302 break;
184bb750
R
1303 }
1304 }
8c660648 1305
184bb750
R
1306 if (success)
1307 {
1308 int dstno, srcno;
8c660648 1309
184bb750
R
1310 /* Remove the death note for SRC from INSN. */
1311 remove_note (insn, src_note);
1312 /* Move the death note for SRC to P if it is used
1313 there. */
1314 if (reg_overlap_mentioned_p (src, PATTERN (p)))
1315 {
1316 XEXP (src_note, 1) = REG_NOTES (p);
1317 REG_NOTES (p) = src_note;
8c660648 1318 }
184bb750
R
1319 /* If there is a REG_DEAD note for DST on P, then remove
1320 it, because DST is now set there. */
5e9defae 1321 if ((dst_note = find_reg_note (p, REG_DEAD, dst)))
184bb750
R
1322 remove_note (p, dst_note);
1323
1324 dstno = REGNO (dst);
1325 srcno = REGNO (src);
1326
1327 REG_N_SETS (dstno)++;
1328 REG_N_SETS (srcno)--;
8c660648 1329
184bb750
R
1330 REG_N_CALLS_CROSSED (dstno) += num_calls;
1331 REG_N_CALLS_CROSSED (srcno) -= num_calls;
1332
1333 REG_LIVE_LENGTH (dstno) += length;
1334 if (REG_LIVE_LENGTH (srcno) >= 0)
8c660648 1335 {
184bb750
R
1336 REG_LIVE_LENGTH (srcno) -= length;
1337 /* REG_LIVE_LENGTH is only an approximation after
1338 combine if sched is not run, so make sure that we
1339 still have a reasonable value. */
1340 if (REG_LIVE_LENGTH (srcno) < 2)
1341 REG_LIVE_LENGTH (srcno) = 2;
1342 }
8c660648 1343
184bb750
R
1344 /* We assume that a register is used exactly once per
1345 insn in the updates above. If this is not correct,
1346 no great harm is done. */
8c660648 1347
184bb750
R
1348 REG_N_REFS (dstno) += 2 * loop_depth;
1349 REG_N_REFS (srcno) -= 2 * loop_depth;
8c660648 1350
184bb750
R
1351 /* If that was the only time src was set,
1352 and src was not live at the start of the
1353 function, we know that we have no more
1354 references to src; clear REG_N_REFS so it
1355 won't make reload do any work. */
1356 if (REG_N_SETS (REGNO (src)) == 0
1357 && ! regno_uninitialized (REGNO (src)))
1358 REG_N_REFS (REGNO (src)) = 0;
8c660648 1359
184bb750
R
1360 if (regmove_dump_file)
1361 fprintf (regmove_dump_file,
1362 "Fixed operand %d of insn %d matching operand %d.\n",
1363 operand_number, INSN_UID (insn), match_number);
8c660648 1364
184bb750 1365 break;
8c660648
JL
1366 }
1367 }
ddc8bed2
MM
1368
1369 /* If we weren't able to replace any of the alternatives, try an
1370 alternative appoach of copying the source to the destination. */
1371 if (!success && copy_src != NULL_RTX)
1372 copy_src_to_dest (insn, copy_src, copy_dst, loop_depth);
1373
8c660648
JL
1374 }
1375 }
1376#endif /* REGISTER_CONSTRAINTS */
1377}
1378
b1a7d591
JW
1379/* Returns the INSN_CODE for INSN if its pattern has matching constraints for
1380 any operand. Returns -1 if INSN can't be recognized, or if the alternative
1381 can't be determined.
1382
1383 Initialize the info in MATCHP based on the constraints. */
184bb750
R
1384
1385static int
1386find_matches (insn, matchp)
1387 rtx insn;
1388 struct match *matchp;
1389{
1390 int likely_spilled[MAX_RECOG_OPERANDS];
1391 int operand_number;
1392 int insn_code_number = recog_memoized (insn);
1393 int any_matches = 0;
1394
1395 if (insn_code_number < 0)
1396 return -1;
1397
1398 insn_extract (insn);
1399 if (! constrain_operands (insn_code_number, 0))
1400 return -1;
1401
1402 /* Must initialize this before main loop, because the code for
1403 the commutative case may set matches for operands other than
1404 the current one. */
1405 for (operand_number = insn_n_operands[insn_code_number];
1406 --operand_number >= 0; )
1407 matchp->with[operand_number] = matchp->commutative[operand_number] = -1;
1408
1409 for (operand_number = 0; operand_number < insn_n_operands[insn_code_number];
1410 operand_number++)
1411 {
184bb750
R
1412 char *p, c;
1413 int i = 0;
1414
1415 p = insn_operand_constraint[insn_code_number][operand_number];
1416
1417 likely_spilled[operand_number] = 0;
1418 matchp->use[operand_number] = READ;
c485e6a0 1419 matchp->early_clobber[operand_number] = 0;
184bb750
R
1420 if (*p == '=')
1421 matchp->use[operand_number] = WRITE;
1422 else if (*p == '+')
1423 matchp->use[operand_number] = READWRITE;
1424
1425 for (;*p && i < which_alternative; p++)
1426 if (*p == ',')
1427 i++;
1428
1429 while ((c = *p++) != '\0' && c != ',')
1430 switch (c)
1431 {
1432 case '=':
1433 break;
1434 case '+':
1435 break;
1436 case '&':
1437 matchp->early_clobber[operand_number] = 1;
1438 break;
1439 case '%':
1440 matchp->commutative[operand_number] = operand_number + 1;
1441 matchp->commutative[operand_number + 1] = operand_number;
1442 break;
1443 case '0': case '1': case '2': case '3': case '4':
1444 case '5': case '6': case '7': case '8': case '9':
1445 c -= '0';
27d7e05d 1446 if (c < operand_number && likely_spilled[(unsigned char) c])
184bb750
R
1447 break;
1448 matchp->with[operand_number] = c;
1449 any_matches = 1;
1450 if (matchp->commutative[operand_number] >= 0)
1451 matchp->with[matchp->commutative[operand_number]] = c;
1452 break;
1453 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h':
1454 case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u':
1455 case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B':
1456 case 'C': case 'D': case 'W': case 'Y': case 'Z':
1457 if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_LETTER (c)))
1458 likely_spilled[operand_number] = 1;
1459 break;
1460 }
1461 }
1462 return any_matches ? insn_code_number : -1;
1463}
1464
1465/* Try to replace output operand DST in SET, with input operand SRC. SET is
1466 the only set in INSN. INSN has just been recgnized and constrained.
1467 SRC is operand number OPERAND_NUMBER in INSN.
1468 DST is operand number MATCH_NUMBER in INSN.
1469 If BACKWARD is nonzero, we have been called in a backward pass.
1470 Return nonzero for success. */
1471static int
1472fixup_match_1 (insn, set, src, src_subreg, dst, backward, operand_number,
1473 match_number, regmove_dump_file)
1474 rtx insn, set, src, src_subreg, dst;
1475 int backward, operand_number, match_number;
1476 FILE *regmove_dump_file;
1477{
1478 rtx p;
1479 rtx post_inc = 0, post_inc_set = 0, search_end = 0;
1480 int success = 0;
1481 int num_calls = 0, s_num_calls = 0;
1482 enum rtx_code code = NOTE;
1483 HOST_WIDE_INT insn_const, newconst;
1484 rtx overlap = 0; /* need to move insn ? */
1485 rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note;
1486 int length, s_length, true_loop_depth;
1487
1488 if (! src_note)
1489 {
1490 /* Look for (set (regX) (op regA constX))
1491 (set (regY) (op regA constY))
1492 and change that to
1493 (set (regA) (op regA constX)).
1494 (set (regY) (op regA constY-constX)).
1495 This works for add and shift operations, if
1496 regA is dead after or set by the second insn. */
1497
1498 code = GET_CODE (SET_SRC (set));
1499 if ((code == PLUS || code == LSHIFTRT
1500 || code == ASHIFT || code == ASHIFTRT)
1501 && XEXP (SET_SRC (set), 0) == src
1502 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
1503 insn_const = INTVAL (XEXP (SET_SRC (set), 1));
1504 else if (! stable_but_for_p (SET_SRC (set), src, dst))
1505 return 0;
1506 else
1507 /* We might find a src_note while scanning. */
1508 code = NOTE;
1509 }
1510
1511 if (regmove_dump_file)
1512 fprintf (regmove_dump_file,
1513 "Could fix operand %d of insn %d matching operand %d.\n",
1514 operand_number, INSN_UID (insn), match_number);
1515
1516 /* If SRC is equivalent to a constant set in a different basic block,
1517 then do not use it for this optimization. We want the equivalence
1518 so that if we have to reload this register, we can reload the
1519 constant, rather than extending the lifespan of the register. */
1520 if (reg_is_remote_constant_p (src, insn, get_insns ()))
1521 return 0;
1522
1523 /* Scan forward to find the next instruction that
1524 uses the output operand. If the operand dies here,
1525 then replace it in both instructions with
1526 operand_number. */
1527
1528 for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
1529 {
1530 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
1531 || (GET_CODE (p) == NOTE
1532 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
1533 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
1534 break;
1535
7bf825d2
JW
1536 /* ??? We can't scan past the end of a basic block without updating
1537 the register lifetime info (REG_DEAD/basic_block_live_at_start).
1538 A CALL_INSN might be the last insn of a basic block, if it is
1539 inside an EH region. There is no easy way to tell, so we just
1540 always break when we see a CALL_INSN if flag_exceptions is nonzero. */
1541 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
1542 break;
1543
184bb750
R
1544 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
1545 continue;
1546
1547 length++;
1548 if (src_note)
1549 s_length++;
1550
1551 if (reg_set_p (src, p) || reg_set_p (dst, p)
1552 || (GET_CODE (PATTERN (p)) == USE
1553 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
1554 break;
1555
1556 /* See if all of DST dies in P. This test is
1557 slightly more conservative than it needs to be. */
1558 if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst)))
1559 && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst)))
1560 {
1561 if (! src_note)
1562 {
1563 rtx q;
1564 rtx set2;
1565
1566 /* If an optimization is done, the value of SRC while P
1567 is executed will be changed. Check that this is OK. */
1568 if (reg_overlap_mentioned_p (src, PATTERN (p)))
1569 break;
1570 for (q = p; q; q = NEXT_INSN (q))
1571 {
1572 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN
1573 || (GET_CODE (q) == NOTE
1574 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG
1575 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END)))
1576 {
1577 q = 0;
1578 break;
1579 }
7bf825d2
JW
1580
1581 /* ??? We can't scan past the end of a basic block without
1582 updating the register lifetime info
1583 (REG_DEAD/basic_block_live_at_start).
1584 A CALL_INSN might be the last insn of a basic block, if
1585 it is inside an EH region. There is no easy way to tell,
1586 so we just always break when we see a CALL_INSN if
1587 flag_exceptions is nonzero. */
a1ecb5ca 1588 if (flag_exceptions && GET_CODE (q) == CALL_INSN)
7bf825d2
JW
1589 {
1590 q = 0;
1591 break;
1592 }
1593
184bb750
R
1594 if (GET_RTX_CLASS (GET_CODE (q)) != 'i')
1595 continue;
1596 if (reg_overlap_mentioned_p (src, PATTERN (q))
1597 || reg_set_p (src, q))
1598 break;
1599 }
1600 if (q)
1601 set2 = single_set (q);
1602 if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code
1603 || XEXP (SET_SRC (set2), 0) != src
1604 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT
1605 || (SET_DEST (set2) != src
1606 && ! find_reg_note (q, REG_DEAD, src)))
1607 {
1608 /* If this is a PLUS, we can still save a register by doing
1609 src += insn_const;
1610 P;
1611 src -= insn_const; .
1612 This also gives opportunities for subsequent
1613 optimizations in the backward pass, so do it there. */
1614 if (code == PLUS && backward
1615#ifdef HAVE_cc0
1616 /* We may not emit an insn directly
1617 after P if the latter sets CC0. */
1618 && ! sets_cc0_p (PATTERN (p))
1619#endif
1620 )
1621
1622 {
1623 search_end = q;
1624 q = insn;
1625 set2 = set;
1626 newconst = -insn_const;
1627 code = MINUS;
1628 }
1629 else
1630 break;
1631 }
1632 else
1633 {
1634 newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const;
1635 /* Reject out of range shifts. */
1636 if (code != PLUS
1637 && (newconst < 0
1638 || (newconst
1639 >= GET_MODE_BITSIZE (GET_MODE (SET_SRC (set2))))))
1640 break;
1641 if (code == PLUS)
1642 {
1643 post_inc = q;
1644 if (SET_DEST (set2) != src)
1645 post_inc_set = set2;
1646 }
1647 }
1648 /* We use 1 as last argument to validate_change so that all
1649 changes are accepted or rejected together by apply_change_group
1650 when it is called by validate_replace_rtx . */
1651 validate_change (q, &XEXP (SET_SRC (set2), 1),
1652 GEN_INT (newconst), 1);
1653 }
1654 validate_change (insn, recog_operand_loc[match_number], src, 1);
1655 if (validate_replace_rtx (dst, src_subreg, p))
1656 success = 1;
1657 break;
1658 }
1659
1660 if (reg_overlap_mentioned_p (dst, PATTERN (p)))
1661 break;
1662 if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p)))
1663 {
1664 /* INSN was already checked to be movable when
1665 we found no REG_DEAD note for src on it. */
1666 overlap = p;
1667 src_note = find_reg_note (p, REG_DEAD, src);
1668 }
1669
1670 /* If we have passed a call instruction, and the pseudo-reg SRC is not
1671 already live across a call, then don't perform the optimization. */
1672 if (GET_CODE (p) == CALL_INSN)
1673 {
1674 if (REG_N_CALLS_CROSSED (REGNO (src)) == 0)
1675 break;
1676
1677 num_calls++;
1678
1679 if (src_note)
1680 s_num_calls++;
1681
1682 }
1683 }
1684
1685 if (! success)
1686 return 0;
1687
1688 true_loop_depth = backward ? 2 - loop_depth : loop_depth;
1689
1690 /* Remove the death note for DST from P. */
1691 remove_note (p, dst_note);
1692 if (code == MINUS)
1693 {
1694 post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p);
1695#if defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT)
1696 if (search_end
1697 && try_auto_increment (search_end, post_inc, 0, src, newconst, 1))
1698 post_inc = 0;
1699#endif
1700 validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0);
1701 REG_N_SETS (REGNO (src))++;
1702 REG_N_REFS (REGNO (src)) += true_loop_depth;
1703 REG_LIVE_LENGTH (REGNO (src))++;
1704 }
1705 if (overlap)
1706 {
1707 /* The lifetime of src and dest overlap,
1708 but we can change this by moving insn. */
1709 rtx pat = PATTERN (insn);
1710 if (src_note)
1711 remove_note (overlap, src_note);
1712#if defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT)
1713 if (code == PLUS
1714 && try_auto_increment (overlap, insn, 0, src, insn_const, 0))
1715 insn = overlap;
1716 else
1717#endif
1718 {
1719 rtx notes = REG_NOTES (insn);
1720
1721 emit_insn_after_with_line_notes (pat, PREV_INSN (p), insn);
1722 PUT_CODE (insn, NOTE);
1723 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1724 NOTE_SOURCE_FILE (insn) = 0;
1725 /* emit_insn_after_with_line_notes has no
1726 return value, so search for the new insn. */
1727 for (insn = p; PATTERN (insn) != pat; )
1728 insn = PREV_INSN (insn);
1729
1730 REG_NOTES (insn) = notes;
1731 }
1732 }
1733 /* Sometimes we'd generate src = const; src += n;
1734 if so, replace the instruction that set src
1735 in the first place. */
1736
1737 if (! overlap && (code == PLUS || code == MINUS))
1738 {
1739 rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1740 rtx q, set2;
1741 int num_calls2 = 0, s_length2 = 0;
1742
1743 if (note && CONSTANT_P (XEXP (note, 0)))
1744 {
1745 for (q = PREV_INSN (insn); q; q = PREV_INSN(q))
1746 {
7bf825d2
JW
1747 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN
1748 || (GET_CODE (q) == NOTE
1749 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG
1750 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END)))
184bb750
R
1751 {
1752 q = 0;
1753 break;
1754 }
7bf825d2
JW
1755
1756 /* ??? We can't scan past the end of a basic block without
1757 updating the register lifetime info
1758 (REG_DEAD/basic_block_live_at_start).
1759 A CALL_INSN might be the last insn of a basic block, if
1760 it is inside an EH region. There is no easy way to tell,
1761 so we just always break when we see a CALL_INSN if
1762 flag_exceptions is nonzero. */
a1ecb5ca 1763 if (flag_exceptions && GET_CODE (q) == CALL_INSN)
7bf825d2
JW
1764 {
1765 q = 0;
1766 break;
1767 }
1768
184bb750
R
1769 if (GET_RTX_CLASS (GET_CODE (q)) != 'i')
1770 continue;
1771 s_length2++;
1772 if (reg_set_p (src, q))
1773 {
1774 set2 = single_set (q);
1775 break;
1776 }
1777 if (reg_overlap_mentioned_p (src, PATTERN (q)))
1778 {
1779 q = 0;
1780 break;
1781 }
1782 if (GET_CODE (p) == CALL_INSN)
1783 num_calls2++;
1784 }
1785 if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2))
1786 && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0))
1787 {
1788 PUT_CODE (q, NOTE);
1789 NOTE_LINE_NUMBER (q) = NOTE_INSN_DELETED;
1790 NOTE_SOURCE_FILE (q) = 0;
1791 REG_N_SETS (REGNO (src))--;
1792 REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2;
1793 REG_N_REFS (REGNO (src)) -= true_loop_depth;
1794 REG_LIVE_LENGTH (REGNO (src)) -= s_length2;
1795 insn_const = 0;
1796 }
1797 }
1798 }
1a56b81f
AS
1799
1800 /* Don't remove this seemingly useless if, it is needed to pair with the
1801 else in the next two conditionally included code blocks. */
1802 if (0)
1803 {;}
184bb750
R
1804#if defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT)
1805 else if ((code == PLUS || code == MINUS) && insn_const
1806 && try_auto_increment (p, insn, 0, src, insn_const, 1))
1807 insn = p;
1808#endif
1809#if defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT)
1810 else if (post_inc
1811 && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0))
1812 post_inc = 0;
1813#endif
1814#if defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT)
1815 /* If post_inc still prevails, try to find an
1816 insn where it can be used as a pre-in/decrement.
1817 If code is MINUS, this was already tried. */
1818 if (post_inc && code == PLUS
1819 /* Check that newconst is likely to be usable
1820 in a pre-in/decrement before starting the search. */
1821 && (0
1822#if defined (HAVE_PRE_INCREMENT)
1823 || (newconst > 0 && newconst <= MOVE_MAX)
1824#endif
1825#if defined (HAVE_PRE_DECREMENT)
1826 || (newconst < 0 && newconst >= -MOVE_MAX)
1827#endif
1828 ) && exact_log2 (newconst))
1829 {
1830 rtx q, inc_dest;
1831
1832 inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src;
51723711 1833 for (q = post_inc; (q = NEXT_INSN (q)); )
184bb750
R
1834 {
1835 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN
1836 || (GET_CODE (q) == NOTE
1837 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG
1838 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END)))
1839 break;
7bf825d2
JW
1840
1841 /* ??? We can't scan past the end of a basic block without updating
1842 the register lifetime info (REG_DEAD/basic_block_live_at_start).
1843 A CALL_INSN might be the last insn of a basic block, if it
1844 is inside an EH region. There is no easy way to tell so we
1845 just always break when we see a CALL_INSN if flag_exceptions
1846 is nonzero. */
a1ecb5ca 1847 if (flag_exceptions && GET_CODE (q) == CALL_INSN)
7bf825d2
JW
1848 break;
1849
184bb750
R
1850 if (GET_RTX_CLASS (GET_CODE (q)) != 'i')
1851 continue;
1852 if (src != inc_dest && (reg_overlap_mentioned_p (src, PATTERN (q))
1853 || reg_set_p (src, q)))
1854 break;
1855 if (reg_set_p (inc_dest, q))
1856 break;
1857 if (reg_overlap_mentioned_p (inc_dest, PATTERN (q)))
1858 {
1859 try_auto_increment (q, post_inc,
1860 post_inc_set, inc_dest, newconst, 1);
1861 break;
1862 }
1863 }
1864 }
1865#endif /* defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT) */
1866 /* Move the death note for DST to INSN if it is used
1867 there. */
1868 if (reg_overlap_mentioned_p (dst, PATTERN (insn)))
1869 {
1870 XEXP (dst_note, 1) = REG_NOTES (insn);
1871 REG_NOTES (insn) = dst_note;
1872 }
1873
1874 if (src_note)
1875 {
1876 /* Move the death note for SRC from INSN to P. */
1877 if (! overlap)
1878 remove_note (insn, src_note);
1879 XEXP (src_note, 1) = REG_NOTES (p);
1880 REG_NOTES (p) = src_note;
1881
1882 REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls;
1883 }
1884
1885 REG_N_SETS (REGNO (src))++;
1886 REG_N_SETS (REGNO (dst))--;
1887
1888 REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls;
1889
1890 REG_LIVE_LENGTH (REGNO (src)) += s_length;
1891 if (REG_LIVE_LENGTH (REGNO (dst)) >= 0)
1892 {
1893 REG_LIVE_LENGTH (REGNO (dst)) -= length;
1894 /* REG_LIVE_LENGTH is only an approximation after
1895 combine if sched is not run, so make sure that we
1896 still have a reasonable value. */
1897 if (REG_LIVE_LENGTH (REGNO (dst)) < 2)
1898 REG_LIVE_LENGTH (REGNO (dst)) = 2;
1899 }
1900
1901 /* We assume that a register is used exactly once per
1902 insn in the updates above. If this is not correct,
1903 no great harm is done. */
1904
1905 REG_N_REFS (REGNO (src)) += 2 * true_loop_depth;
1906 REG_N_REFS (REGNO (dst)) -= 2 * true_loop_depth;
1907
1908 /* If that was the only time dst was set,
1909 and dst was not live at the start of the
1910 function, we know that we have no more
1911 references to dst; clear REG_N_REFS so it
1912 won't make reload do any work. */
1913 if (REG_N_SETS (REGNO (dst)) == 0
1914 && ! regno_uninitialized (REGNO (dst)))
1915 REG_N_REFS (REGNO (dst)) = 0;
1916
1917 if (regmove_dump_file)
1918 fprintf (regmove_dump_file,
1919 "Fixed operand %d of insn %d matching operand %d.\n",
1920 operand_number, INSN_UID (insn), match_number);
1921 return 1;
1922}
1923
1924
8c660648
JL
1925/* return nonzero if X is stable but for mentioning SRC or mentioning /
1926 changing DST . If in doubt, presume it is unstable. */
1927static int
1928stable_but_for_p (x, src, dst)
1929 rtx x, src, dst;
1930{
1931 RTX_CODE code = GET_CODE (x);
1932 switch (GET_RTX_CLASS (code))
1933 {
1934 case '<': case '1': case 'c': case '2': case 'b': case '3':
1935 {
1936 int i;
1937 char *fmt = GET_RTX_FORMAT (code);
1938 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1939 if (fmt[i] == 'e' && ! stable_but_for_p (XEXP (x, i), src, dst))
1940 return 0;
1941 return 1;
1942 }
1943 case 'o':
1944 if (x == src || x == dst)
1945 return 1;
1946 /* fall through */
1947 default:
1948 return ! rtx_unstable_p (x);
1949 }
1950}
184bb750 1951
b1a7d591
JW
1952/* Test if regmove seems profitable for this target. Regmove is useful only
1953 if some common patterns are two address, i.e. require matching constraints,
1954 so we check that condition here. */
1955
184bb750
R
1956int
1957regmove_profitable_p ()
1958{
1959#ifdef REGISTER_CONSTRAINTS
1960 struct match match;
1961 enum machine_mode mode;
1962 optab tstoptab = add_optab;
1963 do /* check add_optab and ashl_optab */
1964 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1965 mode = GET_MODE_WIDER_MODE (mode))
1966 {
1967 int icode = (int) tstoptab->handlers[(int) mode].insn_code;
1968 rtx reg0, reg1, reg2, pat;
1969 int i;
1970
1971 if (GET_MODE_BITSIZE (mode) < 32 || icode == CODE_FOR_nothing)
1972 continue;
1973 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1974 if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i))
1975 break;
1976 if (i + 2 >= FIRST_PSEUDO_REGISTER)
1977 break;
38a448ca
RH
1978 reg0 = gen_rtx_REG (insn_operand_mode[icode][0], i);
1979 reg1 = gen_rtx_REG (insn_operand_mode[icode][1], i + 1);
1980 reg2 = gen_rtx_REG (insn_operand_mode[icode][2], i + 2);
184bb750
R
1981 if (! (*insn_operand_predicate[icode][0]) (reg0, VOIDmode)
1982 || ! (*insn_operand_predicate[icode][1]) (reg1, VOIDmode)
1983 || ! (*insn_operand_predicate[icode][2]) (reg2, VOIDmode))
1984 break;
1985 pat = GEN_FCN (icode) (reg0, reg1, reg2);
1986 if (! pat)
1987 continue;
1988 if (GET_CODE (pat) == SEQUENCE)
1989 pat = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1);
1990 else
1991 pat = make_insn_raw (pat);
1992 if (! single_set (pat)
1993 || GET_CODE (SET_SRC (single_set (pat))) != tstoptab->code)
1994 /* Unexpected complexity; don't need to handle this unless
1995 we find a machine where this occurs and regmove should
1996 be enabled. */
1997 break;
1998 if (find_matches (pat, &match) >= 0)
1999 return 1;
2000 break;
2001 }
2002 while (tstoptab != ashl_optab && (tstoptab = ashl_optab, 1));
2003#endif /* REGISTER_CONSTRAINTS */
2004 return 0;
2005}
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