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8c660648 1/* Move registers around to reduce number of move instructions needed.
184bb750 2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
8c660648
JL
3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
18the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19
20
21/* This module looks for cases where matching constraints would force
22 an instruction to need a reload, and this reload would be a register
23 to register move. It then attempts to change the registers used by the
24 instruction to avoid the move instruction. */
25
26#include "config.h"
27#ifdef __STDC__
28#include <stdarg.h>
29#else
30#include <varargs.h>
31#endif
32
670ee920
KG
33/* stdio.h must precede rtl.h for FFS. */
34#include "system.h"
8c660648
JL
35
36#include "rtl.h"
37#include "insn-config.h"
38#include "recog.h"
39#include "output.h"
40#include "reload.h"
41#include "regs.h"
184bb750
R
42#include "hard-reg-set.h"
43#include "flags.h"
44#include "expr.h"
45#include "insn-flags.h"
46
1230327b
R
47static int optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
48static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
184bb750 49static void optimize_reg_copy_3 PROTO((rtx, rtx, rtx));
1a29f703 50static rtx gen_add3_insn PROTO((rtx, rtx, rtx));
8c660648 51
184bb750
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52struct match {
53 int with[MAX_RECOG_OPERANDS];
54 enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS];
55 int commutative[MAX_RECOG_OPERANDS];
56 int early_clobber[MAX_RECOG_OPERANDS];
57};
58
d06eab0d 59#ifdef AUTO_INC_DEC
0e05e8ea 60static int try_auto_increment PROTO((rtx, rtx, rtx, rtx, HOST_WIDE_INT, int));
d06eab0d 61#endif
184bb750
R
62static int find_matches PROTO((rtx, struct match *));
63static int fixup_match_1 PROTO((rtx, rtx, rtx, rtx, rtx, int, int, int, FILE *))
64;
65static int reg_is_remote_constant_p PROTO((rtx, rtx, rtx));
8c660648 66static int stable_but_for_p PROTO((rtx, rtx, rtx));
184bb750 67static int loop_depth;
8c660648 68
1a29f703
R
69/* Generate and return an insn body to add r1 and c,
70 storing the result in r0. */
71static rtx
72gen_add3_insn (r0, r1, c)
73 rtx r0, r1, c;
74{
75 int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code;
76
77 if (icode == CODE_FOR_nothing
78 || ! (*insn_operand_predicate[icode][0]) (r0, insn_operand_mode[icode][0])
79 || ! (*insn_operand_predicate[icode][1]) (r1, insn_operand_mode[icode][1])
80 || ! (*insn_operand_predicate[icode][2]) (c, insn_operand_mode[icode][2]))
81 return NULL_RTX;
82
83 return (GEN_FCN (icode) (r0, r1, c));
84}
85
184bb750 86#ifdef AUTO_INC_DEC
8c660648
JL
87
88/* INC_INSN is an instruction that adds INCREMENT to REG.
89 Try to fold INC_INSN as a post/pre in/decrement into INSN.
90 Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src.
91 Return nonzero for success. */
92static int
93try_auto_increment (insn, inc_insn, inc_insn_set, reg, increment, pre)
94 rtx reg, insn, inc_insn ,inc_insn_set;
95 HOST_WIDE_INT increment;
96 int pre;
97{
98 enum rtx_code inc_code;
99
100 rtx pset = single_set (insn);
101 if (pset)
102 {
103 /* Can't use the size of SET_SRC, we might have something like
104 (sign_extend:SI (mem:QI ... */
105 rtx use = find_use_as_address (pset, reg, 0);
106 if (use != 0 && use != (rtx) 1)
107 {
108 int size = GET_MODE_SIZE (GET_MODE (use));
109 if (0
110#ifdef HAVE_POST_INCREMENT
111 || (pre == 0 && (inc_code = POST_INC, increment == size))
112#endif
113#ifdef HAVE_PRE_INCREMENT
114 || (pre == 1 && (inc_code = PRE_INC, increment == size))
115#endif
116#ifdef HAVE_POST_DECREMENT
117 || (pre == 0 && (inc_code = POST_DEC, increment == -size))
118#endif
119#ifdef HAVE_PRE_DECREMENT
120 || (pre == 1 && (inc_code = PRE_DEC, increment == -size))
121#endif
184bb750
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122 )
123 {
124 if (inc_insn_set)
125 validate_change
126 (inc_insn,
127 &SET_SRC (inc_insn_set),
8c660648 128 XEXP (SET_SRC (inc_insn_set), 0), 1);
184bb750 129 validate_change (insn, &XEXP (use, 0),
38a448ca 130 gen_rtx_fmt_e (inc_code, Pmode, reg), 1);
184bb750
R
131 if (apply_change_group ())
132 {
133 REG_NOTES (insn)
38a448ca
RH
134 = gen_rtx_EXPR_LIST (REG_INC,
135 reg, REG_NOTES (insn));
184bb750
R
136 if (! inc_insn_set)
137 {
138 PUT_CODE (inc_insn, NOTE);
139 NOTE_LINE_NUMBER (inc_insn) = NOTE_INSN_DELETED;
140 NOTE_SOURCE_FILE (inc_insn) = 0;
141 }
8c660648 142 return 1;
184bb750
R
143 }
144 }
145 }
146 }
147 return 0;
148}
149#endif /* AUTO_INC_DEC */
150
151static int *regno_src_regno;
152
153/* Indicate how good a choice REG (which appears as a source) is to replace
154 a destination register with. The higher the returned value, the better
155 the choice. The main objective is to avoid using a register that is
156 a candidate for tying to a hard register, since the output might in
157 turn be a candidate to be tied to a different hard register. */
158int
159replacement_quality(reg)
160 rtx reg;
161{
162 int src_regno;
163
164 /* Bad if this isn't a register at all. */
165 if (GET_CODE (reg) != REG)
166 return 0;
167
168 /* If this register is not meant to get a hard register,
169 it is a poor choice. */
170 if (REG_LIVE_LENGTH (REGNO (reg)) < 0)
171 return 0;
172
173 src_regno = regno_src_regno[REGNO (reg)];
174
175 /* If it was not copied from another register, it is fine. */
176 if (src_regno < 0)
177 return 3;
178
179 /* Copied from a hard register? */
180 if (src_regno < FIRST_PSEUDO_REGISTER)
181 return 1;
182
183 /* Copied from a pseudo register - not as bad as from a hard register,
184 yet still cumbersome, since the register live length will be lengthened
185 when the registers get tied. */
186 return 2;
187}
188
1230327b
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189/* INSN is a copy from SRC to DEST, both registers, and SRC does not die
190 in INSN.
191
192 Search forward to see if SRC dies before either it or DEST is modified,
193 but don't scan past the end of a basic block. If so, we can replace SRC
194 with DEST and let SRC die in INSN.
195
196 This will reduce the number of registers live in that range and may enable
197 DEST to be tied to SRC, thus often saving one register in addition to a
198 register-register copy. */
199
200static int
201optimize_reg_copy_1 (insn, dest, src)
202 rtx insn;
203 rtx dest;
204 rtx src;
205{
206 rtx p, q;
207 rtx note;
208 rtx dest_death = 0;
209 int sregno = REGNO (src);
210 int dregno = REGNO (dest);
211
212 /* We don't want to mess with hard regs if register classes are small. */
213 if (sregno == dregno
214 || (SMALL_REGISTER_CLASSES
215 && (sregno < FIRST_PSEUDO_REGISTER
216 || dregno < FIRST_PSEUDO_REGISTER))
217 /* We don't see all updates to SP if they are in an auto-inc memory
218 reference, so we must disallow this optimization on them. */
219 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
220 return 0;
221
222 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
223 {
224 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
225 || (GET_CODE (p) == NOTE
226 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
227 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
228 break;
229
7bf825d2
JW
230 /* ??? We can't scan past the end of a basic block without updating
231 the register lifetime info (REG_DEAD/basic_block_live_at_start).
232 A CALL_INSN might be the last insn of a basic block, if it is inside
233 an EH region. There is no easy way to tell, so we just always break
234 when we see a CALL_INSN if flag_exceptions is nonzero. */
235 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
236 break;
237
1230327b
R
238 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
239 continue;
240
241 if (reg_set_p (src, p) || reg_set_p (dest, p)
242 /* Don't change a USE of a register. */
243 || (GET_CODE (PATTERN (p)) == USE
244 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
245 break;
246
247 /* See if all of SRC dies in P. This test is slightly more
248 conservative than it needs to be. */
249 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
250 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
251 {
252 int failed = 0;
253 int length = 0;
254 int d_length = 0;
255 int n_calls = 0;
256 int d_n_calls = 0;
257
258 /* We can do the optimization. Scan forward from INSN again,
259 replacing regs as we go. Set FAILED if a replacement can't
260 be done. In that case, we can't move the death note for SRC.
261 This should be rare. */
262
263 /* Set to stop at next insn. */
264 for (q = next_real_insn (insn);
265 q != next_real_insn (p);
266 q = next_real_insn (q))
267 {
268 if (reg_overlap_mentioned_p (src, PATTERN (q)))
269 {
270 /* If SRC is a hard register, we might miss some
271 overlapping registers with validate_replace_rtx,
272 so we would have to undo it. We can't if DEST is
273 present in the insn, so fail in that combination
274 of cases. */
275 if (sregno < FIRST_PSEUDO_REGISTER
276 && reg_mentioned_p (dest, PATTERN (q)))
277 failed = 1;
278
279 /* Replace all uses and make sure that the register
280 isn't still present. */
281 else if (validate_replace_rtx (src, dest, q)
282 && (sregno >= FIRST_PSEUDO_REGISTER
283 || ! reg_overlap_mentioned_p (src,
284 PATTERN (q))))
285 {
286 /* We assume that a register is used exactly once per
287 insn in the updates below. If this is not correct,
288 no great harm is done. */
289 if (sregno >= FIRST_PSEUDO_REGISTER)
290 REG_N_REFS (sregno) -= loop_depth;
291 if (dregno >= FIRST_PSEUDO_REGISTER)
292 REG_N_REFS (dregno) += loop_depth;
293 }
294 else
295 {
296 validate_replace_rtx (dest, src, q);
297 failed = 1;
298 }
299 }
300
301 /* Count the insns and CALL_INSNs passed. If we passed the
302 death note of DEST, show increased live length. */
303 length++;
304 if (dest_death)
305 d_length++;
306
307 /* If the insn in which SRC dies is a CALL_INSN, don't count it
308 as a call that has been crossed. Otherwise, count it. */
309 if (q != p && GET_CODE (q) == CALL_INSN)
310 {
311 n_calls++;
312 if (dest_death)
313 d_n_calls++;
314 }
315
316 /* If DEST dies here, remove the death note and save it for
317 later. Make sure ALL of DEST dies here; again, this is
318 overly conservative. */
319 if (dest_death == 0
320 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0)
321 {
322 if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest))
323 failed = 1, dest_death = 0;
324 else
325 remove_note (q, dest_death);
326 }
327 }
328
329 if (! failed)
330 {
331 if (sregno >= FIRST_PSEUDO_REGISTER)
332 {
333 if (REG_LIVE_LENGTH (sregno) >= 0)
334 {
335 REG_LIVE_LENGTH (sregno) -= length;
336 /* REG_LIVE_LENGTH is only an approximation after
337 combine if sched is not run, so make sure that we
338 still have a reasonable value. */
339 if (REG_LIVE_LENGTH (sregno) < 2)
340 REG_LIVE_LENGTH (sregno) = 2;
341 }
342
343 REG_N_CALLS_CROSSED (sregno) -= n_calls;
344 }
345
346 if (dregno >= FIRST_PSEUDO_REGISTER)
347 {
348 if (REG_LIVE_LENGTH (dregno) >= 0)
349 REG_LIVE_LENGTH (dregno) += d_length;
350
351 REG_N_CALLS_CROSSED (dregno) += d_n_calls;
352 }
353
354 /* Move death note of SRC from P to INSN. */
355 remove_note (p, note);
356 XEXP (note, 1) = REG_NOTES (insn);
357 REG_NOTES (insn) = note;
358 }
359
360 /* Put death note of DEST on P if we saw it die. */
361 if (dest_death)
362 {
363 XEXP (dest_death, 1) = REG_NOTES (p);
364 REG_NOTES (p) = dest_death;
365 }
366
367 return ! failed;
368 }
369
370 /* If SRC is a hard register which is set or killed in some other
371 way, we can't do this optimization. */
372 else if (sregno < FIRST_PSEUDO_REGISTER
373 && dead_or_set_p (p, src))
374 break;
375 }
376 return 0;
377}
378\f
379/* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
380 a sequence of insns that modify DEST followed by an insn that sets
381 SRC to DEST in which DEST dies, with no prior modification of DEST.
382 (There is no need to check if the insns in between actually modify
383 DEST. We should not have cases where DEST is not modified, but
384 the optimization is safe if no such modification is detected.)
385 In that case, we can replace all uses of DEST, starting with INSN and
386 ending with the set of SRC to DEST, with SRC. We do not do this
387 optimization if a CALL_INSN is crossed unless SRC already crosses a
388 call or if DEST dies before the copy back to SRC.
389
390 It is assumed that DEST and SRC are pseudos; it is too complicated to do
391 this for hard registers since the substitutions we may make might fail. */
392
393static void
394optimize_reg_copy_2 (insn, dest, src)
395 rtx insn;
396 rtx dest;
397 rtx src;
398{
399 rtx p, q;
400 rtx set;
401 int sregno = REGNO (src);
402 int dregno = REGNO (dest);
403
404 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
405 {
406 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
407 || (GET_CODE (p) == NOTE
408 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
409 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
410 break;
411
7bf825d2
JW
412 /* ??? We can't scan past the end of a basic block without updating
413 the register lifetime info (REG_DEAD/basic_block_live_at_start).
414 A CALL_INSN might be the last insn of a basic block, if it is inside
415 an EH region. There is no easy way to tell, so we just always break
416 when we see a CALL_INSN if flag_exceptions is nonzero. */
417 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
418 break;
419
1230327b
R
420 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
421 continue;
422
423 set = single_set (p);
424 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
425 && find_reg_note (p, REG_DEAD, dest))
426 {
427 /* We can do the optimization. Scan forward from INSN again,
428 replacing regs as we go. */
429
430 /* Set to stop at next insn. */
431 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
432 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
433 {
434 if (reg_mentioned_p (dest, PATTERN (q)))
435 {
436 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
437
438 /* We assume that a register is used exactly once per
439 insn in the updates below. If this is not correct,
440 no great harm is done. */
441 REG_N_REFS (dregno) -= loop_depth;
442 REG_N_REFS (sregno) += loop_depth;
443 }
444
445
446 if (GET_CODE (q) == CALL_INSN)
447 {
448 REG_N_CALLS_CROSSED (dregno)--;
449 REG_N_CALLS_CROSSED (sregno)++;
450 }
451 }
452
453 remove_note (p, find_reg_note (p, REG_DEAD, dest));
454 REG_N_DEATHS (dregno)--;
455 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
456 REG_N_DEATHS (sregno)--;
457 return;
458 }
459
460 if (reg_set_p (src, p)
461 || find_reg_note (p, REG_DEAD, dest)
462 || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0))
463 break;
464 }
465}
184bb750
R
466/* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST.
467 Look if SRC dies there, and if it is only set once, by loading
468 it from memory. If so, try to encorporate the zero/sign extension
469 into the memory read, change SRC to the mode of DEST, and alter
470 the remaining accesses to use the appropriate SUBREG. This allows
471 SRC and DEST to be tied later. */
472static void
473optimize_reg_copy_3 (insn, dest, src)
474 rtx insn;
475 rtx dest;
476 rtx src;
477{
478 rtx src_reg = XEXP (src, 0);
479 int src_no = REGNO (src_reg);
480 int dst_no = REGNO (dest);
481 rtx p, set, subreg;
482 enum machine_mode old_mode;
483
484 if (src_no < FIRST_PSEUDO_REGISTER
485 || dst_no < FIRST_PSEUDO_REGISTER
486 || ! find_reg_note (insn, REG_DEAD, src_reg)
487 || REG_N_SETS (src_no) != 1)
488 return;
489 for (p = PREV_INSN (insn); ! reg_set_p (src_reg, p); p = PREV_INSN (p))
490 {
7bf825d2
JW
491 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
492 || (GET_CODE (p) == NOTE
493 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
494 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
495 return;
496
497 /* ??? We can't scan past the end of a basic block without updating
498 the register lifetime info (REG_DEAD/basic_block_live_at_start).
499 A CALL_INSN might be the last insn of a basic block, if it is inside
500 an EH region. There is no easy way to tell, so we just always break
501 when we see a CALL_INSN if flag_exceptions is nonzero. */
502 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
503 return;
504
184bb750
R
505 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
506 continue;
184bb750
R
507 }
508 if (! (set = single_set (p))
509 || GET_CODE (SET_SRC (set)) != MEM
510 || SET_DEST (set) != src_reg)
511 return;
512 old_mode = GET_MODE (src_reg);
513 PUT_MODE (src_reg, GET_MODE (src));
514 XEXP (src, 0) = SET_SRC (set);
515 if (! validate_change (p, &SET_SRC (set), src, 0))
516 {
517 PUT_MODE (src_reg, old_mode);
518 XEXP (src, 0) = src_reg;
519 return;
520 }
38a448ca 521 subreg = gen_rtx_SUBREG (old_mode, src_reg, 0);
184bb750
R
522 while (p = NEXT_INSN (p), p != insn)
523 {
524 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
525 continue;
526 validate_replace_rtx (src_reg, subreg, p);
527 }
528 validate_replace_rtx (src, src_reg, insn);
529}
530
531/* Return whether REG is set in only one location, and is set to a
532 constant, but is set in a different basic block from INSN (an
533 instructions which uses REG). In this case REG is equivalent to a
534 constant, and we don't want to break that equivalence, because that
535 may increase register pressure and make reload harder. If REG is
536 set in the same basic block as INSN, we don't worry about it,
537 because we'll probably need a register anyhow (??? but what if REG
538 is used in a different basic block as well as this one?). FIRST is
539 the first insn in the function. */
540
541static int
542reg_is_remote_constant_p (reg, insn, first)
543 rtx reg;
544 rtx insn;
545 rtx first;
546{
547 register rtx p;
548
549 if (REG_N_SETS (REGNO (reg)) != 1)
550 return 0;
551
552 /* Look for the set. */
553 for (p = LOG_LINKS (insn); p; p = XEXP (p, 1))
554 {
555 rtx s;
556
557 if (REG_NOTE_KIND (p) != 0)
558 continue;
559 s = single_set (XEXP (p, 0));
560 if (s != 0
561 && GET_CODE (SET_DEST (s)) == REG
562 && REGNO (SET_DEST (s)) == REGNO (reg))
563 {
564 /* The register is set in the same basic block. */
565 return 0;
566 }
567 }
568
569 for (p = first; p && p != insn; p = NEXT_INSN (p))
570 {
571 rtx s;
572
573 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
574 continue;
575 s = single_set (p);
576 if (s != 0
577 && GET_CODE (SET_DEST (s)) == REG
578 && REGNO (SET_DEST (s)) == REGNO (reg))
579 {
580 /* This is the instruction which sets REG. If there is a
581 REG_EQUAL note, then REG is equivalent to a constant. */
582 if (find_reg_note (p, REG_EQUAL, NULL_RTX))
583 return 1;
584 return 0;
585 }
586 }
587
588 return 0;
589}
590
b1a7d591
JW
591/* INSN is adding a CONST_INT to a REG. We search backwards looking for
592 another add immediate instruction with the same source and dest registers,
593 and if we find one, we change INSN to an increment, and return 1. If
594 no changes are made, we return 0.
595
596 This changes
597 (set (reg100) (plus reg1 offset1))
598 ...
599 (set (reg100) (plus reg1 offset2))
600 to
601 (set (reg100) (plus reg1 offset1))
602 ...
603 (set (reg100) (plus reg100 offset2-offset1)) */
604
605/* ??? What does this comment mean? */
184bb750
R
606/* cse disrupts preincrement / postdecrement squences when it finds a
607 hard register as ultimate source, like the frame pointer. */
b1a7d591 608
7bf825d2
JW
609int
610fixup_match_2 (insn, dst, src, offset, regmove_dump_file)
184bb750
R
611 rtx insn, dst, src, offset;
612 FILE *regmove_dump_file;
613{
614 rtx p, dst_death = 0;
615 int length, num_calls = 0;
616
617 /* If SRC dies in INSN, we'd have to move the death note. This is
618 considered to be very unlikely, so we just skip the optimization
619 in this case. */
620 if (find_regno_note (insn, REG_DEAD, REGNO (src)))
621 return 0;
622
623 /* Scan backward to find the first instruction that sets DST. */
624
625 for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p))
626 {
627 rtx pset;
628
629 if (GET_CODE (p) == CODE_LABEL
630 || GET_CODE (p) == JUMP_INSN
631 || (GET_CODE (p) == NOTE
632 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
633 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
634 break;
635
7bf825d2
JW
636 /* ??? We can't scan past the end of a basic block without updating
637 the register lifetime info (REG_DEAD/basic_block_live_at_start).
638 A CALL_INSN might be the last insn of a basic block, if it is inside
639 an EH region. There is no easy way to tell, so we just always break
640 when we see a CALL_INSN if flag_exceptions is nonzero. */
641 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
642 break;
643
184bb750
R
644 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
645 continue;
646
7bf825d2
JW
647 if (find_regno_note (p, REG_DEAD, REGNO (dst)))
648 dst_death = p;
649 if (! dst_death)
650 length++;
184bb750
R
651
652 pset = single_set (p);
653 if (pset && SET_DEST (pset) == dst
654 && GET_CODE (SET_SRC (pset)) == PLUS
655 && XEXP (SET_SRC (pset), 0) == src
656 && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT)
657 {
658 HOST_WIDE_INT newconst
659 = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1));
1a29f703
R
660 rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst));
661
662 if (add && validate_change (insn, &PATTERN (insn), add, 0))
184bb750
R
663 {
664 /* Remove the death note for DST from DST_DEATH. */
665 if (dst_death)
666 {
667 remove_death (REGNO (dst), dst_death);
668 REG_LIVE_LENGTH (REGNO (dst)) += length;
669 REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls;
670 }
671
672 REG_N_REFS (REGNO (dst)) += loop_depth;
673 REG_N_REFS (REGNO (src)) -= loop_depth;
674
675 if (regmove_dump_file)
676 fprintf (regmove_dump_file,
677 "Fixed operand of insn %d.\n",
678 INSN_UID (insn));
679
680#ifdef AUTO_INC_DEC
681 for (p = PREV_INSN (insn); p; p = PREV_INSN (p))
682 {
683 if (GET_CODE (p) == CODE_LABEL
684 || GET_CODE (p) == JUMP_INSN
685 || (GET_CODE (p) == NOTE
686 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
687 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
688 break;
689 if (reg_overlap_mentioned_p (dst, PATTERN (p)))
690 {
691 if (try_auto_increment (p, insn, 0, dst, newconst, 0))
692 return 1;
693 break;
694 }
695 }
696 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
697 {
698 if (GET_CODE (p) == CODE_LABEL
699 || GET_CODE (p) == JUMP_INSN
700 || (GET_CODE (p) == NOTE
701 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
702 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
703 break;
704 if (reg_overlap_mentioned_p (dst, PATTERN (p)))
705 {
706 try_auto_increment (p, insn, 0, dst, newconst, 1);
707 break;
708 }
709 }
710#endif
711 return 1;
712 }
8c660648 713 }
184bb750
R
714
715 if (reg_set_p (dst, PATTERN (p)))
716 break;
717
718 /* If we have passed a call instruction, and the
719 pseudo-reg SRC is not already live across a call,
720 then don't perform the optimization. */
721 /* reg_set_p is overly conservative for CALL_INSNS, thinks that all
722 hard regs are clobbered. Thus, we only use it for src for
723 non-call insns. */
724 if (GET_CODE (p) == CALL_INSN)
725 {
726 if (! dst_death)
727 num_calls++;
728
729 if (REG_N_CALLS_CROSSED (REGNO (src)) == 0)
730 break;
731
732 if (call_used_regs [REGNO (dst)]
733 || find_reg_fusage (p, CLOBBER, dst))
734 break;
735 }
736 else if (reg_set_p (src, PATTERN (p)))
737 break;
8c660648 738 }
184bb750 739
8c660648
JL
740 return 0;
741}
8c660648
JL
742
743void
744regmove_optimize (f, nregs, regmove_dump_file)
745 rtx f;
746 int nregs;
747 FILE *regmove_dump_file;
748{
8c660648 749 rtx insn;
184bb750 750 struct match match;
8c660648 751 int pass;
184bb750
R
752 int maxregnum = max_reg_num (), i;
753
754 regno_src_regno = (int *)alloca (sizeof *regno_src_regno * maxregnum);
755 for (i = maxregnum; --i >= 0; ) regno_src_regno[i] = -1;
8c660648
JL
756
757 /* A forward/backward pass. Replace output operands with input operands. */
758
184bb750
R
759 loop_depth = 1;
760
761 for (pass = 0; pass <= 2; pass++)
8c660648 762 {
184bb750
R
763 if (! flag_regmove && pass >= flag_expensive_optimizations)
764 return;
765
8c660648
JL
766 if (regmove_dump_file)
767 fprintf (regmove_dump_file, "Starting %s pass...\n",
768 pass ? "backward" : "forward");
769
770 for (insn = pass ? get_last_insn () : f; insn;
771 insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn))
772 {
184bb750
R
773 rtx set;
774 int insn_code_number;
775 int operand_number, match_number;
776
777 if (GET_CODE (insn) == NOTE)
8c660648 778 {
184bb750
R
779 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
780 loop_depth++;
781 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
782 loop_depth--;
783 }
8c660648 784
184bb750
R
785 set = single_set (insn);
786 if (! set)
787 continue;
8c660648 788
184bb750
R
789 if (flag_expensive_optimizations && ! pass
790 && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND
791 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND)
792 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
793 && GET_CODE (SET_DEST(set)) == REG)
794 optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set));
795
796 if (flag_expensive_optimizations && ! pass
797 && GET_CODE (SET_SRC (set)) == REG
798 && GET_CODE (SET_DEST(set)) == REG)
799 {
800 /* If this is a register-register copy where SRC is not dead,
801 see if we can optimize it. If this optimization succeeds,
802 it will become a copy where SRC is dead. */
803 if ((find_reg_note (insn, REG_DEAD, SET_SRC (set))
804 || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set)))
805 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER)
8c660648 806 {
184bb750
R
807 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
808 if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
809 optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set));
810 if (regno_src_regno[REGNO (SET_DEST (set))] < 0
811 && SET_SRC (set) != SET_DEST (set))
8c660648 812 {
184bb750
R
813 int srcregno = REGNO (SET_SRC(set));
814 if (regno_src_regno[srcregno] >= 0)
815 srcregno = regno_src_regno[srcregno];
816 regno_src_regno[REGNO (SET_DEST (set))] = srcregno;
8c660648
JL
817 }
818 }
184bb750
R
819 }
820#ifdef REGISTER_CONSTRAINTS
821 insn_code_number
822 = find_matches (insn, &match);
823
824 if (insn_code_number < 0)
825 continue;
826
827 /* Now scan through the operands looking for a source operand
828 which is supposed to match the destination operand.
829 Then scan forward for an instruction which uses the dest
830 operand.
831 If it dies there, then replace the dest in both operands with
832 the source operand. */
833
834 for (operand_number = 0;
835 operand_number < insn_n_operands[insn_code_number];
836 operand_number++)
837 {
5e9defae 838 rtx src, dst, src_subreg;
184bb750
R
839 enum reg_class src_class, dst_class;
840
841 match_number = match.with[operand_number];
842
843 /* Nothing to do if the two operands aren't supposed to match. */
844 if (match_number < 0)
845 continue;
846
847 src = recog_operand[operand_number];
848 dst = recog_operand[match_number];
849
850 if (GET_CODE (src) != REG)
851 continue;
852
853 src_subreg = src;
854 if (GET_CODE (dst) == SUBREG
855 && GET_MODE_SIZE (GET_MODE (dst))
856 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst))))
857 {
858 src_subreg
38a448ca
RH
859 = gen_rtx_SUBREG (GET_MODE (SUBREG_REG (dst)),
860 src, SUBREG_WORD (dst));
184bb750
R
861 dst = SUBREG_REG (dst);
862 }
863 if (GET_CODE (dst) != REG
864 || REGNO (dst) < FIRST_PSEUDO_REGISTER)
865 continue;
866
867 if (REGNO (src) < FIRST_PSEUDO_REGISTER)
868 {
869 if (match.commutative[operand_number] < operand_number)
870 regno_src_regno[REGNO (dst)] = REGNO (src);
871 continue;
872 }
873
874 if (REG_LIVE_LENGTH (REGNO (src)) < 0)
875 continue;
876
877 /* operand_number/src must be a read-only operand, and
878 match_operand/dst must be a write-only operand. */
879 if (match.use[operand_number] != READ
880 || match.use[match_number] != WRITE)
881 continue;
882
883 if (match.early_clobber[match_number]
884 && count_occurrences (PATTERN (insn), src) > 1)
885 continue;
886
887 /* Make sure match_operand is the destination. */
888 if (recog_operand[match_number] != SET_DEST (set))
889 continue;
890
891 /* If the operands already match, then there is nothing to do. */
892 /* But in the commutative case, we might find a better match. */
893 if (operands_match_p (src, dst)
894 || (match.commutative[operand_number] >= 0
895 && operands_match_p (recog_operand[match.commutative
896 [operand_number]], dst)
897 && (replacement_quality (recog_operand[match.commutative
898 [operand_number]])
899 >= replacement_quality (src))))
900 continue;
901
902 src_class = reg_preferred_class (REGNO (src));
903 dst_class = reg_preferred_class (REGNO (dst));
904 if (src_class != dst_class
905 && (! reg_class_subset_p (src_class, dst_class)
906 || CLASS_LIKELY_SPILLED_P (src_class))
907 && (! reg_class_subset_p (dst_class, src_class)
908 || CLASS_LIKELY_SPILLED_P (dst_class)))
909 continue;
910
911 if (fixup_match_1 (insn, set, src, src_subreg, dst, pass,
912 operand_number, match_number,
913 regmove_dump_file))
914 break;
8c660648
JL
915 }
916 }
917 }
918
919 /* A backward pass. Replace input operands with output operands. */
920
921 if (regmove_dump_file)
922 fprintf (regmove_dump_file, "Starting backward pass...\n");
923
184bb750
R
924 loop_depth = 1;
925
8c660648
JL
926 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
927 {
184bb750
R
928 if (GET_CODE (insn) == NOTE)
929 {
930 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
931 loop_depth++;
932 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
933 loop_depth--;
934 }
8c660648
JL
935 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
936 {
184bb750 937 int insn_code_number = find_matches (insn, &match);
8c660648
JL
938 int operand_number, match_number;
939
940 if (insn_code_number < 0)
941 continue;
942
8c660648
JL
943 /* Now scan through the operands looking for a destination operand
944 which is supposed to match a source operand.
945 Then scan backward for an instruction which sets the source
946 operand. If safe, then replace the source operand with the
947 dest operand in both instructions. */
948
949 for (operand_number = 0;
950 operand_number < insn_n_operands[insn_code_number];
951 operand_number++)
952 {
184bb750
R
953 rtx set, p, src, dst;
954 rtx src_note, dst_note;
a7db2896 955 int success = 0;
184bb750
R
956 int num_calls = 0;
957 enum reg_class src_class, dst_class;
958 int length;
8c660648 959
184bb750 960 match_number = match.with[operand_number];
8c660648 961
184bb750
R
962 /* Nothing to do if the two operands aren't supposed to match. */
963 if (match_number < 0)
964 continue;
8c660648 965
184bb750
R
966 dst = recog_operand[match_number];
967 src = recog_operand[operand_number];
8c660648 968
184bb750
R
969 if (GET_CODE (src) != REG)
970 continue;
8c660648 971
184bb750
R
972 if (GET_CODE (dst) != REG
973 || REGNO (dst) < FIRST_PSEUDO_REGISTER
974 || REG_LIVE_LENGTH (REGNO (dst)) < 0)
975 continue;
8c660648 976
184bb750
R
977 /* If the operands already match, then there is nothing to do. */
978 if (operands_match_p (src, dst)
979 || (match.commutative[operand_number] >= 0
980 && operands_match_p (recog_operand[match.commutative[operand_number]], dst)))
981 continue;
8c660648 982
184bb750
R
983 set = single_set (insn);
984 if (! set)
985 continue;
8c660648 986
184bb750
R
987 /* match_number/dst must be a write-only operand, and
988 operand_operand/src must be a read-only operand. */
989 if (match.use[operand_number] != READ
990 || match.use[match_number] != WRITE)
991 continue;
8c660648 992
184bb750
R
993 if (match.early_clobber[match_number]
994 && count_occurrences (PATTERN (insn), src) > 1)
995 continue;
8c660648 996
184bb750
R
997 /* Make sure match_number is the destination. */
998 if (recog_operand[match_number] != SET_DEST (set))
999 continue;
8c660648 1000
184bb750
R
1001 if (REGNO (src) < FIRST_PSEUDO_REGISTER)
1002 {
1003 if (GET_CODE (SET_SRC (set)) == PLUS
1004 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT
1005 && XEXP (SET_SRC (set), 0) == src
1006 && fixup_match_2 (insn, dst, src,
1007 XEXP (SET_SRC (set), 1),
1008 regmove_dump_file))
1009 break;
1010 continue;
1011 }
1012 src_class = reg_preferred_class (REGNO (src));
1013 dst_class = reg_preferred_class (REGNO (dst));
1014 if (src_class != dst_class
1015 && (! reg_class_subset_p (src_class, dst_class)
1016 || CLASS_LIKELY_SPILLED_P (src_class))
1017 && (! reg_class_subset_p (dst_class, src_class)
1018 || CLASS_LIKELY_SPILLED_P (dst_class)))
a7db2896
MM
1019 continue;
1020
1021 if (! (src_note = find_reg_note (insn, REG_DEAD, src)))
1022 continue;
8c660648 1023
184bb750
R
1024 /* Can not modify an earlier insn to set dst if this insn
1025 uses an old value in the source. */
1026 if (reg_overlap_mentioned_p (dst, SET_SRC (set)))
a7db2896 1027 continue;
8c660648 1028
a7db2896
MM
1029 if (regmove_dump_file)
1030 fprintf (regmove_dump_file,
1031 "Could fix operand %d of insn %d matching operand %d.\n",
1032 operand_number, INSN_UID (insn), match_number);
8c660648 1033
184bb750
R
1034 /* If src is set once in a different basic block,
1035 and is set equal to a constant, then do not use
1036 it for this optimization, as this would make it
1037 no longer equivalent to a constant. */
a7db2896
MM
1038 if (reg_is_remote_constant_p (src, insn, f))
1039 continue;
8c660648 1040
184bb750
R
1041 /* Scan backward to find the first instruction that uses
1042 the input operand. If the operand is set here, then
1043 replace it in both instructions with match_number. */
1044
1045 for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p))
1046 {
1047 rtx pset;
1048
1049 if (GET_CODE (p) == CODE_LABEL
1050 || GET_CODE (p) == JUMP_INSN
1051 || (GET_CODE (p) == NOTE
1052 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
1053 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
1054 break;
1055
7bf825d2
JW
1056 /* ??? We can't scan past the end of a basic block without
1057 updating the register lifetime info
1058 (REG_DEAD/basic_block_live_at_start).
1059 A CALL_INSN might be the last insn of a basic block, if
1060 it is inside an EH region. There is no easy way to tell,
1061 so we just always break when we see a CALL_INSN if
1062 flag_exceptions is nonzero. */
1063 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
1064 break;
1065
184bb750
R
1066 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
1067 continue;
8c660648 1068
184bb750 1069 length++;
8c660648 1070
184bb750
R
1071 /* ??? See if all of SRC is set in P. This test is much
1072 more conservative than it needs to be. */
1073 pset = single_set (p);
1074 if (pset && SET_DEST (pset) == src)
1075 {
1076 /* We use validate_replace_rtx, in case there
1077 are multiple identical source operands. All of
1078 them have to be changed at the same time. */
1079 if (validate_replace_rtx (src, dst, insn))
8c660648 1080 {
184bb750
R
1081 if (validate_change (p, &SET_DEST (pset),
1082 dst, 0))
1083 success = 1;
1084 else
8c660648 1085 {
184bb750
R
1086 /* Change all source operands back.
1087 This modifies the dst as a side-effect. */
1088 validate_replace_rtx (dst, src, insn);
1089 /* Now make sure the dst is right. */
1090 validate_change (insn,
1091 recog_operand_loc[match_number],
1092 dst, 0);
8c660648 1093 }
8c660648 1094 }
184bb750
R
1095 break;
1096 }
1097
1098 if (reg_overlap_mentioned_p (src, PATTERN (p))
1099 || reg_overlap_mentioned_p (dst, PATTERN (p)))
1100 break;
8c660648 1101
184bb750
R
1102 /* If we have passed a call instruction, and the
1103 pseudo-reg DST is not already live across a call,
1104 then don't perform the optimization. */
1105 if (GET_CODE (p) == CALL_INSN)
1106 {
1107 num_calls++;
1108
1109 if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0)
8c660648 1110 break;
184bb750
R
1111 }
1112 }
8c660648 1113
184bb750
R
1114 if (success)
1115 {
1116 int dstno, srcno;
8c660648 1117
184bb750
R
1118 /* Remove the death note for SRC from INSN. */
1119 remove_note (insn, src_note);
1120 /* Move the death note for SRC to P if it is used
1121 there. */
1122 if (reg_overlap_mentioned_p (src, PATTERN (p)))
1123 {
1124 XEXP (src_note, 1) = REG_NOTES (p);
1125 REG_NOTES (p) = src_note;
8c660648 1126 }
184bb750
R
1127 /* If there is a REG_DEAD note for DST on P, then remove
1128 it, because DST is now set there. */
5e9defae 1129 if ((dst_note = find_reg_note (p, REG_DEAD, dst)))
184bb750
R
1130 remove_note (p, dst_note);
1131
1132 dstno = REGNO (dst);
1133 srcno = REGNO (src);
1134
1135 REG_N_SETS (dstno)++;
1136 REG_N_SETS (srcno)--;
8c660648 1137
184bb750
R
1138 REG_N_CALLS_CROSSED (dstno) += num_calls;
1139 REG_N_CALLS_CROSSED (srcno) -= num_calls;
1140
1141 REG_LIVE_LENGTH (dstno) += length;
1142 if (REG_LIVE_LENGTH (srcno) >= 0)
8c660648 1143 {
184bb750
R
1144 REG_LIVE_LENGTH (srcno) -= length;
1145 /* REG_LIVE_LENGTH is only an approximation after
1146 combine if sched is not run, so make sure that we
1147 still have a reasonable value. */
1148 if (REG_LIVE_LENGTH (srcno) < 2)
1149 REG_LIVE_LENGTH (srcno) = 2;
1150 }
8c660648 1151
184bb750
R
1152 /* We assume that a register is used exactly once per
1153 insn in the updates above. If this is not correct,
1154 no great harm is done. */
8c660648 1155
184bb750
R
1156 REG_N_REFS (dstno) += 2 * loop_depth;
1157 REG_N_REFS (srcno) -= 2 * loop_depth;
8c660648 1158
184bb750
R
1159 /* If that was the only time src was set,
1160 and src was not live at the start of the
1161 function, we know that we have no more
1162 references to src; clear REG_N_REFS so it
1163 won't make reload do any work. */
1164 if (REG_N_SETS (REGNO (src)) == 0
1165 && ! regno_uninitialized (REGNO (src)))
1166 REG_N_REFS (REGNO (src)) = 0;
8c660648 1167
184bb750
R
1168 if (regmove_dump_file)
1169 fprintf (regmove_dump_file,
1170 "Fixed operand %d of insn %d matching operand %d.\n",
1171 operand_number, INSN_UID (insn), match_number);
8c660648 1172
184bb750 1173 break;
8c660648
JL
1174 }
1175 }
8c660648
JL
1176 }
1177 }
1178#endif /* REGISTER_CONSTRAINTS */
1179}
1180
b1a7d591
JW
1181/* Returns the INSN_CODE for INSN if its pattern has matching constraints for
1182 any operand. Returns -1 if INSN can't be recognized, or if the alternative
1183 can't be determined.
1184
1185 Initialize the info in MATCHP based on the constraints. */
184bb750
R
1186
1187static int
1188find_matches (insn, matchp)
1189 rtx insn;
1190 struct match *matchp;
1191{
1192 int likely_spilled[MAX_RECOG_OPERANDS];
1193 int operand_number;
1194 int insn_code_number = recog_memoized (insn);
1195 int any_matches = 0;
1196
1197 if (insn_code_number < 0)
1198 return -1;
1199
1200 insn_extract (insn);
1201 if (! constrain_operands (insn_code_number, 0))
1202 return -1;
1203
1204 /* Must initialize this before main loop, because the code for
1205 the commutative case may set matches for operands other than
1206 the current one. */
1207 for (operand_number = insn_n_operands[insn_code_number];
1208 --operand_number >= 0; )
1209 matchp->with[operand_number] = matchp->commutative[operand_number] = -1;
1210
1211 for (operand_number = 0; operand_number < insn_n_operands[insn_code_number];
1212 operand_number++)
1213 {
184bb750
R
1214 char *p, c;
1215 int i = 0;
1216
1217 p = insn_operand_constraint[insn_code_number][operand_number];
1218
1219 likely_spilled[operand_number] = 0;
1220 matchp->use[operand_number] = READ;
c485e6a0 1221 matchp->early_clobber[operand_number] = 0;
184bb750
R
1222 if (*p == '=')
1223 matchp->use[operand_number] = WRITE;
1224 else if (*p == '+')
1225 matchp->use[operand_number] = READWRITE;
1226
1227 for (;*p && i < which_alternative; p++)
1228 if (*p == ',')
1229 i++;
1230
1231 while ((c = *p++) != '\0' && c != ',')
1232 switch (c)
1233 {
1234 case '=':
1235 break;
1236 case '+':
1237 break;
1238 case '&':
1239 matchp->early_clobber[operand_number] = 1;
1240 break;
1241 case '%':
1242 matchp->commutative[operand_number] = operand_number + 1;
1243 matchp->commutative[operand_number + 1] = operand_number;
1244 break;
1245 case '0': case '1': case '2': case '3': case '4':
1246 case '5': case '6': case '7': case '8': case '9':
1247 c -= '0';
27d7e05d 1248 if (c < operand_number && likely_spilled[(unsigned char) c])
184bb750
R
1249 break;
1250 matchp->with[operand_number] = c;
1251 any_matches = 1;
1252 if (matchp->commutative[operand_number] >= 0)
1253 matchp->with[matchp->commutative[operand_number]] = c;
1254 break;
1255 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h':
1256 case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u':
1257 case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B':
1258 case 'C': case 'D': case 'W': case 'Y': case 'Z':
1259 if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_LETTER (c)))
1260 likely_spilled[operand_number] = 1;
1261 break;
1262 }
1263 }
1264 return any_matches ? insn_code_number : -1;
1265}
1266
1267/* Try to replace output operand DST in SET, with input operand SRC. SET is
1268 the only set in INSN. INSN has just been recgnized and constrained.
1269 SRC is operand number OPERAND_NUMBER in INSN.
1270 DST is operand number MATCH_NUMBER in INSN.
1271 If BACKWARD is nonzero, we have been called in a backward pass.
1272 Return nonzero for success. */
1273static int
1274fixup_match_1 (insn, set, src, src_subreg, dst, backward, operand_number,
1275 match_number, regmove_dump_file)
1276 rtx insn, set, src, src_subreg, dst;
1277 int backward, operand_number, match_number;
1278 FILE *regmove_dump_file;
1279{
1280 rtx p;
1281 rtx post_inc = 0, post_inc_set = 0, search_end = 0;
1282 int success = 0;
1283 int num_calls = 0, s_num_calls = 0;
1284 enum rtx_code code = NOTE;
1285 HOST_WIDE_INT insn_const, newconst;
1286 rtx overlap = 0; /* need to move insn ? */
1287 rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note;
1288 int length, s_length, true_loop_depth;
1289
1290 if (! src_note)
1291 {
1292 /* Look for (set (regX) (op regA constX))
1293 (set (regY) (op regA constY))
1294 and change that to
1295 (set (regA) (op regA constX)).
1296 (set (regY) (op regA constY-constX)).
1297 This works for add and shift operations, if
1298 regA is dead after or set by the second insn. */
1299
1300 code = GET_CODE (SET_SRC (set));
1301 if ((code == PLUS || code == LSHIFTRT
1302 || code == ASHIFT || code == ASHIFTRT)
1303 && XEXP (SET_SRC (set), 0) == src
1304 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
1305 insn_const = INTVAL (XEXP (SET_SRC (set), 1));
1306 else if (! stable_but_for_p (SET_SRC (set), src, dst))
1307 return 0;
1308 else
1309 /* We might find a src_note while scanning. */
1310 code = NOTE;
1311 }
1312
1313 if (regmove_dump_file)
1314 fprintf (regmove_dump_file,
1315 "Could fix operand %d of insn %d matching operand %d.\n",
1316 operand_number, INSN_UID (insn), match_number);
1317
1318 /* If SRC is equivalent to a constant set in a different basic block,
1319 then do not use it for this optimization. We want the equivalence
1320 so that if we have to reload this register, we can reload the
1321 constant, rather than extending the lifespan of the register. */
1322 if (reg_is_remote_constant_p (src, insn, get_insns ()))
1323 return 0;
1324
1325 /* Scan forward to find the next instruction that
1326 uses the output operand. If the operand dies here,
1327 then replace it in both instructions with
1328 operand_number. */
1329
1330 for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
1331 {
1332 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
1333 || (GET_CODE (p) == NOTE
1334 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
1335 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
1336 break;
1337
7bf825d2
JW
1338 /* ??? We can't scan past the end of a basic block without updating
1339 the register lifetime info (REG_DEAD/basic_block_live_at_start).
1340 A CALL_INSN might be the last insn of a basic block, if it is
1341 inside an EH region. There is no easy way to tell, so we just
1342 always break when we see a CALL_INSN if flag_exceptions is nonzero. */
1343 if (flag_exceptions && GET_CODE (p) == CALL_INSN)
1344 break;
1345
184bb750
R
1346 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
1347 continue;
1348
1349 length++;
1350 if (src_note)
1351 s_length++;
1352
1353 if (reg_set_p (src, p) || reg_set_p (dst, p)
1354 || (GET_CODE (PATTERN (p)) == USE
1355 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
1356 break;
1357
1358 /* See if all of DST dies in P. This test is
1359 slightly more conservative than it needs to be. */
1360 if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst)))
1361 && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst)))
1362 {
1363 if (! src_note)
1364 {
1365 rtx q;
1366 rtx set2;
1367
1368 /* If an optimization is done, the value of SRC while P
1369 is executed will be changed. Check that this is OK. */
1370 if (reg_overlap_mentioned_p (src, PATTERN (p)))
1371 break;
1372 for (q = p; q; q = NEXT_INSN (q))
1373 {
1374 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN
1375 || (GET_CODE (q) == NOTE
1376 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG
1377 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END)))
1378 {
1379 q = 0;
1380 break;
1381 }
7bf825d2
JW
1382
1383 /* ??? We can't scan past the end of a basic block without
1384 updating the register lifetime info
1385 (REG_DEAD/basic_block_live_at_start).
1386 A CALL_INSN might be the last insn of a basic block, if
1387 it is inside an EH region. There is no easy way to tell,
1388 so we just always break when we see a CALL_INSN if
1389 flag_exceptions is nonzero. */
a1ecb5ca 1390 if (flag_exceptions && GET_CODE (q) == CALL_INSN)
7bf825d2
JW
1391 {
1392 q = 0;
1393 break;
1394 }
1395
184bb750
R
1396 if (GET_RTX_CLASS (GET_CODE (q)) != 'i')
1397 continue;
1398 if (reg_overlap_mentioned_p (src, PATTERN (q))
1399 || reg_set_p (src, q))
1400 break;
1401 }
1402 if (q)
1403 set2 = single_set (q);
1404 if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code
1405 || XEXP (SET_SRC (set2), 0) != src
1406 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT
1407 || (SET_DEST (set2) != src
1408 && ! find_reg_note (q, REG_DEAD, src)))
1409 {
1410 /* If this is a PLUS, we can still save a register by doing
1411 src += insn_const;
1412 P;
1413 src -= insn_const; .
1414 This also gives opportunities for subsequent
1415 optimizations in the backward pass, so do it there. */
1416 if (code == PLUS && backward
1417#ifdef HAVE_cc0
1418 /* We may not emit an insn directly
1419 after P if the latter sets CC0. */
1420 && ! sets_cc0_p (PATTERN (p))
1421#endif
1422 )
1423
1424 {
1425 search_end = q;
1426 q = insn;
1427 set2 = set;
1428 newconst = -insn_const;
1429 code = MINUS;
1430 }
1431 else
1432 break;
1433 }
1434 else
1435 {
1436 newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const;
1437 /* Reject out of range shifts. */
1438 if (code != PLUS
1439 && (newconst < 0
1440 || (newconst
1441 >= GET_MODE_BITSIZE (GET_MODE (SET_SRC (set2))))))
1442 break;
1443 if (code == PLUS)
1444 {
1445 post_inc = q;
1446 if (SET_DEST (set2) != src)
1447 post_inc_set = set2;
1448 }
1449 }
1450 /* We use 1 as last argument to validate_change so that all
1451 changes are accepted or rejected together by apply_change_group
1452 when it is called by validate_replace_rtx . */
1453 validate_change (q, &XEXP (SET_SRC (set2), 1),
1454 GEN_INT (newconst), 1);
1455 }
1456 validate_change (insn, recog_operand_loc[match_number], src, 1);
1457 if (validate_replace_rtx (dst, src_subreg, p))
1458 success = 1;
1459 break;
1460 }
1461
1462 if (reg_overlap_mentioned_p (dst, PATTERN (p)))
1463 break;
1464 if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p)))
1465 {
1466 /* INSN was already checked to be movable when
1467 we found no REG_DEAD note for src on it. */
1468 overlap = p;
1469 src_note = find_reg_note (p, REG_DEAD, src);
1470 }
1471
1472 /* If we have passed a call instruction, and the pseudo-reg SRC is not
1473 already live across a call, then don't perform the optimization. */
1474 if (GET_CODE (p) == CALL_INSN)
1475 {
1476 if (REG_N_CALLS_CROSSED (REGNO (src)) == 0)
1477 break;
1478
1479 num_calls++;
1480
1481 if (src_note)
1482 s_num_calls++;
1483
1484 }
1485 }
1486
1487 if (! success)
1488 return 0;
1489
1490 true_loop_depth = backward ? 2 - loop_depth : loop_depth;
1491
1492 /* Remove the death note for DST from P. */
1493 remove_note (p, dst_note);
1494 if (code == MINUS)
1495 {
1496 post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p);
1497#if defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT)
1498 if (search_end
1499 && try_auto_increment (search_end, post_inc, 0, src, newconst, 1))
1500 post_inc = 0;
1501#endif
1502 validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0);
1503 REG_N_SETS (REGNO (src))++;
1504 REG_N_REFS (REGNO (src)) += true_loop_depth;
1505 REG_LIVE_LENGTH (REGNO (src))++;
1506 }
1507 if (overlap)
1508 {
1509 /* The lifetime of src and dest overlap,
1510 but we can change this by moving insn. */
1511 rtx pat = PATTERN (insn);
1512 if (src_note)
1513 remove_note (overlap, src_note);
1514#if defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT)
1515 if (code == PLUS
1516 && try_auto_increment (overlap, insn, 0, src, insn_const, 0))
1517 insn = overlap;
1518 else
1519#endif
1520 {
1521 rtx notes = REG_NOTES (insn);
1522
1523 emit_insn_after_with_line_notes (pat, PREV_INSN (p), insn);
1524 PUT_CODE (insn, NOTE);
1525 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1526 NOTE_SOURCE_FILE (insn) = 0;
1527 /* emit_insn_after_with_line_notes has no
1528 return value, so search for the new insn. */
1529 for (insn = p; PATTERN (insn) != pat; )
1530 insn = PREV_INSN (insn);
1531
1532 REG_NOTES (insn) = notes;
1533 }
1534 }
1535 /* Sometimes we'd generate src = const; src += n;
1536 if so, replace the instruction that set src
1537 in the first place. */
1538
1539 if (! overlap && (code == PLUS || code == MINUS))
1540 {
1541 rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1542 rtx q, set2;
1543 int num_calls2 = 0, s_length2 = 0;
1544
1545 if (note && CONSTANT_P (XEXP (note, 0)))
1546 {
1547 for (q = PREV_INSN (insn); q; q = PREV_INSN(q))
1548 {
7bf825d2
JW
1549 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN
1550 || (GET_CODE (q) == NOTE
1551 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG
1552 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END)))
184bb750
R
1553 {
1554 q = 0;
1555 break;
1556 }
7bf825d2
JW
1557
1558 /* ??? We can't scan past the end of a basic block without
1559 updating the register lifetime info
1560 (REG_DEAD/basic_block_live_at_start).
1561 A CALL_INSN might be the last insn of a basic block, if
1562 it is inside an EH region. There is no easy way to tell,
1563 so we just always break when we see a CALL_INSN if
1564 flag_exceptions is nonzero. */
a1ecb5ca 1565 if (flag_exceptions && GET_CODE (q) == CALL_INSN)
7bf825d2
JW
1566 {
1567 q = 0;
1568 break;
1569 }
1570
184bb750
R
1571 if (GET_RTX_CLASS (GET_CODE (q)) != 'i')
1572 continue;
1573 s_length2++;
1574 if (reg_set_p (src, q))
1575 {
1576 set2 = single_set (q);
1577 break;
1578 }
1579 if (reg_overlap_mentioned_p (src, PATTERN (q)))
1580 {
1581 q = 0;
1582 break;
1583 }
1584 if (GET_CODE (p) == CALL_INSN)
1585 num_calls2++;
1586 }
1587 if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2))
1588 && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0))
1589 {
1590 PUT_CODE (q, NOTE);
1591 NOTE_LINE_NUMBER (q) = NOTE_INSN_DELETED;
1592 NOTE_SOURCE_FILE (q) = 0;
1593 REG_N_SETS (REGNO (src))--;
1594 REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2;
1595 REG_N_REFS (REGNO (src)) -= true_loop_depth;
1596 REG_LIVE_LENGTH (REGNO (src)) -= s_length2;
1597 insn_const = 0;
1598 }
1599 }
1600 }
1a56b81f
AS
1601
1602 /* Don't remove this seemingly useless if, it is needed to pair with the
1603 else in the next two conditionally included code blocks. */
1604 if (0)
1605 {;}
184bb750
R
1606#if defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT)
1607 else if ((code == PLUS || code == MINUS) && insn_const
1608 && try_auto_increment (p, insn, 0, src, insn_const, 1))
1609 insn = p;
1610#endif
1611#if defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT)
1612 else if (post_inc
1613 && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0))
1614 post_inc = 0;
1615#endif
1616#if defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT)
1617 /* If post_inc still prevails, try to find an
1618 insn where it can be used as a pre-in/decrement.
1619 If code is MINUS, this was already tried. */
1620 if (post_inc && code == PLUS
1621 /* Check that newconst is likely to be usable
1622 in a pre-in/decrement before starting the search. */
1623 && (0
1624#if defined (HAVE_PRE_INCREMENT)
1625 || (newconst > 0 && newconst <= MOVE_MAX)
1626#endif
1627#if defined (HAVE_PRE_DECREMENT)
1628 || (newconst < 0 && newconst >= -MOVE_MAX)
1629#endif
1630 ) && exact_log2 (newconst))
1631 {
1632 rtx q, inc_dest;
1633
1634 inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src;
51723711 1635 for (q = post_inc; (q = NEXT_INSN (q)); )
184bb750
R
1636 {
1637 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN
1638 || (GET_CODE (q) == NOTE
1639 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG
1640 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END)))
1641 break;
7bf825d2
JW
1642
1643 /* ??? We can't scan past the end of a basic block without updating
1644 the register lifetime info (REG_DEAD/basic_block_live_at_start).
1645 A CALL_INSN might be the last insn of a basic block, if it
1646 is inside an EH region. There is no easy way to tell so we
1647 just always break when we see a CALL_INSN if flag_exceptions
1648 is nonzero. */
a1ecb5ca 1649 if (flag_exceptions && GET_CODE (q) == CALL_INSN)
7bf825d2
JW
1650 break;
1651
184bb750
R
1652 if (GET_RTX_CLASS (GET_CODE (q)) != 'i')
1653 continue;
1654 if (src != inc_dest && (reg_overlap_mentioned_p (src, PATTERN (q))
1655 || reg_set_p (src, q)))
1656 break;
1657 if (reg_set_p (inc_dest, q))
1658 break;
1659 if (reg_overlap_mentioned_p (inc_dest, PATTERN (q)))
1660 {
1661 try_auto_increment (q, post_inc,
1662 post_inc_set, inc_dest, newconst, 1);
1663 break;
1664 }
1665 }
1666 }
1667#endif /* defined (HAVE_PRE_INCREMENT) || defined (HAVE_PRE_DECREMENT) */
1668 /* Move the death note for DST to INSN if it is used
1669 there. */
1670 if (reg_overlap_mentioned_p (dst, PATTERN (insn)))
1671 {
1672 XEXP (dst_note, 1) = REG_NOTES (insn);
1673 REG_NOTES (insn) = dst_note;
1674 }
1675
1676 if (src_note)
1677 {
1678 /* Move the death note for SRC from INSN to P. */
1679 if (! overlap)
1680 remove_note (insn, src_note);
1681 XEXP (src_note, 1) = REG_NOTES (p);
1682 REG_NOTES (p) = src_note;
1683
1684 REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls;
1685 }
1686
1687 REG_N_SETS (REGNO (src))++;
1688 REG_N_SETS (REGNO (dst))--;
1689
1690 REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls;
1691
1692 REG_LIVE_LENGTH (REGNO (src)) += s_length;
1693 if (REG_LIVE_LENGTH (REGNO (dst)) >= 0)
1694 {
1695 REG_LIVE_LENGTH (REGNO (dst)) -= length;
1696 /* REG_LIVE_LENGTH is only an approximation after
1697 combine if sched is not run, so make sure that we
1698 still have a reasonable value. */
1699 if (REG_LIVE_LENGTH (REGNO (dst)) < 2)
1700 REG_LIVE_LENGTH (REGNO (dst)) = 2;
1701 }
1702
1703 /* We assume that a register is used exactly once per
1704 insn in the updates above. If this is not correct,
1705 no great harm is done. */
1706
1707 REG_N_REFS (REGNO (src)) += 2 * true_loop_depth;
1708 REG_N_REFS (REGNO (dst)) -= 2 * true_loop_depth;
1709
1710 /* If that was the only time dst was set,
1711 and dst was not live at the start of the
1712 function, we know that we have no more
1713 references to dst; clear REG_N_REFS so it
1714 won't make reload do any work. */
1715 if (REG_N_SETS (REGNO (dst)) == 0
1716 && ! regno_uninitialized (REGNO (dst)))
1717 REG_N_REFS (REGNO (dst)) = 0;
1718
1719 if (regmove_dump_file)
1720 fprintf (regmove_dump_file,
1721 "Fixed operand %d of insn %d matching operand %d.\n",
1722 operand_number, INSN_UID (insn), match_number);
1723 return 1;
1724}
1725
1726
8c660648
JL
1727/* return nonzero if X is stable but for mentioning SRC or mentioning /
1728 changing DST . If in doubt, presume it is unstable. */
1729static int
1730stable_but_for_p (x, src, dst)
1731 rtx x, src, dst;
1732{
1733 RTX_CODE code = GET_CODE (x);
1734 switch (GET_RTX_CLASS (code))
1735 {
1736 case '<': case '1': case 'c': case '2': case 'b': case '3':
1737 {
1738 int i;
1739 char *fmt = GET_RTX_FORMAT (code);
1740 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1741 if (fmt[i] == 'e' && ! stable_but_for_p (XEXP (x, i), src, dst))
1742 return 0;
1743 return 1;
1744 }
1745 case 'o':
1746 if (x == src || x == dst)
1747 return 1;
1748 /* fall through */
1749 default:
1750 return ! rtx_unstable_p (x);
1751 }
1752}
184bb750 1753
b1a7d591
JW
1754/* Test if regmove seems profitable for this target. Regmove is useful only
1755 if some common patterns are two address, i.e. require matching constraints,
1756 so we check that condition here. */
1757
184bb750
R
1758int
1759regmove_profitable_p ()
1760{
1761#ifdef REGISTER_CONSTRAINTS
1762 struct match match;
1763 enum machine_mode mode;
1764 optab tstoptab = add_optab;
1765 do /* check add_optab and ashl_optab */
1766 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1767 mode = GET_MODE_WIDER_MODE (mode))
1768 {
1769 int icode = (int) tstoptab->handlers[(int) mode].insn_code;
1770 rtx reg0, reg1, reg2, pat;
1771 int i;
1772
1773 if (GET_MODE_BITSIZE (mode) < 32 || icode == CODE_FOR_nothing)
1774 continue;
1775 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1776 if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i))
1777 break;
1778 if (i + 2 >= FIRST_PSEUDO_REGISTER)
1779 break;
38a448ca
RH
1780 reg0 = gen_rtx_REG (insn_operand_mode[icode][0], i);
1781 reg1 = gen_rtx_REG (insn_operand_mode[icode][1], i + 1);
1782 reg2 = gen_rtx_REG (insn_operand_mode[icode][2], i + 2);
184bb750
R
1783 if (! (*insn_operand_predicate[icode][0]) (reg0, VOIDmode)
1784 || ! (*insn_operand_predicate[icode][1]) (reg1, VOIDmode)
1785 || ! (*insn_operand_predicate[icode][2]) (reg2, VOIDmode))
1786 break;
1787 pat = GEN_FCN (icode) (reg0, reg1, reg2);
1788 if (! pat)
1789 continue;
1790 if (GET_CODE (pat) == SEQUENCE)
1791 pat = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1);
1792 else
1793 pat = make_insn_raw (pat);
1794 if (! single_set (pat)
1795 || GET_CODE (SET_SRC (single_set (pat))) != tstoptab->code)
1796 /* Unexpected complexity; don't need to handle this unless
1797 we find a machine where this occurs and regmove should
1798 be enabled. */
1799 break;
1800 if (find_matches (pat, &match) >= 0)
1801 return 1;
1802 break;
1803 }
1804 while (tstoptab != ashl_optab && (tstoptab = ashl_optab, 1));
1805#endif /* REGISTER_CONSTRAINTS */
1806 return 0;
1807}
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