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8c660648 | 1 | /* Move registers around to reduce number of move instructions needed. |
a5cad800 | 2 | Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. |
8c660648 JL |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
5f38fdda JL |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
8c660648 JL |
20 | |
21 | ||
22 | /* This module looks for cases where matching constraints would force | |
23 | an instruction to need a reload, and this reload would be a register | |
24 | to register move. It then attempts to change the registers used by the | |
25 | instruction to avoid the move instruction. */ | |
26 | ||
27 | #include "config.h" | |
670ee920 | 28 | #include "system.h" |
789f983a | 29 | #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ |
8c660648 JL |
30 | #include "insn-config.h" |
31 | #include "recog.h" | |
32 | #include "output.h" | |
33 | #include "reload.h" | |
34 | #include "regs.h" | |
184bb750 R |
35 | #include "hard-reg-set.h" |
36 | #include "flags.h" | |
37 | #include "expr.h" | |
38 | #include "insn-flags.h" | |
ddc8bed2 | 39 | #include "basic-block.h" |
2e107e9e | 40 | #include "toplev.h" |
184bb750 | 41 | |
1230327b R |
42 | static int optimize_reg_copy_1 PROTO((rtx, rtx, rtx)); |
43 | static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx)); | |
184bb750 | 44 | static void optimize_reg_copy_3 PROTO((rtx, rtx, rtx)); |
1a29f703 | 45 | static rtx gen_add3_insn PROTO((rtx, rtx, rtx)); |
ddc8bed2 MM |
46 | static void copy_src_to_dest PROTO((rtx, rtx, rtx, int)); |
47 | static int *regmove_bb_head; | |
8c660648 | 48 | |
184bb750 R |
49 | struct match { |
50 | int with[MAX_RECOG_OPERANDS]; | |
51 | enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS]; | |
52 | int commutative[MAX_RECOG_OPERANDS]; | |
53 | int early_clobber[MAX_RECOG_OPERANDS]; | |
54 | }; | |
55 | ||
dc2cb191 RH |
56 | static rtx discover_flags_reg PROTO((void)); |
57 | static void mark_flags_life_zones PROTO((rtx)); | |
58 | static void flags_set_1 PROTO((rtx, rtx)); | |
59 | ||
0e05e8ea | 60 | static int try_auto_increment PROTO((rtx, rtx, rtx, rtx, HOST_WIDE_INT, int)); |
184bb750 R |
61 | static int find_matches PROTO((rtx, struct match *)); |
62 | static int fixup_match_1 PROTO((rtx, rtx, rtx, rtx, rtx, int, int, int, FILE *)) | |
63 | ; | |
64 | static int reg_is_remote_constant_p PROTO((rtx, rtx, rtx)); | |
8c660648 | 65 | static int stable_but_for_p PROTO((rtx, rtx, rtx)); |
3bb806ed | 66 | static int regclass_compatible_p PROTO((int, int)); |
184bb750 | 67 | static int loop_depth; |
8c660648 | 68 | |
3bb806ed R |
69 | /* Return non-zero if registers with CLASS1 and CLASS2 can be merged without |
70 | causing too much register allocation problems. */ | |
71 | static int | |
72 | regclass_compatible_p (class0, class1) | |
73 | int class0, class1; | |
74 | { | |
75 | return (class0 == class1 | |
76 | || (reg_class_subset_p (class0, class1) | |
77 | && ! CLASS_LIKELY_SPILLED_P (class0)) | |
78 | || (reg_class_subset_p (class1, class0) | |
79 | && ! CLASS_LIKELY_SPILLED_P (class1))); | |
80 | } | |
81 | ||
1a29f703 R |
82 | /* Generate and return an insn body to add r1 and c, |
83 | storing the result in r0. */ | |
84 | static rtx | |
85 | gen_add3_insn (r0, r1, c) | |
86 | rtx r0, r1, c; | |
87 | { | |
88 | int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
89 | ||
90 | if (icode == CODE_FOR_nothing | |
91 | || ! (*insn_operand_predicate[icode][0]) (r0, insn_operand_mode[icode][0]) | |
92 | || ! (*insn_operand_predicate[icode][1]) (r1, insn_operand_mode[icode][1]) | |
93 | || ! (*insn_operand_predicate[icode][2]) (c, insn_operand_mode[icode][2])) | |
94 | return NULL_RTX; | |
95 | ||
96 | return (GEN_FCN (icode) (r0, r1, c)); | |
97 | } | |
98 | ||
8c660648 JL |
99 | |
100 | /* INC_INSN is an instruction that adds INCREMENT to REG. | |
101 | Try to fold INC_INSN as a post/pre in/decrement into INSN. | |
102 | Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src. | |
103 | Return nonzero for success. */ | |
104 | static int | |
105 | try_auto_increment (insn, inc_insn, inc_insn_set, reg, increment, pre) | |
106 | rtx reg, insn, inc_insn ,inc_insn_set; | |
107 | HOST_WIDE_INT increment; | |
108 | int pre; | |
109 | { | |
110 | enum rtx_code inc_code; | |
111 | ||
112 | rtx pset = single_set (insn); | |
113 | if (pset) | |
114 | { | |
115 | /* Can't use the size of SET_SRC, we might have something like | |
116 | (sign_extend:SI (mem:QI ... */ | |
117 | rtx use = find_use_as_address (pset, reg, 0); | |
118 | if (use != 0 && use != (rtx) 1) | |
119 | { | |
120 | int size = GET_MODE_SIZE (GET_MODE (use)); | |
121 | if (0 | |
940da324 JL |
122 | || (HAVE_POST_INCREMENT |
123 | && pre == 0 && (inc_code = POST_INC, increment == size)) | |
124 | || (HAVE_PRE_INCREMENT | |
125 | && pre == 1 && (inc_code = PRE_INC, increment == size)) | |
126 | || (HAVE_POST_DECREMENT | |
127 | && pre == 0 && (inc_code = POST_DEC, increment == -size)) | |
128 | || (HAVE_PRE_DECREMENT | |
129 | && pre == 1 && (inc_code = PRE_DEC, increment == -size)) | |
184bb750 R |
130 | ) |
131 | { | |
132 | if (inc_insn_set) | |
133 | validate_change | |
134 | (inc_insn, | |
135 | &SET_SRC (inc_insn_set), | |
8c660648 | 136 | XEXP (SET_SRC (inc_insn_set), 0), 1); |
184bb750 | 137 | validate_change (insn, &XEXP (use, 0), |
38a448ca | 138 | gen_rtx_fmt_e (inc_code, Pmode, reg), 1); |
184bb750 R |
139 | if (apply_change_group ()) |
140 | { | |
141 | REG_NOTES (insn) | |
38a448ca RH |
142 | = gen_rtx_EXPR_LIST (REG_INC, |
143 | reg, REG_NOTES (insn)); | |
184bb750 R |
144 | if (! inc_insn_set) |
145 | { | |
146 | PUT_CODE (inc_insn, NOTE); | |
147 | NOTE_LINE_NUMBER (inc_insn) = NOTE_INSN_DELETED; | |
148 | NOTE_SOURCE_FILE (inc_insn) = 0; | |
149 | } | |
8c660648 | 150 | return 1; |
184bb750 R |
151 | } |
152 | } | |
153 | } | |
154 | } | |
155 | return 0; | |
156 | } | |
dc2cb191 RH |
157 | \f |
158 | /* Determine if the pattern generated by add_optab has a clobber, | |
159 | such as might be issued for a flags hard register. To make the | |
160 | code elsewhere simpler, we handle cc0 in this same framework. | |
161 | ||
162 | Return the register if one was discovered. Return NULL_RTX if | |
163 | if no flags were found. Return pc_rtx if we got confused. */ | |
164 | ||
165 | static rtx | |
166 | discover_flags_reg () | |
167 | { | |
168 | rtx tmp; | |
cd4b3546 | 169 | tmp = gen_rtx_REG (word_mode, 10000); |
dc2cb191 RH |
170 | tmp = gen_add3_insn (tmp, tmp, GEN_INT (2)); |
171 | ||
172 | /* If we get something that isn't a simple set, or a | |
173 | [(set ..) (clobber ..)], this whole function will go wrong. */ | |
174 | if (GET_CODE (tmp) == SET) | |
175 | return NULL_RTX; | |
176 | else if (GET_CODE (tmp) == PARALLEL) | |
177 | { | |
178 | int found; | |
179 | ||
180 | if (XVECLEN (tmp, 0) != 2) | |
181 | return pc_rtx; | |
182 | tmp = XVECEXP (tmp, 0, 1); | |
183 | if (GET_CODE (tmp) != CLOBBER) | |
184 | return pc_rtx; | |
185 | tmp = XEXP (tmp, 0); | |
186 | ||
187 | /* Don't do anything foolish if the md wanted to clobber a | |
188 | scratch or something. We only care about hard regs. | |
189 | Moreover we don't like the notion of subregs of hard regs. */ | |
190 | if (GET_CODE (tmp) == SUBREG | |
191 | && GET_CODE (SUBREG_REG (tmp)) == REG | |
192 | && REGNO (SUBREG_REG (tmp)) < FIRST_PSEUDO_REGISTER) | |
193 | return pc_rtx; | |
194 | found = (GET_CODE (tmp) == REG && REGNO (tmp) < FIRST_PSEUDO_REGISTER); | |
195 | ||
dc2cb191 | 196 | return (found ? tmp : NULL_RTX); |
dc2cb191 RH |
197 | } |
198 | ||
199 | return pc_rtx; | |
200 | } | |
201 | ||
202 | /* It is a tedious task identifying when the flags register is live and | |
203 | when it is safe to optimize. Since we process the instruction stream | |
204 | multiple times, locate and record these live zones by marking the | |
205 | mode of the instructions -- | |
206 | ||
207 | QImode is used on the instruction at which the flags becomes live. | |
208 | ||
209 | HImode is used within the range (exclusive) that the flags are | |
210 | live. Thus the user of the flags is not marked. | |
211 | ||
212 | All other instructions are cleared to VOIDmode. */ | |
213 | ||
214 | /* Used to communicate with flags_set_1. */ | |
215 | static rtx flags_set_1_rtx; | |
216 | static int flags_set_1_set; | |
217 | ||
218 | static void | |
219 | mark_flags_life_zones (flags) | |
220 | rtx flags; | |
221 | { | |
222 | int flags_regno; | |
223 | int flags_nregs; | |
224 | int block; | |
225 | ||
e7f5b971 RH |
226 | #ifdef HAVE_cc0 |
227 | /* If we found a flags register on a cc0 host, bail. */ | |
228 | if (flags == NULL_RTX) | |
229 | flags = cc0_rtx; | |
230 | else if (flags != cc0_rtx) | |
231 | flags = pc_rtx; | |
232 | #endif | |
233 | ||
dc2cb191 RH |
234 | /* Simple cases first: if no flags, clear all modes. If confusing, |
235 | mark the entire function as being in a flags shadow. */ | |
236 | if (flags == NULL_RTX || flags == pc_rtx) | |
237 | { | |
238 | enum machine_mode mode = (flags ? HImode : VOIDmode); | |
239 | rtx insn; | |
240 | for (insn = get_insns(); insn; insn = NEXT_INSN (insn)) | |
241 | PUT_MODE (insn, mode); | |
242 | return; | |
243 | } | |
244 | ||
245 | #ifdef HAVE_cc0 | |
246 | flags_regno = -1; | |
247 | flags_nregs = 1; | |
248 | #else | |
249 | flags_regno = REGNO (flags); | |
250 | flags_nregs = HARD_REGNO_NREGS (flags_regno, GET_MODE (flags)); | |
251 | #endif | |
252 | flags_set_1_rtx = flags; | |
184bb750 | 253 | |
dc2cb191 RH |
254 | /* Process each basic block. */ |
255 | for (block = n_basic_blocks - 1; block >= 0; block--) | |
256 | { | |
257 | rtx insn, end; | |
258 | int live; | |
259 | ||
260 | insn = BLOCK_HEAD (block); | |
261 | end = BLOCK_END (block); | |
262 | ||
263 | /* Look out for the (unlikely) case of flags being live across | |
264 | basic block boundaries. */ | |
265 | live = 0; | |
266 | #ifndef HAVE_cc0 | |
267 | { | |
268 | int i; | |
269 | for (i = 0; i < flags_nregs; ++i) | |
270 | live |= REGNO_REG_SET_P (basic_block_live_at_start[block], | |
271 | flags_regno + i); | |
272 | } | |
273 | #endif | |
274 | ||
275 | while (1) | |
276 | { | |
277 | /* Process liveness in reverse order of importance -- | |
278 | alive, death, birth. This lets more important info | |
279 | overwrite the mode of lesser info. */ | |
280 | ||
281 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
282 | { | |
283 | #ifdef HAVE_cc0 | |
284 | /* In the cc0 case, death is not marked in reg notes, | |
285 | but is instead the mere use of cc0 when it is alive. */ | |
286 | if (live && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
287 | live = 0; | |
288 | #else | |
289 | /* In the hard reg case, we watch death notes. */ | |
290 | if (live && find_regno_note (insn, REG_DEAD, flags_regno)) | |
291 | live = 0; | |
292 | #endif | |
293 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
294 | ||
295 | /* In either case, birth is denoted simply by it's presence | |
296 | as the destination of a set. */ | |
297 | flags_set_1_set = 0; | |
298 | note_stores (PATTERN (insn), flags_set_1); | |
299 | if (flags_set_1_set) | |
300 | { | |
301 | live = 1; | |
302 | PUT_MODE (insn, QImode); | |
303 | } | |
304 | } | |
305 | else | |
306 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
307 | ||
308 | if (insn == end) | |
309 | break; | |
310 | insn = NEXT_INSN (insn); | |
311 | } | |
312 | } | |
313 | } | |
314 | ||
315 | /* A subroutine of mark_flags_life_zones, called through note_stores. */ | |
316 | ||
317 | static void | |
318 | flags_set_1 (x, pat) | |
319 | rtx x, pat; | |
320 | { | |
321 | if (GET_CODE (pat) == SET | |
322 | && reg_overlap_mentioned_p (x, flags_set_1_rtx)) | |
323 | flags_set_1_set = 1; | |
324 | } | |
325 | \f | |
184bb750 R |
326 | static int *regno_src_regno; |
327 | ||
328 | /* Indicate how good a choice REG (which appears as a source) is to replace | |
329 | a destination register with. The higher the returned value, the better | |
330 | the choice. The main objective is to avoid using a register that is | |
331 | a candidate for tying to a hard register, since the output might in | |
332 | turn be a candidate to be tied to a different hard register. */ | |
333 | int | |
334 | replacement_quality(reg) | |
335 | rtx reg; | |
336 | { | |
337 | int src_regno; | |
338 | ||
339 | /* Bad if this isn't a register at all. */ | |
340 | if (GET_CODE (reg) != REG) | |
341 | return 0; | |
342 | ||
343 | /* If this register is not meant to get a hard register, | |
344 | it is a poor choice. */ | |
345 | if (REG_LIVE_LENGTH (REGNO (reg)) < 0) | |
346 | return 0; | |
347 | ||
348 | src_regno = regno_src_regno[REGNO (reg)]; | |
349 | ||
350 | /* If it was not copied from another register, it is fine. */ | |
351 | if (src_regno < 0) | |
352 | return 3; | |
353 | ||
354 | /* Copied from a hard register? */ | |
355 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
356 | return 1; | |
357 | ||
358 | /* Copied from a pseudo register - not as bad as from a hard register, | |
359 | yet still cumbersome, since the register live length will be lengthened | |
360 | when the registers get tied. */ | |
361 | return 2; | |
362 | } | |
363 | ||
1230327b R |
364 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die |
365 | in INSN. | |
366 | ||
367 | Search forward to see if SRC dies before either it or DEST is modified, | |
368 | but don't scan past the end of a basic block. If so, we can replace SRC | |
369 | with DEST and let SRC die in INSN. | |
370 | ||
371 | This will reduce the number of registers live in that range and may enable | |
372 | DEST to be tied to SRC, thus often saving one register in addition to a | |
373 | register-register copy. */ | |
374 | ||
375 | static int | |
376 | optimize_reg_copy_1 (insn, dest, src) | |
377 | rtx insn; | |
378 | rtx dest; | |
379 | rtx src; | |
380 | { | |
381 | rtx p, q; | |
382 | rtx note; | |
383 | rtx dest_death = 0; | |
384 | int sregno = REGNO (src); | |
385 | int dregno = REGNO (dest); | |
386 | ||
387 | /* We don't want to mess with hard regs if register classes are small. */ | |
388 | if (sregno == dregno | |
389 | || (SMALL_REGISTER_CLASSES | |
390 | && (sregno < FIRST_PSEUDO_REGISTER | |
391 | || dregno < FIRST_PSEUDO_REGISTER)) | |
392 | /* We don't see all updates to SP if they are in an auto-inc memory | |
393 | reference, so we must disallow this optimization on them. */ | |
394 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) | |
395 | return 0; | |
396 | ||
397 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
398 | { | |
399 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN | |
400 | || (GET_CODE (p) == NOTE | |
401 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
402 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
403 | break; | |
404 | ||
7bf825d2 JW |
405 | /* ??? We can't scan past the end of a basic block without updating |
406 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
407 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
408 | an EH region. There is no easy way to tell, so we just always break | |
409 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
410 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
411 | break; | |
412 | ||
1230327b R |
413 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
414 | continue; | |
415 | ||
416 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
417 | /* Don't change a USE of a register. */ | |
418 | || (GET_CODE (PATTERN (p)) == USE | |
419 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
420 | break; | |
421 | ||
422 | /* See if all of SRC dies in P. This test is slightly more | |
423 | conservative than it needs to be. */ | |
424 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 | |
425 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
426 | { | |
427 | int failed = 0; | |
1230327b | 428 | int d_length = 0; |
89098dc1 | 429 | int s_length = 0; |
1230327b | 430 | int d_n_calls = 0; |
89098dc1 | 431 | int s_n_calls = 0; |
1230327b R |
432 | |
433 | /* We can do the optimization. Scan forward from INSN again, | |
434 | replacing regs as we go. Set FAILED if a replacement can't | |
435 | be done. In that case, we can't move the death note for SRC. | |
436 | This should be rare. */ | |
437 | ||
438 | /* Set to stop at next insn. */ | |
439 | for (q = next_real_insn (insn); | |
440 | q != next_real_insn (p); | |
441 | q = next_real_insn (q)) | |
442 | { | |
443 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
444 | { | |
445 | /* If SRC is a hard register, we might miss some | |
446 | overlapping registers with validate_replace_rtx, | |
447 | so we would have to undo it. We can't if DEST is | |
448 | present in the insn, so fail in that combination | |
449 | of cases. */ | |
450 | if (sregno < FIRST_PSEUDO_REGISTER | |
451 | && reg_mentioned_p (dest, PATTERN (q))) | |
452 | failed = 1; | |
453 | ||
454 | /* Replace all uses and make sure that the register | |
455 | isn't still present. */ | |
456 | else if (validate_replace_rtx (src, dest, q) | |
457 | && (sregno >= FIRST_PSEUDO_REGISTER | |
458 | || ! reg_overlap_mentioned_p (src, | |
459 | PATTERN (q)))) | |
460 | { | |
461 | /* We assume that a register is used exactly once per | |
7b31b7d9 JL |
462 | insn in the REG_N_REFS updates below. If this is not |
463 | correct, no great harm is done. | |
464 | ||
89098dc1 JL |
465 | Since we do not know if we will change the lifetime of |
466 | SREGNO or DREGNO, we must not update REG_LIVE_LENGTH | |
467 | or REG_N_CALLS_CROSSED at this time. */ | |
1230327b | 468 | if (sregno >= FIRST_PSEUDO_REGISTER) |
89098dc1 | 469 | REG_N_REFS (sregno) -= loop_depth; |
7b31b7d9 | 470 | |
1230327b | 471 | if (dregno >= FIRST_PSEUDO_REGISTER) |
89098dc1 | 472 | REG_N_REFS (dregno) += loop_depth; |
1230327b R |
473 | } |
474 | else | |
475 | { | |
476 | validate_replace_rtx (dest, src, q); | |
477 | failed = 1; | |
478 | } | |
479 | } | |
480 | ||
89098dc1 JL |
481 | /* For SREGNO, count the total number of insns scanned. |
482 | For DREGNO, count the total number of insns scanned after | |
483 | passing the death note for DREGNO. */ | |
484 | s_length++; | |
1230327b R |
485 | if (dest_death) |
486 | d_length++; | |
487 | ||
488 | /* If the insn in which SRC dies is a CALL_INSN, don't count it | |
489 | as a call that has been crossed. Otherwise, count it. */ | |
490 | if (q != p && GET_CODE (q) == CALL_INSN) | |
491 | { | |
89098dc1 JL |
492 | /* Similarly, total calls for SREGNO, total calls beyond |
493 | the death note for DREGNO. */ | |
494 | s_n_calls++; | |
1230327b R |
495 | if (dest_death) |
496 | d_n_calls++; | |
497 | } | |
498 | ||
499 | /* If DEST dies here, remove the death note and save it for | |
500 | later. Make sure ALL of DEST dies here; again, this is | |
501 | overly conservative. */ | |
502 | if (dest_death == 0 | |
503 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0) | |
504 | { | |
505 | if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest)) | |
506 | failed = 1, dest_death = 0; | |
507 | else | |
508 | remove_note (q, dest_death); | |
509 | } | |
510 | } | |
511 | ||
512 | if (! failed) | |
513 | { | |
89098dc1 JL |
514 | /* These counters need to be updated if and only if we are |
515 | going to move the REG_DEAD note. */ | |
1230327b R |
516 | if (sregno >= FIRST_PSEUDO_REGISTER) |
517 | { | |
518 | if (REG_LIVE_LENGTH (sregno) >= 0) | |
519 | { | |
89098dc1 | 520 | REG_LIVE_LENGTH (sregno) -= s_length; |
1230327b R |
521 | /* REG_LIVE_LENGTH is only an approximation after |
522 | combine if sched is not run, so make sure that we | |
523 | still have a reasonable value. */ | |
524 | if (REG_LIVE_LENGTH (sregno) < 2) | |
525 | REG_LIVE_LENGTH (sregno) = 2; | |
526 | } | |
527 | ||
89098dc1 | 528 | REG_N_CALLS_CROSSED (sregno) -= s_n_calls; |
1230327b R |
529 | } |
530 | ||
531 | /* Move death note of SRC from P to INSN. */ | |
532 | remove_note (p, note); | |
533 | XEXP (note, 1) = REG_NOTES (insn); | |
534 | REG_NOTES (insn) = note; | |
535 | } | |
536 | ||
537 | /* Put death note of DEST on P if we saw it die. */ | |
538 | if (dest_death) | |
539 | { | |
540 | XEXP (dest_death, 1) = REG_NOTES (p); | |
541 | REG_NOTES (p) = dest_death; | |
89098dc1 JL |
542 | |
543 | if (dregno >= FIRST_PSEUDO_REGISTER) | |
544 | { | |
545 | /* If and only if we are moving the death note for DREGNO, | |
546 | then we need to update its counters. */ | |
547 | if (REG_LIVE_LENGTH (dregno) >= 0) | |
548 | REG_LIVE_LENGTH (dregno) += d_length; | |
549 | REG_N_CALLS_CROSSED (dregno) += d_n_calls; | |
550 | } | |
1230327b R |
551 | } |
552 | ||
553 | return ! failed; | |
554 | } | |
555 | ||
556 | /* If SRC is a hard register which is set or killed in some other | |
557 | way, we can't do this optimization. */ | |
558 | else if (sregno < FIRST_PSEUDO_REGISTER | |
559 | && dead_or_set_p (p, src)) | |
560 | break; | |
561 | } | |
562 | return 0; | |
563 | } | |
564 | \f | |
565 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have | |
566 | a sequence of insns that modify DEST followed by an insn that sets | |
567 | SRC to DEST in which DEST dies, with no prior modification of DEST. | |
568 | (There is no need to check if the insns in between actually modify | |
569 | DEST. We should not have cases where DEST is not modified, but | |
570 | the optimization is safe if no such modification is detected.) | |
571 | In that case, we can replace all uses of DEST, starting with INSN and | |
572 | ending with the set of SRC to DEST, with SRC. We do not do this | |
573 | optimization if a CALL_INSN is crossed unless SRC already crosses a | |
574 | call or if DEST dies before the copy back to SRC. | |
575 | ||
576 | It is assumed that DEST and SRC are pseudos; it is too complicated to do | |
577 | this for hard registers since the substitutions we may make might fail. */ | |
578 | ||
579 | static void | |
580 | optimize_reg_copy_2 (insn, dest, src) | |
581 | rtx insn; | |
582 | rtx dest; | |
583 | rtx src; | |
584 | { | |
585 | rtx p, q; | |
586 | rtx set; | |
587 | int sregno = REGNO (src); | |
588 | int dregno = REGNO (dest); | |
589 | ||
590 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
591 | { | |
592 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN | |
593 | || (GET_CODE (p) == NOTE | |
594 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
595 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
596 | break; | |
597 | ||
7bf825d2 JW |
598 | /* ??? We can't scan past the end of a basic block without updating |
599 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
600 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
601 | an EH region. There is no easy way to tell, so we just always break | |
602 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
603 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
604 | break; | |
605 | ||
1230327b R |
606 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
607 | continue; | |
608 | ||
609 | set = single_set (p); | |
610 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src | |
611 | && find_reg_note (p, REG_DEAD, dest)) | |
612 | { | |
613 | /* We can do the optimization. Scan forward from INSN again, | |
614 | replacing regs as we go. */ | |
615 | ||
616 | /* Set to stop at next insn. */ | |
617 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) | |
618 | if (GET_RTX_CLASS (GET_CODE (q)) == 'i') | |
619 | { | |
620 | if (reg_mentioned_p (dest, PATTERN (q))) | |
621 | { | |
622 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); | |
623 | ||
624 | /* We assume that a register is used exactly once per | |
625 | insn in the updates below. If this is not correct, | |
626 | no great harm is done. */ | |
627 | REG_N_REFS (dregno) -= loop_depth; | |
628 | REG_N_REFS (sregno) += loop_depth; | |
629 | } | |
630 | ||
631 | ||
632 | if (GET_CODE (q) == CALL_INSN) | |
633 | { | |
634 | REG_N_CALLS_CROSSED (dregno)--; | |
635 | REG_N_CALLS_CROSSED (sregno)++; | |
636 | } | |
637 | } | |
638 | ||
639 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); | |
640 | REG_N_DEATHS (dregno)--; | |
641 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); | |
642 | REG_N_DEATHS (sregno)--; | |
643 | return; | |
644 | } | |
645 | ||
646 | if (reg_set_p (src, p) | |
647 | || find_reg_note (p, REG_DEAD, dest) | |
648 | || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0)) | |
649 | break; | |
650 | } | |
651 | } | |
184bb750 R |
652 | /* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST. |
653 | Look if SRC dies there, and if it is only set once, by loading | |
654 | it from memory. If so, try to encorporate the zero/sign extension | |
655 | into the memory read, change SRC to the mode of DEST, and alter | |
656 | the remaining accesses to use the appropriate SUBREG. This allows | |
657 | SRC and DEST to be tied later. */ | |
658 | static void | |
659 | optimize_reg_copy_3 (insn, dest, src) | |
660 | rtx insn; | |
661 | rtx dest; | |
662 | rtx src; | |
663 | { | |
664 | rtx src_reg = XEXP (src, 0); | |
665 | int src_no = REGNO (src_reg); | |
666 | int dst_no = REGNO (dest); | |
667 | rtx p, set, subreg; | |
668 | enum machine_mode old_mode; | |
669 | ||
670 | if (src_no < FIRST_PSEUDO_REGISTER | |
671 | || dst_no < FIRST_PSEUDO_REGISTER | |
672 | || ! find_reg_note (insn, REG_DEAD, src_reg) | |
673 | || REG_N_SETS (src_no) != 1) | |
674 | return; | |
675 | for (p = PREV_INSN (insn); ! reg_set_p (src_reg, p); p = PREV_INSN (p)) | |
676 | { | |
7bf825d2 JW |
677 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN |
678 | || (GET_CODE (p) == NOTE | |
679 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
680 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
681 | return; | |
682 | ||
683 | /* ??? We can't scan past the end of a basic block without updating | |
684 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
685 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
686 | an EH region. There is no easy way to tell, so we just always break | |
687 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
688 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
689 | return; | |
690 | ||
184bb750 R |
691 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
692 | continue; | |
184bb750 R |
693 | } |
694 | if (! (set = single_set (p)) | |
695 | || GET_CODE (SET_SRC (set)) != MEM | |
696 | || SET_DEST (set) != src_reg) | |
697 | return; | |
937e37cc | 698 | |
972b320c R |
699 | /* Be conserative: although this optimization is also valid for |
700 | volatile memory references, that could cause trouble in later passes. */ | |
701 | if (MEM_VOLATILE_P (SET_SRC (set))) | |
702 | return; | |
703 | ||
937e37cc JL |
704 | /* Do not use a SUBREG to truncate from one mode to another if truncation |
705 | is not a nop. */ | |
706 | if (GET_MODE_BITSIZE (GET_MODE (src_reg)) <= GET_MODE_BITSIZE (GET_MODE (src)) | |
707 | && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src)), | |
708 | GET_MODE_BITSIZE (GET_MODE (src_reg)))) | |
709 | return; | |
710 | ||
184bb750 R |
711 | old_mode = GET_MODE (src_reg); |
712 | PUT_MODE (src_reg, GET_MODE (src)); | |
713 | XEXP (src, 0) = SET_SRC (set); | |
e757da5e JL |
714 | |
715 | /* Include this change in the group so that it's easily undone if | |
716 | one of the changes in the group is invalid. */ | |
717 | validate_change (p, &SET_SRC (set), src, 1); | |
718 | ||
719 | /* Now walk forward making additional replacements. We want to be able | |
720 | to undo all the changes if a later substitution fails. */ | |
38a448ca | 721 | subreg = gen_rtx_SUBREG (old_mode, src_reg, 0); |
184bb750 R |
722 | while (p = NEXT_INSN (p), p != insn) |
723 | { | |
724 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
725 | continue; | |
e757da5e JL |
726 | |
727 | /* Make a tenative change. */ | |
728 | validate_replace_rtx_group (src_reg, subreg, p); | |
729 | } | |
730 | ||
731 | validate_replace_rtx_group (src, src_reg, insn); | |
732 | ||
733 | /* Now see if all the changes are valid. */ | |
734 | if (! apply_change_group ()) | |
735 | { | |
736 | /* One or more changes were no good. Back out everything. */ | |
737 | PUT_MODE (src_reg, old_mode); | |
738 | XEXP (src, 0) = src_reg; | |
184bb750 | 739 | } |
184bb750 R |
740 | } |
741 | ||
ddc8bed2 MM |
742 | \f |
743 | /* If we were not able to update the users of src to use dest directly, try | |
744 | instead moving the value to dest directly before the operation. */ | |
745 | ||
cab634f2 | 746 | static void |
ddc8bed2 MM |
747 | copy_src_to_dest (insn, src, dest, loop_depth) |
748 | rtx insn; | |
749 | rtx src; | |
750 | rtx dest; | |
29a4c5ed | 751 | int loop_depth; |
ddc8bed2 MM |
752 | { |
753 | rtx seq; | |
754 | rtx link; | |
755 | rtx next; | |
756 | rtx set; | |
757 | rtx move_insn; | |
758 | rtx *p_insn_notes; | |
759 | rtx *p_move_notes; | |
ddc8bed2 MM |
760 | int src_regno; |
761 | int dest_regno; | |
762 | int bb; | |
763 | int insn_uid; | |
764 | int move_uid; | |
765 | ||
766 | /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant | |
767 | or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is | |
768 | parameter when there is no frame pointer that is not allocated a register. | |
769 | For now, we just reject them, rather than incrementing the live length. */ | |
770 | ||
3ac3da71 MM |
771 | if (GET_CODE (src) == REG |
772 | && REG_LIVE_LENGTH (REGNO (src)) > 0 | |
773 | && GET_CODE (dest) == REG | |
774 | && REG_LIVE_LENGTH (REGNO (dest)) > 0 | |
ddc8bed2 | 775 | && (set = single_set (insn)) != NULL_RTX |
9d2106a4 R |
776 | && !reg_mentioned_p (dest, SET_SRC (set)) |
777 | && GET_MODE (src) == GET_MODE (dest)) | |
ddc8bed2 | 778 | { |
1a8fca8a R |
779 | int old_num_regs = reg_rtx_no; |
780 | ||
ddc8bed2 MM |
781 | /* Generate the src->dest move. */ |
782 | start_sequence (); | |
783 | emit_move_insn (dest, src); | |
784 | seq = gen_sequence (); | |
785 | end_sequence (); | |
1a8fca8a R |
786 | /* If this sequence uses new registers, we may not use it. */ |
787 | if (old_num_regs != reg_rtx_no | |
788 | || ! validate_replace_rtx (src, dest, insn)) | |
789 | { | |
790 | /* We have to restore reg_rtx_no to its old value, lest | |
791 | recompute_reg_usage will try to compute the usage of the | |
792 | new regs, yet reg_n_info is not valid for them. */ | |
793 | reg_rtx_no = old_num_regs; | |
794 | return; | |
795 | } | |
ddc8bed2 MM |
796 | emit_insn_before (seq, insn); |
797 | move_insn = PREV_INSN (insn); | |
798 | p_move_notes = ®_NOTES (move_insn); | |
799 | p_insn_notes = ®_NOTES (insn); | |
800 | ||
801 | /* Move any notes mentioning src to the move instruction */ | |
802 | for (link = REG_NOTES (insn); link != NULL_RTX; link = next) | |
803 | { | |
804 | next = XEXP (link, 1); | |
805 | if (XEXP (link, 0) == src) | |
806 | { | |
807 | *p_move_notes = link; | |
808 | p_move_notes = &XEXP (link, 1); | |
809 | } | |
810 | else | |
811 | { | |
812 | *p_insn_notes = link; | |
813 | p_insn_notes = &XEXP (link, 1); | |
814 | } | |
815 | } | |
816 | ||
817 | *p_move_notes = NULL_RTX; | |
818 | *p_insn_notes = NULL_RTX; | |
819 | ||
820 | /* Is the insn the head of a basic block? If so extend it */ | |
821 | insn_uid = INSN_UID (insn); | |
822 | move_uid = INSN_UID (move_insn); | |
823 | bb = regmove_bb_head[insn_uid]; | |
824 | if (bb >= 0) | |
825 | { | |
3b413743 | 826 | BLOCK_HEAD (bb) = move_insn; |
ddc8bed2 MM |
827 | regmove_bb_head[insn_uid] = -1; |
828 | } | |
829 | ||
830 | /* Update the various register tables. */ | |
831 | dest_regno = REGNO (dest); | |
832 | REG_N_SETS (dest_regno) += loop_depth; | |
833 | REG_N_REFS (dest_regno) += loop_depth; | |
834 | REG_LIVE_LENGTH (dest_regno)++; | |
835 | if (REGNO_FIRST_UID (dest_regno) == insn_uid) | |
836 | REGNO_FIRST_UID (dest_regno) = move_uid; | |
837 | ||
838 | src_regno = REGNO (src); | |
839 | if (! find_reg_note (move_insn, REG_DEAD, src)) | |
840 | REG_LIVE_LENGTH (src_regno)++; | |
841 | ||
842 | if (REGNO_FIRST_UID (src_regno) == insn_uid) | |
843 | REGNO_FIRST_UID (src_regno) = move_uid; | |
844 | ||
845 | if (REGNO_LAST_UID (src_regno) == insn_uid) | |
846 | REGNO_LAST_UID (src_regno) = move_uid; | |
847 | ||
848 | if (REGNO_LAST_NOTE_UID (src_regno) == insn_uid) | |
849 | REGNO_LAST_NOTE_UID (src_regno) = move_uid; | |
850 | } | |
851 | } | |
852 | ||
853 | \f | |
184bb750 R |
854 | /* Return whether REG is set in only one location, and is set to a |
855 | constant, but is set in a different basic block from INSN (an | |
856 | instructions which uses REG). In this case REG is equivalent to a | |
857 | constant, and we don't want to break that equivalence, because that | |
858 | may increase register pressure and make reload harder. If REG is | |
859 | set in the same basic block as INSN, we don't worry about it, | |
860 | because we'll probably need a register anyhow (??? but what if REG | |
861 | is used in a different basic block as well as this one?). FIRST is | |
862 | the first insn in the function. */ | |
863 | ||
864 | static int | |
865 | reg_is_remote_constant_p (reg, insn, first) | |
866 | rtx reg; | |
867 | rtx insn; | |
868 | rtx first; | |
869 | { | |
870 | register rtx p; | |
871 | ||
872 | if (REG_N_SETS (REGNO (reg)) != 1) | |
873 | return 0; | |
874 | ||
875 | /* Look for the set. */ | |
876 | for (p = LOG_LINKS (insn); p; p = XEXP (p, 1)) | |
877 | { | |
878 | rtx s; | |
879 | ||
880 | if (REG_NOTE_KIND (p) != 0) | |
881 | continue; | |
882 | s = single_set (XEXP (p, 0)); | |
883 | if (s != 0 | |
884 | && GET_CODE (SET_DEST (s)) == REG | |
885 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
886 | { | |
887 | /* The register is set in the same basic block. */ | |
888 | return 0; | |
889 | } | |
890 | } | |
891 | ||
892 | for (p = first; p && p != insn; p = NEXT_INSN (p)) | |
893 | { | |
894 | rtx s; | |
895 | ||
896 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
897 | continue; | |
898 | s = single_set (p); | |
899 | if (s != 0 | |
900 | && GET_CODE (SET_DEST (s)) == REG | |
901 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
902 | { | |
903 | /* This is the instruction which sets REG. If there is a | |
904 | REG_EQUAL note, then REG is equivalent to a constant. */ | |
905 | if (find_reg_note (p, REG_EQUAL, NULL_RTX)) | |
906 | return 1; | |
907 | return 0; | |
908 | } | |
909 | } | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
b1a7d591 JW |
914 | /* INSN is adding a CONST_INT to a REG. We search backwards looking for |
915 | another add immediate instruction with the same source and dest registers, | |
916 | and if we find one, we change INSN to an increment, and return 1. If | |
917 | no changes are made, we return 0. | |
918 | ||
919 | This changes | |
920 | (set (reg100) (plus reg1 offset1)) | |
921 | ... | |
922 | (set (reg100) (plus reg1 offset2)) | |
923 | to | |
924 | (set (reg100) (plus reg1 offset1)) | |
925 | ... | |
926 | (set (reg100) (plus reg100 offset2-offset1)) */ | |
927 | ||
928 | /* ??? What does this comment mean? */ | |
184bb750 R |
929 | /* cse disrupts preincrement / postdecrement squences when it finds a |
930 | hard register as ultimate source, like the frame pointer. */ | |
b1a7d591 | 931 | |
7bf825d2 JW |
932 | int |
933 | fixup_match_2 (insn, dst, src, offset, regmove_dump_file) | |
184bb750 R |
934 | rtx insn, dst, src, offset; |
935 | FILE *regmove_dump_file; | |
936 | { | |
937 | rtx p, dst_death = 0; | |
938 | int length, num_calls = 0; | |
939 | ||
940 | /* If SRC dies in INSN, we'd have to move the death note. This is | |
941 | considered to be very unlikely, so we just skip the optimization | |
942 | in this case. */ | |
943 | if (find_regno_note (insn, REG_DEAD, REGNO (src))) | |
944 | return 0; | |
945 | ||
946 | /* Scan backward to find the first instruction that sets DST. */ | |
947 | ||
948 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
949 | { | |
950 | rtx pset; | |
951 | ||
952 | if (GET_CODE (p) == CODE_LABEL | |
953 | || GET_CODE (p) == JUMP_INSN | |
954 | || (GET_CODE (p) == NOTE | |
955 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
956 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
957 | break; | |
958 | ||
7bf825d2 JW |
959 | /* ??? We can't scan past the end of a basic block without updating |
960 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
961 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
962 | an EH region. There is no easy way to tell, so we just always break | |
963 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
964 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
965 | break; | |
966 | ||
184bb750 R |
967 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
968 | continue; | |
969 | ||
7bf825d2 JW |
970 | if (find_regno_note (p, REG_DEAD, REGNO (dst))) |
971 | dst_death = p; | |
972 | if (! dst_death) | |
973 | length++; | |
184bb750 R |
974 | |
975 | pset = single_set (p); | |
976 | if (pset && SET_DEST (pset) == dst | |
977 | && GET_CODE (SET_SRC (pset)) == PLUS | |
978 | && XEXP (SET_SRC (pset), 0) == src | |
979 | && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT) | |
980 | { | |
981 | HOST_WIDE_INT newconst | |
982 | = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1)); | |
1a29f703 R |
983 | rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst)); |
984 | ||
985 | if (add && validate_change (insn, &PATTERN (insn), add, 0)) | |
184bb750 R |
986 | { |
987 | /* Remove the death note for DST from DST_DEATH. */ | |
988 | if (dst_death) | |
989 | { | |
990 | remove_death (REGNO (dst), dst_death); | |
991 | REG_LIVE_LENGTH (REGNO (dst)) += length; | |
992 | REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls; | |
993 | } | |
994 | ||
995 | REG_N_REFS (REGNO (dst)) += loop_depth; | |
996 | REG_N_REFS (REGNO (src)) -= loop_depth; | |
997 | ||
998 | if (regmove_dump_file) | |
999 | fprintf (regmove_dump_file, | |
1000 | "Fixed operand of insn %d.\n", | |
1001 | INSN_UID (insn)); | |
1002 | ||
1003 | #ifdef AUTO_INC_DEC | |
1004 | for (p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1005 | { | |
1006 | if (GET_CODE (p) == CODE_LABEL | |
1007 | || GET_CODE (p) == JUMP_INSN | |
1008 | || (GET_CODE (p) == NOTE | |
1009 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
1010 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
1011 | break; | |
e27a5106 JL |
1012 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
1013 | continue; | |
184bb750 R |
1014 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1015 | { | |
1016 | if (try_auto_increment (p, insn, 0, dst, newconst, 0)) | |
1017 | return 1; | |
1018 | break; | |
1019 | } | |
1020 | } | |
1021 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1022 | { | |
1023 | if (GET_CODE (p) == CODE_LABEL | |
1024 | || GET_CODE (p) == JUMP_INSN | |
1025 | || (GET_CODE (p) == NOTE | |
1026 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
1027 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
1028 | break; | |
8543c01e R |
1029 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
1030 | continue; | |
184bb750 R |
1031 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1032 | { | |
1033 | try_auto_increment (p, insn, 0, dst, newconst, 1); | |
1034 | break; | |
1035 | } | |
1036 | } | |
1037 | #endif | |
1038 | return 1; | |
1039 | } | |
8c660648 | 1040 | } |
184bb750 R |
1041 | |
1042 | if (reg_set_p (dst, PATTERN (p))) | |
1043 | break; | |
1044 | ||
1045 | /* If we have passed a call instruction, and the | |
1046 | pseudo-reg SRC is not already live across a call, | |
1047 | then don't perform the optimization. */ | |
1048 | /* reg_set_p is overly conservative for CALL_INSNS, thinks that all | |
1049 | hard regs are clobbered. Thus, we only use it for src for | |
1050 | non-call insns. */ | |
1051 | if (GET_CODE (p) == CALL_INSN) | |
1052 | { | |
1053 | if (! dst_death) | |
1054 | num_calls++; | |
1055 | ||
1056 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1057 | break; | |
1058 | ||
1059 | if (call_used_regs [REGNO (dst)] | |
1060 | || find_reg_fusage (p, CLOBBER, dst)) | |
1061 | break; | |
1062 | } | |
1063 | else if (reg_set_p (src, PATTERN (p))) | |
1064 | break; | |
8c660648 | 1065 | } |
184bb750 | 1066 | |
8c660648 JL |
1067 | return 0; |
1068 | } | |
8c660648 JL |
1069 | |
1070 | void | |
1071 | regmove_optimize (f, nregs, regmove_dump_file) | |
1072 | rtx f; | |
1073 | int nregs; | |
1074 | FILE *regmove_dump_file; | |
1075 | { | |
961d4119 | 1076 | int old_max_uid = get_max_uid (); |
8c660648 | 1077 | rtx insn; |
184bb750 | 1078 | struct match match; |
8c660648 | 1079 | int pass; |
3bb806ed | 1080 | int i; |
ddc8bed2 | 1081 | rtx copy_src, copy_dst; |
184bb750 | 1082 | |
dc2cb191 RH |
1083 | /* Find out where a potential flags register is live, and so that we |
1084 | can supress some optimizations in those zones. */ | |
1085 | mark_flags_life_zones (discover_flags_reg ()); | |
1086 | ||
3bb806ed R |
1087 | regno_src_regno = (int *)alloca (sizeof *regno_src_regno * nregs); |
1088 | for (i = nregs; --i >= 0; ) regno_src_regno[i] = -1; | |
8c660648 | 1089 | |
961d4119 BS |
1090 | regmove_bb_head = (int *)alloca (sizeof (int) * (old_max_uid + 1)); |
1091 | for (i = old_max_uid; i >= 0; i--) regmove_bb_head[i] = -1; | |
ddc8bed2 | 1092 | for (i = 0; i < n_basic_blocks; i++) |
3b413743 | 1093 | regmove_bb_head[INSN_UID (BLOCK_HEAD (i))] = i; |
ddc8bed2 | 1094 | |
8c660648 JL |
1095 | /* A forward/backward pass. Replace output operands with input operands. */ |
1096 | ||
184bb750 R |
1097 | loop_depth = 1; |
1098 | ||
1099 | for (pass = 0; pass <= 2; pass++) | |
8c660648 | 1100 | { |
184bb750 R |
1101 | if (! flag_regmove && pass >= flag_expensive_optimizations) |
1102 | return; | |
1103 | ||
8c660648 JL |
1104 | if (regmove_dump_file) |
1105 | fprintf (regmove_dump_file, "Starting %s pass...\n", | |
1106 | pass ? "backward" : "forward"); | |
1107 | ||
1108 | for (insn = pass ? get_last_insn () : f; insn; | |
1109 | insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn)) | |
1110 | { | |
184bb750 | 1111 | rtx set; |
0eadeb15 | 1112 | int op_no, match_no; |
184bb750 R |
1113 | |
1114 | if (GET_CODE (insn) == NOTE) | |
8c660648 | 1115 | { |
184bb750 R |
1116 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) |
1117 | loop_depth++; | |
1118 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
1119 | loop_depth--; | |
1120 | } | |
8c660648 | 1121 | |
184bb750 R |
1122 | set = single_set (insn); |
1123 | if (! set) | |
1124 | continue; | |
8c660648 | 1125 | |
184bb750 R |
1126 | if (flag_expensive_optimizations && ! pass |
1127 | && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND | |
1128 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND) | |
1129 | && GET_CODE (XEXP (SET_SRC (set), 0)) == REG | |
1130 | && GET_CODE (SET_DEST(set)) == REG) | |
1131 | optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set)); | |
1132 | ||
1133 | if (flag_expensive_optimizations && ! pass | |
1134 | && GET_CODE (SET_SRC (set)) == REG | |
1135 | && GET_CODE (SET_DEST(set)) == REG) | |
1136 | { | |
1137 | /* If this is a register-register copy where SRC is not dead, | |
1138 | see if we can optimize it. If this optimization succeeds, | |
1139 | it will become a copy where SRC is dead. */ | |
1140 | if ((find_reg_note (insn, REG_DEAD, SET_SRC (set)) | |
1141 | || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set))) | |
1142 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) | |
8c660648 | 1143 | { |
184bb750 R |
1144 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ |
1145 | if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1146 | optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set)); | |
1147 | if (regno_src_regno[REGNO (SET_DEST (set))] < 0 | |
1148 | && SET_SRC (set) != SET_DEST (set)) | |
8c660648 | 1149 | { |
184bb750 R |
1150 | int srcregno = REGNO (SET_SRC(set)); |
1151 | if (regno_src_regno[srcregno] >= 0) | |
1152 | srcregno = regno_src_regno[srcregno]; | |
1153 | regno_src_regno[REGNO (SET_DEST (set))] = srcregno; | |
8c660648 JL |
1154 | } |
1155 | } | |
184bb750 | 1156 | } |
8d1d76c1 R |
1157 | if (! flag_regmove) |
1158 | continue; | |
184bb750 | 1159 | |
0eadeb15 | 1160 | #ifdef REGISTER_CONSTRAINTS |
3363316f | 1161 | if (! find_matches (insn, &match)) |
184bb750 R |
1162 | continue; |
1163 | ||
1164 | /* Now scan through the operands looking for a source operand | |
1165 | which is supposed to match the destination operand. | |
1166 | Then scan forward for an instruction which uses the dest | |
1167 | operand. | |
1168 | If it dies there, then replace the dest in both operands with | |
1169 | the source operand. */ | |
1170 | ||
0eadeb15 | 1171 | for (op_no = 0; op_no < recog_n_operands; op_no++) |
184bb750 | 1172 | { |
5e9defae | 1173 | rtx src, dst, src_subreg; |
184bb750 R |
1174 | enum reg_class src_class, dst_class; |
1175 | ||
0eadeb15 | 1176 | match_no = match.with[op_no]; |
184bb750 R |
1177 | |
1178 | /* Nothing to do if the two operands aren't supposed to match. */ | |
0eadeb15 | 1179 | if (match_no < 0) |
184bb750 R |
1180 | continue; |
1181 | ||
0eadeb15 BS |
1182 | src = recog_operand[op_no]; |
1183 | dst = recog_operand[match_no]; | |
184bb750 R |
1184 | |
1185 | if (GET_CODE (src) != REG) | |
1186 | continue; | |
1187 | ||
1188 | src_subreg = src; | |
1189 | if (GET_CODE (dst) == SUBREG | |
1190 | && GET_MODE_SIZE (GET_MODE (dst)) | |
1191 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst)))) | |
1192 | { | |
1193 | src_subreg | |
38a448ca RH |
1194 | = gen_rtx_SUBREG (GET_MODE (SUBREG_REG (dst)), |
1195 | src, SUBREG_WORD (dst)); | |
184bb750 R |
1196 | dst = SUBREG_REG (dst); |
1197 | } | |
1198 | if (GET_CODE (dst) != REG | |
1199 | || REGNO (dst) < FIRST_PSEUDO_REGISTER) | |
1200 | continue; | |
1201 | ||
1202 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) | |
1203 | { | |
0eadeb15 | 1204 | if (match.commutative[op_no] < op_no) |
184bb750 R |
1205 | regno_src_regno[REGNO (dst)] = REGNO (src); |
1206 | continue; | |
1207 | } | |
1208 | ||
1209 | if (REG_LIVE_LENGTH (REGNO (src)) < 0) | |
1210 | continue; | |
1211 | ||
0eadeb15 | 1212 | /* op_no/src must be a read-only operand, and |
184bb750 | 1213 | match_operand/dst must be a write-only operand. */ |
0eadeb15 BS |
1214 | if (match.use[op_no] != READ |
1215 | || match.use[match_no] != WRITE) | |
184bb750 R |
1216 | continue; |
1217 | ||
0eadeb15 | 1218 | if (match.early_clobber[match_no] |
184bb750 R |
1219 | && count_occurrences (PATTERN (insn), src) > 1) |
1220 | continue; | |
1221 | ||
1222 | /* Make sure match_operand is the destination. */ | |
0eadeb15 | 1223 | if (recog_operand[match_no] != SET_DEST (set)) |
184bb750 R |
1224 | continue; |
1225 | ||
1226 | /* If the operands already match, then there is nothing to do. */ | |
1227 | /* But in the commutative case, we might find a better match. */ | |
1228 | if (operands_match_p (src, dst) | |
0eadeb15 | 1229 | || (match.commutative[op_no] >= 0 |
184bb750 | 1230 | && operands_match_p (recog_operand[match.commutative |
0eadeb15 | 1231 | [op_no]], dst) |
184bb750 | 1232 | && (replacement_quality (recog_operand[match.commutative |
0eadeb15 | 1233 | [op_no]]) |
184bb750 R |
1234 | >= replacement_quality (src)))) |
1235 | continue; | |
1236 | ||
1237 | src_class = reg_preferred_class (REGNO (src)); | |
1238 | dst_class = reg_preferred_class (REGNO (dst)); | |
3bb806ed | 1239 | if (! regclass_compatible_p (src_class, dst_class)) |
184bb750 R |
1240 | continue; |
1241 | ||
1242 | if (fixup_match_1 (insn, set, src, src_subreg, dst, pass, | |
0eadeb15 | 1243 | op_no, match_no, |
184bb750 R |
1244 | regmove_dump_file)) |
1245 | break; | |
8c660648 JL |
1246 | } |
1247 | } | |
1248 | } | |
1249 | ||
1250 | /* A backward pass. Replace input operands with output operands. */ | |
1251 | ||
1252 | if (regmove_dump_file) | |
1253 | fprintf (regmove_dump_file, "Starting backward pass...\n"); | |
1254 | ||
184bb750 R |
1255 | loop_depth = 1; |
1256 | ||
8c660648 JL |
1257 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) |
1258 | { | |
184bb750 R |
1259 | if (GET_CODE (insn) == NOTE) |
1260 | { | |
1261 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
1262 | loop_depth++; | |
1263 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
1264 | loop_depth--; | |
1265 | } | |
8c660648 JL |
1266 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') |
1267 | { | |
0eadeb15 | 1268 | int op_no, match_no; |
ddc8bed2 | 1269 | int success = 0; |
0eadeb15 | 1270 | |
3363316f | 1271 | if (! find_matches (insn, &match)) |
8c660648 JL |
1272 | continue; |
1273 | ||
8c660648 JL |
1274 | /* Now scan through the operands looking for a destination operand |
1275 | which is supposed to match a source operand. | |
1276 | Then scan backward for an instruction which sets the source | |
1277 | operand. If safe, then replace the source operand with the | |
1278 | dest operand in both instructions. */ | |
1279 | ||
ddc8bed2 MM |
1280 | copy_src = NULL_RTX; |
1281 | copy_dst = NULL_RTX; | |
0eadeb15 | 1282 | for (op_no = 0; op_no < recog_n_operands; op_no++) |
8c660648 | 1283 | { |
184bb750 R |
1284 | rtx set, p, src, dst; |
1285 | rtx src_note, dst_note; | |
184bb750 R |
1286 | int num_calls = 0; |
1287 | enum reg_class src_class, dst_class; | |
1288 | int length; | |
8c660648 | 1289 | |
0eadeb15 | 1290 | match_no = match.with[op_no]; |
8c660648 | 1291 | |
184bb750 | 1292 | /* Nothing to do if the two operands aren't supposed to match. */ |
0eadeb15 | 1293 | if (match_no < 0) |
184bb750 | 1294 | continue; |
8c660648 | 1295 | |
0eadeb15 BS |
1296 | dst = recog_operand[match_no]; |
1297 | src = recog_operand[op_no]; | |
8c660648 | 1298 | |
184bb750 R |
1299 | if (GET_CODE (src) != REG) |
1300 | continue; | |
8c660648 | 1301 | |
184bb750 R |
1302 | if (GET_CODE (dst) != REG |
1303 | || REGNO (dst) < FIRST_PSEUDO_REGISTER | |
1304 | || REG_LIVE_LENGTH (REGNO (dst)) < 0) | |
1305 | continue; | |
8c660648 | 1306 | |
184bb750 R |
1307 | /* If the operands already match, then there is nothing to do. */ |
1308 | if (operands_match_p (src, dst) | |
0eadeb15 BS |
1309 | || (match.commutative[op_no] >= 0 |
1310 | && operands_match_p (recog_operand[match.commutative[op_no]], dst))) | |
184bb750 | 1311 | continue; |
8c660648 | 1312 | |
184bb750 R |
1313 | set = single_set (insn); |
1314 | if (! set) | |
1315 | continue; | |
8c660648 | 1316 | |
0eadeb15 | 1317 | /* match_no/dst must be a write-only operand, and |
184bb750 | 1318 | operand_operand/src must be a read-only operand. */ |
0eadeb15 BS |
1319 | if (match.use[op_no] != READ |
1320 | || match.use[match_no] != WRITE) | |
184bb750 | 1321 | continue; |
8c660648 | 1322 | |
0eadeb15 | 1323 | if (match.early_clobber[match_no] |
184bb750 R |
1324 | && count_occurrences (PATTERN (insn), src) > 1) |
1325 | continue; | |
8c660648 | 1326 | |
0eadeb15 BS |
1327 | /* Make sure match_no is the destination. */ |
1328 | if (recog_operand[match_no] != SET_DEST (set)) | |
184bb750 | 1329 | continue; |
8c660648 | 1330 | |
184bb750 R |
1331 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) |
1332 | { | |
1333 | if (GET_CODE (SET_SRC (set)) == PLUS | |
1334 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT | |
1335 | && XEXP (SET_SRC (set), 0) == src | |
1336 | && fixup_match_2 (insn, dst, src, | |
1337 | XEXP (SET_SRC (set), 1), | |
1338 | regmove_dump_file)) | |
1339 | break; | |
1340 | continue; | |
1341 | } | |
1342 | src_class = reg_preferred_class (REGNO (src)); | |
1343 | dst_class = reg_preferred_class (REGNO (dst)); | |
3bb806ed | 1344 | if (! regclass_compatible_p (src_class, dst_class)) |
ddc8bed2 MM |
1345 | { |
1346 | if (!copy_src) | |
1347 | { | |
1348 | copy_src = src; | |
1349 | copy_dst = dst; | |
1350 | } | |
1351 | continue; | |
1352 | } | |
8c660648 | 1353 | |
184bb750 R |
1354 | /* Can not modify an earlier insn to set dst if this insn |
1355 | uses an old value in the source. */ | |
1356 | if (reg_overlap_mentioned_p (dst, SET_SRC (set))) | |
ddc8bed2 MM |
1357 | { |
1358 | if (!copy_src) | |
1359 | { | |
1360 | copy_src = src; | |
1361 | copy_dst = dst; | |
1362 | } | |
1363 | continue; | |
1364 | } | |
1365 | ||
1366 | if (! (src_note = find_reg_note (insn, REG_DEAD, src))) | |
1367 | { | |
1368 | if (!copy_src) | |
1369 | { | |
1370 | copy_src = src; | |
1371 | copy_dst = dst; | |
1372 | } | |
1373 | continue; | |
1374 | } | |
8c660648 | 1375 | |
8c660648 | 1376 | |
184bb750 R |
1377 | /* If src is set once in a different basic block, |
1378 | and is set equal to a constant, then do not use | |
1379 | it for this optimization, as this would make it | |
1380 | no longer equivalent to a constant. */ | |
ddc8bed2 MM |
1381 | |
1382 | if (reg_is_remote_constant_p (src, insn, f)) | |
1383 | { | |
1384 | if (!copy_src) | |
1385 | { | |
1386 | copy_src = src; | |
1387 | copy_dst = dst; | |
1388 | } | |
1389 | continue; | |
1390 | } | |
1391 | ||
1392 | ||
1393 | if (regmove_dump_file) | |
1394 | fprintf (regmove_dump_file, | |
1395 | "Could fix operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1396 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1397 | |
184bb750 R |
1398 | /* Scan backward to find the first instruction that uses |
1399 | the input operand. If the operand is set here, then | |
0eadeb15 | 1400 | replace it in both instructions with match_no. */ |
184bb750 R |
1401 | |
1402 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1403 | { | |
1404 | rtx pset; | |
1405 | ||
1406 | if (GET_CODE (p) == CODE_LABEL | |
1407 | || GET_CODE (p) == JUMP_INSN | |
1408 | || (GET_CODE (p) == NOTE | |
1409 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
1410 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
1411 | break; | |
1412 | ||
7bf825d2 JW |
1413 | /* ??? We can't scan past the end of a basic block without |
1414 | updating the register lifetime info | |
1415 | (REG_DEAD/basic_block_live_at_start). | |
1416 | A CALL_INSN might be the last insn of a basic block, if | |
1417 | it is inside an EH region. There is no easy way to tell, | |
1418 | so we just always break when we see a CALL_INSN if | |
1419 | flag_exceptions is nonzero. */ | |
1420 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
1421 | break; | |
1422 | ||
184bb750 R |
1423 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
1424 | continue; | |
8c660648 | 1425 | |
184bb750 | 1426 | length++; |
8c660648 | 1427 | |
184bb750 R |
1428 | /* ??? See if all of SRC is set in P. This test is much |
1429 | more conservative than it needs to be. */ | |
1430 | pset = single_set (p); | |
1431 | if (pset && SET_DEST (pset) == src) | |
1432 | { | |
1433 | /* We use validate_replace_rtx, in case there | |
1434 | are multiple identical source operands. All of | |
1435 | them have to be changed at the same time. */ | |
1436 | if (validate_replace_rtx (src, dst, insn)) | |
8c660648 | 1437 | { |
184bb750 R |
1438 | if (validate_change (p, &SET_DEST (pset), |
1439 | dst, 0)) | |
1440 | success = 1; | |
1441 | else | |
8c660648 | 1442 | { |
184bb750 R |
1443 | /* Change all source operands back. |
1444 | This modifies the dst as a side-effect. */ | |
1445 | validate_replace_rtx (dst, src, insn); | |
1446 | /* Now make sure the dst is right. */ | |
1447 | validate_change (insn, | |
0eadeb15 | 1448 | recog_operand_loc[match_no], |
184bb750 | 1449 | dst, 0); |
8c660648 | 1450 | } |
8c660648 | 1451 | } |
184bb750 R |
1452 | break; |
1453 | } | |
1454 | ||
1455 | if (reg_overlap_mentioned_p (src, PATTERN (p)) | |
1456 | || reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1457 | break; | |
8c660648 | 1458 | |
184bb750 R |
1459 | /* If we have passed a call instruction, and the |
1460 | pseudo-reg DST is not already live across a call, | |
1461 | then don't perform the optimization. */ | |
1462 | if (GET_CODE (p) == CALL_INSN) | |
1463 | { | |
1464 | num_calls++; | |
1465 | ||
1466 | if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0) | |
8c660648 | 1467 | break; |
184bb750 R |
1468 | } |
1469 | } | |
8c660648 | 1470 | |
184bb750 R |
1471 | if (success) |
1472 | { | |
1473 | int dstno, srcno; | |
8c660648 | 1474 | |
184bb750 R |
1475 | /* Remove the death note for SRC from INSN. */ |
1476 | remove_note (insn, src_note); | |
1477 | /* Move the death note for SRC to P if it is used | |
1478 | there. */ | |
1479 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1480 | { | |
1481 | XEXP (src_note, 1) = REG_NOTES (p); | |
1482 | REG_NOTES (p) = src_note; | |
8c660648 | 1483 | } |
184bb750 R |
1484 | /* If there is a REG_DEAD note for DST on P, then remove |
1485 | it, because DST is now set there. */ | |
5e9defae | 1486 | if ((dst_note = find_reg_note (p, REG_DEAD, dst))) |
184bb750 R |
1487 | remove_note (p, dst_note); |
1488 | ||
1489 | dstno = REGNO (dst); | |
1490 | srcno = REGNO (src); | |
1491 | ||
1492 | REG_N_SETS (dstno)++; | |
1493 | REG_N_SETS (srcno)--; | |
8c660648 | 1494 | |
184bb750 R |
1495 | REG_N_CALLS_CROSSED (dstno) += num_calls; |
1496 | REG_N_CALLS_CROSSED (srcno) -= num_calls; | |
1497 | ||
1498 | REG_LIVE_LENGTH (dstno) += length; | |
1499 | if (REG_LIVE_LENGTH (srcno) >= 0) | |
8c660648 | 1500 | { |
184bb750 R |
1501 | REG_LIVE_LENGTH (srcno) -= length; |
1502 | /* REG_LIVE_LENGTH is only an approximation after | |
1503 | combine if sched is not run, so make sure that we | |
1504 | still have a reasonable value. */ | |
1505 | if (REG_LIVE_LENGTH (srcno) < 2) | |
1506 | REG_LIVE_LENGTH (srcno) = 2; | |
1507 | } | |
8c660648 | 1508 | |
184bb750 R |
1509 | /* We assume that a register is used exactly once per |
1510 | insn in the updates above. If this is not correct, | |
1511 | no great harm is done. */ | |
8c660648 | 1512 | |
184bb750 R |
1513 | REG_N_REFS (dstno) += 2 * loop_depth; |
1514 | REG_N_REFS (srcno) -= 2 * loop_depth; | |
8c660648 | 1515 | |
184bb750 R |
1516 | /* If that was the only time src was set, |
1517 | and src was not live at the start of the | |
1518 | function, we know that we have no more | |
1519 | references to src; clear REG_N_REFS so it | |
1520 | won't make reload do any work. */ | |
1521 | if (REG_N_SETS (REGNO (src)) == 0 | |
1522 | && ! regno_uninitialized (REGNO (src))) | |
1523 | REG_N_REFS (REGNO (src)) = 0; | |
8c660648 | 1524 | |
184bb750 R |
1525 | if (regmove_dump_file) |
1526 | fprintf (regmove_dump_file, | |
1527 | "Fixed operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1528 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1529 | |
184bb750 | 1530 | break; |
8c660648 JL |
1531 | } |
1532 | } | |
ddc8bed2 MM |
1533 | |
1534 | /* If we weren't able to replace any of the alternatives, try an | |
1535 | alternative appoach of copying the source to the destination. */ | |
1536 | if (!success && copy_src != NULL_RTX) | |
1537 | copy_src_to_dest (insn, copy_src, copy_dst, loop_depth); | |
1538 | ||
8c660648 JL |
1539 | } |
1540 | } | |
1541 | #endif /* REGISTER_CONSTRAINTS */ | |
961d4119 BS |
1542 | |
1543 | /* In fixup_match_1, some insns may have been inserted after basic block | |
1544 | ends. Fix that here. */ | |
1545 | for (i = 0; i < n_basic_blocks; i++) | |
1546 | { | |
3b413743 | 1547 | rtx end = BLOCK_END (i); |
961d4119 BS |
1548 | rtx new = end; |
1549 | rtx next = NEXT_INSN (new); | |
1550 | while (next != 0 && INSN_UID (next) >= old_max_uid | |
3b413743 | 1551 | && (i == n_basic_blocks - 1 || BLOCK_HEAD (i + 1) != next)) |
961d4119 | 1552 | new = next, next = NEXT_INSN (new); |
3b413743 | 1553 | BLOCK_END (i) = new; |
961d4119 | 1554 | } |
8c660648 JL |
1555 | } |
1556 | ||
0eadeb15 BS |
1557 | /* Returns nonzero if INSN's pattern has matching constraints for any operand. |
1558 | Returns 0 if INSN can't be recognized, or if the alternative can't be | |
1559 | determined. | |
b1a7d591 JW |
1560 | |
1561 | Initialize the info in MATCHP based on the constraints. */ | |
184bb750 R |
1562 | |
1563 | static int | |
1564 | find_matches (insn, matchp) | |
1565 | rtx insn; | |
1566 | struct match *matchp; | |
1567 | { | |
1568 | int likely_spilled[MAX_RECOG_OPERANDS]; | |
0eadeb15 | 1569 | int op_no; |
184bb750 R |
1570 | int any_matches = 0; |
1571 | ||
0eadeb15 BS |
1572 | extract_insn (insn); |
1573 | if (! constrain_operands (0)) | |
1574 | return 0; | |
184bb750 R |
1575 | |
1576 | /* Must initialize this before main loop, because the code for | |
1577 | the commutative case may set matches for operands other than | |
1578 | the current one. */ | |
0eadeb15 BS |
1579 | for (op_no = recog_n_operands; --op_no >= 0; ) |
1580 | matchp->with[op_no] = matchp->commutative[op_no] = -1; | |
184bb750 | 1581 | |
0eadeb15 | 1582 | for (op_no = 0; op_no < recog_n_operands; op_no++) |
184bb750 | 1583 | { |
9b3142b3 KG |
1584 | const char *p; |
1585 | char c; | |
184bb750 R |
1586 | int i = 0; |
1587 | ||
0eadeb15 | 1588 | p = recog_constraints[op_no]; |
184bb750 | 1589 | |
0eadeb15 BS |
1590 | likely_spilled[op_no] = 0; |
1591 | matchp->use[op_no] = READ; | |
1592 | matchp->early_clobber[op_no] = 0; | |
184bb750 | 1593 | if (*p == '=') |
0eadeb15 | 1594 | matchp->use[op_no] = WRITE; |
184bb750 | 1595 | else if (*p == '+') |
0eadeb15 | 1596 | matchp->use[op_no] = READWRITE; |
184bb750 R |
1597 | |
1598 | for (;*p && i < which_alternative; p++) | |
1599 | if (*p == ',') | |
1600 | i++; | |
1601 | ||
1602 | while ((c = *p++) != '\0' && c != ',') | |
1603 | switch (c) | |
1604 | { | |
1605 | case '=': | |
1606 | break; | |
1607 | case '+': | |
1608 | break; | |
1609 | case '&': | |
0eadeb15 | 1610 | matchp->early_clobber[op_no] = 1; |
184bb750 R |
1611 | break; |
1612 | case '%': | |
0eadeb15 BS |
1613 | matchp->commutative[op_no] = op_no + 1; |
1614 | matchp->commutative[op_no + 1] = op_no; | |
184bb750 R |
1615 | break; |
1616 | case '0': case '1': case '2': case '3': case '4': | |
1617 | case '5': case '6': case '7': case '8': case '9': | |
1618 | c -= '0'; | |
0eadeb15 | 1619 | if (c < op_no && likely_spilled[(unsigned char) c]) |
184bb750 | 1620 | break; |
0eadeb15 | 1621 | matchp->with[op_no] = c; |
184bb750 | 1622 | any_matches = 1; |
0eadeb15 BS |
1623 | if (matchp->commutative[op_no] >= 0) |
1624 | matchp->with[matchp->commutative[op_no]] = c; | |
184bb750 R |
1625 | break; |
1626 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h': | |
1627 | case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u': | |
1628 | case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B': | |
1629 | case 'C': case 'D': case 'W': case 'Y': case 'Z': | |
973838fd | 1630 | if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_LETTER ((unsigned char)c))) |
0eadeb15 | 1631 | likely_spilled[op_no] = 1; |
184bb750 R |
1632 | break; |
1633 | } | |
1634 | } | |
0eadeb15 | 1635 | return any_matches; |
184bb750 R |
1636 | } |
1637 | ||
1638 | /* Try to replace output operand DST in SET, with input operand SRC. SET is | |
1639 | the only set in INSN. INSN has just been recgnized and constrained. | |
1640 | SRC is operand number OPERAND_NUMBER in INSN. | |
1641 | DST is operand number MATCH_NUMBER in INSN. | |
1642 | If BACKWARD is nonzero, we have been called in a backward pass. | |
1643 | Return nonzero for success. */ | |
1644 | static int | |
1645 | fixup_match_1 (insn, set, src, src_subreg, dst, backward, operand_number, | |
1646 | match_number, regmove_dump_file) | |
1647 | rtx insn, set, src, src_subreg, dst; | |
1648 | int backward, operand_number, match_number; | |
1649 | FILE *regmove_dump_file; | |
1650 | { | |
1651 | rtx p; | |
1652 | rtx post_inc = 0, post_inc_set = 0, search_end = 0; | |
1653 | int success = 0; | |
1654 | int num_calls = 0, s_num_calls = 0; | |
1655 | enum rtx_code code = NOTE; | |
1656 | HOST_WIDE_INT insn_const, newconst; | |
1657 | rtx overlap = 0; /* need to move insn ? */ | |
1658 | rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note; | |
1659 | int length, s_length, true_loop_depth; | |
1660 | ||
1661 | if (! src_note) | |
1662 | { | |
1663 | /* Look for (set (regX) (op regA constX)) | |
1664 | (set (regY) (op regA constY)) | |
1665 | and change that to | |
1666 | (set (regA) (op regA constX)). | |
1667 | (set (regY) (op regA constY-constX)). | |
1668 | This works for add and shift operations, if | |
1669 | regA is dead after or set by the second insn. */ | |
1670 | ||
1671 | code = GET_CODE (SET_SRC (set)); | |
1672 | if ((code == PLUS || code == LSHIFTRT | |
1673 | || code == ASHIFT || code == ASHIFTRT) | |
1674 | && XEXP (SET_SRC (set), 0) == src | |
1675 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
1676 | insn_const = INTVAL (XEXP (SET_SRC (set), 1)); | |
1677 | else if (! stable_but_for_p (SET_SRC (set), src, dst)) | |
1678 | return 0; | |
1679 | else | |
1680 | /* We might find a src_note while scanning. */ | |
1681 | code = NOTE; | |
1682 | } | |
1683 | ||
1684 | if (regmove_dump_file) | |
1685 | fprintf (regmove_dump_file, | |
1686 | "Could fix operand %d of insn %d matching operand %d.\n", | |
1687 | operand_number, INSN_UID (insn), match_number); | |
1688 | ||
1689 | /* If SRC is equivalent to a constant set in a different basic block, | |
1690 | then do not use it for this optimization. We want the equivalence | |
1691 | so that if we have to reload this register, we can reload the | |
1692 | constant, rather than extending the lifespan of the register. */ | |
1693 | if (reg_is_remote_constant_p (src, insn, get_insns ())) | |
1694 | return 0; | |
1695 | ||
1696 | /* Scan forward to find the next instruction that | |
1697 | uses the output operand. If the operand dies here, | |
1698 | then replace it in both instructions with | |
1699 | operand_number. */ | |
1700 | ||
1701 | for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1702 | { | |
1703 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN | |
1704 | || (GET_CODE (p) == NOTE | |
1705 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
1706 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
1707 | break; | |
1708 | ||
7bf825d2 JW |
1709 | /* ??? We can't scan past the end of a basic block without updating |
1710 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
1711 | A CALL_INSN might be the last insn of a basic block, if it is | |
1712 | inside an EH region. There is no easy way to tell, so we just | |
1713 | always break when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
1714 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
1715 | break; | |
1716 | ||
184bb750 R |
1717 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
1718 | continue; | |
1719 | ||
1720 | length++; | |
1721 | if (src_note) | |
1722 | s_length++; | |
1723 | ||
1724 | if (reg_set_p (src, p) || reg_set_p (dst, p) | |
1725 | || (GET_CODE (PATTERN (p)) == USE | |
1726 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
1727 | break; | |
1728 | ||
1729 | /* See if all of DST dies in P. This test is | |
1730 | slightly more conservative than it needs to be. */ | |
1731 | if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst))) | |
1732 | && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst))) | |
1733 | { | |
1734 | if (! src_note) | |
1735 | { | |
1736 | rtx q; | |
1737 | rtx set2; | |
1738 | ||
1739 | /* If an optimization is done, the value of SRC while P | |
1740 | is executed will be changed. Check that this is OK. */ | |
1741 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1742 | break; | |
1743 | for (q = p; q; q = NEXT_INSN (q)) | |
1744 | { | |
1745 | if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN | |
1746 | || (GET_CODE (q) == NOTE | |
1747 | && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG | |
1748 | || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END))) | |
1749 | { | |
1750 | q = 0; | |
1751 | break; | |
1752 | } | |
7bf825d2 JW |
1753 | |
1754 | /* ??? We can't scan past the end of a basic block without | |
1755 | updating the register lifetime info | |
1756 | (REG_DEAD/basic_block_live_at_start). | |
1757 | A CALL_INSN might be the last insn of a basic block, if | |
1758 | it is inside an EH region. There is no easy way to tell, | |
1759 | so we just always break when we see a CALL_INSN if | |
1760 | flag_exceptions is nonzero. */ | |
a1ecb5ca | 1761 | if (flag_exceptions && GET_CODE (q) == CALL_INSN) |
7bf825d2 JW |
1762 | { |
1763 | q = 0; | |
1764 | break; | |
1765 | } | |
1766 | ||
184bb750 R |
1767 | if (GET_RTX_CLASS (GET_CODE (q)) != 'i') |
1768 | continue; | |
1769 | if (reg_overlap_mentioned_p (src, PATTERN (q)) | |
1770 | || reg_set_p (src, q)) | |
1771 | break; | |
1772 | } | |
1773 | if (q) | |
1774 | set2 = single_set (q); | |
1775 | if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code | |
1776 | || XEXP (SET_SRC (set2), 0) != src | |
1777 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT | |
1778 | || (SET_DEST (set2) != src | |
1779 | && ! find_reg_note (q, REG_DEAD, src))) | |
1780 | { | |
1781 | /* If this is a PLUS, we can still save a register by doing | |
1782 | src += insn_const; | |
1783 | P; | |
1784 | src -= insn_const; . | |
1785 | This also gives opportunities for subsequent | |
1786 | optimizations in the backward pass, so do it there. */ | |
1787 | if (code == PLUS && backward | |
3bb806ed R |
1788 | /* Don't do this if we can likely tie DST to SET_DEST |
1789 | of P later; we can't do this tying here if we got a | |
1790 | hard register. */ | |
1791 | && ! (dst_note && ! REG_N_CALLS_CROSSED (REGNO (dst)) | |
1792 | && single_set (p) | |
1793 | && GET_CODE (SET_DEST (single_set (p))) == REG | |
1794 | && (REGNO (SET_DEST (single_set (p))) | |
1795 | < FIRST_PSEUDO_REGISTER)) | |
dc2cb191 RH |
1796 | /* We may only emit an insn directly after P if we |
1797 | are not in the shadow of a live flags register. */ | |
1798 | && GET_MODE (p) == VOIDmode) | |
184bb750 R |
1799 | { |
1800 | search_end = q; | |
1801 | q = insn; | |
1802 | set2 = set; | |
1803 | newconst = -insn_const; | |
1804 | code = MINUS; | |
1805 | } | |
1806 | else | |
1807 | break; | |
1808 | } | |
1809 | else | |
1810 | { | |
1811 | newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const; | |
1812 | /* Reject out of range shifts. */ | |
1813 | if (code != PLUS | |
1814 | && (newconst < 0 | |
1815 | || (newconst | |
1816 | >= GET_MODE_BITSIZE (GET_MODE (SET_SRC (set2)))))) | |
1817 | break; | |
1818 | if (code == PLUS) | |
1819 | { | |
1820 | post_inc = q; | |
1821 | if (SET_DEST (set2) != src) | |
1822 | post_inc_set = set2; | |
1823 | } | |
1824 | } | |
1825 | /* We use 1 as last argument to validate_change so that all | |
1826 | changes are accepted or rejected together by apply_change_group | |
1827 | when it is called by validate_replace_rtx . */ | |
1828 | validate_change (q, &XEXP (SET_SRC (set2), 1), | |
1829 | GEN_INT (newconst), 1); | |
1830 | } | |
1831 | validate_change (insn, recog_operand_loc[match_number], src, 1); | |
1832 | if (validate_replace_rtx (dst, src_subreg, p)) | |
1833 | success = 1; | |
1834 | break; | |
1835 | } | |
1836 | ||
1837 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1838 | break; | |
1839 | if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p))) | |
1840 | { | |
1841 | /* INSN was already checked to be movable when | |
1842 | we found no REG_DEAD note for src on it. */ | |
1843 | overlap = p; | |
1844 | src_note = find_reg_note (p, REG_DEAD, src); | |
1845 | } | |
1846 | ||
1847 | /* If we have passed a call instruction, and the pseudo-reg SRC is not | |
1848 | already live across a call, then don't perform the optimization. */ | |
1849 | if (GET_CODE (p) == CALL_INSN) | |
1850 | { | |
1851 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1852 | break; | |
1853 | ||
1854 | num_calls++; | |
1855 | ||
1856 | if (src_note) | |
1857 | s_num_calls++; | |
1858 | ||
1859 | } | |
1860 | } | |
1861 | ||
1862 | if (! success) | |
1863 | return 0; | |
1864 | ||
1865 | true_loop_depth = backward ? 2 - loop_depth : loop_depth; | |
1866 | ||
1867 | /* Remove the death note for DST from P. */ | |
1868 | remove_note (p, dst_note); | |
1869 | if (code == MINUS) | |
1870 | { | |
1871 | post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p); | |
940da324 JL |
1872 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
1873 | && search_end | |
184bb750 R |
1874 | && try_auto_increment (search_end, post_inc, 0, src, newconst, 1)) |
1875 | post_inc = 0; | |
184bb750 R |
1876 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0); |
1877 | REG_N_SETS (REGNO (src))++; | |
1878 | REG_N_REFS (REGNO (src)) += true_loop_depth; | |
1879 | REG_LIVE_LENGTH (REGNO (src))++; | |
1880 | } | |
1881 | if (overlap) | |
1882 | { | |
1883 | /* The lifetime of src and dest overlap, | |
1884 | but we can change this by moving insn. */ | |
1885 | rtx pat = PATTERN (insn); | |
1886 | if (src_note) | |
1887 | remove_note (overlap, src_note); | |
1888 | #if defined (HAVE_POST_INCREMENT) || defined (HAVE_POST_DECREMENT) | |
1889 | if (code == PLUS | |
1890 | && try_auto_increment (overlap, insn, 0, src, insn_const, 0)) | |
1891 | insn = overlap; | |
1892 | else | |
1893 | #endif | |
1894 | { | |
1895 | rtx notes = REG_NOTES (insn); | |
1896 | ||
1897 | emit_insn_after_with_line_notes (pat, PREV_INSN (p), insn); | |
1898 | PUT_CODE (insn, NOTE); | |
1899 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1900 | NOTE_SOURCE_FILE (insn) = 0; | |
1901 | /* emit_insn_after_with_line_notes has no | |
1902 | return value, so search for the new insn. */ | |
1903 | for (insn = p; PATTERN (insn) != pat; ) | |
1904 | insn = PREV_INSN (insn); | |
1905 | ||
1906 | REG_NOTES (insn) = notes; | |
1907 | } | |
1908 | } | |
1909 | /* Sometimes we'd generate src = const; src += n; | |
1910 | if so, replace the instruction that set src | |
1911 | in the first place. */ | |
1912 | ||
1913 | if (! overlap && (code == PLUS || code == MINUS)) | |
1914 | { | |
1915 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
1916 | rtx q, set2; | |
1917 | int num_calls2 = 0, s_length2 = 0; | |
1918 | ||
1919 | if (note && CONSTANT_P (XEXP (note, 0))) | |
1920 | { | |
1921 | for (q = PREV_INSN (insn); q; q = PREV_INSN(q)) | |
1922 | { | |
7bf825d2 JW |
1923 | if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN |
1924 | || (GET_CODE (q) == NOTE | |
1925 | && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG | |
1926 | || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END))) | |
184bb750 R |
1927 | { |
1928 | q = 0; | |
1929 | break; | |
1930 | } | |
7bf825d2 JW |
1931 | |
1932 | /* ??? We can't scan past the end of a basic block without | |
1933 | updating the register lifetime info | |
1934 | (REG_DEAD/basic_block_live_at_start). | |
1935 | A CALL_INSN might be the last insn of a basic block, if | |
1936 | it is inside an EH region. There is no easy way to tell, | |
1937 | so we just always break when we see a CALL_INSN if | |
1938 | flag_exceptions is nonzero. */ | |
a1ecb5ca | 1939 | if (flag_exceptions && GET_CODE (q) == CALL_INSN) |
7bf825d2 JW |
1940 | { |
1941 | q = 0; | |
1942 | break; | |
1943 | } | |
1944 | ||
184bb750 R |
1945 | if (GET_RTX_CLASS (GET_CODE (q)) != 'i') |
1946 | continue; | |
1947 | s_length2++; | |
1948 | if (reg_set_p (src, q)) | |
1949 | { | |
1950 | set2 = single_set (q); | |
1951 | break; | |
1952 | } | |
1953 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
1954 | { | |
1955 | q = 0; | |
1956 | break; | |
1957 | } | |
1958 | if (GET_CODE (p) == CALL_INSN) | |
1959 | num_calls2++; | |
1960 | } | |
1961 | if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2)) | |
1962 | && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0)) | |
1963 | { | |
1964 | PUT_CODE (q, NOTE); | |
1965 | NOTE_LINE_NUMBER (q) = NOTE_INSN_DELETED; | |
1966 | NOTE_SOURCE_FILE (q) = 0; | |
1967 | REG_N_SETS (REGNO (src))--; | |
1968 | REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2; | |
1969 | REG_N_REFS (REGNO (src)) -= true_loop_depth; | |
1970 | REG_LIVE_LENGTH (REGNO (src)) -= s_length2; | |
1971 | insn_const = 0; | |
1972 | } | |
1973 | } | |
1974 | } | |
1a56b81f AS |
1975 | |
1976 | /* Don't remove this seemingly useless if, it is needed to pair with the | |
1977 | else in the next two conditionally included code blocks. */ | |
1978 | if (0) | |
1979 | {;} | |
940da324 JL |
1980 | else if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
1981 | && (code == PLUS || code == MINUS) && insn_const | |
184bb750 R |
1982 | && try_auto_increment (p, insn, 0, src, insn_const, 1)) |
1983 | insn = p; | |
940da324 JL |
1984 | else if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1985 | && post_inc | |
184bb750 R |
1986 | && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0)) |
1987 | post_inc = 0; | |
184bb750 R |
1988 | /* If post_inc still prevails, try to find an |
1989 | insn where it can be used as a pre-in/decrement. | |
1990 | If code is MINUS, this was already tried. */ | |
1991 | if (post_inc && code == PLUS | |
1992 | /* Check that newconst is likely to be usable | |
1993 | in a pre-in/decrement before starting the search. */ | |
940da324 JL |
1994 | && ((HAVE_PRE_INCREMENT && newconst > 0 && newconst <= MOVE_MAX) |
1995 | || (HAVE_PRE_DECREMENT && newconst < 0 && newconst >= -MOVE_MAX)) | |
1996 | && exact_log2 (newconst)) | |
184bb750 R |
1997 | { |
1998 | rtx q, inc_dest; | |
1999 | ||
2000 | inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src; | |
51723711 | 2001 | for (q = post_inc; (q = NEXT_INSN (q)); ) |
184bb750 R |
2002 | { |
2003 | if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN | |
2004 | || (GET_CODE (q) == NOTE | |
2005 | && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG | |
2006 | || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END))) | |
2007 | break; | |
7bf825d2 JW |
2008 | |
2009 | /* ??? We can't scan past the end of a basic block without updating | |
2010 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
2011 | A CALL_INSN might be the last insn of a basic block, if it | |
2012 | is inside an EH region. There is no easy way to tell so we | |
2013 | just always break when we see a CALL_INSN if flag_exceptions | |
2014 | is nonzero. */ | |
a1ecb5ca | 2015 | if (flag_exceptions && GET_CODE (q) == CALL_INSN) |
7bf825d2 JW |
2016 | break; |
2017 | ||
184bb750 R |
2018 | if (GET_RTX_CLASS (GET_CODE (q)) != 'i') |
2019 | continue; | |
2020 | if (src != inc_dest && (reg_overlap_mentioned_p (src, PATTERN (q)) | |
2021 | || reg_set_p (src, q))) | |
2022 | break; | |
2023 | if (reg_set_p (inc_dest, q)) | |
2024 | break; | |
2025 | if (reg_overlap_mentioned_p (inc_dest, PATTERN (q))) | |
2026 | { | |
2027 | try_auto_increment (q, post_inc, | |
2028 | post_inc_set, inc_dest, newconst, 1); | |
2029 | break; | |
2030 | } | |
2031 | } | |
2032 | } | |
184bb750 R |
2033 | /* Move the death note for DST to INSN if it is used |
2034 | there. */ | |
2035 | if (reg_overlap_mentioned_p (dst, PATTERN (insn))) | |
2036 | { | |
2037 | XEXP (dst_note, 1) = REG_NOTES (insn); | |
2038 | REG_NOTES (insn) = dst_note; | |
2039 | } | |
2040 | ||
2041 | if (src_note) | |
2042 | { | |
2043 | /* Move the death note for SRC from INSN to P. */ | |
2044 | if (! overlap) | |
2045 | remove_note (insn, src_note); | |
2046 | XEXP (src_note, 1) = REG_NOTES (p); | |
2047 | REG_NOTES (p) = src_note; | |
2048 | ||
2049 | REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls; | |
2050 | } | |
2051 | ||
2052 | REG_N_SETS (REGNO (src))++; | |
2053 | REG_N_SETS (REGNO (dst))--; | |
2054 | ||
2055 | REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls; | |
2056 | ||
2057 | REG_LIVE_LENGTH (REGNO (src)) += s_length; | |
2058 | if (REG_LIVE_LENGTH (REGNO (dst)) >= 0) | |
2059 | { | |
2060 | REG_LIVE_LENGTH (REGNO (dst)) -= length; | |
2061 | /* REG_LIVE_LENGTH is only an approximation after | |
2062 | combine if sched is not run, so make sure that we | |
2063 | still have a reasonable value. */ | |
2064 | if (REG_LIVE_LENGTH (REGNO (dst)) < 2) | |
2065 | REG_LIVE_LENGTH (REGNO (dst)) = 2; | |
2066 | } | |
2067 | ||
2068 | /* We assume that a register is used exactly once per | |
2069 | insn in the updates above. If this is not correct, | |
2070 | no great harm is done. */ | |
2071 | ||
2072 | REG_N_REFS (REGNO (src)) += 2 * true_loop_depth; | |
2073 | REG_N_REFS (REGNO (dst)) -= 2 * true_loop_depth; | |
2074 | ||
2075 | /* If that was the only time dst was set, | |
2076 | and dst was not live at the start of the | |
2077 | function, we know that we have no more | |
2078 | references to dst; clear REG_N_REFS so it | |
2079 | won't make reload do any work. */ | |
2080 | if (REG_N_SETS (REGNO (dst)) == 0 | |
2081 | && ! regno_uninitialized (REGNO (dst))) | |
2082 | REG_N_REFS (REGNO (dst)) = 0; | |
2083 | ||
2084 | if (regmove_dump_file) | |
2085 | fprintf (regmove_dump_file, | |
2086 | "Fixed operand %d of insn %d matching operand %d.\n", | |
2087 | operand_number, INSN_UID (insn), match_number); | |
2088 | return 1; | |
2089 | } | |
2090 | ||
2091 | ||
8c660648 JL |
2092 | /* return nonzero if X is stable but for mentioning SRC or mentioning / |
2093 | changing DST . If in doubt, presume it is unstable. */ | |
2094 | static int | |
2095 | stable_but_for_p (x, src, dst) | |
2096 | rtx x, src, dst; | |
2097 | { | |
2098 | RTX_CODE code = GET_CODE (x); | |
2099 | switch (GET_RTX_CLASS (code)) | |
2100 | { | |
2101 | case '<': case '1': case 'c': case '2': case 'b': case '3': | |
2102 | { | |
2103 | int i; | |
2104 | char *fmt = GET_RTX_FORMAT (code); | |
2105 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2106 | if (fmt[i] == 'e' && ! stable_but_for_p (XEXP (x, i), src, dst)) | |
2107 | return 0; | |
2108 | return 1; | |
2109 | } | |
2110 | case 'o': | |
2111 | if (x == src || x == dst) | |
2112 | return 1; | |
2113 | /* fall through */ | |
2114 | default: | |
2115 | return ! rtx_unstable_p (x); | |
2116 | } | |
2117 | } | |
184bb750 | 2118 | |
b1a7d591 JW |
2119 | /* Test if regmove seems profitable for this target. Regmove is useful only |
2120 | if some common patterns are two address, i.e. require matching constraints, | |
2121 | so we check that condition here. */ | |
2122 | ||
184bb750 R |
2123 | int |
2124 | regmove_profitable_p () | |
2125 | { | |
2126 | #ifdef REGISTER_CONSTRAINTS | |
2127 | struct match match; | |
2128 | enum machine_mode mode; | |
2129 | optab tstoptab = add_optab; | |
2130 | do /* check add_optab and ashl_optab */ | |
2131 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
2132 | mode = GET_MODE_WIDER_MODE (mode)) | |
2133 | { | |
2134 | int icode = (int) tstoptab->handlers[(int) mode].insn_code; | |
2135 | rtx reg0, reg1, reg2, pat; | |
2136 | int i; | |
2137 | ||
2138 | if (GET_MODE_BITSIZE (mode) < 32 || icode == CODE_FOR_nothing) | |
2139 | continue; | |
2140 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2141 | if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i)) | |
2142 | break; | |
2143 | if (i + 2 >= FIRST_PSEUDO_REGISTER) | |
2144 | break; | |
38a448ca RH |
2145 | reg0 = gen_rtx_REG (insn_operand_mode[icode][0], i); |
2146 | reg1 = gen_rtx_REG (insn_operand_mode[icode][1], i + 1); | |
2147 | reg2 = gen_rtx_REG (insn_operand_mode[icode][2], i + 2); | |
184bb750 R |
2148 | if (! (*insn_operand_predicate[icode][0]) (reg0, VOIDmode) |
2149 | || ! (*insn_operand_predicate[icode][1]) (reg1, VOIDmode) | |
2150 | || ! (*insn_operand_predicate[icode][2]) (reg2, VOIDmode)) | |
2151 | break; | |
2152 | pat = GEN_FCN (icode) (reg0, reg1, reg2); | |
2153 | if (! pat) | |
2154 | continue; | |
2155 | if (GET_CODE (pat) == SEQUENCE) | |
2156 | pat = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1); | |
2157 | else | |
2158 | pat = make_insn_raw (pat); | |
2159 | if (! single_set (pat) | |
2160 | || GET_CODE (SET_SRC (single_set (pat))) != tstoptab->code) | |
2161 | /* Unexpected complexity; don't need to handle this unless | |
2162 | we find a machine where this occurs and regmove should | |
2163 | be enabled. */ | |
2164 | break; | |
3d2f8eb6 | 2165 | if (find_matches (pat, &match)) |
184bb750 R |
2166 | return 1; |
2167 | break; | |
2168 | } | |
2169 | while (tstoptab != ashl_optab && (tstoptab = ashl_optab, 1)); | |
2170 | #endif /* REGISTER_CONSTRAINTS */ | |
2171 | return 0; | |
2172 | } |