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8c660648 | 1 | /* Move registers around to reduce number of move instructions needed. |
af841dbd JL |
2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
8c660648 JL |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
5f38fdda JL |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
8c660648 JL |
21 | |
22 | ||
23 | /* This module looks for cases where matching constraints would force | |
24 | an instruction to need a reload, and this reload would be a register | |
25 | to register move. It then attempts to change the registers used by the | |
26 | instruction to avoid the move instruction. */ | |
27 | ||
28 | #include "config.h" | |
670ee920 | 29 | #include "system.h" |
789f983a | 30 | #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ |
6baf1cc8 | 31 | #include "tm_p.h" |
8c660648 JL |
32 | #include "insn-config.h" |
33 | #include "recog.h" | |
34 | #include "output.h" | |
35 | #include "reload.h" | |
36 | #include "regs.h" | |
184bb750 R |
37 | #include "hard-reg-set.h" |
38 | #include "flags.h" | |
49ad7cfa | 39 | #include "function.h" |
184bb750 R |
40 | #include "expr.h" |
41 | #include "insn-flags.h" | |
ddc8bed2 | 42 | #include "basic-block.h" |
2e107e9e | 43 | #include "toplev.h" |
184bb750 | 44 | |
13536812 KG |
45 | static int optimize_reg_copy_1 PARAMS ((rtx, rtx, rtx)); |
46 | static void optimize_reg_copy_2 PARAMS ((rtx, rtx, rtx)); | |
47 | static void optimize_reg_copy_3 PARAMS ((rtx, rtx, rtx)); | |
48 | static rtx gen_add3_insn PARAMS ((rtx, rtx, rtx)); | |
49 | static void copy_src_to_dest PARAMS ((rtx, rtx, rtx, int)); | |
ddc8bed2 | 50 | static int *regmove_bb_head; |
8c660648 | 51 | |
184bb750 R |
52 | struct match { |
53 | int with[MAX_RECOG_OPERANDS]; | |
54 | enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS]; | |
55 | int commutative[MAX_RECOG_OPERANDS]; | |
56 | int early_clobber[MAX_RECOG_OPERANDS]; | |
57 | }; | |
58 | ||
13536812 KG |
59 | static rtx discover_flags_reg PARAMS ((void)); |
60 | static void mark_flags_life_zones PARAMS ((rtx)); | |
61 | static void flags_set_1 PARAMS ((rtx, rtx, void *)); | |
dc2cb191 | 62 | |
13536812 KG |
63 | static int try_auto_increment PARAMS ((rtx, rtx, rtx, rtx, HOST_WIDE_INT, int)); |
64 | static int find_matches PARAMS ((rtx, struct match *)); | |
65 | static int fixup_match_1 PARAMS ((rtx, rtx, rtx, rtx, rtx, int, int, int, FILE *)) | |
184bb750 | 66 | ; |
13536812 KG |
67 | static int reg_is_remote_constant_p PARAMS ((rtx, rtx, rtx)); |
68 | static int stable_and_no_regs_but_for_p PARAMS ((rtx, rtx, rtx)); | |
69 | static int regclass_compatible_p PARAMS ((int, int)); | |
70 | static int replacement_quality PARAMS ((rtx)); | |
71 | static int fixup_match_2 PARAMS ((rtx, rtx, rtx, rtx, FILE *)); | |
8c660648 | 72 | |
3bb806ed R |
73 | /* Return non-zero if registers with CLASS1 and CLASS2 can be merged without |
74 | causing too much register allocation problems. */ | |
75 | static int | |
76 | regclass_compatible_p (class0, class1) | |
77 | int class0, class1; | |
78 | { | |
79 | return (class0 == class1 | |
80 | || (reg_class_subset_p (class0, class1) | |
81 | && ! CLASS_LIKELY_SPILLED_P (class0)) | |
82 | || (reg_class_subset_p (class1, class0) | |
83 | && ! CLASS_LIKELY_SPILLED_P (class1))); | |
84 | } | |
85 | ||
1a29f703 R |
86 | /* Generate and return an insn body to add r1 and c, |
87 | storing the result in r0. */ | |
88 | static rtx | |
89 | gen_add3_insn (r0, r1, c) | |
90 | rtx r0, r1, c; | |
91 | { | |
92 | int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
93 | ||
94 | if (icode == CODE_FOR_nothing | |
a995e389 RH |
95 | || ! ((*insn_data[icode].operand[0].predicate) |
96 | (r0, insn_data[icode].operand[0].mode)) | |
97 | || ! ((*insn_data[icode].operand[1].predicate) | |
98 | (r1, insn_data[icode].operand[1].mode)) | |
99 | || ! ((*insn_data[icode].operand[2].predicate) | |
100 | (c, insn_data[icode].operand[2].mode))) | |
1a29f703 R |
101 | return NULL_RTX; |
102 | ||
103 | return (GEN_FCN (icode) (r0, r1, c)); | |
104 | } | |
105 | ||
8c660648 JL |
106 | |
107 | /* INC_INSN is an instruction that adds INCREMENT to REG. | |
108 | Try to fold INC_INSN as a post/pre in/decrement into INSN. | |
109 | Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src. | |
110 | Return nonzero for success. */ | |
111 | static int | |
112 | try_auto_increment (insn, inc_insn, inc_insn_set, reg, increment, pre) | |
113 | rtx reg, insn, inc_insn ,inc_insn_set; | |
114 | HOST_WIDE_INT increment; | |
115 | int pre; | |
116 | { | |
117 | enum rtx_code inc_code; | |
118 | ||
119 | rtx pset = single_set (insn); | |
120 | if (pset) | |
121 | { | |
122 | /* Can't use the size of SET_SRC, we might have something like | |
123 | (sign_extend:SI (mem:QI ... */ | |
124 | rtx use = find_use_as_address (pset, reg, 0); | |
125 | if (use != 0 && use != (rtx) 1) | |
126 | { | |
127 | int size = GET_MODE_SIZE (GET_MODE (use)); | |
128 | if (0 | |
940da324 JL |
129 | || (HAVE_POST_INCREMENT |
130 | && pre == 0 && (inc_code = POST_INC, increment == size)) | |
131 | || (HAVE_PRE_INCREMENT | |
132 | && pre == 1 && (inc_code = PRE_INC, increment == size)) | |
133 | || (HAVE_POST_DECREMENT | |
134 | && pre == 0 && (inc_code = POST_DEC, increment == -size)) | |
135 | || (HAVE_PRE_DECREMENT | |
136 | && pre == 1 && (inc_code = PRE_DEC, increment == -size)) | |
184bb750 R |
137 | ) |
138 | { | |
139 | if (inc_insn_set) | |
140 | validate_change | |
141 | (inc_insn, | |
142 | &SET_SRC (inc_insn_set), | |
8c660648 | 143 | XEXP (SET_SRC (inc_insn_set), 0), 1); |
184bb750 | 144 | validate_change (insn, &XEXP (use, 0), |
38a448ca | 145 | gen_rtx_fmt_e (inc_code, Pmode, reg), 1); |
184bb750 R |
146 | if (apply_change_group ()) |
147 | { | |
148 | REG_NOTES (insn) | |
38a448ca RH |
149 | = gen_rtx_EXPR_LIST (REG_INC, |
150 | reg, REG_NOTES (insn)); | |
184bb750 R |
151 | if (! inc_insn_set) |
152 | { | |
153 | PUT_CODE (inc_insn, NOTE); | |
154 | NOTE_LINE_NUMBER (inc_insn) = NOTE_INSN_DELETED; | |
155 | NOTE_SOURCE_FILE (inc_insn) = 0; | |
156 | } | |
8c660648 | 157 | return 1; |
184bb750 R |
158 | } |
159 | } | |
160 | } | |
161 | } | |
162 | return 0; | |
163 | } | |
dc2cb191 RH |
164 | \f |
165 | /* Determine if the pattern generated by add_optab has a clobber, | |
166 | such as might be issued for a flags hard register. To make the | |
167 | code elsewhere simpler, we handle cc0 in this same framework. | |
168 | ||
169 | Return the register if one was discovered. Return NULL_RTX if | |
170 | if no flags were found. Return pc_rtx if we got confused. */ | |
171 | ||
172 | static rtx | |
173 | discover_flags_reg () | |
174 | { | |
175 | rtx tmp; | |
cd4b3546 | 176 | tmp = gen_rtx_REG (word_mode, 10000); |
dc2cb191 RH |
177 | tmp = gen_add3_insn (tmp, tmp, GEN_INT (2)); |
178 | ||
179 | /* If we get something that isn't a simple set, or a | |
180 | [(set ..) (clobber ..)], this whole function will go wrong. */ | |
181 | if (GET_CODE (tmp) == SET) | |
182 | return NULL_RTX; | |
183 | else if (GET_CODE (tmp) == PARALLEL) | |
184 | { | |
185 | int found; | |
186 | ||
187 | if (XVECLEN (tmp, 0) != 2) | |
188 | return pc_rtx; | |
189 | tmp = XVECEXP (tmp, 0, 1); | |
190 | if (GET_CODE (tmp) != CLOBBER) | |
191 | return pc_rtx; | |
192 | tmp = XEXP (tmp, 0); | |
193 | ||
194 | /* Don't do anything foolish if the md wanted to clobber a | |
195 | scratch or something. We only care about hard regs. | |
196 | Moreover we don't like the notion of subregs of hard regs. */ | |
197 | if (GET_CODE (tmp) == SUBREG | |
198 | && GET_CODE (SUBREG_REG (tmp)) == REG | |
199 | && REGNO (SUBREG_REG (tmp)) < FIRST_PSEUDO_REGISTER) | |
200 | return pc_rtx; | |
201 | found = (GET_CODE (tmp) == REG && REGNO (tmp) < FIRST_PSEUDO_REGISTER); | |
202 | ||
dc2cb191 | 203 | return (found ? tmp : NULL_RTX); |
dc2cb191 RH |
204 | } |
205 | ||
206 | return pc_rtx; | |
207 | } | |
208 | ||
209 | /* It is a tedious task identifying when the flags register is live and | |
210 | when it is safe to optimize. Since we process the instruction stream | |
211 | multiple times, locate and record these live zones by marking the | |
212 | mode of the instructions -- | |
213 | ||
214 | QImode is used on the instruction at which the flags becomes live. | |
215 | ||
216 | HImode is used within the range (exclusive) that the flags are | |
217 | live. Thus the user of the flags is not marked. | |
218 | ||
219 | All other instructions are cleared to VOIDmode. */ | |
220 | ||
221 | /* Used to communicate with flags_set_1. */ | |
222 | static rtx flags_set_1_rtx; | |
223 | static int flags_set_1_set; | |
224 | ||
225 | static void | |
226 | mark_flags_life_zones (flags) | |
227 | rtx flags; | |
228 | { | |
229 | int flags_regno; | |
230 | int flags_nregs; | |
231 | int block; | |
232 | ||
e7f5b971 RH |
233 | #ifdef HAVE_cc0 |
234 | /* If we found a flags register on a cc0 host, bail. */ | |
235 | if (flags == NULL_RTX) | |
236 | flags = cc0_rtx; | |
237 | else if (flags != cc0_rtx) | |
238 | flags = pc_rtx; | |
239 | #endif | |
240 | ||
dc2cb191 RH |
241 | /* Simple cases first: if no flags, clear all modes. If confusing, |
242 | mark the entire function as being in a flags shadow. */ | |
243 | if (flags == NULL_RTX || flags == pc_rtx) | |
244 | { | |
245 | enum machine_mode mode = (flags ? HImode : VOIDmode); | |
246 | rtx insn; | |
247 | for (insn = get_insns(); insn; insn = NEXT_INSN (insn)) | |
248 | PUT_MODE (insn, mode); | |
249 | return; | |
250 | } | |
251 | ||
252 | #ifdef HAVE_cc0 | |
253 | flags_regno = -1; | |
254 | flags_nregs = 1; | |
255 | #else | |
256 | flags_regno = REGNO (flags); | |
257 | flags_nregs = HARD_REGNO_NREGS (flags_regno, GET_MODE (flags)); | |
258 | #endif | |
259 | flags_set_1_rtx = flags; | |
184bb750 | 260 | |
dc2cb191 RH |
261 | /* Process each basic block. */ |
262 | for (block = n_basic_blocks - 1; block >= 0; block--) | |
263 | { | |
264 | rtx insn, end; | |
265 | int live; | |
266 | ||
267 | insn = BLOCK_HEAD (block); | |
268 | end = BLOCK_END (block); | |
269 | ||
270 | /* Look out for the (unlikely) case of flags being live across | |
271 | basic block boundaries. */ | |
272 | live = 0; | |
273 | #ifndef HAVE_cc0 | |
274 | { | |
275 | int i; | |
276 | for (i = 0; i < flags_nregs; ++i) | |
e881bb1b | 277 | live |= REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, |
dc2cb191 RH |
278 | flags_regno + i); |
279 | } | |
280 | #endif | |
281 | ||
282 | while (1) | |
283 | { | |
284 | /* Process liveness in reverse order of importance -- | |
285 | alive, death, birth. This lets more important info | |
286 | overwrite the mode of lesser info. */ | |
287 | ||
288 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
289 | { | |
290 | #ifdef HAVE_cc0 | |
291 | /* In the cc0 case, death is not marked in reg notes, | |
292 | but is instead the mere use of cc0 when it is alive. */ | |
293 | if (live && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
294 | live = 0; | |
295 | #else | |
296 | /* In the hard reg case, we watch death notes. */ | |
297 | if (live && find_regno_note (insn, REG_DEAD, flags_regno)) | |
298 | live = 0; | |
299 | #endif | |
300 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
301 | ||
302 | /* In either case, birth is denoted simply by it's presence | |
303 | as the destination of a set. */ | |
304 | flags_set_1_set = 0; | |
84832317 | 305 | note_stores (PATTERN (insn), flags_set_1, NULL); |
dc2cb191 RH |
306 | if (flags_set_1_set) |
307 | { | |
308 | live = 1; | |
309 | PUT_MODE (insn, QImode); | |
310 | } | |
311 | } | |
312 | else | |
313 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
314 | ||
315 | if (insn == end) | |
316 | break; | |
317 | insn = NEXT_INSN (insn); | |
318 | } | |
319 | } | |
320 | } | |
321 | ||
322 | /* A subroutine of mark_flags_life_zones, called through note_stores. */ | |
323 | ||
324 | static void | |
84832317 | 325 | flags_set_1 (x, pat, data) |
dc2cb191 | 326 | rtx x, pat; |
84832317 | 327 | void *data ATTRIBUTE_UNUSED; |
dc2cb191 RH |
328 | { |
329 | if (GET_CODE (pat) == SET | |
330 | && reg_overlap_mentioned_p (x, flags_set_1_rtx)) | |
331 | flags_set_1_set = 1; | |
332 | } | |
333 | \f | |
184bb750 R |
334 | static int *regno_src_regno; |
335 | ||
336 | /* Indicate how good a choice REG (which appears as a source) is to replace | |
337 | a destination register with. The higher the returned value, the better | |
338 | the choice. The main objective is to avoid using a register that is | |
339 | a candidate for tying to a hard register, since the output might in | |
340 | turn be a candidate to be tied to a different hard register. */ | |
95d75019 | 341 | static int |
184bb750 R |
342 | replacement_quality(reg) |
343 | rtx reg; | |
344 | { | |
345 | int src_regno; | |
346 | ||
347 | /* Bad if this isn't a register at all. */ | |
348 | if (GET_CODE (reg) != REG) | |
349 | return 0; | |
350 | ||
351 | /* If this register is not meant to get a hard register, | |
352 | it is a poor choice. */ | |
353 | if (REG_LIVE_LENGTH (REGNO (reg)) < 0) | |
354 | return 0; | |
355 | ||
356 | src_regno = regno_src_regno[REGNO (reg)]; | |
357 | ||
358 | /* If it was not copied from another register, it is fine. */ | |
359 | if (src_regno < 0) | |
360 | return 3; | |
361 | ||
362 | /* Copied from a hard register? */ | |
363 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
364 | return 1; | |
365 | ||
366 | /* Copied from a pseudo register - not as bad as from a hard register, | |
367 | yet still cumbersome, since the register live length will be lengthened | |
368 | when the registers get tied. */ | |
369 | return 2; | |
370 | } | |
371 | ||
1230327b R |
372 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die |
373 | in INSN. | |
374 | ||
375 | Search forward to see if SRC dies before either it or DEST is modified, | |
376 | but don't scan past the end of a basic block. If so, we can replace SRC | |
377 | with DEST and let SRC die in INSN. | |
378 | ||
379 | This will reduce the number of registers live in that range and may enable | |
380 | DEST to be tied to SRC, thus often saving one register in addition to a | |
381 | register-register copy. */ | |
382 | ||
383 | static int | |
384 | optimize_reg_copy_1 (insn, dest, src) | |
385 | rtx insn; | |
386 | rtx dest; | |
387 | rtx src; | |
388 | { | |
389 | rtx p, q; | |
390 | rtx note; | |
391 | rtx dest_death = 0; | |
392 | int sregno = REGNO (src); | |
393 | int dregno = REGNO (dest); | |
394 | ||
395 | /* We don't want to mess with hard regs if register classes are small. */ | |
396 | if (sregno == dregno | |
397 | || (SMALL_REGISTER_CLASSES | |
398 | && (sregno < FIRST_PSEUDO_REGISTER | |
399 | || dregno < FIRST_PSEUDO_REGISTER)) | |
400 | /* We don't see all updates to SP if they are in an auto-inc memory | |
401 | reference, so we must disallow this optimization on them. */ | |
402 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) | |
403 | return 0; | |
404 | ||
405 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
406 | { | |
07aaad94 | 407 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) |
1230327b R |
408 | break; |
409 | ||
7bf825d2 JW |
410 | /* ??? We can't scan past the end of a basic block without updating |
411 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
412 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
413 | an EH region. There is no easy way to tell, so we just always break | |
414 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
415 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
416 | break; | |
417 | ||
1230327b R |
418 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
419 | continue; | |
420 | ||
421 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
422 | /* Don't change a USE of a register. */ | |
423 | || (GET_CODE (PATTERN (p)) == USE | |
424 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
425 | break; | |
426 | ||
427 | /* See if all of SRC dies in P. This test is slightly more | |
428 | conservative than it needs to be. */ | |
429 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 | |
430 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
431 | { | |
432 | int failed = 0; | |
1230327b | 433 | int d_length = 0; |
89098dc1 | 434 | int s_length = 0; |
1230327b | 435 | int d_n_calls = 0; |
89098dc1 | 436 | int s_n_calls = 0; |
1230327b R |
437 | |
438 | /* We can do the optimization. Scan forward from INSN again, | |
439 | replacing regs as we go. Set FAILED if a replacement can't | |
440 | be done. In that case, we can't move the death note for SRC. | |
441 | This should be rare. */ | |
442 | ||
443 | /* Set to stop at next insn. */ | |
444 | for (q = next_real_insn (insn); | |
445 | q != next_real_insn (p); | |
446 | q = next_real_insn (q)) | |
447 | { | |
448 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
449 | { | |
450 | /* If SRC is a hard register, we might miss some | |
451 | overlapping registers with validate_replace_rtx, | |
452 | so we would have to undo it. We can't if DEST is | |
453 | present in the insn, so fail in that combination | |
454 | of cases. */ | |
455 | if (sregno < FIRST_PSEUDO_REGISTER | |
456 | && reg_mentioned_p (dest, PATTERN (q))) | |
457 | failed = 1; | |
458 | ||
459 | /* Replace all uses and make sure that the register | |
460 | isn't still present. */ | |
461 | else if (validate_replace_rtx (src, dest, q) | |
462 | && (sregno >= FIRST_PSEUDO_REGISTER | |
463 | || ! reg_overlap_mentioned_p (src, | |
464 | PATTERN (q)))) | |
1b7c4a37 | 465 | ; |
1230327b R |
466 | else |
467 | { | |
468 | validate_replace_rtx (dest, src, q); | |
469 | failed = 1; | |
470 | } | |
471 | } | |
472 | ||
89098dc1 JL |
473 | /* For SREGNO, count the total number of insns scanned. |
474 | For DREGNO, count the total number of insns scanned after | |
475 | passing the death note for DREGNO. */ | |
476 | s_length++; | |
1230327b R |
477 | if (dest_death) |
478 | d_length++; | |
479 | ||
480 | /* If the insn in which SRC dies is a CALL_INSN, don't count it | |
481 | as a call that has been crossed. Otherwise, count it. */ | |
482 | if (q != p && GET_CODE (q) == CALL_INSN) | |
483 | { | |
89098dc1 JL |
484 | /* Similarly, total calls for SREGNO, total calls beyond |
485 | the death note for DREGNO. */ | |
486 | s_n_calls++; | |
1230327b R |
487 | if (dest_death) |
488 | d_n_calls++; | |
489 | } | |
490 | ||
491 | /* If DEST dies here, remove the death note and save it for | |
492 | later. Make sure ALL of DEST dies here; again, this is | |
493 | overly conservative. */ | |
494 | if (dest_death == 0 | |
495 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0) | |
496 | { | |
497 | if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest)) | |
498 | failed = 1, dest_death = 0; | |
499 | else | |
500 | remove_note (q, dest_death); | |
501 | } | |
502 | } | |
503 | ||
504 | if (! failed) | |
505 | { | |
89098dc1 JL |
506 | /* These counters need to be updated if and only if we are |
507 | going to move the REG_DEAD note. */ | |
1230327b R |
508 | if (sregno >= FIRST_PSEUDO_REGISTER) |
509 | { | |
510 | if (REG_LIVE_LENGTH (sregno) >= 0) | |
511 | { | |
89098dc1 | 512 | REG_LIVE_LENGTH (sregno) -= s_length; |
1230327b R |
513 | /* REG_LIVE_LENGTH is only an approximation after |
514 | combine if sched is not run, so make sure that we | |
515 | still have a reasonable value. */ | |
516 | if (REG_LIVE_LENGTH (sregno) < 2) | |
517 | REG_LIVE_LENGTH (sregno) = 2; | |
518 | } | |
519 | ||
89098dc1 | 520 | REG_N_CALLS_CROSSED (sregno) -= s_n_calls; |
1230327b R |
521 | } |
522 | ||
523 | /* Move death note of SRC from P to INSN. */ | |
524 | remove_note (p, note); | |
525 | XEXP (note, 1) = REG_NOTES (insn); | |
526 | REG_NOTES (insn) = note; | |
527 | } | |
528 | ||
124d535f JW |
529 | /* DEST is also dead if INSN has a REG_UNUSED note for DEST. */ |
530 | if (! dest_death | |
531 | && (dest_death = find_regno_note (insn, REG_UNUSED, dregno))) | |
532 | { | |
533 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
534 | remove_note (insn, dest_death); | |
535 | } | |
536 | ||
1230327b R |
537 | /* Put death note of DEST on P if we saw it die. */ |
538 | if (dest_death) | |
539 | { | |
540 | XEXP (dest_death, 1) = REG_NOTES (p); | |
541 | REG_NOTES (p) = dest_death; | |
89098dc1 JL |
542 | |
543 | if (dregno >= FIRST_PSEUDO_REGISTER) | |
544 | { | |
545 | /* If and only if we are moving the death note for DREGNO, | |
546 | then we need to update its counters. */ | |
547 | if (REG_LIVE_LENGTH (dregno) >= 0) | |
548 | REG_LIVE_LENGTH (dregno) += d_length; | |
549 | REG_N_CALLS_CROSSED (dregno) += d_n_calls; | |
550 | } | |
1230327b R |
551 | } |
552 | ||
553 | return ! failed; | |
554 | } | |
555 | ||
556 | /* If SRC is a hard register which is set or killed in some other | |
557 | way, we can't do this optimization. */ | |
558 | else if (sregno < FIRST_PSEUDO_REGISTER | |
559 | && dead_or_set_p (p, src)) | |
560 | break; | |
561 | } | |
562 | return 0; | |
563 | } | |
564 | \f | |
565 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have | |
566 | a sequence of insns that modify DEST followed by an insn that sets | |
567 | SRC to DEST in which DEST dies, with no prior modification of DEST. | |
568 | (There is no need to check if the insns in between actually modify | |
569 | DEST. We should not have cases where DEST is not modified, but | |
570 | the optimization is safe if no such modification is detected.) | |
571 | In that case, we can replace all uses of DEST, starting with INSN and | |
572 | ending with the set of SRC to DEST, with SRC. We do not do this | |
573 | optimization if a CALL_INSN is crossed unless SRC already crosses a | |
574 | call or if DEST dies before the copy back to SRC. | |
575 | ||
576 | It is assumed that DEST and SRC are pseudos; it is too complicated to do | |
577 | this for hard registers since the substitutions we may make might fail. */ | |
578 | ||
579 | static void | |
580 | optimize_reg_copy_2 (insn, dest, src) | |
581 | rtx insn; | |
582 | rtx dest; | |
583 | rtx src; | |
584 | { | |
585 | rtx p, q; | |
586 | rtx set; | |
587 | int sregno = REGNO (src); | |
588 | int dregno = REGNO (dest); | |
589 | ||
590 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
591 | { | |
07aaad94 | 592 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) |
1230327b R |
593 | break; |
594 | ||
7bf825d2 JW |
595 | /* ??? We can't scan past the end of a basic block without updating |
596 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
597 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
598 | an EH region. There is no easy way to tell, so we just always break | |
599 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
600 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
601 | break; | |
602 | ||
1230327b R |
603 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
604 | continue; | |
605 | ||
606 | set = single_set (p); | |
607 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src | |
608 | && find_reg_note (p, REG_DEAD, dest)) | |
609 | { | |
610 | /* We can do the optimization. Scan forward from INSN again, | |
611 | replacing regs as we go. */ | |
612 | ||
613 | /* Set to stop at next insn. */ | |
614 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) | |
615 | if (GET_RTX_CLASS (GET_CODE (q)) == 'i') | |
616 | { | |
617 | if (reg_mentioned_p (dest, PATTERN (q))) | |
1b7c4a37 | 618 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); |
1230327b R |
619 | |
620 | ||
621 | if (GET_CODE (q) == CALL_INSN) | |
622 | { | |
623 | REG_N_CALLS_CROSSED (dregno)--; | |
624 | REG_N_CALLS_CROSSED (sregno)++; | |
625 | } | |
626 | } | |
627 | ||
628 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); | |
629 | REG_N_DEATHS (dregno)--; | |
630 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); | |
631 | REG_N_DEATHS (sregno)--; | |
632 | return; | |
633 | } | |
634 | ||
635 | if (reg_set_p (src, p) | |
636 | || find_reg_note (p, REG_DEAD, dest) | |
637 | || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0)) | |
638 | break; | |
639 | } | |
640 | } | |
184bb750 R |
641 | /* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST. |
642 | Look if SRC dies there, and if it is only set once, by loading | |
643 | it from memory. If so, try to encorporate the zero/sign extension | |
644 | into the memory read, change SRC to the mode of DEST, and alter | |
645 | the remaining accesses to use the appropriate SUBREG. This allows | |
646 | SRC and DEST to be tied later. */ | |
647 | static void | |
648 | optimize_reg_copy_3 (insn, dest, src) | |
649 | rtx insn; | |
650 | rtx dest; | |
651 | rtx src; | |
652 | { | |
653 | rtx src_reg = XEXP (src, 0); | |
654 | int src_no = REGNO (src_reg); | |
655 | int dst_no = REGNO (dest); | |
656 | rtx p, set, subreg; | |
657 | enum machine_mode old_mode; | |
658 | ||
659 | if (src_no < FIRST_PSEUDO_REGISTER | |
660 | || dst_no < FIRST_PSEUDO_REGISTER | |
661 | || ! find_reg_note (insn, REG_DEAD, src_reg) | |
662 | || REG_N_SETS (src_no) != 1) | |
663 | return; | |
9c07e479 | 664 | for (p = PREV_INSN (insn); p && ! reg_set_p (src_reg, p); p = PREV_INSN (p)) |
184bb750 | 665 | { |
07aaad94 | 666 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) |
7bf825d2 JW |
667 | return; |
668 | ||
669 | /* ??? We can't scan past the end of a basic block without updating | |
670 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
671 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
672 | an EH region. There is no easy way to tell, so we just always break | |
673 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
674 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
675 | return; | |
676 | ||
184bb750 R |
677 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
678 | continue; | |
184bb750 | 679 | } |
9c07e479 BK |
680 | if (! p) |
681 | return; | |
682 | ||
184bb750 R |
683 | if (! (set = single_set (p)) |
684 | || GET_CODE (SET_SRC (set)) != MEM | |
685 | || SET_DEST (set) != src_reg) | |
686 | return; | |
937e37cc | 687 | |
972b320c R |
688 | /* Be conserative: although this optimization is also valid for |
689 | volatile memory references, that could cause trouble in later passes. */ | |
690 | if (MEM_VOLATILE_P (SET_SRC (set))) | |
691 | return; | |
692 | ||
937e37cc JL |
693 | /* Do not use a SUBREG to truncate from one mode to another if truncation |
694 | is not a nop. */ | |
695 | if (GET_MODE_BITSIZE (GET_MODE (src_reg)) <= GET_MODE_BITSIZE (GET_MODE (src)) | |
696 | && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src)), | |
697 | GET_MODE_BITSIZE (GET_MODE (src_reg)))) | |
698 | return; | |
699 | ||
184bb750 R |
700 | old_mode = GET_MODE (src_reg); |
701 | PUT_MODE (src_reg, GET_MODE (src)); | |
702 | XEXP (src, 0) = SET_SRC (set); | |
e757da5e JL |
703 | |
704 | /* Include this change in the group so that it's easily undone if | |
705 | one of the changes in the group is invalid. */ | |
706 | validate_change (p, &SET_SRC (set), src, 1); | |
707 | ||
708 | /* Now walk forward making additional replacements. We want to be able | |
709 | to undo all the changes if a later substitution fails. */ | |
38a448ca | 710 | subreg = gen_rtx_SUBREG (old_mode, src_reg, 0); |
184bb750 R |
711 | while (p = NEXT_INSN (p), p != insn) |
712 | { | |
713 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
714 | continue; | |
e757da5e JL |
715 | |
716 | /* Make a tenative change. */ | |
717 | validate_replace_rtx_group (src_reg, subreg, p); | |
718 | } | |
719 | ||
720 | validate_replace_rtx_group (src, src_reg, insn); | |
721 | ||
722 | /* Now see if all the changes are valid. */ | |
723 | if (! apply_change_group ()) | |
724 | { | |
725 | /* One or more changes were no good. Back out everything. */ | |
726 | PUT_MODE (src_reg, old_mode); | |
727 | XEXP (src, 0) = src_reg; | |
184bb750 | 728 | } |
184bb750 R |
729 | } |
730 | ||
ddc8bed2 MM |
731 | \f |
732 | /* If we were not able to update the users of src to use dest directly, try | |
733 | instead moving the value to dest directly before the operation. */ | |
734 | ||
cab634f2 | 735 | static void |
1b7c4a37 | 736 | copy_src_to_dest (insn, src, dest, old_max_uid) |
ddc8bed2 MM |
737 | rtx insn; |
738 | rtx src; | |
739 | rtx dest; | |
78dd9906 | 740 | int old_max_uid; |
ddc8bed2 MM |
741 | { |
742 | rtx seq; | |
743 | rtx link; | |
744 | rtx next; | |
745 | rtx set; | |
746 | rtx move_insn; | |
747 | rtx *p_insn_notes; | |
748 | rtx *p_move_notes; | |
ddc8bed2 MM |
749 | int src_regno; |
750 | int dest_regno; | |
751 | int bb; | |
752 | int insn_uid; | |
753 | int move_uid; | |
754 | ||
755 | /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant | |
756 | or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is | |
757 | parameter when there is no frame pointer that is not allocated a register. | |
758 | For now, we just reject them, rather than incrementing the live length. */ | |
759 | ||
3ac3da71 MM |
760 | if (GET_CODE (src) == REG |
761 | && REG_LIVE_LENGTH (REGNO (src)) > 0 | |
762 | && GET_CODE (dest) == REG | |
40546a78 | 763 | && !RTX_UNCHANGING_P (dest) |
3ac3da71 | 764 | && REG_LIVE_LENGTH (REGNO (dest)) > 0 |
ddc8bed2 | 765 | && (set = single_set (insn)) != NULL_RTX |
9d2106a4 R |
766 | && !reg_mentioned_p (dest, SET_SRC (set)) |
767 | && GET_MODE (src) == GET_MODE (dest)) | |
ddc8bed2 | 768 | { |
1a8fca8a R |
769 | int old_num_regs = reg_rtx_no; |
770 | ||
ddc8bed2 MM |
771 | /* Generate the src->dest move. */ |
772 | start_sequence (); | |
773 | emit_move_insn (dest, src); | |
774 | seq = gen_sequence (); | |
775 | end_sequence (); | |
1a8fca8a R |
776 | /* If this sequence uses new registers, we may not use it. */ |
777 | if (old_num_regs != reg_rtx_no | |
778 | || ! validate_replace_rtx (src, dest, insn)) | |
779 | { | |
780 | /* We have to restore reg_rtx_no to its old value, lest | |
781 | recompute_reg_usage will try to compute the usage of the | |
782 | new regs, yet reg_n_info is not valid for them. */ | |
783 | reg_rtx_no = old_num_regs; | |
784 | return; | |
785 | } | |
ddc8bed2 MM |
786 | emit_insn_before (seq, insn); |
787 | move_insn = PREV_INSN (insn); | |
788 | p_move_notes = ®_NOTES (move_insn); | |
789 | p_insn_notes = ®_NOTES (insn); | |
790 | ||
791 | /* Move any notes mentioning src to the move instruction */ | |
792 | for (link = REG_NOTES (insn); link != NULL_RTX; link = next) | |
793 | { | |
794 | next = XEXP (link, 1); | |
795 | if (XEXP (link, 0) == src) | |
796 | { | |
797 | *p_move_notes = link; | |
798 | p_move_notes = &XEXP (link, 1); | |
799 | } | |
800 | else | |
801 | { | |
802 | *p_insn_notes = link; | |
803 | p_insn_notes = &XEXP (link, 1); | |
804 | } | |
805 | } | |
806 | ||
807 | *p_move_notes = NULL_RTX; | |
808 | *p_insn_notes = NULL_RTX; | |
809 | ||
810 | /* Is the insn the head of a basic block? If so extend it */ | |
811 | insn_uid = INSN_UID (insn); | |
812 | move_uid = INSN_UID (move_insn); | |
78dd9906 | 813 | if (insn_uid < old_max_uid) |
ddc8bed2 | 814 | { |
78dd9906 R |
815 | bb = regmove_bb_head[insn_uid]; |
816 | if (bb >= 0) | |
817 | { | |
818 | BLOCK_HEAD (bb) = move_insn; | |
819 | regmove_bb_head[insn_uid] = -1; | |
820 | } | |
ddc8bed2 MM |
821 | } |
822 | ||
823 | /* Update the various register tables. */ | |
824 | dest_regno = REGNO (dest); | |
1b7c4a37 | 825 | REG_N_SETS (dest_regno) ++; |
ddc8bed2 MM |
826 | REG_LIVE_LENGTH (dest_regno)++; |
827 | if (REGNO_FIRST_UID (dest_regno) == insn_uid) | |
828 | REGNO_FIRST_UID (dest_regno) = move_uid; | |
829 | ||
830 | src_regno = REGNO (src); | |
831 | if (! find_reg_note (move_insn, REG_DEAD, src)) | |
832 | REG_LIVE_LENGTH (src_regno)++; | |
833 | ||
834 | if (REGNO_FIRST_UID (src_regno) == insn_uid) | |
835 | REGNO_FIRST_UID (src_regno) = move_uid; | |
836 | ||
837 | if (REGNO_LAST_UID (src_regno) == insn_uid) | |
838 | REGNO_LAST_UID (src_regno) = move_uid; | |
839 | ||
840 | if (REGNO_LAST_NOTE_UID (src_regno) == insn_uid) | |
841 | REGNO_LAST_NOTE_UID (src_regno) = move_uid; | |
842 | } | |
843 | } | |
844 | ||
845 | \f | |
184bb750 R |
846 | /* Return whether REG is set in only one location, and is set to a |
847 | constant, but is set in a different basic block from INSN (an | |
848 | instructions which uses REG). In this case REG is equivalent to a | |
849 | constant, and we don't want to break that equivalence, because that | |
850 | may increase register pressure and make reload harder. If REG is | |
851 | set in the same basic block as INSN, we don't worry about it, | |
852 | because we'll probably need a register anyhow (??? but what if REG | |
853 | is used in a different basic block as well as this one?). FIRST is | |
854 | the first insn in the function. */ | |
855 | ||
856 | static int | |
857 | reg_is_remote_constant_p (reg, insn, first) | |
858 | rtx reg; | |
859 | rtx insn; | |
860 | rtx first; | |
861 | { | |
862 | register rtx p; | |
863 | ||
864 | if (REG_N_SETS (REGNO (reg)) != 1) | |
865 | return 0; | |
866 | ||
867 | /* Look for the set. */ | |
868 | for (p = LOG_LINKS (insn); p; p = XEXP (p, 1)) | |
869 | { | |
870 | rtx s; | |
871 | ||
872 | if (REG_NOTE_KIND (p) != 0) | |
873 | continue; | |
874 | s = single_set (XEXP (p, 0)); | |
875 | if (s != 0 | |
876 | && GET_CODE (SET_DEST (s)) == REG | |
877 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
878 | { | |
879 | /* The register is set in the same basic block. */ | |
880 | return 0; | |
881 | } | |
882 | } | |
883 | ||
884 | for (p = first; p && p != insn; p = NEXT_INSN (p)) | |
885 | { | |
886 | rtx s; | |
887 | ||
888 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
889 | continue; | |
890 | s = single_set (p); | |
891 | if (s != 0 | |
892 | && GET_CODE (SET_DEST (s)) == REG | |
893 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
894 | { | |
895 | /* This is the instruction which sets REG. If there is a | |
896 | REG_EQUAL note, then REG is equivalent to a constant. */ | |
897 | if (find_reg_note (p, REG_EQUAL, NULL_RTX)) | |
898 | return 1; | |
899 | return 0; | |
900 | } | |
901 | } | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
b1a7d591 JW |
906 | /* INSN is adding a CONST_INT to a REG. We search backwards looking for |
907 | another add immediate instruction with the same source and dest registers, | |
908 | and if we find one, we change INSN to an increment, and return 1. If | |
909 | no changes are made, we return 0. | |
910 | ||
911 | This changes | |
912 | (set (reg100) (plus reg1 offset1)) | |
913 | ... | |
914 | (set (reg100) (plus reg1 offset2)) | |
915 | to | |
916 | (set (reg100) (plus reg1 offset1)) | |
917 | ... | |
918 | (set (reg100) (plus reg100 offset2-offset1)) */ | |
919 | ||
920 | /* ??? What does this comment mean? */ | |
184bb750 R |
921 | /* cse disrupts preincrement / postdecrement squences when it finds a |
922 | hard register as ultimate source, like the frame pointer. */ | |
b1a7d591 | 923 | |
95d75019 | 924 | static int |
7bf825d2 | 925 | fixup_match_2 (insn, dst, src, offset, regmove_dump_file) |
184bb750 R |
926 | rtx insn, dst, src, offset; |
927 | FILE *regmove_dump_file; | |
928 | { | |
929 | rtx p, dst_death = 0; | |
930 | int length, num_calls = 0; | |
931 | ||
932 | /* If SRC dies in INSN, we'd have to move the death note. This is | |
933 | considered to be very unlikely, so we just skip the optimization | |
934 | in this case. */ | |
935 | if (find_regno_note (insn, REG_DEAD, REGNO (src))) | |
936 | return 0; | |
937 | ||
938 | /* Scan backward to find the first instruction that sets DST. */ | |
939 | ||
940 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
941 | { | |
942 | rtx pset; | |
943 | ||
944 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 945 | || GET_CODE (p) == JUMP_INSN) |
184bb750 R |
946 | break; |
947 | ||
7bf825d2 JW |
948 | /* ??? We can't scan past the end of a basic block without updating |
949 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
950 | A CALL_INSN might be the last insn of a basic block, if it is inside | |
951 | an EH region. There is no easy way to tell, so we just always break | |
952 | when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
953 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
954 | break; | |
955 | ||
184bb750 R |
956 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
957 | continue; | |
958 | ||
7bf825d2 JW |
959 | if (find_regno_note (p, REG_DEAD, REGNO (dst))) |
960 | dst_death = p; | |
961 | if (! dst_death) | |
962 | length++; | |
184bb750 R |
963 | |
964 | pset = single_set (p); | |
965 | if (pset && SET_DEST (pset) == dst | |
966 | && GET_CODE (SET_SRC (pset)) == PLUS | |
967 | && XEXP (SET_SRC (pset), 0) == src | |
968 | && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT) | |
969 | { | |
970 | HOST_WIDE_INT newconst | |
971 | = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1)); | |
1a29f703 R |
972 | rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst)); |
973 | ||
974 | if (add && validate_change (insn, &PATTERN (insn), add, 0)) | |
184bb750 R |
975 | { |
976 | /* Remove the death note for DST from DST_DEATH. */ | |
977 | if (dst_death) | |
978 | { | |
979 | remove_death (REGNO (dst), dst_death); | |
980 | REG_LIVE_LENGTH (REGNO (dst)) += length; | |
981 | REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls; | |
982 | } | |
983 | ||
184bb750 R |
984 | if (regmove_dump_file) |
985 | fprintf (regmove_dump_file, | |
986 | "Fixed operand of insn %d.\n", | |
987 | INSN_UID (insn)); | |
988 | ||
989 | #ifdef AUTO_INC_DEC | |
990 | for (p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
991 | { | |
992 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 993 | || GET_CODE (p) == JUMP_INSN) |
184bb750 | 994 | break; |
e27a5106 JL |
995 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
996 | continue; | |
184bb750 R |
997 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
998 | { | |
999 | if (try_auto_increment (p, insn, 0, dst, newconst, 0)) | |
1000 | return 1; | |
1001 | break; | |
1002 | } | |
1003 | } | |
1004 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1005 | { | |
1006 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 1007 | || GET_CODE (p) == JUMP_INSN) |
184bb750 | 1008 | break; |
8543c01e R |
1009 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
1010 | continue; | |
184bb750 R |
1011 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1012 | { | |
1013 | try_auto_increment (p, insn, 0, dst, newconst, 1); | |
1014 | break; | |
1015 | } | |
1016 | } | |
1017 | #endif | |
1018 | return 1; | |
1019 | } | |
8c660648 | 1020 | } |
184bb750 R |
1021 | |
1022 | if (reg_set_p (dst, PATTERN (p))) | |
1023 | break; | |
1024 | ||
1025 | /* If we have passed a call instruction, and the | |
1026 | pseudo-reg SRC is not already live across a call, | |
1027 | then don't perform the optimization. */ | |
1028 | /* reg_set_p is overly conservative for CALL_INSNS, thinks that all | |
1029 | hard regs are clobbered. Thus, we only use it for src for | |
1030 | non-call insns. */ | |
1031 | if (GET_CODE (p) == CALL_INSN) | |
1032 | { | |
1033 | if (! dst_death) | |
1034 | num_calls++; | |
1035 | ||
1036 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1037 | break; | |
1038 | ||
1039 | if (call_used_regs [REGNO (dst)] | |
1040 | || find_reg_fusage (p, CLOBBER, dst)) | |
1041 | break; | |
1042 | } | |
1043 | else if (reg_set_p (src, PATTERN (p))) | |
1044 | break; | |
8c660648 | 1045 | } |
184bb750 | 1046 | |
8c660648 JL |
1047 | return 0; |
1048 | } | |
8c660648 JL |
1049 | |
1050 | void | |
1051 | regmove_optimize (f, nregs, regmove_dump_file) | |
1052 | rtx f; | |
1053 | int nregs; | |
1054 | FILE *regmove_dump_file; | |
1055 | { | |
961d4119 | 1056 | int old_max_uid = get_max_uid (); |
8c660648 | 1057 | rtx insn; |
184bb750 | 1058 | struct match match; |
8c660648 | 1059 | int pass; |
3bb806ed | 1060 | int i; |
ddc8bed2 | 1061 | rtx copy_src, copy_dst; |
184bb750 | 1062 | |
dc2cb191 RH |
1063 | /* Find out where a potential flags register is live, and so that we |
1064 | can supress some optimizations in those zones. */ | |
1065 | mark_flags_life_zones (discover_flags_reg ()); | |
1066 | ||
4da896b2 | 1067 | regno_src_regno = (int *) xmalloc (sizeof *regno_src_regno * nregs); |
3bb806ed | 1068 | for (i = nregs; --i >= 0; ) regno_src_regno[i] = -1; |
8c660648 | 1069 | |
4da896b2 | 1070 | regmove_bb_head = (int *) xmalloc (sizeof (int) * (old_max_uid + 1)); |
961d4119 | 1071 | for (i = old_max_uid; i >= 0; i--) regmove_bb_head[i] = -1; |
ddc8bed2 | 1072 | for (i = 0; i < n_basic_blocks; i++) |
3b413743 | 1073 | regmove_bb_head[INSN_UID (BLOCK_HEAD (i))] = i; |
ddc8bed2 | 1074 | |
8c660648 JL |
1075 | /* A forward/backward pass. Replace output operands with input operands. */ |
1076 | ||
184bb750 | 1077 | for (pass = 0; pass <= 2; pass++) |
8c660648 | 1078 | { |
184bb750 | 1079 | if (! flag_regmove && pass >= flag_expensive_optimizations) |
4da896b2 | 1080 | goto done; |
184bb750 | 1081 | |
8c660648 JL |
1082 | if (regmove_dump_file) |
1083 | fprintf (regmove_dump_file, "Starting %s pass...\n", | |
1084 | pass ? "backward" : "forward"); | |
1085 | ||
1086 | for (insn = pass ? get_last_insn () : f; insn; | |
1087 | insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn)) | |
1088 | { | |
184bb750 | 1089 | rtx set; |
0eadeb15 | 1090 | int op_no, match_no; |
184bb750 | 1091 | |
184bb750 R |
1092 | set = single_set (insn); |
1093 | if (! set) | |
1094 | continue; | |
8c660648 | 1095 | |
184bb750 R |
1096 | if (flag_expensive_optimizations && ! pass |
1097 | && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND | |
1098 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND) | |
1099 | && GET_CODE (XEXP (SET_SRC (set), 0)) == REG | |
1100 | && GET_CODE (SET_DEST(set)) == REG) | |
1101 | optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set)); | |
1102 | ||
1103 | if (flag_expensive_optimizations && ! pass | |
1104 | && GET_CODE (SET_SRC (set)) == REG | |
1105 | && GET_CODE (SET_DEST(set)) == REG) | |
1106 | { | |
1107 | /* If this is a register-register copy where SRC is not dead, | |
1108 | see if we can optimize it. If this optimization succeeds, | |
1109 | it will become a copy where SRC is dead. */ | |
1110 | if ((find_reg_note (insn, REG_DEAD, SET_SRC (set)) | |
1111 | || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set))) | |
1112 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) | |
8c660648 | 1113 | { |
184bb750 R |
1114 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ |
1115 | if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1116 | optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set)); | |
1117 | if (regno_src_regno[REGNO (SET_DEST (set))] < 0 | |
1118 | && SET_SRC (set) != SET_DEST (set)) | |
8c660648 | 1119 | { |
184bb750 R |
1120 | int srcregno = REGNO (SET_SRC(set)); |
1121 | if (regno_src_regno[srcregno] >= 0) | |
1122 | srcregno = regno_src_regno[srcregno]; | |
1123 | regno_src_regno[REGNO (SET_DEST (set))] = srcregno; | |
8c660648 JL |
1124 | } |
1125 | } | |
184bb750 | 1126 | } |
8d1d76c1 R |
1127 | if (! flag_regmove) |
1128 | continue; | |
184bb750 | 1129 | |
3363316f | 1130 | if (! find_matches (insn, &match)) |
184bb750 R |
1131 | continue; |
1132 | ||
1133 | /* Now scan through the operands looking for a source operand | |
1134 | which is supposed to match the destination operand. | |
1135 | Then scan forward for an instruction which uses the dest | |
1136 | operand. | |
1137 | If it dies there, then replace the dest in both operands with | |
1138 | the source operand. */ | |
1139 | ||
1ccbefce | 1140 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1141 | { |
5e9defae | 1142 | rtx src, dst, src_subreg; |
184bb750 R |
1143 | enum reg_class src_class, dst_class; |
1144 | ||
0eadeb15 | 1145 | match_no = match.with[op_no]; |
184bb750 R |
1146 | |
1147 | /* Nothing to do if the two operands aren't supposed to match. */ | |
0eadeb15 | 1148 | if (match_no < 0) |
184bb750 R |
1149 | continue; |
1150 | ||
1ccbefce RH |
1151 | src = recog_data.operand[op_no]; |
1152 | dst = recog_data.operand[match_no]; | |
184bb750 R |
1153 | |
1154 | if (GET_CODE (src) != REG) | |
1155 | continue; | |
1156 | ||
1157 | src_subreg = src; | |
1158 | if (GET_CODE (dst) == SUBREG | |
1159 | && GET_MODE_SIZE (GET_MODE (dst)) | |
1160 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst)))) | |
1161 | { | |
1162 | src_subreg | |
38a448ca RH |
1163 | = gen_rtx_SUBREG (GET_MODE (SUBREG_REG (dst)), |
1164 | src, SUBREG_WORD (dst)); | |
184bb750 R |
1165 | dst = SUBREG_REG (dst); |
1166 | } | |
1167 | if (GET_CODE (dst) != REG | |
1168 | || REGNO (dst) < FIRST_PSEUDO_REGISTER) | |
1169 | continue; | |
1170 | ||
1171 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) | |
1172 | { | |
0eadeb15 | 1173 | if (match.commutative[op_no] < op_no) |
184bb750 R |
1174 | regno_src_regno[REGNO (dst)] = REGNO (src); |
1175 | continue; | |
1176 | } | |
1177 | ||
1178 | if (REG_LIVE_LENGTH (REGNO (src)) < 0) | |
1179 | continue; | |
1180 | ||
0eadeb15 | 1181 | /* op_no/src must be a read-only operand, and |
184bb750 | 1182 | match_operand/dst must be a write-only operand. */ |
0eadeb15 BS |
1183 | if (match.use[op_no] != READ |
1184 | || match.use[match_no] != WRITE) | |
184bb750 R |
1185 | continue; |
1186 | ||
0eadeb15 | 1187 | if (match.early_clobber[match_no] |
184bb750 R |
1188 | && count_occurrences (PATTERN (insn), src) > 1) |
1189 | continue; | |
1190 | ||
1191 | /* Make sure match_operand is the destination. */ | |
1ccbefce | 1192 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 R |
1193 | continue; |
1194 | ||
1ccbefce RH |
1195 | /* If the operands already match, then there is nothing to do. */ |
1196 | if (operands_match_p (src, dst)) | |
184bb750 R |
1197 | continue; |
1198 | ||
1ccbefce RH |
1199 | /* But in the commutative case, we might find a better match. */ |
1200 | if (match.commutative[op_no] >= 0) | |
1201 | { | |
1202 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1203 | if (operands_match_p (comm, dst) | |
1204 | && (replacement_quality (comm) | |
1205 | >= replacement_quality (src))) | |
1206 | continue; | |
1207 | } | |
1208 | ||
184bb750 R |
1209 | src_class = reg_preferred_class (REGNO (src)); |
1210 | dst_class = reg_preferred_class (REGNO (dst)); | |
3bb806ed | 1211 | if (! regclass_compatible_p (src_class, dst_class)) |
184bb750 R |
1212 | continue; |
1213 | ||
1214 | if (fixup_match_1 (insn, set, src, src_subreg, dst, pass, | |
0eadeb15 | 1215 | op_no, match_no, |
184bb750 R |
1216 | regmove_dump_file)) |
1217 | break; | |
8c660648 JL |
1218 | } |
1219 | } | |
1220 | } | |
1221 | ||
1222 | /* A backward pass. Replace input operands with output operands. */ | |
1223 | ||
1224 | if (regmove_dump_file) | |
1225 | fprintf (regmove_dump_file, "Starting backward pass...\n"); | |
1226 | ||
1227 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
1228 | { | |
1229 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1230 | { | |
0eadeb15 | 1231 | int op_no, match_no; |
ddc8bed2 | 1232 | int success = 0; |
0eadeb15 | 1233 | |
3363316f | 1234 | if (! find_matches (insn, &match)) |
8c660648 JL |
1235 | continue; |
1236 | ||
8c660648 JL |
1237 | /* Now scan through the operands looking for a destination operand |
1238 | which is supposed to match a source operand. | |
1239 | Then scan backward for an instruction which sets the source | |
1240 | operand. If safe, then replace the source operand with the | |
1241 | dest operand in both instructions. */ | |
1242 | ||
ddc8bed2 MM |
1243 | copy_src = NULL_RTX; |
1244 | copy_dst = NULL_RTX; | |
1ccbefce | 1245 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
8c660648 | 1246 | { |
184bb750 R |
1247 | rtx set, p, src, dst; |
1248 | rtx src_note, dst_note; | |
184bb750 R |
1249 | int num_calls = 0; |
1250 | enum reg_class src_class, dst_class; | |
1251 | int length; | |
8c660648 | 1252 | |
0eadeb15 | 1253 | match_no = match.with[op_no]; |
8c660648 | 1254 | |
184bb750 | 1255 | /* Nothing to do if the two operands aren't supposed to match. */ |
0eadeb15 | 1256 | if (match_no < 0) |
184bb750 | 1257 | continue; |
8c660648 | 1258 | |
1ccbefce RH |
1259 | dst = recog_data.operand[match_no]; |
1260 | src = recog_data.operand[op_no]; | |
8c660648 | 1261 | |
184bb750 R |
1262 | if (GET_CODE (src) != REG) |
1263 | continue; | |
8c660648 | 1264 | |
184bb750 R |
1265 | if (GET_CODE (dst) != REG |
1266 | || REGNO (dst) < FIRST_PSEUDO_REGISTER | |
1267 | || REG_LIVE_LENGTH (REGNO (dst)) < 0) | |
1268 | continue; | |
8c660648 | 1269 | |
1ccbefce RH |
1270 | /* If the operands already match, then there is nothing to do. */ |
1271 | if (operands_match_p (src, dst)) | |
184bb750 | 1272 | continue; |
8c660648 | 1273 | |
1ccbefce RH |
1274 | if (match.commutative[op_no] >= 0) |
1275 | { | |
1276 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1277 | if (operands_match_p (comm, dst)) | |
1278 | continue; | |
1279 | } | |
1280 | ||
184bb750 R |
1281 | set = single_set (insn); |
1282 | if (! set) | |
1283 | continue; | |
8c660648 | 1284 | |
0eadeb15 | 1285 | /* match_no/dst must be a write-only operand, and |
184bb750 | 1286 | operand_operand/src must be a read-only operand. */ |
0eadeb15 BS |
1287 | if (match.use[op_no] != READ |
1288 | || match.use[match_no] != WRITE) | |
184bb750 | 1289 | continue; |
8c660648 | 1290 | |
0eadeb15 | 1291 | if (match.early_clobber[match_no] |
184bb750 R |
1292 | && count_occurrences (PATTERN (insn), src) > 1) |
1293 | continue; | |
8c660648 | 1294 | |
0eadeb15 | 1295 | /* Make sure match_no is the destination. */ |
1ccbefce | 1296 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 | 1297 | continue; |
8c660648 | 1298 | |
184bb750 R |
1299 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) |
1300 | { | |
1301 | if (GET_CODE (SET_SRC (set)) == PLUS | |
1302 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT | |
1303 | && XEXP (SET_SRC (set), 0) == src | |
1304 | && fixup_match_2 (insn, dst, src, | |
1305 | XEXP (SET_SRC (set), 1), | |
1306 | regmove_dump_file)) | |
1307 | break; | |
1308 | continue; | |
1309 | } | |
1310 | src_class = reg_preferred_class (REGNO (src)); | |
1311 | dst_class = reg_preferred_class (REGNO (dst)); | |
3bb806ed | 1312 | if (! regclass_compatible_p (src_class, dst_class)) |
ddc8bed2 MM |
1313 | { |
1314 | if (!copy_src) | |
1315 | { | |
1316 | copy_src = src; | |
1317 | copy_dst = dst; | |
1318 | } | |
1319 | continue; | |
1320 | } | |
8c660648 | 1321 | |
184bb750 R |
1322 | /* Can not modify an earlier insn to set dst if this insn |
1323 | uses an old value in the source. */ | |
1324 | if (reg_overlap_mentioned_p (dst, SET_SRC (set))) | |
ddc8bed2 MM |
1325 | { |
1326 | if (!copy_src) | |
1327 | { | |
1328 | copy_src = src; | |
1329 | copy_dst = dst; | |
1330 | } | |
1331 | continue; | |
1332 | } | |
1333 | ||
1334 | if (! (src_note = find_reg_note (insn, REG_DEAD, src))) | |
1335 | { | |
1336 | if (!copy_src) | |
1337 | { | |
1338 | copy_src = src; | |
1339 | copy_dst = dst; | |
1340 | } | |
1341 | continue; | |
1342 | } | |
8c660648 | 1343 | |
8c660648 | 1344 | |
184bb750 R |
1345 | /* If src is set once in a different basic block, |
1346 | and is set equal to a constant, then do not use | |
1347 | it for this optimization, as this would make it | |
1348 | no longer equivalent to a constant. */ | |
ddc8bed2 MM |
1349 | |
1350 | if (reg_is_remote_constant_p (src, insn, f)) | |
1351 | { | |
1352 | if (!copy_src) | |
1353 | { | |
1354 | copy_src = src; | |
1355 | copy_dst = dst; | |
1356 | } | |
1357 | continue; | |
1358 | } | |
1359 | ||
1360 | ||
1361 | if (regmove_dump_file) | |
1362 | fprintf (regmove_dump_file, | |
1363 | "Could fix operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1364 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1365 | |
184bb750 R |
1366 | /* Scan backward to find the first instruction that uses |
1367 | the input operand. If the operand is set here, then | |
0eadeb15 | 1368 | replace it in both instructions with match_no. */ |
184bb750 R |
1369 | |
1370 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1371 | { | |
1372 | rtx pset; | |
1373 | ||
1374 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 1375 | || GET_CODE (p) == JUMP_INSN) |
184bb750 R |
1376 | break; |
1377 | ||
7bf825d2 JW |
1378 | /* ??? We can't scan past the end of a basic block without |
1379 | updating the register lifetime info | |
1380 | (REG_DEAD/basic_block_live_at_start). | |
1381 | A CALL_INSN might be the last insn of a basic block, if | |
1382 | it is inside an EH region. There is no easy way to tell, | |
1383 | so we just always break when we see a CALL_INSN if | |
1384 | flag_exceptions is nonzero. */ | |
1385 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
1386 | break; | |
1387 | ||
184bb750 R |
1388 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
1389 | continue; | |
8c660648 | 1390 | |
184bb750 | 1391 | length++; |
8c660648 | 1392 | |
184bb750 R |
1393 | /* ??? See if all of SRC is set in P. This test is much |
1394 | more conservative than it needs to be. */ | |
1395 | pset = single_set (p); | |
1396 | if (pset && SET_DEST (pset) == src) | |
1397 | { | |
1398 | /* We use validate_replace_rtx, in case there | |
1399 | are multiple identical source operands. All of | |
1400 | them have to be changed at the same time. */ | |
1401 | if (validate_replace_rtx (src, dst, insn)) | |
8c660648 | 1402 | { |
184bb750 R |
1403 | if (validate_change (p, &SET_DEST (pset), |
1404 | dst, 0)) | |
1405 | success = 1; | |
1406 | else | |
8c660648 | 1407 | { |
184bb750 R |
1408 | /* Change all source operands back. |
1409 | This modifies the dst as a side-effect. */ | |
1410 | validate_replace_rtx (dst, src, insn); | |
1411 | /* Now make sure the dst is right. */ | |
1412 | validate_change (insn, | |
1ccbefce | 1413 | recog_data.operand_loc[match_no], |
184bb750 | 1414 | dst, 0); |
8c660648 | 1415 | } |
8c660648 | 1416 | } |
184bb750 R |
1417 | break; |
1418 | } | |
1419 | ||
1420 | if (reg_overlap_mentioned_p (src, PATTERN (p)) | |
1421 | || reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1422 | break; | |
8c660648 | 1423 | |
184bb750 R |
1424 | /* If we have passed a call instruction, and the |
1425 | pseudo-reg DST is not already live across a call, | |
1426 | then don't perform the optimization. */ | |
1427 | if (GET_CODE (p) == CALL_INSN) | |
1428 | { | |
1429 | num_calls++; | |
1430 | ||
1431 | if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0) | |
8c660648 | 1432 | break; |
184bb750 R |
1433 | } |
1434 | } | |
8c660648 | 1435 | |
184bb750 R |
1436 | if (success) |
1437 | { | |
1438 | int dstno, srcno; | |
8c660648 | 1439 | |
184bb750 R |
1440 | /* Remove the death note for SRC from INSN. */ |
1441 | remove_note (insn, src_note); | |
1442 | /* Move the death note for SRC to P if it is used | |
1443 | there. */ | |
1444 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1445 | { | |
1446 | XEXP (src_note, 1) = REG_NOTES (p); | |
1447 | REG_NOTES (p) = src_note; | |
8c660648 | 1448 | } |
184bb750 R |
1449 | /* If there is a REG_DEAD note for DST on P, then remove |
1450 | it, because DST is now set there. */ | |
5e9defae | 1451 | if ((dst_note = find_reg_note (p, REG_DEAD, dst))) |
184bb750 R |
1452 | remove_note (p, dst_note); |
1453 | ||
1454 | dstno = REGNO (dst); | |
1455 | srcno = REGNO (src); | |
1456 | ||
1457 | REG_N_SETS (dstno)++; | |
1458 | REG_N_SETS (srcno)--; | |
8c660648 | 1459 | |
184bb750 R |
1460 | REG_N_CALLS_CROSSED (dstno) += num_calls; |
1461 | REG_N_CALLS_CROSSED (srcno) -= num_calls; | |
1462 | ||
1463 | REG_LIVE_LENGTH (dstno) += length; | |
1464 | if (REG_LIVE_LENGTH (srcno) >= 0) | |
8c660648 | 1465 | { |
184bb750 R |
1466 | REG_LIVE_LENGTH (srcno) -= length; |
1467 | /* REG_LIVE_LENGTH is only an approximation after | |
1468 | combine if sched is not run, so make sure that we | |
1469 | still have a reasonable value. */ | |
1470 | if (REG_LIVE_LENGTH (srcno) < 2) | |
1471 | REG_LIVE_LENGTH (srcno) = 2; | |
1472 | } | |
8c660648 | 1473 | |
184bb750 R |
1474 | if (regmove_dump_file) |
1475 | fprintf (regmove_dump_file, | |
1476 | "Fixed operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1477 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1478 | |
184bb750 | 1479 | break; |
8c660648 JL |
1480 | } |
1481 | } | |
ddc8bed2 MM |
1482 | |
1483 | /* If we weren't able to replace any of the alternatives, try an | |
1484 | alternative appoach of copying the source to the destination. */ | |
1485 | if (!success && copy_src != NULL_RTX) | |
1b7c4a37 | 1486 | copy_src_to_dest (insn, copy_src, copy_dst, old_max_uid); |
ddc8bed2 | 1487 | |
8c660648 JL |
1488 | } |
1489 | } | |
961d4119 BS |
1490 | |
1491 | /* In fixup_match_1, some insns may have been inserted after basic block | |
1492 | ends. Fix that here. */ | |
1493 | for (i = 0; i < n_basic_blocks; i++) | |
1494 | { | |
3b413743 | 1495 | rtx end = BLOCK_END (i); |
961d4119 BS |
1496 | rtx new = end; |
1497 | rtx next = NEXT_INSN (new); | |
1498 | while (next != 0 && INSN_UID (next) >= old_max_uid | |
3b413743 | 1499 | && (i == n_basic_blocks - 1 || BLOCK_HEAD (i + 1) != next)) |
961d4119 | 1500 | new = next, next = NEXT_INSN (new); |
3b413743 | 1501 | BLOCK_END (i) = new; |
961d4119 | 1502 | } |
4da896b2 MM |
1503 | |
1504 | done: | |
1505 | /* Clean up. */ | |
1506 | free (regno_src_regno); | |
1507 | free (regmove_bb_head); | |
8c660648 JL |
1508 | } |
1509 | ||
0eadeb15 BS |
1510 | /* Returns nonzero if INSN's pattern has matching constraints for any operand. |
1511 | Returns 0 if INSN can't be recognized, or if the alternative can't be | |
1512 | determined. | |
b1a7d591 JW |
1513 | |
1514 | Initialize the info in MATCHP based on the constraints. */ | |
184bb750 R |
1515 | |
1516 | static int | |
1517 | find_matches (insn, matchp) | |
1518 | rtx insn; | |
1519 | struct match *matchp; | |
1520 | { | |
1521 | int likely_spilled[MAX_RECOG_OPERANDS]; | |
0eadeb15 | 1522 | int op_no; |
184bb750 R |
1523 | int any_matches = 0; |
1524 | ||
0eadeb15 BS |
1525 | extract_insn (insn); |
1526 | if (! constrain_operands (0)) | |
1527 | return 0; | |
184bb750 R |
1528 | |
1529 | /* Must initialize this before main loop, because the code for | |
1530 | the commutative case may set matches for operands other than | |
1531 | the current one. */ | |
1ccbefce | 1532 | for (op_no = recog_data.n_operands; --op_no >= 0; ) |
0eadeb15 | 1533 | matchp->with[op_no] = matchp->commutative[op_no] = -1; |
184bb750 | 1534 | |
1ccbefce | 1535 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1536 | { |
9b3142b3 KG |
1537 | const char *p; |
1538 | char c; | |
184bb750 R |
1539 | int i = 0; |
1540 | ||
1ccbefce | 1541 | p = recog_data.constraints[op_no]; |
184bb750 | 1542 | |
0eadeb15 BS |
1543 | likely_spilled[op_no] = 0; |
1544 | matchp->use[op_no] = READ; | |
1545 | matchp->early_clobber[op_no] = 0; | |
184bb750 | 1546 | if (*p == '=') |
0eadeb15 | 1547 | matchp->use[op_no] = WRITE; |
184bb750 | 1548 | else if (*p == '+') |
0eadeb15 | 1549 | matchp->use[op_no] = READWRITE; |
184bb750 R |
1550 | |
1551 | for (;*p && i < which_alternative; p++) | |
1552 | if (*p == ',') | |
1553 | i++; | |
1554 | ||
1555 | while ((c = *p++) != '\0' && c != ',') | |
1556 | switch (c) | |
1557 | { | |
1558 | case '=': | |
1559 | break; | |
1560 | case '+': | |
1561 | break; | |
1562 | case '&': | |
0eadeb15 | 1563 | matchp->early_clobber[op_no] = 1; |
184bb750 R |
1564 | break; |
1565 | case '%': | |
0eadeb15 BS |
1566 | matchp->commutative[op_no] = op_no + 1; |
1567 | matchp->commutative[op_no + 1] = op_no; | |
184bb750 R |
1568 | break; |
1569 | case '0': case '1': case '2': case '3': case '4': | |
1570 | case '5': case '6': case '7': case '8': case '9': | |
1571 | c -= '0'; | |
0eadeb15 | 1572 | if (c < op_no && likely_spilled[(unsigned char) c]) |
184bb750 | 1573 | break; |
0eadeb15 | 1574 | matchp->with[op_no] = c; |
184bb750 | 1575 | any_matches = 1; |
0eadeb15 BS |
1576 | if (matchp->commutative[op_no] >= 0) |
1577 | matchp->with[matchp->commutative[op_no]] = c; | |
184bb750 R |
1578 | break; |
1579 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h': | |
1580 | case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u': | |
1581 | case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B': | |
1582 | case 'C': case 'D': case 'W': case 'Y': case 'Z': | |
973838fd | 1583 | if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_LETTER ((unsigned char)c))) |
0eadeb15 | 1584 | likely_spilled[op_no] = 1; |
184bb750 R |
1585 | break; |
1586 | } | |
1587 | } | |
0eadeb15 | 1588 | return any_matches; |
184bb750 R |
1589 | } |
1590 | ||
1591 | /* Try to replace output operand DST in SET, with input operand SRC. SET is | |
06671717 | 1592 | the only set in INSN. INSN has just been recognized and constrained. |
184bb750 R |
1593 | SRC is operand number OPERAND_NUMBER in INSN. |
1594 | DST is operand number MATCH_NUMBER in INSN. | |
1595 | If BACKWARD is nonzero, we have been called in a backward pass. | |
1596 | Return nonzero for success. */ | |
1597 | static int | |
1598 | fixup_match_1 (insn, set, src, src_subreg, dst, backward, operand_number, | |
1599 | match_number, regmove_dump_file) | |
1600 | rtx insn, set, src, src_subreg, dst; | |
1601 | int backward, operand_number, match_number; | |
1602 | FILE *regmove_dump_file; | |
1603 | { | |
1604 | rtx p; | |
1605 | rtx post_inc = 0, post_inc_set = 0, search_end = 0; | |
1606 | int success = 0; | |
1607 | int num_calls = 0, s_num_calls = 0; | |
1608 | enum rtx_code code = NOTE; | |
a544cfd2 | 1609 | HOST_WIDE_INT insn_const = 0, newconst; |
184bb750 | 1610 | rtx overlap = 0; /* need to move insn ? */ |
a544cfd2 | 1611 | rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note = NULL_RTX; |
1b7c4a37 | 1612 | int length, s_length; |
184bb750 | 1613 | |
18bf656f R |
1614 | /* If SRC is marked as unchanging, we may not change it. |
1615 | ??? Maybe we could get better code by removing the unchanging bit | |
1616 | instead, and changing it back if we don't succeed? */ | |
1617 | if (RTX_UNCHANGING_P (src)) | |
1618 | return 0; | |
1619 | ||
184bb750 R |
1620 | if (! src_note) |
1621 | { | |
1622 | /* Look for (set (regX) (op regA constX)) | |
1623 | (set (regY) (op regA constY)) | |
1624 | and change that to | |
1625 | (set (regA) (op regA constX)). | |
1626 | (set (regY) (op regA constY-constX)). | |
1627 | This works for add and shift operations, if | |
1628 | regA is dead after or set by the second insn. */ | |
1629 | ||
1630 | code = GET_CODE (SET_SRC (set)); | |
1631 | if ((code == PLUS || code == LSHIFTRT | |
1632 | || code == ASHIFT || code == ASHIFTRT) | |
1633 | && XEXP (SET_SRC (set), 0) == src | |
1634 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
1635 | insn_const = INTVAL (XEXP (SET_SRC (set), 1)); | |
18bf656f | 1636 | else if (! stable_and_no_regs_but_for_p (SET_SRC (set), src, dst)) |
184bb750 R |
1637 | return 0; |
1638 | else | |
1639 | /* We might find a src_note while scanning. */ | |
1640 | code = NOTE; | |
1641 | } | |
1642 | ||
1643 | if (regmove_dump_file) | |
1644 | fprintf (regmove_dump_file, | |
1645 | "Could fix operand %d of insn %d matching operand %d.\n", | |
1646 | operand_number, INSN_UID (insn), match_number); | |
1647 | ||
1648 | /* If SRC is equivalent to a constant set in a different basic block, | |
1649 | then do not use it for this optimization. We want the equivalence | |
1650 | so that if we have to reload this register, we can reload the | |
1651 | constant, rather than extending the lifespan of the register. */ | |
1652 | if (reg_is_remote_constant_p (src, insn, get_insns ())) | |
1653 | return 0; | |
1654 | ||
1655 | /* Scan forward to find the next instruction that | |
1656 | uses the output operand. If the operand dies here, | |
1657 | then replace it in both instructions with | |
1658 | operand_number. */ | |
1659 | ||
1660 | for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1661 | { | |
07aaad94 | 1662 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) |
184bb750 R |
1663 | break; |
1664 | ||
7bf825d2 JW |
1665 | /* ??? We can't scan past the end of a basic block without updating |
1666 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
1667 | A CALL_INSN might be the last insn of a basic block, if it is | |
1668 | inside an EH region. There is no easy way to tell, so we just | |
1669 | always break when we see a CALL_INSN if flag_exceptions is nonzero. */ | |
1670 | if (flag_exceptions && GET_CODE (p) == CALL_INSN) | |
1671 | break; | |
1672 | ||
184bb750 R |
1673 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
1674 | continue; | |
1675 | ||
1676 | length++; | |
1677 | if (src_note) | |
1678 | s_length++; | |
1679 | ||
1680 | if (reg_set_p (src, p) || reg_set_p (dst, p) | |
1681 | || (GET_CODE (PATTERN (p)) == USE | |
1682 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
1683 | break; | |
1684 | ||
1685 | /* See if all of DST dies in P. This test is | |
1686 | slightly more conservative than it needs to be. */ | |
1687 | if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst))) | |
1688 | && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst))) | |
1689 | { | |
2219e921 R |
1690 | /* If we would be moving INSN, check that we won't move it |
1691 | into the shadow of a live a live flags register. */ | |
1692 | /* ??? We only try to move it in front of P, although | |
1693 | we could move it anywhere between OVERLAP and P. */ | |
1694 | if (overlap && GET_MODE (PREV_INSN (p)) != VOIDmode) | |
1695 | break; | |
1696 | ||
184bb750 R |
1697 | if (! src_note) |
1698 | { | |
1699 | rtx q; | |
a544cfd2 | 1700 | rtx set2 = NULL_RTX; |
184bb750 R |
1701 | |
1702 | /* If an optimization is done, the value of SRC while P | |
1703 | is executed will be changed. Check that this is OK. */ | |
1704 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1705 | break; | |
1706 | for (q = p; q; q = NEXT_INSN (q)) | |
1707 | { | |
07aaad94 | 1708 | if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN) |
184bb750 R |
1709 | { |
1710 | q = 0; | |
1711 | break; | |
1712 | } | |
7bf825d2 JW |
1713 | |
1714 | /* ??? We can't scan past the end of a basic block without | |
1715 | updating the register lifetime info | |
1716 | (REG_DEAD/basic_block_live_at_start). | |
1717 | A CALL_INSN might be the last insn of a basic block, if | |
1718 | it is inside an EH region. There is no easy way to tell, | |
1719 | so we just always break when we see a CALL_INSN if | |
1720 | flag_exceptions is nonzero. */ | |
a1ecb5ca | 1721 | if (flag_exceptions && GET_CODE (q) == CALL_INSN) |
7bf825d2 JW |
1722 | { |
1723 | q = 0; | |
1724 | break; | |
1725 | } | |
1726 | ||
184bb750 R |
1727 | if (GET_RTX_CLASS (GET_CODE (q)) != 'i') |
1728 | continue; | |
1729 | if (reg_overlap_mentioned_p (src, PATTERN (q)) | |
1730 | || reg_set_p (src, q)) | |
1731 | break; | |
1732 | } | |
1733 | if (q) | |
1734 | set2 = single_set (q); | |
1735 | if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code | |
1736 | || XEXP (SET_SRC (set2), 0) != src | |
1737 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT | |
1738 | || (SET_DEST (set2) != src | |
1739 | && ! find_reg_note (q, REG_DEAD, src))) | |
1740 | { | |
1741 | /* If this is a PLUS, we can still save a register by doing | |
1742 | src += insn_const; | |
1743 | P; | |
1744 | src -= insn_const; . | |
1745 | This also gives opportunities for subsequent | |
1746 | optimizations in the backward pass, so do it there. */ | |
1747 | if (code == PLUS && backward | |
3bb806ed R |
1748 | /* Don't do this if we can likely tie DST to SET_DEST |
1749 | of P later; we can't do this tying here if we got a | |
1750 | hard register. */ | |
1751 | && ! (dst_note && ! REG_N_CALLS_CROSSED (REGNO (dst)) | |
1752 | && single_set (p) | |
1753 | && GET_CODE (SET_DEST (single_set (p))) == REG | |
1754 | && (REGNO (SET_DEST (single_set (p))) | |
1755 | < FIRST_PSEUDO_REGISTER)) | |
dc2cb191 RH |
1756 | /* We may only emit an insn directly after P if we |
1757 | are not in the shadow of a live flags register. */ | |
1758 | && GET_MODE (p) == VOIDmode) | |
184bb750 R |
1759 | { |
1760 | search_end = q; | |
1761 | q = insn; | |
1762 | set2 = set; | |
1763 | newconst = -insn_const; | |
1764 | code = MINUS; | |
1765 | } | |
1766 | else | |
1767 | break; | |
1768 | } | |
1769 | else | |
1770 | { | |
1771 | newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const; | |
1772 | /* Reject out of range shifts. */ | |
1773 | if (code != PLUS | |
1774 | && (newconst < 0 | |
1775 | || (newconst | |
1776 | >= GET_MODE_BITSIZE (GET_MODE (SET_SRC (set2)))))) | |
1777 | break; | |
1778 | if (code == PLUS) | |
1779 | { | |
1780 | post_inc = q; | |
1781 | if (SET_DEST (set2) != src) | |
1782 | post_inc_set = set2; | |
1783 | } | |
1784 | } | |
1785 | /* We use 1 as last argument to validate_change so that all | |
1786 | changes are accepted or rejected together by apply_change_group | |
1787 | when it is called by validate_replace_rtx . */ | |
1788 | validate_change (q, &XEXP (SET_SRC (set2), 1), | |
1789 | GEN_INT (newconst), 1); | |
1790 | } | |
1ccbefce | 1791 | validate_change (insn, recog_data.operand_loc[match_number], src, 1); |
184bb750 R |
1792 | if (validate_replace_rtx (dst, src_subreg, p)) |
1793 | success = 1; | |
1794 | break; | |
1795 | } | |
1796 | ||
1797 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1798 | break; | |
1799 | if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p))) | |
1800 | { | |
2219e921 R |
1801 | /* INSN was already checked to be movable wrt. the registers that it |
1802 | sets / uses when we found no REG_DEAD note for src on it, but it | |
1803 | still might clobber the flags register. We'll have to check that | |
1804 | we won't insert it into the shadow of a live flags register when | |
1805 | we finally know where we are to move it. */ | |
184bb750 R |
1806 | overlap = p; |
1807 | src_note = find_reg_note (p, REG_DEAD, src); | |
1808 | } | |
1809 | ||
1810 | /* If we have passed a call instruction, and the pseudo-reg SRC is not | |
1811 | already live across a call, then don't perform the optimization. */ | |
1812 | if (GET_CODE (p) == CALL_INSN) | |
1813 | { | |
1814 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1815 | break; | |
1816 | ||
1817 | num_calls++; | |
1818 | ||
1819 | if (src_note) | |
1820 | s_num_calls++; | |
1821 | ||
1822 | } | |
1823 | } | |
1824 | ||
1825 | if (! success) | |
1826 | return 0; | |
1827 | ||
184bb750 R |
1828 | /* Remove the death note for DST from P. */ |
1829 | remove_note (p, dst_note); | |
1830 | if (code == MINUS) | |
1831 | { | |
1832 | post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p); | |
940da324 JL |
1833 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
1834 | && search_end | |
184bb750 R |
1835 | && try_auto_increment (search_end, post_inc, 0, src, newconst, 1)) |
1836 | post_inc = 0; | |
184bb750 R |
1837 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0); |
1838 | REG_N_SETS (REGNO (src))++; | |
184bb750 R |
1839 | REG_LIVE_LENGTH (REGNO (src))++; |
1840 | } | |
1841 | if (overlap) | |
1842 | { | |
1843 | /* The lifetime of src and dest overlap, | |
1844 | but we can change this by moving insn. */ | |
1845 | rtx pat = PATTERN (insn); | |
1846 | if (src_note) | |
1847 | remove_note (overlap, src_note); | |
1ed9faee TM |
1848 | if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1849 | && code == PLUS | |
184bb750 R |
1850 | && try_auto_increment (overlap, insn, 0, src, insn_const, 0)) |
1851 | insn = overlap; | |
1852 | else | |
184bb750 R |
1853 | { |
1854 | rtx notes = REG_NOTES (insn); | |
1855 | ||
1856 | emit_insn_after_with_line_notes (pat, PREV_INSN (p), insn); | |
1857 | PUT_CODE (insn, NOTE); | |
1858 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1859 | NOTE_SOURCE_FILE (insn) = 0; | |
1860 | /* emit_insn_after_with_line_notes has no | |
1861 | return value, so search for the new insn. */ | |
ef178af3 ZW |
1862 | insn = p; |
1863 | while (GET_RTX_CLASS (GET_CODE (insn)) != 'i' | |
1864 | || PATTERN (insn) != pat) | |
184bb750 R |
1865 | insn = PREV_INSN (insn); |
1866 | ||
1867 | REG_NOTES (insn) = notes; | |
1868 | } | |
1869 | } | |
1870 | /* Sometimes we'd generate src = const; src += n; | |
1871 | if so, replace the instruction that set src | |
1872 | in the first place. */ | |
1873 | ||
1874 | if (! overlap && (code == PLUS || code == MINUS)) | |
1875 | { | |
1876 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
a544cfd2 | 1877 | rtx q, set2 = NULL_RTX; |
184bb750 R |
1878 | int num_calls2 = 0, s_length2 = 0; |
1879 | ||
1880 | if (note && CONSTANT_P (XEXP (note, 0))) | |
1881 | { | |
1882 | for (q = PREV_INSN (insn); q; q = PREV_INSN(q)) | |
1883 | { | |
07aaad94 | 1884 | if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN) |
184bb750 R |
1885 | { |
1886 | q = 0; | |
1887 | break; | |
1888 | } | |
7bf825d2 JW |
1889 | |
1890 | /* ??? We can't scan past the end of a basic block without | |
1891 | updating the register lifetime info | |
1892 | (REG_DEAD/basic_block_live_at_start). | |
1893 | A CALL_INSN might be the last insn of a basic block, if | |
1894 | it is inside an EH region. There is no easy way to tell, | |
1895 | so we just always break when we see a CALL_INSN if | |
1896 | flag_exceptions is nonzero. */ | |
a1ecb5ca | 1897 | if (flag_exceptions && GET_CODE (q) == CALL_INSN) |
7bf825d2 JW |
1898 | { |
1899 | q = 0; | |
1900 | break; | |
1901 | } | |
1902 | ||
184bb750 R |
1903 | if (GET_RTX_CLASS (GET_CODE (q)) != 'i') |
1904 | continue; | |
1905 | s_length2++; | |
1906 | if (reg_set_p (src, q)) | |
1907 | { | |
1908 | set2 = single_set (q); | |
1909 | break; | |
1910 | } | |
1911 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
1912 | { | |
1913 | q = 0; | |
1914 | break; | |
1915 | } | |
1916 | if (GET_CODE (p) == CALL_INSN) | |
1917 | num_calls2++; | |
1918 | } | |
1919 | if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2)) | |
1920 | && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0)) | |
1921 | { | |
1922 | PUT_CODE (q, NOTE); | |
1923 | NOTE_LINE_NUMBER (q) = NOTE_INSN_DELETED; | |
1924 | NOTE_SOURCE_FILE (q) = 0; | |
1925 | REG_N_SETS (REGNO (src))--; | |
1926 | REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2; | |
184bb750 R |
1927 | REG_LIVE_LENGTH (REGNO (src)) -= s_length2; |
1928 | insn_const = 0; | |
1929 | } | |
1930 | } | |
1931 | } | |
1a56b81f | 1932 | |
cb084004 | 1933 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
940da324 | 1934 | && (code == PLUS || code == MINUS) && insn_const |
184bb750 R |
1935 | && try_auto_increment (p, insn, 0, src, insn_const, 1)) |
1936 | insn = p; | |
940da324 JL |
1937 | else if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1938 | && post_inc | |
184bb750 R |
1939 | && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0)) |
1940 | post_inc = 0; | |
184bb750 R |
1941 | /* If post_inc still prevails, try to find an |
1942 | insn where it can be used as a pre-in/decrement. | |
1943 | If code is MINUS, this was already tried. */ | |
1944 | if (post_inc && code == PLUS | |
1945 | /* Check that newconst is likely to be usable | |
1946 | in a pre-in/decrement before starting the search. */ | |
940da324 JL |
1947 | && ((HAVE_PRE_INCREMENT && newconst > 0 && newconst <= MOVE_MAX) |
1948 | || (HAVE_PRE_DECREMENT && newconst < 0 && newconst >= -MOVE_MAX)) | |
1949 | && exact_log2 (newconst)) | |
184bb750 R |
1950 | { |
1951 | rtx q, inc_dest; | |
1952 | ||
1953 | inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src; | |
51723711 | 1954 | for (q = post_inc; (q = NEXT_INSN (q)); ) |
184bb750 | 1955 | { |
07aaad94 | 1956 | if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN) |
184bb750 | 1957 | break; |
7bf825d2 JW |
1958 | |
1959 | /* ??? We can't scan past the end of a basic block without updating | |
1960 | the register lifetime info (REG_DEAD/basic_block_live_at_start). | |
1961 | A CALL_INSN might be the last insn of a basic block, if it | |
1962 | is inside an EH region. There is no easy way to tell so we | |
1963 | just always break when we see a CALL_INSN if flag_exceptions | |
1964 | is nonzero. */ | |
a1ecb5ca | 1965 | if (flag_exceptions && GET_CODE (q) == CALL_INSN) |
7bf825d2 JW |
1966 | break; |
1967 | ||
184bb750 R |
1968 | if (GET_RTX_CLASS (GET_CODE (q)) != 'i') |
1969 | continue; | |
1970 | if (src != inc_dest && (reg_overlap_mentioned_p (src, PATTERN (q)) | |
1971 | || reg_set_p (src, q))) | |
1972 | break; | |
1973 | if (reg_set_p (inc_dest, q)) | |
1974 | break; | |
1975 | if (reg_overlap_mentioned_p (inc_dest, PATTERN (q))) | |
1976 | { | |
1977 | try_auto_increment (q, post_inc, | |
1978 | post_inc_set, inc_dest, newconst, 1); | |
1979 | break; | |
1980 | } | |
1981 | } | |
1982 | } | |
184bb750 R |
1983 | /* Move the death note for DST to INSN if it is used |
1984 | there. */ | |
1985 | if (reg_overlap_mentioned_p (dst, PATTERN (insn))) | |
1986 | { | |
1987 | XEXP (dst_note, 1) = REG_NOTES (insn); | |
1988 | REG_NOTES (insn) = dst_note; | |
1989 | } | |
1990 | ||
1991 | if (src_note) | |
1992 | { | |
1993 | /* Move the death note for SRC from INSN to P. */ | |
1994 | if (! overlap) | |
1995 | remove_note (insn, src_note); | |
1996 | XEXP (src_note, 1) = REG_NOTES (p); | |
1997 | REG_NOTES (p) = src_note; | |
1998 | ||
1999 | REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls; | |
2000 | } | |
2001 | ||
2002 | REG_N_SETS (REGNO (src))++; | |
2003 | REG_N_SETS (REGNO (dst))--; | |
2004 | ||
2005 | REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls; | |
2006 | ||
2007 | REG_LIVE_LENGTH (REGNO (src)) += s_length; | |
2008 | if (REG_LIVE_LENGTH (REGNO (dst)) >= 0) | |
2009 | { | |
2010 | REG_LIVE_LENGTH (REGNO (dst)) -= length; | |
2011 | /* REG_LIVE_LENGTH is only an approximation after | |
2012 | combine if sched is not run, so make sure that we | |
2013 | still have a reasonable value. */ | |
2014 | if (REG_LIVE_LENGTH (REGNO (dst)) < 2) | |
2015 | REG_LIVE_LENGTH (REGNO (dst)) = 2; | |
2016 | } | |
184bb750 R |
2017 | if (regmove_dump_file) |
2018 | fprintf (regmove_dump_file, | |
2019 | "Fixed operand %d of insn %d matching operand %d.\n", | |
2020 | operand_number, INSN_UID (insn), match_number); | |
2021 | return 1; | |
2022 | } | |
2023 | ||
2024 | ||
18bf656f R |
2025 | /* return nonzero if X is stable and mentions no regsiters but for |
2026 | mentioning SRC or mentioning / changing DST . If in doubt, presume | |
2027 | it is unstable. | |
2028 | The rationale is that we want to check if we can move an insn easily | |
2029 | while just paying attention to SRC and DST. A register is considered | |
2030 | stable if it has the RTX_UNCHANGING_P bit set, but that would still | |
2031 | leave the burden to update REG_DEAD / REG_UNUSED notes, so we don't | |
2032 | want any registers but SRC and DST. */ | |
8c660648 | 2033 | static int |
18bf656f | 2034 | stable_and_no_regs_but_for_p (x, src, dst) |
8c660648 JL |
2035 | rtx x, src, dst; |
2036 | { | |
2037 | RTX_CODE code = GET_CODE (x); | |
2038 | switch (GET_RTX_CLASS (code)) | |
2039 | { | |
2040 | case '<': case '1': case 'c': case '2': case 'b': case '3': | |
2041 | { | |
2042 | int i; | |
6f7d635c | 2043 | const char *fmt = GET_RTX_FORMAT (code); |
8c660648 | 2044 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
18bf656f R |
2045 | if (fmt[i] == 'e' |
2046 | && ! stable_and_no_regs_but_for_p (XEXP (x, i), src, dst)) | |
8c660648 JL |
2047 | return 0; |
2048 | return 1; | |
2049 | } | |
2050 | case 'o': | |
18bf656f R |
2051 | if (code == REG) |
2052 | return x == src || x == dst; | |
2053 | /* If this is a MEM, look inside - there might be a register hidden in | |
2054 | the address of an unchanging MEM. */ | |
2055 | if (code == MEM | |
2056 | && ! stable_and_no_regs_but_for_p (XEXP (x, 0), src, dst)) | |
2057 | return 0; | |
8c660648 JL |
2058 | /* fall through */ |
2059 | default: | |
2060 | return ! rtx_unstable_p (x); | |
2061 | } | |
2062 | } | |
1e7f0a48 RH |
2063 | \f |
2064 | /* Track stack adjustments and stack memory references. Attempt to | |
2065 | reduce the number of stack adjustments by back-propogating across | |
2066 | the memory references. | |
2067 | ||
2068 | This is intended primarily for use with targets that do not define | |
2069 | ACCUMULATE_OUTGOING_ARGS. It is of significantly more value to | |
2070 | targets that define PREFERRED_STACK_BOUNDARY more aligned than | |
2071 | STACK_BOUNDARY (e.g. x86), or if not all registers can be pushed | |
2072 | (e.g. x86 fp regs) which would ordinarily have to be implemented | |
2073 | as a sub/mov pair due to restrictions in calls.c. | |
2074 | ||
2075 | Propogation stops when any of the insns that need adjusting are | |
2076 | (a) no longer valid because we've exceeded their range, (b) a | |
2077 | non-trivial push instruction, or (c) a call instruction. | |
2078 | ||
2079 | Restriction B is based on the assumption that push instructions | |
2080 | are smaller or faster. If a port really wants to remove all | |
2081 | pushes, it should have defined ACCUMULATE_OUTGOING_ARGS. The | |
2082 | one exception that is made is for an add immediately followed | |
2083 | by a push. */ | |
2084 | ||
2085 | /* This structure records stack memory references between stack adjusting | |
2086 | instructions. */ | |
2087 | ||
2088 | struct csa_memlist | |
2089 | { | |
2090 | HOST_WIDE_INT sp_offset; | |
5a97f7c2 | 2091 | rtx insn, *mem; |
1e7f0a48 RH |
2092 | struct csa_memlist *next; |
2093 | }; | |
2094 | ||
2095 | static int stack_memref_p PARAMS ((rtx)); | |
2096 | static rtx single_set_for_csa PARAMS ((rtx)); | |
2097 | static void free_csa_memlist PARAMS ((struct csa_memlist *)); | |
2098 | static struct csa_memlist *record_one_stack_memref | |
5a97f7c2 | 2099 | PARAMS ((rtx, rtx *, struct csa_memlist *)); |
1e7f0a48 RH |
2100 | static int try_apply_stack_adjustment |
2101 | PARAMS ((rtx, struct csa_memlist *, HOST_WIDE_INT, HOST_WIDE_INT)); | |
2102 | static void combine_stack_adjustments_for_block PARAMS ((basic_block)); | |
2103 | ||
2104 | ||
2105 | /* Main entry point for stack adjustment combination. */ | |
2106 | ||
2107 | void | |
2108 | combine_stack_adjustments () | |
2109 | { | |
2110 | int i; | |
2111 | ||
2112 | for (i = 0; i < n_basic_blocks; ++i) | |
2113 | combine_stack_adjustments_for_block (BASIC_BLOCK (i)); | |
2114 | } | |
2115 | ||
2116 | /* Recognize a MEM of the form (sp) or (plus sp const). */ | |
2117 | ||
2118 | static int | |
9e11785b RH |
2119 | stack_memref_p (x) |
2120 | rtx x; | |
1e7f0a48 | 2121 | { |
9e11785b RH |
2122 | if (GET_CODE (x) != MEM) |
2123 | return 0; | |
2124 | x = XEXP (x, 0); | |
2125 | ||
2126 | if (x == stack_pointer_rtx) | |
2127 | return 1; | |
2128 | if (GET_CODE (x) == PLUS | |
2129 | && XEXP (x, 0) == stack_pointer_rtx | |
2130 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2131 | return 1; | |
2132 | ||
2133 | return 0; | |
1e7f0a48 RH |
2134 | } |
2135 | ||
2136 | /* Recognize either normal single_set or the hack in i386.md for | |
2137 | tying fp and sp adjustments. */ | |
2138 | ||
2139 | static rtx | |
2140 | single_set_for_csa (insn) | |
2141 | rtx insn; | |
2142 | { | |
2143 | int i; | |
2144 | rtx tmp = single_set (insn); | |
2145 | if (tmp) | |
2146 | return tmp; | |
2147 | ||
2148 | if (GET_CODE (insn) != INSN | |
2149 | || GET_CODE (PATTERN (insn)) != PARALLEL) | |
2150 | return NULL_RTX; | |
2151 | ||
2152 | tmp = PATTERN (insn); | |
2153 | if (GET_CODE (XVECEXP (tmp, 0, 0)) != SET) | |
2154 | return NULL_RTX; | |
2155 | ||
2156 | for (i = 1; i < XVECLEN (tmp, 0); ++i) | |
2157 | { | |
2158 | rtx this = XVECEXP (tmp, 0, i); | |
2159 | ||
2160 | /* The special case is allowing a no-op set. */ | |
2161 | if (GET_CODE (this) == SET | |
2162 | && SET_SRC (this) == SET_DEST (this)) | |
2163 | ; | |
2164 | else if (GET_CODE (this) != CLOBBER | |
2165 | && GET_CODE (this) != USE) | |
2166 | return NULL_RTX; | |
2167 | } | |
2168 | ||
2169 | return XVECEXP (tmp, 0, 0); | |
2170 | } | |
2171 | ||
2172 | /* Free the list of csa_memlist nodes. */ | |
2173 | ||
2174 | static void | |
2175 | free_csa_memlist (memlist) | |
2176 | struct csa_memlist *memlist; | |
2177 | { | |
2178 | struct csa_memlist *next; | |
2179 | for (; memlist ; memlist = next) | |
2180 | { | |
2181 | next = memlist->next; | |
2182 | free (memlist); | |
2183 | } | |
2184 | } | |
2185 | ||
2186 | /* Create a new csa_memlist node from the given memory reference. | |
2187 | It is already known that the memory is stack_memref_p. */ | |
2188 | ||
2189 | static struct csa_memlist * | |
2190 | record_one_stack_memref (insn, mem, next_memlist) | |
5a97f7c2 | 2191 | rtx insn, *mem; |
1e7f0a48 RH |
2192 | struct csa_memlist *next_memlist; |
2193 | { | |
2194 | struct csa_memlist *ml; | |
2195 | ||
2196 | ml = (struct csa_memlist *) xmalloc (sizeof (*ml)); | |
2197 | ||
5a97f7c2 | 2198 | if (XEXP (*mem, 0) == stack_pointer_rtx) |
1e7f0a48 RH |
2199 | ml->sp_offset = 0; |
2200 | else | |
5a97f7c2 | 2201 | ml->sp_offset = INTVAL (XEXP (XEXP (*mem, 0), 1)); |
1e7f0a48 RH |
2202 | |
2203 | ml->insn = insn; | |
2204 | ml->mem = mem; | |
2205 | ml->next = next_memlist; | |
2206 | ||
2207 | return ml; | |
2208 | } | |
2209 | ||
2210 | /* Attempt to apply ADJUST to the stack adjusting insn INSN, as well | |
2211 | as each of the memories in MEMLIST. Return true on success. */ | |
2212 | ||
2213 | static int | |
2214 | try_apply_stack_adjustment (insn, memlist, new_adjust, delta) | |
2215 | rtx insn; | |
2216 | struct csa_memlist *memlist; | |
2217 | HOST_WIDE_INT new_adjust, delta; | |
2218 | { | |
2219 | struct csa_memlist *ml; | |
2220 | rtx set; | |
2221 | ||
2222 | /* We know INSN matches single_set_for_csa, because that's what we | |
2223 | recognized earlier. However, if INSN is not single_set, it is | |
2224 | doing double duty as a barrier for frame pointer memory accesses, | |
2225 | which we are not recording. Therefore, an adjust insn that is not | |
2226 | single_set may not have a positive delta applied. */ | |
2227 | ||
2228 | if (delta > 0 && ! single_set (insn)) | |
2229 | return 0; | |
2230 | set = single_set_for_csa (insn); | |
2231 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (new_adjust), 1); | |
2232 | ||
2233 | for (ml = memlist; ml ; ml = ml->next) | |
2234 | { | |
2235 | HOST_WIDE_INT c = ml->sp_offset - delta; | |
2236 | ||
2237 | /* Don't reference memory below the stack pointer. */ | |
2238 | if (c < 0) | |
2239 | { | |
2240 | cancel_changes (0); | |
2241 | return 0; | |
2242 | } | |
2243 | ||
5a97f7c2 JH |
2244 | validate_change (ml->insn, ml->mem, |
2245 | gen_rtx_MEM (GET_MODE (*ml->mem), | |
2246 | plus_constant (stack_pointer_rtx, c)), 1); | |
1e7f0a48 RH |
2247 | } |
2248 | ||
2249 | if (apply_change_group ()) | |
2250 | { | |
2251 | /* Succeeded. Update our knowledge of the memory references. */ | |
2252 | for (ml = memlist; ml ; ml = ml->next) | |
2253 | ml->sp_offset -= delta; | |
2254 | ||
2255 | return 1; | |
2256 | } | |
2257 | else | |
2258 | return 0; | |
2259 | } | |
2260 | ||
2261 | /* Subroutine of combine_stack_adjustments, called for each basic block. */ | |
2262 | ||
2263 | static void | |
2264 | combine_stack_adjustments_for_block (bb) | |
2265 | basic_block bb; | |
2266 | { | |
2267 | HOST_WIDE_INT last_sp_adjust = 0; | |
2268 | rtx last_sp_set = NULL_RTX; | |
2269 | struct csa_memlist *memlist = NULL; | |
2270 | rtx pending_delete; | |
2271 | rtx insn, next; | |
2272 | ||
2273 | for (insn = bb->head; ; insn = next) | |
2274 | { | |
2275 | rtx set; | |
2276 | ||
2277 | pending_delete = NULL_RTX; | |
2278 | next = NEXT_INSN (insn); | |
2279 | ||
2280 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
2281 | goto processed; | |
2282 | ||
2283 | set = single_set_for_csa (insn); | |
2284 | if (set) | |
2285 | { | |
2286 | rtx dest = SET_DEST (set); | |
2287 | rtx src = SET_SRC (set); | |
2288 | ||
2289 | /* Find constant additions to the stack pointer. */ | |
2290 | if (dest == stack_pointer_rtx | |
2291 | && GET_CODE (src) == PLUS | |
2292 | && XEXP (src, 0) == stack_pointer_rtx | |
2293 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2294 | { | |
2295 | HOST_WIDE_INT this_adjust = INTVAL (XEXP (src, 1)); | |
2296 | ||
2297 | /* If we've not seen an adjustment previously, record | |
2298 | it now and continue. */ | |
2299 | if (! last_sp_set) | |
2300 | { | |
2301 | last_sp_set = insn; | |
2302 | last_sp_adjust = this_adjust; | |
2303 | goto processed; | |
2304 | } | |
2305 | ||
2306 | /* If not all recorded memrefs can be adjusted, or the | |
2307 | adjustment is now too large for a constant addition, | |
2308 | we cannot merge the two stack adjustments. */ | |
2309 | if (! try_apply_stack_adjustment (last_sp_set, memlist, | |
2310 | last_sp_adjust + this_adjust, | |
2311 | this_adjust)) | |
2312 | { | |
2313 | free_csa_memlist (memlist); | |
2314 | memlist = NULL; | |
2315 | last_sp_set = insn; | |
2316 | last_sp_adjust = this_adjust; | |
2317 | goto processed; | |
2318 | } | |
2319 | ||
2320 | /* It worked! */ | |
2321 | pending_delete = insn; | |
2322 | last_sp_adjust += this_adjust; | |
2323 | ||
2324 | /* If, by some accident, the adjustments cancel out, | |
2325 | delete both insns and start from scratch. */ | |
2326 | if (last_sp_adjust == 0) | |
2327 | { | |
2328 | if (last_sp_set == bb->head) | |
2329 | bb->head = NEXT_INSN (last_sp_set); | |
2330 | flow_delete_insn (last_sp_set); | |
2331 | ||
2332 | free_csa_memlist (memlist); | |
2333 | memlist = NULL; | |
2334 | last_sp_set = NULL_RTX; | |
2335 | } | |
2336 | ||
2337 | goto processed; | |
2338 | } | |
2339 | ||
2340 | /* Find loads from stack memory and record them. */ | |
9e11785b RH |
2341 | if (last_sp_set && stack_memref_p (src) |
2342 | && ! reg_mentioned_p (stack_pointer_rtx, dest)) | |
1e7f0a48 | 2343 | { |
5a97f7c2 | 2344 | memlist = record_one_stack_memref (insn, &SET_SRC (set), memlist); |
1e7f0a48 RH |
2345 | goto processed; |
2346 | } | |
2347 | ||
2348 | /* Find stores to stack memory and record them. */ | |
9e11785b RH |
2349 | if (last_sp_set && stack_memref_p (dest) |
2350 | && ! reg_mentioned_p (stack_pointer_rtx, src)) | |
1e7f0a48 | 2351 | { |
5a97f7c2 JH |
2352 | memlist = record_one_stack_memref (insn, &SET_DEST (set), |
2353 | memlist); | |
1e7f0a48 RH |
2354 | goto processed; |
2355 | } | |
2356 | ||
2357 | /* Find a predecrement of exactly the previous adjustment and | |
2358 | turn it into a direct store. Obviously we can't do this if | |
2359 | there were any intervening uses of the stack pointer. */ | |
2360 | if (memlist == NULL | |
2361 | && last_sp_adjust == GET_MODE_SIZE (GET_MODE (dest)) | |
2362 | && GET_CODE (dest) == MEM | |
2363 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
2364 | && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx | |
9e11785b | 2365 | && ! reg_mentioned_p (stack_pointer_rtx, src) |
5d64361b | 2366 | && memory_address_p (GET_MODE (dest), stack_pointer_rtx) |
1e7f0a48 RH |
2367 | && validate_change (insn, &SET_DEST (set), |
2368 | change_address (dest, VOIDmode, | |
2369 | stack_pointer_rtx), 0)) | |
2370 | { | |
2371 | if (last_sp_set == bb->head) | |
2372 | bb->head = NEXT_INSN (last_sp_set); | |
2373 | flow_delete_insn (last_sp_set); | |
2374 | ||
2375 | free_csa_memlist (memlist); | |
2376 | memlist = NULL; | |
2377 | last_sp_set = NULL_RTX; | |
2378 | last_sp_adjust = 0; | |
2379 | goto processed; | |
2380 | } | |
2381 | } | |
2382 | ||
2383 | /* Otherwise, we were not able to process the instruction. | |
2384 | Do not continue collecting data across such a one. */ | |
2385 | if (last_sp_set | |
2386 | && (GET_CODE (insn) == CALL_INSN | |
2387 | || reg_mentioned_p (stack_pointer_rtx, PATTERN (insn)))) | |
2388 | { | |
2389 | free_csa_memlist (memlist); | |
2390 | memlist = NULL; | |
2391 | last_sp_set = NULL_RTX; | |
2392 | last_sp_adjust = 0; | |
2393 | } | |
2394 | ||
2395 | processed: | |
2396 | if (insn == bb->end) | |
2397 | break; | |
2398 | ||
2399 | if (pending_delete) | |
2400 | flow_delete_insn (pending_delete); | |
2401 | } | |
2402 | ||
2403 | if (pending_delete) | |
2404 | { | |
2405 | bb->end = PREV_INSN (pending_delete); | |
2406 | flow_delete_insn (pending_delete); | |
2407 | } | |
2408 | } |