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Commit | Line | Data |
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8c660648 | 1 | /* Move registers around to reduce number of move instructions needed. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
d9221e01 | 3 | 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
8c660648 | 4 | |
1322177d | 5 | This file is part of GCC. |
8c660648 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
8c660648 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
8c660648 JL |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
8c660648 JL |
21 | |
22 | ||
23 | /* This module looks for cases where matching constraints would force | |
24 | an instruction to need a reload, and this reload would be a register | |
25 | to register move. It then attempts to change the registers used by the | |
26 | instruction to avoid the move instruction. */ | |
27 | ||
28 | #include "config.h" | |
670ee920 | 29 | #include "system.h" |
4977bab6 ZW |
30 | #include "coretypes.h" |
31 | #include "tm.h" | |
789f983a | 32 | #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ |
6baf1cc8 | 33 | #include "tm_p.h" |
8c660648 JL |
34 | #include "insn-config.h" |
35 | #include "recog.h" | |
36 | #include "output.h" | |
8c660648 | 37 | #include "regs.h" |
184bb750 R |
38 | #include "hard-reg-set.h" |
39 | #include "flags.h" | |
49ad7cfa | 40 | #include "function.h" |
184bb750 | 41 | #include "expr.h" |
ddc8bed2 | 42 | #include "basic-block.h" |
1a5428f7 | 43 | #include "except.h" |
2e107e9e | 44 | #include "toplev.h" |
8461e984 | 45 | #include "reload.h" |
184bb750 | 46 | |
595c2290 JH |
47 | |
48 | /* Turn STACK_GROWS_DOWNWARD into a boolean. */ | |
49 | #ifdef STACK_GROWS_DOWNWARD | |
50 | #undef STACK_GROWS_DOWNWARD | |
51 | #define STACK_GROWS_DOWNWARD 1 | |
52 | #else | |
53 | #define STACK_GROWS_DOWNWARD 0 | |
54 | #endif | |
55 | ||
0c20a65f AJ |
56 | static int perhaps_ends_bb_p (rtx); |
57 | static int optimize_reg_copy_1 (rtx, rtx, rtx); | |
58 | static void optimize_reg_copy_2 (rtx, rtx, rtx); | |
59 | static void optimize_reg_copy_3 (rtx, rtx, rtx); | |
60 | static void copy_src_to_dest (rtx, rtx, rtx, int); | |
ddc8bed2 | 61 | static int *regmove_bb_head; |
8c660648 | 62 | |
184bb750 R |
63 | struct match { |
64 | int with[MAX_RECOG_OPERANDS]; | |
65 | enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS]; | |
66 | int commutative[MAX_RECOG_OPERANDS]; | |
67 | int early_clobber[MAX_RECOG_OPERANDS]; | |
68 | }; | |
69 | ||
0c20a65f AJ |
70 | static rtx discover_flags_reg (void); |
71 | static void mark_flags_life_zones (rtx); | |
72 | static void flags_set_1 (rtx, rtx, void *); | |
73 | ||
74 | static int try_auto_increment (rtx, rtx, rtx, rtx, HOST_WIDE_INT, int); | |
75 | static int find_matches (rtx, struct match *); | |
76 | static void replace_in_call_usage (rtx *, unsigned int, rtx, rtx); | |
77 | static int fixup_match_1 (rtx, rtx, rtx, rtx, rtx, int, int, int, FILE *); | |
78 | static int reg_is_remote_constant_p (rtx, rtx, rtx); | |
79 | static int stable_and_no_regs_but_for_p (rtx, rtx, rtx); | |
80 | static int regclass_compatible_p (int, int); | |
81 | static int replacement_quality (rtx); | |
82 | static int fixup_match_2 (rtx, rtx, rtx, rtx, FILE *); | |
8c660648 | 83 | |
40f03658 | 84 | /* Return nonzero if registers with CLASS1 and CLASS2 can be merged without |
3bb806ed R |
85 | causing too much register allocation problems. */ |
86 | static int | |
0c20a65f | 87 | regclass_compatible_p (int class0, int class1) |
3bb806ed R |
88 | { |
89 | return (class0 == class1 | |
90 | || (reg_class_subset_p (class0, class1) | |
91 | && ! CLASS_LIKELY_SPILLED_P (class0)) | |
92 | || (reg_class_subset_p (class1, class0) | |
93 | && ! CLASS_LIKELY_SPILLED_P (class1))); | |
94 | } | |
95 | ||
8c660648 JL |
96 | /* INC_INSN is an instruction that adds INCREMENT to REG. |
97 | Try to fold INC_INSN as a post/pre in/decrement into INSN. | |
98 | Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src. | |
99 | Return nonzero for success. */ | |
100 | static int | |
0c20a65f AJ |
101 | try_auto_increment (rtx insn, rtx inc_insn, rtx inc_insn_set, rtx reg, |
102 | HOST_WIDE_INT increment, int pre) | |
8c660648 JL |
103 | { |
104 | enum rtx_code inc_code; | |
105 | ||
106 | rtx pset = single_set (insn); | |
107 | if (pset) | |
108 | { | |
109 | /* Can't use the size of SET_SRC, we might have something like | |
110 | (sign_extend:SI (mem:QI ... */ | |
111 | rtx use = find_use_as_address (pset, reg, 0); | |
60e8b9f0 | 112 | if (use != 0 && use != (rtx) (size_t) 1) |
8c660648 JL |
113 | { |
114 | int size = GET_MODE_SIZE (GET_MODE (use)); | |
115 | if (0 | |
940da324 JL |
116 | || (HAVE_POST_INCREMENT |
117 | && pre == 0 && (inc_code = POST_INC, increment == size)) | |
118 | || (HAVE_PRE_INCREMENT | |
119 | && pre == 1 && (inc_code = PRE_INC, increment == size)) | |
120 | || (HAVE_POST_DECREMENT | |
121 | && pre == 0 && (inc_code = POST_DEC, increment == -size)) | |
122 | || (HAVE_PRE_DECREMENT | |
123 | && pre == 1 && (inc_code = PRE_DEC, increment == -size)) | |
184bb750 R |
124 | ) |
125 | { | |
126 | if (inc_insn_set) | |
127 | validate_change | |
174fa2c4 | 128 | (inc_insn, |
184bb750 | 129 | &SET_SRC (inc_insn_set), |
8c660648 | 130 | XEXP (SET_SRC (inc_insn_set), 0), 1); |
184bb750 | 131 | validate_change (insn, &XEXP (use, 0), |
38a448ca | 132 | gen_rtx_fmt_e (inc_code, Pmode, reg), 1); |
184bb750 R |
133 | if (apply_change_group ()) |
134 | { | |
2f33c635 HB |
135 | /* If there is a REG_DEAD note on this insn, we must |
136 | change this not to REG_UNUSED meaning that the register | |
137 | is set, but the value is dead. Failure to do so will | |
138 | result in a sched1 abort -- when it recomputes lifetime | |
139 | information, the number of REG_DEAD notes will have | |
140 | changed. */ | |
141 | rtx note = find_reg_note (insn, REG_DEAD, reg); | |
142 | if (note) | |
143 | PUT_MODE (note, REG_UNUSED); | |
144 | ||
184bb750 | 145 | REG_NOTES (insn) |
38a448ca RH |
146 | = gen_rtx_EXPR_LIST (REG_INC, |
147 | reg, REG_NOTES (insn)); | |
184bb750 | 148 | if (! inc_insn_set) |
ca6c03ca | 149 | delete_insn (inc_insn); |
8c660648 | 150 | return 1; |
184bb750 R |
151 | } |
152 | } | |
153 | } | |
154 | } | |
155 | return 0; | |
156 | } | |
dc2cb191 RH |
157 | \f |
158 | /* Determine if the pattern generated by add_optab has a clobber, | |
159 | such as might be issued for a flags hard register. To make the | |
160 | code elsewhere simpler, we handle cc0 in this same framework. | |
161 | ||
162 | Return the register if one was discovered. Return NULL_RTX if | |
163 | if no flags were found. Return pc_rtx if we got confused. */ | |
164 | ||
165 | static rtx | |
0c20a65f | 166 | discover_flags_reg (void) |
dc2cb191 RH |
167 | { |
168 | rtx tmp; | |
cd4b3546 | 169 | tmp = gen_rtx_REG (word_mode, 10000); |
60c81c89 | 170 | tmp = gen_add3_insn (tmp, tmp, const2_rtx); |
dc2cb191 | 171 | |
174fa2c4 | 172 | /* If we get something that isn't a simple set, or a |
dc2cb191 RH |
173 | [(set ..) (clobber ..)], this whole function will go wrong. */ |
174 | if (GET_CODE (tmp) == SET) | |
175 | return NULL_RTX; | |
176 | else if (GET_CODE (tmp) == PARALLEL) | |
177 | { | |
178 | int found; | |
179 | ||
180 | if (XVECLEN (tmp, 0) != 2) | |
181 | return pc_rtx; | |
182 | tmp = XVECEXP (tmp, 0, 1); | |
183 | if (GET_CODE (tmp) != CLOBBER) | |
184 | return pc_rtx; | |
185 | tmp = XEXP (tmp, 0); | |
186 | ||
187 | /* Don't do anything foolish if the md wanted to clobber a | |
188 | scratch or something. We only care about hard regs. | |
189 | Moreover we don't like the notion of subregs of hard regs. */ | |
190 | if (GET_CODE (tmp) == SUBREG | |
191 | && GET_CODE (SUBREG_REG (tmp)) == REG | |
192 | && REGNO (SUBREG_REG (tmp)) < FIRST_PSEUDO_REGISTER) | |
193 | return pc_rtx; | |
194 | found = (GET_CODE (tmp) == REG && REGNO (tmp) < FIRST_PSEUDO_REGISTER); | |
195 | ||
dc2cb191 | 196 | return (found ? tmp : NULL_RTX); |
dc2cb191 RH |
197 | } |
198 | ||
199 | return pc_rtx; | |
200 | } | |
201 | ||
202 | /* It is a tedious task identifying when the flags register is live and | |
203 | when it is safe to optimize. Since we process the instruction stream | |
204 | multiple times, locate and record these live zones by marking the | |
174fa2c4 | 205 | mode of the instructions -- |
dc2cb191 RH |
206 | |
207 | QImode is used on the instruction at which the flags becomes live. | |
208 | ||
209 | HImode is used within the range (exclusive) that the flags are | |
210 | live. Thus the user of the flags is not marked. | |
211 | ||
212 | All other instructions are cleared to VOIDmode. */ | |
213 | ||
214 | /* Used to communicate with flags_set_1. */ | |
215 | static rtx flags_set_1_rtx; | |
216 | static int flags_set_1_set; | |
217 | ||
218 | static void | |
0c20a65f | 219 | mark_flags_life_zones (rtx flags) |
dc2cb191 RH |
220 | { |
221 | int flags_regno; | |
222 | int flags_nregs; | |
e0082a72 | 223 | basic_block block; |
dc2cb191 | 224 | |
e7f5b971 RH |
225 | #ifdef HAVE_cc0 |
226 | /* If we found a flags register on a cc0 host, bail. */ | |
227 | if (flags == NULL_RTX) | |
228 | flags = cc0_rtx; | |
229 | else if (flags != cc0_rtx) | |
230 | flags = pc_rtx; | |
231 | #endif | |
174fa2c4 | 232 | |
dc2cb191 RH |
233 | /* Simple cases first: if no flags, clear all modes. If confusing, |
234 | mark the entire function as being in a flags shadow. */ | |
235 | if (flags == NULL_RTX || flags == pc_rtx) | |
236 | { | |
237 | enum machine_mode mode = (flags ? HImode : VOIDmode); | |
238 | rtx insn; | |
8e2e89f7 | 239 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
dc2cb191 RH |
240 | PUT_MODE (insn, mode); |
241 | return; | |
242 | } | |
243 | ||
244 | #ifdef HAVE_cc0 | |
245 | flags_regno = -1; | |
246 | flags_nregs = 1; | |
247 | #else | |
248 | flags_regno = REGNO (flags); | |
66fd46b6 | 249 | flags_nregs = hard_regno_nregs[flags_regno][GET_MODE (flags)]; |
dc2cb191 RH |
250 | #endif |
251 | flags_set_1_rtx = flags; | |
184bb750 | 252 | |
dc2cb191 | 253 | /* Process each basic block. */ |
e0082a72 | 254 | FOR_EACH_BB_REVERSE (block) |
dc2cb191 RH |
255 | { |
256 | rtx insn, end; | |
257 | int live; | |
258 | ||
a813c111 SB |
259 | insn = BB_HEAD (block); |
260 | end = BB_END (block); | |
dc2cb191 RH |
261 | |
262 | /* Look out for the (unlikely) case of flags being live across | |
263 | basic block boundaries. */ | |
264 | live = 0; | |
265 | #ifndef HAVE_cc0 | |
266 | { | |
267 | int i; | |
268 | for (i = 0; i < flags_nregs; ++i) | |
e0082a72 | 269 | live |= REGNO_REG_SET_P (block->global_live_at_start, |
dc2cb191 RH |
270 | flags_regno + i); |
271 | } | |
272 | #endif | |
273 | ||
274 | while (1) | |
275 | { | |
276 | /* Process liveness in reverse order of importance -- | |
277 | alive, death, birth. This lets more important info | |
278 | overwrite the mode of lesser info. */ | |
279 | ||
2c3c49de | 280 | if (INSN_P (insn)) |
dc2cb191 RH |
281 | { |
282 | #ifdef HAVE_cc0 | |
283 | /* In the cc0 case, death is not marked in reg notes, | |
284 | but is instead the mere use of cc0 when it is alive. */ | |
285 | if (live && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
286 | live = 0; | |
287 | #else | |
288 | /* In the hard reg case, we watch death notes. */ | |
289 | if (live && find_regno_note (insn, REG_DEAD, flags_regno)) | |
290 | live = 0; | |
291 | #endif | |
292 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
293 | ||
d1a6adeb | 294 | /* In either case, birth is denoted simply by its presence |
dc2cb191 RH |
295 | as the destination of a set. */ |
296 | flags_set_1_set = 0; | |
84832317 | 297 | note_stores (PATTERN (insn), flags_set_1, NULL); |
dc2cb191 RH |
298 | if (flags_set_1_set) |
299 | { | |
300 | live = 1; | |
301 | PUT_MODE (insn, QImode); | |
302 | } | |
303 | } | |
304 | else | |
305 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
306 | ||
307 | if (insn == end) | |
308 | break; | |
309 | insn = NEXT_INSN (insn); | |
310 | } | |
311 | } | |
312 | } | |
313 | ||
314 | /* A subroutine of mark_flags_life_zones, called through note_stores. */ | |
315 | ||
316 | static void | |
0c20a65f | 317 | flags_set_1 (rtx x, rtx pat, void *data ATTRIBUTE_UNUSED) |
dc2cb191 RH |
318 | { |
319 | if (GET_CODE (pat) == SET | |
320 | && reg_overlap_mentioned_p (x, flags_set_1_rtx)) | |
321 | flags_set_1_set = 1; | |
322 | } | |
323 | \f | |
184bb750 R |
324 | static int *regno_src_regno; |
325 | ||
326 | /* Indicate how good a choice REG (which appears as a source) is to replace | |
327 | a destination register with. The higher the returned value, the better | |
328 | the choice. The main objective is to avoid using a register that is | |
329 | a candidate for tying to a hard register, since the output might in | |
330 | turn be a candidate to be tied to a different hard register. */ | |
95d75019 | 331 | static int |
0c20a65f | 332 | replacement_quality (rtx reg) |
184bb750 R |
333 | { |
334 | int src_regno; | |
335 | ||
336 | /* Bad if this isn't a register at all. */ | |
337 | if (GET_CODE (reg) != REG) | |
338 | return 0; | |
339 | ||
340 | /* If this register is not meant to get a hard register, | |
341 | it is a poor choice. */ | |
342 | if (REG_LIVE_LENGTH (REGNO (reg)) < 0) | |
343 | return 0; | |
344 | ||
345 | src_regno = regno_src_regno[REGNO (reg)]; | |
346 | ||
347 | /* If it was not copied from another register, it is fine. */ | |
348 | if (src_regno < 0) | |
349 | return 3; | |
350 | ||
351 | /* Copied from a hard register? */ | |
352 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
353 | return 1; | |
354 | ||
355 | /* Copied from a pseudo register - not as bad as from a hard register, | |
356 | yet still cumbersome, since the register live length will be lengthened | |
357 | when the registers get tied. */ | |
358 | return 2; | |
359 | } | |
a1c1fdd0 RK |
360 | \f |
361 | /* Return 1 if INSN might end a basic block. */ | |
362 | ||
5671bf27 | 363 | static int perhaps_ends_bb_p (rtx insn) |
a1c1fdd0 RK |
364 | { |
365 | switch (GET_CODE (insn)) | |
366 | { | |
367 | case CODE_LABEL: | |
368 | case JUMP_INSN: | |
369 | /* These always end a basic block. */ | |
370 | return 1; | |
184bb750 | 371 | |
a1c1fdd0 RK |
372 | case CALL_INSN: |
373 | /* A CALL_INSN might be the last insn of a basic block, if it is inside | |
374 | an EH region or if there are nonlocal gotos. Note that this test is | |
375 | very conservative. */ | |
a614d82e RH |
376 | if (nonlocal_goto_handler_labels) |
377 | return 1; | |
5d3cc252 | 378 | /* Fall through. */ |
a1c1fdd0 | 379 | default: |
a614d82e | 380 | return can_throw_internal (insn); |
a1c1fdd0 RK |
381 | } |
382 | } | |
383 | \f | |
1230327b R |
384 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die |
385 | in INSN. | |
386 | ||
387 | Search forward to see if SRC dies before either it or DEST is modified, | |
388 | but don't scan past the end of a basic block. If so, we can replace SRC | |
174fa2c4 | 389 | with DEST and let SRC die in INSN. |
1230327b R |
390 | |
391 | This will reduce the number of registers live in that range and may enable | |
392 | DEST to be tied to SRC, thus often saving one register in addition to a | |
393 | register-register copy. */ | |
394 | ||
395 | static int | |
0c20a65f | 396 | optimize_reg_copy_1 (rtx insn, rtx dest, rtx src) |
1230327b R |
397 | { |
398 | rtx p, q; | |
399 | rtx note; | |
400 | rtx dest_death = 0; | |
401 | int sregno = REGNO (src); | |
402 | int dregno = REGNO (dest); | |
403 | ||
dc297297 | 404 | /* We don't want to mess with hard regs if register classes are small. */ |
1230327b R |
405 | if (sregno == dregno |
406 | || (SMALL_REGISTER_CLASSES | |
407 | && (sregno < FIRST_PSEUDO_REGISTER | |
408 | || dregno < FIRST_PSEUDO_REGISTER)) | |
409 | /* We don't see all updates to SP if they are in an auto-inc memory | |
410 | reference, so we must disallow this optimization on them. */ | |
411 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) | |
412 | return 0; | |
413 | ||
414 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
415 | { | |
7bf825d2 | 416 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
417 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
418 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 419 | break; |
a1c1fdd0 | 420 | else if (! INSN_P (p)) |
1230327b R |
421 | continue; |
422 | ||
423 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
51928907 HPN |
424 | /* If SRC is an asm-declared register, it must not be replaced |
425 | in any asm. Unfortunately, the REG_EXPR tree for the asm | |
426 | variable may be absent in the SRC rtx, so we can't check the | |
427 | actual register declaration easily (the asm operand will have | |
428 | it, though). To avoid complicating the test for a rare case, | |
429 | we just don't perform register replacement for a hard reg | |
430 | mentioned in an asm. */ | |
431 | || (sregno < FIRST_PSEUDO_REGISTER | |
432 | && asm_noperands (PATTERN (p)) >= 0 | |
433 | && reg_overlap_mentioned_p (src, PATTERN (p))) | |
1230327b R |
434 | /* Don't change a USE of a register. */ |
435 | || (GET_CODE (PATTERN (p)) == USE | |
436 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
437 | break; | |
438 | ||
439 | /* See if all of SRC dies in P. This test is slightly more | |
440 | conservative than it needs to be. */ | |
441 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 | |
442 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
443 | { | |
444 | int failed = 0; | |
1230327b | 445 | int d_length = 0; |
89098dc1 | 446 | int s_length = 0; |
1230327b | 447 | int d_n_calls = 0; |
89098dc1 | 448 | int s_n_calls = 0; |
1230327b R |
449 | |
450 | /* We can do the optimization. Scan forward from INSN again, | |
451 | replacing regs as we go. Set FAILED if a replacement can't | |
452 | be done. In that case, we can't move the death note for SRC. | |
453 | This should be rare. */ | |
454 | ||
455 | /* Set to stop at next insn. */ | |
456 | for (q = next_real_insn (insn); | |
457 | q != next_real_insn (p); | |
458 | q = next_real_insn (q)) | |
459 | { | |
460 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
461 | { | |
462 | /* If SRC is a hard register, we might miss some | |
463 | overlapping registers with validate_replace_rtx, | |
464 | so we would have to undo it. We can't if DEST is | |
465 | present in the insn, so fail in that combination | |
466 | of cases. */ | |
467 | if (sregno < FIRST_PSEUDO_REGISTER | |
468 | && reg_mentioned_p (dest, PATTERN (q))) | |
469 | failed = 1; | |
470 | ||
471 | /* Replace all uses and make sure that the register | |
472 | isn't still present. */ | |
473 | else if (validate_replace_rtx (src, dest, q) | |
474 | && (sregno >= FIRST_PSEUDO_REGISTER | |
475 | || ! reg_overlap_mentioned_p (src, | |
476 | PATTERN (q)))) | |
1b7c4a37 | 477 | ; |
1230327b R |
478 | else |
479 | { | |
480 | validate_replace_rtx (dest, src, q); | |
481 | failed = 1; | |
482 | } | |
483 | } | |
484 | ||
89098dc1 JL |
485 | /* For SREGNO, count the total number of insns scanned. |
486 | For DREGNO, count the total number of insns scanned after | |
487 | passing the death note for DREGNO. */ | |
488 | s_length++; | |
1230327b R |
489 | if (dest_death) |
490 | d_length++; | |
491 | ||
492 | /* If the insn in which SRC dies is a CALL_INSN, don't count it | |
493 | as a call that has been crossed. Otherwise, count it. */ | |
494 | if (q != p && GET_CODE (q) == CALL_INSN) | |
495 | { | |
89098dc1 JL |
496 | /* Similarly, total calls for SREGNO, total calls beyond |
497 | the death note for DREGNO. */ | |
498 | s_n_calls++; | |
1230327b R |
499 | if (dest_death) |
500 | d_n_calls++; | |
501 | } | |
502 | ||
503 | /* If DEST dies here, remove the death note and save it for | |
504 | later. Make sure ALL of DEST dies here; again, this is | |
505 | overly conservative. */ | |
506 | if (dest_death == 0 | |
507 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0) | |
508 | { | |
509 | if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest)) | |
510 | failed = 1, dest_death = 0; | |
511 | else | |
512 | remove_note (q, dest_death); | |
513 | } | |
514 | } | |
515 | ||
516 | if (! failed) | |
517 | { | |
89098dc1 JL |
518 | /* These counters need to be updated if and only if we are |
519 | going to move the REG_DEAD note. */ | |
1230327b R |
520 | if (sregno >= FIRST_PSEUDO_REGISTER) |
521 | { | |
522 | if (REG_LIVE_LENGTH (sregno) >= 0) | |
523 | { | |
89098dc1 | 524 | REG_LIVE_LENGTH (sregno) -= s_length; |
1230327b R |
525 | /* REG_LIVE_LENGTH is only an approximation after |
526 | combine if sched is not run, so make sure that we | |
527 | still have a reasonable value. */ | |
528 | if (REG_LIVE_LENGTH (sregno) < 2) | |
529 | REG_LIVE_LENGTH (sregno) = 2; | |
530 | } | |
531 | ||
89098dc1 | 532 | REG_N_CALLS_CROSSED (sregno) -= s_n_calls; |
1230327b R |
533 | } |
534 | ||
535 | /* Move death note of SRC from P to INSN. */ | |
536 | remove_note (p, note); | |
537 | XEXP (note, 1) = REG_NOTES (insn); | |
538 | REG_NOTES (insn) = note; | |
539 | } | |
540 | ||
124d535f JW |
541 | /* DEST is also dead if INSN has a REG_UNUSED note for DEST. */ |
542 | if (! dest_death | |
543 | && (dest_death = find_regno_note (insn, REG_UNUSED, dregno))) | |
544 | { | |
545 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
546 | remove_note (insn, dest_death); | |
547 | } | |
548 | ||
1230327b R |
549 | /* Put death note of DEST on P if we saw it die. */ |
550 | if (dest_death) | |
551 | { | |
552 | XEXP (dest_death, 1) = REG_NOTES (p); | |
553 | REG_NOTES (p) = dest_death; | |
89098dc1 JL |
554 | |
555 | if (dregno >= FIRST_PSEUDO_REGISTER) | |
556 | { | |
557 | /* If and only if we are moving the death note for DREGNO, | |
558 | then we need to update its counters. */ | |
559 | if (REG_LIVE_LENGTH (dregno) >= 0) | |
560 | REG_LIVE_LENGTH (dregno) += d_length; | |
561 | REG_N_CALLS_CROSSED (dregno) += d_n_calls; | |
562 | } | |
1230327b R |
563 | } |
564 | ||
565 | return ! failed; | |
566 | } | |
567 | ||
568 | /* If SRC is a hard register which is set or killed in some other | |
569 | way, we can't do this optimization. */ | |
570 | else if (sregno < FIRST_PSEUDO_REGISTER | |
571 | && dead_or_set_p (p, src)) | |
572 | break; | |
573 | } | |
574 | return 0; | |
575 | } | |
576 | \f | |
577 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have | |
578 | a sequence of insns that modify DEST followed by an insn that sets | |
579 | SRC to DEST in which DEST dies, with no prior modification of DEST. | |
580 | (There is no need to check if the insns in between actually modify | |
581 | DEST. We should not have cases where DEST is not modified, but | |
582 | the optimization is safe if no such modification is detected.) | |
583 | In that case, we can replace all uses of DEST, starting with INSN and | |
584 | ending with the set of SRC to DEST, with SRC. We do not do this | |
585 | optimization if a CALL_INSN is crossed unless SRC already crosses a | |
586 | call or if DEST dies before the copy back to SRC. | |
587 | ||
588 | It is assumed that DEST and SRC are pseudos; it is too complicated to do | |
589 | this for hard registers since the substitutions we may make might fail. */ | |
590 | ||
591 | static void | |
0c20a65f | 592 | optimize_reg_copy_2 (rtx insn, rtx dest, rtx src) |
1230327b R |
593 | { |
594 | rtx p, q; | |
595 | rtx set; | |
596 | int sregno = REGNO (src); | |
597 | int dregno = REGNO (dest); | |
598 | ||
599 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
600 | { | |
7bf825d2 | 601 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
602 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
603 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 604 | break; |
a1c1fdd0 | 605 | else if (! INSN_P (p)) |
1230327b R |
606 | continue; |
607 | ||
608 | set = single_set (p); | |
609 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src | |
610 | && find_reg_note (p, REG_DEAD, dest)) | |
611 | { | |
612 | /* We can do the optimization. Scan forward from INSN again, | |
613 | replacing regs as we go. */ | |
614 | ||
615 | /* Set to stop at next insn. */ | |
616 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) | |
2c3c49de | 617 | if (INSN_P (q)) |
1230327b R |
618 | { |
619 | if (reg_mentioned_p (dest, PATTERN (q))) | |
1b7c4a37 | 620 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); |
1230327b R |
621 | |
622 | ||
623 | if (GET_CODE (q) == CALL_INSN) | |
624 | { | |
625 | REG_N_CALLS_CROSSED (dregno)--; | |
626 | REG_N_CALLS_CROSSED (sregno)++; | |
627 | } | |
628 | } | |
629 | ||
630 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); | |
631 | REG_N_DEATHS (dregno)--; | |
632 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); | |
633 | REG_N_DEATHS (sregno)--; | |
634 | return; | |
635 | } | |
636 | ||
637 | if (reg_set_p (src, p) | |
638 | || find_reg_note (p, REG_DEAD, dest) | |
639 | || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0)) | |
640 | break; | |
641 | } | |
642 | } | |
184bb750 R |
643 | /* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST. |
644 | Look if SRC dies there, and if it is only set once, by loading | |
3d042e77 | 645 | it from memory. If so, try to incorporate the zero/sign extension |
184bb750 R |
646 | into the memory read, change SRC to the mode of DEST, and alter |
647 | the remaining accesses to use the appropriate SUBREG. This allows | |
648 | SRC and DEST to be tied later. */ | |
649 | static void | |
0c20a65f | 650 | optimize_reg_copy_3 (rtx insn, rtx dest, rtx src) |
184bb750 R |
651 | { |
652 | rtx src_reg = XEXP (src, 0); | |
653 | int src_no = REGNO (src_reg); | |
654 | int dst_no = REGNO (dest); | |
655 | rtx p, set, subreg; | |
656 | enum machine_mode old_mode; | |
657 | ||
658 | if (src_no < FIRST_PSEUDO_REGISTER | |
659 | || dst_no < FIRST_PSEUDO_REGISTER | |
660 | || ! find_reg_note (insn, REG_DEAD, src_reg) | |
6d80a854 | 661 | || REG_N_DEATHS (src_no) != 1 |
184bb750 R |
662 | || REG_N_SETS (src_no) != 1) |
663 | return; | |
9c07e479 | 664 | for (p = PREV_INSN (insn); p && ! reg_set_p (src_reg, p); p = PREV_INSN (p)) |
a1c1fdd0 RK |
665 | /* ??? We can't scan past the end of a basic block without updating |
666 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ | |
667 | if (perhaps_ends_bb_p (p)) | |
668 | break; | |
7bf825d2 | 669 | |
9c07e479 BK |
670 | if (! p) |
671 | return; | |
672 | ||
184bb750 R |
673 | if (! (set = single_set (p)) |
674 | || GET_CODE (SET_SRC (set)) != MEM | |
4fb3cbd7 BS |
675 | /* If there's a REG_EQUIV note, this must be an insn that loads an |
676 | argument. Prefer keeping the note over doing this optimization. */ | |
677 | || find_reg_note (p, REG_EQUIV, NULL_RTX) | |
184bb750 R |
678 | || SET_DEST (set) != src_reg) |
679 | return; | |
937e37cc | 680 | |
14b493d6 | 681 | /* Be conservative: although this optimization is also valid for |
972b320c R |
682 | volatile memory references, that could cause trouble in later passes. */ |
683 | if (MEM_VOLATILE_P (SET_SRC (set))) | |
684 | return; | |
685 | ||
937e37cc JL |
686 | /* Do not use a SUBREG to truncate from one mode to another if truncation |
687 | is not a nop. */ | |
688 | if (GET_MODE_BITSIZE (GET_MODE (src_reg)) <= GET_MODE_BITSIZE (GET_MODE (src)) | |
689 | && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src)), | |
690 | GET_MODE_BITSIZE (GET_MODE (src_reg)))) | |
691 | return; | |
692 | ||
184bb750 R |
693 | old_mode = GET_MODE (src_reg); |
694 | PUT_MODE (src_reg, GET_MODE (src)); | |
695 | XEXP (src, 0) = SET_SRC (set); | |
e757da5e JL |
696 | |
697 | /* Include this change in the group so that it's easily undone if | |
698 | one of the changes in the group is invalid. */ | |
699 | validate_change (p, &SET_SRC (set), src, 1); | |
700 | ||
701 | /* Now walk forward making additional replacements. We want to be able | |
702 | to undo all the changes if a later substitution fails. */ | |
ddef6bc7 | 703 | subreg = gen_lowpart_SUBREG (old_mode, src_reg); |
184bb750 R |
704 | while (p = NEXT_INSN (p), p != insn) |
705 | { | |
2c3c49de | 706 | if (! INSN_P (p)) |
184bb750 | 707 | continue; |
e757da5e | 708 | |
2067c116 | 709 | /* Make a tentative change. */ |
e757da5e JL |
710 | validate_replace_rtx_group (src_reg, subreg, p); |
711 | } | |
712 | ||
713 | validate_replace_rtx_group (src, src_reg, insn); | |
714 | ||
715 | /* Now see if all the changes are valid. */ | |
716 | if (! apply_change_group ()) | |
717 | { | |
718 | /* One or more changes were no good. Back out everything. */ | |
719 | PUT_MODE (src_reg, old_mode); | |
720 | XEXP (src, 0) = src_reg; | |
184bb750 | 721 | } |
4fb3cbd7 BS |
722 | else |
723 | { | |
724 | rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); | |
725 | if (note) | |
726 | remove_note (p, note); | |
727 | } | |
184bb750 R |
728 | } |
729 | ||
ddc8bed2 MM |
730 | \f |
731 | /* If we were not able to update the users of src to use dest directly, try | |
732 | instead moving the value to dest directly before the operation. */ | |
733 | ||
cab634f2 | 734 | static void |
0c20a65f | 735 | copy_src_to_dest (rtx insn, rtx src, rtx dest, int old_max_uid) |
ddc8bed2 MM |
736 | { |
737 | rtx seq; | |
738 | rtx link; | |
739 | rtx next; | |
740 | rtx set; | |
741 | rtx move_insn; | |
742 | rtx *p_insn_notes; | |
743 | rtx *p_move_notes; | |
ddc8bed2 MM |
744 | int src_regno; |
745 | int dest_regno; | |
746 | int bb; | |
747 | int insn_uid; | |
748 | int move_uid; | |
749 | ||
750 | /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant | |
751 | or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is | |
752 | parameter when there is no frame pointer that is not allocated a register. | |
753 | For now, we just reject them, rather than incrementing the live length. */ | |
754 | ||
3ac3da71 MM |
755 | if (GET_CODE (src) == REG |
756 | && REG_LIVE_LENGTH (REGNO (src)) > 0 | |
757 | && GET_CODE (dest) == REG | |
40546a78 | 758 | && !RTX_UNCHANGING_P (dest) |
3ac3da71 | 759 | && REG_LIVE_LENGTH (REGNO (dest)) > 0 |
ddc8bed2 | 760 | && (set = single_set (insn)) != NULL_RTX |
9d2106a4 R |
761 | && !reg_mentioned_p (dest, SET_SRC (set)) |
762 | && GET_MODE (src) == GET_MODE (dest)) | |
ddc8bed2 | 763 | { |
1a8fca8a R |
764 | int old_num_regs = reg_rtx_no; |
765 | ||
ddc8bed2 MM |
766 | /* Generate the src->dest move. */ |
767 | start_sequence (); | |
768 | emit_move_insn (dest, src); | |
2f937369 | 769 | seq = get_insns (); |
ddc8bed2 | 770 | end_sequence (); |
1a8fca8a R |
771 | /* If this sequence uses new registers, we may not use it. */ |
772 | if (old_num_regs != reg_rtx_no | |
773 | || ! validate_replace_rtx (src, dest, insn)) | |
774 | { | |
775 | /* We have to restore reg_rtx_no to its old value, lest | |
776 | recompute_reg_usage will try to compute the usage of the | |
777 | new regs, yet reg_n_info is not valid for them. */ | |
778 | reg_rtx_no = old_num_regs; | |
779 | return; | |
780 | } | |
ddc8bed2 MM |
781 | emit_insn_before (seq, insn); |
782 | move_insn = PREV_INSN (insn); | |
783 | p_move_notes = ®_NOTES (move_insn); | |
784 | p_insn_notes = ®_NOTES (insn); | |
785 | ||
3eae4643 | 786 | /* Move any notes mentioning src to the move instruction. */ |
ddc8bed2 MM |
787 | for (link = REG_NOTES (insn); link != NULL_RTX; link = next) |
788 | { | |
789 | next = XEXP (link, 1); | |
790 | if (XEXP (link, 0) == src) | |
791 | { | |
792 | *p_move_notes = link; | |
793 | p_move_notes = &XEXP (link, 1); | |
794 | } | |
795 | else | |
796 | { | |
797 | *p_insn_notes = link; | |
798 | p_insn_notes = &XEXP (link, 1); | |
799 | } | |
800 | } | |
801 | ||
802 | *p_move_notes = NULL_RTX; | |
803 | *p_insn_notes = NULL_RTX; | |
804 | ||
3eae4643 | 805 | /* Is the insn the head of a basic block? If so extend it. */ |
ddc8bed2 MM |
806 | insn_uid = INSN_UID (insn); |
807 | move_uid = INSN_UID (move_insn); | |
78dd9906 | 808 | if (insn_uid < old_max_uid) |
ddc8bed2 | 809 | { |
78dd9906 R |
810 | bb = regmove_bb_head[insn_uid]; |
811 | if (bb >= 0) | |
812 | { | |
a813c111 | 813 | BB_HEAD (BASIC_BLOCK (bb)) = move_insn; |
78dd9906 R |
814 | regmove_bb_head[insn_uid] = -1; |
815 | } | |
ddc8bed2 MM |
816 | } |
817 | ||
818 | /* Update the various register tables. */ | |
819 | dest_regno = REGNO (dest); | |
1b7c4a37 | 820 | REG_N_SETS (dest_regno) ++; |
ddc8bed2 MM |
821 | REG_LIVE_LENGTH (dest_regno)++; |
822 | if (REGNO_FIRST_UID (dest_regno) == insn_uid) | |
823 | REGNO_FIRST_UID (dest_regno) = move_uid; | |
824 | ||
825 | src_regno = REGNO (src); | |
826 | if (! find_reg_note (move_insn, REG_DEAD, src)) | |
827 | REG_LIVE_LENGTH (src_regno)++; | |
828 | ||
829 | if (REGNO_FIRST_UID (src_regno) == insn_uid) | |
830 | REGNO_FIRST_UID (src_regno) = move_uid; | |
831 | ||
832 | if (REGNO_LAST_UID (src_regno) == insn_uid) | |
833 | REGNO_LAST_UID (src_regno) = move_uid; | |
834 | ||
835 | if (REGNO_LAST_NOTE_UID (src_regno) == insn_uid) | |
836 | REGNO_LAST_NOTE_UID (src_regno) = move_uid; | |
837 | } | |
838 | } | |
839 | ||
840 | \f | |
184bb750 R |
841 | /* Return whether REG is set in only one location, and is set to a |
842 | constant, but is set in a different basic block from INSN (an | |
843 | instructions which uses REG). In this case REG is equivalent to a | |
844 | constant, and we don't want to break that equivalence, because that | |
845 | may increase register pressure and make reload harder. If REG is | |
846 | set in the same basic block as INSN, we don't worry about it, | |
847 | because we'll probably need a register anyhow (??? but what if REG | |
848 | is used in a different basic block as well as this one?). FIRST is | |
849 | the first insn in the function. */ | |
850 | ||
851 | static int | |
0c20a65f | 852 | reg_is_remote_constant_p (rtx reg, rtx insn, rtx first) |
184bb750 | 853 | { |
b3694847 | 854 | rtx p; |
184bb750 R |
855 | |
856 | if (REG_N_SETS (REGNO (reg)) != 1) | |
857 | return 0; | |
858 | ||
859 | /* Look for the set. */ | |
860 | for (p = LOG_LINKS (insn); p; p = XEXP (p, 1)) | |
861 | { | |
862 | rtx s; | |
863 | ||
864 | if (REG_NOTE_KIND (p) != 0) | |
865 | continue; | |
866 | s = single_set (XEXP (p, 0)); | |
867 | if (s != 0 | |
868 | && GET_CODE (SET_DEST (s)) == REG | |
869 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
870 | { | |
871 | /* The register is set in the same basic block. */ | |
872 | return 0; | |
873 | } | |
874 | } | |
875 | ||
876 | for (p = first; p && p != insn; p = NEXT_INSN (p)) | |
877 | { | |
878 | rtx s; | |
879 | ||
2c3c49de | 880 | if (! INSN_P (p)) |
184bb750 R |
881 | continue; |
882 | s = single_set (p); | |
883 | if (s != 0 | |
884 | && GET_CODE (SET_DEST (s)) == REG | |
885 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
886 | { | |
887 | /* This is the instruction which sets REG. If there is a | |
888 | REG_EQUAL note, then REG is equivalent to a constant. */ | |
889 | if (find_reg_note (p, REG_EQUAL, NULL_RTX)) | |
890 | return 1; | |
891 | return 0; | |
892 | } | |
893 | } | |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
b1a7d591 JW |
898 | /* INSN is adding a CONST_INT to a REG. We search backwards looking for |
899 | another add immediate instruction with the same source and dest registers, | |
900 | and if we find one, we change INSN to an increment, and return 1. If | |
901 | no changes are made, we return 0. | |
902 | ||
903 | This changes | |
904 | (set (reg100) (plus reg1 offset1)) | |
905 | ... | |
906 | (set (reg100) (plus reg1 offset2)) | |
907 | to | |
908 | (set (reg100) (plus reg1 offset1)) | |
909 | ... | |
910 | (set (reg100) (plus reg100 offset2-offset1)) */ | |
911 | ||
912 | /* ??? What does this comment mean? */ | |
14b493d6 | 913 | /* cse disrupts preincrement / postdecrement sequences when it finds a |
184bb750 | 914 | hard register as ultimate source, like the frame pointer. */ |
b1a7d591 | 915 | |
95d75019 | 916 | static int |
0c20a65f | 917 | fixup_match_2 (rtx insn, rtx dst, rtx src, rtx offset, FILE *regmove_dump_file) |
184bb750 R |
918 | { |
919 | rtx p, dst_death = 0; | |
920 | int length, num_calls = 0; | |
921 | ||
922 | /* If SRC dies in INSN, we'd have to move the death note. This is | |
923 | considered to be very unlikely, so we just skip the optimization | |
924 | in this case. */ | |
925 | if (find_regno_note (insn, REG_DEAD, REGNO (src))) | |
926 | return 0; | |
927 | ||
928 | /* Scan backward to find the first instruction that sets DST. */ | |
929 | ||
930 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
931 | { | |
932 | rtx pset; | |
933 | ||
7bf825d2 | 934 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
935 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
936 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 937 | break; |
a1c1fdd0 | 938 | else if (! INSN_P (p)) |
a6a2274a | 939 | continue; |
184bb750 | 940 | |
7bf825d2 JW |
941 | if (find_regno_note (p, REG_DEAD, REGNO (dst))) |
942 | dst_death = p; | |
943 | if (! dst_death) | |
944 | length++; | |
184bb750 R |
945 | |
946 | pset = single_set (p); | |
947 | if (pset && SET_DEST (pset) == dst | |
948 | && GET_CODE (SET_SRC (pset)) == PLUS | |
949 | && XEXP (SET_SRC (pset), 0) == src | |
950 | && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT) | |
a6a2274a | 951 | { |
184bb750 R |
952 | HOST_WIDE_INT newconst |
953 | = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1)); | |
1a29f703 R |
954 | rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst)); |
955 | ||
956 | if (add && validate_change (insn, &PATTERN (insn), add, 0)) | |
184bb750 R |
957 | { |
958 | /* Remove the death note for DST from DST_DEATH. */ | |
959 | if (dst_death) | |
960 | { | |
961 | remove_death (REGNO (dst), dst_death); | |
962 | REG_LIVE_LENGTH (REGNO (dst)) += length; | |
963 | REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls; | |
964 | } | |
965 | ||
184bb750 R |
966 | if (regmove_dump_file) |
967 | fprintf (regmove_dump_file, | |
968 | "Fixed operand of insn %d.\n", | |
969 | INSN_UID (insn)); | |
970 | ||
971 | #ifdef AUTO_INC_DEC | |
972 | for (p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
973 | { | |
974 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 975 | || GET_CODE (p) == JUMP_INSN) |
184bb750 | 976 | break; |
2c3c49de | 977 | if (! INSN_P (p)) |
e27a5106 | 978 | continue; |
184bb750 R |
979 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
980 | { | |
981 | if (try_auto_increment (p, insn, 0, dst, newconst, 0)) | |
982 | return 1; | |
983 | break; | |
984 | } | |
985 | } | |
986 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
987 | { | |
988 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 989 | || GET_CODE (p) == JUMP_INSN) |
184bb750 | 990 | break; |
2c3c49de | 991 | if (! INSN_P (p)) |
8543c01e | 992 | continue; |
184bb750 R |
993 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
994 | { | |
995 | try_auto_increment (p, insn, 0, dst, newconst, 1); | |
996 | break; | |
997 | } | |
998 | } | |
999 | #endif | |
1000 | return 1; | |
1001 | } | |
a6a2274a | 1002 | } |
184bb750 R |
1003 | |
1004 | if (reg_set_p (dst, PATTERN (p))) | |
a6a2274a | 1005 | break; |
184bb750 R |
1006 | |
1007 | /* If we have passed a call instruction, and the | |
1008 | pseudo-reg SRC is not already live across a call, | |
1009 | then don't perform the optimization. */ | |
1010 | /* reg_set_p is overly conservative for CALL_INSNS, thinks that all | |
1011 | hard regs are clobbered. Thus, we only use it for src for | |
1012 | non-call insns. */ | |
1013 | if (GET_CODE (p) == CALL_INSN) | |
a6a2274a | 1014 | { |
184bb750 R |
1015 | if (! dst_death) |
1016 | num_calls++; | |
1017 | ||
a6a2274a KH |
1018 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) |
1019 | break; | |
184bb750 R |
1020 | |
1021 | if (call_used_regs [REGNO (dst)] | |
1022 | || find_reg_fusage (p, CLOBBER, dst)) | |
1023 | break; | |
a6a2274a | 1024 | } |
184bb750 | 1025 | else if (reg_set_p (src, PATTERN (p))) |
a6a2274a | 1026 | break; |
8c660648 | 1027 | } |
184bb750 | 1028 | |
8c660648 JL |
1029 | return 0; |
1030 | } | |
8c660648 | 1031 | |
3721581a JJ |
1032 | /* Main entry for the register move optimization. |
1033 | F is the first instruction. | |
1034 | NREGS is one plus the highest pseudo-reg number used in the instruction. | |
1035 | REGMOVE_DUMP_FILE is a stream for output of a trace of actions taken | |
1036 | (or 0 if none should be output). */ | |
1037 | ||
8c660648 | 1038 | void |
0c20a65f | 1039 | regmove_optimize (rtx f, int nregs, FILE *regmove_dump_file) |
8c660648 | 1040 | { |
961d4119 | 1041 | int old_max_uid = get_max_uid (); |
8c660648 | 1042 | rtx insn; |
184bb750 | 1043 | struct match match; |
8c660648 | 1044 | int pass; |
3bb806ed | 1045 | int i; |
ddc8bed2 | 1046 | rtx copy_src, copy_dst; |
e0082a72 | 1047 | basic_block bb; |
184bb750 | 1048 | |
a614d82e RH |
1049 | /* ??? Hack. Regmove doesn't examine the CFG, and gets mightily |
1050 | confused by non-call exceptions ending blocks. */ | |
1051 | if (flag_non_call_exceptions) | |
1052 | return; | |
1053 | ||
dc2cb191 | 1054 | /* Find out where a potential flags register is live, and so that we |
14b493d6 | 1055 | can suppress some optimizations in those zones. */ |
dc2cb191 RH |
1056 | mark_flags_life_zones (discover_flags_reg ()); |
1057 | ||
703ad42b | 1058 | regno_src_regno = xmalloc (sizeof *regno_src_regno * nregs); |
3bb806ed | 1059 | for (i = nregs; --i >= 0; ) regno_src_regno[i] = -1; |
8c660648 | 1060 | |
703ad42b | 1061 | regmove_bb_head = xmalloc (sizeof (int) * (old_max_uid + 1)); |
961d4119 | 1062 | for (i = old_max_uid; i >= 0; i--) regmove_bb_head[i] = -1; |
e0082a72 | 1063 | FOR_EACH_BB (bb) |
a813c111 | 1064 | regmove_bb_head[INSN_UID (BB_HEAD (bb))] = bb->index; |
ddc8bed2 | 1065 | |
8c660648 JL |
1066 | /* A forward/backward pass. Replace output operands with input operands. */ |
1067 | ||
184bb750 | 1068 | for (pass = 0; pass <= 2; pass++) |
8c660648 | 1069 | { |
184bb750 | 1070 | if (! flag_regmove && pass >= flag_expensive_optimizations) |
4da896b2 | 1071 | goto done; |
184bb750 | 1072 | |
8c660648 JL |
1073 | if (regmove_dump_file) |
1074 | fprintf (regmove_dump_file, "Starting %s pass...\n", | |
1075 | pass ? "backward" : "forward"); | |
1076 | ||
1077 | for (insn = pass ? get_last_insn () : f; insn; | |
1078 | insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn)) | |
1079 | { | |
184bb750 | 1080 | rtx set; |
0eadeb15 | 1081 | int op_no, match_no; |
184bb750 | 1082 | |
184bb750 R |
1083 | set = single_set (insn); |
1084 | if (! set) | |
1085 | continue; | |
8c660648 | 1086 | |
184bb750 R |
1087 | if (flag_expensive_optimizations && ! pass |
1088 | && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND | |
1089 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND) | |
1090 | && GET_CODE (XEXP (SET_SRC (set), 0)) == REG | |
8e2e89f7 | 1091 | && GET_CODE (SET_DEST (set)) == REG) |
184bb750 R |
1092 | optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set)); |
1093 | ||
1094 | if (flag_expensive_optimizations && ! pass | |
1095 | && GET_CODE (SET_SRC (set)) == REG | |
8e2e89f7 | 1096 | && GET_CODE (SET_DEST (set)) == REG) |
184bb750 R |
1097 | { |
1098 | /* If this is a register-register copy where SRC is not dead, | |
1099 | see if we can optimize it. If this optimization succeeds, | |
1100 | it will become a copy where SRC is dead. */ | |
1101 | if ((find_reg_note (insn, REG_DEAD, SET_SRC (set)) | |
1102 | || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set))) | |
1103 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) | |
8c660648 | 1104 | { |
184bb750 R |
1105 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ |
1106 | if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1107 | optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set)); | |
1108 | if (regno_src_regno[REGNO (SET_DEST (set))] < 0 | |
1109 | && SET_SRC (set) != SET_DEST (set)) | |
8c660648 | 1110 | { |
8e2e89f7 | 1111 | int srcregno = REGNO (SET_SRC (set)); |
184bb750 R |
1112 | if (regno_src_regno[srcregno] >= 0) |
1113 | srcregno = regno_src_regno[srcregno]; | |
1114 | regno_src_regno[REGNO (SET_DEST (set))] = srcregno; | |
8c660648 JL |
1115 | } |
1116 | } | |
184bb750 | 1117 | } |
a6a2274a KH |
1118 | if (! flag_regmove) |
1119 | continue; | |
184bb750 | 1120 | |
3363316f | 1121 | if (! find_matches (insn, &match)) |
184bb750 R |
1122 | continue; |
1123 | ||
1124 | /* Now scan through the operands looking for a source operand | |
1125 | which is supposed to match the destination operand. | |
1126 | Then scan forward for an instruction which uses the dest | |
1127 | operand. | |
1128 | If it dies there, then replace the dest in both operands with | |
1129 | the source operand. */ | |
1130 | ||
1ccbefce | 1131 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1132 | { |
5e9defae | 1133 | rtx src, dst, src_subreg; |
184bb750 R |
1134 | enum reg_class src_class, dst_class; |
1135 | ||
0eadeb15 | 1136 | match_no = match.with[op_no]; |
184bb750 R |
1137 | |
1138 | /* Nothing to do if the two operands aren't supposed to match. */ | |
0eadeb15 | 1139 | if (match_no < 0) |
184bb750 R |
1140 | continue; |
1141 | ||
1ccbefce RH |
1142 | src = recog_data.operand[op_no]; |
1143 | dst = recog_data.operand[match_no]; | |
184bb750 R |
1144 | |
1145 | if (GET_CODE (src) != REG) | |
1146 | continue; | |
1147 | ||
1148 | src_subreg = src; | |
1149 | if (GET_CODE (dst) == SUBREG | |
1150 | && GET_MODE_SIZE (GET_MODE (dst)) | |
1151 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst)))) | |
1152 | { | |
1153 | src_subreg | |
38a448ca | 1154 | = gen_rtx_SUBREG (GET_MODE (SUBREG_REG (dst)), |
ddef6bc7 | 1155 | src, SUBREG_BYTE (dst)); |
184bb750 R |
1156 | dst = SUBREG_REG (dst); |
1157 | } | |
1158 | if (GET_CODE (dst) != REG | |
1159 | || REGNO (dst) < FIRST_PSEUDO_REGISTER) | |
1160 | continue; | |
1161 | ||
1162 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) | |
1163 | { | |
0eadeb15 | 1164 | if (match.commutative[op_no] < op_no) |
184bb750 R |
1165 | regno_src_regno[REGNO (dst)] = REGNO (src); |
1166 | continue; | |
1167 | } | |
1168 | ||
1169 | if (REG_LIVE_LENGTH (REGNO (src)) < 0) | |
1170 | continue; | |
1171 | ||
0eadeb15 | 1172 | /* op_no/src must be a read-only operand, and |
184bb750 | 1173 | match_operand/dst must be a write-only operand. */ |
0eadeb15 BS |
1174 | if (match.use[op_no] != READ |
1175 | || match.use[match_no] != WRITE) | |
184bb750 R |
1176 | continue; |
1177 | ||
0eadeb15 | 1178 | if (match.early_clobber[match_no] |
4b983fdc | 1179 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
184bb750 R |
1180 | continue; |
1181 | ||
1182 | /* Make sure match_operand is the destination. */ | |
1ccbefce | 1183 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 R |
1184 | continue; |
1185 | ||
dc297297 | 1186 | /* If the operands already match, then there is nothing to do. */ |
1ccbefce | 1187 | if (operands_match_p (src, dst)) |
184bb750 R |
1188 | continue; |
1189 | ||
1ccbefce RH |
1190 | /* But in the commutative case, we might find a better match. */ |
1191 | if (match.commutative[op_no] >= 0) | |
1192 | { | |
1193 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1194 | if (operands_match_p (comm, dst) | |
1195 | && (replacement_quality (comm) | |
1196 | >= replacement_quality (src))) | |
1197 | continue; | |
1198 | } | |
1199 | ||
184bb750 R |
1200 | src_class = reg_preferred_class (REGNO (src)); |
1201 | dst_class = reg_preferred_class (REGNO (dst)); | |
3bb806ed | 1202 | if (! regclass_compatible_p (src_class, dst_class)) |
184bb750 | 1203 | continue; |
174fa2c4 | 1204 | |
f3029065 KH |
1205 | if (GET_MODE (src) != GET_MODE (dst)) |
1206 | continue; | |
1207 | ||
184bb750 | 1208 | if (fixup_match_1 (insn, set, src, src_subreg, dst, pass, |
0eadeb15 | 1209 | op_no, match_no, |
184bb750 R |
1210 | regmove_dump_file)) |
1211 | break; | |
8c660648 JL |
1212 | } |
1213 | } | |
1214 | } | |
1215 | ||
1216 | /* A backward pass. Replace input operands with output operands. */ | |
1217 | ||
1218 | if (regmove_dump_file) | |
1219 | fprintf (regmove_dump_file, "Starting backward pass...\n"); | |
1220 | ||
1221 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
1222 | { | |
2c3c49de | 1223 | if (INSN_P (insn)) |
8c660648 | 1224 | { |
0eadeb15 | 1225 | int op_no, match_no; |
ddc8bed2 | 1226 | int success = 0; |
0eadeb15 | 1227 | |
3363316f | 1228 | if (! find_matches (insn, &match)) |
8c660648 JL |
1229 | continue; |
1230 | ||
8c660648 JL |
1231 | /* Now scan through the operands looking for a destination operand |
1232 | which is supposed to match a source operand. | |
1233 | Then scan backward for an instruction which sets the source | |
1234 | operand. If safe, then replace the source operand with the | |
1235 | dest operand in both instructions. */ | |
1236 | ||
ddc8bed2 MM |
1237 | copy_src = NULL_RTX; |
1238 | copy_dst = NULL_RTX; | |
1ccbefce | 1239 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
8c660648 | 1240 | { |
184bb750 R |
1241 | rtx set, p, src, dst; |
1242 | rtx src_note, dst_note; | |
184bb750 R |
1243 | int num_calls = 0; |
1244 | enum reg_class src_class, dst_class; | |
1245 | int length; | |
8c660648 | 1246 | |
0eadeb15 | 1247 | match_no = match.with[op_no]; |
8c660648 | 1248 | |
184bb750 | 1249 | /* Nothing to do if the two operands aren't supposed to match. */ |
0eadeb15 | 1250 | if (match_no < 0) |
184bb750 | 1251 | continue; |
8c660648 | 1252 | |
1ccbefce RH |
1253 | dst = recog_data.operand[match_no]; |
1254 | src = recog_data.operand[op_no]; | |
8c660648 | 1255 | |
184bb750 R |
1256 | if (GET_CODE (src) != REG) |
1257 | continue; | |
8c660648 | 1258 | |
184bb750 R |
1259 | if (GET_CODE (dst) != REG |
1260 | || REGNO (dst) < FIRST_PSEUDO_REGISTER | |
3721581a | 1261 | || REG_LIVE_LENGTH (REGNO (dst)) < 0 |
41b3243e JH |
1262 | || RTX_UNCHANGING_P (dst) |
1263 | || GET_MODE (src) != GET_MODE (dst)) | |
184bb750 | 1264 | continue; |
8c660648 | 1265 | |
dc297297 | 1266 | /* If the operands already match, then there is nothing to do. */ |
1ccbefce | 1267 | if (operands_match_p (src, dst)) |
184bb750 | 1268 | continue; |
8c660648 | 1269 | |
1ccbefce RH |
1270 | if (match.commutative[op_no] >= 0) |
1271 | { | |
1272 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1273 | if (operands_match_p (comm, dst)) | |
1274 | continue; | |
1275 | } | |
1276 | ||
184bb750 R |
1277 | set = single_set (insn); |
1278 | if (! set) | |
1279 | continue; | |
8c660648 | 1280 | |
bb948ad3 RZ |
1281 | /* Note that single_set ignores parts of a parallel set for |
1282 | which one of the destinations is REG_UNUSED. We can't | |
1283 | handle that here, since we can wind up rewriting things | |
1284 | such that a single register is set twice within a single | |
1285 | parallel. */ | |
1286 | if (reg_set_p (src, insn)) | |
1287 | continue; | |
1288 | ||
0eadeb15 | 1289 | /* match_no/dst must be a write-only operand, and |
184bb750 | 1290 | operand_operand/src must be a read-only operand. */ |
0eadeb15 BS |
1291 | if (match.use[op_no] != READ |
1292 | || match.use[match_no] != WRITE) | |
184bb750 | 1293 | continue; |
8c660648 | 1294 | |
0eadeb15 | 1295 | if (match.early_clobber[match_no] |
4b983fdc | 1296 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
184bb750 | 1297 | continue; |
8c660648 | 1298 | |
0eadeb15 | 1299 | /* Make sure match_no is the destination. */ |
1ccbefce | 1300 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 | 1301 | continue; |
8c660648 | 1302 | |
184bb750 R |
1303 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) |
1304 | { | |
1305 | if (GET_CODE (SET_SRC (set)) == PLUS | |
1306 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT | |
1307 | && XEXP (SET_SRC (set), 0) == src | |
1308 | && fixup_match_2 (insn, dst, src, | |
1309 | XEXP (SET_SRC (set), 1), | |
1310 | regmove_dump_file)) | |
1311 | break; | |
1312 | continue; | |
1313 | } | |
1314 | src_class = reg_preferred_class (REGNO (src)); | |
1315 | dst_class = reg_preferred_class (REGNO (dst)); | |
fd973d56 JH |
1316 | |
1317 | if (! (src_note = find_reg_note (insn, REG_DEAD, src))) | |
ddc8bed2 | 1318 | { |
fd973d56 JH |
1319 | /* We used to force the copy here like in other cases, but |
1320 | it produces worse code, as it eliminates no copy | |
1321 | instructions and the copy emitted will be produced by | |
1322 | reload anyway. On patterns with multiple alternatives, | |
14b493d6 | 1323 | there may be better solution available. |
fd973d56 JH |
1324 | |
1325 | In particular this change produced slower code for numeric | |
1326 | i387 programs. */ | |
1327 | ||
ddc8bed2 MM |
1328 | continue; |
1329 | } | |
8c660648 | 1330 | |
fd973d56 | 1331 | if (! regclass_compatible_p (src_class, dst_class)) |
ddc8bed2 MM |
1332 | { |
1333 | if (!copy_src) | |
1334 | { | |
1335 | copy_src = src; | |
1336 | copy_dst = dst; | |
1337 | } | |
1338 | continue; | |
1339 | } | |
1340 | ||
fd973d56 JH |
1341 | /* Can not modify an earlier insn to set dst if this insn |
1342 | uses an old value in the source. */ | |
1343 | if (reg_overlap_mentioned_p (dst, SET_SRC (set))) | |
ddc8bed2 MM |
1344 | { |
1345 | if (!copy_src) | |
1346 | { | |
1347 | copy_src = src; | |
1348 | copy_dst = dst; | |
1349 | } | |
1350 | continue; | |
1351 | } | |
8c660648 | 1352 | |
184bb750 R |
1353 | /* If src is set once in a different basic block, |
1354 | and is set equal to a constant, then do not use | |
1355 | it for this optimization, as this would make it | |
1356 | no longer equivalent to a constant. */ | |
ddc8bed2 | 1357 | |
a6a2274a | 1358 | if (reg_is_remote_constant_p (src, insn, f)) |
ddc8bed2 MM |
1359 | { |
1360 | if (!copy_src) | |
1361 | { | |
1362 | copy_src = src; | |
1363 | copy_dst = dst; | |
1364 | } | |
1365 | continue; | |
1366 | } | |
1367 | ||
1368 | ||
1369 | if (regmove_dump_file) | |
1370 | fprintf (regmove_dump_file, | |
1371 | "Could fix operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1372 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1373 | |
184bb750 R |
1374 | /* Scan backward to find the first instruction that uses |
1375 | the input operand. If the operand is set here, then | |
0eadeb15 | 1376 | replace it in both instructions with match_no. */ |
184bb750 R |
1377 | |
1378 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1379 | { | |
1380 | rtx pset; | |
1381 | ||
7bf825d2 JW |
1382 | /* ??? We can't scan past the end of a basic block without |
1383 | updating the register lifetime info | |
a1c1fdd0 RK |
1384 | (REG_DEAD/basic_block_live_at_start). */ |
1385 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 1386 | break; |
a1c1fdd0 | 1387 | else if (! INSN_P (p)) |
184bb750 | 1388 | continue; |
8c660648 | 1389 | |
184bb750 | 1390 | length++; |
8c660648 | 1391 | |
184bb750 R |
1392 | /* ??? See if all of SRC is set in P. This test is much |
1393 | more conservative than it needs to be. */ | |
1394 | pset = single_set (p); | |
1395 | if (pset && SET_DEST (pset) == src) | |
1396 | { | |
1397 | /* We use validate_replace_rtx, in case there | |
1398 | are multiple identical source operands. All of | |
1399 | them have to be changed at the same time. */ | |
1400 | if (validate_replace_rtx (src, dst, insn)) | |
8c660648 | 1401 | { |
184bb750 R |
1402 | if (validate_change (p, &SET_DEST (pset), |
1403 | dst, 0)) | |
1404 | success = 1; | |
1405 | else | |
8c660648 | 1406 | { |
184bb750 R |
1407 | /* Change all source operands back. |
1408 | This modifies the dst as a side-effect. */ | |
1409 | validate_replace_rtx (dst, src, insn); | |
1410 | /* Now make sure the dst is right. */ | |
1411 | validate_change (insn, | |
1ccbefce | 1412 | recog_data.operand_loc[match_no], |
184bb750 | 1413 | dst, 0); |
8c660648 | 1414 | } |
8c660648 | 1415 | } |
184bb750 R |
1416 | break; |
1417 | } | |
1418 | ||
1419 | if (reg_overlap_mentioned_p (src, PATTERN (p)) | |
1420 | || reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1421 | break; | |
8c660648 | 1422 | |
184bb750 R |
1423 | /* If we have passed a call instruction, and the |
1424 | pseudo-reg DST is not already live across a call, | |
1425 | then don't perform the optimization. */ | |
1426 | if (GET_CODE (p) == CALL_INSN) | |
1427 | { | |
1428 | num_calls++; | |
1429 | ||
1430 | if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0) | |
8c660648 | 1431 | break; |
184bb750 R |
1432 | } |
1433 | } | |
8c660648 | 1434 | |
184bb750 R |
1435 | if (success) |
1436 | { | |
1437 | int dstno, srcno; | |
8c660648 | 1438 | |
184bb750 R |
1439 | /* Remove the death note for SRC from INSN. */ |
1440 | remove_note (insn, src_note); | |
1441 | /* Move the death note for SRC to P if it is used | |
1442 | there. */ | |
1443 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1444 | { | |
1445 | XEXP (src_note, 1) = REG_NOTES (p); | |
1446 | REG_NOTES (p) = src_note; | |
8c660648 | 1447 | } |
184bb750 R |
1448 | /* If there is a REG_DEAD note for DST on P, then remove |
1449 | it, because DST is now set there. */ | |
5e9defae | 1450 | if ((dst_note = find_reg_note (p, REG_DEAD, dst))) |
184bb750 R |
1451 | remove_note (p, dst_note); |
1452 | ||
1453 | dstno = REGNO (dst); | |
1454 | srcno = REGNO (src); | |
1455 | ||
1456 | REG_N_SETS (dstno)++; | |
1457 | REG_N_SETS (srcno)--; | |
8c660648 | 1458 | |
184bb750 R |
1459 | REG_N_CALLS_CROSSED (dstno) += num_calls; |
1460 | REG_N_CALLS_CROSSED (srcno) -= num_calls; | |
1461 | ||
1462 | REG_LIVE_LENGTH (dstno) += length; | |
1463 | if (REG_LIVE_LENGTH (srcno) >= 0) | |
8c660648 | 1464 | { |
184bb750 R |
1465 | REG_LIVE_LENGTH (srcno) -= length; |
1466 | /* REG_LIVE_LENGTH is only an approximation after | |
1467 | combine if sched is not run, so make sure that we | |
1468 | still have a reasonable value. */ | |
1469 | if (REG_LIVE_LENGTH (srcno) < 2) | |
1470 | REG_LIVE_LENGTH (srcno) = 2; | |
1471 | } | |
8c660648 | 1472 | |
184bb750 R |
1473 | if (regmove_dump_file) |
1474 | fprintf (regmove_dump_file, | |
1475 | "Fixed operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1476 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1477 | |
184bb750 | 1478 | break; |
8c660648 JL |
1479 | } |
1480 | } | |
ddc8bed2 MM |
1481 | |
1482 | /* If we weren't able to replace any of the alternatives, try an | |
14b493d6 | 1483 | alternative approach of copying the source to the destination. */ |
ddc8bed2 | 1484 | if (!success && copy_src != NULL_RTX) |
1b7c4a37 | 1485 | copy_src_to_dest (insn, copy_src, copy_dst, old_max_uid); |
ddc8bed2 | 1486 | |
8c660648 JL |
1487 | } |
1488 | } | |
961d4119 BS |
1489 | |
1490 | /* In fixup_match_1, some insns may have been inserted after basic block | |
1491 | ends. Fix that here. */ | |
e0082a72 | 1492 | FOR_EACH_BB (bb) |
961d4119 | 1493 | { |
a813c111 | 1494 | rtx end = BB_END (bb); |
961d4119 BS |
1495 | rtx new = end; |
1496 | rtx next = NEXT_INSN (new); | |
1497 | while (next != 0 && INSN_UID (next) >= old_max_uid | |
a813c111 | 1498 | && (bb->next_bb == EXIT_BLOCK_PTR || BB_HEAD (bb->next_bb) != next)) |
961d4119 | 1499 | new = next, next = NEXT_INSN (new); |
a813c111 | 1500 | BB_END (bb) = new; |
961d4119 | 1501 | } |
4da896b2 MM |
1502 | |
1503 | done: | |
1504 | /* Clean up. */ | |
1505 | free (regno_src_regno); | |
1506 | free (regmove_bb_head); | |
8c660648 JL |
1507 | } |
1508 | ||
0eadeb15 BS |
1509 | /* Returns nonzero if INSN's pattern has matching constraints for any operand. |
1510 | Returns 0 if INSN can't be recognized, or if the alternative can't be | |
1511 | determined. | |
b1a7d591 JW |
1512 | |
1513 | Initialize the info in MATCHP based on the constraints. */ | |
184bb750 R |
1514 | |
1515 | static int | |
0c20a65f | 1516 | find_matches (rtx insn, struct match *matchp) |
184bb750 R |
1517 | { |
1518 | int likely_spilled[MAX_RECOG_OPERANDS]; | |
0eadeb15 | 1519 | int op_no; |
184bb750 R |
1520 | int any_matches = 0; |
1521 | ||
0eadeb15 BS |
1522 | extract_insn (insn); |
1523 | if (! constrain_operands (0)) | |
1524 | return 0; | |
184bb750 R |
1525 | |
1526 | /* Must initialize this before main loop, because the code for | |
1527 | the commutative case may set matches for operands other than | |
1528 | the current one. */ | |
1ccbefce | 1529 | for (op_no = recog_data.n_operands; --op_no >= 0; ) |
0eadeb15 | 1530 | matchp->with[op_no] = matchp->commutative[op_no] = -1; |
184bb750 | 1531 | |
1ccbefce | 1532 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1533 | { |
9b3142b3 KG |
1534 | const char *p; |
1535 | char c; | |
184bb750 R |
1536 | int i = 0; |
1537 | ||
1ccbefce | 1538 | p = recog_data.constraints[op_no]; |
184bb750 | 1539 | |
0eadeb15 BS |
1540 | likely_spilled[op_no] = 0; |
1541 | matchp->use[op_no] = READ; | |
1542 | matchp->early_clobber[op_no] = 0; | |
184bb750 | 1543 | if (*p == '=') |
0eadeb15 | 1544 | matchp->use[op_no] = WRITE; |
184bb750 | 1545 | else if (*p == '+') |
0eadeb15 | 1546 | matchp->use[op_no] = READWRITE; |
184bb750 R |
1547 | |
1548 | for (;*p && i < which_alternative; p++) | |
1549 | if (*p == ',') | |
1550 | i++; | |
1551 | ||
97488870 R |
1552 | while ((c = *p) != '\0' && c != ',') |
1553 | { | |
1554 | switch (c) | |
84b72302 | 1555 | { |
97488870 R |
1556 | case '=': |
1557 | break; | |
1558 | case '+': | |
1559 | break; | |
1560 | case '&': | |
1561 | matchp->early_clobber[op_no] = 1; | |
1562 | break; | |
1563 | case '%': | |
1564 | matchp->commutative[op_no] = op_no + 1; | |
1565 | matchp->commutative[op_no + 1] = op_no; | |
1566 | break; | |
1567 | ||
1568 | case '0': case '1': case '2': case '3': case '4': | |
1569 | case '5': case '6': case '7': case '8': case '9': | |
1570 | { | |
1571 | char *end; | |
1572 | unsigned long match_ul = strtoul (p, &end, 10); | |
1573 | int match = match_ul; | |
2cc2d4bb | 1574 | |
97488870 | 1575 | p = end; |
84b72302 | 1576 | |
97488870 R |
1577 | if (match < op_no && likely_spilled[match]) |
1578 | continue; | |
1579 | matchp->with[op_no] = match; | |
1580 | any_matches = 1; | |
1581 | if (matchp->commutative[op_no] >= 0) | |
1582 | matchp->with[matchp->commutative[op_no]] = match; | |
1583 | } | |
1584 | continue; | |
84b72302 | 1585 | |
184bb750 R |
1586 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h': |
1587 | case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u': | |
1588 | case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B': | |
1589 | case 'C': case 'D': case 'W': case 'Y': case 'Z': | |
97488870 | 1590 | if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p) )) |
0eadeb15 | 1591 | likely_spilled[op_no] = 1; |
184bb750 R |
1592 | break; |
1593 | } | |
97488870 R |
1594 | p += CONSTRAINT_LEN (c, p); |
1595 | } | |
184bb750 | 1596 | } |
0eadeb15 | 1597 | return any_matches; |
184bb750 R |
1598 | } |
1599 | ||
ec7c0481 AO |
1600 | /* Try to replace all occurrences of DST_REG with SRC in LOC, that is |
1601 | assumed to be in INSN. */ | |
1602 | ||
1603 | static void | |
0c20a65f | 1604 | replace_in_call_usage (rtx *loc, unsigned int dst_reg, rtx src, rtx insn) |
ec7c0481 AO |
1605 | { |
1606 | rtx x = *loc; | |
1607 | enum rtx_code code; | |
1608 | const char *fmt; | |
1609 | int i, j; | |
1610 | ||
1611 | if (! x) | |
1612 | return; | |
174fa2c4 | 1613 | |
ec7c0481 AO |
1614 | code = GET_CODE (x); |
1615 | if (code == REG) | |
1616 | { | |
1617 | if (REGNO (x) != dst_reg) | |
1618 | return; | |
174fa2c4 | 1619 | |
ec7c0481 AO |
1620 | validate_change (insn, loc, src, 1); |
1621 | ||
1622 | return; | |
1623 | } | |
174fa2c4 | 1624 | |
ec7c0481 AO |
1625 | /* Process each of our operands recursively. */ |
1626 | fmt = GET_RTX_FORMAT (code); | |
1627 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
1628 | if (*fmt == 'e') | |
1629 | replace_in_call_usage (&XEXP (x, i), dst_reg, src, insn); | |
1630 | else if (*fmt == 'E') | |
1631 | for (j = 0; j < XVECLEN (x, i); j++) | |
1632 | replace_in_call_usage (& XVECEXP (x, i, j), dst_reg, src, insn); | |
1633 | } | |
1634 | ||
184bb750 | 1635 | /* Try to replace output operand DST in SET, with input operand SRC. SET is |
06671717 | 1636 | the only set in INSN. INSN has just been recognized and constrained. |
184bb750 R |
1637 | SRC is operand number OPERAND_NUMBER in INSN. |
1638 | DST is operand number MATCH_NUMBER in INSN. | |
1639 | If BACKWARD is nonzero, we have been called in a backward pass. | |
1640 | Return nonzero for success. */ | |
a1c1fdd0 | 1641 | |
184bb750 | 1642 | static int |
0c20a65f AJ |
1643 | fixup_match_1 (rtx insn, rtx set, rtx src, rtx src_subreg, rtx dst, |
1644 | int backward, int operand_number, int match_number, | |
1645 | FILE *regmove_dump_file) | |
184bb750 R |
1646 | { |
1647 | rtx p; | |
1648 | rtx post_inc = 0, post_inc_set = 0, search_end = 0; | |
1649 | int success = 0; | |
1650 | int num_calls = 0, s_num_calls = 0; | |
1651 | enum rtx_code code = NOTE; | |
0334ef47 | 1652 | HOST_WIDE_INT insn_const = 0, newconst = 0; |
184bb750 | 1653 | rtx overlap = 0; /* need to move insn ? */ |
a544cfd2 | 1654 | rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note = NULL_RTX; |
1b7c4a37 | 1655 | int length, s_length; |
184bb750 | 1656 | |
18bf656f R |
1657 | /* If SRC is marked as unchanging, we may not change it. |
1658 | ??? Maybe we could get better code by removing the unchanging bit | |
1659 | instead, and changing it back if we don't succeed? */ | |
1660 | if (RTX_UNCHANGING_P (src)) | |
1661 | return 0; | |
1662 | ||
184bb750 R |
1663 | if (! src_note) |
1664 | { | |
1665 | /* Look for (set (regX) (op regA constX)) | |
1666 | (set (regY) (op regA constY)) | |
1667 | and change that to | |
1668 | (set (regA) (op regA constX)). | |
1669 | (set (regY) (op regA constY-constX)). | |
1670 | This works for add and shift operations, if | |
1671 | regA is dead after or set by the second insn. */ | |
1672 | ||
1673 | code = GET_CODE (SET_SRC (set)); | |
1674 | if ((code == PLUS || code == LSHIFTRT | |
1675 | || code == ASHIFT || code == ASHIFTRT) | |
1676 | && XEXP (SET_SRC (set), 0) == src | |
1677 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
1678 | insn_const = INTVAL (XEXP (SET_SRC (set), 1)); | |
18bf656f | 1679 | else if (! stable_and_no_regs_but_for_p (SET_SRC (set), src, dst)) |
184bb750 R |
1680 | return 0; |
1681 | else | |
1682 | /* We might find a src_note while scanning. */ | |
1683 | code = NOTE; | |
1684 | } | |
1685 | ||
1686 | if (regmove_dump_file) | |
1687 | fprintf (regmove_dump_file, | |
1688 | "Could fix operand %d of insn %d matching operand %d.\n", | |
1689 | operand_number, INSN_UID (insn), match_number); | |
1690 | ||
1691 | /* If SRC is equivalent to a constant set in a different basic block, | |
1692 | then do not use it for this optimization. We want the equivalence | |
1693 | so that if we have to reload this register, we can reload the | |
1694 | constant, rather than extending the lifespan of the register. */ | |
1695 | if (reg_is_remote_constant_p (src, insn, get_insns ())) | |
1696 | return 0; | |
1697 | ||
1698 | /* Scan forward to find the next instruction that | |
1699 | uses the output operand. If the operand dies here, | |
1700 | then replace it in both instructions with | |
1701 | operand_number. */ | |
1702 | ||
1703 | for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1704 | { | |
ec7c0481 AO |
1705 | if (GET_CODE (p) == CALL_INSN) |
1706 | replace_in_call_usage (& CALL_INSN_FUNCTION_USAGE (p), | |
1707 | REGNO (dst), src, p); | |
174fa2c4 | 1708 | |
7bf825d2 | 1709 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
1710 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
1711 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 1712 | break; |
a1c1fdd0 | 1713 | else if (! INSN_P (p)) |
184bb750 R |
1714 | continue; |
1715 | ||
1716 | length++; | |
1717 | if (src_note) | |
1718 | s_length++; | |
1719 | ||
1720 | if (reg_set_p (src, p) || reg_set_p (dst, p) | |
1721 | || (GET_CODE (PATTERN (p)) == USE | |
1722 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
1723 | break; | |
1724 | ||
1725 | /* See if all of DST dies in P. This test is | |
1726 | slightly more conservative than it needs to be. */ | |
1727 | if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst))) | |
1728 | && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst))) | |
1729 | { | |
2219e921 R |
1730 | /* If we would be moving INSN, check that we won't move it |
1731 | into the shadow of a live a live flags register. */ | |
1732 | /* ??? We only try to move it in front of P, although | |
1733 | we could move it anywhere between OVERLAP and P. */ | |
1734 | if (overlap && GET_MODE (PREV_INSN (p)) != VOIDmode) | |
1735 | break; | |
1736 | ||
184bb750 R |
1737 | if (! src_note) |
1738 | { | |
1739 | rtx q; | |
a544cfd2 | 1740 | rtx set2 = NULL_RTX; |
184bb750 R |
1741 | |
1742 | /* If an optimization is done, the value of SRC while P | |
1743 | is executed will be changed. Check that this is OK. */ | |
1744 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1745 | break; | |
1746 | for (q = p; q; q = NEXT_INSN (q)) | |
1747 | { | |
7bf825d2 JW |
1748 | /* ??? We can't scan past the end of a basic block without |
1749 | updating the register lifetime info | |
a1c1fdd0 RK |
1750 | (REG_DEAD/basic_block_live_at_start). */ |
1751 | if (perhaps_ends_bb_p (q)) | |
7bf825d2 JW |
1752 | { |
1753 | q = 0; | |
1754 | break; | |
1755 | } | |
a1c1fdd0 | 1756 | else if (! INSN_P (q)) |
184bb750 | 1757 | continue; |
a1c1fdd0 RK |
1758 | else if (reg_overlap_mentioned_p (src, PATTERN (q)) |
1759 | || reg_set_p (src, q)) | |
184bb750 R |
1760 | break; |
1761 | } | |
1762 | if (q) | |
1763 | set2 = single_set (q); | |
1764 | if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code | |
1765 | || XEXP (SET_SRC (set2), 0) != src | |
1766 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT | |
1767 | || (SET_DEST (set2) != src | |
1768 | && ! find_reg_note (q, REG_DEAD, src))) | |
1769 | { | |
1770 | /* If this is a PLUS, we can still save a register by doing | |
1771 | src += insn_const; | |
1772 | P; | |
1773 | src -= insn_const; . | |
1774 | This also gives opportunities for subsequent | |
1775 | optimizations in the backward pass, so do it there. */ | |
1776 | if (code == PLUS && backward | |
3bb806ed R |
1777 | /* Don't do this if we can likely tie DST to SET_DEST |
1778 | of P later; we can't do this tying here if we got a | |
1779 | hard register. */ | |
1780 | && ! (dst_note && ! REG_N_CALLS_CROSSED (REGNO (dst)) | |
1781 | && single_set (p) | |
1782 | && GET_CODE (SET_DEST (single_set (p))) == REG | |
1783 | && (REGNO (SET_DEST (single_set (p))) | |
1784 | < FIRST_PSEUDO_REGISTER)) | |
dc2cb191 RH |
1785 | /* We may only emit an insn directly after P if we |
1786 | are not in the shadow of a live flags register. */ | |
1787 | && GET_MODE (p) == VOIDmode) | |
184bb750 R |
1788 | { |
1789 | search_end = q; | |
1790 | q = insn; | |
1791 | set2 = set; | |
1792 | newconst = -insn_const; | |
1793 | code = MINUS; | |
1794 | } | |
1795 | else | |
1796 | break; | |
1797 | } | |
1798 | else | |
1799 | { | |
1800 | newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const; | |
1801 | /* Reject out of range shifts. */ | |
1802 | if (code != PLUS | |
1803 | && (newconst < 0 | |
a1c1fdd0 RK |
1804 | || ((unsigned HOST_WIDE_INT) newconst |
1805 | >= (GET_MODE_BITSIZE (GET_MODE | |
1806 | (SET_SRC (set2))))))) | |
184bb750 R |
1807 | break; |
1808 | if (code == PLUS) | |
1809 | { | |
1810 | post_inc = q; | |
1811 | if (SET_DEST (set2) != src) | |
1812 | post_inc_set = set2; | |
1813 | } | |
1814 | } | |
1815 | /* We use 1 as last argument to validate_change so that all | |
1816 | changes are accepted or rejected together by apply_change_group | |
1817 | when it is called by validate_replace_rtx . */ | |
1818 | validate_change (q, &XEXP (SET_SRC (set2), 1), | |
1819 | GEN_INT (newconst), 1); | |
1820 | } | |
1ccbefce | 1821 | validate_change (insn, recog_data.operand_loc[match_number], src, 1); |
184bb750 R |
1822 | if (validate_replace_rtx (dst, src_subreg, p)) |
1823 | success = 1; | |
1824 | break; | |
1825 | } | |
1826 | ||
1827 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1828 | break; | |
1829 | if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p))) | |
1830 | { | |
2219e921 R |
1831 | /* INSN was already checked to be movable wrt. the registers that it |
1832 | sets / uses when we found no REG_DEAD note for src on it, but it | |
1833 | still might clobber the flags register. We'll have to check that | |
1834 | we won't insert it into the shadow of a live flags register when | |
1835 | we finally know where we are to move it. */ | |
184bb750 R |
1836 | overlap = p; |
1837 | src_note = find_reg_note (p, REG_DEAD, src); | |
1838 | } | |
1839 | ||
1840 | /* If we have passed a call instruction, and the pseudo-reg SRC is not | |
1841 | already live across a call, then don't perform the optimization. */ | |
1842 | if (GET_CODE (p) == CALL_INSN) | |
1843 | { | |
1844 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1845 | break; | |
1846 | ||
1847 | num_calls++; | |
1848 | ||
1849 | if (src_note) | |
1850 | s_num_calls++; | |
1851 | ||
1852 | } | |
1853 | } | |
1854 | ||
1855 | if (! success) | |
1856 | return 0; | |
1857 | ||
184bb750 R |
1858 | /* Remove the death note for DST from P. */ |
1859 | remove_note (p, dst_note); | |
1860 | if (code == MINUS) | |
1861 | { | |
1862 | post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p); | |
940da324 JL |
1863 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
1864 | && search_end | |
184bb750 R |
1865 | && try_auto_increment (search_end, post_inc, 0, src, newconst, 1)) |
1866 | post_inc = 0; | |
184bb750 R |
1867 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0); |
1868 | REG_N_SETS (REGNO (src))++; | |
184bb750 R |
1869 | REG_LIVE_LENGTH (REGNO (src))++; |
1870 | } | |
1871 | if (overlap) | |
1872 | { | |
1873 | /* The lifetime of src and dest overlap, | |
1874 | but we can change this by moving insn. */ | |
1875 | rtx pat = PATTERN (insn); | |
1876 | if (src_note) | |
1877 | remove_note (overlap, src_note); | |
1ed9faee TM |
1878 | if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1879 | && code == PLUS | |
184bb750 R |
1880 | && try_auto_increment (overlap, insn, 0, src, insn_const, 0)) |
1881 | insn = overlap; | |
1882 | else | |
184bb750 R |
1883 | { |
1884 | rtx notes = REG_NOTES (insn); | |
1885 | ||
1886 | emit_insn_after_with_line_notes (pat, PREV_INSN (p), insn); | |
ca6c03ca | 1887 | delete_insn (insn); |
184bb750 R |
1888 | /* emit_insn_after_with_line_notes has no |
1889 | return value, so search for the new insn. */ | |
ef178af3 | 1890 | insn = p; |
2c3c49de | 1891 | while (! INSN_P (insn) || PATTERN (insn) != pat) |
184bb750 R |
1892 | insn = PREV_INSN (insn); |
1893 | ||
1894 | REG_NOTES (insn) = notes; | |
1895 | } | |
1896 | } | |
1897 | /* Sometimes we'd generate src = const; src += n; | |
1898 | if so, replace the instruction that set src | |
1899 | in the first place. */ | |
1900 | ||
1901 | if (! overlap && (code == PLUS || code == MINUS)) | |
1902 | { | |
1903 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
a544cfd2 | 1904 | rtx q, set2 = NULL_RTX; |
184bb750 R |
1905 | int num_calls2 = 0, s_length2 = 0; |
1906 | ||
1907 | if (note && CONSTANT_P (XEXP (note, 0))) | |
1908 | { | |
8e2e89f7 | 1909 | for (q = PREV_INSN (insn); q; q = PREV_INSN (q)) |
184bb750 | 1910 | { |
7bf825d2 JW |
1911 | /* ??? We can't scan past the end of a basic block without |
1912 | updating the register lifetime info | |
a1c1fdd0 RK |
1913 | (REG_DEAD/basic_block_live_at_start). */ |
1914 | if (perhaps_ends_bb_p (q)) | |
7bf825d2 JW |
1915 | { |
1916 | q = 0; | |
1917 | break; | |
1918 | } | |
a1c1fdd0 | 1919 | else if (! INSN_P (q)) |
184bb750 | 1920 | continue; |
a1c1fdd0 | 1921 | |
184bb750 R |
1922 | s_length2++; |
1923 | if (reg_set_p (src, q)) | |
1924 | { | |
1925 | set2 = single_set (q); | |
1926 | break; | |
1927 | } | |
1928 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
1929 | { | |
1930 | q = 0; | |
1931 | break; | |
1932 | } | |
1933 | if (GET_CODE (p) == CALL_INSN) | |
1934 | num_calls2++; | |
1935 | } | |
1936 | if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2)) | |
1937 | && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0)) | |
1938 | { | |
ca6c03ca | 1939 | delete_insn (q); |
184bb750 R |
1940 | REG_N_SETS (REGNO (src))--; |
1941 | REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2; | |
184bb750 R |
1942 | REG_LIVE_LENGTH (REGNO (src)) -= s_length2; |
1943 | insn_const = 0; | |
1944 | } | |
1945 | } | |
1946 | } | |
1a56b81f | 1947 | |
cb084004 | 1948 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
940da324 | 1949 | && (code == PLUS || code == MINUS) && insn_const |
184bb750 R |
1950 | && try_auto_increment (p, insn, 0, src, insn_const, 1)) |
1951 | insn = p; | |
940da324 JL |
1952 | else if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1953 | && post_inc | |
184bb750 R |
1954 | && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0)) |
1955 | post_inc = 0; | |
184bb750 R |
1956 | /* If post_inc still prevails, try to find an |
1957 | insn where it can be used as a pre-in/decrement. | |
1958 | If code is MINUS, this was already tried. */ | |
1959 | if (post_inc && code == PLUS | |
1960 | /* Check that newconst is likely to be usable | |
1961 | in a pre-in/decrement before starting the search. */ | |
940da324 JL |
1962 | && ((HAVE_PRE_INCREMENT && newconst > 0 && newconst <= MOVE_MAX) |
1963 | || (HAVE_PRE_DECREMENT && newconst < 0 && newconst >= -MOVE_MAX)) | |
1964 | && exact_log2 (newconst)) | |
184bb750 R |
1965 | { |
1966 | rtx q, inc_dest; | |
1967 | ||
1968 | inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src; | |
51723711 | 1969 | for (q = post_inc; (q = NEXT_INSN (q)); ) |
184bb750 | 1970 | { |
7bf825d2 | 1971 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 | 1972 | the register lifetime info |
dc297297 | 1973 | (REG_DEAD/basic_block_live_at_start). */ |
a1c1fdd0 | 1974 | if (perhaps_ends_bb_p (q)) |
7bf825d2 | 1975 | break; |
a1c1fdd0 | 1976 | else if (! INSN_P (q)) |
184bb750 | 1977 | continue; |
a1c1fdd0 RK |
1978 | else if (src != inc_dest |
1979 | && (reg_overlap_mentioned_p (src, PATTERN (q)) | |
1980 | || reg_set_p (src, q))) | |
184bb750 | 1981 | break; |
a1c1fdd0 | 1982 | else if (reg_set_p (inc_dest, q)) |
184bb750 | 1983 | break; |
a1c1fdd0 | 1984 | else if (reg_overlap_mentioned_p (inc_dest, PATTERN (q))) |
184bb750 R |
1985 | { |
1986 | try_auto_increment (q, post_inc, | |
1987 | post_inc_set, inc_dest, newconst, 1); | |
1988 | break; | |
1989 | } | |
1990 | } | |
1991 | } | |
a1c1fdd0 | 1992 | |
184bb750 R |
1993 | /* Move the death note for DST to INSN if it is used |
1994 | there. */ | |
1995 | if (reg_overlap_mentioned_p (dst, PATTERN (insn))) | |
1996 | { | |
1997 | XEXP (dst_note, 1) = REG_NOTES (insn); | |
1998 | REG_NOTES (insn) = dst_note; | |
1999 | } | |
2000 | ||
2001 | if (src_note) | |
2002 | { | |
2003 | /* Move the death note for SRC from INSN to P. */ | |
2004 | if (! overlap) | |
2005 | remove_note (insn, src_note); | |
2006 | XEXP (src_note, 1) = REG_NOTES (p); | |
2007 | REG_NOTES (p) = src_note; | |
2008 | ||
2009 | REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls; | |
2010 | } | |
2011 | ||
2012 | REG_N_SETS (REGNO (src))++; | |
2013 | REG_N_SETS (REGNO (dst))--; | |
2014 | ||
2015 | REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls; | |
2016 | ||
2017 | REG_LIVE_LENGTH (REGNO (src)) += s_length; | |
2018 | if (REG_LIVE_LENGTH (REGNO (dst)) >= 0) | |
2019 | { | |
2020 | REG_LIVE_LENGTH (REGNO (dst)) -= length; | |
2021 | /* REG_LIVE_LENGTH is only an approximation after | |
2022 | combine if sched is not run, so make sure that we | |
2023 | still have a reasonable value. */ | |
2024 | if (REG_LIVE_LENGTH (REGNO (dst)) < 2) | |
2025 | REG_LIVE_LENGTH (REGNO (dst)) = 2; | |
2026 | } | |
184bb750 R |
2027 | if (regmove_dump_file) |
2028 | fprintf (regmove_dump_file, | |
2029 | "Fixed operand %d of insn %d matching operand %d.\n", | |
2030 | operand_number, INSN_UID (insn), match_number); | |
2031 | return 1; | |
2032 | } | |
2033 | ||
2034 | ||
beb235f8 | 2035 | /* Return nonzero if X is stable and mentions no registers but for |
18bf656f R |
2036 | mentioning SRC or mentioning / changing DST . If in doubt, presume |
2037 | it is unstable. | |
2038 | The rationale is that we want to check if we can move an insn easily | |
2039 | while just paying attention to SRC and DST. A register is considered | |
2040 | stable if it has the RTX_UNCHANGING_P bit set, but that would still | |
2041 | leave the burden to update REG_DEAD / REG_UNUSED notes, so we don't | |
2042 | want any registers but SRC and DST. */ | |
8c660648 | 2043 | static int |
0c20a65f | 2044 | stable_and_no_regs_but_for_p (rtx x, rtx src, rtx dst) |
8c660648 JL |
2045 | { |
2046 | RTX_CODE code = GET_CODE (x); | |
2047 | switch (GET_RTX_CLASS (code)) | |
2048 | { | |
ec8e098d PB |
2049 | case RTX_UNARY: |
2050 | case RTX_BIN_ARITH: | |
2051 | case RTX_COMM_ARITH: | |
2052 | case RTX_COMPARE: | |
2053 | case RTX_COMM_COMPARE: | |
2054 | case RTX_TERNARY: | |
2055 | case RTX_BITFIELD_OPS: | |
8c660648 JL |
2056 | { |
2057 | int i; | |
6f7d635c | 2058 | const char *fmt = GET_RTX_FORMAT (code); |
8c660648 | 2059 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
18bf656f R |
2060 | if (fmt[i] == 'e' |
2061 | && ! stable_and_no_regs_but_for_p (XEXP (x, i), src, dst)) | |
8c660648 JL |
2062 | return 0; |
2063 | return 1; | |
2064 | } | |
ec8e098d | 2065 | case RTX_OBJ: |
18bf656f R |
2066 | if (code == REG) |
2067 | return x == src || x == dst; | |
2068 | /* If this is a MEM, look inside - there might be a register hidden in | |
2069 | the address of an unchanging MEM. */ | |
2070 | if (code == MEM | |
2071 | && ! stable_and_no_regs_but_for_p (XEXP (x, 0), src, dst)) | |
2072 | return 0; | |
938d968e | 2073 | /* Fall through. */ |
8c660648 JL |
2074 | default: |
2075 | return ! rtx_unstable_p (x); | |
2076 | } | |
2077 | } | |
1e7f0a48 | 2078 | \f |
174fa2c4 | 2079 | /* Track stack adjustments and stack memory references. Attempt to |
a1f300c0 | 2080 | reduce the number of stack adjustments by back-propagating across |
1e7f0a48 RH |
2081 | the memory references. |
2082 | ||
2083 | This is intended primarily for use with targets that do not define | |
2084 | ACCUMULATE_OUTGOING_ARGS. It is of significantly more value to | |
2085 | targets that define PREFERRED_STACK_BOUNDARY more aligned than | |
2086 | STACK_BOUNDARY (e.g. x86), or if not all registers can be pushed | |
2087 | (e.g. x86 fp regs) which would ordinarily have to be implemented | |
2088 | as a sub/mov pair due to restrictions in calls.c. | |
2089 | ||
a1f300c0 | 2090 | Propagation stops when any of the insns that need adjusting are |
1e7f0a48 RH |
2091 | (a) no longer valid because we've exceeded their range, (b) a |
2092 | non-trivial push instruction, or (c) a call instruction. | |
2093 | ||
2094 | Restriction B is based on the assumption that push instructions | |
2095 | are smaller or faster. If a port really wants to remove all | |
2096 | pushes, it should have defined ACCUMULATE_OUTGOING_ARGS. The | |
2097 | one exception that is made is for an add immediately followed | |
2098 | by a push. */ | |
2099 | ||
2100 | /* This structure records stack memory references between stack adjusting | |
2101 | instructions. */ | |
2102 | ||
2103 | struct csa_memlist | |
2104 | { | |
2105 | HOST_WIDE_INT sp_offset; | |
5a97f7c2 | 2106 | rtx insn, *mem; |
1e7f0a48 RH |
2107 | struct csa_memlist *next; |
2108 | }; | |
2109 | ||
0c20a65f AJ |
2110 | static int stack_memref_p (rtx); |
2111 | static rtx single_set_for_csa (rtx); | |
2112 | static void free_csa_memlist (struct csa_memlist *); | |
2113 | static struct csa_memlist *record_one_stack_memref (rtx, rtx *, | |
2114 | struct csa_memlist *); | |
2115 | static int try_apply_stack_adjustment (rtx, struct csa_memlist *, | |
2116 | HOST_WIDE_INT, HOST_WIDE_INT); | |
2117 | static void combine_stack_adjustments_for_block (basic_block); | |
2118 | static int record_stack_memrefs (rtx *, void *); | |
1e7f0a48 RH |
2119 | |
2120 | ||
2121 | /* Main entry point for stack adjustment combination. */ | |
2122 | ||
2123 | void | |
0c20a65f | 2124 | combine_stack_adjustments (void) |
1e7f0a48 | 2125 | { |
e0082a72 | 2126 | basic_block bb; |
1e7f0a48 | 2127 | |
e0082a72 ZD |
2128 | FOR_EACH_BB (bb) |
2129 | combine_stack_adjustments_for_block (bb); | |
1e7f0a48 RH |
2130 | } |
2131 | ||
2132 | /* Recognize a MEM of the form (sp) or (plus sp const). */ | |
2133 | ||
2134 | static int | |
0c20a65f | 2135 | stack_memref_p (rtx x) |
1e7f0a48 | 2136 | { |
9e11785b RH |
2137 | if (GET_CODE (x) != MEM) |
2138 | return 0; | |
2139 | x = XEXP (x, 0); | |
2140 | ||
2141 | if (x == stack_pointer_rtx) | |
2142 | return 1; | |
2143 | if (GET_CODE (x) == PLUS | |
2144 | && XEXP (x, 0) == stack_pointer_rtx | |
2145 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2146 | return 1; | |
2147 | ||
2148 | return 0; | |
1e7f0a48 RH |
2149 | } |
2150 | ||
2151 | /* Recognize either normal single_set or the hack in i386.md for | |
2152 | tying fp and sp adjustments. */ | |
2153 | ||
2154 | static rtx | |
0c20a65f | 2155 | single_set_for_csa (rtx insn) |
1e7f0a48 RH |
2156 | { |
2157 | int i; | |
2158 | rtx tmp = single_set (insn); | |
2159 | if (tmp) | |
2160 | return tmp; | |
2161 | ||
2162 | if (GET_CODE (insn) != INSN | |
2163 | || GET_CODE (PATTERN (insn)) != PARALLEL) | |
2164 | return NULL_RTX; | |
2165 | ||
2166 | tmp = PATTERN (insn); | |
2167 | if (GET_CODE (XVECEXP (tmp, 0, 0)) != SET) | |
2168 | return NULL_RTX; | |
2169 | ||
2170 | for (i = 1; i < XVECLEN (tmp, 0); ++i) | |
2171 | { | |
2172 | rtx this = XVECEXP (tmp, 0, i); | |
2173 | ||
2174 | /* The special case is allowing a no-op set. */ | |
2175 | if (GET_CODE (this) == SET | |
2176 | && SET_SRC (this) == SET_DEST (this)) | |
2177 | ; | |
2178 | else if (GET_CODE (this) != CLOBBER | |
2179 | && GET_CODE (this) != USE) | |
2180 | return NULL_RTX; | |
2181 | } | |
2182 | ||
2183 | return XVECEXP (tmp, 0, 0); | |
2184 | } | |
2185 | ||
2186 | /* Free the list of csa_memlist nodes. */ | |
2187 | ||
2188 | static void | |
0c20a65f | 2189 | free_csa_memlist (struct csa_memlist *memlist) |
1e7f0a48 RH |
2190 | { |
2191 | struct csa_memlist *next; | |
2192 | for (; memlist ; memlist = next) | |
2193 | { | |
2194 | next = memlist->next; | |
2195 | free (memlist); | |
2196 | } | |
2197 | } | |
2198 | ||
2199 | /* Create a new csa_memlist node from the given memory reference. | |
2200 | It is already known that the memory is stack_memref_p. */ | |
2201 | ||
2202 | static struct csa_memlist * | |
0c20a65f | 2203 | record_one_stack_memref (rtx insn, rtx *mem, struct csa_memlist *next_memlist) |
1e7f0a48 RH |
2204 | { |
2205 | struct csa_memlist *ml; | |
2206 | ||
703ad42b | 2207 | ml = xmalloc (sizeof (*ml)); |
1e7f0a48 | 2208 | |
5a97f7c2 | 2209 | if (XEXP (*mem, 0) == stack_pointer_rtx) |
1e7f0a48 RH |
2210 | ml->sp_offset = 0; |
2211 | else | |
5a97f7c2 | 2212 | ml->sp_offset = INTVAL (XEXP (XEXP (*mem, 0), 1)); |
1e7f0a48 RH |
2213 | |
2214 | ml->insn = insn; | |
2215 | ml->mem = mem; | |
2216 | ml->next = next_memlist; | |
2217 | ||
2218 | return ml; | |
2219 | } | |
2220 | ||
2221 | /* Attempt to apply ADJUST to the stack adjusting insn INSN, as well | |
2222 | as each of the memories in MEMLIST. Return true on success. */ | |
2223 | ||
2224 | static int | |
0c20a65f AJ |
2225 | try_apply_stack_adjustment (rtx insn, struct csa_memlist *memlist, HOST_WIDE_INT new_adjust, |
2226 | HOST_WIDE_INT delta) | |
1e7f0a48 RH |
2227 | { |
2228 | struct csa_memlist *ml; | |
2229 | rtx set; | |
2230 | ||
1e7f0a48 RH |
2231 | set = single_set_for_csa (insn); |
2232 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (new_adjust), 1); | |
2233 | ||
2234 | for (ml = memlist; ml ; ml = ml->next) | |
f1ec5147 RK |
2235 | validate_change |
2236 | (ml->insn, ml->mem, | |
2237 | replace_equiv_address_nv (*ml->mem, | |
2238 | plus_constant (stack_pointer_rtx, | |
2239 | ml->sp_offset - delta)), 1); | |
1e7f0a48 RH |
2240 | |
2241 | if (apply_change_group ()) | |
2242 | { | |
2243 | /* Succeeded. Update our knowledge of the memory references. */ | |
2244 | for (ml = memlist; ml ; ml = ml->next) | |
2245 | ml->sp_offset -= delta; | |
2246 | ||
2247 | return 1; | |
2248 | } | |
2249 | else | |
2250 | return 0; | |
2251 | } | |
2252 | ||
a2ee8430 JH |
2253 | /* Called via for_each_rtx and used to record all stack memory references in |
2254 | the insn and discard all other stack pointer references. */ | |
2255 | struct record_stack_memrefs_data | |
2256 | { | |
2257 | rtx insn; | |
2258 | struct csa_memlist *memlist; | |
2259 | }; | |
2260 | ||
2261 | static int | |
0c20a65f | 2262 | record_stack_memrefs (rtx *xp, void *data) |
a2ee8430 JH |
2263 | { |
2264 | rtx x = *xp; | |
2265 | struct record_stack_memrefs_data *d = | |
2266 | (struct record_stack_memrefs_data *) data; | |
2267 | if (!x) | |
2268 | return 0; | |
2269 | switch (GET_CODE (x)) | |
2270 | { | |
2271 | case MEM: | |
2272 | if (!reg_mentioned_p (stack_pointer_rtx, x)) | |
2273 | return -1; | |
2274 | /* We are not able to handle correctly all possible memrefs containing | |
f63d1bf7 | 2275 | stack pointer, so this check is necessary. */ |
a2ee8430 JH |
2276 | if (stack_memref_p (x)) |
2277 | { | |
2278 | d->memlist = record_one_stack_memref (d->insn, xp, d->memlist); | |
2279 | return -1; | |
2280 | } | |
2281 | return 1; | |
2282 | case REG: | |
d60e5448 | 2283 | /* ??? We want be able to handle non-memory stack pointer |
e0bb17a8 | 2284 | references later. For now just discard all insns referring to |
d60e5448 MM |
2285 | stack pointer outside mem expressions. We would probably |
2286 | want to teach validate_replace to simplify expressions first. | |
2287 | ||
2288 | We can't just compare with STACK_POINTER_RTX because the | |
2289 | reference to the stack pointer might be in some other mode. | |
14b493d6 | 2290 | In particular, an explicit clobber in an asm statement will |
e0bb17a8 | 2291 | result in a QImode clobber. */ |
d60e5448 | 2292 | if (REGNO (x) == STACK_POINTER_REGNUM) |
a2ee8430 JH |
2293 | return 1; |
2294 | break; | |
2295 | default: | |
2296 | break; | |
2297 | } | |
2298 | return 0; | |
2299 | } | |
2300 | ||
1e7f0a48 RH |
2301 | /* Subroutine of combine_stack_adjustments, called for each basic block. */ |
2302 | ||
174fa2c4 | 2303 | static void |
0c20a65f | 2304 | combine_stack_adjustments_for_block (basic_block bb) |
1e7f0a48 RH |
2305 | { |
2306 | HOST_WIDE_INT last_sp_adjust = 0; | |
2307 | rtx last_sp_set = NULL_RTX; | |
2308 | struct csa_memlist *memlist = NULL; | |
78414d74 | 2309 | rtx insn, next, set; |
a2ee8430 | 2310 | struct record_stack_memrefs_data data; |
78414d74 | 2311 | bool end_of_block = false; |
1e7f0a48 | 2312 | |
a813c111 | 2313 | for (insn = BB_HEAD (bb); !end_of_block ; insn = next) |
1e7f0a48 | 2314 | { |
a813c111 | 2315 | end_of_block = insn == BB_END (bb); |
1e7f0a48 RH |
2316 | next = NEXT_INSN (insn); |
2317 | ||
a2ee8430 | 2318 | if (! INSN_P (insn)) |
78414d74 | 2319 | continue; |
1e7f0a48 RH |
2320 | |
2321 | set = single_set_for_csa (insn); | |
2322 | if (set) | |
2323 | { | |
2324 | rtx dest = SET_DEST (set); | |
2325 | rtx src = SET_SRC (set); | |
2326 | ||
2327 | /* Find constant additions to the stack pointer. */ | |
2328 | if (dest == stack_pointer_rtx | |
2329 | && GET_CODE (src) == PLUS | |
2330 | && XEXP (src, 0) == stack_pointer_rtx | |
2331 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2332 | { | |
2333 | HOST_WIDE_INT this_adjust = INTVAL (XEXP (src, 1)); | |
2334 | ||
2335 | /* If we've not seen an adjustment previously, record | |
2336 | it now and continue. */ | |
2337 | if (! last_sp_set) | |
2338 | { | |
2339 | last_sp_set = insn; | |
2340 | last_sp_adjust = this_adjust; | |
78414d74 | 2341 | continue; |
1e7f0a48 RH |
2342 | } |
2343 | ||
2344 | /* If not all recorded memrefs can be adjusted, or the | |
2345 | adjustment is now too large for a constant addition, | |
595c2290 JH |
2346 | we cannot merge the two stack adjustments. |
2347 | ||
14b493d6 | 2348 | Also we need to be careful to not move stack pointer |
595c2290 JH |
2349 | such that we create stack accesses outside the allocated |
2350 | area. We can combine an allocation into the first insn, | |
2351 | or a deallocation into the second insn. We can not | |
2352 | combine an allocation followed by a deallocation. | |
2353 | ||
ff7cc307 | 2354 | The only somewhat frequent occurrence of the later is when |
595c2290 JH |
2355 | a function allocates a stack frame but does not use it. |
2356 | For this case, we would need to analyze rtl stream to be | |
2357 | sure that allocated area is really unused. This means not | |
2358 | only checking the memory references, but also all registers | |
2359 | or global memory references possibly containing a stack | |
2360 | frame address. | |
2361 | ||
2362 | Perhaps the best way to address this problem is to teach | |
2363 | gcc not to allocate stack for objects never used. */ | |
2364 | ||
2365 | /* Combine an allocation into the first instruction. */ | |
2366 | if (STACK_GROWS_DOWNWARD ? this_adjust <= 0 : this_adjust >= 0) | |
1e7f0a48 | 2367 | { |
595c2290 JH |
2368 | if (try_apply_stack_adjustment (last_sp_set, memlist, |
2369 | last_sp_adjust + this_adjust, | |
2370 | this_adjust)) | |
2371 | { | |
2372 | /* It worked! */ | |
78414d74 | 2373 | delete_insn (insn); |
595c2290 | 2374 | last_sp_adjust += this_adjust; |
78414d74 | 2375 | continue; |
595c2290 | 2376 | } |
1e7f0a48 RH |
2377 | } |
2378 | ||
595c2290 JH |
2379 | /* Otherwise we have a deallocation. Do not combine with |
2380 | a previous allocation. Combine into the second insn. */ | |
2381 | else if (STACK_GROWS_DOWNWARD | |
2382 | ? last_sp_adjust >= 0 : last_sp_adjust <= 0) | |
1e7f0a48 | 2383 | { |
595c2290 JH |
2384 | if (try_apply_stack_adjustment (insn, memlist, |
2385 | last_sp_adjust + this_adjust, | |
2386 | -last_sp_adjust)) | |
2387 | { | |
2388 | /* It worked! */ | |
53c17031 | 2389 | delete_insn (last_sp_set); |
595c2290 JH |
2390 | last_sp_set = insn; |
2391 | last_sp_adjust += this_adjust; | |
2392 | free_csa_memlist (memlist); | |
2393 | memlist = NULL; | |
78414d74 | 2394 | continue; |
595c2290 | 2395 | } |
1e7f0a48 RH |
2396 | } |
2397 | ||
78414d74 RS |
2398 | /* Combination failed. Restart processing from here. If |
2399 | deallocation+allocation conspired to cancel, we can | |
2400 | delete the old deallocation insn. */ | |
2401 | if (last_sp_set && last_sp_adjust == 0) | |
2402 | delete_insn (insn); | |
595c2290 JH |
2403 | free_csa_memlist (memlist); |
2404 | memlist = NULL; | |
2405 | last_sp_set = insn; | |
2406 | last_sp_adjust = this_adjust; | |
78414d74 | 2407 | continue; |
1e7f0a48 RH |
2408 | } |
2409 | ||
1e7f0a48 RH |
2410 | /* Find a predecrement of exactly the previous adjustment and |
2411 | turn it into a direct store. Obviously we can't do this if | |
2412 | there were any intervening uses of the stack pointer. */ | |
2413 | if (memlist == NULL | |
1e7f0a48 | 2414 | && GET_CODE (dest) == MEM |
756d6f0c JH |
2415 | && ((GET_CODE (XEXP (dest, 0)) == PRE_DEC |
2416 | && (last_sp_adjust | |
2417 | == (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (dest)))) | |
2418 | || (GET_CODE (XEXP (dest, 0)) == PRE_MODIFY | |
2419 | && GET_CODE (XEXP (XEXP (dest, 0), 1)) == PLUS | |
2420 | && XEXP (XEXP (XEXP (dest, 0), 1), 0) == stack_pointer_rtx | |
2421 | && (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1)) | |
2422 | == CONST_INT) | |
2423 | && (INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1)) | |
2424 | == -last_sp_adjust))) | |
1e7f0a48 | 2425 | && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx |
9e11785b | 2426 | && ! reg_mentioned_p (stack_pointer_rtx, src) |
5d64361b | 2427 | && memory_address_p (GET_MODE (dest), stack_pointer_rtx) |
1e7f0a48 | 2428 | && validate_change (insn, &SET_DEST (set), |
792760b9 RK |
2429 | replace_equiv_address (dest, |
2430 | stack_pointer_rtx), | |
2431 | 0)) | |
1e7f0a48 | 2432 | { |
53c17031 | 2433 | delete_insn (last_sp_set); |
1e7f0a48 RH |
2434 | free_csa_memlist (memlist); |
2435 | memlist = NULL; | |
2436 | last_sp_set = NULL_RTX; | |
2437 | last_sp_adjust = 0; | |
78414d74 | 2438 | continue; |
1e7f0a48 RH |
2439 | } |
2440 | } | |
2441 | ||
a2ee8430 JH |
2442 | data.insn = insn; |
2443 | data.memlist = memlist; | |
2444 | if (GET_CODE (insn) != CALL_INSN && last_sp_set | |
2445 | && !for_each_rtx (&PATTERN (insn), record_stack_memrefs, &data)) | |
2446 | { | |
2447 | memlist = data.memlist; | |
78414d74 | 2448 | continue; |
a2ee8430 JH |
2449 | } |
2450 | memlist = data.memlist; | |
2451 | ||
174fa2c4 | 2452 | /* Otherwise, we were not able to process the instruction. |
1e7f0a48 RH |
2453 | Do not continue collecting data across such a one. */ |
2454 | if (last_sp_set | |
2455 | && (GET_CODE (insn) == CALL_INSN | |
2456 | || reg_mentioned_p (stack_pointer_rtx, PATTERN (insn)))) | |
2457 | { | |
78414d74 RS |
2458 | if (last_sp_set && last_sp_adjust == 0) |
2459 | delete_insn (last_sp_set); | |
1e7f0a48 RH |
2460 | free_csa_memlist (memlist); |
2461 | memlist = NULL; | |
2462 | last_sp_set = NULL_RTX; | |
2463 | last_sp_adjust = 0; | |
2464 | } | |
1e7f0a48 RH |
2465 | } |
2466 | ||
78414d74 RS |
2467 | if (last_sp_set && last_sp_adjust == 0) |
2468 | delete_insn (last_sp_set); | |
1e7f0a48 | 2469 | } |