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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
29a82058 | 2 | Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
670ee920 | 27 | #include "system.h" |
54dac99e RK |
28 | #include "rtl.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "flags.h" | |
31 | #include "basic-block.h" | |
32 | #include "regs.h" | |
33 | #include "insn-config.h" | |
34 | #include "recog.h" | |
e4600702 RK |
35 | #include "reload.h" |
36 | #include "real.h" | |
10f0ad3d | 37 | #include "toplev.h" |
d6f4ec51 | 38 | #include "output.h" |
54dac99e RK |
39 | |
40 | #ifndef REGISTER_MOVE_COST | |
41 | #define REGISTER_MOVE_COST(x, y) 2 | |
42 | #endif | |
43 | ||
24deb20a L |
44 | static void init_reg_sets_1 PROTO((void)); |
45 | static void init_reg_modes PROTO((void)); | |
46 | ||
533d0835 RK |
47 | /* If we have auto-increment or auto-decrement and we can have secondary |
48 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 49 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
50 | |
51 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 52 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
53 | #define FORBIDDEN_INC_DEC_CLASSES |
54 | #endif | |
55 | #endif | |
54dac99e RK |
56 | \f |
57 | /* Register tables used by many passes. */ | |
58 | ||
59 | /* Indexed by hard register number, contains 1 for registers | |
60 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
61 | These are the registers that cannot be used to allocate | |
252f342a | 62 | a pseudo reg for general use. */ |
54dac99e RK |
63 | |
64 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
65 | ||
66 | /* Same info as a HARD_REG_SET. */ | |
67 | ||
68 | HARD_REG_SET fixed_reg_set; | |
69 | ||
70 | /* Data for initializing the above. */ | |
71 | ||
72 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
73 | ||
74 | /* Indexed by hard register number, contains 1 for registers | |
75 | that are fixed use or are clobbered by function calls. | |
76 | These are the registers that cannot be used to allocate | |
252f342a MH |
77 | a pseudo reg whose life crosses calls unless we are able |
78 | to save/restore them across the calls. */ | |
54dac99e RK |
79 | |
80 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
81 | ||
82 | /* Same info as a HARD_REG_SET. */ | |
83 | ||
84 | HARD_REG_SET call_used_reg_set; | |
85 | ||
6cad67d2 JL |
86 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
87 | HARD_REG_SET losing_caller_save_reg_set; | |
88 | ||
54dac99e RK |
89 | /* Data for initializing the above. */ |
90 | ||
91 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
92 | ||
93 | /* Indexed by hard register number, contains 1 for registers that are | |
252f342a MH |
94 | fixed use or call used registers that cannot hold quantities across |
95 | calls even if we are willing to save and restore them. call fixed | |
96 | registers are a subset of call used registers. */ | |
54dac99e RK |
97 | |
98 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
99 | ||
100 | /* The same info as a HARD_REG_SET. */ | |
101 | ||
102 | HARD_REG_SET call_fixed_reg_set; | |
103 | ||
104 | /* Number of non-fixed registers. */ | |
105 | ||
106 | int n_non_fixed_regs; | |
107 | ||
108 | /* Indexed by hard register number, contains 1 for registers | |
109 | that are being used for global register decls. | |
110 | These must be exempt from ordinary flow analysis | |
111 | and are also considered fixed. */ | |
112 | ||
113 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
114 | ||
115 | /* Table of register numbers in the order in which to try to use them. */ | |
116 | #ifdef REG_ALLOC_ORDER | |
117 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
118 | #endif | |
119 | ||
120 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
121 | ||
2e0e2b76 CH |
122 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
123 | ||
089e575b RS |
124 | /* The same information, but as an array of unsigned ints. We copy from |
125 | these unsigned ints to the table above. We do this so the tm.h files | |
126 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
127 | |
128 | #define N_REG_INTS \ | |
129 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
130 | ||
089e575b | 131 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 132 | = REG_CLASS_CONTENTS; |
54dac99e RK |
133 | |
134 | /* For each reg class, number of regs it contains. */ | |
135 | ||
136 | int reg_class_size[N_REG_CLASSES]; | |
137 | ||
138 | /* For each reg class, table listing all the containing classes. */ | |
139 | ||
140 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
141 | ||
142 | /* For each reg class, table listing all the classes contained in it. */ | |
143 | ||
144 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
145 | ||
146 | /* For each pair of reg classes, | |
147 | a largest reg class contained in their union. */ | |
148 | ||
149 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
150 | ||
151 | /* For each pair of reg classes, | |
152 | the smallest reg class containing their union. */ | |
153 | ||
154 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
155 | ||
d05c8ee7 RS |
156 | /* Array containing all of the register names */ |
157 | ||
158 | char *reg_names[] = REGISTER_NAMES; | |
159 | ||
ca4aac00 DE |
160 | /* For each hard register, the widest mode object that it can contain. |
161 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
162 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
163 | register. */ | |
164 | ||
165 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
166 | ||
e4600702 RK |
167 | /* Maximum cost of moving from a register in one class to a register in |
168 | another class. Based on REGISTER_MOVE_COST. */ | |
169 | ||
170 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
171 | ||
172 | /* Similar, but here we don't have to move if the first index is a subset | |
173 | of the second so in that case the cost is zero. */ | |
174 | ||
175 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
176 | ||
533d0835 RK |
177 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
178 | ||
179 | /* These are the classes that regs which are auto-incremented or decremented | |
180 | cannot be put in. */ | |
181 | ||
182 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
183 | ||
184 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
185 | context. */ | |
186 | ||
187 | static char *in_inc_dec; | |
188 | ||
5fcb671c | 189 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 190 | |
473fe49b KR |
191 | #ifdef HAVE_SECONDARY_RELOADS |
192 | ||
193 | /* Sample MEM values for use by memory_move_secondary_cost. */ | |
194 | ||
195 | static rtx top_of_stack[MAX_MACHINE_MODE]; | |
196 | ||
197 | #endif /* HAVE_SECONDARY_RELOADS */ | |
198 | ||
6feacd09 MM |
199 | /* Linked list of reg_info structures allocated for reg_n_info array. |
200 | Grouping all of the allocated structures together in one lump | |
201 | means only one call to bzero to clear them, rather than n smaller | |
202 | calls. */ | |
203 | struct reg_info_data { | |
204 | struct reg_info_data *next; /* next set of reg_info structures */ | |
205 | size_t min_index; /* minimum index # */ | |
206 | size_t max_index; /* maximum index # */ | |
207 | char used_p; /* non-zero if this has been used previously */ | |
208 | reg_info data[1]; /* beginning of the reg_info data */ | |
209 | }; | |
210 | ||
211 | static struct reg_info_data *reg_info_head; | |
212 | ||
213 | ||
54dac99e RK |
214 | /* Function called only once to initialize the above data on reg usage. |
215 | Once this is done, various switches may override. */ | |
216 | ||
217 | void | |
218 | init_reg_sets () | |
219 | { | |
220 | register int i, j; | |
221 | ||
2e0e2b76 CH |
222 | /* First copy the register information from the initial int form into |
223 | the regsets. */ | |
224 | ||
225 | for (i = 0; i < N_REG_CLASSES; i++) | |
226 | { | |
227 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
228 | ||
229 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
230 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 231 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
232 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
233 | } | |
234 | ||
54dac99e RK |
235 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
236 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
237 | bzero (global_regs, sizeof global_regs); | |
238 | ||
910bc42d R |
239 | /* Do any additional initialization regsets may need */ |
240 | INIT_ONCE_REG_SET (); | |
241 | } | |
242 | ||
243 | /* After switches have been processed, which perhaps alter | |
244 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
245 | ||
246 | static void | |
247 | init_reg_sets_1 () | |
248 | { | |
249 | register unsigned int i, j; | |
250 | ||
251 | /* This macro allows the fixed or call-used registers | |
252 | and the register classes to depend on target flags. */ | |
253 | ||
254 | #ifdef CONDITIONAL_REGISTER_USAGE | |
255 | CONDITIONAL_REGISTER_USAGE; | |
256 | #endif | |
257 | ||
54dac99e RK |
258 | /* Compute number of hard regs in each class. */ |
259 | ||
4c9a05bc | 260 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
261 | for (i = 0; i < N_REG_CLASSES; i++) |
262 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
263 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
264 | reg_class_size[i]++; | |
265 | ||
266 | /* Initialize the table of subunions. | |
267 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
268 | that is contained in the union of classes I and J. */ | |
269 | ||
270 | for (i = 0; i < N_REG_CLASSES; i++) | |
271 | { | |
272 | for (j = 0; j < N_REG_CLASSES; j++) | |
273 | { | |
274 | #ifdef HARD_REG_SET | |
275 | register /* Declare it register if it's a scalar. */ | |
276 | #endif | |
277 | HARD_REG_SET c; | |
278 | register int k; | |
279 | ||
280 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
281 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
282 | for (k = 0; k < N_REG_CLASSES; k++) | |
283 | { | |
284 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
285 | subclass1); | |
286 | continue; | |
287 | ||
288 | subclass1: | |
289 | /* keep the largest subclass */ /* SPEE 900308 */ | |
290 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
291 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
292 | subclass2); | |
293 | reg_class_subunion[i][j] = (enum reg_class) k; | |
294 | subclass2: | |
295 | ; | |
296 | } | |
297 | } | |
298 | } | |
299 | ||
300 | /* Initialize the table of superunions. | |
301 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
302 | containing the union of classes I and J. */ | |
303 | ||
304 | for (i = 0; i < N_REG_CLASSES; i++) | |
305 | { | |
306 | for (j = 0; j < N_REG_CLASSES; j++) | |
307 | { | |
308 | #ifdef HARD_REG_SET | |
309 | register /* Declare it register if it's a scalar. */ | |
310 | #endif | |
311 | HARD_REG_SET c; | |
312 | register int k; | |
313 | ||
314 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
315 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
316 | for (k = 0; k < N_REG_CLASSES; k++) | |
317 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
318 | ||
319 | superclass: | |
320 | reg_class_superunion[i][j] = (enum reg_class) k; | |
321 | } | |
322 | } | |
323 | ||
324 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
325 | First clear the whole table, then add the elements as they are found. */ | |
326 | ||
327 | for (i = 0; i < N_REG_CLASSES; i++) | |
328 | { | |
329 | for (j = 0; j < N_REG_CLASSES; j++) | |
330 | { | |
331 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
332 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
333 | } | |
334 | } | |
335 | ||
336 | for (i = 0; i < N_REG_CLASSES; i++) | |
337 | { | |
338 | if (i == (int) NO_REGS) | |
339 | continue; | |
340 | ||
341 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
342 | { | |
343 | enum reg_class *p; | |
344 | ||
345 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
346 | subclass); | |
347 | continue; | |
348 | subclass: | |
349 | /* Reg class I is a subclass of J. | |
350 | Add J to the table of superclasses of I. */ | |
351 | p = ®_class_superclasses[i][0]; | |
352 | while (*p != LIM_REG_CLASSES) p++; | |
353 | *p = (enum reg_class) j; | |
354 | /* Add I to the table of superclasses of J. */ | |
355 | p = ®_class_subclasses[j][0]; | |
356 | while (*p != LIM_REG_CLASSES) p++; | |
357 | *p = (enum reg_class) i; | |
358 | } | |
359 | } | |
e4600702 | 360 | |
54dac99e RK |
361 | /* Initialize "constant" tables. */ |
362 | ||
363 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
364 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
365 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
366 | ||
367 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
368 | |
369 | n_non_fixed_regs = 0; | |
370 | ||
371 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
372 | { | |
54dac99e RK |
373 | if (fixed_regs[i]) |
374 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
375 | else | |
376 | n_non_fixed_regs++; | |
377 | ||
378 | if (call_used_regs[i]) | |
379 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
380 | if (call_fixed_regs[i]) | |
381 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
382 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
383 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 384 | } |
acbce667 KR |
385 | |
386 | /* Initialize the move cost table. Find every subset of each class | |
387 | and take the maximum cost of moving any subset to any other. */ | |
388 | ||
389 | for (i = 0; i < N_REG_CLASSES; i++) | |
390 | for (j = 0; j < N_REG_CLASSES; j++) | |
391 | { | |
392 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
393 | enum reg_class *p1, *p2; | |
394 | ||
395 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
396 | if (*p2 != i) | |
397 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
398 | ||
399 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
400 | { | |
401 | if (*p1 != j) | |
402 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
403 | ||
404 | for (p2 = ®_class_subclasses[j][0]; | |
405 | *p2 != LIM_REG_CLASSES; p2++) | |
406 | if (*p1 != *p2) | |
407 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
408 | } | |
409 | ||
410 | move_cost[i][j] = cost; | |
411 | ||
412 | if (reg_class_subset_p (i, j)) | |
413 | cost = 0; | |
414 | ||
415 | may_move_cost[i][j] = cost; | |
416 | } | |
c27c5281 DE |
417 | } |
418 | ||
419 | /* Compute the table of register modes. | |
420 | These values are used to record death information for individual registers | |
421 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 422 | |
c27c5281 DE |
423 | static void |
424 | init_reg_modes () | |
425 | { | |
426 | register int i; | |
ca4aac00 DE |
427 | |
428 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
429 | { |
430 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
431 | ||
066c2fea | 432 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
433 | ??? One situation in which we need to do this is on the mips where |
434 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
435 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 436 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 437 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 438 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 439 | } |
ca4aac00 DE |
440 | } |
441 | ||
c27c5281 DE |
442 | /* Finish initializing the register sets and |
443 | initialize the register modes. */ | |
444 | ||
445 | void | |
446 | init_regs () | |
447 | { | |
448 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
449 | until after register usage was specified. */ | |
b93a436e | 450 | init_reg_sets_1 (); |
c27c5281 DE |
451 | |
452 | init_reg_modes (); | |
473fe49b KR |
453 | |
454 | #ifdef HAVE_SECONDARY_RELOADS | |
455 | { | |
456 | /* Make some fake stack-frame MEM references for use in | |
457 | memory_move_secondary_cost. */ | |
458 | int i; | |
459 | for (i = 0; i < MAX_MACHINE_MODE; i++) | |
9ec36da5 | 460 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
461 | } |
462 | #endif | |
c27c5281 DE |
463 | } |
464 | ||
cbd5b9a2 | 465 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 466 | |
cbd5b9a2 KR |
467 | /* Compute extra cost of moving registers to/from memory due to reloads. |
468 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 469 | |
cbd5b9a2 KR |
470 | int |
471 | memory_move_secondary_cost (mode, class, in) | |
472 | enum machine_mode mode; | |
473 | enum reg_class class; | |
474 | int in; | |
475 | { | |
476 | enum reg_class altclass; | |
477 | int partial_cost = 0; | |
cbd5b9a2 | 478 | /* We need a memory reference to feed to SECONDARY... macros. */ |
473fe49b | 479 | rtx mem = top_of_stack[(int) mode]; |
cbd5b9a2 KR |
480 | |
481 | if (in) | |
473fe49b | 482 | { |
321c0828 | 483 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 484 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 485 | #else |
473fe49b | 486 | altclass = NO_REGS; |
321c0828 | 487 | #endif |
473fe49b | 488 | } |
cbd5b9a2 | 489 | else |
473fe49b | 490 | { |
321c0828 | 491 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 492 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 493 | #else |
473fe49b | 494 | altclass = NO_REGS; |
321c0828 | 495 | #endif |
473fe49b KR |
496 | } |
497 | ||
cbd5b9a2 KR |
498 | if (altclass == NO_REGS) |
499 | return 0; | |
500 | ||
501 | if (in) | |
502 | partial_cost = REGISTER_MOVE_COST (altclass, class); | |
503 | else | |
504 | partial_cost = REGISTER_MOVE_COST (class, altclass); | |
505 | ||
506 | if (class == altclass) | |
507 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
508 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
509 | here in that case. | |
510 | ||
511 | I'm tempted to put in an abort here, but returning this will | |
512 | probably only give poor estimates, which is what we would've | |
513 | had before this code anyways. */ | |
514 | return partial_cost; | |
515 | ||
516 | /* Check if the secondary reload register will also need a | |
517 | secondary reload. */ | |
518 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
519 | } | |
520 | #endif | |
521 | ||
ca4aac00 DE |
522 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
523 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
524 | ||
525 | enum machine_mode | |
526 | choose_hard_reg_mode (regno, nregs) | |
527 | int regno; | |
528 | int nregs; | |
529 | { | |
530 | enum machine_mode found_mode = VOIDmode, mode; | |
531 | ||
532 | /* We first look for the largest integer mode that can be validly | |
533 | held in REGNO. If none, we look for the largest floating-point mode. | |
534 | If we still didn't find a valid mode, try CCmode. */ | |
535 | ||
536 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
537 | mode != VOIDmode; | |
538 | mode = GET_MODE_WIDER_MODE (mode)) | |
539 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
540 | && HARD_REGNO_MODE_OK (regno, mode)) | |
541 | found_mode = mode; | |
542 | ||
543 | if (found_mode != VOIDmode) | |
544 | return found_mode; | |
545 | ||
546 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
547 | mode != VOIDmode; | |
548 | mode = GET_MODE_WIDER_MODE (mode)) | |
549 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
550 | && HARD_REGNO_MODE_OK (regno, mode)) | |
551 | found_mode = mode; | |
552 | ||
553 | if (found_mode != VOIDmode) | |
554 | return found_mode; | |
555 | ||
556 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
557 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
558 | return CCmode; | |
559 | ||
560 | /* We can't find a mode valid for this register. */ | |
561 | return VOIDmode; | |
54dac99e RK |
562 | } |
563 | ||
564 | /* Specify the usage characteristics of the register named NAME. | |
565 | It should be a fixed register if FIXED and a | |
566 | call-used register if CALL_USED. */ | |
567 | ||
568 | void | |
569 | fix_register (name, fixed, call_used) | |
570 | char *name; | |
571 | int fixed, call_used; | |
572 | { | |
573 | int i; | |
574 | ||
575 | /* Decode the name and update the primary form of | |
576 | the register info. */ | |
577 | ||
e5c90c23 TW |
578 | if ((i = decode_reg_name (name)) >= 0) |
579 | { | |
cb2fdc84 GRK |
580 | if ((i == STACK_POINTER_REGNUM |
581 | #ifdef HARD_FRAME_POINTER_REGNUM | |
582 | || i == HARD_FRAME_POINTER_REGNUM | |
583 | #else | |
584 | || i == FRAME_POINTER_REGNUM | |
585 | #endif | |
586 | ) | |
587 | && (fixed == 0 || call_used == 0)) | |
588 | { | |
589 | static char* what_option[2][2] = { | |
7f7f8214 KG |
590 | { "call-saved", "call-used" }, |
591 | { "no-such-option", "fixed" }}; | |
cb2fdc84 GRK |
592 | |
593 | error ("can't use '%s' as a %s register", name, | |
594 | what_option[fixed][call_used]); | |
595 | } | |
596 | else | |
597 | { | |
598 | fixed_regs[i] = fixed; | |
599 | call_used_regs[i] = call_used; | |
600 | } | |
e5c90c23 TW |
601 | } |
602 | else | |
54dac99e RK |
603 | { |
604 | warning ("unknown register name: %s", name); | |
54dac99e RK |
605 | } |
606 | } | |
614f68e2 RK |
607 | |
608 | /* Mark register number I as global. */ | |
609 | ||
610 | void | |
611 | globalize_reg (i) | |
612 | int i; | |
613 | { | |
614 | if (global_regs[i]) | |
615 | { | |
616 | warning ("register used for two global register variables"); | |
617 | return; | |
618 | } | |
619 | ||
620 | if (call_used_regs[i] && ! fixed_regs[i]) | |
621 | warning ("call-clobbered register used for global register variable"); | |
622 | ||
623 | global_regs[i] = 1; | |
624 | ||
625 | /* If already fixed, nothing else to do. */ | |
626 | if (fixed_regs[i]) | |
627 | return; | |
628 | ||
629 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
630 | n_non_fixed_regs--; | |
631 | ||
632 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
633 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
634 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
635 | } | |
54dac99e RK |
636 | \f |
637 | /* Now the data and code for the `regclass' pass, which happens | |
638 | just before local-alloc. */ | |
639 | ||
e4600702 RK |
640 | /* The `costs' struct records the cost of using a hard register of each class |
641 | and of using memory for each pseudo. We use this data to set up | |
642 | register class preferences. */ | |
54dac99e | 643 | |
e4600702 | 644 | struct costs |
54dac99e | 645 | { |
e4600702 RK |
646 | int cost[N_REG_CLASSES]; |
647 | int mem_cost; | |
54dac99e RK |
648 | }; |
649 | ||
e4600702 RK |
650 | /* Record the cost of each class for each pseudo. */ |
651 | ||
652 | static struct costs *costs; | |
653 | ||
61719ba7 BS |
654 | /* Initialized once, and used to initialize cost values for each insn. */ |
655 | ||
656 | static struct costs init_cost; | |
657 | ||
e4600702 RK |
658 | /* Record the same data by operand number, accumulated for each alternative |
659 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
660 | alternative. */ | |
661 | ||
662 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
663 | |
664 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
665 | This is available after `regclass' is run. */ | |
666 | ||
667 | static char *prefclass; | |
668 | ||
54d23420 RK |
669 | /* altclass[R] is a register class that we should use for allocating |
670 | pseudo number R if no register in the preferred class is available. | |
671 | If no register in this class is available, memory is preferred. | |
672 | ||
673 | It might appear to be more general to have a bitmask of classes here, | |
674 | but since it is recommended that there be a class corresponding to the | |
675 | union of most major pair of classes, that generality is not required. | |
676 | ||
54dac99e RK |
677 | This is available after `regclass' is run. */ |
678 | ||
54d23420 | 679 | static char *altclass; |
54dac99e | 680 | |
6feacd09 MM |
681 | /* Allocated buffers for prefclass and altclass. */ |
682 | static char *prefclass_buffer; | |
683 | static char *altclass_buffer; | |
684 | ||
54d23420 | 685 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
686 | |
687 | static int loop_depth; | |
688 | ||
54d23420 RK |
689 | /* Account for the fact that insns within a loop are executed very commonly, |
690 | but don't keep doing this as loops go too deep. */ | |
691 | ||
692 | static int loop_cost; | |
693 | ||
0a578fee | 694 | static int n_occurrences PROTO((int, char *)); |
61719ba7 | 695 | static rtx scan_one_insn PROTO((rtx, int)); |
08d95f91 RK |
696 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
697 | char **, rtx)); | |
698 | static int copy_cost PROTO((rtx, enum machine_mode, | |
699 | enum reg_class, int)); | |
700 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
701 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
702 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
703 | #endif | |
f903b91f | 704 | static void reg_scan_mark_refs PROTO((rtx, rtx, int, int)); |
54dac99e RK |
705 | |
706 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
707 | This function is sometimes called before the info has been computed. | |
708 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
709 | ||
710 | enum reg_class | |
711 | reg_preferred_class (regno) | |
712 | int regno; | |
713 | { | |
714 | if (prefclass == 0) | |
715 | return GENERAL_REGS; | |
716 | return (enum reg_class) prefclass[regno]; | |
717 | } | |
718 | ||
e4600702 RK |
719 | enum reg_class |
720 | reg_alternate_class (regno) | |
b729186a | 721 | int regno; |
54dac99e RK |
722 | { |
723 | if (prefclass == 0) | |
e4600702 RK |
724 | return ALL_REGS; |
725 | ||
726 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
727 | } |
728 | ||
61719ba7 | 729 | /* Initialize some global data for this pass. */ |
54dac99e RK |
730 | |
731 | void | |
732 | regclass_init () | |
733 | { | |
61719ba7 BS |
734 | int i; |
735 | ||
736 | init_cost.mem_cost = 10000; | |
737 | for (i = 0; i < N_REG_CLASSES; i++) | |
738 | init_cost.cost[i] = 10000; | |
739 | ||
740 | /* This prevents dump_flow_info from losing if called | |
741 | before regclass is run. */ | |
54dac99e RK |
742 | prefclass = 0; |
743 | } | |
744 | \f | |
0a578fee BS |
745 | /* Return the number of times character C occurs in string S. */ |
746 | static int | |
747 | n_occurrences (c, s) | |
748 | int c; | |
749 | char *s; | |
750 | { | |
751 | int n = 0; | |
752 | while (*s) | |
753 | n += (*s++ == c); | |
754 | return n; | |
755 | } | |
756 | ||
61719ba7 BS |
757 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
758 | time it would save code to put a certain register in a certain class. | |
759 | PASS, when nonzero, inhibits some optimizations which need only be done | |
760 | once. | |
761 | Return the last insn processed, so that the scan can be continued from | |
762 | there. */ | |
763 | ||
764 | static rtx | |
765 | scan_one_insn (insn, pass) | |
766 | rtx insn; | |
767 | int pass; | |
768 | { | |
769 | enum rtx_code code = GET_CODE (insn); | |
770 | enum rtx_code pat_code; | |
61719ba7 BS |
771 | char *constraints[MAX_RECOG_OPERANDS]; |
772 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
0eadeb15 | 773 | rtx set, note; |
61719ba7 BS |
774 | int i, j; |
775 | ||
776 | /* Show that an insn inside a loop is likely to be executed three | |
777 | times more than insns outside a loop. This is much more aggressive | |
778 | than the assumptions made elsewhere and is being tried as an | |
779 | experiment. */ | |
780 | ||
781 | if (code == NOTE) | |
782 | { | |
783 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
784 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
785 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
786 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
787 | ||
788 | return insn; | |
789 | } | |
790 | ||
791 | if (GET_RTX_CLASS (code) != 'i') | |
792 | return insn; | |
793 | ||
794 | pat_code = GET_CODE (PATTERN (insn)); | |
795 | if (pat_code == USE | |
796 | || pat_code == CLOBBER | |
797 | || pat_code == ASM_INPUT | |
798 | || pat_code == ADDR_VEC | |
799 | || pat_code == ADDR_DIFF_VEC) | |
800 | return insn; | |
801 | ||
0eadeb15 BS |
802 | set = single_set (insn); |
803 | extract_insn (insn); | |
804 | ||
805 | for (i = 0; i < recog_n_operands; i++) | |
61719ba7 | 806 | { |
0eadeb15 BS |
807 | constraints[i] = recog_constraints[i]; |
808 | modes[i] = recog_operand_mode[i]; | |
61719ba7 | 809 | } |
61719ba7 | 810 | |
0eadeb15 BS |
811 | /* If this insn loads a parameter from its stack slot, then |
812 | it represents a savings, rather than a cost, if the | |
813 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 814 | |
0eadeb15 BS |
815 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
816 | && GET_CODE (SET_SRC (set)) == MEM | |
817 | && (note = find_reg_note (insn, REG_EQUIV, | |
818 | NULL_RTX)) != 0 | |
819 | && GET_CODE (XEXP (note, 0)) == MEM) | |
820 | { | |
821 | costs[REGNO (SET_DEST (set))].mem_cost | |
822 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
823 | GENERAL_REGS, 1) | |
824 | * loop_cost); | |
825 | record_address_regs (XEXP (SET_SRC (set), 0), | |
826 | BASE_REG_CLASS, loop_cost * 2); | |
827 | return insn; | |
828 | } | |
61719ba7 | 829 | |
0eadeb15 BS |
830 | /* Improve handling of two-address insns such as |
831 | (set X (ashift CONST Y)) where CONST must be made to | |
832 | match X. Change it into two insns: (set X CONST) | |
833 | (set X (ashift X Y)). If we left this for reloading, it | |
834 | would probably get three insns because X and Y might go | |
835 | in the same place. This prevents X and Y from receiving | |
836 | the same hard reg. | |
837 | ||
838 | We can only do this if the modes of operands 0 and 1 | |
839 | (which might not be the same) are tieable and we only need | |
840 | do this during our first pass. */ | |
841 | ||
842 | if (pass == 0 && optimize | |
843 | && recog_n_operands >= 3 | |
844 | && recog_constraints[1][0] == '0' | |
845 | && recog_constraints[1][1] == 0 | |
846 | && CONSTANT_P (recog_operand[1]) | |
847 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
848 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
849 | && GET_CODE (recog_operand[0]) == REG | |
850 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
851 | recog_operand_mode[1])) | |
852 | { | |
853 | rtx previnsn = prev_real_insn (insn); | |
854 | rtx dest | |
855 | = gen_lowpart (recog_operand_mode[1], | |
856 | recog_operand[0]); | |
857 | rtx newinsn | |
858 | = emit_insn_before (gen_move_insn (dest, | |
859 | recog_operand[1]), | |
860 | insn); | |
61719ba7 | 861 | |
0eadeb15 BS |
862 | /* If this insn was the start of a basic block, |
863 | include the new insn in that block. | |
864 | We need not check for code_label here; | |
865 | while a basic block can start with a code_label, | |
866 | INSN could not be at the beginning of that block. */ | |
867 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 868 | { |
0eadeb15 BS |
869 | int b; |
870 | for (b = 0; b < n_basic_blocks; b++) | |
871 | if (insn == basic_block_head[b]) | |
872 | basic_block_head[b] = newinsn; | |
61719ba7 BS |
873 | } |
874 | ||
0eadeb15 BS |
875 | /* This makes one more setting of new insns's dest. */ |
876 | REG_N_SETS (REGNO (recog_operand[0]))++; | |
61719ba7 | 877 | |
0eadeb15 BS |
878 | *recog_operand_loc[1] = recog_operand[0]; |
879 | for (i = recog_n_dups - 1; i >= 0; i--) | |
880 | if (recog_dup_num[i] == 1) | |
881 | *recog_dup_loc[i] = recog_operand[0]; | |
61719ba7 | 882 | |
0eadeb15 | 883 | return PREV_INSN (newinsn); |
61719ba7 BS |
884 | } |
885 | ||
886 | /* If we get here, we are set up to record the costs of all the | |
887 | operands for this insn. Start by initializing the costs. | |
888 | Then handle any address registers. Finally record the desired | |
889 | classes for any pseudos, doing it twice if some pair of | |
890 | operands are commutative. */ | |
891 | ||
0eadeb15 | 892 | for (i = 0; i < recog_n_operands; i++) |
61719ba7 BS |
893 | { |
894 | op_costs[i] = init_cost; | |
895 | ||
896 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
897 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
898 | ||
899 | if (GET_CODE (recog_operand[i]) == MEM) | |
900 | record_address_regs (XEXP (recog_operand[i], 0), | |
901 | BASE_REG_CLASS, loop_cost * 2); | |
902 | else if (constraints[i][0] == 'p') | |
903 | record_address_regs (recog_operand[i], | |
904 | BASE_REG_CLASS, loop_cost * 2); | |
905 | } | |
906 | ||
907 | /* Check for commutative in a separate loop so everything will | |
908 | have been initialized. We must do this even if one operand | |
909 | is a constant--see addsi3 in m68k.md. */ | |
910 | ||
0eadeb15 | 911 | for (i = 0; i < recog_n_operands - 1; i++) |
61719ba7 BS |
912 | if (constraints[i][0] == '%') |
913 | { | |
914 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
915 | int j; | |
916 | ||
917 | /* Handle commutative operands by swapping the constraints. | |
918 | We assume the modes are the same. */ | |
919 | ||
0eadeb15 | 920 | for (j = 0; j < recog_n_operands; j++) |
61719ba7 BS |
921 | xconstraints[j] = constraints[j]; |
922 | ||
923 | xconstraints[i] = constraints[i+1]; | |
924 | xconstraints[i+1] = constraints[i]; | |
0eadeb15 | 925 | record_reg_classes (recog_n_alternatives, recog_n_operands, |
61719ba7 BS |
926 | recog_operand, modes, xconstraints, |
927 | insn); | |
928 | } | |
929 | ||
0eadeb15 | 930 | record_reg_classes (recog_n_alternatives, recog_n_operands, recog_operand, |
61719ba7 BS |
931 | modes, constraints, insn); |
932 | ||
933 | /* Now add the cost for each operand to the total costs for | |
934 | its register. */ | |
935 | ||
0eadeb15 | 936 | for (i = 0; i < recog_n_operands; i++) |
61719ba7 BS |
937 | if (GET_CODE (recog_operand[i]) == REG |
938 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
939 | { | |
940 | int regno = REGNO (recog_operand[i]); | |
941 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
942 | ||
943 | p->mem_cost += q->mem_cost * loop_cost; | |
944 | for (j = 0; j < N_REG_CLASSES; j++) | |
945 | p->cost[j] += q->cost[j] * loop_cost; | |
946 | } | |
947 | ||
948 | return insn; | |
949 | } | |
950 | ||
54dac99e RK |
951 | /* This is a pass of the compiler that scans all instructions |
952 | and calculates the preferred class for each pseudo-register. | |
953 | This information can be accessed later by calling `reg_preferred_class'. | |
954 | This pass comes just before local register allocation. */ | |
955 | ||
956 | void | |
957 | regclass (f, nregs) | |
958 | rtx f; | |
959 | int nregs; | |
960 | { | |
961 | #ifdef REGISTER_CONSTRAINTS | |
962 | register rtx insn; | |
61719ba7 | 963 | register int i; |
e4600702 | 964 | int pass; |
54dac99e RK |
965 | |
966 | init_recog (); | |
967 | ||
56a65848 | 968 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 RK |
969 | |
970 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
971 | ||
972 | in_inc_dec = (char *) alloca (nregs); | |
973 | ||
974 | /* Initialize information about which register classes can be used for | |
975 | pseudos that are auto-incremented or auto-decremented. It would | |
976 | seem better to put this in init_reg_sets, but we need to be able | |
977 | to allocate rtx, which we can't do that early. */ | |
978 | ||
979 | for (i = 0; i < N_REG_CLASSES; i++) | |
980 | { | |
38a448ca | 981 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 | 982 | enum machine_mode m; |
8c368ee2 | 983 | register int j; |
533d0835 RK |
984 | |
985 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
986 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
987 | { | |
988 | REGNO (r) = j; | |
989 | ||
990 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 991 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
992 | if (HARD_REGNO_MODE_OK (j, m)) |
993 | { | |
994 | PUT_MODE (r, m); | |
08d95f91 RK |
995 | |
996 | /* If a register is not directly suitable for an | |
997 | auto-increment or decrement addressing mode and | |
998 | requires secondary reloads, disallow its class from | |
999 | being used in such addresses. */ | |
1000 | ||
1001 | if ((0 | |
041d7180 JL |
1002 | #ifdef SECONDARY_RELOAD_CLASS |
1003 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
1004 | != NO_REGS) | |
1005 | #else | |
533d0835 | 1006 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
1007 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1008 | != NO_REGS) | |
533d0835 RK |
1009 | #endif |
1010 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
1011 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1012 | != NO_REGS) | |
041d7180 | 1013 | #endif |
533d0835 | 1014 | #endif |
08d95f91 RK |
1015 | ) |
1016 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1017 | forbidden_inc_dec_class[i] = 1; |
1018 | } | |
1019 | } | |
1020 | } | |
1021 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1022 | ||
e4600702 RK |
1023 | /* Normally we scan the insns once and determine the best class to use for |
1024 | each register. However, if -fexpensive_optimizations are on, we do so | |
1025 | twice, the second time using the tentative best classes to guide the | |
1026 | selection. */ | |
54dac99e | 1027 | |
e4600702 RK |
1028 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1029 | { | |
1030 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 1031 | |
4c9a05bc | 1032 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 1033 | |
533d0835 RK |
1034 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1035 | bzero (in_inc_dec, nregs); | |
1036 | #endif | |
1037 | ||
e4600702 RK |
1038 | loop_depth = 0, loop_cost = 1; |
1039 | ||
1040 | /* Scan the instructions and record each time it would | |
1041 | save code to put a certain register in a certain class. */ | |
1042 | ||
1043 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 1044 | { |
61719ba7 | 1045 | insn = scan_one_insn (insn, pass); |
54dac99e | 1046 | } |
61719ba7 | 1047 | |
e4600702 RK |
1048 | /* Now for each register look at how desirable each class is |
1049 | and find which class is preferred. Store that in | |
1050 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
1051 | class any of whose registers is better than memory. */ | |
54dac99e | 1052 | |
e4600702 RK |
1053 | if (pass == 0) |
1054 | { | |
6feacd09 MM |
1055 | prefclass = prefclass_buffer; |
1056 | altclass = altclass_buffer; | |
e4600702 | 1057 | } |
54dac99e | 1058 | |
e4600702 | 1059 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1060 | { |
ca3c6eae | 1061 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1062 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1063 | /* This is an enum reg_class, but we call it an int | |
1064 | to save lots of casts. */ | |
1065 | register int class; | |
1066 | register struct costs *p = &costs[i]; | |
1067 | ||
1068 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 1069 | { |
533d0835 RK |
1070 | /* Ignore classes that are too small for this operand or |
1071 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 1072 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
1073 | > reg_class_size[class] |
1074 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1075 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1076 | #endif | |
1077 | ) | |
e4600702 RK |
1078 | ; |
1079 | else if (p->cost[class] < best_cost) | |
1080 | { | |
1081 | best_cost = p->cost[class]; | |
1082 | best = (enum reg_class) class; | |
1083 | } | |
1084 | else if (p->cost[class] == best_cost) | |
1085 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 1086 | } |
54dac99e | 1087 | |
e4600702 RK |
1088 | /* Record the alternate register class; i.e., a class for which |
1089 | every register in it is better than using memory. If adding a | |
1090 | class would make a smaller class (i.e., no union of just those | |
1091 | classes exists), skip that class. The major unions of classes | |
1092 | should be provided as a register class. Don't do this if we | |
1093 | will be doing it again later. */ | |
1094 | ||
1095 | if (pass == 1 || ! flag_expensive_optimizations) | |
1096 | for (class = 0; class < N_REG_CLASSES; class++) | |
1097 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1098 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1099 | > reg_class_size[(int) alt]) |
1100 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1101 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1102 | #endif | |
1103 | ) | |
e4600702 RK |
1104 | alt = reg_class_subunion[(int) alt][class]; |
1105 | ||
1106 | /* If we don't add any classes, nothing to try. */ | |
1107 | if (alt == best) | |
995d54dd | 1108 | alt = NO_REGS; |
e4600702 RK |
1109 | |
1110 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
1111 | prefclass[i] = (int) best; | |
1112 | altclass[i] = (int) alt; | |
1113 | } | |
54dac99e RK |
1114 | } |
1115 | #endif /* REGISTER_CONSTRAINTS */ | |
56a65848 DB |
1116 | |
1117 | free (costs); | |
54dac99e RK |
1118 | } |
1119 | \f | |
1120 | #ifdef REGISTER_CONSTRAINTS | |
1121 | ||
e4600702 RK |
1122 | /* Record the cost of using memory or registers of various classes for |
1123 | the operands in INSN. | |
54dac99e | 1124 | |
e4600702 | 1125 | N_ALTS is the number of alternatives. |
54dac99e | 1126 | |
e4600702 RK |
1127 | N_OPS is the number of operands. |
1128 | ||
1129 | OPS is an array of the operands. | |
1130 | ||
1131 | MODES are the modes of the operands, in case any are VOIDmode. | |
1132 | ||
1133 | CONSTRAINTS are the constraints to use for the operands. This array | |
1134 | is modified by this procedure. | |
1135 | ||
1136 | This procedure works alternative by alternative. For each alternative | |
1137 | we assume that we will be able to allocate all pseudos to their ideal | |
1138 | register class and calculate the cost of using that alternative. Then | |
1139 | we compute for each operand that is a pseudo-register, the cost of | |
1140 | having the pseudo allocated to each register class and using it in that | |
1141 | alternative. To this cost is added the cost of the alternative. | |
1142 | ||
1143 | The cost of each class for this insn is its lowest cost among all the | |
1144 | alternatives. */ | |
1145 | ||
1146 | static void | |
1147 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
1148 | int n_alts; | |
1149 | int n_ops; | |
1150 | rtx *ops; | |
1151 | enum machine_mode *modes; | |
54dac99e | 1152 | char **constraints; |
e4600702 | 1153 | rtx insn; |
54dac99e | 1154 | { |
e4600702 | 1155 | int alt; |
e4600702 | 1156 | int i, j; |
ec2d92af | 1157 | rtx set; |
e4600702 | 1158 | |
e4600702 RK |
1159 | /* Process each alternative, each time minimizing an operand's cost with |
1160 | the cost for each operand in that alternative. */ | |
54dac99e | 1161 | |
e4600702 | 1162 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1163 | { |
e4600702 RK |
1164 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1165 | int alt_fail = 0; | |
1166 | int alt_cost = 0; | |
1167 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
1168 | int class; | |
54dac99e | 1169 | |
e4600702 RK |
1170 | for (i = 0; i < n_ops; i++) |
1171 | { | |
1172 | char *p = constraints[i]; | |
1173 | rtx op = ops[i]; | |
1174 | enum machine_mode mode = modes[i]; | |
1175 | int allows_mem = 0; | |
1176 | int win = 0; | |
e51712db | 1177 | unsigned char c; |
54dac99e | 1178 | |
7405d9a1 DE |
1179 | /* Initially show we know nothing about the register class. */ |
1180 | classes[i] = NO_REGS; | |
1181 | ||
e4600702 RK |
1182 | /* If this operand has no constraints at all, we can conclude |
1183 | nothing about it since anything is valid. */ | |
54dac99e | 1184 | |
e4600702 RK |
1185 | if (*p == 0) |
1186 | { | |
1187 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1188 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1189 | |
e4600702 RK |
1190 | continue; |
1191 | } | |
54dac99e | 1192 | |
7405d9a1 DE |
1193 | /* If this alternative is only relevant when this operand |
1194 | matches a previous operand, we do different things depending | |
1195 | on whether this operand is a pseudo-reg or not. We must process | |
1196 | any modifiers for the operand before we can make this test. */ | |
1197 | ||
8c368ee2 | 1198 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1199 | p++; |
8c368ee2 | 1200 | |
e4600702 RK |
1201 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1202 | { | |
1203 | j = p[0] - '0'; | |
1204 | classes[i] = classes[j]; | |
1205 | ||
1206 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1207 | { | |
1208 | /* If this matches the other operand, we have no added | |
dc903608 | 1209 | cost and we win. */ |
e4600702 | 1210 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1211 | win = 1; |
e4600702 | 1212 | |
77e67eac RK |
1213 | /* If we can put the other operand into a register, add to |
1214 | the cost of this alternative the cost to copy this | |
1215 | operand to the register used for the other operand. */ | |
e4600702 | 1216 | |
dc903608 | 1217 | else if (classes[j] != NO_REGS) |
77e67eac | 1218 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1219 | } |
07d8ca2d RS |
1220 | else if (GET_CODE (ops[j]) != REG |
1221 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1222 | { | |
1223 | /* This op is a pseudo but the one it matches is not. */ | |
1224 | ||
1225 | /* If we can't put the other operand into a register, this | |
1226 | alternative can't be used. */ | |
1227 | ||
1228 | if (classes[j] == NO_REGS) | |
1229 | alt_fail = 1; | |
e4600702 | 1230 | |
07d8ca2d RS |
1231 | /* Otherwise, add to the cost of this alternative the cost |
1232 | to copy the other operand to the register used for this | |
1233 | operand. */ | |
1234 | ||
1235 | else | |
1236 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1237 | } | |
e4600702 RK |
1238 | else |
1239 | { | |
1240 | /* The costs of this operand are the same as that of the | |
1241 | other operand. However, if we cannot tie them, this | |
1242 | alternative needs to do a copy, which is one | |
1243 | instruction. */ | |
1244 | ||
1245 | this_op_costs[i] = this_op_costs[j]; | |
37747c82 RK |
1246 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1247 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1248 | alt_cost += 2; | |
e4600702 | 1249 | |
347099d6 | 1250 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1251 | for this operand, so skip to the end of the |
1252 | alternative (should be just one character). */ | |
1253 | while (*p && *p++ != ',') | |
1254 | ; | |
1255 | ||
1256 | constraints[i] = p; | |
347099d6 RS |
1257 | continue; |
1258 | } | |
e4600702 RK |
1259 | } |
1260 | ||
1261 | /* Scan all the constraint letters. See if the operand matches | |
1262 | any of the constraints. Collect the valid register classes | |
1263 | and see if this operand accepts memory. */ | |
1264 | ||
e4600702 RK |
1265 | while (*p && (c = *p++) != ',') |
1266 | switch (c) | |
1267 | { | |
e4600702 RK |
1268 | case '*': |
1269 | /* Ignore the next letter for this pass. */ | |
1270 | p++; | |
1271 | break; | |
1272 | ||
812f2051 R |
1273 | case '?': |
1274 | alt_cost += 2; | |
8c368ee2 | 1275 | case '!': case '#': case '&': |
e4600702 | 1276 | case '0': case '1': case '2': case '3': case '4': |
8c368ee2 | 1277 | case '5': case '6': case '7': case '8': case '9': |
e4600702 RK |
1278 | case 'p': |
1279 | break; | |
1280 | ||
1281 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1282 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 RK |
1283 | and non-offsettable addresses here. */ |
1284 | allows_mem = 1; | |
1285 | if (GET_CODE (op) == MEM) | |
1286 | win = 1; | |
1287 | break; | |
1288 | ||
1289 | case '<': | |
1290 | if (GET_CODE (op) == MEM | |
1291 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1292 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1293 | win = 1; | |
1294 | break; | |
1295 | ||
1296 | case '>': | |
1297 | if (GET_CODE (op) == MEM | |
1298 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1299 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1300 | win = 1; | |
1301 | break; | |
1302 | ||
1303 | case 'E': | |
7ac2547f | 1304 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1305 | /* Match any floating double constant, but only if |
1306 | we can examine the bits of it reliably. */ | |
1307 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1308 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1309 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1310 | break; | |
7ac2547f | 1311 | #endif |
e4600702 RK |
1312 | if (GET_CODE (op) == CONST_DOUBLE) |
1313 | win = 1; | |
1314 | break; | |
1315 | ||
1316 | case 'F': | |
1317 | if (GET_CODE (op) == CONST_DOUBLE) | |
1318 | win = 1; | |
1319 | break; | |
1320 | ||
1321 | case 'G': | |
1322 | case 'H': | |
1323 | if (GET_CODE (op) == CONST_DOUBLE | |
1324 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1325 | win = 1; | |
1326 | break; | |
1327 | ||
1328 | case 's': | |
1329 | if (GET_CODE (op) == CONST_INT | |
1330 | || (GET_CODE (op) == CONST_DOUBLE | |
1331 | && GET_MODE (op) == VOIDmode)) | |
1332 | break; | |
1333 | case 'i': | |
1334 | if (CONSTANT_P (op) | |
1335 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1336 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1337 | #endif | |
1338 | ) | |
1339 | win = 1; | |
1340 | break; | |
1341 | ||
1342 | case 'n': | |
1343 | if (GET_CODE (op) == CONST_INT | |
1344 | || (GET_CODE (op) == CONST_DOUBLE | |
1345 | && GET_MODE (op) == VOIDmode)) | |
1346 | win = 1; | |
1347 | break; | |
1348 | ||
1349 | case 'I': | |
1350 | case 'J': | |
1351 | case 'K': | |
1352 | case 'L': | |
1353 | case 'M': | |
1354 | case 'N': | |
1355 | case 'O': | |
1356 | case 'P': | |
1357 | if (GET_CODE (op) == CONST_INT | |
1358 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1359 | win = 1; | |
1360 | break; | |
1361 | ||
1362 | case 'X': | |
1363 | win = 1; | |
1364 | break; | |
54dac99e | 1365 | |
54dac99e | 1366 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1367 | case 'Q': |
1368 | case 'R': | |
1369 | case 'S': | |
1370 | case 'T': | |
1371 | case 'U': | |
1372 | if (EXTRA_CONSTRAINT (op, c)) | |
1373 | win = 1; | |
1374 | break; | |
1375 | #endif | |
1376 | ||
1377 | case 'g': | |
1378 | if (GET_CODE (op) == MEM | |
1379 | || (CONSTANT_P (op) | |
1380 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1381 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1382 | #endif |
e4600702 RK |
1383 | )) |
1384 | win = 1; | |
1385 | allows_mem = 1; | |
1386 | case 'r': | |
1387 | classes[i] | |
1388 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1389 | break; | |
1390 | ||
1391 | default: | |
1392 | classes[i] | |
1393 | = reg_class_subunion[(int) classes[i]] | |
1394 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1395 | } | |
1396 | ||
1397 | constraints[i] = p; | |
1398 | ||
1399 | /* How we account for this operand now depends on whether it is a | |
1400 | pseudo register or not. If it is, we first check if any | |
1401 | register classes are valid. If not, we ignore this alternative, | |
1402 | since we want to assume that all pseudos get allocated for | |
1403 | register preferencing. If some register class is valid, compute | |
1404 | the costs of moving the pseudo into that class. */ | |
1405 | ||
1406 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1407 | { |
e4600702 RK |
1408 | if (classes[i] == NO_REGS) |
1409 | alt_fail = 1; | |
1410 | else | |
1411 | { | |
1412 | struct costs *pp = &this_op_costs[i]; | |
1413 | ||
1414 | for (class = 0; class < N_REG_CLASSES; class++) | |
1415 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1416 | ||
1417 | /* If the alternative actually allows memory, make things | |
1418 | a bit cheaper since we won't need an extra insn to | |
1419 | load it. */ | |
1420 | ||
cbd5b9a2 KR |
1421 | pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) |
1422 | - allows_mem); | |
e4600702 RK |
1423 | |
1424 | /* If we have assigned a class to this register in our | |
1425 | first pass, add a cost to this alternative corresponding | |
1426 | to what we would add if this register were not in the | |
1427 | appropriate class. */ | |
1428 | ||
1429 | if (prefclass) | |
1430 | alt_cost | |
e51712db | 1431 | += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]]; |
e4600702 | 1432 | } |
4db18574 | 1433 | } |
54dac99e | 1434 | |
e4600702 RK |
1435 | /* Otherwise, if this alternative wins, either because we |
1436 | have already determined that or if we have a hard register of | |
1437 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1438 | |
e4600702 RK |
1439 | else if (win |
1440 | || (GET_CODE (op) == REG | |
6f654776 | 1441 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1442 | ; |
54dac99e | 1443 | |
e4600702 RK |
1444 | /* If registers are valid, the cost of this alternative includes |
1445 | copying the object to and/or from a register. */ | |
54dac99e | 1446 | |
e4600702 RK |
1447 | else if (classes[i] != NO_REGS) |
1448 | { | |
0eadeb15 | 1449 | if (recog_op_type[i] != OP_OUT) |
e4600702 | 1450 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1451 | |
0eadeb15 | 1452 | if (recog_op_type[i] != OP_IN) |
e4600702 RK |
1453 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1454 | } | |
54dac99e | 1455 | |
e4600702 RK |
1456 | /* The only other way this alternative can be used is if this is a |
1457 | constant that could be placed into memory. */ | |
1458 | ||
1459 | else if (CONSTANT_P (op) && allows_mem) | |
cbd5b9a2 | 1460 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1461 | else |
1462 | alt_fail = 1; | |
1463 | } | |
1464 | ||
1465 | if (alt_fail) | |
1466 | continue; | |
1467 | ||
1468 | /* Finally, update the costs with the information we've calculated | |
1469 | about this alternative. */ | |
1470 | ||
1471 | for (i = 0; i < n_ops; i++) | |
1472 | if (GET_CODE (ops[i]) == REG | |
1473 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1474 | { |
e4600702 | 1475 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
0eadeb15 | 1476 | int scale = 1 + (recog_op_type[i] == OP_INOUT); |
54dac99e | 1477 | |
e4600702 RK |
1478 | pp->mem_cost = MIN (pp->mem_cost, |
1479 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1480 | |
e4600702 RK |
1481 | for (class = 0; class < N_REG_CLASSES; class++) |
1482 | pp->cost[class] = MIN (pp->cost[class], | |
1483 | (qq->cost[class] + alt_cost) * scale); | |
1484 | } | |
1485 | } | |
ec2d92af RK |
1486 | |
1487 | /* If this insn is a single set copying operand 1 to operand 0 | |
1488 | and one is a pseudo with the other a hard reg that is in its | |
1489 | own register class, set the cost of that register class to -1. */ | |
1490 | ||
1491 | if ((set = single_set (insn)) != 0 | |
1492 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1493 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1494 | for (i = 0; i <= 1; i++) | |
1495 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1496 | { | |
1497 | int regno = REGNO (ops[!i]); | |
1498 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1499 | int class; | |
4841ba4b | 1500 | int nr; |
ec2d92af RK |
1501 | |
1502 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 | |
e51712db | 1503 | && (reg_class_size[(unsigned char)prefclass[regno]] |
ec2d92af | 1504 | == CLASS_MAX_NREGS (prefclass[regno], mode))) |
e51712db | 1505 | op_costs[i].cost[(unsigned char)prefclass[regno]] = -1; |
ec2d92af RK |
1506 | else if (regno < FIRST_PSEUDO_REGISTER) |
1507 | for (class = 0; class < N_REG_CLASSES; class++) | |
1508 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1509 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1510 | { |
1511 | if (reg_class_size[class] == 1) | |
1512 | op_costs[i].cost[class] = -1; | |
1513 | else | |
1514 | { | |
1515 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1516 | { | |
1517 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1518 | break; | |
1519 | } | |
1520 | ||
1521 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1522 | op_costs[i].cost[class] = -1; | |
1523 | } | |
1524 | } | |
ec2d92af | 1525 | } |
54dac99e | 1526 | } |
e4600702 RK |
1527 | \f |
1528 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1529 | TO_P is zero) a register of class CLASS in mode MODE. | |
1530 | ||
1531 | X must not be a pseudo. */ | |
1532 | ||
1533 | static int | |
1534 | copy_cost (x, mode, class, to_p) | |
1535 | rtx x; | |
1536 | enum machine_mode mode; | |
1537 | enum reg_class class; | |
1538 | int to_p; | |
1539 | { | |
29a82058 | 1540 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1541 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1542 | #endif |
e4600702 RK |
1543 | |
1544 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1545 | assuming optimal allocation. */ | |
1546 | ||
1547 | if (GET_CODE (x) == SCRATCH) | |
1548 | return 0; | |
1549 | ||
1550 | /* Get the class we will actually use for a reload. */ | |
1551 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1552 | ||
1553 | #ifdef HAVE_SECONDARY_RELOADS | |
1554 | /* If we need a secondary reload (we assume here that we are using | |
1555 | the secondary reload as an intermediate, not a scratch register), the | |
1556 | cost is that to load the input into the intermediate register, then | |
1557 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1558 | ||
1559 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1560 | if (to_p == 1) | |
1561 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1562 | #endif | |
1563 | ||
dd9f0e8f | 1564 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1565 | if (! to_p) |
1566 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1567 | #endif | |
1568 | ||
1569 | if (secondary_class != NO_REGS) | |
1570 | return (move_cost[(int) secondary_class][(int) class] | |
1571 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1572 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1573 | |
1574 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1575 | cost to move between the register classes, and use 2 for everything | |
1576 | else (constants). */ | |
1577 | ||
1578 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1579 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1580 | |
e4600702 RK |
1581 | else if (GET_CODE (x) == REG) |
1582 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1583 | ||
1584 | else | |
1585 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1586 | return 2; | |
1587 | } | |
1588 | \f | |
54dac99e RK |
1589 | /* Record the pseudo registers we must reload into hard registers |
1590 | in a subexpression of a memory address, X. | |
e4600702 RK |
1591 | |
1592 | CLASS is the class that the register needs to be in and is either | |
1593 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1594 | ||
1595 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1596 | can represent half-cost adjustments). */ | |
54dac99e | 1597 | |
197d6480 | 1598 | static void |
e4600702 | 1599 | record_address_regs (x, class, scale) |
54dac99e | 1600 | rtx x; |
e4600702 RK |
1601 | enum reg_class class; |
1602 | int scale; | |
54dac99e RK |
1603 | { |
1604 | register enum rtx_code code = GET_CODE (x); | |
1605 | ||
1606 | switch (code) | |
1607 | { | |
1608 | case CONST_INT: | |
1609 | case CONST: | |
1610 | case CC0: | |
1611 | case PC: | |
1612 | case SYMBOL_REF: | |
1613 | case LABEL_REF: | |
1614 | return; | |
1615 | ||
1616 | case PLUS: | |
1617 | /* When we have an address that is a sum, | |
1618 | we must determine whether registers are "base" or "index" regs. | |
1619 | If there is a sum of two registers, we must choose one to be | |
1620 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1621 | to make a good choice most of the time. We only need to do this |
1622 | on machines that can have two registers in an address and where | |
1623 | the base and index register classes are different. | |
1624 | ||
1625 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1626 | that seems bogus since it should only be set when we are sure | |
1627 | the register is being used as a pointer. */ | |
1628 | ||
54dac99e RK |
1629 | { |
1630 | rtx arg0 = XEXP (x, 0); | |
1631 | rtx arg1 = XEXP (x, 1); | |
1632 | register enum rtx_code code0 = GET_CODE (arg0); | |
1633 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1634 | |
1635 | /* Look inside subregs. */ | |
e4600702 | 1636 | if (code0 == SUBREG) |
54dac99e | 1637 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1638 | if (code1 == SUBREG) |
54dac99e RK |
1639 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1640 | ||
e4600702 RK |
1641 | /* If this machine only allows one register per address, it must |
1642 | be in the first operand. */ | |
1643 | ||
1644 | if (MAX_REGS_PER_ADDRESS == 1) | |
1645 | record_address_regs (arg0, class, scale); | |
1646 | ||
1647 | /* If index and base registers are the same on this machine, just | |
1648 | record registers in any non-constant operands. We assume here, | |
1649 | as well as in the tests below, that all addresses are in | |
1650 | canonical form. */ | |
1651 | ||
1652 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1653 | { |
e4600702 RK |
1654 | record_address_regs (arg0, class, scale); |
1655 | if (! CONSTANT_P (arg1)) | |
1656 | record_address_regs (arg1, class, scale); | |
54dac99e | 1657 | } |
e4600702 RK |
1658 | |
1659 | /* If the second operand is a constant integer, it doesn't change | |
1660 | what class the first operand must be. */ | |
1661 | ||
1662 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1663 | record_address_regs (arg0, class, scale); | |
1664 | ||
1665 | /* If the second operand is a symbolic constant, the first operand | |
1666 | must be an index register. */ | |
1667 | ||
1668 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1669 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1670 | ||
956d6950 JL |
1671 | /* If both operands are registers but one is already a hard register |
1672 | of index or base class, give the other the class that the hard | |
1673 | register is not. */ | |
1674 | ||
3f9e9508 | 1675 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1676 | else if (code0 == REG && code1 == REG |
1677 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1678 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1679 | record_address_regs (arg1, | |
1680 | REG_OK_FOR_BASE_P (arg0) | |
1681 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1682 | scale); | |
1683 | else if (code0 == REG && code1 == REG | |
1684 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1685 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1686 | record_address_regs (arg0, | |
1687 | REG_OK_FOR_BASE_P (arg1) | |
1688 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1689 | scale); | |
3f9e9508 | 1690 | #endif |
956d6950 | 1691 | |
e9a25f70 JL |
1692 | /* If one operand is known to be a pointer, it must be the base |
1693 | with the other operand the index. Likewise if the other operand | |
1694 | is a MULT. */ | |
f22376c7 | 1695 | |
e9a25f70 JL |
1696 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1697 | || code1 == MULT) | |
f22376c7 CI |
1698 | { |
1699 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1700 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1701 | } | |
e9a25f70 JL |
1702 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1703 | || code0 == MULT) | |
f22376c7 CI |
1704 | { |
1705 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1706 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1707 | } | |
1708 | ||
e9a25f70 | 1709 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1710 | or index register. This case should be rare. */ |
1711 | ||
e9a25f70 | 1712 | else |
54dac99e | 1713 | { |
e4600702 RK |
1714 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1715 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1716 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1717 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1718 | } |
54dac99e RK |
1719 | } |
1720 | break; | |
1721 | ||
1722 | case POST_INC: | |
1723 | case PRE_INC: | |
1724 | case POST_DEC: | |
1725 | case PRE_DEC: | |
1726 | /* Double the importance of a pseudo register that is incremented | |
1727 | or decremented, since it would take two extra insns | |
533d0835 RK |
1728 | if it ends up in the wrong place. If the operand is a pseudo, |
1729 | show it is being used in an INC_DEC context. */ | |
1730 | ||
1731 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1732 | if (GET_CODE (XEXP (x, 0)) == REG | |
1733 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1734 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1735 | #endif | |
e4600702 RK |
1736 | |
1737 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1738 | break; |
1739 | ||
1740 | case REG: | |
1741 | { | |
e4600702 RK |
1742 | register struct costs *pp = &costs[REGNO (x)]; |
1743 | register int i; | |
54dac99e | 1744 | |
cbd5b9a2 | 1745 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1746 | |
e4600702 RK |
1747 | for (i = 0; i < N_REG_CLASSES; i++) |
1748 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1749 | } |
1750 | break; | |
1751 | ||
1752 | default: | |
1753 | { | |
1754 | register char *fmt = GET_RTX_FORMAT (code); | |
1755 | register int i; | |
1756 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1757 | if (fmt[i] == 'e') | |
e4600702 | 1758 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1759 | } |
1760 | } | |
1761 | } | |
08d95f91 RK |
1762 | \f |
1763 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1764 | ||
1765 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1766 | to an object of MODE. */ | |
1767 | ||
1d300e19 | 1768 | static int |
08d95f91 RK |
1769 | auto_inc_dec_reg_p (reg, mode) |
1770 | rtx reg; | |
1771 | enum machine_mode mode; | |
1772 | { | |
940da324 JL |
1773 | if (HAVE_POST_INCREMENT |
1774 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 1775 | return 1; |
08d95f91 | 1776 | |
940da324 JL |
1777 | if (HAVE_POST_DECREMENT |
1778 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 1779 | return 1; |
08d95f91 | 1780 | |
940da324 JL |
1781 | if (HAVE_PRE_INCREMENT |
1782 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 1783 | return 1; |
08d95f91 | 1784 | |
940da324 JL |
1785 | if (HAVE_PRE_DECREMENT |
1786 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 1787 | return 1; |
08d95f91 RK |
1788 | |
1789 | return 0; | |
1790 | } | |
1791 | #endif | |
1792 | ||
54dac99e | 1793 | #endif /* REGISTER_CONSTRAINTS */ |
b1f21e0a | 1794 | \f |
ed396e68 BS |
1795 | static short *renumber = (short *)0; |
1796 | static size_t regno_allocated = 0; | |
1797 | ||
b1f21e0a MM |
1798 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
1799 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1800 | NEW_P is non zero, initialize all of the registers, otherwise only |
1801 | initialize the new registers allocated. The same table is kept from | |
1802 | function to function, only reallocating it when we need more room. If | |
1803 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1804 | |
1805 | void | |
39379e67 | 1806 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 1807 | size_t num_regs; |
b1f21e0a | 1808 | int new_p; |
39379e67 | 1809 | int renumber_p; |
b1f21e0a | 1810 | { |
6feacd09 MM |
1811 | size_t size_info; |
1812 | size_t size_renumber; | |
1813 | size_t min = (new_p) ? 0 : reg_n_max; | |
1814 | struct reg_info_data *reg_data; | |
1815 | struct reg_info_data *reg_next; | |
39379e67 | 1816 | |
b1f21e0a MM |
1817 | if (num_regs > regno_allocated) |
1818 | { | |
6feacd09 MM |
1819 | size_t old_allocated = regno_allocated; |
1820 | ||
b1f21e0a | 1821 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
1822 | size_renumber = regno_allocated * sizeof (short); |
1823 | ||
1824 | if (!reg_n_info) | |
1825 | { | |
6feacd09 | 1826 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 1827 | renumber = (short *) xmalloc (size_renumber); |
6feacd09 MM |
1828 | prefclass_buffer = (char *) xmalloc (regno_allocated); |
1829 | altclass_buffer = (char *) xmalloc (regno_allocated); | |
39379e67 MM |
1830 | } |
1831 | ||
1832 | else | |
1833 | { | |
6feacd09 MM |
1834 | VARRAY_GROW (reg_n_info, regno_allocated); |
1835 | ||
1836 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
1837 | { | |
1838 | free ((char *)renumber); | |
1839 | free ((char *)prefclass_buffer); | |
1840 | free ((char *)altclass_buffer); | |
1841 | renumber = (short *) xmalloc (size_renumber); | |
1842 | prefclass_buffer = (char *) xmalloc (regno_allocated); | |
1843 | altclass_buffer = (char *) xmalloc (regno_allocated); | |
1844 | } | |
1845 | ||
1846 | else | |
1847 | { | |
1848 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
1849 | prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer, | |
1850 | regno_allocated); | |
1851 | ||
1852 | altclass_buffer = (char *) xrealloc ((char *)altclass_buffer, | |
1853 | regno_allocated); | |
1854 | } | |
39379e67 | 1855 | } |
6feacd09 MM |
1856 | |
1857 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
1858 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
1859 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
1860 | reg_data->min_index = old_allocated; | |
1861 | reg_data->max_index = regno_allocated - 1; | |
1862 | reg_data->next = reg_info_head; | |
1863 | reg_info_head = reg_data; | |
b1f21e0a MM |
1864 | } |
1865 | ||
6feacd09 | 1866 | reg_n_max = num_regs; |
b1f21e0a MM |
1867 | if (min < num_regs) |
1868 | { | |
6feacd09 MM |
1869 | /* Loop through each of the segments allocated for the actual |
1870 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
1871 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
39379e67 | 1872 | { |
6feacd09 MM |
1873 | size_t min_index = reg_data->min_index; |
1874 | size_t max_index = reg_data->max_index; | |
1875 | ||
1876 | reg_next = reg_data->next; | |
29f63881 | 1877 | if (min <= max_index) |
6feacd09 | 1878 | { |
eafdfea8 | 1879 | size_t max = max_index; |
29f63881 | 1880 | size_t local_min = min - min_index; |
7f7f8214 KG |
1881 | size_t i; |
1882 | ||
29f63881 RH |
1883 | if (min < min_index) |
1884 | local_min = 0; | |
6feacd09 MM |
1885 | if (!reg_data->used_p) /* page just allocated with calloc */ |
1886 | reg_data->used_p = 1; /* no need to zero */ | |
1887 | else | |
29f63881 RH |
1888 | bzero ((char *) ®_data->data[local_min], |
1889 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
6feacd09 | 1890 | |
29f63881 | 1891 | for (i = min_index+local_min; i <= max; i++) |
6feacd09 MM |
1892 | { |
1893 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
1894 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
1895 | renumber[i] = -1; | |
1896 | prefclass_buffer[i] = (char) NO_REGS; | |
1897 | altclass_buffer[i] = (char) NO_REGS; | |
1898 | } | |
1899 | } | |
39379e67 | 1900 | } |
b1f21e0a MM |
1901 | } |
1902 | ||
6feacd09 MM |
1903 | /* If {pref,alt}class have already been allocated, update the pointers to |
1904 | the newly realloced ones. */ | |
1905 | if (prefclass) | |
1906 | { | |
1907 | prefclass = prefclass_buffer; | |
1908 | altclass = altclass_buffer; | |
1909 | } | |
1910 | ||
39379e67 MM |
1911 | if (renumber_p) |
1912 | reg_renumber = renumber; | |
1913 | ||
73b76448 RK |
1914 | /* Tell the regset code about the new number of registers */ |
1915 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
1916 | } |
1917 | ||
ed396e68 BS |
1918 | /* Free up the space allocated by allocate_reg_info. */ |
1919 | void | |
1920 | free_reg_info () | |
1921 | { | |
1922 | if (reg_n_info) | |
1923 | { | |
1924 | struct reg_info_data *reg_data; | |
1925 | struct reg_info_data *reg_next; | |
1926 | ||
1927 | VARRAY_FREE (reg_n_info); | |
1928 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
1929 | { | |
1930 | reg_next = reg_data->next; | |
1931 | free ((char *)reg_data); | |
1932 | } | |
1933 | ||
1934 | free (prefclass_buffer); | |
1935 | free (altclass_buffer); | |
1936 | prefclass_buffer = (char *)0; | |
1937 | altclass_buffer = (char *)0; | |
1938 | reg_info_head = (struct reg_info_data *)0; | |
1939 | renumber = (short *)0; | |
1940 | } | |
1941 | regno_allocated = 0; | |
1942 | reg_n_max = 0; | |
1943 | } | |
54dac99e RK |
1944 | \f |
1945 | /* This is the `regscan' pass of the compiler, run just before cse | |
1946 | and again just before loop. | |
1947 | ||
1948 | It finds the first and last use of each pseudo-register | |
1949 | and records them in the vectors regno_first_uid, regno_last_uid | |
1950 | and counts the number of sets in the vector reg_n_sets. | |
1951 | ||
1952 | REPEAT is nonzero the second time this is called. */ | |
1953 | ||
54dac99e | 1954 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 1955 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
1956 | and we want this to remain correct for all the remaining passes. */ |
1957 | ||
1958 | int max_parallel; | |
1959 | ||
54dac99e RK |
1960 | void |
1961 | reg_scan (f, nregs, repeat) | |
1962 | rtx f; | |
1963 | int nregs; | |
1964 | int repeat; | |
1965 | { | |
1966 | register rtx insn; | |
1967 | ||
39379e67 | 1968 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
1969 | max_parallel = 3; |
1970 | ||
1971 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1972 | if (GET_CODE (insn) == INSN | |
1973 | || GET_CODE (insn) == CALL_INSN | |
1974 | || GET_CODE (insn) == JUMP_INSN) | |
1975 | { | |
1976 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1977 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1978 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 1979 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
1980 | |
1981 | if (REG_NOTES (insn)) | |
f903b91f DM |
1982 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
1983 | } | |
1984 | } | |
1985 | ||
1986 | /* Update 'regscan' information by looking at the insns | |
1987 | from FIRST to LAST. Some new REGs have been created, | |
1988 | and any REG with number greater than OLD_MAX_REGNO is | |
1989 | such a REG. We only update information for those. */ | |
1990 | ||
1991 | void | |
1992 | reg_scan_update(first, last, old_max_regno) | |
1993 | rtx first; | |
1994 | rtx last; | |
1995 | int old_max_regno; | |
1996 | { | |
1997 | register rtx insn; | |
1998 | ||
1999 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2000 | ||
2001 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2002 | if (GET_CODE (insn) == INSN | |
2003 | || GET_CODE (insn) == CALL_INSN | |
2004 | || GET_CODE (insn) == JUMP_INSN) | |
2005 | { | |
2006 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2007 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2008 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2009 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2010 | ||
2011 | if (REG_NOTES (insn)) | |
2012 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2013 | } |
2014 | } | |
2015 | ||
1ebecb64 | 2016 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2017 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2018 | We should only record information for REGs with numbers | |
2019 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2020 | |
08d95f91 | 2021 | static void |
f903b91f | 2022 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2023 | rtx x; |
be8dcd74 | 2024 | rtx insn; |
1ebecb64 | 2025 | int note_flag; |
f903b91f | 2026 | int min_regno; |
54dac99e | 2027 | { |
fa23c636 | 2028 | register enum rtx_code code; |
54dac99e | 2029 | register rtx dest; |
be8dcd74 | 2030 | register rtx note; |
54dac99e | 2031 | |
fa23c636 | 2032 | code = GET_CODE (x); |
54dac99e RK |
2033 | switch (code) |
2034 | { | |
2035 | case CONST_INT: | |
2036 | case CONST: | |
2037 | case CONST_DOUBLE: | |
2038 | case CC0: | |
2039 | case PC: | |
2040 | case SYMBOL_REF: | |
2041 | case LABEL_REF: | |
2042 | case ADDR_VEC: | |
2043 | case ADDR_DIFF_VEC: | |
2044 | return; | |
2045 | ||
2046 | case REG: | |
2047 | { | |
2048 | register int regno = REGNO (x); | |
2049 | ||
f903b91f DM |
2050 | if (regno >= min_regno) |
2051 | { | |
2052 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2053 | if (!note_flag) | |
2054 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2055 | if (REGNO_FIRST_UID (regno) == 0) | |
2056 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
2057 | } | |
54dac99e RK |
2058 | } |
2059 | break; | |
2060 | ||
01565a55 | 2061 | case EXPR_LIST: |
7b18c3db | 2062 | if (XEXP (x, 0)) |
f903b91f | 2063 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2064 | if (XEXP (x, 1)) |
f903b91f | 2065 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2066 | break; |
2067 | ||
2068 | case INSN_LIST: | |
2069 | if (XEXP (x, 1)) | |
f903b91f | 2070 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2071 | break; |
2072 | ||
54dac99e RK |
2073 | case SET: |
2074 | /* Count a set of the destination if it is a register. */ | |
2075 | for (dest = SET_DEST (x); | |
2076 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2077 | || GET_CODE (dest) == ZERO_EXTEND; | |
2078 | dest = XEXP (dest, 0)) | |
2079 | ; | |
2080 | ||
f903b91f DM |
2081 | if (GET_CODE (dest) == REG |
2082 | && REGNO (dest) >= min_regno) | |
b1f21e0a | 2083 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 2084 | |
be8dcd74 RK |
2085 | /* If this is setting a pseudo from another pseudo or the sum of a |
2086 | pseudo and a constant integer and the other pseudo is known to be | |
2087 | a pointer, set the destination to be a pointer as well. | |
2088 | ||
2089 | Likewise if it is setting the destination from an address or from a | |
2090 | value equivalent to an address or to the sum of an address and | |
2091 | something else. | |
2092 | ||
2093 | But don't do any of this if the pseudo corresponds to a user | |
2094 | variable since it should have already been set as a pointer based | |
2095 | on the type. */ | |
2096 | ||
2097 | if (GET_CODE (SET_DEST (x)) == REG | |
2098 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2099 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2100 | /* If the destination pseudo is set more than once, then other |
2101 | sets might not be to a pointer value (consider access to a | |
2102 | union in two threads of control in the presense of global | |
2103 | optimizations). So only set REGNO_POINTER_FLAG on the destination | |
2104 | pseudo if this is the only set of that pseudo. */ | |
2105 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 RK |
2106 | && ! REG_USERVAR_P (SET_DEST (x)) |
2107 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
2108 | && ((GET_CODE (SET_SRC (x)) == REG | |
2109 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
2110 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2111 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2112 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2113 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
2114 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
2115 | || GET_CODE (SET_SRC (x)) == CONST | |
2116 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2117 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2118 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2119 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2120 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2121 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2122 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2123 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2124 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2125 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2126 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2127 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2128 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2129 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2130 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
2131 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
2132 | ||
0f41302f | 2133 | /* ... fall through ... */ |
54dac99e RK |
2134 | |
2135 | default: | |
2136 | { | |
2137 | register char *fmt = GET_RTX_FORMAT (code); | |
2138 | register int i; | |
2139 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2140 | { | |
2141 | if (fmt[i] == 'e') | |
f903b91f | 2142 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2143 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2144 | { | |
2145 | register int j; | |
2146 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f903b91f | 2147 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2148 | } |
2149 | } | |
2150 | } | |
2151 | } | |
2152 | } | |
2153 | \f | |
2154 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2155 | is also in C2. */ | |
2156 | ||
2157 | int | |
2158 | reg_class_subset_p (c1, c2) | |
2159 | register enum reg_class c1; | |
2160 | register enum reg_class c2; | |
2161 | { | |
2162 | if (c1 == c2) return 1; | |
2163 | ||
2164 | if (c2 == ALL_REGS) | |
2165 | win: | |
2166 | return 1; | |
2167 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
2168 | reg_class_contents[(int)c2], | |
2169 | win); | |
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2174 | ||
2175 | int | |
2176 | reg_classes_intersect_p (c1, c2) | |
2177 | register enum reg_class c1; | |
2178 | register enum reg_class c2; | |
2179 | { | |
2180 | #ifdef HARD_REG_SET | |
2181 | register | |
2182 | #endif | |
2183 | HARD_REG_SET c; | |
2184 | ||
2185 | if (c1 == c2) return 1; | |
2186 | ||
2187 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2188 | return 1; | |
2189 | ||
2190 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2191 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2192 | ||
2193 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2194 | return 1; | |
2195 | ||
2196 | lose: | |
2197 | return 0; | |
2198 | } | |
2199 | ||
73b76448 RK |
2200 | /* Release any memory allocated by register sets. */ |
2201 | ||
2202 | void | |
2203 | regset_release_memory () | |
2204 | { | |
2205 | if (basic_block_live_at_start) | |
2206 | { | |
2207 | free_regset_vector (basic_block_live_at_start, n_basic_blocks); | |
2208 | basic_block_live_at_start = 0; | |
2209 | } | |
2210 | ||
2211 | FREE_REG_SET (regs_live_at_setjmp); | |
2212 | bitmap_release_memory (); | |
2213 | } |