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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
29a82058 | 2 | Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
e9a25f70 | 27 | #include <stdio.h> |
b729186a JL |
28 | #if HAVE_STDLIB_H |
29 | #include <stdlib.h> | |
30 | #endif | |
54dac99e RK |
31 | #include "rtl.h" |
32 | #include "hard-reg-set.h" | |
33 | #include "flags.h" | |
34 | #include "basic-block.h" | |
35 | #include "regs.h" | |
36 | #include "insn-config.h" | |
37 | #include "recog.h" | |
e4600702 RK |
38 | #include "reload.h" |
39 | #include "real.h" | |
54dac99e RK |
40 | |
41 | #ifndef REGISTER_MOVE_COST | |
42 | #define REGISTER_MOVE_COST(x, y) 2 | |
43 | #endif | |
44 | ||
533d0835 RK |
45 | /* If we have auto-increment or auto-decrement and we can have secondary |
46 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 47 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
48 | |
49 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 50 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
51 | #define FORBIDDEN_INC_DEC_CLASSES |
52 | #endif | |
53 | #endif | |
54dac99e RK |
54 | \f |
55 | /* Register tables used by many passes. */ | |
56 | ||
57 | /* Indexed by hard register number, contains 1 for registers | |
58 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
59 | These are the registers that cannot be used to allocate | |
60 | a pseudo reg whose life does not cross calls. */ | |
61 | ||
62 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
63 | ||
64 | /* Same info as a HARD_REG_SET. */ | |
65 | ||
66 | HARD_REG_SET fixed_reg_set; | |
67 | ||
68 | /* Data for initializing the above. */ | |
69 | ||
70 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
71 | ||
72 | /* Indexed by hard register number, contains 1 for registers | |
73 | that are fixed use or are clobbered by function calls. | |
74 | These are the registers that cannot be used to allocate | |
75 | a pseudo reg whose life crosses calls. */ | |
76 | ||
77 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
78 | ||
79 | /* Same info as a HARD_REG_SET. */ | |
80 | ||
81 | HARD_REG_SET call_used_reg_set; | |
82 | ||
6cad67d2 JL |
83 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
84 | HARD_REG_SET losing_caller_save_reg_set; | |
85 | ||
54dac99e RK |
86 | /* Data for initializing the above. */ |
87 | ||
88 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
89 | ||
90 | /* Indexed by hard register number, contains 1 for registers that are | |
91 | fixed use -- i.e. in fixed_regs -- or a function value return register | |
92 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the | |
93 | registers that cannot hold quantities across calls even if we are | |
94 | willing to save and restore them. */ | |
95 | ||
96 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
97 | ||
98 | /* The same info as a HARD_REG_SET. */ | |
99 | ||
100 | HARD_REG_SET call_fixed_reg_set; | |
101 | ||
102 | /* Number of non-fixed registers. */ | |
103 | ||
104 | int n_non_fixed_regs; | |
105 | ||
106 | /* Indexed by hard register number, contains 1 for registers | |
107 | that are being used for global register decls. | |
108 | These must be exempt from ordinary flow analysis | |
109 | and are also considered fixed. */ | |
110 | ||
111 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
112 | ||
113 | /* Table of register numbers in the order in which to try to use them. */ | |
114 | #ifdef REG_ALLOC_ORDER | |
115 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
116 | #endif | |
117 | ||
118 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
119 | ||
2e0e2b76 CH |
120 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
121 | ||
089e575b RS |
122 | /* The same information, but as an array of unsigned ints. We copy from |
123 | these unsigned ints to the table above. We do this so the tm.h files | |
124 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
125 | |
126 | #define N_REG_INTS \ | |
127 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
128 | ||
089e575b | 129 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 130 | = REG_CLASS_CONTENTS; |
54dac99e RK |
131 | |
132 | /* For each reg class, number of regs it contains. */ | |
133 | ||
134 | int reg_class_size[N_REG_CLASSES]; | |
135 | ||
136 | /* For each reg class, table listing all the containing classes. */ | |
137 | ||
138 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
139 | ||
140 | /* For each reg class, table listing all the classes contained in it. */ | |
141 | ||
142 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
143 | ||
144 | /* For each pair of reg classes, | |
145 | a largest reg class contained in their union. */ | |
146 | ||
147 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
148 | ||
149 | /* For each pair of reg classes, | |
150 | the smallest reg class containing their union. */ | |
151 | ||
152 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
153 | ||
d05c8ee7 RS |
154 | /* Array containing all of the register names */ |
155 | ||
156 | char *reg_names[] = REGISTER_NAMES; | |
157 | ||
ca4aac00 DE |
158 | /* For each hard register, the widest mode object that it can contain. |
159 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
160 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
161 | register. */ | |
162 | ||
163 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
164 | ||
e4600702 RK |
165 | /* Maximum cost of moving from a register in one class to a register in |
166 | another class. Based on REGISTER_MOVE_COST. */ | |
167 | ||
168 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
169 | ||
170 | /* Similar, but here we don't have to move if the first index is a subset | |
171 | of the second so in that case the cost is zero. */ | |
172 | ||
173 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
174 | ||
533d0835 RK |
175 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
176 | ||
177 | /* These are the classes that regs which are auto-incremented or decremented | |
178 | cannot be put in. */ | |
179 | ||
180 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
181 | ||
182 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
183 | context. */ | |
184 | ||
185 | static char *in_inc_dec; | |
186 | ||
5fcb671c | 187 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 188 | |
54dac99e RK |
189 | /* Function called only once to initialize the above data on reg usage. |
190 | Once this is done, various switches may override. */ | |
191 | ||
192 | void | |
193 | init_reg_sets () | |
194 | { | |
195 | register int i, j; | |
196 | ||
2e0e2b76 CH |
197 | /* First copy the register information from the initial int form into |
198 | the regsets. */ | |
199 | ||
200 | for (i = 0; i < N_REG_CLASSES; i++) | |
201 | { | |
202 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
203 | ||
204 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
205 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 206 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
207 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
208 | } | |
209 | ||
54dac99e RK |
210 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
211 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
212 | bzero (global_regs, sizeof global_regs); | |
213 | ||
214 | /* Compute number of hard regs in each class. */ | |
215 | ||
4c9a05bc | 216 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
217 | for (i = 0; i < N_REG_CLASSES; i++) |
218 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
219 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
220 | reg_class_size[i]++; | |
221 | ||
222 | /* Initialize the table of subunions. | |
223 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
224 | that is contained in the union of classes I and J. */ | |
225 | ||
226 | for (i = 0; i < N_REG_CLASSES; i++) | |
227 | { | |
228 | for (j = 0; j < N_REG_CLASSES; j++) | |
229 | { | |
230 | #ifdef HARD_REG_SET | |
231 | register /* Declare it register if it's a scalar. */ | |
232 | #endif | |
233 | HARD_REG_SET c; | |
234 | register int k; | |
235 | ||
236 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
237 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
238 | for (k = 0; k < N_REG_CLASSES; k++) | |
239 | { | |
240 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
241 | subclass1); | |
242 | continue; | |
243 | ||
244 | subclass1: | |
245 | /* keep the largest subclass */ /* SPEE 900308 */ | |
246 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
247 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
248 | subclass2); | |
249 | reg_class_subunion[i][j] = (enum reg_class) k; | |
250 | subclass2: | |
251 | ; | |
252 | } | |
253 | } | |
254 | } | |
255 | ||
256 | /* Initialize the table of superunions. | |
257 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
258 | containing the union of classes I and J. */ | |
259 | ||
260 | for (i = 0; i < N_REG_CLASSES; i++) | |
261 | { | |
262 | for (j = 0; j < N_REG_CLASSES; j++) | |
263 | { | |
264 | #ifdef HARD_REG_SET | |
265 | register /* Declare it register if it's a scalar. */ | |
266 | #endif | |
267 | HARD_REG_SET c; | |
268 | register int k; | |
269 | ||
270 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
271 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
272 | for (k = 0; k < N_REG_CLASSES; k++) | |
273 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
274 | ||
275 | superclass: | |
276 | reg_class_superunion[i][j] = (enum reg_class) k; | |
277 | } | |
278 | } | |
279 | ||
280 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
281 | First clear the whole table, then add the elements as they are found. */ | |
282 | ||
283 | for (i = 0; i < N_REG_CLASSES; i++) | |
284 | { | |
285 | for (j = 0; j < N_REG_CLASSES; j++) | |
286 | { | |
287 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
288 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
289 | } | |
290 | } | |
291 | ||
292 | for (i = 0; i < N_REG_CLASSES; i++) | |
293 | { | |
294 | if (i == (int) NO_REGS) | |
295 | continue; | |
296 | ||
297 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
298 | { | |
299 | enum reg_class *p; | |
300 | ||
301 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
302 | subclass); | |
303 | continue; | |
304 | subclass: | |
305 | /* Reg class I is a subclass of J. | |
306 | Add J to the table of superclasses of I. */ | |
307 | p = ®_class_superclasses[i][0]; | |
308 | while (*p != LIM_REG_CLASSES) p++; | |
309 | *p = (enum reg_class) j; | |
310 | /* Add I to the table of superclasses of J. */ | |
311 | p = ®_class_subclasses[j][0]; | |
312 | while (*p != LIM_REG_CLASSES) p++; | |
313 | *p = (enum reg_class) i; | |
314 | } | |
315 | } | |
e4600702 | 316 | |
73b76448 RK |
317 | /* Do any additional initialization regsets may need */ |
318 | INIT_ONCE_REG_SET (); | |
54dac99e RK |
319 | } |
320 | ||
321 | /* After switches have been processed, which perhaps alter | |
322 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
323 | ||
c27c5281 | 324 | static void |
54dac99e RK |
325 | init_reg_sets_1 () |
326 | { | |
f8344bea | 327 | register unsigned int i, j; |
54dac99e RK |
328 | |
329 | /* This macro allows the fixed or call-used registers | |
330 | to depend on target flags. */ | |
331 | ||
332 | #ifdef CONDITIONAL_REGISTER_USAGE | |
333 | CONDITIONAL_REGISTER_USAGE; | |
334 | #endif | |
335 | ||
54dac99e RK |
336 | /* Initialize "constant" tables. */ |
337 | ||
338 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
339 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
340 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
341 | ||
342 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
343 | |
344 | n_non_fixed_regs = 0; | |
345 | ||
346 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
347 | { | |
54dac99e RK |
348 | if (fixed_regs[i]) |
349 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
350 | else | |
351 | n_non_fixed_regs++; | |
352 | ||
353 | if (call_used_regs[i]) | |
354 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
355 | if (call_fixed_regs[i]) | |
356 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
357 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
358 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 359 | } |
acbce667 KR |
360 | |
361 | /* Initialize the move cost table. Find every subset of each class | |
362 | and take the maximum cost of moving any subset to any other. */ | |
363 | ||
364 | for (i = 0; i < N_REG_CLASSES; i++) | |
365 | for (j = 0; j < N_REG_CLASSES; j++) | |
366 | { | |
367 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
368 | enum reg_class *p1, *p2; | |
369 | ||
370 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
371 | if (*p2 != i) | |
372 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
373 | ||
374 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
375 | { | |
376 | if (*p1 != j) | |
377 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
378 | ||
379 | for (p2 = ®_class_subclasses[j][0]; | |
380 | *p2 != LIM_REG_CLASSES; p2++) | |
381 | if (*p1 != *p2) | |
382 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
383 | } | |
384 | ||
385 | move_cost[i][j] = cost; | |
386 | ||
387 | if (reg_class_subset_p (i, j)) | |
388 | cost = 0; | |
389 | ||
390 | may_move_cost[i][j] = cost; | |
391 | } | |
c27c5281 DE |
392 | } |
393 | ||
394 | /* Compute the table of register modes. | |
395 | These values are used to record death information for individual registers | |
396 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 397 | |
c27c5281 DE |
398 | static void |
399 | init_reg_modes () | |
400 | { | |
401 | register int i; | |
ca4aac00 DE |
402 | |
403 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
404 | { |
405 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
406 | ||
066c2fea | 407 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
408 | ??? One situation in which we need to do this is on the mips where |
409 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
410 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 411 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 412 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 413 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 414 | } |
ca4aac00 DE |
415 | } |
416 | ||
c27c5281 DE |
417 | /* Finish initializing the register sets and |
418 | initialize the register modes. */ | |
419 | ||
420 | void | |
421 | init_regs () | |
422 | { | |
423 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
424 | until after register usage was specified. */ | |
b93a436e | 425 | init_reg_sets_1 (); |
c27c5281 DE |
426 | |
427 | init_reg_modes (); | |
428 | } | |
429 | ||
cbd5b9a2 KR |
430 | #ifdef HAVE_SECONDARY_RELOADS |
431 | /* Compute extra cost of moving registers to/from memory due to reloads. | |
432 | Only needed if secondary reloads are required for memory moves. */ | |
433 | int | |
434 | memory_move_secondary_cost (mode, class, in) | |
435 | enum machine_mode mode; | |
436 | enum reg_class class; | |
437 | int in; | |
438 | { | |
439 | enum reg_class altclass; | |
440 | int partial_cost = 0; | |
441 | rtx mem; | |
442 | ||
443 | /* We need a memory reference to feed to SECONDARY... macros. */ | |
444 | mem = gen_rtx (MEM, mode, stack_pointer_rtx); | |
445 | ||
446 | if (in) | |
447 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); | |
448 | else | |
449 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); | |
450 | if (altclass == NO_REGS) | |
451 | return 0; | |
452 | ||
453 | if (in) | |
454 | partial_cost = REGISTER_MOVE_COST (altclass, class); | |
455 | else | |
456 | partial_cost = REGISTER_MOVE_COST (class, altclass); | |
457 | ||
458 | if (class == altclass) | |
459 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
460 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
461 | here in that case. | |
462 | ||
463 | I'm tempted to put in an abort here, but returning this will | |
464 | probably only give poor estimates, which is what we would've | |
465 | had before this code anyways. */ | |
466 | return partial_cost; | |
467 | ||
468 | /* Check if the secondary reload register will also need a | |
469 | secondary reload. */ | |
470 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
471 | } | |
472 | #endif | |
473 | ||
ca4aac00 DE |
474 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
475 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
476 | ||
477 | enum machine_mode | |
478 | choose_hard_reg_mode (regno, nregs) | |
479 | int regno; | |
480 | int nregs; | |
481 | { | |
482 | enum machine_mode found_mode = VOIDmode, mode; | |
483 | ||
484 | /* We first look for the largest integer mode that can be validly | |
485 | held in REGNO. If none, we look for the largest floating-point mode. | |
486 | If we still didn't find a valid mode, try CCmode. */ | |
487 | ||
488 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
489 | mode != VOIDmode; | |
490 | mode = GET_MODE_WIDER_MODE (mode)) | |
491 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
492 | && HARD_REGNO_MODE_OK (regno, mode)) | |
493 | found_mode = mode; | |
494 | ||
495 | if (found_mode != VOIDmode) | |
496 | return found_mode; | |
497 | ||
498 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
499 | mode != VOIDmode; | |
500 | mode = GET_MODE_WIDER_MODE (mode)) | |
501 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
502 | && HARD_REGNO_MODE_OK (regno, mode)) | |
503 | found_mode = mode; | |
504 | ||
505 | if (found_mode != VOIDmode) | |
506 | return found_mode; | |
507 | ||
508 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
509 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
510 | return CCmode; | |
511 | ||
512 | /* We can't find a mode valid for this register. */ | |
513 | return VOIDmode; | |
54dac99e RK |
514 | } |
515 | ||
516 | /* Specify the usage characteristics of the register named NAME. | |
517 | It should be a fixed register if FIXED and a | |
518 | call-used register if CALL_USED. */ | |
519 | ||
520 | void | |
521 | fix_register (name, fixed, call_used) | |
522 | char *name; | |
523 | int fixed, call_used; | |
524 | { | |
525 | int i; | |
526 | ||
527 | /* Decode the name and update the primary form of | |
528 | the register info. */ | |
529 | ||
e5c90c23 TW |
530 | if ((i = decode_reg_name (name)) >= 0) |
531 | { | |
532 | fixed_regs[i] = fixed; | |
533 | call_used_regs[i] = call_used; | |
534 | } | |
535 | else | |
54dac99e RK |
536 | { |
537 | warning ("unknown register name: %s", name); | |
54dac99e RK |
538 | } |
539 | } | |
614f68e2 RK |
540 | |
541 | /* Mark register number I as global. */ | |
542 | ||
543 | void | |
544 | globalize_reg (i) | |
545 | int i; | |
546 | { | |
547 | if (global_regs[i]) | |
548 | { | |
549 | warning ("register used for two global register variables"); | |
550 | return; | |
551 | } | |
552 | ||
553 | if (call_used_regs[i] && ! fixed_regs[i]) | |
554 | warning ("call-clobbered register used for global register variable"); | |
555 | ||
556 | global_regs[i] = 1; | |
557 | ||
558 | /* If already fixed, nothing else to do. */ | |
559 | if (fixed_regs[i]) | |
560 | return; | |
561 | ||
562 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
563 | n_non_fixed_regs--; | |
564 | ||
565 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
566 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
567 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
568 | } | |
54dac99e RK |
569 | \f |
570 | /* Now the data and code for the `regclass' pass, which happens | |
571 | just before local-alloc. */ | |
572 | ||
e4600702 RK |
573 | /* The `costs' struct records the cost of using a hard register of each class |
574 | and of using memory for each pseudo. We use this data to set up | |
575 | register class preferences. */ | |
54dac99e | 576 | |
e4600702 | 577 | struct costs |
54dac99e | 578 | { |
e4600702 RK |
579 | int cost[N_REG_CLASSES]; |
580 | int mem_cost; | |
54dac99e RK |
581 | }; |
582 | ||
e4600702 RK |
583 | /* Record the cost of each class for each pseudo. */ |
584 | ||
585 | static struct costs *costs; | |
586 | ||
587 | /* Record the same data by operand number, accumulated for each alternative | |
588 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
589 | alternative. */ | |
590 | ||
591 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
592 | |
593 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
594 | This is available after `regclass' is run. */ | |
595 | ||
596 | static char *prefclass; | |
597 | ||
54d23420 RK |
598 | /* altclass[R] is a register class that we should use for allocating |
599 | pseudo number R if no register in the preferred class is available. | |
600 | If no register in this class is available, memory is preferred. | |
601 | ||
602 | It might appear to be more general to have a bitmask of classes here, | |
603 | but since it is recommended that there be a class corresponding to the | |
604 | union of most major pair of classes, that generality is not required. | |
605 | ||
54dac99e RK |
606 | This is available after `regclass' is run. */ |
607 | ||
54d23420 | 608 | static char *altclass; |
54dac99e | 609 | |
54d23420 | 610 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
611 | |
612 | static int loop_depth; | |
613 | ||
54d23420 RK |
614 | /* Account for the fact that insns within a loop are executed very commonly, |
615 | but don't keep doing this as loops go too deep. */ | |
616 | ||
617 | static int loop_cost; | |
618 | ||
08d95f91 RK |
619 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
620 | char **, rtx)); | |
621 | static int copy_cost PROTO((rtx, enum machine_mode, | |
622 | enum reg_class, int)); | |
623 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
624 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
625 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
626 | #endif | |
08d95f91 | 627 | static void reg_scan_mark_refs PROTO((rtx, rtx, int)); |
54dac99e RK |
628 | |
629 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
630 | This function is sometimes called before the info has been computed. | |
631 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
632 | ||
633 | enum reg_class | |
634 | reg_preferred_class (regno) | |
635 | int regno; | |
636 | { | |
637 | if (prefclass == 0) | |
638 | return GENERAL_REGS; | |
639 | return (enum reg_class) prefclass[regno]; | |
640 | } | |
641 | ||
e4600702 RK |
642 | enum reg_class |
643 | reg_alternate_class (regno) | |
b729186a | 644 | int regno; |
54dac99e RK |
645 | { |
646 | if (prefclass == 0) | |
e4600702 RK |
647 | return ALL_REGS; |
648 | ||
649 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
650 | } |
651 | ||
652 | /* This prevents dump_flow_info from losing if called | |
653 | before regclass is run. */ | |
654 | ||
655 | void | |
656 | regclass_init () | |
657 | { | |
658 | prefclass = 0; | |
659 | } | |
660 | \f | |
661 | /* This is a pass of the compiler that scans all instructions | |
662 | and calculates the preferred class for each pseudo-register. | |
663 | This information can be accessed later by calling `reg_preferred_class'. | |
664 | This pass comes just before local register allocation. */ | |
665 | ||
666 | void | |
667 | regclass (f, nregs) | |
668 | rtx f; | |
669 | int nregs; | |
670 | { | |
671 | #ifdef REGISTER_CONSTRAINTS | |
672 | register rtx insn; | |
e4600702 RK |
673 | register int i, j; |
674 | struct costs init_cost; | |
675 | rtx set; | |
676 | int pass; | |
54dac99e RK |
677 | |
678 | init_recog (); | |
679 | ||
533d0835 RK |
680 | costs = (struct costs *) alloca (nregs * sizeof (struct costs)); |
681 | ||
682 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
683 | ||
684 | in_inc_dec = (char *) alloca (nregs); | |
685 | ||
686 | /* Initialize information about which register classes can be used for | |
687 | pseudos that are auto-incremented or auto-decremented. It would | |
688 | seem better to put this in init_reg_sets, but we need to be able | |
689 | to allocate rtx, which we can't do that early. */ | |
690 | ||
691 | for (i = 0; i < N_REG_CLASSES; i++) | |
692 | { | |
38a448ca | 693 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 RK |
694 | enum machine_mode m; |
695 | ||
696 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
697 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
698 | { | |
699 | REGNO (r) = j; | |
700 | ||
701 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 702 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
703 | if (HARD_REGNO_MODE_OK (j, m)) |
704 | { | |
705 | PUT_MODE (r, m); | |
08d95f91 RK |
706 | |
707 | /* If a register is not directly suitable for an | |
708 | auto-increment or decrement addressing mode and | |
709 | requires secondary reloads, disallow its class from | |
710 | being used in such addresses. */ | |
711 | ||
712 | if ((0 | |
041d7180 JL |
713 | #ifdef SECONDARY_RELOAD_CLASS |
714 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
715 | != NO_REGS) | |
716 | #else | |
533d0835 | 717 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
718 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
719 | != NO_REGS) | |
533d0835 RK |
720 | #endif |
721 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
722 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
723 | != NO_REGS) | |
041d7180 | 724 | #endif |
533d0835 | 725 | #endif |
08d95f91 RK |
726 | ) |
727 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
728 | forbidden_inc_dec_class[i] = 1; |
729 | } | |
730 | } | |
731 | } | |
732 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
733 | ||
e4600702 RK |
734 | init_cost.mem_cost = 10000; |
735 | for (i = 0; i < N_REG_CLASSES; i++) | |
736 | init_cost.cost[i] = 10000; | |
54dac99e | 737 | |
e4600702 RK |
738 | /* Normally we scan the insns once and determine the best class to use for |
739 | each register. However, if -fexpensive_optimizations are on, we do so | |
740 | twice, the second time using the tentative best classes to guide the | |
741 | selection. */ | |
54dac99e | 742 | |
e4600702 RK |
743 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
744 | { | |
745 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 746 | |
4c9a05bc | 747 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 748 | |
533d0835 RK |
749 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
750 | bzero (in_inc_dec, nregs); | |
751 | #endif | |
752 | ||
e4600702 RK |
753 | loop_depth = 0, loop_cost = 1; |
754 | ||
755 | /* Scan the instructions and record each time it would | |
756 | save code to put a certain register in a certain class. */ | |
757 | ||
758 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 759 | { |
e4600702 RK |
760 | char *constraints[MAX_RECOG_OPERANDS]; |
761 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
762 | int nalternatives; | |
763 | int noperands; | |
764 | ||
765 | /* Show that an insn inside a loop is likely to be executed three | |
ac2a9454 | 766 | times more than insns outside a loop. This is much more aggressive |
e4600702 RK |
767 | than the assumptions made elsewhere and is being tried as an |
768 | experiment. */ | |
769 | ||
770 | if (GET_CODE (insn) == NOTE | |
771 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
772 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
773 | else if (GET_CODE (insn) == NOTE | |
774 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
775 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
776 | ||
777 | else if ((GET_CODE (insn) == INSN | |
778 | && GET_CODE (PATTERN (insn)) != USE | |
779 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
780 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) | |
781 | || (GET_CODE (insn) == JUMP_INSN | |
782 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
783 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
784 | || GET_CODE (insn) == CALL_INSN) | |
54dac99e | 785 | { |
e4600702 RK |
786 | if (GET_CODE (insn) == INSN |
787 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) | |
788 | { | |
37366632 | 789 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, |
e4600702 | 790 | constraints, modes); |
e5ed2155 TW |
791 | nalternatives = (noperands == 0 ? 0 |
792 | : n_occurrences (',', constraints[0]) + 1); | |
e4600702 RK |
793 | } |
794 | else | |
795 | { | |
796 | int insn_code_number = recog_memoized (insn); | |
797 | rtx note; | |
54dac99e | 798 | |
e4600702 RK |
799 | set = single_set (insn); |
800 | insn_extract (insn); | |
54dac99e | 801 | |
e4600702 RK |
802 | nalternatives = insn_n_alternatives[insn_code_number]; |
803 | noperands = insn_n_operands[insn_code_number]; | |
54dac99e | 804 | |
e4600702 RK |
805 | /* If this insn loads a parameter from its stack slot, then |
806 | it represents a savings, rather than a cost, if the | |
807 | parameter is stored in memory. Record this fact. */ | |
54dac99e | 808 | |
e4600702 RK |
809 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
810 | && GET_CODE (SET_SRC (set)) == MEM | |
37366632 RK |
811 | && (note = find_reg_note (insn, REG_EQUIV, |
812 | NULL_RTX)) != 0 | |
e4600702 RK |
813 | && GET_CODE (XEXP (note, 0)) == MEM) |
814 | { | |
815 | costs[REGNO (SET_DEST (set))].mem_cost | |
cbd5b9a2 KR |
816 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), |
817 | GENERAL_REGS, 1) | |
e4600702 RK |
818 | * loop_cost); |
819 | record_address_regs (XEXP (SET_SRC (set), 0), | |
820 | BASE_REG_CLASS, loop_cost * 2); | |
821 | continue; | |
822 | } | |
823 | ||
824 | /* Improve handling of two-address insns such as | |
825 | (set X (ashift CONST Y)) where CONST must be made to | |
826 | match X. Change it into two insns: (set X CONST) | |
827 | (set X (ashift X Y)). If we left this for reloading, it | |
828 | would probably get three insns because X and Y might go | |
829 | in the same place. This prevents X and Y from receiving | |
830 | the same hard reg. | |
831 | ||
832 | We can only do this if the modes of operands 0 and 1 | |
833 | (which might not be the same) are tieable and we only need | |
834 | do this during our first pass. */ | |
835 | ||
836 | if (pass == 0 && optimize | |
837 | && noperands >= 3 | |
838 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
839 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
840 | && CONSTANT_P (recog_operand[1]) | |
841 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
842 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
843 | && GET_CODE (recog_operand[0]) == REG | |
844 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
845 | insn_operand_mode[insn_code_number][1])) | |
846 | { | |
847 | rtx previnsn = prev_real_insn (insn); | |
848 | rtx dest | |
849 | = gen_lowpart (insn_operand_mode[insn_code_number][1], | |
850 | recog_operand[0]); | |
851 | rtx newinsn | |
852 | = emit_insn_before (gen_move_insn (dest, | |
853 | recog_operand[1]), | |
854 | insn); | |
855 | ||
856 | /* If this insn was the start of a basic block, | |
61b01243 RS |
857 | include the new insn in that block. |
858 | We need not check for code_label here; | |
859 | while a basic block can start with a code_label, | |
860 | INSN could not be at the beginning of that block. */ | |
e4600702 RK |
861 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) |
862 | { | |
863 | int b; | |
864 | for (b = 0; b < n_basic_blocks; b++) | |
865 | if (insn == basic_block_head[b]) | |
866 | basic_block_head[b] = newinsn; | |
867 | } | |
868 | ||
0f41302f | 869 | /* This makes one more setting of new insns's dest. */ |
b1f21e0a | 870 | REG_N_SETS (REGNO (recog_operand[0]))++; |
e4600702 | 871 | |
20912ad0 RK |
872 | *recog_operand_loc[1] = recog_operand[0]; |
873 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
874 | if (recog_dup_num[i] == 1) | |
875 | *recog_dup_loc[i] = recog_operand[0]; | |
876 | ||
e4600702 RK |
877 | insn = PREV_INSN (newinsn); |
878 | continue; | |
879 | } | |
54dac99e | 880 | |
e4600702 RK |
881 | for (i = 0; i < noperands; i++) |
882 | { | |
883 | constraints[i] | |
884 | = insn_operand_constraint[insn_code_number][i]; | |
885 | modes[i] = insn_operand_mode[insn_code_number][i]; | |
886 | } | |
887 | } | |
54dac99e | 888 | |
e4600702 RK |
889 | /* If we get here, we are set up to record the costs of all the |
890 | operands for this insn. Start by initializing the costs. | |
891 | Then handle any address registers. Finally record the desired | |
892 | classes for any pseudos, doing it twice if some pair of | |
893 | operands are commutative. */ | |
894 | ||
895 | for (i = 0; i < noperands; i++) | |
54dac99e | 896 | { |
e4600702 RK |
897 | op_costs[i] = init_cost; |
898 | ||
899 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
900 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
901 | ||
902 | if (GET_CODE (recog_operand[i]) == MEM) | |
903 | record_address_regs (XEXP (recog_operand[i], 0), | |
904 | BASE_REG_CLASS, loop_cost * 2); | |
905 | else if (constraints[i][0] == 'p') | |
906 | record_address_regs (recog_operand[i], | |
907 | BASE_REG_CLASS, loop_cost * 2); | |
54dac99e | 908 | } |
e4600702 RK |
909 | |
910 | /* Check for commutative in a separate loop so everything will | |
cc4c133a RS |
911 | have been initialized. We must do this even if one operand |
912 | is a constant--see addsi3 in m68k.md. */ | |
54dac99e | 913 | |
e5ed2155 | 914 | for (i = 0; i < noperands - 1; i++) |
cc4c133a | 915 | if (constraints[i][0] == '%') |
e4600702 RK |
916 | { |
917 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
918 | int j; | |
919 | ||
920 | /* Handle commutative operands by swapping the constraints. | |
921 | We assume the modes are the same. */ | |
922 | ||
923 | for (j = 0; j < noperands; j++) | |
924 | xconstraints[j] = constraints[j]; | |
925 | ||
926 | xconstraints[i] = constraints[i+1]; | |
927 | xconstraints[i+1] = constraints[i]; | |
928 | record_reg_classes (nalternatives, noperands, | |
929 | recog_operand, modes, xconstraints, | |
54dac99e | 930 | insn); |
e4600702 | 931 | } |
54dac99e | 932 | |
e4600702 RK |
933 | record_reg_classes (nalternatives, noperands, recog_operand, |
934 | modes, constraints, insn); | |
54dac99e | 935 | |
e4600702 RK |
936 | /* Now add the cost for each operand to the total costs for |
937 | its register. */ | |
54dac99e | 938 | |
e4600702 RK |
939 | for (i = 0; i < noperands; i++) |
940 | if (GET_CODE (recog_operand[i]) == REG | |
941 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
942 | { | |
943 | int regno = REGNO (recog_operand[i]); | |
944 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
945 | ||
946 | p->mem_cost += q->mem_cost * loop_cost; | |
947 | for (j = 0; j < N_REG_CLASSES; j++) | |
948 | p->cost[j] += q->cost[j] * loop_cost; | |
949 | } | |
54dac99e RK |
950 | } |
951 | } | |
54dac99e | 952 | |
e4600702 RK |
953 | /* Now for each register look at how desirable each class is |
954 | and find which class is preferred. Store that in | |
955 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
956 | class any of whose registers is better than memory. */ | |
54dac99e | 957 | |
e4600702 RK |
958 | if (pass == 0) |
959 | { | |
960 | prefclass = (char *) oballoc (nregs); | |
961 | altclass = (char *) oballoc (nregs); | |
962 | } | |
54dac99e | 963 | |
e4600702 | 964 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 965 | { |
ca3c6eae | 966 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
967 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
968 | /* This is an enum reg_class, but we call it an int | |
969 | to save lots of casts. */ | |
970 | register int class; | |
971 | register struct costs *p = &costs[i]; | |
972 | ||
973 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 974 | { |
533d0835 RK |
975 | /* Ignore classes that are too small for this operand or |
976 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 977 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
978 | > reg_class_size[class] |
979 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
980 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
981 | #endif | |
982 | ) | |
e4600702 RK |
983 | ; |
984 | else if (p->cost[class] < best_cost) | |
985 | { | |
986 | best_cost = p->cost[class]; | |
987 | best = (enum reg_class) class; | |
988 | } | |
989 | else if (p->cost[class] == best_cost) | |
990 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 991 | } |
54dac99e | 992 | |
e4600702 RK |
993 | /* Record the alternate register class; i.e., a class for which |
994 | every register in it is better than using memory. If adding a | |
995 | class would make a smaller class (i.e., no union of just those | |
996 | classes exists), skip that class. The major unions of classes | |
997 | should be provided as a register class. Don't do this if we | |
998 | will be doing it again later. */ | |
999 | ||
1000 | if (pass == 1 || ! flag_expensive_optimizations) | |
1001 | for (class = 0; class < N_REG_CLASSES; class++) | |
1002 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1003 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1004 | > reg_class_size[(int) alt]) |
1005 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1006 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1007 | #endif | |
1008 | ) | |
e4600702 RK |
1009 | alt = reg_class_subunion[(int) alt][class]; |
1010 | ||
1011 | /* If we don't add any classes, nothing to try. */ | |
1012 | if (alt == best) | |
995d54dd | 1013 | alt = NO_REGS; |
e4600702 RK |
1014 | |
1015 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
1016 | prefclass[i] = (int) best; | |
1017 | altclass[i] = (int) alt; | |
1018 | } | |
54dac99e RK |
1019 | } |
1020 | #endif /* REGISTER_CONSTRAINTS */ | |
1021 | } | |
1022 | \f | |
1023 | #ifdef REGISTER_CONSTRAINTS | |
1024 | ||
e4600702 RK |
1025 | /* Record the cost of using memory or registers of various classes for |
1026 | the operands in INSN. | |
54dac99e | 1027 | |
e4600702 | 1028 | N_ALTS is the number of alternatives. |
54dac99e | 1029 | |
e4600702 RK |
1030 | N_OPS is the number of operands. |
1031 | ||
1032 | OPS is an array of the operands. | |
1033 | ||
1034 | MODES are the modes of the operands, in case any are VOIDmode. | |
1035 | ||
1036 | CONSTRAINTS are the constraints to use for the operands. This array | |
1037 | is modified by this procedure. | |
1038 | ||
1039 | This procedure works alternative by alternative. For each alternative | |
1040 | we assume that we will be able to allocate all pseudos to their ideal | |
1041 | register class and calculate the cost of using that alternative. Then | |
1042 | we compute for each operand that is a pseudo-register, the cost of | |
1043 | having the pseudo allocated to each register class and using it in that | |
1044 | alternative. To this cost is added the cost of the alternative. | |
1045 | ||
1046 | The cost of each class for this insn is its lowest cost among all the | |
1047 | alternatives. */ | |
1048 | ||
1049 | static void | |
1050 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
1051 | int n_alts; | |
1052 | int n_ops; | |
1053 | rtx *ops; | |
1054 | enum machine_mode *modes; | |
54dac99e | 1055 | char **constraints; |
e4600702 | 1056 | rtx insn; |
54dac99e | 1057 | { |
e4600702 RK |
1058 | int alt; |
1059 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; | |
1060 | int i, j; | |
ec2d92af | 1061 | rtx set; |
e4600702 RK |
1062 | |
1063 | /* By default, each operand is an input operand. */ | |
1064 | ||
1065 | for (i = 0; i < n_ops; i++) | |
1066 | op_types[i] = OP_READ; | |
54dac99e | 1067 | |
e4600702 RK |
1068 | /* Process each alternative, each time minimizing an operand's cost with |
1069 | the cost for each operand in that alternative. */ | |
54dac99e | 1070 | |
e4600702 | 1071 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1072 | { |
e4600702 RK |
1073 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1074 | int alt_fail = 0; | |
1075 | int alt_cost = 0; | |
1076 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
1077 | int class; | |
54dac99e | 1078 | |
e4600702 RK |
1079 | for (i = 0; i < n_ops; i++) |
1080 | { | |
1081 | char *p = constraints[i]; | |
1082 | rtx op = ops[i]; | |
1083 | enum machine_mode mode = modes[i]; | |
1084 | int allows_mem = 0; | |
1085 | int win = 0; | |
1086 | char c; | |
54dac99e | 1087 | |
e4600702 RK |
1088 | /* If this operand has no constraints at all, we can conclude |
1089 | nothing about it since anything is valid. */ | |
54dac99e | 1090 | |
e4600702 RK |
1091 | if (*p == 0) |
1092 | { | |
1093 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1094 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1095 | |
e4600702 RK |
1096 | continue; |
1097 | } | |
54dac99e | 1098 | |
347099d6 RS |
1099 | if (*p == '%') |
1100 | p++; | |
1101 | ||
e4600702 RK |
1102 | /* If this alternative is only relevant when this operand |
1103 | matches a previous operand, we do different things depending | |
1104 | on whether this operand is a pseudo-reg or not. */ | |
54dac99e | 1105 | |
e4600702 RK |
1106 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1107 | { | |
1108 | j = p[0] - '0'; | |
1109 | classes[i] = classes[j]; | |
1110 | ||
1111 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1112 | { | |
1113 | /* If this matches the other operand, we have no added | |
dc903608 | 1114 | cost and we win. */ |
e4600702 | 1115 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1116 | win = 1; |
e4600702 | 1117 | |
77e67eac RK |
1118 | /* If we can put the other operand into a register, add to |
1119 | the cost of this alternative the cost to copy this | |
1120 | operand to the register used for the other operand. */ | |
e4600702 | 1121 | |
dc903608 | 1122 | else if (classes[j] != NO_REGS) |
77e67eac | 1123 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1124 | } |
07d8ca2d RS |
1125 | else if (GET_CODE (ops[j]) != REG |
1126 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1127 | { | |
1128 | /* This op is a pseudo but the one it matches is not. */ | |
1129 | ||
1130 | /* If we can't put the other operand into a register, this | |
1131 | alternative can't be used. */ | |
1132 | ||
1133 | if (classes[j] == NO_REGS) | |
1134 | alt_fail = 1; | |
e4600702 | 1135 | |
07d8ca2d RS |
1136 | /* Otherwise, add to the cost of this alternative the cost |
1137 | to copy the other operand to the register used for this | |
1138 | operand. */ | |
1139 | ||
1140 | else | |
1141 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1142 | } | |
e4600702 RK |
1143 | else |
1144 | { | |
1145 | /* The costs of this operand are the same as that of the | |
1146 | other operand. However, if we cannot tie them, this | |
1147 | alternative needs to do a copy, which is one | |
1148 | instruction. */ | |
1149 | ||
1150 | this_op_costs[i] = this_op_costs[j]; | |
37747c82 RK |
1151 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1152 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1153 | alt_cost += 2; | |
e4600702 | 1154 | |
347099d6 | 1155 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1156 | for this operand, so skip to the end of the |
1157 | alternative (should be just one character). */ | |
1158 | while (*p && *p++ != ',') | |
1159 | ; | |
1160 | ||
1161 | constraints[i] = p; | |
347099d6 RS |
1162 | continue; |
1163 | } | |
e4600702 RK |
1164 | } |
1165 | ||
1166 | /* Scan all the constraint letters. See if the operand matches | |
1167 | any of the constraints. Collect the valid register classes | |
1168 | and see if this operand accepts memory. */ | |
1169 | ||
1170 | classes[i] = NO_REGS; | |
1171 | while (*p && (c = *p++) != ',') | |
1172 | switch (c) | |
1173 | { | |
1174 | case '=': | |
1175 | op_types[i] = OP_WRITE; | |
1176 | break; | |
1177 | ||
1178 | case '+': | |
1179 | op_types[i] = OP_READ_WRITE; | |
1180 | break; | |
1181 | ||
1182 | case '*': | |
1183 | /* Ignore the next letter for this pass. */ | |
1184 | p++; | |
1185 | break; | |
1186 | ||
1187 | case '%': | |
1188 | case '?': case '!': case '#': | |
1189 | case '&': | |
1190 | case '0': case '1': case '2': case '3': case '4': | |
1191 | case 'p': | |
1192 | break; | |
1193 | ||
1194 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1195 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 RK |
1196 | and non-offsettable addresses here. */ |
1197 | allows_mem = 1; | |
1198 | if (GET_CODE (op) == MEM) | |
1199 | win = 1; | |
1200 | break; | |
1201 | ||
1202 | case '<': | |
1203 | if (GET_CODE (op) == MEM | |
1204 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1205 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1206 | win = 1; | |
1207 | break; | |
1208 | ||
1209 | case '>': | |
1210 | if (GET_CODE (op) == MEM | |
1211 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1212 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1213 | win = 1; | |
1214 | break; | |
1215 | ||
1216 | case 'E': | |
7ac2547f | 1217 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1218 | /* Match any floating double constant, but only if |
1219 | we can examine the bits of it reliably. */ | |
1220 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1221 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1222 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1223 | break; | |
7ac2547f | 1224 | #endif |
e4600702 RK |
1225 | if (GET_CODE (op) == CONST_DOUBLE) |
1226 | win = 1; | |
1227 | break; | |
1228 | ||
1229 | case 'F': | |
1230 | if (GET_CODE (op) == CONST_DOUBLE) | |
1231 | win = 1; | |
1232 | break; | |
1233 | ||
1234 | case 'G': | |
1235 | case 'H': | |
1236 | if (GET_CODE (op) == CONST_DOUBLE | |
1237 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1238 | win = 1; | |
1239 | break; | |
1240 | ||
1241 | case 's': | |
1242 | if (GET_CODE (op) == CONST_INT | |
1243 | || (GET_CODE (op) == CONST_DOUBLE | |
1244 | && GET_MODE (op) == VOIDmode)) | |
1245 | break; | |
1246 | case 'i': | |
1247 | if (CONSTANT_P (op) | |
1248 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1249 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1250 | #endif | |
1251 | ) | |
1252 | win = 1; | |
1253 | break; | |
1254 | ||
1255 | case 'n': | |
1256 | if (GET_CODE (op) == CONST_INT | |
1257 | || (GET_CODE (op) == CONST_DOUBLE | |
1258 | && GET_MODE (op) == VOIDmode)) | |
1259 | win = 1; | |
1260 | break; | |
1261 | ||
1262 | case 'I': | |
1263 | case 'J': | |
1264 | case 'K': | |
1265 | case 'L': | |
1266 | case 'M': | |
1267 | case 'N': | |
1268 | case 'O': | |
1269 | case 'P': | |
1270 | if (GET_CODE (op) == CONST_INT | |
1271 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1272 | win = 1; | |
1273 | break; | |
1274 | ||
1275 | case 'X': | |
1276 | win = 1; | |
1277 | break; | |
54dac99e | 1278 | |
54dac99e | 1279 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1280 | case 'Q': |
1281 | case 'R': | |
1282 | case 'S': | |
1283 | case 'T': | |
1284 | case 'U': | |
1285 | if (EXTRA_CONSTRAINT (op, c)) | |
1286 | win = 1; | |
1287 | break; | |
1288 | #endif | |
1289 | ||
1290 | case 'g': | |
1291 | if (GET_CODE (op) == MEM | |
1292 | || (CONSTANT_P (op) | |
1293 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1294 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1295 | #endif |
e4600702 RK |
1296 | )) |
1297 | win = 1; | |
1298 | allows_mem = 1; | |
1299 | case 'r': | |
1300 | classes[i] | |
1301 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1302 | break; | |
1303 | ||
1304 | default: | |
1305 | classes[i] | |
1306 | = reg_class_subunion[(int) classes[i]] | |
1307 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1308 | } | |
1309 | ||
1310 | constraints[i] = p; | |
1311 | ||
1312 | /* How we account for this operand now depends on whether it is a | |
1313 | pseudo register or not. If it is, we first check if any | |
1314 | register classes are valid. If not, we ignore this alternative, | |
1315 | since we want to assume that all pseudos get allocated for | |
1316 | register preferencing. If some register class is valid, compute | |
1317 | the costs of moving the pseudo into that class. */ | |
1318 | ||
1319 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1320 | { |
e4600702 RK |
1321 | if (classes[i] == NO_REGS) |
1322 | alt_fail = 1; | |
1323 | else | |
1324 | { | |
1325 | struct costs *pp = &this_op_costs[i]; | |
1326 | ||
1327 | for (class = 0; class < N_REG_CLASSES; class++) | |
1328 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1329 | ||
1330 | /* If the alternative actually allows memory, make things | |
1331 | a bit cheaper since we won't need an extra insn to | |
1332 | load it. */ | |
1333 | ||
cbd5b9a2 KR |
1334 | pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) |
1335 | - allows_mem); | |
e4600702 RK |
1336 | |
1337 | /* If we have assigned a class to this register in our | |
1338 | first pass, add a cost to this alternative corresponding | |
1339 | to what we would add if this register were not in the | |
1340 | appropriate class. */ | |
1341 | ||
1342 | if (prefclass) | |
1343 | alt_cost | |
1344 | += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; | |
1345 | } | |
4db18574 | 1346 | } |
54dac99e | 1347 | |
e4600702 RK |
1348 | /* Otherwise, if this alternative wins, either because we |
1349 | have already determined that or if we have a hard register of | |
1350 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1351 | |
e4600702 RK |
1352 | else if (win |
1353 | || (GET_CODE (op) == REG | |
6f654776 | 1354 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1355 | ; |
54dac99e | 1356 | |
e4600702 RK |
1357 | /* If registers are valid, the cost of this alternative includes |
1358 | copying the object to and/or from a register. */ | |
54dac99e | 1359 | |
e4600702 RK |
1360 | else if (classes[i] != NO_REGS) |
1361 | { | |
1362 | if (op_types[i] != OP_WRITE) | |
1363 | alt_cost += copy_cost (op, mode, classes[i], 1); | |
54dac99e | 1364 | |
e4600702 RK |
1365 | if (op_types[i] != OP_READ) |
1366 | alt_cost += copy_cost (op, mode, classes[i], 0); | |
1367 | } | |
54dac99e | 1368 | |
e4600702 RK |
1369 | /* The only other way this alternative can be used is if this is a |
1370 | constant that could be placed into memory. */ | |
1371 | ||
1372 | else if (CONSTANT_P (op) && allows_mem) | |
cbd5b9a2 | 1373 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1374 | else |
1375 | alt_fail = 1; | |
1376 | } | |
1377 | ||
1378 | if (alt_fail) | |
1379 | continue; | |
1380 | ||
1381 | /* Finally, update the costs with the information we've calculated | |
1382 | about this alternative. */ | |
1383 | ||
1384 | for (i = 0; i < n_ops; i++) | |
1385 | if (GET_CODE (ops[i]) == REG | |
1386 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1387 | { |
e4600702 RK |
1388 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1389 | int scale = 1 + (op_types[i] == OP_READ_WRITE); | |
54dac99e | 1390 | |
e4600702 RK |
1391 | pp->mem_cost = MIN (pp->mem_cost, |
1392 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1393 | |
e4600702 RK |
1394 | for (class = 0; class < N_REG_CLASSES; class++) |
1395 | pp->cost[class] = MIN (pp->cost[class], | |
1396 | (qq->cost[class] + alt_cost) * scale); | |
1397 | } | |
1398 | } | |
ec2d92af RK |
1399 | |
1400 | /* If this insn is a single set copying operand 1 to operand 0 | |
1401 | and one is a pseudo with the other a hard reg that is in its | |
1402 | own register class, set the cost of that register class to -1. */ | |
1403 | ||
1404 | if ((set = single_set (insn)) != 0 | |
1405 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1406 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1407 | for (i = 0; i <= 1; i++) | |
1408 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1409 | { | |
1410 | int regno = REGNO (ops[!i]); | |
1411 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1412 | int class; | |
4841ba4b | 1413 | int nr; |
ec2d92af RK |
1414 | |
1415 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 | |
1416 | && (reg_class_size[prefclass[regno]] | |
1417 | == CLASS_MAX_NREGS (prefclass[regno], mode))) | |
1418 | op_costs[i].cost[prefclass[regno]] = -1; | |
1419 | else if (regno < FIRST_PSEUDO_REGISTER) | |
1420 | for (class = 0; class < N_REG_CLASSES; class++) | |
1421 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1422 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1423 | { |
1424 | if (reg_class_size[class] == 1) | |
1425 | op_costs[i].cost[class] = -1; | |
1426 | else | |
1427 | { | |
1428 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1429 | { | |
1430 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1431 | break; | |
1432 | } | |
1433 | ||
1434 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1435 | op_costs[i].cost[class] = -1; | |
1436 | } | |
1437 | } | |
ec2d92af | 1438 | } |
54dac99e | 1439 | } |
e4600702 RK |
1440 | \f |
1441 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1442 | TO_P is zero) a register of class CLASS in mode MODE. | |
1443 | ||
1444 | X must not be a pseudo. */ | |
1445 | ||
1446 | static int | |
1447 | copy_cost (x, mode, class, to_p) | |
1448 | rtx x; | |
1449 | enum machine_mode mode; | |
1450 | enum reg_class class; | |
1451 | int to_p; | |
1452 | { | |
29a82058 | 1453 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1454 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1455 | #endif |
e4600702 RK |
1456 | |
1457 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1458 | assuming optimal allocation. */ | |
1459 | ||
1460 | if (GET_CODE (x) == SCRATCH) | |
1461 | return 0; | |
1462 | ||
1463 | /* Get the class we will actually use for a reload. */ | |
1464 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1465 | ||
1466 | #ifdef HAVE_SECONDARY_RELOADS | |
1467 | /* If we need a secondary reload (we assume here that we are using | |
1468 | the secondary reload as an intermediate, not a scratch register), the | |
1469 | cost is that to load the input into the intermediate register, then | |
1470 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1471 | ||
1472 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1473 | if (to_p == 1) | |
1474 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1475 | #endif | |
1476 | ||
dd9f0e8f | 1477 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1478 | if (! to_p) |
1479 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1480 | #endif | |
1481 | ||
1482 | if (secondary_class != NO_REGS) | |
1483 | return (move_cost[(int) secondary_class][(int) class] | |
1484 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1485 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1486 | |
1487 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1488 | cost to move between the register classes, and use 2 for everything | |
1489 | else (constants). */ | |
1490 | ||
1491 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1492 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1493 | |
e4600702 RK |
1494 | else if (GET_CODE (x) == REG) |
1495 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1496 | ||
1497 | else | |
1498 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1499 | return 2; | |
1500 | } | |
1501 | \f | |
54dac99e RK |
1502 | /* Record the pseudo registers we must reload into hard registers |
1503 | in a subexpression of a memory address, X. | |
e4600702 RK |
1504 | |
1505 | CLASS is the class that the register needs to be in and is either | |
1506 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1507 | ||
1508 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1509 | can represent half-cost adjustments). */ | |
54dac99e | 1510 | |
197d6480 | 1511 | static void |
e4600702 | 1512 | record_address_regs (x, class, scale) |
54dac99e | 1513 | rtx x; |
e4600702 RK |
1514 | enum reg_class class; |
1515 | int scale; | |
54dac99e RK |
1516 | { |
1517 | register enum rtx_code code = GET_CODE (x); | |
1518 | ||
1519 | switch (code) | |
1520 | { | |
1521 | case CONST_INT: | |
1522 | case CONST: | |
1523 | case CC0: | |
1524 | case PC: | |
1525 | case SYMBOL_REF: | |
1526 | case LABEL_REF: | |
1527 | return; | |
1528 | ||
1529 | case PLUS: | |
1530 | /* When we have an address that is a sum, | |
1531 | we must determine whether registers are "base" or "index" regs. | |
1532 | If there is a sum of two registers, we must choose one to be | |
1533 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1534 | to make a good choice most of the time. We only need to do this |
1535 | on machines that can have two registers in an address and where | |
1536 | the base and index register classes are different. | |
1537 | ||
1538 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1539 | that seems bogus since it should only be set when we are sure | |
1540 | the register is being used as a pointer. */ | |
1541 | ||
54dac99e RK |
1542 | { |
1543 | rtx arg0 = XEXP (x, 0); | |
1544 | rtx arg1 = XEXP (x, 1); | |
1545 | register enum rtx_code code0 = GET_CODE (arg0); | |
1546 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1547 | |
1548 | /* Look inside subregs. */ | |
e4600702 | 1549 | if (code0 == SUBREG) |
54dac99e | 1550 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1551 | if (code1 == SUBREG) |
54dac99e RK |
1552 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1553 | ||
e4600702 RK |
1554 | /* If this machine only allows one register per address, it must |
1555 | be in the first operand. */ | |
1556 | ||
1557 | if (MAX_REGS_PER_ADDRESS == 1) | |
1558 | record_address_regs (arg0, class, scale); | |
1559 | ||
1560 | /* If index and base registers are the same on this machine, just | |
1561 | record registers in any non-constant operands. We assume here, | |
1562 | as well as in the tests below, that all addresses are in | |
1563 | canonical form. */ | |
1564 | ||
1565 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1566 | { |
e4600702 RK |
1567 | record_address_regs (arg0, class, scale); |
1568 | if (! CONSTANT_P (arg1)) | |
1569 | record_address_regs (arg1, class, scale); | |
54dac99e | 1570 | } |
e4600702 RK |
1571 | |
1572 | /* If the second operand is a constant integer, it doesn't change | |
1573 | what class the first operand must be. */ | |
1574 | ||
1575 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1576 | record_address_regs (arg0, class, scale); | |
1577 | ||
1578 | /* If the second operand is a symbolic constant, the first operand | |
1579 | must be an index register. */ | |
1580 | ||
1581 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1582 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1583 | ||
956d6950 JL |
1584 | /* If both operands are registers but one is already a hard register |
1585 | of index or base class, give the other the class that the hard | |
1586 | register is not. */ | |
1587 | ||
3f9e9508 | 1588 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1589 | else if (code0 == REG && code1 == REG |
1590 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1591 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1592 | record_address_regs (arg1, | |
1593 | REG_OK_FOR_BASE_P (arg0) | |
1594 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1595 | scale); | |
1596 | else if (code0 == REG && code1 == REG | |
1597 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1598 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1599 | record_address_regs (arg0, | |
1600 | REG_OK_FOR_BASE_P (arg1) | |
1601 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1602 | scale); | |
3f9e9508 | 1603 | #endif |
956d6950 | 1604 | |
e9a25f70 JL |
1605 | /* If one operand is known to be a pointer, it must be the base |
1606 | with the other operand the index. Likewise if the other operand | |
1607 | is a MULT. */ | |
f22376c7 | 1608 | |
e9a25f70 JL |
1609 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1610 | || code1 == MULT) | |
f22376c7 CI |
1611 | { |
1612 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1613 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1614 | } | |
e9a25f70 JL |
1615 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1616 | || code0 == MULT) | |
f22376c7 CI |
1617 | { |
1618 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1619 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1620 | } | |
1621 | ||
e9a25f70 | 1622 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1623 | or index register. This case should be rare. */ |
1624 | ||
e9a25f70 | 1625 | else |
54dac99e | 1626 | { |
e4600702 RK |
1627 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1628 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1629 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1630 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1631 | } |
54dac99e RK |
1632 | } |
1633 | break; | |
1634 | ||
1635 | case POST_INC: | |
1636 | case PRE_INC: | |
1637 | case POST_DEC: | |
1638 | case PRE_DEC: | |
1639 | /* Double the importance of a pseudo register that is incremented | |
1640 | or decremented, since it would take two extra insns | |
533d0835 RK |
1641 | if it ends up in the wrong place. If the operand is a pseudo, |
1642 | show it is being used in an INC_DEC context. */ | |
1643 | ||
1644 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1645 | if (GET_CODE (XEXP (x, 0)) == REG | |
1646 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1647 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1648 | #endif | |
e4600702 RK |
1649 | |
1650 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1651 | break; |
1652 | ||
1653 | case REG: | |
1654 | { | |
e4600702 RK |
1655 | register struct costs *pp = &costs[REGNO (x)]; |
1656 | register int i; | |
54dac99e | 1657 | |
cbd5b9a2 | 1658 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1659 | |
e4600702 RK |
1660 | for (i = 0; i < N_REG_CLASSES; i++) |
1661 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1662 | } |
1663 | break; | |
1664 | ||
1665 | default: | |
1666 | { | |
1667 | register char *fmt = GET_RTX_FORMAT (code); | |
1668 | register int i; | |
1669 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1670 | if (fmt[i] == 'e') | |
e4600702 | 1671 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1672 | } |
1673 | } | |
1674 | } | |
08d95f91 RK |
1675 | \f |
1676 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1677 | ||
1678 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1679 | to an object of MODE. */ | |
1680 | ||
1d300e19 | 1681 | static int |
08d95f91 RK |
1682 | auto_inc_dec_reg_p (reg, mode) |
1683 | rtx reg; | |
1684 | enum machine_mode mode; | |
1685 | { | |
1686 | #ifdef HAVE_POST_INCREMENT | |
38a448ca | 1687 | if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) |
08d95f91 RK |
1688 | return 1; |
1689 | #endif | |
1690 | ||
1691 | #ifdef HAVE_POST_DECREMENT | |
38a448ca | 1692 | if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) |
08d95f91 RK |
1693 | return 1; |
1694 | #endif | |
1695 | ||
1696 | #ifdef HAVE_PRE_INCREMENT | |
38a448ca | 1697 | if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) |
08d95f91 RK |
1698 | return 1; |
1699 | #endif | |
1700 | ||
1701 | #ifdef HAVE_PRE_DECREMENT | |
38a448ca | 1702 | if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) |
08d95f91 RK |
1703 | return 1; |
1704 | #endif | |
1705 | ||
1706 | return 0; | |
1707 | } | |
1708 | #endif | |
1709 | ||
54dac99e | 1710 | #endif /* REGISTER_CONSTRAINTS */ |
b1f21e0a MM |
1711 | \f |
1712 | /* Allocate enough space to hold NUM_REGS registers for the tables used for | |
1713 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1714 | NEW_P is non zero, initialize all of the registers, otherwise only |
1715 | initialize the new registers allocated. The same table is kept from | |
1716 | function to function, only reallocating it when we need more room. If | |
1717 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1718 | |
1719 | void | |
39379e67 | 1720 | allocate_reg_info (num_regs, new_p, renumber_p) |
b1f21e0a MM |
1721 | int num_regs; |
1722 | int new_p; | |
39379e67 | 1723 | int renumber_p; |
b1f21e0a MM |
1724 | { |
1725 | static int regno_allocated = 0; | |
1726 | static int regno_max = 0; | |
39379e67 | 1727 | static short *renumber = (short *)0; |
b1f21e0a | 1728 | int i; |
39379e67 MM |
1729 | int size_info; |
1730 | int size_renumber; | |
7ec189f2 | 1731 | int min = (new_p) ? 0 : regno_max; |
b1f21e0a | 1732 | |
39379e67 MM |
1733 | /* If this message come up, and you want to fix it, then all of the tables |
1734 | like reg_renumber, etc. that use short will have to be found and lengthed | |
1735 | to int or HOST_WIDE_INT. */ | |
1736 | ||
1737 | /* Free up all storage allocated */ | |
1738 | if (num_regs < 0) | |
1739 | { | |
1740 | if (reg_n_info) | |
1741 | { | |
1742 | free ((char *)reg_n_info); | |
1743 | free ((char *)renumber); | |
1744 | reg_n_info = (reg_info *)0; | |
1745 | renumber = (short *)0; | |
1746 | } | |
1747 | regno_allocated = 0; | |
1748 | regno_max = 0; | |
1749 | return; | |
1750 | } | |
1751 | ||
b1f21e0a MM |
1752 | if (num_regs > regno_allocated) |
1753 | { | |
1754 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ | |
39379e67 MM |
1755 | size_info = regno_allocated * sizeof (reg_info); |
1756 | size_renumber = regno_allocated * sizeof (short); | |
1757 | ||
1758 | if (!reg_n_info) | |
1759 | { | |
1760 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1761 | renumber = (short *) xmalloc (size_renumber); | |
1762 | } | |
1763 | ||
1764 | else if (new_p) /* if we're zapping everything, no need to realloc */ | |
1765 | { | |
1766 | free ((char *)reg_n_info); | |
1767 | free ((char *)renumber); | |
1768 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1769 | renumber = (short *) xmalloc (size_renumber); | |
1770 | } | |
1771 | ||
1772 | else | |
1773 | { | |
1774 | reg_n_info = (reg_info *) xrealloc ((char *)reg_n_info, size_info); | |
1775 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
1776 | } | |
b1f21e0a MM |
1777 | } |
1778 | ||
1779 | if (min < num_regs) | |
1780 | { | |
1781 | bzero ((char *) ®_n_info[min], (num_regs - min) * sizeof (reg_info)); | |
1782 | for (i = min; i < num_regs; i++) | |
39379e67 MM |
1783 | { |
1784 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
1785 | renumber[i] = -1; | |
1786 | } | |
b1f21e0a MM |
1787 | } |
1788 | ||
39379e67 MM |
1789 | if (renumber_p) |
1790 | reg_renumber = renumber; | |
1791 | ||
73b76448 RK |
1792 | /* Tell the regset code about the new number of registers */ |
1793 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
1794 | ||
b1f21e0a MM |
1795 | regno_max = num_regs; |
1796 | } | |
1797 | ||
54dac99e RK |
1798 | \f |
1799 | /* This is the `regscan' pass of the compiler, run just before cse | |
1800 | and again just before loop. | |
1801 | ||
1802 | It finds the first and last use of each pseudo-register | |
1803 | and records them in the vectors regno_first_uid, regno_last_uid | |
1804 | and counts the number of sets in the vector reg_n_sets. | |
1805 | ||
1806 | REPEAT is nonzero the second time this is called. */ | |
1807 | ||
54dac99e | 1808 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 1809 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
1810 | and we want this to remain correct for all the remaining passes. */ |
1811 | ||
1812 | int max_parallel; | |
1813 | ||
54dac99e RK |
1814 | void |
1815 | reg_scan (f, nregs, repeat) | |
1816 | rtx f; | |
1817 | int nregs; | |
1818 | int repeat; | |
1819 | { | |
1820 | register rtx insn; | |
1821 | ||
39379e67 | 1822 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
1823 | max_parallel = 3; |
1824 | ||
1825 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1826 | if (GET_CODE (insn) == INSN | |
1827 | || GET_CODE (insn) == CALL_INSN | |
1828 | || GET_CODE (insn) == JUMP_INSN) | |
1829 | { | |
1830 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1831 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1832 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
1ebecb64 | 1833 | reg_scan_mark_refs (PATTERN (insn), insn, 0); |
01565a55 RK |
1834 | |
1835 | if (REG_NOTES (insn)) | |
1836 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1); | |
54dac99e RK |
1837 | } |
1838 | } | |
1839 | ||
1ebecb64 RS |
1840 | /* X is the expression to scan. INSN is the insn it appears in. |
1841 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ | |
1842 | ||
08d95f91 | 1843 | static void |
1ebecb64 | 1844 | reg_scan_mark_refs (x, insn, note_flag) |
54dac99e | 1845 | rtx x; |
be8dcd74 | 1846 | rtx insn; |
1ebecb64 | 1847 | int note_flag; |
54dac99e RK |
1848 | { |
1849 | register enum rtx_code code = GET_CODE (x); | |
1850 | register rtx dest; | |
be8dcd74 | 1851 | register rtx note; |
54dac99e RK |
1852 | |
1853 | switch (code) | |
1854 | { | |
1855 | case CONST_INT: | |
1856 | case CONST: | |
1857 | case CONST_DOUBLE: | |
1858 | case CC0: | |
1859 | case PC: | |
1860 | case SYMBOL_REF: | |
1861 | case LABEL_REF: | |
1862 | case ADDR_VEC: | |
1863 | case ADDR_DIFF_VEC: | |
1864 | return; | |
1865 | ||
1866 | case REG: | |
1867 | { | |
1868 | register int regno = REGNO (x); | |
1869 | ||
b1f21e0a | 1870 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); |
1ebecb64 | 1871 | if (!note_flag) |
b1f21e0a MM |
1872 | REGNO_LAST_UID (regno) = INSN_UID (insn); |
1873 | if (REGNO_FIRST_UID (regno) == 0) | |
1874 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
54dac99e RK |
1875 | } |
1876 | break; | |
1877 | ||
01565a55 | 1878 | case EXPR_LIST: |
7b18c3db RS |
1879 | if (XEXP (x, 0)) |
1880 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); | |
01565a55 RK |
1881 | if (XEXP (x, 1)) |
1882 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1883 | break; | |
1884 | ||
1885 | case INSN_LIST: | |
1886 | if (XEXP (x, 1)) | |
1887 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1888 | break; | |
1889 | ||
54dac99e RK |
1890 | case SET: |
1891 | /* Count a set of the destination if it is a register. */ | |
1892 | for (dest = SET_DEST (x); | |
1893 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
1894 | || GET_CODE (dest) == ZERO_EXTEND; | |
1895 | dest = XEXP (dest, 0)) | |
1896 | ; | |
1897 | ||
1898 | if (GET_CODE (dest) == REG) | |
b1f21e0a | 1899 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 1900 | |
be8dcd74 RK |
1901 | /* If this is setting a pseudo from another pseudo or the sum of a |
1902 | pseudo and a constant integer and the other pseudo is known to be | |
1903 | a pointer, set the destination to be a pointer as well. | |
1904 | ||
1905 | Likewise if it is setting the destination from an address or from a | |
1906 | value equivalent to an address or to the sum of an address and | |
1907 | something else. | |
1908 | ||
1909 | But don't do any of this if the pseudo corresponds to a user | |
1910 | variable since it should have already been set as a pointer based | |
1911 | on the type. */ | |
1912 | ||
1913 | if (GET_CODE (SET_DEST (x)) == REG | |
1914 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
1915 | && ! REG_USERVAR_P (SET_DEST (x)) | |
1916 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
1917 | && ((GET_CODE (SET_SRC (x)) == REG | |
1918 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
1919 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1920 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1921 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
1922 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
1923 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
1924 | || GET_CODE (SET_SRC (x)) == CONST | |
1925 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
1926 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
1927 | || (GET_CODE (SET_SRC (x)) == HIGH | |
1928 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
1929 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
1930 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
1931 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1932 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1933 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
1934 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
1935 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
1936 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
1937 | && (GET_CODE (XEXP (note, 0)) == CONST | |
1938 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
1939 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
1940 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
1941 | ||
0f41302f | 1942 | /* ... fall through ... */ |
54dac99e RK |
1943 | |
1944 | default: | |
1945 | { | |
1946 | register char *fmt = GET_RTX_FORMAT (code); | |
1947 | register int i; | |
1948 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1949 | { | |
1950 | if (fmt[i] == 'e') | |
1ebecb64 | 1951 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag); |
54dac99e RK |
1952 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
1953 | { | |
1954 | register int j; | |
1955 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1ebecb64 | 1956 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); |
54dac99e RK |
1957 | } |
1958 | } | |
1959 | } | |
1960 | } | |
1961 | } | |
1962 | \f | |
1963 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
1964 | is also in C2. */ | |
1965 | ||
1966 | int | |
1967 | reg_class_subset_p (c1, c2) | |
1968 | register enum reg_class c1; | |
1969 | register enum reg_class c2; | |
1970 | { | |
1971 | if (c1 == c2) return 1; | |
1972 | ||
1973 | if (c2 == ALL_REGS) | |
1974 | win: | |
1975 | return 1; | |
1976 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
1977 | reg_class_contents[(int)c2], | |
1978 | win); | |
1979 | return 0; | |
1980 | } | |
1981 | ||
1982 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
1983 | ||
1984 | int | |
1985 | reg_classes_intersect_p (c1, c2) | |
1986 | register enum reg_class c1; | |
1987 | register enum reg_class c2; | |
1988 | { | |
1989 | #ifdef HARD_REG_SET | |
1990 | register | |
1991 | #endif | |
1992 | HARD_REG_SET c; | |
1993 | ||
1994 | if (c1 == c2) return 1; | |
1995 | ||
1996 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
1997 | return 1; | |
1998 | ||
1999 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2000 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2001 | ||
2002 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2003 | return 1; | |
2004 | ||
2005 | lose: | |
2006 | return 0; | |
2007 | } | |
2008 | ||
73b76448 RK |
2009 | /* Release any memory allocated by register sets. */ |
2010 | ||
2011 | void | |
2012 | regset_release_memory () | |
2013 | { | |
2014 | if (basic_block_live_at_start) | |
2015 | { | |
2016 | free_regset_vector (basic_block_live_at_start, n_basic_blocks); | |
2017 | basic_block_live_at_start = 0; | |
2018 | } | |
2019 | ||
2020 | FREE_REG_SET (regs_live_at_setjmp); | |
2021 | bitmap_release_memory (); | |
2022 | } |