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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
f4f4d0f8 | 3 | 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
54dac99e | 4 | |
1322177d | 5 | This file is part of GCC. |
54dac99e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
54dac99e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
54dac99e RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
54dac99e RK |
21 | |
22 | ||
23 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
24 | It also defines some tables of information about the hardware registers | |
25 | and a function init_reg_sets to initialize the tables. */ | |
26 | ||
27 | #include "config.h" | |
670ee920 | 28 | #include "system.h" |
54dac99e | 29 | #include "rtl.h" |
0829d244 | 30 | #include "expr.h" |
6baf1cc8 | 31 | #include "tm_p.h" |
54dac99e RK |
32 | #include "hard-reg-set.h" |
33 | #include "flags.h" | |
34 | #include "basic-block.h" | |
35 | #include "regs.h" | |
49ad7cfa | 36 | #include "function.h" |
54dac99e RK |
37 | #include "insn-config.h" |
38 | #include "recog.h" | |
e4600702 RK |
39 | #include "reload.h" |
40 | #include "real.h" | |
10f0ad3d | 41 | #include "toplev.h" |
d6f4ec51 | 42 | #include "output.h" |
8b0212ca | 43 | #include "ggc.h" |
54dac99e RK |
44 | |
45 | #ifndef REGISTER_MOVE_COST | |
e56b4594 | 46 | #define REGISTER_MOVE_COST(m, x, y) 2 |
54dac99e RK |
47 | #endif |
48 | ||
13536812 KG |
49 | static void init_reg_sets_1 PARAMS ((void)); |
50 | static void init_reg_modes PARAMS ((void)); | |
24deb20a | 51 | |
533d0835 RK |
52 | /* If we have auto-increment or auto-decrement and we can have secondary |
53 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 54 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
55 | |
56 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 57 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
58 | #define FORBIDDEN_INC_DEC_CLASSES |
59 | #endif | |
60 | #endif | |
54dac99e RK |
61 | \f |
62 | /* Register tables used by many passes. */ | |
63 | ||
64 | /* Indexed by hard register number, contains 1 for registers | |
65 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
66 | These are the registers that cannot be used to allocate | |
252f342a | 67 | a pseudo reg for general use. */ |
54dac99e RK |
68 | |
69 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
70 | ||
71 | /* Same info as a HARD_REG_SET. */ | |
72 | ||
73 | HARD_REG_SET fixed_reg_set; | |
74 | ||
75 | /* Data for initializing the above. */ | |
76 | ||
8b60264b | 77 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
54dac99e RK |
78 | |
79 | /* Indexed by hard register number, contains 1 for registers | |
80 | that are fixed use or are clobbered by function calls. | |
81 | These are the registers that cannot be used to allocate | |
252f342a MH |
82 | a pseudo reg whose life crosses calls unless we are able |
83 | to save/restore them across the calls. */ | |
54dac99e RK |
84 | |
85 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
86 | ||
87 | /* Same info as a HARD_REG_SET. */ | |
88 | ||
89 | HARD_REG_SET call_used_reg_set; | |
90 | ||
6cad67d2 JL |
91 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
92 | HARD_REG_SET losing_caller_save_reg_set; | |
93 | ||
54dac99e RK |
94 | /* Data for initializing the above. */ |
95 | ||
8b60264b | 96 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
fc1296b7 AM |
97 | |
98 | /* This is much like call_used_regs, except it doesn't have to | |
99 | be a superset of FIXED_REGISTERS. This vector indicates | |
a6a2274a | 100 | what is really call clobbered, and is used when defining |
fc1296b7 AM |
101 | regs_invalidated_by_call. */ |
102 | ||
fc1296b7 | 103 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa | 104 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
fc1296b7 | 105 | #endif |
a6a2274a | 106 | |
54dac99e | 107 | /* Indexed by hard register number, contains 1 for registers that are |
252f342a MH |
108 | fixed use or call used registers that cannot hold quantities across |
109 | calls even if we are willing to save and restore them. call fixed | |
110 | registers are a subset of call used registers. */ | |
54dac99e RK |
111 | |
112 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
113 | ||
114 | /* The same info as a HARD_REG_SET. */ | |
115 | ||
116 | HARD_REG_SET call_fixed_reg_set; | |
117 | ||
118 | /* Number of non-fixed registers. */ | |
119 | ||
120 | int n_non_fixed_regs; | |
121 | ||
122 | /* Indexed by hard register number, contains 1 for registers | |
123 | that are being used for global register decls. | |
124 | These must be exempt from ordinary flow analysis | |
125 | and are also considered fixed. */ | |
126 | ||
127 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
4e2db584 RH |
128 | |
129 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
130 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
131 | for someone's bright idea to have call_used_regs strictly include | |
132 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
133 | that are actually preserved. We know for sure that those associated | |
134 | with the local stack frame are safe, but scant others. */ | |
135 | ||
136 | HARD_REG_SET regs_invalidated_by_call; | |
137 | ||
54dac99e RK |
138 | /* Table of register numbers in the order in which to try to use them. */ |
139 | #ifdef REG_ALLOC_ORDER | |
140 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
141 | |
142 | /* The inverse of reg_alloc_order. */ | |
143 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
144 | #endif |
145 | ||
146 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
147 | ||
2e0e2b76 CH |
148 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
149 | ||
089e575b RS |
150 | /* The same information, but as an array of unsigned ints. We copy from |
151 | these unsigned ints to the table above. We do this so the tm.h files | |
d4845339 RH |
152 | do not have to be aware of the wordsize for machines with <= 64 regs. |
153 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
2e0e2b76 CH |
154 | |
155 | #define N_REG_INTS \ | |
d4845339 | 156 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
2e0e2b76 | 157 | |
a6a2274a | 158 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 159 | = REG_CLASS_CONTENTS; |
54dac99e RK |
160 | |
161 | /* For each reg class, number of regs it contains. */ | |
162 | ||
770ae6cc | 163 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
164 | |
165 | /* For each reg class, table listing all the containing classes. */ | |
166 | ||
167 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
168 | ||
169 | /* For each reg class, table listing all the classes contained in it. */ | |
170 | ||
171 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
172 | ||
173 | /* For each pair of reg classes, | |
174 | a largest reg class contained in their union. */ | |
175 | ||
176 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
177 | ||
178 | /* For each pair of reg classes, | |
179 | the smallest reg class containing their union. */ | |
180 | ||
181 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
182 | ||
fbd40359 ZW |
183 | /* Array containing all of the register names. Unless |
184 | DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ | |
d05c8ee7 | 185 | |
fbd40359 | 186 | #ifdef DEBUG_REGISTER_NAMES |
e087aeb2 | 187 | const char * reg_names[] = REGISTER_NAMES; |
fbd40359 | 188 | #endif |
d05c8ee7 | 189 | |
ca4aac00 DE |
190 | /* For each hard register, the widest mode object that it can contain. |
191 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
192 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
193 | register. */ | |
194 | ||
195 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
196 | ||
6df26b8f JH |
197 | /* 1 if class does contain register of given mode. */ |
198 | ||
199 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
200 | ||
e4600702 RK |
201 | /* Maximum cost of moving from a register in one class to a register in |
202 | another class. Based on REGISTER_MOVE_COST. */ | |
203 | ||
e56b4594 | 204 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
205 | |
206 | /* Similar, but here we don't have to move if the first index is a subset | |
207 | of the second so in that case the cost is zero. */ | |
208 | ||
e56b4594 | 209 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
210 | |
211 | /* Similar, but here we don't have to move if the first index is a superset | |
212 | of the second so in that case the cost is zero. */ | |
213 | ||
e56b4594 | 214 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 215 | |
533d0835 RK |
216 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
217 | ||
218 | /* These are the classes that regs which are auto-incremented or decremented | |
219 | cannot be put in. */ | |
220 | ||
221 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
222 | ||
223 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
224 | context. */ | |
225 | ||
226 | static char *in_inc_dec; | |
227 | ||
5fcb671c | 228 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 229 | |
02188693 | 230 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
231 | |
232 | /* These are the classes containing only registers that can be used in | |
02188693 RH |
233 | a SUBREG expression that changes the mode of the register in some |
234 | way that is illegal. */ | |
e79f71f7 | 235 | |
02188693 | 236 | static int class_can_change_mode[N_REG_CLASSES]; |
e79f71f7 | 237 | |
02188693 RH |
238 | /* Registers, including pseudos, which change modes in some way that |
239 | is illegal. */ | |
e79f71f7 | 240 | |
02188693 | 241 | static regset reg_changes_mode; |
e79f71f7 | 242 | |
02188693 | 243 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
e79f71f7 | 244 | |
473fe49b KR |
245 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
246 | ||
e2500fed | 247 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
473fe49b | 248 | |
6feacd09 MM |
249 | /* Linked list of reg_info structures allocated for reg_n_info array. |
250 | Grouping all of the allocated structures together in one lump | |
251 | means only one call to bzero to clear them, rather than n smaller | |
252 | calls. */ | |
253 | struct reg_info_data { | |
254 | struct reg_info_data *next; /* next set of reg_info structures */ | |
255 | size_t min_index; /* minimum index # */ | |
256 | size_t max_index; /* maximum index # */ | |
257 | char used_p; /* non-zero if this has been used previously */ | |
258 | reg_info data[1]; /* beginning of the reg_info data */ | |
259 | }; | |
260 | ||
261 | static struct reg_info_data *reg_info_head; | |
262 | ||
c07c7c9d | 263 | /* No more global register variables may be declared; true once |
dc297297 | 264 | regclass has been initialized. */ |
6c85df69 AH |
265 | |
266 | static int no_global_reg_vars = 0; | |
267 | ||
6feacd09 | 268 | |
54dac99e RK |
269 | /* Function called only once to initialize the above data on reg usage. |
270 | Once this is done, various switches may override. */ | |
271 | ||
272 | void | |
273 | init_reg_sets () | |
274 | { | |
b3694847 | 275 | int i, j; |
54dac99e | 276 | |
2e0e2b76 CH |
277 | /* First copy the register information from the initial int form into |
278 | the regsets. */ | |
279 | ||
280 | for (i = 0; i < N_REG_CLASSES; i++) | |
281 | { | |
282 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
283 | ||
b85946fc | 284 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
2e0e2b76 | 285 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
b85946fc RH |
286 | if (int_reg_class_contents[i][j / 32] |
287 | & ((unsigned) 1 << (j % 32))) | |
2e0e2b76 CH |
288 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
289 | } | |
290 | ||
4e135bdd KG |
291 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
292 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 293 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 294 | |
910bc42d R |
295 | /* Do any additional initialization regsets may need */ |
296 | INIT_ONCE_REG_SET (); | |
f5d8c9f4 BS |
297 | |
298 | #ifdef REG_ALLOC_ORDER | |
299 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
300 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
301 | #endif | |
910bc42d R |
302 | } |
303 | ||
304 | /* After switches have been processed, which perhaps alter | |
305 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
306 | ||
307 | static void | |
308 | init_reg_sets_1 () | |
309 | { | |
b3694847 SS |
310 | unsigned int i, j; |
311 | unsigned int /* enum machine_mode */ m; | |
6836e024 | 312 | char allocatable_regs_of_mode [MAX_MACHINE_MODE]; |
910bc42d R |
313 | |
314 | /* This macro allows the fixed or call-used registers | |
315 | and the register classes to depend on target flags. */ | |
316 | ||
317 | #ifdef CONDITIONAL_REGISTER_USAGE | |
318 | CONDITIONAL_REGISTER_USAGE; | |
319 | #endif | |
320 | ||
54dac99e RK |
321 | /* Compute number of hard regs in each class. */ |
322 | ||
961192e1 | 323 | memset ((char *) reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
324 | for (i = 0; i < N_REG_CLASSES; i++) |
325 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
326 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
327 | reg_class_size[i]++; | |
328 | ||
329 | /* Initialize the table of subunions. | |
330 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
331 | that is contained in the union of classes I and J. */ | |
332 | ||
333 | for (i = 0; i < N_REG_CLASSES; i++) | |
334 | { | |
335 | for (j = 0; j < N_REG_CLASSES; j++) | |
336 | { | |
337 | #ifdef HARD_REG_SET | |
338 | register /* Declare it register if it's a scalar. */ | |
339 | #endif | |
340 | HARD_REG_SET c; | |
b3694847 | 341 | int k; |
54dac99e RK |
342 | |
343 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
344 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
345 | for (k = 0; k < N_REG_CLASSES; k++) | |
346 | { | |
347 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
348 | subclass1); | |
349 | continue; | |
350 | ||
351 | subclass1: | |
352 | /* keep the largest subclass */ /* SPEE 900308 */ | |
353 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
354 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
355 | subclass2); | |
356 | reg_class_subunion[i][j] = (enum reg_class) k; | |
357 | subclass2: | |
358 | ; | |
359 | } | |
360 | } | |
361 | } | |
362 | ||
363 | /* Initialize the table of superunions. | |
364 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
365 | containing the union of classes I and J. */ | |
366 | ||
367 | for (i = 0; i < N_REG_CLASSES; i++) | |
368 | { | |
369 | for (j = 0; j < N_REG_CLASSES; j++) | |
370 | { | |
371 | #ifdef HARD_REG_SET | |
372 | register /* Declare it register if it's a scalar. */ | |
373 | #endif | |
374 | HARD_REG_SET c; | |
b3694847 | 375 | int k; |
54dac99e RK |
376 | |
377 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
378 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
379 | for (k = 0; k < N_REG_CLASSES; k++) | |
380 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
381 | ||
382 | superclass: | |
383 | reg_class_superunion[i][j] = (enum reg_class) k; | |
384 | } | |
385 | } | |
386 | ||
387 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
388 | First clear the whole table, then add the elements as they are found. */ | |
389 | ||
390 | for (i = 0; i < N_REG_CLASSES; i++) | |
391 | { | |
392 | for (j = 0; j < N_REG_CLASSES; j++) | |
393 | { | |
394 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
395 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
396 | } | |
397 | } | |
398 | ||
399 | for (i = 0; i < N_REG_CLASSES; i++) | |
400 | { | |
401 | if (i == (int) NO_REGS) | |
402 | continue; | |
403 | ||
404 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
405 | { | |
406 | enum reg_class *p; | |
407 | ||
408 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
409 | subclass); | |
410 | continue; | |
411 | subclass: | |
412 | /* Reg class I is a subclass of J. | |
413 | Add J to the table of superclasses of I. */ | |
414 | p = ®_class_superclasses[i][0]; | |
415 | while (*p != LIM_REG_CLASSES) p++; | |
416 | *p = (enum reg_class) j; | |
417 | /* Add I to the table of superclasses of J. */ | |
418 | p = ®_class_subclasses[j][0]; | |
419 | while (*p != LIM_REG_CLASSES) p++; | |
420 | *p = (enum reg_class) i; | |
421 | } | |
422 | } | |
e4600702 | 423 | |
54dac99e RK |
424 | /* Initialize "constant" tables. */ |
425 | ||
426 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
427 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
428 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
4e2db584 | 429 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
54dac99e | 430 | |
4e135bdd | 431 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e RK |
432 | |
433 | n_non_fixed_regs = 0; | |
434 | ||
435 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
436 | { | |
54dac99e RK |
437 | if (fixed_regs[i]) |
438 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
439 | else | |
440 | n_non_fixed_regs++; | |
441 | ||
442 | if (call_used_regs[i]) | |
443 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
444 | if (call_fixed_regs[i]) | |
445 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
446 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
447 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
4e2db584 RH |
448 | |
449 | /* There are a couple of fixed registers that we know are safe to | |
450 | exclude from being clobbered by calls: | |
451 | ||
452 | The frame pointer is always preserved across calls. The arg pointer | |
453 | is if it is fixed. The stack pointer usually is, unless | |
454 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
455 | If we are generating PIC code, the PIC offset table register is | |
456 | preserved across calls, though the target can override that. */ | |
a6a2274a | 457 | |
4e2db584 RH |
458 | if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) |
459 | ; | |
460 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
461 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
462 | ; | |
463 | #endif | |
464 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
465 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
466 | ; | |
467 | #endif | |
468 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
12beba6f | 469 | else if (i == PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
4e2db584 RH |
470 | ; |
471 | #endif | |
d3259baa | 472 | else if (0 |
6ca3c22f | 473 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa RH |
474 | || call_really_used_regs[i] |
475 | #else | |
476 | || call_used_regs[i] | |
477 | #endif | |
478 | || global_regs[i]) | |
4e2db584 | 479 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
54dac99e | 480 | } |
4e2db584 | 481 | |
6836e024 JH |
482 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
483 | memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); | |
dbbbbf3b | 484 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 | 485 | for (i = 0; i < N_REG_CLASSES; i++) |
6df26b8f JH |
486 | if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
487 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
488 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
489 | && HARD_REGNO_MODE_OK (j, m)) | |
490 | { | |
491 | contains_reg_of_mode [i][m] = 1; | |
492 | allocatable_regs_of_mode [m] = 1; | |
493 | break; | |
494 | } | |
acbce667 KR |
495 | |
496 | /* Initialize the move cost table. Find every subset of each class | |
497 | and take the maximum cost of moving any subset to any other. */ | |
498 | ||
dbbbbf3b | 499 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 JH |
500 | if (allocatable_regs_of_mode [m]) |
501 | { | |
502 | for (i = 0; i < N_REG_CLASSES; i++) | |
503 | if (contains_reg_of_mode [i][m]) | |
504 | for (j = 0; j < N_REG_CLASSES; j++) | |
505 | { | |
506 | int cost; | |
507 | enum reg_class *p1, *p2; | |
508 | ||
509 | if (!contains_reg_of_mode [j][m]) | |
510 | { | |
511 | move_cost[m][i][j] = 65536; | |
512 | may_move_in_cost[m][i][j] = 65536; | |
513 | may_move_out_cost[m][i][j] = 65536; | |
514 | } | |
515 | else | |
516 | { | |
26a952a8 | 517 | cost = REGISTER_MOVE_COST (m, i, j); |
6836e024 JH |
518 | |
519 | for (p2 = ®_class_subclasses[j][0]; | |
520 | *p2 != LIM_REG_CLASSES; | |
521 | p2++) | |
522 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
523 | cost = MAX (cost, move_cost [m][i][*p2]); | |
524 | ||
525 | for (p1 = ®_class_subclasses[i][0]; | |
526 | *p1 != LIM_REG_CLASSES; | |
527 | p1++) | |
528 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
529 | cost = MAX (cost, move_cost [m][*p1][j]); | |
530 | ||
531 | move_cost[m][i][j] = cost; | |
532 | ||
533 | if (reg_class_subset_p (i, j)) | |
534 | may_move_in_cost[m][i][j] = 0; | |
535 | else | |
536 | may_move_in_cost[m][i][j] = cost; | |
537 | ||
538 | if (reg_class_subset_p (j, i)) | |
539 | may_move_out_cost[m][i][j] = 0; | |
540 | else | |
541 | may_move_out_cost[m][i][j] = cost; | |
542 | } | |
543 | } | |
1464632b | 544 | else |
6836e024 JH |
545 | for (j = 0; j < N_REG_CLASSES; j++) |
546 | { | |
547 | move_cost[m][i][j] = 65536; | |
548 | may_move_in_cost[m][i][j] = 65536; | |
549 | may_move_out_cost[m][i][j] = 65536; | |
550 | } | |
551 | } | |
e79f71f7 | 552 | |
02188693 | 553 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
554 | { |
555 | HARD_REG_SET c; | |
02188693 | 556 | COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]); |
a6a2274a | 557 | |
e79f71f7 GK |
558 | for (i = 0; i < N_REG_CLASSES; i++) |
559 | { | |
560 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class); | |
02188693 | 561 | class_can_change_mode [i] = 0; |
e79f71f7 GK |
562 | continue; |
563 | ok_class: | |
02188693 | 564 | class_can_change_mode [i] = 1; |
e79f71f7 GK |
565 | } |
566 | } | |
02188693 | 567 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
c27c5281 DE |
568 | } |
569 | ||
570 | /* Compute the table of register modes. | |
571 | These values are used to record death information for individual registers | |
572 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 573 | |
c27c5281 DE |
574 | static void |
575 | init_reg_modes () | |
576 | { | |
b3694847 | 577 | int i; |
ca4aac00 DE |
578 | |
579 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
580 | { |
581 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
582 | ||
066c2fea | 583 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
584 | ??? One situation in which we need to do this is on the mips where |
585 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
586 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 587 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 588 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 589 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 590 | } |
ca4aac00 DE |
591 | } |
592 | ||
c27c5281 DE |
593 | /* Finish initializing the register sets and |
594 | initialize the register modes. */ | |
595 | ||
596 | void | |
597 | init_regs () | |
598 | { | |
599 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
600 | until after register usage was specified. */ | |
b93a436e | 601 | init_reg_sets_1 (); |
c27c5281 DE |
602 | |
603 | init_reg_modes (); | |
6cde4876 JL |
604 | } |
605 | ||
606 | /* Initialize some fake stack-frame MEM references for use in | |
607 | memory_move_secondary_cost. */ | |
473fe49b | 608 | |
6cde4876 JL |
609 | void |
610 | init_fake_stack_mems () | |
611 | { | |
473fe49b KR |
612 | #ifdef HAVE_SECONDARY_RELOADS |
613 | { | |
473fe49b | 614 | int i; |
d067e2aa | 615 | |
473fe49b | 616 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 617 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
618 | } |
619 | #endif | |
c27c5281 DE |
620 | } |
621 | ||
cbd5b9a2 | 622 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 623 | |
cbd5b9a2 KR |
624 | /* Compute extra cost of moving registers to/from memory due to reloads. |
625 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 626 | |
cbd5b9a2 KR |
627 | int |
628 | memory_move_secondary_cost (mode, class, in) | |
629 | enum machine_mode mode; | |
630 | enum reg_class class; | |
631 | int in; | |
632 | { | |
633 | enum reg_class altclass; | |
634 | int partial_cost = 0; | |
cbd5b9a2 | 635 | /* We need a memory reference to feed to SECONDARY... macros. */ |
dc297297 | 636 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
272df862 KG |
637 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
638 | ||
cbd5b9a2 KR |
639 | |
640 | if (in) | |
473fe49b | 641 | { |
321c0828 | 642 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 643 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 644 | #else |
473fe49b | 645 | altclass = NO_REGS; |
321c0828 | 646 | #endif |
473fe49b | 647 | } |
cbd5b9a2 | 648 | else |
473fe49b | 649 | { |
321c0828 | 650 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 651 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 652 | #else |
473fe49b | 653 | altclass = NO_REGS; |
321c0828 | 654 | #endif |
473fe49b KR |
655 | } |
656 | ||
cbd5b9a2 KR |
657 | if (altclass == NO_REGS) |
658 | return 0; | |
659 | ||
660 | if (in) | |
e56b4594 | 661 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 662 | else |
e56b4594 | 663 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
664 | |
665 | if (class == altclass) | |
666 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
667 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
668 | here in that case. | |
669 | ||
670 | I'm tempted to put in an abort here, but returning this will | |
671 | probably only give poor estimates, which is what we would've | |
672 | had before this code anyways. */ | |
673 | return partial_cost; | |
674 | ||
675 | /* Check if the secondary reload register will also need a | |
676 | secondary reload. */ | |
677 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
678 | } | |
679 | #endif | |
680 | ||
ca4aac00 DE |
681 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
682 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
683 | ||
684 | enum machine_mode | |
685 | choose_hard_reg_mode (regno, nregs) | |
770ae6cc RK |
686 | unsigned int regno ATTRIBUTE_UNUSED; |
687 | unsigned int nregs; | |
ca4aac00 | 688 | { |
dbbbbf3b | 689 | unsigned int /* enum machine_mode */ m; |
ca4aac00 DE |
690 | enum machine_mode found_mode = VOIDmode, mode; |
691 | ||
692 | /* We first look for the largest integer mode that can be validly | |
693 | held in REGNO. If none, we look for the largest floating-point mode. | |
694 | If we still didn't find a valid mode, try CCmode. */ | |
695 | ||
696 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
697 | mode != VOIDmode; | |
698 | mode = GET_MODE_WIDER_MODE (mode)) | |
699 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
700 | && HARD_REGNO_MODE_OK (regno, mode)) | |
701 | found_mode = mode; | |
702 | ||
703 | if (found_mode != VOIDmode) | |
704 | return found_mode; | |
705 | ||
706 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
707 | mode != VOIDmode; | |
708 | mode = GET_MODE_WIDER_MODE (mode)) | |
709 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
710 | && HARD_REGNO_MODE_OK (regno, mode)) | |
711 | found_mode = mode; | |
712 | ||
713 | if (found_mode != VOIDmode) | |
714 | return found_mode; | |
715 | ||
78b583fe AH |
716 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
717 | mode != VOIDmode; | |
718 | mode = GET_MODE_WIDER_MODE (mode)) | |
719 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
720 | && HARD_REGNO_MODE_OK (regno, mode)) | |
721 | found_mode = mode; | |
722 | ||
723 | if (found_mode != VOIDmode) | |
724 | return found_mode; | |
725 | ||
726 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
727 | mode != VOIDmode; | |
728 | mode = GET_MODE_WIDER_MODE (mode)) | |
729 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
730 | && HARD_REGNO_MODE_OK (regno, mode)) | |
731 | found_mode = mode; | |
732 | ||
733 | if (found_mode != VOIDmode) | |
734 | return found_mode; | |
735 | ||
0548a9df | 736 | /* Iterate over all of the CCmodes. */ |
dbbbbf3b JDA |
737 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
738 | { | |
739 | mode = (enum machine_mode) m; | |
740 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
741 | && HARD_REGNO_MODE_OK (regno, mode)) | |
742 | return mode; | |
743 | } | |
ca4aac00 DE |
744 | |
745 | /* We can't find a mode valid for this register. */ | |
746 | return VOIDmode; | |
54dac99e RK |
747 | } |
748 | ||
749 | /* Specify the usage characteristics of the register named NAME. | |
750 | It should be a fixed register if FIXED and a | |
751 | call-used register if CALL_USED. */ | |
752 | ||
753 | void | |
754 | fix_register (name, fixed, call_used) | |
ec0ce6e2 | 755 | const char *name; |
54dac99e RK |
756 | int fixed, call_used; |
757 | { | |
758 | int i; | |
759 | ||
760 | /* Decode the name and update the primary form of | |
761 | the register info. */ | |
762 | ||
e5c90c23 TW |
763 | if ((i = decode_reg_name (name)) >= 0) |
764 | { | |
cb2fdc84 GRK |
765 | if ((i == STACK_POINTER_REGNUM |
766 | #ifdef HARD_FRAME_POINTER_REGNUM | |
767 | || i == HARD_FRAME_POINTER_REGNUM | |
768 | #else | |
769 | || i == FRAME_POINTER_REGNUM | |
770 | #endif | |
771 | ) | |
772 | && (fixed == 0 || call_used == 0)) | |
773 | { | |
6f7d635c | 774 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
775 | { "call-saved", "call-used" }, |
776 | { "no-such-option", "fixed" }}; | |
a6a2274a KH |
777 | |
778 | error ("can't use '%s' as a %s register", name, | |
cb2fdc84 GRK |
779 | what_option[fixed][call_used]); |
780 | } | |
781 | else | |
782 | { | |
783 | fixed_regs[i] = fixed; | |
784 | call_used_regs[i] = call_used; | |
ec523c2f | 785 | #ifdef CALL_REALLY_USED_REGISTERS |
fc1296b7 AM |
786 | if (fixed == 0) |
787 | call_really_used_regs[i] = call_used; | |
d3259baa | 788 | #endif |
cb2fdc84 | 789 | } |
e5c90c23 TW |
790 | } |
791 | else | |
54dac99e RK |
792 | { |
793 | warning ("unknown register name: %s", name); | |
54dac99e RK |
794 | } |
795 | } | |
614f68e2 RK |
796 | |
797 | /* Mark register number I as global. */ | |
798 | ||
799 | void | |
800 | globalize_reg (i) | |
801 | int i; | |
802 | { | |
c07c7c9d | 803 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
804 | error ("global register variable follows a function definition"); |
805 | ||
614f68e2 RK |
806 | if (global_regs[i]) |
807 | { | |
808 | warning ("register used for two global register variables"); | |
809 | return; | |
810 | } | |
811 | ||
812 | if (call_used_regs[i] && ! fixed_regs[i]) | |
813 | warning ("call-clobbered register used for global register variable"); | |
814 | ||
815 | global_regs[i] = 1; | |
816 | ||
817 | /* If already fixed, nothing else to do. */ | |
818 | if (fixed_regs[i]) | |
819 | return; | |
820 | ||
821 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
822 | n_non_fixed_regs--; | |
823 | ||
824 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
825 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
826 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
caecc099 | 827 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
614f68e2 | 828 | } |
54dac99e RK |
829 | \f |
830 | /* Now the data and code for the `regclass' pass, which happens | |
831 | just before local-alloc. */ | |
832 | ||
e4600702 RK |
833 | /* The `costs' struct records the cost of using a hard register of each class |
834 | and of using memory for each pseudo. We use this data to set up | |
835 | register class preferences. */ | |
54dac99e | 836 | |
e4600702 | 837 | struct costs |
54dac99e | 838 | { |
e4600702 RK |
839 | int cost[N_REG_CLASSES]; |
840 | int mem_cost; | |
54dac99e RK |
841 | }; |
842 | ||
9ffc5a70 JH |
843 | /* Structure used to record preferrences of given pseudo. */ |
844 | struct reg_pref | |
845 | { | |
846 | /* (enum reg_class) prefclass is the preferred class. */ | |
847 | char prefclass; | |
848 | ||
849 | /* altclass is a register class that we should use for allocating | |
850 | pseudo if no register in the preferred class is available. | |
851 | If no register in this class is available, memory is preferred. | |
852 | ||
853 | It might appear to be more general to have a bitmask of classes here, | |
854 | but since it is recommended that there be a class corresponding to the | |
855 | union of most major pair of classes, that generality is not required. */ | |
856 | char altclass; | |
857 | }; | |
858 | ||
e4600702 RK |
859 | /* Record the cost of each class for each pseudo. */ |
860 | ||
861 | static struct costs *costs; | |
862 | ||
61719ba7 BS |
863 | /* Initialized once, and used to initialize cost values for each insn. */ |
864 | ||
865 | static struct costs init_cost; | |
866 | ||
9ffc5a70 | 867 | /* Record preferrences of each pseudo. |
54dac99e RK |
868 | This is available after `regclass' is run. */ |
869 | ||
9ffc5a70 | 870 | static struct reg_pref *reg_pref; |
54d23420 | 871 | |
dc297297 | 872 | /* Allocated buffers for reg_pref. */ |
54dac99e | 873 | |
9ffc5a70 | 874 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 875 | |
9401afe3 | 876 | /* Frequency of executions of current insn. */ |
54d23420 | 877 | |
9401afe3 | 878 | static int frequency; |
54d23420 | 879 | |
13536812 KG |
880 | static rtx scan_one_insn PARAMS ((rtx, int)); |
881 | static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); | |
882 | static void dump_regclass PARAMS ((FILE *)); | |
883 | static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, | |
e79f71f7 | 884 | const char **, rtx, |
f741a71c | 885 | struct costs *, struct reg_pref *)); |
a6a2274a | 886 | static int copy_cost PARAMS ((rtx, enum machine_mode, |
08d95f91 | 887 | enum reg_class, int)); |
13536812 | 888 | static void record_address_regs PARAMS ((rtx, enum reg_class, int)); |
1d300e19 | 889 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
13536812 | 890 | static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); |
1d300e19 | 891 | #endif |
770ae6cc | 892 | static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); |
54dac99e RK |
893 | |
894 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
895 | This function is sometimes called before the info has been computed. | |
896 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
897 | ||
898 | enum reg_class | |
899 | reg_preferred_class (regno) | |
900 | int regno; | |
901 | { | |
9ffc5a70 | 902 | if (reg_pref == 0) |
54dac99e | 903 | return GENERAL_REGS; |
9ffc5a70 | 904 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
905 | } |
906 | ||
e4600702 RK |
907 | enum reg_class |
908 | reg_alternate_class (regno) | |
b729186a | 909 | int regno; |
54dac99e | 910 | { |
9ffc5a70 | 911 | if (reg_pref == 0) |
e4600702 RK |
912 | return ALL_REGS; |
913 | ||
9ffc5a70 | 914 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
915 | } |
916 | ||
61719ba7 | 917 | /* Initialize some global data for this pass. */ |
54dac99e RK |
918 | |
919 | void | |
920 | regclass_init () | |
921 | { | |
61719ba7 BS |
922 | int i; |
923 | ||
924 | init_cost.mem_cost = 10000; | |
925 | for (i = 0; i < N_REG_CLASSES; i++) | |
926 | init_cost.cost[i] = 10000; | |
927 | ||
928 | /* This prevents dump_flow_info from losing if called | |
929 | before regclass is run. */ | |
9ffc5a70 | 930 | reg_pref = NULL; |
6c85df69 | 931 | |
dc297297 | 932 | /* No more global register variables may be declared. */ |
6c85df69 | 933 | no_global_reg_vars = 1; |
54dac99e | 934 | } |
246fd41f JH |
935 | \f |
936 | /* Dump register costs. */ | |
915b80ed | 937 | static void |
246fd41f JH |
938 | dump_regclass (dump) |
939 | FILE *dump; | |
940 | { | |
941 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
942 | int i; | |
943 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
944 | { | |
dbbbbf3b | 945 | int /* enum reg_class */ class; |
246fd41f JH |
946 | if (REG_N_REFS (i)) |
947 | { | |
f741a71c | 948 | fprintf (dump, " Register %i costs:", i); |
dbbbbf3b JDA |
949 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
950 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
6df26b8f | 951 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
dbbbbf3b JDA |
952 | && (!in_inc_dec[i] |
953 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
6df26b8f JH |
954 | #endif |
955 | #ifdef CLASS_CANNOT_CHANGE_MODE | |
956 | && (!REGNO_REG_SET_P (reg_changes_mode, i) | |
dbbbbf3b | 957 | || class_can_change_mode [(enum reg_class) class]) |
6df26b8f JH |
958 | #endif |
959 | ) | |
dbbbbf3b JDA |
960 | fprintf (dump, " %s:%i", reg_class_names[class], |
961 | costs[i].cost[(enum reg_class) class]); | |
f741a71c | 962 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
963 | } |
964 | } | |
965 | } | |
f741a71c JH |
966 | \f |
967 | ||
968 | /* Calculate the costs of insn operands. */ | |
969 | ||
970 | static void | |
971 | record_operand_costs (insn, op_costs, reg_pref) | |
972 | rtx insn; | |
973 | struct costs *op_costs; | |
974 | struct reg_pref *reg_pref; | |
975 | { | |
976 | const char *constraints[MAX_RECOG_OPERANDS]; | |
977 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
978 | int i; |
979 | ||
980 | for (i = 0; i < recog_data.n_operands; i++) | |
981 | { | |
982 | constraints[i] = recog_data.constraints[i]; | |
983 | modes[i] = recog_data.operand_mode[i]; | |
984 | } | |
f741a71c JH |
985 | |
986 | /* If we get here, we are set up to record the costs of all the | |
987 | operands for this insn. Start by initializing the costs. | |
988 | Then handle any address registers. Finally record the desired | |
989 | classes for any pseudos, doing it twice if some pair of | |
990 | operands are commutative. */ | |
a6a2274a | 991 | |
f741a71c JH |
992 | for (i = 0; i < recog_data.n_operands; i++) |
993 | { | |
994 | op_costs[i] = init_cost; | |
995 | ||
996 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
997 | { | |
998 | rtx inner = SUBREG_REG (recog_data.operand[i]); | |
02188693 RH |
999 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1000 | if (GET_CODE (inner) == REG | |
1001 | && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner))) | |
1002 | SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner)); | |
9ef07cf1 | 1003 | #endif |
f741a71c JH |
1004 | recog_data.operand[i] = inner; |
1005 | } | |
1006 | ||
1007 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
1008 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
3dcc68a4 | 1009 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
ccfc6cc8 UW |
1010 | else if (constraints[i][0] == 'p' |
1011 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0])) | |
f741a71c | 1012 | record_address_regs (recog_data.operand[i], |
3dcc68a4 | 1013 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
f741a71c JH |
1014 | } |
1015 | ||
1016 | /* Check for commutative in a separate loop so everything will | |
1017 | have been initialized. We must do this even if one operand | |
1018 | is a constant--see addsi3 in m68k.md. */ | |
1019 | ||
1020 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
1021 | if (constraints[i][0] == '%') | |
1022 | { | |
1023 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1024 | int j; | |
246fd41f | 1025 | |
f741a71c JH |
1026 | /* Handle commutative operands by swapping the constraints. |
1027 | We assume the modes are the same. */ | |
1028 | ||
1029 | for (j = 0; j < recog_data.n_operands; j++) | |
1030 | xconstraints[j] = constraints[j]; | |
1031 | ||
1032 | xconstraints[i] = constraints[i+1]; | |
1033 | xconstraints[i+1] = constraints[i]; | |
1034 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1035 | recog_data.operand, modes, |
f741a71c JH |
1036 | xconstraints, insn, op_costs, reg_pref); |
1037 | } | |
1038 | ||
1039 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1040 | recog_data.operand, modes, |
f741a71c JH |
1041 | constraints, insn, op_costs, reg_pref); |
1042 | } | |
54dac99e | 1043 | \f |
61719ba7 BS |
1044 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1045 | time it would save code to put a certain register in a certain class. | |
1046 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1047 | once. | |
1048 | Return the last insn processed, so that the scan can be continued from | |
1049 | there. */ | |
1050 | ||
1051 | static rtx | |
1052 | scan_one_insn (insn, pass) | |
1053 | rtx insn; | |
1054 | int pass; | |
1055 | { | |
1056 | enum rtx_code code = GET_CODE (insn); | |
1057 | enum rtx_code pat_code; | |
0eadeb15 | 1058 | rtx set, note; |
61719ba7 | 1059 | int i, j; |
f741a71c | 1060 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 1061 | |
61719ba7 BS |
1062 | if (GET_RTX_CLASS (code) != 'i') |
1063 | return insn; | |
1064 | ||
1065 | pat_code = GET_CODE (PATTERN (insn)); | |
1066 | if (pat_code == USE | |
1067 | || pat_code == CLOBBER | |
1068 | || pat_code == ASM_INPUT | |
1069 | || pat_code == ADDR_VEC | |
1070 | || pat_code == ADDR_DIFF_VEC) | |
1071 | return insn; | |
1072 | ||
0eadeb15 BS |
1073 | set = single_set (insn); |
1074 | extract_insn (insn); | |
1075 | ||
0eadeb15 BS |
1076 | /* If this insn loads a parameter from its stack slot, then |
1077 | it represents a savings, rather than a cost, if the | |
1078 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 1079 | |
0eadeb15 BS |
1080 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
1081 | && GET_CODE (SET_SRC (set)) == MEM | |
1082 | && (note = find_reg_note (insn, REG_EQUIV, | |
1083 | NULL_RTX)) != 0 | |
1084 | && GET_CODE (XEXP (note, 0)) == MEM) | |
1085 | { | |
1086 | costs[REGNO (SET_DEST (set))].mem_cost | |
1087 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1088 | GENERAL_REGS, 1) | |
9401afe3 | 1089 | * frequency); |
0eadeb15 | 1090 | record_address_regs (XEXP (SET_SRC (set), 0), |
3dcc68a4 | 1091 | MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); |
0eadeb15 BS |
1092 | return insn; |
1093 | } | |
61719ba7 | 1094 | |
0eadeb15 BS |
1095 | /* Improve handling of two-address insns such as |
1096 | (set X (ashift CONST Y)) where CONST must be made to | |
1097 | match X. Change it into two insns: (set X CONST) | |
1098 | (set X (ashift X Y)). If we left this for reloading, it | |
1099 | would probably get three insns because X and Y might go | |
1100 | in the same place. This prevents X and Y from receiving | |
1101 | the same hard reg. | |
1102 | ||
1103 | We can only do this if the modes of operands 0 and 1 | |
1104 | (which might not be the same) are tieable and we only need | |
1105 | do this during our first pass. */ | |
1106 | ||
1107 | if (pass == 0 && optimize | |
1ccbefce RH |
1108 | && recog_data.n_operands >= 3 |
1109 | && recog_data.constraints[1][0] == '0' | |
1110 | && recog_data.constraints[1][1] == 0 | |
1111 | && CONSTANT_P (recog_data.operand[1]) | |
1112 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1113 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
1114 | && GET_CODE (recog_data.operand[0]) == REG | |
1115 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
1116 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
1117 | { |
1118 | rtx previnsn = prev_real_insn (insn); | |
1119 | rtx dest | |
1ccbefce RH |
1120 | = gen_lowpart (recog_data.operand_mode[1], |
1121 | recog_data.operand[0]); | |
0eadeb15 | 1122 | rtx newinsn |
1ccbefce | 1123 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 1124 | |
0eadeb15 BS |
1125 | /* If this insn was the start of a basic block, |
1126 | include the new insn in that block. | |
1127 | We need not check for code_label here; | |
1128 | while a basic block can start with a code_label, | |
1129 | INSN could not be at the beginning of that block. */ | |
1130 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 1131 | { |
e0082a72 ZD |
1132 | basic_block b; |
1133 | FOR_EACH_BB (b) | |
1134 | if (insn == b->head) | |
1135 | b->head = newinsn; | |
61719ba7 BS |
1136 | } |
1137 | ||
0eadeb15 | 1138 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1139 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d3c7d45e | 1140 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1141 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
61719ba7 | 1142 | |
1ccbefce | 1143 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d3c7d45e | 1144 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1145 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
1ccbefce RH |
1146 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1147 | if (recog_data.dup_num[i] == 1) | |
d3c7d45e AO |
1148 | { |
1149 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1150 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
9401afe3 | 1151 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d3c7d45e | 1152 | } |
61719ba7 | 1153 | |
0eadeb15 | 1154 | return PREV_INSN (newinsn); |
61719ba7 BS |
1155 | } |
1156 | ||
4963c995 | 1157 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1158 | |
1159 | /* Now add the cost for each operand to the total costs for | |
1160 | its register. */ | |
1161 | ||
1ccbefce RH |
1162 | for (i = 0; i < recog_data.n_operands; i++) |
1163 | if (GET_CODE (recog_data.operand[i]) == REG | |
1164 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 1165 | { |
1ccbefce | 1166 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1167 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1168 | ||
9401afe3 | 1169 | p->mem_cost += q->mem_cost * frequency; |
61719ba7 | 1170 | for (j = 0; j < N_REG_CLASSES; j++) |
9401afe3 | 1171 | p->cost[j] += q->cost[j] * frequency; |
61719ba7 BS |
1172 | } |
1173 | ||
1174 | return insn; | |
1175 | } | |
1176 | ||
54dac99e RK |
1177 | /* This is a pass of the compiler that scans all instructions |
1178 | and calculates the preferred class for each pseudo-register. | |
1179 | This information can be accessed later by calling `reg_preferred_class'. | |
1180 | This pass comes just before local register allocation. */ | |
1181 | ||
1182 | void | |
246fd41f | 1183 | regclass (f, nregs, dump) |
54dac99e RK |
1184 | rtx f; |
1185 | int nregs; | |
246fd41f | 1186 | FILE *dump; |
54dac99e | 1187 | { |
b3694847 SS |
1188 | rtx insn; |
1189 | int i; | |
e4600702 | 1190 | int pass; |
54dac99e RK |
1191 | |
1192 | init_recog (); | |
1193 | ||
56a65848 | 1194 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 | 1195 | |
02188693 | 1196 | #ifdef CLASS_CANNOT_CHANGE_MODE |
8e2e89f7 | 1197 | reg_changes_mode = BITMAP_XMALLOC (); |
a6a2274a | 1198 | #endif |
e79f71f7 | 1199 | |
533d0835 RK |
1200 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1201 | ||
4da896b2 | 1202 | in_inc_dec = (char *) xmalloc (nregs); |
533d0835 RK |
1203 | |
1204 | /* Initialize information about which register classes can be used for | |
1205 | pseudos that are auto-incremented or auto-decremented. It would | |
1206 | seem better to put this in init_reg_sets, but we need to be able | |
1207 | to allocate rtx, which we can't do that early. */ | |
1208 | ||
1209 | for (i = 0; i < N_REG_CLASSES; i++) | |
1210 | { | |
38a448ca | 1211 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 | 1212 | enum machine_mode m; |
b3694847 | 1213 | int j; |
533d0835 RK |
1214 | |
1215 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1216 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1217 | { | |
1218 | REGNO (r) = j; | |
1219 | ||
1220 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1221 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1222 | if (HARD_REGNO_MODE_OK (j, m)) |
1223 | { | |
1224 | PUT_MODE (r, m); | |
08d95f91 RK |
1225 | |
1226 | /* If a register is not directly suitable for an | |
1227 | auto-increment or decrement addressing mode and | |
1228 | requires secondary reloads, disallow its class from | |
1229 | being used in such addresses. */ | |
1230 | ||
1231 | if ((0 | |
041d7180 | 1232 | #ifdef SECONDARY_RELOAD_CLASS |
3dcc68a4 | 1233 | || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
041d7180 JL |
1234 | != NO_REGS) |
1235 | #else | |
533d0835 | 1236 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
3dcc68a4 | 1237 | || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1238 | != NO_REGS) |
533d0835 RK |
1239 | #endif |
1240 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
3dcc68a4 | 1241 | || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1242 | != NO_REGS) |
041d7180 | 1243 | #endif |
533d0835 | 1244 | #endif |
08d95f91 RK |
1245 | ) |
1246 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1247 | forbidden_inc_dec_class[i] = 1; |
1248 | } | |
1249 | } | |
1250 | } | |
1251 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1252 | ||
e4600702 RK |
1253 | /* Normally we scan the insns once and determine the best class to use for |
1254 | each register. However, if -fexpensive_optimizations are on, we do so | |
1255 | twice, the second time using the tentative best classes to guide the | |
1256 | selection. */ | |
54dac99e | 1257 | |
e4600702 RK |
1258 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1259 | { | |
e0082a72 | 1260 | basic_block bb; |
f741a71c JH |
1261 | |
1262 | if (dump) | |
a6a2274a | 1263 | fprintf (dump, "\n\nPass %i\n\n",pass); |
e4600702 | 1264 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1265 | |
961192e1 | 1266 | memset ((char *) costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1267 | |
533d0835 | 1268 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1269 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1270 | #endif |
1271 | ||
e4600702 RK |
1272 | /* Scan the instructions and record each time it would |
1273 | save code to put a certain register in a certain class. */ | |
1274 | ||
1f01879e | 1275 | if (!optimize) |
54dac99e | 1276 | { |
a08b2604 | 1277 | frequency = REG_FREQ_MAX; |
1f01879e JH |
1278 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1279 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1280 | } |
1f01879e | 1281 | else |
e0082a72 | 1282 | FOR_EACH_BB (bb) |
1f01879e | 1283 | { |
1f01879e | 1284 | /* Show that an insn inside a loop is likely to be executed three |
9b15c17f RH |
1285 | times more than insns outside a loop. This is much more |
1286 | aggressive than the assumptions made elsewhere and is being | |
1287 | tried as an experiment. */ | |
a08b2604 | 1288 | frequency = REG_FREQ_FROM_BB (bb); |
1f01879e JH |
1289 | for (insn = bb->head; ; insn = NEXT_INSN (insn)) |
1290 | { | |
1291 | insn = scan_one_insn (insn, pass); | |
1292 | if (insn == bb->end) | |
1293 | break; | |
1294 | } | |
1295 | } | |
a6a2274a | 1296 | |
e4600702 RK |
1297 | /* Now for each register look at how desirable each class is |
1298 | and find which class is preferred. Store that in | |
9ffc5a70 | 1299 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1300 | class any of whose registers is better than memory. */ |
a6a2274a | 1301 | |
e4600702 | 1302 | if (pass == 0) |
9ffc5a70 | 1303 | reg_pref = reg_pref_buffer; |
54dac99e | 1304 | |
f741a71c | 1305 | if (dump) |
a6a2274a | 1306 | { |
f741a71c | 1307 | dump_regclass (dump); |
4963c995 | 1308 | fprintf (dump,"\n"); |
f741a71c | 1309 | } |
e4600702 | 1310 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1311 | { |
b3694847 | 1312 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1313 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1314 | /* This is an enum reg_class, but we call it an int | |
1315 | to save lots of casts. */ | |
b3694847 SS |
1316 | int class; |
1317 | struct costs *p = &costs[i]; | |
e4600702 | 1318 | |
64615302 JH |
1319 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1320 | yet. */ | |
ed8d2920 | 1321 | if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) |
f741a71c JH |
1322 | continue; |
1323 | ||
e4600702 | 1324 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1325 | { |
533d0835 | 1326 | /* Ignore classes that are too small for this operand or |
4fe9b91c | 1327 | invalid for an operand that was auto-incremented. */ |
6df26b8f | 1328 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
533d0835 RK |
1329 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1330 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1331 | #endif |
02188693 RH |
1332 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1333 | || (REGNO_REG_SET_P (reg_changes_mode, i) | |
1334 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1335 | #endif |
1336 | ) | |
e4600702 RK |
1337 | ; |
1338 | else if (p->cost[class] < best_cost) | |
1339 | { | |
1340 | best_cost = p->cost[class]; | |
1341 | best = (enum reg_class) class; | |
1342 | } | |
1343 | else if (p->cost[class] == best_cost) | |
8e2e89f7 | 1344 | best = reg_class_subunion[(int) best][class]; |
54dac99e | 1345 | } |
54dac99e | 1346 | |
e4600702 RK |
1347 | /* Record the alternate register class; i.e., a class for which |
1348 | every register in it is better than using memory. If adding a | |
1349 | class would make a smaller class (i.e., no union of just those | |
1350 | classes exists), skip that class. The major unions of classes | |
1351 | should be provided as a register class. Don't do this if we | |
1352 | will be doing it again later. */ | |
1353 | ||
f741a71c | 1354 | if ((pass == 1 || dump) || ! flag_expensive_optimizations) |
e4600702 RK |
1355 | for (class = 0; class < N_REG_CLASSES; class++) |
1356 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1357 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1358 | > reg_class_size[(int) alt]) |
1359 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1360 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1361 | #endif |
02188693 RH |
1362 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1363 | && ! (REGNO_REG_SET_P (reg_changes_mode, i) | |
1364 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1365 | #endif |
1366 | ) | |
e4600702 | 1367 | alt = reg_class_subunion[(int) alt][class]; |
a6a2274a | 1368 | |
e4600702 RK |
1369 | /* If we don't add any classes, nothing to try. */ |
1370 | if (alt == best) | |
995d54dd | 1371 | alt = NO_REGS; |
e4600702 | 1372 | |
a6a2274a | 1373 | if (dump |
f741a71c JH |
1374 | && (reg_pref[i].prefclass != (int) best |
1375 | || reg_pref[i].altclass != (int) alt)) | |
1376 | { | |
1377 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
4963c995 | 1378 | fprintf (dump, " Register %i", i); |
f741a71c JH |
1379 | if (alt == ALL_REGS || best == ALL_REGS) |
1380 | fprintf (dump, " pref %s\n", reg_class_names[(int) best]); | |
1381 | else if (alt == NO_REGS) | |
1382 | fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); | |
1383 | else | |
1384 | fprintf (dump, " pref %s, else %s\n", | |
1385 | reg_class_names[(int) best], | |
1386 | reg_class_names[(int) alt]); | |
1387 | } | |
1388 | ||
e4600702 | 1389 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1390 | reg_pref[i].prefclass = (int) best; |
1391 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1392 | } |
54dac99e | 1393 | } |
56a65848 | 1394 | |
4da896b2 MM |
1395 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1396 | free (in_inc_dec); | |
e79f71f7 | 1397 | #endif |
02188693 RH |
1398 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1399 | BITMAP_XFREE (reg_changes_mode); | |
4da896b2 | 1400 | #endif |
56a65848 | 1401 | free (costs); |
54dac99e RK |
1402 | } |
1403 | \f | |
e4600702 RK |
1404 | /* Record the cost of using memory or registers of various classes for |
1405 | the operands in INSN. | |
54dac99e | 1406 | |
e4600702 | 1407 | N_ALTS is the number of alternatives. |
54dac99e | 1408 | |
e4600702 RK |
1409 | N_OPS is the number of operands. |
1410 | ||
1411 | OPS is an array of the operands. | |
1412 | ||
1413 | MODES are the modes of the operands, in case any are VOIDmode. | |
1414 | ||
1415 | CONSTRAINTS are the constraints to use for the operands. This array | |
1416 | is modified by this procedure. | |
1417 | ||
1418 | This procedure works alternative by alternative. For each alternative | |
1419 | we assume that we will be able to allocate all pseudos to their ideal | |
1420 | register class and calculate the cost of using that alternative. Then | |
a6a2274a | 1421 | we compute for each operand that is a pseudo-register, the cost of |
e4600702 RK |
1422 | having the pseudo allocated to each register class and using it in that |
1423 | alternative. To this cost is added the cost of the alternative. | |
1424 | ||
1425 | The cost of each class for this insn is its lowest cost among all the | |
1426 | alternatives. */ | |
1427 | ||
1428 | static void | |
e79f71f7 | 1429 | record_reg_classes (n_alts, n_ops, ops, modes, |
f741a71c | 1430 | constraints, insn, op_costs, reg_pref) |
e4600702 RK |
1431 | int n_alts; |
1432 | int n_ops; | |
1433 | rtx *ops; | |
1434 | enum machine_mode *modes; | |
9b3142b3 | 1435 | const char **constraints; |
e4600702 | 1436 | rtx insn; |
f741a71c JH |
1437 | struct costs *op_costs; |
1438 | struct reg_pref *reg_pref; | |
54dac99e | 1439 | { |
e4600702 | 1440 | int alt; |
e4600702 | 1441 | int i, j; |
ec2d92af | 1442 | rtx set; |
e4600702 | 1443 | |
e4600702 RK |
1444 | /* Process each alternative, each time minimizing an operand's cost with |
1445 | the cost for each operand in that alternative. */ | |
54dac99e | 1446 | |
e4600702 | 1447 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1448 | { |
e4600702 RK |
1449 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1450 | int alt_fail = 0; | |
1451 | int alt_cost = 0; | |
1452 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1453 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1454 | int class; |
54dac99e | 1455 | |
e4600702 RK |
1456 | for (i = 0; i < n_ops; i++) |
1457 | { | |
9b3142b3 | 1458 | const char *p = constraints[i]; |
e4600702 RK |
1459 | rtx op = ops[i]; |
1460 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1461 | int allows_addr = 0; |
e4600702 | 1462 | int win = 0; |
e51712db | 1463 | unsigned char c; |
54dac99e | 1464 | |
7405d9a1 DE |
1465 | /* Initially show we know nothing about the register class. */ |
1466 | classes[i] = NO_REGS; | |
da2c0219 | 1467 | allows_mem[i] = 0; |
7405d9a1 | 1468 | |
a6a2274a | 1469 | /* If this operand has no constraints at all, we can conclude |
e4600702 | 1470 | nothing about it since anything is valid. */ |
54dac99e | 1471 | |
e4600702 RK |
1472 | if (*p == 0) |
1473 | { | |
1474 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
961192e1 | 1475 | memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1476 | |
e4600702 RK |
1477 | continue; |
1478 | } | |
54dac99e | 1479 | |
7405d9a1 DE |
1480 | /* If this alternative is only relevant when this operand |
1481 | matches a previous operand, we do different things depending | |
1482 | on whether this operand is a pseudo-reg or not. We must process | |
1483 | any modifiers for the operand before we can make this test. */ | |
1484 | ||
8c368ee2 | 1485 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1486 | p++; |
8c368ee2 | 1487 | |
e4600702 RK |
1488 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1489 | { | |
da2c0219 RK |
1490 | /* Copy class and whether memory is allowed from the matching |
1491 | alternative. Then perform any needed cost computations | |
1492 | and/or adjustments. */ | |
e4600702 RK |
1493 | j = p[0] - '0'; |
1494 | classes[i] = classes[j]; | |
da2c0219 | 1495 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1496 | |
1497 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1498 | { | |
1499 | /* If this matches the other operand, we have no added | |
dc903608 | 1500 | cost and we win. */ |
e4600702 | 1501 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1502 | win = 1; |
e4600702 | 1503 | |
77e67eac RK |
1504 | /* If we can put the other operand into a register, add to |
1505 | the cost of this alternative the cost to copy this | |
1506 | operand to the register used for the other operand. */ | |
e4600702 | 1507 | |
dc903608 | 1508 | else if (classes[j] != NO_REGS) |
77e67eac | 1509 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1510 | } |
07d8ca2d RS |
1511 | else if (GET_CODE (ops[j]) != REG |
1512 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1513 | { | |
1514 | /* This op is a pseudo but the one it matches is not. */ | |
a6a2274a | 1515 | |
07d8ca2d RS |
1516 | /* If we can't put the other operand into a register, this |
1517 | alternative can't be used. */ | |
1518 | ||
1519 | if (classes[j] == NO_REGS) | |
1520 | alt_fail = 1; | |
e4600702 | 1521 | |
07d8ca2d RS |
1522 | /* Otherwise, add to the cost of this alternative the cost |
1523 | to copy the other operand to the register used for this | |
1524 | operand. */ | |
1525 | ||
1526 | else | |
1527 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1528 | } | |
e4600702 RK |
1529 | else |
1530 | { | |
da2c0219 RK |
1531 | /* The costs of this operand are not the same as the other |
1532 | operand since move costs are not symmetric. Moreover, | |
1533 | if we cannot tie them, this alternative needs to do a | |
1534 | copy, which is one instruction. */ | |
1535 | ||
1536 | struct costs *pp = &this_op_costs[i]; | |
1537 | ||
1538 | for (class = 0; class < N_REG_CLASSES; class++) | |
1539 | pp->cost[class] | |
d5e2075d | 1540 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1541 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1542 | : 0) |
1543 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1544 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1545 | : 0)); |
a6a2274a | 1546 | |
da2c0219 RK |
1547 | /* If the alternative actually allows memory, make things |
1548 | a bit cheaper since we won't need an extra insn to | |
1549 | load it. */ | |
1550 | ||
1551 | pp->mem_cost | |
d5e2075d JH |
1552 | = ((recog_data.operand_type[i] != OP_IN |
1553 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1554 | : 0) | |
1555 | + (recog_data.operand_type[i] != OP_OUT | |
1556 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1557 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1558 | |
1559 | /* If we have assigned a class to this register in our | |
1560 | first pass, add a cost to this alternative corresponding | |
1561 | to what we would add if this register were not in the | |
1562 | appropriate class. */ | |
1563 | ||
9ffc5a70 | 1564 | if (reg_pref) |
da2c0219 | 1565 | alt_cost |
e56b4594 AO |
1566 | += (may_move_in_cost[mode] |
1567 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1568 | [(int) classes[i]]); |
e4600702 | 1569 | |
37747c82 RK |
1570 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1571 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1572 | alt_cost += 2; | |
e4600702 | 1573 | |
347099d6 | 1574 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1575 | for this operand, so skip to the end of the |
1576 | alternative (should be just one character). */ | |
1577 | while (*p && *p++ != ',') | |
1578 | ; | |
1579 | ||
1580 | constraints[i] = p; | |
347099d6 RS |
1581 | continue; |
1582 | } | |
e4600702 RK |
1583 | } |
1584 | ||
1585 | /* Scan all the constraint letters. See if the operand matches | |
1586 | any of the constraints. Collect the valid register classes | |
1587 | and see if this operand accepts memory. */ | |
1588 | ||
e4600702 RK |
1589 | while (*p && (c = *p++) != ',') |
1590 | switch (c) | |
1591 | { | |
e4600702 RK |
1592 | case '*': |
1593 | /* Ignore the next letter for this pass. */ | |
1594 | p++; | |
1595 | break; | |
1596 | ||
812f2051 R |
1597 | case '?': |
1598 | alt_cost += 2; | |
8c368ee2 | 1599 | case '!': case '#': case '&': |
e4600702 | 1600 | case '0': case '1': case '2': case '3': case '4': |
8c368ee2 | 1601 | case '5': case '6': case '7': case '8': case '9': |
94e6f783 DE |
1602 | break; |
1603 | ||
e4600702 | 1604 | case 'p': |
94e6f783 DE |
1605 | allows_addr = 1; |
1606 | win = address_operand (op, GET_MODE (op)); | |
46f40127 JL |
1607 | /* We know this operand is an address, so we want it to be |
1608 | allocated to a register that can be the base of an | |
1609 | address, ie BASE_REG_CLASS. */ | |
1610 | classes[i] | |
1611 | = reg_class_subunion[(int) classes[i]] | |
3dcc68a4 | 1612 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; |
e4600702 RK |
1613 | break; |
1614 | ||
1615 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1616 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 | 1617 | and non-offsettable addresses here. */ |
da2c0219 | 1618 | allows_mem[i] = 1; |
e4600702 RK |
1619 | if (GET_CODE (op) == MEM) |
1620 | win = 1; | |
1621 | break; | |
1622 | ||
1623 | case '<': | |
1624 | if (GET_CODE (op) == MEM | |
1625 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1626 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1627 | win = 1; | |
1628 | break; | |
1629 | ||
1630 | case '>': | |
1631 | if (GET_CODE (op) == MEM | |
1632 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1633 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1634 | win = 1; | |
1635 | break; | |
1636 | ||
1637 | case 'E': | |
e4600702 | 1638 | case 'F': |
bf7cd754 R |
1639 | if (GET_CODE (op) == CONST_DOUBLE |
1640 | || (GET_CODE (op) == CONST_VECTOR | |
1641 | && (GET_MODE_CLASS (GET_MODE (op)) | |
1642 | == MODE_VECTOR_FLOAT))) | |
e4600702 RK |
1643 | win = 1; |
1644 | break; | |
1645 | ||
1646 | case 'G': | |
1647 | case 'H': | |
1648 | if (GET_CODE (op) == CONST_DOUBLE | |
1649 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1650 | win = 1; | |
1651 | break; | |
1652 | ||
1653 | case 's': | |
1654 | if (GET_CODE (op) == CONST_INT | |
1655 | || (GET_CODE (op) == CONST_DOUBLE | |
1656 | && GET_MODE (op) == VOIDmode)) | |
1657 | break; | |
1658 | case 'i': | |
1659 | if (CONSTANT_P (op) | |
1660 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1661 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1662 | #endif | |
1663 | ) | |
1664 | win = 1; | |
1665 | break; | |
1666 | ||
1667 | case 'n': | |
1668 | if (GET_CODE (op) == CONST_INT | |
1669 | || (GET_CODE (op) == CONST_DOUBLE | |
1670 | && GET_MODE (op) == VOIDmode)) | |
1671 | win = 1; | |
1672 | break; | |
1673 | ||
1674 | case 'I': | |
1675 | case 'J': | |
1676 | case 'K': | |
1677 | case 'L': | |
1678 | case 'M': | |
1679 | case 'N': | |
1680 | case 'O': | |
1681 | case 'P': | |
1682 | if (GET_CODE (op) == CONST_INT | |
1683 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1684 | win = 1; | |
1685 | break; | |
1686 | ||
1687 | case 'X': | |
1688 | win = 1; | |
1689 | break; | |
54dac99e | 1690 | |
e4600702 RK |
1691 | case 'g': |
1692 | if (GET_CODE (op) == MEM | |
1693 | || (CONSTANT_P (op) | |
1694 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1695 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1696 | #endif |
e4600702 RK |
1697 | )) |
1698 | win = 1; | |
da2c0219 | 1699 | allows_mem[i] = 1; |
e4600702 RK |
1700 | case 'r': |
1701 | classes[i] | |
1702 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1703 | break; | |
1704 | ||
1705 | default: | |
c2cba7a9 RH |
1706 | if (REG_CLASS_FROM_LETTER (c) != NO_REGS) |
1707 | classes[i] | |
1708 | = reg_class_subunion[(int) classes[i]] | |
1709 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1710 | #ifdef EXTRA_CONSTRAINT | |
1711 | else if (EXTRA_CONSTRAINT (op, c)) | |
1712 | win = 1; | |
ccfc6cc8 UW |
1713 | |
1714 | if (EXTRA_MEMORY_CONSTRAINT (c)) | |
1715 | { | |
1716 | /* Every MEM can be reloaded to fit. */ | |
1717 | allows_mem[i] = 1; | |
1718 | if (GET_CODE (op) == MEM) | |
1719 | win = 1; | |
1720 | } | |
1721 | if (EXTRA_ADDRESS_CONSTRAINT (op)) | |
1722 | { | |
1723 | /* Every address can be reloaded to fit. */ | |
1724 | allows_addr = 1; | |
1725 | if (address_operand (op, GET_MODE (op))) | |
1726 | win = 1; | |
1727 | /* We know this operand is an address, so we want it to be | |
1728 | allocated to a register that can be the base of an | |
1729 | address, ie BASE_REG_CLASS. */ | |
1730 | classes[i] | |
1731 | = reg_class_subunion[(int) classes[i]] | |
1732 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1733 | } | |
c2cba7a9 RH |
1734 | #endif |
1735 | break; | |
e4600702 RK |
1736 | } |
1737 | ||
1738 | constraints[i] = p; | |
1739 | ||
1740 | /* How we account for this operand now depends on whether it is a | |
1741 | pseudo register or not. If it is, we first check if any | |
1742 | register classes are valid. If not, we ignore this alternative, | |
1743 | since we want to assume that all pseudos get allocated for | |
1744 | register preferencing. If some register class is valid, compute | |
1745 | the costs of moving the pseudo into that class. */ | |
1746 | ||
1747 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1748 | { |
e4600702 | 1749 | if (classes[i] == NO_REGS) |
94e6f783 | 1750 | { |
e79f71f7 GK |
1751 | /* We must always fail if the operand is a REG, but |
1752 | we did not find a suitable class. | |
a6a2274a | 1753 | |
e79f71f7 GK |
1754 | Otherwise we may perform an uninitialized read |
1755 | from this_op_costs after the `continue' statement | |
1756 | below. */ | |
1757 | alt_fail = 1; | |
94e6f783 | 1758 | } |
e4600702 RK |
1759 | else |
1760 | { | |
1761 | struct costs *pp = &this_op_costs[i]; | |
1762 | ||
1763 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1764 | pp->cost[class] |
d5e2075d | 1765 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1766 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1767 | : 0) |
1768 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1769 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1770 | : 0)); |
e4600702 RK |
1771 | |
1772 | /* If the alternative actually allows memory, make things | |
1773 | a bit cheaper since we won't need an extra insn to | |
1774 | load it. */ | |
1775 | ||
14a774a9 | 1776 | pp->mem_cost |
d5e2075d JH |
1777 | = ((recog_data.operand_type[i] != OP_IN |
1778 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1779 | : 0) | |
1780 | + (recog_data.operand_type[i] != OP_OUT | |
1781 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1782 | : 0) - allows_mem[i]); | |
e4600702 RK |
1783 | |
1784 | /* If we have assigned a class to this register in our | |
1785 | first pass, add a cost to this alternative corresponding | |
1786 | to what we would add if this register were not in the | |
1787 | appropriate class. */ | |
1788 | ||
9ffc5a70 | 1789 | if (reg_pref) |
e4600702 | 1790 | alt_cost |
e56b4594 AO |
1791 | += (may_move_in_cost[mode] |
1792 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1793 | [(int) classes[i]]); |
e4600702 | 1794 | } |
4db18574 | 1795 | } |
54dac99e | 1796 | |
e4600702 RK |
1797 | /* Otherwise, if this alternative wins, either because we |
1798 | have already determined that or if we have a hard register of | |
1799 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1800 | |
e4600702 RK |
1801 | else if (win |
1802 | || (GET_CODE (op) == REG | |
6f654776 | 1803 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1804 | ; |
54dac99e | 1805 | |
e4600702 RK |
1806 | /* If registers are valid, the cost of this alternative includes |
1807 | copying the object to and/or from a register. */ | |
54dac99e | 1808 | |
e4600702 RK |
1809 | else if (classes[i] != NO_REGS) |
1810 | { | |
1ccbefce | 1811 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1812 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1813 | |
1ccbefce | 1814 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1815 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1816 | } | |
54dac99e | 1817 | |
e4600702 RK |
1818 | /* The only other way this alternative can be used is if this is a |
1819 | constant that could be placed into memory. */ | |
1820 | ||
da2c0219 | 1821 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1822 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1823 | else |
1824 | alt_fail = 1; | |
1825 | } | |
1826 | ||
1827 | if (alt_fail) | |
1828 | continue; | |
1829 | ||
1830 | /* Finally, update the costs with the information we've calculated | |
1831 | about this alternative. */ | |
1832 | ||
1833 | for (i = 0; i < n_ops; i++) | |
1834 | if (GET_CODE (ops[i]) == REG | |
1835 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1836 | { |
e4600702 | 1837 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1838 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1839 | |
e4600702 RK |
1840 | pp->mem_cost = MIN (pp->mem_cost, |
1841 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1842 | |
e4600702 RK |
1843 | for (class = 0; class < N_REG_CLASSES; class++) |
1844 | pp->cost[class] = MIN (pp->cost[class], | |
1845 | (qq->cost[class] + alt_cost) * scale); | |
1846 | } | |
1847 | } | |
ec2d92af RK |
1848 | |
1849 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1850 | and one operand is a pseudo with the other a hard reg or a pseudo |
1851 | that prefers a register that is in its own register class then | |
1852 | we may want to adjust the cost of that register class to -1. | |
a6a2274a | 1853 | |
accef103 JL |
1854 | Avoid the adjustment if the source does not die to avoid stressing of |
1855 | register allocator by preferrencing two coliding registers into single | |
1856 | class. | |
1857 | ||
1858 | Also avoid the adjustment if a copy between registers of the class | |
1859 | is expensive (ten times the cost of a default copy is considered | |
1860 | arbitrarily expensive). This avoids losing when the preferred class | |
1861 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1862 | |
1863 | if ((set = single_set (insn)) != 0 | |
1864 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
0dc0641b JH |
1865 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG |
1866 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
ec2d92af RK |
1867 | for (i = 0; i <= 1; i++) |
1868 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1869 | { | |
770ae6cc | 1870 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1871 | enum machine_mode mode = GET_MODE (ops[!i]); |
1872 | int class; | |
770ae6cc | 1873 | unsigned int nr; |
ec2d92af | 1874 | |
accef103 JL |
1875 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1876 | { | |
1877 | enum reg_class pref = reg_pref[regno].prefclass; | |
1878 | ||
1879 | if ((reg_class_size[(unsigned char) pref] | |
1880 | == CLASS_MAX_NREGS (pref, mode)) | |
e56b4594 | 1881 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1882 | op_costs[i].cost[(unsigned char) pref] = -1; |
1883 | } | |
ec2d92af RK |
1884 | else if (regno < FIRST_PSEUDO_REGISTER) |
1885 | for (class = 0; class < N_REG_CLASSES; class++) | |
1886 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1887 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1888 | { |
1889 | if (reg_class_size[class] == 1) | |
1890 | op_costs[i].cost[class] = -1; | |
1891 | else | |
1892 | { | |
770ae6cc | 1893 | for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++) |
4841ba4b | 1894 | { |
770ae6cc RK |
1895 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1896 | regno + nr)) | |
4841ba4b RK |
1897 | break; |
1898 | } | |
1899 | ||
770ae6cc | 1900 | if (nr == HARD_REGNO_NREGS (regno,mode)) |
4841ba4b RK |
1901 | op_costs[i].cost[class] = -1; |
1902 | } | |
1903 | } | |
ec2d92af | 1904 | } |
54dac99e | 1905 | } |
e4600702 RK |
1906 | \f |
1907 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1908 | TO_P is zero) a register of class CLASS in mode MODE. | |
1909 | ||
1910 | X must not be a pseudo. */ | |
1911 | ||
1912 | static int | |
1913 | copy_cost (x, mode, class, to_p) | |
1914 | rtx x; | |
d0af450d | 1915 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e4600702 | 1916 | enum reg_class class; |
d0af450d | 1917 | int to_p ATTRIBUTE_UNUSED; |
e4600702 | 1918 | { |
29a82058 | 1919 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1920 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1921 | #endif |
e4600702 RK |
1922 | |
1923 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1924 | assuming optimal allocation. */ | |
1925 | ||
1926 | if (GET_CODE (x) == SCRATCH) | |
1927 | return 0; | |
1928 | ||
1929 | /* Get the class we will actually use for a reload. */ | |
1930 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1931 | ||
1932 | #ifdef HAVE_SECONDARY_RELOADS | |
a6a2274a | 1933 | /* If we need a secondary reload (we assume here that we are using |
e4600702 RK |
1934 | the secondary reload as an intermediate, not a scratch register), the |
1935 | cost is that to load the input into the intermediate register, then | |
1936 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1937 | ||
1938 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1939 | if (to_p == 1) | |
1940 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1941 | #endif | |
1942 | ||
dd9f0e8f | 1943 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1944 | if (! to_p) |
1945 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1946 | #endif | |
1947 | ||
1948 | if (secondary_class != NO_REGS) | |
e56b4594 | 1949 | return (move_cost[mode][(int) secondary_class][(int) class] |
e4600702 | 1950 | + copy_cost (x, mode, secondary_class, 2)); |
dd9f0e8f | 1951 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1952 | |
1953 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1954 | cost to move between the register classes, and use 2 for everything | |
1955 | else (constants). */ | |
1956 | ||
1957 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1958 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1959 | |
e4600702 | 1960 | else if (GET_CODE (x) == REG) |
e56b4594 | 1961 | return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
e4600702 RK |
1962 | |
1963 | else | |
1964 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
b437f1a7 | 1965 | return COSTS_N_INSNS (1); |
e4600702 RK |
1966 | } |
1967 | \f | |
54dac99e RK |
1968 | /* Record the pseudo registers we must reload into hard registers |
1969 | in a subexpression of a memory address, X. | |
e4600702 RK |
1970 | |
1971 | CLASS is the class that the register needs to be in and is either | |
1972 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1973 | ||
1974 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1975 | can represent half-cost adjustments). */ | |
54dac99e | 1976 | |
197d6480 | 1977 | static void |
e4600702 | 1978 | record_address_regs (x, class, scale) |
54dac99e | 1979 | rtx x; |
e4600702 RK |
1980 | enum reg_class class; |
1981 | int scale; | |
54dac99e | 1982 | { |
b3694847 | 1983 | enum rtx_code code = GET_CODE (x); |
54dac99e RK |
1984 | |
1985 | switch (code) | |
1986 | { | |
1987 | case CONST_INT: | |
1988 | case CONST: | |
1989 | case CC0: | |
1990 | case PC: | |
1991 | case SYMBOL_REF: | |
1992 | case LABEL_REF: | |
1993 | return; | |
1994 | ||
1995 | case PLUS: | |
1996 | /* When we have an address that is a sum, | |
1997 | we must determine whether registers are "base" or "index" regs. | |
1998 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1999 | the "base". Luckily, we can use the REG_POINTER to make a good |
2000 | choice most of the time. We only need to do this on machines | |
2001 | that can have two registers in an address and where the base | |
2002 | and index register classes are different. | |
e4600702 RK |
2003 | |
2004 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
2005 | that seems bogus since it should only be set when we are sure | |
2006 | the register is being used as a pointer. */ | |
2007 | ||
54dac99e RK |
2008 | { |
2009 | rtx arg0 = XEXP (x, 0); | |
2010 | rtx arg1 = XEXP (x, 1); | |
b3694847 SS |
2011 | enum rtx_code code0 = GET_CODE (arg0); |
2012 | enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
2013 | |
2014 | /* Look inside subregs. */ | |
e4600702 | 2015 | if (code0 == SUBREG) |
54dac99e | 2016 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 2017 | if (code1 == SUBREG) |
54dac99e RK |
2018 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
2019 | ||
e4600702 RK |
2020 | /* If this machine only allows one register per address, it must |
2021 | be in the first operand. */ | |
2022 | ||
2023 | if (MAX_REGS_PER_ADDRESS == 1) | |
2024 | record_address_regs (arg0, class, scale); | |
2025 | ||
2026 | /* If index and base registers are the same on this machine, just | |
2027 | record registers in any non-constant operands. We assume here, | |
a6a2274a | 2028 | as well as in the tests below, that all addresses are in |
e4600702 RK |
2029 | canonical form. */ |
2030 | ||
3dcc68a4 | 2031 | else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) |
54dac99e | 2032 | { |
e4600702 RK |
2033 | record_address_regs (arg0, class, scale); |
2034 | if (! CONSTANT_P (arg1)) | |
2035 | record_address_regs (arg1, class, scale); | |
54dac99e | 2036 | } |
e4600702 RK |
2037 | |
2038 | /* If the second operand is a constant integer, it doesn't change | |
2039 | what class the first operand must be. */ | |
2040 | ||
2041 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
2042 | record_address_regs (arg0, class, scale); | |
2043 | ||
2044 | /* If the second operand is a symbolic constant, the first operand | |
2045 | must be an index register. */ | |
2046 | ||
2047 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
2048 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
2049 | ||
956d6950 JL |
2050 | /* If both operands are registers but one is already a hard register |
2051 | of index or base class, give the other the class that the hard | |
2052 | register is not. */ | |
2053 | ||
3f9e9508 | 2054 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
2055 | else if (code0 == REG && code1 == REG |
2056 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
2057 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
2058 | record_address_regs (arg1, | |
2059 | REG_OK_FOR_BASE_P (arg0) | |
3dcc68a4 | 2060 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 JL |
2061 | scale); |
2062 | else if (code0 == REG && code1 == REG | |
2063 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
2064 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
2065 | record_address_regs (arg0, | |
2066 | REG_OK_FOR_BASE_P (arg1) | |
3dcc68a4 | 2067 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 | 2068 | scale); |
3f9e9508 | 2069 | #endif |
956d6950 | 2070 | |
e9a25f70 JL |
2071 | /* If one operand is known to be a pointer, it must be the base |
2072 | with the other operand the index. Likewise if the other operand | |
2073 | is a MULT. */ | |
f22376c7 | 2074 | |
3502dc9c | 2075 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 2076 | || code1 == MULT) |
f22376c7 | 2077 | { |
3dcc68a4 | 2078 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2079 | record_address_regs (arg1, INDEX_REG_CLASS, scale); |
2080 | } | |
3502dc9c | 2081 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 2082 | || code0 == MULT) |
f22376c7 CI |
2083 | { |
2084 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
3dcc68a4 | 2085 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2086 | } |
2087 | ||
e9a25f70 | 2088 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
2089 | or index register. This case should be rare. */ |
2090 | ||
e9a25f70 | 2091 | else |
54dac99e | 2092 | { |
3dcc68a4 NC |
2093 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), |
2094 | scale / 2); | |
e4600702 | 2095 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); |
3dcc68a4 NC |
2096 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), |
2097 | scale / 2); | |
e4600702 | 2098 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); |
54dac99e | 2099 | } |
54dac99e RK |
2100 | } |
2101 | break; | |
2102 | ||
4b983fdc RH |
2103 | /* Double the importance of a pseudo register that is incremented |
2104 | or decremented, since it would take two extra insns | |
2105 | if it ends up in the wrong place. */ | |
2106 | case POST_MODIFY: | |
2107 | case PRE_MODIFY: | |
3dcc68a4 NC |
2108 | record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), |
2109 | 2 * scale); | |
4b983fdc RH |
2110 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
2111 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
2112 | INDEX_REG_CLASS, 2 * scale); | |
2113 | break; | |
2114 | ||
54dac99e RK |
2115 | case POST_INC: |
2116 | case PRE_INC: | |
2117 | case POST_DEC: | |
2118 | case PRE_DEC: | |
2119 | /* Double the importance of a pseudo register that is incremented | |
2120 | or decremented, since it would take two extra insns | |
533d0835 RK |
2121 | if it ends up in the wrong place. If the operand is a pseudo, |
2122 | show it is being used in an INC_DEC context. */ | |
2123 | ||
2124 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2125 | if (GET_CODE (XEXP (x, 0)) == REG | |
2126 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
2127 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2128 | #endif | |
e4600702 RK |
2129 | |
2130 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
2131 | break; |
2132 | ||
2133 | case REG: | |
2134 | { | |
b3694847 SS |
2135 | struct costs *pp = &costs[REGNO (x)]; |
2136 | int i; | |
54dac99e | 2137 | |
cbd5b9a2 | 2138 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 2139 | |
e4600702 | 2140 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 2141 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
2142 | } |
2143 | break; | |
2144 | ||
2145 | default: | |
2146 | { | |
b3694847 SS |
2147 | const char *fmt = GET_RTX_FORMAT (code); |
2148 | int i; | |
54dac99e RK |
2149 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2150 | if (fmt[i] == 'e') | |
e4600702 | 2151 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
2152 | } |
2153 | } | |
2154 | } | |
08d95f91 RK |
2155 | \f |
2156 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2157 | ||
2158 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2159 | to an object of MODE. */ | |
2160 | ||
1d300e19 | 2161 | static int |
08d95f91 RK |
2162 | auto_inc_dec_reg_p (reg, mode) |
2163 | rtx reg; | |
2164 | enum machine_mode mode; | |
2165 | { | |
940da324 JL |
2166 | if (HAVE_POST_INCREMENT |
2167 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2168 | return 1; |
08d95f91 | 2169 | |
940da324 JL |
2170 | if (HAVE_POST_DECREMENT |
2171 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2172 | return 1; |
08d95f91 | 2173 | |
940da324 JL |
2174 | if (HAVE_PRE_INCREMENT |
2175 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2176 | return 1; |
08d95f91 | 2177 | |
940da324 JL |
2178 | if (HAVE_PRE_DECREMENT |
2179 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2180 | return 1; |
08d95f91 RK |
2181 | |
2182 | return 0; | |
2183 | } | |
2184 | #endif | |
b1f21e0a | 2185 | \f |
da668e9c MM |
2186 | static short *renumber; |
2187 | static size_t regno_allocated; | |
2188 | static unsigned int reg_n_max; | |
ed396e68 | 2189 | |
b1f21e0a MM |
2190 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2191 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
2192 | NEW_P is non zero, initialize all of the registers, otherwise only |
2193 | initialize the new registers allocated. The same table is kept from | |
2194 | function to function, only reallocating it when we need more room. If | |
2195 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
2196 | |
2197 | void | |
39379e67 | 2198 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 2199 | size_t num_regs; |
b1f21e0a | 2200 | int new_p; |
39379e67 | 2201 | int renumber_p; |
b1f21e0a | 2202 | { |
6feacd09 MM |
2203 | size_t size_info; |
2204 | size_t size_renumber; | |
2205 | size_t min = (new_p) ? 0 : reg_n_max; | |
2206 | struct reg_info_data *reg_data; | |
39379e67 | 2207 | |
b1f21e0a MM |
2208 | if (num_regs > regno_allocated) |
2209 | { | |
6feacd09 MM |
2210 | size_t old_allocated = regno_allocated; |
2211 | ||
b1f21e0a | 2212 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
2213 | size_renumber = regno_allocated * sizeof (short); |
2214 | ||
2215 | if (!reg_n_info) | |
2216 | { | |
6feacd09 | 2217 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 2218 | renumber = (short *) xmalloc (size_renumber); |
a6a2274a | 2219 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
9ffc5a70 | 2220 | * sizeof (struct reg_pref)); |
39379e67 MM |
2221 | } |
2222 | ||
2223 | else | |
2224 | { | |
6feacd09 MM |
2225 | VARRAY_GROW (reg_n_info, regno_allocated); |
2226 | ||
2227 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
2228 | { | |
8e2e89f7 KH |
2229 | free ((char *) renumber); |
2230 | free ((char *) reg_pref); | |
6feacd09 | 2231 | renumber = (short *) xmalloc (size_renumber); |
a6a2274a | 2232 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
9ffc5a70 | 2233 | * sizeof (struct reg_pref)); |
6feacd09 MM |
2234 | } |
2235 | ||
2236 | else | |
2237 | { | |
8e2e89f7 KH |
2238 | renumber = (short *) xrealloc ((char *) renumber, size_renumber); |
2239 | reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer, | |
a6a2274a | 2240 | regno_allocated |
9ffc5a70 | 2241 | * sizeof (struct reg_pref)); |
6feacd09 | 2242 | } |
39379e67 | 2243 | } |
6feacd09 MM |
2244 | |
2245 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2246 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
2247 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
2248 | reg_data->min_index = old_allocated; | |
2249 | reg_data->max_index = regno_allocated - 1; | |
2250 | reg_data->next = reg_info_head; | |
2251 | reg_info_head = reg_data; | |
b1f21e0a MM |
2252 | } |
2253 | ||
6feacd09 | 2254 | reg_n_max = num_regs; |
b1f21e0a MM |
2255 | if (min < num_regs) |
2256 | { | |
6feacd09 MM |
2257 | /* Loop through each of the segments allocated for the actual |
2258 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
a6a2274a | 2259 | for (reg_data = reg_info_head; |
da668e9c MM |
2260 | reg_data && reg_data->max_index >= min; |
2261 | reg_data = reg_data->next) | |
39379e67 | 2262 | { |
6feacd09 MM |
2263 | size_t min_index = reg_data->min_index; |
2264 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2265 | size_t max = MIN (max_index, num_regs); |
2266 | size_t local_min = min - min_index; | |
2267 | size_t i; | |
6feacd09 | 2268 | |
da668e9c MM |
2269 | if (reg_data->min_index > num_regs) |
2270 | continue; | |
6feacd09 | 2271 | |
da668e9c MM |
2272 | if (min < min_index) |
2273 | local_min = 0; | |
2274 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2275 | reg_data->used_p = 1; /* no need to zero */ | |
2276 | else | |
961192e1 | 2277 | memset ((char *) ®_data->data[local_min], 0, |
da668e9c MM |
2278 | sizeof (reg_info) * (max - min_index - local_min + 1)); |
2279 | ||
2280 | for (i = min_index+local_min; i <= max; i++) | |
2281 | { | |
2282 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2283 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2284 | renumber[i] = -1; | |
2285 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2286 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2287 | } |
39379e67 | 2288 | } |
b1f21e0a MM |
2289 | } |
2290 | ||
6feacd09 MM |
2291 | /* If {pref,alt}class have already been allocated, update the pointers to |
2292 | the newly realloced ones. */ | |
9ffc5a70 JH |
2293 | if (reg_pref) |
2294 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2295 | |
39379e67 MM |
2296 | if (renumber_p) |
2297 | reg_renumber = renumber; | |
2298 | ||
73b76448 RK |
2299 | /* Tell the regset code about the new number of registers */ |
2300 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
2301 | } |
2302 | ||
ed396e68 BS |
2303 | /* Free up the space allocated by allocate_reg_info. */ |
2304 | void | |
2305 | free_reg_info () | |
2306 | { | |
2307 | if (reg_n_info) | |
2308 | { | |
2309 | struct reg_info_data *reg_data; | |
2310 | struct reg_info_data *reg_next; | |
2311 | ||
2312 | VARRAY_FREE (reg_n_info); | |
2313 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2314 | { | |
2315 | reg_next = reg_data->next; | |
8e2e89f7 | 2316 | free ((char *) reg_data); |
ed396e68 BS |
2317 | } |
2318 | ||
9ffc5a70 | 2319 | free (reg_pref_buffer); |
f4f4d0f8 KH |
2320 | reg_pref_buffer = (struct reg_pref *) 0; |
2321 | reg_info_head = (struct reg_info_data *) 0; | |
2322 | renumber = (short *) 0; | |
ed396e68 BS |
2323 | } |
2324 | regno_allocated = 0; | |
2325 | reg_n_max = 0; | |
2326 | } | |
54dac99e RK |
2327 | \f |
2328 | /* This is the `regscan' pass of the compiler, run just before cse | |
2329 | and again just before loop. | |
2330 | ||
2331 | It finds the first and last use of each pseudo-register | |
2332 | and records them in the vectors regno_first_uid, regno_last_uid | |
2333 | and counts the number of sets in the vector reg_n_sets. | |
2334 | ||
2335 | REPEAT is nonzero the second time this is called. */ | |
2336 | ||
54dac99e | 2337 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2338 | Always at least 3, since the combiner could put that many together |
79b9ec0d RK |
2339 | and we want this to remain correct for all the remaining passes. |
2340 | This corresponds to the maximum number of times note_stores will call | |
2341 | a function for any insn. */ | |
54dac99e RK |
2342 | |
2343 | int max_parallel; | |
2344 | ||
a6a2274a | 2345 | /* Used as a temporary to record the largest number of registers in |
79b9ec0d RK |
2346 | PARALLEL in a SET_DEST. This is added to max_parallel. */ |
2347 | ||
2348 | static int max_set_parallel; | |
2349 | ||
54dac99e RK |
2350 | void |
2351 | reg_scan (f, nregs, repeat) | |
2352 | rtx f; | |
770ae6cc | 2353 | unsigned int nregs; |
272df862 | 2354 | int repeat ATTRIBUTE_UNUSED; |
54dac99e | 2355 | { |
b3694847 | 2356 | rtx insn; |
54dac99e | 2357 | |
39379e67 | 2358 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e | 2359 | max_parallel = 3; |
79b9ec0d | 2360 | max_set_parallel = 0; |
54dac99e RK |
2361 | |
2362 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2363 | if (GET_CODE (insn) == INSN | |
2364 | || GET_CODE (insn) == CALL_INSN | |
2365 | || GET_CODE (insn) == JUMP_INSN) | |
2366 | { | |
2367 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2368 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2369 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2370 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2371 | |
2372 | if (REG_NOTES (insn)) | |
f903b91f DM |
2373 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2374 | } | |
79b9ec0d RK |
2375 | |
2376 | max_parallel += max_set_parallel; | |
f903b91f DM |
2377 | } |
2378 | ||
2379 | /* Update 'regscan' information by looking at the insns | |
2380 | from FIRST to LAST. Some new REGs have been created, | |
2381 | and any REG with number greater than OLD_MAX_REGNO is | |
2382 | such a REG. We only update information for those. */ | |
2383 | ||
2384 | void | |
770ae6cc | 2385 | reg_scan_update (first, last, old_max_regno) |
f903b91f DM |
2386 | rtx first; |
2387 | rtx last; | |
770ae6cc | 2388 | unsigned int old_max_regno; |
f903b91f | 2389 | { |
b3694847 | 2390 | rtx insn; |
f903b91f DM |
2391 | |
2392 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2393 | ||
2394 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2395 | if (GET_CODE (insn) == INSN | |
2396 | || GET_CODE (insn) == CALL_INSN | |
2397 | || GET_CODE (insn) == JUMP_INSN) | |
2398 | { | |
2399 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2400 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2401 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2402 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2403 | ||
2404 | if (REG_NOTES (insn)) | |
2405 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2406 | } |
2407 | } | |
2408 | ||
1ebecb64 | 2409 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2410 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2411 | We should only record information for REGs with numbers | |
2412 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2413 | |
08d95f91 | 2414 | static void |
f903b91f | 2415 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2416 | rtx x; |
be8dcd74 | 2417 | rtx insn; |
1ebecb64 | 2418 | int note_flag; |
770ae6cc | 2419 | unsigned int min_regno; |
54dac99e | 2420 | { |
b3694847 SS |
2421 | enum rtx_code code; |
2422 | rtx dest; | |
2423 | rtx note; | |
54dac99e | 2424 | |
ed8d2920 MM |
2425 | if (!x) |
2426 | return; | |
fa23c636 | 2427 | code = GET_CODE (x); |
54dac99e RK |
2428 | switch (code) |
2429 | { | |
54dac99e | 2430 | case CONST: |
185ebd6c | 2431 | case CONST_INT: |
54dac99e | 2432 | case CONST_DOUBLE: |
69ef87e2 | 2433 | case CONST_VECTOR: |
54dac99e RK |
2434 | case CC0: |
2435 | case PC: | |
2436 | case SYMBOL_REF: | |
2437 | case LABEL_REF: | |
2438 | case ADDR_VEC: | |
2439 | case ADDR_DIFF_VEC: | |
2440 | return; | |
2441 | ||
2442 | case REG: | |
2443 | { | |
770ae6cc | 2444 | unsigned int regno = REGNO (x); |
54dac99e | 2445 | |
f903b91f DM |
2446 | if (regno >= min_regno) |
2447 | { | |
2448 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2449 | if (!note_flag) | |
2450 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2451 | if (REGNO_FIRST_UID (regno) == 0) | |
2452 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
ed8d2920 MM |
2453 | /* If we are called by reg_scan_update() (indicated by min_regno |
2454 | being set), we also need to update the reference count. */ | |
2455 | if (min_regno) | |
2456 | REG_N_REFS (regno)++; | |
f903b91f | 2457 | } |
54dac99e RK |
2458 | } |
2459 | break; | |
2460 | ||
01565a55 | 2461 | case EXPR_LIST: |
7b18c3db | 2462 | if (XEXP (x, 0)) |
f903b91f | 2463 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2464 | if (XEXP (x, 1)) |
f903b91f | 2465 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2466 | break; |
2467 | ||
2468 | case INSN_LIST: | |
2469 | if (XEXP (x, 1)) | |
f903b91f | 2470 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2471 | break; |
2472 | ||
ed8d2920 MM |
2473 | case CLOBBER: |
2474 | { | |
2475 | rtx reg = XEXP (x, 0); | |
2476 | if (REG_P (reg) | |
2477 | && REGNO (reg) >= min_regno) | |
2478 | { | |
2479 | REG_N_SETS (REGNO (reg))++; | |
2480 | REG_N_REFS (REGNO (reg))++; | |
2481 | } | |
2482 | } | |
2483 | break; | |
2484 | ||
54dac99e RK |
2485 | case SET: |
2486 | /* Count a set of the destination if it is a register. */ | |
2487 | for (dest = SET_DEST (x); | |
2488 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2489 | || GET_CODE (dest) == ZERO_EXTEND; | |
2490 | dest = XEXP (dest, 0)) | |
2491 | ; | |
2492 | ||
79b9ec0d RK |
2493 | /* For a PARALLEL, record the number of things (less the usual one for a |
2494 | SET) that are set. */ | |
2495 | if (GET_CODE (dest) == PARALLEL) | |
2496 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2497 | ||
f903b91f DM |
2498 | if (GET_CODE (dest) == REG |
2499 | && REGNO (dest) >= min_regno) | |
b2d57793 DB |
2500 | { |
2501 | REG_N_SETS (REGNO (dest))++; | |
2502 | REG_N_REFS (REGNO (dest))++; | |
2503 | } | |
54dac99e | 2504 | |
be8dcd74 RK |
2505 | /* If this is setting a pseudo from another pseudo or the sum of a |
2506 | pseudo and a constant integer and the other pseudo is known to be | |
2507 | a pointer, set the destination to be a pointer as well. | |
2508 | ||
2509 | Likewise if it is setting the destination from an address or from a | |
2510 | value equivalent to an address or to the sum of an address and | |
2511 | something else. | |
a6a2274a | 2512 | |
be8dcd74 RK |
2513 | But don't do any of this if the pseudo corresponds to a user |
2514 | variable since it should have already been set as a pointer based | |
2515 | on the type. */ | |
2516 | ||
2517 | if (GET_CODE (SET_DEST (x)) == REG | |
2518 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2519 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2520 | /* If the destination pseudo is set more than once, then other |
2521 | sets might not be to a pointer value (consider access to a | |
2522 | union in two threads of control in the presense of global | |
3502dc9c | 2523 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2524 | pseudo if this is the only set of that pseudo. */ |
2525 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2526 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2527 | && ! REG_POINTER (SET_DEST (x)) |
be8dcd74 | 2528 | && ((GET_CODE (SET_SRC (x)) == REG |
3502dc9c | 2529 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2530 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2531 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2532 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2533 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3502dc9c | 2534 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2535 | || GET_CODE (SET_SRC (x)) == CONST |
2536 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2537 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2538 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2539 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2540 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2541 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2542 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2543 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2544 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2545 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2546 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2547 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2548 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2549 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2550 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2551 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2552 | |
0d4903b8 RK |
2553 | /* If this is setting a register from a register or from a simple |
2554 | conversion of a register, propagate REG_DECL. */ | |
2555 | if (GET_CODE (dest) == REG) | |
2556 | { | |
2557 | rtx src = SET_SRC (x); | |
2558 | ||
2559 | while (GET_CODE (src) == SIGN_EXTEND | |
2560 | || GET_CODE (src) == ZERO_EXTEND | |
2561 | || GET_CODE (src) == TRUNCATE | |
2562 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2563 | src = XEXP (src, 0); | |
2564 | ||
2565 | if (GET_CODE (src) == REG && REGNO_DECL (REGNO (src)) == 0) | |
2566 | REGNO_DECL (REGNO (src)) = REGNO_DECL (REGNO (dest)); | |
2567 | else if (GET_CODE (src) == REG && REGNO_DECL (REGNO (dest)) == 0) | |
2568 | REGNO_DECL (REGNO (dest)) = REGNO_DECL (REGNO (src)); | |
2569 | } | |
2570 | ||
0f41302f | 2571 | /* ... fall through ... */ |
54dac99e RK |
2572 | |
2573 | default: | |
2574 | { | |
b3694847 SS |
2575 | const char *fmt = GET_RTX_FORMAT (code); |
2576 | int i; | |
54dac99e RK |
2577 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2578 | { | |
2579 | if (fmt[i] == 'e') | |
f903b91f | 2580 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2581 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2582 | { | |
b3694847 | 2583 | int j; |
54dac99e | 2584 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
f903b91f | 2585 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2586 | } |
2587 | } | |
2588 | } | |
2589 | } | |
2590 | } | |
2591 | \f | |
2592 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2593 | is also in C2. */ | |
2594 | ||
2595 | int | |
2596 | reg_class_subset_p (c1, c2) | |
b3694847 SS |
2597 | enum reg_class c1; |
2598 | enum reg_class c2; | |
54dac99e RK |
2599 | { |
2600 | if (c1 == c2) return 1; | |
2601 | ||
2602 | if (c2 == ALL_REGS) | |
2603 | win: | |
2604 | return 1; | |
8e2e89f7 KH |
2605 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], |
2606 | reg_class_contents[(int) c2], | |
54dac99e RK |
2607 | win); |
2608 | return 0; | |
2609 | } | |
2610 | ||
2611 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2612 | ||
2613 | int | |
2614 | reg_classes_intersect_p (c1, c2) | |
b3694847 SS |
2615 | enum reg_class c1; |
2616 | enum reg_class c2; | |
54dac99e RK |
2617 | { |
2618 | #ifdef HARD_REG_SET | |
2619 | register | |
2620 | #endif | |
2621 | HARD_REG_SET c; | |
2622 | ||
2623 | if (c1 == c2) return 1; | |
2624 | ||
2625 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2626 | return 1; | |
2627 | ||
2628 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2629 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2630 | ||
2631 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2632 | return 1; | |
2633 | ||
2634 | lose: | |
2635 | return 0; | |
2636 | } | |
2637 | ||
73b76448 RK |
2638 | /* Release any memory allocated by register sets. */ |
2639 | ||
2640 | void | |
2641 | regset_release_memory () | |
2642 | { | |
73b76448 RK |
2643 | bitmap_release_memory (); |
2644 | } | |
e2500fed GK |
2645 | |
2646 | #include "gt-regclass.h" |