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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
29a82058 | 2 | Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
670ee920 | 27 | #include "system.h" |
54dac99e RK |
28 | #include "rtl.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "flags.h" | |
31 | #include "basic-block.h" | |
32 | #include "regs.h" | |
33 | #include "insn-config.h" | |
34 | #include "recog.h" | |
e4600702 RK |
35 | #include "reload.h" |
36 | #include "real.h" | |
10f0ad3d | 37 | #include "toplev.h" |
d6f4ec51 | 38 | #include "output.h" |
54dac99e RK |
39 | |
40 | #ifndef REGISTER_MOVE_COST | |
41 | #define REGISTER_MOVE_COST(x, y) 2 | |
42 | #endif | |
43 | ||
533d0835 RK |
44 | /* If we have auto-increment or auto-decrement and we can have secondary |
45 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 46 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
47 | |
48 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 49 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
50 | #define FORBIDDEN_INC_DEC_CLASSES |
51 | #endif | |
52 | #endif | |
54dac99e RK |
53 | \f |
54 | /* Register tables used by many passes. */ | |
55 | ||
56 | /* Indexed by hard register number, contains 1 for registers | |
57 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
58 | These are the registers that cannot be used to allocate | |
252f342a | 59 | a pseudo reg for general use. */ |
54dac99e RK |
60 | |
61 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
62 | ||
63 | /* Same info as a HARD_REG_SET. */ | |
64 | ||
65 | HARD_REG_SET fixed_reg_set; | |
66 | ||
67 | /* Data for initializing the above. */ | |
68 | ||
69 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
70 | ||
71 | /* Indexed by hard register number, contains 1 for registers | |
72 | that are fixed use or are clobbered by function calls. | |
73 | These are the registers that cannot be used to allocate | |
252f342a MH |
74 | a pseudo reg whose life crosses calls unless we are able |
75 | to save/restore them across the calls. */ | |
54dac99e RK |
76 | |
77 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
78 | ||
79 | /* Same info as a HARD_REG_SET. */ | |
80 | ||
81 | HARD_REG_SET call_used_reg_set; | |
82 | ||
6cad67d2 JL |
83 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
84 | HARD_REG_SET losing_caller_save_reg_set; | |
85 | ||
54dac99e RK |
86 | /* Data for initializing the above. */ |
87 | ||
88 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
89 | ||
90 | /* Indexed by hard register number, contains 1 for registers that are | |
252f342a MH |
91 | fixed use or call used registers that cannot hold quantities across |
92 | calls even if we are willing to save and restore them. call fixed | |
93 | registers are a subset of call used registers. */ | |
54dac99e RK |
94 | |
95 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
96 | ||
97 | /* The same info as a HARD_REG_SET. */ | |
98 | ||
99 | HARD_REG_SET call_fixed_reg_set; | |
100 | ||
101 | /* Number of non-fixed registers. */ | |
102 | ||
103 | int n_non_fixed_regs; | |
104 | ||
105 | /* Indexed by hard register number, contains 1 for registers | |
106 | that are being used for global register decls. | |
107 | These must be exempt from ordinary flow analysis | |
108 | and are also considered fixed. */ | |
109 | ||
110 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
111 | ||
112 | /* Table of register numbers in the order in which to try to use them. */ | |
113 | #ifdef REG_ALLOC_ORDER | |
114 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
115 | #endif | |
116 | ||
117 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
118 | ||
2e0e2b76 CH |
119 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
120 | ||
089e575b RS |
121 | /* The same information, but as an array of unsigned ints. We copy from |
122 | these unsigned ints to the table above. We do this so the tm.h files | |
123 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
124 | |
125 | #define N_REG_INTS \ | |
126 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
127 | ||
089e575b | 128 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 129 | = REG_CLASS_CONTENTS; |
54dac99e RK |
130 | |
131 | /* For each reg class, number of regs it contains. */ | |
132 | ||
133 | int reg_class_size[N_REG_CLASSES]; | |
134 | ||
135 | /* For each reg class, table listing all the containing classes. */ | |
136 | ||
137 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
138 | ||
139 | /* For each reg class, table listing all the classes contained in it. */ | |
140 | ||
141 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
142 | ||
143 | /* For each pair of reg classes, | |
144 | a largest reg class contained in their union. */ | |
145 | ||
146 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
147 | ||
148 | /* For each pair of reg classes, | |
149 | the smallest reg class containing their union. */ | |
150 | ||
151 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
152 | ||
d05c8ee7 RS |
153 | /* Array containing all of the register names */ |
154 | ||
155 | char *reg_names[] = REGISTER_NAMES; | |
156 | ||
ca4aac00 DE |
157 | /* For each hard register, the widest mode object that it can contain. |
158 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
159 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
160 | register. */ | |
161 | ||
162 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
163 | ||
e4600702 RK |
164 | /* Maximum cost of moving from a register in one class to a register in |
165 | another class. Based on REGISTER_MOVE_COST. */ | |
166 | ||
167 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
168 | ||
169 | /* Similar, but here we don't have to move if the first index is a subset | |
170 | of the second so in that case the cost is zero. */ | |
171 | ||
172 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
173 | ||
533d0835 RK |
174 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
175 | ||
176 | /* These are the classes that regs which are auto-incremented or decremented | |
177 | cannot be put in. */ | |
178 | ||
179 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
180 | ||
181 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
182 | context. */ | |
183 | ||
184 | static char *in_inc_dec; | |
185 | ||
5fcb671c | 186 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 187 | |
473fe49b KR |
188 | #ifdef HAVE_SECONDARY_RELOADS |
189 | ||
190 | /* Sample MEM values for use by memory_move_secondary_cost. */ | |
191 | ||
192 | static rtx top_of_stack[MAX_MACHINE_MODE]; | |
193 | ||
194 | #endif /* HAVE_SECONDARY_RELOADS */ | |
195 | ||
6feacd09 MM |
196 | /* Linked list of reg_info structures allocated for reg_n_info array. |
197 | Grouping all of the allocated structures together in one lump | |
198 | means only one call to bzero to clear them, rather than n smaller | |
199 | calls. */ | |
200 | struct reg_info_data { | |
201 | struct reg_info_data *next; /* next set of reg_info structures */ | |
202 | size_t min_index; /* minimum index # */ | |
203 | size_t max_index; /* maximum index # */ | |
204 | char used_p; /* non-zero if this has been used previously */ | |
205 | reg_info data[1]; /* beginning of the reg_info data */ | |
206 | }; | |
207 | ||
208 | static struct reg_info_data *reg_info_head; | |
209 | ||
210 | ||
54dac99e RK |
211 | /* Function called only once to initialize the above data on reg usage. |
212 | Once this is done, various switches may override. */ | |
213 | ||
214 | void | |
215 | init_reg_sets () | |
216 | { | |
217 | register int i, j; | |
218 | ||
2e0e2b76 CH |
219 | /* First copy the register information from the initial int form into |
220 | the regsets. */ | |
221 | ||
222 | for (i = 0; i < N_REG_CLASSES; i++) | |
223 | { | |
224 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
225 | ||
226 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
227 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 228 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
229 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
230 | } | |
231 | ||
54dac99e RK |
232 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
233 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
234 | bzero (global_regs, sizeof global_regs); | |
235 | ||
236 | /* Compute number of hard regs in each class. */ | |
237 | ||
4c9a05bc | 238 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
239 | for (i = 0; i < N_REG_CLASSES; i++) |
240 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
241 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
242 | reg_class_size[i]++; | |
243 | ||
244 | /* Initialize the table of subunions. | |
245 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
246 | that is contained in the union of classes I and J. */ | |
247 | ||
248 | for (i = 0; i < N_REG_CLASSES; i++) | |
249 | { | |
250 | for (j = 0; j < N_REG_CLASSES; j++) | |
251 | { | |
252 | #ifdef HARD_REG_SET | |
253 | register /* Declare it register if it's a scalar. */ | |
254 | #endif | |
255 | HARD_REG_SET c; | |
256 | register int k; | |
257 | ||
258 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
259 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
260 | for (k = 0; k < N_REG_CLASSES; k++) | |
261 | { | |
262 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
263 | subclass1); | |
264 | continue; | |
265 | ||
266 | subclass1: | |
267 | /* keep the largest subclass */ /* SPEE 900308 */ | |
268 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
269 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
270 | subclass2); | |
271 | reg_class_subunion[i][j] = (enum reg_class) k; | |
272 | subclass2: | |
273 | ; | |
274 | } | |
275 | } | |
276 | } | |
277 | ||
278 | /* Initialize the table of superunions. | |
279 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
280 | containing the union of classes I and J. */ | |
281 | ||
282 | for (i = 0; i < N_REG_CLASSES; i++) | |
283 | { | |
284 | for (j = 0; j < N_REG_CLASSES; j++) | |
285 | { | |
286 | #ifdef HARD_REG_SET | |
287 | register /* Declare it register if it's a scalar. */ | |
288 | #endif | |
289 | HARD_REG_SET c; | |
290 | register int k; | |
291 | ||
292 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
293 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
294 | for (k = 0; k < N_REG_CLASSES; k++) | |
295 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
296 | ||
297 | superclass: | |
298 | reg_class_superunion[i][j] = (enum reg_class) k; | |
299 | } | |
300 | } | |
301 | ||
302 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
303 | First clear the whole table, then add the elements as they are found. */ | |
304 | ||
305 | for (i = 0; i < N_REG_CLASSES; i++) | |
306 | { | |
307 | for (j = 0; j < N_REG_CLASSES; j++) | |
308 | { | |
309 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
310 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
311 | } | |
312 | } | |
313 | ||
314 | for (i = 0; i < N_REG_CLASSES; i++) | |
315 | { | |
316 | if (i == (int) NO_REGS) | |
317 | continue; | |
318 | ||
319 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
320 | { | |
321 | enum reg_class *p; | |
322 | ||
323 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
324 | subclass); | |
325 | continue; | |
326 | subclass: | |
327 | /* Reg class I is a subclass of J. | |
328 | Add J to the table of superclasses of I. */ | |
329 | p = ®_class_superclasses[i][0]; | |
330 | while (*p != LIM_REG_CLASSES) p++; | |
331 | *p = (enum reg_class) j; | |
332 | /* Add I to the table of superclasses of J. */ | |
333 | p = ®_class_subclasses[j][0]; | |
334 | while (*p != LIM_REG_CLASSES) p++; | |
335 | *p = (enum reg_class) i; | |
336 | } | |
337 | } | |
e4600702 | 338 | |
73b76448 RK |
339 | /* Do any additional initialization regsets may need */ |
340 | INIT_ONCE_REG_SET (); | |
54dac99e RK |
341 | } |
342 | ||
343 | /* After switches have been processed, which perhaps alter | |
344 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
345 | ||
c27c5281 | 346 | static void |
54dac99e RK |
347 | init_reg_sets_1 () |
348 | { | |
f8344bea | 349 | register unsigned int i, j; |
54dac99e RK |
350 | |
351 | /* This macro allows the fixed or call-used registers | |
352 | to depend on target flags. */ | |
353 | ||
354 | #ifdef CONDITIONAL_REGISTER_USAGE | |
355 | CONDITIONAL_REGISTER_USAGE; | |
356 | #endif | |
357 | ||
54dac99e RK |
358 | /* Initialize "constant" tables. */ |
359 | ||
360 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
361 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
362 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
363 | ||
364 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
365 | |
366 | n_non_fixed_regs = 0; | |
367 | ||
368 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
369 | { | |
54dac99e RK |
370 | if (fixed_regs[i]) |
371 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
372 | else | |
373 | n_non_fixed_regs++; | |
374 | ||
375 | if (call_used_regs[i]) | |
376 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
377 | if (call_fixed_regs[i]) | |
378 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
379 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
380 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 381 | } |
acbce667 KR |
382 | |
383 | /* Initialize the move cost table. Find every subset of each class | |
384 | and take the maximum cost of moving any subset to any other. */ | |
385 | ||
386 | for (i = 0; i < N_REG_CLASSES; i++) | |
387 | for (j = 0; j < N_REG_CLASSES; j++) | |
388 | { | |
389 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
390 | enum reg_class *p1, *p2; | |
391 | ||
392 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
393 | if (*p2 != i) | |
394 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
395 | ||
396 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
397 | { | |
398 | if (*p1 != j) | |
399 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
400 | ||
401 | for (p2 = ®_class_subclasses[j][0]; | |
402 | *p2 != LIM_REG_CLASSES; p2++) | |
403 | if (*p1 != *p2) | |
404 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
405 | } | |
406 | ||
407 | move_cost[i][j] = cost; | |
408 | ||
409 | if (reg_class_subset_p (i, j)) | |
410 | cost = 0; | |
411 | ||
412 | may_move_cost[i][j] = cost; | |
413 | } | |
c27c5281 DE |
414 | } |
415 | ||
416 | /* Compute the table of register modes. | |
417 | These values are used to record death information for individual registers | |
418 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 419 | |
c27c5281 DE |
420 | static void |
421 | init_reg_modes () | |
422 | { | |
423 | register int i; | |
ca4aac00 DE |
424 | |
425 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
426 | { |
427 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
428 | ||
066c2fea | 429 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
430 | ??? One situation in which we need to do this is on the mips where |
431 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
432 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 433 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 434 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 435 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 436 | } |
ca4aac00 DE |
437 | } |
438 | ||
c27c5281 DE |
439 | /* Finish initializing the register sets and |
440 | initialize the register modes. */ | |
441 | ||
442 | void | |
443 | init_regs () | |
444 | { | |
445 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
446 | until after register usage was specified. */ | |
b93a436e | 447 | init_reg_sets_1 (); |
c27c5281 DE |
448 | |
449 | init_reg_modes (); | |
473fe49b KR |
450 | |
451 | #ifdef HAVE_SECONDARY_RELOADS | |
452 | { | |
453 | /* Make some fake stack-frame MEM references for use in | |
454 | memory_move_secondary_cost. */ | |
455 | int i; | |
456 | for (i = 0; i < MAX_MACHINE_MODE; i++) | |
9ec36da5 | 457 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
458 | } |
459 | #endif | |
c27c5281 DE |
460 | } |
461 | ||
cbd5b9a2 | 462 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 463 | |
cbd5b9a2 KR |
464 | /* Compute extra cost of moving registers to/from memory due to reloads. |
465 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 466 | |
cbd5b9a2 KR |
467 | int |
468 | memory_move_secondary_cost (mode, class, in) | |
469 | enum machine_mode mode; | |
470 | enum reg_class class; | |
471 | int in; | |
472 | { | |
473 | enum reg_class altclass; | |
474 | int partial_cost = 0; | |
cbd5b9a2 | 475 | /* We need a memory reference to feed to SECONDARY... macros. */ |
473fe49b | 476 | rtx mem = top_of_stack[(int) mode]; |
cbd5b9a2 KR |
477 | |
478 | if (in) | |
473fe49b | 479 | { |
321c0828 | 480 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 481 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 482 | #else |
473fe49b | 483 | altclass = NO_REGS; |
321c0828 | 484 | #endif |
473fe49b | 485 | } |
cbd5b9a2 | 486 | else |
473fe49b | 487 | { |
321c0828 | 488 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 489 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 490 | #else |
473fe49b | 491 | altclass = NO_REGS; |
321c0828 | 492 | #endif |
473fe49b KR |
493 | } |
494 | ||
cbd5b9a2 KR |
495 | if (altclass == NO_REGS) |
496 | return 0; | |
497 | ||
498 | if (in) | |
499 | partial_cost = REGISTER_MOVE_COST (altclass, class); | |
500 | else | |
501 | partial_cost = REGISTER_MOVE_COST (class, altclass); | |
502 | ||
503 | if (class == altclass) | |
504 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
505 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
506 | here in that case. | |
507 | ||
508 | I'm tempted to put in an abort here, but returning this will | |
509 | probably only give poor estimates, which is what we would've | |
510 | had before this code anyways. */ | |
511 | return partial_cost; | |
512 | ||
513 | /* Check if the secondary reload register will also need a | |
514 | secondary reload. */ | |
515 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
516 | } | |
517 | #endif | |
518 | ||
ca4aac00 DE |
519 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
520 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
521 | ||
522 | enum machine_mode | |
523 | choose_hard_reg_mode (regno, nregs) | |
524 | int regno; | |
525 | int nregs; | |
526 | { | |
527 | enum machine_mode found_mode = VOIDmode, mode; | |
528 | ||
529 | /* We first look for the largest integer mode that can be validly | |
530 | held in REGNO. If none, we look for the largest floating-point mode. | |
531 | If we still didn't find a valid mode, try CCmode. */ | |
532 | ||
533 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
534 | mode != VOIDmode; | |
535 | mode = GET_MODE_WIDER_MODE (mode)) | |
536 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
537 | && HARD_REGNO_MODE_OK (regno, mode)) | |
538 | found_mode = mode; | |
539 | ||
540 | if (found_mode != VOIDmode) | |
541 | return found_mode; | |
542 | ||
543 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
544 | mode != VOIDmode; | |
545 | mode = GET_MODE_WIDER_MODE (mode)) | |
546 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
547 | && HARD_REGNO_MODE_OK (regno, mode)) | |
548 | found_mode = mode; | |
549 | ||
550 | if (found_mode != VOIDmode) | |
551 | return found_mode; | |
552 | ||
553 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
554 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
555 | return CCmode; | |
556 | ||
557 | /* We can't find a mode valid for this register. */ | |
558 | return VOIDmode; | |
54dac99e RK |
559 | } |
560 | ||
561 | /* Specify the usage characteristics of the register named NAME. | |
562 | It should be a fixed register if FIXED and a | |
563 | call-used register if CALL_USED. */ | |
564 | ||
565 | void | |
566 | fix_register (name, fixed, call_used) | |
567 | char *name; | |
568 | int fixed, call_used; | |
569 | { | |
570 | int i; | |
571 | ||
572 | /* Decode the name and update the primary form of | |
573 | the register info. */ | |
574 | ||
e5c90c23 TW |
575 | if ((i = decode_reg_name (name)) >= 0) |
576 | { | |
cb2fdc84 GRK |
577 | if ((i == STACK_POINTER_REGNUM |
578 | #ifdef HARD_FRAME_POINTER_REGNUM | |
579 | || i == HARD_FRAME_POINTER_REGNUM | |
580 | #else | |
581 | || i == FRAME_POINTER_REGNUM | |
582 | #endif | |
583 | ) | |
584 | && (fixed == 0 || call_used == 0)) | |
585 | { | |
586 | static char* what_option[2][2] = { | |
587 | "call-saved", "call-used", | |
588 | "no-such-option", "fixed" }; | |
589 | ||
590 | error ("can't use '%s' as a %s register", name, | |
591 | what_option[fixed][call_used]); | |
592 | } | |
593 | else | |
594 | { | |
595 | fixed_regs[i] = fixed; | |
596 | call_used_regs[i] = call_used; | |
597 | } | |
e5c90c23 TW |
598 | } |
599 | else | |
54dac99e RK |
600 | { |
601 | warning ("unknown register name: %s", name); | |
54dac99e RK |
602 | } |
603 | } | |
614f68e2 RK |
604 | |
605 | /* Mark register number I as global. */ | |
606 | ||
607 | void | |
608 | globalize_reg (i) | |
609 | int i; | |
610 | { | |
611 | if (global_regs[i]) | |
612 | { | |
613 | warning ("register used for two global register variables"); | |
614 | return; | |
615 | } | |
616 | ||
617 | if (call_used_regs[i] && ! fixed_regs[i]) | |
618 | warning ("call-clobbered register used for global register variable"); | |
619 | ||
620 | global_regs[i] = 1; | |
621 | ||
622 | /* If already fixed, nothing else to do. */ | |
623 | if (fixed_regs[i]) | |
624 | return; | |
625 | ||
626 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
627 | n_non_fixed_regs--; | |
628 | ||
629 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
630 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
631 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
632 | } | |
54dac99e RK |
633 | \f |
634 | /* Now the data and code for the `regclass' pass, which happens | |
635 | just before local-alloc. */ | |
636 | ||
e4600702 RK |
637 | /* The `costs' struct records the cost of using a hard register of each class |
638 | and of using memory for each pseudo. We use this data to set up | |
639 | register class preferences. */ | |
54dac99e | 640 | |
e4600702 | 641 | struct costs |
54dac99e | 642 | { |
e4600702 RK |
643 | int cost[N_REG_CLASSES]; |
644 | int mem_cost; | |
54dac99e RK |
645 | }; |
646 | ||
e4600702 RK |
647 | /* Record the cost of each class for each pseudo. */ |
648 | ||
649 | static struct costs *costs; | |
650 | ||
61719ba7 BS |
651 | /* Initialized once, and used to initialize cost values for each insn. */ |
652 | ||
653 | static struct costs init_cost; | |
654 | ||
e4600702 RK |
655 | /* Record the same data by operand number, accumulated for each alternative |
656 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
657 | alternative. */ | |
658 | ||
659 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
660 | |
661 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
662 | This is available after `regclass' is run. */ | |
663 | ||
664 | static char *prefclass; | |
665 | ||
54d23420 RK |
666 | /* altclass[R] is a register class that we should use for allocating |
667 | pseudo number R if no register in the preferred class is available. | |
668 | If no register in this class is available, memory is preferred. | |
669 | ||
670 | It might appear to be more general to have a bitmask of classes here, | |
671 | but since it is recommended that there be a class corresponding to the | |
672 | union of most major pair of classes, that generality is not required. | |
673 | ||
54dac99e RK |
674 | This is available after `regclass' is run. */ |
675 | ||
54d23420 | 676 | static char *altclass; |
54dac99e | 677 | |
6feacd09 MM |
678 | /* Allocated buffers for prefclass and altclass. */ |
679 | static char *prefclass_buffer; | |
680 | static char *altclass_buffer; | |
681 | ||
54d23420 | 682 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
683 | |
684 | static int loop_depth; | |
685 | ||
54d23420 RK |
686 | /* Account for the fact that insns within a loop are executed very commonly, |
687 | but don't keep doing this as loops go too deep. */ | |
688 | ||
689 | static int loop_cost; | |
690 | ||
0a578fee | 691 | static int n_occurrences PROTO((int, char *)); |
61719ba7 | 692 | static rtx scan_one_insn PROTO((rtx, int)); |
08d95f91 RK |
693 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
694 | char **, rtx)); | |
695 | static int copy_cost PROTO((rtx, enum machine_mode, | |
696 | enum reg_class, int)); | |
697 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
698 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
699 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
700 | #endif | |
f903b91f | 701 | static void reg_scan_mark_refs PROTO((rtx, rtx, int, int)); |
54dac99e RK |
702 | |
703 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
704 | This function is sometimes called before the info has been computed. | |
705 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
706 | ||
707 | enum reg_class | |
708 | reg_preferred_class (regno) | |
709 | int regno; | |
710 | { | |
711 | if (prefclass == 0) | |
712 | return GENERAL_REGS; | |
713 | return (enum reg_class) prefclass[regno]; | |
714 | } | |
715 | ||
e4600702 RK |
716 | enum reg_class |
717 | reg_alternate_class (regno) | |
b729186a | 718 | int regno; |
54dac99e RK |
719 | { |
720 | if (prefclass == 0) | |
e4600702 RK |
721 | return ALL_REGS; |
722 | ||
723 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
724 | } |
725 | ||
61719ba7 | 726 | /* Initialize some global data for this pass. */ |
54dac99e RK |
727 | |
728 | void | |
729 | regclass_init () | |
730 | { | |
61719ba7 BS |
731 | int i; |
732 | ||
733 | init_cost.mem_cost = 10000; | |
734 | for (i = 0; i < N_REG_CLASSES; i++) | |
735 | init_cost.cost[i] = 10000; | |
736 | ||
737 | /* This prevents dump_flow_info from losing if called | |
738 | before regclass is run. */ | |
54dac99e RK |
739 | prefclass = 0; |
740 | } | |
741 | \f | |
0a578fee BS |
742 | /* Return the number of times character C occurs in string S. */ |
743 | static int | |
744 | n_occurrences (c, s) | |
745 | int c; | |
746 | char *s; | |
747 | { | |
748 | int n = 0; | |
749 | while (*s) | |
750 | n += (*s++ == c); | |
751 | return n; | |
752 | } | |
753 | ||
61719ba7 BS |
754 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
755 | time it would save code to put a certain register in a certain class. | |
756 | PASS, when nonzero, inhibits some optimizations which need only be done | |
757 | once. | |
758 | Return the last insn processed, so that the scan can be continued from | |
759 | there. */ | |
760 | ||
761 | static rtx | |
762 | scan_one_insn (insn, pass) | |
763 | rtx insn; | |
764 | int pass; | |
765 | { | |
766 | enum rtx_code code = GET_CODE (insn); | |
767 | enum rtx_code pat_code; | |
768 | ||
769 | char *constraints[MAX_RECOG_OPERANDS]; | |
770 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
771 | int nalternatives; | |
772 | int noperands; | |
773 | rtx set; | |
774 | int i, j; | |
775 | ||
776 | /* Show that an insn inside a loop is likely to be executed three | |
777 | times more than insns outside a loop. This is much more aggressive | |
778 | than the assumptions made elsewhere and is being tried as an | |
779 | experiment. */ | |
780 | ||
781 | if (code == NOTE) | |
782 | { | |
783 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
784 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
785 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
786 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
787 | ||
788 | return insn; | |
789 | } | |
790 | ||
791 | if (GET_RTX_CLASS (code) != 'i') | |
792 | return insn; | |
793 | ||
794 | pat_code = GET_CODE (PATTERN (insn)); | |
795 | if (pat_code == USE | |
796 | || pat_code == CLOBBER | |
797 | || pat_code == ASM_INPUT | |
798 | || pat_code == ADDR_VEC | |
799 | || pat_code == ADDR_DIFF_VEC) | |
800 | return insn; | |
801 | ||
802 | if (code == INSN | |
803 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) | |
804 | { | |
805 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, | |
806 | constraints, modes); | |
807 | nalternatives = (noperands == 0 ? 0 | |
808 | : n_occurrences (',', constraints[0]) + 1); | |
809 | } | |
810 | else | |
811 | { | |
812 | int insn_code_number = recog_memoized (insn); | |
813 | rtx note; | |
814 | ||
815 | set = single_set (insn); | |
816 | insn_extract (insn); | |
817 | ||
818 | nalternatives = insn_n_alternatives[insn_code_number]; | |
819 | noperands = insn_n_operands[insn_code_number]; | |
820 | ||
821 | /* If this insn loads a parameter from its stack slot, then | |
822 | it represents a savings, rather than a cost, if the | |
823 | parameter is stored in memory. Record this fact. */ | |
824 | ||
825 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG | |
826 | && GET_CODE (SET_SRC (set)) == MEM | |
827 | && (note = find_reg_note (insn, REG_EQUIV, | |
828 | NULL_RTX)) != 0 | |
829 | && GET_CODE (XEXP (note, 0)) == MEM) | |
830 | { | |
831 | costs[REGNO (SET_DEST (set))].mem_cost | |
832 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
833 | GENERAL_REGS, 1) | |
834 | * loop_cost); | |
835 | record_address_regs (XEXP (SET_SRC (set), 0), | |
836 | BASE_REG_CLASS, loop_cost * 2); | |
837 | return insn; | |
838 | } | |
839 | ||
840 | /* Improve handling of two-address insns such as | |
841 | (set X (ashift CONST Y)) where CONST must be made to | |
842 | match X. Change it into two insns: (set X CONST) | |
843 | (set X (ashift X Y)). If we left this for reloading, it | |
844 | would probably get three insns because X and Y might go | |
845 | in the same place. This prevents X and Y from receiving | |
846 | the same hard reg. | |
847 | ||
848 | We can only do this if the modes of operands 0 and 1 | |
849 | (which might not be the same) are tieable and we only need | |
850 | do this during our first pass. */ | |
851 | ||
852 | if (pass == 0 && optimize | |
853 | && noperands >= 3 | |
854 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
855 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
856 | && CONSTANT_P (recog_operand[1]) | |
857 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
858 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
859 | && GET_CODE (recog_operand[0]) == REG | |
860 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
861 | insn_operand_mode[insn_code_number][1])) | |
862 | { | |
863 | rtx previnsn = prev_real_insn (insn); | |
864 | rtx dest | |
865 | = gen_lowpart (insn_operand_mode[insn_code_number][1], | |
866 | recog_operand[0]); | |
867 | rtx newinsn | |
868 | = emit_insn_before (gen_move_insn (dest, | |
869 | recog_operand[1]), | |
870 | insn); | |
871 | ||
872 | /* If this insn was the start of a basic block, | |
873 | include the new insn in that block. | |
874 | We need not check for code_label here; | |
875 | while a basic block can start with a code_label, | |
876 | INSN could not be at the beginning of that block. */ | |
877 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
878 | { | |
879 | int b; | |
880 | for (b = 0; b < n_basic_blocks; b++) | |
881 | if (insn == basic_block_head[b]) | |
882 | basic_block_head[b] = newinsn; | |
883 | } | |
884 | ||
885 | /* This makes one more setting of new insns's dest. */ | |
886 | REG_N_SETS (REGNO (recog_operand[0]))++; | |
887 | ||
888 | *recog_operand_loc[1] = recog_operand[0]; | |
889 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
890 | if (recog_dup_num[i] == 1) | |
891 | *recog_dup_loc[i] = recog_operand[0]; | |
892 | ||
893 | return PREV_INSN (newinsn); | |
894 | } | |
895 | ||
896 | for (i = 0; i < noperands; i++) | |
897 | { | |
898 | constraints[i] | |
899 | = insn_operand_constraint[insn_code_number][i]; | |
900 | modes[i] = insn_operand_mode[insn_code_number][i]; | |
901 | } | |
902 | } | |
903 | ||
904 | /* If we get here, we are set up to record the costs of all the | |
905 | operands for this insn. Start by initializing the costs. | |
906 | Then handle any address registers. Finally record the desired | |
907 | classes for any pseudos, doing it twice if some pair of | |
908 | operands are commutative. */ | |
909 | ||
910 | for (i = 0; i < noperands; i++) | |
911 | { | |
912 | op_costs[i] = init_cost; | |
913 | ||
914 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
915 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
916 | ||
917 | if (GET_CODE (recog_operand[i]) == MEM) | |
918 | record_address_regs (XEXP (recog_operand[i], 0), | |
919 | BASE_REG_CLASS, loop_cost * 2); | |
920 | else if (constraints[i][0] == 'p') | |
921 | record_address_regs (recog_operand[i], | |
922 | BASE_REG_CLASS, loop_cost * 2); | |
923 | } | |
924 | ||
925 | /* Check for commutative in a separate loop so everything will | |
926 | have been initialized. We must do this even if one operand | |
927 | is a constant--see addsi3 in m68k.md. */ | |
928 | ||
929 | for (i = 0; i < noperands - 1; i++) | |
930 | if (constraints[i][0] == '%') | |
931 | { | |
932 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
933 | int j; | |
934 | ||
935 | /* Handle commutative operands by swapping the constraints. | |
936 | We assume the modes are the same. */ | |
937 | ||
938 | for (j = 0; j < noperands; j++) | |
939 | xconstraints[j] = constraints[j]; | |
940 | ||
941 | xconstraints[i] = constraints[i+1]; | |
942 | xconstraints[i+1] = constraints[i]; | |
943 | record_reg_classes (nalternatives, noperands, | |
944 | recog_operand, modes, xconstraints, | |
945 | insn); | |
946 | } | |
947 | ||
948 | record_reg_classes (nalternatives, noperands, recog_operand, | |
949 | modes, constraints, insn); | |
950 | ||
951 | /* Now add the cost for each operand to the total costs for | |
952 | its register. */ | |
953 | ||
954 | for (i = 0; i < noperands; i++) | |
955 | if (GET_CODE (recog_operand[i]) == REG | |
956 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
957 | { | |
958 | int regno = REGNO (recog_operand[i]); | |
959 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
960 | ||
961 | p->mem_cost += q->mem_cost * loop_cost; | |
962 | for (j = 0; j < N_REG_CLASSES; j++) | |
963 | p->cost[j] += q->cost[j] * loop_cost; | |
964 | } | |
965 | ||
966 | return insn; | |
967 | } | |
968 | ||
54dac99e RK |
969 | /* This is a pass of the compiler that scans all instructions |
970 | and calculates the preferred class for each pseudo-register. | |
971 | This information can be accessed later by calling `reg_preferred_class'. | |
972 | This pass comes just before local register allocation. */ | |
973 | ||
974 | void | |
975 | regclass (f, nregs) | |
976 | rtx f; | |
977 | int nregs; | |
978 | { | |
979 | #ifdef REGISTER_CONSTRAINTS | |
980 | register rtx insn; | |
61719ba7 | 981 | register int i; |
e4600702 | 982 | int pass; |
54dac99e RK |
983 | |
984 | init_recog (); | |
985 | ||
56a65848 | 986 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 RK |
987 | |
988 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
989 | ||
990 | in_inc_dec = (char *) alloca (nregs); | |
991 | ||
992 | /* Initialize information about which register classes can be used for | |
993 | pseudos that are auto-incremented or auto-decremented. It would | |
994 | seem better to put this in init_reg_sets, but we need to be able | |
995 | to allocate rtx, which we can't do that early. */ | |
996 | ||
997 | for (i = 0; i < N_REG_CLASSES; i++) | |
998 | { | |
38a448ca | 999 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 RK |
1000 | enum machine_mode m; |
1001 | ||
1002 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1003 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1004 | { | |
1005 | REGNO (r) = j; | |
1006 | ||
1007 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1008 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1009 | if (HARD_REGNO_MODE_OK (j, m)) |
1010 | { | |
1011 | PUT_MODE (r, m); | |
08d95f91 RK |
1012 | |
1013 | /* If a register is not directly suitable for an | |
1014 | auto-increment or decrement addressing mode and | |
1015 | requires secondary reloads, disallow its class from | |
1016 | being used in such addresses. */ | |
1017 | ||
1018 | if ((0 | |
041d7180 JL |
1019 | #ifdef SECONDARY_RELOAD_CLASS |
1020 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
1021 | != NO_REGS) | |
1022 | #else | |
533d0835 | 1023 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
1024 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1025 | != NO_REGS) | |
533d0835 RK |
1026 | #endif |
1027 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
1028 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1029 | != NO_REGS) | |
041d7180 | 1030 | #endif |
533d0835 | 1031 | #endif |
08d95f91 RK |
1032 | ) |
1033 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1034 | forbidden_inc_dec_class[i] = 1; |
1035 | } | |
1036 | } | |
1037 | } | |
1038 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1039 | ||
e4600702 RK |
1040 | /* Normally we scan the insns once and determine the best class to use for |
1041 | each register. However, if -fexpensive_optimizations are on, we do so | |
1042 | twice, the second time using the tentative best classes to guide the | |
1043 | selection. */ | |
54dac99e | 1044 | |
e4600702 RK |
1045 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1046 | { | |
1047 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 1048 | |
4c9a05bc | 1049 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 1050 | |
533d0835 RK |
1051 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1052 | bzero (in_inc_dec, nregs); | |
1053 | #endif | |
1054 | ||
e4600702 RK |
1055 | loop_depth = 0, loop_cost = 1; |
1056 | ||
1057 | /* Scan the instructions and record each time it would | |
1058 | save code to put a certain register in a certain class. */ | |
1059 | ||
1060 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 1061 | { |
61719ba7 | 1062 | insn = scan_one_insn (insn, pass); |
54dac99e | 1063 | } |
61719ba7 | 1064 | |
e4600702 RK |
1065 | /* Now for each register look at how desirable each class is |
1066 | and find which class is preferred. Store that in | |
1067 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
1068 | class any of whose registers is better than memory. */ | |
54dac99e | 1069 | |
e4600702 RK |
1070 | if (pass == 0) |
1071 | { | |
6feacd09 MM |
1072 | prefclass = prefclass_buffer; |
1073 | altclass = altclass_buffer; | |
e4600702 | 1074 | } |
54dac99e | 1075 | |
e4600702 | 1076 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1077 | { |
ca3c6eae | 1078 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1079 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1080 | /* This is an enum reg_class, but we call it an int | |
1081 | to save lots of casts. */ | |
1082 | register int class; | |
1083 | register struct costs *p = &costs[i]; | |
1084 | ||
1085 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 1086 | { |
533d0835 RK |
1087 | /* Ignore classes that are too small for this operand or |
1088 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 1089 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
1090 | > reg_class_size[class] |
1091 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1092 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1093 | #endif | |
1094 | ) | |
e4600702 RK |
1095 | ; |
1096 | else if (p->cost[class] < best_cost) | |
1097 | { | |
1098 | best_cost = p->cost[class]; | |
1099 | best = (enum reg_class) class; | |
1100 | } | |
1101 | else if (p->cost[class] == best_cost) | |
1102 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 1103 | } |
54dac99e | 1104 | |
e4600702 RK |
1105 | /* Record the alternate register class; i.e., a class for which |
1106 | every register in it is better than using memory. If adding a | |
1107 | class would make a smaller class (i.e., no union of just those | |
1108 | classes exists), skip that class. The major unions of classes | |
1109 | should be provided as a register class. Don't do this if we | |
1110 | will be doing it again later. */ | |
1111 | ||
1112 | if (pass == 1 || ! flag_expensive_optimizations) | |
1113 | for (class = 0; class < N_REG_CLASSES; class++) | |
1114 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1115 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1116 | > reg_class_size[(int) alt]) |
1117 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1118 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1119 | #endif | |
1120 | ) | |
e4600702 RK |
1121 | alt = reg_class_subunion[(int) alt][class]; |
1122 | ||
1123 | /* If we don't add any classes, nothing to try. */ | |
1124 | if (alt == best) | |
995d54dd | 1125 | alt = NO_REGS; |
e4600702 RK |
1126 | |
1127 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
1128 | prefclass[i] = (int) best; | |
1129 | altclass[i] = (int) alt; | |
1130 | } | |
54dac99e RK |
1131 | } |
1132 | #endif /* REGISTER_CONSTRAINTS */ | |
56a65848 DB |
1133 | |
1134 | free (costs); | |
54dac99e RK |
1135 | } |
1136 | \f | |
1137 | #ifdef REGISTER_CONSTRAINTS | |
1138 | ||
e4600702 RK |
1139 | /* Record the cost of using memory or registers of various classes for |
1140 | the operands in INSN. | |
54dac99e | 1141 | |
e4600702 | 1142 | N_ALTS is the number of alternatives. |
54dac99e | 1143 | |
e4600702 RK |
1144 | N_OPS is the number of operands. |
1145 | ||
1146 | OPS is an array of the operands. | |
1147 | ||
1148 | MODES are the modes of the operands, in case any are VOIDmode. | |
1149 | ||
1150 | CONSTRAINTS are the constraints to use for the operands. This array | |
1151 | is modified by this procedure. | |
1152 | ||
1153 | This procedure works alternative by alternative. For each alternative | |
1154 | we assume that we will be able to allocate all pseudos to their ideal | |
1155 | register class and calculate the cost of using that alternative. Then | |
1156 | we compute for each operand that is a pseudo-register, the cost of | |
1157 | having the pseudo allocated to each register class and using it in that | |
1158 | alternative. To this cost is added the cost of the alternative. | |
1159 | ||
1160 | The cost of each class for this insn is its lowest cost among all the | |
1161 | alternatives. */ | |
1162 | ||
1163 | static void | |
1164 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
1165 | int n_alts; | |
1166 | int n_ops; | |
1167 | rtx *ops; | |
1168 | enum machine_mode *modes; | |
54dac99e | 1169 | char **constraints; |
e4600702 | 1170 | rtx insn; |
54dac99e | 1171 | { |
e4600702 RK |
1172 | int alt; |
1173 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; | |
1174 | int i, j; | |
ec2d92af | 1175 | rtx set; |
e4600702 RK |
1176 | |
1177 | /* By default, each operand is an input operand. */ | |
1178 | ||
1179 | for (i = 0; i < n_ops; i++) | |
1180 | op_types[i] = OP_READ; | |
54dac99e | 1181 | |
e4600702 RK |
1182 | /* Process each alternative, each time minimizing an operand's cost with |
1183 | the cost for each operand in that alternative. */ | |
54dac99e | 1184 | |
e4600702 | 1185 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1186 | { |
e4600702 RK |
1187 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1188 | int alt_fail = 0; | |
1189 | int alt_cost = 0; | |
1190 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
1191 | int class; | |
54dac99e | 1192 | |
e4600702 RK |
1193 | for (i = 0; i < n_ops; i++) |
1194 | { | |
1195 | char *p = constraints[i]; | |
1196 | rtx op = ops[i]; | |
1197 | enum machine_mode mode = modes[i]; | |
1198 | int allows_mem = 0; | |
1199 | int win = 0; | |
e51712db | 1200 | unsigned char c; |
54dac99e | 1201 | |
e4600702 RK |
1202 | /* If this operand has no constraints at all, we can conclude |
1203 | nothing about it since anything is valid. */ | |
54dac99e | 1204 | |
e4600702 RK |
1205 | if (*p == 0) |
1206 | { | |
1207 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1208 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1209 | |
e4600702 RK |
1210 | continue; |
1211 | } | |
54dac99e | 1212 | |
347099d6 RS |
1213 | if (*p == '%') |
1214 | p++; | |
1215 | ||
e4600702 RK |
1216 | /* If this alternative is only relevant when this operand |
1217 | matches a previous operand, we do different things depending | |
1218 | on whether this operand is a pseudo-reg or not. */ | |
54dac99e | 1219 | |
e4600702 RK |
1220 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1221 | { | |
1222 | j = p[0] - '0'; | |
1223 | classes[i] = classes[j]; | |
1224 | ||
1225 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1226 | { | |
1227 | /* If this matches the other operand, we have no added | |
dc903608 | 1228 | cost and we win. */ |
e4600702 | 1229 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1230 | win = 1; |
e4600702 | 1231 | |
77e67eac RK |
1232 | /* If we can put the other operand into a register, add to |
1233 | the cost of this alternative the cost to copy this | |
1234 | operand to the register used for the other operand. */ | |
e4600702 | 1235 | |
dc903608 | 1236 | else if (classes[j] != NO_REGS) |
77e67eac | 1237 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1238 | } |
07d8ca2d RS |
1239 | else if (GET_CODE (ops[j]) != REG |
1240 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1241 | { | |
1242 | /* This op is a pseudo but the one it matches is not. */ | |
1243 | ||
1244 | /* If we can't put the other operand into a register, this | |
1245 | alternative can't be used. */ | |
1246 | ||
1247 | if (classes[j] == NO_REGS) | |
1248 | alt_fail = 1; | |
e4600702 | 1249 | |
07d8ca2d RS |
1250 | /* Otherwise, add to the cost of this alternative the cost |
1251 | to copy the other operand to the register used for this | |
1252 | operand. */ | |
1253 | ||
1254 | else | |
1255 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1256 | } | |
e4600702 RK |
1257 | else |
1258 | { | |
1259 | /* The costs of this operand are the same as that of the | |
1260 | other operand. However, if we cannot tie them, this | |
1261 | alternative needs to do a copy, which is one | |
1262 | instruction. */ | |
1263 | ||
1264 | this_op_costs[i] = this_op_costs[j]; | |
37747c82 RK |
1265 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1266 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1267 | alt_cost += 2; | |
e4600702 | 1268 | |
347099d6 | 1269 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1270 | for this operand, so skip to the end of the |
1271 | alternative (should be just one character). */ | |
1272 | while (*p && *p++ != ',') | |
1273 | ; | |
1274 | ||
1275 | constraints[i] = p; | |
347099d6 RS |
1276 | continue; |
1277 | } | |
e4600702 RK |
1278 | } |
1279 | ||
1280 | /* Scan all the constraint letters. See if the operand matches | |
1281 | any of the constraints. Collect the valid register classes | |
1282 | and see if this operand accepts memory. */ | |
1283 | ||
1284 | classes[i] = NO_REGS; | |
1285 | while (*p && (c = *p++) != ',') | |
1286 | switch (c) | |
1287 | { | |
1288 | case '=': | |
1289 | op_types[i] = OP_WRITE; | |
1290 | break; | |
1291 | ||
1292 | case '+': | |
1293 | op_types[i] = OP_READ_WRITE; | |
1294 | break; | |
1295 | ||
1296 | case '*': | |
1297 | /* Ignore the next letter for this pass. */ | |
1298 | p++; | |
1299 | break; | |
1300 | ||
812f2051 R |
1301 | case '?': |
1302 | alt_cost += 2; | |
e4600702 | 1303 | case '%': |
812f2051 | 1304 | case '!': case '#': |
e4600702 RK |
1305 | case '&': |
1306 | case '0': case '1': case '2': case '3': case '4': | |
1307 | case 'p': | |
1308 | break; | |
1309 | ||
1310 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1311 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 RK |
1312 | and non-offsettable addresses here. */ |
1313 | allows_mem = 1; | |
1314 | if (GET_CODE (op) == MEM) | |
1315 | win = 1; | |
1316 | break; | |
1317 | ||
1318 | case '<': | |
1319 | if (GET_CODE (op) == MEM | |
1320 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1321 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1322 | win = 1; | |
1323 | break; | |
1324 | ||
1325 | case '>': | |
1326 | if (GET_CODE (op) == MEM | |
1327 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1328 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1329 | win = 1; | |
1330 | break; | |
1331 | ||
1332 | case 'E': | |
7ac2547f | 1333 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1334 | /* Match any floating double constant, but only if |
1335 | we can examine the bits of it reliably. */ | |
1336 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1337 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1338 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1339 | break; | |
7ac2547f | 1340 | #endif |
e4600702 RK |
1341 | if (GET_CODE (op) == CONST_DOUBLE) |
1342 | win = 1; | |
1343 | break; | |
1344 | ||
1345 | case 'F': | |
1346 | if (GET_CODE (op) == CONST_DOUBLE) | |
1347 | win = 1; | |
1348 | break; | |
1349 | ||
1350 | case 'G': | |
1351 | case 'H': | |
1352 | if (GET_CODE (op) == CONST_DOUBLE | |
1353 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1354 | win = 1; | |
1355 | break; | |
1356 | ||
1357 | case 's': | |
1358 | if (GET_CODE (op) == CONST_INT | |
1359 | || (GET_CODE (op) == CONST_DOUBLE | |
1360 | && GET_MODE (op) == VOIDmode)) | |
1361 | break; | |
1362 | case 'i': | |
1363 | if (CONSTANT_P (op) | |
1364 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1365 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1366 | #endif | |
1367 | ) | |
1368 | win = 1; | |
1369 | break; | |
1370 | ||
1371 | case 'n': | |
1372 | if (GET_CODE (op) == CONST_INT | |
1373 | || (GET_CODE (op) == CONST_DOUBLE | |
1374 | && GET_MODE (op) == VOIDmode)) | |
1375 | win = 1; | |
1376 | break; | |
1377 | ||
1378 | case 'I': | |
1379 | case 'J': | |
1380 | case 'K': | |
1381 | case 'L': | |
1382 | case 'M': | |
1383 | case 'N': | |
1384 | case 'O': | |
1385 | case 'P': | |
1386 | if (GET_CODE (op) == CONST_INT | |
1387 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1388 | win = 1; | |
1389 | break; | |
1390 | ||
1391 | case 'X': | |
1392 | win = 1; | |
1393 | break; | |
54dac99e | 1394 | |
54dac99e | 1395 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1396 | case 'Q': |
1397 | case 'R': | |
1398 | case 'S': | |
1399 | case 'T': | |
1400 | case 'U': | |
1401 | if (EXTRA_CONSTRAINT (op, c)) | |
1402 | win = 1; | |
1403 | break; | |
1404 | #endif | |
1405 | ||
1406 | case 'g': | |
1407 | if (GET_CODE (op) == MEM | |
1408 | || (CONSTANT_P (op) | |
1409 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1410 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1411 | #endif |
e4600702 RK |
1412 | )) |
1413 | win = 1; | |
1414 | allows_mem = 1; | |
1415 | case 'r': | |
1416 | classes[i] | |
1417 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1418 | break; | |
1419 | ||
1420 | default: | |
1421 | classes[i] | |
1422 | = reg_class_subunion[(int) classes[i]] | |
1423 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1424 | } | |
1425 | ||
1426 | constraints[i] = p; | |
1427 | ||
1428 | /* How we account for this operand now depends on whether it is a | |
1429 | pseudo register or not. If it is, we first check if any | |
1430 | register classes are valid. If not, we ignore this alternative, | |
1431 | since we want to assume that all pseudos get allocated for | |
1432 | register preferencing. If some register class is valid, compute | |
1433 | the costs of moving the pseudo into that class. */ | |
1434 | ||
1435 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1436 | { |
e4600702 RK |
1437 | if (classes[i] == NO_REGS) |
1438 | alt_fail = 1; | |
1439 | else | |
1440 | { | |
1441 | struct costs *pp = &this_op_costs[i]; | |
1442 | ||
1443 | for (class = 0; class < N_REG_CLASSES; class++) | |
1444 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1445 | ||
1446 | /* If the alternative actually allows memory, make things | |
1447 | a bit cheaper since we won't need an extra insn to | |
1448 | load it. */ | |
1449 | ||
cbd5b9a2 KR |
1450 | pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) |
1451 | - allows_mem); | |
e4600702 RK |
1452 | |
1453 | /* If we have assigned a class to this register in our | |
1454 | first pass, add a cost to this alternative corresponding | |
1455 | to what we would add if this register were not in the | |
1456 | appropriate class. */ | |
1457 | ||
1458 | if (prefclass) | |
1459 | alt_cost | |
e51712db | 1460 | += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]]; |
e4600702 | 1461 | } |
4db18574 | 1462 | } |
54dac99e | 1463 | |
e4600702 RK |
1464 | /* Otherwise, if this alternative wins, either because we |
1465 | have already determined that or if we have a hard register of | |
1466 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1467 | |
e4600702 RK |
1468 | else if (win |
1469 | || (GET_CODE (op) == REG | |
6f654776 | 1470 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1471 | ; |
54dac99e | 1472 | |
e4600702 RK |
1473 | /* If registers are valid, the cost of this alternative includes |
1474 | copying the object to and/or from a register. */ | |
54dac99e | 1475 | |
e4600702 RK |
1476 | else if (classes[i] != NO_REGS) |
1477 | { | |
1478 | if (op_types[i] != OP_WRITE) | |
1479 | alt_cost += copy_cost (op, mode, classes[i], 1); | |
54dac99e | 1480 | |
e4600702 RK |
1481 | if (op_types[i] != OP_READ) |
1482 | alt_cost += copy_cost (op, mode, classes[i], 0); | |
1483 | } | |
54dac99e | 1484 | |
e4600702 RK |
1485 | /* The only other way this alternative can be used is if this is a |
1486 | constant that could be placed into memory. */ | |
1487 | ||
1488 | else if (CONSTANT_P (op) && allows_mem) | |
cbd5b9a2 | 1489 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1490 | else |
1491 | alt_fail = 1; | |
1492 | } | |
1493 | ||
1494 | if (alt_fail) | |
1495 | continue; | |
1496 | ||
1497 | /* Finally, update the costs with the information we've calculated | |
1498 | about this alternative. */ | |
1499 | ||
1500 | for (i = 0; i < n_ops; i++) | |
1501 | if (GET_CODE (ops[i]) == REG | |
1502 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1503 | { |
e4600702 RK |
1504 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1505 | int scale = 1 + (op_types[i] == OP_READ_WRITE); | |
54dac99e | 1506 | |
e4600702 RK |
1507 | pp->mem_cost = MIN (pp->mem_cost, |
1508 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1509 | |
e4600702 RK |
1510 | for (class = 0; class < N_REG_CLASSES; class++) |
1511 | pp->cost[class] = MIN (pp->cost[class], | |
1512 | (qq->cost[class] + alt_cost) * scale); | |
1513 | } | |
1514 | } | |
ec2d92af RK |
1515 | |
1516 | /* If this insn is a single set copying operand 1 to operand 0 | |
1517 | and one is a pseudo with the other a hard reg that is in its | |
1518 | own register class, set the cost of that register class to -1. */ | |
1519 | ||
1520 | if ((set = single_set (insn)) != 0 | |
1521 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1522 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1523 | for (i = 0; i <= 1; i++) | |
1524 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1525 | { | |
1526 | int regno = REGNO (ops[!i]); | |
1527 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1528 | int class; | |
4841ba4b | 1529 | int nr; |
ec2d92af RK |
1530 | |
1531 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 | |
e51712db | 1532 | && (reg_class_size[(unsigned char)prefclass[regno]] |
ec2d92af | 1533 | == CLASS_MAX_NREGS (prefclass[regno], mode))) |
e51712db | 1534 | op_costs[i].cost[(unsigned char)prefclass[regno]] = -1; |
ec2d92af RK |
1535 | else if (regno < FIRST_PSEUDO_REGISTER) |
1536 | for (class = 0; class < N_REG_CLASSES; class++) | |
1537 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1538 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1539 | { |
1540 | if (reg_class_size[class] == 1) | |
1541 | op_costs[i].cost[class] = -1; | |
1542 | else | |
1543 | { | |
1544 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1545 | { | |
1546 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1547 | break; | |
1548 | } | |
1549 | ||
1550 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1551 | op_costs[i].cost[class] = -1; | |
1552 | } | |
1553 | } | |
ec2d92af | 1554 | } |
54dac99e | 1555 | } |
e4600702 RK |
1556 | \f |
1557 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1558 | TO_P is zero) a register of class CLASS in mode MODE. | |
1559 | ||
1560 | X must not be a pseudo. */ | |
1561 | ||
1562 | static int | |
1563 | copy_cost (x, mode, class, to_p) | |
1564 | rtx x; | |
1565 | enum machine_mode mode; | |
1566 | enum reg_class class; | |
1567 | int to_p; | |
1568 | { | |
29a82058 | 1569 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1570 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1571 | #endif |
e4600702 RK |
1572 | |
1573 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1574 | assuming optimal allocation. */ | |
1575 | ||
1576 | if (GET_CODE (x) == SCRATCH) | |
1577 | return 0; | |
1578 | ||
1579 | /* Get the class we will actually use for a reload. */ | |
1580 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1581 | ||
1582 | #ifdef HAVE_SECONDARY_RELOADS | |
1583 | /* If we need a secondary reload (we assume here that we are using | |
1584 | the secondary reload as an intermediate, not a scratch register), the | |
1585 | cost is that to load the input into the intermediate register, then | |
1586 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1587 | ||
1588 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1589 | if (to_p == 1) | |
1590 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1591 | #endif | |
1592 | ||
dd9f0e8f | 1593 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1594 | if (! to_p) |
1595 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1596 | #endif | |
1597 | ||
1598 | if (secondary_class != NO_REGS) | |
1599 | return (move_cost[(int) secondary_class][(int) class] | |
1600 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1601 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1602 | |
1603 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1604 | cost to move between the register classes, and use 2 for everything | |
1605 | else (constants). */ | |
1606 | ||
1607 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1608 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1609 | |
e4600702 RK |
1610 | else if (GET_CODE (x) == REG) |
1611 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1612 | ||
1613 | else | |
1614 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1615 | return 2; | |
1616 | } | |
1617 | \f | |
54dac99e RK |
1618 | /* Record the pseudo registers we must reload into hard registers |
1619 | in a subexpression of a memory address, X. | |
e4600702 RK |
1620 | |
1621 | CLASS is the class that the register needs to be in and is either | |
1622 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1623 | ||
1624 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1625 | can represent half-cost adjustments). */ | |
54dac99e | 1626 | |
197d6480 | 1627 | static void |
e4600702 | 1628 | record_address_regs (x, class, scale) |
54dac99e | 1629 | rtx x; |
e4600702 RK |
1630 | enum reg_class class; |
1631 | int scale; | |
54dac99e RK |
1632 | { |
1633 | register enum rtx_code code = GET_CODE (x); | |
1634 | ||
1635 | switch (code) | |
1636 | { | |
1637 | case CONST_INT: | |
1638 | case CONST: | |
1639 | case CC0: | |
1640 | case PC: | |
1641 | case SYMBOL_REF: | |
1642 | case LABEL_REF: | |
1643 | return; | |
1644 | ||
1645 | case PLUS: | |
1646 | /* When we have an address that is a sum, | |
1647 | we must determine whether registers are "base" or "index" regs. | |
1648 | If there is a sum of two registers, we must choose one to be | |
1649 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1650 | to make a good choice most of the time. We only need to do this |
1651 | on machines that can have two registers in an address and where | |
1652 | the base and index register classes are different. | |
1653 | ||
1654 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1655 | that seems bogus since it should only be set when we are sure | |
1656 | the register is being used as a pointer. */ | |
1657 | ||
54dac99e RK |
1658 | { |
1659 | rtx arg0 = XEXP (x, 0); | |
1660 | rtx arg1 = XEXP (x, 1); | |
1661 | register enum rtx_code code0 = GET_CODE (arg0); | |
1662 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1663 | |
1664 | /* Look inside subregs. */ | |
e4600702 | 1665 | if (code0 == SUBREG) |
54dac99e | 1666 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1667 | if (code1 == SUBREG) |
54dac99e RK |
1668 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1669 | ||
e4600702 RK |
1670 | /* If this machine only allows one register per address, it must |
1671 | be in the first operand. */ | |
1672 | ||
1673 | if (MAX_REGS_PER_ADDRESS == 1) | |
1674 | record_address_regs (arg0, class, scale); | |
1675 | ||
1676 | /* If index and base registers are the same on this machine, just | |
1677 | record registers in any non-constant operands. We assume here, | |
1678 | as well as in the tests below, that all addresses are in | |
1679 | canonical form. */ | |
1680 | ||
1681 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1682 | { |
e4600702 RK |
1683 | record_address_regs (arg0, class, scale); |
1684 | if (! CONSTANT_P (arg1)) | |
1685 | record_address_regs (arg1, class, scale); | |
54dac99e | 1686 | } |
e4600702 RK |
1687 | |
1688 | /* If the second operand is a constant integer, it doesn't change | |
1689 | what class the first operand must be. */ | |
1690 | ||
1691 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1692 | record_address_regs (arg0, class, scale); | |
1693 | ||
1694 | /* If the second operand is a symbolic constant, the first operand | |
1695 | must be an index register. */ | |
1696 | ||
1697 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1698 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1699 | ||
956d6950 JL |
1700 | /* If both operands are registers but one is already a hard register |
1701 | of index or base class, give the other the class that the hard | |
1702 | register is not. */ | |
1703 | ||
3f9e9508 | 1704 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1705 | else if (code0 == REG && code1 == REG |
1706 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1707 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1708 | record_address_regs (arg1, | |
1709 | REG_OK_FOR_BASE_P (arg0) | |
1710 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1711 | scale); | |
1712 | else if (code0 == REG && code1 == REG | |
1713 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1714 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1715 | record_address_regs (arg0, | |
1716 | REG_OK_FOR_BASE_P (arg1) | |
1717 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1718 | scale); | |
3f9e9508 | 1719 | #endif |
956d6950 | 1720 | |
e9a25f70 JL |
1721 | /* If one operand is known to be a pointer, it must be the base |
1722 | with the other operand the index. Likewise if the other operand | |
1723 | is a MULT. */ | |
f22376c7 | 1724 | |
e9a25f70 JL |
1725 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1726 | || code1 == MULT) | |
f22376c7 CI |
1727 | { |
1728 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1729 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1730 | } | |
e9a25f70 JL |
1731 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1732 | || code0 == MULT) | |
f22376c7 CI |
1733 | { |
1734 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1735 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1736 | } | |
1737 | ||
e9a25f70 | 1738 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1739 | or index register. This case should be rare. */ |
1740 | ||
e9a25f70 | 1741 | else |
54dac99e | 1742 | { |
e4600702 RK |
1743 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1744 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1745 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1746 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1747 | } |
54dac99e RK |
1748 | } |
1749 | break; | |
1750 | ||
1751 | case POST_INC: | |
1752 | case PRE_INC: | |
1753 | case POST_DEC: | |
1754 | case PRE_DEC: | |
1755 | /* Double the importance of a pseudo register that is incremented | |
1756 | or decremented, since it would take two extra insns | |
533d0835 RK |
1757 | if it ends up in the wrong place. If the operand is a pseudo, |
1758 | show it is being used in an INC_DEC context. */ | |
1759 | ||
1760 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1761 | if (GET_CODE (XEXP (x, 0)) == REG | |
1762 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1763 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1764 | #endif | |
e4600702 RK |
1765 | |
1766 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1767 | break; |
1768 | ||
1769 | case REG: | |
1770 | { | |
e4600702 RK |
1771 | register struct costs *pp = &costs[REGNO (x)]; |
1772 | register int i; | |
54dac99e | 1773 | |
cbd5b9a2 | 1774 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1775 | |
e4600702 RK |
1776 | for (i = 0; i < N_REG_CLASSES; i++) |
1777 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1778 | } |
1779 | break; | |
1780 | ||
1781 | default: | |
1782 | { | |
1783 | register char *fmt = GET_RTX_FORMAT (code); | |
1784 | register int i; | |
1785 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1786 | if (fmt[i] == 'e') | |
e4600702 | 1787 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1788 | } |
1789 | } | |
1790 | } | |
08d95f91 RK |
1791 | \f |
1792 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1793 | ||
1794 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1795 | to an object of MODE. */ | |
1796 | ||
1d300e19 | 1797 | static int |
08d95f91 RK |
1798 | auto_inc_dec_reg_p (reg, mode) |
1799 | rtx reg; | |
1800 | enum machine_mode mode; | |
1801 | { | |
1802 | #ifdef HAVE_POST_INCREMENT | |
38a448ca | 1803 | if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) |
08d95f91 RK |
1804 | return 1; |
1805 | #endif | |
1806 | ||
1807 | #ifdef HAVE_POST_DECREMENT | |
38a448ca | 1808 | if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) |
08d95f91 RK |
1809 | return 1; |
1810 | #endif | |
1811 | ||
1812 | #ifdef HAVE_PRE_INCREMENT | |
38a448ca | 1813 | if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) |
08d95f91 RK |
1814 | return 1; |
1815 | #endif | |
1816 | ||
1817 | #ifdef HAVE_PRE_DECREMENT | |
38a448ca | 1818 | if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) |
08d95f91 RK |
1819 | return 1; |
1820 | #endif | |
1821 | ||
1822 | return 0; | |
1823 | } | |
1824 | #endif | |
1825 | ||
54dac99e | 1826 | #endif /* REGISTER_CONSTRAINTS */ |
b1f21e0a MM |
1827 | \f |
1828 | /* Allocate enough space to hold NUM_REGS registers for the tables used for | |
1829 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1830 | NEW_P is non zero, initialize all of the registers, otherwise only |
1831 | initialize the new registers allocated. The same table is kept from | |
1832 | function to function, only reallocating it when we need more room. If | |
1833 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1834 | |
1835 | void | |
39379e67 | 1836 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 1837 | size_t num_regs; |
b1f21e0a | 1838 | int new_p; |
39379e67 | 1839 | int renumber_p; |
b1f21e0a | 1840 | { |
6feacd09 | 1841 | static size_t regno_allocated = 0; |
39379e67 | 1842 | static short *renumber = (short *)0; |
b1f21e0a | 1843 | int i; |
6feacd09 MM |
1844 | size_t size_info; |
1845 | size_t size_renumber; | |
1846 | size_t min = (new_p) ? 0 : reg_n_max; | |
1847 | struct reg_info_data *reg_data; | |
1848 | struct reg_info_data *reg_next; | |
39379e67 MM |
1849 | |
1850 | /* Free up all storage allocated */ | |
1851 | if (num_regs < 0) | |
1852 | { | |
1853 | if (reg_n_info) | |
1854 | { | |
6feacd09 MM |
1855 | VARRAY_FREE (reg_n_info); |
1856 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
1857 | { | |
1858 | reg_next = reg_data->next; | |
1859 | free ((char *)reg_data); | |
1860 | } | |
1861 | ||
1862 | free (prefclass_buffer); | |
1863 | free (altclass_buffer); | |
1864 | prefclass_buffer = (char *)0; | |
1865 | altclass_buffer = (char *)0; | |
1866 | reg_info_head = (struct reg_info_data *)0; | |
39379e67 MM |
1867 | renumber = (short *)0; |
1868 | } | |
1869 | regno_allocated = 0; | |
a494747c | 1870 | reg_n_max = 0; |
39379e67 MM |
1871 | return; |
1872 | } | |
1873 | ||
b1f21e0a MM |
1874 | if (num_regs > regno_allocated) |
1875 | { | |
6feacd09 MM |
1876 | size_t old_allocated = regno_allocated; |
1877 | ||
b1f21e0a | 1878 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
1879 | size_renumber = regno_allocated * sizeof (short); |
1880 | ||
1881 | if (!reg_n_info) | |
1882 | { | |
6feacd09 | 1883 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 1884 | renumber = (short *) xmalloc (size_renumber); |
6feacd09 MM |
1885 | prefclass_buffer = (char *) xmalloc (regno_allocated); |
1886 | altclass_buffer = (char *) xmalloc (regno_allocated); | |
39379e67 MM |
1887 | } |
1888 | ||
1889 | else | |
1890 | { | |
6feacd09 MM |
1891 | VARRAY_GROW (reg_n_info, regno_allocated); |
1892 | ||
1893 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
1894 | { | |
1895 | free ((char *)renumber); | |
1896 | free ((char *)prefclass_buffer); | |
1897 | free ((char *)altclass_buffer); | |
1898 | renumber = (short *) xmalloc (size_renumber); | |
1899 | prefclass_buffer = (char *) xmalloc (regno_allocated); | |
1900 | altclass_buffer = (char *) xmalloc (regno_allocated); | |
1901 | } | |
1902 | ||
1903 | else | |
1904 | { | |
1905 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
1906 | prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer, | |
1907 | regno_allocated); | |
1908 | ||
1909 | altclass_buffer = (char *) xrealloc ((char *)altclass_buffer, | |
1910 | regno_allocated); | |
1911 | } | |
39379e67 | 1912 | } |
6feacd09 MM |
1913 | |
1914 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
1915 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
1916 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
1917 | reg_data->min_index = old_allocated; | |
1918 | reg_data->max_index = regno_allocated - 1; | |
1919 | reg_data->next = reg_info_head; | |
1920 | reg_info_head = reg_data; | |
b1f21e0a MM |
1921 | } |
1922 | ||
6feacd09 | 1923 | reg_n_max = num_regs; |
b1f21e0a MM |
1924 | if (min < num_regs) |
1925 | { | |
6feacd09 MM |
1926 | /* Loop through each of the segments allocated for the actual |
1927 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
1928 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
39379e67 | 1929 | { |
6feacd09 MM |
1930 | size_t min_index = reg_data->min_index; |
1931 | size_t max_index = reg_data->max_index; | |
1932 | ||
1933 | reg_next = reg_data->next; | |
29f63881 | 1934 | if (min <= max_index) |
6feacd09 | 1935 | { |
eafdfea8 | 1936 | size_t max = max_index; |
29f63881 RH |
1937 | size_t local_min = min - min_index; |
1938 | if (min < min_index) | |
1939 | local_min = 0; | |
6feacd09 MM |
1940 | if (!reg_data->used_p) /* page just allocated with calloc */ |
1941 | reg_data->used_p = 1; /* no need to zero */ | |
1942 | else | |
29f63881 RH |
1943 | bzero ((char *) ®_data->data[local_min], |
1944 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
6feacd09 | 1945 | |
29f63881 | 1946 | for (i = min_index+local_min; i <= max; i++) |
6feacd09 MM |
1947 | { |
1948 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
1949 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
1950 | renumber[i] = -1; | |
1951 | prefclass_buffer[i] = (char) NO_REGS; | |
1952 | altclass_buffer[i] = (char) NO_REGS; | |
1953 | } | |
1954 | } | |
39379e67 | 1955 | } |
b1f21e0a MM |
1956 | } |
1957 | ||
6feacd09 MM |
1958 | /* If {pref,alt}class have already been allocated, update the pointers to |
1959 | the newly realloced ones. */ | |
1960 | if (prefclass) | |
1961 | { | |
1962 | prefclass = prefclass_buffer; | |
1963 | altclass = altclass_buffer; | |
1964 | } | |
1965 | ||
39379e67 MM |
1966 | if (renumber_p) |
1967 | reg_renumber = renumber; | |
1968 | ||
73b76448 RK |
1969 | /* Tell the regset code about the new number of registers */ |
1970 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
1971 | } |
1972 | ||
54dac99e RK |
1973 | \f |
1974 | /* This is the `regscan' pass of the compiler, run just before cse | |
1975 | and again just before loop. | |
1976 | ||
1977 | It finds the first and last use of each pseudo-register | |
1978 | and records them in the vectors regno_first_uid, regno_last_uid | |
1979 | and counts the number of sets in the vector reg_n_sets. | |
1980 | ||
1981 | REPEAT is nonzero the second time this is called. */ | |
1982 | ||
54dac99e | 1983 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 1984 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
1985 | and we want this to remain correct for all the remaining passes. */ |
1986 | ||
1987 | int max_parallel; | |
1988 | ||
54dac99e RK |
1989 | void |
1990 | reg_scan (f, nregs, repeat) | |
1991 | rtx f; | |
1992 | int nregs; | |
1993 | int repeat; | |
1994 | { | |
1995 | register rtx insn; | |
1996 | ||
39379e67 | 1997 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
1998 | max_parallel = 3; |
1999 | ||
2000 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2001 | if (GET_CODE (insn) == INSN | |
2002 | || GET_CODE (insn) == CALL_INSN | |
2003 | || GET_CODE (insn) == JUMP_INSN) | |
2004 | { | |
2005 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2006 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2007 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2008 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2009 | |
2010 | if (REG_NOTES (insn)) | |
f903b91f DM |
2011 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2012 | } | |
2013 | } | |
2014 | ||
2015 | /* Update 'regscan' information by looking at the insns | |
2016 | from FIRST to LAST. Some new REGs have been created, | |
2017 | and any REG with number greater than OLD_MAX_REGNO is | |
2018 | such a REG. We only update information for those. */ | |
2019 | ||
2020 | void | |
2021 | reg_scan_update(first, last, old_max_regno) | |
2022 | rtx first; | |
2023 | rtx last; | |
2024 | int old_max_regno; | |
2025 | { | |
2026 | register rtx insn; | |
2027 | ||
2028 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2029 | ||
2030 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2031 | if (GET_CODE (insn) == INSN | |
2032 | || GET_CODE (insn) == CALL_INSN | |
2033 | || GET_CODE (insn) == JUMP_INSN) | |
2034 | { | |
2035 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2036 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2037 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2038 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2039 | ||
2040 | if (REG_NOTES (insn)) | |
2041 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2042 | } |
2043 | } | |
2044 | ||
1ebecb64 | 2045 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2046 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2047 | We should only record information for REGs with numbers | |
2048 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2049 | |
08d95f91 | 2050 | static void |
f903b91f | 2051 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2052 | rtx x; |
be8dcd74 | 2053 | rtx insn; |
1ebecb64 | 2054 | int note_flag; |
f903b91f | 2055 | int min_regno; |
54dac99e | 2056 | { |
fa23c636 | 2057 | register enum rtx_code code; |
54dac99e | 2058 | register rtx dest; |
be8dcd74 | 2059 | register rtx note; |
54dac99e | 2060 | |
fa23c636 | 2061 | code = GET_CODE (x); |
54dac99e RK |
2062 | switch (code) |
2063 | { | |
2064 | case CONST_INT: | |
2065 | case CONST: | |
2066 | case CONST_DOUBLE: | |
2067 | case CC0: | |
2068 | case PC: | |
2069 | case SYMBOL_REF: | |
2070 | case LABEL_REF: | |
2071 | case ADDR_VEC: | |
2072 | case ADDR_DIFF_VEC: | |
2073 | return; | |
2074 | ||
2075 | case REG: | |
2076 | { | |
2077 | register int regno = REGNO (x); | |
2078 | ||
f903b91f DM |
2079 | if (regno >= min_regno) |
2080 | { | |
2081 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2082 | if (!note_flag) | |
2083 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2084 | if (REGNO_FIRST_UID (regno) == 0) | |
2085 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
2086 | } | |
54dac99e RK |
2087 | } |
2088 | break; | |
2089 | ||
01565a55 | 2090 | case EXPR_LIST: |
7b18c3db | 2091 | if (XEXP (x, 0)) |
f903b91f | 2092 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2093 | if (XEXP (x, 1)) |
f903b91f | 2094 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2095 | break; |
2096 | ||
2097 | case INSN_LIST: | |
2098 | if (XEXP (x, 1)) | |
f903b91f | 2099 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2100 | break; |
2101 | ||
54dac99e RK |
2102 | case SET: |
2103 | /* Count a set of the destination if it is a register. */ | |
2104 | for (dest = SET_DEST (x); | |
2105 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2106 | || GET_CODE (dest) == ZERO_EXTEND; | |
2107 | dest = XEXP (dest, 0)) | |
2108 | ; | |
2109 | ||
f903b91f DM |
2110 | if (GET_CODE (dest) == REG |
2111 | && REGNO (dest) >= min_regno) | |
b1f21e0a | 2112 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 2113 | |
be8dcd74 RK |
2114 | /* If this is setting a pseudo from another pseudo or the sum of a |
2115 | pseudo and a constant integer and the other pseudo is known to be | |
2116 | a pointer, set the destination to be a pointer as well. | |
2117 | ||
2118 | Likewise if it is setting the destination from an address or from a | |
2119 | value equivalent to an address or to the sum of an address and | |
2120 | something else. | |
2121 | ||
2122 | But don't do any of this if the pseudo corresponds to a user | |
2123 | variable since it should have already been set as a pointer based | |
2124 | on the type. */ | |
2125 | ||
2126 | if (GET_CODE (SET_DEST (x)) == REG | |
2127 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2128 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2129 | /* If the destination pseudo is set more than once, then other |
2130 | sets might not be to a pointer value (consider access to a | |
2131 | union in two threads of control in the presense of global | |
2132 | optimizations). So only set REGNO_POINTER_FLAG on the destination | |
2133 | pseudo if this is the only set of that pseudo. */ | |
2134 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 RK |
2135 | && ! REG_USERVAR_P (SET_DEST (x)) |
2136 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
2137 | && ((GET_CODE (SET_SRC (x)) == REG | |
2138 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
2139 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2140 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2141 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2142 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
2143 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
2144 | || GET_CODE (SET_SRC (x)) == CONST | |
2145 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2146 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2147 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2148 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2149 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2150 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2151 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2152 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2153 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2154 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2155 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2156 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2157 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2158 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2159 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
2160 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
2161 | ||
0f41302f | 2162 | /* ... fall through ... */ |
54dac99e RK |
2163 | |
2164 | default: | |
2165 | { | |
2166 | register char *fmt = GET_RTX_FORMAT (code); | |
2167 | register int i; | |
2168 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2169 | { | |
2170 | if (fmt[i] == 'e') | |
f903b91f | 2171 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2172 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2173 | { | |
2174 | register int j; | |
2175 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f903b91f | 2176 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2177 | } |
2178 | } | |
2179 | } | |
2180 | } | |
2181 | } | |
2182 | \f | |
2183 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2184 | is also in C2. */ | |
2185 | ||
2186 | int | |
2187 | reg_class_subset_p (c1, c2) | |
2188 | register enum reg_class c1; | |
2189 | register enum reg_class c2; | |
2190 | { | |
2191 | if (c1 == c2) return 1; | |
2192 | ||
2193 | if (c2 == ALL_REGS) | |
2194 | win: | |
2195 | return 1; | |
2196 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
2197 | reg_class_contents[(int)c2], | |
2198 | win); | |
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2203 | ||
2204 | int | |
2205 | reg_classes_intersect_p (c1, c2) | |
2206 | register enum reg_class c1; | |
2207 | register enum reg_class c2; | |
2208 | { | |
2209 | #ifdef HARD_REG_SET | |
2210 | register | |
2211 | #endif | |
2212 | HARD_REG_SET c; | |
2213 | ||
2214 | if (c1 == c2) return 1; | |
2215 | ||
2216 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2217 | return 1; | |
2218 | ||
2219 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2220 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2221 | ||
2222 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2223 | return 1; | |
2224 | ||
2225 | lose: | |
2226 | return 0; | |
2227 | } | |
2228 | ||
73b76448 RK |
2229 | /* Release any memory allocated by register sets. */ |
2230 | ||
2231 | void | |
2232 | regset_release_memory () | |
2233 | { | |
2234 | if (basic_block_live_at_start) | |
2235 | { | |
2236 | free_regset_vector (basic_block_live_at_start, n_basic_blocks); | |
2237 | basic_block_live_at_start = 0; | |
2238 | } | |
2239 | ||
2240 | FREE_REG_SET (regs_live_at_setjmp); | |
2241 | bitmap_release_memory (); | |
2242 | } |