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Commit | Line | Data |
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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
58b23af8 | 3 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
54dac99e | 4 | |
1322177d | 5 | This file is part of GCC. |
54dac99e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
54dac99e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
54dac99e RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
54dac99e RK |
21 | |
22 | ||
23 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
24 | It also defines some tables of information about the hardware registers | |
25 | and a function init_reg_sets to initialize the tables. */ | |
26 | ||
27 | #include "config.h" | |
670ee920 | 28 | #include "system.h" |
4977bab6 ZW |
29 | #include "coretypes.h" |
30 | #include "tm.h" | |
cff9f8d5 | 31 | #include "hard-reg-set.h" |
54dac99e | 32 | #include "rtl.h" |
0829d244 | 33 | #include "expr.h" |
6baf1cc8 | 34 | #include "tm_p.h" |
54dac99e RK |
35 | #include "flags.h" |
36 | #include "basic-block.h" | |
37 | #include "regs.h" | |
49ad7cfa | 38 | #include "function.h" |
54dac99e RK |
39 | #include "insn-config.h" |
40 | #include "recog.h" | |
e4600702 RK |
41 | #include "reload.h" |
42 | #include "real.h" | |
10f0ad3d | 43 | #include "toplev.h" |
d6f4ec51 | 44 | #include "output.h" |
8b0212ca | 45 | #include "ggc.h" |
54dac99e RK |
46 | |
47 | #ifndef REGISTER_MOVE_COST | |
e56b4594 | 48 | #define REGISTER_MOVE_COST(m, x, y) 2 |
54dac99e RK |
49 | #endif |
50 | ||
13536812 KG |
51 | static void init_reg_sets_1 PARAMS ((void)); |
52 | static void init_reg_modes PARAMS ((void)); | |
24deb20a | 53 | |
533d0835 RK |
54 | /* If we have auto-increment or auto-decrement and we can have secondary |
55 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 56 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
57 | |
58 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 59 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
60 | #define FORBIDDEN_INC_DEC_CLASSES |
61 | #endif | |
62 | #endif | |
54dac99e RK |
63 | \f |
64 | /* Register tables used by many passes. */ | |
65 | ||
66 | /* Indexed by hard register number, contains 1 for registers | |
67 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
68 | These are the registers that cannot be used to allocate | |
252f342a | 69 | a pseudo reg for general use. */ |
54dac99e RK |
70 | |
71 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
72 | ||
73 | /* Same info as a HARD_REG_SET. */ | |
74 | ||
75 | HARD_REG_SET fixed_reg_set; | |
76 | ||
77 | /* Data for initializing the above. */ | |
78 | ||
8b60264b | 79 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
54dac99e RK |
80 | |
81 | /* Indexed by hard register number, contains 1 for registers | |
82 | that are fixed use or are clobbered by function calls. | |
83 | These are the registers that cannot be used to allocate | |
252f342a MH |
84 | a pseudo reg whose life crosses calls unless we are able |
85 | to save/restore them across the calls. */ | |
54dac99e RK |
86 | |
87 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
88 | ||
89 | /* Same info as a HARD_REG_SET. */ | |
90 | ||
91 | HARD_REG_SET call_used_reg_set; | |
92 | ||
6cad67d2 JL |
93 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
94 | HARD_REG_SET losing_caller_save_reg_set; | |
95 | ||
54dac99e RK |
96 | /* Data for initializing the above. */ |
97 | ||
8b60264b | 98 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
fc1296b7 AM |
99 | |
100 | /* This is much like call_used_regs, except it doesn't have to | |
101 | be a superset of FIXED_REGISTERS. This vector indicates | |
a6a2274a | 102 | what is really call clobbered, and is used when defining |
fc1296b7 AM |
103 | regs_invalidated_by_call. */ |
104 | ||
fc1296b7 | 105 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa | 106 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
fc1296b7 | 107 | #endif |
a6a2274a | 108 | |
54dac99e | 109 | /* Indexed by hard register number, contains 1 for registers that are |
252f342a MH |
110 | fixed use or call used registers that cannot hold quantities across |
111 | calls even if we are willing to save and restore them. call fixed | |
112 | registers are a subset of call used registers. */ | |
54dac99e RK |
113 | |
114 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
115 | ||
116 | /* The same info as a HARD_REG_SET. */ | |
117 | ||
118 | HARD_REG_SET call_fixed_reg_set; | |
119 | ||
120 | /* Number of non-fixed registers. */ | |
121 | ||
122 | int n_non_fixed_regs; | |
123 | ||
124 | /* Indexed by hard register number, contains 1 for registers | |
125 | that are being used for global register decls. | |
126 | These must be exempt from ordinary flow analysis | |
127 | and are also considered fixed. */ | |
128 | ||
129 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
4e2db584 RH |
130 | |
131 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
132 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
133 | for someone's bright idea to have call_used_regs strictly include | |
134 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
135 | that are actually preserved. We know for sure that those associated | |
136 | with the local stack frame are safe, but scant others. */ | |
137 | ||
138 | HARD_REG_SET regs_invalidated_by_call; | |
139 | ||
54dac99e RK |
140 | /* Table of register numbers in the order in which to try to use them. */ |
141 | #ifdef REG_ALLOC_ORDER | |
142 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
143 | |
144 | /* The inverse of reg_alloc_order. */ | |
145 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
146 | #endif |
147 | ||
148 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
149 | ||
2e0e2b76 CH |
150 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
151 | ||
089e575b RS |
152 | /* The same information, but as an array of unsigned ints. We copy from |
153 | these unsigned ints to the table above. We do this so the tm.h files | |
d4845339 RH |
154 | do not have to be aware of the wordsize for machines with <= 64 regs. |
155 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
2e0e2b76 CH |
156 | |
157 | #define N_REG_INTS \ | |
d4845339 | 158 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
2e0e2b76 | 159 | |
a6a2274a | 160 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 161 | = REG_CLASS_CONTENTS; |
54dac99e RK |
162 | |
163 | /* For each reg class, number of regs it contains. */ | |
164 | ||
770ae6cc | 165 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
166 | |
167 | /* For each reg class, table listing all the containing classes. */ | |
168 | ||
169 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
170 | ||
171 | /* For each reg class, table listing all the classes contained in it. */ | |
172 | ||
173 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
174 | ||
175 | /* For each pair of reg classes, | |
176 | a largest reg class contained in their union. */ | |
177 | ||
178 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
179 | ||
180 | /* For each pair of reg classes, | |
181 | the smallest reg class containing their union. */ | |
182 | ||
183 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
184 | ||
fbd40359 ZW |
185 | /* Array containing all of the register names. Unless |
186 | DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ | |
d05c8ee7 | 187 | |
fbd40359 | 188 | #ifdef DEBUG_REGISTER_NAMES |
e087aeb2 | 189 | const char * reg_names[] = REGISTER_NAMES; |
fbd40359 | 190 | #endif |
d05c8ee7 | 191 | |
ca4aac00 DE |
192 | /* For each hard register, the widest mode object that it can contain. |
193 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
194 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
195 | register. */ | |
196 | ||
197 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
198 | ||
6df26b8f JH |
199 | /* 1 if class does contain register of given mode. */ |
200 | ||
201 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
202 | ||
e4600702 RK |
203 | /* Maximum cost of moving from a register in one class to a register in |
204 | another class. Based on REGISTER_MOVE_COST. */ | |
205 | ||
e56b4594 | 206 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
207 | |
208 | /* Similar, but here we don't have to move if the first index is a subset | |
209 | of the second so in that case the cost is zero. */ | |
210 | ||
e56b4594 | 211 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
212 | |
213 | /* Similar, but here we don't have to move if the first index is a superset | |
214 | of the second so in that case the cost is zero. */ | |
215 | ||
e56b4594 | 216 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 217 | |
533d0835 RK |
218 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
219 | ||
220 | /* These are the classes that regs which are auto-incremented or decremented | |
221 | cannot be put in. */ | |
222 | ||
223 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
224 | ||
40f03658 | 225 | /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec |
533d0835 RK |
226 | context. */ |
227 | ||
228 | static char *in_inc_dec; | |
229 | ||
5fcb671c | 230 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 231 | |
cff9f8d5 AH |
232 | #ifdef CANNOT_CHANGE_MODE_CLASS |
233 | /* All registers that have been subreged. Indexed by mode, where each | |
234 | entry is a regset of registers. */ | |
235 | regset_head subregs_of_mode [NUM_MACHINE_MODES]; | |
236 | #endif | |
e79f71f7 | 237 | |
473fe49b KR |
238 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
239 | ||
e2500fed | 240 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
473fe49b | 241 | |
6feacd09 MM |
242 | /* Linked list of reg_info structures allocated for reg_n_info array. |
243 | Grouping all of the allocated structures together in one lump | |
244 | means only one call to bzero to clear them, rather than n smaller | |
245 | calls. */ | |
246 | struct reg_info_data { | |
247 | struct reg_info_data *next; /* next set of reg_info structures */ | |
248 | size_t min_index; /* minimum index # */ | |
249 | size_t max_index; /* maximum index # */ | |
40f03658 | 250 | char used_p; /* nonzero if this has been used previously */ |
6feacd09 MM |
251 | reg_info data[1]; /* beginning of the reg_info data */ |
252 | }; | |
253 | ||
254 | static struct reg_info_data *reg_info_head; | |
255 | ||
c07c7c9d | 256 | /* No more global register variables may be declared; true once |
dc297297 | 257 | regclass has been initialized. */ |
6c85df69 AH |
258 | |
259 | static int no_global_reg_vars = 0; | |
260 | ||
6feacd09 | 261 | |
54dac99e RK |
262 | /* Function called only once to initialize the above data on reg usage. |
263 | Once this is done, various switches may override. */ | |
264 | ||
265 | void | |
266 | init_reg_sets () | |
267 | { | |
b3694847 | 268 | int i, j; |
54dac99e | 269 | |
2e0e2b76 CH |
270 | /* First copy the register information from the initial int form into |
271 | the regsets. */ | |
272 | ||
273 | for (i = 0; i < N_REG_CLASSES; i++) | |
274 | { | |
275 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
276 | ||
b85946fc | 277 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
2e0e2b76 | 278 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
b85946fc RH |
279 | if (int_reg_class_contents[i][j / 32] |
280 | & ((unsigned) 1 << (j % 32))) | |
2e0e2b76 CH |
281 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
282 | } | |
283 | ||
4e135bdd KG |
284 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
285 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 286 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 287 | |
3eae4643 | 288 | /* Do any additional initialization regsets may need. */ |
910bc42d | 289 | INIT_ONCE_REG_SET (); |
f5d8c9f4 BS |
290 | |
291 | #ifdef REG_ALLOC_ORDER | |
292 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
293 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
294 | #endif | |
910bc42d R |
295 | } |
296 | ||
297 | /* After switches have been processed, which perhaps alter | |
298 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
299 | ||
300 | static void | |
301 | init_reg_sets_1 () | |
302 | { | |
b3694847 SS |
303 | unsigned int i, j; |
304 | unsigned int /* enum machine_mode */ m; | |
6836e024 | 305 | char allocatable_regs_of_mode [MAX_MACHINE_MODE]; |
910bc42d R |
306 | |
307 | /* This macro allows the fixed or call-used registers | |
308 | and the register classes to depend on target flags. */ | |
309 | ||
310 | #ifdef CONDITIONAL_REGISTER_USAGE | |
311 | CONDITIONAL_REGISTER_USAGE; | |
312 | #endif | |
313 | ||
54dac99e RK |
314 | /* Compute number of hard regs in each class. */ |
315 | ||
961192e1 | 316 | memset ((char *) reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
317 | for (i = 0; i < N_REG_CLASSES; i++) |
318 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
319 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
320 | reg_class_size[i]++; | |
321 | ||
322 | /* Initialize the table of subunions. | |
323 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
324 | that is contained in the union of classes I and J. */ | |
325 | ||
326 | for (i = 0; i < N_REG_CLASSES; i++) | |
327 | { | |
328 | for (j = 0; j < N_REG_CLASSES; j++) | |
329 | { | |
330 | #ifdef HARD_REG_SET | |
331 | register /* Declare it register if it's a scalar. */ | |
332 | #endif | |
333 | HARD_REG_SET c; | |
b3694847 | 334 | int k; |
54dac99e RK |
335 | |
336 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
337 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
338 | for (k = 0; k < N_REG_CLASSES; k++) | |
339 | { | |
340 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
341 | subclass1); | |
342 | continue; | |
343 | ||
344 | subclass1: | |
345 | /* keep the largest subclass */ /* SPEE 900308 */ | |
346 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
347 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
348 | subclass2); | |
349 | reg_class_subunion[i][j] = (enum reg_class) k; | |
350 | subclass2: | |
351 | ; | |
352 | } | |
353 | } | |
354 | } | |
355 | ||
356 | /* Initialize the table of superunions. | |
357 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
358 | containing the union of classes I and J. */ | |
359 | ||
360 | for (i = 0; i < N_REG_CLASSES; i++) | |
361 | { | |
362 | for (j = 0; j < N_REG_CLASSES; j++) | |
363 | { | |
364 | #ifdef HARD_REG_SET | |
365 | register /* Declare it register if it's a scalar. */ | |
366 | #endif | |
367 | HARD_REG_SET c; | |
b3694847 | 368 | int k; |
54dac99e RK |
369 | |
370 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
371 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
372 | for (k = 0; k < N_REG_CLASSES; k++) | |
373 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
374 | ||
375 | superclass: | |
376 | reg_class_superunion[i][j] = (enum reg_class) k; | |
377 | } | |
378 | } | |
379 | ||
380 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
381 | First clear the whole table, then add the elements as they are found. */ | |
382 | ||
383 | for (i = 0; i < N_REG_CLASSES; i++) | |
384 | { | |
385 | for (j = 0; j < N_REG_CLASSES; j++) | |
386 | { | |
387 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
388 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
389 | } | |
390 | } | |
391 | ||
392 | for (i = 0; i < N_REG_CLASSES; i++) | |
393 | { | |
394 | if (i == (int) NO_REGS) | |
395 | continue; | |
396 | ||
397 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
398 | { | |
399 | enum reg_class *p; | |
400 | ||
401 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
402 | subclass); | |
403 | continue; | |
404 | subclass: | |
405 | /* Reg class I is a subclass of J. | |
406 | Add J to the table of superclasses of I. */ | |
407 | p = ®_class_superclasses[i][0]; | |
408 | while (*p != LIM_REG_CLASSES) p++; | |
409 | *p = (enum reg_class) j; | |
410 | /* Add I to the table of superclasses of J. */ | |
411 | p = ®_class_subclasses[j][0]; | |
412 | while (*p != LIM_REG_CLASSES) p++; | |
413 | *p = (enum reg_class) i; | |
414 | } | |
415 | } | |
e4600702 | 416 | |
54dac99e RK |
417 | /* Initialize "constant" tables. */ |
418 | ||
419 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
420 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
421 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
4e2db584 | 422 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
54dac99e | 423 | |
4e135bdd | 424 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e RK |
425 | |
426 | n_non_fixed_regs = 0; | |
427 | ||
428 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
429 | { | |
54dac99e RK |
430 | if (fixed_regs[i]) |
431 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
432 | else | |
433 | n_non_fixed_regs++; | |
434 | ||
435 | if (call_used_regs[i]) | |
436 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
437 | if (call_fixed_regs[i]) | |
438 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
439 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
440 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
4e2db584 RH |
441 | |
442 | /* There are a couple of fixed registers that we know are safe to | |
443 | exclude from being clobbered by calls: | |
444 | ||
445 | The frame pointer is always preserved across calls. The arg pointer | |
446 | is if it is fixed. The stack pointer usually is, unless | |
447 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
448 | If we are generating PIC code, the PIC offset table register is | |
449 | preserved across calls, though the target can override that. */ | |
a6a2274a | 450 | |
4e2db584 RH |
451 | if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) |
452 | ; | |
453 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
454 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
455 | ; | |
456 | #endif | |
457 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
458 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
459 | ; | |
460 | #endif | |
461 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
fc555370 | 462 | else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
4e2db584 RH |
463 | ; |
464 | #endif | |
d3259baa | 465 | else if (0 |
6ca3c22f | 466 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa RH |
467 | || call_really_used_regs[i] |
468 | #else | |
469 | || call_used_regs[i] | |
470 | #endif | |
471 | || global_regs[i]) | |
4e2db584 | 472 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
54dac99e | 473 | } |
4e2db584 | 474 | |
6836e024 JH |
475 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
476 | memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); | |
dbbbbf3b | 477 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 | 478 | for (i = 0; i < N_REG_CLASSES; i++) |
f7043461 | 479 | if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
6df26b8f JH |
480 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
481 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
482 | && HARD_REGNO_MODE_OK (j, m)) | |
483 | { | |
484 | contains_reg_of_mode [i][m] = 1; | |
485 | allocatable_regs_of_mode [m] = 1; | |
486 | break; | |
487 | } | |
acbce667 KR |
488 | |
489 | /* Initialize the move cost table. Find every subset of each class | |
490 | and take the maximum cost of moving any subset to any other. */ | |
491 | ||
dbbbbf3b | 492 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 JH |
493 | if (allocatable_regs_of_mode [m]) |
494 | { | |
495 | for (i = 0; i < N_REG_CLASSES; i++) | |
496 | if (contains_reg_of_mode [i][m]) | |
497 | for (j = 0; j < N_REG_CLASSES; j++) | |
498 | { | |
499 | int cost; | |
500 | enum reg_class *p1, *p2; | |
501 | ||
502 | if (!contains_reg_of_mode [j][m]) | |
503 | { | |
504 | move_cost[m][i][j] = 65536; | |
505 | may_move_in_cost[m][i][j] = 65536; | |
506 | may_move_out_cost[m][i][j] = 65536; | |
507 | } | |
508 | else | |
509 | { | |
26a952a8 | 510 | cost = REGISTER_MOVE_COST (m, i, j); |
6836e024 JH |
511 | |
512 | for (p2 = ®_class_subclasses[j][0]; | |
513 | *p2 != LIM_REG_CLASSES; | |
514 | p2++) | |
515 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
516 | cost = MAX (cost, move_cost [m][i][*p2]); | |
517 | ||
518 | for (p1 = ®_class_subclasses[i][0]; | |
519 | *p1 != LIM_REG_CLASSES; | |
520 | p1++) | |
521 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
522 | cost = MAX (cost, move_cost [m][*p1][j]); | |
523 | ||
524 | move_cost[m][i][j] = cost; | |
525 | ||
526 | if (reg_class_subset_p (i, j)) | |
527 | may_move_in_cost[m][i][j] = 0; | |
528 | else | |
529 | may_move_in_cost[m][i][j] = cost; | |
530 | ||
531 | if (reg_class_subset_p (j, i)) | |
532 | may_move_out_cost[m][i][j] = 0; | |
533 | else | |
534 | may_move_out_cost[m][i][j] = cost; | |
535 | } | |
536 | } | |
1464632b | 537 | else |
6836e024 JH |
538 | for (j = 0; j < N_REG_CLASSES; j++) |
539 | { | |
540 | move_cost[m][i][j] = 65536; | |
541 | may_move_in_cost[m][i][j] = 65536; | |
542 | may_move_out_cost[m][i][j] = 65536; | |
543 | } | |
544 | } | |
c27c5281 DE |
545 | } |
546 | ||
547 | /* Compute the table of register modes. | |
548 | These values are used to record death information for individual registers | |
549 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 550 | |
c27c5281 DE |
551 | static void |
552 | init_reg_modes () | |
553 | { | |
b3694847 | 554 | int i; |
ca4aac00 DE |
555 | |
556 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
557 | { |
558 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
559 | ||
066c2fea | 560 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
561 | ??? One situation in which we need to do this is on the mips where |
562 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
563 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 564 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 565 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 566 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 567 | } |
ca4aac00 DE |
568 | } |
569 | ||
c27c5281 DE |
570 | /* Finish initializing the register sets and |
571 | initialize the register modes. */ | |
572 | ||
573 | void | |
574 | init_regs () | |
575 | { | |
576 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
577 | until after register usage was specified. */ | |
b93a436e | 578 | init_reg_sets_1 (); |
c27c5281 DE |
579 | |
580 | init_reg_modes (); | |
6cde4876 JL |
581 | } |
582 | ||
583 | /* Initialize some fake stack-frame MEM references for use in | |
584 | memory_move_secondary_cost. */ | |
473fe49b | 585 | |
6cde4876 JL |
586 | void |
587 | init_fake_stack_mems () | |
588 | { | |
473fe49b KR |
589 | #ifdef HAVE_SECONDARY_RELOADS |
590 | { | |
473fe49b | 591 | int i; |
d067e2aa | 592 | |
473fe49b | 593 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 594 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
595 | } |
596 | #endif | |
c27c5281 DE |
597 | } |
598 | ||
cbd5b9a2 | 599 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 600 | |
cbd5b9a2 KR |
601 | /* Compute extra cost of moving registers to/from memory due to reloads. |
602 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 603 | |
cbd5b9a2 KR |
604 | int |
605 | memory_move_secondary_cost (mode, class, in) | |
606 | enum machine_mode mode; | |
607 | enum reg_class class; | |
608 | int in; | |
609 | { | |
610 | enum reg_class altclass; | |
611 | int partial_cost = 0; | |
cbd5b9a2 | 612 | /* We need a memory reference to feed to SECONDARY... macros. */ |
dc297297 | 613 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
272df862 KG |
614 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
615 | ||
cbd5b9a2 KR |
616 | |
617 | if (in) | |
473fe49b | 618 | { |
321c0828 | 619 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 620 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 621 | #else |
473fe49b | 622 | altclass = NO_REGS; |
321c0828 | 623 | #endif |
473fe49b | 624 | } |
cbd5b9a2 | 625 | else |
473fe49b | 626 | { |
321c0828 | 627 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 628 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 629 | #else |
473fe49b | 630 | altclass = NO_REGS; |
321c0828 | 631 | #endif |
473fe49b KR |
632 | } |
633 | ||
cbd5b9a2 KR |
634 | if (altclass == NO_REGS) |
635 | return 0; | |
636 | ||
637 | if (in) | |
e56b4594 | 638 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 639 | else |
e56b4594 | 640 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
641 | |
642 | if (class == altclass) | |
643 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
644 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
645 | here in that case. | |
646 | ||
647 | I'm tempted to put in an abort here, but returning this will | |
648 | probably only give poor estimates, which is what we would've | |
649 | had before this code anyways. */ | |
650 | return partial_cost; | |
651 | ||
652 | /* Check if the secondary reload register will also need a | |
653 | secondary reload. */ | |
654 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
655 | } | |
656 | #endif | |
657 | ||
ca4aac00 DE |
658 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
659 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
660 | ||
661 | enum machine_mode | |
662 | choose_hard_reg_mode (regno, nregs) | |
770ae6cc RK |
663 | unsigned int regno ATTRIBUTE_UNUSED; |
664 | unsigned int nregs; | |
ca4aac00 | 665 | { |
dbbbbf3b | 666 | unsigned int /* enum machine_mode */ m; |
ca4aac00 DE |
667 | enum machine_mode found_mode = VOIDmode, mode; |
668 | ||
669 | /* We first look for the largest integer mode that can be validly | |
670 | held in REGNO. If none, we look for the largest floating-point mode. | |
671 | If we still didn't find a valid mode, try CCmode. */ | |
672 | ||
673 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
674 | mode != VOIDmode; | |
675 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 676 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
ca4aac00 DE |
677 | && HARD_REGNO_MODE_OK (regno, mode)) |
678 | found_mode = mode; | |
679 | ||
680 | if (found_mode != VOIDmode) | |
681 | return found_mode; | |
682 | ||
683 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
684 | mode != VOIDmode; | |
685 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 686 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
ca4aac00 DE |
687 | && HARD_REGNO_MODE_OK (regno, mode)) |
688 | found_mode = mode; | |
689 | ||
690 | if (found_mode != VOIDmode) | |
691 | return found_mode; | |
692 | ||
78b583fe AH |
693 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
694 | mode != VOIDmode; | |
695 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 696 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
78b583fe AH |
697 | && HARD_REGNO_MODE_OK (regno, mode)) |
698 | found_mode = mode; | |
699 | ||
700 | if (found_mode != VOIDmode) | |
701 | return found_mode; | |
702 | ||
703 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
704 | mode != VOIDmode; | |
705 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 706 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
78b583fe AH |
707 | && HARD_REGNO_MODE_OK (regno, mode)) |
708 | found_mode = mode; | |
709 | ||
710 | if (found_mode != VOIDmode) | |
711 | return found_mode; | |
712 | ||
0548a9df | 713 | /* Iterate over all of the CCmodes. */ |
dbbbbf3b JDA |
714 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
715 | { | |
716 | mode = (enum machine_mode) m; | |
f7043461 | 717 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
dbbbbf3b JDA |
718 | && HARD_REGNO_MODE_OK (regno, mode)) |
719 | return mode; | |
720 | } | |
ca4aac00 DE |
721 | |
722 | /* We can't find a mode valid for this register. */ | |
723 | return VOIDmode; | |
54dac99e RK |
724 | } |
725 | ||
726 | /* Specify the usage characteristics of the register named NAME. | |
727 | It should be a fixed register if FIXED and a | |
728 | call-used register if CALL_USED. */ | |
729 | ||
730 | void | |
731 | fix_register (name, fixed, call_used) | |
ec0ce6e2 | 732 | const char *name; |
54dac99e RK |
733 | int fixed, call_used; |
734 | { | |
735 | int i; | |
736 | ||
737 | /* Decode the name and update the primary form of | |
738 | the register info. */ | |
739 | ||
e5c90c23 TW |
740 | if ((i = decode_reg_name (name)) >= 0) |
741 | { | |
cb2fdc84 GRK |
742 | if ((i == STACK_POINTER_REGNUM |
743 | #ifdef HARD_FRAME_POINTER_REGNUM | |
744 | || i == HARD_FRAME_POINTER_REGNUM | |
745 | #else | |
746 | || i == FRAME_POINTER_REGNUM | |
747 | #endif | |
748 | ) | |
749 | && (fixed == 0 || call_used == 0)) | |
750 | { | |
6f7d635c | 751 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
752 | { "call-saved", "call-used" }, |
753 | { "no-such-option", "fixed" }}; | |
a6a2274a KH |
754 | |
755 | error ("can't use '%s' as a %s register", name, | |
cb2fdc84 GRK |
756 | what_option[fixed][call_used]); |
757 | } | |
758 | else | |
759 | { | |
760 | fixed_regs[i] = fixed; | |
761 | call_used_regs[i] = call_used; | |
ec523c2f | 762 | #ifdef CALL_REALLY_USED_REGISTERS |
fc1296b7 AM |
763 | if (fixed == 0) |
764 | call_really_used_regs[i] = call_used; | |
d3259baa | 765 | #endif |
cb2fdc84 | 766 | } |
e5c90c23 TW |
767 | } |
768 | else | |
54dac99e RK |
769 | { |
770 | warning ("unknown register name: %s", name); | |
54dac99e RK |
771 | } |
772 | } | |
614f68e2 RK |
773 | |
774 | /* Mark register number I as global. */ | |
775 | ||
776 | void | |
777 | globalize_reg (i) | |
778 | int i; | |
779 | { | |
c07c7c9d | 780 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
781 | error ("global register variable follows a function definition"); |
782 | ||
614f68e2 RK |
783 | if (global_regs[i]) |
784 | { | |
785 | warning ("register used for two global register variables"); | |
786 | return; | |
787 | } | |
788 | ||
789 | if (call_used_regs[i] && ! fixed_regs[i]) | |
790 | warning ("call-clobbered register used for global register variable"); | |
791 | ||
792 | global_regs[i] = 1; | |
793 | ||
794 | /* If already fixed, nothing else to do. */ | |
795 | if (fixed_regs[i]) | |
796 | return; | |
797 | ||
798 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
799 | n_non_fixed_regs--; | |
800 | ||
801 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
802 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
803 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
caecc099 | 804 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
614f68e2 | 805 | } |
54dac99e RK |
806 | \f |
807 | /* Now the data and code for the `regclass' pass, which happens | |
808 | just before local-alloc. */ | |
809 | ||
e4600702 RK |
810 | /* The `costs' struct records the cost of using a hard register of each class |
811 | and of using memory for each pseudo. We use this data to set up | |
812 | register class preferences. */ | |
54dac99e | 813 | |
e4600702 | 814 | struct costs |
54dac99e | 815 | { |
e4600702 RK |
816 | int cost[N_REG_CLASSES]; |
817 | int mem_cost; | |
54dac99e RK |
818 | }; |
819 | ||
d55d8fc7 | 820 | /* Structure used to record preferences of given pseudo. */ |
9ffc5a70 JH |
821 | struct reg_pref |
822 | { | |
823 | /* (enum reg_class) prefclass is the preferred class. */ | |
824 | char prefclass; | |
825 | ||
826 | /* altclass is a register class that we should use for allocating | |
827 | pseudo if no register in the preferred class is available. | |
828 | If no register in this class is available, memory is preferred. | |
829 | ||
830 | It might appear to be more general to have a bitmask of classes here, | |
831 | but since it is recommended that there be a class corresponding to the | |
832 | union of most major pair of classes, that generality is not required. */ | |
833 | char altclass; | |
834 | }; | |
835 | ||
e4600702 RK |
836 | /* Record the cost of each class for each pseudo. */ |
837 | ||
838 | static struct costs *costs; | |
839 | ||
61719ba7 BS |
840 | /* Initialized once, and used to initialize cost values for each insn. */ |
841 | ||
842 | static struct costs init_cost; | |
843 | ||
d55d8fc7 | 844 | /* Record preferences of each pseudo. |
54dac99e RK |
845 | This is available after `regclass' is run. */ |
846 | ||
9ffc5a70 | 847 | static struct reg_pref *reg_pref; |
54d23420 | 848 | |
dc297297 | 849 | /* Allocated buffers for reg_pref. */ |
54dac99e | 850 | |
9ffc5a70 | 851 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 852 | |
9401afe3 | 853 | /* Frequency of executions of current insn. */ |
54d23420 | 854 | |
9401afe3 | 855 | static int frequency; |
54d23420 | 856 | |
13536812 KG |
857 | static rtx scan_one_insn PARAMS ((rtx, int)); |
858 | static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); | |
859 | static void dump_regclass PARAMS ((FILE *)); | |
860 | static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, | |
e79f71f7 | 861 | const char **, rtx, |
f741a71c | 862 | struct costs *, struct reg_pref *)); |
a6a2274a | 863 | static int copy_cost PARAMS ((rtx, enum machine_mode, |
08d95f91 | 864 | enum reg_class, int)); |
13536812 | 865 | static void record_address_regs PARAMS ((rtx, enum reg_class, int)); |
1d300e19 | 866 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
13536812 | 867 | static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); |
1d300e19 | 868 | #endif |
770ae6cc | 869 | static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); |
54dac99e RK |
870 | |
871 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
872 | This function is sometimes called before the info has been computed. | |
873 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
874 | ||
875 | enum reg_class | |
876 | reg_preferred_class (regno) | |
877 | int regno; | |
878 | { | |
9ffc5a70 | 879 | if (reg_pref == 0) |
54dac99e | 880 | return GENERAL_REGS; |
9ffc5a70 | 881 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
882 | } |
883 | ||
e4600702 RK |
884 | enum reg_class |
885 | reg_alternate_class (regno) | |
b729186a | 886 | int regno; |
54dac99e | 887 | { |
9ffc5a70 | 888 | if (reg_pref == 0) |
e4600702 RK |
889 | return ALL_REGS; |
890 | ||
9ffc5a70 | 891 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
892 | } |
893 | ||
61719ba7 | 894 | /* Initialize some global data for this pass. */ |
54dac99e RK |
895 | |
896 | void | |
897 | regclass_init () | |
898 | { | |
61719ba7 BS |
899 | int i; |
900 | ||
901 | init_cost.mem_cost = 10000; | |
902 | for (i = 0; i < N_REG_CLASSES; i++) | |
903 | init_cost.cost[i] = 10000; | |
904 | ||
905 | /* This prevents dump_flow_info from losing if called | |
906 | before regclass is run. */ | |
9ffc5a70 | 907 | reg_pref = NULL; |
6c85df69 | 908 | |
dc297297 | 909 | /* No more global register variables may be declared. */ |
6c85df69 | 910 | no_global_reg_vars = 1; |
54dac99e | 911 | } |
246fd41f JH |
912 | \f |
913 | /* Dump register costs. */ | |
915b80ed | 914 | static void |
246fd41f JH |
915 | dump_regclass (dump) |
916 | FILE *dump; | |
917 | { | |
918 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
919 | int i; | |
920 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
921 | { | |
dbbbbf3b | 922 | int /* enum reg_class */ class; |
246fd41f JH |
923 | if (REG_N_REFS (i)) |
924 | { | |
f741a71c | 925 | fprintf (dump, " Register %i costs:", i); |
dbbbbf3b JDA |
926 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
927 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
6df26b8f | 928 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
dbbbbf3b JDA |
929 | && (!in_inc_dec[i] |
930 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
6df26b8f | 931 | #endif |
cff9f8d5 AH |
932 | #ifdef CANNOT_CHANGE_MODE_CLASS |
933 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
934 | PSEUDO_REGNO_MODE (i)) | |
6df26b8f JH |
935 | #endif |
936 | ) | |
dbbbbf3b JDA |
937 | fprintf (dump, " %s:%i", reg_class_names[class], |
938 | costs[i].cost[(enum reg_class) class]); | |
f741a71c | 939 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
940 | } |
941 | } | |
942 | } | |
f741a71c JH |
943 | \f |
944 | ||
945 | /* Calculate the costs of insn operands. */ | |
946 | ||
947 | static void | |
948 | record_operand_costs (insn, op_costs, reg_pref) | |
949 | rtx insn; | |
950 | struct costs *op_costs; | |
951 | struct reg_pref *reg_pref; | |
952 | { | |
953 | const char *constraints[MAX_RECOG_OPERANDS]; | |
954 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
955 | int i; |
956 | ||
957 | for (i = 0; i < recog_data.n_operands; i++) | |
958 | { | |
959 | constraints[i] = recog_data.constraints[i]; | |
960 | modes[i] = recog_data.operand_mode[i]; | |
961 | } | |
f741a71c JH |
962 | |
963 | /* If we get here, we are set up to record the costs of all the | |
964 | operands for this insn. Start by initializing the costs. | |
965 | Then handle any address registers. Finally record the desired | |
966 | classes for any pseudos, doing it twice if some pair of | |
967 | operands are commutative. */ | |
a6a2274a | 968 | |
f741a71c JH |
969 | for (i = 0; i < recog_data.n_operands; i++) |
970 | { | |
971 | op_costs[i] = init_cost; | |
972 | ||
973 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
cff9f8d5 | 974 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
f741a71c JH |
975 | |
976 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
977 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
3dcc68a4 | 978 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
ccfc6cc8 | 979 | else if (constraints[i][0] == 'p' |
97488870 | 980 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
f741a71c | 981 | record_address_regs (recog_data.operand[i], |
3dcc68a4 | 982 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
f741a71c JH |
983 | } |
984 | ||
985 | /* Check for commutative in a separate loop so everything will | |
986 | have been initialized. We must do this even if one operand | |
987 | is a constant--see addsi3 in m68k.md. */ | |
988 | ||
989 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
990 | if (constraints[i][0] == '%') | |
991 | { | |
992 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
993 | int j; | |
246fd41f | 994 | |
f741a71c JH |
995 | /* Handle commutative operands by swapping the constraints. |
996 | We assume the modes are the same. */ | |
997 | ||
998 | for (j = 0; j < recog_data.n_operands; j++) | |
999 | xconstraints[j] = constraints[j]; | |
1000 | ||
1001 | xconstraints[i] = constraints[i+1]; | |
1002 | xconstraints[i+1] = constraints[i]; | |
1003 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1004 | recog_data.operand, modes, |
f741a71c JH |
1005 | xconstraints, insn, op_costs, reg_pref); |
1006 | } | |
1007 | ||
1008 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1009 | recog_data.operand, modes, |
f741a71c JH |
1010 | constraints, insn, op_costs, reg_pref); |
1011 | } | |
54dac99e | 1012 | \f |
61719ba7 BS |
1013 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1014 | time it would save code to put a certain register in a certain class. | |
1015 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1016 | once. | |
1017 | Return the last insn processed, so that the scan can be continued from | |
1018 | there. */ | |
1019 | ||
1020 | static rtx | |
1021 | scan_one_insn (insn, pass) | |
1022 | rtx insn; | |
1023 | int pass; | |
1024 | { | |
1025 | enum rtx_code code = GET_CODE (insn); | |
1026 | enum rtx_code pat_code; | |
0eadeb15 | 1027 | rtx set, note; |
61719ba7 | 1028 | int i, j; |
f741a71c | 1029 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 1030 | |
61719ba7 BS |
1031 | if (GET_RTX_CLASS (code) != 'i') |
1032 | return insn; | |
1033 | ||
1034 | pat_code = GET_CODE (PATTERN (insn)); | |
1035 | if (pat_code == USE | |
1036 | || pat_code == CLOBBER | |
1037 | || pat_code == ASM_INPUT | |
1038 | || pat_code == ADDR_VEC | |
1039 | || pat_code == ADDR_DIFF_VEC) | |
1040 | return insn; | |
1041 | ||
0eadeb15 BS |
1042 | set = single_set (insn); |
1043 | extract_insn (insn); | |
1044 | ||
0eadeb15 BS |
1045 | /* If this insn loads a parameter from its stack slot, then |
1046 | it represents a savings, rather than a cost, if the | |
1047 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 1048 | |
0eadeb15 BS |
1049 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
1050 | && GET_CODE (SET_SRC (set)) == MEM | |
1051 | && (note = find_reg_note (insn, REG_EQUIV, | |
1052 | NULL_RTX)) != 0 | |
1053 | && GET_CODE (XEXP (note, 0)) == MEM) | |
1054 | { | |
1055 | costs[REGNO (SET_DEST (set))].mem_cost | |
1056 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1057 | GENERAL_REGS, 1) | |
9401afe3 | 1058 | * frequency); |
0eadeb15 | 1059 | record_address_regs (XEXP (SET_SRC (set), 0), |
3dcc68a4 | 1060 | MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); |
0eadeb15 BS |
1061 | return insn; |
1062 | } | |
61719ba7 | 1063 | |
0eadeb15 BS |
1064 | /* Improve handling of two-address insns such as |
1065 | (set X (ashift CONST Y)) where CONST must be made to | |
1066 | match X. Change it into two insns: (set X CONST) | |
1067 | (set X (ashift X Y)). If we left this for reloading, it | |
1068 | would probably get three insns because X and Y might go | |
1069 | in the same place. This prevents X and Y from receiving | |
1070 | the same hard reg. | |
1071 | ||
1072 | We can only do this if the modes of operands 0 and 1 | |
1073 | (which might not be the same) are tieable and we only need | |
1074 | do this during our first pass. */ | |
1075 | ||
1076 | if (pass == 0 && optimize | |
1ccbefce RH |
1077 | && recog_data.n_operands >= 3 |
1078 | && recog_data.constraints[1][0] == '0' | |
1079 | && recog_data.constraints[1][1] == 0 | |
1080 | && CONSTANT_P (recog_data.operand[1]) | |
1081 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1082 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
1083 | && GET_CODE (recog_data.operand[0]) == REG | |
1084 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
1085 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
1086 | { |
1087 | rtx previnsn = prev_real_insn (insn); | |
1088 | rtx dest | |
1ccbefce RH |
1089 | = gen_lowpart (recog_data.operand_mode[1], |
1090 | recog_data.operand[0]); | |
0eadeb15 | 1091 | rtx newinsn |
1ccbefce | 1092 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 1093 | |
0eadeb15 BS |
1094 | /* If this insn was the start of a basic block, |
1095 | include the new insn in that block. | |
1096 | We need not check for code_label here; | |
1097 | while a basic block can start with a code_label, | |
1098 | INSN could not be at the beginning of that block. */ | |
1099 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 1100 | { |
e0082a72 ZD |
1101 | basic_block b; |
1102 | FOR_EACH_BB (b) | |
1103 | if (insn == b->head) | |
1104 | b->head = newinsn; | |
61719ba7 BS |
1105 | } |
1106 | ||
0eadeb15 | 1107 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1108 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d3c7d45e | 1109 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1110 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
61719ba7 | 1111 | |
1ccbefce | 1112 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d3c7d45e | 1113 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1114 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
1ccbefce RH |
1115 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1116 | if (recog_data.dup_num[i] == 1) | |
d3c7d45e AO |
1117 | { |
1118 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1119 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
9401afe3 | 1120 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d3c7d45e | 1121 | } |
61719ba7 | 1122 | |
0eadeb15 | 1123 | return PREV_INSN (newinsn); |
61719ba7 BS |
1124 | } |
1125 | ||
4963c995 | 1126 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1127 | |
1128 | /* Now add the cost for each operand to the total costs for | |
1129 | its register. */ | |
1130 | ||
1ccbefce RH |
1131 | for (i = 0; i < recog_data.n_operands; i++) |
1132 | if (GET_CODE (recog_data.operand[i]) == REG | |
1133 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 1134 | { |
1ccbefce | 1135 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1136 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1137 | ||
9401afe3 | 1138 | p->mem_cost += q->mem_cost * frequency; |
61719ba7 | 1139 | for (j = 0; j < N_REG_CLASSES; j++) |
9401afe3 | 1140 | p->cost[j] += q->cost[j] * frequency; |
61719ba7 BS |
1141 | } |
1142 | ||
1143 | return insn; | |
1144 | } | |
1145 | ||
54dac99e RK |
1146 | /* This is a pass of the compiler that scans all instructions |
1147 | and calculates the preferred class for each pseudo-register. | |
1148 | This information can be accessed later by calling `reg_preferred_class'. | |
1149 | This pass comes just before local register allocation. */ | |
1150 | ||
1151 | void | |
246fd41f | 1152 | regclass (f, nregs, dump) |
54dac99e RK |
1153 | rtx f; |
1154 | int nregs; | |
246fd41f | 1155 | FILE *dump; |
54dac99e | 1156 | { |
b3694847 SS |
1157 | rtx insn; |
1158 | int i; | |
e4600702 | 1159 | int pass; |
54dac99e RK |
1160 | |
1161 | init_recog (); | |
1162 | ||
56a65848 | 1163 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 RK |
1164 | |
1165 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1166 | ||
4da896b2 | 1167 | in_inc_dec = (char *) xmalloc (nregs); |
533d0835 RK |
1168 | |
1169 | /* Initialize information about which register classes can be used for | |
1170 | pseudos that are auto-incremented or auto-decremented. It would | |
1171 | seem better to put this in init_reg_sets, but we need to be able | |
1172 | to allocate rtx, which we can't do that early. */ | |
1173 | ||
1174 | for (i = 0; i < N_REG_CLASSES; i++) | |
1175 | { | |
38a448ca | 1176 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 | 1177 | enum machine_mode m; |
b3694847 | 1178 | int j; |
533d0835 RK |
1179 | |
1180 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1181 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1182 | { | |
1183 | REGNO (r) = j; | |
1184 | ||
1185 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1186 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1187 | if (HARD_REGNO_MODE_OK (j, m)) |
1188 | { | |
1189 | PUT_MODE (r, m); | |
08d95f91 RK |
1190 | |
1191 | /* If a register is not directly suitable for an | |
1192 | auto-increment or decrement addressing mode and | |
1193 | requires secondary reloads, disallow its class from | |
1194 | being used in such addresses. */ | |
1195 | ||
1196 | if ((0 | |
041d7180 | 1197 | #ifdef SECONDARY_RELOAD_CLASS |
3dcc68a4 | 1198 | || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
041d7180 JL |
1199 | != NO_REGS) |
1200 | #else | |
533d0835 | 1201 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
3dcc68a4 | 1202 | || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1203 | != NO_REGS) |
533d0835 RK |
1204 | #endif |
1205 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
3dcc68a4 | 1206 | || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1207 | != NO_REGS) |
041d7180 | 1208 | #endif |
533d0835 | 1209 | #endif |
08d95f91 RK |
1210 | ) |
1211 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1212 | forbidden_inc_dec_class[i] = 1; |
1213 | } | |
1214 | } | |
1215 | } | |
1216 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1217 | ||
e4600702 RK |
1218 | /* Normally we scan the insns once and determine the best class to use for |
1219 | each register. However, if -fexpensive_optimizations are on, we do so | |
1220 | twice, the second time using the tentative best classes to guide the | |
1221 | selection. */ | |
54dac99e | 1222 | |
e4600702 RK |
1223 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1224 | { | |
e0082a72 | 1225 | basic_block bb; |
f741a71c JH |
1226 | |
1227 | if (dump) | |
a6a2274a | 1228 | fprintf (dump, "\n\nPass %i\n\n",pass); |
e4600702 | 1229 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1230 | |
961192e1 | 1231 | memset ((char *) costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1232 | |
533d0835 | 1233 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1234 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1235 | #endif |
1236 | ||
e4600702 RK |
1237 | /* Scan the instructions and record each time it would |
1238 | save code to put a certain register in a certain class. */ | |
1239 | ||
1f01879e | 1240 | if (!optimize) |
54dac99e | 1241 | { |
a08b2604 | 1242 | frequency = REG_FREQ_MAX; |
1f01879e JH |
1243 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1244 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1245 | } |
1f01879e | 1246 | else |
e0082a72 | 1247 | FOR_EACH_BB (bb) |
1f01879e | 1248 | { |
1f01879e | 1249 | /* Show that an insn inside a loop is likely to be executed three |
9b15c17f RH |
1250 | times more than insns outside a loop. This is much more |
1251 | aggressive than the assumptions made elsewhere and is being | |
1252 | tried as an experiment. */ | |
a08b2604 | 1253 | frequency = REG_FREQ_FROM_BB (bb); |
1f01879e JH |
1254 | for (insn = bb->head; ; insn = NEXT_INSN (insn)) |
1255 | { | |
1256 | insn = scan_one_insn (insn, pass); | |
1257 | if (insn == bb->end) | |
1258 | break; | |
1259 | } | |
1260 | } | |
a6a2274a | 1261 | |
e4600702 RK |
1262 | /* Now for each register look at how desirable each class is |
1263 | and find which class is preferred. Store that in | |
9ffc5a70 | 1264 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1265 | class any of whose registers is better than memory. */ |
a6a2274a | 1266 | |
e4600702 | 1267 | if (pass == 0) |
9ffc5a70 | 1268 | reg_pref = reg_pref_buffer; |
54dac99e | 1269 | |
f741a71c | 1270 | if (dump) |
a6a2274a | 1271 | { |
f741a71c | 1272 | dump_regclass (dump); |
4963c995 | 1273 | fprintf (dump,"\n"); |
f741a71c | 1274 | } |
e4600702 | 1275 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1276 | { |
b3694847 | 1277 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1278 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1279 | /* This is an enum reg_class, but we call it an int | |
1280 | to save lots of casts. */ | |
b3694847 SS |
1281 | int class; |
1282 | struct costs *p = &costs[i]; | |
e4600702 | 1283 | |
64615302 JH |
1284 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1285 | yet. */ | |
ed8d2920 | 1286 | if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) |
f741a71c JH |
1287 | continue; |
1288 | ||
e4600702 | 1289 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1290 | { |
533d0835 | 1291 | /* Ignore classes that are too small for this operand or |
4fe9b91c | 1292 | invalid for an operand that was auto-incremented. */ |
6df26b8f | 1293 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
533d0835 RK |
1294 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1295 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1296 | #endif |
cff9f8d5 AH |
1297 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1298 | || invalid_mode_change_p (i, (enum reg_class) class, | |
1299 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1300 | #endif |
1301 | ) | |
e4600702 RK |
1302 | ; |
1303 | else if (p->cost[class] < best_cost) | |
1304 | { | |
1305 | best_cost = p->cost[class]; | |
1306 | best = (enum reg_class) class; | |
1307 | } | |
1308 | else if (p->cost[class] == best_cost) | |
8e2e89f7 | 1309 | best = reg_class_subunion[(int) best][class]; |
54dac99e | 1310 | } |
54dac99e | 1311 | |
e4600702 RK |
1312 | /* Record the alternate register class; i.e., a class for which |
1313 | every register in it is better than using memory. If adding a | |
1314 | class would make a smaller class (i.e., no union of just those | |
1315 | classes exists), skip that class. The major unions of classes | |
1316 | should be provided as a register class. Don't do this if we | |
1317 | will be doing it again later. */ | |
1318 | ||
f741a71c | 1319 | if ((pass == 1 || dump) || ! flag_expensive_optimizations) |
e4600702 RK |
1320 | for (class = 0; class < N_REG_CLASSES; class++) |
1321 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1322 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1323 | > reg_class_size[(int) alt]) |
1324 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1325 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1326 | #endif |
cff9f8d5 AH |
1327 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1328 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
1329 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1330 | #endif |
1331 | ) | |
e4600702 | 1332 | alt = reg_class_subunion[(int) alt][class]; |
a6a2274a | 1333 | |
e4600702 RK |
1334 | /* If we don't add any classes, nothing to try. */ |
1335 | if (alt == best) | |
995d54dd | 1336 | alt = NO_REGS; |
e4600702 | 1337 | |
a6a2274a | 1338 | if (dump |
f741a71c JH |
1339 | && (reg_pref[i].prefclass != (int) best |
1340 | || reg_pref[i].altclass != (int) alt)) | |
1341 | { | |
1342 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
4963c995 | 1343 | fprintf (dump, " Register %i", i); |
f741a71c JH |
1344 | if (alt == ALL_REGS || best == ALL_REGS) |
1345 | fprintf (dump, " pref %s\n", reg_class_names[(int) best]); | |
1346 | else if (alt == NO_REGS) | |
1347 | fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); | |
1348 | else | |
1349 | fprintf (dump, " pref %s, else %s\n", | |
1350 | reg_class_names[(int) best], | |
1351 | reg_class_names[(int) alt]); | |
1352 | } | |
1353 | ||
e4600702 | 1354 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1355 | reg_pref[i].prefclass = (int) best; |
1356 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1357 | } |
54dac99e | 1358 | } |
56a65848 | 1359 | |
4da896b2 MM |
1360 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1361 | free (in_inc_dec); | |
1362 | #endif | |
56a65848 | 1363 | free (costs); |
54dac99e RK |
1364 | } |
1365 | \f | |
e4600702 RK |
1366 | /* Record the cost of using memory or registers of various classes for |
1367 | the operands in INSN. | |
54dac99e | 1368 | |
e4600702 | 1369 | N_ALTS is the number of alternatives. |
54dac99e | 1370 | |
e4600702 RK |
1371 | N_OPS is the number of operands. |
1372 | ||
1373 | OPS is an array of the operands. | |
1374 | ||
1375 | MODES are the modes of the operands, in case any are VOIDmode. | |
1376 | ||
1377 | CONSTRAINTS are the constraints to use for the operands. This array | |
1378 | is modified by this procedure. | |
1379 | ||
1380 | This procedure works alternative by alternative. For each alternative | |
1381 | we assume that we will be able to allocate all pseudos to their ideal | |
1382 | register class and calculate the cost of using that alternative. Then | |
a6a2274a | 1383 | we compute for each operand that is a pseudo-register, the cost of |
e4600702 RK |
1384 | having the pseudo allocated to each register class and using it in that |
1385 | alternative. To this cost is added the cost of the alternative. | |
1386 | ||
1387 | The cost of each class for this insn is its lowest cost among all the | |
1388 | alternatives. */ | |
1389 | ||
1390 | static void | |
e79f71f7 | 1391 | record_reg_classes (n_alts, n_ops, ops, modes, |
f741a71c | 1392 | constraints, insn, op_costs, reg_pref) |
e4600702 RK |
1393 | int n_alts; |
1394 | int n_ops; | |
1395 | rtx *ops; | |
1396 | enum machine_mode *modes; | |
9b3142b3 | 1397 | const char **constraints; |
e4600702 | 1398 | rtx insn; |
f741a71c JH |
1399 | struct costs *op_costs; |
1400 | struct reg_pref *reg_pref; | |
54dac99e | 1401 | { |
e4600702 | 1402 | int alt; |
e4600702 | 1403 | int i, j; |
ec2d92af | 1404 | rtx set; |
e4600702 | 1405 | |
e4600702 RK |
1406 | /* Process each alternative, each time minimizing an operand's cost with |
1407 | the cost for each operand in that alternative. */ | |
54dac99e | 1408 | |
e4600702 | 1409 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1410 | { |
e4600702 RK |
1411 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1412 | int alt_fail = 0; | |
1413 | int alt_cost = 0; | |
1414 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1415 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1416 | int class; |
54dac99e | 1417 | |
e4600702 RK |
1418 | for (i = 0; i < n_ops; i++) |
1419 | { | |
9b3142b3 | 1420 | const char *p = constraints[i]; |
e4600702 RK |
1421 | rtx op = ops[i]; |
1422 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1423 | int allows_addr = 0; |
e4600702 | 1424 | int win = 0; |
e51712db | 1425 | unsigned char c; |
54dac99e | 1426 | |
7405d9a1 DE |
1427 | /* Initially show we know nothing about the register class. */ |
1428 | classes[i] = NO_REGS; | |
da2c0219 | 1429 | allows_mem[i] = 0; |
7405d9a1 | 1430 | |
a6a2274a | 1431 | /* If this operand has no constraints at all, we can conclude |
e4600702 | 1432 | nothing about it since anything is valid. */ |
54dac99e | 1433 | |
e4600702 RK |
1434 | if (*p == 0) |
1435 | { | |
1436 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
961192e1 | 1437 | memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1438 | |
e4600702 RK |
1439 | continue; |
1440 | } | |
54dac99e | 1441 | |
7405d9a1 DE |
1442 | /* If this alternative is only relevant when this operand |
1443 | matches a previous operand, we do different things depending | |
1444 | on whether this operand is a pseudo-reg or not. We must process | |
1445 | any modifiers for the operand before we can make this test. */ | |
1446 | ||
8c368ee2 | 1447 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1448 | p++; |
8c368ee2 | 1449 | |
e4600702 RK |
1450 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1451 | { | |
da2c0219 RK |
1452 | /* Copy class and whether memory is allowed from the matching |
1453 | alternative. Then perform any needed cost computations | |
1454 | and/or adjustments. */ | |
e4600702 RK |
1455 | j = p[0] - '0'; |
1456 | classes[i] = classes[j]; | |
da2c0219 | 1457 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1458 | |
1459 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1460 | { | |
1461 | /* If this matches the other operand, we have no added | |
dc903608 | 1462 | cost and we win. */ |
e4600702 | 1463 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1464 | win = 1; |
e4600702 | 1465 | |
77e67eac RK |
1466 | /* If we can put the other operand into a register, add to |
1467 | the cost of this alternative the cost to copy this | |
1468 | operand to the register used for the other operand. */ | |
e4600702 | 1469 | |
dc903608 | 1470 | else if (classes[j] != NO_REGS) |
77e67eac | 1471 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1472 | } |
07d8ca2d RS |
1473 | else if (GET_CODE (ops[j]) != REG |
1474 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1475 | { | |
1476 | /* This op is a pseudo but the one it matches is not. */ | |
a6a2274a | 1477 | |
07d8ca2d RS |
1478 | /* If we can't put the other operand into a register, this |
1479 | alternative can't be used. */ | |
1480 | ||
1481 | if (classes[j] == NO_REGS) | |
1482 | alt_fail = 1; | |
e4600702 | 1483 | |
07d8ca2d RS |
1484 | /* Otherwise, add to the cost of this alternative the cost |
1485 | to copy the other operand to the register used for this | |
1486 | operand. */ | |
1487 | ||
1488 | else | |
1489 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1490 | } | |
e4600702 RK |
1491 | else |
1492 | { | |
da2c0219 RK |
1493 | /* The costs of this operand are not the same as the other |
1494 | operand since move costs are not symmetric. Moreover, | |
1495 | if we cannot tie them, this alternative needs to do a | |
1496 | copy, which is one instruction. */ | |
1497 | ||
1498 | struct costs *pp = &this_op_costs[i]; | |
1499 | ||
1500 | for (class = 0; class < N_REG_CLASSES; class++) | |
1501 | pp->cost[class] | |
d5e2075d | 1502 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1503 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1504 | : 0) |
1505 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1506 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1507 | : 0)); |
a6a2274a | 1508 | |
da2c0219 RK |
1509 | /* If the alternative actually allows memory, make things |
1510 | a bit cheaper since we won't need an extra insn to | |
1511 | load it. */ | |
1512 | ||
1513 | pp->mem_cost | |
d5e2075d JH |
1514 | = ((recog_data.operand_type[i] != OP_IN |
1515 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1516 | : 0) | |
1517 | + (recog_data.operand_type[i] != OP_OUT | |
1518 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1519 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1520 | |
1521 | /* If we have assigned a class to this register in our | |
1522 | first pass, add a cost to this alternative corresponding | |
1523 | to what we would add if this register were not in the | |
1524 | appropriate class. */ | |
1525 | ||
9ffc5a70 | 1526 | if (reg_pref) |
da2c0219 | 1527 | alt_cost |
e56b4594 AO |
1528 | += (may_move_in_cost[mode] |
1529 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1530 | [(int) classes[i]]); |
e4600702 | 1531 | |
37747c82 RK |
1532 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1533 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1534 | alt_cost += 2; | |
e4600702 | 1535 | |
347099d6 | 1536 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1537 | for this operand, so skip to the end of the |
1538 | alternative (should be just one character). */ | |
1539 | while (*p && *p++ != ',') | |
1540 | ; | |
1541 | ||
1542 | constraints[i] = p; | |
347099d6 RS |
1543 | continue; |
1544 | } | |
e4600702 RK |
1545 | } |
1546 | ||
1547 | /* Scan all the constraint letters. See if the operand matches | |
1548 | any of the constraints. Collect the valid register classes | |
1549 | and see if this operand accepts memory. */ | |
1550 | ||
97488870 R |
1551 | while ((c = *p)) |
1552 | { | |
1553 | switch (c) | |
1554 | { | |
1555 | case ',': | |
1556 | break; | |
1557 | case '*': | |
1558 | /* Ignore the next letter for this pass. */ | |
1559 | c = *++p; | |
1560 | break; | |
94e6f783 | 1561 | |
97488870 R |
1562 | case '?': |
1563 | alt_cost += 2; | |
1564 | case '!': case '#': case '&': | |
1565 | case '0': case '1': case '2': case '3': case '4': | |
1566 | case '5': case '6': case '7': case '8': case '9': | |
1567 | break; | |
e4600702 | 1568 | |
97488870 R |
1569 | case 'p': |
1570 | allows_addr = 1; | |
1571 | win = address_operand (op, GET_MODE (op)); | |
1572 | /* We know this operand is an address, so we want it to be | |
1573 | allocated to a register that can be the base of an | |
1574 | address, ie BASE_REG_CLASS. */ | |
1575 | classes[i] | |
1576 | = reg_class_subunion[(int) classes[i]] | |
1577 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1578 | break; | |
e4600702 | 1579 | |
97488870 R |
1580 | case 'm': case 'o': case 'V': |
1581 | /* It doesn't seem worth distinguishing between offsettable | |
1582 | and non-offsettable addresses here. */ | |
1583 | allows_mem[i] = 1; | |
1584 | if (GET_CODE (op) == MEM) | |
1585 | win = 1; | |
1586 | break; | |
e4600702 | 1587 | |
97488870 R |
1588 | case '<': |
1589 | if (GET_CODE (op) == MEM | |
1590 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1591 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1592 | win = 1; | |
1593 | break; | |
e4600702 | 1594 | |
97488870 R |
1595 | case '>': |
1596 | if (GET_CODE (op) == MEM | |
1597 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1598 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1599 | win = 1; | |
1600 | break; | |
e4600702 | 1601 | |
97488870 R |
1602 | case 'E': |
1603 | case 'F': | |
1604 | if (GET_CODE (op) == CONST_DOUBLE | |
1605 | || (GET_CODE (op) == CONST_VECTOR | |
1606 | && (GET_MODE_CLASS (GET_MODE (op)) | |
1607 | == MODE_VECTOR_FLOAT))) | |
1608 | win = 1; | |
1609 | break; | |
e4600702 | 1610 | |
97488870 R |
1611 | case 'G': |
1612 | case 'H': | |
1613 | if (GET_CODE (op) == CONST_DOUBLE | |
1614 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
1615 | win = 1; | |
e4600702 | 1616 | break; |
97488870 R |
1617 | |
1618 | case 's': | |
1619 | if (GET_CODE (op) == CONST_INT | |
1620 | || (GET_CODE (op) == CONST_DOUBLE | |
1621 | && GET_MODE (op) == VOIDmode)) | |
1622 | break; | |
1623 | case 'i': | |
1624 | if (CONSTANT_P (op) | |
e4600702 | 1625 | #ifdef LEGITIMATE_PIC_OPERAND_P |
97488870 | 1626 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
e4600702 | 1627 | #endif |
97488870 R |
1628 | ) |
1629 | win = 1; | |
1630 | break; | |
e4600702 | 1631 | |
97488870 R |
1632 | case 'n': |
1633 | if (GET_CODE (op) == CONST_INT | |
1634 | || (GET_CODE (op) == CONST_DOUBLE | |
1635 | && GET_MODE (op) == VOIDmode)) | |
1636 | win = 1; | |
1637 | break; | |
e4600702 | 1638 | |
97488870 R |
1639 | case 'I': |
1640 | case 'J': | |
1641 | case 'K': | |
1642 | case 'L': | |
1643 | case 'M': | |
1644 | case 'N': | |
1645 | case 'O': | |
1646 | case 'P': | |
1647 | if (GET_CODE (op) == CONST_INT | |
1648 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1649 | win = 1; | |
1650 | break; | |
e4600702 | 1651 | |
97488870 R |
1652 | case 'X': |
1653 | win = 1; | |
1654 | break; | |
54dac99e | 1655 | |
97488870 R |
1656 | case 'g': |
1657 | if (GET_CODE (op) == MEM | |
1658 | || (CONSTANT_P (op) | |
e4600702 | 1659 | #ifdef LEGITIMATE_PIC_OPERAND_P |
97488870 | 1660 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
54dac99e | 1661 | #endif |
97488870 R |
1662 | )) |
1663 | win = 1; | |
1664 | allows_mem[i] = 1; | |
1665 | case 'r': | |
c2cba7a9 | 1666 | classes[i] |
97488870 R |
1667 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; |
1668 | break; | |
ccfc6cc8 | 1669 | |
97488870 R |
1670 | default: |
1671 | if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
ccfc6cc8 UW |
1672 | classes[i] |
1673 | = reg_class_subunion[(int) classes[i]] | |
97488870 R |
1674 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
1675 | #ifdef EXTRA_CONSTRAINT_STR | |
1676 | else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1677 | win = 1; | |
1678 | ||
1679 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1680 | { | |
1681 | /* Every MEM can be reloaded to fit. */ | |
1682 | allows_mem[i] = 1; | |
1683 | if (GET_CODE (op) == MEM) | |
1684 | win = 1; | |
1685 | } | |
1686 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1687 | { | |
1688 | /* Every address can be reloaded to fit. */ | |
1689 | allows_addr = 1; | |
1690 | if (address_operand (op, GET_MODE (op))) | |
1691 | win = 1; | |
1692 | /* We know this operand is an address, so we want it to | |
1693 | be allocated to a register that can be the base of an | |
1694 | address, ie BASE_REG_CLASS. */ | |
1695 | classes[i] | |
1696 | = reg_class_subunion[(int) classes[i]] | |
1697 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1698 | } | |
c2cba7a9 | 1699 | #endif |
97488870 R |
1700 | break; |
1701 | } | |
1702 | p += CONSTRAINT_LEN (c, p); | |
1703 | if (c == ',') | |
c2cba7a9 | 1704 | break; |
97488870 | 1705 | } |
e4600702 RK |
1706 | |
1707 | constraints[i] = p; | |
1708 | ||
1709 | /* How we account for this operand now depends on whether it is a | |
1710 | pseudo register or not. If it is, we first check if any | |
1711 | register classes are valid. If not, we ignore this alternative, | |
1712 | since we want to assume that all pseudos get allocated for | |
1713 | register preferencing. If some register class is valid, compute | |
1714 | the costs of moving the pseudo into that class. */ | |
1715 | ||
1716 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1717 | { |
e4600702 | 1718 | if (classes[i] == NO_REGS) |
94e6f783 | 1719 | { |
e79f71f7 GK |
1720 | /* We must always fail if the operand is a REG, but |
1721 | we did not find a suitable class. | |
a6a2274a | 1722 | |
e79f71f7 GK |
1723 | Otherwise we may perform an uninitialized read |
1724 | from this_op_costs after the `continue' statement | |
1725 | below. */ | |
1726 | alt_fail = 1; | |
94e6f783 | 1727 | } |
e4600702 RK |
1728 | else |
1729 | { | |
1730 | struct costs *pp = &this_op_costs[i]; | |
1731 | ||
1732 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1733 | pp->cost[class] |
d5e2075d | 1734 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1735 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1736 | : 0) |
1737 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1738 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1739 | : 0)); |
e4600702 RK |
1740 | |
1741 | /* If the alternative actually allows memory, make things | |
1742 | a bit cheaper since we won't need an extra insn to | |
1743 | load it. */ | |
1744 | ||
14a774a9 | 1745 | pp->mem_cost |
d5e2075d JH |
1746 | = ((recog_data.operand_type[i] != OP_IN |
1747 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1748 | : 0) | |
1749 | + (recog_data.operand_type[i] != OP_OUT | |
1750 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1751 | : 0) - allows_mem[i]); | |
e4600702 RK |
1752 | |
1753 | /* If we have assigned a class to this register in our | |
1754 | first pass, add a cost to this alternative corresponding | |
1755 | to what we would add if this register were not in the | |
1756 | appropriate class. */ | |
1757 | ||
9ffc5a70 | 1758 | if (reg_pref) |
e4600702 | 1759 | alt_cost |
e56b4594 AO |
1760 | += (may_move_in_cost[mode] |
1761 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1762 | [(int) classes[i]]); |
e4600702 | 1763 | } |
4db18574 | 1764 | } |
54dac99e | 1765 | |
e4600702 RK |
1766 | /* Otherwise, if this alternative wins, either because we |
1767 | have already determined that or if we have a hard register of | |
1768 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1769 | |
e4600702 RK |
1770 | else if (win |
1771 | || (GET_CODE (op) == REG | |
6f654776 | 1772 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1773 | ; |
54dac99e | 1774 | |
e4600702 RK |
1775 | /* If registers are valid, the cost of this alternative includes |
1776 | copying the object to and/or from a register. */ | |
54dac99e | 1777 | |
e4600702 RK |
1778 | else if (classes[i] != NO_REGS) |
1779 | { | |
1ccbefce | 1780 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1781 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1782 | |
1ccbefce | 1783 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1784 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1785 | } | |
54dac99e | 1786 | |
e4600702 RK |
1787 | /* The only other way this alternative can be used is if this is a |
1788 | constant that could be placed into memory. */ | |
1789 | ||
da2c0219 | 1790 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1791 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1792 | else |
1793 | alt_fail = 1; | |
1794 | } | |
1795 | ||
1796 | if (alt_fail) | |
1797 | continue; | |
1798 | ||
1799 | /* Finally, update the costs with the information we've calculated | |
1800 | about this alternative. */ | |
1801 | ||
1802 | for (i = 0; i < n_ops; i++) | |
1803 | if (GET_CODE (ops[i]) == REG | |
1804 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1805 | { |
e4600702 | 1806 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1807 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1808 | |
e4600702 RK |
1809 | pp->mem_cost = MIN (pp->mem_cost, |
1810 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1811 | |
e4600702 RK |
1812 | for (class = 0; class < N_REG_CLASSES; class++) |
1813 | pp->cost[class] = MIN (pp->cost[class], | |
1814 | (qq->cost[class] + alt_cost) * scale); | |
1815 | } | |
1816 | } | |
ec2d92af RK |
1817 | |
1818 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1819 | and one operand is a pseudo with the other a hard reg or a pseudo |
1820 | that prefers a register that is in its own register class then | |
1821 | we may want to adjust the cost of that register class to -1. | |
a6a2274a | 1822 | |
accef103 JL |
1823 | Avoid the adjustment if the source does not die to avoid stressing of |
1824 | register allocator by preferrencing two coliding registers into single | |
1825 | class. | |
1826 | ||
1827 | Also avoid the adjustment if a copy between registers of the class | |
1828 | is expensive (ten times the cost of a default copy is considered | |
1829 | arbitrarily expensive). This avoids losing when the preferred class | |
1830 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1831 | |
1832 | if ((set = single_set (insn)) != 0 | |
1833 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
0dc0641b JH |
1834 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG |
1835 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
ec2d92af RK |
1836 | for (i = 0; i <= 1; i++) |
1837 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1838 | { | |
770ae6cc | 1839 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1840 | enum machine_mode mode = GET_MODE (ops[!i]); |
1841 | int class; | |
770ae6cc | 1842 | unsigned int nr; |
ec2d92af | 1843 | |
accef103 JL |
1844 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1845 | { | |
1846 | enum reg_class pref = reg_pref[regno].prefclass; | |
1847 | ||
1848 | if ((reg_class_size[(unsigned char) pref] | |
f7043461 | 1849 | == (unsigned) CLASS_MAX_NREGS (pref, mode)) |
e56b4594 | 1850 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1851 | op_costs[i].cost[(unsigned char) pref] = -1; |
1852 | } | |
ec2d92af RK |
1853 | else if (regno < FIRST_PSEUDO_REGISTER) |
1854 | for (class = 0; class < N_REG_CLASSES; class++) | |
1855 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
f7043461 | 1856 | && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) |
4841ba4b RK |
1857 | { |
1858 | if (reg_class_size[class] == 1) | |
1859 | op_costs[i].cost[class] = -1; | |
1860 | else | |
1861 | { | |
f7043461 | 1862 | for (nr = 0; nr < (unsigned) HARD_REGNO_NREGS (regno, mode); nr++) |
4841ba4b | 1863 | { |
770ae6cc RK |
1864 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1865 | regno + nr)) | |
4841ba4b RK |
1866 | break; |
1867 | } | |
1868 | ||
f7043461 | 1869 | if (nr == (unsigned) HARD_REGNO_NREGS (regno,mode)) |
4841ba4b RK |
1870 | op_costs[i].cost[class] = -1; |
1871 | } | |
1872 | } | |
ec2d92af | 1873 | } |
54dac99e | 1874 | } |
e4600702 | 1875 | \f |
40f03658 | 1876 | /* Compute the cost of loading X into (if TO_P is nonzero) or from (if |
e4600702 RK |
1877 | TO_P is zero) a register of class CLASS in mode MODE. |
1878 | ||
1879 | X must not be a pseudo. */ | |
1880 | ||
1881 | static int | |
1882 | copy_cost (x, mode, class, to_p) | |
1883 | rtx x; | |
d0af450d | 1884 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e4600702 | 1885 | enum reg_class class; |
d0af450d | 1886 | int to_p ATTRIBUTE_UNUSED; |
e4600702 | 1887 | { |
29a82058 | 1888 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1889 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1890 | #endif |
e4600702 RK |
1891 | |
1892 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1893 | assuming optimal allocation. */ | |
1894 | ||
1895 | if (GET_CODE (x) == SCRATCH) | |
1896 | return 0; | |
1897 | ||
1898 | /* Get the class we will actually use for a reload. */ | |
1899 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1900 | ||
1901 | #ifdef HAVE_SECONDARY_RELOADS | |
a6a2274a | 1902 | /* If we need a secondary reload (we assume here that we are using |
e4600702 RK |
1903 | the secondary reload as an intermediate, not a scratch register), the |
1904 | cost is that to load the input into the intermediate register, then | |
1905 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1906 | ||
1907 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1908 | if (to_p == 1) | |
1909 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1910 | #endif | |
1911 | ||
dd9f0e8f | 1912 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1913 | if (! to_p) |
1914 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1915 | #endif | |
1916 | ||
1917 | if (secondary_class != NO_REGS) | |
e56b4594 | 1918 | return (move_cost[mode][(int) secondary_class][(int) class] |
e4600702 | 1919 | + copy_cost (x, mode, secondary_class, 2)); |
dd9f0e8f | 1920 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1921 | |
1922 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1923 | cost to move between the register classes, and use 2 for everything | |
1924 | else (constants). */ | |
1925 | ||
1926 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1927 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1928 | |
e4600702 | 1929 | else if (GET_CODE (x) == REG) |
e56b4594 | 1930 | return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
e4600702 RK |
1931 | |
1932 | else | |
1933 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
b437f1a7 | 1934 | return COSTS_N_INSNS (1); |
e4600702 RK |
1935 | } |
1936 | \f | |
54dac99e RK |
1937 | /* Record the pseudo registers we must reload into hard registers |
1938 | in a subexpression of a memory address, X. | |
e4600702 RK |
1939 | |
1940 | CLASS is the class that the register needs to be in and is either | |
1941 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1942 | ||
1943 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1944 | can represent half-cost adjustments). */ | |
54dac99e | 1945 | |
197d6480 | 1946 | static void |
e4600702 | 1947 | record_address_regs (x, class, scale) |
54dac99e | 1948 | rtx x; |
e4600702 RK |
1949 | enum reg_class class; |
1950 | int scale; | |
54dac99e | 1951 | { |
b3694847 | 1952 | enum rtx_code code = GET_CODE (x); |
54dac99e RK |
1953 | |
1954 | switch (code) | |
1955 | { | |
1956 | case CONST_INT: | |
1957 | case CONST: | |
1958 | case CC0: | |
1959 | case PC: | |
1960 | case SYMBOL_REF: | |
1961 | case LABEL_REF: | |
1962 | return; | |
1963 | ||
1964 | case PLUS: | |
1965 | /* When we have an address that is a sum, | |
1966 | we must determine whether registers are "base" or "index" regs. | |
1967 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1968 | the "base". Luckily, we can use the REG_POINTER to make a good |
1969 | choice most of the time. We only need to do this on machines | |
1970 | that can have two registers in an address and where the base | |
1971 | and index register classes are different. | |
e4600702 RK |
1972 | |
1973 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1974 | that seems bogus since it should only be set when we are sure | |
1975 | the register is being used as a pointer. */ | |
1976 | ||
54dac99e RK |
1977 | { |
1978 | rtx arg0 = XEXP (x, 0); | |
1979 | rtx arg1 = XEXP (x, 1); | |
b3694847 SS |
1980 | enum rtx_code code0 = GET_CODE (arg0); |
1981 | enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1982 | |
1983 | /* Look inside subregs. */ | |
e4600702 | 1984 | if (code0 == SUBREG) |
54dac99e | 1985 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1986 | if (code1 == SUBREG) |
54dac99e RK |
1987 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1988 | ||
e4600702 RK |
1989 | /* If this machine only allows one register per address, it must |
1990 | be in the first operand. */ | |
1991 | ||
1992 | if (MAX_REGS_PER_ADDRESS == 1) | |
1993 | record_address_regs (arg0, class, scale); | |
1994 | ||
1995 | /* If index and base registers are the same on this machine, just | |
1996 | record registers in any non-constant operands. We assume here, | |
a6a2274a | 1997 | as well as in the tests below, that all addresses are in |
e4600702 RK |
1998 | canonical form. */ |
1999 | ||
3dcc68a4 | 2000 | else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) |
54dac99e | 2001 | { |
e4600702 RK |
2002 | record_address_regs (arg0, class, scale); |
2003 | if (! CONSTANT_P (arg1)) | |
2004 | record_address_regs (arg1, class, scale); | |
54dac99e | 2005 | } |
e4600702 RK |
2006 | |
2007 | /* If the second operand is a constant integer, it doesn't change | |
2008 | what class the first operand must be. */ | |
2009 | ||
2010 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
2011 | record_address_regs (arg0, class, scale); | |
2012 | ||
2013 | /* If the second operand is a symbolic constant, the first operand | |
2014 | must be an index register. */ | |
2015 | ||
2016 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
2017 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
2018 | ||
956d6950 JL |
2019 | /* If both operands are registers but one is already a hard register |
2020 | of index or base class, give the other the class that the hard | |
2021 | register is not. */ | |
2022 | ||
3f9e9508 | 2023 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
2024 | else if (code0 == REG && code1 == REG |
2025 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
2026 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
2027 | record_address_regs (arg1, | |
2028 | REG_OK_FOR_BASE_P (arg0) | |
3dcc68a4 | 2029 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 JL |
2030 | scale); |
2031 | else if (code0 == REG && code1 == REG | |
2032 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
2033 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
2034 | record_address_regs (arg0, | |
2035 | REG_OK_FOR_BASE_P (arg1) | |
3dcc68a4 | 2036 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 | 2037 | scale); |
3f9e9508 | 2038 | #endif |
956d6950 | 2039 | |
e9a25f70 JL |
2040 | /* If one operand is known to be a pointer, it must be the base |
2041 | with the other operand the index. Likewise if the other operand | |
2042 | is a MULT. */ | |
f22376c7 | 2043 | |
3502dc9c | 2044 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 2045 | || code1 == MULT) |
f22376c7 | 2046 | { |
3dcc68a4 | 2047 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2048 | record_address_regs (arg1, INDEX_REG_CLASS, scale); |
2049 | } | |
3502dc9c | 2050 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 2051 | || code0 == MULT) |
f22376c7 CI |
2052 | { |
2053 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
3dcc68a4 | 2054 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2055 | } |
2056 | ||
e9a25f70 | 2057 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
2058 | or index register. This case should be rare. */ |
2059 | ||
e9a25f70 | 2060 | else |
54dac99e | 2061 | { |
3dcc68a4 NC |
2062 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), |
2063 | scale / 2); | |
e4600702 | 2064 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); |
3dcc68a4 NC |
2065 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), |
2066 | scale / 2); | |
e4600702 | 2067 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); |
54dac99e | 2068 | } |
54dac99e RK |
2069 | } |
2070 | break; | |
2071 | ||
4b983fdc RH |
2072 | /* Double the importance of a pseudo register that is incremented |
2073 | or decremented, since it would take two extra insns | |
2074 | if it ends up in the wrong place. */ | |
2075 | case POST_MODIFY: | |
2076 | case PRE_MODIFY: | |
3dcc68a4 NC |
2077 | record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), |
2078 | 2 * scale); | |
4b983fdc RH |
2079 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
2080 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
2081 | INDEX_REG_CLASS, 2 * scale); | |
2082 | break; | |
2083 | ||
54dac99e RK |
2084 | case POST_INC: |
2085 | case PRE_INC: | |
2086 | case POST_DEC: | |
2087 | case PRE_DEC: | |
2088 | /* Double the importance of a pseudo register that is incremented | |
2089 | or decremented, since it would take two extra insns | |
533d0835 RK |
2090 | if it ends up in the wrong place. If the operand is a pseudo, |
2091 | show it is being used in an INC_DEC context. */ | |
2092 | ||
2093 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2094 | if (GET_CODE (XEXP (x, 0)) == REG | |
2095 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
2096 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2097 | #endif | |
e4600702 RK |
2098 | |
2099 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
2100 | break; |
2101 | ||
2102 | case REG: | |
2103 | { | |
b3694847 SS |
2104 | struct costs *pp = &costs[REGNO (x)]; |
2105 | int i; | |
54dac99e | 2106 | |
cbd5b9a2 | 2107 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 2108 | |
e4600702 | 2109 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 2110 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
2111 | } |
2112 | break; | |
2113 | ||
2114 | default: | |
2115 | { | |
b3694847 SS |
2116 | const char *fmt = GET_RTX_FORMAT (code); |
2117 | int i; | |
54dac99e RK |
2118 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2119 | if (fmt[i] == 'e') | |
e4600702 | 2120 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
2121 | } |
2122 | } | |
2123 | } | |
08d95f91 RK |
2124 | \f |
2125 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2126 | ||
2127 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2128 | to an object of MODE. */ | |
2129 | ||
1d300e19 | 2130 | static int |
08d95f91 RK |
2131 | auto_inc_dec_reg_p (reg, mode) |
2132 | rtx reg; | |
2133 | enum machine_mode mode; | |
2134 | { | |
940da324 JL |
2135 | if (HAVE_POST_INCREMENT |
2136 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2137 | return 1; |
08d95f91 | 2138 | |
940da324 JL |
2139 | if (HAVE_POST_DECREMENT |
2140 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2141 | return 1; |
08d95f91 | 2142 | |
940da324 JL |
2143 | if (HAVE_PRE_INCREMENT |
2144 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2145 | return 1; |
08d95f91 | 2146 | |
940da324 JL |
2147 | if (HAVE_PRE_DECREMENT |
2148 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2149 | return 1; |
08d95f91 RK |
2150 | |
2151 | return 0; | |
2152 | } | |
2153 | #endif | |
b1f21e0a | 2154 | \f |
da668e9c MM |
2155 | static short *renumber; |
2156 | static size_t regno_allocated; | |
2157 | static unsigned int reg_n_max; | |
ed396e68 | 2158 | |
b1f21e0a MM |
2159 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2160 | reg_scan and flow_analysis that are indexed by the register number. If | |
88cad84b | 2161 | NEW_P is nonzero, initialize all of the registers, otherwise only |
39379e67 MM |
2162 | initialize the new registers allocated. The same table is kept from |
2163 | function to function, only reallocating it when we need more room. If | |
88cad84b | 2164 | RENUMBER_P is nonzero, allocate the reg_renumber array also. */ |
b1f21e0a MM |
2165 | |
2166 | void | |
39379e67 | 2167 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 2168 | size_t num_regs; |
b1f21e0a | 2169 | int new_p; |
39379e67 | 2170 | int renumber_p; |
b1f21e0a | 2171 | { |
6feacd09 MM |
2172 | size_t size_info; |
2173 | size_t size_renumber; | |
2174 | size_t min = (new_p) ? 0 : reg_n_max; | |
2175 | struct reg_info_data *reg_data; | |
39379e67 | 2176 | |
b1f21e0a MM |
2177 | if (num_regs > regno_allocated) |
2178 | { | |
6feacd09 MM |
2179 | size_t old_allocated = regno_allocated; |
2180 | ||
b1f21e0a | 2181 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
2182 | size_renumber = regno_allocated * sizeof (short); |
2183 | ||
2184 | if (!reg_n_info) | |
2185 | { | |
6feacd09 | 2186 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 2187 | renumber = (short *) xmalloc (size_renumber); |
a6a2274a | 2188 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
9ffc5a70 | 2189 | * sizeof (struct reg_pref)); |
39379e67 MM |
2190 | } |
2191 | ||
2192 | else | |
2193 | { | |
6feacd09 MM |
2194 | VARRAY_GROW (reg_n_info, regno_allocated); |
2195 | ||
2196 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
2197 | { | |
8e2e89f7 KH |
2198 | free ((char *) renumber); |
2199 | free ((char *) reg_pref); | |
6feacd09 | 2200 | renumber = (short *) xmalloc (size_renumber); |
a6a2274a | 2201 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
9ffc5a70 | 2202 | * sizeof (struct reg_pref)); |
6feacd09 MM |
2203 | } |
2204 | ||
2205 | else | |
2206 | { | |
8e2e89f7 KH |
2207 | renumber = (short *) xrealloc ((char *) renumber, size_renumber); |
2208 | reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer, | |
a6a2274a | 2209 | regno_allocated |
9ffc5a70 | 2210 | * sizeof (struct reg_pref)); |
6feacd09 | 2211 | } |
39379e67 | 2212 | } |
6feacd09 MM |
2213 | |
2214 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2215 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
2216 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
2217 | reg_data->min_index = old_allocated; | |
2218 | reg_data->max_index = regno_allocated - 1; | |
2219 | reg_data->next = reg_info_head; | |
2220 | reg_info_head = reg_data; | |
b1f21e0a MM |
2221 | } |
2222 | ||
6feacd09 | 2223 | reg_n_max = num_regs; |
b1f21e0a MM |
2224 | if (min < num_regs) |
2225 | { | |
6feacd09 MM |
2226 | /* Loop through each of the segments allocated for the actual |
2227 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
a6a2274a | 2228 | for (reg_data = reg_info_head; |
da668e9c MM |
2229 | reg_data && reg_data->max_index >= min; |
2230 | reg_data = reg_data->next) | |
39379e67 | 2231 | { |
6feacd09 MM |
2232 | size_t min_index = reg_data->min_index; |
2233 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2234 | size_t max = MIN (max_index, num_regs); |
2235 | size_t local_min = min - min_index; | |
2236 | size_t i; | |
6feacd09 | 2237 | |
da668e9c MM |
2238 | if (reg_data->min_index > num_regs) |
2239 | continue; | |
6feacd09 | 2240 | |
da668e9c MM |
2241 | if (min < min_index) |
2242 | local_min = 0; | |
2243 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2244 | reg_data->used_p = 1; /* no need to zero */ | |
2245 | else | |
961192e1 | 2246 | memset ((char *) ®_data->data[local_min], 0, |
da668e9c MM |
2247 | sizeof (reg_info) * (max - min_index - local_min + 1)); |
2248 | ||
2249 | for (i = min_index+local_min; i <= max; i++) | |
2250 | { | |
2251 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2252 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2253 | renumber[i] = -1; | |
2254 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2255 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2256 | } |
39379e67 | 2257 | } |
b1f21e0a MM |
2258 | } |
2259 | ||
6feacd09 MM |
2260 | /* If {pref,alt}class have already been allocated, update the pointers to |
2261 | the newly realloced ones. */ | |
9ffc5a70 JH |
2262 | if (reg_pref) |
2263 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2264 | |
39379e67 MM |
2265 | if (renumber_p) |
2266 | reg_renumber = renumber; | |
2267 | ||
3eae4643 | 2268 | /* Tell the regset code about the new number of registers. */ |
73b76448 | 2269 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); |
b1f21e0a MM |
2270 | } |
2271 | ||
ed396e68 BS |
2272 | /* Free up the space allocated by allocate_reg_info. */ |
2273 | void | |
2274 | free_reg_info () | |
2275 | { | |
2276 | if (reg_n_info) | |
2277 | { | |
2278 | struct reg_info_data *reg_data; | |
2279 | struct reg_info_data *reg_next; | |
2280 | ||
2281 | VARRAY_FREE (reg_n_info); | |
2282 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2283 | { | |
2284 | reg_next = reg_data->next; | |
8e2e89f7 | 2285 | free ((char *) reg_data); |
ed396e68 BS |
2286 | } |
2287 | ||
9ffc5a70 | 2288 | free (reg_pref_buffer); |
f4f4d0f8 KH |
2289 | reg_pref_buffer = (struct reg_pref *) 0; |
2290 | reg_info_head = (struct reg_info_data *) 0; | |
2291 | renumber = (short *) 0; | |
ed396e68 BS |
2292 | } |
2293 | regno_allocated = 0; | |
2294 | reg_n_max = 0; | |
2295 | } | |
54dac99e RK |
2296 | \f |
2297 | /* This is the `regscan' pass of the compiler, run just before cse | |
2298 | and again just before loop. | |
2299 | ||
2300 | It finds the first and last use of each pseudo-register | |
2301 | and records them in the vectors regno_first_uid, regno_last_uid | |
2302 | and counts the number of sets in the vector reg_n_sets. | |
2303 | ||
2304 | REPEAT is nonzero the second time this is called. */ | |
2305 | ||
54dac99e | 2306 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2307 | Always at least 3, since the combiner could put that many together |
79b9ec0d RK |
2308 | and we want this to remain correct for all the remaining passes. |
2309 | This corresponds to the maximum number of times note_stores will call | |
2310 | a function for any insn. */ | |
54dac99e RK |
2311 | |
2312 | int max_parallel; | |
2313 | ||
a6a2274a | 2314 | /* Used as a temporary to record the largest number of registers in |
79b9ec0d RK |
2315 | PARALLEL in a SET_DEST. This is added to max_parallel. */ |
2316 | ||
2317 | static int max_set_parallel; | |
2318 | ||
54dac99e RK |
2319 | void |
2320 | reg_scan (f, nregs, repeat) | |
2321 | rtx f; | |
770ae6cc | 2322 | unsigned int nregs; |
272df862 | 2323 | int repeat ATTRIBUTE_UNUSED; |
54dac99e | 2324 | { |
b3694847 | 2325 | rtx insn; |
54dac99e | 2326 | |
39379e67 | 2327 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e | 2328 | max_parallel = 3; |
79b9ec0d | 2329 | max_set_parallel = 0; |
54dac99e RK |
2330 | |
2331 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2332 | if (GET_CODE (insn) == INSN | |
2333 | || GET_CODE (insn) == CALL_INSN | |
2334 | || GET_CODE (insn) == JUMP_INSN) | |
2335 | { | |
2336 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2337 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2338 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2339 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2340 | |
2341 | if (REG_NOTES (insn)) | |
f903b91f DM |
2342 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2343 | } | |
79b9ec0d RK |
2344 | |
2345 | max_parallel += max_set_parallel; | |
f903b91f DM |
2346 | } |
2347 | ||
2348 | /* Update 'regscan' information by looking at the insns | |
2349 | from FIRST to LAST. Some new REGs have been created, | |
2350 | and any REG with number greater than OLD_MAX_REGNO is | |
2351 | such a REG. We only update information for those. */ | |
2352 | ||
2353 | void | |
770ae6cc | 2354 | reg_scan_update (first, last, old_max_regno) |
f903b91f DM |
2355 | rtx first; |
2356 | rtx last; | |
770ae6cc | 2357 | unsigned int old_max_regno; |
f903b91f | 2358 | { |
b3694847 | 2359 | rtx insn; |
f903b91f DM |
2360 | |
2361 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2362 | ||
2363 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2364 | if (GET_CODE (insn) == INSN | |
2365 | || GET_CODE (insn) == CALL_INSN | |
2366 | || GET_CODE (insn) == JUMP_INSN) | |
2367 | { | |
2368 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2369 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2370 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2371 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2372 | ||
2373 | if (REG_NOTES (insn)) | |
2374 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2375 | } |
2376 | } | |
2377 | ||
1ebecb64 | 2378 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2379 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2380 | We should only record information for REGs with numbers | |
2381 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2382 | |
08d95f91 | 2383 | static void |
f903b91f | 2384 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2385 | rtx x; |
be8dcd74 | 2386 | rtx insn; |
1ebecb64 | 2387 | int note_flag; |
770ae6cc | 2388 | unsigned int min_regno; |
54dac99e | 2389 | { |
b3694847 SS |
2390 | enum rtx_code code; |
2391 | rtx dest; | |
2392 | rtx note; | |
54dac99e | 2393 | |
ed8d2920 MM |
2394 | if (!x) |
2395 | return; | |
fa23c636 | 2396 | code = GET_CODE (x); |
54dac99e RK |
2397 | switch (code) |
2398 | { | |
54dac99e | 2399 | case CONST: |
185ebd6c | 2400 | case CONST_INT: |
54dac99e | 2401 | case CONST_DOUBLE: |
69ef87e2 | 2402 | case CONST_VECTOR: |
54dac99e RK |
2403 | case CC0: |
2404 | case PC: | |
2405 | case SYMBOL_REF: | |
2406 | case LABEL_REF: | |
2407 | case ADDR_VEC: | |
2408 | case ADDR_DIFF_VEC: | |
2409 | return; | |
2410 | ||
2411 | case REG: | |
2412 | { | |
770ae6cc | 2413 | unsigned int regno = REGNO (x); |
54dac99e | 2414 | |
f903b91f DM |
2415 | if (regno >= min_regno) |
2416 | { | |
2417 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2418 | if (!note_flag) | |
2419 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2420 | if (REGNO_FIRST_UID (regno) == 0) | |
2421 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
ed8d2920 MM |
2422 | /* If we are called by reg_scan_update() (indicated by min_regno |
2423 | being set), we also need to update the reference count. */ | |
2424 | if (min_regno) | |
2425 | REG_N_REFS (regno)++; | |
f903b91f | 2426 | } |
54dac99e RK |
2427 | } |
2428 | break; | |
2429 | ||
01565a55 | 2430 | case EXPR_LIST: |
7b18c3db | 2431 | if (XEXP (x, 0)) |
f903b91f | 2432 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2433 | if (XEXP (x, 1)) |
f903b91f | 2434 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2435 | break; |
2436 | ||
2437 | case INSN_LIST: | |
2438 | if (XEXP (x, 1)) | |
f903b91f | 2439 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2440 | break; |
2441 | ||
ed8d2920 MM |
2442 | case CLOBBER: |
2443 | { | |
2444 | rtx reg = XEXP (x, 0); | |
2445 | if (REG_P (reg) | |
2446 | && REGNO (reg) >= min_regno) | |
2447 | { | |
2448 | REG_N_SETS (REGNO (reg))++; | |
2449 | REG_N_REFS (REGNO (reg))++; | |
2450 | } | |
2451 | } | |
2452 | break; | |
2453 | ||
54dac99e RK |
2454 | case SET: |
2455 | /* Count a set of the destination if it is a register. */ | |
2456 | for (dest = SET_DEST (x); | |
2457 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2458 | || GET_CODE (dest) == ZERO_EXTEND; | |
2459 | dest = XEXP (dest, 0)) | |
2460 | ; | |
2461 | ||
79b9ec0d RK |
2462 | /* For a PARALLEL, record the number of things (less the usual one for a |
2463 | SET) that are set. */ | |
2464 | if (GET_CODE (dest) == PARALLEL) | |
2465 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2466 | ||
f903b91f DM |
2467 | if (GET_CODE (dest) == REG |
2468 | && REGNO (dest) >= min_regno) | |
b2d57793 DB |
2469 | { |
2470 | REG_N_SETS (REGNO (dest))++; | |
2471 | REG_N_REFS (REGNO (dest))++; | |
2472 | } | |
54dac99e | 2473 | |
be8dcd74 RK |
2474 | /* If this is setting a pseudo from another pseudo or the sum of a |
2475 | pseudo and a constant integer and the other pseudo is known to be | |
2476 | a pointer, set the destination to be a pointer as well. | |
2477 | ||
2478 | Likewise if it is setting the destination from an address or from a | |
2479 | value equivalent to an address or to the sum of an address and | |
2480 | something else. | |
a6a2274a | 2481 | |
be8dcd74 RK |
2482 | But don't do any of this if the pseudo corresponds to a user |
2483 | variable since it should have already been set as a pointer based | |
2484 | on the type. */ | |
2485 | ||
2486 | if (GET_CODE (SET_DEST (x)) == REG | |
2487 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2488 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2489 | /* If the destination pseudo is set more than once, then other |
2490 | sets might not be to a pointer value (consider access to a | |
d55d8fc7 | 2491 | union in two threads of control in the presence of global |
3502dc9c | 2492 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2493 | pseudo if this is the only set of that pseudo. */ |
2494 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2495 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2496 | && ! REG_POINTER (SET_DEST (x)) |
be8dcd74 | 2497 | && ((GET_CODE (SET_SRC (x)) == REG |
3502dc9c | 2498 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2499 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2500 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2501 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2502 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3502dc9c | 2503 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2504 | || GET_CODE (SET_SRC (x)) == CONST |
2505 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2506 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2507 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2508 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2509 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2510 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2511 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2512 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2513 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2514 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2515 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2516 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2517 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2518 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2519 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2520 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2521 | |
0d4903b8 | 2522 | /* If this is setting a register from a register or from a simple |
a560d4d4 | 2523 | conversion of a register, propagate REG_EXPR. */ |
0d4903b8 RK |
2524 | if (GET_CODE (dest) == REG) |
2525 | { | |
2526 | rtx src = SET_SRC (x); | |
2527 | ||
2528 | while (GET_CODE (src) == SIGN_EXTEND | |
2529 | || GET_CODE (src) == ZERO_EXTEND | |
2530 | || GET_CODE (src) == TRUNCATE | |
2531 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2532 | src = XEXP (src, 0); | |
2533 | ||
a560d4d4 JH |
2534 | if (!REG_ATTRS (dest) && REG_P (src)) |
2535 | REG_ATTRS (dest) = REG_ATTRS (src); | |
2536 | if (!REG_ATTRS (dest) && GET_CODE (src) == MEM) | |
2537 | set_reg_attrs_from_mem (dest, src); | |
0d4903b8 RK |
2538 | } |
2539 | ||
0f41302f | 2540 | /* ... fall through ... */ |
54dac99e RK |
2541 | |
2542 | default: | |
2543 | { | |
b3694847 SS |
2544 | const char *fmt = GET_RTX_FORMAT (code); |
2545 | int i; | |
54dac99e RK |
2546 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2547 | { | |
2548 | if (fmt[i] == 'e') | |
f903b91f | 2549 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2550 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2551 | { | |
b3694847 | 2552 | int j; |
54dac99e | 2553 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
f903b91f | 2554 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2555 | } |
2556 | } | |
2557 | } | |
2558 | } | |
2559 | } | |
2560 | \f | |
2561 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2562 | is also in C2. */ | |
2563 | ||
2564 | int | |
2565 | reg_class_subset_p (c1, c2) | |
b3694847 SS |
2566 | enum reg_class c1; |
2567 | enum reg_class c2; | |
54dac99e RK |
2568 | { |
2569 | if (c1 == c2) return 1; | |
2570 | ||
2571 | if (c2 == ALL_REGS) | |
2572 | win: | |
2573 | return 1; | |
8e2e89f7 KH |
2574 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], |
2575 | reg_class_contents[(int) c2], | |
54dac99e RK |
2576 | win); |
2577 | return 0; | |
2578 | } | |
2579 | ||
2580 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2581 | ||
2582 | int | |
2583 | reg_classes_intersect_p (c1, c2) | |
b3694847 SS |
2584 | enum reg_class c1; |
2585 | enum reg_class c2; | |
54dac99e RK |
2586 | { |
2587 | #ifdef HARD_REG_SET | |
2588 | register | |
2589 | #endif | |
2590 | HARD_REG_SET c; | |
2591 | ||
2592 | if (c1 == c2) return 1; | |
2593 | ||
2594 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2595 | return 1; | |
2596 | ||
2597 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2598 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2599 | ||
2600 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2601 | return 1; | |
2602 | ||
2603 | lose: | |
2604 | return 0; | |
2605 | } | |
2606 | ||
73b76448 RK |
2607 | /* Release any memory allocated by register sets. */ |
2608 | ||
2609 | void | |
2610 | regset_release_memory () | |
2611 | { | |
73b76448 RK |
2612 | bitmap_release_memory (); |
2613 | } | |
e2500fed | 2614 | |
cff9f8d5 AH |
2615 | #ifdef CANNOT_CHANGE_MODE_CLASS |
2616 | /* Set bits in *USED which correspond to registers which can't change | |
2617 | their mode from FROM to any mode in which REGNO was encountered. */ | |
2618 | ||
2619 | void | |
2620 | cannot_change_mode_set_regs (used, from, regno) | |
2621 | HARD_REG_SET *used; | |
2622 | enum machine_mode from; | |
2623 | unsigned int regno; | |
2624 | { | |
2625 | enum machine_mode to; | |
2626 | enum reg_class class; | |
2627 | ||
2628 | for (to = VOIDmode; to < MAX_MACHINE_MODE; ++to) | |
2629 | if (REGNO_REG_SET_P (&subregs_of_mode[to], regno)) | |
2630 | { | |
2631 | class = CANNOT_CHANGE_MODE_CLASS (from, to); | |
2632 | if (class != NO_REGS) | |
2633 | IOR_HARD_REG_SET (*used, reg_class_contents [(int) class]); | |
2634 | } | |
2635 | } | |
2636 | ||
2637 | /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM | |
2638 | mode. */ | |
2639 | ||
2640 | bool | |
2641 | invalid_mode_change_p (regno, class, from_mode) | |
2642 | unsigned int regno; | |
2643 | enum reg_class class; | |
2644 | enum machine_mode from_mode; | |
2645 | { | |
2646 | enum machine_mode to_mode; | |
2647 | ||
2648 | for (to_mode = 0; to_mode < NUM_MACHINE_MODES; ++to_mode) | |
2649 | if (REGNO_REG_SET_P (&subregs_of_mode[(int) to_mode], regno) | |
2650 | && reg_classes_intersect_p | |
2651 | (class, CANNOT_CHANGE_MODE_CLASS (from_mode, to_mode))) | |
2652 | return 1; | |
2653 | return 0; | |
2654 | } | |
2655 | #endif /* CANNOT_CHANGE_MODE_CLASS */ | |
2656 | ||
e2500fed | 2657 | #include "gt-regclass.h" |