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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
e56b4594 | 3 | 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
54dac99e | 4 | |
1322177d | 5 | This file is part of GCC. |
54dac99e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
54dac99e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
54dac99e RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
54dac99e RK |
21 | |
22 | ||
23 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
24 | It also defines some tables of information about the hardware registers | |
25 | and a function init_reg_sets to initialize the tables. */ | |
26 | ||
27 | #include "config.h" | |
670ee920 | 28 | #include "system.h" |
54dac99e | 29 | #include "rtl.h" |
0829d244 | 30 | #include "expr.h" |
6baf1cc8 | 31 | #include "tm_p.h" |
54dac99e RK |
32 | #include "hard-reg-set.h" |
33 | #include "flags.h" | |
34 | #include "basic-block.h" | |
35 | #include "regs.h" | |
49ad7cfa | 36 | #include "function.h" |
54dac99e RK |
37 | #include "insn-config.h" |
38 | #include "recog.h" | |
e4600702 RK |
39 | #include "reload.h" |
40 | #include "real.h" | |
10f0ad3d | 41 | #include "toplev.h" |
d6f4ec51 | 42 | #include "output.h" |
8b0212ca | 43 | #include "ggc.h" |
54dac99e RK |
44 | |
45 | #ifndef REGISTER_MOVE_COST | |
e56b4594 | 46 | #define REGISTER_MOVE_COST(m, x, y) 2 |
54dac99e RK |
47 | #endif |
48 | ||
13536812 KG |
49 | static void init_reg_sets_1 PARAMS ((void)); |
50 | static void init_reg_modes PARAMS ((void)); | |
24deb20a | 51 | |
533d0835 RK |
52 | /* If we have auto-increment or auto-decrement and we can have secondary |
53 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 54 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
55 | |
56 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 57 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
58 | #define FORBIDDEN_INC_DEC_CLASSES |
59 | #endif | |
60 | #endif | |
54dac99e RK |
61 | \f |
62 | /* Register tables used by many passes. */ | |
63 | ||
64 | /* Indexed by hard register number, contains 1 for registers | |
65 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
66 | These are the registers that cannot be used to allocate | |
252f342a | 67 | a pseudo reg for general use. */ |
54dac99e RK |
68 | |
69 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
70 | ||
71 | /* Same info as a HARD_REG_SET. */ | |
72 | ||
73 | HARD_REG_SET fixed_reg_set; | |
74 | ||
75 | /* Data for initializing the above. */ | |
76 | ||
8b60264b | 77 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
54dac99e RK |
78 | |
79 | /* Indexed by hard register number, contains 1 for registers | |
80 | that are fixed use or are clobbered by function calls. | |
81 | These are the registers that cannot be used to allocate | |
252f342a MH |
82 | a pseudo reg whose life crosses calls unless we are able |
83 | to save/restore them across the calls. */ | |
54dac99e RK |
84 | |
85 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
86 | ||
87 | /* Same info as a HARD_REG_SET. */ | |
88 | ||
89 | HARD_REG_SET call_used_reg_set; | |
90 | ||
6cad67d2 JL |
91 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
92 | HARD_REG_SET losing_caller_save_reg_set; | |
93 | ||
54dac99e RK |
94 | /* Data for initializing the above. */ |
95 | ||
8b60264b | 96 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
fc1296b7 AM |
97 | |
98 | /* This is much like call_used_regs, except it doesn't have to | |
99 | be a superset of FIXED_REGISTERS. This vector indicates | |
100 | what is really call clobbered, and is used when defining | |
101 | regs_invalidated_by_call. */ | |
102 | ||
fc1296b7 | 103 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa | 104 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
fc1296b7 | 105 | #endif |
54dac99e RK |
106 | |
107 | /* Indexed by hard register number, contains 1 for registers that are | |
252f342a MH |
108 | fixed use or call used registers that cannot hold quantities across |
109 | calls even if we are willing to save and restore them. call fixed | |
110 | registers are a subset of call used registers. */ | |
54dac99e RK |
111 | |
112 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
113 | ||
114 | /* The same info as a HARD_REG_SET. */ | |
115 | ||
116 | HARD_REG_SET call_fixed_reg_set; | |
117 | ||
118 | /* Number of non-fixed registers. */ | |
119 | ||
120 | int n_non_fixed_regs; | |
121 | ||
122 | /* Indexed by hard register number, contains 1 for registers | |
123 | that are being used for global register decls. | |
124 | These must be exempt from ordinary flow analysis | |
125 | and are also considered fixed. */ | |
126 | ||
127 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
4e2db584 RH |
128 | |
129 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
130 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
131 | for someone's bright idea to have call_used_regs strictly include | |
132 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
133 | that are actually preserved. We know for sure that those associated | |
134 | with the local stack frame are safe, but scant others. */ | |
135 | ||
136 | HARD_REG_SET regs_invalidated_by_call; | |
137 | ||
54dac99e RK |
138 | /* Table of register numbers in the order in which to try to use them. */ |
139 | #ifdef REG_ALLOC_ORDER | |
140 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
141 | |
142 | /* The inverse of reg_alloc_order. */ | |
143 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
144 | #endif |
145 | ||
146 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
147 | ||
2e0e2b76 CH |
148 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
149 | ||
089e575b RS |
150 | /* The same information, but as an array of unsigned ints. We copy from |
151 | these unsigned ints to the table above. We do this so the tm.h files | |
d4845339 RH |
152 | do not have to be aware of the wordsize for machines with <= 64 regs. |
153 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
2e0e2b76 CH |
154 | |
155 | #define N_REG_INTS \ | |
d4845339 | 156 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
2e0e2b76 | 157 | |
089e575b | 158 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 159 | = REG_CLASS_CONTENTS; |
54dac99e RK |
160 | |
161 | /* For each reg class, number of regs it contains. */ | |
162 | ||
770ae6cc | 163 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
164 | |
165 | /* For each reg class, table listing all the containing classes. */ | |
166 | ||
167 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
168 | ||
169 | /* For each reg class, table listing all the classes contained in it. */ | |
170 | ||
171 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
172 | ||
173 | /* For each pair of reg classes, | |
174 | a largest reg class contained in their union. */ | |
175 | ||
176 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
177 | ||
178 | /* For each pair of reg classes, | |
179 | the smallest reg class containing their union. */ | |
180 | ||
181 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
182 | ||
fbd40359 ZW |
183 | /* Array containing all of the register names. Unless |
184 | DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ | |
d05c8ee7 | 185 | |
fbd40359 | 186 | #ifdef DEBUG_REGISTER_NAMES |
e087aeb2 | 187 | const char * reg_names[] = REGISTER_NAMES; |
fbd40359 | 188 | #endif |
d05c8ee7 | 189 | |
ca4aac00 DE |
190 | /* For each hard register, the widest mode object that it can contain. |
191 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
192 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
193 | register. */ | |
194 | ||
195 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
196 | ||
6df26b8f JH |
197 | /* 1 if class does contain register of given mode. */ |
198 | ||
199 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
200 | ||
e4600702 RK |
201 | /* Maximum cost of moving from a register in one class to a register in |
202 | another class. Based on REGISTER_MOVE_COST. */ | |
203 | ||
e56b4594 | 204 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
205 | |
206 | /* Similar, but here we don't have to move if the first index is a subset | |
207 | of the second so in that case the cost is zero. */ | |
208 | ||
e56b4594 | 209 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
210 | |
211 | /* Similar, but here we don't have to move if the first index is a superset | |
212 | of the second so in that case the cost is zero. */ | |
213 | ||
e56b4594 | 214 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 215 | |
533d0835 RK |
216 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
217 | ||
218 | /* These are the classes that regs which are auto-incremented or decremented | |
219 | cannot be put in. */ | |
220 | ||
221 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
222 | ||
223 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
224 | context. */ | |
225 | ||
226 | static char *in_inc_dec; | |
227 | ||
5fcb671c | 228 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 229 | |
02188693 | 230 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
231 | |
232 | /* These are the classes containing only registers that can be used in | |
02188693 RH |
233 | a SUBREG expression that changes the mode of the register in some |
234 | way that is illegal. */ | |
e79f71f7 | 235 | |
02188693 | 236 | static int class_can_change_mode[N_REG_CLASSES]; |
e79f71f7 | 237 | |
02188693 RH |
238 | /* Registers, including pseudos, which change modes in some way that |
239 | is illegal. */ | |
e79f71f7 | 240 | |
02188693 | 241 | static regset reg_changes_mode; |
e79f71f7 | 242 | |
02188693 | 243 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
e79f71f7 | 244 | |
473fe49b KR |
245 | #ifdef HAVE_SECONDARY_RELOADS |
246 | ||
247 | /* Sample MEM values for use by memory_move_secondary_cost. */ | |
248 | ||
249 | static rtx top_of_stack[MAX_MACHINE_MODE]; | |
250 | ||
251 | #endif /* HAVE_SECONDARY_RELOADS */ | |
252 | ||
6feacd09 MM |
253 | /* Linked list of reg_info structures allocated for reg_n_info array. |
254 | Grouping all of the allocated structures together in one lump | |
255 | means only one call to bzero to clear them, rather than n smaller | |
256 | calls. */ | |
257 | struct reg_info_data { | |
258 | struct reg_info_data *next; /* next set of reg_info structures */ | |
259 | size_t min_index; /* minimum index # */ | |
260 | size_t max_index; /* maximum index # */ | |
261 | char used_p; /* non-zero if this has been used previously */ | |
262 | reg_info data[1]; /* beginning of the reg_info data */ | |
263 | }; | |
264 | ||
265 | static struct reg_info_data *reg_info_head; | |
266 | ||
c07c7c9d | 267 | /* No more global register variables may be declared; true once |
dc297297 | 268 | regclass has been initialized. */ |
6c85df69 AH |
269 | |
270 | static int no_global_reg_vars = 0; | |
271 | ||
6feacd09 | 272 | |
54dac99e RK |
273 | /* Function called only once to initialize the above data on reg usage. |
274 | Once this is done, various switches may override. */ | |
275 | ||
276 | void | |
277 | init_reg_sets () | |
278 | { | |
279 | register int i, j; | |
280 | ||
2e0e2b76 CH |
281 | /* First copy the register information from the initial int form into |
282 | the regsets. */ | |
283 | ||
284 | for (i = 0; i < N_REG_CLASSES; i++) | |
285 | { | |
286 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
287 | ||
b85946fc | 288 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
2e0e2b76 | 289 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
b85946fc RH |
290 | if (int_reg_class_contents[i][j / 32] |
291 | & ((unsigned) 1 << (j % 32))) | |
2e0e2b76 CH |
292 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
293 | } | |
294 | ||
4e135bdd KG |
295 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
296 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 297 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 298 | |
910bc42d R |
299 | /* Do any additional initialization regsets may need */ |
300 | INIT_ONCE_REG_SET (); | |
f5d8c9f4 BS |
301 | |
302 | #ifdef REG_ALLOC_ORDER | |
303 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
304 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
305 | #endif | |
910bc42d R |
306 | } |
307 | ||
308 | /* After switches have been processed, which perhaps alter | |
309 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
310 | ||
311 | static void | |
312 | init_reg_sets_1 () | |
313 | { | |
314 | register unsigned int i, j; | |
e56b4594 | 315 | register unsigned int /* enum machine_mode */ m; |
6836e024 | 316 | char allocatable_regs_of_mode [MAX_MACHINE_MODE]; |
910bc42d R |
317 | |
318 | /* This macro allows the fixed or call-used registers | |
319 | and the register classes to depend on target flags. */ | |
320 | ||
321 | #ifdef CONDITIONAL_REGISTER_USAGE | |
322 | CONDITIONAL_REGISTER_USAGE; | |
323 | #endif | |
324 | ||
54dac99e RK |
325 | /* Compute number of hard regs in each class. */ |
326 | ||
961192e1 | 327 | memset ((char *) reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
328 | for (i = 0; i < N_REG_CLASSES; i++) |
329 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
330 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
331 | reg_class_size[i]++; | |
332 | ||
333 | /* Initialize the table of subunions. | |
334 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
335 | that is contained in the union of classes I and J. */ | |
336 | ||
337 | for (i = 0; i < N_REG_CLASSES; i++) | |
338 | { | |
339 | for (j = 0; j < N_REG_CLASSES; j++) | |
340 | { | |
341 | #ifdef HARD_REG_SET | |
342 | register /* Declare it register if it's a scalar. */ | |
343 | #endif | |
344 | HARD_REG_SET c; | |
345 | register int k; | |
346 | ||
347 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
348 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
349 | for (k = 0; k < N_REG_CLASSES; k++) | |
350 | { | |
351 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
352 | subclass1); | |
353 | continue; | |
354 | ||
355 | subclass1: | |
356 | /* keep the largest subclass */ /* SPEE 900308 */ | |
357 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
358 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
359 | subclass2); | |
360 | reg_class_subunion[i][j] = (enum reg_class) k; | |
361 | subclass2: | |
362 | ; | |
363 | } | |
364 | } | |
365 | } | |
366 | ||
367 | /* Initialize the table of superunions. | |
368 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
369 | containing the union of classes I and J. */ | |
370 | ||
371 | for (i = 0; i < N_REG_CLASSES; i++) | |
372 | { | |
373 | for (j = 0; j < N_REG_CLASSES; j++) | |
374 | { | |
375 | #ifdef HARD_REG_SET | |
376 | register /* Declare it register if it's a scalar. */ | |
377 | #endif | |
378 | HARD_REG_SET c; | |
379 | register int k; | |
380 | ||
381 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
382 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
383 | for (k = 0; k < N_REG_CLASSES; k++) | |
384 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
385 | ||
386 | superclass: | |
387 | reg_class_superunion[i][j] = (enum reg_class) k; | |
388 | } | |
389 | } | |
390 | ||
391 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
392 | First clear the whole table, then add the elements as they are found. */ | |
393 | ||
394 | for (i = 0; i < N_REG_CLASSES; i++) | |
395 | { | |
396 | for (j = 0; j < N_REG_CLASSES; j++) | |
397 | { | |
398 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
399 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
400 | } | |
401 | } | |
402 | ||
403 | for (i = 0; i < N_REG_CLASSES; i++) | |
404 | { | |
405 | if (i == (int) NO_REGS) | |
406 | continue; | |
407 | ||
408 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
409 | { | |
410 | enum reg_class *p; | |
411 | ||
412 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
413 | subclass); | |
414 | continue; | |
415 | subclass: | |
416 | /* Reg class I is a subclass of J. | |
417 | Add J to the table of superclasses of I. */ | |
418 | p = ®_class_superclasses[i][0]; | |
419 | while (*p != LIM_REG_CLASSES) p++; | |
420 | *p = (enum reg_class) j; | |
421 | /* Add I to the table of superclasses of J. */ | |
422 | p = ®_class_subclasses[j][0]; | |
423 | while (*p != LIM_REG_CLASSES) p++; | |
424 | *p = (enum reg_class) i; | |
425 | } | |
426 | } | |
e4600702 | 427 | |
54dac99e RK |
428 | /* Initialize "constant" tables. */ |
429 | ||
430 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
431 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
432 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
4e2db584 | 433 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
54dac99e | 434 | |
4e135bdd | 435 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e RK |
436 | |
437 | n_non_fixed_regs = 0; | |
438 | ||
439 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
440 | { | |
54dac99e RK |
441 | if (fixed_regs[i]) |
442 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
443 | else | |
444 | n_non_fixed_regs++; | |
445 | ||
446 | if (call_used_regs[i]) | |
447 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
448 | if (call_fixed_regs[i]) | |
449 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
450 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
451 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
4e2db584 RH |
452 | |
453 | /* There are a couple of fixed registers that we know are safe to | |
454 | exclude from being clobbered by calls: | |
455 | ||
456 | The frame pointer is always preserved across calls. The arg pointer | |
457 | is if it is fixed. The stack pointer usually is, unless | |
458 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
459 | If we are generating PIC code, the PIC offset table register is | |
460 | preserved across calls, though the target can override that. */ | |
461 | ||
462 | if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) | |
463 | ; | |
464 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
465 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
466 | ; | |
467 | #endif | |
468 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
469 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
470 | ; | |
471 | #endif | |
472 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
473 | else if (i == PIC_OFFSET_TABLE_REGNUM && flag_pic) | |
474 | ; | |
475 | #endif | |
d3259baa | 476 | else if (0 |
6ca3c22f | 477 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa RH |
478 | || call_really_used_regs[i] |
479 | #else | |
480 | || call_used_regs[i] | |
481 | #endif | |
482 | || global_regs[i]) | |
4e2db584 | 483 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
54dac99e | 484 | } |
4e2db584 | 485 | |
6836e024 JH |
486 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
487 | memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); | |
dbbbbf3b | 488 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 | 489 | for (i = 0; i < N_REG_CLASSES; i++) |
6df26b8f JH |
490 | if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
491 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
492 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
493 | && HARD_REGNO_MODE_OK (j, m)) | |
494 | { | |
495 | contains_reg_of_mode [i][m] = 1; | |
496 | allocatable_regs_of_mode [m] = 1; | |
497 | break; | |
498 | } | |
acbce667 KR |
499 | |
500 | /* Initialize the move cost table. Find every subset of each class | |
501 | and take the maximum cost of moving any subset to any other. */ | |
502 | ||
dbbbbf3b | 503 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 JH |
504 | if (allocatable_regs_of_mode [m]) |
505 | { | |
506 | for (i = 0; i < N_REG_CLASSES; i++) | |
507 | if (contains_reg_of_mode [i][m]) | |
508 | for (j = 0; j < N_REG_CLASSES; j++) | |
509 | { | |
510 | int cost; | |
511 | enum reg_class *p1, *p2; | |
512 | ||
513 | if (!contains_reg_of_mode [j][m]) | |
514 | { | |
515 | move_cost[m][i][j] = 65536; | |
516 | may_move_in_cost[m][i][j] = 65536; | |
517 | may_move_out_cost[m][i][j] = 65536; | |
518 | } | |
519 | else | |
520 | { | |
26a952a8 | 521 | cost = REGISTER_MOVE_COST (m, i, j); |
6836e024 JH |
522 | |
523 | for (p2 = ®_class_subclasses[j][0]; | |
524 | *p2 != LIM_REG_CLASSES; | |
525 | p2++) | |
526 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
527 | cost = MAX (cost, move_cost [m][i][*p2]); | |
528 | ||
529 | for (p1 = ®_class_subclasses[i][0]; | |
530 | *p1 != LIM_REG_CLASSES; | |
531 | p1++) | |
532 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
533 | cost = MAX (cost, move_cost [m][*p1][j]); | |
534 | ||
535 | move_cost[m][i][j] = cost; | |
536 | ||
537 | if (reg_class_subset_p (i, j)) | |
538 | may_move_in_cost[m][i][j] = 0; | |
539 | else | |
540 | may_move_in_cost[m][i][j] = cost; | |
541 | ||
542 | if (reg_class_subset_p (j, i)) | |
543 | may_move_out_cost[m][i][j] = 0; | |
544 | else | |
545 | may_move_out_cost[m][i][j] = cost; | |
546 | } | |
547 | } | |
1464632b | 548 | else |
6836e024 JH |
549 | for (j = 0; j < N_REG_CLASSES; j++) |
550 | { | |
551 | move_cost[m][i][j] = 65536; | |
552 | may_move_in_cost[m][i][j] = 65536; | |
553 | may_move_out_cost[m][i][j] = 65536; | |
554 | } | |
555 | } | |
e79f71f7 | 556 | |
02188693 | 557 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
558 | { |
559 | HARD_REG_SET c; | |
02188693 | 560 | COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]); |
e79f71f7 GK |
561 | |
562 | for (i = 0; i < N_REG_CLASSES; i++) | |
563 | { | |
564 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class); | |
02188693 | 565 | class_can_change_mode [i] = 0; |
e79f71f7 GK |
566 | continue; |
567 | ok_class: | |
02188693 | 568 | class_can_change_mode [i] = 1; |
e79f71f7 GK |
569 | } |
570 | } | |
02188693 | 571 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
c27c5281 DE |
572 | } |
573 | ||
574 | /* Compute the table of register modes. | |
575 | These values are used to record death information for individual registers | |
576 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 577 | |
c27c5281 DE |
578 | static void |
579 | init_reg_modes () | |
580 | { | |
581 | register int i; | |
ca4aac00 DE |
582 | |
583 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
584 | { |
585 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
586 | ||
066c2fea | 587 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
588 | ??? One situation in which we need to do this is on the mips where |
589 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
590 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 591 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 592 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 593 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 594 | } |
ca4aac00 DE |
595 | } |
596 | ||
c27c5281 DE |
597 | /* Finish initializing the register sets and |
598 | initialize the register modes. */ | |
599 | ||
600 | void | |
601 | init_regs () | |
602 | { | |
603 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
604 | until after register usage was specified. */ | |
b93a436e | 605 | init_reg_sets_1 (); |
c27c5281 DE |
606 | |
607 | init_reg_modes (); | |
473fe49b KR |
608 | |
609 | #ifdef HAVE_SECONDARY_RELOADS | |
610 | { | |
611 | /* Make some fake stack-frame MEM references for use in | |
612 | memory_move_secondary_cost. */ | |
613 | int i; | |
d067e2aa | 614 | |
473fe49b | 615 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 616 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
00d33cb2 | 617 | ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE); |
473fe49b KR |
618 | } |
619 | #endif | |
c27c5281 DE |
620 | } |
621 | ||
cbd5b9a2 | 622 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 623 | |
cbd5b9a2 KR |
624 | /* Compute extra cost of moving registers to/from memory due to reloads. |
625 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 626 | |
cbd5b9a2 KR |
627 | int |
628 | memory_move_secondary_cost (mode, class, in) | |
629 | enum machine_mode mode; | |
630 | enum reg_class class; | |
631 | int in; | |
632 | { | |
633 | enum reg_class altclass; | |
634 | int partial_cost = 0; | |
cbd5b9a2 | 635 | /* We need a memory reference to feed to SECONDARY... macros. */ |
dc297297 | 636 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
272df862 KG |
637 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
638 | ||
cbd5b9a2 KR |
639 | |
640 | if (in) | |
473fe49b | 641 | { |
321c0828 | 642 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 643 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 644 | #else |
473fe49b | 645 | altclass = NO_REGS; |
321c0828 | 646 | #endif |
473fe49b | 647 | } |
cbd5b9a2 | 648 | else |
473fe49b | 649 | { |
321c0828 | 650 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 651 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 652 | #else |
473fe49b | 653 | altclass = NO_REGS; |
321c0828 | 654 | #endif |
473fe49b KR |
655 | } |
656 | ||
cbd5b9a2 KR |
657 | if (altclass == NO_REGS) |
658 | return 0; | |
659 | ||
660 | if (in) | |
e56b4594 | 661 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 662 | else |
e56b4594 | 663 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
664 | |
665 | if (class == altclass) | |
666 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
667 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
668 | here in that case. | |
669 | ||
670 | I'm tempted to put in an abort here, but returning this will | |
671 | probably only give poor estimates, which is what we would've | |
672 | had before this code anyways. */ | |
673 | return partial_cost; | |
674 | ||
675 | /* Check if the secondary reload register will also need a | |
676 | secondary reload. */ | |
677 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
678 | } | |
679 | #endif | |
680 | ||
ca4aac00 DE |
681 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
682 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
683 | ||
684 | enum machine_mode | |
685 | choose_hard_reg_mode (regno, nregs) | |
770ae6cc RK |
686 | unsigned int regno ATTRIBUTE_UNUSED; |
687 | unsigned int nregs; | |
ca4aac00 | 688 | { |
dbbbbf3b | 689 | unsigned int /* enum machine_mode */ m; |
ca4aac00 DE |
690 | enum machine_mode found_mode = VOIDmode, mode; |
691 | ||
692 | /* We first look for the largest integer mode that can be validly | |
693 | held in REGNO. If none, we look for the largest floating-point mode. | |
694 | If we still didn't find a valid mode, try CCmode. */ | |
695 | ||
696 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
697 | mode != VOIDmode; | |
698 | mode = GET_MODE_WIDER_MODE (mode)) | |
699 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
700 | && HARD_REGNO_MODE_OK (regno, mode)) | |
701 | found_mode = mode; | |
702 | ||
703 | if (found_mode != VOIDmode) | |
704 | return found_mode; | |
705 | ||
706 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
707 | mode != VOIDmode; | |
708 | mode = GET_MODE_WIDER_MODE (mode)) | |
709 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
710 | && HARD_REGNO_MODE_OK (regno, mode)) | |
711 | found_mode = mode; | |
712 | ||
713 | if (found_mode != VOIDmode) | |
714 | return found_mode; | |
715 | ||
0548a9df | 716 | /* Iterate over all of the CCmodes. */ |
dbbbbf3b JDA |
717 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
718 | { | |
719 | mode = (enum machine_mode) m; | |
720 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
721 | && HARD_REGNO_MODE_OK (regno, mode)) | |
722 | return mode; | |
723 | } | |
ca4aac00 DE |
724 | |
725 | /* We can't find a mode valid for this register. */ | |
726 | return VOIDmode; | |
54dac99e RK |
727 | } |
728 | ||
729 | /* Specify the usage characteristics of the register named NAME. | |
730 | It should be a fixed register if FIXED and a | |
731 | call-used register if CALL_USED. */ | |
732 | ||
733 | void | |
734 | fix_register (name, fixed, call_used) | |
ec0ce6e2 | 735 | const char *name; |
54dac99e RK |
736 | int fixed, call_used; |
737 | { | |
738 | int i; | |
739 | ||
740 | /* Decode the name and update the primary form of | |
741 | the register info. */ | |
742 | ||
e5c90c23 TW |
743 | if ((i = decode_reg_name (name)) >= 0) |
744 | { | |
cb2fdc84 GRK |
745 | if ((i == STACK_POINTER_REGNUM |
746 | #ifdef HARD_FRAME_POINTER_REGNUM | |
747 | || i == HARD_FRAME_POINTER_REGNUM | |
748 | #else | |
749 | || i == FRAME_POINTER_REGNUM | |
750 | #endif | |
751 | ) | |
752 | && (fixed == 0 || call_used == 0)) | |
753 | { | |
6f7d635c | 754 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
755 | { "call-saved", "call-used" }, |
756 | { "no-such-option", "fixed" }}; | |
cb2fdc84 GRK |
757 | |
758 | error ("can't use '%s' as a %s register", name, | |
759 | what_option[fixed][call_used]); | |
760 | } | |
761 | else | |
762 | { | |
763 | fixed_regs[i] = fixed; | |
764 | call_used_regs[i] = call_used; | |
ec523c2f | 765 | #ifdef CALL_REALLY_USED_REGISTERS |
fc1296b7 AM |
766 | if (fixed == 0) |
767 | call_really_used_regs[i] = call_used; | |
d3259baa | 768 | #endif |
cb2fdc84 | 769 | } |
e5c90c23 TW |
770 | } |
771 | else | |
54dac99e RK |
772 | { |
773 | warning ("unknown register name: %s", name); | |
54dac99e RK |
774 | } |
775 | } | |
614f68e2 RK |
776 | |
777 | /* Mark register number I as global. */ | |
778 | ||
779 | void | |
780 | globalize_reg (i) | |
781 | int i; | |
782 | { | |
c07c7c9d | 783 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
784 | error ("global register variable follows a function definition"); |
785 | ||
614f68e2 RK |
786 | if (global_regs[i]) |
787 | { | |
788 | warning ("register used for two global register variables"); | |
789 | return; | |
790 | } | |
791 | ||
792 | if (call_used_regs[i] && ! fixed_regs[i]) | |
793 | warning ("call-clobbered register used for global register variable"); | |
794 | ||
795 | global_regs[i] = 1; | |
796 | ||
797 | /* If already fixed, nothing else to do. */ | |
798 | if (fixed_regs[i]) | |
799 | return; | |
800 | ||
801 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
802 | n_non_fixed_regs--; | |
803 | ||
804 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
805 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
806 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
807 | } | |
54dac99e RK |
808 | \f |
809 | /* Now the data and code for the `regclass' pass, which happens | |
810 | just before local-alloc. */ | |
811 | ||
e4600702 RK |
812 | /* The `costs' struct records the cost of using a hard register of each class |
813 | and of using memory for each pseudo. We use this data to set up | |
814 | register class preferences. */ | |
54dac99e | 815 | |
e4600702 | 816 | struct costs |
54dac99e | 817 | { |
e4600702 RK |
818 | int cost[N_REG_CLASSES]; |
819 | int mem_cost; | |
54dac99e RK |
820 | }; |
821 | ||
9ffc5a70 JH |
822 | /* Structure used to record preferrences of given pseudo. */ |
823 | struct reg_pref | |
824 | { | |
825 | /* (enum reg_class) prefclass is the preferred class. */ | |
826 | char prefclass; | |
827 | ||
828 | /* altclass is a register class that we should use for allocating | |
829 | pseudo if no register in the preferred class is available. | |
830 | If no register in this class is available, memory is preferred. | |
831 | ||
832 | It might appear to be more general to have a bitmask of classes here, | |
833 | but since it is recommended that there be a class corresponding to the | |
834 | union of most major pair of classes, that generality is not required. */ | |
835 | char altclass; | |
836 | }; | |
837 | ||
e4600702 RK |
838 | /* Record the cost of each class for each pseudo. */ |
839 | ||
840 | static struct costs *costs; | |
841 | ||
61719ba7 BS |
842 | /* Initialized once, and used to initialize cost values for each insn. */ |
843 | ||
844 | static struct costs init_cost; | |
845 | ||
9ffc5a70 | 846 | /* Record preferrences of each pseudo. |
54dac99e RK |
847 | This is available after `regclass' is run. */ |
848 | ||
9ffc5a70 | 849 | static struct reg_pref *reg_pref; |
54d23420 | 850 | |
dc297297 | 851 | /* Allocated buffers for reg_pref. */ |
54dac99e | 852 | |
9ffc5a70 | 853 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 854 | |
9401afe3 | 855 | /* Frequency of executions of current insn. */ |
54d23420 | 856 | |
9401afe3 | 857 | static int frequency; |
54d23420 | 858 | |
13536812 KG |
859 | static rtx scan_one_insn PARAMS ((rtx, int)); |
860 | static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); | |
861 | static void dump_regclass PARAMS ((FILE *)); | |
862 | static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, | |
e79f71f7 | 863 | const char **, rtx, |
f741a71c | 864 | struct costs *, struct reg_pref *)); |
13536812 | 865 | static int copy_cost PARAMS ((rtx, enum machine_mode, |
08d95f91 | 866 | enum reg_class, int)); |
13536812 | 867 | static void record_address_regs PARAMS ((rtx, enum reg_class, int)); |
1d300e19 | 868 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
13536812 | 869 | static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); |
1d300e19 | 870 | #endif |
770ae6cc | 871 | static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); |
54dac99e RK |
872 | |
873 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
874 | This function is sometimes called before the info has been computed. | |
875 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
876 | ||
877 | enum reg_class | |
878 | reg_preferred_class (regno) | |
879 | int regno; | |
880 | { | |
9ffc5a70 | 881 | if (reg_pref == 0) |
54dac99e | 882 | return GENERAL_REGS; |
9ffc5a70 | 883 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
884 | } |
885 | ||
e4600702 RK |
886 | enum reg_class |
887 | reg_alternate_class (regno) | |
b729186a | 888 | int regno; |
54dac99e | 889 | { |
9ffc5a70 | 890 | if (reg_pref == 0) |
e4600702 RK |
891 | return ALL_REGS; |
892 | ||
9ffc5a70 | 893 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
894 | } |
895 | ||
61719ba7 | 896 | /* Initialize some global data for this pass. */ |
54dac99e RK |
897 | |
898 | void | |
899 | regclass_init () | |
900 | { | |
61719ba7 BS |
901 | int i; |
902 | ||
903 | init_cost.mem_cost = 10000; | |
904 | for (i = 0; i < N_REG_CLASSES; i++) | |
905 | init_cost.cost[i] = 10000; | |
906 | ||
907 | /* This prevents dump_flow_info from losing if called | |
908 | before regclass is run. */ | |
9ffc5a70 | 909 | reg_pref = NULL; |
6c85df69 | 910 | |
dc297297 | 911 | /* No more global register variables may be declared. */ |
6c85df69 | 912 | no_global_reg_vars = 1; |
54dac99e | 913 | } |
246fd41f JH |
914 | \f |
915 | /* Dump register costs. */ | |
915b80ed | 916 | static void |
246fd41f JH |
917 | dump_regclass (dump) |
918 | FILE *dump; | |
919 | { | |
920 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
921 | int i; | |
922 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
923 | { | |
dbbbbf3b | 924 | int /* enum reg_class */ class; |
246fd41f JH |
925 | if (REG_N_REFS (i)) |
926 | { | |
f741a71c | 927 | fprintf (dump, " Register %i costs:", i); |
dbbbbf3b JDA |
928 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
929 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
6df26b8f | 930 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
dbbbbf3b JDA |
931 | && (!in_inc_dec[i] |
932 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
6df26b8f JH |
933 | #endif |
934 | #ifdef CLASS_CANNOT_CHANGE_MODE | |
935 | && (!REGNO_REG_SET_P (reg_changes_mode, i) | |
dbbbbf3b | 936 | || class_can_change_mode [(enum reg_class) class]) |
6df26b8f JH |
937 | #endif |
938 | ) | |
dbbbbf3b JDA |
939 | fprintf (dump, " %s:%i", reg_class_names[class], |
940 | costs[i].cost[(enum reg_class) class]); | |
f741a71c | 941 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
942 | } |
943 | } | |
944 | } | |
f741a71c JH |
945 | \f |
946 | ||
947 | /* Calculate the costs of insn operands. */ | |
948 | ||
949 | static void | |
950 | record_operand_costs (insn, op_costs, reg_pref) | |
951 | rtx insn; | |
952 | struct costs *op_costs; | |
953 | struct reg_pref *reg_pref; | |
954 | { | |
955 | const char *constraints[MAX_RECOG_OPERANDS]; | |
956 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
957 | int i; |
958 | ||
959 | for (i = 0; i < recog_data.n_operands; i++) | |
960 | { | |
961 | constraints[i] = recog_data.constraints[i]; | |
962 | modes[i] = recog_data.operand_mode[i]; | |
963 | } | |
f741a71c JH |
964 | |
965 | /* If we get here, we are set up to record the costs of all the | |
966 | operands for this insn. Start by initializing the costs. | |
967 | Then handle any address registers. Finally record the desired | |
968 | classes for any pseudos, doing it twice if some pair of | |
969 | operands are commutative. */ | |
970 | ||
971 | for (i = 0; i < recog_data.n_operands; i++) | |
972 | { | |
973 | op_costs[i] = init_cost; | |
974 | ||
975 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
976 | { | |
977 | rtx inner = SUBREG_REG (recog_data.operand[i]); | |
02188693 RH |
978 | #ifdef CLASS_CANNOT_CHANGE_MODE |
979 | if (GET_CODE (inner) == REG | |
980 | && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner))) | |
981 | SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner)); | |
9ef07cf1 | 982 | #endif |
f741a71c JH |
983 | recog_data.operand[i] = inner; |
984 | } | |
985 | ||
986 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
987 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
9401afe3 | 988 | BASE_REG_CLASS, frequency * 2); |
f741a71c JH |
989 | else if (constraints[i][0] == 'p') |
990 | record_address_regs (recog_data.operand[i], | |
9401afe3 | 991 | BASE_REG_CLASS, frequency * 2); |
f741a71c JH |
992 | } |
993 | ||
994 | /* Check for commutative in a separate loop so everything will | |
995 | have been initialized. We must do this even if one operand | |
996 | is a constant--see addsi3 in m68k.md. */ | |
997 | ||
998 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
999 | if (constraints[i][0] == '%') | |
1000 | { | |
1001 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1002 | int j; | |
246fd41f | 1003 | |
f741a71c JH |
1004 | /* Handle commutative operands by swapping the constraints. |
1005 | We assume the modes are the same. */ | |
1006 | ||
1007 | for (j = 0; j < recog_data.n_operands; j++) | |
1008 | xconstraints[j] = constraints[j]; | |
1009 | ||
1010 | xconstraints[i] = constraints[i+1]; | |
1011 | xconstraints[i+1] = constraints[i]; | |
1012 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
e79f71f7 | 1013 | recog_data.operand, modes, |
f741a71c JH |
1014 | xconstraints, insn, op_costs, reg_pref); |
1015 | } | |
1016 | ||
1017 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
e79f71f7 | 1018 | recog_data.operand, modes, |
f741a71c JH |
1019 | constraints, insn, op_costs, reg_pref); |
1020 | } | |
54dac99e | 1021 | \f |
61719ba7 BS |
1022 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1023 | time it would save code to put a certain register in a certain class. | |
1024 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1025 | once. | |
1026 | Return the last insn processed, so that the scan can be continued from | |
1027 | there. */ | |
1028 | ||
1029 | static rtx | |
1030 | scan_one_insn (insn, pass) | |
1031 | rtx insn; | |
1032 | int pass; | |
1033 | { | |
1034 | enum rtx_code code = GET_CODE (insn); | |
1035 | enum rtx_code pat_code; | |
0eadeb15 | 1036 | rtx set, note; |
61719ba7 | 1037 | int i, j; |
f741a71c | 1038 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 1039 | |
61719ba7 BS |
1040 | if (GET_RTX_CLASS (code) != 'i') |
1041 | return insn; | |
1042 | ||
1043 | pat_code = GET_CODE (PATTERN (insn)); | |
1044 | if (pat_code == USE | |
1045 | || pat_code == CLOBBER | |
1046 | || pat_code == ASM_INPUT | |
1047 | || pat_code == ADDR_VEC | |
1048 | || pat_code == ADDR_DIFF_VEC) | |
1049 | return insn; | |
1050 | ||
0eadeb15 BS |
1051 | set = single_set (insn); |
1052 | extract_insn (insn); | |
1053 | ||
0eadeb15 BS |
1054 | /* If this insn loads a parameter from its stack slot, then |
1055 | it represents a savings, rather than a cost, if the | |
1056 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 1057 | |
0eadeb15 BS |
1058 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
1059 | && GET_CODE (SET_SRC (set)) == MEM | |
1060 | && (note = find_reg_note (insn, REG_EQUIV, | |
1061 | NULL_RTX)) != 0 | |
1062 | && GET_CODE (XEXP (note, 0)) == MEM) | |
1063 | { | |
1064 | costs[REGNO (SET_DEST (set))].mem_cost | |
1065 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1066 | GENERAL_REGS, 1) | |
9401afe3 | 1067 | * frequency); |
0eadeb15 | 1068 | record_address_regs (XEXP (SET_SRC (set), 0), |
9401afe3 | 1069 | BASE_REG_CLASS, frequency * 2); |
0eadeb15 BS |
1070 | return insn; |
1071 | } | |
61719ba7 | 1072 | |
0eadeb15 BS |
1073 | /* Improve handling of two-address insns such as |
1074 | (set X (ashift CONST Y)) where CONST must be made to | |
1075 | match X. Change it into two insns: (set X CONST) | |
1076 | (set X (ashift X Y)). If we left this for reloading, it | |
1077 | would probably get three insns because X and Y might go | |
1078 | in the same place. This prevents X and Y from receiving | |
1079 | the same hard reg. | |
1080 | ||
1081 | We can only do this if the modes of operands 0 and 1 | |
1082 | (which might not be the same) are tieable and we only need | |
1083 | do this during our first pass. */ | |
1084 | ||
1085 | if (pass == 0 && optimize | |
1ccbefce RH |
1086 | && recog_data.n_operands >= 3 |
1087 | && recog_data.constraints[1][0] == '0' | |
1088 | && recog_data.constraints[1][1] == 0 | |
1089 | && CONSTANT_P (recog_data.operand[1]) | |
1090 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1091 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
1092 | && GET_CODE (recog_data.operand[0]) == REG | |
1093 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
1094 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
1095 | { |
1096 | rtx previnsn = prev_real_insn (insn); | |
1097 | rtx dest | |
1ccbefce RH |
1098 | = gen_lowpart (recog_data.operand_mode[1], |
1099 | recog_data.operand[0]); | |
0eadeb15 | 1100 | rtx newinsn |
1ccbefce | 1101 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 1102 | |
0eadeb15 BS |
1103 | /* If this insn was the start of a basic block, |
1104 | include the new insn in that block. | |
1105 | We need not check for code_label here; | |
1106 | while a basic block can start with a code_label, | |
1107 | INSN could not be at the beginning of that block. */ | |
1108 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 1109 | { |
0eadeb15 BS |
1110 | int b; |
1111 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 RH |
1112 | if (insn == BLOCK_HEAD (b)) |
1113 | BLOCK_HEAD (b) = newinsn; | |
61719ba7 BS |
1114 | } |
1115 | ||
0eadeb15 | 1116 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1117 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d3c7d45e | 1118 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1119 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
61719ba7 | 1120 | |
1ccbefce | 1121 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d3c7d45e | 1122 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1123 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
1ccbefce RH |
1124 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1125 | if (recog_data.dup_num[i] == 1) | |
d3c7d45e AO |
1126 | { |
1127 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1128 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
9401afe3 | 1129 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d3c7d45e | 1130 | } |
61719ba7 | 1131 | |
0eadeb15 | 1132 | return PREV_INSN (newinsn); |
61719ba7 BS |
1133 | } |
1134 | ||
4963c995 | 1135 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1136 | |
1137 | /* Now add the cost for each operand to the total costs for | |
1138 | its register. */ | |
1139 | ||
1ccbefce RH |
1140 | for (i = 0; i < recog_data.n_operands; i++) |
1141 | if (GET_CODE (recog_data.operand[i]) == REG | |
1142 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 1143 | { |
1ccbefce | 1144 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1145 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1146 | ||
9401afe3 | 1147 | p->mem_cost += q->mem_cost * frequency; |
61719ba7 | 1148 | for (j = 0; j < N_REG_CLASSES; j++) |
9401afe3 | 1149 | p->cost[j] += q->cost[j] * frequency; |
61719ba7 BS |
1150 | } |
1151 | ||
1152 | return insn; | |
1153 | } | |
1154 | ||
54dac99e RK |
1155 | /* This is a pass of the compiler that scans all instructions |
1156 | and calculates the preferred class for each pseudo-register. | |
1157 | This information can be accessed later by calling `reg_preferred_class'. | |
1158 | This pass comes just before local register allocation. */ | |
1159 | ||
1160 | void | |
246fd41f | 1161 | regclass (f, nregs, dump) |
54dac99e RK |
1162 | rtx f; |
1163 | int nregs; | |
246fd41f | 1164 | FILE *dump; |
54dac99e | 1165 | { |
54dac99e | 1166 | register rtx insn; |
61719ba7 | 1167 | register int i; |
e4600702 | 1168 | int pass; |
54dac99e RK |
1169 | |
1170 | init_recog (); | |
1171 | ||
56a65848 | 1172 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 | 1173 | |
02188693 RH |
1174 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1175 | reg_changes_mode = BITMAP_XMALLOC(); | |
e79f71f7 GK |
1176 | #endif |
1177 | ||
533d0835 RK |
1178 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1179 | ||
4da896b2 | 1180 | in_inc_dec = (char *) xmalloc (nregs); |
533d0835 RK |
1181 | |
1182 | /* Initialize information about which register classes can be used for | |
1183 | pseudos that are auto-incremented or auto-decremented. It would | |
1184 | seem better to put this in init_reg_sets, but we need to be able | |
1185 | to allocate rtx, which we can't do that early. */ | |
1186 | ||
1187 | for (i = 0; i < N_REG_CLASSES; i++) | |
1188 | { | |
38a448ca | 1189 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 | 1190 | enum machine_mode m; |
8c368ee2 | 1191 | register int j; |
533d0835 RK |
1192 | |
1193 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1194 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1195 | { | |
1196 | REGNO (r) = j; | |
1197 | ||
1198 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1199 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1200 | if (HARD_REGNO_MODE_OK (j, m)) |
1201 | { | |
1202 | PUT_MODE (r, m); | |
08d95f91 RK |
1203 | |
1204 | /* If a register is not directly suitable for an | |
1205 | auto-increment or decrement addressing mode and | |
1206 | requires secondary reloads, disallow its class from | |
1207 | being used in such addresses. */ | |
1208 | ||
1209 | if ((0 | |
041d7180 JL |
1210 | #ifdef SECONDARY_RELOAD_CLASS |
1211 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
1212 | != NO_REGS) | |
1213 | #else | |
533d0835 | 1214 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
1215 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1216 | != NO_REGS) | |
533d0835 RK |
1217 | #endif |
1218 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
1219 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1220 | != NO_REGS) | |
041d7180 | 1221 | #endif |
533d0835 | 1222 | #endif |
08d95f91 RK |
1223 | ) |
1224 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1225 | forbidden_inc_dec_class[i] = 1; |
1226 | } | |
1227 | } | |
1228 | } | |
1229 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1230 | ||
e4600702 RK |
1231 | /* Normally we scan the insns once and determine the best class to use for |
1232 | each register. However, if -fexpensive_optimizations are on, we do so | |
1233 | twice, the second time using the tentative best classes to guide the | |
1234 | selection. */ | |
54dac99e | 1235 | |
e4600702 RK |
1236 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1237 | { | |
954d8e99 | 1238 | int index; |
f741a71c JH |
1239 | |
1240 | if (dump) | |
1241 | fprintf (dump, "\n\nPass %i\n\n",pass); | |
e4600702 | 1242 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1243 | |
961192e1 | 1244 | memset ((char *) costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1245 | |
533d0835 | 1246 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1247 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1248 | #endif |
1249 | ||
e4600702 RK |
1250 | /* Scan the instructions and record each time it would |
1251 | save code to put a certain register in a certain class. */ | |
1252 | ||
1f01879e | 1253 | if (!optimize) |
54dac99e | 1254 | { |
a08b2604 | 1255 | frequency = REG_FREQ_MAX; |
1f01879e JH |
1256 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1257 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1258 | } |
1f01879e JH |
1259 | else |
1260 | for (index = 0; index < n_basic_blocks; index++) | |
1261 | { | |
1262 | basic_block bb = BASIC_BLOCK (index); | |
1263 | ||
1264 | /* Show that an insn inside a loop is likely to be executed three | |
9b15c17f RH |
1265 | times more than insns outside a loop. This is much more |
1266 | aggressive than the assumptions made elsewhere and is being | |
1267 | tried as an experiment. */ | |
a08b2604 | 1268 | frequency = REG_FREQ_FROM_BB (bb); |
1f01879e JH |
1269 | for (insn = bb->head; ; insn = NEXT_INSN (insn)) |
1270 | { | |
1271 | insn = scan_one_insn (insn, pass); | |
1272 | if (insn == bb->end) | |
1273 | break; | |
1274 | } | |
1275 | } | |
61719ba7 | 1276 | |
e4600702 RK |
1277 | /* Now for each register look at how desirable each class is |
1278 | and find which class is preferred. Store that in | |
9ffc5a70 | 1279 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1280 | class any of whose registers is better than memory. */ |
54dac99e | 1281 | |
e4600702 | 1282 | if (pass == 0) |
9ffc5a70 | 1283 | reg_pref = reg_pref_buffer; |
54dac99e | 1284 | |
f741a71c JH |
1285 | if (dump) |
1286 | { | |
1287 | dump_regclass (dump); | |
4963c995 | 1288 | fprintf (dump,"\n"); |
f741a71c | 1289 | } |
e4600702 | 1290 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1291 | { |
ca3c6eae | 1292 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1293 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1294 | /* This is an enum reg_class, but we call it an int | |
1295 | to save lots of casts. */ | |
1296 | register int class; | |
1297 | register struct costs *p = &costs[i]; | |
1298 | ||
64615302 JH |
1299 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1300 | yet. */ | |
1301 | if (optimize && !REG_N_REFS (i)) | |
f741a71c JH |
1302 | continue; |
1303 | ||
e4600702 | 1304 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1305 | { |
533d0835 RK |
1306 | /* Ignore classes that are too small for this operand or |
1307 | invalid for a operand that was auto-incremented. */ | |
6df26b8f | 1308 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
533d0835 RK |
1309 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1310 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1311 | #endif |
02188693 RH |
1312 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1313 | || (REGNO_REG_SET_P (reg_changes_mode, i) | |
1314 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1315 | #endif |
1316 | ) | |
e4600702 RK |
1317 | ; |
1318 | else if (p->cost[class] < best_cost) | |
1319 | { | |
1320 | best_cost = p->cost[class]; | |
1321 | best = (enum reg_class) class; | |
1322 | } | |
1323 | else if (p->cost[class] == best_cost) | |
1324 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 1325 | } |
54dac99e | 1326 | |
e4600702 RK |
1327 | /* Record the alternate register class; i.e., a class for which |
1328 | every register in it is better than using memory. If adding a | |
1329 | class would make a smaller class (i.e., no union of just those | |
1330 | classes exists), skip that class. The major unions of classes | |
1331 | should be provided as a register class. Don't do this if we | |
1332 | will be doing it again later. */ | |
1333 | ||
f741a71c | 1334 | if ((pass == 1 || dump) || ! flag_expensive_optimizations) |
e4600702 RK |
1335 | for (class = 0; class < N_REG_CLASSES; class++) |
1336 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1337 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1338 | > reg_class_size[(int) alt]) |
1339 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1340 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1341 | #endif |
02188693 RH |
1342 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1343 | && ! (REGNO_REG_SET_P (reg_changes_mode, i) | |
1344 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1345 | #endif |
1346 | ) | |
e4600702 RK |
1347 | alt = reg_class_subunion[(int) alt][class]; |
1348 | ||
1349 | /* If we don't add any classes, nothing to try. */ | |
1350 | if (alt == best) | |
995d54dd | 1351 | alt = NO_REGS; |
e4600702 | 1352 | |
f741a71c JH |
1353 | if (dump |
1354 | && (reg_pref[i].prefclass != (int) best | |
1355 | || reg_pref[i].altclass != (int) alt)) | |
1356 | { | |
1357 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
4963c995 | 1358 | fprintf (dump, " Register %i", i); |
f741a71c JH |
1359 | if (alt == ALL_REGS || best == ALL_REGS) |
1360 | fprintf (dump, " pref %s\n", reg_class_names[(int) best]); | |
1361 | else if (alt == NO_REGS) | |
1362 | fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); | |
1363 | else | |
1364 | fprintf (dump, " pref %s, else %s\n", | |
1365 | reg_class_names[(int) best], | |
1366 | reg_class_names[(int) alt]); | |
1367 | } | |
1368 | ||
e4600702 | 1369 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1370 | reg_pref[i].prefclass = (int) best; |
1371 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1372 | } |
54dac99e | 1373 | } |
56a65848 | 1374 | |
4da896b2 MM |
1375 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1376 | free (in_inc_dec); | |
e79f71f7 | 1377 | #endif |
02188693 RH |
1378 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1379 | BITMAP_XFREE (reg_changes_mode); | |
4da896b2 | 1380 | #endif |
56a65848 | 1381 | free (costs); |
54dac99e RK |
1382 | } |
1383 | \f | |
e4600702 RK |
1384 | /* Record the cost of using memory or registers of various classes for |
1385 | the operands in INSN. | |
54dac99e | 1386 | |
e4600702 | 1387 | N_ALTS is the number of alternatives. |
54dac99e | 1388 | |
e4600702 RK |
1389 | N_OPS is the number of operands. |
1390 | ||
1391 | OPS is an array of the operands. | |
1392 | ||
1393 | MODES are the modes of the operands, in case any are VOIDmode. | |
1394 | ||
1395 | CONSTRAINTS are the constraints to use for the operands. This array | |
1396 | is modified by this procedure. | |
1397 | ||
1398 | This procedure works alternative by alternative. For each alternative | |
1399 | we assume that we will be able to allocate all pseudos to their ideal | |
1400 | register class and calculate the cost of using that alternative. Then | |
1401 | we compute for each operand that is a pseudo-register, the cost of | |
1402 | having the pseudo allocated to each register class and using it in that | |
1403 | alternative. To this cost is added the cost of the alternative. | |
1404 | ||
1405 | The cost of each class for this insn is its lowest cost among all the | |
1406 | alternatives. */ | |
1407 | ||
1408 | static void | |
e79f71f7 | 1409 | record_reg_classes (n_alts, n_ops, ops, modes, |
f741a71c | 1410 | constraints, insn, op_costs, reg_pref) |
e4600702 RK |
1411 | int n_alts; |
1412 | int n_ops; | |
1413 | rtx *ops; | |
1414 | enum machine_mode *modes; | |
9b3142b3 | 1415 | const char **constraints; |
e4600702 | 1416 | rtx insn; |
f741a71c JH |
1417 | struct costs *op_costs; |
1418 | struct reg_pref *reg_pref; | |
54dac99e | 1419 | { |
e4600702 | 1420 | int alt; |
e4600702 | 1421 | int i, j; |
ec2d92af | 1422 | rtx set; |
e4600702 | 1423 | |
e4600702 RK |
1424 | /* Process each alternative, each time minimizing an operand's cost with |
1425 | the cost for each operand in that alternative. */ | |
54dac99e | 1426 | |
e4600702 | 1427 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1428 | { |
e4600702 RK |
1429 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1430 | int alt_fail = 0; | |
1431 | int alt_cost = 0; | |
1432 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1433 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1434 | int class; |
54dac99e | 1435 | |
e4600702 RK |
1436 | for (i = 0; i < n_ops; i++) |
1437 | { | |
9b3142b3 | 1438 | const char *p = constraints[i]; |
e4600702 RK |
1439 | rtx op = ops[i]; |
1440 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1441 | int allows_addr = 0; |
e4600702 | 1442 | int win = 0; |
e51712db | 1443 | unsigned char c; |
54dac99e | 1444 | |
7405d9a1 DE |
1445 | /* Initially show we know nothing about the register class. */ |
1446 | classes[i] = NO_REGS; | |
da2c0219 | 1447 | allows_mem[i] = 0; |
7405d9a1 | 1448 | |
e4600702 RK |
1449 | /* If this operand has no constraints at all, we can conclude |
1450 | nothing about it since anything is valid. */ | |
54dac99e | 1451 | |
e4600702 RK |
1452 | if (*p == 0) |
1453 | { | |
1454 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
961192e1 | 1455 | memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1456 | |
e4600702 RK |
1457 | continue; |
1458 | } | |
54dac99e | 1459 | |
7405d9a1 DE |
1460 | /* If this alternative is only relevant when this operand |
1461 | matches a previous operand, we do different things depending | |
1462 | on whether this operand is a pseudo-reg or not. We must process | |
1463 | any modifiers for the operand before we can make this test. */ | |
1464 | ||
8c368ee2 | 1465 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1466 | p++; |
8c368ee2 | 1467 | |
e4600702 RK |
1468 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1469 | { | |
da2c0219 RK |
1470 | /* Copy class and whether memory is allowed from the matching |
1471 | alternative. Then perform any needed cost computations | |
1472 | and/or adjustments. */ | |
e4600702 RK |
1473 | j = p[0] - '0'; |
1474 | classes[i] = classes[j]; | |
da2c0219 | 1475 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1476 | |
1477 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1478 | { | |
1479 | /* If this matches the other operand, we have no added | |
dc903608 | 1480 | cost and we win. */ |
e4600702 | 1481 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1482 | win = 1; |
e4600702 | 1483 | |
77e67eac RK |
1484 | /* If we can put the other operand into a register, add to |
1485 | the cost of this alternative the cost to copy this | |
1486 | operand to the register used for the other operand. */ | |
e4600702 | 1487 | |
dc903608 | 1488 | else if (classes[j] != NO_REGS) |
77e67eac | 1489 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1490 | } |
07d8ca2d RS |
1491 | else if (GET_CODE (ops[j]) != REG |
1492 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1493 | { | |
1494 | /* This op is a pseudo but the one it matches is not. */ | |
1495 | ||
1496 | /* If we can't put the other operand into a register, this | |
1497 | alternative can't be used. */ | |
1498 | ||
1499 | if (classes[j] == NO_REGS) | |
1500 | alt_fail = 1; | |
e4600702 | 1501 | |
07d8ca2d RS |
1502 | /* Otherwise, add to the cost of this alternative the cost |
1503 | to copy the other operand to the register used for this | |
1504 | operand. */ | |
1505 | ||
1506 | else | |
1507 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1508 | } | |
e4600702 RK |
1509 | else |
1510 | { | |
da2c0219 RK |
1511 | /* The costs of this operand are not the same as the other |
1512 | operand since move costs are not symmetric. Moreover, | |
1513 | if we cannot tie them, this alternative needs to do a | |
1514 | copy, which is one instruction. */ | |
1515 | ||
1516 | struct costs *pp = &this_op_costs[i]; | |
1517 | ||
1518 | for (class = 0; class < N_REG_CLASSES; class++) | |
1519 | pp->cost[class] | |
d5e2075d | 1520 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1521 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1522 | : 0) |
1523 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1524 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1525 | : 0)); |
da2c0219 RK |
1526 | |
1527 | /* If the alternative actually allows memory, make things | |
1528 | a bit cheaper since we won't need an extra insn to | |
1529 | load it. */ | |
1530 | ||
1531 | pp->mem_cost | |
d5e2075d JH |
1532 | = ((recog_data.operand_type[i] != OP_IN |
1533 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1534 | : 0) | |
1535 | + (recog_data.operand_type[i] != OP_OUT | |
1536 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1537 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1538 | |
1539 | /* If we have assigned a class to this register in our | |
1540 | first pass, add a cost to this alternative corresponding | |
1541 | to what we would add if this register were not in the | |
1542 | appropriate class. */ | |
1543 | ||
9ffc5a70 | 1544 | if (reg_pref) |
da2c0219 | 1545 | alt_cost |
e56b4594 AO |
1546 | += (may_move_in_cost[mode] |
1547 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1548 | [(int) classes[i]]); |
e4600702 | 1549 | |
37747c82 RK |
1550 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1551 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1552 | alt_cost += 2; | |
e4600702 | 1553 | |
347099d6 | 1554 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1555 | for this operand, so skip to the end of the |
1556 | alternative (should be just one character). */ | |
1557 | while (*p && *p++ != ',') | |
1558 | ; | |
1559 | ||
1560 | constraints[i] = p; | |
347099d6 RS |
1561 | continue; |
1562 | } | |
e4600702 RK |
1563 | } |
1564 | ||
1565 | /* Scan all the constraint letters. See if the operand matches | |
1566 | any of the constraints. Collect the valid register classes | |
1567 | and see if this operand accepts memory. */ | |
1568 | ||
e4600702 RK |
1569 | while (*p && (c = *p++) != ',') |
1570 | switch (c) | |
1571 | { | |
e4600702 RK |
1572 | case '*': |
1573 | /* Ignore the next letter for this pass. */ | |
1574 | p++; | |
1575 | break; | |
1576 | ||
812f2051 R |
1577 | case '?': |
1578 | alt_cost += 2; | |
8c368ee2 | 1579 | case '!': case '#': case '&': |
e4600702 | 1580 | case '0': case '1': case '2': case '3': case '4': |
8c368ee2 | 1581 | case '5': case '6': case '7': case '8': case '9': |
94e6f783 DE |
1582 | break; |
1583 | ||
e4600702 | 1584 | case 'p': |
94e6f783 DE |
1585 | allows_addr = 1; |
1586 | win = address_operand (op, GET_MODE (op)); | |
46f40127 JL |
1587 | /* We know this operand is an address, so we want it to be |
1588 | allocated to a register that can be the base of an | |
1589 | address, ie BASE_REG_CLASS. */ | |
1590 | classes[i] | |
1591 | = reg_class_subunion[(int) classes[i]] | |
1592 | [(int) BASE_REG_CLASS]; | |
e4600702 RK |
1593 | break; |
1594 | ||
1595 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1596 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 | 1597 | and non-offsettable addresses here. */ |
da2c0219 | 1598 | allows_mem[i] = 1; |
e4600702 RK |
1599 | if (GET_CODE (op) == MEM) |
1600 | win = 1; | |
1601 | break; | |
1602 | ||
1603 | case '<': | |
1604 | if (GET_CODE (op) == MEM | |
1605 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1606 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1607 | win = 1; | |
1608 | break; | |
1609 | ||
1610 | case '>': | |
1611 | if (GET_CODE (op) == MEM | |
1612 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1613 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1614 | win = 1; | |
1615 | break; | |
1616 | ||
1617 | case 'E': | |
7ac2547f | 1618 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1619 | /* Match any floating double constant, but only if |
1620 | we can examine the bits of it reliably. */ | |
1621 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1622 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1623 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1624 | break; | |
7ac2547f | 1625 | #endif |
e4600702 RK |
1626 | if (GET_CODE (op) == CONST_DOUBLE) |
1627 | win = 1; | |
1628 | break; | |
1629 | ||
1630 | case 'F': | |
1631 | if (GET_CODE (op) == CONST_DOUBLE) | |
1632 | win = 1; | |
1633 | break; | |
1634 | ||
1635 | case 'G': | |
1636 | case 'H': | |
1637 | if (GET_CODE (op) == CONST_DOUBLE | |
1638 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1639 | win = 1; | |
1640 | break; | |
1641 | ||
1642 | case 's': | |
1643 | if (GET_CODE (op) == CONST_INT | |
1644 | || (GET_CODE (op) == CONST_DOUBLE | |
1645 | && GET_MODE (op) == VOIDmode)) | |
1646 | break; | |
1647 | case 'i': | |
1648 | if (CONSTANT_P (op) | |
1649 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1650 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1651 | #endif | |
1652 | ) | |
1653 | win = 1; | |
1654 | break; | |
1655 | ||
1656 | case 'n': | |
1657 | if (GET_CODE (op) == CONST_INT | |
1658 | || (GET_CODE (op) == CONST_DOUBLE | |
1659 | && GET_MODE (op) == VOIDmode)) | |
1660 | win = 1; | |
1661 | break; | |
1662 | ||
1663 | case 'I': | |
1664 | case 'J': | |
1665 | case 'K': | |
1666 | case 'L': | |
1667 | case 'M': | |
1668 | case 'N': | |
1669 | case 'O': | |
1670 | case 'P': | |
1671 | if (GET_CODE (op) == CONST_INT | |
1672 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1673 | win = 1; | |
1674 | break; | |
1675 | ||
1676 | case 'X': | |
1677 | win = 1; | |
1678 | break; | |
54dac99e | 1679 | |
e4600702 RK |
1680 | case 'g': |
1681 | if (GET_CODE (op) == MEM | |
1682 | || (CONSTANT_P (op) | |
1683 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1684 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1685 | #endif |
e4600702 RK |
1686 | )) |
1687 | win = 1; | |
da2c0219 | 1688 | allows_mem[i] = 1; |
e4600702 RK |
1689 | case 'r': |
1690 | classes[i] | |
1691 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1692 | break; | |
1693 | ||
1694 | default: | |
c2cba7a9 RH |
1695 | if (REG_CLASS_FROM_LETTER (c) != NO_REGS) |
1696 | classes[i] | |
1697 | = reg_class_subunion[(int) classes[i]] | |
1698 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1699 | #ifdef EXTRA_CONSTRAINT | |
1700 | else if (EXTRA_CONSTRAINT (op, c)) | |
1701 | win = 1; | |
1702 | #endif | |
1703 | break; | |
e4600702 RK |
1704 | } |
1705 | ||
1706 | constraints[i] = p; | |
1707 | ||
1708 | /* How we account for this operand now depends on whether it is a | |
1709 | pseudo register or not. If it is, we first check if any | |
1710 | register classes are valid. If not, we ignore this alternative, | |
1711 | since we want to assume that all pseudos get allocated for | |
1712 | register preferencing. If some register class is valid, compute | |
1713 | the costs of moving the pseudo into that class. */ | |
1714 | ||
1715 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1716 | { |
e4600702 | 1717 | if (classes[i] == NO_REGS) |
94e6f783 | 1718 | { |
e79f71f7 GK |
1719 | /* We must always fail if the operand is a REG, but |
1720 | we did not find a suitable class. | |
1721 | ||
1722 | Otherwise we may perform an uninitialized read | |
1723 | from this_op_costs after the `continue' statement | |
1724 | below. */ | |
1725 | alt_fail = 1; | |
94e6f783 | 1726 | } |
e4600702 RK |
1727 | else |
1728 | { | |
1729 | struct costs *pp = &this_op_costs[i]; | |
1730 | ||
1731 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1732 | pp->cost[class] |
d5e2075d | 1733 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1734 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1735 | : 0) |
1736 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1737 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1738 | : 0)); |
e4600702 RK |
1739 | |
1740 | /* If the alternative actually allows memory, make things | |
1741 | a bit cheaper since we won't need an extra insn to | |
1742 | load it. */ | |
1743 | ||
14a774a9 | 1744 | pp->mem_cost |
d5e2075d JH |
1745 | = ((recog_data.operand_type[i] != OP_IN |
1746 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1747 | : 0) | |
1748 | + (recog_data.operand_type[i] != OP_OUT | |
1749 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1750 | : 0) - allows_mem[i]); | |
e4600702 RK |
1751 | |
1752 | /* If we have assigned a class to this register in our | |
1753 | first pass, add a cost to this alternative corresponding | |
1754 | to what we would add if this register were not in the | |
1755 | appropriate class. */ | |
1756 | ||
9ffc5a70 | 1757 | if (reg_pref) |
e4600702 | 1758 | alt_cost |
e56b4594 AO |
1759 | += (may_move_in_cost[mode] |
1760 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1761 | [(int) classes[i]]); |
e4600702 | 1762 | } |
4db18574 | 1763 | } |
54dac99e | 1764 | |
e4600702 RK |
1765 | /* Otherwise, if this alternative wins, either because we |
1766 | have already determined that or if we have a hard register of | |
1767 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1768 | |
e4600702 RK |
1769 | else if (win |
1770 | || (GET_CODE (op) == REG | |
6f654776 | 1771 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1772 | ; |
54dac99e | 1773 | |
e4600702 RK |
1774 | /* If registers are valid, the cost of this alternative includes |
1775 | copying the object to and/or from a register. */ | |
54dac99e | 1776 | |
e4600702 RK |
1777 | else if (classes[i] != NO_REGS) |
1778 | { | |
1ccbefce | 1779 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1780 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1781 | |
1ccbefce | 1782 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1783 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1784 | } | |
54dac99e | 1785 | |
e4600702 RK |
1786 | /* The only other way this alternative can be used is if this is a |
1787 | constant that could be placed into memory. */ | |
1788 | ||
da2c0219 | 1789 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1790 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1791 | else |
1792 | alt_fail = 1; | |
1793 | } | |
1794 | ||
1795 | if (alt_fail) | |
1796 | continue; | |
1797 | ||
1798 | /* Finally, update the costs with the information we've calculated | |
1799 | about this alternative. */ | |
1800 | ||
1801 | for (i = 0; i < n_ops; i++) | |
1802 | if (GET_CODE (ops[i]) == REG | |
1803 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1804 | { |
e4600702 | 1805 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1806 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1807 | |
e4600702 RK |
1808 | pp->mem_cost = MIN (pp->mem_cost, |
1809 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1810 | |
e4600702 RK |
1811 | for (class = 0; class < N_REG_CLASSES; class++) |
1812 | pp->cost[class] = MIN (pp->cost[class], | |
1813 | (qq->cost[class] + alt_cost) * scale); | |
1814 | } | |
1815 | } | |
ec2d92af RK |
1816 | |
1817 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1818 | and one operand is a pseudo with the other a hard reg or a pseudo |
1819 | that prefers a register that is in its own register class then | |
1820 | we may want to adjust the cost of that register class to -1. | |
1821 | ||
1822 | Avoid the adjustment if the source does not die to avoid stressing of | |
1823 | register allocator by preferrencing two coliding registers into single | |
1824 | class. | |
1825 | ||
1826 | Also avoid the adjustment if a copy between registers of the class | |
1827 | is expensive (ten times the cost of a default copy is considered | |
1828 | arbitrarily expensive). This avoids losing when the preferred class | |
1829 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1830 | |
1831 | if ((set = single_set (insn)) != 0 | |
1832 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
0dc0641b JH |
1833 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG |
1834 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
ec2d92af RK |
1835 | for (i = 0; i <= 1; i++) |
1836 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1837 | { | |
770ae6cc | 1838 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1839 | enum machine_mode mode = GET_MODE (ops[!i]); |
1840 | int class; | |
770ae6cc | 1841 | unsigned int nr; |
ec2d92af | 1842 | |
accef103 JL |
1843 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1844 | { | |
1845 | enum reg_class pref = reg_pref[regno].prefclass; | |
1846 | ||
1847 | if ((reg_class_size[(unsigned char) pref] | |
1848 | == CLASS_MAX_NREGS (pref, mode)) | |
e56b4594 | 1849 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1850 | op_costs[i].cost[(unsigned char) pref] = -1; |
1851 | } | |
ec2d92af RK |
1852 | else if (regno < FIRST_PSEUDO_REGISTER) |
1853 | for (class = 0; class < N_REG_CLASSES; class++) | |
1854 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1855 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1856 | { |
1857 | if (reg_class_size[class] == 1) | |
1858 | op_costs[i].cost[class] = -1; | |
1859 | else | |
1860 | { | |
770ae6cc | 1861 | for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++) |
4841ba4b | 1862 | { |
770ae6cc RK |
1863 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1864 | regno + nr)) | |
4841ba4b RK |
1865 | break; |
1866 | } | |
1867 | ||
770ae6cc | 1868 | if (nr == HARD_REGNO_NREGS (regno,mode)) |
4841ba4b RK |
1869 | op_costs[i].cost[class] = -1; |
1870 | } | |
1871 | } | |
ec2d92af | 1872 | } |
54dac99e | 1873 | } |
e4600702 RK |
1874 | \f |
1875 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1876 | TO_P is zero) a register of class CLASS in mode MODE. | |
1877 | ||
1878 | X must not be a pseudo. */ | |
1879 | ||
1880 | static int | |
1881 | copy_cost (x, mode, class, to_p) | |
1882 | rtx x; | |
d0af450d | 1883 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e4600702 | 1884 | enum reg_class class; |
d0af450d | 1885 | int to_p ATTRIBUTE_UNUSED; |
e4600702 | 1886 | { |
29a82058 | 1887 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1888 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1889 | #endif |
e4600702 RK |
1890 | |
1891 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1892 | assuming optimal allocation. */ | |
1893 | ||
1894 | if (GET_CODE (x) == SCRATCH) | |
1895 | return 0; | |
1896 | ||
1897 | /* Get the class we will actually use for a reload. */ | |
1898 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1899 | ||
1900 | #ifdef HAVE_SECONDARY_RELOADS | |
1901 | /* If we need a secondary reload (we assume here that we are using | |
1902 | the secondary reload as an intermediate, not a scratch register), the | |
1903 | cost is that to load the input into the intermediate register, then | |
1904 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1905 | ||
1906 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1907 | if (to_p == 1) | |
1908 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1909 | #endif | |
1910 | ||
dd9f0e8f | 1911 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1912 | if (! to_p) |
1913 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1914 | #endif | |
1915 | ||
1916 | if (secondary_class != NO_REGS) | |
e56b4594 | 1917 | return (move_cost[mode][(int) secondary_class][(int) class] |
e4600702 | 1918 | + copy_cost (x, mode, secondary_class, 2)); |
dd9f0e8f | 1919 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1920 | |
1921 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1922 | cost to move between the register classes, and use 2 for everything | |
1923 | else (constants). */ | |
1924 | ||
1925 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1926 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1927 | |
e4600702 | 1928 | else if (GET_CODE (x) == REG) |
e56b4594 | 1929 | return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
e4600702 RK |
1930 | |
1931 | else | |
1932 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
b437f1a7 | 1933 | return COSTS_N_INSNS (1); |
e4600702 RK |
1934 | } |
1935 | \f | |
54dac99e RK |
1936 | /* Record the pseudo registers we must reload into hard registers |
1937 | in a subexpression of a memory address, X. | |
e4600702 RK |
1938 | |
1939 | CLASS is the class that the register needs to be in and is either | |
1940 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1941 | ||
1942 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1943 | can represent half-cost adjustments). */ | |
54dac99e | 1944 | |
197d6480 | 1945 | static void |
e4600702 | 1946 | record_address_regs (x, class, scale) |
54dac99e | 1947 | rtx x; |
e4600702 RK |
1948 | enum reg_class class; |
1949 | int scale; | |
54dac99e RK |
1950 | { |
1951 | register enum rtx_code code = GET_CODE (x); | |
1952 | ||
1953 | switch (code) | |
1954 | { | |
1955 | case CONST_INT: | |
1956 | case CONST: | |
1957 | case CC0: | |
1958 | case PC: | |
1959 | case SYMBOL_REF: | |
1960 | case LABEL_REF: | |
1961 | return; | |
1962 | ||
1963 | case PLUS: | |
1964 | /* When we have an address that is a sum, | |
1965 | we must determine whether registers are "base" or "index" regs. | |
1966 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1967 | the "base". Luckily, we can use the REG_POINTER to make a good |
1968 | choice most of the time. We only need to do this on machines | |
1969 | that can have two registers in an address and where the base | |
1970 | and index register classes are different. | |
e4600702 RK |
1971 | |
1972 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1973 | that seems bogus since it should only be set when we are sure | |
1974 | the register is being used as a pointer. */ | |
1975 | ||
54dac99e RK |
1976 | { |
1977 | rtx arg0 = XEXP (x, 0); | |
1978 | rtx arg1 = XEXP (x, 1); | |
1979 | register enum rtx_code code0 = GET_CODE (arg0); | |
1980 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1981 | |
1982 | /* Look inside subregs. */ | |
e4600702 | 1983 | if (code0 == SUBREG) |
54dac99e | 1984 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1985 | if (code1 == SUBREG) |
54dac99e RK |
1986 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1987 | ||
e4600702 RK |
1988 | /* If this machine only allows one register per address, it must |
1989 | be in the first operand. */ | |
1990 | ||
1991 | if (MAX_REGS_PER_ADDRESS == 1) | |
1992 | record_address_regs (arg0, class, scale); | |
1993 | ||
1994 | /* If index and base registers are the same on this machine, just | |
1995 | record registers in any non-constant operands. We assume here, | |
1996 | as well as in the tests below, that all addresses are in | |
1997 | canonical form. */ | |
1998 | ||
1999 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 2000 | { |
e4600702 RK |
2001 | record_address_regs (arg0, class, scale); |
2002 | if (! CONSTANT_P (arg1)) | |
2003 | record_address_regs (arg1, class, scale); | |
54dac99e | 2004 | } |
e4600702 RK |
2005 | |
2006 | /* If the second operand is a constant integer, it doesn't change | |
2007 | what class the first operand must be. */ | |
2008 | ||
2009 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
2010 | record_address_regs (arg0, class, scale); | |
2011 | ||
2012 | /* If the second operand is a symbolic constant, the first operand | |
2013 | must be an index register. */ | |
2014 | ||
2015 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
2016 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
2017 | ||
956d6950 JL |
2018 | /* If both operands are registers but one is already a hard register |
2019 | of index or base class, give the other the class that the hard | |
2020 | register is not. */ | |
2021 | ||
3f9e9508 | 2022 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
2023 | else if (code0 == REG && code1 == REG |
2024 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
2025 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
2026 | record_address_regs (arg1, | |
2027 | REG_OK_FOR_BASE_P (arg0) | |
2028 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
2029 | scale); | |
2030 | else if (code0 == REG && code1 == REG | |
2031 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
2032 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
2033 | record_address_regs (arg0, | |
2034 | REG_OK_FOR_BASE_P (arg1) | |
2035 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
2036 | scale); | |
3f9e9508 | 2037 | #endif |
956d6950 | 2038 | |
e9a25f70 JL |
2039 | /* If one operand is known to be a pointer, it must be the base |
2040 | with the other operand the index. Likewise if the other operand | |
2041 | is a MULT. */ | |
f22376c7 | 2042 | |
3502dc9c | 2043 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 2044 | || code1 == MULT) |
f22376c7 CI |
2045 | { |
2046 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
2047 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
2048 | } | |
3502dc9c | 2049 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 2050 | || code0 == MULT) |
f22376c7 CI |
2051 | { |
2052 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
2053 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
2054 | } | |
2055 | ||
e9a25f70 | 2056 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
2057 | or index register. This case should be rare. */ |
2058 | ||
e9a25f70 | 2059 | else |
54dac99e | 2060 | { |
e4600702 RK |
2061 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
2062 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
2063 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
2064 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 2065 | } |
54dac99e RK |
2066 | } |
2067 | break; | |
2068 | ||
4b983fdc RH |
2069 | /* Double the importance of a pseudo register that is incremented |
2070 | or decremented, since it would take two extra insns | |
2071 | if it ends up in the wrong place. */ | |
2072 | case POST_MODIFY: | |
2073 | case PRE_MODIFY: | |
2074 | record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale); | |
2075 | if (REG_P (XEXP (XEXP (x, 1), 1))) | |
2076 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
2077 | INDEX_REG_CLASS, 2 * scale); | |
2078 | break; | |
2079 | ||
54dac99e RK |
2080 | case POST_INC: |
2081 | case PRE_INC: | |
2082 | case POST_DEC: | |
2083 | case PRE_DEC: | |
2084 | /* Double the importance of a pseudo register that is incremented | |
2085 | or decremented, since it would take two extra insns | |
533d0835 RK |
2086 | if it ends up in the wrong place. If the operand is a pseudo, |
2087 | show it is being used in an INC_DEC context. */ | |
2088 | ||
2089 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2090 | if (GET_CODE (XEXP (x, 0)) == REG | |
2091 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
2092 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2093 | #endif | |
e4600702 RK |
2094 | |
2095 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
2096 | break; |
2097 | ||
2098 | case REG: | |
2099 | { | |
e4600702 RK |
2100 | register struct costs *pp = &costs[REGNO (x)]; |
2101 | register int i; | |
54dac99e | 2102 | |
cbd5b9a2 | 2103 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 2104 | |
e4600702 | 2105 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 2106 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
2107 | } |
2108 | break; | |
2109 | ||
2110 | default: | |
2111 | { | |
6f7d635c | 2112 | register const char *fmt = GET_RTX_FORMAT (code); |
54dac99e RK |
2113 | register int i; |
2114 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2115 | if (fmt[i] == 'e') | |
e4600702 | 2116 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
2117 | } |
2118 | } | |
2119 | } | |
08d95f91 RK |
2120 | \f |
2121 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2122 | ||
2123 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2124 | to an object of MODE. */ | |
2125 | ||
1d300e19 | 2126 | static int |
08d95f91 RK |
2127 | auto_inc_dec_reg_p (reg, mode) |
2128 | rtx reg; | |
2129 | enum machine_mode mode; | |
2130 | { | |
940da324 JL |
2131 | if (HAVE_POST_INCREMENT |
2132 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2133 | return 1; |
08d95f91 | 2134 | |
940da324 JL |
2135 | if (HAVE_POST_DECREMENT |
2136 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2137 | return 1; |
08d95f91 | 2138 | |
940da324 JL |
2139 | if (HAVE_PRE_INCREMENT |
2140 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2141 | return 1; |
08d95f91 | 2142 | |
940da324 JL |
2143 | if (HAVE_PRE_DECREMENT |
2144 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2145 | return 1; |
08d95f91 RK |
2146 | |
2147 | return 0; | |
2148 | } | |
2149 | #endif | |
b1f21e0a | 2150 | \f |
da668e9c MM |
2151 | static short *renumber; |
2152 | static size_t regno_allocated; | |
2153 | static unsigned int reg_n_max; | |
ed396e68 | 2154 | |
b1f21e0a MM |
2155 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2156 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
2157 | NEW_P is non zero, initialize all of the registers, otherwise only |
2158 | initialize the new registers allocated. The same table is kept from | |
2159 | function to function, only reallocating it when we need more room. If | |
2160 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
2161 | |
2162 | void | |
39379e67 | 2163 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 2164 | size_t num_regs; |
b1f21e0a | 2165 | int new_p; |
39379e67 | 2166 | int renumber_p; |
b1f21e0a | 2167 | { |
6feacd09 MM |
2168 | size_t size_info; |
2169 | size_t size_renumber; | |
2170 | size_t min = (new_p) ? 0 : reg_n_max; | |
2171 | struct reg_info_data *reg_data; | |
39379e67 | 2172 | |
b1f21e0a MM |
2173 | if (num_regs > regno_allocated) |
2174 | { | |
6feacd09 MM |
2175 | size_t old_allocated = regno_allocated; |
2176 | ||
b1f21e0a | 2177 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
2178 | size_renumber = regno_allocated * sizeof (short); |
2179 | ||
2180 | if (!reg_n_info) | |
2181 | { | |
6feacd09 | 2182 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 2183 | renumber = (short *) xmalloc (size_renumber); |
9ffc5a70 JH |
2184 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
2185 | * sizeof (struct reg_pref)); | |
39379e67 MM |
2186 | } |
2187 | ||
2188 | else | |
2189 | { | |
6feacd09 MM |
2190 | VARRAY_GROW (reg_n_info, regno_allocated); |
2191 | ||
2192 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
2193 | { | |
2194 | free ((char *)renumber); | |
9ffc5a70 | 2195 | free ((char *)reg_pref); |
6feacd09 | 2196 | renumber = (short *) xmalloc (size_renumber); |
9ffc5a70 JH |
2197 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
2198 | * sizeof (struct reg_pref)); | |
6feacd09 MM |
2199 | } |
2200 | ||
2201 | else | |
2202 | { | |
2203 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
9ffc5a70 JH |
2204 | reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer, |
2205 | regno_allocated | |
2206 | * sizeof (struct reg_pref)); | |
6feacd09 | 2207 | } |
39379e67 | 2208 | } |
6feacd09 MM |
2209 | |
2210 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2211 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
2212 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
2213 | reg_data->min_index = old_allocated; | |
2214 | reg_data->max_index = regno_allocated - 1; | |
2215 | reg_data->next = reg_info_head; | |
2216 | reg_info_head = reg_data; | |
b1f21e0a MM |
2217 | } |
2218 | ||
6feacd09 | 2219 | reg_n_max = num_regs; |
b1f21e0a MM |
2220 | if (min < num_regs) |
2221 | { | |
6feacd09 MM |
2222 | /* Loop through each of the segments allocated for the actual |
2223 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
da668e9c MM |
2224 | for (reg_data = reg_info_head; |
2225 | reg_data && reg_data->max_index >= min; | |
2226 | reg_data = reg_data->next) | |
39379e67 | 2227 | { |
6feacd09 MM |
2228 | size_t min_index = reg_data->min_index; |
2229 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2230 | size_t max = MIN (max_index, num_regs); |
2231 | size_t local_min = min - min_index; | |
2232 | size_t i; | |
6feacd09 | 2233 | |
da668e9c MM |
2234 | if (reg_data->min_index > num_regs) |
2235 | continue; | |
6feacd09 | 2236 | |
da668e9c MM |
2237 | if (min < min_index) |
2238 | local_min = 0; | |
2239 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2240 | reg_data->used_p = 1; /* no need to zero */ | |
2241 | else | |
961192e1 | 2242 | memset ((char *) ®_data->data[local_min], 0, |
da668e9c MM |
2243 | sizeof (reg_info) * (max - min_index - local_min + 1)); |
2244 | ||
2245 | for (i = min_index+local_min; i <= max; i++) | |
2246 | { | |
2247 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2248 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2249 | renumber[i] = -1; | |
2250 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2251 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2252 | } |
39379e67 | 2253 | } |
b1f21e0a MM |
2254 | } |
2255 | ||
6feacd09 MM |
2256 | /* If {pref,alt}class have already been allocated, update the pointers to |
2257 | the newly realloced ones. */ | |
9ffc5a70 JH |
2258 | if (reg_pref) |
2259 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2260 | |
39379e67 MM |
2261 | if (renumber_p) |
2262 | reg_renumber = renumber; | |
2263 | ||
73b76448 RK |
2264 | /* Tell the regset code about the new number of registers */ |
2265 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
2266 | } |
2267 | ||
ed396e68 BS |
2268 | /* Free up the space allocated by allocate_reg_info. */ |
2269 | void | |
2270 | free_reg_info () | |
2271 | { | |
2272 | if (reg_n_info) | |
2273 | { | |
2274 | struct reg_info_data *reg_data; | |
2275 | struct reg_info_data *reg_next; | |
2276 | ||
2277 | VARRAY_FREE (reg_n_info); | |
2278 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2279 | { | |
2280 | reg_next = reg_data->next; | |
2281 | free ((char *)reg_data); | |
2282 | } | |
2283 | ||
9ffc5a70 JH |
2284 | free (reg_pref_buffer); |
2285 | reg_pref_buffer = (struct reg_pref *)0; | |
ed396e68 BS |
2286 | reg_info_head = (struct reg_info_data *)0; |
2287 | renumber = (short *)0; | |
2288 | } | |
2289 | regno_allocated = 0; | |
2290 | reg_n_max = 0; | |
2291 | } | |
54dac99e RK |
2292 | \f |
2293 | /* This is the `regscan' pass of the compiler, run just before cse | |
2294 | and again just before loop. | |
2295 | ||
2296 | It finds the first and last use of each pseudo-register | |
2297 | and records them in the vectors regno_first_uid, regno_last_uid | |
2298 | and counts the number of sets in the vector reg_n_sets. | |
2299 | ||
2300 | REPEAT is nonzero the second time this is called. */ | |
2301 | ||
54dac99e | 2302 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2303 | Always at least 3, since the combiner could put that many together |
79b9ec0d RK |
2304 | and we want this to remain correct for all the remaining passes. |
2305 | This corresponds to the maximum number of times note_stores will call | |
2306 | a function for any insn. */ | |
54dac99e RK |
2307 | |
2308 | int max_parallel; | |
2309 | ||
79b9ec0d RK |
2310 | /* Used as a temporary to record the largest number of registers in |
2311 | PARALLEL in a SET_DEST. This is added to max_parallel. */ | |
2312 | ||
2313 | static int max_set_parallel; | |
2314 | ||
54dac99e RK |
2315 | void |
2316 | reg_scan (f, nregs, repeat) | |
2317 | rtx f; | |
770ae6cc | 2318 | unsigned int nregs; |
272df862 | 2319 | int repeat ATTRIBUTE_UNUSED; |
54dac99e RK |
2320 | { |
2321 | register rtx insn; | |
2322 | ||
39379e67 | 2323 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e | 2324 | max_parallel = 3; |
79b9ec0d | 2325 | max_set_parallel = 0; |
54dac99e RK |
2326 | |
2327 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2328 | if (GET_CODE (insn) == INSN | |
2329 | || GET_CODE (insn) == CALL_INSN | |
2330 | || GET_CODE (insn) == JUMP_INSN) | |
2331 | { | |
2332 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2333 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2334 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2335 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2336 | |
2337 | if (REG_NOTES (insn)) | |
f903b91f DM |
2338 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2339 | } | |
79b9ec0d RK |
2340 | |
2341 | max_parallel += max_set_parallel; | |
f903b91f DM |
2342 | } |
2343 | ||
2344 | /* Update 'regscan' information by looking at the insns | |
2345 | from FIRST to LAST. Some new REGs have been created, | |
2346 | and any REG with number greater than OLD_MAX_REGNO is | |
2347 | such a REG. We only update information for those. */ | |
2348 | ||
2349 | void | |
770ae6cc | 2350 | reg_scan_update (first, last, old_max_regno) |
f903b91f DM |
2351 | rtx first; |
2352 | rtx last; | |
770ae6cc | 2353 | unsigned int old_max_regno; |
f903b91f DM |
2354 | { |
2355 | register rtx insn; | |
2356 | ||
2357 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2358 | ||
2359 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2360 | if (GET_CODE (insn) == INSN | |
2361 | || GET_CODE (insn) == CALL_INSN | |
2362 | || GET_CODE (insn) == JUMP_INSN) | |
2363 | { | |
2364 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2365 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2366 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2367 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2368 | ||
2369 | if (REG_NOTES (insn)) | |
2370 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2371 | } |
2372 | } | |
2373 | ||
1ebecb64 | 2374 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2375 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2376 | We should only record information for REGs with numbers | |
2377 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2378 | |
08d95f91 | 2379 | static void |
f903b91f | 2380 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2381 | rtx x; |
be8dcd74 | 2382 | rtx insn; |
1ebecb64 | 2383 | int note_flag; |
770ae6cc | 2384 | unsigned int min_regno; |
54dac99e | 2385 | { |
fa23c636 | 2386 | register enum rtx_code code; |
54dac99e | 2387 | register rtx dest; |
be8dcd74 | 2388 | register rtx note; |
54dac99e | 2389 | |
fa23c636 | 2390 | code = GET_CODE (x); |
54dac99e RK |
2391 | switch (code) |
2392 | { | |
54dac99e | 2393 | case CONST: |
185ebd6c | 2394 | case CONST_INT: |
54dac99e RK |
2395 | case CONST_DOUBLE: |
2396 | case CC0: | |
2397 | case PC: | |
2398 | case SYMBOL_REF: | |
2399 | case LABEL_REF: | |
2400 | case ADDR_VEC: | |
2401 | case ADDR_DIFF_VEC: | |
2402 | return; | |
2403 | ||
2404 | case REG: | |
2405 | { | |
770ae6cc | 2406 | unsigned int regno = REGNO (x); |
54dac99e | 2407 | |
f903b91f DM |
2408 | if (regno >= min_regno) |
2409 | { | |
2410 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2411 | if (!note_flag) | |
2412 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2413 | if (REGNO_FIRST_UID (regno) == 0) | |
2414 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
2415 | } | |
54dac99e RK |
2416 | } |
2417 | break; | |
2418 | ||
01565a55 | 2419 | case EXPR_LIST: |
7b18c3db | 2420 | if (XEXP (x, 0)) |
f903b91f | 2421 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2422 | if (XEXP (x, 1)) |
f903b91f | 2423 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2424 | break; |
2425 | ||
2426 | case INSN_LIST: | |
2427 | if (XEXP (x, 1)) | |
f903b91f | 2428 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2429 | break; |
2430 | ||
54dac99e RK |
2431 | case SET: |
2432 | /* Count a set of the destination if it is a register. */ | |
2433 | for (dest = SET_DEST (x); | |
2434 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2435 | || GET_CODE (dest) == ZERO_EXTEND; | |
2436 | dest = XEXP (dest, 0)) | |
2437 | ; | |
2438 | ||
79b9ec0d RK |
2439 | /* For a PARALLEL, record the number of things (less the usual one for a |
2440 | SET) that are set. */ | |
2441 | if (GET_CODE (dest) == PARALLEL) | |
2442 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2443 | ||
f903b91f DM |
2444 | if (GET_CODE (dest) == REG |
2445 | && REGNO (dest) >= min_regno) | |
b2d57793 DB |
2446 | { |
2447 | REG_N_SETS (REGNO (dest))++; | |
2448 | REG_N_REFS (REGNO (dest))++; | |
2449 | } | |
54dac99e | 2450 | |
be8dcd74 RK |
2451 | /* If this is setting a pseudo from another pseudo or the sum of a |
2452 | pseudo and a constant integer and the other pseudo is known to be | |
2453 | a pointer, set the destination to be a pointer as well. | |
2454 | ||
2455 | Likewise if it is setting the destination from an address or from a | |
2456 | value equivalent to an address or to the sum of an address and | |
2457 | something else. | |
2458 | ||
2459 | But don't do any of this if the pseudo corresponds to a user | |
2460 | variable since it should have already been set as a pointer based | |
2461 | on the type. */ | |
2462 | ||
2463 | if (GET_CODE (SET_DEST (x)) == REG | |
2464 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2465 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2466 | /* If the destination pseudo is set more than once, then other |
2467 | sets might not be to a pointer value (consider access to a | |
2468 | union in two threads of control in the presense of global | |
3502dc9c | 2469 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2470 | pseudo if this is the only set of that pseudo. */ |
2471 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2472 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2473 | && ! REG_POINTER (SET_DEST (x)) |
be8dcd74 | 2474 | && ((GET_CODE (SET_SRC (x)) == REG |
3502dc9c | 2475 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2476 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2477 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2478 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2479 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3502dc9c | 2480 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2481 | || GET_CODE (SET_SRC (x)) == CONST |
2482 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2483 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2484 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2485 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2486 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2487 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2488 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2489 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2490 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2491 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2492 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2493 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2494 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2495 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2496 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2497 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2498 | |
0f41302f | 2499 | /* ... fall through ... */ |
54dac99e RK |
2500 | |
2501 | default: | |
2502 | { | |
6f7d635c | 2503 | register const char *fmt = GET_RTX_FORMAT (code); |
54dac99e RK |
2504 | register int i; |
2505 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2506 | { | |
2507 | if (fmt[i] == 'e') | |
f903b91f | 2508 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2509 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2510 | { | |
2511 | register int j; | |
2512 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f903b91f | 2513 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2514 | } |
2515 | } | |
2516 | } | |
2517 | } | |
2518 | } | |
2519 | \f | |
2520 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2521 | is also in C2. */ | |
2522 | ||
2523 | int | |
2524 | reg_class_subset_p (c1, c2) | |
2525 | register enum reg_class c1; | |
2526 | register enum reg_class c2; | |
2527 | { | |
2528 | if (c1 == c2) return 1; | |
2529 | ||
2530 | if (c2 == ALL_REGS) | |
2531 | win: | |
2532 | return 1; | |
2533 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
2534 | reg_class_contents[(int)c2], | |
2535 | win); | |
2536 | return 0; | |
2537 | } | |
2538 | ||
2539 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2540 | ||
2541 | int | |
2542 | reg_classes_intersect_p (c1, c2) | |
2543 | register enum reg_class c1; | |
2544 | register enum reg_class c2; | |
2545 | { | |
2546 | #ifdef HARD_REG_SET | |
2547 | register | |
2548 | #endif | |
2549 | HARD_REG_SET c; | |
2550 | ||
2551 | if (c1 == c2) return 1; | |
2552 | ||
2553 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2554 | return 1; | |
2555 | ||
2556 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2557 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2558 | ||
2559 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2560 | return 1; | |
2561 | ||
2562 | lose: | |
2563 | return 0; | |
2564 | } | |
2565 | ||
73b76448 RK |
2566 | /* Release any memory allocated by register sets. */ |
2567 | ||
2568 | void | |
2569 | regset_release_memory () | |
2570 | { | |
73b76448 RK |
2571 | bitmap_release_memory (); |
2572 | } |