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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
e56b4594 | 3 | 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
54dac99e RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
21 | |
22 | ||
23 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
24 | It also defines some tables of information about the hardware registers | |
25 | and a function init_reg_sets to initialize the tables. */ | |
26 | ||
27 | #include "config.h" | |
670ee920 | 28 | #include "system.h" |
54dac99e | 29 | #include "rtl.h" |
6baf1cc8 | 30 | #include "tm_p.h" |
54dac99e RK |
31 | #include "hard-reg-set.h" |
32 | #include "flags.h" | |
33 | #include "basic-block.h" | |
34 | #include "regs.h" | |
49ad7cfa | 35 | #include "function.h" |
54dac99e RK |
36 | #include "insn-config.h" |
37 | #include "recog.h" | |
e4600702 RK |
38 | #include "reload.h" |
39 | #include "real.h" | |
10f0ad3d | 40 | #include "toplev.h" |
d6f4ec51 | 41 | #include "output.h" |
8b0212ca | 42 | #include "ggc.h" |
54dac99e RK |
43 | |
44 | #ifndef REGISTER_MOVE_COST | |
e56b4594 | 45 | #define REGISTER_MOVE_COST(m, x, y) 2 |
54dac99e RK |
46 | #endif |
47 | ||
13536812 KG |
48 | static void init_reg_sets_1 PARAMS ((void)); |
49 | static void init_reg_modes PARAMS ((void)); | |
24deb20a | 50 | |
533d0835 RK |
51 | /* If we have auto-increment or auto-decrement and we can have secondary |
52 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 53 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
54 | |
55 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 56 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
57 | #define FORBIDDEN_INC_DEC_CLASSES |
58 | #endif | |
59 | #endif | |
54dac99e RK |
60 | \f |
61 | /* Register tables used by many passes. */ | |
62 | ||
63 | /* Indexed by hard register number, contains 1 for registers | |
64 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
65 | These are the registers that cannot be used to allocate | |
252f342a | 66 | a pseudo reg for general use. */ |
54dac99e RK |
67 | |
68 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
69 | ||
70 | /* Same info as a HARD_REG_SET. */ | |
71 | ||
72 | HARD_REG_SET fixed_reg_set; | |
73 | ||
74 | /* Data for initializing the above. */ | |
75 | ||
76 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
77 | ||
78 | /* Indexed by hard register number, contains 1 for registers | |
79 | that are fixed use or are clobbered by function calls. | |
80 | These are the registers that cannot be used to allocate | |
252f342a MH |
81 | a pseudo reg whose life crosses calls unless we are able |
82 | to save/restore them across the calls. */ | |
54dac99e RK |
83 | |
84 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
85 | ||
86 | /* Same info as a HARD_REG_SET. */ | |
87 | ||
88 | HARD_REG_SET call_used_reg_set; | |
89 | ||
6cad67d2 JL |
90 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
91 | HARD_REG_SET losing_caller_save_reg_set; | |
92 | ||
54dac99e RK |
93 | /* Data for initializing the above. */ |
94 | ||
95 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
96 | ||
97 | /* Indexed by hard register number, contains 1 for registers that are | |
252f342a MH |
98 | fixed use or call used registers that cannot hold quantities across |
99 | calls even if we are willing to save and restore them. call fixed | |
100 | registers are a subset of call used registers. */ | |
54dac99e RK |
101 | |
102 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
103 | ||
104 | /* The same info as a HARD_REG_SET. */ | |
105 | ||
106 | HARD_REG_SET call_fixed_reg_set; | |
107 | ||
108 | /* Number of non-fixed registers. */ | |
109 | ||
110 | int n_non_fixed_regs; | |
111 | ||
112 | /* Indexed by hard register number, contains 1 for registers | |
113 | that are being used for global register decls. | |
114 | These must be exempt from ordinary flow analysis | |
115 | and are also considered fixed. */ | |
116 | ||
117 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
118 | ||
119 | /* Table of register numbers in the order in which to try to use them. */ | |
120 | #ifdef REG_ALLOC_ORDER | |
121 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
122 | |
123 | /* The inverse of reg_alloc_order. */ | |
124 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
125 | #endif |
126 | ||
127 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
128 | ||
2e0e2b76 CH |
129 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
130 | ||
089e575b RS |
131 | /* The same information, but as an array of unsigned ints. We copy from |
132 | these unsigned ints to the table above. We do this so the tm.h files | |
133 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
134 | |
135 | #define N_REG_INTS \ | |
136 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
137 | ||
089e575b | 138 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 139 | = REG_CLASS_CONTENTS; |
54dac99e RK |
140 | |
141 | /* For each reg class, number of regs it contains. */ | |
142 | ||
770ae6cc | 143 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
144 | |
145 | /* For each reg class, table listing all the containing classes. */ | |
146 | ||
147 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
148 | ||
149 | /* For each reg class, table listing all the classes contained in it. */ | |
150 | ||
151 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
152 | ||
153 | /* For each pair of reg classes, | |
154 | a largest reg class contained in their union. */ | |
155 | ||
156 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
157 | ||
158 | /* For each pair of reg classes, | |
159 | the smallest reg class containing their union. */ | |
160 | ||
161 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
162 | ||
fbd40359 ZW |
163 | /* Array containing all of the register names. Unless |
164 | DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ | |
d05c8ee7 | 165 | |
fbd40359 | 166 | #ifdef DEBUG_REGISTER_NAMES |
e087aeb2 | 167 | const char * reg_names[] = REGISTER_NAMES; |
fbd40359 | 168 | #endif |
d05c8ee7 | 169 | |
ca4aac00 DE |
170 | /* For each hard register, the widest mode object that it can contain. |
171 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
172 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
173 | register. */ | |
174 | ||
175 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
176 | ||
e4600702 RK |
177 | /* Maximum cost of moving from a register in one class to a register in |
178 | another class. Based on REGISTER_MOVE_COST. */ | |
179 | ||
e56b4594 | 180 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
181 | |
182 | /* Similar, but here we don't have to move if the first index is a subset | |
183 | of the second so in that case the cost is zero. */ | |
184 | ||
e56b4594 | 185 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
186 | |
187 | /* Similar, but here we don't have to move if the first index is a superset | |
188 | of the second so in that case the cost is zero. */ | |
189 | ||
e56b4594 | 190 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 191 | |
533d0835 RK |
192 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
193 | ||
194 | /* These are the classes that regs which are auto-incremented or decremented | |
195 | cannot be put in. */ | |
196 | ||
197 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
198 | ||
199 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
200 | context. */ | |
201 | ||
202 | static char *in_inc_dec; | |
203 | ||
5fcb671c | 204 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 205 | |
02188693 | 206 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
207 | |
208 | /* These are the classes containing only registers that can be used in | |
02188693 RH |
209 | a SUBREG expression that changes the mode of the register in some |
210 | way that is illegal. */ | |
e79f71f7 | 211 | |
02188693 | 212 | static int class_can_change_mode[N_REG_CLASSES]; |
e79f71f7 | 213 | |
02188693 RH |
214 | /* Registers, including pseudos, which change modes in some way that |
215 | is illegal. */ | |
e79f71f7 | 216 | |
02188693 | 217 | static regset reg_changes_mode; |
e79f71f7 | 218 | |
02188693 | 219 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
e79f71f7 | 220 | |
473fe49b KR |
221 | #ifdef HAVE_SECONDARY_RELOADS |
222 | ||
223 | /* Sample MEM values for use by memory_move_secondary_cost. */ | |
224 | ||
225 | static rtx top_of_stack[MAX_MACHINE_MODE]; | |
226 | ||
227 | #endif /* HAVE_SECONDARY_RELOADS */ | |
228 | ||
6feacd09 MM |
229 | /* Linked list of reg_info structures allocated for reg_n_info array. |
230 | Grouping all of the allocated structures together in one lump | |
231 | means only one call to bzero to clear them, rather than n smaller | |
232 | calls. */ | |
233 | struct reg_info_data { | |
234 | struct reg_info_data *next; /* next set of reg_info structures */ | |
235 | size_t min_index; /* minimum index # */ | |
236 | size_t max_index; /* maximum index # */ | |
237 | char used_p; /* non-zero if this has been used previously */ | |
238 | reg_info data[1]; /* beginning of the reg_info data */ | |
239 | }; | |
240 | ||
241 | static struct reg_info_data *reg_info_head; | |
242 | ||
c07c7c9d | 243 | /* No more global register variables may be declared; true once |
6c85df69 AH |
244 | regclass has been initialized. */ |
245 | ||
246 | static int no_global_reg_vars = 0; | |
247 | ||
6feacd09 | 248 | |
54dac99e RK |
249 | /* Function called only once to initialize the above data on reg usage. |
250 | Once this is done, various switches may override. */ | |
251 | ||
252 | void | |
253 | init_reg_sets () | |
254 | { | |
255 | register int i, j; | |
256 | ||
2e0e2b76 CH |
257 | /* First copy the register information from the initial int form into |
258 | the regsets. */ | |
259 | ||
260 | for (i = 0; i < N_REG_CLASSES; i++) | |
261 | { | |
262 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
263 | ||
264 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
265 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 266 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
267 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
268 | } | |
269 | ||
4e135bdd KG |
270 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
271 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 272 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 273 | |
910bc42d R |
274 | /* Do any additional initialization regsets may need */ |
275 | INIT_ONCE_REG_SET (); | |
f5d8c9f4 BS |
276 | |
277 | #ifdef REG_ALLOC_ORDER | |
278 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
279 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
280 | #endif | |
910bc42d R |
281 | } |
282 | ||
283 | /* After switches have been processed, which perhaps alter | |
284 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
285 | ||
286 | static void | |
287 | init_reg_sets_1 () | |
288 | { | |
289 | register unsigned int i, j; | |
e56b4594 | 290 | register unsigned int /* enum machine_mode */ m; |
910bc42d R |
291 | |
292 | /* This macro allows the fixed or call-used registers | |
293 | and the register classes to depend on target flags. */ | |
294 | ||
295 | #ifdef CONDITIONAL_REGISTER_USAGE | |
296 | CONDITIONAL_REGISTER_USAGE; | |
297 | #endif | |
298 | ||
54dac99e RK |
299 | /* Compute number of hard regs in each class. */ |
300 | ||
961192e1 | 301 | memset ((char *) reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
302 | for (i = 0; i < N_REG_CLASSES; i++) |
303 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
304 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
305 | reg_class_size[i]++; | |
306 | ||
307 | /* Initialize the table of subunions. | |
308 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
309 | that is contained in the union of classes I and J. */ | |
310 | ||
311 | for (i = 0; i < N_REG_CLASSES; i++) | |
312 | { | |
313 | for (j = 0; j < N_REG_CLASSES; j++) | |
314 | { | |
315 | #ifdef HARD_REG_SET | |
316 | register /* Declare it register if it's a scalar. */ | |
317 | #endif | |
318 | HARD_REG_SET c; | |
319 | register int k; | |
320 | ||
321 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
322 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
323 | for (k = 0; k < N_REG_CLASSES; k++) | |
324 | { | |
325 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
326 | subclass1); | |
327 | continue; | |
328 | ||
329 | subclass1: | |
330 | /* keep the largest subclass */ /* SPEE 900308 */ | |
331 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
332 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
333 | subclass2); | |
334 | reg_class_subunion[i][j] = (enum reg_class) k; | |
335 | subclass2: | |
336 | ; | |
337 | } | |
338 | } | |
339 | } | |
340 | ||
341 | /* Initialize the table of superunions. | |
342 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
343 | containing the union of classes I and J. */ | |
344 | ||
345 | for (i = 0; i < N_REG_CLASSES; i++) | |
346 | { | |
347 | for (j = 0; j < N_REG_CLASSES; j++) | |
348 | { | |
349 | #ifdef HARD_REG_SET | |
350 | register /* Declare it register if it's a scalar. */ | |
351 | #endif | |
352 | HARD_REG_SET c; | |
353 | register int k; | |
354 | ||
355 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
356 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
357 | for (k = 0; k < N_REG_CLASSES; k++) | |
358 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
359 | ||
360 | superclass: | |
361 | reg_class_superunion[i][j] = (enum reg_class) k; | |
362 | } | |
363 | } | |
364 | ||
365 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
366 | First clear the whole table, then add the elements as they are found. */ | |
367 | ||
368 | for (i = 0; i < N_REG_CLASSES; i++) | |
369 | { | |
370 | for (j = 0; j < N_REG_CLASSES; j++) | |
371 | { | |
372 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
373 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
374 | } | |
375 | } | |
376 | ||
377 | for (i = 0; i < N_REG_CLASSES; i++) | |
378 | { | |
379 | if (i == (int) NO_REGS) | |
380 | continue; | |
381 | ||
382 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
383 | { | |
384 | enum reg_class *p; | |
385 | ||
386 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
387 | subclass); | |
388 | continue; | |
389 | subclass: | |
390 | /* Reg class I is a subclass of J. | |
391 | Add J to the table of superclasses of I. */ | |
392 | p = ®_class_superclasses[i][0]; | |
393 | while (*p != LIM_REG_CLASSES) p++; | |
394 | *p = (enum reg_class) j; | |
395 | /* Add I to the table of superclasses of J. */ | |
396 | p = ®_class_subclasses[j][0]; | |
397 | while (*p != LIM_REG_CLASSES) p++; | |
398 | *p = (enum reg_class) i; | |
399 | } | |
400 | } | |
e4600702 | 401 | |
54dac99e RK |
402 | /* Initialize "constant" tables. */ |
403 | ||
404 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
405 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
406 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
407 | ||
4e135bdd | 408 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e RK |
409 | |
410 | n_non_fixed_regs = 0; | |
411 | ||
412 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
413 | { | |
54dac99e RK |
414 | if (fixed_regs[i]) |
415 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
416 | else | |
417 | n_non_fixed_regs++; | |
418 | ||
419 | if (call_used_regs[i]) | |
420 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
421 | if (call_fixed_regs[i]) | |
422 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
423 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
424 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 425 | } |
acbce667 KR |
426 | |
427 | /* Initialize the move cost table. Find every subset of each class | |
428 | and take the maximum cost of moving any subset to any other. */ | |
429 | ||
e56b4594 AO |
430 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
431 | for (i = 0; i < N_REG_CLASSES; i++) | |
432 | for (j = 0; j < N_REG_CLASSES; j++) | |
433 | { | |
434 | int cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j); | |
435 | enum reg_class *p1, *p2; | |
acbce667 | 436 | |
e56b4594 AO |
437 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) |
438 | if (*p2 != i) | |
439 | cost = MAX (cost, REGISTER_MOVE_COST (m, i, *p2)); | |
acbce667 | 440 | |
e56b4594 AO |
441 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) |
442 | { | |
443 | if (*p1 != j) | |
444 | cost = MAX (cost, REGISTER_MOVE_COST (m, *p1, j)); | |
acbce667 | 445 | |
e56b4594 AO |
446 | for (p2 = ®_class_subclasses[j][0]; |
447 | *p2 != LIM_REG_CLASSES; p2++) | |
448 | if (*p1 != *p2) | |
449 | cost = MAX (cost, REGISTER_MOVE_COST (m, *p1, *p2)); | |
450 | } | |
acbce667 | 451 | |
e56b4594 | 452 | move_cost[m][i][j] = cost; |
acbce667 | 453 | |
e56b4594 AO |
454 | if (reg_class_subset_p (i, j)) |
455 | may_move_in_cost[m][i][j] = 0; | |
456 | else | |
457 | may_move_in_cost[m][i][j] = cost; | |
acbce667 | 458 | |
e56b4594 AO |
459 | if (reg_class_subset_p (j, i)) |
460 | may_move_out_cost[m][i][j] = 0; | |
461 | else | |
462 | may_move_out_cost[m][i][j] = cost; | |
463 | } | |
e79f71f7 | 464 | |
02188693 | 465 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
466 | { |
467 | HARD_REG_SET c; | |
02188693 | 468 | COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]); |
e79f71f7 GK |
469 | |
470 | for (i = 0; i < N_REG_CLASSES; i++) | |
471 | { | |
472 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class); | |
02188693 | 473 | class_can_change_mode [i] = 0; |
e79f71f7 GK |
474 | continue; |
475 | ok_class: | |
02188693 | 476 | class_can_change_mode [i] = 1; |
e79f71f7 GK |
477 | } |
478 | } | |
02188693 | 479 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
c27c5281 DE |
480 | } |
481 | ||
482 | /* Compute the table of register modes. | |
483 | These values are used to record death information for individual registers | |
484 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 485 | |
c27c5281 DE |
486 | static void |
487 | init_reg_modes () | |
488 | { | |
489 | register int i; | |
ca4aac00 DE |
490 | |
491 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
492 | { |
493 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
494 | ||
066c2fea | 495 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
496 | ??? One situation in which we need to do this is on the mips where |
497 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
498 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 499 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 500 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 501 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 502 | } |
ca4aac00 DE |
503 | } |
504 | ||
c27c5281 DE |
505 | /* Finish initializing the register sets and |
506 | initialize the register modes. */ | |
507 | ||
508 | void | |
509 | init_regs () | |
510 | { | |
511 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
512 | until after register usage was specified. */ | |
b93a436e | 513 | init_reg_sets_1 (); |
c27c5281 DE |
514 | |
515 | init_reg_modes (); | |
473fe49b KR |
516 | |
517 | #ifdef HAVE_SECONDARY_RELOADS | |
518 | { | |
519 | /* Make some fake stack-frame MEM references for use in | |
520 | memory_move_secondary_cost. */ | |
521 | int i; | |
d067e2aa | 522 | |
473fe49b | 523 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 524 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
00d33cb2 | 525 | ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE); |
473fe49b KR |
526 | } |
527 | #endif | |
c27c5281 DE |
528 | } |
529 | ||
cbd5b9a2 | 530 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 531 | |
cbd5b9a2 KR |
532 | /* Compute extra cost of moving registers to/from memory due to reloads. |
533 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 534 | |
cbd5b9a2 KR |
535 | int |
536 | memory_move_secondary_cost (mode, class, in) | |
537 | enum machine_mode mode; | |
538 | enum reg_class class; | |
539 | int in; | |
540 | { | |
541 | enum reg_class altclass; | |
542 | int partial_cost = 0; | |
cbd5b9a2 | 543 | /* We need a memory reference to feed to SECONDARY... macros. */ |
272df862 KG |
544 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
545 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; | |
546 | ||
cbd5b9a2 KR |
547 | |
548 | if (in) | |
473fe49b | 549 | { |
321c0828 | 550 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 551 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 552 | #else |
473fe49b | 553 | altclass = NO_REGS; |
321c0828 | 554 | #endif |
473fe49b | 555 | } |
cbd5b9a2 | 556 | else |
473fe49b | 557 | { |
321c0828 | 558 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 559 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 560 | #else |
473fe49b | 561 | altclass = NO_REGS; |
321c0828 | 562 | #endif |
473fe49b KR |
563 | } |
564 | ||
cbd5b9a2 KR |
565 | if (altclass == NO_REGS) |
566 | return 0; | |
567 | ||
568 | if (in) | |
e56b4594 | 569 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 570 | else |
e56b4594 | 571 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
572 | |
573 | if (class == altclass) | |
574 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
575 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
576 | here in that case. | |
577 | ||
578 | I'm tempted to put in an abort here, but returning this will | |
579 | probably only give poor estimates, which is what we would've | |
580 | had before this code anyways. */ | |
581 | return partial_cost; | |
582 | ||
583 | /* Check if the secondary reload register will also need a | |
584 | secondary reload. */ | |
585 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
586 | } | |
587 | #endif | |
588 | ||
ca4aac00 DE |
589 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
590 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
591 | ||
592 | enum machine_mode | |
593 | choose_hard_reg_mode (regno, nregs) | |
770ae6cc RK |
594 | unsigned int regno ATTRIBUTE_UNUSED; |
595 | unsigned int nregs; | |
ca4aac00 DE |
596 | { |
597 | enum machine_mode found_mode = VOIDmode, mode; | |
598 | ||
599 | /* We first look for the largest integer mode that can be validly | |
600 | held in REGNO. If none, we look for the largest floating-point mode. | |
601 | If we still didn't find a valid mode, try CCmode. */ | |
602 | ||
603 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
604 | mode != VOIDmode; | |
605 | mode = GET_MODE_WIDER_MODE (mode)) | |
606 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
607 | && HARD_REGNO_MODE_OK (regno, mode)) | |
608 | found_mode = mode; | |
609 | ||
610 | if (found_mode != VOIDmode) | |
611 | return found_mode; | |
612 | ||
613 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
614 | mode != VOIDmode; | |
615 | mode = GET_MODE_WIDER_MODE (mode)) | |
616 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
617 | && HARD_REGNO_MODE_OK (regno, mode)) | |
618 | found_mode = mode; | |
619 | ||
620 | if (found_mode != VOIDmode) | |
621 | return found_mode; | |
622 | ||
0548a9df RH |
623 | /* Iterate over all of the CCmodes. */ |
624 | for (mode = CCmode; mode < NUM_MACHINE_MODES; ++mode) | |
625 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
626 | && HARD_REGNO_MODE_OK (regno, mode)) | |
627 | return mode; | |
ca4aac00 DE |
628 | |
629 | /* We can't find a mode valid for this register. */ | |
630 | return VOIDmode; | |
54dac99e RK |
631 | } |
632 | ||
633 | /* Specify the usage characteristics of the register named NAME. | |
634 | It should be a fixed register if FIXED and a | |
635 | call-used register if CALL_USED. */ | |
636 | ||
637 | void | |
638 | fix_register (name, fixed, call_used) | |
ec0ce6e2 | 639 | const char *name; |
54dac99e RK |
640 | int fixed, call_used; |
641 | { | |
642 | int i; | |
643 | ||
644 | /* Decode the name and update the primary form of | |
645 | the register info. */ | |
646 | ||
e5c90c23 TW |
647 | if ((i = decode_reg_name (name)) >= 0) |
648 | { | |
cb2fdc84 GRK |
649 | if ((i == STACK_POINTER_REGNUM |
650 | #ifdef HARD_FRAME_POINTER_REGNUM | |
651 | || i == HARD_FRAME_POINTER_REGNUM | |
652 | #else | |
653 | || i == FRAME_POINTER_REGNUM | |
654 | #endif | |
655 | ) | |
656 | && (fixed == 0 || call_used == 0)) | |
657 | { | |
6f7d635c | 658 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
659 | { "call-saved", "call-used" }, |
660 | { "no-such-option", "fixed" }}; | |
cb2fdc84 GRK |
661 | |
662 | error ("can't use '%s' as a %s register", name, | |
663 | what_option[fixed][call_used]); | |
664 | } | |
665 | else | |
666 | { | |
667 | fixed_regs[i] = fixed; | |
668 | call_used_regs[i] = call_used; | |
669 | } | |
e5c90c23 TW |
670 | } |
671 | else | |
54dac99e RK |
672 | { |
673 | warning ("unknown register name: %s", name); | |
54dac99e RK |
674 | } |
675 | } | |
614f68e2 RK |
676 | |
677 | /* Mark register number I as global. */ | |
678 | ||
679 | void | |
680 | globalize_reg (i) | |
681 | int i; | |
682 | { | |
c07c7c9d | 683 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
684 | error ("global register variable follows a function definition"); |
685 | ||
614f68e2 RK |
686 | if (global_regs[i]) |
687 | { | |
688 | warning ("register used for two global register variables"); | |
689 | return; | |
690 | } | |
691 | ||
692 | if (call_used_regs[i] && ! fixed_regs[i]) | |
693 | warning ("call-clobbered register used for global register variable"); | |
694 | ||
695 | global_regs[i] = 1; | |
696 | ||
697 | /* If already fixed, nothing else to do. */ | |
698 | if (fixed_regs[i]) | |
699 | return; | |
700 | ||
701 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
702 | n_non_fixed_regs--; | |
703 | ||
704 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
705 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
706 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
707 | } | |
54dac99e RK |
708 | \f |
709 | /* Now the data and code for the `regclass' pass, which happens | |
710 | just before local-alloc. */ | |
711 | ||
e4600702 RK |
712 | /* The `costs' struct records the cost of using a hard register of each class |
713 | and of using memory for each pseudo. We use this data to set up | |
714 | register class preferences. */ | |
54dac99e | 715 | |
e4600702 | 716 | struct costs |
54dac99e | 717 | { |
e4600702 RK |
718 | int cost[N_REG_CLASSES]; |
719 | int mem_cost; | |
54dac99e RK |
720 | }; |
721 | ||
9ffc5a70 JH |
722 | /* Structure used to record preferrences of given pseudo. */ |
723 | struct reg_pref | |
724 | { | |
725 | /* (enum reg_class) prefclass is the preferred class. */ | |
726 | char prefclass; | |
727 | ||
728 | /* altclass is a register class that we should use for allocating | |
729 | pseudo if no register in the preferred class is available. | |
730 | If no register in this class is available, memory is preferred. | |
731 | ||
732 | It might appear to be more general to have a bitmask of classes here, | |
733 | but since it is recommended that there be a class corresponding to the | |
734 | union of most major pair of classes, that generality is not required. */ | |
735 | char altclass; | |
736 | }; | |
737 | ||
e4600702 RK |
738 | /* Record the cost of each class for each pseudo. */ |
739 | ||
740 | static struct costs *costs; | |
741 | ||
61719ba7 BS |
742 | /* Initialized once, and used to initialize cost values for each insn. */ |
743 | ||
744 | static struct costs init_cost; | |
745 | ||
9ffc5a70 | 746 | /* Record preferrences of each pseudo. |
54dac99e RK |
747 | This is available after `regclass' is run. */ |
748 | ||
9ffc5a70 | 749 | static struct reg_pref *reg_pref; |
54d23420 | 750 | |
9ffc5a70 | 751 | /* Allocated buffers for reg_pref. */ |
54dac99e | 752 | |
9ffc5a70 | 753 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 754 | |
54d23420 RK |
755 | /* Account for the fact that insns within a loop are executed very commonly, |
756 | but don't keep doing this as loops go too deep. */ | |
757 | ||
758 | static int loop_cost; | |
759 | ||
13536812 KG |
760 | static rtx scan_one_insn PARAMS ((rtx, int)); |
761 | static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); | |
762 | static void dump_regclass PARAMS ((FILE *)); | |
763 | static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, | |
e79f71f7 | 764 | const char **, rtx, |
f741a71c | 765 | struct costs *, struct reg_pref *)); |
13536812 | 766 | static int copy_cost PARAMS ((rtx, enum machine_mode, |
08d95f91 | 767 | enum reg_class, int)); |
13536812 | 768 | static void record_address_regs PARAMS ((rtx, enum reg_class, int)); |
1d300e19 | 769 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
13536812 | 770 | static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); |
1d300e19 | 771 | #endif |
770ae6cc | 772 | static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); |
54dac99e RK |
773 | |
774 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
775 | This function is sometimes called before the info has been computed. | |
776 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
777 | ||
778 | enum reg_class | |
779 | reg_preferred_class (regno) | |
780 | int regno; | |
781 | { | |
9ffc5a70 | 782 | if (reg_pref == 0) |
54dac99e | 783 | return GENERAL_REGS; |
9ffc5a70 | 784 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
785 | } |
786 | ||
e4600702 RK |
787 | enum reg_class |
788 | reg_alternate_class (regno) | |
b729186a | 789 | int regno; |
54dac99e | 790 | { |
9ffc5a70 | 791 | if (reg_pref == 0) |
e4600702 RK |
792 | return ALL_REGS; |
793 | ||
9ffc5a70 | 794 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
795 | } |
796 | ||
61719ba7 | 797 | /* Initialize some global data for this pass. */ |
54dac99e RK |
798 | |
799 | void | |
800 | regclass_init () | |
801 | { | |
61719ba7 BS |
802 | int i; |
803 | ||
804 | init_cost.mem_cost = 10000; | |
805 | for (i = 0; i < N_REG_CLASSES; i++) | |
806 | init_cost.cost[i] = 10000; | |
807 | ||
808 | /* This prevents dump_flow_info from losing if called | |
809 | before regclass is run. */ | |
9ffc5a70 | 810 | reg_pref = NULL; |
6c85df69 | 811 | |
c07c7c9d | 812 | /* No more global register variables may be declared. */ |
6c85df69 | 813 | no_global_reg_vars = 1; |
54dac99e | 814 | } |
246fd41f JH |
815 | \f |
816 | /* Dump register costs. */ | |
915b80ed | 817 | static void |
246fd41f JH |
818 | dump_regclass (dump) |
819 | FILE *dump; | |
820 | { | |
821 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
822 | int i; | |
823 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
824 | { | |
825 | enum reg_class class; | |
826 | if (REG_N_REFS (i)) | |
827 | { | |
f741a71c | 828 | fprintf (dump, " Register %i costs:", i); |
246fd41f JH |
829 | for (class = 0; class < N_REG_CLASSES; class++) |
830 | fprintf (dump, " %s:%i", reg_class_names[(int) class], | |
831 | costs[i].cost[class]); | |
f741a71c | 832 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
833 | } |
834 | } | |
835 | } | |
f741a71c JH |
836 | \f |
837 | ||
838 | /* Calculate the costs of insn operands. */ | |
839 | ||
840 | static void | |
841 | record_operand_costs (insn, op_costs, reg_pref) | |
842 | rtx insn; | |
843 | struct costs *op_costs; | |
844 | struct reg_pref *reg_pref; | |
845 | { | |
846 | const char *constraints[MAX_RECOG_OPERANDS]; | |
847 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
848 | int i; |
849 | ||
850 | for (i = 0; i < recog_data.n_operands; i++) | |
851 | { | |
852 | constraints[i] = recog_data.constraints[i]; | |
853 | modes[i] = recog_data.operand_mode[i]; | |
854 | } | |
f741a71c JH |
855 | |
856 | /* If we get here, we are set up to record the costs of all the | |
857 | operands for this insn. Start by initializing the costs. | |
858 | Then handle any address registers. Finally record the desired | |
859 | classes for any pseudos, doing it twice if some pair of | |
860 | operands are commutative. */ | |
861 | ||
862 | for (i = 0; i < recog_data.n_operands; i++) | |
863 | { | |
864 | op_costs[i] = init_cost; | |
865 | ||
866 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
867 | { | |
868 | rtx inner = SUBREG_REG (recog_data.operand[i]); | |
02188693 RH |
869 | #ifdef CLASS_CANNOT_CHANGE_MODE |
870 | if (GET_CODE (inner) == REG | |
871 | && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner))) | |
872 | SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner)); | |
9ef07cf1 | 873 | #endif |
f741a71c JH |
874 | recog_data.operand[i] = inner; |
875 | } | |
876 | ||
877 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
878 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
879 | BASE_REG_CLASS, loop_cost * 2); | |
880 | else if (constraints[i][0] == 'p') | |
881 | record_address_regs (recog_data.operand[i], | |
882 | BASE_REG_CLASS, loop_cost * 2); | |
883 | } | |
884 | ||
885 | /* Check for commutative in a separate loop so everything will | |
886 | have been initialized. We must do this even if one operand | |
887 | is a constant--see addsi3 in m68k.md. */ | |
888 | ||
889 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
890 | if (constraints[i][0] == '%') | |
891 | { | |
892 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
893 | int j; | |
246fd41f | 894 | |
f741a71c JH |
895 | /* Handle commutative operands by swapping the constraints. |
896 | We assume the modes are the same. */ | |
897 | ||
898 | for (j = 0; j < recog_data.n_operands; j++) | |
899 | xconstraints[j] = constraints[j]; | |
900 | ||
901 | xconstraints[i] = constraints[i+1]; | |
902 | xconstraints[i+1] = constraints[i]; | |
903 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
e79f71f7 | 904 | recog_data.operand, modes, |
f741a71c JH |
905 | xconstraints, insn, op_costs, reg_pref); |
906 | } | |
907 | ||
908 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
e79f71f7 | 909 | recog_data.operand, modes, |
f741a71c JH |
910 | constraints, insn, op_costs, reg_pref); |
911 | } | |
54dac99e | 912 | \f |
61719ba7 BS |
913 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
914 | time it would save code to put a certain register in a certain class. | |
915 | PASS, when nonzero, inhibits some optimizations which need only be done | |
916 | once. | |
917 | Return the last insn processed, so that the scan can be continued from | |
918 | there. */ | |
919 | ||
920 | static rtx | |
921 | scan_one_insn (insn, pass) | |
922 | rtx insn; | |
923 | int pass; | |
924 | { | |
925 | enum rtx_code code = GET_CODE (insn); | |
926 | enum rtx_code pat_code; | |
0eadeb15 | 927 | rtx set, note; |
61719ba7 | 928 | int i, j; |
f741a71c | 929 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 930 | |
61719ba7 BS |
931 | if (GET_RTX_CLASS (code) != 'i') |
932 | return insn; | |
933 | ||
934 | pat_code = GET_CODE (PATTERN (insn)); | |
935 | if (pat_code == USE | |
936 | || pat_code == CLOBBER | |
937 | || pat_code == ASM_INPUT | |
938 | || pat_code == ADDR_VEC | |
939 | || pat_code == ADDR_DIFF_VEC) | |
940 | return insn; | |
941 | ||
0eadeb15 BS |
942 | set = single_set (insn); |
943 | extract_insn (insn); | |
944 | ||
0eadeb15 BS |
945 | /* If this insn loads a parameter from its stack slot, then |
946 | it represents a savings, rather than a cost, if the | |
947 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 948 | |
0eadeb15 BS |
949 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
950 | && GET_CODE (SET_SRC (set)) == MEM | |
951 | && (note = find_reg_note (insn, REG_EQUIV, | |
952 | NULL_RTX)) != 0 | |
953 | && GET_CODE (XEXP (note, 0)) == MEM) | |
954 | { | |
955 | costs[REGNO (SET_DEST (set))].mem_cost | |
956 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
957 | GENERAL_REGS, 1) | |
958 | * loop_cost); | |
959 | record_address_regs (XEXP (SET_SRC (set), 0), | |
960 | BASE_REG_CLASS, loop_cost * 2); | |
961 | return insn; | |
962 | } | |
61719ba7 | 963 | |
0eadeb15 BS |
964 | /* Improve handling of two-address insns such as |
965 | (set X (ashift CONST Y)) where CONST must be made to | |
966 | match X. Change it into two insns: (set X CONST) | |
967 | (set X (ashift X Y)). If we left this for reloading, it | |
968 | would probably get three insns because X and Y might go | |
969 | in the same place. This prevents X and Y from receiving | |
970 | the same hard reg. | |
971 | ||
972 | We can only do this if the modes of operands 0 and 1 | |
973 | (which might not be the same) are tieable and we only need | |
974 | do this during our first pass. */ | |
975 | ||
976 | if (pass == 0 && optimize | |
1ccbefce RH |
977 | && recog_data.n_operands >= 3 |
978 | && recog_data.constraints[1][0] == '0' | |
979 | && recog_data.constraints[1][1] == 0 | |
980 | && CONSTANT_P (recog_data.operand[1]) | |
981 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
982 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
983 | && GET_CODE (recog_data.operand[0]) == REG | |
984 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
985 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
986 | { |
987 | rtx previnsn = prev_real_insn (insn); | |
988 | rtx dest | |
1ccbefce RH |
989 | = gen_lowpart (recog_data.operand_mode[1], |
990 | recog_data.operand[0]); | |
0eadeb15 | 991 | rtx newinsn |
1ccbefce | 992 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 993 | |
0eadeb15 BS |
994 | /* If this insn was the start of a basic block, |
995 | include the new insn in that block. | |
996 | We need not check for code_label here; | |
997 | while a basic block can start with a code_label, | |
998 | INSN could not be at the beginning of that block. */ | |
999 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 1000 | { |
0eadeb15 BS |
1001 | int b; |
1002 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 RH |
1003 | if (insn == BLOCK_HEAD (b)) |
1004 | BLOCK_HEAD (b) = newinsn; | |
61719ba7 BS |
1005 | } |
1006 | ||
0eadeb15 | 1007 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1008 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
61719ba7 | 1009 | |
1ccbefce RH |
1010 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
1011 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
1012 | if (recog_data.dup_num[i] == 1) | |
1013 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
61719ba7 | 1014 | |
0eadeb15 | 1015 | return PREV_INSN (newinsn); |
61719ba7 BS |
1016 | } |
1017 | ||
4963c995 | 1018 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1019 | |
1020 | /* Now add the cost for each operand to the total costs for | |
1021 | its register. */ | |
1022 | ||
1ccbefce RH |
1023 | for (i = 0; i < recog_data.n_operands; i++) |
1024 | if (GET_CODE (recog_data.operand[i]) == REG | |
1025 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 1026 | { |
1ccbefce | 1027 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1028 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1029 | ||
1030 | p->mem_cost += q->mem_cost * loop_cost; | |
1031 | for (j = 0; j < N_REG_CLASSES; j++) | |
1032 | p->cost[j] += q->cost[j] * loop_cost; | |
1033 | } | |
1034 | ||
1035 | return insn; | |
1036 | } | |
1037 | ||
54dac99e RK |
1038 | /* This is a pass of the compiler that scans all instructions |
1039 | and calculates the preferred class for each pseudo-register. | |
1040 | This information can be accessed later by calling `reg_preferred_class'. | |
1041 | This pass comes just before local register allocation. */ | |
1042 | ||
1043 | void | |
246fd41f | 1044 | regclass (f, nregs, dump) |
54dac99e RK |
1045 | rtx f; |
1046 | int nregs; | |
246fd41f | 1047 | FILE *dump; |
54dac99e | 1048 | { |
54dac99e | 1049 | register rtx insn; |
61719ba7 | 1050 | register int i; |
e4600702 | 1051 | int pass; |
54dac99e RK |
1052 | |
1053 | init_recog (); | |
1054 | ||
56a65848 | 1055 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 | 1056 | |
02188693 RH |
1057 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1058 | reg_changes_mode = BITMAP_XMALLOC(); | |
e79f71f7 GK |
1059 | #endif |
1060 | ||
533d0835 RK |
1061 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1062 | ||
4da896b2 | 1063 | in_inc_dec = (char *) xmalloc (nregs); |
533d0835 RK |
1064 | |
1065 | /* Initialize information about which register classes can be used for | |
1066 | pseudos that are auto-incremented or auto-decremented. It would | |
1067 | seem better to put this in init_reg_sets, but we need to be able | |
1068 | to allocate rtx, which we can't do that early. */ | |
1069 | ||
1070 | for (i = 0; i < N_REG_CLASSES; i++) | |
1071 | { | |
38a448ca | 1072 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 | 1073 | enum machine_mode m; |
8c368ee2 | 1074 | register int j; |
533d0835 RK |
1075 | |
1076 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1077 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1078 | { | |
1079 | REGNO (r) = j; | |
1080 | ||
1081 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1082 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1083 | if (HARD_REGNO_MODE_OK (j, m)) |
1084 | { | |
1085 | PUT_MODE (r, m); | |
08d95f91 RK |
1086 | |
1087 | /* If a register is not directly suitable for an | |
1088 | auto-increment or decrement addressing mode and | |
1089 | requires secondary reloads, disallow its class from | |
1090 | being used in such addresses. */ | |
1091 | ||
1092 | if ((0 | |
041d7180 JL |
1093 | #ifdef SECONDARY_RELOAD_CLASS |
1094 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
1095 | != NO_REGS) | |
1096 | #else | |
533d0835 | 1097 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
1098 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1099 | != NO_REGS) | |
533d0835 RK |
1100 | #endif |
1101 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
1102 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1103 | != NO_REGS) | |
041d7180 | 1104 | #endif |
533d0835 | 1105 | #endif |
08d95f91 RK |
1106 | ) |
1107 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1108 | forbidden_inc_dec_class[i] = 1; |
1109 | } | |
1110 | } | |
1111 | } | |
1112 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1113 | ||
e4600702 RK |
1114 | /* Normally we scan the insns once and determine the best class to use for |
1115 | each register. However, if -fexpensive_optimizations are on, we do so | |
1116 | twice, the second time using the tentative best classes to guide the | |
1117 | selection. */ | |
54dac99e | 1118 | |
e4600702 RK |
1119 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1120 | { | |
954d8e99 | 1121 | int index; |
f741a71c JH |
1122 | |
1123 | if (dump) | |
1124 | fprintf (dump, "\n\nPass %i\n\n",pass); | |
e4600702 | 1125 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1126 | |
961192e1 | 1127 | memset ((char *) costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1128 | |
533d0835 | 1129 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1130 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1131 | #endif |
1132 | ||
e4600702 RK |
1133 | /* Scan the instructions and record each time it would |
1134 | save code to put a certain register in a certain class. */ | |
1135 | ||
1f01879e | 1136 | if (!optimize) |
54dac99e | 1137 | { |
1f01879e JH |
1138 | loop_cost = 1; |
1139 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1140 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1141 | } |
1f01879e JH |
1142 | else |
1143 | for (index = 0; index < n_basic_blocks; index++) | |
1144 | { | |
1145 | basic_block bb = BASIC_BLOCK (index); | |
1146 | ||
1147 | /* Show that an insn inside a loop is likely to be executed three | |
9b15c17f RH |
1148 | times more than insns outside a loop. This is much more |
1149 | aggressive than the assumptions made elsewhere and is being | |
1150 | tried as an experiment. */ | |
1f01879e JH |
1151 | if (optimize_size) |
1152 | loop_cost = 1; | |
1153 | else | |
9b15c17f | 1154 | loop_cost = 1 << (2 * MIN (bb->loop_depth, 5)); |
1f01879e JH |
1155 | for (insn = bb->head; ; insn = NEXT_INSN (insn)) |
1156 | { | |
1157 | insn = scan_one_insn (insn, pass); | |
1158 | if (insn == bb->end) | |
1159 | break; | |
1160 | } | |
1161 | } | |
61719ba7 | 1162 | |
e4600702 RK |
1163 | /* Now for each register look at how desirable each class is |
1164 | and find which class is preferred. Store that in | |
9ffc5a70 | 1165 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1166 | class any of whose registers is better than memory. */ |
54dac99e | 1167 | |
e4600702 | 1168 | if (pass == 0) |
9ffc5a70 | 1169 | reg_pref = reg_pref_buffer; |
54dac99e | 1170 | |
f741a71c JH |
1171 | if (dump) |
1172 | { | |
1173 | dump_regclass (dump); | |
4963c995 | 1174 | fprintf (dump,"\n"); |
f741a71c | 1175 | } |
e4600702 | 1176 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1177 | { |
ca3c6eae | 1178 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1179 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1180 | /* This is an enum reg_class, but we call it an int | |
1181 | to save lots of casts. */ | |
1182 | register int class; | |
1183 | register struct costs *p = &costs[i]; | |
1184 | ||
64615302 JH |
1185 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1186 | yet. */ | |
1187 | if (optimize && !REG_N_REFS (i)) | |
f741a71c JH |
1188 | continue; |
1189 | ||
e4600702 | 1190 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1191 | { |
533d0835 RK |
1192 | /* Ignore classes that are too small for this operand or |
1193 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 1194 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
1195 | > reg_class_size[class] |
1196 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1197 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1198 | #endif |
02188693 RH |
1199 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1200 | || (REGNO_REG_SET_P (reg_changes_mode, i) | |
1201 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1202 | #endif |
1203 | ) | |
e4600702 RK |
1204 | ; |
1205 | else if (p->cost[class] < best_cost) | |
1206 | { | |
1207 | best_cost = p->cost[class]; | |
1208 | best = (enum reg_class) class; | |
1209 | } | |
1210 | else if (p->cost[class] == best_cost) | |
1211 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 1212 | } |
54dac99e | 1213 | |
e4600702 RK |
1214 | /* Record the alternate register class; i.e., a class for which |
1215 | every register in it is better than using memory. If adding a | |
1216 | class would make a smaller class (i.e., no union of just those | |
1217 | classes exists), skip that class. The major unions of classes | |
1218 | should be provided as a register class. Don't do this if we | |
1219 | will be doing it again later. */ | |
1220 | ||
f741a71c | 1221 | if ((pass == 1 || dump) || ! flag_expensive_optimizations) |
e4600702 RK |
1222 | for (class = 0; class < N_REG_CLASSES; class++) |
1223 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1224 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1225 | > reg_class_size[(int) alt]) |
1226 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1227 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1228 | #endif |
02188693 RH |
1229 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1230 | && ! (REGNO_REG_SET_P (reg_changes_mode, i) | |
1231 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1232 | #endif |
1233 | ) | |
e4600702 RK |
1234 | alt = reg_class_subunion[(int) alt][class]; |
1235 | ||
1236 | /* If we don't add any classes, nothing to try. */ | |
1237 | if (alt == best) | |
995d54dd | 1238 | alt = NO_REGS; |
e4600702 | 1239 | |
f741a71c JH |
1240 | if (dump |
1241 | && (reg_pref[i].prefclass != (int) best | |
1242 | || reg_pref[i].altclass != (int) alt)) | |
1243 | { | |
1244 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
4963c995 | 1245 | fprintf (dump, " Register %i", i); |
f741a71c JH |
1246 | if (alt == ALL_REGS || best == ALL_REGS) |
1247 | fprintf (dump, " pref %s\n", reg_class_names[(int) best]); | |
1248 | else if (alt == NO_REGS) | |
1249 | fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); | |
1250 | else | |
1251 | fprintf (dump, " pref %s, else %s\n", | |
1252 | reg_class_names[(int) best], | |
1253 | reg_class_names[(int) alt]); | |
1254 | } | |
1255 | ||
e4600702 | 1256 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1257 | reg_pref[i].prefclass = (int) best; |
1258 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1259 | } |
54dac99e | 1260 | } |
56a65848 | 1261 | |
4da896b2 MM |
1262 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1263 | free (in_inc_dec); | |
e79f71f7 | 1264 | #endif |
02188693 RH |
1265 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1266 | BITMAP_XFREE (reg_changes_mode); | |
4da896b2 | 1267 | #endif |
56a65848 | 1268 | free (costs); |
54dac99e RK |
1269 | } |
1270 | \f | |
e4600702 RK |
1271 | /* Record the cost of using memory or registers of various classes for |
1272 | the operands in INSN. | |
54dac99e | 1273 | |
e4600702 | 1274 | N_ALTS is the number of alternatives. |
54dac99e | 1275 | |
e4600702 RK |
1276 | N_OPS is the number of operands. |
1277 | ||
1278 | OPS is an array of the operands. | |
1279 | ||
1280 | MODES are the modes of the operands, in case any are VOIDmode. | |
1281 | ||
1282 | CONSTRAINTS are the constraints to use for the operands. This array | |
1283 | is modified by this procedure. | |
1284 | ||
1285 | This procedure works alternative by alternative. For each alternative | |
1286 | we assume that we will be able to allocate all pseudos to their ideal | |
1287 | register class and calculate the cost of using that alternative. Then | |
1288 | we compute for each operand that is a pseudo-register, the cost of | |
1289 | having the pseudo allocated to each register class and using it in that | |
1290 | alternative. To this cost is added the cost of the alternative. | |
1291 | ||
1292 | The cost of each class for this insn is its lowest cost among all the | |
1293 | alternatives. */ | |
1294 | ||
1295 | static void | |
e79f71f7 | 1296 | record_reg_classes (n_alts, n_ops, ops, modes, |
f741a71c | 1297 | constraints, insn, op_costs, reg_pref) |
e4600702 RK |
1298 | int n_alts; |
1299 | int n_ops; | |
1300 | rtx *ops; | |
1301 | enum machine_mode *modes; | |
9b3142b3 | 1302 | const char **constraints; |
e4600702 | 1303 | rtx insn; |
f741a71c JH |
1304 | struct costs *op_costs; |
1305 | struct reg_pref *reg_pref; | |
54dac99e | 1306 | { |
e4600702 | 1307 | int alt; |
e4600702 | 1308 | int i, j; |
ec2d92af | 1309 | rtx set; |
e4600702 | 1310 | |
e4600702 RK |
1311 | /* Process each alternative, each time minimizing an operand's cost with |
1312 | the cost for each operand in that alternative. */ | |
54dac99e | 1313 | |
e4600702 | 1314 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1315 | { |
e4600702 RK |
1316 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1317 | int alt_fail = 0; | |
1318 | int alt_cost = 0; | |
1319 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1320 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1321 | int class; |
54dac99e | 1322 | |
e4600702 RK |
1323 | for (i = 0; i < n_ops; i++) |
1324 | { | |
9b3142b3 | 1325 | const char *p = constraints[i]; |
e4600702 RK |
1326 | rtx op = ops[i]; |
1327 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1328 | int allows_addr = 0; |
e4600702 | 1329 | int win = 0; |
e51712db | 1330 | unsigned char c; |
54dac99e | 1331 | |
7405d9a1 DE |
1332 | /* Initially show we know nothing about the register class. */ |
1333 | classes[i] = NO_REGS; | |
da2c0219 | 1334 | allows_mem[i] = 0; |
7405d9a1 | 1335 | |
e4600702 RK |
1336 | /* If this operand has no constraints at all, we can conclude |
1337 | nothing about it since anything is valid. */ | |
54dac99e | 1338 | |
e4600702 RK |
1339 | if (*p == 0) |
1340 | { | |
1341 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
961192e1 | 1342 | memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1343 | |
e4600702 RK |
1344 | continue; |
1345 | } | |
54dac99e | 1346 | |
7405d9a1 DE |
1347 | /* If this alternative is only relevant when this operand |
1348 | matches a previous operand, we do different things depending | |
1349 | on whether this operand is a pseudo-reg or not. We must process | |
1350 | any modifiers for the operand before we can make this test. */ | |
1351 | ||
8c368ee2 | 1352 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1353 | p++; |
8c368ee2 | 1354 | |
e4600702 RK |
1355 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1356 | { | |
da2c0219 RK |
1357 | /* Copy class and whether memory is allowed from the matching |
1358 | alternative. Then perform any needed cost computations | |
1359 | and/or adjustments. */ | |
e4600702 RK |
1360 | j = p[0] - '0'; |
1361 | classes[i] = classes[j]; | |
da2c0219 | 1362 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1363 | |
1364 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1365 | { | |
1366 | /* If this matches the other operand, we have no added | |
dc903608 | 1367 | cost and we win. */ |
e4600702 | 1368 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1369 | win = 1; |
e4600702 | 1370 | |
77e67eac RK |
1371 | /* If we can put the other operand into a register, add to |
1372 | the cost of this alternative the cost to copy this | |
1373 | operand to the register used for the other operand. */ | |
e4600702 | 1374 | |
dc903608 | 1375 | else if (classes[j] != NO_REGS) |
77e67eac | 1376 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1377 | } |
07d8ca2d RS |
1378 | else if (GET_CODE (ops[j]) != REG |
1379 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1380 | { | |
1381 | /* This op is a pseudo but the one it matches is not. */ | |
1382 | ||
1383 | /* If we can't put the other operand into a register, this | |
1384 | alternative can't be used. */ | |
1385 | ||
1386 | if (classes[j] == NO_REGS) | |
1387 | alt_fail = 1; | |
e4600702 | 1388 | |
07d8ca2d RS |
1389 | /* Otherwise, add to the cost of this alternative the cost |
1390 | to copy the other operand to the register used for this | |
1391 | operand. */ | |
1392 | ||
1393 | else | |
1394 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1395 | } | |
e4600702 RK |
1396 | else |
1397 | { | |
da2c0219 RK |
1398 | /* The costs of this operand are not the same as the other |
1399 | operand since move costs are not symmetric. Moreover, | |
1400 | if we cannot tie them, this alternative needs to do a | |
1401 | copy, which is one instruction. */ | |
1402 | ||
1403 | struct costs *pp = &this_op_costs[i]; | |
1404 | ||
1405 | for (class = 0; class < N_REG_CLASSES; class++) | |
1406 | pp->cost[class] | |
d5e2075d | 1407 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1408 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1409 | : 0) |
1410 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1411 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1412 | : 0)); |
da2c0219 RK |
1413 | |
1414 | /* If the alternative actually allows memory, make things | |
1415 | a bit cheaper since we won't need an extra insn to | |
1416 | load it. */ | |
1417 | ||
1418 | pp->mem_cost | |
d5e2075d JH |
1419 | = ((recog_data.operand_type[i] != OP_IN |
1420 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1421 | : 0) | |
1422 | + (recog_data.operand_type[i] != OP_OUT | |
1423 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1424 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1425 | |
1426 | /* If we have assigned a class to this register in our | |
1427 | first pass, add a cost to this alternative corresponding | |
1428 | to what we would add if this register were not in the | |
1429 | appropriate class. */ | |
1430 | ||
9ffc5a70 | 1431 | if (reg_pref) |
da2c0219 | 1432 | alt_cost |
e56b4594 AO |
1433 | += (may_move_in_cost[mode] |
1434 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1435 | [(int) classes[i]]); |
e4600702 | 1436 | |
37747c82 RK |
1437 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1438 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1439 | alt_cost += 2; | |
e4600702 | 1440 | |
347099d6 | 1441 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1442 | for this operand, so skip to the end of the |
1443 | alternative (should be just one character). */ | |
1444 | while (*p && *p++ != ',') | |
1445 | ; | |
1446 | ||
1447 | constraints[i] = p; | |
347099d6 RS |
1448 | continue; |
1449 | } | |
e4600702 RK |
1450 | } |
1451 | ||
1452 | /* Scan all the constraint letters. See if the operand matches | |
1453 | any of the constraints. Collect the valid register classes | |
1454 | and see if this operand accepts memory. */ | |
1455 | ||
e4600702 RK |
1456 | while (*p && (c = *p++) != ',') |
1457 | switch (c) | |
1458 | { | |
e4600702 RK |
1459 | case '*': |
1460 | /* Ignore the next letter for this pass. */ | |
1461 | p++; | |
1462 | break; | |
1463 | ||
812f2051 R |
1464 | case '?': |
1465 | alt_cost += 2; | |
8c368ee2 | 1466 | case '!': case '#': case '&': |
e4600702 | 1467 | case '0': case '1': case '2': case '3': case '4': |
8c368ee2 | 1468 | case '5': case '6': case '7': case '8': case '9': |
94e6f783 DE |
1469 | break; |
1470 | ||
e4600702 | 1471 | case 'p': |
94e6f783 DE |
1472 | allows_addr = 1; |
1473 | win = address_operand (op, GET_MODE (op)); | |
46f40127 JL |
1474 | /* We know this operand is an address, so we want it to be |
1475 | allocated to a register that can be the base of an | |
1476 | address, ie BASE_REG_CLASS. */ | |
1477 | classes[i] | |
1478 | = reg_class_subunion[(int) classes[i]] | |
1479 | [(int) BASE_REG_CLASS]; | |
e4600702 RK |
1480 | break; |
1481 | ||
1482 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1483 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 | 1484 | and non-offsettable addresses here. */ |
da2c0219 | 1485 | allows_mem[i] = 1; |
e4600702 RK |
1486 | if (GET_CODE (op) == MEM) |
1487 | win = 1; | |
1488 | break; | |
1489 | ||
1490 | case '<': | |
1491 | if (GET_CODE (op) == MEM | |
1492 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1493 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1494 | win = 1; | |
1495 | break; | |
1496 | ||
1497 | case '>': | |
1498 | if (GET_CODE (op) == MEM | |
1499 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1500 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1501 | win = 1; | |
1502 | break; | |
1503 | ||
1504 | case 'E': | |
7ac2547f | 1505 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1506 | /* Match any floating double constant, but only if |
1507 | we can examine the bits of it reliably. */ | |
1508 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1509 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1510 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1511 | break; | |
7ac2547f | 1512 | #endif |
e4600702 RK |
1513 | if (GET_CODE (op) == CONST_DOUBLE) |
1514 | win = 1; | |
1515 | break; | |
1516 | ||
1517 | case 'F': | |
1518 | if (GET_CODE (op) == CONST_DOUBLE) | |
1519 | win = 1; | |
1520 | break; | |
1521 | ||
1522 | case 'G': | |
1523 | case 'H': | |
1524 | if (GET_CODE (op) == CONST_DOUBLE | |
1525 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1526 | win = 1; | |
1527 | break; | |
1528 | ||
1529 | case 's': | |
1530 | if (GET_CODE (op) == CONST_INT | |
1531 | || (GET_CODE (op) == CONST_DOUBLE | |
1532 | && GET_MODE (op) == VOIDmode)) | |
1533 | break; | |
1534 | case 'i': | |
1535 | if (CONSTANT_P (op) | |
1536 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1537 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1538 | #endif | |
1539 | ) | |
1540 | win = 1; | |
1541 | break; | |
1542 | ||
1543 | case 'n': | |
1544 | if (GET_CODE (op) == CONST_INT | |
1545 | || (GET_CODE (op) == CONST_DOUBLE | |
1546 | && GET_MODE (op) == VOIDmode)) | |
1547 | win = 1; | |
1548 | break; | |
1549 | ||
1550 | case 'I': | |
1551 | case 'J': | |
1552 | case 'K': | |
1553 | case 'L': | |
1554 | case 'M': | |
1555 | case 'N': | |
1556 | case 'O': | |
1557 | case 'P': | |
1558 | if (GET_CODE (op) == CONST_INT | |
1559 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1560 | win = 1; | |
1561 | break; | |
1562 | ||
1563 | case 'X': | |
1564 | win = 1; | |
1565 | break; | |
54dac99e | 1566 | |
e4600702 RK |
1567 | case 'g': |
1568 | if (GET_CODE (op) == MEM | |
1569 | || (CONSTANT_P (op) | |
1570 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1571 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1572 | #endif |
e4600702 RK |
1573 | )) |
1574 | win = 1; | |
da2c0219 | 1575 | allows_mem[i] = 1; |
e4600702 RK |
1576 | case 'r': |
1577 | classes[i] | |
1578 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1579 | break; | |
1580 | ||
1581 | default: | |
c2cba7a9 RH |
1582 | if (REG_CLASS_FROM_LETTER (c) != NO_REGS) |
1583 | classes[i] | |
1584 | = reg_class_subunion[(int) classes[i]] | |
1585 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1586 | #ifdef EXTRA_CONSTRAINT | |
1587 | else if (EXTRA_CONSTRAINT (op, c)) | |
1588 | win = 1; | |
1589 | #endif | |
1590 | break; | |
e4600702 RK |
1591 | } |
1592 | ||
1593 | constraints[i] = p; | |
1594 | ||
1595 | /* How we account for this operand now depends on whether it is a | |
1596 | pseudo register or not. If it is, we first check if any | |
1597 | register classes are valid. If not, we ignore this alternative, | |
1598 | since we want to assume that all pseudos get allocated for | |
1599 | register preferencing. If some register class is valid, compute | |
1600 | the costs of moving the pseudo into that class. */ | |
1601 | ||
1602 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1603 | { |
e4600702 | 1604 | if (classes[i] == NO_REGS) |
94e6f783 | 1605 | { |
e79f71f7 GK |
1606 | /* We must always fail if the operand is a REG, but |
1607 | we did not find a suitable class. | |
1608 | ||
1609 | Otherwise we may perform an uninitialized read | |
1610 | from this_op_costs after the `continue' statement | |
1611 | below. */ | |
1612 | alt_fail = 1; | |
94e6f783 | 1613 | } |
e4600702 RK |
1614 | else |
1615 | { | |
1616 | struct costs *pp = &this_op_costs[i]; | |
1617 | ||
1618 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1619 | pp->cost[class] |
d5e2075d | 1620 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1621 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1622 | : 0) |
1623 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1624 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1625 | : 0)); |
e4600702 RK |
1626 | |
1627 | /* If the alternative actually allows memory, make things | |
1628 | a bit cheaper since we won't need an extra insn to | |
1629 | load it. */ | |
1630 | ||
14a774a9 | 1631 | pp->mem_cost |
d5e2075d JH |
1632 | = ((recog_data.operand_type[i] != OP_IN |
1633 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1634 | : 0) | |
1635 | + (recog_data.operand_type[i] != OP_OUT | |
1636 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1637 | : 0) - allows_mem[i]); | |
e4600702 RK |
1638 | |
1639 | /* If we have assigned a class to this register in our | |
1640 | first pass, add a cost to this alternative corresponding | |
1641 | to what we would add if this register were not in the | |
1642 | appropriate class. */ | |
1643 | ||
9ffc5a70 | 1644 | if (reg_pref) |
e4600702 | 1645 | alt_cost |
e56b4594 AO |
1646 | += (may_move_in_cost[mode] |
1647 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1648 | [(int) classes[i]]); |
e4600702 | 1649 | } |
4db18574 | 1650 | } |
54dac99e | 1651 | |
e4600702 RK |
1652 | /* Otherwise, if this alternative wins, either because we |
1653 | have already determined that or if we have a hard register of | |
1654 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1655 | |
e4600702 RK |
1656 | else if (win |
1657 | || (GET_CODE (op) == REG | |
6f654776 | 1658 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1659 | ; |
54dac99e | 1660 | |
e4600702 RK |
1661 | /* If registers are valid, the cost of this alternative includes |
1662 | copying the object to and/or from a register. */ | |
54dac99e | 1663 | |
e4600702 RK |
1664 | else if (classes[i] != NO_REGS) |
1665 | { | |
1ccbefce | 1666 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1667 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1668 | |
1ccbefce | 1669 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1670 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1671 | } | |
54dac99e | 1672 | |
e4600702 RK |
1673 | /* The only other way this alternative can be used is if this is a |
1674 | constant that could be placed into memory. */ | |
1675 | ||
da2c0219 | 1676 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1677 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1678 | else |
1679 | alt_fail = 1; | |
1680 | } | |
1681 | ||
1682 | if (alt_fail) | |
1683 | continue; | |
1684 | ||
1685 | /* Finally, update the costs with the information we've calculated | |
1686 | about this alternative. */ | |
1687 | ||
1688 | for (i = 0; i < n_ops; i++) | |
1689 | if (GET_CODE (ops[i]) == REG | |
1690 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1691 | { |
e4600702 | 1692 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1693 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1694 | |
e4600702 RK |
1695 | pp->mem_cost = MIN (pp->mem_cost, |
1696 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1697 | |
e4600702 RK |
1698 | for (class = 0; class < N_REG_CLASSES; class++) |
1699 | pp->cost[class] = MIN (pp->cost[class], | |
1700 | (qq->cost[class] + alt_cost) * scale); | |
1701 | } | |
1702 | } | |
ec2d92af RK |
1703 | |
1704 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1705 | and one operand is a pseudo with the other a hard reg or a pseudo |
1706 | that prefers a register that is in its own register class then | |
1707 | we may want to adjust the cost of that register class to -1. | |
1708 | ||
1709 | Avoid the adjustment if the source does not die to avoid stressing of | |
1710 | register allocator by preferrencing two coliding registers into single | |
1711 | class. | |
1712 | ||
1713 | Also avoid the adjustment if a copy between registers of the class | |
1714 | is expensive (ten times the cost of a default copy is considered | |
1715 | arbitrarily expensive). This avoids losing when the preferred class | |
1716 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1717 | |
1718 | if ((set = single_set (insn)) != 0 | |
1719 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
0dc0641b JH |
1720 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG |
1721 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
ec2d92af RK |
1722 | for (i = 0; i <= 1; i++) |
1723 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1724 | { | |
770ae6cc | 1725 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1726 | enum machine_mode mode = GET_MODE (ops[!i]); |
1727 | int class; | |
770ae6cc | 1728 | unsigned int nr; |
ec2d92af | 1729 | |
accef103 JL |
1730 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1731 | { | |
1732 | enum reg_class pref = reg_pref[regno].prefclass; | |
1733 | ||
1734 | if ((reg_class_size[(unsigned char) pref] | |
1735 | == CLASS_MAX_NREGS (pref, mode)) | |
e56b4594 | 1736 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1737 | op_costs[i].cost[(unsigned char) pref] = -1; |
1738 | } | |
ec2d92af RK |
1739 | else if (regno < FIRST_PSEUDO_REGISTER) |
1740 | for (class = 0; class < N_REG_CLASSES; class++) | |
1741 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1742 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1743 | { |
1744 | if (reg_class_size[class] == 1) | |
1745 | op_costs[i].cost[class] = -1; | |
1746 | else | |
1747 | { | |
770ae6cc | 1748 | for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++) |
4841ba4b | 1749 | { |
770ae6cc RK |
1750 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1751 | regno + nr)) | |
4841ba4b RK |
1752 | break; |
1753 | } | |
1754 | ||
770ae6cc | 1755 | if (nr == HARD_REGNO_NREGS (regno,mode)) |
4841ba4b RK |
1756 | op_costs[i].cost[class] = -1; |
1757 | } | |
1758 | } | |
ec2d92af | 1759 | } |
54dac99e | 1760 | } |
e4600702 RK |
1761 | \f |
1762 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1763 | TO_P is zero) a register of class CLASS in mode MODE. | |
1764 | ||
1765 | X must not be a pseudo. */ | |
1766 | ||
1767 | static int | |
1768 | copy_cost (x, mode, class, to_p) | |
1769 | rtx x; | |
d0af450d | 1770 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e4600702 | 1771 | enum reg_class class; |
d0af450d | 1772 | int to_p ATTRIBUTE_UNUSED; |
e4600702 | 1773 | { |
29a82058 | 1774 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1775 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1776 | #endif |
e4600702 RK |
1777 | |
1778 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1779 | assuming optimal allocation. */ | |
1780 | ||
1781 | if (GET_CODE (x) == SCRATCH) | |
1782 | return 0; | |
1783 | ||
1784 | /* Get the class we will actually use for a reload. */ | |
1785 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1786 | ||
1787 | #ifdef HAVE_SECONDARY_RELOADS | |
1788 | /* If we need a secondary reload (we assume here that we are using | |
1789 | the secondary reload as an intermediate, not a scratch register), the | |
1790 | cost is that to load the input into the intermediate register, then | |
1791 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1792 | ||
1793 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1794 | if (to_p == 1) | |
1795 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1796 | #endif | |
1797 | ||
dd9f0e8f | 1798 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1799 | if (! to_p) |
1800 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1801 | #endif | |
1802 | ||
1803 | if (secondary_class != NO_REGS) | |
e56b4594 | 1804 | return (move_cost[mode][(int) secondary_class][(int) class] |
e4600702 | 1805 | + copy_cost (x, mode, secondary_class, 2)); |
dd9f0e8f | 1806 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1807 | |
1808 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1809 | cost to move between the register classes, and use 2 for everything | |
1810 | else (constants). */ | |
1811 | ||
1812 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1813 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1814 | |
e4600702 | 1815 | else if (GET_CODE (x) == REG) |
e56b4594 | 1816 | return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
e4600702 RK |
1817 | |
1818 | else | |
1819 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
b437f1a7 | 1820 | return COSTS_N_INSNS (1); |
e4600702 RK |
1821 | } |
1822 | \f | |
54dac99e RK |
1823 | /* Record the pseudo registers we must reload into hard registers |
1824 | in a subexpression of a memory address, X. | |
e4600702 RK |
1825 | |
1826 | CLASS is the class that the register needs to be in and is either | |
1827 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1828 | ||
1829 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1830 | can represent half-cost adjustments). */ | |
54dac99e | 1831 | |
197d6480 | 1832 | static void |
e4600702 | 1833 | record_address_regs (x, class, scale) |
54dac99e | 1834 | rtx x; |
e4600702 RK |
1835 | enum reg_class class; |
1836 | int scale; | |
54dac99e RK |
1837 | { |
1838 | register enum rtx_code code = GET_CODE (x); | |
1839 | ||
1840 | switch (code) | |
1841 | { | |
1842 | case CONST_INT: | |
1843 | case CONST: | |
1844 | case CC0: | |
1845 | case PC: | |
1846 | case SYMBOL_REF: | |
1847 | case LABEL_REF: | |
1848 | return; | |
1849 | ||
1850 | case PLUS: | |
1851 | /* When we have an address that is a sum, | |
1852 | we must determine whether registers are "base" or "index" regs. | |
1853 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1854 | the "base". Luckily, we can use the REG_POINTER to make a good |
1855 | choice most of the time. We only need to do this on machines | |
1856 | that can have two registers in an address and where the base | |
1857 | and index register classes are different. | |
e4600702 RK |
1858 | |
1859 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1860 | that seems bogus since it should only be set when we are sure | |
1861 | the register is being used as a pointer. */ | |
1862 | ||
54dac99e RK |
1863 | { |
1864 | rtx arg0 = XEXP (x, 0); | |
1865 | rtx arg1 = XEXP (x, 1); | |
1866 | register enum rtx_code code0 = GET_CODE (arg0); | |
1867 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1868 | |
1869 | /* Look inside subregs. */ | |
e4600702 | 1870 | if (code0 == SUBREG) |
54dac99e | 1871 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1872 | if (code1 == SUBREG) |
54dac99e RK |
1873 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1874 | ||
e4600702 RK |
1875 | /* If this machine only allows one register per address, it must |
1876 | be in the first operand. */ | |
1877 | ||
1878 | if (MAX_REGS_PER_ADDRESS == 1) | |
1879 | record_address_regs (arg0, class, scale); | |
1880 | ||
1881 | /* If index and base registers are the same on this machine, just | |
1882 | record registers in any non-constant operands. We assume here, | |
1883 | as well as in the tests below, that all addresses are in | |
1884 | canonical form. */ | |
1885 | ||
1886 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1887 | { |
e4600702 RK |
1888 | record_address_regs (arg0, class, scale); |
1889 | if (! CONSTANT_P (arg1)) | |
1890 | record_address_regs (arg1, class, scale); | |
54dac99e | 1891 | } |
e4600702 RK |
1892 | |
1893 | /* If the second operand is a constant integer, it doesn't change | |
1894 | what class the first operand must be. */ | |
1895 | ||
1896 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1897 | record_address_regs (arg0, class, scale); | |
1898 | ||
1899 | /* If the second operand is a symbolic constant, the first operand | |
1900 | must be an index register. */ | |
1901 | ||
1902 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1903 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1904 | ||
956d6950 JL |
1905 | /* If both operands are registers but one is already a hard register |
1906 | of index or base class, give the other the class that the hard | |
1907 | register is not. */ | |
1908 | ||
3f9e9508 | 1909 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1910 | else if (code0 == REG && code1 == REG |
1911 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1912 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1913 | record_address_regs (arg1, | |
1914 | REG_OK_FOR_BASE_P (arg0) | |
1915 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1916 | scale); | |
1917 | else if (code0 == REG && code1 == REG | |
1918 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1919 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1920 | record_address_regs (arg0, | |
1921 | REG_OK_FOR_BASE_P (arg1) | |
1922 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1923 | scale); | |
3f9e9508 | 1924 | #endif |
956d6950 | 1925 | |
e9a25f70 JL |
1926 | /* If one operand is known to be a pointer, it must be the base |
1927 | with the other operand the index. Likewise if the other operand | |
1928 | is a MULT. */ | |
f22376c7 | 1929 | |
3502dc9c | 1930 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 1931 | || code1 == MULT) |
f22376c7 CI |
1932 | { |
1933 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1934 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1935 | } | |
3502dc9c | 1936 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 1937 | || code0 == MULT) |
f22376c7 CI |
1938 | { |
1939 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1940 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1941 | } | |
1942 | ||
e9a25f70 | 1943 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1944 | or index register. This case should be rare. */ |
1945 | ||
e9a25f70 | 1946 | else |
54dac99e | 1947 | { |
e4600702 RK |
1948 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1949 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1950 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1951 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1952 | } |
54dac99e RK |
1953 | } |
1954 | break; | |
1955 | ||
4b983fdc RH |
1956 | /* Double the importance of a pseudo register that is incremented |
1957 | or decremented, since it would take two extra insns | |
1958 | if it ends up in the wrong place. */ | |
1959 | case POST_MODIFY: | |
1960 | case PRE_MODIFY: | |
1961 | record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale); | |
1962 | if (REG_P (XEXP (XEXP (x, 1), 1))) | |
1963 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
1964 | INDEX_REG_CLASS, 2 * scale); | |
1965 | break; | |
1966 | ||
54dac99e RK |
1967 | case POST_INC: |
1968 | case PRE_INC: | |
1969 | case POST_DEC: | |
1970 | case PRE_DEC: | |
1971 | /* Double the importance of a pseudo register that is incremented | |
1972 | or decremented, since it would take two extra insns | |
533d0835 RK |
1973 | if it ends up in the wrong place. If the operand is a pseudo, |
1974 | show it is being used in an INC_DEC context. */ | |
1975 | ||
1976 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1977 | if (GET_CODE (XEXP (x, 0)) == REG | |
1978 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1979 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1980 | #endif | |
e4600702 RK |
1981 | |
1982 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1983 | break; |
1984 | ||
1985 | case REG: | |
1986 | { | |
e4600702 RK |
1987 | register struct costs *pp = &costs[REGNO (x)]; |
1988 | register int i; | |
54dac99e | 1989 | |
cbd5b9a2 | 1990 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1991 | |
e4600702 | 1992 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 1993 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
1994 | } |
1995 | break; | |
1996 | ||
1997 | default: | |
1998 | { | |
6f7d635c | 1999 | register const char *fmt = GET_RTX_FORMAT (code); |
54dac99e RK |
2000 | register int i; |
2001 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2002 | if (fmt[i] == 'e') | |
e4600702 | 2003 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
2004 | } |
2005 | } | |
2006 | } | |
08d95f91 RK |
2007 | \f |
2008 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2009 | ||
2010 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2011 | to an object of MODE. */ | |
2012 | ||
1d300e19 | 2013 | static int |
08d95f91 RK |
2014 | auto_inc_dec_reg_p (reg, mode) |
2015 | rtx reg; | |
2016 | enum machine_mode mode; | |
2017 | { | |
940da324 JL |
2018 | if (HAVE_POST_INCREMENT |
2019 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2020 | return 1; |
08d95f91 | 2021 | |
940da324 JL |
2022 | if (HAVE_POST_DECREMENT |
2023 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2024 | return 1; |
08d95f91 | 2025 | |
940da324 JL |
2026 | if (HAVE_PRE_INCREMENT |
2027 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2028 | return 1; |
08d95f91 | 2029 | |
940da324 JL |
2030 | if (HAVE_PRE_DECREMENT |
2031 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2032 | return 1; |
08d95f91 RK |
2033 | |
2034 | return 0; | |
2035 | } | |
2036 | #endif | |
b1f21e0a | 2037 | \f |
da668e9c MM |
2038 | static short *renumber; |
2039 | static size_t regno_allocated; | |
2040 | static unsigned int reg_n_max; | |
ed396e68 | 2041 | |
b1f21e0a MM |
2042 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2043 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
2044 | NEW_P is non zero, initialize all of the registers, otherwise only |
2045 | initialize the new registers allocated. The same table is kept from | |
2046 | function to function, only reallocating it when we need more room. If | |
2047 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
2048 | |
2049 | void | |
39379e67 | 2050 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 2051 | size_t num_regs; |
b1f21e0a | 2052 | int new_p; |
39379e67 | 2053 | int renumber_p; |
b1f21e0a | 2054 | { |
6feacd09 MM |
2055 | size_t size_info; |
2056 | size_t size_renumber; | |
2057 | size_t min = (new_p) ? 0 : reg_n_max; | |
2058 | struct reg_info_data *reg_data; | |
39379e67 | 2059 | |
b1f21e0a MM |
2060 | if (num_regs > regno_allocated) |
2061 | { | |
6feacd09 MM |
2062 | size_t old_allocated = regno_allocated; |
2063 | ||
b1f21e0a | 2064 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
2065 | size_renumber = regno_allocated * sizeof (short); |
2066 | ||
2067 | if (!reg_n_info) | |
2068 | { | |
6feacd09 | 2069 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 2070 | renumber = (short *) xmalloc (size_renumber); |
9ffc5a70 JH |
2071 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
2072 | * sizeof (struct reg_pref)); | |
39379e67 MM |
2073 | } |
2074 | ||
2075 | else | |
2076 | { | |
6feacd09 MM |
2077 | VARRAY_GROW (reg_n_info, regno_allocated); |
2078 | ||
2079 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
2080 | { | |
2081 | free ((char *)renumber); | |
9ffc5a70 | 2082 | free ((char *)reg_pref); |
6feacd09 | 2083 | renumber = (short *) xmalloc (size_renumber); |
9ffc5a70 JH |
2084 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
2085 | * sizeof (struct reg_pref)); | |
6feacd09 MM |
2086 | } |
2087 | ||
2088 | else | |
2089 | { | |
2090 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
9ffc5a70 JH |
2091 | reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer, |
2092 | regno_allocated | |
2093 | * sizeof (struct reg_pref)); | |
6feacd09 | 2094 | } |
39379e67 | 2095 | } |
6feacd09 MM |
2096 | |
2097 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2098 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
2099 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
2100 | reg_data->min_index = old_allocated; | |
2101 | reg_data->max_index = regno_allocated - 1; | |
2102 | reg_data->next = reg_info_head; | |
2103 | reg_info_head = reg_data; | |
b1f21e0a MM |
2104 | } |
2105 | ||
6feacd09 | 2106 | reg_n_max = num_regs; |
b1f21e0a MM |
2107 | if (min < num_regs) |
2108 | { | |
6feacd09 MM |
2109 | /* Loop through each of the segments allocated for the actual |
2110 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
da668e9c MM |
2111 | for (reg_data = reg_info_head; |
2112 | reg_data && reg_data->max_index >= min; | |
2113 | reg_data = reg_data->next) | |
39379e67 | 2114 | { |
6feacd09 MM |
2115 | size_t min_index = reg_data->min_index; |
2116 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2117 | size_t max = MIN (max_index, num_regs); |
2118 | size_t local_min = min - min_index; | |
2119 | size_t i; | |
6feacd09 | 2120 | |
da668e9c MM |
2121 | if (reg_data->min_index > num_regs) |
2122 | continue; | |
6feacd09 | 2123 | |
da668e9c MM |
2124 | if (min < min_index) |
2125 | local_min = 0; | |
2126 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2127 | reg_data->used_p = 1; /* no need to zero */ | |
2128 | else | |
961192e1 | 2129 | memset ((char *) ®_data->data[local_min], 0, |
da668e9c MM |
2130 | sizeof (reg_info) * (max - min_index - local_min + 1)); |
2131 | ||
2132 | for (i = min_index+local_min; i <= max; i++) | |
2133 | { | |
2134 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2135 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2136 | renumber[i] = -1; | |
2137 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2138 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2139 | } |
39379e67 | 2140 | } |
b1f21e0a MM |
2141 | } |
2142 | ||
6feacd09 MM |
2143 | /* If {pref,alt}class have already been allocated, update the pointers to |
2144 | the newly realloced ones. */ | |
9ffc5a70 JH |
2145 | if (reg_pref) |
2146 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2147 | |
39379e67 MM |
2148 | if (renumber_p) |
2149 | reg_renumber = renumber; | |
2150 | ||
73b76448 RK |
2151 | /* Tell the regset code about the new number of registers */ |
2152 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
2153 | } |
2154 | ||
ed396e68 BS |
2155 | /* Free up the space allocated by allocate_reg_info. */ |
2156 | void | |
2157 | free_reg_info () | |
2158 | { | |
2159 | if (reg_n_info) | |
2160 | { | |
2161 | struct reg_info_data *reg_data; | |
2162 | struct reg_info_data *reg_next; | |
2163 | ||
2164 | VARRAY_FREE (reg_n_info); | |
2165 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2166 | { | |
2167 | reg_next = reg_data->next; | |
2168 | free ((char *)reg_data); | |
2169 | } | |
2170 | ||
9ffc5a70 JH |
2171 | free (reg_pref_buffer); |
2172 | reg_pref_buffer = (struct reg_pref *)0; | |
ed396e68 BS |
2173 | reg_info_head = (struct reg_info_data *)0; |
2174 | renumber = (short *)0; | |
2175 | } | |
2176 | regno_allocated = 0; | |
2177 | reg_n_max = 0; | |
2178 | } | |
54dac99e RK |
2179 | \f |
2180 | /* This is the `regscan' pass of the compiler, run just before cse | |
2181 | and again just before loop. | |
2182 | ||
2183 | It finds the first and last use of each pseudo-register | |
2184 | and records them in the vectors regno_first_uid, regno_last_uid | |
2185 | and counts the number of sets in the vector reg_n_sets. | |
2186 | ||
2187 | REPEAT is nonzero the second time this is called. */ | |
2188 | ||
54dac99e | 2189 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2190 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
2191 | and we want this to remain correct for all the remaining passes. */ |
2192 | ||
2193 | int max_parallel; | |
2194 | ||
54dac99e RK |
2195 | void |
2196 | reg_scan (f, nregs, repeat) | |
2197 | rtx f; | |
770ae6cc | 2198 | unsigned int nregs; |
272df862 | 2199 | int repeat ATTRIBUTE_UNUSED; |
54dac99e RK |
2200 | { |
2201 | register rtx insn; | |
2202 | ||
39379e67 | 2203 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
2204 | max_parallel = 3; |
2205 | ||
2206 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2207 | if (GET_CODE (insn) == INSN | |
2208 | || GET_CODE (insn) == CALL_INSN | |
2209 | || GET_CODE (insn) == JUMP_INSN) | |
2210 | { | |
2211 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2212 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2213 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2214 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2215 | |
2216 | if (REG_NOTES (insn)) | |
f903b91f DM |
2217 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2218 | } | |
2219 | } | |
2220 | ||
2221 | /* Update 'regscan' information by looking at the insns | |
2222 | from FIRST to LAST. Some new REGs have been created, | |
2223 | and any REG with number greater than OLD_MAX_REGNO is | |
2224 | such a REG. We only update information for those. */ | |
2225 | ||
2226 | void | |
770ae6cc | 2227 | reg_scan_update (first, last, old_max_regno) |
f903b91f DM |
2228 | rtx first; |
2229 | rtx last; | |
770ae6cc | 2230 | unsigned int old_max_regno; |
f903b91f DM |
2231 | { |
2232 | register rtx insn; | |
2233 | ||
2234 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2235 | ||
2236 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2237 | if (GET_CODE (insn) == INSN | |
2238 | || GET_CODE (insn) == CALL_INSN | |
2239 | || GET_CODE (insn) == JUMP_INSN) | |
2240 | { | |
2241 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2242 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2243 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2244 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2245 | ||
2246 | if (REG_NOTES (insn)) | |
2247 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2248 | } |
2249 | } | |
2250 | ||
1ebecb64 | 2251 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2252 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2253 | We should only record information for REGs with numbers | |
2254 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2255 | |
08d95f91 | 2256 | static void |
f903b91f | 2257 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2258 | rtx x; |
be8dcd74 | 2259 | rtx insn; |
1ebecb64 | 2260 | int note_flag; |
770ae6cc | 2261 | unsigned int min_regno; |
54dac99e | 2262 | { |
fa23c636 | 2263 | register enum rtx_code code; |
54dac99e | 2264 | register rtx dest; |
be8dcd74 | 2265 | register rtx note; |
54dac99e | 2266 | |
fa23c636 | 2267 | code = GET_CODE (x); |
54dac99e RK |
2268 | switch (code) |
2269 | { | |
54dac99e | 2270 | case CONST: |
185ebd6c | 2271 | case CONST_INT: |
54dac99e RK |
2272 | case CONST_DOUBLE: |
2273 | case CC0: | |
2274 | case PC: | |
2275 | case SYMBOL_REF: | |
2276 | case LABEL_REF: | |
2277 | case ADDR_VEC: | |
2278 | case ADDR_DIFF_VEC: | |
2279 | return; | |
2280 | ||
2281 | case REG: | |
2282 | { | |
770ae6cc | 2283 | unsigned int regno = REGNO (x); |
54dac99e | 2284 | |
f903b91f DM |
2285 | if (regno >= min_regno) |
2286 | { | |
2287 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2288 | if (!note_flag) | |
2289 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2290 | if (REGNO_FIRST_UID (regno) == 0) | |
2291 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
2292 | } | |
54dac99e RK |
2293 | } |
2294 | break; | |
2295 | ||
01565a55 | 2296 | case EXPR_LIST: |
7b18c3db | 2297 | if (XEXP (x, 0)) |
f903b91f | 2298 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2299 | if (XEXP (x, 1)) |
f903b91f | 2300 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2301 | break; |
2302 | ||
2303 | case INSN_LIST: | |
2304 | if (XEXP (x, 1)) | |
f903b91f | 2305 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2306 | break; |
2307 | ||
54dac99e RK |
2308 | case SET: |
2309 | /* Count a set of the destination if it is a register. */ | |
2310 | for (dest = SET_DEST (x); | |
2311 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2312 | || GET_CODE (dest) == ZERO_EXTEND; | |
2313 | dest = XEXP (dest, 0)) | |
2314 | ; | |
2315 | ||
f903b91f DM |
2316 | if (GET_CODE (dest) == REG |
2317 | && REGNO (dest) >= min_regno) | |
b1f21e0a | 2318 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 2319 | |
be8dcd74 RK |
2320 | /* If this is setting a pseudo from another pseudo or the sum of a |
2321 | pseudo and a constant integer and the other pseudo is known to be | |
2322 | a pointer, set the destination to be a pointer as well. | |
2323 | ||
2324 | Likewise if it is setting the destination from an address or from a | |
2325 | value equivalent to an address or to the sum of an address and | |
2326 | something else. | |
2327 | ||
2328 | But don't do any of this if the pseudo corresponds to a user | |
2329 | variable since it should have already been set as a pointer based | |
2330 | on the type. */ | |
2331 | ||
2332 | if (GET_CODE (SET_DEST (x)) == REG | |
2333 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2334 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2335 | /* If the destination pseudo is set more than once, then other |
2336 | sets might not be to a pointer value (consider access to a | |
2337 | union in two threads of control in the presense of global | |
3502dc9c | 2338 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2339 | pseudo if this is the only set of that pseudo. */ |
2340 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2341 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2342 | && ! REG_POINTER (SET_DEST (x)) |
be8dcd74 | 2343 | && ((GET_CODE (SET_SRC (x)) == REG |
3502dc9c | 2344 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2345 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2346 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2347 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2348 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3502dc9c | 2349 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2350 | || GET_CODE (SET_SRC (x)) == CONST |
2351 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2352 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2353 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2354 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2355 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2356 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2357 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2358 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2359 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2360 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2361 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2362 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2363 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2364 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2365 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2366 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2367 | |
0f41302f | 2368 | /* ... fall through ... */ |
54dac99e RK |
2369 | |
2370 | default: | |
2371 | { | |
6f7d635c | 2372 | register const char *fmt = GET_RTX_FORMAT (code); |
54dac99e RK |
2373 | register int i; |
2374 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2375 | { | |
2376 | if (fmt[i] == 'e') | |
f903b91f | 2377 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2378 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2379 | { | |
2380 | register int j; | |
2381 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f903b91f | 2382 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2383 | } |
2384 | } | |
2385 | } | |
2386 | } | |
2387 | } | |
2388 | \f | |
2389 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2390 | is also in C2. */ | |
2391 | ||
2392 | int | |
2393 | reg_class_subset_p (c1, c2) | |
2394 | register enum reg_class c1; | |
2395 | register enum reg_class c2; | |
2396 | { | |
2397 | if (c1 == c2) return 1; | |
2398 | ||
2399 | if (c2 == ALL_REGS) | |
2400 | win: | |
2401 | return 1; | |
2402 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
2403 | reg_class_contents[(int)c2], | |
2404 | win); | |
2405 | return 0; | |
2406 | } | |
2407 | ||
2408 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2409 | ||
2410 | int | |
2411 | reg_classes_intersect_p (c1, c2) | |
2412 | register enum reg_class c1; | |
2413 | register enum reg_class c2; | |
2414 | { | |
2415 | #ifdef HARD_REG_SET | |
2416 | register | |
2417 | #endif | |
2418 | HARD_REG_SET c; | |
2419 | ||
2420 | if (c1 == c2) return 1; | |
2421 | ||
2422 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2423 | return 1; | |
2424 | ||
2425 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2426 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2427 | ||
2428 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2429 | return 1; | |
2430 | ||
2431 | lose: | |
2432 | return 0; | |
2433 | } | |
2434 | ||
73b76448 RK |
2435 | /* Release any memory allocated by register sets. */ |
2436 | ||
2437 | void | |
2438 | regset_release_memory () | |
2439 | { | |
73b76448 RK |
2440 | bitmap_release_memory (); |
2441 | } |