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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
f4f4d0f8 | 3 | 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
54dac99e | 4 | |
1322177d | 5 | This file is part of GCC. |
54dac99e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
54dac99e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
54dac99e RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
54dac99e RK |
21 | |
22 | ||
23 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
24 | It also defines some tables of information about the hardware registers | |
25 | and a function init_reg_sets to initialize the tables. */ | |
26 | ||
27 | #include "config.h" | |
670ee920 | 28 | #include "system.h" |
54dac99e | 29 | #include "rtl.h" |
0829d244 | 30 | #include "expr.h" |
6baf1cc8 | 31 | #include "tm_p.h" |
54dac99e RK |
32 | #include "hard-reg-set.h" |
33 | #include "flags.h" | |
34 | #include "basic-block.h" | |
35 | #include "regs.h" | |
49ad7cfa | 36 | #include "function.h" |
54dac99e RK |
37 | #include "insn-config.h" |
38 | #include "recog.h" | |
e4600702 RK |
39 | #include "reload.h" |
40 | #include "real.h" | |
10f0ad3d | 41 | #include "toplev.h" |
d6f4ec51 | 42 | #include "output.h" |
8b0212ca | 43 | #include "ggc.h" |
54dac99e RK |
44 | |
45 | #ifndef REGISTER_MOVE_COST | |
e56b4594 | 46 | #define REGISTER_MOVE_COST(m, x, y) 2 |
54dac99e RK |
47 | #endif |
48 | ||
13536812 KG |
49 | static void init_reg_sets_1 PARAMS ((void)); |
50 | static void init_reg_modes PARAMS ((void)); | |
24deb20a | 51 | |
533d0835 RK |
52 | /* If we have auto-increment or auto-decrement and we can have secondary |
53 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 54 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
55 | |
56 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 57 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
58 | #define FORBIDDEN_INC_DEC_CLASSES |
59 | #endif | |
60 | #endif | |
54dac99e RK |
61 | \f |
62 | /* Register tables used by many passes. */ | |
63 | ||
64 | /* Indexed by hard register number, contains 1 for registers | |
65 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
66 | These are the registers that cannot be used to allocate | |
252f342a | 67 | a pseudo reg for general use. */ |
54dac99e RK |
68 | |
69 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
70 | ||
71 | /* Same info as a HARD_REG_SET. */ | |
72 | ||
73 | HARD_REG_SET fixed_reg_set; | |
74 | ||
75 | /* Data for initializing the above. */ | |
76 | ||
8b60264b | 77 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
54dac99e RK |
78 | |
79 | /* Indexed by hard register number, contains 1 for registers | |
80 | that are fixed use or are clobbered by function calls. | |
81 | These are the registers that cannot be used to allocate | |
252f342a MH |
82 | a pseudo reg whose life crosses calls unless we are able |
83 | to save/restore them across the calls. */ | |
54dac99e RK |
84 | |
85 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
86 | ||
87 | /* Same info as a HARD_REG_SET. */ | |
88 | ||
89 | HARD_REG_SET call_used_reg_set; | |
90 | ||
6cad67d2 JL |
91 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
92 | HARD_REG_SET losing_caller_save_reg_set; | |
93 | ||
54dac99e RK |
94 | /* Data for initializing the above. */ |
95 | ||
8b60264b | 96 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
fc1296b7 AM |
97 | |
98 | /* This is much like call_used_regs, except it doesn't have to | |
99 | be a superset of FIXED_REGISTERS. This vector indicates | |
a6a2274a | 100 | what is really call clobbered, and is used when defining |
fc1296b7 AM |
101 | regs_invalidated_by_call. */ |
102 | ||
fc1296b7 | 103 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa | 104 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
fc1296b7 | 105 | #endif |
a6a2274a | 106 | |
54dac99e | 107 | /* Indexed by hard register number, contains 1 for registers that are |
252f342a MH |
108 | fixed use or call used registers that cannot hold quantities across |
109 | calls even if we are willing to save and restore them. call fixed | |
110 | registers are a subset of call used registers. */ | |
54dac99e RK |
111 | |
112 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
113 | ||
114 | /* The same info as a HARD_REG_SET. */ | |
115 | ||
116 | HARD_REG_SET call_fixed_reg_set; | |
117 | ||
118 | /* Number of non-fixed registers. */ | |
119 | ||
120 | int n_non_fixed_regs; | |
121 | ||
122 | /* Indexed by hard register number, contains 1 for registers | |
123 | that are being used for global register decls. | |
124 | These must be exempt from ordinary flow analysis | |
125 | and are also considered fixed. */ | |
126 | ||
127 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
4e2db584 RH |
128 | |
129 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
130 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
131 | for someone's bright idea to have call_used_regs strictly include | |
132 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
133 | that are actually preserved. We know for sure that those associated | |
134 | with the local stack frame are safe, but scant others. */ | |
135 | ||
136 | HARD_REG_SET regs_invalidated_by_call; | |
137 | ||
54dac99e RK |
138 | /* Table of register numbers in the order in which to try to use them. */ |
139 | #ifdef REG_ALLOC_ORDER | |
140 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
141 | |
142 | /* The inverse of reg_alloc_order. */ | |
143 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
144 | #endif |
145 | ||
146 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
147 | ||
2e0e2b76 CH |
148 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
149 | ||
089e575b RS |
150 | /* The same information, but as an array of unsigned ints. We copy from |
151 | these unsigned ints to the table above. We do this so the tm.h files | |
d4845339 RH |
152 | do not have to be aware of the wordsize for machines with <= 64 regs. |
153 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
2e0e2b76 CH |
154 | |
155 | #define N_REG_INTS \ | |
d4845339 | 156 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
2e0e2b76 | 157 | |
a6a2274a | 158 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 159 | = REG_CLASS_CONTENTS; |
54dac99e RK |
160 | |
161 | /* For each reg class, number of regs it contains. */ | |
162 | ||
770ae6cc | 163 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
164 | |
165 | /* For each reg class, table listing all the containing classes. */ | |
166 | ||
167 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
168 | ||
169 | /* For each reg class, table listing all the classes contained in it. */ | |
170 | ||
171 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
172 | ||
173 | /* For each pair of reg classes, | |
174 | a largest reg class contained in their union. */ | |
175 | ||
176 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
177 | ||
178 | /* For each pair of reg classes, | |
179 | the smallest reg class containing their union. */ | |
180 | ||
181 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
182 | ||
fbd40359 ZW |
183 | /* Array containing all of the register names. Unless |
184 | DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ | |
d05c8ee7 | 185 | |
fbd40359 | 186 | #ifdef DEBUG_REGISTER_NAMES |
e087aeb2 | 187 | const char * reg_names[] = REGISTER_NAMES; |
fbd40359 | 188 | #endif |
d05c8ee7 | 189 | |
ca4aac00 DE |
190 | /* For each hard register, the widest mode object that it can contain. |
191 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
192 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
193 | register. */ | |
194 | ||
195 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
196 | ||
6df26b8f JH |
197 | /* 1 if class does contain register of given mode. */ |
198 | ||
199 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
200 | ||
e4600702 RK |
201 | /* Maximum cost of moving from a register in one class to a register in |
202 | another class. Based on REGISTER_MOVE_COST. */ | |
203 | ||
e56b4594 | 204 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
205 | |
206 | /* Similar, but here we don't have to move if the first index is a subset | |
207 | of the second so in that case the cost is zero. */ | |
208 | ||
e56b4594 | 209 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
210 | |
211 | /* Similar, but here we don't have to move if the first index is a superset | |
212 | of the second so in that case the cost is zero. */ | |
213 | ||
e56b4594 | 214 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 215 | |
533d0835 RK |
216 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
217 | ||
218 | /* These are the classes that regs which are auto-incremented or decremented | |
219 | cannot be put in. */ | |
220 | ||
221 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
222 | ||
223 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
224 | context. */ | |
225 | ||
226 | static char *in_inc_dec; | |
227 | ||
5fcb671c | 228 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 229 | |
02188693 | 230 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
231 | |
232 | /* These are the classes containing only registers that can be used in | |
02188693 RH |
233 | a SUBREG expression that changes the mode of the register in some |
234 | way that is illegal. */ | |
e79f71f7 | 235 | |
02188693 | 236 | static int class_can_change_mode[N_REG_CLASSES]; |
e79f71f7 | 237 | |
02188693 RH |
238 | /* Registers, including pseudos, which change modes in some way that |
239 | is illegal. */ | |
e79f71f7 | 240 | |
02188693 | 241 | static regset reg_changes_mode; |
e79f71f7 | 242 | |
02188693 | 243 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
e79f71f7 | 244 | |
473fe49b KR |
245 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
246 | ||
e2500fed | 247 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
473fe49b | 248 | |
6feacd09 MM |
249 | /* Linked list of reg_info structures allocated for reg_n_info array. |
250 | Grouping all of the allocated structures together in one lump | |
251 | means only one call to bzero to clear them, rather than n smaller | |
252 | calls. */ | |
253 | struct reg_info_data { | |
254 | struct reg_info_data *next; /* next set of reg_info structures */ | |
255 | size_t min_index; /* minimum index # */ | |
256 | size_t max_index; /* maximum index # */ | |
257 | char used_p; /* non-zero if this has been used previously */ | |
258 | reg_info data[1]; /* beginning of the reg_info data */ | |
259 | }; | |
260 | ||
261 | static struct reg_info_data *reg_info_head; | |
262 | ||
c07c7c9d | 263 | /* No more global register variables may be declared; true once |
dc297297 | 264 | regclass has been initialized. */ |
6c85df69 AH |
265 | |
266 | static int no_global_reg_vars = 0; | |
267 | ||
6feacd09 | 268 | |
54dac99e RK |
269 | /* Function called only once to initialize the above data on reg usage. |
270 | Once this is done, various switches may override. */ | |
271 | ||
272 | void | |
273 | init_reg_sets () | |
274 | { | |
b3694847 | 275 | int i, j; |
54dac99e | 276 | |
2e0e2b76 CH |
277 | /* First copy the register information from the initial int form into |
278 | the regsets. */ | |
279 | ||
280 | for (i = 0; i < N_REG_CLASSES; i++) | |
281 | { | |
282 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
283 | ||
b85946fc | 284 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
2e0e2b76 | 285 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
b85946fc RH |
286 | if (int_reg_class_contents[i][j / 32] |
287 | & ((unsigned) 1 << (j % 32))) | |
2e0e2b76 CH |
288 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
289 | } | |
290 | ||
4e135bdd KG |
291 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
292 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 293 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 294 | |
910bc42d R |
295 | /* Do any additional initialization regsets may need */ |
296 | INIT_ONCE_REG_SET (); | |
f5d8c9f4 BS |
297 | |
298 | #ifdef REG_ALLOC_ORDER | |
299 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
300 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
301 | #endif | |
910bc42d R |
302 | } |
303 | ||
304 | /* After switches have been processed, which perhaps alter | |
305 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
306 | ||
307 | static void | |
308 | init_reg_sets_1 () | |
309 | { | |
b3694847 SS |
310 | unsigned int i, j; |
311 | unsigned int /* enum machine_mode */ m; | |
6836e024 | 312 | char allocatable_regs_of_mode [MAX_MACHINE_MODE]; |
910bc42d R |
313 | |
314 | /* This macro allows the fixed or call-used registers | |
315 | and the register classes to depend on target flags. */ | |
316 | ||
317 | #ifdef CONDITIONAL_REGISTER_USAGE | |
318 | CONDITIONAL_REGISTER_USAGE; | |
319 | #endif | |
320 | ||
54dac99e RK |
321 | /* Compute number of hard regs in each class. */ |
322 | ||
961192e1 | 323 | memset ((char *) reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
324 | for (i = 0; i < N_REG_CLASSES; i++) |
325 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
326 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
327 | reg_class_size[i]++; | |
328 | ||
329 | /* Initialize the table of subunions. | |
330 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
331 | that is contained in the union of classes I and J. */ | |
332 | ||
333 | for (i = 0; i < N_REG_CLASSES; i++) | |
334 | { | |
335 | for (j = 0; j < N_REG_CLASSES; j++) | |
336 | { | |
337 | #ifdef HARD_REG_SET | |
338 | register /* Declare it register if it's a scalar. */ | |
339 | #endif | |
340 | HARD_REG_SET c; | |
b3694847 | 341 | int k; |
54dac99e RK |
342 | |
343 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
344 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
345 | for (k = 0; k < N_REG_CLASSES; k++) | |
346 | { | |
347 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
348 | subclass1); | |
349 | continue; | |
350 | ||
351 | subclass1: | |
352 | /* keep the largest subclass */ /* SPEE 900308 */ | |
353 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
354 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
355 | subclass2); | |
356 | reg_class_subunion[i][j] = (enum reg_class) k; | |
357 | subclass2: | |
358 | ; | |
359 | } | |
360 | } | |
361 | } | |
362 | ||
363 | /* Initialize the table of superunions. | |
364 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
365 | containing the union of classes I and J. */ | |
366 | ||
367 | for (i = 0; i < N_REG_CLASSES; i++) | |
368 | { | |
369 | for (j = 0; j < N_REG_CLASSES; j++) | |
370 | { | |
371 | #ifdef HARD_REG_SET | |
372 | register /* Declare it register if it's a scalar. */ | |
373 | #endif | |
374 | HARD_REG_SET c; | |
b3694847 | 375 | int k; |
54dac99e RK |
376 | |
377 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
378 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
379 | for (k = 0; k < N_REG_CLASSES; k++) | |
380 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
381 | ||
382 | superclass: | |
383 | reg_class_superunion[i][j] = (enum reg_class) k; | |
384 | } | |
385 | } | |
386 | ||
387 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
388 | First clear the whole table, then add the elements as they are found. */ | |
389 | ||
390 | for (i = 0; i < N_REG_CLASSES; i++) | |
391 | { | |
392 | for (j = 0; j < N_REG_CLASSES; j++) | |
393 | { | |
394 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
395 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
396 | } | |
397 | } | |
398 | ||
399 | for (i = 0; i < N_REG_CLASSES; i++) | |
400 | { | |
401 | if (i == (int) NO_REGS) | |
402 | continue; | |
403 | ||
404 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
405 | { | |
406 | enum reg_class *p; | |
407 | ||
408 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
409 | subclass); | |
410 | continue; | |
411 | subclass: | |
412 | /* Reg class I is a subclass of J. | |
413 | Add J to the table of superclasses of I. */ | |
414 | p = ®_class_superclasses[i][0]; | |
415 | while (*p != LIM_REG_CLASSES) p++; | |
416 | *p = (enum reg_class) j; | |
417 | /* Add I to the table of superclasses of J. */ | |
418 | p = ®_class_subclasses[j][0]; | |
419 | while (*p != LIM_REG_CLASSES) p++; | |
420 | *p = (enum reg_class) i; | |
421 | } | |
422 | } | |
e4600702 | 423 | |
54dac99e RK |
424 | /* Initialize "constant" tables. */ |
425 | ||
426 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
427 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
428 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
4e2db584 | 429 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
54dac99e | 430 | |
4e135bdd | 431 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e RK |
432 | |
433 | n_non_fixed_regs = 0; | |
434 | ||
435 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
436 | { | |
54dac99e RK |
437 | if (fixed_regs[i]) |
438 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
439 | else | |
440 | n_non_fixed_regs++; | |
441 | ||
442 | if (call_used_regs[i]) | |
443 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
444 | if (call_fixed_regs[i]) | |
445 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
446 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
447 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
4e2db584 RH |
448 | |
449 | /* There are a couple of fixed registers that we know are safe to | |
450 | exclude from being clobbered by calls: | |
451 | ||
452 | The frame pointer is always preserved across calls. The arg pointer | |
453 | is if it is fixed. The stack pointer usually is, unless | |
454 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
455 | If we are generating PIC code, the PIC offset table register is | |
456 | preserved across calls, though the target can override that. */ | |
a6a2274a | 457 | |
4e2db584 RH |
458 | if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) |
459 | ; | |
460 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
461 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
462 | ; | |
463 | #endif | |
464 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
465 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
466 | ; | |
467 | #endif | |
468 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
12beba6f | 469 | else if (i == PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
4e2db584 RH |
470 | ; |
471 | #endif | |
d3259baa | 472 | else if (0 |
6ca3c22f | 473 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa RH |
474 | || call_really_used_regs[i] |
475 | #else | |
476 | || call_used_regs[i] | |
477 | #endif | |
478 | || global_regs[i]) | |
4e2db584 | 479 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
54dac99e | 480 | } |
4e2db584 | 481 | |
6836e024 JH |
482 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
483 | memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); | |
dbbbbf3b | 484 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 | 485 | for (i = 0; i < N_REG_CLASSES; i++) |
6df26b8f JH |
486 | if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
487 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
488 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
489 | && HARD_REGNO_MODE_OK (j, m)) | |
490 | { | |
491 | contains_reg_of_mode [i][m] = 1; | |
492 | allocatable_regs_of_mode [m] = 1; | |
493 | break; | |
494 | } | |
acbce667 KR |
495 | |
496 | /* Initialize the move cost table. Find every subset of each class | |
497 | and take the maximum cost of moving any subset to any other. */ | |
498 | ||
dbbbbf3b | 499 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 JH |
500 | if (allocatable_regs_of_mode [m]) |
501 | { | |
502 | for (i = 0; i < N_REG_CLASSES; i++) | |
503 | if (contains_reg_of_mode [i][m]) | |
504 | for (j = 0; j < N_REG_CLASSES; j++) | |
505 | { | |
506 | int cost; | |
507 | enum reg_class *p1, *p2; | |
508 | ||
509 | if (!contains_reg_of_mode [j][m]) | |
510 | { | |
511 | move_cost[m][i][j] = 65536; | |
512 | may_move_in_cost[m][i][j] = 65536; | |
513 | may_move_out_cost[m][i][j] = 65536; | |
514 | } | |
515 | else | |
516 | { | |
26a952a8 | 517 | cost = REGISTER_MOVE_COST (m, i, j); |
6836e024 JH |
518 | |
519 | for (p2 = ®_class_subclasses[j][0]; | |
520 | *p2 != LIM_REG_CLASSES; | |
521 | p2++) | |
522 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
523 | cost = MAX (cost, move_cost [m][i][*p2]); | |
524 | ||
525 | for (p1 = ®_class_subclasses[i][0]; | |
526 | *p1 != LIM_REG_CLASSES; | |
527 | p1++) | |
528 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
529 | cost = MAX (cost, move_cost [m][*p1][j]); | |
530 | ||
531 | move_cost[m][i][j] = cost; | |
532 | ||
533 | if (reg_class_subset_p (i, j)) | |
534 | may_move_in_cost[m][i][j] = 0; | |
535 | else | |
536 | may_move_in_cost[m][i][j] = cost; | |
537 | ||
538 | if (reg_class_subset_p (j, i)) | |
539 | may_move_out_cost[m][i][j] = 0; | |
540 | else | |
541 | may_move_out_cost[m][i][j] = cost; | |
542 | } | |
543 | } | |
1464632b | 544 | else |
6836e024 JH |
545 | for (j = 0; j < N_REG_CLASSES; j++) |
546 | { | |
547 | move_cost[m][i][j] = 65536; | |
548 | may_move_in_cost[m][i][j] = 65536; | |
549 | may_move_out_cost[m][i][j] = 65536; | |
550 | } | |
551 | } | |
e79f71f7 | 552 | |
02188693 | 553 | #ifdef CLASS_CANNOT_CHANGE_MODE |
e79f71f7 GK |
554 | { |
555 | HARD_REG_SET c; | |
02188693 | 556 | COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]); |
a6a2274a | 557 | |
e79f71f7 GK |
558 | for (i = 0; i < N_REG_CLASSES; i++) |
559 | { | |
560 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class); | |
02188693 | 561 | class_can_change_mode [i] = 0; |
e79f71f7 GK |
562 | continue; |
563 | ok_class: | |
02188693 | 564 | class_can_change_mode [i] = 1; |
e79f71f7 GK |
565 | } |
566 | } | |
02188693 | 567 | #endif /* CLASS_CANNOT_CHANGE_MODE */ |
c27c5281 DE |
568 | } |
569 | ||
570 | /* Compute the table of register modes. | |
571 | These values are used to record death information for individual registers | |
572 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 573 | |
c27c5281 DE |
574 | static void |
575 | init_reg_modes () | |
576 | { | |
b3694847 | 577 | int i; |
ca4aac00 DE |
578 | |
579 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
580 | { |
581 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
582 | ||
066c2fea | 583 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
584 | ??? One situation in which we need to do this is on the mips where |
585 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
586 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 587 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 588 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 589 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 590 | } |
ca4aac00 DE |
591 | } |
592 | ||
c27c5281 DE |
593 | /* Finish initializing the register sets and |
594 | initialize the register modes. */ | |
595 | ||
596 | void | |
597 | init_regs () | |
598 | { | |
599 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
600 | until after register usage was specified. */ | |
b93a436e | 601 | init_reg_sets_1 (); |
c27c5281 DE |
602 | |
603 | init_reg_modes (); | |
6cde4876 JL |
604 | } |
605 | ||
606 | /* Initialize some fake stack-frame MEM references for use in | |
607 | memory_move_secondary_cost. */ | |
473fe49b | 608 | |
6cde4876 JL |
609 | void |
610 | init_fake_stack_mems () | |
611 | { | |
473fe49b KR |
612 | #ifdef HAVE_SECONDARY_RELOADS |
613 | { | |
473fe49b | 614 | int i; |
d067e2aa | 615 | |
473fe49b | 616 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 617 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
618 | } |
619 | #endif | |
c27c5281 DE |
620 | } |
621 | ||
cbd5b9a2 | 622 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 623 | |
cbd5b9a2 KR |
624 | /* Compute extra cost of moving registers to/from memory due to reloads. |
625 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 626 | |
cbd5b9a2 KR |
627 | int |
628 | memory_move_secondary_cost (mode, class, in) | |
629 | enum machine_mode mode; | |
630 | enum reg_class class; | |
631 | int in; | |
632 | { | |
633 | enum reg_class altclass; | |
634 | int partial_cost = 0; | |
cbd5b9a2 | 635 | /* We need a memory reference to feed to SECONDARY... macros. */ |
dc297297 | 636 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
272df862 KG |
637 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
638 | ||
cbd5b9a2 KR |
639 | |
640 | if (in) | |
473fe49b | 641 | { |
321c0828 | 642 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 643 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 644 | #else |
473fe49b | 645 | altclass = NO_REGS; |
321c0828 | 646 | #endif |
473fe49b | 647 | } |
cbd5b9a2 | 648 | else |
473fe49b | 649 | { |
321c0828 | 650 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 651 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 652 | #else |
473fe49b | 653 | altclass = NO_REGS; |
321c0828 | 654 | #endif |
473fe49b KR |
655 | } |
656 | ||
cbd5b9a2 KR |
657 | if (altclass == NO_REGS) |
658 | return 0; | |
659 | ||
660 | if (in) | |
e56b4594 | 661 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 662 | else |
e56b4594 | 663 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
664 | |
665 | if (class == altclass) | |
666 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
667 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
668 | here in that case. | |
669 | ||
670 | I'm tempted to put in an abort here, but returning this will | |
671 | probably only give poor estimates, which is what we would've | |
672 | had before this code anyways. */ | |
673 | return partial_cost; | |
674 | ||
675 | /* Check if the secondary reload register will also need a | |
676 | secondary reload. */ | |
677 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
678 | } | |
679 | #endif | |
680 | ||
ca4aac00 DE |
681 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
682 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
683 | ||
684 | enum machine_mode | |
685 | choose_hard_reg_mode (regno, nregs) | |
770ae6cc RK |
686 | unsigned int regno ATTRIBUTE_UNUSED; |
687 | unsigned int nregs; | |
ca4aac00 | 688 | { |
dbbbbf3b | 689 | unsigned int /* enum machine_mode */ m; |
ca4aac00 DE |
690 | enum machine_mode found_mode = VOIDmode, mode; |
691 | ||
692 | /* We first look for the largest integer mode that can be validly | |
693 | held in REGNO. If none, we look for the largest floating-point mode. | |
694 | If we still didn't find a valid mode, try CCmode. */ | |
695 | ||
696 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
697 | mode != VOIDmode; | |
698 | mode = GET_MODE_WIDER_MODE (mode)) | |
699 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
700 | && HARD_REGNO_MODE_OK (regno, mode)) | |
701 | found_mode = mode; | |
702 | ||
703 | if (found_mode != VOIDmode) | |
704 | return found_mode; | |
705 | ||
706 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
707 | mode != VOIDmode; | |
708 | mode = GET_MODE_WIDER_MODE (mode)) | |
709 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
710 | && HARD_REGNO_MODE_OK (regno, mode)) | |
711 | found_mode = mode; | |
712 | ||
713 | if (found_mode != VOIDmode) | |
714 | return found_mode; | |
715 | ||
78b583fe AH |
716 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
717 | mode != VOIDmode; | |
718 | mode = GET_MODE_WIDER_MODE (mode)) | |
719 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
720 | && HARD_REGNO_MODE_OK (regno, mode)) | |
721 | found_mode = mode; | |
722 | ||
723 | if (found_mode != VOIDmode) | |
724 | return found_mode; | |
725 | ||
726 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
727 | mode != VOIDmode; | |
728 | mode = GET_MODE_WIDER_MODE (mode)) | |
729 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
730 | && HARD_REGNO_MODE_OK (regno, mode)) | |
731 | found_mode = mode; | |
732 | ||
733 | if (found_mode != VOIDmode) | |
734 | return found_mode; | |
735 | ||
0548a9df | 736 | /* Iterate over all of the CCmodes. */ |
dbbbbf3b JDA |
737 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
738 | { | |
739 | mode = (enum machine_mode) m; | |
740 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
741 | && HARD_REGNO_MODE_OK (regno, mode)) | |
742 | return mode; | |
743 | } | |
ca4aac00 DE |
744 | |
745 | /* We can't find a mode valid for this register. */ | |
746 | return VOIDmode; | |
54dac99e RK |
747 | } |
748 | ||
749 | /* Specify the usage characteristics of the register named NAME. | |
750 | It should be a fixed register if FIXED and a | |
751 | call-used register if CALL_USED. */ | |
752 | ||
753 | void | |
754 | fix_register (name, fixed, call_used) | |
ec0ce6e2 | 755 | const char *name; |
54dac99e RK |
756 | int fixed, call_used; |
757 | { | |
758 | int i; | |
759 | ||
760 | /* Decode the name and update the primary form of | |
761 | the register info. */ | |
762 | ||
e5c90c23 TW |
763 | if ((i = decode_reg_name (name)) >= 0) |
764 | { | |
cb2fdc84 GRK |
765 | if ((i == STACK_POINTER_REGNUM |
766 | #ifdef HARD_FRAME_POINTER_REGNUM | |
767 | || i == HARD_FRAME_POINTER_REGNUM | |
768 | #else | |
769 | || i == FRAME_POINTER_REGNUM | |
770 | #endif | |
771 | ) | |
772 | && (fixed == 0 || call_used == 0)) | |
773 | { | |
6f7d635c | 774 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
775 | { "call-saved", "call-used" }, |
776 | { "no-such-option", "fixed" }}; | |
a6a2274a KH |
777 | |
778 | error ("can't use '%s' as a %s register", name, | |
cb2fdc84 GRK |
779 | what_option[fixed][call_used]); |
780 | } | |
781 | else | |
782 | { | |
783 | fixed_regs[i] = fixed; | |
784 | call_used_regs[i] = call_used; | |
ec523c2f | 785 | #ifdef CALL_REALLY_USED_REGISTERS |
fc1296b7 AM |
786 | if (fixed == 0) |
787 | call_really_used_regs[i] = call_used; | |
d3259baa | 788 | #endif |
cb2fdc84 | 789 | } |
e5c90c23 TW |
790 | } |
791 | else | |
54dac99e RK |
792 | { |
793 | warning ("unknown register name: %s", name); | |
54dac99e RK |
794 | } |
795 | } | |
614f68e2 RK |
796 | |
797 | /* Mark register number I as global. */ | |
798 | ||
799 | void | |
800 | globalize_reg (i) | |
801 | int i; | |
802 | { | |
c07c7c9d | 803 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
804 | error ("global register variable follows a function definition"); |
805 | ||
614f68e2 RK |
806 | if (global_regs[i]) |
807 | { | |
808 | warning ("register used for two global register variables"); | |
809 | return; | |
810 | } | |
811 | ||
812 | if (call_used_regs[i] && ! fixed_regs[i]) | |
813 | warning ("call-clobbered register used for global register variable"); | |
814 | ||
815 | global_regs[i] = 1; | |
816 | ||
817 | /* If already fixed, nothing else to do. */ | |
818 | if (fixed_regs[i]) | |
819 | return; | |
820 | ||
821 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
822 | n_non_fixed_regs--; | |
823 | ||
824 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
825 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
826 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
caecc099 | 827 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
614f68e2 | 828 | } |
54dac99e RK |
829 | \f |
830 | /* Now the data and code for the `regclass' pass, which happens | |
831 | just before local-alloc. */ | |
832 | ||
e4600702 RK |
833 | /* The `costs' struct records the cost of using a hard register of each class |
834 | and of using memory for each pseudo. We use this data to set up | |
835 | register class preferences. */ | |
54dac99e | 836 | |
e4600702 | 837 | struct costs |
54dac99e | 838 | { |
e4600702 RK |
839 | int cost[N_REG_CLASSES]; |
840 | int mem_cost; | |
54dac99e RK |
841 | }; |
842 | ||
9ffc5a70 JH |
843 | /* Structure used to record preferrences of given pseudo. */ |
844 | struct reg_pref | |
845 | { | |
846 | /* (enum reg_class) prefclass is the preferred class. */ | |
847 | char prefclass; | |
848 | ||
849 | /* altclass is a register class that we should use for allocating | |
850 | pseudo if no register in the preferred class is available. | |
851 | If no register in this class is available, memory is preferred. | |
852 | ||
853 | It might appear to be more general to have a bitmask of classes here, | |
854 | but since it is recommended that there be a class corresponding to the | |
855 | union of most major pair of classes, that generality is not required. */ | |
856 | char altclass; | |
857 | }; | |
858 | ||
e4600702 RK |
859 | /* Record the cost of each class for each pseudo. */ |
860 | ||
861 | static struct costs *costs; | |
862 | ||
61719ba7 BS |
863 | /* Initialized once, and used to initialize cost values for each insn. */ |
864 | ||
865 | static struct costs init_cost; | |
866 | ||
9ffc5a70 | 867 | /* Record preferrences of each pseudo. |
54dac99e RK |
868 | This is available after `regclass' is run. */ |
869 | ||
9ffc5a70 | 870 | static struct reg_pref *reg_pref; |
54d23420 | 871 | |
dc297297 | 872 | /* Allocated buffers for reg_pref. */ |
54dac99e | 873 | |
9ffc5a70 | 874 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 875 | |
9401afe3 | 876 | /* Frequency of executions of current insn. */ |
54d23420 | 877 | |
9401afe3 | 878 | static int frequency; |
54d23420 | 879 | |
13536812 KG |
880 | static rtx scan_one_insn PARAMS ((rtx, int)); |
881 | static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); | |
882 | static void dump_regclass PARAMS ((FILE *)); | |
883 | static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, | |
e79f71f7 | 884 | const char **, rtx, |
f741a71c | 885 | struct costs *, struct reg_pref *)); |
a6a2274a | 886 | static int copy_cost PARAMS ((rtx, enum machine_mode, |
08d95f91 | 887 | enum reg_class, int)); |
13536812 | 888 | static void record_address_regs PARAMS ((rtx, enum reg_class, int)); |
1d300e19 | 889 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
13536812 | 890 | static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); |
1d300e19 | 891 | #endif |
770ae6cc | 892 | static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); |
54dac99e RK |
893 | |
894 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
895 | This function is sometimes called before the info has been computed. | |
896 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
897 | ||
898 | enum reg_class | |
899 | reg_preferred_class (regno) | |
900 | int regno; | |
901 | { | |
9ffc5a70 | 902 | if (reg_pref == 0) |
54dac99e | 903 | return GENERAL_REGS; |
9ffc5a70 | 904 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
905 | } |
906 | ||
e4600702 RK |
907 | enum reg_class |
908 | reg_alternate_class (regno) | |
b729186a | 909 | int regno; |
54dac99e | 910 | { |
9ffc5a70 | 911 | if (reg_pref == 0) |
e4600702 RK |
912 | return ALL_REGS; |
913 | ||
9ffc5a70 | 914 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
915 | } |
916 | ||
61719ba7 | 917 | /* Initialize some global data for this pass. */ |
54dac99e RK |
918 | |
919 | void | |
920 | regclass_init () | |
921 | { | |
61719ba7 BS |
922 | int i; |
923 | ||
924 | init_cost.mem_cost = 10000; | |
925 | for (i = 0; i < N_REG_CLASSES; i++) | |
926 | init_cost.cost[i] = 10000; | |
927 | ||
928 | /* This prevents dump_flow_info from losing if called | |
929 | before regclass is run. */ | |
9ffc5a70 | 930 | reg_pref = NULL; |
6c85df69 | 931 | |
dc297297 | 932 | /* No more global register variables may be declared. */ |
6c85df69 | 933 | no_global_reg_vars = 1; |
54dac99e | 934 | } |
246fd41f JH |
935 | \f |
936 | /* Dump register costs. */ | |
915b80ed | 937 | static void |
246fd41f JH |
938 | dump_regclass (dump) |
939 | FILE *dump; | |
940 | { | |
941 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
942 | int i; | |
943 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
944 | { | |
dbbbbf3b | 945 | int /* enum reg_class */ class; |
246fd41f JH |
946 | if (REG_N_REFS (i)) |
947 | { | |
f741a71c | 948 | fprintf (dump, " Register %i costs:", i); |
dbbbbf3b JDA |
949 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
950 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
6df26b8f | 951 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
dbbbbf3b JDA |
952 | && (!in_inc_dec[i] |
953 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
6df26b8f JH |
954 | #endif |
955 | #ifdef CLASS_CANNOT_CHANGE_MODE | |
956 | && (!REGNO_REG_SET_P (reg_changes_mode, i) | |
dbbbbf3b | 957 | || class_can_change_mode [(enum reg_class) class]) |
6df26b8f JH |
958 | #endif |
959 | ) | |
dbbbbf3b JDA |
960 | fprintf (dump, " %s:%i", reg_class_names[class], |
961 | costs[i].cost[(enum reg_class) class]); | |
f741a71c | 962 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
963 | } |
964 | } | |
965 | } | |
f741a71c JH |
966 | \f |
967 | ||
968 | /* Calculate the costs of insn operands. */ | |
969 | ||
970 | static void | |
971 | record_operand_costs (insn, op_costs, reg_pref) | |
972 | rtx insn; | |
973 | struct costs *op_costs; | |
974 | struct reg_pref *reg_pref; | |
975 | { | |
976 | const char *constraints[MAX_RECOG_OPERANDS]; | |
977 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
978 | int i; |
979 | ||
980 | for (i = 0; i < recog_data.n_operands; i++) | |
981 | { | |
982 | constraints[i] = recog_data.constraints[i]; | |
983 | modes[i] = recog_data.operand_mode[i]; | |
984 | } | |
f741a71c JH |
985 | |
986 | /* If we get here, we are set up to record the costs of all the | |
987 | operands for this insn. Start by initializing the costs. | |
988 | Then handle any address registers. Finally record the desired | |
989 | classes for any pseudos, doing it twice if some pair of | |
990 | operands are commutative. */ | |
a6a2274a | 991 | |
f741a71c JH |
992 | for (i = 0; i < recog_data.n_operands; i++) |
993 | { | |
994 | op_costs[i] = init_cost; | |
995 | ||
996 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
997 | { | |
998 | rtx inner = SUBREG_REG (recog_data.operand[i]); | |
02188693 RH |
999 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1000 | if (GET_CODE (inner) == REG | |
1001 | && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner))) | |
1002 | SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner)); | |
9ef07cf1 | 1003 | #endif |
f741a71c JH |
1004 | recog_data.operand[i] = inner; |
1005 | } | |
1006 | ||
1007 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
1008 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
3dcc68a4 | 1009 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
f741a71c JH |
1010 | else if (constraints[i][0] == 'p') |
1011 | record_address_regs (recog_data.operand[i], | |
3dcc68a4 | 1012 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
f741a71c JH |
1013 | } |
1014 | ||
1015 | /* Check for commutative in a separate loop so everything will | |
1016 | have been initialized. We must do this even if one operand | |
1017 | is a constant--see addsi3 in m68k.md. */ | |
1018 | ||
1019 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
1020 | if (constraints[i][0] == '%') | |
1021 | { | |
1022 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1023 | int j; | |
246fd41f | 1024 | |
f741a71c JH |
1025 | /* Handle commutative operands by swapping the constraints. |
1026 | We assume the modes are the same. */ | |
1027 | ||
1028 | for (j = 0; j < recog_data.n_operands; j++) | |
1029 | xconstraints[j] = constraints[j]; | |
1030 | ||
1031 | xconstraints[i] = constraints[i+1]; | |
1032 | xconstraints[i+1] = constraints[i]; | |
1033 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1034 | recog_data.operand, modes, |
f741a71c JH |
1035 | xconstraints, insn, op_costs, reg_pref); |
1036 | } | |
1037 | ||
1038 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1039 | recog_data.operand, modes, |
f741a71c JH |
1040 | constraints, insn, op_costs, reg_pref); |
1041 | } | |
54dac99e | 1042 | \f |
61719ba7 BS |
1043 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1044 | time it would save code to put a certain register in a certain class. | |
1045 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1046 | once. | |
1047 | Return the last insn processed, so that the scan can be continued from | |
1048 | there. */ | |
1049 | ||
1050 | static rtx | |
1051 | scan_one_insn (insn, pass) | |
1052 | rtx insn; | |
1053 | int pass; | |
1054 | { | |
1055 | enum rtx_code code = GET_CODE (insn); | |
1056 | enum rtx_code pat_code; | |
0eadeb15 | 1057 | rtx set, note; |
61719ba7 | 1058 | int i, j; |
f741a71c | 1059 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 1060 | |
61719ba7 BS |
1061 | if (GET_RTX_CLASS (code) != 'i') |
1062 | return insn; | |
1063 | ||
1064 | pat_code = GET_CODE (PATTERN (insn)); | |
1065 | if (pat_code == USE | |
1066 | || pat_code == CLOBBER | |
1067 | || pat_code == ASM_INPUT | |
1068 | || pat_code == ADDR_VEC | |
1069 | || pat_code == ADDR_DIFF_VEC) | |
1070 | return insn; | |
1071 | ||
0eadeb15 BS |
1072 | set = single_set (insn); |
1073 | extract_insn (insn); | |
1074 | ||
0eadeb15 BS |
1075 | /* If this insn loads a parameter from its stack slot, then |
1076 | it represents a savings, rather than a cost, if the | |
1077 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 1078 | |
0eadeb15 BS |
1079 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
1080 | && GET_CODE (SET_SRC (set)) == MEM | |
1081 | && (note = find_reg_note (insn, REG_EQUIV, | |
1082 | NULL_RTX)) != 0 | |
1083 | && GET_CODE (XEXP (note, 0)) == MEM) | |
1084 | { | |
1085 | costs[REGNO (SET_DEST (set))].mem_cost | |
1086 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1087 | GENERAL_REGS, 1) | |
9401afe3 | 1088 | * frequency); |
0eadeb15 | 1089 | record_address_regs (XEXP (SET_SRC (set), 0), |
3dcc68a4 | 1090 | MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); |
0eadeb15 BS |
1091 | return insn; |
1092 | } | |
61719ba7 | 1093 | |
0eadeb15 BS |
1094 | /* Improve handling of two-address insns such as |
1095 | (set X (ashift CONST Y)) where CONST must be made to | |
1096 | match X. Change it into two insns: (set X CONST) | |
1097 | (set X (ashift X Y)). If we left this for reloading, it | |
1098 | would probably get three insns because X and Y might go | |
1099 | in the same place. This prevents X and Y from receiving | |
1100 | the same hard reg. | |
1101 | ||
1102 | We can only do this if the modes of operands 0 and 1 | |
1103 | (which might not be the same) are tieable and we only need | |
1104 | do this during our first pass. */ | |
1105 | ||
1106 | if (pass == 0 && optimize | |
1ccbefce RH |
1107 | && recog_data.n_operands >= 3 |
1108 | && recog_data.constraints[1][0] == '0' | |
1109 | && recog_data.constraints[1][1] == 0 | |
1110 | && CONSTANT_P (recog_data.operand[1]) | |
1111 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1112 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
1113 | && GET_CODE (recog_data.operand[0]) == REG | |
1114 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
1115 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
1116 | { |
1117 | rtx previnsn = prev_real_insn (insn); | |
1118 | rtx dest | |
1ccbefce RH |
1119 | = gen_lowpart (recog_data.operand_mode[1], |
1120 | recog_data.operand[0]); | |
0eadeb15 | 1121 | rtx newinsn |
1ccbefce | 1122 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 1123 | |
0eadeb15 BS |
1124 | /* If this insn was the start of a basic block, |
1125 | include the new insn in that block. | |
1126 | We need not check for code_label here; | |
1127 | while a basic block can start with a code_label, | |
1128 | INSN could not be at the beginning of that block. */ | |
1129 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 1130 | { |
e0082a72 ZD |
1131 | basic_block b; |
1132 | FOR_EACH_BB (b) | |
1133 | if (insn == b->head) | |
1134 | b->head = newinsn; | |
61719ba7 BS |
1135 | } |
1136 | ||
0eadeb15 | 1137 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1138 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d3c7d45e | 1139 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1140 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
61719ba7 | 1141 | |
1ccbefce | 1142 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d3c7d45e | 1143 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1144 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
1ccbefce RH |
1145 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1146 | if (recog_data.dup_num[i] == 1) | |
d3c7d45e AO |
1147 | { |
1148 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1149 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
9401afe3 | 1150 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d3c7d45e | 1151 | } |
61719ba7 | 1152 | |
0eadeb15 | 1153 | return PREV_INSN (newinsn); |
61719ba7 BS |
1154 | } |
1155 | ||
4963c995 | 1156 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1157 | |
1158 | /* Now add the cost for each operand to the total costs for | |
1159 | its register. */ | |
1160 | ||
1ccbefce RH |
1161 | for (i = 0; i < recog_data.n_operands; i++) |
1162 | if (GET_CODE (recog_data.operand[i]) == REG | |
1163 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 1164 | { |
1ccbefce | 1165 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1166 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1167 | ||
9401afe3 | 1168 | p->mem_cost += q->mem_cost * frequency; |
61719ba7 | 1169 | for (j = 0; j < N_REG_CLASSES; j++) |
9401afe3 | 1170 | p->cost[j] += q->cost[j] * frequency; |
61719ba7 BS |
1171 | } |
1172 | ||
1173 | return insn; | |
1174 | } | |
1175 | ||
54dac99e RK |
1176 | /* This is a pass of the compiler that scans all instructions |
1177 | and calculates the preferred class for each pseudo-register. | |
1178 | This information can be accessed later by calling `reg_preferred_class'. | |
1179 | This pass comes just before local register allocation. */ | |
1180 | ||
1181 | void | |
246fd41f | 1182 | regclass (f, nregs, dump) |
54dac99e RK |
1183 | rtx f; |
1184 | int nregs; | |
246fd41f | 1185 | FILE *dump; |
54dac99e | 1186 | { |
b3694847 SS |
1187 | rtx insn; |
1188 | int i; | |
e4600702 | 1189 | int pass; |
54dac99e RK |
1190 | |
1191 | init_recog (); | |
1192 | ||
56a65848 | 1193 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 | 1194 | |
02188693 | 1195 | #ifdef CLASS_CANNOT_CHANGE_MODE |
8e2e89f7 | 1196 | reg_changes_mode = BITMAP_XMALLOC (); |
a6a2274a | 1197 | #endif |
e79f71f7 | 1198 | |
533d0835 RK |
1199 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1200 | ||
4da896b2 | 1201 | in_inc_dec = (char *) xmalloc (nregs); |
533d0835 RK |
1202 | |
1203 | /* Initialize information about which register classes can be used for | |
1204 | pseudos that are auto-incremented or auto-decremented. It would | |
1205 | seem better to put this in init_reg_sets, but we need to be able | |
1206 | to allocate rtx, which we can't do that early. */ | |
1207 | ||
1208 | for (i = 0; i < N_REG_CLASSES; i++) | |
1209 | { | |
38a448ca | 1210 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 | 1211 | enum machine_mode m; |
b3694847 | 1212 | int j; |
533d0835 RK |
1213 | |
1214 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1215 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1216 | { | |
1217 | REGNO (r) = j; | |
1218 | ||
1219 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1220 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1221 | if (HARD_REGNO_MODE_OK (j, m)) |
1222 | { | |
1223 | PUT_MODE (r, m); | |
08d95f91 RK |
1224 | |
1225 | /* If a register is not directly suitable for an | |
1226 | auto-increment or decrement addressing mode and | |
1227 | requires secondary reloads, disallow its class from | |
1228 | being used in such addresses. */ | |
1229 | ||
1230 | if ((0 | |
041d7180 | 1231 | #ifdef SECONDARY_RELOAD_CLASS |
3dcc68a4 | 1232 | || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
041d7180 JL |
1233 | != NO_REGS) |
1234 | #else | |
533d0835 | 1235 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
3dcc68a4 | 1236 | || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1237 | != NO_REGS) |
533d0835 RK |
1238 | #endif |
1239 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
3dcc68a4 | 1240 | || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1241 | != NO_REGS) |
041d7180 | 1242 | #endif |
533d0835 | 1243 | #endif |
08d95f91 RK |
1244 | ) |
1245 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1246 | forbidden_inc_dec_class[i] = 1; |
1247 | } | |
1248 | } | |
1249 | } | |
1250 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1251 | ||
e4600702 RK |
1252 | /* Normally we scan the insns once and determine the best class to use for |
1253 | each register. However, if -fexpensive_optimizations are on, we do so | |
1254 | twice, the second time using the tentative best classes to guide the | |
1255 | selection. */ | |
54dac99e | 1256 | |
e4600702 RK |
1257 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1258 | { | |
e0082a72 | 1259 | basic_block bb; |
f741a71c JH |
1260 | |
1261 | if (dump) | |
a6a2274a | 1262 | fprintf (dump, "\n\nPass %i\n\n",pass); |
e4600702 | 1263 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1264 | |
961192e1 | 1265 | memset ((char *) costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1266 | |
533d0835 | 1267 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1268 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1269 | #endif |
1270 | ||
e4600702 RK |
1271 | /* Scan the instructions and record each time it would |
1272 | save code to put a certain register in a certain class. */ | |
1273 | ||
1f01879e | 1274 | if (!optimize) |
54dac99e | 1275 | { |
a08b2604 | 1276 | frequency = REG_FREQ_MAX; |
1f01879e JH |
1277 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1278 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1279 | } |
1f01879e | 1280 | else |
e0082a72 | 1281 | FOR_EACH_BB (bb) |
1f01879e | 1282 | { |
1f01879e | 1283 | /* Show that an insn inside a loop is likely to be executed three |
9b15c17f RH |
1284 | times more than insns outside a loop. This is much more |
1285 | aggressive than the assumptions made elsewhere and is being | |
1286 | tried as an experiment. */ | |
a08b2604 | 1287 | frequency = REG_FREQ_FROM_BB (bb); |
1f01879e JH |
1288 | for (insn = bb->head; ; insn = NEXT_INSN (insn)) |
1289 | { | |
1290 | insn = scan_one_insn (insn, pass); | |
1291 | if (insn == bb->end) | |
1292 | break; | |
1293 | } | |
1294 | } | |
a6a2274a | 1295 | |
e4600702 RK |
1296 | /* Now for each register look at how desirable each class is |
1297 | and find which class is preferred. Store that in | |
9ffc5a70 | 1298 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1299 | class any of whose registers is better than memory. */ |
a6a2274a | 1300 | |
e4600702 | 1301 | if (pass == 0) |
9ffc5a70 | 1302 | reg_pref = reg_pref_buffer; |
54dac99e | 1303 | |
f741a71c | 1304 | if (dump) |
a6a2274a | 1305 | { |
f741a71c | 1306 | dump_regclass (dump); |
4963c995 | 1307 | fprintf (dump,"\n"); |
f741a71c | 1308 | } |
e4600702 | 1309 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1310 | { |
b3694847 | 1311 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1312 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1313 | /* This is an enum reg_class, but we call it an int | |
1314 | to save lots of casts. */ | |
b3694847 SS |
1315 | int class; |
1316 | struct costs *p = &costs[i]; | |
e4600702 | 1317 | |
64615302 JH |
1318 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1319 | yet. */ | |
1320 | if (optimize && !REG_N_REFS (i)) | |
f741a71c JH |
1321 | continue; |
1322 | ||
e4600702 | 1323 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1324 | { |
533d0835 | 1325 | /* Ignore classes that are too small for this operand or |
4fe9b91c | 1326 | invalid for an operand that was auto-incremented. */ |
6df26b8f | 1327 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
533d0835 RK |
1328 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1329 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1330 | #endif |
02188693 RH |
1331 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1332 | || (REGNO_REG_SET_P (reg_changes_mode, i) | |
1333 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1334 | #endif |
1335 | ) | |
e4600702 RK |
1336 | ; |
1337 | else if (p->cost[class] < best_cost) | |
1338 | { | |
1339 | best_cost = p->cost[class]; | |
1340 | best = (enum reg_class) class; | |
1341 | } | |
1342 | else if (p->cost[class] == best_cost) | |
8e2e89f7 | 1343 | best = reg_class_subunion[(int) best][class]; |
54dac99e | 1344 | } |
54dac99e | 1345 | |
e4600702 RK |
1346 | /* Record the alternate register class; i.e., a class for which |
1347 | every register in it is better than using memory. If adding a | |
1348 | class would make a smaller class (i.e., no union of just those | |
1349 | classes exists), skip that class. The major unions of classes | |
1350 | should be provided as a register class. Don't do this if we | |
1351 | will be doing it again later. */ | |
1352 | ||
f741a71c | 1353 | if ((pass == 1 || dump) || ! flag_expensive_optimizations) |
e4600702 RK |
1354 | for (class = 0; class < N_REG_CLASSES; class++) |
1355 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1356 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1357 | > reg_class_size[(int) alt]) |
1358 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1359 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1360 | #endif |
02188693 RH |
1361 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1362 | && ! (REGNO_REG_SET_P (reg_changes_mode, i) | |
1363 | && ! class_can_change_mode [class]) | |
533d0835 RK |
1364 | #endif |
1365 | ) | |
e4600702 | 1366 | alt = reg_class_subunion[(int) alt][class]; |
a6a2274a | 1367 | |
e4600702 RK |
1368 | /* If we don't add any classes, nothing to try. */ |
1369 | if (alt == best) | |
995d54dd | 1370 | alt = NO_REGS; |
e4600702 | 1371 | |
a6a2274a | 1372 | if (dump |
f741a71c JH |
1373 | && (reg_pref[i].prefclass != (int) best |
1374 | || reg_pref[i].altclass != (int) alt)) | |
1375 | { | |
1376 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
4963c995 | 1377 | fprintf (dump, " Register %i", i); |
f741a71c JH |
1378 | if (alt == ALL_REGS || best == ALL_REGS) |
1379 | fprintf (dump, " pref %s\n", reg_class_names[(int) best]); | |
1380 | else if (alt == NO_REGS) | |
1381 | fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); | |
1382 | else | |
1383 | fprintf (dump, " pref %s, else %s\n", | |
1384 | reg_class_names[(int) best], | |
1385 | reg_class_names[(int) alt]); | |
1386 | } | |
1387 | ||
e4600702 | 1388 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1389 | reg_pref[i].prefclass = (int) best; |
1390 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1391 | } |
54dac99e | 1392 | } |
56a65848 | 1393 | |
4da896b2 MM |
1394 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1395 | free (in_inc_dec); | |
e79f71f7 | 1396 | #endif |
02188693 RH |
1397 | #ifdef CLASS_CANNOT_CHANGE_MODE |
1398 | BITMAP_XFREE (reg_changes_mode); | |
4da896b2 | 1399 | #endif |
56a65848 | 1400 | free (costs); |
54dac99e RK |
1401 | } |
1402 | \f | |
e4600702 RK |
1403 | /* Record the cost of using memory or registers of various classes for |
1404 | the operands in INSN. | |
54dac99e | 1405 | |
e4600702 | 1406 | N_ALTS is the number of alternatives. |
54dac99e | 1407 | |
e4600702 RK |
1408 | N_OPS is the number of operands. |
1409 | ||
1410 | OPS is an array of the operands. | |
1411 | ||
1412 | MODES are the modes of the operands, in case any are VOIDmode. | |
1413 | ||
1414 | CONSTRAINTS are the constraints to use for the operands. This array | |
1415 | is modified by this procedure. | |
1416 | ||
1417 | This procedure works alternative by alternative. For each alternative | |
1418 | we assume that we will be able to allocate all pseudos to their ideal | |
1419 | register class and calculate the cost of using that alternative. Then | |
a6a2274a | 1420 | we compute for each operand that is a pseudo-register, the cost of |
e4600702 RK |
1421 | having the pseudo allocated to each register class and using it in that |
1422 | alternative. To this cost is added the cost of the alternative. | |
1423 | ||
1424 | The cost of each class for this insn is its lowest cost among all the | |
1425 | alternatives. */ | |
1426 | ||
1427 | static void | |
e79f71f7 | 1428 | record_reg_classes (n_alts, n_ops, ops, modes, |
f741a71c | 1429 | constraints, insn, op_costs, reg_pref) |
e4600702 RK |
1430 | int n_alts; |
1431 | int n_ops; | |
1432 | rtx *ops; | |
1433 | enum machine_mode *modes; | |
9b3142b3 | 1434 | const char **constraints; |
e4600702 | 1435 | rtx insn; |
f741a71c JH |
1436 | struct costs *op_costs; |
1437 | struct reg_pref *reg_pref; | |
54dac99e | 1438 | { |
e4600702 | 1439 | int alt; |
e4600702 | 1440 | int i, j; |
ec2d92af | 1441 | rtx set; |
e4600702 | 1442 | |
e4600702 RK |
1443 | /* Process each alternative, each time minimizing an operand's cost with |
1444 | the cost for each operand in that alternative. */ | |
54dac99e | 1445 | |
e4600702 | 1446 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1447 | { |
e4600702 RK |
1448 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1449 | int alt_fail = 0; | |
1450 | int alt_cost = 0; | |
1451 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1452 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1453 | int class; |
54dac99e | 1454 | |
e4600702 RK |
1455 | for (i = 0; i < n_ops; i++) |
1456 | { | |
9b3142b3 | 1457 | const char *p = constraints[i]; |
e4600702 RK |
1458 | rtx op = ops[i]; |
1459 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1460 | int allows_addr = 0; |
e4600702 | 1461 | int win = 0; |
e51712db | 1462 | unsigned char c; |
54dac99e | 1463 | |
7405d9a1 DE |
1464 | /* Initially show we know nothing about the register class. */ |
1465 | classes[i] = NO_REGS; | |
da2c0219 | 1466 | allows_mem[i] = 0; |
7405d9a1 | 1467 | |
a6a2274a | 1468 | /* If this operand has no constraints at all, we can conclude |
e4600702 | 1469 | nothing about it since anything is valid. */ |
54dac99e | 1470 | |
e4600702 RK |
1471 | if (*p == 0) |
1472 | { | |
1473 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
961192e1 | 1474 | memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1475 | |
e4600702 RK |
1476 | continue; |
1477 | } | |
54dac99e | 1478 | |
7405d9a1 DE |
1479 | /* If this alternative is only relevant when this operand |
1480 | matches a previous operand, we do different things depending | |
1481 | on whether this operand is a pseudo-reg or not. We must process | |
1482 | any modifiers for the operand before we can make this test. */ | |
1483 | ||
8c368ee2 | 1484 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1485 | p++; |
8c368ee2 | 1486 | |
e4600702 RK |
1487 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1488 | { | |
da2c0219 RK |
1489 | /* Copy class and whether memory is allowed from the matching |
1490 | alternative. Then perform any needed cost computations | |
1491 | and/or adjustments. */ | |
e4600702 RK |
1492 | j = p[0] - '0'; |
1493 | classes[i] = classes[j]; | |
da2c0219 | 1494 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1495 | |
1496 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1497 | { | |
1498 | /* If this matches the other operand, we have no added | |
dc903608 | 1499 | cost and we win. */ |
e4600702 | 1500 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1501 | win = 1; |
e4600702 | 1502 | |
77e67eac RK |
1503 | /* If we can put the other operand into a register, add to |
1504 | the cost of this alternative the cost to copy this | |
1505 | operand to the register used for the other operand. */ | |
e4600702 | 1506 | |
dc903608 | 1507 | else if (classes[j] != NO_REGS) |
77e67eac | 1508 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1509 | } |
07d8ca2d RS |
1510 | else if (GET_CODE (ops[j]) != REG |
1511 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1512 | { | |
1513 | /* This op is a pseudo but the one it matches is not. */ | |
a6a2274a | 1514 | |
07d8ca2d RS |
1515 | /* If we can't put the other operand into a register, this |
1516 | alternative can't be used. */ | |
1517 | ||
1518 | if (classes[j] == NO_REGS) | |
1519 | alt_fail = 1; | |
e4600702 | 1520 | |
07d8ca2d RS |
1521 | /* Otherwise, add to the cost of this alternative the cost |
1522 | to copy the other operand to the register used for this | |
1523 | operand. */ | |
1524 | ||
1525 | else | |
1526 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1527 | } | |
e4600702 RK |
1528 | else |
1529 | { | |
da2c0219 RK |
1530 | /* The costs of this operand are not the same as the other |
1531 | operand since move costs are not symmetric. Moreover, | |
1532 | if we cannot tie them, this alternative needs to do a | |
1533 | copy, which is one instruction. */ | |
1534 | ||
1535 | struct costs *pp = &this_op_costs[i]; | |
1536 | ||
1537 | for (class = 0; class < N_REG_CLASSES; class++) | |
1538 | pp->cost[class] | |
d5e2075d | 1539 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1540 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1541 | : 0) |
1542 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1543 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1544 | : 0)); |
a6a2274a | 1545 | |
da2c0219 RK |
1546 | /* If the alternative actually allows memory, make things |
1547 | a bit cheaper since we won't need an extra insn to | |
1548 | load it. */ | |
1549 | ||
1550 | pp->mem_cost | |
d5e2075d JH |
1551 | = ((recog_data.operand_type[i] != OP_IN |
1552 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1553 | : 0) | |
1554 | + (recog_data.operand_type[i] != OP_OUT | |
1555 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1556 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1557 | |
1558 | /* If we have assigned a class to this register in our | |
1559 | first pass, add a cost to this alternative corresponding | |
1560 | to what we would add if this register were not in the | |
1561 | appropriate class. */ | |
1562 | ||
9ffc5a70 | 1563 | if (reg_pref) |
da2c0219 | 1564 | alt_cost |
e56b4594 AO |
1565 | += (may_move_in_cost[mode] |
1566 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1567 | [(int) classes[i]]); |
e4600702 | 1568 | |
37747c82 RK |
1569 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1570 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1571 | alt_cost += 2; | |
e4600702 | 1572 | |
347099d6 | 1573 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1574 | for this operand, so skip to the end of the |
1575 | alternative (should be just one character). */ | |
1576 | while (*p && *p++ != ',') | |
1577 | ; | |
1578 | ||
1579 | constraints[i] = p; | |
347099d6 RS |
1580 | continue; |
1581 | } | |
e4600702 RK |
1582 | } |
1583 | ||
1584 | /* Scan all the constraint letters. See if the operand matches | |
1585 | any of the constraints. Collect the valid register classes | |
1586 | and see if this operand accepts memory. */ | |
1587 | ||
e4600702 RK |
1588 | while (*p && (c = *p++) != ',') |
1589 | switch (c) | |
1590 | { | |
e4600702 RK |
1591 | case '*': |
1592 | /* Ignore the next letter for this pass. */ | |
1593 | p++; | |
1594 | break; | |
1595 | ||
812f2051 R |
1596 | case '?': |
1597 | alt_cost += 2; | |
8c368ee2 | 1598 | case '!': case '#': case '&': |
e4600702 | 1599 | case '0': case '1': case '2': case '3': case '4': |
8c368ee2 | 1600 | case '5': case '6': case '7': case '8': case '9': |
94e6f783 DE |
1601 | break; |
1602 | ||
e4600702 | 1603 | case 'p': |
94e6f783 DE |
1604 | allows_addr = 1; |
1605 | win = address_operand (op, GET_MODE (op)); | |
46f40127 JL |
1606 | /* We know this operand is an address, so we want it to be |
1607 | allocated to a register that can be the base of an | |
1608 | address, ie BASE_REG_CLASS. */ | |
1609 | classes[i] | |
1610 | = reg_class_subunion[(int) classes[i]] | |
3dcc68a4 | 1611 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; |
e4600702 RK |
1612 | break; |
1613 | ||
1614 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1615 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 | 1616 | and non-offsettable addresses here. */ |
da2c0219 | 1617 | allows_mem[i] = 1; |
e4600702 RK |
1618 | if (GET_CODE (op) == MEM) |
1619 | win = 1; | |
1620 | break; | |
1621 | ||
1622 | case '<': | |
1623 | if (GET_CODE (op) == MEM | |
1624 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1625 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1626 | win = 1; | |
1627 | break; | |
1628 | ||
1629 | case '>': | |
1630 | if (GET_CODE (op) == MEM | |
1631 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1632 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1633 | win = 1; | |
1634 | break; | |
1635 | ||
1636 | case 'E': | |
e4600702 RK |
1637 | case 'F': |
1638 | if (GET_CODE (op) == CONST_DOUBLE) | |
1639 | win = 1; | |
1640 | break; | |
1641 | ||
1642 | case 'G': | |
1643 | case 'H': | |
1644 | if (GET_CODE (op) == CONST_DOUBLE | |
1645 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1646 | win = 1; | |
1647 | break; | |
1648 | ||
1649 | case 's': | |
1650 | if (GET_CODE (op) == CONST_INT | |
1651 | || (GET_CODE (op) == CONST_DOUBLE | |
1652 | && GET_MODE (op) == VOIDmode)) | |
1653 | break; | |
1654 | case 'i': | |
1655 | if (CONSTANT_P (op) | |
1656 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1657 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1658 | #endif | |
1659 | ) | |
1660 | win = 1; | |
1661 | break; | |
1662 | ||
1663 | case 'n': | |
1664 | if (GET_CODE (op) == CONST_INT | |
1665 | || (GET_CODE (op) == CONST_DOUBLE | |
1666 | && GET_MODE (op) == VOIDmode)) | |
1667 | win = 1; | |
1668 | break; | |
1669 | ||
1670 | case 'I': | |
1671 | case 'J': | |
1672 | case 'K': | |
1673 | case 'L': | |
1674 | case 'M': | |
1675 | case 'N': | |
1676 | case 'O': | |
1677 | case 'P': | |
1678 | if (GET_CODE (op) == CONST_INT | |
1679 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1680 | win = 1; | |
1681 | break; | |
1682 | ||
1683 | case 'X': | |
1684 | win = 1; | |
1685 | break; | |
54dac99e | 1686 | |
e4600702 RK |
1687 | case 'g': |
1688 | if (GET_CODE (op) == MEM | |
1689 | || (CONSTANT_P (op) | |
1690 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1691 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1692 | #endif |
e4600702 RK |
1693 | )) |
1694 | win = 1; | |
da2c0219 | 1695 | allows_mem[i] = 1; |
e4600702 RK |
1696 | case 'r': |
1697 | classes[i] | |
1698 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1699 | break; | |
1700 | ||
1701 | default: | |
c2cba7a9 RH |
1702 | if (REG_CLASS_FROM_LETTER (c) != NO_REGS) |
1703 | classes[i] | |
1704 | = reg_class_subunion[(int) classes[i]] | |
1705 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1706 | #ifdef EXTRA_CONSTRAINT | |
1707 | else if (EXTRA_CONSTRAINT (op, c)) | |
1708 | win = 1; | |
1709 | #endif | |
1710 | break; | |
e4600702 RK |
1711 | } |
1712 | ||
1713 | constraints[i] = p; | |
1714 | ||
1715 | /* How we account for this operand now depends on whether it is a | |
1716 | pseudo register or not. If it is, we first check if any | |
1717 | register classes are valid. If not, we ignore this alternative, | |
1718 | since we want to assume that all pseudos get allocated for | |
1719 | register preferencing. If some register class is valid, compute | |
1720 | the costs of moving the pseudo into that class. */ | |
1721 | ||
1722 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1723 | { |
e4600702 | 1724 | if (classes[i] == NO_REGS) |
94e6f783 | 1725 | { |
e79f71f7 GK |
1726 | /* We must always fail if the operand is a REG, but |
1727 | we did not find a suitable class. | |
a6a2274a | 1728 | |
e79f71f7 GK |
1729 | Otherwise we may perform an uninitialized read |
1730 | from this_op_costs after the `continue' statement | |
1731 | below. */ | |
1732 | alt_fail = 1; | |
94e6f783 | 1733 | } |
e4600702 RK |
1734 | else |
1735 | { | |
1736 | struct costs *pp = &this_op_costs[i]; | |
1737 | ||
1738 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1739 | pp->cost[class] |
d5e2075d | 1740 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1741 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1742 | : 0) |
1743 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1744 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1745 | : 0)); |
e4600702 RK |
1746 | |
1747 | /* If the alternative actually allows memory, make things | |
1748 | a bit cheaper since we won't need an extra insn to | |
1749 | load it. */ | |
1750 | ||
14a774a9 | 1751 | pp->mem_cost |
d5e2075d JH |
1752 | = ((recog_data.operand_type[i] != OP_IN |
1753 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1754 | : 0) | |
1755 | + (recog_data.operand_type[i] != OP_OUT | |
1756 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1757 | : 0) - allows_mem[i]); | |
e4600702 RK |
1758 | |
1759 | /* If we have assigned a class to this register in our | |
1760 | first pass, add a cost to this alternative corresponding | |
1761 | to what we would add if this register were not in the | |
1762 | appropriate class. */ | |
1763 | ||
9ffc5a70 | 1764 | if (reg_pref) |
e4600702 | 1765 | alt_cost |
e56b4594 AO |
1766 | += (may_move_in_cost[mode] |
1767 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1768 | [(int) classes[i]]); |
e4600702 | 1769 | } |
4db18574 | 1770 | } |
54dac99e | 1771 | |
e4600702 RK |
1772 | /* Otherwise, if this alternative wins, either because we |
1773 | have already determined that or if we have a hard register of | |
1774 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1775 | |
e4600702 RK |
1776 | else if (win |
1777 | || (GET_CODE (op) == REG | |
6f654776 | 1778 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1779 | ; |
54dac99e | 1780 | |
e4600702 RK |
1781 | /* If registers are valid, the cost of this alternative includes |
1782 | copying the object to and/or from a register. */ | |
54dac99e | 1783 | |
e4600702 RK |
1784 | else if (classes[i] != NO_REGS) |
1785 | { | |
1ccbefce | 1786 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1787 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1788 | |
1ccbefce | 1789 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1790 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1791 | } | |
54dac99e | 1792 | |
e4600702 RK |
1793 | /* The only other way this alternative can be used is if this is a |
1794 | constant that could be placed into memory. */ | |
1795 | ||
da2c0219 | 1796 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1797 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1798 | else |
1799 | alt_fail = 1; | |
1800 | } | |
1801 | ||
1802 | if (alt_fail) | |
1803 | continue; | |
1804 | ||
1805 | /* Finally, update the costs with the information we've calculated | |
1806 | about this alternative. */ | |
1807 | ||
1808 | for (i = 0; i < n_ops; i++) | |
1809 | if (GET_CODE (ops[i]) == REG | |
1810 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1811 | { |
e4600702 | 1812 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1813 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1814 | |
e4600702 RK |
1815 | pp->mem_cost = MIN (pp->mem_cost, |
1816 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1817 | |
e4600702 RK |
1818 | for (class = 0; class < N_REG_CLASSES; class++) |
1819 | pp->cost[class] = MIN (pp->cost[class], | |
1820 | (qq->cost[class] + alt_cost) * scale); | |
1821 | } | |
1822 | } | |
ec2d92af RK |
1823 | |
1824 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1825 | and one operand is a pseudo with the other a hard reg or a pseudo |
1826 | that prefers a register that is in its own register class then | |
1827 | we may want to adjust the cost of that register class to -1. | |
a6a2274a | 1828 | |
accef103 JL |
1829 | Avoid the adjustment if the source does not die to avoid stressing of |
1830 | register allocator by preferrencing two coliding registers into single | |
1831 | class. | |
1832 | ||
1833 | Also avoid the adjustment if a copy between registers of the class | |
1834 | is expensive (ten times the cost of a default copy is considered | |
1835 | arbitrarily expensive). This avoids losing when the preferred class | |
1836 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1837 | |
1838 | if ((set = single_set (insn)) != 0 | |
1839 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
0dc0641b JH |
1840 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG |
1841 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
ec2d92af RK |
1842 | for (i = 0; i <= 1; i++) |
1843 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1844 | { | |
770ae6cc | 1845 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1846 | enum machine_mode mode = GET_MODE (ops[!i]); |
1847 | int class; | |
770ae6cc | 1848 | unsigned int nr; |
ec2d92af | 1849 | |
accef103 JL |
1850 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1851 | { | |
1852 | enum reg_class pref = reg_pref[regno].prefclass; | |
1853 | ||
1854 | if ((reg_class_size[(unsigned char) pref] | |
1855 | == CLASS_MAX_NREGS (pref, mode)) | |
e56b4594 | 1856 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1857 | op_costs[i].cost[(unsigned char) pref] = -1; |
1858 | } | |
ec2d92af RK |
1859 | else if (regno < FIRST_PSEUDO_REGISTER) |
1860 | for (class = 0; class < N_REG_CLASSES; class++) | |
1861 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1862 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1863 | { |
1864 | if (reg_class_size[class] == 1) | |
1865 | op_costs[i].cost[class] = -1; | |
1866 | else | |
1867 | { | |
770ae6cc | 1868 | for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++) |
4841ba4b | 1869 | { |
770ae6cc RK |
1870 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1871 | regno + nr)) | |
4841ba4b RK |
1872 | break; |
1873 | } | |
1874 | ||
770ae6cc | 1875 | if (nr == HARD_REGNO_NREGS (regno,mode)) |
4841ba4b RK |
1876 | op_costs[i].cost[class] = -1; |
1877 | } | |
1878 | } | |
ec2d92af | 1879 | } |
54dac99e | 1880 | } |
e4600702 RK |
1881 | \f |
1882 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1883 | TO_P is zero) a register of class CLASS in mode MODE. | |
1884 | ||
1885 | X must not be a pseudo. */ | |
1886 | ||
1887 | static int | |
1888 | copy_cost (x, mode, class, to_p) | |
1889 | rtx x; | |
d0af450d | 1890 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e4600702 | 1891 | enum reg_class class; |
d0af450d | 1892 | int to_p ATTRIBUTE_UNUSED; |
e4600702 | 1893 | { |
29a82058 | 1894 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1895 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1896 | #endif |
e4600702 RK |
1897 | |
1898 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1899 | assuming optimal allocation. */ | |
1900 | ||
1901 | if (GET_CODE (x) == SCRATCH) | |
1902 | return 0; | |
1903 | ||
1904 | /* Get the class we will actually use for a reload. */ | |
1905 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1906 | ||
1907 | #ifdef HAVE_SECONDARY_RELOADS | |
a6a2274a | 1908 | /* If we need a secondary reload (we assume here that we are using |
e4600702 RK |
1909 | the secondary reload as an intermediate, not a scratch register), the |
1910 | cost is that to load the input into the intermediate register, then | |
1911 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1912 | ||
1913 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1914 | if (to_p == 1) | |
1915 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1916 | #endif | |
1917 | ||
dd9f0e8f | 1918 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1919 | if (! to_p) |
1920 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1921 | #endif | |
1922 | ||
1923 | if (secondary_class != NO_REGS) | |
e56b4594 | 1924 | return (move_cost[mode][(int) secondary_class][(int) class] |
e4600702 | 1925 | + copy_cost (x, mode, secondary_class, 2)); |
dd9f0e8f | 1926 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1927 | |
1928 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1929 | cost to move between the register classes, and use 2 for everything | |
1930 | else (constants). */ | |
1931 | ||
1932 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1933 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1934 | |
e4600702 | 1935 | else if (GET_CODE (x) == REG) |
e56b4594 | 1936 | return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
e4600702 RK |
1937 | |
1938 | else | |
1939 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
b437f1a7 | 1940 | return COSTS_N_INSNS (1); |
e4600702 RK |
1941 | } |
1942 | \f | |
54dac99e RK |
1943 | /* Record the pseudo registers we must reload into hard registers |
1944 | in a subexpression of a memory address, X. | |
e4600702 RK |
1945 | |
1946 | CLASS is the class that the register needs to be in and is either | |
1947 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1948 | ||
1949 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1950 | can represent half-cost adjustments). */ | |
54dac99e | 1951 | |
197d6480 | 1952 | static void |
e4600702 | 1953 | record_address_regs (x, class, scale) |
54dac99e | 1954 | rtx x; |
e4600702 RK |
1955 | enum reg_class class; |
1956 | int scale; | |
54dac99e | 1957 | { |
b3694847 | 1958 | enum rtx_code code = GET_CODE (x); |
54dac99e RK |
1959 | |
1960 | switch (code) | |
1961 | { | |
1962 | case CONST_INT: | |
1963 | case CONST: | |
1964 | case CC0: | |
1965 | case PC: | |
1966 | case SYMBOL_REF: | |
1967 | case LABEL_REF: | |
1968 | return; | |
1969 | ||
1970 | case PLUS: | |
1971 | /* When we have an address that is a sum, | |
1972 | we must determine whether registers are "base" or "index" regs. | |
1973 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1974 | the "base". Luckily, we can use the REG_POINTER to make a good |
1975 | choice most of the time. We only need to do this on machines | |
1976 | that can have two registers in an address and where the base | |
1977 | and index register classes are different. | |
e4600702 RK |
1978 | |
1979 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1980 | that seems bogus since it should only be set when we are sure | |
1981 | the register is being used as a pointer. */ | |
1982 | ||
54dac99e RK |
1983 | { |
1984 | rtx arg0 = XEXP (x, 0); | |
1985 | rtx arg1 = XEXP (x, 1); | |
b3694847 SS |
1986 | enum rtx_code code0 = GET_CODE (arg0); |
1987 | enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1988 | |
1989 | /* Look inside subregs. */ | |
e4600702 | 1990 | if (code0 == SUBREG) |
54dac99e | 1991 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1992 | if (code1 == SUBREG) |
54dac99e RK |
1993 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1994 | ||
e4600702 RK |
1995 | /* If this machine only allows one register per address, it must |
1996 | be in the first operand. */ | |
1997 | ||
1998 | if (MAX_REGS_PER_ADDRESS == 1) | |
1999 | record_address_regs (arg0, class, scale); | |
2000 | ||
2001 | /* If index and base registers are the same on this machine, just | |
2002 | record registers in any non-constant operands. We assume here, | |
a6a2274a | 2003 | as well as in the tests below, that all addresses are in |
e4600702 RK |
2004 | canonical form. */ |
2005 | ||
3dcc68a4 | 2006 | else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) |
54dac99e | 2007 | { |
e4600702 RK |
2008 | record_address_regs (arg0, class, scale); |
2009 | if (! CONSTANT_P (arg1)) | |
2010 | record_address_regs (arg1, class, scale); | |
54dac99e | 2011 | } |
e4600702 RK |
2012 | |
2013 | /* If the second operand is a constant integer, it doesn't change | |
2014 | what class the first operand must be. */ | |
2015 | ||
2016 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
2017 | record_address_regs (arg0, class, scale); | |
2018 | ||
2019 | /* If the second operand is a symbolic constant, the first operand | |
2020 | must be an index register. */ | |
2021 | ||
2022 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
2023 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
2024 | ||
956d6950 JL |
2025 | /* If both operands are registers but one is already a hard register |
2026 | of index or base class, give the other the class that the hard | |
2027 | register is not. */ | |
2028 | ||
3f9e9508 | 2029 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
2030 | else if (code0 == REG && code1 == REG |
2031 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
2032 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
2033 | record_address_regs (arg1, | |
2034 | REG_OK_FOR_BASE_P (arg0) | |
3dcc68a4 | 2035 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 JL |
2036 | scale); |
2037 | else if (code0 == REG && code1 == REG | |
2038 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
2039 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
2040 | record_address_regs (arg0, | |
2041 | REG_OK_FOR_BASE_P (arg1) | |
3dcc68a4 | 2042 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 | 2043 | scale); |
3f9e9508 | 2044 | #endif |
956d6950 | 2045 | |
e9a25f70 JL |
2046 | /* If one operand is known to be a pointer, it must be the base |
2047 | with the other operand the index. Likewise if the other operand | |
2048 | is a MULT. */ | |
f22376c7 | 2049 | |
3502dc9c | 2050 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 2051 | || code1 == MULT) |
f22376c7 | 2052 | { |
3dcc68a4 | 2053 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2054 | record_address_regs (arg1, INDEX_REG_CLASS, scale); |
2055 | } | |
3502dc9c | 2056 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 2057 | || code0 == MULT) |
f22376c7 CI |
2058 | { |
2059 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
3dcc68a4 | 2060 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2061 | } |
2062 | ||
e9a25f70 | 2063 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
2064 | or index register. This case should be rare. */ |
2065 | ||
e9a25f70 | 2066 | else |
54dac99e | 2067 | { |
3dcc68a4 NC |
2068 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), |
2069 | scale / 2); | |
e4600702 | 2070 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); |
3dcc68a4 NC |
2071 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), |
2072 | scale / 2); | |
e4600702 | 2073 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); |
54dac99e | 2074 | } |
54dac99e RK |
2075 | } |
2076 | break; | |
2077 | ||
4b983fdc RH |
2078 | /* Double the importance of a pseudo register that is incremented |
2079 | or decremented, since it would take two extra insns | |
2080 | if it ends up in the wrong place. */ | |
2081 | case POST_MODIFY: | |
2082 | case PRE_MODIFY: | |
3dcc68a4 NC |
2083 | record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), |
2084 | 2 * scale); | |
4b983fdc RH |
2085 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
2086 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
2087 | INDEX_REG_CLASS, 2 * scale); | |
2088 | break; | |
2089 | ||
54dac99e RK |
2090 | case POST_INC: |
2091 | case PRE_INC: | |
2092 | case POST_DEC: | |
2093 | case PRE_DEC: | |
2094 | /* Double the importance of a pseudo register that is incremented | |
2095 | or decremented, since it would take two extra insns | |
533d0835 RK |
2096 | if it ends up in the wrong place. If the operand is a pseudo, |
2097 | show it is being used in an INC_DEC context. */ | |
2098 | ||
2099 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2100 | if (GET_CODE (XEXP (x, 0)) == REG | |
2101 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
2102 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2103 | #endif | |
e4600702 RK |
2104 | |
2105 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
2106 | break; |
2107 | ||
2108 | case REG: | |
2109 | { | |
b3694847 SS |
2110 | struct costs *pp = &costs[REGNO (x)]; |
2111 | int i; | |
54dac99e | 2112 | |
cbd5b9a2 | 2113 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 2114 | |
e4600702 | 2115 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 2116 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
2117 | } |
2118 | break; | |
2119 | ||
2120 | default: | |
2121 | { | |
b3694847 SS |
2122 | const char *fmt = GET_RTX_FORMAT (code); |
2123 | int i; | |
54dac99e RK |
2124 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2125 | if (fmt[i] == 'e') | |
e4600702 | 2126 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
2127 | } |
2128 | } | |
2129 | } | |
08d95f91 RK |
2130 | \f |
2131 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2132 | ||
2133 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2134 | to an object of MODE. */ | |
2135 | ||
1d300e19 | 2136 | static int |
08d95f91 RK |
2137 | auto_inc_dec_reg_p (reg, mode) |
2138 | rtx reg; | |
2139 | enum machine_mode mode; | |
2140 | { | |
940da324 JL |
2141 | if (HAVE_POST_INCREMENT |
2142 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2143 | return 1; |
08d95f91 | 2144 | |
940da324 JL |
2145 | if (HAVE_POST_DECREMENT |
2146 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2147 | return 1; |
08d95f91 | 2148 | |
940da324 JL |
2149 | if (HAVE_PRE_INCREMENT |
2150 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2151 | return 1; |
08d95f91 | 2152 | |
940da324 JL |
2153 | if (HAVE_PRE_DECREMENT |
2154 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2155 | return 1; |
08d95f91 RK |
2156 | |
2157 | return 0; | |
2158 | } | |
2159 | #endif | |
b1f21e0a | 2160 | \f |
da668e9c MM |
2161 | static short *renumber; |
2162 | static size_t regno_allocated; | |
2163 | static unsigned int reg_n_max; | |
ed396e68 | 2164 | |
b1f21e0a MM |
2165 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2166 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
2167 | NEW_P is non zero, initialize all of the registers, otherwise only |
2168 | initialize the new registers allocated. The same table is kept from | |
2169 | function to function, only reallocating it when we need more room. If | |
2170 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
2171 | |
2172 | void | |
39379e67 | 2173 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 2174 | size_t num_regs; |
b1f21e0a | 2175 | int new_p; |
39379e67 | 2176 | int renumber_p; |
b1f21e0a | 2177 | { |
6feacd09 MM |
2178 | size_t size_info; |
2179 | size_t size_renumber; | |
2180 | size_t min = (new_p) ? 0 : reg_n_max; | |
2181 | struct reg_info_data *reg_data; | |
39379e67 | 2182 | |
b1f21e0a MM |
2183 | if (num_regs > regno_allocated) |
2184 | { | |
6feacd09 MM |
2185 | size_t old_allocated = regno_allocated; |
2186 | ||
b1f21e0a | 2187 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
2188 | size_renumber = regno_allocated * sizeof (short); |
2189 | ||
2190 | if (!reg_n_info) | |
2191 | { | |
6feacd09 | 2192 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 2193 | renumber = (short *) xmalloc (size_renumber); |
a6a2274a | 2194 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
9ffc5a70 | 2195 | * sizeof (struct reg_pref)); |
39379e67 MM |
2196 | } |
2197 | ||
2198 | else | |
2199 | { | |
6feacd09 MM |
2200 | VARRAY_GROW (reg_n_info, regno_allocated); |
2201 | ||
2202 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
2203 | { | |
8e2e89f7 KH |
2204 | free ((char *) renumber); |
2205 | free ((char *) reg_pref); | |
6feacd09 | 2206 | renumber = (short *) xmalloc (size_renumber); |
a6a2274a | 2207 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
9ffc5a70 | 2208 | * sizeof (struct reg_pref)); |
6feacd09 MM |
2209 | } |
2210 | ||
2211 | else | |
2212 | { | |
8e2e89f7 KH |
2213 | renumber = (short *) xrealloc ((char *) renumber, size_renumber); |
2214 | reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer, | |
a6a2274a | 2215 | regno_allocated |
9ffc5a70 | 2216 | * sizeof (struct reg_pref)); |
6feacd09 | 2217 | } |
39379e67 | 2218 | } |
6feacd09 MM |
2219 | |
2220 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2221 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
2222 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
2223 | reg_data->min_index = old_allocated; | |
2224 | reg_data->max_index = regno_allocated - 1; | |
2225 | reg_data->next = reg_info_head; | |
2226 | reg_info_head = reg_data; | |
b1f21e0a MM |
2227 | } |
2228 | ||
6feacd09 | 2229 | reg_n_max = num_regs; |
b1f21e0a MM |
2230 | if (min < num_regs) |
2231 | { | |
6feacd09 MM |
2232 | /* Loop through each of the segments allocated for the actual |
2233 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
a6a2274a | 2234 | for (reg_data = reg_info_head; |
da668e9c MM |
2235 | reg_data && reg_data->max_index >= min; |
2236 | reg_data = reg_data->next) | |
39379e67 | 2237 | { |
6feacd09 MM |
2238 | size_t min_index = reg_data->min_index; |
2239 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2240 | size_t max = MIN (max_index, num_regs); |
2241 | size_t local_min = min - min_index; | |
2242 | size_t i; | |
6feacd09 | 2243 | |
da668e9c MM |
2244 | if (reg_data->min_index > num_regs) |
2245 | continue; | |
6feacd09 | 2246 | |
da668e9c MM |
2247 | if (min < min_index) |
2248 | local_min = 0; | |
2249 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2250 | reg_data->used_p = 1; /* no need to zero */ | |
2251 | else | |
961192e1 | 2252 | memset ((char *) ®_data->data[local_min], 0, |
da668e9c MM |
2253 | sizeof (reg_info) * (max - min_index - local_min + 1)); |
2254 | ||
2255 | for (i = min_index+local_min; i <= max; i++) | |
2256 | { | |
2257 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2258 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2259 | renumber[i] = -1; | |
2260 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2261 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2262 | } |
39379e67 | 2263 | } |
b1f21e0a MM |
2264 | } |
2265 | ||
6feacd09 MM |
2266 | /* If {pref,alt}class have already been allocated, update the pointers to |
2267 | the newly realloced ones. */ | |
9ffc5a70 JH |
2268 | if (reg_pref) |
2269 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2270 | |
39379e67 MM |
2271 | if (renumber_p) |
2272 | reg_renumber = renumber; | |
2273 | ||
73b76448 RK |
2274 | /* Tell the regset code about the new number of registers */ |
2275 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
2276 | } |
2277 | ||
ed396e68 BS |
2278 | /* Free up the space allocated by allocate_reg_info. */ |
2279 | void | |
2280 | free_reg_info () | |
2281 | { | |
2282 | if (reg_n_info) | |
2283 | { | |
2284 | struct reg_info_data *reg_data; | |
2285 | struct reg_info_data *reg_next; | |
2286 | ||
2287 | VARRAY_FREE (reg_n_info); | |
2288 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2289 | { | |
2290 | reg_next = reg_data->next; | |
8e2e89f7 | 2291 | free ((char *) reg_data); |
ed396e68 BS |
2292 | } |
2293 | ||
9ffc5a70 | 2294 | free (reg_pref_buffer); |
f4f4d0f8 KH |
2295 | reg_pref_buffer = (struct reg_pref *) 0; |
2296 | reg_info_head = (struct reg_info_data *) 0; | |
2297 | renumber = (short *) 0; | |
ed396e68 BS |
2298 | } |
2299 | regno_allocated = 0; | |
2300 | reg_n_max = 0; | |
2301 | } | |
54dac99e RK |
2302 | \f |
2303 | /* This is the `regscan' pass of the compiler, run just before cse | |
2304 | and again just before loop. | |
2305 | ||
2306 | It finds the first and last use of each pseudo-register | |
2307 | and records them in the vectors regno_first_uid, regno_last_uid | |
2308 | and counts the number of sets in the vector reg_n_sets. | |
2309 | ||
2310 | REPEAT is nonzero the second time this is called. */ | |
2311 | ||
54dac99e | 2312 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2313 | Always at least 3, since the combiner could put that many together |
79b9ec0d RK |
2314 | and we want this to remain correct for all the remaining passes. |
2315 | This corresponds to the maximum number of times note_stores will call | |
2316 | a function for any insn. */ | |
54dac99e RK |
2317 | |
2318 | int max_parallel; | |
2319 | ||
a6a2274a | 2320 | /* Used as a temporary to record the largest number of registers in |
79b9ec0d RK |
2321 | PARALLEL in a SET_DEST. This is added to max_parallel. */ |
2322 | ||
2323 | static int max_set_parallel; | |
2324 | ||
54dac99e RK |
2325 | void |
2326 | reg_scan (f, nregs, repeat) | |
2327 | rtx f; | |
770ae6cc | 2328 | unsigned int nregs; |
272df862 | 2329 | int repeat ATTRIBUTE_UNUSED; |
54dac99e | 2330 | { |
b3694847 | 2331 | rtx insn; |
54dac99e | 2332 | |
39379e67 | 2333 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e | 2334 | max_parallel = 3; |
79b9ec0d | 2335 | max_set_parallel = 0; |
54dac99e RK |
2336 | |
2337 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2338 | if (GET_CODE (insn) == INSN | |
2339 | || GET_CODE (insn) == CALL_INSN | |
2340 | || GET_CODE (insn) == JUMP_INSN) | |
2341 | { | |
2342 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2343 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2344 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2345 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2346 | |
2347 | if (REG_NOTES (insn)) | |
f903b91f DM |
2348 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2349 | } | |
79b9ec0d RK |
2350 | |
2351 | max_parallel += max_set_parallel; | |
f903b91f DM |
2352 | } |
2353 | ||
2354 | /* Update 'regscan' information by looking at the insns | |
2355 | from FIRST to LAST. Some new REGs have been created, | |
2356 | and any REG with number greater than OLD_MAX_REGNO is | |
2357 | such a REG. We only update information for those. */ | |
2358 | ||
2359 | void | |
770ae6cc | 2360 | reg_scan_update (first, last, old_max_regno) |
f903b91f DM |
2361 | rtx first; |
2362 | rtx last; | |
770ae6cc | 2363 | unsigned int old_max_regno; |
f903b91f | 2364 | { |
b3694847 | 2365 | rtx insn; |
f903b91f DM |
2366 | |
2367 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2368 | ||
2369 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2370 | if (GET_CODE (insn) == INSN | |
2371 | || GET_CODE (insn) == CALL_INSN | |
2372 | || GET_CODE (insn) == JUMP_INSN) | |
2373 | { | |
2374 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2375 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2376 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2377 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2378 | ||
2379 | if (REG_NOTES (insn)) | |
2380 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2381 | } |
2382 | } | |
2383 | ||
1ebecb64 | 2384 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2385 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2386 | We should only record information for REGs with numbers | |
2387 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2388 | |
08d95f91 | 2389 | static void |
f903b91f | 2390 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2391 | rtx x; |
be8dcd74 | 2392 | rtx insn; |
1ebecb64 | 2393 | int note_flag; |
770ae6cc | 2394 | unsigned int min_regno; |
54dac99e | 2395 | { |
b3694847 SS |
2396 | enum rtx_code code; |
2397 | rtx dest; | |
2398 | rtx note; | |
54dac99e | 2399 | |
fa23c636 | 2400 | code = GET_CODE (x); |
54dac99e RK |
2401 | switch (code) |
2402 | { | |
54dac99e | 2403 | case CONST: |
185ebd6c | 2404 | case CONST_INT: |
54dac99e | 2405 | case CONST_DOUBLE: |
69ef87e2 | 2406 | case CONST_VECTOR: |
54dac99e RK |
2407 | case CC0: |
2408 | case PC: | |
2409 | case SYMBOL_REF: | |
2410 | case LABEL_REF: | |
2411 | case ADDR_VEC: | |
2412 | case ADDR_DIFF_VEC: | |
2413 | return; | |
2414 | ||
2415 | case REG: | |
2416 | { | |
770ae6cc | 2417 | unsigned int regno = REGNO (x); |
54dac99e | 2418 | |
f903b91f DM |
2419 | if (regno >= min_regno) |
2420 | { | |
2421 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2422 | if (!note_flag) | |
2423 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2424 | if (REGNO_FIRST_UID (regno) == 0) | |
2425 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
2426 | } | |
54dac99e RK |
2427 | } |
2428 | break; | |
2429 | ||
01565a55 | 2430 | case EXPR_LIST: |
7b18c3db | 2431 | if (XEXP (x, 0)) |
f903b91f | 2432 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2433 | if (XEXP (x, 1)) |
f903b91f | 2434 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2435 | break; |
2436 | ||
2437 | case INSN_LIST: | |
2438 | if (XEXP (x, 1)) | |
f903b91f | 2439 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2440 | break; |
2441 | ||
54dac99e RK |
2442 | case SET: |
2443 | /* Count a set of the destination if it is a register. */ | |
2444 | for (dest = SET_DEST (x); | |
2445 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2446 | || GET_CODE (dest) == ZERO_EXTEND; | |
2447 | dest = XEXP (dest, 0)) | |
2448 | ; | |
2449 | ||
79b9ec0d RK |
2450 | /* For a PARALLEL, record the number of things (less the usual one for a |
2451 | SET) that are set. */ | |
2452 | if (GET_CODE (dest) == PARALLEL) | |
2453 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2454 | ||
f903b91f DM |
2455 | if (GET_CODE (dest) == REG |
2456 | && REGNO (dest) >= min_regno) | |
b2d57793 DB |
2457 | { |
2458 | REG_N_SETS (REGNO (dest))++; | |
2459 | REG_N_REFS (REGNO (dest))++; | |
2460 | } | |
54dac99e | 2461 | |
be8dcd74 RK |
2462 | /* If this is setting a pseudo from another pseudo or the sum of a |
2463 | pseudo and a constant integer and the other pseudo is known to be | |
2464 | a pointer, set the destination to be a pointer as well. | |
2465 | ||
2466 | Likewise if it is setting the destination from an address or from a | |
2467 | value equivalent to an address or to the sum of an address and | |
2468 | something else. | |
a6a2274a | 2469 | |
be8dcd74 RK |
2470 | But don't do any of this if the pseudo corresponds to a user |
2471 | variable since it should have already been set as a pointer based | |
2472 | on the type. */ | |
2473 | ||
2474 | if (GET_CODE (SET_DEST (x)) == REG | |
2475 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2476 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2477 | /* If the destination pseudo is set more than once, then other |
2478 | sets might not be to a pointer value (consider access to a | |
2479 | union in two threads of control in the presense of global | |
3502dc9c | 2480 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2481 | pseudo if this is the only set of that pseudo. */ |
2482 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2483 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2484 | && ! REG_POINTER (SET_DEST (x)) |
be8dcd74 | 2485 | && ((GET_CODE (SET_SRC (x)) == REG |
3502dc9c | 2486 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2487 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2488 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2489 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2490 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3502dc9c | 2491 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2492 | || GET_CODE (SET_SRC (x)) == CONST |
2493 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2494 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2495 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2496 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2497 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2498 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2499 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2500 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2501 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2502 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2503 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2504 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2505 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2506 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2507 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2508 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2509 | |
0d4903b8 RK |
2510 | /* If this is setting a register from a register or from a simple |
2511 | conversion of a register, propagate REG_DECL. */ | |
2512 | if (GET_CODE (dest) == REG) | |
2513 | { | |
2514 | rtx src = SET_SRC (x); | |
2515 | ||
2516 | while (GET_CODE (src) == SIGN_EXTEND | |
2517 | || GET_CODE (src) == ZERO_EXTEND | |
2518 | || GET_CODE (src) == TRUNCATE | |
2519 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2520 | src = XEXP (src, 0); | |
2521 | ||
2522 | if (GET_CODE (src) == REG && REGNO_DECL (REGNO (src)) == 0) | |
2523 | REGNO_DECL (REGNO (src)) = REGNO_DECL (REGNO (dest)); | |
2524 | else if (GET_CODE (src) == REG && REGNO_DECL (REGNO (dest)) == 0) | |
2525 | REGNO_DECL (REGNO (dest)) = REGNO_DECL (REGNO (src)); | |
2526 | } | |
2527 | ||
0f41302f | 2528 | /* ... fall through ... */ |
54dac99e RK |
2529 | |
2530 | default: | |
2531 | { | |
b3694847 SS |
2532 | const char *fmt = GET_RTX_FORMAT (code); |
2533 | int i; | |
54dac99e RK |
2534 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2535 | { | |
2536 | if (fmt[i] == 'e') | |
f903b91f | 2537 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2538 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2539 | { | |
b3694847 | 2540 | int j; |
54dac99e | 2541 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
f903b91f | 2542 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2543 | } |
2544 | } | |
2545 | } | |
2546 | } | |
2547 | } | |
2548 | \f | |
2549 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2550 | is also in C2. */ | |
2551 | ||
2552 | int | |
2553 | reg_class_subset_p (c1, c2) | |
b3694847 SS |
2554 | enum reg_class c1; |
2555 | enum reg_class c2; | |
54dac99e RK |
2556 | { |
2557 | if (c1 == c2) return 1; | |
2558 | ||
2559 | if (c2 == ALL_REGS) | |
2560 | win: | |
2561 | return 1; | |
8e2e89f7 KH |
2562 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], |
2563 | reg_class_contents[(int) c2], | |
54dac99e RK |
2564 | win); |
2565 | return 0; | |
2566 | } | |
2567 | ||
2568 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2569 | ||
2570 | int | |
2571 | reg_classes_intersect_p (c1, c2) | |
b3694847 SS |
2572 | enum reg_class c1; |
2573 | enum reg_class c2; | |
54dac99e RK |
2574 | { |
2575 | #ifdef HARD_REG_SET | |
2576 | register | |
2577 | #endif | |
2578 | HARD_REG_SET c; | |
2579 | ||
2580 | if (c1 == c2) return 1; | |
2581 | ||
2582 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2583 | return 1; | |
2584 | ||
2585 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2586 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2587 | ||
2588 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2589 | return 1; | |
2590 | ||
2591 | lose: | |
2592 | return 0; | |
2593 | } | |
2594 | ||
73b76448 RK |
2595 | /* Release any memory allocated by register sets. */ |
2596 | ||
2597 | void | |
2598 | regset_release_memory () | |
2599 | { | |
73b76448 RK |
2600 | bitmap_release_memory (); |
2601 | } | |
e2500fed GK |
2602 | |
2603 | #include "gt-regclass.h" |