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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
58b23af8 | 3 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
54dac99e | 4 | |
1322177d | 5 | This file is part of GCC. |
54dac99e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
54dac99e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
54dac99e RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
54dac99e RK |
21 | |
22 | ||
23 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
24 | It also defines some tables of information about the hardware registers | |
25 | and a function init_reg_sets to initialize the tables. */ | |
26 | ||
27 | #include "config.h" | |
670ee920 | 28 | #include "system.h" |
4977bab6 ZW |
29 | #include "coretypes.h" |
30 | #include "tm.h" | |
cff9f8d5 | 31 | #include "hard-reg-set.h" |
54dac99e | 32 | #include "rtl.h" |
0829d244 | 33 | #include "expr.h" |
6baf1cc8 | 34 | #include "tm_p.h" |
54dac99e RK |
35 | #include "flags.h" |
36 | #include "basic-block.h" | |
37 | #include "regs.h" | |
49ad7cfa | 38 | #include "function.h" |
54dac99e RK |
39 | #include "insn-config.h" |
40 | #include "recog.h" | |
e4600702 RK |
41 | #include "reload.h" |
42 | #include "real.h" | |
10f0ad3d | 43 | #include "toplev.h" |
d6f4ec51 | 44 | #include "output.h" |
8b0212ca | 45 | #include "ggc.h" |
0d446150 | 46 | #include "timevar.h" |
54dac99e | 47 | |
0c20a65f AJ |
48 | static void init_reg_sets_1 (void); |
49 | static void init_reg_modes (void); | |
50 | static void init_reg_autoinc (void); | |
24deb20a | 51 | |
533d0835 RK |
52 | /* If we have auto-increment or auto-decrement and we can have secondary |
53 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 54 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
55 | |
56 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 57 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
58 | #define FORBIDDEN_INC_DEC_CLASSES |
59 | #endif | |
60 | #endif | |
54dac99e RK |
61 | \f |
62 | /* Register tables used by many passes. */ | |
63 | ||
64 | /* Indexed by hard register number, contains 1 for registers | |
65 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
66 | These are the registers that cannot be used to allocate | |
252f342a | 67 | a pseudo reg for general use. */ |
54dac99e RK |
68 | |
69 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
70 | ||
71 | /* Same info as a HARD_REG_SET. */ | |
72 | ||
73 | HARD_REG_SET fixed_reg_set; | |
74 | ||
75 | /* Data for initializing the above. */ | |
76 | ||
8b60264b | 77 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
54dac99e RK |
78 | |
79 | /* Indexed by hard register number, contains 1 for registers | |
80 | that are fixed use or are clobbered by function calls. | |
81 | These are the registers that cannot be used to allocate | |
252f342a MH |
82 | a pseudo reg whose life crosses calls unless we are able |
83 | to save/restore them across the calls. */ | |
54dac99e RK |
84 | |
85 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
86 | ||
87 | /* Same info as a HARD_REG_SET. */ | |
88 | ||
89 | HARD_REG_SET call_used_reg_set; | |
90 | ||
6cad67d2 JL |
91 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
92 | HARD_REG_SET losing_caller_save_reg_set; | |
93 | ||
54dac99e RK |
94 | /* Data for initializing the above. */ |
95 | ||
8b60264b | 96 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
fc1296b7 AM |
97 | |
98 | /* This is much like call_used_regs, except it doesn't have to | |
99 | be a superset of FIXED_REGISTERS. This vector indicates | |
a6a2274a | 100 | what is really call clobbered, and is used when defining |
fc1296b7 AM |
101 | regs_invalidated_by_call. */ |
102 | ||
fc1296b7 | 103 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa | 104 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
fc1296b7 | 105 | #endif |
a6a2274a | 106 | |
54dac99e | 107 | /* Indexed by hard register number, contains 1 for registers that are |
252f342a MH |
108 | fixed use or call used registers that cannot hold quantities across |
109 | calls even if we are willing to save and restore them. call fixed | |
110 | registers are a subset of call used registers. */ | |
54dac99e RK |
111 | |
112 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
113 | ||
114 | /* The same info as a HARD_REG_SET. */ | |
115 | ||
116 | HARD_REG_SET call_fixed_reg_set; | |
117 | ||
118 | /* Number of non-fixed registers. */ | |
119 | ||
120 | int n_non_fixed_regs; | |
121 | ||
122 | /* Indexed by hard register number, contains 1 for registers | |
123 | that are being used for global register decls. | |
124 | These must be exempt from ordinary flow analysis | |
125 | and are also considered fixed. */ | |
126 | ||
127 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
4e2db584 RH |
128 | |
129 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
130 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
131 | for someone's bright idea to have call_used_regs strictly include | |
132 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
133 | that are actually preserved. We know for sure that those associated | |
134 | with the local stack frame are safe, but scant others. */ | |
135 | ||
136 | HARD_REG_SET regs_invalidated_by_call; | |
137 | ||
54dac99e RK |
138 | /* Table of register numbers in the order in which to try to use them. */ |
139 | #ifdef REG_ALLOC_ORDER | |
140 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
141 | |
142 | /* The inverse of reg_alloc_order. */ | |
143 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
144 | #endif |
145 | ||
146 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
147 | ||
2e0e2b76 CH |
148 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
149 | ||
089e575b RS |
150 | /* The same information, but as an array of unsigned ints. We copy from |
151 | these unsigned ints to the table above. We do this so the tm.h files | |
d4845339 RH |
152 | do not have to be aware of the wordsize for machines with <= 64 regs. |
153 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
2e0e2b76 CH |
154 | |
155 | #define N_REG_INTS \ | |
d4845339 | 156 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
2e0e2b76 | 157 | |
a6a2274a | 158 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 159 | = REG_CLASS_CONTENTS; |
54dac99e RK |
160 | |
161 | /* For each reg class, number of regs it contains. */ | |
162 | ||
770ae6cc | 163 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
164 | |
165 | /* For each reg class, table listing all the containing classes. */ | |
166 | ||
167 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
168 | ||
169 | /* For each reg class, table listing all the classes contained in it. */ | |
170 | ||
171 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
172 | ||
173 | /* For each pair of reg classes, | |
174 | a largest reg class contained in their union. */ | |
175 | ||
176 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
177 | ||
178 | /* For each pair of reg classes, | |
179 | the smallest reg class containing their union. */ | |
180 | ||
181 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
182 | ||
fbd40359 ZW |
183 | /* Array containing all of the register names. Unless |
184 | DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ | |
d05c8ee7 | 185 | |
fbd40359 | 186 | #ifdef DEBUG_REGISTER_NAMES |
e087aeb2 | 187 | const char * reg_names[] = REGISTER_NAMES; |
fbd40359 | 188 | #endif |
d05c8ee7 | 189 | |
ca4aac00 DE |
190 | /* For each hard register, the widest mode object that it can contain. |
191 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
192 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
193 | register. */ | |
194 | ||
195 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
196 | ||
6df26b8f JH |
197 | /* 1 if class does contain register of given mode. */ |
198 | ||
199 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
200 | ||
e4600702 RK |
201 | /* Maximum cost of moving from a register in one class to a register in |
202 | another class. Based on REGISTER_MOVE_COST. */ | |
203 | ||
e56b4594 | 204 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
205 | |
206 | /* Similar, but here we don't have to move if the first index is a subset | |
207 | of the second so in that case the cost is zero. */ | |
208 | ||
e56b4594 | 209 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
210 | |
211 | /* Similar, but here we don't have to move if the first index is a superset | |
212 | of the second so in that case the cost is zero. */ | |
213 | ||
e56b4594 | 214 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 215 | |
533d0835 RK |
216 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
217 | ||
218 | /* These are the classes that regs which are auto-incremented or decremented | |
219 | cannot be put in. */ | |
220 | ||
221 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
222 | ||
40f03658 | 223 | /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec |
533d0835 RK |
224 | context. */ |
225 | ||
226 | static char *in_inc_dec; | |
227 | ||
5fcb671c | 228 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 229 | |
cff9f8d5 | 230 | #ifdef CANNOT_CHANGE_MODE_CLASS |
10a3fdd9 JH |
231 | /* All registers that have been subreged. Indexed by regno * MAX_MACHINE_MODE |
232 | + mode. */ | |
233 | bitmap_head subregs_of_mode; | |
cff9f8d5 | 234 | #endif |
e79f71f7 | 235 | |
473fe49b KR |
236 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
237 | ||
e2500fed | 238 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
473fe49b | 239 | |
6feacd09 MM |
240 | /* Linked list of reg_info structures allocated for reg_n_info array. |
241 | Grouping all of the allocated structures together in one lump | |
242 | means only one call to bzero to clear them, rather than n smaller | |
243 | calls. */ | |
244 | struct reg_info_data { | |
245 | struct reg_info_data *next; /* next set of reg_info structures */ | |
246 | size_t min_index; /* minimum index # */ | |
247 | size_t max_index; /* maximum index # */ | |
40f03658 | 248 | char used_p; /* nonzero if this has been used previously */ |
6feacd09 MM |
249 | reg_info data[1]; /* beginning of the reg_info data */ |
250 | }; | |
251 | ||
252 | static struct reg_info_data *reg_info_head; | |
253 | ||
c07c7c9d | 254 | /* No more global register variables may be declared; true once |
dc297297 | 255 | regclass has been initialized. */ |
6c85df69 AH |
256 | |
257 | static int no_global_reg_vars = 0; | |
258 | ||
6feacd09 | 259 | |
54dac99e RK |
260 | /* Function called only once to initialize the above data on reg usage. |
261 | Once this is done, various switches may override. */ | |
262 | ||
263 | void | |
0c20a65f | 264 | init_reg_sets (void) |
54dac99e | 265 | { |
b3694847 | 266 | int i, j; |
54dac99e | 267 | |
2e0e2b76 CH |
268 | /* First copy the register information from the initial int form into |
269 | the regsets. */ | |
270 | ||
271 | for (i = 0; i < N_REG_CLASSES; i++) | |
272 | { | |
273 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
274 | ||
b85946fc | 275 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
2e0e2b76 | 276 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
b85946fc RH |
277 | if (int_reg_class_contents[i][j / 32] |
278 | & ((unsigned) 1 << (j % 32))) | |
2e0e2b76 CH |
279 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
280 | } | |
281 | ||
4e135bdd KG |
282 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
283 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 284 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 285 | |
3eae4643 | 286 | /* Do any additional initialization regsets may need. */ |
910bc42d | 287 | INIT_ONCE_REG_SET (); |
f5d8c9f4 BS |
288 | |
289 | #ifdef REG_ALLOC_ORDER | |
290 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
291 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
292 | #endif | |
910bc42d R |
293 | } |
294 | ||
295 | /* After switches have been processed, which perhaps alter | |
296 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
297 | ||
298 | static void | |
0c20a65f | 299 | init_reg_sets_1 (void) |
910bc42d | 300 | { |
b3694847 SS |
301 | unsigned int i, j; |
302 | unsigned int /* enum machine_mode */ m; | |
6836e024 | 303 | char allocatable_regs_of_mode [MAX_MACHINE_MODE]; |
910bc42d R |
304 | |
305 | /* This macro allows the fixed or call-used registers | |
306 | and the register classes to depend on target flags. */ | |
307 | ||
308 | #ifdef CONDITIONAL_REGISTER_USAGE | |
309 | CONDITIONAL_REGISTER_USAGE; | |
310 | #endif | |
311 | ||
54dac99e RK |
312 | /* Compute number of hard regs in each class. */ |
313 | ||
703ad42b | 314 | memset (reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
315 | for (i = 0; i < N_REG_CLASSES; i++) |
316 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
317 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
318 | reg_class_size[i]++; | |
319 | ||
320 | /* Initialize the table of subunions. | |
321 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
322 | that is contained in the union of classes I and J. */ | |
323 | ||
324 | for (i = 0; i < N_REG_CLASSES; i++) | |
325 | { | |
326 | for (j = 0; j < N_REG_CLASSES; j++) | |
327 | { | |
328 | #ifdef HARD_REG_SET | |
329 | register /* Declare it register if it's a scalar. */ | |
330 | #endif | |
331 | HARD_REG_SET c; | |
b3694847 | 332 | int k; |
54dac99e RK |
333 | |
334 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
335 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
336 | for (k = 0; k < N_REG_CLASSES; k++) | |
337 | { | |
338 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
339 | subclass1); | |
340 | continue; | |
341 | ||
342 | subclass1: | |
343 | /* keep the largest subclass */ /* SPEE 900308 */ | |
344 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
345 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
346 | subclass2); | |
347 | reg_class_subunion[i][j] = (enum reg_class) k; | |
348 | subclass2: | |
349 | ; | |
350 | } | |
351 | } | |
352 | } | |
353 | ||
354 | /* Initialize the table of superunions. | |
355 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
356 | containing the union of classes I and J. */ | |
357 | ||
358 | for (i = 0; i < N_REG_CLASSES; i++) | |
359 | { | |
360 | for (j = 0; j < N_REG_CLASSES; j++) | |
361 | { | |
362 | #ifdef HARD_REG_SET | |
363 | register /* Declare it register if it's a scalar. */ | |
364 | #endif | |
365 | HARD_REG_SET c; | |
b3694847 | 366 | int k; |
54dac99e RK |
367 | |
368 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
369 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
370 | for (k = 0; k < N_REG_CLASSES; k++) | |
371 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
372 | ||
373 | superclass: | |
374 | reg_class_superunion[i][j] = (enum reg_class) k; | |
375 | } | |
376 | } | |
377 | ||
378 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
379 | First clear the whole table, then add the elements as they are found. */ | |
380 | ||
381 | for (i = 0; i < N_REG_CLASSES; i++) | |
382 | { | |
383 | for (j = 0; j < N_REG_CLASSES; j++) | |
384 | { | |
385 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
386 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
387 | } | |
388 | } | |
389 | ||
390 | for (i = 0; i < N_REG_CLASSES; i++) | |
391 | { | |
392 | if (i == (int) NO_REGS) | |
393 | continue; | |
394 | ||
395 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
396 | { | |
397 | enum reg_class *p; | |
398 | ||
399 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
400 | subclass); | |
401 | continue; | |
402 | subclass: | |
403 | /* Reg class I is a subclass of J. | |
404 | Add J to the table of superclasses of I. */ | |
405 | p = ®_class_superclasses[i][0]; | |
406 | while (*p != LIM_REG_CLASSES) p++; | |
407 | *p = (enum reg_class) j; | |
408 | /* Add I to the table of superclasses of J. */ | |
409 | p = ®_class_subclasses[j][0]; | |
410 | while (*p != LIM_REG_CLASSES) p++; | |
411 | *p = (enum reg_class) i; | |
412 | } | |
413 | } | |
e4600702 | 414 | |
54dac99e RK |
415 | /* Initialize "constant" tables. */ |
416 | ||
417 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
418 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
419 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
4e2db584 | 420 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
54dac99e | 421 | |
4e135bdd | 422 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e RK |
423 | |
424 | n_non_fixed_regs = 0; | |
425 | ||
426 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
427 | { | |
54dac99e RK |
428 | if (fixed_regs[i]) |
429 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
430 | else | |
431 | n_non_fixed_regs++; | |
432 | ||
433 | if (call_used_regs[i]) | |
434 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
435 | if (call_fixed_regs[i]) | |
436 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
437 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
438 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
4e2db584 RH |
439 | |
440 | /* There are a couple of fixed registers that we know are safe to | |
441 | exclude from being clobbered by calls: | |
442 | ||
443 | The frame pointer is always preserved across calls. The arg pointer | |
444 | is if it is fixed. The stack pointer usually is, unless | |
445 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
446 | If we are generating PIC code, the PIC offset table register is | |
447 | preserved across calls, though the target can override that. */ | |
a6a2274a | 448 | |
4e2db584 RH |
449 | if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) |
450 | ; | |
451 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
452 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
453 | ; | |
454 | #endif | |
455 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
456 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
457 | ; | |
458 | #endif | |
459 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
fc555370 | 460 | else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
4e2db584 RH |
461 | ; |
462 | #endif | |
d3259baa | 463 | else if (0 |
6ca3c22f | 464 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa RH |
465 | || call_really_used_regs[i] |
466 | #else | |
467 | || call_used_regs[i] | |
468 | #endif | |
469 | || global_regs[i]) | |
4e2db584 | 470 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
54dac99e | 471 | } |
4e2db584 | 472 | |
6836e024 JH |
473 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
474 | memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); | |
dbbbbf3b | 475 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 | 476 | for (i = 0; i < N_REG_CLASSES; i++) |
f7043461 | 477 | if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
6df26b8f JH |
478 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
479 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
480 | && HARD_REGNO_MODE_OK (j, m)) | |
481 | { | |
482 | contains_reg_of_mode [i][m] = 1; | |
483 | allocatable_regs_of_mode [m] = 1; | |
484 | break; | |
485 | } | |
acbce667 KR |
486 | |
487 | /* Initialize the move cost table. Find every subset of each class | |
488 | and take the maximum cost of moving any subset to any other. */ | |
489 | ||
dbbbbf3b | 490 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 JH |
491 | if (allocatable_regs_of_mode [m]) |
492 | { | |
493 | for (i = 0; i < N_REG_CLASSES; i++) | |
494 | if (contains_reg_of_mode [i][m]) | |
495 | for (j = 0; j < N_REG_CLASSES; j++) | |
496 | { | |
497 | int cost; | |
498 | enum reg_class *p1, *p2; | |
499 | ||
500 | if (!contains_reg_of_mode [j][m]) | |
501 | { | |
502 | move_cost[m][i][j] = 65536; | |
503 | may_move_in_cost[m][i][j] = 65536; | |
504 | may_move_out_cost[m][i][j] = 65536; | |
505 | } | |
506 | else | |
507 | { | |
26a952a8 | 508 | cost = REGISTER_MOVE_COST (m, i, j); |
6836e024 JH |
509 | |
510 | for (p2 = ®_class_subclasses[j][0]; | |
511 | *p2 != LIM_REG_CLASSES; | |
512 | p2++) | |
513 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
514 | cost = MAX (cost, move_cost [m][i][*p2]); | |
515 | ||
516 | for (p1 = ®_class_subclasses[i][0]; | |
517 | *p1 != LIM_REG_CLASSES; | |
518 | p1++) | |
519 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
520 | cost = MAX (cost, move_cost [m][*p1][j]); | |
521 | ||
522 | move_cost[m][i][j] = cost; | |
523 | ||
524 | if (reg_class_subset_p (i, j)) | |
525 | may_move_in_cost[m][i][j] = 0; | |
526 | else | |
527 | may_move_in_cost[m][i][j] = cost; | |
528 | ||
529 | if (reg_class_subset_p (j, i)) | |
530 | may_move_out_cost[m][i][j] = 0; | |
531 | else | |
532 | may_move_out_cost[m][i][j] = cost; | |
533 | } | |
534 | } | |
1464632b | 535 | else |
6836e024 JH |
536 | for (j = 0; j < N_REG_CLASSES; j++) |
537 | { | |
538 | move_cost[m][i][j] = 65536; | |
539 | may_move_in_cost[m][i][j] = 65536; | |
540 | may_move_out_cost[m][i][j] = 65536; | |
541 | } | |
542 | } | |
c27c5281 DE |
543 | } |
544 | ||
545 | /* Compute the table of register modes. | |
546 | These values are used to record death information for individual registers | |
547 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 548 | |
c27c5281 | 549 | static void |
0c20a65f | 550 | init_reg_modes (void) |
c27c5281 | 551 | { |
b3694847 | 552 | int i; |
ca4aac00 DE |
553 | |
554 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 | 555 | { |
fee226d2 | 556 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); |
7f21d440 | 557 | |
066c2fea | 558 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
559 | ??? One situation in which we need to do this is on the mips where |
560 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
561 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 562 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 563 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 564 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 565 | } |
ca4aac00 DE |
566 | } |
567 | ||
c27c5281 DE |
568 | /* Finish initializing the register sets and |
569 | initialize the register modes. */ | |
570 | ||
571 | void | |
0c20a65f | 572 | init_regs (void) |
c27c5281 DE |
573 | { |
574 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
575 | until after register usage was specified. */ | |
b93a436e | 576 | init_reg_sets_1 (); |
c27c5281 DE |
577 | |
578 | init_reg_modes (); | |
1f80c9ef MS |
579 | |
580 | init_reg_autoinc (); | |
6cde4876 JL |
581 | } |
582 | ||
583 | /* Initialize some fake stack-frame MEM references for use in | |
584 | memory_move_secondary_cost. */ | |
473fe49b | 585 | |
6cde4876 | 586 | void |
0c20a65f | 587 | init_fake_stack_mems (void) |
6cde4876 | 588 | { |
473fe49b KR |
589 | #ifdef HAVE_SECONDARY_RELOADS |
590 | { | |
473fe49b | 591 | int i; |
d067e2aa | 592 | |
473fe49b | 593 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 594 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
595 | } |
596 | #endif | |
c27c5281 DE |
597 | } |
598 | ||
cbd5b9a2 | 599 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 600 | |
cbd5b9a2 KR |
601 | /* Compute extra cost of moving registers to/from memory due to reloads. |
602 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 603 | |
cbd5b9a2 | 604 | int |
0c20a65f | 605 | memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in) |
cbd5b9a2 KR |
606 | { |
607 | enum reg_class altclass; | |
608 | int partial_cost = 0; | |
cbd5b9a2 | 609 | /* We need a memory reference to feed to SECONDARY... macros. */ |
dc297297 | 610 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
272df862 KG |
611 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
612 | ||
cbd5b9a2 KR |
613 | |
614 | if (in) | |
473fe49b | 615 | { |
321c0828 | 616 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 617 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 618 | #else |
473fe49b | 619 | altclass = NO_REGS; |
321c0828 | 620 | #endif |
473fe49b | 621 | } |
cbd5b9a2 | 622 | else |
473fe49b | 623 | { |
321c0828 | 624 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 625 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 626 | #else |
473fe49b | 627 | altclass = NO_REGS; |
321c0828 | 628 | #endif |
473fe49b KR |
629 | } |
630 | ||
cbd5b9a2 KR |
631 | if (altclass == NO_REGS) |
632 | return 0; | |
633 | ||
634 | if (in) | |
e56b4594 | 635 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 636 | else |
e56b4594 | 637 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
638 | |
639 | if (class == altclass) | |
640 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
641 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
642 | here in that case. | |
643 | ||
644 | I'm tempted to put in an abort here, but returning this will | |
645 | probably only give poor estimates, which is what we would've | |
646 | had before this code anyways. */ | |
647 | return partial_cost; | |
648 | ||
649 | /* Check if the secondary reload register will also need a | |
650 | secondary reload. */ | |
651 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
652 | } | |
653 | #endif | |
654 | ||
ca4aac00 | 655 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
fee226d2 R |
656 | enough to save nregs. If we can't find one, return VOIDmode. |
657 | If CALL_SAVED is true, only consider modes that are call saved. */ | |
ca4aac00 DE |
658 | |
659 | enum machine_mode | |
0c20a65f | 660 | choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, |
fee226d2 | 661 | unsigned int nregs, bool call_saved) |
ca4aac00 | 662 | { |
dbbbbf3b | 663 | unsigned int /* enum machine_mode */ m; |
ca4aac00 DE |
664 | enum machine_mode found_mode = VOIDmode, mode; |
665 | ||
666 | /* We first look for the largest integer mode that can be validly | |
667 | held in REGNO. If none, we look for the largest floating-point mode. | |
668 | If we still didn't find a valid mode, try CCmode. */ | |
669 | ||
670 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
671 | mode != VOIDmode; | |
672 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 673 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
fee226d2 R |
674 | && HARD_REGNO_MODE_OK (regno, mode) |
675 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
ca4aac00 DE |
676 | found_mode = mode; |
677 | ||
678 | if (found_mode != VOIDmode) | |
679 | return found_mode; | |
680 | ||
681 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
682 | mode != VOIDmode; | |
683 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 684 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
fee226d2 R |
685 | && HARD_REGNO_MODE_OK (regno, mode) |
686 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
ca4aac00 DE |
687 | found_mode = mode; |
688 | ||
689 | if (found_mode != VOIDmode) | |
690 | return found_mode; | |
691 | ||
78b583fe AH |
692 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
693 | mode != VOIDmode; | |
694 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 695 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
fee226d2 R |
696 | && HARD_REGNO_MODE_OK (regno, mode) |
697 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
78b583fe AH |
698 | found_mode = mode; |
699 | ||
700 | if (found_mode != VOIDmode) | |
701 | return found_mode; | |
702 | ||
703 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
704 | mode != VOIDmode; | |
705 | mode = GET_MODE_WIDER_MODE (mode)) | |
f7043461 | 706 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
fee226d2 R |
707 | && HARD_REGNO_MODE_OK (regno, mode) |
708 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
78b583fe AH |
709 | found_mode = mode; |
710 | ||
711 | if (found_mode != VOIDmode) | |
712 | return found_mode; | |
713 | ||
0548a9df | 714 | /* Iterate over all of the CCmodes. */ |
dbbbbf3b JDA |
715 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
716 | { | |
717 | mode = (enum machine_mode) m; | |
f7043461 | 718 | if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs |
fee226d2 R |
719 | && HARD_REGNO_MODE_OK (regno, mode) |
720 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
dbbbbf3b JDA |
721 | return mode; |
722 | } | |
ca4aac00 DE |
723 | |
724 | /* We can't find a mode valid for this register. */ | |
725 | return VOIDmode; | |
54dac99e RK |
726 | } |
727 | ||
728 | /* Specify the usage characteristics of the register named NAME. | |
729 | It should be a fixed register if FIXED and a | |
730 | call-used register if CALL_USED. */ | |
731 | ||
732 | void | |
0c20a65f | 733 | fix_register (const char *name, int fixed, int call_used) |
54dac99e RK |
734 | { |
735 | int i; | |
736 | ||
737 | /* Decode the name and update the primary form of | |
738 | the register info. */ | |
739 | ||
e5c90c23 TW |
740 | if ((i = decode_reg_name (name)) >= 0) |
741 | { | |
cb2fdc84 GRK |
742 | if ((i == STACK_POINTER_REGNUM |
743 | #ifdef HARD_FRAME_POINTER_REGNUM | |
744 | || i == HARD_FRAME_POINTER_REGNUM | |
745 | #else | |
746 | || i == FRAME_POINTER_REGNUM | |
747 | #endif | |
748 | ) | |
749 | && (fixed == 0 || call_used == 0)) | |
750 | { | |
6f7d635c | 751 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
752 | { "call-saved", "call-used" }, |
753 | { "no-such-option", "fixed" }}; | |
a6a2274a KH |
754 | |
755 | error ("can't use '%s' as a %s register", name, | |
cb2fdc84 GRK |
756 | what_option[fixed][call_used]); |
757 | } | |
758 | else | |
759 | { | |
760 | fixed_regs[i] = fixed; | |
761 | call_used_regs[i] = call_used; | |
ec523c2f | 762 | #ifdef CALL_REALLY_USED_REGISTERS |
fc1296b7 AM |
763 | if (fixed == 0) |
764 | call_really_used_regs[i] = call_used; | |
d3259baa | 765 | #endif |
cb2fdc84 | 766 | } |
e5c90c23 TW |
767 | } |
768 | else | |
54dac99e RK |
769 | { |
770 | warning ("unknown register name: %s", name); | |
54dac99e RK |
771 | } |
772 | } | |
614f68e2 RK |
773 | |
774 | /* Mark register number I as global. */ | |
775 | ||
776 | void | |
0c20a65f | 777 | globalize_reg (int i) |
614f68e2 | 778 | { |
c07c7c9d | 779 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
780 | error ("global register variable follows a function definition"); |
781 | ||
614f68e2 RK |
782 | if (global_regs[i]) |
783 | { | |
784 | warning ("register used for two global register variables"); | |
785 | return; | |
786 | } | |
787 | ||
788 | if (call_used_regs[i] && ! fixed_regs[i]) | |
789 | warning ("call-clobbered register used for global register variable"); | |
790 | ||
791 | global_regs[i] = 1; | |
792 | ||
793 | /* If already fixed, nothing else to do. */ | |
794 | if (fixed_regs[i]) | |
795 | return; | |
796 | ||
797 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
798 | n_non_fixed_regs--; | |
799 | ||
800 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
801 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
802 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
caecc099 | 803 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
614f68e2 | 804 | } |
54dac99e RK |
805 | \f |
806 | /* Now the data and code for the `regclass' pass, which happens | |
807 | just before local-alloc. */ | |
808 | ||
e4600702 RK |
809 | /* The `costs' struct records the cost of using a hard register of each class |
810 | and of using memory for each pseudo. We use this data to set up | |
811 | register class preferences. */ | |
54dac99e | 812 | |
e4600702 | 813 | struct costs |
54dac99e | 814 | { |
e4600702 RK |
815 | int cost[N_REG_CLASSES]; |
816 | int mem_cost; | |
54dac99e RK |
817 | }; |
818 | ||
d55d8fc7 | 819 | /* Structure used to record preferences of given pseudo. */ |
9ffc5a70 JH |
820 | struct reg_pref |
821 | { | |
822 | /* (enum reg_class) prefclass is the preferred class. */ | |
823 | char prefclass; | |
824 | ||
825 | /* altclass is a register class that we should use for allocating | |
826 | pseudo if no register in the preferred class is available. | |
827 | If no register in this class is available, memory is preferred. | |
828 | ||
829 | It might appear to be more general to have a bitmask of classes here, | |
830 | but since it is recommended that there be a class corresponding to the | |
831 | union of most major pair of classes, that generality is not required. */ | |
832 | char altclass; | |
833 | }; | |
834 | ||
e4600702 RK |
835 | /* Record the cost of each class for each pseudo. */ |
836 | ||
837 | static struct costs *costs; | |
838 | ||
61719ba7 BS |
839 | /* Initialized once, and used to initialize cost values for each insn. */ |
840 | ||
841 | static struct costs init_cost; | |
842 | ||
d55d8fc7 | 843 | /* Record preferences of each pseudo. |
54dac99e RK |
844 | This is available after `regclass' is run. */ |
845 | ||
9ffc5a70 | 846 | static struct reg_pref *reg_pref; |
54d23420 | 847 | |
dc297297 | 848 | /* Allocated buffers for reg_pref. */ |
54dac99e | 849 | |
9ffc5a70 | 850 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 851 | |
9401afe3 | 852 | /* Frequency of executions of current insn. */ |
54d23420 | 853 | |
9401afe3 | 854 | static int frequency; |
54d23420 | 855 | |
0c20a65f AJ |
856 | static rtx scan_one_insn (rtx, int); |
857 | static void record_operand_costs (rtx, struct costs *, struct reg_pref *); | |
858 | static void dump_regclass (FILE *); | |
859 | static void record_reg_classes (int, int, rtx *, enum machine_mode *, | |
860 | const char **, rtx, struct costs *, | |
861 | struct reg_pref *); | |
862 | static int copy_cost (rtx, enum machine_mode, enum reg_class, int); | |
863 | static void record_address_regs (rtx, enum reg_class, int); | |
1d300e19 | 864 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
0c20a65f | 865 | static int auto_inc_dec_reg_p (rtx, enum machine_mode); |
1d300e19 | 866 | #endif |
0c20a65f | 867 | static void reg_scan_mark_refs (rtx, rtx, int, unsigned int); |
54dac99e RK |
868 | |
869 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
870 | This function is sometimes called before the info has been computed. | |
871 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
872 | ||
873 | enum reg_class | |
0c20a65f | 874 | reg_preferred_class (int regno) |
54dac99e | 875 | { |
9ffc5a70 | 876 | if (reg_pref == 0) |
54dac99e | 877 | return GENERAL_REGS; |
9ffc5a70 | 878 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
879 | } |
880 | ||
e4600702 | 881 | enum reg_class |
0c20a65f | 882 | reg_alternate_class (int regno) |
54dac99e | 883 | { |
9ffc5a70 | 884 | if (reg_pref == 0) |
e4600702 RK |
885 | return ALL_REGS; |
886 | ||
9ffc5a70 | 887 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
888 | } |
889 | ||
61719ba7 | 890 | /* Initialize some global data for this pass. */ |
54dac99e RK |
891 | |
892 | void | |
0c20a65f | 893 | regclass_init (void) |
54dac99e | 894 | { |
61719ba7 BS |
895 | int i; |
896 | ||
897 | init_cost.mem_cost = 10000; | |
898 | for (i = 0; i < N_REG_CLASSES; i++) | |
899 | init_cost.cost[i] = 10000; | |
900 | ||
901 | /* This prevents dump_flow_info from losing if called | |
902 | before regclass is run. */ | |
9ffc5a70 | 903 | reg_pref = NULL; |
6c85df69 | 904 | |
dc297297 | 905 | /* No more global register variables may be declared. */ |
6c85df69 | 906 | no_global_reg_vars = 1; |
54dac99e | 907 | } |
246fd41f JH |
908 | \f |
909 | /* Dump register costs. */ | |
915b80ed | 910 | static void |
0c20a65f | 911 | dump_regclass (FILE *dump) |
246fd41f JH |
912 | { |
913 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
914 | int i; | |
915 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
916 | { | |
dbbbbf3b | 917 | int /* enum reg_class */ class; |
246fd41f JH |
918 | if (REG_N_REFS (i)) |
919 | { | |
f741a71c | 920 | fprintf (dump, " Register %i costs:", i); |
dbbbbf3b JDA |
921 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
922 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
6df26b8f | 923 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
dbbbbf3b JDA |
924 | && (!in_inc_dec[i] |
925 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
6df26b8f | 926 | #endif |
cff9f8d5 AH |
927 | #ifdef CANNOT_CHANGE_MODE_CLASS |
928 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
929 | PSEUDO_REGNO_MODE (i)) | |
6df26b8f JH |
930 | #endif |
931 | ) | |
dbbbbf3b JDA |
932 | fprintf (dump, " %s:%i", reg_class_names[class], |
933 | costs[i].cost[(enum reg_class) class]); | |
f741a71c | 934 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
935 | } |
936 | } | |
937 | } | |
f741a71c JH |
938 | \f |
939 | ||
940 | /* Calculate the costs of insn operands. */ | |
941 | ||
942 | static void | |
0c20a65f AJ |
943 | record_operand_costs (rtx insn, struct costs *op_costs, |
944 | struct reg_pref *reg_pref) | |
f741a71c JH |
945 | { |
946 | const char *constraints[MAX_RECOG_OPERANDS]; | |
947 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
948 | int i; |
949 | ||
950 | for (i = 0; i < recog_data.n_operands; i++) | |
951 | { | |
952 | constraints[i] = recog_data.constraints[i]; | |
953 | modes[i] = recog_data.operand_mode[i]; | |
954 | } | |
f741a71c JH |
955 | |
956 | /* If we get here, we are set up to record the costs of all the | |
957 | operands for this insn. Start by initializing the costs. | |
958 | Then handle any address registers. Finally record the desired | |
959 | classes for any pseudos, doing it twice if some pair of | |
960 | operands are commutative. */ | |
a6a2274a | 961 | |
f741a71c JH |
962 | for (i = 0; i < recog_data.n_operands; i++) |
963 | { | |
964 | op_costs[i] = init_cost; | |
965 | ||
966 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
cff9f8d5 | 967 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
f741a71c JH |
968 | |
969 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
970 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
3dcc68a4 | 971 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
ccfc6cc8 | 972 | else if (constraints[i][0] == 'p' |
97488870 | 973 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
f741a71c | 974 | record_address_regs (recog_data.operand[i], |
3dcc68a4 | 975 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
f741a71c JH |
976 | } |
977 | ||
978 | /* Check for commutative in a separate loop so everything will | |
979 | have been initialized. We must do this even if one operand | |
980 | is a constant--see addsi3 in m68k.md. */ | |
981 | ||
982 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
983 | if (constraints[i][0] == '%') | |
984 | { | |
985 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
986 | int j; | |
246fd41f | 987 | |
f741a71c JH |
988 | /* Handle commutative operands by swapping the constraints. |
989 | We assume the modes are the same. */ | |
990 | ||
991 | for (j = 0; j < recog_data.n_operands; j++) | |
992 | xconstraints[j] = constraints[j]; | |
993 | ||
994 | xconstraints[i] = constraints[i+1]; | |
995 | xconstraints[i+1] = constraints[i]; | |
996 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 997 | recog_data.operand, modes, |
f741a71c JH |
998 | xconstraints, insn, op_costs, reg_pref); |
999 | } | |
1000 | ||
1001 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1002 | recog_data.operand, modes, |
f741a71c JH |
1003 | constraints, insn, op_costs, reg_pref); |
1004 | } | |
54dac99e | 1005 | \f |
61719ba7 BS |
1006 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1007 | time it would save code to put a certain register in a certain class. | |
1008 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1009 | once. | |
1010 | Return the last insn processed, so that the scan can be continued from | |
1011 | there. */ | |
1012 | ||
1013 | static rtx | |
0c20a65f | 1014 | scan_one_insn (rtx insn, int pass) |
61719ba7 BS |
1015 | { |
1016 | enum rtx_code code = GET_CODE (insn); | |
1017 | enum rtx_code pat_code; | |
0eadeb15 | 1018 | rtx set, note; |
61719ba7 | 1019 | int i, j; |
f741a71c | 1020 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 1021 | |
61719ba7 BS |
1022 | if (GET_RTX_CLASS (code) != 'i') |
1023 | return insn; | |
1024 | ||
1025 | pat_code = GET_CODE (PATTERN (insn)); | |
1026 | if (pat_code == USE | |
1027 | || pat_code == CLOBBER | |
1028 | || pat_code == ASM_INPUT | |
1029 | || pat_code == ADDR_VEC | |
1030 | || pat_code == ADDR_DIFF_VEC) | |
1031 | return insn; | |
1032 | ||
0eadeb15 BS |
1033 | set = single_set (insn); |
1034 | extract_insn (insn); | |
1035 | ||
0eadeb15 BS |
1036 | /* If this insn loads a parameter from its stack slot, then |
1037 | it represents a savings, rather than a cost, if the | |
1038 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 1039 | |
0eadeb15 BS |
1040 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
1041 | && GET_CODE (SET_SRC (set)) == MEM | |
1042 | && (note = find_reg_note (insn, REG_EQUIV, | |
1043 | NULL_RTX)) != 0 | |
1044 | && GET_CODE (XEXP (note, 0)) == MEM) | |
1045 | { | |
1046 | costs[REGNO (SET_DEST (set))].mem_cost | |
1047 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1048 | GENERAL_REGS, 1) | |
9401afe3 | 1049 | * frequency); |
0eadeb15 | 1050 | record_address_regs (XEXP (SET_SRC (set), 0), |
3dcc68a4 | 1051 | MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); |
0eadeb15 BS |
1052 | return insn; |
1053 | } | |
61719ba7 | 1054 | |
0eadeb15 BS |
1055 | /* Improve handling of two-address insns such as |
1056 | (set X (ashift CONST Y)) where CONST must be made to | |
1057 | match X. Change it into two insns: (set X CONST) | |
1058 | (set X (ashift X Y)). If we left this for reloading, it | |
1059 | would probably get three insns because X and Y might go | |
1060 | in the same place. This prevents X and Y from receiving | |
1061 | the same hard reg. | |
1062 | ||
1063 | We can only do this if the modes of operands 0 and 1 | |
1064 | (which might not be the same) are tieable and we only need | |
1065 | do this during our first pass. */ | |
1066 | ||
1067 | if (pass == 0 && optimize | |
1ccbefce RH |
1068 | && recog_data.n_operands >= 3 |
1069 | && recog_data.constraints[1][0] == '0' | |
1070 | && recog_data.constraints[1][1] == 0 | |
1071 | && CONSTANT_P (recog_data.operand[1]) | |
1072 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1073 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
1074 | && GET_CODE (recog_data.operand[0]) == REG | |
1075 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
1076 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
1077 | { |
1078 | rtx previnsn = prev_real_insn (insn); | |
1079 | rtx dest | |
1ccbefce RH |
1080 | = gen_lowpart (recog_data.operand_mode[1], |
1081 | recog_data.operand[0]); | |
0eadeb15 | 1082 | rtx newinsn |
1ccbefce | 1083 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 1084 | |
0eadeb15 BS |
1085 | /* If this insn was the start of a basic block, |
1086 | include the new insn in that block. | |
1087 | We need not check for code_label here; | |
1088 | while a basic block can start with a code_label, | |
1089 | INSN could not be at the beginning of that block. */ | |
1090 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 1091 | { |
e0082a72 ZD |
1092 | basic_block b; |
1093 | FOR_EACH_BB (b) | |
1094 | if (insn == b->head) | |
1095 | b->head = newinsn; | |
61719ba7 BS |
1096 | } |
1097 | ||
0eadeb15 | 1098 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1099 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d3c7d45e | 1100 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1101 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
61719ba7 | 1102 | |
1ccbefce | 1103 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d3c7d45e | 1104 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1105 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
1ccbefce RH |
1106 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1107 | if (recog_data.dup_num[i] == 1) | |
d3c7d45e AO |
1108 | { |
1109 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1110 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
9401afe3 | 1111 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d3c7d45e | 1112 | } |
61719ba7 | 1113 | |
0eadeb15 | 1114 | return PREV_INSN (newinsn); |
61719ba7 BS |
1115 | } |
1116 | ||
4963c995 | 1117 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1118 | |
1119 | /* Now add the cost for each operand to the total costs for | |
1120 | its register. */ | |
1121 | ||
1ccbefce RH |
1122 | for (i = 0; i < recog_data.n_operands; i++) |
1123 | if (GET_CODE (recog_data.operand[i]) == REG | |
1124 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 1125 | { |
1ccbefce | 1126 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1127 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1128 | ||
9401afe3 | 1129 | p->mem_cost += q->mem_cost * frequency; |
61719ba7 | 1130 | for (j = 0; j < N_REG_CLASSES; j++) |
9401afe3 | 1131 | p->cost[j] += q->cost[j] * frequency; |
61719ba7 BS |
1132 | } |
1133 | ||
1134 | return insn; | |
1135 | } | |
1136 | ||
1f80c9ef MS |
1137 | /* Initialize information about which register classes can be used for |
1138 | pseudos that are auto-incremented or auto-decremented. */ | |
54dac99e | 1139 | |
1f80c9ef | 1140 | static void |
0c20a65f | 1141 | init_reg_autoinc (void) |
54dac99e | 1142 | { |
533d0835 | 1143 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1f80c9ef | 1144 | int i; |
533d0835 RK |
1145 | |
1146 | for (i = 0; i < N_REG_CLASSES; i++) | |
1147 | { | |
1f80c9ef | 1148 | rtx r = gen_rtx_raw_REG (VOIDmode, 0); |
533d0835 | 1149 | enum machine_mode m; |
b3694847 | 1150 | int j; |
533d0835 RK |
1151 | |
1152 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1153 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1154 | { | |
1155 | REGNO (r) = j; | |
1156 | ||
1157 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1158 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1159 | if (HARD_REGNO_MODE_OK (j, m)) |
1160 | { | |
1161 | PUT_MODE (r, m); | |
08d95f91 RK |
1162 | |
1163 | /* If a register is not directly suitable for an | |
1164 | auto-increment or decrement addressing mode and | |
1165 | requires secondary reloads, disallow its class from | |
1166 | being used in such addresses. */ | |
1167 | ||
1168 | if ((0 | |
041d7180 | 1169 | #ifdef SECONDARY_RELOAD_CLASS |
3dcc68a4 | 1170 | || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
041d7180 JL |
1171 | != NO_REGS) |
1172 | #else | |
533d0835 | 1173 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
3dcc68a4 | 1174 | || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1175 | != NO_REGS) |
533d0835 RK |
1176 | #endif |
1177 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
3dcc68a4 | 1178 | || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1179 | != NO_REGS) |
041d7180 | 1180 | #endif |
533d0835 | 1181 | #endif |
08d95f91 RK |
1182 | ) |
1183 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1184 | forbidden_inc_dec_class[i] = 1; |
1185 | } | |
1186 | } | |
1187 | } | |
1f80c9ef MS |
1188 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1189 | } | |
1190 | ||
1191 | /* This is a pass of the compiler that scans all instructions | |
1192 | and calculates the preferred class for each pseudo-register. | |
1193 | This information can be accessed later by calling `reg_preferred_class'. | |
1194 | This pass comes just before local register allocation. */ | |
1195 | ||
1196 | void | |
0c20a65f | 1197 | regclass (rtx f, int nregs, FILE *dump) |
1f80c9ef MS |
1198 | { |
1199 | rtx insn; | |
1200 | int i; | |
1201 | int pass; | |
1202 | ||
1203 | init_recog (); | |
1204 | ||
703ad42b | 1205 | costs = xmalloc (nregs * sizeof (struct costs)); |
1f80c9ef MS |
1206 | |
1207 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1208 | ||
703ad42b | 1209 | in_inc_dec = xmalloc (nregs); |
1f80c9ef | 1210 | |
533d0835 RK |
1211 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1212 | ||
e4600702 RK |
1213 | /* Normally we scan the insns once and determine the best class to use for |
1214 | each register. However, if -fexpensive_optimizations are on, we do so | |
1215 | twice, the second time using the tentative best classes to guide the | |
1216 | selection. */ | |
54dac99e | 1217 | |
e4600702 RK |
1218 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1219 | { | |
e0082a72 | 1220 | basic_block bb; |
f741a71c JH |
1221 | |
1222 | if (dump) | |
a6a2274a | 1223 | fprintf (dump, "\n\nPass %i\n\n",pass); |
e4600702 | 1224 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1225 | |
703ad42b | 1226 | memset (costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1227 | |
533d0835 | 1228 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1229 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1230 | #endif |
1231 | ||
e4600702 RK |
1232 | /* Scan the instructions and record each time it would |
1233 | save code to put a certain register in a certain class. */ | |
1234 | ||
1f01879e | 1235 | if (!optimize) |
54dac99e | 1236 | { |
a08b2604 | 1237 | frequency = REG_FREQ_MAX; |
1f01879e JH |
1238 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1239 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1240 | } |
1f01879e | 1241 | else |
e0082a72 | 1242 | FOR_EACH_BB (bb) |
1f01879e | 1243 | { |
1f01879e | 1244 | /* Show that an insn inside a loop is likely to be executed three |
9b15c17f RH |
1245 | times more than insns outside a loop. This is much more |
1246 | aggressive than the assumptions made elsewhere and is being | |
1247 | tried as an experiment. */ | |
a08b2604 | 1248 | frequency = REG_FREQ_FROM_BB (bb); |
1f01879e JH |
1249 | for (insn = bb->head; ; insn = NEXT_INSN (insn)) |
1250 | { | |
1251 | insn = scan_one_insn (insn, pass); | |
1252 | if (insn == bb->end) | |
1253 | break; | |
1254 | } | |
1255 | } | |
a6a2274a | 1256 | |
e4600702 RK |
1257 | /* Now for each register look at how desirable each class is |
1258 | and find which class is preferred. Store that in | |
9ffc5a70 | 1259 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1260 | class any of whose registers is better than memory. */ |
a6a2274a | 1261 | |
e4600702 | 1262 | if (pass == 0) |
9ffc5a70 | 1263 | reg_pref = reg_pref_buffer; |
54dac99e | 1264 | |
f741a71c | 1265 | if (dump) |
a6a2274a | 1266 | { |
f741a71c | 1267 | dump_regclass (dump); |
4963c995 | 1268 | fprintf (dump,"\n"); |
f741a71c | 1269 | } |
e4600702 | 1270 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1271 | { |
b3694847 | 1272 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1273 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1274 | /* This is an enum reg_class, but we call it an int | |
1275 | to save lots of casts. */ | |
b3694847 SS |
1276 | int class; |
1277 | struct costs *p = &costs[i]; | |
e4600702 | 1278 | |
64615302 JH |
1279 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1280 | yet. */ | |
ed8d2920 | 1281 | if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) |
f741a71c JH |
1282 | continue; |
1283 | ||
e4600702 | 1284 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1285 | { |
533d0835 | 1286 | /* Ignore classes that are too small for this operand or |
4fe9b91c | 1287 | invalid for an operand that was auto-incremented. */ |
6df26b8f | 1288 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
533d0835 RK |
1289 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1290 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1291 | #endif |
cff9f8d5 AH |
1292 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1293 | || invalid_mode_change_p (i, (enum reg_class) class, | |
1294 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1295 | #endif |
1296 | ) | |
e4600702 RK |
1297 | ; |
1298 | else if (p->cost[class] < best_cost) | |
1299 | { | |
1300 | best_cost = p->cost[class]; | |
1301 | best = (enum reg_class) class; | |
1302 | } | |
1303 | else if (p->cost[class] == best_cost) | |
8e2e89f7 | 1304 | best = reg_class_subunion[(int) best][class]; |
54dac99e | 1305 | } |
54dac99e | 1306 | |
e4600702 RK |
1307 | /* Record the alternate register class; i.e., a class for which |
1308 | every register in it is better than using memory. If adding a | |
1309 | class would make a smaller class (i.e., no union of just those | |
1310 | classes exists), skip that class. The major unions of classes | |
1311 | should be provided as a register class. Don't do this if we | |
1312 | will be doing it again later. */ | |
1313 | ||
f741a71c | 1314 | if ((pass == 1 || dump) || ! flag_expensive_optimizations) |
e4600702 RK |
1315 | for (class = 0; class < N_REG_CLASSES; class++) |
1316 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1317 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1318 | > reg_class_size[(int) alt]) |
1319 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1320 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1321 | #endif |
cff9f8d5 AH |
1322 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1323 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
1324 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1325 | #endif |
1326 | ) | |
e4600702 | 1327 | alt = reg_class_subunion[(int) alt][class]; |
a6a2274a | 1328 | |
e4600702 RK |
1329 | /* If we don't add any classes, nothing to try. */ |
1330 | if (alt == best) | |
995d54dd | 1331 | alt = NO_REGS; |
e4600702 | 1332 | |
a6a2274a | 1333 | if (dump |
f741a71c JH |
1334 | && (reg_pref[i].prefclass != (int) best |
1335 | || reg_pref[i].altclass != (int) alt)) | |
1336 | { | |
1337 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
4963c995 | 1338 | fprintf (dump, " Register %i", i); |
f741a71c JH |
1339 | if (alt == ALL_REGS || best == ALL_REGS) |
1340 | fprintf (dump, " pref %s\n", reg_class_names[(int) best]); | |
1341 | else if (alt == NO_REGS) | |
1342 | fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); | |
1343 | else | |
1344 | fprintf (dump, " pref %s, else %s\n", | |
1345 | reg_class_names[(int) best], | |
1346 | reg_class_names[(int) alt]); | |
1347 | } | |
1348 | ||
e4600702 | 1349 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1350 | reg_pref[i].prefclass = (int) best; |
1351 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1352 | } |
54dac99e | 1353 | } |
56a65848 | 1354 | |
4da896b2 MM |
1355 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1356 | free (in_inc_dec); | |
1357 | #endif | |
56a65848 | 1358 | free (costs); |
54dac99e RK |
1359 | } |
1360 | \f | |
e4600702 RK |
1361 | /* Record the cost of using memory or registers of various classes for |
1362 | the operands in INSN. | |
54dac99e | 1363 | |
e4600702 | 1364 | N_ALTS is the number of alternatives. |
54dac99e | 1365 | |
e4600702 RK |
1366 | N_OPS is the number of operands. |
1367 | ||
1368 | OPS is an array of the operands. | |
1369 | ||
1370 | MODES are the modes of the operands, in case any are VOIDmode. | |
1371 | ||
1372 | CONSTRAINTS are the constraints to use for the operands. This array | |
1373 | is modified by this procedure. | |
1374 | ||
1375 | This procedure works alternative by alternative. For each alternative | |
1376 | we assume that we will be able to allocate all pseudos to their ideal | |
1377 | register class and calculate the cost of using that alternative. Then | |
a6a2274a | 1378 | we compute for each operand that is a pseudo-register, the cost of |
e4600702 RK |
1379 | having the pseudo allocated to each register class and using it in that |
1380 | alternative. To this cost is added the cost of the alternative. | |
1381 | ||
1382 | The cost of each class for this insn is its lowest cost among all the | |
1383 | alternatives. */ | |
1384 | ||
1385 | static void | |
0c20a65f AJ |
1386 | record_reg_classes (int n_alts, int n_ops, rtx *ops, |
1387 | enum machine_mode *modes, const char **constraints, | |
1388 | rtx insn, struct costs *op_costs, | |
1389 | struct reg_pref *reg_pref) | |
54dac99e | 1390 | { |
e4600702 | 1391 | int alt; |
e4600702 | 1392 | int i, j; |
ec2d92af | 1393 | rtx set; |
e4600702 | 1394 | |
e4600702 RK |
1395 | /* Process each alternative, each time minimizing an operand's cost with |
1396 | the cost for each operand in that alternative. */ | |
54dac99e | 1397 | |
e4600702 | 1398 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1399 | { |
e4600702 RK |
1400 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1401 | int alt_fail = 0; | |
1402 | int alt_cost = 0; | |
1403 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1404 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1405 | int class; |
54dac99e | 1406 | |
e4600702 RK |
1407 | for (i = 0; i < n_ops; i++) |
1408 | { | |
9b3142b3 | 1409 | const char *p = constraints[i]; |
e4600702 RK |
1410 | rtx op = ops[i]; |
1411 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1412 | int allows_addr = 0; |
e4600702 | 1413 | int win = 0; |
e51712db | 1414 | unsigned char c; |
54dac99e | 1415 | |
7405d9a1 DE |
1416 | /* Initially show we know nothing about the register class. */ |
1417 | classes[i] = NO_REGS; | |
da2c0219 | 1418 | allows_mem[i] = 0; |
7405d9a1 | 1419 | |
a6a2274a | 1420 | /* If this operand has no constraints at all, we can conclude |
e4600702 | 1421 | nothing about it since anything is valid. */ |
54dac99e | 1422 | |
e4600702 RK |
1423 | if (*p == 0) |
1424 | { | |
1425 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
703ad42b | 1426 | memset (&this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1427 | |
e4600702 RK |
1428 | continue; |
1429 | } | |
54dac99e | 1430 | |
7405d9a1 DE |
1431 | /* If this alternative is only relevant when this operand |
1432 | matches a previous operand, we do different things depending | |
1433 | on whether this operand is a pseudo-reg or not. We must process | |
1434 | any modifiers for the operand before we can make this test. */ | |
1435 | ||
8c368ee2 | 1436 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1437 | p++; |
8c368ee2 | 1438 | |
e4600702 RK |
1439 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1440 | { | |
da2c0219 RK |
1441 | /* Copy class and whether memory is allowed from the matching |
1442 | alternative. Then perform any needed cost computations | |
1443 | and/or adjustments. */ | |
e4600702 RK |
1444 | j = p[0] - '0'; |
1445 | classes[i] = classes[j]; | |
da2c0219 | 1446 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1447 | |
1448 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1449 | { | |
1450 | /* If this matches the other operand, we have no added | |
dc903608 | 1451 | cost and we win. */ |
e4600702 | 1452 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1453 | win = 1; |
e4600702 | 1454 | |
77e67eac RK |
1455 | /* If we can put the other operand into a register, add to |
1456 | the cost of this alternative the cost to copy this | |
1457 | operand to the register used for the other operand. */ | |
e4600702 | 1458 | |
dc903608 | 1459 | else if (classes[j] != NO_REGS) |
77e67eac | 1460 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1461 | } |
07d8ca2d RS |
1462 | else if (GET_CODE (ops[j]) != REG |
1463 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1464 | { | |
1465 | /* This op is a pseudo but the one it matches is not. */ | |
a6a2274a | 1466 | |
07d8ca2d RS |
1467 | /* If we can't put the other operand into a register, this |
1468 | alternative can't be used. */ | |
1469 | ||
1470 | if (classes[j] == NO_REGS) | |
1471 | alt_fail = 1; | |
e4600702 | 1472 | |
07d8ca2d RS |
1473 | /* Otherwise, add to the cost of this alternative the cost |
1474 | to copy the other operand to the register used for this | |
1475 | operand. */ | |
1476 | ||
1477 | else | |
1478 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1479 | } | |
e4600702 RK |
1480 | else |
1481 | { | |
da2c0219 RK |
1482 | /* The costs of this operand are not the same as the other |
1483 | operand since move costs are not symmetric. Moreover, | |
1484 | if we cannot tie them, this alternative needs to do a | |
1485 | copy, which is one instruction. */ | |
1486 | ||
1487 | struct costs *pp = &this_op_costs[i]; | |
1488 | ||
1489 | for (class = 0; class < N_REG_CLASSES; class++) | |
1490 | pp->cost[class] | |
d5e2075d | 1491 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1492 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1493 | : 0) |
1494 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1495 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1496 | : 0)); |
a6a2274a | 1497 | |
da2c0219 RK |
1498 | /* If the alternative actually allows memory, make things |
1499 | a bit cheaper since we won't need an extra insn to | |
1500 | load it. */ | |
1501 | ||
1502 | pp->mem_cost | |
d5e2075d JH |
1503 | = ((recog_data.operand_type[i] != OP_IN |
1504 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1505 | : 0) | |
1506 | + (recog_data.operand_type[i] != OP_OUT | |
1507 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1508 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1509 | |
1510 | /* If we have assigned a class to this register in our | |
1511 | first pass, add a cost to this alternative corresponding | |
1512 | to what we would add if this register were not in the | |
1513 | appropriate class. */ | |
1514 | ||
9ffc5a70 | 1515 | if (reg_pref) |
da2c0219 | 1516 | alt_cost |
e56b4594 AO |
1517 | += (may_move_in_cost[mode] |
1518 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1519 | [(int) classes[i]]); |
e4600702 | 1520 | |
37747c82 RK |
1521 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1522 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1523 | alt_cost += 2; | |
e4600702 | 1524 | |
347099d6 | 1525 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1526 | for this operand, so skip to the end of the |
1527 | alternative (should be just one character). */ | |
1528 | while (*p && *p++ != ',') | |
1529 | ; | |
1530 | ||
1531 | constraints[i] = p; | |
347099d6 RS |
1532 | continue; |
1533 | } | |
e4600702 RK |
1534 | } |
1535 | ||
1536 | /* Scan all the constraint letters. See if the operand matches | |
1537 | any of the constraints. Collect the valid register classes | |
1538 | and see if this operand accepts memory. */ | |
1539 | ||
97488870 R |
1540 | while ((c = *p)) |
1541 | { | |
1542 | switch (c) | |
1543 | { | |
1544 | case ',': | |
1545 | break; | |
1546 | case '*': | |
1547 | /* Ignore the next letter for this pass. */ | |
1548 | c = *++p; | |
1549 | break; | |
94e6f783 | 1550 | |
97488870 R |
1551 | case '?': |
1552 | alt_cost += 2; | |
1553 | case '!': case '#': case '&': | |
1554 | case '0': case '1': case '2': case '3': case '4': | |
1555 | case '5': case '6': case '7': case '8': case '9': | |
1556 | break; | |
e4600702 | 1557 | |
97488870 R |
1558 | case 'p': |
1559 | allows_addr = 1; | |
1560 | win = address_operand (op, GET_MODE (op)); | |
1561 | /* We know this operand is an address, so we want it to be | |
1562 | allocated to a register that can be the base of an | |
1563 | address, ie BASE_REG_CLASS. */ | |
1564 | classes[i] | |
1565 | = reg_class_subunion[(int) classes[i]] | |
1566 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1567 | break; | |
e4600702 | 1568 | |
97488870 R |
1569 | case 'm': case 'o': case 'V': |
1570 | /* It doesn't seem worth distinguishing between offsettable | |
1571 | and non-offsettable addresses here. */ | |
1572 | allows_mem[i] = 1; | |
1573 | if (GET_CODE (op) == MEM) | |
1574 | win = 1; | |
1575 | break; | |
e4600702 | 1576 | |
97488870 R |
1577 | case '<': |
1578 | if (GET_CODE (op) == MEM | |
1579 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1580 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1581 | win = 1; | |
1582 | break; | |
e4600702 | 1583 | |
97488870 R |
1584 | case '>': |
1585 | if (GET_CODE (op) == MEM | |
1586 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1587 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1588 | win = 1; | |
1589 | break; | |
e4600702 | 1590 | |
97488870 R |
1591 | case 'E': |
1592 | case 'F': | |
1593 | if (GET_CODE (op) == CONST_DOUBLE | |
1594 | || (GET_CODE (op) == CONST_VECTOR | |
1595 | && (GET_MODE_CLASS (GET_MODE (op)) | |
1596 | == MODE_VECTOR_FLOAT))) | |
1597 | win = 1; | |
1598 | break; | |
e4600702 | 1599 | |
97488870 R |
1600 | case 'G': |
1601 | case 'H': | |
1602 | if (GET_CODE (op) == CONST_DOUBLE | |
1603 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
1604 | win = 1; | |
e4600702 | 1605 | break; |
97488870 R |
1606 | |
1607 | case 's': | |
1608 | if (GET_CODE (op) == CONST_INT | |
1609 | || (GET_CODE (op) == CONST_DOUBLE | |
1610 | && GET_MODE (op) == VOIDmode)) | |
1611 | break; | |
1612 | case 'i': | |
1613 | if (CONSTANT_P (op) | |
e4600702 | 1614 | #ifdef LEGITIMATE_PIC_OPERAND_P |
97488870 | 1615 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
e4600702 | 1616 | #endif |
97488870 R |
1617 | ) |
1618 | win = 1; | |
1619 | break; | |
e4600702 | 1620 | |
97488870 R |
1621 | case 'n': |
1622 | if (GET_CODE (op) == CONST_INT | |
1623 | || (GET_CODE (op) == CONST_DOUBLE | |
1624 | && GET_MODE (op) == VOIDmode)) | |
1625 | win = 1; | |
1626 | break; | |
e4600702 | 1627 | |
97488870 R |
1628 | case 'I': |
1629 | case 'J': | |
1630 | case 'K': | |
1631 | case 'L': | |
1632 | case 'M': | |
1633 | case 'N': | |
1634 | case 'O': | |
1635 | case 'P': | |
1636 | if (GET_CODE (op) == CONST_INT | |
1637 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1638 | win = 1; | |
1639 | break; | |
e4600702 | 1640 | |
97488870 R |
1641 | case 'X': |
1642 | win = 1; | |
1643 | break; | |
54dac99e | 1644 | |
97488870 R |
1645 | case 'g': |
1646 | if (GET_CODE (op) == MEM | |
1647 | || (CONSTANT_P (op) | |
e4600702 | 1648 | #ifdef LEGITIMATE_PIC_OPERAND_P |
97488870 | 1649 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
54dac99e | 1650 | #endif |
97488870 R |
1651 | )) |
1652 | win = 1; | |
1653 | allows_mem[i] = 1; | |
1654 | case 'r': | |
c2cba7a9 | 1655 | classes[i] |
97488870 R |
1656 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; |
1657 | break; | |
ccfc6cc8 | 1658 | |
97488870 R |
1659 | default: |
1660 | if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
ccfc6cc8 UW |
1661 | classes[i] |
1662 | = reg_class_subunion[(int) classes[i]] | |
97488870 R |
1663 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
1664 | #ifdef EXTRA_CONSTRAINT_STR | |
1665 | else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1666 | win = 1; | |
1667 | ||
1668 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1669 | { | |
1670 | /* Every MEM can be reloaded to fit. */ | |
1671 | allows_mem[i] = 1; | |
1672 | if (GET_CODE (op) == MEM) | |
1673 | win = 1; | |
1674 | } | |
1675 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1676 | { | |
1677 | /* Every address can be reloaded to fit. */ | |
1678 | allows_addr = 1; | |
1679 | if (address_operand (op, GET_MODE (op))) | |
1680 | win = 1; | |
1681 | /* We know this operand is an address, so we want it to | |
1682 | be allocated to a register that can be the base of an | |
1683 | address, ie BASE_REG_CLASS. */ | |
1684 | classes[i] | |
1685 | = reg_class_subunion[(int) classes[i]] | |
1686 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1687 | } | |
c2cba7a9 | 1688 | #endif |
97488870 R |
1689 | break; |
1690 | } | |
1691 | p += CONSTRAINT_LEN (c, p); | |
1692 | if (c == ',') | |
c2cba7a9 | 1693 | break; |
97488870 | 1694 | } |
e4600702 RK |
1695 | |
1696 | constraints[i] = p; | |
1697 | ||
1698 | /* How we account for this operand now depends on whether it is a | |
1699 | pseudo register or not. If it is, we first check if any | |
1700 | register classes are valid. If not, we ignore this alternative, | |
1701 | since we want to assume that all pseudos get allocated for | |
1702 | register preferencing. If some register class is valid, compute | |
1703 | the costs of moving the pseudo into that class. */ | |
1704 | ||
1705 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1706 | { |
e4600702 | 1707 | if (classes[i] == NO_REGS) |
94e6f783 | 1708 | { |
e79f71f7 GK |
1709 | /* We must always fail if the operand is a REG, but |
1710 | we did not find a suitable class. | |
a6a2274a | 1711 | |
e79f71f7 GK |
1712 | Otherwise we may perform an uninitialized read |
1713 | from this_op_costs after the `continue' statement | |
1714 | below. */ | |
1715 | alt_fail = 1; | |
94e6f783 | 1716 | } |
e4600702 RK |
1717 | else |
1718 | { | |
1719 | struct costs *pp = &this_op_costs[i]; | |
1720 | ||
1721 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1722 | pp->cost[class] |
d5e2075d | 1723 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1724 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1725 | : 0) |
1726 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1727 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1728 | : 0)); |
e4600702 RK |
1729 | |
1730 | /* If the alternative actually allows memory, make things | |
1731 | a bit cheaper since we won't need an extra insn to | |
1732 | load it. */ | |
1733 | ||
14a774a9 | 1734 | pp->mem_cost |
d5e2075d JH |
1735 | = ((recog_data.operand_type[i] != OP_IN |
1736 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1737 | : 0) | |
1738 | + (recog_data.operand_type[i] != OP_OUT | |
1739 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1740 | : 0) - allows_mem[i]); | |
e4600702 RK |
1741 | |
1742 | /* If we have assigned a class to this register in our | |
1743 | first pass, add a cost to this alternative corresponding | |
1744 | to what we would add if this register were not in the | |
1745 | appropriate class. */ | |
1746 | ||
9ffc5a70 | 1747 | if (reg_pref) |
e4600702 | 1748 | alt_cost |
e56b4594 AO |
1749 | += (may_move_in_cost[mode] |
1750 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1751 | [(int) classes[i]]); |
e4600702 | 1752 | } |
4db18574 | 1753 | } |
54dac99e | 1754 | |
e4600702 RK |
1755 | /* Otherwise, if this alternative wins, either because we |
1756 | have already determined that or if we have a hard register of | |
1757 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1758 | |
e4600702 RK |
1759 | else if (win |
1760 | || (GET_CODE (op) == REG | |
6f654776 | 1761 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1762 | ; |
54dac99e | 1763 | |
e4600702 RK |
1764 | /* If registers are valid, the cost of this alternative includes |
1765 | copying the object to and/or from a register. */ | |
54dac99e | 1766 | |
e4600702 RK |
1767 | else if (classes[i] != NO_REGS) |
1768 | { | |
1ccbefce | 1769 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1770 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1771 | |
1ccbefce | 1772 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1773 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1774 | } | |
54dac99e | 1775 | |
e4600702 RK |
1776 | /* The only other way this alternative can be used is if this is a |
1777 | constant that could be placed into memory. */ | |
1778 | ||
da2c0219 | 1779 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1780 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1781 | else |
1782 | alt_fail = 1; | |
1783 | } | |
1784 | ||
1785 | if (alt_fail) | |
1786 | continue; | |
1787 | ||
1788 | /* Finally, update the costs with the information we've calculated | |
1789 | about this alternative. */ | |
1790 | ||
1791 | for (i = 0; i < n_ops; i++) | |
1792 | if (GET_CODE (ops[i]) == REG | |
1793 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1794 | { |
e4600702 | 1795 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1796 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1797 | |
e4600702 RK |
1798 | pp->mem_cost = MIN (pp->mem_cost, |
1799 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1800 | |
e4600702 RK |
1801 | for (class = 0; class < N_REG_CLASSES; class++) |
1802 | pp->cost[class] = MIN (pp->cost[class], | |
1803 | (qq->cost[class] + alt_cost) * scale); | |
1804 | } | |
1805 | } | |
ec2d92af RK |
1806 | |
1807 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1808 | and one operand is a pseudo with the other a hard reg or a pseudo |
1809 | that prefers a register that is in its own register class then | |
1810 | we may want to adjust the cost of that register class to -1. | |
a6a2274a | 1811 | |
accef103 | 1812 | Avoid the adjustment if the source does not die to avoid stressing of |
4d6922ee | 1813 | register allocator by preferrencing two colliding registers into single |
accef103 JL |
1814 | class. |
1815 | ||
1816 | Also avoid the adjustment if a copy between registers of the class | |
1817 | is expensive (ten times the cost of a default copy is considered | |
1818 | arbitrarily expensive). This avoids losing when the preferred class | |
1819 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1820 | |
1821 | if ((set = single_set (insn)) != 0 | |
1822 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
0dc0641b JH |
1823 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG |
1824 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
ec2d92af RK |
1825 | for (i = 0; i <= 1; i++) |
1826 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1827 | { | |
770ae6cc | 1828 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1829 | enum machine_mode mode = GET_MODE (ops[!i]); |
1830 | int class; | |
770ae6cc | 1831 | unsigned int nr; |
ec2d92af | 1832 | |
accef103 JL |
1833 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1834 | { | |
1835 | enum reg_class pref = reg_pref[regno].prefclass; | |
1836 | ||
1837 | if ((reg_class_size[(unsigned char) pref] | |
f7043461 | 1838 | == (unsigned) CLASS_MAX_NREGS (pref, mode)) |
e56b4594 | 1839 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1840 | op_costs[i].cost[(unsigned char) pref] = -1; |
1841 | } | |
ec2d92af RK |
1842 | else if (regno < FIRST_PSEUDO_REGISTER) |
1843 | for (class = 0; class < N_REG_CLASSES; class++) | |
1844 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
f7043461 | 1845 | && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) |
4841ba4b RK |
1846 | { |
1847 | if (reg_class_size[class] == 1) | |
1848 | op_costs[i].cost[class] = -1; | |
1849 | else | |
1850 | { | |
f7043461 | 1851 | for (nr = 0; nr < (unsigned) HARD_REGNO_NREGS (regno, mode); nr++) |
4841ba4b | 1852 | { |
770ae6cc RK |
1853 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1854 | regno + nr)) | |
4841ba4b RK |
1855 | break; |
1856 | } | |
1857 | ||
f7043461 | 1858 | if (nr == (unsigned) HARD_REGNO_NREGS (regno,mode)) |
4841ba4b RK |
1859 | op_costs[i].cost[class] = -1; |
1860 | } | |
1861 | } | |
ec2d92af | 1862 | } |
54dac99e | 1863 | } |
e4600702 | 1864 | \f |
40f03658 | 1865 | /* Compute the cost of loading X into (if TO_P is nonzero) or from (if |
e4600702 RK |
1866 | TO_P is zero) a register of class CLASS in mode MODE. |
1867 | ||
1868 | X must not be a pseudo. */ | |
1869 | ||
1870 | static int | |
0c20a65f AJ |
1871 | copy_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, |
1872 | enum reg_class class, int to_p ATTRIBUTE_UNUSED) | |
e4600702 | 1873 | { |
29a82058 | 1874 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1875 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1876 | #endif |
e4600702 RK |
1877 | |
1878 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1879 | assuming optimal allocation. */ | |
1880 | ||
1881 | if (GET_CODE (x) == SCRATCH) | |
1882 | return 0; | |
1883 | ||
1884 | /* Get the class we will actually use for a reload. */ | |
1885 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1886 | ||
1887 | #ifdef HAVE_SECONDARY_RELOADS | |
a6a2274a | 1888 | /* If we need a secondary reload (we assume here that we are using |
e4600702 RK |
1889 | the secondary reload as an intermediate, not a scratch register), the |
1890 | cost is that to load the input into the intermediate register, then | |
1891 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1892 | ||
1893 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1894 | if (to_p == 1) | |
1895 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1896 | #endif | |
1897 | ||
dd9f0e8f | 1898 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1899 | if (! to_p) |
1900 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1901 | #endif | |
1902 | ||
1903 | if (secondary_class != NO_REGS) | |
e56b4594 | 1904 | return (move_cost[mode][(int) secondary_class][(int) class] |
e4600702 | 1905 | + copy_cost (x, mode, secondary_class, 2)); |
dd9f0e8f | 1906 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1907 | |
1908 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1909 | cost to move between the register classes, and use 2 for everything | |
1910 | else (constants). */ | |
1911 | ||
1912 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1913 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1914 | |
e4600702 | 1915 | else if (GET_CODE (x) == REG) |
e56b4594 | 1916 | return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
e4600702 RK |
1917 | |
1918 | else | |
1919 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
b437f1a7 | 1920 | return COSTS_N_INSNS (1); |
e4600702 RK |
1921 | } |
1922 | \f | |
54dac99e RK |
1923 | /* Record the pseudo registers we must reload into hard registers |
1924 | in a subexpression of a memory address, X. | |
e4600702 RK |
1925 | |
1926 | CLASS is the class that the register needs to be in and is either | |
1927 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1928 | ||
1929 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1930 | can represent half-cost adjustments). */ | |
54dac99e | 1931 | |
197d6480 | 1932 | static void |
0c20a65f | 1933 | record_address_regs (rtx x, enum reg_class class, int scale) |
54dac99e | 1934 | { |
b3694847 | 1935 | enum rtx_code code = GET_CODE (x); |
54dac99e RK |
1936 | |
1937 | switch (code) | |
1938 | { | |
1939 | case CONST_INT: | |
1940 | case CONST: | |
1941 | case CC0: | |
1942 | case PC: | |
1943 | case SYMBOL_REF: | |
1944 | case LABEL_REF: | |
1945 | return; | |
1946 | ||
1947 | case PLUS: | |
1948 | /* When we have an address that is a sum, | |
1949 | we must determine whether registers are "base" or "index" regs. | |
1950 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1951 | the "base". Luckily, we can use the REG_POINTER to make a good |
1952 | choice most of the time. We only need to do this on machines | |
1953 | that can have two registers in an address and where the base | |
1954 | and index register classes are different. | |
e4600702 RK |
1955 | |
1956 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1957 | that seems bogus since it should only be set when we are sure | |
1958 | the register is being used as a pointer. */ | |
1959 | ||
54dac99e RK |
1960 | { |
1961 | rtx arg0 = XEXP (x, 0); | |
1962 | rtx arg1 = XEXP (x, 1); | |
b3694847 SS |
1963 | enum rtx_code code0 = GET_CODE (arg0); |
1964 | enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1965 | |
1966 | /* Look inside subregs. */ | |
e4600702 | 1967 | if (code0 == SUBREG) |
54dac99e | 1968 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1969 | if (code1 == SUBREG) |
54dac99e RK |
1970 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1971 | ||
e4600702 RK |
1972 | /* If this machine only allows one register per address, it must |
1973 | be in the first operand. */ | |
1974 | ||
1975 | if (MAX_REGS_PER_ADDRESS == 1) | |
1976 | record_address_regs (arg0, class, scale); | |
1977 | ||
1978 | /* If index and base registers are the same on this machine, just | |
1979 | record registers in any non-constant operands. We assume here, | |
a6a2274a | 1980 | as well as in the tests below, that all addresses are in |
e4600702 RK |
1981 | canonical form. */ |
1982 | ||
3dcc68a4 | 1983 | else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) |
54dac99e | 1984 | { |
e4600702 RK |
1985 | record_address_regs (arg0, class, scale); |
1986 | if (! CONSTANT_P (arg1)) | |
1987 | record_address_regs (arg1, class, scale); | |
54dac99e | 1988 | } |
e4600702 RK |
1989 | |
1990 | /* If the second operand is a constant integer, it doesn't change | |
1991 | what class the first operand must be. */ | |
1992 | ||
1993 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1994 | record_address_regs (arg0, class, scale); | |
1995 | ||
1996 | /* If the second operand is a symbolic constant, the first operand | |
1997 | must be an index register. */ | |
1998 | ||
1999 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
2000 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
2001 | ||
956d6950 JL |
2002 | /* If both operands are registers but one is already a hard register |
2003 | of index or base class, give the other the class that the hard | |
2004 | register is not. */ | |
2005 | ||
3f9e9508 | 2006 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
2007 | else if (code0 == REG && code1 == REG |
2008 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
2009 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
2010 | record_address_regs (arg1, | |
2011 | REG_OK_FOR_BASE_P (arg0) | |
3dcc68a4 | 2012 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 JL |
2013 | scale); |
2014 | else if (code0 == REG && code1 == REG | |
2015 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
2016 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
2017 | record_address_regs (arg0, | |
2018 | REG_OK_FOR_BASE_P (arg1) | |
3dcc68a4 | 2019 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 | 2020 | scale); |
3f9e9508 | 2021 | #endif |
956d6950 | 2022 | |
e9a25f70 JL |
2023 | /* If one operand is known to be a pointer, it must be the base |
2024 | with the other operand the index. Likewise if the other operand | |
2025 | is a MULT. */ | |
f22376c7 | 2026 | |
3502dc9c | 2027 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 2028 | || code1 == MULT) |
f22376c7 | 2029 | { |
3dcc68a4 | 2030 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2031 | record_address_regs (arg1, INDEX_REG_CLASS, scale); |
2032 | } | |
3502dc9c | 2033 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 2034 | || code0 == MULT) |
f22376c7 CI |
2035 | { |
2036 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
3dcc68a4 | 2037 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2038 | } |
2039 | ||
e9a25f70 | 2040 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
2041 | or index register. This case should be rare. */ |
2042 | ||
e9a25f70 | 2043 | else |
54dac99e | 2044 | { |
3dcc68a4 NC |
2045 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), |
2046 | scale / 2); | |
e4600702 | 2047 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); |
3dcc68a4 NC |
2048 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), |
2049 | scale / 2); | |
e4600702 | 2050 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); |
54dac99e | 2051 | } |
54dac99e RK |
2052 | } |
2053 | break; | |
2054 | ||
4b983fdc RH |
2055 | /* Double the importance of a pseudo register that is incremented |
2056 | or decremented, since it would take two extra insns | |
2057 | if it ends up in the wrong place. */ | |
2058 | case POST_MODIFY: | |
2059 | case PRE_MODIFY: | |
3dcc68a4 NC |
2060 | record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), |
2061 | 2 * scale); | |
4b983fdc RH |
2062 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
2063 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
2064 | INDEX_REG_CLASS, 2 * scale); | |
2065 | break; | |
2066 | ||
54dac99e RK |
2067 | case POST_INC: |
2068 | case PRE_INC: | |
2069 | case POST_DEC: | |
2070 | case PRE_DEC: | |
2071 | /* Double the importance of a pseudo register that is incremented | |
2072 | or decremented, since it would take two extra insns | |
533d0835 RK |
2073 | if it ends up in the wrong place. If the operand is a pseudo, |
2074 | show it is being used in an INC_DEC context. */ | |
2075 | ||
2076 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2077 | if (GET_CODE (XEXP (x, 0)) == REG | |
2078 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
2079 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2080 | #endif | |
e4600702 RK |
2081 | |
2082 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
2083 | break; |
2084 | ||
2085 | case REG: | |
2086 | { | |
b3694847 SS |
2087 | struct costs *pp = &costs[REGNO (x)]; |
2088 | int i; | |
54dac99e | 2089 | |
cbd5b9a2 | 2090 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 2091 | |
e4600702 | 2092 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 2093 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
2094 | } |
2095 | break; | |
2096 | ||
2097 | default: | |
2098 | { | |
b3694847 SS |
2099 | const char *fmt = GET_RTX_FORMAT (code); |
2100 | int i; | |
54dac99e RK |
2101 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2102 | if (fmt[i] == 'e') | |
e4600702 | 2103 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
2104 | } |
2105 | } | |
2106 | } | |
08d95f91 RK |
2107 | \f |
2108 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2109 | ||
2110 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2111 | to an object of MODE. */ | |
2112 | ||
1d300e19 | 2113 | static int |
0c20a65f | 2114 | auto_inc_dec_reg_p (rtx reg, enum machine_mode mode) |
08d95f91 | 2115 | { |
940da324 JL |
2116 | if (HAVE_POST_INCREMENT |
2117 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2118 | return 1; |
08d95f91 | 2119 | |
940da324 JL |
2120 | if (HAVE_POST_DECREMENT |
2121 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2122 | return 1; |
08d95f91 | 2123 | |
940da324 JL |
2124 | if (HAVE_PRE_INCREMENT |
2125 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2126 | return 1; |
08d95f91 | 2127 | |
940da324 JL |
2128 | if (HAVE_PRE_DECREMENT |
2129 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2130 | return 1; |
08d95f91 RK |
2131 | |
2132 | return 0; | |
2133 | } | |
2134 | #endif | |
b1f21e0a | 2135 | \f |
da668e9c MM |
2136 | static short *renumber; |
2137 | static size_t regno_allocated; | |
2138 | static unsigned int reg_n_max; | |
ed396e68 | 2139 | |
b1f21e0a MM |
2140 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2141 | reg_scan and flow_analysis that are indexed by the register number. If | |
88cad84b | 2142 | NEW_P is nonzero, initialize all of the registers, otherwise only |
39379e67 MM |
2143 | initialize the new registers allocated. The same table is kept from |
2144 | function to function, only reallocating it when we need more room. If | |
88cad84b | 2145 | RENUMBER_P is nonzero, allocate the reg_renumber array also. */ |
b1f21e0a MM |
2146 | |
2147 | void | |
0c20a65f | 2148 | allocate_reg_info (size_t num_regs, int new_p, int renumber_p) |
b1f21e0a | 2149 | { |
6feacd09 MM |
2150 | size_t size_info; |
2151 | size_t size_renumber; | |
2152 | size_t min = (new_p) ? 0 : reg_n_max; | |
2153 | struct reg_info_data *reg_data; | |
39379e67 | 2154 | |
b1f21e0a MM |
2155 | if (num_regs > regno_allocated) |
2156 | { | |
6feacd09 MM |
2157 | size_t old_allocated = regno_allocated; |
2158 | ||
b1f21e0a | 2159 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
2160 | size_renumber = regno_allocated * sizeof (short); |
2161 | ||
2162 | if (!reg_n_info) | |
2163 | { | |
6feacd09 | 2164 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
703ad42b KG |
2165 | renumber = xmalloc (size_renumber); |
2166 | reg_pref_buffer = xmalloc (regno_allocated | |
2167 | * sizeof (struct reg_pref)); | |
39379e67 MM |
2168 | } |
2169 | ||
2170 | else | |
2171 | { | |
6feacd09 MM |
2172 | VARRAY_GROW (reg_n_info, regno_allocated); |
2173 | ||
2174 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
2175 | { | |
8e2e89f7 KH |
2176 | free ((char *) renumber); |
2177 | free ((char *) reg_pref); | |
703ad42b KG |
2178 | renumber = xmalloc (size_renumber); |
2179 | reg_pref_buffer = xmalloc (regno_allocated | |
2180 | * sizeof (struct reg_pref)); | |
6feacd09 MM |
2181 | } |
2182 | ||
2183 | else | |
2184 | { | |
703ad42b KG |
2185 | renumber = xrealloc (renumber, size_renumber); |
2186 | reg_pref_buffer = xrealloc (reg_pref_buffer, | |
2187 | regno_allocated | |
2188 | * sizeof (struct reg_pref)); | |
6feacd09 | 2189 | } |
39379e67 | 2190 | } |
6feacd09 MM |
2191 | |
2192 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2193 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
703ad42b | 2194 | reg_data = xcalloc (size_info, 1); |
6feacd09 MM |
2195 | reg_data->min_index = old_allocated; |
2196 | reg_data->max_index = regno_allocated - 1; | |
2197 | reg_data->next = reg_info_head; | |
2198 | reg_info_head = reg_data; | |
b1f21e0a MM |
2199 | } |
2200 | ||
6feacd09 | 2201 | reg_n_max = num_regs; |
b1f21e0a MM |
2202 | if (min < num_regs) |
2203 | { | |
6feacd09 MM |
2204 | /* Loop through each of the segments allocated for the actual |
2205 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
a6a2274a | 2206 | for (reg_data = reg_info_head; |
da668e9c MM |
2207 | reg_data && reg_data->max_index >= min; |
2208 | reg_data = reg_data->next) | |
39379e67 | 2209 | { |
6feacd09 MM |
2210 | size_t min_index = reg_data->min_index; |
2211 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2212 | size_t max = MIN (max_index, num_regs); |
2213 | size_t local_min = min - min_index; | |
2214 | size_t i; | |
6feacd09 | 2215 | |
da668e9c MM |
2216 | if (reg_data->min_index > num_regs) |
2217 | continue; | |
6feacd09 | 2218 | |
da668e9c MM |
2219 | if (min < min_index) |
2220 | local_min = 0; | |
2221 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2222 | reg_data->used_p = 1; /* no need to zero */ | |
2223 | else | |
703ad42b KG |
2224 | memset (®_data->data[local_min], 0, |
2225 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
da668e9c MM |
2226 | |
2227 | for (i = min_index+local_min; i <= max; i++) | |
2228 | { | |
2229 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2230 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2231 | renumber[i] = -1; | |
2232 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2233 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2234 | } |
39379e67 | 2235 | } |
b1f21e0a MM |
2236 | } |
2237 | ||
6feacd09 MM |
2238 | /* If {pref,alt}class have already been allocated, update the pointers to |
2239 | the newly realloced ones. */ | |
9ffc5a70 JH |
2240 | if (reg_pref) |
2241 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2242 | |
39379e67 MM |
2243 | if (renumber_p) |
2244 | reg_renumber = renumber; | |
2245 | ||
3eae4643 | 2246 | /* Tell the regset code about the new number of registers. */ |
73b76448 | 2247 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); |
b1f21e0a MM |
2248 | } |
2249 | ||
ed396e68 BS |
2250 | /* Free up the space allocated by allocate_reg_info. */ |
2251 | void | |
0c20a65f | 2252 | free_reg_info (void) |
ed396e68 BS |
2253 | { |
2254 | if (reg_n_info) | |
2255 | { | |
2256 | struct reg_info_data *reg_data; | |
2257 | struct reg_info_data *reg_next; | |
2258 | ||
2259 | VARRAY_FREE (reg_n_info); | |
2260 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2261 | { | |
2262 | reg_next = reg_data->next; | |
8e2e89f7 | 2263 | free ((char *) reg_data); |
ed396e68 BS |
2264 | } |
2265 | ||
9ffc5a70 | 2266 | free (reg_pref_buffer); |
f4f4d0f8 KH |
2267 | reg_pref_buffer = (struct reg_pref *) 0; |
2268 | reg_info_head = (struct reg_info_data *) 0; | |
2269 | renumber = (short *) 0; | |
ed396e68 BS |
2270 | } |
2271 | regno_allocated = 0; | |
2272 | reg_n_max = 0; | |
2273 | } | |
54dac99e RK |
2274 | \f |
2275 | /* This is the `regscan' pass of the compiler, run just before cse | |
2276 | and again just before loop. | |
2277 | ||
2278 | It finds the first and last use of each pseudo-register | |
2279 | and records them in the vectors regno_first_uid, regno_last_uid | |
2280 | and counts the number of sets in the vector reg_n_sets. | |
2281 | ||
2282 | REPEAT is nonzero the second time this is called. */ | |
2283 | ||
54dac99e | 2284 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2285 | Always at least 3, since the combiner could put that many together |
79b9ec0d RK |
2286 | and we want this to remain correct for all the remaining passes. |
2287 | This corresponds to the maximum number of times note_stores will call | |
2288 | a function for any insn. */ | |
54dac99e RK |
2289 | |
2290 | int max_parallel; | |
2291 | ||
a6a2274a | 2292 | /* Used as a temporary to record the largest number of registers in |
79b9ec0d RK |
2293 | PARALLEL in a SET_DEST. This is added to max_parallel. */ |
2294 | ||
2295 | static int max_set_parallel; | |
2296 | ||
54dac99e | 2297 | void |
0c20a65f | 2298 | reg_scan (rtx f, unsigned int nregs, int repeat ATTRIBUTE_UNUSED) |
54dac99e | 2299 | { |
b3694847 | 2300 | rtx insn; |
54dac99e | 2301 | |
39379e67 | 2302 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e | 2303 | max_parallel = 3; |
79b9ec0d | 2304 | max_set_parallel = 0; |
54dac99e | 2305 | |
0d446150 JH |
2306 | timevar_push (TV_REG_SCAN); |
2307 | ||
54dac99e RK |
2308 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
2309 | if (GET_CODE (insn) == INSN | |
2310 | || GET_CODE (insn) == CALL_INSN | |
2311 | || GET_CODE (insn) == JUMP_INSN) | |
2312 | { | |
2313 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2314 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2315 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2316 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2317 | |
2318 | if (REG_NOTES (insn)) | |
f903b91f DM |
2319 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2320 | } | |
79b9ec0d RK |
2321 | |
2322 | max_parallel += max_set_parallel; | |
0d446150 JH |
2323 | |
2324 | timevar_pop (TV_REG_SCAN); | |
f903b91f DM |
2325 | } |
2326 | ||
2327 | /* Update 'regscan' information by looking at the insns | |
2328 | from FIRST to LAST. Some new REGs have been created, | |
2329 | and any REG with number greater than OLD_MAX_REGNO is | |
2330 | such a REG. We only update information for those. */ | |
2331 | ||
2332 | void | |
0c20a65f | 2333 | reg_scan_update (rtx first, rtx last, unsigned int old_max_regno) |
f903b91f | 2334 | { |
b3694847 | 2335 | rtx insn; |
f903b91f DM |
2336 | |
2337 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2338 | ||
2339 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2340 | if (GET_CODE (insn) == INSN | |
2341 | || GET_CODE (insn) == CALL_INSN | |
2342 | || GET_CODE (insn) == JUMP_INSN) | |
2343 | { | |
2344 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2345 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2346 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2347 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2348 | ||
2349 | if (REG_NOTES (insn)) | |
2350 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2351 | } |
2352 | } | |
2353 | ||
1ebecb64 | 2354 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2355 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2356 | We should only record information for REGs with numbers | |
2357 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2358 | |
08d95f91 | 2359 | static void |
0c20a65f | 2360 | reg_scan_mark_refs (rtx x, rtx insn, int note_flag, unsigned int min_regno) |
54dac99e | 2361 | { |
b3694847 SS |
2362 | enum rtx_code code; |
2363 | rtx dest; | |
2364 | rtx note; | |
54dac99e | 2365 | |
ed8d2920 MM |
2366 | if (!x) |
2367 | return; | |
fa23c636 | 2368 | code = GET_CODE (x); |
54dac99e RK |
2369 | switch (code) |
2370 | { | |
54dac99e | 2371 | case CONST: |
185ebd6c | 2372 | case CONST_INT: |
54dac99e | 2373 | case CONST_DOUBLE: |
69ef87e2 | 2374 | case CONST_VECTOR: |
54dac99e RK |
2375 | case CC0: |
2376 | case PC: | |
2377 | case SYMBOL_REF: | |
2378 | case LABEL_REF: | |
2379 | case ADDR_VEC: | |
2380 | case ADDR_DIFF_VEC: | |
2381 | return; | |
2382 | ||
2383 | case REG: | |
2384 | { | |
770ae6cc | 2385 | unsigned int regno = REGNO (x); |
54dac99e | 2386 | |
f903b91f DM |
2387 | if (regno >= min_regno) |
2388 | { | |
2389 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2390 | if (!note_flag) | |
2391 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2392 | if (REGNO_FIRST_UID (regno) == 0) | |
2393 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
ed8d2920 MM |
2394 | /* If we are called by reg_scan_update() (indicated by min_regno |
2395 | being set), we also need to update the reference count. */ | |
2396 | if (min_regno) | |
2397 | REG_N_REFS (regno)++; | |
f903b91f | 2398 | } |
54dac99e RK |
2399 | } |
2400 | break; | |
2401 | ||
01565a55 | 2402 | case EXPR_LIST: |
7b18c3db | 2403 | if (XEXP (x, 0)) |
f903b91f | 2404 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2405 | if (XEXP (x, 1)) |
f903b91f | 2406 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2407 | break; |
2408 | ||
2409 | case INSN_LIST: | |
2410 | if (XEXP (x, 1)) | |
f903b91f | 2411 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2412 | break; |
2413 | ||
ed8d2920 MM |
2414 | case CLOBBER: |
2415 | { | |
2416 | rtx reg = XEXP (x, 0); | |
2417 | if (REG_P (reg) | |
2418 | && REGNO (reg) >= min_regno) | |
2419 | { | |
2420 | REG_N_SETS (REGNO (reg))++; | |
2421 | REG_N_REFS (REGNO (reg))++; | |
2422 | } | |
2423 | } | |
2424 | break; | |
2425 | ||
54dac99e RK |
2426 | case SET: |
2427 | /* Count a set of the destination if it is a register. */ | |
2428 | for (dest = SET_DEST (x); | |
2429 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2430 | || GET_CODE (dest) == ZERO_EXTEND; | |
2431 | dest = XEXP (dest, 0)) | |
2432 | ; | |
2433 | ||
79b9ec0d RK |
2434 | /* For a PARALLEL, record the number of things (less the usual one for a |
2435 | SET) that are set. */ | |
2436 | if (GET_CODE (dest) == PARALLEL) | |
2437 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2438 | ||
f903b91f DM |
2439 | if (GET_CODE (dest) == REG |
2440 | && REGNO (dest) >= min_regno) | |
b2d57793 DB |
2441 | { |
2442 | REG_N_SETS (REGNO (dest))++; | |
2443 | REG_N_REFS (REGNO (dest))++; | |
2444 | } | |
54dac99e | 2445 | |
be8dcd74 RK |
2446 | /* If this is setting a pseudo from another pseudo or the sum of a |
2447 | pseudo and a constant integer and the other pseudo is known to be | |
2448 | a pointer, set the destination to be a pointer as well. | |
2449 | ||
2450 | Likewise if it is setting the destination from an address or from a | |
2451 | value equivalent to an address or to the sum of an address and | |
2452 | something else. | |
a6a2274a | 2453 | |
be8dcd74 RK |
2454 | But don't do any of this if the pseudo corresponds to a user |
2455 | variable since it should have already been set as a pointer based | |
2456 | on the type. */ | |
2457 | ||
2458 | if (GET_CODE (SET_DEST (x)) == REG | |
2459 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2460 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2461 | /* If the destination pseudo is set more than once, then other |
2462 | sets might not be to a pointer value (consider access to a | |
d55d8fc7 | 2463 | union in two threads of control in the presence of global |
3502dc9c | 2464 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2465 | pseudo if this is the only set of that pseudo. */ |
2466 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2467 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2468 | && ! REG_POINTER (SET_DEST (x)) |
be8dcd74 | 2469 | && ((GET_CODE (SET_SRC (x)) == REG |
3502dc9c | 2470 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2471 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2472 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2473 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2474 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3502dc9c | 2475 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2476 | || GET_CODE (SET_SRC (x)) == CONST |
2477 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2478 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2479 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2480 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2481 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2482 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2483 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2484 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2485 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2486 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2487 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2488 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2489 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2490 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2491 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2492 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2493 | |
0d4903b8 | 2494 | /* If this is setting a register from a register or from a simple |
a560d4d4 | 2495 | conversion of a register, propagate REG_EXPR. */ |
0d4903b8 RK |
2496 | if (GET_CODE (dest) == REG) |
2497 | { | |
2498 | rtx src = SET_SRC (x); | |
2499 | ||
2500 | while (GET_CODE (src) == SIGN_EXTEND | |
2501 | || GET_CODE (src) == ZERO_EXTEND | |
2502 | || GET_CODE (src) == TRUNCATE | |
2503 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2504 | src = XEXP (src, 0); | |
2505 | ||
a560d4d4 JH |
2506 | if (!REG_ATTRS (dest) && REG_P (src)) |
2507 | REG_ATTRS (dest) = REG_ATTRS (src); | |
2508 | if (!REG_ATTRS (dest) && GET_CODE (src) == MEM) | |
2509 | set_reg_attrs_from_mem (dest, src); | |
0d4903b8 RK |
2510 | } |
2511 | ||
0f41302f | 2512 | /* ... fall through ... */ |
54dac99e RK |
2513 | |
2514 | default: | |
2515 | { | |
b3694847 SS |
2516 | const char *fmt = GET_RTX_FORMAT (code); |
2517 | int i; | |
54dac99e RK |
2518 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2519 | { | |
2520 | if (fmt[i] == 'e') | |
f903b91f | 2521 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2522 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2523 | { | |
b3694847 | 2524 | int j; |
54dac99e | 2525 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
f903b91f | 2526 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2527 | } |
2528 | } | |
2529 | } | |
2530 | } | |
2531 | } | |
2532 | \f | |
2533 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2534 | is also in C2. */ | |
2535 | ||
2536 | int | |
0c20a65f | 2537 | reg_class_subset_p (enum reg_class c1, enum reg_class c2) |
54dac99e RK |
2538 | { |
2539 | if (c1 == c2) return 1; | |
2540 | ||
2541 | if (c2 == ALL_REGS) | |
2542 | win: | |
2543 | return 1; | |
8e2e89f7 KH |
2544 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], |
2545 | reg_class_contents[(int) c2], | |
54dac99e RK |
2546 | win); |
2547 | return 0; | |
2548 | } | |
2549 | ||
2550 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2551 | ||
2552 | int | |
0c20a65f | 2553 | reg_classes_intersect_p (enum reg_class c1, enum reg_class c2) |
54dac99e RK |
2554 | { |
2555 | #ifdef HARD_REG_SET | |
2556 | register | |
2557 | #endif | |
2558 | HARD_REG_SET c; | |
2559 | ||
2560 | if (c1 == c2) return 1; | |
2561 | ||
2562 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2563 | return 1; | |
2564 | ||
2565 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2566 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2567 | ||
2568 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2569 | return 1; | |
2570 | ||
2571 | lose: | |
2572 | return 0; | |
2573 | } | |
2574 | ||
73b76448 RK |
2575 | /* Release any memory allocated by register sets. */ |
2576 | ||
2577 | void | |
0c20a65f | 2578 | regset_release_memory (void) |
73b76448 | 2579 | { |
73b76448 RK |
2580 | bitmap_release_memory (); |
2581 | } | |
e2500fed | 2582 | |
cff9f8d5 AH |
2583 | #ifdef CANNOT_CHANGE_MODE_CLASS |
2584 | /* Set bits in *USED which correspond to registers which can't change | |
2585 | their mode from FROM to any mode in which REGNO was encountered. */ | |
2586 | ||
2587 | void | |
0c20a65f AJ |
2588 | cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from, |
2589 | unsigned int regno) | |
cff9f8d5 AH |
2590 | { |
2591 | enum machine_mode to; | |
10a3fdd9 JH |
2592 | int n, i; |
2593 | int start = regno * MAX_MACHINE_MODE; | |
cff9f8d5 | 2594 | |
10a3fdd9 JH |
2595 | EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, |
2596 | if (n >= MAX_MACHINE_MODE + start) | |
2597 | return; | |
2598 | to = n - start; | |
2599 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2600 | if (! TEST_HARD_REG_BIT (*used, i) | |
2601 | && REG_CANNOT_CHANGE_MODE_P (i, from, to)) | |
2602 | SET_HARD_REG_BIT (*used, i); | |
2603 | ); | |
cff9f8d5 AH |
2604 | } |
2605 | ||
2606 | /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM | |
2607 | mode. */ | |
2608 | ||
2609 | bool | |
0c20a65f AJ |
2610 | invalid_mode_change_p (unsigned int regno, enum reg_class class, |
2611 | enum machine_mode from_mode) | |
cff9f8d5 AH |
2612 | { |
2613 | enum machine_mode to_mode; | |
10a3fdd9 JH |
2614 | int n; |
2615 | int start = regno * MAX_MACHINE_MODE; | |
2616 | ||
2617 | EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, | |
2618 | if (n >= MAX_MACHINE_MODE + start) | |
2619 | return 0; | |
2620 | to_mode = n - start; | |
2621 | if (CANNOT_CHANGE_MODE_CLASS (from_mode, to_mode, class)) | |
cff9f8d5 | 2622 | return 1; |
10a3fdd9 | 2623 | ); |
cff9f8d5 AH |
2624 | return 0; |
2625 | } | |
2626 | #endif /* CANNOT_CHANGE_MODE_CLASS */ | |
2627 | ||
e2500fed | 2628 | #include "gt-regclass.h" |