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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
29a82058 | 2 | Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
670ee920 | 27 | #include "system.h" |
54dac99e RK |
28 | #include "rtl.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "flags.h" | |
31 | #include "basic-block.h" | |
32 | #include "regs.h" | |
33 | #include "insn-config.h" | |
34 | #include "recog.h" | |
e4600702 RK |
35 | #include "reload.h" |
36 | #include "real.h" | |
54dac99e RK |
37 | |
38 | #ifndef REGISTER_MOVE_COST | |
39 | #define REGISTER_MOVE_COST(x, y) 2 | |
40 | #endif | |
41 | ||
533d0835 RK |
42 | /* If we have auto-increment or auto-decrement and we can have secondary |
43 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 44 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
45 | |
46 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 47 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
48 | #define FORBIDDEN_INC_DEC_CLASSES |
49 | #endif | |
50 | #endif | |
54dac99e RK |
51 | \f |
52 | /* Register tables used by many passes. */ | |
53 | ||
54 | /* Indexed by hard register number, contains 1 for registers | |
55 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
56 | These are the registers that cannot be used to allocate | |
57 | a pseudo reg whose life does not cross calls. */ | |
58 | ||
59 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
60 | ||
61 | /* Same info as a HARD_REG_SET. */ | |
62 | ||
63 | HARD_REG_SET fixed_reg_set; | |
64 | ||
65 | /* Data for initializing the above. */ | |
66 | ||
67 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
68 | ||
69 | /* Indexed by hard register number, contains 1 for registers | |
70 | that are fixed use or are clobbered by function calls. | |
71 | These are the registers that cannot be used to allocate | |
72 | a pseudo reg whose life crosses calls. */ | |
73 | ||
74 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
75 | ||
76 | /* Same info as a HARD_REG_SET. */ | |
77 | ||
78 | HARD_REG_SET call_used_reg_set; | |
79 | ||
6cad67d2 JL |
80 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
81 | HARD_REG_SET losing_caller_save_reg_set; | |
82 | ||
54dac99e RK |
83 | /* Data for initializing the above. */ |
84 | ||
85 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
86 | ||
87 | /* Indexed by hard register number, contains 1 for registers that are | |
88 | fixed use -- i.e. in fixed_regs -- or a function value return register | |
89 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the | |
90 | registers that cannot hold quantities across calls even if we are | |
91 | willing to save and restore them. */ | |
92 | ||
93 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
94 | ||
95 | /* The same info as a HARD_REG_SET. */ | |
96 | ||
97 | HARD_REG_SET call_fixed_reg_set; | |
98 | ||
99 | /* Number of non-fixed registers. */ | |
100 | ||
101 | int n_non_fixed_regs; | |
102 | ||
103 | /* Indexed by hard register number, contains 1 for registers | |
104 | that are being used for global register decls. | |
105 | These must be exempt from ordinary flow analysis | |
106 | and are also considered fixed. */ | |
107 | ||
108 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
109 | ||
110 | /* Table of register numbers in the order in which to try to use them. */ | |
111 | #ifdef REG_ALLOC_ORDER | |
112 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
113 | #endif | |
114 | ||
115 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
116 | ||
2e0e2b76 CH |
117 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
118 | ||
089e575b RS |
119 | /* The same information, but as an array of unsigned ints. We copy from |
120 | these unsigned ints to the table above. We do this so the tm.h files | |
121 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
122 | |
123 | #define N_REG_INTS \ | |
124 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
125 | ||
089e575b | 126 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 127 | = REG_CLASS_CONTENTS; |
54dac99e RK |
128 | |
129 | /* For each reg class, number of regs it contains. */ | |
130 | ||
131 | int reg_class_size[N_REG_CLASSES]; | |
132 | ||
133 | /* For each reg class, table listing all the containing classes. */ | |
134 | ||
135 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
136 | ||
137 | /* For each reg class, table listing all the classes contained in it. */ | |
138 | ||
139 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
140 | ||
141 | /* For each pair of reg classes, | |
142 | a largest reg class contained in their union. */ | |
143 | ||
144 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
145 | ||
146 | /* For each pair of reg classes, | |
147 | the smallest reg class containing their union. */ | |
148 | ||
149 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
150 | ||
d05c8ee7 RS |
151 | /* Array containing all of the register names */ |
152 | ||
153 | char *reg_names[] = REGISTER_NAMES; | |
154 | ||
ca4aac00 DE |
155 | /* For each hard register, the widest mode object that it can contain. |
156 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
157 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
158 | register. */ | |
159 | ||
160 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
161 | ||
e4600702 RK |
162 | /* Maximum cost of moving from a register in one class to a register in |
163 | another class. Based on REGISTER_MOVE_COST. */ | |
164 | ||
165 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
166 | ||
167 | /* Similar, but here we don't have to move if the first index is a subset | |
168 | of the second so in that case the cost is zero. */ | |
169 | ||
170 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
171 | ||
533d0835 RK |
172 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
173 | ||
174 | /* These are the classes that regs which are auto-incremented or decremented | |
175 | cannot be put in. */ | |
176 | ||
177 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
178 | ||
179 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
180 | context. */ | |
181 | ||
182 | static char *in_inc_dec; | |
183 | ||
5fcb671c | 184 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 185 | |
54dac99e RK |
186 | /* Function called only once to initialize the above data on reg usage. |
187 | Once this is done, various switches may override. */ | |
188 | ||
189 | void | |
190 | init_reg_sets () | |
191 | { | |
192 | register int i, j; | |
193 | ||
2e0e2b76 CH |
194 | /* First copy the register information from the initial int form into |
195 | the regsets. */ | |
196 | ||
197 | for (i = 0; i < N_REG_CLASSES; i++) | |
198 | { | |
199 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
200 | ||
201 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
202 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 203 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
204 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
205 | } | |
206 | ||
54dac99e RK |
207 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
208 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
209 | bzero (global_regs, sizeof global_regs); | |
210 | ||
211 | /* Compute number of hard regs in each class. */ | |
212 | ||
4c9a05bc | 213 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
214 | for (i = 0; i < N_REG_CLASSES; i++) |
215 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
216 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
217 | reg_class_size[i]++; | |
218 | ||
219 | /* Initialize the table of subunions. | |
220 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
221 | that is contained in the union of classes I and J. */ | |
222 | ||
223 | for (i = 0; i < N_REG_CLASSES; i++) | |
224 | { | |
225 | for (j = 0; j < N_REG_CLASSES; j++) | |
226 | { | |
227 | #ifdef HARD_REG_SET | |
228 | register /* Declare it register if it's a scalar. */ | |
229 | #endif | |
230 | HARD_REG_SET c; | |
231 | register int k; | |
232 | ||
233 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
234 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
235 | for (k = 0; k < N_REG_CLASSES; k++) | |
236 | { | |
237 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
238 | subclass1); | |
239 | continue; | |
240 | ||
241 | subclass1: | |
242 | /* keep the largest subclass */ /* SPEE 900308 */ | |
243 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
244 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
245 | subclass2); | |
246 | reg_class_subunion[i][j] = (enum reg_class) k; | |
247 | subclass2: | |
248 | ; | |
249 | } | |
250 | } | |
251 | } | |
252 | ||
253 | /* Initialize the table of superunions. | |
254 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
255 | containing the union of classes I and J. */ | |
256 | ||
257 | for (i = 0; i < N_REG_CLASSES; i++) | |
258 | { | |
259 | for (j = 0; j < N_REG_CLASSES; j++) | |
260 | { | |
261 | #ifdef HARD_REG_SET | |
262 | register /* Declare it register if it's a scalar. */ | |
263 | #endif | |
264 | HARD_REG_SET c; | |
265 | register int k; | |
266 | ||
267 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
268 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
269 | for (k = 0; k < N_REG_CLASSES; k++) | |
270 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
271 | ||
272 | superclass: | |
273 | reg_class_superunion[i][j] = (enum reg_class) k; | |
274 | } | |
275 | } | |
276 | ||
277 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
278 | First clear the whole table, then add the elements as they are found. */ | |
279 | ||
280 | for (i = 0; i < N_REG_CLASSES; i++) | |
281 | { | |
282 | for (j = 0; j < N_REG_CLASSES; j++) | |
283 | { | |
284 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
285 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
286 | } | |
287 | } | |
288 | ||
289 | for (i = 0; i < N_REG_CLASSES; i++) | |
290 | { | |
291 | if (i == (int) NO_REGS) | |
292 | continue; | |
293 | ||
294 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
295 | { | |
296 | enum reg_class *p; | |
297 | ||
298 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
299 | subclass); | |
300 | continue; | |
301 | subclass: | |
302 | /* Reg class I is a subclass of J. | |
303 | Add J to the table of superclasses of I. */ | |
304 | p = ®_class_superclasses[i][0]; | |
305 | while (*p != LIM_REG_CLASSES) p++; | |
306 | *p = (enum reg_class) j; | |
307 | /* Add I to the table of superclasses of J. */ | |
308 | p = ®_class_subclasses[j][0]; | |
309 | while (*p != LIM_REG_CLASSES) p++; | |
310 | *p = (enum reg_class) i; | |
311 | } | |
312 | } | |
e4600702 | 313 | |
73b76448 RK |
314 | /* Do any additional initialization regsets may need */ |
315 | INIT_ONCE_REG_SET (); | |
54dac99e RK |
316 | } |
317 | ||
318 | /* After switches have been processed, which perhaps alter | |
319 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
320 | ||
c27c5281 | 321 | static void |
54dac99e RK |
322 | init_reg_sets_1 () |
323 | { | |
f8344bea | 324 | register unsigned int i, j; |
54dac99e RK |
325 | |
326 | /* This macro allows the fixed or call-used registers | |
327 | to depend on target flags. */ | |
328 | ||
329 | #ifdef CONDITIONAL_REGISTER_USAGE | |
330 | CONDITIONAL_REGISTER_USAGE; | |
331 | #endif | |
332 | ||
54dac99e RK |
333 | /* Initialize "constant" tables. */ |
334 | ||
335 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
336 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
337 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
338 | ||
339 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
340 | |
341 | n_non_fixed_regs = 0; | |
342 | ||
343 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
344 | { | |
54dac99e RK |
345 | if (fixed_regs[i]) |
346 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
347 | else | |
348 | n_non_fixed_regs++; | |
349 | ||
350 | if (call_used_regs[i]) | |
351 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
352 | if (call_fixed_regs[i]) | |
353 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
354 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
355 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 356 | } |
acbce667 KR |
357 | |
358 | /* Initialize the move cost table. Find every subset of each class | |
359 | and take the maximum cost of moving any subset to any other. */ | |
360 | ||
361 | for (i = 0; i < N_REG_CLASSES; i++) | |
362 | for (j = 0; j < N_REG_CLASSES; j++) | |
363 | { | |
364 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
365 | enum reg_class *p1, *p2; | |
366 | ||
367 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
368 | if (*p2 != i) | |
369 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
370 | ||
371 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
372 | { | |
373 | if (*p1 != j) | |
374 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
375 | ||
376 | for (p2 = ®_class_subclasses[j][0]; | |
377 | *p2 != LIM_REG_CLASSES; p2++) | |
378 | if (*p1 != *p2) | |
379 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
380 | } | |
381 | ||
382 | move_cost[i][j] = cost; | |
383 | ||
384 | if (reg_class_subset_p (i, j)) | |
385 | cost = 0; | |
386 | ||
387 | may_move_cost[i][j] = cost; | |
388 | } | |
c27c5281 DE |
389 | } |
390 | ||
391 | /* Compute the table of register modes. | |
392 | These values are used to record death information for individual registers | |
393 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 394 | |
c27c5281 DE |
395 | static void |
396 | init_reg_modes () | |
397 | { | |
398 | register int i; | |
ca4aac00 DE |
399 | |
400 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
401 | { |
402 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
403 | ||
066c2fea | 404 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
405 | ??? One situation in which we need to do this is on the mips where |
406 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
407 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 408 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 409 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 410 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 411 | } |
ca4aac00 DE |
412 | } |
413 | ||
c27c5281 DE |
414 | /* Finish initializing the register sets and |
415 | initialize the register modes. */ | |
416 | ||
417 | void | |
418 | init_regs () | |
419 | { | |
420 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
421 | until after register usage was specified. */ | |
b93a436e | 422 | init_reg_sets_1 (); |
c27c5281 DE |
423 | |
424 | init_reg_modes (); | |
425 | } | |
426 | ||
cbd5b9a2 KR |
427 | #ifdef HAVE_SECONDARY_RELOADS |
428 | /* Compute extra cost of moving registers to/from memory due to reloads. | |
429 | Only needed if secondary reloads are required for memory moves. */ | |
430 | int | |
431 | memory_move_secondary_cost (mode, class, in) | |
432 | enum machine_mode mode; | |
433 | enum reg_class class; | |
434 | int in; | |
435 | { | |
436 | enum reg_class altclass; | |
437 | int partial_cost = 0; | |
438 | rtx mem; | |
439 | ||
440 | /* We need a memory reference to feed to SECONDARY... macros. */ | |
441 | mem = gen_rtx (MEM, mode, stack_pointer_rtx); | |
442 | ||
443 | if (in) | |
321c0828 | 444 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
cbd5b9a2 | 445 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 MH |
446 | #else |
447 | altclass = NO_REGS; | |
448 | #endif | |
cbd5b9a2 | 449 | else |
321c0828 | 450 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
cbd5b9a2 | 451 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 MH |
452 | #else |
453 | altclass = NO_REGS; | |
454 | #endif | |
cbd5b9a2 KR |
455 | if (altclass == NO_REGS) |
456 | return 0; | |
457 | ||
458 | if (in) | |
459 | partial_cost = REGISTER_MOVE_COST (altclass, class); | |
460 | else | |
461 | partial_cost = REGISTER_MOVE_COST (class, altclass); | |
462 | ||
463 | if (class == altclass) | |
464 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
465 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
466 | here in that case. | |
467 | ||
468 | I'm tempted to put in an abort here, but returning this will | |
469 | probably only give poor estimates, which is what we would've | |
470 | had before this code anyways. */ | |
471 | return partial_cost; | |
472 | ||
473 | /* Check if the secondary reload register will also need a | |
474 | secondary reload. */ | |
475 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
476 | } | |
477 | #endif | |
478 | ||
ca4aac00 DE |
479 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
480 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
481 | ||
482 | enum machine_mode | |
483 | choose_hard_reg_mode (regno, nregs) | |
484 | int regno; | |
485 | int nregs; | |
486 | { | |
487 | enum machine_mode found_mode = VOIDmode, mode; | |
488 | ||
489 | /* We first look for the largest integer mode that can be validly | |
490 | held in REGNO. If none, we look for the largest floating-point mode. | |
491 | If we still didn't find a valid mode, try CCmode. */ | |
492 | ||
493 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
494 | mode != VOIDmode; | |
495 | mode = GET_MODE_WIDER_MODE (mode)) | |
496 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
497 | && HARD_REGNO_MODE_OK (regno, mode)) | |
498 | found_mode = mode; | |
499 | ||
500 | if (found_mode != VOIDmode) | |
501 | return found_mode; | |
502 | ||
503 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
504 | mode != VOIDmode; | |
505 | mode = GET_MODE_WIDER_MODE (mode)) | |
506 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
507 | && HARD_REGNO_MODE_OK (regno, mode)) | |
508 | found_mode = mode; | |
509 | ||
510 | if (found_mode != VOIDmode) | |
511 | return found_mode; | |
512 | ||
513 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
514 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
515 | return CCmode; | |
516 | ||
517 | /* We can't find a mode valid for this register. */ | |
518 | return VOIDmode; | |
54dac99e RK |
519 | } |
520 | ||
521 | /* Specify the usage characteristics of the register named NAME. | |
522 | It should be a fixed register if FIXED and a | |
523 | call-used register if CALL_USED. */ | |
524 | ||
525 | void | |
526 | fix_register (name, fixed, call_used) | |
527 | char *name; | |
528 | int fixed, call_used; | |
529 | { | |
530 | int i; | |
531 | ||
532 | /* Decode the name and update the primary form of | |
533 | the register info. */ | |
534 | ||
e5c90c23 TW |
535 | if ((i = decode_reg_name (name)) >= 0) |
536 | { | |
537 | fixed_regs[i] = fixed; | |
538 | call_used_regs[i] = call_used; | |
539 | } | |
540 | else | |
54dac99e RK |
541 | { |
542 | warning ("unknown register name: %s", name); | |
54dac99e RK |
543 | } |
544 | } | |
614f68e2 RK |
545 | |
546 | /* Mark register number I as global. */ | |
547 | ||
548 | void | |
549 | globalize_reg (i) | |
550 | int i; | |
551 | { | |
552 | if (global_regs[i]) | |
553 | { | |
554 | warning ("register used for two global register variables"); | |
555 | return; | |
556 | } | |
557 | ||
558 | if (call_used_regs[i] && ! fixed_regs[i]) | |
559 | warning ("call-clobbered register used for global register variable"); | |
560 | ||
561 | global_regs[i] = 1; | |
562 | ||
563 | /* If already fixed, nothing else to do. */ | |
564 | if (fixed_regs[i]) | |
565 | return; | |
566 | ||
567 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
568 | n_non_fixed_regs--; | |
569 | ||
570 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
571 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
572 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
573 | } | |
54dac99e RK |
574 | \f |
575 | /* Now the data and code for the `regclass' pass, which happens | |
576 | just before local-alloc. */ | |
577 | ||
e4600702 RK |
578 | /* The `costs' struct records the cost of using a hard register of each class |
579 | and of using memory for each pseudo. We use this data to set up | |
580 | register class preferences. */ | |
54dac99e | 581 | |
e4600702 | 582 | struct costs |
54dac99e | 583 | { |
e4600702 RK |
584 | int cost[N_REG_CLASSES]; |
585 | int mem_cost; | |
54dac99e RK |
586 | }; |
587 | ||
e4600702 RK |
588 | /* Record the cost of each class for each pseudo. */ |
589 | ||
590 | static struct costs *costs; | |
591 | ||
592 | /* Record the same data by operand number, accumulated for each alternative | |
593 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
594 | alternative. */ | |
595 | ||
596 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
597 | |
598 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
599 | This is available after `regclass' is run. */ | |
600 | ||
601 | static char *prefclass; | |
602 | ||
54d23420 RK |
603 | /* altclass[R] is a register class that we should use for allocating |
604 | pseudo number R if no register in the preferred class is available. | |
605 | If no register in this class is available, memory is preferred. | |
606 | ||
607 | It might appear to be more general to have a bitmask of classes here, | |
608 | but since it is recommended that there be a class corresponding to the | |
609 | union of most major pair of classes, that generality is not required. | |
610 | ||
54dac99e RK |
611 | This is available after `regclass' is run. */ |
612 | ||
54d23420 | 613 | static char *altclass; |
54dac99e | 614 | |
54d23420 | 615 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
616 | |
617 | static int loop_depth; | |
618 | ||
54d23420 RK |
619 | /* Account for the fact that insns within a loop are executed very commonly, |
620 | but don't keep doing this as loops go too deep. */ | |
621 | ||
622 | static int loop_cost; | |
623 | ||
08d95f91 RK |
624 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
625 | char **, rtx)); | |
626 | static int copy_cost PROTO((rtx, enum machine_mode, | |
627 | enum reg_class, int)); | |
628 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
629 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
630 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
631 | #endif | |
08d95f91 | 632 | static void reg_scan_mark_refs PROTO((rtx, rtx, int)); |
54dac99e RK |
633 | |
634 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
635 | This function is sometimes called before the info has been computed. | |
636 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
637 | ||
638 | enum reg_class | |
639 | reg_preferred_class (regno) | |
640 | int regno; | |
641 | { | |
642 | if (prefclass == 0) | |
643 | return GENERAL_REGS; | |
644 | return (enum reg_class) prefclass[regno]; | |
645 | } | |
646 | ||
e4600702 RK |
647 | enum reg_class |
648 | reg_alternate_class (regno) | |
b729186a | 649 | int regno; |
54dac99e RK |
650 | { |
651 | if (prefclass == 0) | |
e4600702 RK |
652 | return ALL_REGS; |
653 | ||
654 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
655 | } |
656 | ||
657 | /* This prevents dump_flow_info from losing if called | |
658 | before regclass is run. */ | |
659 | ||
660 | void | |
661 | regclass_init () | |
662 | { | |
663 | prefclass = 0; | |
664 | } | |
665 | \f | |
666 | /* This is a pass of the compiler that scans all instructions | |
667 | and calculates the preferred class for each pseudo-register. | |
668 | This information can be accessed later by calling `reg_preferred_class'. | |
669 | This pass comes just before local register allocation. */ | |
670 | ||
671 | void | |
672 | regclass (f, nregs) | |
673 | rtx f; | |
674 | int nregs; | |
675 | { | |
676 | #ifdef REGISTER_CONSTRAINTS | |
677 | register rtx insn; | |
e4600702 RK |
678 | register int i, j; |
679 | struct costs init_cost; | |
680 | rtx set; | |
681 | int pass; | |
54dac99e RK |
682 | |
683 | init_recog (); | |
684 | ||
533d0835 RK |
685 | costs = (struct costs *) alloca (nregs * sizeof (struct costs)); |
686 | ||
687 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
688 | ||
689 | in_inc_dec = (char *) alloca (nregs); | |
690 | ||
691 | /* Initialize information about which register classes can be used for | |
692 | pseudos that are auto-incremented or auto-decremented. It would | |
693 | seem better to put this in init_reg_sets, but we need to be able | |
694 | to allocate rtx, which we can't do that early. */ | |
695 | ||
696 | for (i = 0; i < N_REG_CLASSES; i++) | |
697 | { | |
38a448ca | 698 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 RK |
699 | enum machine_mode m; |
700 | ||
701 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
702 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
703 | { | |
704 | REGNO (r) = j; | |
705 | ||
706 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 707 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
708 | if (HARD_REGNO_MODE_OK (j, m)) |
709 | { | |
710 | PUT_MODE (r, m); | |
08d95f91 RK |
711 | |
712 | /* If a register is not directly suitable for an | |
713 | auto-increment or decrement addressing mode and | |
714 | requires secondary reloads, disallow its class from | |
715 | being used in such addresses. */ | |
716 | ||
717 | if ((0 | |
041d7180 JL |
718 | #ifdef SECONDARY_RELOAD_CLASS |
719 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
720 | != NO_REGS) | |
721 | #else | |
533d0835 | 722 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
723 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
724 | != NO_REGS) | |
533d0835 RK |
725 | #endif |
726 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
727 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
728 | != NO_REGS) | |
041d7180 | 729 | #endif |
533d0835 | 730 | #endif |
08d95f91 RK |
731 | ) |
732 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
733 | forbidden_inc_dec_class[i] = 1; |
734 | } | |
735 | } | |
736 | } | |
737 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
738 | ||
e4600702 RK |
739 | init_cost.mem_cost = 10000; |
740 | for (i = 0; i < N_REG_CLASSES; i++) | |
741 | init_cost.cost[i] = 10000; | |
54dac99e | 742 | |
e4600702 RK |
743 | /* Normally we scan the insns once and determine the best class to use for |
744 | each register. However, if -fexpensive_optimizations are on, we do so | |
745 | twice, the second time using the tentative best classes to guide the | |
746 | selection. */ | |
54dac99e | 747 | |
e4600702 RK |
748 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
749 | { | |
750 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 751 | |
4c9a05bc | 752 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 753 | |
533d0835 RK |
754 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
755 | bzero (in_inc_dec, nregs); | |
756 | #endif | |
757 | ||
e4600702 RK |
758 | loop_depth = 0, loop_cost = 1; |
759 | ||
760 | /* Scan the instructions and record each time it would | |
761 | save code to put a certain register in a certain class. */ | |
762 | ||
763 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 764 | { |
e4600702 RK |
765 | char *constraints[MAX_RECOG_OPERANDS]; |
766 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
767 | int nalternatives; | |
768 | int noperands; | |
769 | ||
770 | /* Show that an insn inside a loop is likely to be executed three | |
ac2a9454 | 771 | times more than insns outside a loop. This is much more aggressive |
e4600702 RK |
772 | than the assumptions made elsewhere and is being tried as an |
773 | experiment. */ | |
774 | ||
775 | if (GET_CODE (insn) == NOTE | |
776 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
777 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
778 | else if (GET_CODE (insn) == NOTE | |
779 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
780 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
781 | ||
782 | else if ((GET_CODE (insn) == INSN | |
783 | && GET_CODE (PATTERN (insn)) != USE | |
784 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
785 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) | |
786 | || (GET_CODE (insn) == JUMP_INSN | |
787 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
788 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
789 | || GET_CODE (insn) == CALL_INSN) | |
54dac99e | 790 | { |
e4600702 RK |
791 | if (GET_CODE (insn) == INSN |
792 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) | |
793 | { | |
37366632 | 794 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, |
e4600702 | 795 | constraints, modes); |
e5ed2155 TW |
796 | nalternatives = (noperands == 0 ? 0 |
797 | : n_occurrences (',', constraints[0]) + 1); | |
e4600702 RK |
798 | } |
799 | else | |
800 | { | |
801 | int insn_code_number = recog_memoized (insn); | |
802 | rtx note; | |
54dac99e | 803 | |
e4600702 RK |
804 | set = single_set (insn); |
805 | insn_extract (insn); | |
54dac99e | 806 | |
e4600702 RK |
807 | nalternatives = insn_n_alternatives[insn_code_number]; |
808 | noperands = insn_n_operands[insn_code_number]; | |
54dac99e | 809 | |
e4600702 RK |
810 | /* If this insn loads a parameter from its stack slot, then |
811 | it represents a savings, rather than a cost, if the | |
812 | parameter is stored in memory. Record this fact. */ | |
54dac99e | 813 | |
e4600702 RK |
814 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
815 | && GET_CODE (SET_SRC (set)) == MEM | |
37366632 RK |
816 | && (note = find_reg_note (insn, REG_EQUIV, |
817 | NULL_RTX)) != 0 | |
e4600702 RK |
818 | && GET_CODE (XEXP (note, 0)) == MEM) |
819 | { | |
820 | costs[REGNO (SET_DEST (set))].mem_cost | |
cbd5b9a2 KR |
821 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), |
822 | GENERAL_REGS, 1) | |
e4600702 RK |
823 | * loop_cost); |
824 | record_address_regs (XEXP (SET_SRC (set), 0), | |
825 | BASE_REG_CLASS, loop_cost * 2); | |
826 | continue; | |
827 | } | |
828 | ||
829 | /* Improve handling of two-address insns such as | |
830 | (set X (ashift CONST Y)) where CONST must be made to | |
831 | match X. Change it into two insns: (set X CONST) | |
832 | (set X (ashift X Y)). If we left this for reloading, it | |
833 | would probably get three insns because X and Y might go | |
834 | in the same place. This prevents X and Y from receiving | |
835 | the same hard reg. | |
836 | ||
837 | We can only do this if the modes of operands 0 and 1 | |
838 | (which might not be the same) are tieable and we only need | |
839 | do this during our first pass. */ | |
840 | ||
841 | if (pass == 0 && optimize | |
842 | && noperands >= 3 | |
843 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
844 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
845 | && CONSTANT_P (recog_operand[1]) | |
846 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
847 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
848 | && GET_CODE (recog_operand[0]) == REG | |
849 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
850 | insn_operand_mode[insn_code_number][1])) | |
851 | { | |
852 | rtx previnsn = prev_real_insn (insn); | |
853 | rtx dest | |
854 | = gen_lowpart (insn_operand_mode[insn_code_number][1], | |
855 | recog_operand[0]); | |
856 | rtx newinsn | |
857 | = emit_insn_before (gen_move_insn (dest, | |
858 | recog_operand[1]), | |
859 | insn); | |
860 | ||
861 | /* If this insn was the start of a basic block, | |
61b01243 RS |
862 | include the new insn in that block. |
863 | We need not check for code_label here; | |
864 | while a basic block can start with a code_label, | |
865 | INSN could not be at the beginning of that block. */ | |
e4600702 RK |
866 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) |
867 | { | |
868 | int b; | |
869 | for (b = 0; b < n_basic_blocks; b++) | |
870 | if (insn == basic_block_head[b]) | |
871 | basic_block_head[b] = newinsn; | |
872 | } | |
873 | ||
0f41302f | 874 | /* This makes one more setting of new insns's dest. */ |
b1f21e0a | 875 | REG_N_SETS (REGNO (recog_operand[0]))++; |
e4600702 | 876 | |
20912ad0 RK |
877 | *recog_operand_loc[1] = recog_operand[0]; |
878 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
879 | if (recog_dup_num[i] == 1) | |
880 | *recog_dup_loc[i] = recog_operand[0]; | |
881 | ||
e4600702 RK |
882 | insn = PREV_INSN (newinsn); |
883 | continue; | |
884 | } | |
54dac99e | 885 | |
e4600702 RK |
886 | for (i = 0; i < noperands; i++) |
887 | { | |
888 | constraints[i] | |
889 | = insn_operand_constraint[insn_code_number][i]; | |
890 | modes[i] = insn_operand_mode[insn_code_number][i]; | |
891 | } | |
892 | } | |
54dac99e | 893 | |
e4600702 RK |
894 | /* If we get here, we are set up to record the costs of all the |
895 | operands for this insn. Start by initializing the costs. | |
896 | Then handle any address registers. Finally record the desired | |
897 | classes for any pseudos, doing it twice if some pair of | |
898 | operands are commutative. */ | |
899 | ||
900 | for (i = 0; i < noperands; i++) | |
54dac99e | 901 | { |
e4600702 RK |
902 | op_costs[i] = init_cost; |
903 | ||
904 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
905 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
906 | ||
907 | if (GET_CODE (recog_operand[i]) == MEM) | |
908 | record_address_regs (XEXP (recog_operand[i], 0), | |
909 | BASE_REG_CLASS, loop_cost * 2); | |
910 | else if (constraints[i][0] == 'p') | |
911 | record_address_regs (recog_operand[i], | |
912 | BASE_REG_CLASS, loop_cost * 2); | |
54dac99e | 913 | } |
e4600702 RK |
914 | |
915 | /* Check for commutative in a separate loop so everything will | |
cc4c133a RS |
916 | have been initialized. We must do this even if one operand |
917 | is a constant--see addsi3 in m68k.md. */ | |
54dac99e | 918 | |
e5ed2155 | 919 | for (i = 0; i < noperands - 1; i++) |
cc4c133a | 920 | if (constraints[i][0] == '%') |
e4600702 RK |
921 | { |
922 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
923 | int j; | |
924 | ||
925 | /* Handle commutative operands by swapping the constraints. | |
926 | We assume the modes are the same. */ | |
927 | ||
928 | for (j = 0; j < noperands; j++) | |
929 | xconstraints[j] = constraints[j]; | |
930 | ||
931 | xconstraints[i] = constraints[i+1]; | |
932 | xconstraints[i+1] = constraints[i]; | |
933 | record_reg_classes (nalternatives, noperands, | |
934 | recog_operand, modes, xconstraints, | |
54dac99e | 935 | insn); |
e4600702 | 936 | } |
54dac99e | 937 | |
e4600702 RK |
938 | record_reg_classes (nalternatives, noperands, recog_operand, |
939 | modes, constraints, insn); | |
54dac99e | 940 | |
e4600702 RK |
941 | /* Now add the cost for each operand to the total costs for |
942 | its register. */ | |
54dac99e | 943 | |
e4600702 RK |
944 | for (i = 0; i < noperands; i++) |
945 | if (GET_CODE (recog_operand[i]) == REG | |
946 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
947 | { | |
948 | int regno = REGNO (recog_operand[i]); | |
949 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
950 | ||
951 | p->mem_cost += q->mem_cost * loop_cost; | |
952 | for (j = 0; j < N_REG_CLASSES; j++) | |
953 | p->cost[j] += q->cost[j] * loop_cost; | |
954 | } | |
54dac99e RK |
955 | } |
956 | } | |
54dac99e | 957 | |
e4600702 RK |
958 | /* Now for each register look at how desirable each class is |
959 | and find which class is preferred. Store that in | |
960 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
961 | class any of whose registers is better than memory. */ | |
54dac99e | 962 | |
e4600702 RK |
963 | if (pass == 0) |
964 | { | |
965 | prefclass = (char *) oballoc (nregs); | |
966 | altclass = (char *) oballoc (nregs); | |
967 | } | |
54dac99e | 968 | |
e4600702 | 969 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 970 | { |
ca3c6eae | 971 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
972 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
973 | /* This is an enum reg_class, but we call it an int | |
974 | to save lots of casts. */ | |
975 | register int class; | |
976 | register struct costs *p = &costs[i]; | |
977 | ||
978 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 979 | { |
533d0835 RK |
980 | /* Ignore classes that are too small for this operand or |
981 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 982 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
983 | > reg_class_size[class] |
984 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
985 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
986 | #endif | |
987 | ) | |
e4600702 RK |
988 | ; |
989 | else if (p->cost[class] < best_cost) | |
990 | { | |
991 | best_cost = p->cost[class]; | |
992 | best = (enum reg_class) class; | |
993 | } | |
994 | else if (p->cost[class] == best_cost) | |
995 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 996 | } |
54dac99e | 997 | |
e4600702 RK |
998 | /* Record the alternate register class; i.e., a class for which |
999 | every register in it is better than using memory. If adding a | |
1000 | class would make a smaller class (i.e., no union of just those | |
1001 | classes exists), skip that class. The major unions of classes | |
1002 | should be provided as a register class. Don't do this if we | |
1003 | will be doing it again later. */ | |
1004 | ||
1005 | if (pass == 1 || ! flag_expensive_optimizations) | |
1006 | for (class = 0; class < N_REG_CLASSES; class++) | |
1007 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1008 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1009 | > reg_class_size[(int) alt]) |
1010 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1011 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1012 | #endif | |
1013 | ) | |
e4600702 RK |
1014 | alt = reg_class_subunion[(int) alt][class]; |
1015 | ||
1016 | /* If we don't add any classes, nothing to try. */ | |
1017 | if (alt == best) | |
995d54dd | 1018 | alt = NO_REGS; |
e4600702 RK |
1019 | |
1020 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
1021 | prefclass[i] = (int) best; | |
1022 | altclass[i] = (int) alt; | |
1023 | } | |
54dac99e RK |
1024 | } |
1025 | #endif /* REGISTER_CONSTRAINTS */ | |
1026 | } | |
1027 | \f | |
1028 | #ifdef REGISTER_CONSTRAINTS | |
1029 | ||
e4600702 RK |
1030 | /* Record the cost of using memory or registers of various classes for |
1031 | the operands in INSN. | |
54dac99e | 1032 | |
e4600702 | 1033 | N_ALTS is the number of alternatives. |
54dac99e | 1034 | |
e4600702 RK |
1035 | N_OPS is the number of operands. |
1036 | ||
1037 | OPS is an array of the operands. | |
1038 | ||
1039 | MODES are the modes of the operands, in case any are VOIDmode. | |
1040 | ||
1041 | CONSTRAINTS are the constraints to use for the operands. This array | |
1042 | is modified by this procedure. | |
1043 | ||
1044 | This procedure works alternative by alternative. For each alternative | |
1045 | we assume that we will be able to allocate all pseudos to their ideal | |
1046 | register class and calculate the cost of using that alternative. Then | |
1047 | we compute for each operand that is a pseudo-register, the cost of | |
1048 | having the pseudo allocated to each register class and using it in that | |
1049 | alternative. To this cost is added the cost of the alternative. | |
1050 | ||
1051 | The cost of each class for this insn is its lowest cost among all the | |
1052 | alternatives. */ | |
1053 | ||
1054 | static void | |
1055 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
1056 | int n_alts; | |
1057 | int n_ops; | |
1058 | rtx *ops; | |
1059 | enum machine_mode *modes; | |
54dac99e | 1060 | char **constraints; |
e4600702 | 1061 | rtx insn; |
54dac99e | 1062 | { |
e4600702 RK |
1063 | int alt; |
1064 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; | |
1065 | int i, j; | |
ec2d92af | 1066 | rtx set; |
e4600702 RK |
1067 | |
1068 | /* By default, each operand is an input operand. */ | |
1069 | ||
1070 | for (i = 0; i < n_ops; i++) | |
1071 | op_types[i] = OP_READ; | |
54dac99e | 1072 | |
e4600702 RK |
1073 | /* Process each alternative, each time minimizing an operand's cost with |
1074 | the cost for each operand in that alternative. */ | |
54dac99e | 1075 | |
e4600702 | 1076 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1077 | { |
e4600702 RK |
1078 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1079 | int alt_fail = 0; | |
1080 | int alt_cost = 0; | |
1081 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
1082 | int class; | |
54dac99e | 1083 | |
e4600702 RK |
1084 | for (i = 0; i < n_ops; i++) |
1085 | { | |
1086 | char *p = constraints[i]; | |
1087 | rtx op = ops[i]; | |
1088 | enum machine_mode mode = modes[i]; | |
1089 | int allows_mem = 0; | |
1090 | int win = 0; | |
1091 | char c; | |
54dac99e | 1092 | |
e4600702 RK |
1093 | /* If this operand has no constraints at all, we can conclude |
1094 | nothing about it since anything is valid. */ | |
54dac99e | 1095 | |
e4600702 RK |
1096 | if (*p == 0) |
1097 | { | |
1098 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1099 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1100 | |
e4600702 RK |
1101 | continue; |
1102 | } | |
54dac99e | 1103 | |
347099d6 RS |
1104 | if (*p == '%') |
1105 | p++; | |
1106 | ||
e4600702 RK |
1107 | /* If this alternative is only relevant when this operand |
1108 | matches a previous operand, we do different things depending | |
1109 | on whether this operand is a pseudo-reg or not. */ | |
54dac99e | 1110 | |
e4600702 RK |
1111 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1112 | { | |
1113 | j = p[0] - '0'; | |
1114 | classes[i] = classes[j]; | |
1115 | ||
1116 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1117 | { | |
1118 | /* If this matches the other operand, we have no added | |
dc903608 | 1119 | cost and we win. */ |
e4600702 | 1120 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1121 | win = 1; |
e4600702 | 1122 | |
77e67eac RK |
1123 | /* If we can put the other operand into a register, add to |
1124 | the cost of this alternative the cost to copy this | |
1125 | operand to the register used for the other operand. */ | |
e4600702 | 1126 | |
dc903608 | 1127 | else if (classes[j] != NO_REGS) |
77e67eac | 1128 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1129 | } |
07d8ca2d RS |
1130 | else if (GET_CODE (ops[j]) != REG |
1131 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1132 | { | |
1133 | /* This op is a pseudo but the one it matches is not. */ | |
1134 | ||
1135 | /* If we can't put the other operand into a register, this | |
1136 | alternative can't be used. */ | |
1137 | ||
1138 | if (classes[j] == NO_REGS) | |
1139 | alt_fail = 1; | |
e4600702 | 1140 | |
07d8ca2d RS |
1141 | /* Otherwise, add to the cost of this alternative the cost |
1142 | to copy the other operand to the register used for this | |
1143 | operand. */ | |
1144 | ||
1145 | else | |
1146 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1147 | } | |
e4600702 RK |
1148 | else |
1149 | { | |
1150 | /* The costs of this operand are the same as that of the | |
1151 | other operand. However, if we cannot tie them, this | |
1152 | alternative needs to do a copy, which is one | |
1153 | instruction. */ | |
1154 | ||
1155 | this_op_costs[i] = this_op_costs[j]; | |
37747c82 RK |
1156 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1157 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1158 | alt_cost += 2; | |
e4600702 | 1159 | |
347099d6 | 1160 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1161 | for this operand, so skip to the end of the |
1162 | alternative (should be just one character). */ | |
1163 | while (*p && *p++ != ',') | |
1164 | ; | |
1165 | ||
1166 | constraints[i] = p; | |
347099d6 RS |
1167 | continue; |
1168 | } | |
e4600702 RK |
1169 | } |
1170 | ||
1171 | /* Scan all the constraint letters. See if the operand matches | |
1172 | any of the constraints. Collect the valid register classes | |
1173 | and see if this operand accepts memory. */ | |
1174 | ||
1175 | classes[i] = NO_REGS; | |
1176 | while (*p && (c = *p++) != ',') | |
1177 | switch (c) | |
1178 | { | |
1179 | case '=': | |
1180 | op_types[i] = OP_WRITE; | |
1181 | break; | |
1182 | ||
1183 | case '+': | |
1184 | op_types[i] = OP_READ_WRITE; | |
1185 | break; | |
1186 | ||
1187 | case '*': | |
1188 | /* Ignore the next letter for this pass. */ | |
1189 | p++; | |
1190 | break; | |
1191 | ||
1192 | case '%': | |
1193 | case '?': case '!': case '#': | |
1194 | case '&': | |
1195 | case '0': case '1': case '2': case '3': case '4': | |
1196 | case 'p': | |
1197 | break; | |
1198 | ||
1199 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1200 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 RK |
1201 | and non-offsettable addresses here. */ |
1202 | allows_mem = 1; | |
1203 | if (GET_CODE (op) == MEM) | |
1204 | win = 1; | |
1205 | break; | |
1206 | ||
1207 | case '<': | |
1208 | if (GET_CODE (op) == MEM | |
1209 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1210 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1211 | win = 1; | |
1212 | break; | |
1213 | ||
1214 | case '>': | |
1215 | if (GET_CODE (op) == MEM | |
1216 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1217 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1218 | win = 1; | |
1219 | break; | |
1220 | ||
1221 | case 'E': | |
7ac2547f | 1222 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1223 | /* Match any floating double constant, but only if |
1224 | we can examine the bits of it reliably. */ | |
1225 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1226 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1227 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1228 | break; | |
7ac2547f | 1229 | #endif |
e4600702 RK |
1230 | if (GET_CODE (op) == CONST_DOUBLE) |
1231 | win = 1; | |
1232 | break; | |
1233 | ||
1234 | case 'F': | |
1235 | if (GET_CODE (op) == CONST_DOUBLE) | |
1236 | win = 1; | |
1237 | break; | |
1238 | ||
1239 | case 'G': | |
1240 | case 'H': | |
1241 | if (GET_CODE (op) == CONST_DOUBLE | |
1242 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1243 | win = 1; | |
1244 | break; | |
1245 | ||
1246 | case 's': | |
1247 | if (GET_CODE (op) == CONST_INT | |
1248 | || (GET_CODE (op) == CONST_DOUBLE | |
1249 | && GET_MODE (op) == VOIDmode)) | |
1250 | break; | |
1251 | case 'i': | |
1252 | if (CONSTANT_P (op) | |
1253 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1254 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1255 | #endif | |
1256 | ) | |
1257 | win = 1; | |
1258 | break; | |
1259 | ||
1260 | case 'n': | |
1261 | if (GET_CODE (op) == CONST_INT | |
1262 | || (GET_CODE (op) == CONST_DOUBLE | |
1263 | && GET_MODE (op) == VOIDmode)) | |
1264 | win = 1; | |
1265 | break; | |
1266 | ||
1267 | case 'I': | |
1268 | case 'J': | |
1269 | case 'K': | |
1270 | case 'L': | |
1271 | case 'M': | |
1272 | case 'N': | |
1273 | case 'O': | |
1274 | case 'P': | |
1275 | if (GET_CODE (op) == CONST_INT | |
1276 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1277 | win = 1; | |
1278 | break; | |
1279 | ||
1280 | case 'X': | |
1281 | win = 1; | |
1282 | break; | |
54dac99e | 1283 | |
54dac99e | 1284 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1285 | case 'Q': |
1286 | case 'R': | |
1287 | case 'S': | |
1288 | case 'T': | |
1289 | case 'U': | |
1290 | if (EXTRA_CONSTRAINT (op, c)) | |
1291 | win = 1; | |
1292 | break; | |
1293 | #endif | |
1294 | ||
1295 | case 'g': | |
1296 | if (GET_CODE (op) == MEM | |
1297 | || (CONSTANT_P (op) | |
1298 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1299 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1300 | #endif |
e4600702 RK |
1301 | )) |
1302 | win = 1; | |
1303 | allows_mem = 1; | |
1304 | case 'r': | |
1305 | classes[i] | |
1306 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1307 | break; | |
1308 | ||
1309 | default: | |
1310 | classes[i] | |
1311 | = reg_class_subunion[(int) classes[i]] | |
1312 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1313 | } | |
1314 | ||
1315 | constraints[i] = p; | |
1316 | ||
1317 | /* How we account for this operand now depends on whether it is a | |
1318 | pseudo register or not. If it is, we first check if any | |
1319 | register classes are valid. If not, we ignore this alternative, | |
1320 | since we want to assume that all pseudos get allocated for | |
1321 | register preferencing. If some register class is valid, compute | |
1322 | the costs of moving the pseudo into that class. */ | |
1323 | ||
1324 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1325 | { |
e4600702 RK |
1326 | if (classes[i] == NO_REGS) |
1327 | alt_fail = 1; | |
1328 | else | |
1329 | { | |
1330 | struct costs *pp = &this_op_costs[i]; | |
1331 | ||
1332 | for (class = 0; class < N_REG_CLASSES; class++) | |
1333 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1334 | ||
1335 | /* If the alternative actually allows memory, make things | |
1336 | a bit cheaper since we won't need an extra insn to | |
1337 | load it. */ | |
1338 | ||
cbd5b9a2 KR |
1339 | pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) |
1340 | - allows_mem); | |
e4600702 RK |
1341 | |
1342 | /* If we have assigned a class to this register in our | |
1343 | first pass, add a cost to this alternative corresponding | |
1344 | to what we would add if this register were not in the | |
1345 | appropriate class. */ | |
1346 | ||
1347 | if (prefclass) | |
1348 | alt_cost | |
1349 | += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; | |
1350 | } | |
4db18574 | 1351 | } |
54dac99e | 1352 | |
e4600702 RK |
1353 | /* Otherwise, if this alternative wins, either because we |
1354 | have already determined that or if we have a hard register of | |
1355 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1356 | |
e4600702 RK |
1357 | else if (win |
1358 | || (GET_CODE (op) == REG | |
6f654776 | 1359 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1360 | ; |
54dac99e | 1361 | |
e4600702 RK |
1362 | /* If registers are valid, the cost of this alternative includes |
1363 | copying the object to and/or from a register. */ | |
54dac99e | 1364 | |
e4600702 RK |
1365 | else if (classes[i] != NO_REGS) |
1366 | { | |
1367 | if (op_types[i] != OP_WRITE) | |
1368 | alt_cost += copy_cost (op, mode, classes[i], 1); | |
54dac99e | 1369 | |
e4600702 RK |
1370 | if (op_types[i] != OP_READ) |
1371 | alt_cost += copy_cost (op, mode, classes[i], 0); | |
1372 | } | |
54dac99e | 1373 | |
e4600702 RK |
1374 | /* The only other way this alternative can be used is if this is a |
1375 | constant that could be placed into memory. */ | |
1376 | ||
1377 | else if (CONSTANT_P (op) && allows_mem) | |
cbd5b9a2 | 1378 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1379 | else |
1380 | alt_fail = 1; | |
1381 | } | |
1382 | ||
1383 | if (alt_fail) | |
1384 | continue; | |
1385 | ||
1386 | /* Finally, update the costs with the information we've calculated | |
1387 | about this alternative. */ | |
1388 | ||
1389 | for (i = 0; i < n_ops; i++) | |
1390 | if (GET_CODE (ops[i]) == REG | |
1391 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1392 | { |
e4600702 RK |
1393 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1394 | int scale = 1 + (op_types[i] == OP_READ_WRITE); | |
54dac99e | 1395 | |
e4600702 RK |
1396 | pp->mem_cost = MIN (pp->mem_cost, |
1397 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1398 | |
e4600702 RK |
1399 | for (class = 0; class < N_REG_CLASSES; class++) |
1400 | pp->cost[class] = MIN (pp->cost[class], | |
1401 | (qq->cost[class] + alt_cost) * scale); | |
1402 | } | |
1403 | } | |
ec2d92af RK |
1404 | |
1405 | /* If this insn is a single set copying operand 1 to operand 0 | |
1406 | and one is a pseudo with the other a hard reg that is in its | |
1407 | own register class, set the cost of that register class to -1. */ | |
1408 | ||
1409 | if ((set = single_set (insn)) != 0 | |
1410 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1411 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1412 | for (i = 0; i <= 1; i++) | |
1413 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1414 | { | |
1415 | int regno = REGNO (ops[!i]); | |
1416 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1417 | int class; | |
4841ba4b | 1418 | int nr; |
ec2d92af RK |
1419 | |
1420 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 | |
1421 | && (reg_class_size[prefclass[regno]] | |
1422 | == CLASS_MAX_NREGS (prefclass[regno], mode))) | |
1423 | op_costs[i].cost[prefclass[regno]] = -1; | |
1424 | else if (regno < FIRST_PSEUDO_REGISTER) | |
1425 | for (class = 0; class < N_REG_CLASSES; class++) | |
1426 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1427 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1428 | { |
1429 | if (reg_class_size[class] == 1) | |
1430 | op_costs[i].cost[class] = -1; | |
1431 | else | |
1432 | { | |
1433 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1434 | { | |
1435 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1436 | break; | |
1437 | } | |
1438 | ||
1439 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1440 | op_costs[i].cost[class] = -1; | |
1441 | } | |
1442 | } | |
ec2d92af | 1443 | } |
54dac99e | 1444 | } |
e4600702 RK |
1445 | \f |
1446 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1447 | TO_P is zero) a register of class CLASS in mode MODE. | |
1448 | ||
1449 | X must not be a pseudo. */ | |
1450 | ||
1451 | static int | |
1452 | copy_cost (x, mode, class, to_p) | |
1453 | rtx x; | |
1454 | enum machine_mode mode; | |
1455 | enum reg_class class; | |
1456 | int to_p; | |
1457 | { | |
29a82058 | 1458 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1459 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1460 | #endif |
e4600702 RK |
1461 | |
1462 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1463 | assuming optimal allocation. */ | |
1464 | ||
1465 | if (GET_CODE (x) == SCRATCH) | |
1466 | return 0; | |
1467 | ||
1468 | /* Get the class we will actually use for a reload. */ | |
1469 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1470 | ||
1471 | #ifdef HAVE_SECONDARY_RELOADS | |
1472 | /* If we need a secondary reload (we assume here that we are using | |
1473 | the secondary reload as an intermediate, not a scratch register), the | |
1474 | cost is that to load the input into the intermediate register, then | |
1475 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1476 | ||
1477 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1478 | if (to_p == 1) | |
1479 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1480 | #endif | |
1481 | ||
dd9f0e8f | 1482 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1483 | if (! to_p) |
1484 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1485 | #endif | |
1486 | ||
1487 | if (secondary_class != NO_REGS) | |
1488 | return (move_cost[(int) secondary_class][(int) class] | |
1489 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1490 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1491 | |
1492 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1493 | cost to move between the register classes, and use 2 for everything | |
1494 | else (constants). */ | |
1495 | ||
1496 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1497 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1498 | |
e4600702 RK |
1499 | else if (GET_CODE (x) == REG) |
1500 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1501 | ||
1502 | else | |
1503 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1504 | return 2; | |
1505 | } | |
1506 | \f | |
54dac99e RK |
1507 | /* Record the pseudo registers we must reload into hard registers |
1508 | in a subexpression of a memory address, X. | |
e4600702 RK |
1509 | |
1510 | CLASS is the class that the register needs to be in and is either | |
1511 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1512 | ||
1513 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1514 | can represent half-cost adjustments). */ | |
54dac99e | 1515 | |
197d6480 | 1516 | static void |
e4600702 | 1517 | record_address_regs (x, class, scale) |
54dac99e | 1518 | rtx x; |
e4600702 RK |
1519 | enum reg_class class; |
1520 | int scale; | |
54dac99e RK |
1521 | { |
1522 | register enum rtx_code code = GET_CODE (x); | |
1523 | ||
1524 | switch (code) | |
1525 | { | |
1526 | case CONST_INT: | |
1527 | case CONST: | |
1528 | case CC0: | |
1529 | case PC: | |
1530 | case SYMBOL_REF: | |
1531 | case LABEL_REF: | |
1532 | return; | |
1533 | ||
1534 | case PLUS: | |
1535 | /* When we have an address that is a sum, | |
1536 | we must determine whether registers are "base" or "index" regs. | |
1537 | If there is a sum of two registers, we must choose one to be | |
1538 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1539 | to make a good choice most of the time. We only need to do this |
1540 | on machines that can have two registers in an address and where | |
1541 | the base and index register classes are different. | |
1542 | ||
1543 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1544 | that seems bogus since it should only be set when we are sure | |
1545 | the register is being used as a pointer. */ | |
1546 | ||
54dac99e RK |
1547 | { |
1548 | rtx arg0 = XEXP (x, 0); | |
1549 | rtx arg1 = XEXP (x, 1); | |
1550 | register enum rtx_code code0 = GET_CODE (arg0); | |
1551 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1552 | |
1553 | /* Look inside subregs. */ | |
e4600702 | 1554 | if (code0 == SUBREG) |
54dac99e | 1555 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1556 | if (code1 == SUBREG) |
54dac99e RK |
1557 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1558 | ||
e4600702 RK |
1559 | /* If this machine only allows one register per address, it must |
1560 | be in the first operand. */ | |
1561 | ||
1562 | if (MAX_REGS_PER_ADDRESS == 1) | |
1563 | record_address_regs (arg0, class, scale); | |
1564 | ||
1565 | /* If index and base registers are the same on this machine, just | |
1566 | record registers in any non-constant operands. We assume here, | |
1567 | as well as in the tests below, that all addresses are in | |
1568 | canonical form. */ | |
1569 | ||
1570 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1571 | { |
e4600702 RK |
1572 | record_address_regs (arg0, class, scale); |
1573 | if (! CONSTANT_P (arg1)) | |
1574 | record_address_regs (arg1, class, scale); | |
54dac99e | 1575 | } |
e4600702 RK |
1576 | |
1577 | /* If the second operand is a constant integer, it doesn't change | |
1578 | what class the first operand must be. */ | |
1579 | ||
1580 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1581 | record_address_regs (arg0, class, scale); | |
1582 | ||
1583 | /* If the second operand is a symbolic constant, the first operand | |
1584 | must be an index register. */ | |
1585 | ||
1586 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1587 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1588 | ||
956d6950 JL |
1589 | /* If both operands are registers but one is already a hard register |
1590 | of index or base class, give the other the class that the hard | |
1591 | register is not. */ | |
1592 | ||
3f9e9508 | 1593 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1594 | else if (code0 == REG && code1 == REG |
1595 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1596 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1597 | record_address_regs (arg1, | |
1598 | REG_OK_FOR_BASE_P (arg0) | |
1599 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1600 | scale); | |
1601 | else if (code0 == REG && code1 == REG | |
1602 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1603 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1604 | record_address_regs (arg0, | |
1605 | REG_OK_FOR_BASE_P (arg1) | |
1606 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1607 | scale); | |
3f9e9508 | 1608 | #endif |
956d6950 | 1609 | |
e9a25f70 JL |
1610 | /* If one operand is known to be a pointer, it must be the base |
1611 | with the other operand the index. Likewise if the other operand | |
1612 | is a MULT. */ | |
f22376c7 | 1613 | |
e9a25f70 JL |
1614 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1615 | || code1 == MULT) | |
f22376c7 CI |
1616 | { |
1617 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1618 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1619 | } | |
e9a25f70 JL |
1620 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1621 | || code0 == MULT) | |
f22376c7 CI |
1622 | { |
1623 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1624 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1625 | } | |
1626 | ||
e9a25f70 | 1627 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1628 | or index register. This case should be rare. */ |
1629 | ||
e9a25f70 | 1630 | else |
54dac99e | 1631 | { |
e4600702 RK |
1632 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1633 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1634 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1635 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1636 | } |
54dac99e RK |
1637 | } |
1638 | break; | |
1639 | ||
1640 | case POST_INC: | |
1641 | case PRE_INC: | |
1642 | case POST_DEC: | |
1643 | case PRE_DEC: | |
1644 | /* Double the importance of a pseudo register that is incremented | |
1645 | or decremented, since it would take two extra insns | |
533d0835 RK |
1646 | if it ends up in the wrong place. If the operand is a pseudo, |
1647 | show it is being used in an INC_DEC context. */ | |
1648 | ||
1649 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1650 | if (GET_CODE (XEXP (x, 0)) == REG | |
1651 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1652 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1653 | #endif | |
e4600702 RK |
1654 | |
1655 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1656 | break; |
1657 | ||
1658 | case REG: | |
1659 | { | |
e4600702 RK |
1660 | register struct costs *pp = &costs[REGNO (x)]; |
1661 | register int i; | |
54dac99e | 1662 | |
cbd5b9a2 | 1663 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1664 | |
e4600702 RK |
1665 | for (i = 0; i < N_REG_CLASSES; i++) |
1666 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1667 | } |
1668 | break; | |
1669 | ||
1670 | default: | |
1671 | { | |
1672 | register char *fmt = GET_RTX_FORMAT (code); | |
1673 | register int i; | |
1674 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1675 | if (fmt[i] == 'e') | |
e4600702 | 1676 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1677 | } |
1678 | } | |
1679 | } | |
08d95f91 RK |
1680 | \f |
1681 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1682 | ||
1683 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1684 | to an object of MODE. */ | |
1685 | ||
1d300e19 | 1686 | static int |
08d95f91 RK |
1687 | auto_inc_dec_reg_p (reg, mode) |
1688 | rtx reg; | |
1689 | enum machine_mode mode; | |
1690 | { | |
1691 | #ifdef HAVE_POST_INCREMENT | |
38a448ca | 1692 | if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) |
08d95f91 RK |
1693 | return 1; |
1694 | #endif | |
1695 | ||
1696 | #ifdef HAVE_POST_DECREMENT | |
38a448ca | 1697 | if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) |
08d95f91 RK |
1698 | return 1; |
1699 | #endif | |
1700 | ||
1701 | #ifdef HAVE_PRE_INCREMENT | |
38a448ca | 1702 | if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) |
08d95f91 RK |
1703 | return 1; |
1704 | #endif | |
1705 | ||
1706 | #ifdef HAVE_PRE_DECREMENT | |
38a448ca | 1707 | if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) |
08d95f91 RK |
1708 | return 1; |
1709 | #endif | |
1710 | ||
1711 | return 0; | |
1712 | } | |
1713 | #endif | |
1714 | ||
54dac99e | 1715 | #endif /* REGISTER_CONSTRAINTS */ |
b1f21e0a MM |
1716 | \f |
1717 | /* Allocate enough space to hold NUM_REGS registers for the tables used for | |
1718 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1719 | NEW_P is non zero, initialize all of the registers, otherwise only |
1720 | initialize the new registers allocated. The same table is kept from | |
1721 | function to function, only reallocating it when we need more room. If | |
1722 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1723 | |
1724 | void | |
39379e67 | 1725 | allocate_reg_info (num_regs, new_p, renumber_p) |
b1f21e0a MM |
1726 | int num_regs; |
1727 | int new_p; | |
39379e67 | 1728 | int renumber_p; |
b1f21e0a MM |
1729 | { |
1730 | static int regno_allocated = 0; | |
1731 | static int regno_max = 0; | |
39379e67 | 1732 | static short *renumber = (short *)0; |
b1f21e0a | 1733 | int i; |
39379e67 MM |
1734 | int size_info; |
1735 | int size_renumber; | |
7ec189f2 | 1736 | int min = (new_p) ? 0 : regno_max; |
b1f21e0a | 1737 | |
39379e67 MM |
1738 | /* If this message come up, and you want to fix it, then all of the tables |
1739 | like reg_renumber, etc. that use short will have to be found and lengthed | |
1740 | to int or HOST_WIDE_INT. */ | |
1741 | ||
1742 | /* Free up all storage allocated */ | |
1743 | if (num_regs < 0) | |
1744 | { | |
1745 | if (reg_n_info) | |
1746 | { | |
1747 | free ((char *)reg_n_info); | |
1748 | free ((char *)renumber); | |
1749 | reg_n_info = (reg_info *)0; | |
1750 | renumber = (short *)0; | |
1751 | } | |
1752 | regno_allocated = 0; | |
1753 | regno_max = 0; | |
1754 | return; | |
1755 | } | |
1756 | ||
b1f21e0a MM |
1757 | if (num_regs > regno_allocated) |
1758 | { | |
1759 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ | |
39379e67 MM |
1760 | size_info = regno_allocated * sizeof (reg_info); |
1761 | size_renumber = regno_allocated * sizeof (short); | |
1762 | ||
1763 | if (!reg_n_info) | |
1764 | { | |
1765 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1766 | renumber = (short *) xmalloc (size_renumber); | |
1767 | } | |
1768 | ||
1769 | else if (new_p) /* if we're zapping everything, no need to realloc */ | |
1770 | { | |
1771 | free ((char *)reg_n_info); | |
1772 | free ((char *)renumber); | |
1773 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1774 | renumber = (short *) xmalloc (size_renumber); | |
1775 | } | |
1776 | ||
1777 | else | |
1778 | { | |
1779 | reg_n_info = (reg_info *) xrealloc ((char *)reg_n_info, size_info); | |
1780 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
1781 | } | |
b1f21e0a MM |
1782 | } |
1783 | ||
1784 | if (min < num_regs) | |
1785 | { | |
1786 | bzero ((char *) ®_n_info[min], (num_regs - min) * sizeof (reg_info)); | |
1787 | for (i = min; i < num_regs; i++) | |
39379e67 MM |
1788 | { |
1789 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
1790 | renumber[i] = -1; | |
1791 | } | |
b1f21e0a MM |
1792 | } |
1793 | ||
39379e67 MM |
1794 | if (renumber_p) |
1795 | reg_renumber = renumber; | |
1796 | ||
73b76448 RK |
1797 | /* Tell the regset code about the new number of registers */ |
1798 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
1799 | ||
b1f21e0a MM |
1800 | regno_max = num_regs; |
1801 | } | |
1802 | ||
54dac99e RK |
1803 | \f |
1804 | /* This is the `regscan' pass of the compiler, run just before cse | |
1805 | and again just before loop. | |
1806 | ||
1807 | It finds the first and last use of each pseudo-register | |
1808 | and records them in the vectors regno_first_uid, regno_last_uid | |
1809 | and counts the number of sets in the vector reg_n_sets. | |
1810 | ||
1811 | REPEAT is nonzero the second time this is called. */ | |
1812 | ||
54dac99e | 1813 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 1814 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
1815 | and we want this to remain correct for all the remaining passes. */ |
1816 | ||
1817 | int max_parallel; | |
1818 | ||
54dac99e RK |
1819 | void |
1820 | reg_scan (f, nregs, repeat) | |
1821 | rtx f; | |
1822 | int nregs; | |
1823 | int repeat; | |
1824 | { | |
1825 | register rtx insn; | |
1826 | ||
39379e67 | 1827 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
1828 | max_parallel = 3; |
1829 | ||
1830 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1831 | if (GET_CODE (insn) == INSN | |
1832 | || GET_CODE (insn) == CALL_INSN | |
1833 | || GET_CODE (insn) == JUMP_INSN) | |
1834 | { | |
1835 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1836 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1837 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
1ebecb64 | 1838 | reg_scan_mark_refs (PATTERN (insn), insn, 0); |
01565a55 RK |
1839 | |
1840 | if (REG_NOTES (insn)) | |
1841 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1); | |
54dac99e RK |
1842 | } |
1843 | } | |
1844 | ||
1ebecb64 RS |
1845 | /* X is the expression to scan. INSN is the insn it appears in. |
1846 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ | |
1847 | ||
08d95f91 | 1848 | static void |
1ebecb64 | 1849 | reg_scan_mark_refs (x, insn, note_flag) |
54dac99e | 1850 | rtx x; |
be8dcd74 | 1851 | rtx insn; |
1ebecb64 | 1852 | int note_flag; |
54dac99e RK |
1853 | { |
1854 | register enum rtx_code code = GET_CODE (x); | |
1855 | register rtx dest; | |
be8dcd74 | 1856 | register rtx note; |
54dac99e RK |
1857 | |
1858 | switch (code) | |
1859 | { | |
1860 | case CONST_INT: | |
1861 | case CONST: | |
1862 | case CONST_DOUBLE: | |
1863 | case CC0: | |
1864 | case PC: | |
1865 | case SYMBOL_REF: | |
1866 | case LABEL_REF: | |
1867 | case ADDR_VEC: | |
1868 | case ADDR_DIFF_VEC: | |
1869 | return; | |
1870 | ||
1871 | case REG: | |
1872 | { | |
1873 | register int regno = REGNO (x); | |
1874 | ||
b1f21e0a | 1875 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); |
1ebecb64 | 1876 | if (!note_flag) |
b1f21e0a MM |
1877 | REGNO_LAST_UID (regno) = INSN_UID (insn); |
1878 | if (REGNO_FIRST_UID (regno) == 0) | |
1879 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
54dac99e RK |
1880 | } |
1881 | break; | |
1882 | ||
01565a55 | 1883 | case EXPR_LIST: |
7b18c3db RS |
1884 | if (XEXP (x, 0)) |
1885 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); | |
01565a55 RK |
1886 | if (XEXP (x, 1)) |
1887 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1888 | break; | |
1889 | ||
1890 | case INSN_LIST: | |
1891 | if (XEXP (x, 1)) | |
1892 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1893 | break; | |
1894 | ||
54dac99e RK |
1895 | case SET: |
1896 | /* Count a set of the destination if it is a register. */ | |
1897 | for (dest = SET_DEST (x); | |
1898 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
1899 | || GET_CODE (dest) == ZERO_EXTEND; | |
1900 | dest = XEXP (dest, 0)) | |
1901 | ; | |
1902 | ||
1903 | if (GET_CODE (dest) == REG) | |
b1f21e0a | 1904 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 1905 | |
be8dcd74 RK |
1906 | /* If this is setting a pseudo from another pseudo or the sum of a |
1907 | pseudo and a constant integer and the other pseudo is known to be | |
1908 | a pointer, set the destination to be a pointer as well. | |
1909 | ||
1910 | Likewise if it is setting the destination from an address or from a | |
1911 | value equivalent to an address or to the sum of an address and | |
1912 | something else. | |
1913 | ||
1914 | But don't do any of this if the pseudo corresponds to a user | |
1915 | variable since it should have already been set as a pointer based | |
1916 | on the type. */ | |
1917 | ||
1918 | if (GET_CODE (SET_DEST (x)) == REG | |
1919 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
1920 | && ! REG_USERVAR_P (SET_DEST (x)) | |
1921 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
1922 | && ((GET_CODE (SET_SRC (x)) == REG | |
1923 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
1924 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1925 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1926 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
1927 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
1928 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
1929 | || GET_CODE (SET_SRC (x)) == CONST | |
1930 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
1931 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
1932 | || (GET_CODE (SET_SRC (x)) == HIGH | |
1933 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
1934 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
1935 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
1936 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1937 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1938 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
1939 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
1940 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
1941 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
1942 | && (GET_CODE (XEXP (note, 0)) == CONST | |
1943 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
1944 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
1945 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
1946 | ||
0f41302f | 1947 | /* ... fall through ... */ |
54dac99e RK |
1948 | |
1949 | default: | |
1950 | { | |
1951 | register char *fmt = GET_RTX_FORMAT (code); | |
1952 | register int i; | |
1953 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1954 | { | |
1955 | if (fmt[i] == 'e') | |
1ebecb64 | 1956 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag); |
54dac99e RK |
1957 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
1958 | { | |
1959 | register int j; | |
1960 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1ebecb64 | 1961 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); |
54dac99e RK |
1962 | } |
1963 | } | |
1964 | } | |
1965 | } | |
1966 | } | |
1967 | \f | |
1968 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
1969 | is also in C2. */ | |
1970 | ||
1971 | int | |
1972 | reg_class_subset_p (c1, c2) | |
1973 | register enum reg_class c1; | |
1974 | register enum reg_class c2; | |
1975 | { | |
1976 | if (c1 == c2) return 1; | |
1977 | ||
1978 | if (c2 == ALL_REGS) | |
1979 | win: | |
1980 | return 1; | |
1981 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
1982 | reg_class_contents[(int)c2], | |
1983 | win); | |
1984 | return 0; | |
1985 | } | |
1986 | ||
1987 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
1988 | ||
1989 | int | |
1990 | reg_classes_intersect_p (c1, c2) | |
1991 | register enum reg_class c1; | |
1992 | register enum reg_class c2; | |
1993 | { | |
1994 | #ifdef HARD_REG_SET | |
1995 | register | |
1996 | #endif | |
1997 | HARD_REG_SET c; | |
1998 | ||
1999 | if (c1 == c2) return 1; | |
2000 | ||
2001 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2002 | return 1; | |
2003 | ||
2004 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2005 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2006 | ||
2007 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2008 | return 1; | |
2009 | ||
2010 | lose: | |
2011 | return 0; | |
2012 | } | |
2013 | ||
73b76448 RK |
2014 | /* Release any memory allocated by register sets. */ |
2015 | ||
2016 | void | |
2017 | regset_release_memory () | |
2018 | { | |
2019 | if (basic_block_live_at_start) | |
2020 | { | |
2021 | free_regset_vector (basic_block_live_at_start, n_basic_blocks); | |
2022 | basic_block_live_at_start = 0; | |
2023 | } | |
2024 | ||
2025 | FREE_REG_SET (regs_live_at_setjmp); | |
2026 | bitmap_release_memory (); | |
2027 | } |