]>
Commit | Line | Data |
---|---|---|
54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
29a82058 | 2 | Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
670ee920 | 27 | #include "system.h" |
54dac99e RK |
28 | #include "rtl.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "flags.h" | |
31 | #include "basic-block.h" | |
32 | #include "regs.h" | |
33 | #include "insn-config.h" | |
34 | #include "recog.h" | |
e4600702 RK |
35 | #include "reload.h" |
36 | #include "real.h" | |
54dac99e RK |
37 | |
38 | #ifndef REGISTER_MOVE_COST | |
39 | #define REGISTER_MOVE_COST(x, y) 2 | |
40 | #endif | |
41 | ||
533d0835 RK |
42 | /* If we have auto-increment or auto-decrement and we can have secondary |
43 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 44 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
45 | |
46 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 47 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
48 | #define FORBIDDEN_INC_DEC_CLASSES |
49 | #endif | |
50 | #endif | |
54dac99e RK |
51 | \f |
52 | /* Register tables used by many passes. */ | |
53 | ||
54 | /* Indexed by hard register number, contains 1 for registers | |
55 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
56 | These are the registers that cannot be used to allocate | |
57 | a pseudo reg whose life does not cross calls. */ | |
58 | ||
59 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
60 | ||
61 | /* Same info as a HARD_REG_SET. */ | |
62 | ||
63 | HARD_REG_SET fixed_reg_set; | |
64 | ||
65 | /* Data for initializing the above. */ | |
66 | ||
67 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
68 | ||
69 | /* Indexed by hard register number, contains 1 for registers | |
70 | that are fixed use or are clobbered by function calls. | |
71 | These are the registers that cannot be used to allocate | |
72 | a pseudo reg whose life crosses calls. */ | |
73 | ||
74 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
75 | ||
76 | /* Same info as a HARD_REG_SET. */ | |
77 | ||
78 | HARD_REG_SET call_used_reg_set; | |
79 | ||
6cad67d2 JL |
80 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
81 | HARD_REG_SET losing_caller_save_reg_set; | |
82 | ||
54dac99e RK |
83 | /* Data for initializing the above. */ |
84 | ||
85 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
86 | ||
87 | /* Indexed by hard register number, contains 1 for registers that are | |
88 | fixed use -- i.e. in fixed_regs -- or a function value return register | |
89 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the | |
90 | registers that cannot hold quantities across calls even if we are | |
91 | willing to save and restore them. */ | |
92 | ||
93 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
94 | ||
95 | /* The same info as a HARD_REG_SET. */ | |
96 | ||
97 | HARD_REG_SET call_fixed_reg_set; | |
98 | ||
99 | /* Number of non-fixed registers. */ | |
100 | ||
101 | int n_non_fixed_regs; | |
102 | ||
103 | /* Indexed by hard register number, contains 1 for registers | |
104 | that are being used for global register decls. | |
105 | These must be exempt from ordinary flow analysis | |
106 | and are also considered fixed. */ | |
107 | ||
108 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
109 | ||
110 | /* Table of register numbers in the order in which to try to use them. */ | |
111 | #ifdef REG_ALLOC_ORDER | |
112 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
113 | #endif | |
114 | ||
115 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
116 | ||
2e0e2b76 CH |
117 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
118 | ||
089e575b RS |
119 | /* The same information, but as an array of unsigned ints. We copy from |
120 | these unsigned ints to the table above. We do this so the tm.h files | |
121 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
122 | |
123 | #define N_REG_INTS \ | |
124 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
125 | ||
089e575b | 126 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 127 | = REG_CLASS_CONTENTS; |
54dac99e RK |
128 | |
129 | /* For each reg class, number of regs it contains. */ | |
130 | ||
131 | int reg_class_size[N_REG_CLASSES]; | |
132 | ||
133 | /* For each reg class, table listing all the containing classes. */ | |
134 | ||
135 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
136 | ||
137 | /* For each reg class, table listing all the classes contained in it. */ | |
138 | ||
139 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
140 | ||
141 | /* For each pair of reg classes, | |
142 | a largest reg class contained in their union. */ | |
143 | ||
144 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
145 | ||
146 | /* For each pair of reg classes, | |
147 | the smallest reg class containing their union. */ | |
148 | ||
149 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
150 | ||
d05c8ee7 RS |
151 | /* Array containing all of the register names */ |
152 | ||
153 | char *reg_names[] = REGISTER_NAMES; | |
154 | ||
ca4aac00 DE |
155 | /* For each hard register, the widest mode object that it can contain. |
156 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
157 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
158 | register. */ | |
159 | ||
160 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
161 | ||
e4600702 RK |
162 | /* Maximum cost of moving from a register in one class to a register in |
163 | another class. Based on REGISTER_MOVE_COST. */ | |
164 | ||
165 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
166 | ||
167 | /* Similar, but here we don't have to move if the first index is a subset | |
168 | of the second so in that case the cost is zero. */ | |
169 | ||
170 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
171 | ||
533d0835 RK |
172 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
173 | ||
174 | /* These are the classes that regs which are auto-incremented or decremented | |
175 | cannot be put in. */ | |
176 | ||
177 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
178 | ||
179 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
180 | context. */ | |
181 | ||
182 | static char *in_inc_dec; | |
183 | ||
5fcb671c | 184 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 185 | |
473fe49b KR |
186 | #ifdef HAVE_SECONDARY_RELOADS |
187 | ||
188 | /* Sample MEM values for use by memory_move_secondary_cost. */ | |
189 | ||
190 | static rtx top_of_stack[MAX_MACHINE_MODE]; | |
191 | ||
192 | #endif /* HAVE_SECONDARY_RELOADS */ | |
193 | ||
54dac99e RK |
194 | /* Function called only once to initialize the above data on reg usage. |
195 | Once this is done, various switches may override. */ | |
196 | ||
197 | void | |
198 | init_reg_sets () | |
199 | { | |
200 | register int i, j; | |
201 | ||
2e0e2b76 CH |
202 | /* First copy the register information from the initial int form into |
203 | the regsets. */ | |
204 | ||
205 | for (i = 0; i < N_REG_CLASSES; i++) | |
206 | { | |
207 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
208 | ||
209 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
210 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 211 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
212 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
213 | } | |
214 | ||
54dac99e RK |
215 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
216 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
217 | bzero (global_regs, sizeof global_regs); | |
218 | ||
219 | /* Compute number of hard regs in each class. */ | |
220 | ||
4c9a05bc | 221 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
222 | for (i = 0; i < N_REG_CLASSES; i++) |
223 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
224 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
225 | reg_class_size[i]++; | |
226 | ||
227 | /* Initialize the table of subunions. | |
228 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
229 | that is contained in the union of classes I and J. */ | |
230 | ||
231 | for (i = 0; i < N_REG_CLASSES; i++) | |
232 | { | |
233 | for (j = 0; j < N_REG_CLASSES; j++) | |
234 | { | |
235 | #ifdef HARD_REG_SET | |
236 | register /* Declare it register if it's a scalar. */ | |
237 | #endif | |
238 | HARD_REG_SET c; | |
239 | register int k; | |
240 | ||
241 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
242 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
243 | for (k = 0; k < N_REG_CLASSES; k++) | |
244 | { | |
245 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
246 | subclass1); | |
247 | continue; | |
248 | ||
249 | subclass1: | |
250 | /* keep the largest subclass */ /* SPEE 900308 */ | |
251 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
252 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
253 | subclass2); | |
254 | reg_class_subunion[i][j] = (enum reg_class) k; | |
255 | subclass2: | |
256 | ; | |
257 | } | |
258 | } | |
259 | } | |
260 | ||
261 | /* Initialize the table of superunions. | |
262 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
263 | containing the union of classes I and J. */ | |
264 | ||
265 | for (i = 0; i < N_REG_CLASSES; i++) | |
266 | { | |
267 | for (j = 0; j < N_REG_CLASSES; j++) | |
268 | { | |
269 | #ifdef HARD_REG_SET | |
270 | register /* Declare it register if it's a scalar. */ | |
271 | #endif | |
272 | HARD_REG_SET c; | |
273 | register int k; | |
274 | ||
275 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
276 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
277 | for (k = 0; k < N_REG_CLASSES; k++) | |
278 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
279 | ||
280 | superclass: | |
281 | reg_class_superunion[i][j] = (enum reg_class) k; | |
282 | } | |
283 | } | |
284 | ||
285 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
286 | First clear the whole table, then add the elements as they are found. */ | |
287 | ||
288 | for (i = 0; i < N_REG_CLASSES; i++) | |
289 | { | |
290 | for (j = 0; j < N_REG_CLASSES; j++) | |
291 | { | |
292 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
293 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
294 | } | |
295 | } | |
296 | ||
297 | for (i = 0; i < N_REG_CLASSES; i++) | |
298 | { | |
299 | if (i == (int) NO_REGS) | |
300 | continue; | |
301 | ||
302 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
303 | { | |
304 | enum reg_class *p; | |
305 | ||
306 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
307 | subclass); | |
308 | continue; | |
309 | subclass: | |
310 | /* Reg class I is a subclass of J. | |
311 | Add J to the table of superclasses of I. */ | |
312 | p = ®_class_superclasses[i][0]; | |
313 | while (*p != LIM_REG_CLASSES) p++; | |
314 | *p = (enum reg_class) j; | |
315 | /* Add I to the table of superclasses of J. */ | |
316 | p = ®_class_subclasses[j][0]; | |
317 | while (*p != LIM_REG_CLASSES) p++; | |
318 | *p = (enum reg_class) i; | |
319 | } | |
320 | } | |
e4600702 | 321 | |
73b76448 RK |
322 | /* Do any additional initialization regsets may need */ |
323 | INIT_ONCE_REG_SET (); | |
54dac99e RK |
324 | } |
325 | ||
326 | /* After switches have been processed, which perhaps alter | |
327 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
328 | ||
c27c5281 | 329 | static void |
54dac99e RK |
330 | init_reg_sets_1 () |
331 | { | |
f8344bea | 332 | register unsigned int i, j; |
54dac99e RK |
333 | |
334 | /* This macro allows the fixed or call-used registers | |
335 | to depend on target flags. */ | |
336 | ||
337 | #ifdef CONDITIONAL_REGISTER_USAGE | |
338 | CONDITIONAL_REGISTER_USAGE; | |
339 | #endif | |
340 | ||
54dac99e RK |
341 | /* Initialize "constant" tables. */ |
342 | ||
343 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
344 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
345 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
346 | ||
347 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
348 | |
349 | n_non_fixed_regs = 0; | |
350 | ||
351 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
352 | { | |
54dac99e RK |
353 | if (fixed_regs[i]) |
354 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
355 | else | |
356 | n_non_fixed_regs++; | |
357 | ||
358 | if (call_used_regs[i]) | |
359 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
360 | if (call_fixed_regs[i]) | |
361 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
362 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
363 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 364 | } |
acbce667 KR |
365 | |
366 | /* Initialize the move cost table. Find every subset of each class | |
367 | and take the maximum cost of moving any subset to any other. */ | |
368 | ||
369 | for (i = 0; i < N_REG_CLASSES; i++) | |
370 | for (j = 0; j < N_REG_CLASSES; j++) | |
371 | { | |
372 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
373 | enum reg_class *p1, *p2; | |
374 | ||
375 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
376 | if (*p2 != i) | |
377 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
378 | ||
379 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
380 | { | |
381 | if (*p1 != j) | |
382 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
383 | ||
384 | for (p2 = ®_class_subclasses[j][0]; | |
385 | *p2 != LIM_REG_CLASSES; p2++) | |
386 | if (*p1 != *p2) | |
387 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
388 | } | |
389 | ||
390 | move_cost[i][j] = cost; | |
391 | ||
392 | if (reg_class_subset_p (i, j)) | |
393 | cost = 0; | |
394 | ||
395 | may_move_cost[i][j] = cost; | |
396 | } | |
c27c5281 DE |
397 | } |
398 | ||
399 | /* Compute the table of register modes. | |
400 | These values are used to record death information for individual registers | |
401 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 402 | |
c27c5281 DE |
403 | static void |
404 | init_reg_modes () | |
405 | { | |
406 | register int i; | |
ca4aac00 DE |
407 | |
408 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
409 | { |
410 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
411 | ||
066c2fea | 412 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
413 | ??? One situation in which we need to do this is on the mips where |
414 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
415 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 416 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 417 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 418 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 419 | } |
ca4aac00 DE |
420 | } |
421 | ||
c27c5281 DE |
422 | /* Finish initializing the register sets and |
423 | initialize the register modes. */ | |
424 | ||
425 | void | |
426 | init_regs () | |
427 | { | |
428 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
429 | until after register usage was specified. */ | |
b93a436e | 430 | init_reg_sets_1 (); |
c27c5281 DE |
431 | |
432 | init_reg_modes (); | |
473fe49b KR |
433 | |
434 | #ifdef HAVE_SECONDARY_RELOADS | |
435 | { | |
436 | /* Make some fake stack-frame MEM references for use in | |
437 | memory_move_secondary_cost. */ | |
438 | int i; | |
439 | for (i = 0; i < MAX_MACHINE_MODE; i++) | |
440 | top_of_stack[i] = gen_rtx (MEM, i, stack_pointer_rtx); | |
441 | } | |
442 | #endif | |
c27c5281 DE |
443 | } |
444 | ||
cbd5b9a2 | 445 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 446 | |
cbd5b9a2 KR |
447 | /* Compute extra cost of moving registers to/from memory due to reloads. |
448 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 449 | |
cbd5b9a2 KR |
450 | int |
451 | memory_move_secondary_cost (mode, class, in) | |
452 | enum machine_mode mode; | |
453 | enum reg_class class; | |
454 | int in; | |
455 | { | |
456 | enum reg_class altclass; | |
457 | int partial_cost = 0; | |
cbd5b9a2 | 458 | /* We need a memory reference to feed to SECONDARY... macros. */ |
473fe49b | 459 | rtx mem = top_of_stack[(int) mode]; |
cbd5b9a2 KR |
460 | |
461 | if (in) | |
473fe49b | 462 | { |
321c0828 | 463 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 464 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 465 | #else |
473fe49b | 466 | altclass = NO_REGS; |
321c0828 | 467 | #endif |
473fe49b | 468 | } |
cbd5b9a2 | 469 | else |
473fe49b | 470 | { |
321c0828 | 471 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 472 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 473 | #else |
473fe49b | 474 | altclass = NO_REGS; |
321c0828 | 475 | #endif |
473fe49b KR |
476 | } |
477 | ||
cbd5b9a2 KR |
478 | if (altclass == NO_REGS) |
479 | return 0; | |
480 | ||
481 | if (in) | |
482 | partial_cost = REGISTER_MOVE_COST (altclass, class); | |
483 | else | |
484 | partial_cost = REGISTER_MOVE_COST (class, altclass); | |
485 | ||
486 | if (class == altclass) | |
487 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
488 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
489 | here in that case. | |
490 | ||
491 | I'm tempted to put in an abort here, but returning this will | |
492 | probably only give poor estimates, which is what we would've | |
493 | had before this code anyways. */ | |
494 | return partial_cost; | |
495 | ||
496 | /* Check if the secondary reload register will also need a | |
497 | secondary reload. */ | |
498 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
499 | } | |
500 | #endif | |
501 | ||
ca4aac00 DE |
502 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
503 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
504 | ||
505 | enum machine_mode | |
506 | choose_hard_reg_mode (regno, nregs) | |
507 | int regno; | |
508 | int nregs; | |
509 | { | |
510 | enum machine_mode found_mode = VOIDmode, mode; | |
511 | ||
512 | /* We first look for the largest integer mode that can be validly | |
513 | held in REGNO. If none, we look for the largest floating-point mode. | |
514 | If we still didn't find a valid mode, try CCmode. */ | |
515 | ||
516 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
517 | mode != VOIDmode; | |
518 | mode = GET_MODE_WIDER_MODE (mode)) | |
519 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
520 | && HARD_REGNO_MODE_OK (regno, mode)) | |
521 | found_mode = mode; | |
522 | ||
523 | if (found_mode != VOIDmode) | |
524 | return found_mode; | |
525 | ||
526 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
527 | mode != VOIDmode; | |
528 | mode = GET_MODE_WIDER_MODE (mode)) | |
529 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
530 | && HARD_REGNO_MODE_OK (regno, mode)) | |
531 | found_mode = mode; | |
532 | ||
533 | if (found_mode != VOIDmode) | |
534 | return found_mode; | |
535 | ||
536 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
537 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
538 | return CCmode; | |
539 | ||
540 | /* We can't find a mode valid for this register. */ | |
541 | return VOIDmode; | |
54dac99e RK |
542 | } |
543 | ||
544 | /* Specify the usage characteristics of the register named NAME. | |
545 | It should be a fixed register if FIXED and a | |
546 | call-used register if CALL_USED. */ | |
547 | ||
548 | void | |
549 | fix_register (name, fixed, call_used) | |
550 | char *name; | |
551 | int fixed, call_used; | |
552 | { | |
553 | int i; | |
554 | ||
555 | /* Decode the name and update the primary form of | |
556 | the register info. */ | |
557 | ||
e5c90c23 TW |
558 | if ((i = decode_reg_name (name)) >= 0) |
559 | { | |
560 | fixed_regs[i] = fixed; | |
561 | call_used_regs[i] = call_used; | |
562 | } | |
563 | else | |
54dac99e RK |
564 | { |
565 | warning ("unknown register name: %s", name); | |
54dac99e RK |
566 | } |
567 | } | |
614f68e2 RK |
568 | |
569 | /* Mark register number I as global. */ | |
570 | ||
571 | void | |
572 | globalize_reg (i) | |
573 | int i; | |
574 | { | |
575 | if (global_regs[i]) | |
576 | { | |
577 | warning ("register used for two global register variables"); | |
578 | return; | |
579 | } | |
580 | ||
581 | if (call_used_regs[i] && ! fixed_regs[i]) | |
582 | warning ("call-clobbered register used for global register variable"); | |
583 | ||
584 | global_regs[i] = 1; | |
585 | ||
586 | /* If already fixed, nothing else to do. */ | |
587 | if (fixed_regs[i]) | |
588 | return; | |
589 | ||
590 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
591 | n_non_fixed_regs--; | |
592 | ||
593 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
594 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
595 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
596 | } | |
54dac99e RK |
597 | \f |
598 | /* Now the data and code for the `regclass' pass, which happens | |
599 | just before local-alloc. */ | |
600 | ||
e4600702 RK |
601 | /* The `costs' struct records the cost of using a hard register of each class |
602 | and of using memory for each pseudo. We use this data to set up | |
603 | register class preferences. */ | |
54dac99e | 604 | |
e4600702 | 605 | struct costs |
54dac99e | 606 | { |
e4600702 RK |
607 | int cost[N_REG_CLASSES]; |
608 | int mem_cost; | |
54dac99e RK |
609 | }; |
610 | ||
e4600702 RK |
611 | /* Record the cost of each class for each pseudo. */ |
612 | ||
613 | static struct costs *costs; | |
614 | ||
615 | /* Record the same data by operand number, accumulated for each alternative | |
616 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
617 | alternative. */ | |
618 | ||
619 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
620 | |
621 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
622 | This is available after `regclass' is run. */ | |
623 | ||
624 | static char *prefclass; | |
625 | ||
54d23420 RK |
626 | /* altclass[R] is a register class that we should use for allocating |
627 | pseudo number R if no register in the preferred class is available. | |
628 | If no register in this class is available, memory is preferred. | |
629 | ||
630 | It might appear to be more general to have a bitmask of classes here, | |
631 | but since it is recommended that there be a class corresponding to the | |
632 | union of most major pair of classes, that generality is not required. | |
633 | ||
54dac99e RK |
634 | This is available after `regclass' is run. */ |
635 | ||
54d23420 | 636 | static char *altclass; |
54dac99e | 637 | |
54d23420 | 638 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
639 | |
640 | static int loop_depth; | |
641 | ||
54d23420 RK |
642 | /* Account for the fact that insns within a loop are executed very commonly, |
643 | but don't keep doing this as loops go too deep. */ | |
644 | ||
645 | static int loop_cost; | |
646 | ||
08d95f91 RK |
647 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
648 | char **, rtx)); | |
649 | static int copy_cost PROTO((rtx, enum machine_mode, | |
650 | enum reg_class, int)); | |
651 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
652 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
653 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
654 | #endif | |
08d95f91 | 655 | static void reg_scan_mark_refs PROTO((rtx, rtx, int)); |
54dac99e RK |
656 | |
657 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
658 | This function is sometimes called before the info has been computed. | |
659 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
660 | ||
661 | enum reg_class | |
662 | reg_preferred_class (regno) | |
663 | int regno; | |
664 | { | |
665 | if (prefclass == 0) | |
666 | return GENERAL_REGS; | |
667 | return (enum reg_class) prefclass[regno]; | |
668 | } | |
669 | ||
e4600702 RK |
670 | enum reg_class |
671 | reg_alternate_class (regno) | |
b729186a | 672 | int regno; |
54dac99e RK |
673 | { |
674 | if (prefclass == 0) | |
e4600702 RK |
675 | return ALL_REGS; |
676 | ||
677 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
678 | } |
679 | ||
680 | /* This prevents dump_flow_info from losing if called | |
681 | before regclass is run. */ | |
682 | ||
683 | void | |
684 | regclass_init () | |
685 | { | |
686 | prefclass = 0; | |
687 | } | |
688 | \f | |
689 | /* This is a pass of the compiler that scans all instructions | |
690 | and calculates the preferred class for each pseudo-register. | |
691 | This information can be accessed later by calling `reg_preferred_class'. | |
692 | This pass comes just before local register allocation. */ | |
693 | ||
694 | void | |
695 | regclass (f, nregs) | |
696 | rtx f; | |
697 | int nregs; | |
698 | { | |
699 | #ifdef REGISTER_CONSTRAINTS | |
700 | register rtx insn; | |
e4600702 RK |
701 | register int i, j; |
702 | struct costs init_cost; | |
703 | rtx set; | |
704 | int pass; | |
54dac99e RK |
705 | |
706 | init_recog (); | |
707 | ||
533d0835 RK |
708 | costs = (struct costs *) alloca (nregs * sizeof (struct costs)); |
709 | ||
710 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
711 | ||
712 | in_inc_dec = (char *) alloca (nregs); | |
713 | ||
714 | /* Initialize information about which register classes can be used for | |
715 | pseudos that are auto-incremented or auto-decremented. It would | |
716 | seem better to put this in init_reg_sets, but we need to be able | |
717 | to allocate rtx, which we can't do that early. */ | |
718 | ||
719 | for (i = 0; i < N_REG_CLASSES; i++) | |
720 | { | |
38a448ca | 721 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 RK |
722 | enum machine_mode m; |
723 | ||
724 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
725 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
726 | { | |
727 | REGNO (r) = j; | |
728 | ||
729 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 730 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
731 | if (HARD_REGNO_MODE_OK (j, m)) |
732 | { | |
733 | PUT_MODE (r, m); | |
08d95f91 RK |
734 | |
735 | /* If a register is not directly suitable for an | |
736 | auto-increment or decrement addressing mode and | |
737 | requires secondary reloads, disallow its class from | |
738 | being used in such addresses. */ | |
739 | ||
740 | if ((0 | |
041d7180 JL |
741 | #ifdef SECONDARY_RELOAD_CLASS |
742 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
743 | != NO_REGS) | |
744 | #else | |
533d0835 | 745 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
746 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
747 | != NO_REGS) | |
533d0835 RK |
748 | #endif |
749 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
750 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
751 | != NO_REGS) | |
041d7180 | 752 | #endif |
533d0835 | 753 | #endif |
08d95f91 RK |
754 | ) |
755 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
756 | forbidden_inc_dec_class[i] = 1; |
757 | } | |
758 | } | |
759 | } | |
760 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
761 | ||
e4600702 RK |
762 | init_cost.mem_cost = 10000; |
763 | for (i = 0; i < N_REG_CLASSES; i++) | |
764 | init_cost.cost[i] = 10000; | |
54dac99e | 765 | |
e4600702 RK |
766 | /* Normally we scan the insns once and determine the best class to use for |
767 | each register. However, if -fexpensive_optimizations are on, we do so | |
768 | twice, the second time using the tentative best classes to guide the | |
769 | selection. */ | |
54dac99e | 770 | |
e4600702 RK |
771 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
772 | { | |
773 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 774 | |
4c9a05bc | 775 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 776 | |
533d0835 RK |
777 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
778 | bzero (in_inc_dec, nregs); | |
779 | #endif | |
780 | ||
e4600702 RK |
781 | loop_depth = 0, loop_cost = 1; |
782 | ||
783 | /* Scan the instructions and record each time it would | |
784 | save code to put a certain register in a certain class. */ | |
785 | ||
786 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 787 | { |
e4600702 RK |
788 | char *constraints[MAX_RECOG_OPERANDS]; |
789 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
790 | int nalternatives; | |
791 | int noperands; | |
792 | ||
793 | /* Show that an insn inside a loop is likely to be executed three | |
ac2a9454 | 794 | times more than insns outside a loop. This is much more aggressive |
e4600702 RK |
795 | than the assumptions made elsewhere and is being tried as an |
796 | experiment. */ | |
797 | ||
798 | if (GET_CODE (insn) == NOTE | |
799 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
800 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
801 | else if (GET_CODE (insn) == NOTE | |
802 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
803 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
804 | ||
805 | else if ((GET_CODE (insn) == INSN | |
806 | && GET_CODE (PATTERN (insn)) != USE | |
807 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
808 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) | |
809 | || (GET_CODE (insn) == JUMP_INSN | |
810 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
811 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
812 | || GET_CODE (insn) == CALL_INSN) | |
54dac99e | 813 | { |
e4600702 RK |
814 | if (GET_CODE (insn) == INSN |
815 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) | |
816 | { | |
37366632 | 817 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, |
e4600702 | 818 | constraints, modes); |
e5ed2155 TW |
819 | nalternatives = (noperands == 0 ? 0 |
820 | : n_occurrences (',', constraints[0]) + 1); | |
e4600702 RK |
821 | } |
822 | else | |
823 | { | |
824 | int insn_code_number = recog_memoized (insn); | |
825 | rtx note; | |
54dac99e | 826 | |
e4600702 RK |
827 | set = single_set (insn); |
828 | insn_extract (insn); | |
54dac99e | 829 | |
e4600702 RK |
830 | nalternatives = insn_n_alternatives[insn_code_number]; |
831 | noperands = insn_n_operands[insn_code_number]; | |
54dac99e | 832 | |
e4600702 RK |
833 | /* If this insn loads a parameter from its stack slot, then |
834 | it represents a savings, rather than a cost, if the | |
835 | parameter is stored in memory. Record this fact. */ | |
54dac99e | 836 | |
e4600702 RK |
837 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
838 | && GET_CODE (SET_SRC (set)) == MEM | |
37366632 RK |
839 | && (note = find_reg_note (insn, REG_EQUIV, |
840 | NULL_RTX)) != 0 | |
e4600702 RK |
841 | && GET_CODE (XEXP (note, 0)) == MEM) |
842 | { | |
843 | costs[REGNO (SET_DEST (set))].mem_cost | |
cbd5b9a2 KR |
844 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), |
845 | GENERAL_REGS, 1) | |
e4600702 RK |
846 | * loop_cost); |
847 | record_address_regs (XEXP (SET_SRC (set), 0), | |
848 | BASE_REG_CLASS, loop_cost * 2); | |
849 | continue; | |
850 | } | |
851 | ||
852 | /* Improve handling of two-address insns such as | |
853 | (set X (ashift CONST Y)) where CONST must be made to | |
854 | match X. Change it into two insns: (set X CONST) | |
855 | (set X (ashift X Y)). If we left this for reloading, it | |
856 | would probably get three insns because X and Y might go | |
857 | in the same place. This prevents X and Y from receiving | |
858 | the same hard reg. | |
859 | ||
860 | We can only do this if the modes of operands 0 and 1 | |
861 | (which might not be the same) are tieable and we only need | |
862 | do this during our first pass. */ | |
863 | ||
864 | if (pass == 0 && optimize | |
865 | && noperands >= 3 | |
866 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
867 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
868 | && CONSTANT_P (recog_operand[1]) | |
869 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
870 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
871 | && GET_CODE (recog_operand[0]) == REG | |
872 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
873 | insn_operand_mode[insn_code_number][1])) | |
874 | { | |
875 | rtx previnsn = prev_real_insn (insn); | |
876 | rtx dest | |
877 | = gen_lowpart (insn_operand_mode[insn_code_number][1], | |
878 | recog_operand[0]); | |
879 | rtx newinsn | |
880 | = emit_insn_before (gen_move_insn (dest, | |
881 | recog_operand[1]), | |
882 | insn); | |
883 | ||
884 | /* If this insn was the start of a basic block, | |
61b01243 RS |
885 | include the new insn in that block. |
886 | We need not check for code_label here; | |
887 | while a basic block can start with a code_label, | |
888 | INSN could not be at the beginning of that block. */ | |
e4600702 RK |
889 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) |
890 | { | |
891 | int b; | |
892 | for (b = 0; b < n_basic_blocks; b++) | |
893 | if (insn == basic_block_head[b]) | |
894 | basic_block_head[b] = newinsn; | |
895 | } | |
896 | ||
0f41302f | 897 | /* This makes one more setting of new insns's dest. */ |
b1f21e0a | 898 | REG_N_SETS (REGNO (recog_operand[0]))++; |
e4600702 | 899 | |
20912ad0 RK |
900 | *recog_operand_loc[1] = recog_operand[0]; |
901 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
902 | if (recog_dup_num[i] == 1) | |
903 | *recog_dup_loc[i] = recog_operand[0]; | |
904 | ||
e4600702 RK |
905 | insn = PREV_INSN (newinsn); |
906 | continue; | |
907 | } | |
54dac99e | 908 | |
e4600702 RK |
909 | for (i = 0; i < noperands; i++) |
910 | { | |
911 | constraints[i] | |
912 | = insn_operand_constraint[insn_code_number][i]; | |
913 | modes[i] = insn_operand_mode[insn_code_number][i]; | |
914 | } | |
915 | } | |
54dac99e | 916 | |
e4600702 RK |
917 | /* If we get here, we are set up to record the costs of all the |
918 | operands for this insn. Start by initializing the costs. | |
919 | Then handle any address registers. Finally record the desired | |
920 | classes for any pseudos, doing it twice if some pair of | |
921 | operands are commutative. */ | |
922 | ||
923 | for (i = 0; i < noperands; i++) | |
54dac99e | 924 | { |
e4600702 RK |
925 | op_costs[i] = init_cost; |
926 | ||
927 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
928 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
929 | ||
930 | if (GET_CODE (recog_operand[i]) == MEM) | |
931 | record_address_regs (XEXP (recog_operand[i], 0), | |
932 | BASE_REG_CLASS, loop_cost * 2); | |
933 | else if (constraints[i][0] == 'p') | |
934 | record_address_regs (recog_operand[i], | |
935 | BASE_REG_CLASS, loop_cost * 2); | |
54dac99e | 936 | } |
e4600702 RK |
937 | |
938 | /* Check for commutative in a separate loop so everything will | |
cc4c133a RS |
939 | have been initialized. We must do this even if one operand |
940 | is a constant--see addsi3 in m68k.md. */ | |
54dac99e | 941 | |
e5ed2155 | 942 | for (i = 0; i < noperands - 1; i++) |
cc4c133a | 943 | if (constraints[i][0] == '%') |
e4600702 RK |
944 | { |
945 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
946 | int j; | |
947 | ||
948 | /* Handle commutative operands by swapping the constraints. | |
949 | We assume the modes are the same. */ | |
950 | ||
951 | for (j = 0; j < noperands; j++) | |
952 | xconstraints[j] = constraints[j]; | |
953 | ||
954 | xconstraints[i] = constraints[i+1]; | |
955 | xconstraints[i+1] = constraints[i]; | |
956 | record_reg_classes (nalternatives, noperands, | |
957 | recog_operand, modes, xconstraints, | |
54dac99e | 958 | insn); |
e4600702 | 959 | } |
54dac99e | 960 | |
e4600702 RK |
961 | record_reg_classes (nalternatives, noperands, recog_operand, |
962 | modes, constraints, insn); | |
54dac99e | 963 | |
e4600702 RK |
964 | /* Now add the cost for each operand to the total costs for |
965 | its register. */ | |
54dac99e | 966 | |
e4600702 RK |
967 | for (i = 0; i < noperands; i++) |
968 | if (GET_CODE (recog_operand[i]) == REG | |
969 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
970 | { | |
971 | int regno = REGNO (recog_operand[i]); | |
972 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
973 | ||
974 | p->mem_cost += q->mem_cost * loop_cost; | |
975 | for (j = 0; j < N_REG_CLASSES; j++) | |
976 | p->cost[j] += q->cost[j] * loop_cost; | |
977 | } | |
54dac99e RK |
978 | } |
979 | } | |
54dac99e | 980 | |
e4600702 RK |
981 | /* Now for each register look at how desirable each class is |
982 | and find which class is preferred. Store that in | |
983 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
984 | class any of whose registers is better than memory. */ | |
54dac99e | 985 | |
e4600702 RK |
986 | if (pass == 0) |
987 | { | |
988 | prefclass = (char *) oballoc (nregs); | |
989 | altclass = (char *) oballoc (nregs); | |
990 | } | |
54dac99e | 991 | |
e4600702 | 992 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 993 | { |
ca3c6eae | 994 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
995 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
996 | /* This is an enum reg_class, but we call it an int | |
997 | to save lots of casts. */ | |
998 | register int class; | |
999 | register struct costs *p = &costs[i]; | |
1000 | ||
1001 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 1002 | { |
533d0835 RK |
1003 | /* Ignore classes that are too small for this operand or |
1004 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 1005 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
1006 | > reg_class_size[class] |
1007 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1008 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1009 | #endif | |
1010 | ) | |
e4600702 RK |
1011 | ; |
1012 | else if (p->cost[class] < best_cost) | |
1013 | { | |
1014 | best_cost = p->cost[class]; | |
1015 | best = (enum reg_class) class; | |
1016 | } | |
1017 | else if (p->cost[class] == best_cost) | |
1018 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 1019 | } |
54dac99e | 1020 | |
e4600702 RK |
1021 | /* Record the alternate register class; i.e., a class for which |
1022 | every register in it is better than using memory. If adding a | |
1023 | class would make a smaller class (i.e., no union of just those | |
1024 | classes exists), skip that class. The major unions of classes | |
1025 | should be provided as a register class. Don't do this if we | |
1026 | will be doing it again later. */ | |
1027 | ||
1028 | if (pass == 1 || ! flag_expensive_optimizations) | |
1029 | for (class = 0; class < N_REG_CLASSES; class++) | |
1030 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1031 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1032 | > reg_class_size[(int) alt]) |
1033 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1034 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1035 | #endif | |
1036 | ) | |
e4600702 RK |
1037 | alt = reg_class_subunion[(int) alt][class]; |
1038 | ||
1039 | /* If we don't add any classes, nothing to try. */ | |
1040 | if (alt == best) | |
995d54dd | 1041 | alt = NO_REGS; |
e4600702 RK |
1042 | |
1043 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
1044 | prefclass[i] = (int) best; | |
1045 | altclass[i] = (int) alt; | |
1046 | } | |
54dac99e RK |
1047 | } |
1048 | #endif /* REGISTER_CONSTRAINTS */ | |
1049 | } | |
1050 | \f | |
1051 | #ifdef REGISTER_CONSTRAINTS | |
1052 | ||
e4600702 RK |
1053 | /* Record the cost of using memory or registers of various classes for |
1054 | the operands in INSN. | |
54dac99e | 1055 | |
e4600702 | 1056 | N_ALTS is the number of alternatives. |
54dac99e | 1057 | |
e4600702 RK |
1058 | N_OPS is the number of operands. |
1059 | ||
1060 | OPS is an array of the operands. | |
1061 | ||
1062 | MODES are the modes of the operands, in case any are VOIDmode. | |
1063 | ||
1064 | CONSTRAINTS are the constraints to use for the operands. This array | |
1065 | is modified by this procedure. | |
1066 | ||
1067 | This procedure works alternative by alternative. For each alternative | |
1068 | we assume that we will be able to allocate all pseudos to their ideal | |
1069 | register class and calculate the cost of using that alternative. Then | |
1070 | we compute for each operand that is a pseudo-register, the cost of | |
1071 | having the pseudo allocated to each register class and using it in that | |
1072 | alternative. To this cost is added the cost of the alternative. | |
1073 | ||
1074 | The cost of each class for this insn is its lowest cost among all the | |
1075 | alternatives. */ | |
1076 | ||
1077 | static void | |
1078 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
1079 | int n_alts; | |
1080 | int n_ops; | |
1081 | rtx *ops; | |
1082 | enum machine_mode *modes; | |
54dac99e | 1083 | char **constraints; |
e4600702 | 1084 | rtx insn; |
54dac99e | 1085 | { |
e4600702 RK |
1086 | int alt; |
1087 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; | |
1088 | int i, j; | |
ec2d92af | 1089 | rtx set; |
e4600702 RK |
1090 | |
1091 | /* By default, each operand is an input operand. */ | |
1092 | ||
1093 | for (i = 0; i < n_ops; i++) | |
1094 | op_types[i] = OP_READ; | |
54dac99e | 1095 | |
e4600702 RK |
1096 | /* Process each alternative, each time minimizing an operand's cost with |
1097 | the cost for each operand in that alternative. */ | |
54dac99e | 1098 | |
e4600702 | 1099 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1100 | { |
e4600702 RK |
1101 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1102 | int alt_fail = 0; | |
1103 | int alt_cost = 0; | |
1104 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
1105 | int class; | |
54dac99e | 1106 | |
e4600702 RK |
1107 | for (i = 0; i < n_ops; i++) |
1108 | { | |
1109 | char *p = constraints[i]; | |
1110 | rtx op = ops[i]; | |
1111 | enum machine_mode mode = modes[i]; | |
1112 | int allows_mem = 0; | |
1113 | int win = 0; | |
1114 | char c; | |
54dac99e | 1115 | |
e4600702 RK |
1116 | /* If this operand has no constraints at all, we can conclude |
1117 | nothing about it since anything is valid. */ | |
54dac99e | 1118 | |
e4600702 RK |
1119 | if (*p == 0) |
1120 | { | |
1121 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1122 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1123 | |
e4600702 RK |
1124 | continue; |
1125 | } | |
54dac99e | 1126 | |
347099d6 RS |
1127 | if (*p == '%') |
1128 | p++; | |
1129 | ||
e4600702 RK |
1130 | /* If this alternative is only relevant when this operand |
1131 | matches a previous operand, we do different things depending | |
1132 | on whether this operand is a pseudo-reg or not. */ | |
54dac99e | 1133 | |
e4600702 RK |
1134 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1135 | { | |
1136 | j = p[0] - '0'; | |
1137 | classes[i] = classes[j]; | |
1138 | ||
1139 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1140 | { | |
1141 | /* If this matches the other operand, we have no added | |
dc903608 | 1142 | cost and we win. */ |
e4600702 | 1143 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1144 | win = 1; |
e4600702 | 1145 | |
77e67eac RK |
1146 | /* If we can put the other operand into a register, add to |
1147 | the cost of this alternative the cost to copy this | |
1148 | operand to the register used for the other operand. */ | |
e4600702 | 1149 | |
dc903608 | 1150 | else if (classes[j] != NO_REGS) |
77e67eac | 1151 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1152 | } |
07d8ca2d RS |
1153 | else if (GET_CODE (ops[j]) != REG |
1154 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1155 | { | |
1156 | /* This op is a pseudo but the one it matches is not. */ | |
1157 | ||
1158 | /* If we can't put the other operand into a register, this | |
1159 | alternative can't be used. */ | |
1160 | ||
1161 | if (classes[j] == NO_REGS) | |
1162 | alt_fail = 1; | |
e4600702 | 1163 | |
07d8ca2d RS |
1164 | /* Otherwise, add to the cost of this alternative the cost |
1165 | to copy the other operand to the register used for this | |
1166 | operand. */ | |
1167 | ||
1168 | else | |
1169 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1170 | } | |
e4600702 RK |
1171 | else |
1172 | { | |
1173 | /* The costs of this operand are the same as that of the | |
1174 | other operand. However, if we cannot tie them, this | |
1175 | alternative needs to do a copy, which is one | |
1176 | instruction. */ | |
1177 | ||
1178 | this_op_costs[i] = this_op_costs[j]; | |
37747c82 RK |
1179 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1180 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1181 | alt_cost += 2; | |
e4600702 | 1182 | |
347099d6 | 1183 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1184 | for this operand, so skip to the end of the |
1185 | alternative (should be just one character). */ | |
1186 | while (*p && *p++ != ',') | |
1187 | ; | |
1188 | ||
1189 | constraints[i] = p; | |
347099d6 RS |
1190 | continue; |
1191 | } | |
e4600702 RK |
1192 | } |
1193 | ||
1194 | /* Scan all the constraint letters. See if the operand matches | |
1195 | any of the constraints. Collect the valid register classes | |
1196 | and see if this operand accepts memory. */ | |
1197 | ||
1198 | classes[i] = NO_REGS; | |
1199 | while (*p && (c = *p++) != ',') | |
1200 | switch (c) | |
1201 | { | |
1202 | case '=': | |
1203 | op_types[i] = OP_WRITE; | |
1204 | break; | |
1205 | ||
1206 | case '+': | |
1207 | op_types[i] = OP_READ_WRITE; | |
1208 | break; | |
1209 | ||
1210 | case '*': | |
1211 | /* Ignore the next letter for this pass. */ | |
1212 | p++; | |
1213 | break; | |
1214 | ||
812f2051 R |
1215 | case '?': |
1216 | alt_cost += 2; | |
e4600702 | 1217 | case '%': |
812f2051 | 1218 | case '!': case '#': |
e4600702 RK |
1219 | case '&': |
1220 | case '0': case '1': case '2': case '3': case '4': | |
1221 | case 'p': | |
1222 | break; | |
1223 | ||
1224 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1225 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 RK |
1226 | and non-offsettable addresses here. */ |
1227 | allows_mem = 1; | |
1228 | if (GET_CODE (op) == MEM) | |
1229 | win = 1; | |
1230 | break; | |
1231 | ||
1232 | case '<': | |
1233 | if (GET_CODE (op) == MEM | |
1234 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1235 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1236 | win = 1; | |
1237 | break; | |
1238 | ||
1239 | case '>': | |
1240 | if (GET_CODE (op) == MEM | |
1241 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1242 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1243 | win = 1; | |
1244 | break; | |
1245 | ||
1246 | case 'E': | |
7ac2547f | 1247 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1248 | /* Match any floating double constant, but only if |
1249 | we can examine the bits of it reliably. */ | |
1250 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1251 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1252 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1253 | break; | |
7ac2547f | 1254 | #endif |
e4600702 RK |
1255 | if (GET_CODE (op) == CONST_DOUBLE) |
1256 | win = 1; | |
1257 | break; | |
1258 | ||
1259 | case 'F': | |
1260 | if (GET_CODE (op) == CONST_DOUBLE) | |
1261 | win = 1; | |
1262 | break; | |
1263 | ||
1264 | case 'G': | |
1265 | case 'H': | |
1266 | if (GET_CODE (op) == CONST_DOUBLE | |
1267 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1268 | win = 1; | |
1269 | break; | |
1270 | ||
1271 | case 's': | |
1272 | if (GET_CODE (op) == CONST_INT | |
1273 | || (GET_CODE (op) == CONST_DOUBLE | |
1274 | && GET_MODE (op) == VOIDmode)) | |
1275 | break; | |
1276 | case 'i': | |
1277 | if (CONSTANT_P (op) | |
1278 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1279 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1280 | #endif | |
1281 | ) | |
1282 | win = 1; | |
1283 | break; | |
1284 | ||
1285 | case 'n': | |
1286 | if (GET_CODE (op) == CONST_INT | |
1287 | || (GET_CODE (op) == CONST_DOUBLE | |
1288 | && GET_MODE (op) == VOIDmode)) | |
1289 | win = 1; | |
1290 | break; | |
1291 | ||
1292 | case 'I': | |
1293 | case 'J': | |
1294 | case 'K': | |
1295 | case 'L': | |
1296 | case 'M': | |
1297 | case 'N': | |
1298 | case 'O': | |
1299 | case 'P': | |
1300 | if (GET_CODE (op) == CONST_INT | |
1301 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1302 | win = 1; | |
1303 | break; | |
1304 | ||
1305 | case 'X': | |
1306 | win = 1; | |
1307 | break; | |
54dac99e | 1308 | |
54dac99e | 1309 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1310 | case 'Q': |
1311 | case 'R': | |
1312 | case 'S': | |
1313 | case 'T': | |
1314 | case 'U': | |
1315 | if (EXTRA_CONSTRAINT (op, c)) | |
1316 | win = 1; | |
1317 | break; | |
1318 | #endif | |
1319 | ||
1320 | case 'g': | |
1321 | if (GET_CODE (op) == MEM | |
1322 | || (CONSTANT_P (op) | |
1323 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1324 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1325 | #endif |
e4600702 RK |
1326 | )) |
1327 | win = 1; | |
1328 | allows_mem = 1; | |
1329 | case 'r': | |
1330 | classes[i] | |
1331 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1332 | break; | |
1333 | ||
1334 | default: | |
1335 | classes[i] | |
1336 | = reg_class_subunion[(int) classes[i]] | |
1337 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1338 | } | |
1339 | ||
1340 | constraints[i] = p; | |
1341 | ||
1342 | /* How we account for this operand now depends on whether it is a | |
1343 | pseudo register or not. If it is, we first check if any | |
1344 | register classes are valid. If not, we ignore this alternative, | |
1345 | since we want to assume that all pseudos get allocated for | |
1346 | register preferencing. If some register class is valid, compute | |
1347 | the costs of moving the pseudo into that class. */ | |
1348 | ||
1349 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1350 | { |
e4600702 RK |
1351 | if (classes[i] == NO_REGS) |
1352 | alt_fail = 1; | |
1353 | else | |
1354 | { | |
1355 | struct costs *pp = &this_op_costs[i]; | |
1356 | ||
1357 | for (class = 0; class < N_REG_CLASSES; class++) | |
1358 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1359 | ||
1360 | /* If the alternative actually allows memory, make things | |
1361 | a bit cheaper since we won't need an extra insn to | |
1362 | load it. */ | |
1363 | ||
cbd5b9a2 KR |
1364 | pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) |
1365 | - allows_mem); | |
e4600702 RK |
1366 | |
1367 | /* If we have assigned a class to this register in our | |
1368 | first pass, add a cost to this alternative corresponding | |
1369 | to what we would add if this register were not in the | |
1370 | appropriate class. */ | |
1371 | ||
1372 | if (prefclass) | |
1373 | alt_cost | |
1374 | += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; | |
1375 | } | |
4db18574 | 1376 | } |
54dac99e | 1377 | |
e4600702 RK |
1378 | /* Otherwise, if this alternative wins, either because we |
1379 | have already determined that or if we have a hard register of | |
1380 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1381 | |
e4600702 RK |
1382 | else if (win |
1383 | || (GET_CODE (op) == REG | |
6f654776 | 1384 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1385 | ; |
54dac99e | 1386 | |
e4600702 RK |
1387 | /* If registers are valid, the cost of this alternative includes |
1388 | copying the object to and/or from a register. */ | |
54dac99e | 1389 | |
e4600702 RK |
1390 | else if (classes[i] != NO_REGS) |
1391 | { | |
1392 | if (op_types[i] != OP_WRITE) | |
1393 | alt_cost += copy_cost (op, mode, classes[i], 1); | |
54dac99e | 1394 | |
e4600702 RK |
1395 | if (op_types[i] != OP_READ) |
1396 | alt_cost += copy_cost (op, mode, classes[i], 0); | |
1397 | } | |
54dac99e | 1398 | |
e4600702 RK |
1399 | /* The only other way this alternative can be used is if this is a |
1400 | constant that could be placed into memory. */ | |
1401 | ||
1402 | else if (CONSTANT_P (op) && allows_mem) | |
cbd5b9a2 | 1403 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1404 | else |
1405 | alt_fail = 1; | |
1406 | } | |
1407 | ||
1408 | if (alt_fail) | |
1409 | continue; | |
1410 | ||
1411 | /* Finally, update the costs with the information we've calculated | |
1412 | about this alternative. */ | |
1413 | ||
1414 | for (i = 0; i < n_ops; i++) | |
1415 | if (GET_CODE (ops[i]) == REG | |
1416 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1417 | { |
e4600702 RK |
1418 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1419 | int scale = 1 + (op_types[i] == OP_READ_WRITE); | |
54dac99e | 1420 | |
e4600702 RK |
1421 | pp->mem_cost = MIN (pp->mem_cost, |
1422 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1423 | |
e4600702 RK |
1424 | for (class = 0; class < N_REG_CLASSES; class++) |
1425 | pp->cost[class] = MIN (pp->cost[class], | |
1426 | (qq->cost[class] + alt_cost) * scale); | |
1427 | } | |
1428 | } | |
ec2d92af RK |
1429 | |
1430 | /* If this insn is a single set copying operand 1 to operand 0 | |
1431 | and one is a pseudo with the other a hard reg that is in its | |
1432 | own register class, set the cost of that register class to -1. */ | |
1433 | ||
1434 | if ((set = single_set (insn)) != 0 | |
1435 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1436 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1437 | for (i = 0; i <= 1; i++) | |
1438 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1439 | { | |
1440 | int regno = REGNO (ops[!i]); | |
1441 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1442 | int class; | |
4841ba4b | 1443 | int nr; |
ec2d92af RK |
1444 | |
1445 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 | |
1446 | && (reg_class_size[prefclass[regno]] | |
1447 | == CLASS_MAX_NREGS (prefclass[regno], mode))) | |
1448 | op_costs[i].cost[prefclass[regno]] = -1; | |
1449 | else if (regno < FIRST_PSEUDO_REGISTER) | |
1450 | for (class = 0; class < N_REG_CLASSES; class++) | |
1451 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1452 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1453 | { |
1454 | if (reg_class_size[class] == 1) | |
1455 | op_costs[i].cost[class] = -1; | |
1456 | else | |
1457 | { | |
1458 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1459 | { | |
1460 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1461 | break; | |
1462 | } | |
1463 | ||
1464 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1465 | op_costs[i].cost[class] = -1; | |
1466 | } | |
1467 | } | |
ec2d92af | 1468 | } |
54dac99e | 1469 | } |
e4600702 RK |
1470 | \f |
1471 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1472 | TO_P is zero) a register of class CLASS in mode MODE. | |
1473 | ||
1474 | X must not be a pseudo. */ | |
1475 | ||
1476 | static int | |
1477 | copy_cost (x, mode, class, to_p) | |
1478 | rtx x; | |
1479 | enum machine_mode mode; | |
1480 | enum reg_class class; | |
1481 | int to_p; | |
1482 | { | |
29a82058 | 1483 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1484 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1485 | #endif |
e4600702 RK |
1486 | |
1487 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1488 | assuming optimal allocation. */ | |
1489 | ||
1490 | if (GET_CODE (x) == SCRATCH) | |
1491 | return 0; | |
1492 | ||
1493 | /* Get the class we will actually use for a reload. */ | |
1494 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1495 | ||
1496 | #ifdef HAVE_SECONDARY_RELOADS | |
1497 | /* If we need a secondary reload (we assume here that we are using | |
1498 | the secondary reload as an intermediate, not a scratch register), the | |
1499 | cost is that to load the input into the intermediate register, then | |
1500 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1501 | ||
1502 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1503 | if (to_p == 1) | |
1504 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1505 | #endif | |
1506 | ||
dd9f0e8f | 1507 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1508 | if (! to_p) |
1509 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1510 | #endif | |
1511 | ||
1512 | if (secondary_class != NO_REGS) | |
1513 | return (move_cost[(int) secondary_class][(int) class] | |
1514 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1515 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1516 | |
1517 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1518 | cost to move between the register classes, and use 2 for everything | |
1519 | else (constants). */ | |
1520 | ||
1521 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1522 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1523 | |
e4600702 RK |
1524 | else if (GET_CODE (x) == REG) |
1525 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1526 | ||
1527 | else | |
1528 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1529 | return 2; | |
1530 | } | |
1531 | \f | |
54dac99e RK |
1532 | /* Record the pseudo registers we must reload into hard registers |
1533 | in a subexpression of a memory address, X. | |
e4600702 RK |
1534 | |
1535 | CLASS is the class that the register needs to be in and is either | |
1536 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1537 | ||
1538 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1539 | can represent half-cost adjustments). */ | |
54dac99e | 1540 | |
197d6480 | 1541 | static void |
e4600702 | 1542 | record_address_regs (x, class, scale) |
54dac99e | 1543 | rtx x; |
e4600702 RK |
1544 | enum reg_class class; |
1545 | int scale; | |
54dac99e RK |
1546 | { |
1547 | register enum rtx_code code = GET_CODE (x); | |
1548 | ||
1549 | switch (code) | |
1550 | { | |
1551 | case CONST_INT: | |
1552 | case CONST: | |
1553 | case CC0: | |
1554 | case PC: | |
1555 | case SYMBOL_REF: | |
1556 | case LABEL_REF: | |
1557 | return; | |
1558 | ||
1559 | case PLUS: | |
1560 | /* When we have an address that is a sum, | |
1561 | we must determine whether registers are "base" or "index" regs. | |
1562 | If there is a sum of two registers, we must choose one to be | |
1563 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1564 | to make a good choice most of the time. We only need to do this |
1565 | on machines that can have two registers in an address and where | |
1566 | the base and index register classes are different. | |
1567 | ||
1568 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1569 | that seems bogus since it should only be set when we are sure | |
1570 | the register is being used as a pointer. */ | |
1571 | ||
54dac99e RK |
1572 | { |
1573 | rtx arg0 = XEXP (x, 0); | |
1574 | rtx arg1 = XEXP (x, 1); | |
1575 | register enum rtx_code code0 = GET_CODE (arg0); | |
1576 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1577 | |
1578 | /* Look inside subregs. */ | |
e4600702 | 1579 | if (code0 == SUBREG) |
54dac99e | 1580 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1581 | if (code1 == SUBREG) |
54dac99e RK |
1582 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1583 | ||
e4600702 RK |
1584 | /* If this machine only allows one register per address, it must |
1585 | be in the first operand. */ | |
1586 | ||
1587 | if (MAX_REGS_PER_ADDRESS == 1) | |
1588 | record_address_regs (arg0, class, scale); | |
1589 | ||
1590 | /* If index and base registers are the same on this machine, just | |
1591 | record registers in any non-constant operands. We assume here, | |
1592 | as well as in the tests below, that all addresses are in | |
1593 | canonical form. */ | |
1594 | ||
1595 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1596 | { |
e4600702 RK |
1597 | record_address_regs (arg0, class, scale); |
1598 | if (! CONSTANT_P (arg1)) | |
1599 | record_address_regs (arg1, class, scale); | |
54dac99e | 1600 | } |
e4600702 RK |
1601 | |
1602 | /* If the second operand is a constant integer, it doesn't change | |
1603 | what class the first operand must be. */ | |
1604 | ||
1605 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1606 | record_address_regs (arg0, class, scale); | |
1607 | ||
1608 | /* If the second operand is a symbolic constant, the first operand | |
1609 | must be an index register. */ | |
1610 | ||
1611 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1612 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1613 | ||
956d6950 JL |
1614 | /* If both operands are registers but one is already a hard register |
1615 | of index or base class, give the other the class that the hard | |
1616 | register is not. */ | |
1617 | ||
3f9e9508 | 1618 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1619 | else if (code0 == REG && code1 == REG |
1620 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1621 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1622 | record_address_regs (arg1, | |
1623 | REG_OK_FOR_BASE_P (arg0) | |
1624 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1625 | scale); | |
1626 | else if (code0 == REG && code1 == REG | |
1627 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1628 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1629 | record_address_regs (arg0, | |
1630 | REG_OK_FOR_BASE_P (arg1) | |
1631 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1632 | scale); | |
3f9e9508 | 1633 | #endif |
956d6950 | 1634 | |
e9a25f70 JL |
1635 | /* If one operand is known to be a pointer, it must be the base |
1636 | with the other operand the index. Likewise if the other operand | |
1637 | is a MULT. */ | |
f22376c7 | 1638 | |
e9a25f70 JL |
1639 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1640 | || code1 == MULT) | |
f22376c7 CI |
1641 | { |
1642 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1643 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1644 | } | |
e9a25f70 JL |
1645 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1646 | || code0 == MULT) | |
f22376c7 CI |
1647 | { |
1648 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1649 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1650 | } | |
1651 | ||
e9a25f70 | 1652 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1653 | or index register. This case should be rare. */ |
1654 | ||
e9a25f70 | 1655 | else |
54dac99e | 1656 | { |
e4600702 RK |
1657 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1658 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1659 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1660 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1661 | } |
54dac99e RK |
1662 | } |
1663 | break; | |
1664 | ||
1665 | case POST_INC: | |
1666 | case PRE_INC: | |
1667 | case POST_DEC: | |
1668 | case PRE_DEC: | |
1669 | /* Double the importance of a pseudo register that is incremented | |
1670 | or decremented, since it would take two extra insns | |
533d0835 RK |
1671 | if it ends up in the wrong place. If the operand is a pseudo, |
1672 | show it is being used in an INC_DEC context. */ | |
1673 | ||
1674 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1675 | if (GET_CODE (XEXP (x, 0)) == REG | |
1676 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1677 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1678 | #endif | |
e4600702 RK |
1679 | |
1680 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1681 | break; |
1682 | ||
1683 | case REG: | |
1684 | { | |
e4600702 RK |
1685 | register struct costs *pp = &costs[REGNO (x)]; |
1686 | register int i; | |
54dac99e | 1687 | |
cbd5b9a2 | 1688 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1689 | |
e4600702 RK |
1690 | for (i = 0; i < N_REG_CLASSES; i++) |
1691 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1692 | } |
1693 | break; | |
1694 | ||
1695 | default: | |
1696 | { | |
1697 | register char *fmt = GET_RTX_FORMAT (code); | |
1698 | register int i; | |
1699 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1700 | if (fmt[i] == 'e') | |
e4600702 | 1701 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1702 | } |
1703 | } | |
1704 | } | |
08d95f91 RK |
1705 | \f |
1706 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1707 | ||
1708 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1709 | to an object of MODE. */ | |
1710 | ||
1d300e19 | 1711 | static int |
08d95f91 RK |
1712 | auto_inc_dec_reg_p (reg, mode) |
1713 | rtx reg; | |
1714 | enum machine_mode mode; | |
1715 | { | |
1716 | #ifdef HAVE_POST_INCREMENT | |
38a448ca | 1717 | if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) |
08d95f91 RK |
1718 | return 1; |
1719 | #endif | |
1720 | ||
1721 | #ifdef HAVE_POST_DECREMENT | |
38a448ca | 1722 | if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) |
08d95f91 RK |
1723 | return 1; |
1724 | #endif | |
1725 | ||
1726 | #ifdef HAVE_PRE_INCREMENT | |
38a448ca | 1727 | if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) |
08d95f91 RK |
1728 | return 1; |
1729 | #endif | |
1730 | ||
1731 | #ifdef HAVE_PRE_DECREMENT | |
38a448ca | 1732 | if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) |
08d95f91 RK |
1733 | return 1; |
1734 | #endif | |
1735 | ||
1736 | return 0; | |
1737 | } | |
1738 | #endif | |
1739 | ||
54dac99e | 1740 | #endif /* REGISTER_CONSTRAINTS */ |
b1f21e0a MM |
1741 | \f |
1742 | /* Allocate enough space to hold NUM_REGS registers for the tables used for | |
1743 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1744 | NEW_P is non zero, initialize all of the registers, otherwise only |
1745 | initialize the new registers allocated. The same table is kept from | |
1746 | function to function, only reallocating it when we need more room. If | |
1747 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1748 | |
1749 | void | |
39379e67 | 1750 | allocate_reg_info (num_regs, new_p, renumber_p) |
b1f21e0a MM |
1751 | int num_regs; |
1752 | int new_p; | |
39379e67 | 1753 | int renumber_p; |
b1f21e0a MM |
1754 | { |
1755 | static int regno_allocated = 0; | |
1756 | static int regno_max = 0; | |
39379e67 | 1757 | static short *renumber = (short *)0; |
b1f21e0a | 1758 | int i; |
39379e67 MM |
1759 | int size_info; |
1760 | int size_renumber; | |
7ec189f2 | 1761 | int min = (new_p) ? 0 : regno_max; |
b1f21e0a | 1762 | |
39379e67 MM |
1763 | /* If this message come up, and you want to fix it, then all of the tables |
1764 | like reg_renumber, etc. that use short will have to be found and lengthed | |
1765 | to int or HOST_WIDE_INT. */ | |
1766 | ||
1767 | /* Free up all storage allocated */ | |
1768 | if (num_regs < 0) | |
1769 | { | |
1770 | if (reg_n_info) | |
1771 | { | |
1772 | free ((char *)reg_n_info); | |
1773 | free ((char *)renumber); | |
1774 | reg_n_info = (reg_info *)0; | |
1775 | renumber = (short *)0; | |
1776 | } | |
1777 | regno_allocated = 0; | |
1778 | regno_max = 0; | |
1779 | return; | |
1780 | } | |
1781 | ||
b1f21e0a MM |
1782 | if (num_regs > regno_allocated) |
1783 | { | |
1784 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ | |
39379e67 MM |
1785 | size_info = regno_allocated * sizeof (reg_info); |
1786 | size_renumber = regno_allocated * sizeof (short); | |
1787 | ||
1788 | if (!reg_n_info) | |
1789 | { | |
1790 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1791 | renumber = (short *) xmalloc (size_renumber); | |
1792 | } | |
1793 | ||
1794 | else if (new_p) /* if we're zapping everything, no need to realloc */ | |
1795 | { | |
1796 | free ((char *)reg_n_info); | |
1797 | free ((char *)renumber); | |
1798 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1799 | renumber = (short *) xmalloc (size_renumber); | |
1800 | } | |
1801 | ||
1802 | else | |
1803 | { | |
1804 | reg_n_info = (reg_info *) xrealloc ((char *)reg_n_info, size_info); | |
1805 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
1806 | } | |
b1f21e0a MM |
1807 | } |
1808 | ||
1809 | if (min < num_regs) | |
1810 | { | |
1811 | bzero ((char *) ®_n_info[min], (num_regs - min) * sizeof (reg_info)); | |
1812 | for (i = min; i < num_regs; i++) | |
39379e67 MM |
1813 | { |
1814 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
1815 | renumber[i] = -1; | |
1816 | } | |
b1f21e0a MM |
1817 | } |
1818 | ||
39379e67 MM |
1819 | if (renumber_p) |
1820 | reg_renumber = renumber; | |
1821 | ||
73b76448 RK |
1822 | /* Tell the regset code about the new number of registers */ |
1823 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
1824 | ||
b1f21e0a MM |
1825 | regno_max = num_regs; |
1826 | } | |
1827 | ||
54dac99e RK |
1828 | \f |
1829 | /* This is the `regscan' pass of the compiler, run just before cse | |
1830 | and again just before loop. | |
1831 | ||
1832 | It finds the first and last use of each pseudo-register | |
1833 | and records them in the vectors regno_first_uid, regno_last_uid | |
1834 | and counts the number of sets in the vector reg_n_sets. | |
1835 | ||
1836 | REPEAT is nonzero the second time this is called. */ | |
1837 | ||
54dac99e | 1838 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 1839 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
1840 | and we want this to remain correct for all the remaining passes. */ |
1841 | ||
1842 | int max_parallel; | |
1843 | ||
54dac99e RK |
1844 | void |
1845 | reg_scan (f, nregs, repeat) | |
1846 | rtx f; | |
1847 | int nregs; | |
1848 | int repeat; | |
1849 | { | |
1850 | register rtx insn; | |
1851 | ||
39379e67 | 1852 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
1853 | max_parallel = 3; |
1854 | ||
1855 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1856 | if (GET_CODE (insn) == INSN | |
1857 | || GET_CODE (insn) == CALL_INSN | |
1858 | || GET_CODE (insn) == JUMP_INSN) | |
1859 | { | |
1860 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1861 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1862 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
1ebecb64 | 1863 | reg_scan_mark_refs (PATTERN (insn), insn, 0); |
01565a55 RK |
1864 | |
1865 | if (REG_NOTES (insn)) | |
1866 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1); | |
54dac99e RK |
1867 | } |
1868 | } | |
1869 | ||
1ebecb64 RS |
1870 | /* X is the expression to scan. INSN is the insn it appears in. |
1871 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ | |
1872 | ||
08d95f91 | 1873 | static void |
1ebecb64 | 1874 | reg_scan_mark_refs (x, insn, note_flag) |
54dac99e | 1875 | rtx x; |
be8dcd74 | 1876 | rtx insn; |
1ebecb64 | 1877 | int note_flag; |
54dac99e RK |
1878 | { |
1879 | register enum rtx_code code = GET_CODE (x); | |
1880 | register rtx dest; | |
be8dcd74 | 1881 | register rtx note; |
54dac99e RK |
1882 | |
1883 | switch (code) | |
1884 | { | |
1885 | case CONST_INT: | |
1886 | case CONST: | |
1887 | case CONST_DOUBLE: | |
1888 | case CC0: | |
1889 | case PC: | |
1890 | case SYMBOL_REF: | |
1891 | case LABEL_REF: | |
1892 | case ADDR_VEC: | |
1893 | case ADDR_DIFF_VEC: | |
1894 | return; | |
1895 | ||
1896 | case REG: | |
1897 | { | |
1898 | register int regno = REGNO (x); | |
1899 | ||
b1f21e0a | 1900 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); |
1ebecb64 | 1901 | if (!note_flag) |
b1f21e0a MM |
1902 | REGNO_LAST_UID (regno) = INSN_UID (insn); |
1903 | if (REGNO_FIRST_UID (regno) == 0) | |
1904 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
54dac99e RK |
1905 | } |
1906 | break; | |
1907 | ||
01565a55 | 1908 | case EXPR_LIST: |
7b18c3db RS |
1909 | if (XEXP (x, 0)) |
1910 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); | |
01565a55 RK |
1911 | if (XEXP (x, 1)) |
1912 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1913 | break; | |
1914 | ||
1915 | case INSN_LIST: | |
1916 | if (XEXP (x, 1)) | |
1917 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1918 | break; | |
1919 | ||
54dac99e RK |
1920 | case SET: |
1921 | /* Count a set of the destination if it is a register. */ | |
1922 | for (dest = SET_DEST (x); | |
1923 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
1924 | || GET_CODE (dest) == ZERO_EXTEND; | |
1925 | dest = XEXP (dest, 0)) | |
1926 | ; | |
1927 | ||
1928 | if (GET_CODE (dest) == REG) | |
b1f21e0a | 1929 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 1930 | |
be8dcd74 RK |
1931 | /* If this is setting a pseudo from another pseudo or the sum of a |
1932 | pseudo and a constant integer and the other pseudo is known to be | |
1933 | a pointer, set the destination to be a pointer as well. | |
1934 | ||
1935 | Likewise if it is setting the destination from an address or from a | |
1936 | value equivalent to an address or to the sum of an address and | |
1937 | something else. | |
1938 | ||
1939 | But don't do any of this if the pseudo corresponds to a user | |
1940 | variable since it should have already been set as a pointer based | |
1941 | on the type. */ | |
1942 | ||
1943 | if (GET_CODE (SET_DEST (x)) == REG | |
1944 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
64d3b4ca JL |
1945 | /* If the destination pseudo is set more than once, then other |
1946 | sets might not be to a pointer value (consider access to a | |
1947 | union in two threads of control in the presense of global | |
1948 | optimizations). So only set REGNO_POINTER_FLAG on the destination | |
1949 | pseudo if this is the only set of that pseudo. */ | |
1950 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 RK |
1951 | && ! REG_USERVAR_P (SET_DEST (x)) |
1952 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
1953 | && ((GET_CODE (SET_SRC (x)) == REG | |
1954 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
1955 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1956 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1957 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
1958 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
1959 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
1960 | || GET_CODE (SET_SRC (x)) == CONST | |
1961 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
1962 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
1963 | || (GET_CODE (SET_SRC (x)) == HIGH | |
1964 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
1965 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
1966 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
1967 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1968 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1969 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
1970 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
1971 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
1972 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
1973 | && (GET_CODE (XEXP (note, 0)) == CONST | |
1974 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
1975 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
1976 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
1977 | ||
0f41302f | 1978 | /* ... fall through ... */ |
54dac99e RK |
1979 | |
1980 | default: | |
1981 | { | |
1982 | register char *fmt = GET_RTX_FORMAT (code); | |
1983 | register int i; | |
1984 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1985 | { | |
1986 | if (fmt[i] == 'e') | |
1ebecb64 | 1987 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag); |
54dac99e RK |
1988 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
1989 | { | |
1990 | register int j; | |
1991 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1ebecb64 | 1992 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); |
54dac99e RK |
1993 | } |
1994 | } | |
1995 | } | |
1996 | } | |
1997 | } | |
1998 | \f | |
1999 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2000 | is also in C2. */ | |
2001 | ||
2002 | int | |
2003 | reg_class_subset_p (c1, c2) | |
2004 | register enum reg_class c1; | |
2005 | register enum reg_class c2; | |
2006 | { | |
2007 | if (c1 == c2) return 1; | |
2008 | ||
2009 | if (c2 == ALL_REGS) | |
2010 | win: | |
2011 | return 1; | |
2012 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
2013 | reg_class_contents[(int)c2], | |
2014 | win); | |
2015 | return 0; | |
2016 | } | |
2017 | ||
2018 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2019 | ||
2020 | int | |
2021 | reg_classes_intersect_p (c1, c2) | |
2022 | register enum reg_class c1; | |
2023 | register enum reg_class c2; | |
2024 | { | |
2025 | #ifdef HARD_REG_SET | |
2026 | register | |
2027 | #endif | |
2028 | HARD_REG_SET c; | |
2029 | ||
2030 | if (c1 == c2) return 1; | |
2031 | ||
2032 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2033 | return 1; | |
2034 | ||
2035 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2036 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2037 | ||
2038 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2039 | return 1; | |
2040 | ||
2041 | lose: | |
2042 | return 0; | |
2043 | } | |
2044 | ||
73b76448 RK |
2045 | /* Release any memory allocated by register sets. */ |
2046 | ||
2047 | void | |
2048 | regset_release_memory () | |
2049 | { | |
2050 | if (basic_block_live_at_start) | |
2051 | { | |
2052 | free_regset_vector (basic_block_live_at_start, n_basic_blocks); | |
2053 | basic_block_live_at_start = 0; | |
2054 | } | |
2055 | ||
2056 | FREE_REG_SET (regs_live_at_setjmp); | |
2057 | bitmap_release_memory (); | |
2058 | } |