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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
e4600702 | 2 | Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
22 | It also defines some tables of information about the hardware registers | |
23 | and a function init_reg_sets to initialize the tables. */ | |
24 | ||
25 | #include "config.h" | |
26 | #include "rtl.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "flags.h" | |
29 | #include "basic-block.h" | |
30 | #include "regs.h" | |
31 | #include "insn-config.h" | |
32 | #include "recog.h" | |
e4600702 RK |
33 | #include "reload.h" |
34 | #include "real.h" | |
54dac99e RK |
35 | |
36 | #ifndef REGISTER_MOVE_COST | |
37 | #define REGISTER_MOVE_COST(x, y) 2 | |
38 | #endif | |
39 | ||
40 | #ifndef MEMORY_MOVE_COST | |
e4600702 | 41 | #define MEMORY_MOVE_COST(x) 4 |
54dac99e RK |
42 | #endif |
43 | \f | |
44 | /* Register tables used by many passes. */ | |
45 | ||
46 | /* Indexed by hard register number, contains 1 for registers | |
47 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
48 | These are the registers that cannot be used to allocate | |
49 | a pseudo reg whose life does not cross calls. */ | |
50 | ||
51 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
52 | ||
53 | /* Same info as a HARD_REG_SET. */ | |
54 | ||
55 | HARD_REG_SET fixed_reg_set; | |
56 | ||
57 | /* Data for initializing the above. */ | |
58 | ||
59 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
60 | ||
61 | /* Indexed by hard register number, contains 1 for registers | |
62 | that are fixed use or are clobbered by function calls. | |
63 | These are the registers that cannot be used to allocate | |
64 | a pseudo reg whose life crosses calls. */ | |
65 | ||
66 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
67 | ||
68 | /* Same info as a HARD_REG_SET. */ | |
69 | ||
70 | HARD_REG_SET call_used_reg_set; | |
71 | ||
72 | /* Data for initializing the above. */ | |
73 | ||
74 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
75 | ||
76 | /* Indexed by hard register number, contains 1 for registers that are | |
77 | fixed use -- i.e. in fixed_regs -- or a function value return register | |
78 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the | |
79 | registers that cannot hold quantities across calls even if we are | |
80 | willing to save and restore them. */ | |
81 | ||
82 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
83 | ||
84 | /* The same info as a HARD_REG_SET. */ | |
85 | ||
86 | HARD_REG_SET call_fixed_reg_set; | |
87 | ||
88 | /* Number of non-fixed registers. */ | |
89 | ||
90 | int n_non_fixed_regs; | |
91 | ||
92 | /* Indexed by hard register number, contains 1 for registers | |
93 | that are being used for global register decls. | |
94 | These must be exempt from ordinary flow analysis | |
95 | and are also considered fixed. */ | |
96 | ||
97 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
98 | ||
99 | /* Table of register numbers in the order in which to try to use them. */ | |
100 | #ifdef REG_ALLOC_ORDER | |
101 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
102 | #endif | |
103 | ||
104 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
105 | ||
106 | HARD_REG_SET reg_class_contents[] = REG_CLASS_CONTENTS; | |
107 | ||
108 | /* For each reg class, number of regs it contains. */ | |
109 | ||
110 | int reg_class_size[N_REG_CLASSES]; | |
111 | ||
112 | /* For each reg class, table listing all the containing classes. */ | |
113 | ||
114 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
115 | ||
116 | /* For each reg class, table listing all the classes contained in it. */ | |
117 | ||
118 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
119 | ||
120 | /* For each pair of reg classes, | |
121 | a largest reg class contained in their union. */ | |
122 | ||
123 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
124 | ||
125 | /* For each pair of reg classes, | |
126 | the smallest reg class containing their union. */ | |
127 | ||
128 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
129 | ||
130 | /* Array containing all of the register names */ | |
131 | ||
132 | char *reg_names[] = REGISTER_NAMES; | |
133 | ||
54dac99e RK |
134 | /* Indexed by n, gives number of times (REG n) is set or clobbered. |
135 | This information remains valid for the rest of the compilation | |
136 | of the current function; it is used to control register allocation. | |
137 | ||
138 | This information applies to both hard registers and pseudo registers, | |
139 | unlike much of the information above. */ | |
140 | ||
141 | short *reg_n_sets; | |
142 | ||
e4600702 RK |
143 | /* Maximum cost of moving from a register in one class to a register in |
144 | another class. Based on REGISTER_MOVE_COST. */ | |
145 | ||
146 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
147 | ||
148 | /* Similar, but here we don't have to move if the first index is a subset | |
149 | of the second so in that case the cost is zero. */ | |
150 | ||
151 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
152 | ||
54dac99e RK |
153 | /* Function called only once to initialize the above data on reg usage. |
154 | Once this is done, various switches may override. */ | |
155 | ||
156 | void | |
157 | init_reg_sets () | |
158 | { | |
159 | register int i, j; | |
160 | ||
161 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); | |
162 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
163 | bzero (global_regs, sizeof global_regs); | |
164 | ||
165 | /* Compute number of hard regs in each class. */ | |
166 | ||
167 | bzero (reg_class_size, sizeof reg_class_size); | |
168 | for (i = 0; i < N_REG_CLASSES; i++) | |
169 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
170 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
171 | reg_class_size[i]++; | |
172 | ||
173 | /* Initialize the table of subunions. | |
174 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
175 | that is contained in the union of classes I and J. */ | |
176 | ||
177 | for (i = 0; i < N_REG_CLASSES; i++) | |
178 | { | |
179 | for (j = 0; j < N_REG_CLASSES; j++) | |
180 | { | |
181 | #ifdef HARD_REG_SET | |
182 | register /* Declare it register if it's a scalar. */ | |
183 | #endif | |
184 | HARD_REG_SET c; | |
185 | register int k; | |
186 | ||
187 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
188 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
189 | for (k = 0; k < N_REG_CLASSES; k++) | |
190 | { | |
191 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
192 | subclass1); | |
193 | continue; | |
194 | ||
195 | subclass1: | |
196 | /* keep the largest subclass */ /* SPEE 900308 */ | |
197 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
198 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
199 | subclass2); | |
200 | reg_class_subunion[i][j] = (enum reg_class) k; | |
201 | subclass2: | |
202 | ; | |
203 | } | |
204 | } | |
205 | } | |
206 | ||
207 | /* Initialize the table of superunions. | |
208 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
209 | containing the union of classes I and J. */ | |
210 | ||
211 | for (i = 0; i < N_REG_CLASSES; i++) | |
212 | { | |
213 | for (j = 0; j < N_REG_CLASSES; j++) | |
214 | { | |
215 | #ifdef HARD_REG_SET | |
216 | register /* Declare it register if it's a scalar. */ | |
217 | #endif | |
218 | HARD_REG_SET c; | |
219 | register int k; | |
220 | ||
221 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
222 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
223 | for (k = 0; k < N_REG_CLASSES; k++) | |
224 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
225 | ||
226 | superclass: | |
227 | reg_class_superunion[i][j] = (enum reg_class) k; | |
228 | } | |
229 | } | |
230 | ||
231 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
232 | First clear the whole table, then add the elements as they are found. */ | |
233 | ||
234 | for (i = 0; i < N_REG_CLASSES; i++) | |
235 | { | |
236 | for (j = 0; j < N_REG_CLASSES; j++) | |
237 | { | |
238 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
239 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
240 | } | |
241 | } | |
242 | ||
243 | for (i = 0; i < N_REG_CLASSES; i++) | |
244 | { | |
245 | if (i == (int) NO_REGS) | |
246 | continue; | |
247 | ||
248 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
249 | { | |
250 | enum reg_class *p; | |
251 | ||
252 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
253 | subclass); | |
254 | continue; | |
255 | subclass: | |
256 | /* Reg class I is a subclass of J. | |
257 | Add J to the table of superclasses of I. */ | |
258 | p = ®_class_superclasses[i][0]; | |
259 | while (*p != LIM_REG_CLASSES) p++; | |
260 | *p = (enum reg_class) j; | |
261 | /* Add I to the table of superclasses of J. */ | |
262 | p = ®_class_subclasses[j][0]; | |
263 | while (*p != LIM_REG_CLASSES) p++; | |
264 | *p = (enum reg_class) i; | |
265 | } | |
266 | } | |
e4600702 RK |
267 | |
268 | /* Initialize the move cost table. Find every subset of each class | |
269 | and take the maximum cost of moving any subset to any other. */ | |
270 | ||
271 | for (i = 0; i < N_REG_CLASSES; i++) | |
272 | for (j = 0; j < N_REG_CLASSES; j++) | |
273 | { | |
274 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
275 | enum reg_class *p1, *p2; | |
276 | ||
277 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
278 | if (*p2 != i) | |
279 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
280 | ||
281 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
282 | { | |
283 | if (*p1 != j) | |
284 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
285 | ||
286 | for (p2 = ®_class_subclasses[j][0]; | |
287 | *p2 != LIM_REG_CLASSES; p2++) | |
288 | if (*p1 != *p2) | |
289 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
290 | } | |
291 | ||
292 | move_cost[i][j] = cost; | |
293 | ||
294 | if (reg_class_subset_p (i, j)) | |
295 | cost = 0; | |
296 | ||
297 | may_move_cost[i][j] = cost; | |
298 | } | |
54dac99e RK |
299 | } |
300 | ||
301 | /* After switches have been processed, which perhaps alter | |
302 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
303 | ||
304 | void | |
305 | init_reg_sets_1 () | |
306 | { | |
307 | register int i; | |
308 | ||
309 | /* This macro allows the fixed or call-used registers | |
310 | to depend on target flags. */ | |
311 | ||
312 | #ifdef CONDITIONAL_REGISTER_USAGE | |
313 | CONDITIONAL_REGISTER_USAGE; | |
314 | #endif | |
315 | ||
316 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
317 | if (global_regs[i]) | |
318 | { | |
319 | if (call_used_regs[i] && ! fixed_regs[i]) | |
320 | warning ("call-clobbered register used for global register variable"); | |
321 | fixed_regs[i] = 1; | |
322 | /* Prevent saving/restoring of this reg. */ | |
323 | call_used_regs[i] = 1; | |
324 | } | |
325 | ||
326 | /* Initialize "constant" tables. */ | |
327 | ||
328 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
329 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
330 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
331 | ||
332 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
333 | #ifdef STRUCT_VALUE_REGNUM | |
334 | call_fixed_regs[STRUCT_VALUE_REGNUM] = 1; | |
335 | #endif | |
336 | #ifdef STATIC_CHAIN_REGNUM | |
337 | call_fixed_regs[STATIC_CHAIN_REGNUM] = 1; | |
338 | #endif | |
339 | ||
340 | n_non_fixed_regs = 0; | |
341 | ||
342 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
343 | { | |
344 | if (FUNCTION_VALUE_REGNO_P (i)) | |
345 | call_fixed_regs[i] = 1; | |
346 | if (fixed_regs[i]) | |
347 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
348 | else | |
349 | n_non_fixed_regs++; | |
350 | ||
351 | if (call_used_regs[i]) | |
352 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
353 | if (call_fixed_regs[i]) | |
354 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
355 | } | |
356 | } | |
357 | ||
358 | /* Specify the usage characteristics of the register named NAME. | |
359 | It should be a fixed register if FIXED and a | |
360 | call-used register if CALL_USED. */ | |
361 | ||
362 | void | |
363 | fix_register (name, fixed, call_used) | |
364 | char *name; | |
365 | int fixed, call_used; | |
366 | { | |
367 | int i; | |
368 | ||
369 | /* Decode the name and update the primary form of | |
370 | the register info. */ | |
371 | ||
e5c90c23 TW |
372 | if ((i = decode_reg_name (name)) >= 0) |
373 | { | |
374 | fixed_regs[i] = fixed; | |
375 | call_used_regs[i] = call_used; | |
376 | } | |
377 | else | |
54dac99e RK |
378 | { |
379 | warning ("unknown register name: %s", name); | |
54dac99e RK |
380 | } |
381 | } | |
382 | \f | |
383 | /* Now the data and code for the `regclass' pass, which happens | |
384 | just before local-alloc. */ | |
385 | ||
e4600702 RK |
386 | /* The `costs' struct records the cost of using a hard register of each class |
387 | and of using memory for each pseudo. We use this data to set up | |
388 | register class preferences. */ | |
54dac99e | 389 | |
e4600702 | 390 | struct costs |
54dac99e | 391 | { |
e4600702 RK |
392 | int cost[N_REG_CLASSES]; |
393 | int mem_cost; | |
54dac99e RK |
394 | }; |
395 | ||
e4600702 RK |
396 | /* Record the cost of each class for each pseudo. */ |
397 | ||
398 | static struct costs *costs; | |
399 | ||
400 | /* Record the same data by operand number, accumulated for each alternative | |
401 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
402 | alternative. */ | |
403 | ||
404 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
405 | |
406 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
407 | This is available after `regclass' is run. */ | |
408 | ||
409 | static char *prefclass; | |
410 | ||
54d23420 RK |
411 | /* altclass[R] is a register class that we should use for allocating |
412 | pseudo number R if no register in the preferred class is available. | |
413 | If no register in this class is available, memory is preferred. | |
414 | ||
415 | It might appear to be more general to have a bitmask of classes here, | |
416 | but since it is recommended that there be a class corresponding to the | |
417 | union of most major pair of classes, that generality is not required. | |
418 | ||
54dac99e RK |
419 | This is available after `regclass' is run. */ |
420 | ||
54d23420 | 421 | static char *altclass; |
54dac99e | 422 | |
54d23420 | 423 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
424 | |
425 | static int loop_depth; | |
426 | ||
54d23420 RK |
427 | /* Account for the fact that insns within a loop are executed very commonly, |
428 | but don't keep doing this as loops go too deep. */ | |
429 | ||
430 | static int loop_cost; | |
431 | ||
432 | static int copy_cost (); | |
433 | static void record_reg_classes (); | |
434 | static void record_address_regs (); | |
54dac99e RK |
435 | |
436 | ||
437 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
438 | This function is sometimes called before the info has been computed. | |
439 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
440 | ||
441 | enum reg_class | |
442 | reg_preferred_class (regno) | |
443 | int regno; | |
444 | { | |
445 | if (prefclass == 0) | |
446 | return GENERAL_REGS; | |
447 | return (enum reg_class) prefclass[regno]; | |
448 | } | |
449 | ||
e4600702 RK |
450 | enum reg_class |
451 | reg_alternate_class (regno) | |
54dac99e RK |
452 | { |
453 | if (prefclass == 0) | |
e4600702 RK |
454 | return ALL_REGS; |
455 | ||
456 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
457 | } |
458 | ||
459 | /* This prevents dump_flow_info from losing if called | |
460 | before regclass is run. */ | |
461 | ||
462 | void | |
463 | regclass_init () | |
464 | { | |
465 | prefclass = 0; | |
466 | } | |
467 | \f | |
468 | /* This is a pass of the compiler that scans all instructions | |
469 | and calculates the preferred class for each pseudo-register. | |
470 | This information can be accessed later by calling `reg_preferred_class'. | |
471 | This pass comes just before local register allocation. */ | |
472 | ||
473 | void | |
474 | regclass (f, nregs) | |
475 | rtx f; | |
476 | int nregs; | |
477 | { | |
478 | #ifdef REGISTER_CONSTRAINTS | |
479 | register rtx insn; | |
e4600702 RK |
480 | register int i, j; |
481 | struct costs init_cost; | |
482 | rtx set; | |
483 | int pass; | |
54dac99e RK |
484 | |
485 | init_recog (); | |
486 | ||
e4600702 RK |
487 | init_cost.mem_cost = 10000; |
488 | for (i = 0; i < N_REG_CLASSES; i++) | |
489 | init_cost.cost[i] = 10000; | |
54dac99e | 490 | |
e4600702 RK |
491 | /* Normally we scan the insns once and determine the best class to use for |
492 | each register. However, if -fexpensive_optimizations are on, we do so | |
493 | twice, the second time using the tentative best classes to guide the | |
494 | selection. */ | |
54dac99e | 495 | |
e4600702 RK |
496 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
497 | { | |
498 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 499 | |
e4600702 RK |
500 | costs = (struct costs *) alloca (nregs * sizeof (struct costs)); |
501 | bzero (costs, nregs * sizeof (struct costs)); | |
54dac99e | 502 | |
e4600702 RK |
503 | loop_depth = 0, loop_cost = 1; |
504 | ||
505 | /* Scan the instructions and record each time it would | |
506 | save code to put a certain register in a certain class. */ | |
507 | ||
508 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 509 | { |
e4600702 RK |
510 | char *constraints[MAX_RECOG_OPERANDS]; |
511 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
512 | int nalternatives; | |
513 | int noperands; | |
514 | ||
515 | /* Show that an insn inside a loop is likely to be executed three | |
516 | times more than insns outside a loop. This is much more agressive | |
517 | than the assumptions made elsewhere and is being tried as an | |
518 | experiment. */ | |
519 | ||
520 | if (GET_CODE (insn) == NOTE | |
521 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
522 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
523 | else if (GET_CODE (insn) == NOTE | |
524 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
525 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
526 | ||
527 | else if ((GET_CODE (insn) == INSN | |
528 | && GET_CODE (PATTERN (insn)) != USE | |
529 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
530 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) | |
531 | || (GET_CODE (insn) == JUMP_INSN | |
532 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
533 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
534 | || GET_CODE (insn) == CALL_INSN) | |
54dac99e | 535 | { |
e4600702 RK |
536 | if (GET_CODE (insn) == INSN |
537 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) | |
538 | { | |
37366632 | 539 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, |
e4600702 RK |
540 | constraints, modes); |
541 | nalternatives = n_occurrences (',', constraints[0]) + 1; | |
542 | } | |
543 | else | |
544 | { | |
545 | int insn_code_number = recog_memoized (insn); | |
546 | rtx note; | |
54dac99e | 547 | |
e4600702 RK |
548 | set = single_set (insn); |
549 | insn_extract (insn); | |
54dac99e | 550 | |
e4600702 RK |
551 | nalternatives = insn_n_alternatives[insn_code_number]; |
552 | noperands = insn_n_operands[insn_code_number]; | |
54dac99e | 553 | |
e4600702 RK |
554 | /* If this insn loads a parameter from its stack slot, then |
555 | it represents a savings, rather than a cost, if the | |
556 | parameter is stored in memory. Record this fact. */ | |
54dac99e | 557 | |
e4600702 RK |
558 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
559 | && GET_CODE (SET_SRC (set)) == MEM | |
37366632 RK |
560 | && (note = find_reg_note (insn, REG_EQUIV, |
561 | NULL_RTX)) != 0 | |
e4600702 RK |
562 | && GET_CODE (XEXP (note, 0)) == MEM) |
563 | { | |
564 | costs[REGNO (SET_DEST (set))].mem_cost | |
565 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set))) | |
566 | * loop_cost); | |
567 | record_address_regs (XEXP (SET_SRC (set), 0), | |
568 | BASE_REG_CLASS, loop_cost * 2); | |
569 | continue; | |
570 | } | |
571 | ||
572 | /* Improve handling of two-address insns such as | |
573 | (set X (ashift CONST Y)) where CONST must be made to | |
574 | match X. Change it into two insns: (set X CONST) | |
575 | (set X (ashift X Y)). If we left this for reloading, it | |
576 | would probably get three insns because X and Y might go | |
577 | in the same place. This prevents X and Y from receiving | |
578 | the same hard reg. | |
579 | ||
580 | We can only do this if the modes of operands 0 and 1 | |
581 | (which might not be the same) are tieable and we only need | |
582 | do this during our first pass. */ | |
583 | ||
584 | if (pass == 0 && optimize | |
585 | && noperands >= 3 | |
586 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
587 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
588 | && CONSTANT_P (recog_operand[1]) | |
589 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
590 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
591 | && GET_CODE (recog_operand[0]) == REG | |
592 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
593 | insn_operand_mode[insn_code_number][1])) | |
594 | { | |
595 | rtx previnsn = prev_real_insn (insn); | |
596 | rtx dest | |
597 | = gen_lowpart (insn_operand_mode[insn_code_number][1], | |
598 | recog_operand[0]); | |
599 | rtx newinsn | |
600 | = emit_insn_before (gen_move_insn (dest, | |
601 | recog_operand[1]), | |
602 | insn); | |
603 | ||
604 | /* If this insn was the start of a basic block, | |
61b01243 RS |
605 | include the new insn in that block. |
606 | We need not check for code_label here; | |
607 | while a basic block can start with a code_label, | |
608 | INSN could not be at the beginning of that block. */ | |
e4600702 RK |
609 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) |
610 | { | |
611 | int b; | |
612 | for (b = 0; b < n_basic_blocks; b++) | |
613 | if (insn == basic_block_head[b]) | |
614 | basic_block_head[b] = newinsn; | |
615 | } | |
616 | ||
617 | /* This makes one more setting of new insns's dest. */ | |
618 | reg_n_sets[REGNO (recog_operand[0])]++; | |
619 | ||
20912ad0 RK |
620 | *recog_operand_loc[1] = recog_operand[0]; |
621 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
622 | if (recog_dup_num[i] == 1) | |
623 | *recog_dup_loc[i] = recog_operand[0]; | |
624 | ||
e4600702 RK |
625 | insn = PREV_INSN (newinsn); |
626 | continue; | |
627 | } | |
54dac99e | 628 | |
e4600702 RK |
629 | /* If this is setting a pseudo from another pseudo or the |
630 | sum of a pseudo and a constant integer and the other | |
631 | pseudo is known to be a pointer, set the destination to | |
632 | be a pointer as well. | |
633 | ||
634 | Likewise if it is setting the destination from an address | |
635 | or from a value equivalent to an address or to the sum of | |
636 | an address and something else. | |
637 | ||
638 | But don't do any of this if the pseudo corresponds to | |
639 | a user variable since it should have already been set | |
640 | as a pointer based on the type. | |
641 | ||
642 | There is no point in doing this during our second | |
643 | pass since not enough should have changed. */ | |
644 | ||
645 | if (pass == 0 && set != 0 && GET_CODE (SET_DEST (set)) == REG | |
646 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER | |
647 | && ! REG_USERVAR_P (SET_DEST (set)) | |
648 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (set))) | |
649 | && ((GET_CODE (SET_SRC (set)) == REG | |
650 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (set)))) | |
651 | || ((GET_CODE (SET_SRC (set)) == PLUS | |
652 | || GET_CODE (SET_SRC (set)) == LO_SUM) | |
653 | && (GET_CODE (XEXP (SET_SRC (set), 1)) | |
654 | == CONST_INT) | |
655 | && GET_CODE (XEXP (SET_SRC (set), 0)) == REG | |
656 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (set), 0)))) | |
657 | || GET_CODE (SET_SRC (set)) == CONST | |
658 | || GET_CODE (SET_SRC (set)) == SYMBOL_REF | |
659 | || GET_CODE (SET_SRC (set)) == LABEL_REF | |
660 | || (GET_CODE (SET_SRC (set)) == HIGH | |
661 | && (GET_CODE (XEXP (SET_SRC (set), 0)) == CONST | |
662 | || (GET_CODE (XEXP (SET_SRC (set), 0)) | |
663 | == SYMBOL_REF) | |
664 | || (GET_CODE (XEXP (SET_SRC (set), 0)) | |
665 | == LABEL_REF))) | |
666 | || ((GET_CODE (SET_SRC (set)) == PLUS | |
667 | || GET_CODE (SET_SRC (set)) == LO_SUM) | |
668 | && (GET_CODE (XEXP (SET_SRC (set), 1)) == CONST | |
669 | || (GET_CODE (XEXP (SET_SRC (set), 1)) | |
670 | == SYMBOL_REF) | |
671 | || (GET_CODE (XEXP (SET_SRC (set), 1)) | |
672 | == LABEL_REF))) | |
673 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
674 | && (GET_CODE (XEXP (note, 0)) == CONST | |
675 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
676 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
677 | REGNO_POINTER_FLAG (REGNO (SET_DEST (set))) = 1; | |
678 | ||
679 | for (i = 0; i < noperands; i++) | |
680 | { | |
681 | constraints[i] | |
682 | = insn_operand_constraint[insn_code_number][i]; | |
683 | modes[i] = insn_operand_mode[insn_code_number][i]; | |
684 | } | |
685 | } | |
54dac99e | 686 | |
e4600702 RK |
687 | /* If we get here, we are set up to record the costs of all the |
688 | operands for this insn. Start by initializing the costs. | |
689 | Then handle any address registers. Finally record the desired | |
690 | classes for any pseudos, doing it twice if some pair of | |
691 | operands are commutative. */ | |
692 | ||
693 | for (i = 0; i < noperands; i++) | |
54dac99e | 694 | { |
e4600702 RK |
695 | op_costs[i] = init_cost; |
696 | ||
697 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
698 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
699 | ||
700 | if (GET_CODE (recog_operand[i]) == MEM) | |
701 | record_address_regs (XEXP (recog_operand[i], 0), | |
702 | BASE_REG_CLASS, loop_cost * 2); | |
703 | else if (constraints[i][0] == 'p') | |
704 | record_address_regs (recog_operand[i], | |
705 | BASE_REG_CLASS, loop_cost * 2); | |
54dac99e | 706 | } |
e4600702 RK |
707 | |
708 | /* Check for commutative in a separate loop so everything will | |
709 | have been initialized. Don't bother doing anything if the | |
710 | second operand is a constant since that is the case | |
711 | for which the constraints should have been written. */ | |
54dac99e | 712 | |
e4600702 RK |
713 | for (i = 0; i < noperands; i++) |
714 | if (constraints[i][0] == '%' | |
715 | && ! CONSTANT_P (recog_operand[i+1])) | |
716 | { | |
717 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
718 | int j; | |
719 | ||
720 | /* Handle commutative operands by swapping the constraints. | |
721 | We assume the modes are the same. */ | |
722 | ||
723 | for (j = 0; j < noperands; j++) | |
724 | xconstraints[j] = constraints[j]; | |
725 | ||
726 | xconstraints[i] = constraints[i+1]; | |
727 | xconstraints[i+1] = constraints[i]; | |
728 | record_reg_classes (nalternatives, noperands, | |
729 | recog_operand, modes, xconstraints, | |
54dac99e | 730 | insn); |
e4600702 | 731 | } |
54dac99e | 732 | |
e4600702 RK |
733 | record_reg_classes (nalternatives, noperands, recog_operand, |
734 | modes, constraints, insn); | |
54dac99e | 735 | |
e4600702 RK |
736 | /* Now add the cost for each operand to the total costs for |
737 | its register. */ | |
54dac99e | 738 | |
e4600702 RK |
739 | for (i = 0; i < noperands; i++) |
740 | if (GET_CODE (recog_operand[i]) == REG | |
741 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
742 | { | |
743 | int regno = REGNO (recog_operand[i]); | |
744 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
745 | ||
746 | p->mem_cost += q->mem_cost * loop_cost; | |
747 | for (j = 0; j < N_REG_CLASSES; j++) | |
748 | p->cost[j] += q->cost[j] * loop_cost; | |
749 | } | |
54dac99e RK |
750 | } |
751 | } | |
54dac99e | 752 | |
e4600702 RK |
753 | /* Now for each register look at how desirable each class is |
754 | and find which class is preferred. Store that in | |
755 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
756 | class any of whose registers is better than memory. */ | |
54dac99e | 757 | |
e4600702 RK |
758 | if (pass == 0) |
759 | { | |
760 | prefclass = (char *) oballoc (nregs); | |
761 | altclass = (char *) oballoc (nregs); | |
762 | } | |
54dac99e | 763 | |
e4600702 | 764 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 765 | { |
ca3c6eae | 766 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
767 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
768 | /* This is an enum reg_class, but we call it an int | |
769 | to save lots of casts. */ | |
770 | register int class; | |
771 | register struct costs *p = &costs[i]; | |
772 | ||
773 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 774 | { |
e4600702 RK |
775 | /* Ignore classes that are too small for this operand. */ |
776 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) | |
777 | > reg_class_size[class]) | |
778 | ; | |
779 | else if (p->cost[class] < best_cost) | |
780 | { | |
781 | best_cost = p->cost[class]; | |
782 | best = (enum reg_class) class; | |
783 | } | |
784 | else if (p->cost[class] == best_cost) | |
785 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 786 | } |
54dac99e | 787 | |
e4600702 RK |
788 | /* Record the alternate register class; i.e., a class for which |
789 | every register in it is better than using memory. If adding a | |
790 | class would make a smaller class (i.e., no union of just those | |
791 | classes exists), skip that class. The major unions of classes | |
792 | should be provided as a register class. Don't do this if we | |
793 | will be doing it again later. */ | |
794 | ||
795 | if (pass == 1 || ! flag_expensive_optimizations) | |
796 | for (class = 0; class < N_REG_CLASSES; class++) | |
797 | if (p->cost[class] < p->mem_cost | |
798 | && (reg_class_size[reg_class_subunion[(int) alt][class]] | |
799 | > reg_class_size[(int) alt])) | |
800 | alt = reg_class_subunion[(int) alt][class]; | |
801 | ||
802 | /* If we don't add any classes, nothing to try. */ | |
803 | if (alt == best) | |
804 | alt = (int) NO_REGS; | |
805 | ||
806 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
807 | prefclass[i] = (int) best; | |
808 | altclass[i] = (int) alt; | |
809 | } | |
54dac99e RK |
810 | } |
811 | #endif /* REGISTER_CONSTRAINTS */ | |
812 | } | |
813 | \f | |
814 | #ifdef REGISTER_CONSTRAINTS | |
815 | ||
e4600702 RK |
816 | /* Record the cost of using memory or registers of various classes for |
817 | the operands in INSN. | |
54dac99e | 818 | |
e4600702 | 819 | N_ALTS is the number of alternatives. |
54dac99e | 820 | |
e4600702 RK |
821 | N_OPS is the number of operands. |
822 | ||
823 | OPS is an array of the operands. | |
824 | ||
825 | MODES are the modes of the operands, in case any are VOIDmode. | |
826 | ||
827 | CONSTRAINTS are the constraints to use for the operands. This array | |
828 | is modified by this procedure. | |
829 | ||
830 | This procedure works alternative by alternative. For each alternative | |
831 | we assume that we will be able to allocate all pseudos to their ideal | |
832 | register class and calculate the cost of using that alternative. Then | |
833 | we compute for each operand that is a pseudo-register, the cost of | |
834 | having the pseudo allocated to each register class and using it in that | |
835 | alternative. To this cost is added the cost of the alternative. | |
836 | ||
837 | The cost of each class for this insn is its lowest cost among all the | |
838 | alternatives. */ | |
839 | ||
840 | static void | |
841 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
842 | int n_alts; | |
843 | int n_ops; | |
844 | rtx *ops; | |
845 | enum machine_mode *modes; | |
54dac99e | 846 | char **constraints; |
e4600702 | 847 | rtx insn; |
54dac99e | 848 | { |
e4600702 RK |
849 | int alt; |
850 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; | |
851 | int i, j; | |
852 | ||
853 | /* By default, each operand is an input operand. */ | |
854 | ||
855 | for (i = 0; i < n_ops; i++) | |
856 | op_types[i] = OP_READ; | |
54dac99e | 857 | |
e4600702 RK |
858 | /* Process each alternative, each time minimizing an operand's cost with |
859 | the cost for each operand in that alternative. */ | |
54dac99e | 860 | |
e4600702 | 861 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 862 | { |
e4600702 RK |
863 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
864 | int alt_fail = 0; | |
865 | int alt_cost = 0; | |
866 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
867 | int class; | |
54dac99e | 868 | |
e4600702 RK |
869 | for (i = 0; i < n_ops; i++) |
870 | { | |
871 | char *p = constraints[i]; | |
872 | rtx op = ops[i]; | |
873 | enum machine_mode mode = modes[i]; | |
874 | int allows_mem = 0; | |
875 | int win = 0; | |
876 | char c; | |
54dac99e | 877 | |
e4600702 RK |
878 | /* If this operand has no constraints at all, we can conclude |
879 | nothing about it since anything is valid. */ | |
54dac99e | 880 | |
e4600702 RK |
881 | if (*p == 0) |
882 | { | |
883 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
884 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 885 | |
e4600702 RK |
886 | continue; |
887 | } | |
54dac99e | 888 | |
e4600702 RK |
889 | /* If this alternative is only relevant when this operand |
890 | matches a previous operand, we do different things depending | |
891 | on whether this operand is a pseudo-reg or not. */ | |
54dac99e | 892 | |
e4600702 RK |
893 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
894 | { | |
895 | j = p[0] - '0'; | |
896 | classes[i] = classes[j]; | |
897 | ||
898 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
899 | { | |
900 | /* If this matches the other operand, we have no added | |
901 | cost. */ | |
902 | if (rtx_equal_p (ops[j], op)) | |
903 | ; | |
904 | ||
905 | /* If we can't put the other operand into a register, this | |
906 | alternative can't be used. */ | |
907 | ||
908 | else if (classes[j] == NO_REGS) | |
909 | alt_fail = 1; | |
910 | ||
911 | /* Otherwise, add to the cost of this alternative the cost | |
912 | to copy this operand to the register used for the other | |
913 | operand. */ | |
914 | ||
915 | else | |
916 | alt_cost += copy_cost (op, mode, classes[j], 1); | |
917 | } | |
918 | ||
919 | else | |
920 | { | |
921 | /* The costs of this operand are the same as that of the | |
922 | other operand. However, if we cannot tie them, this | |
923 | alternative needs to do a copy, which is one | |
924 | instruction. */ | |
925 | ||
926 | this_op_costs[i] = this_op_costs[j]; | |
927 | if (! find_reg_note (insn, REG_DEAD, op)) | |
928 | alt_cost += 2; | |
929 | } | |
930 | ||
931 | continue; | |
932 | } | |
933 | ||
934 | /* Scan all the constraint letters. See if the operand matches | |
935 | any of the constraints. Collect the valid register classes | |
936 | and see if this operand accepts memory. */ | |
937 | ||
938 | classes[i] = NO_REGS; | |
939 | while (*p && (c = *p++) != ',') | |
940 | switch (c) | |
941 | { | |
942 | case '=': | |
943 | op_types[i] = OP_WRITE; | |
944 | break; | |
945 | ||
946 | case '+': | |
947 | op_types[i] = OP_READ_WRITE; | |
948 | break; | |
949 | ||
950 | case '*': | |
951 | /* Ignore the next letter for this pass. */ | |
952 | p++; | |
953 | break; | |
954 | ||
955 | case '%': | |
956 | case '?': case '!': case '#': | |
957 | case '&': | |
958 | case '0': case '1': case '2': case '3': case '4': | |
959 | case 'p': | |
960 | break; | |
961 | ||
962 | case 'm': case 'o': case 'V': | |
963 | /* It doesn't seem worth distingishing between offsettable | |
964 | and non-offsettable addresses here. */ | |
965 | allows_mem = 1; | |
966 | if (GET_CODE (op) == MEM) | |
967 | win = 1; | |
968 | break; | |
969 | ||
970 | case '<': | |
971 | if (GET_CODE (op) == MEM | |
972 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
973 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
974 | win = 1; | |
975 | break; | |
976 | ||
977 | case '>': | |
978 | if (GET_CODE (op) == MEM | |
979 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
980 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
981 | win = 1; | |
982 | break; | |
983 | ||
984 | case 'E': | |
985 | /* Match any floating double constant, but only if | |
986 | we can examine the bits of it reliably. */ | |
987 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 988 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
989 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
990 | break; | |
991 | if (GET_CODE (op) == CONST_DOUBLE) | |
992 | win = 1; | |
993 | break; | |
994 | ||
995 | case 'F': | |
996 | if (GET_CODE (op) == CONST_DOUBLE) | |
997 | win = 1; | |
998 | break; | |
999 | ||
1000 | case 'G': | |
1001 | case 'H': | |
1002 | if (GET_CODE (op) == CONST_DOUBLE | |
1003 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1004 | win = 1; | |
1005 | break; | |
1006 | ||
1007 | case 's': | |
1008 | if (GET_CODE (op) == CONST_INT | |
1009 | || (GET_CODE (op) == CONST_DOUBLE | |
1010 | && GET_MODE (op) == VOIDmode)) | |
1011 | break; | |
1012 | case 'i': | |
1013 | if (CONSTANT_P (op) | |
1014 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1015 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1016 | #endif | |
1017 | ) | |
1018 | win = 1; | |
1019 | break; | |
1020 | ||
1021 | case 'n': | |
1022 | if (GET_CODE (op) == CONST_INT | |
1023 | || (GET_CODE (op) == CONST_DOUBLE | |
1024 | && GET_MODE (op) == VOIDmode)) | |
1025 | win = 1; | |
1026 | break; | |
1027 | ||
1028 | case 'I': | |
1029 | case 'J': | |
1030 | case 'K': | |
1031 | case 'L': | |
1032 | case 'M': | |
1033 | case 'N': | |
1034 | case 'O': | |
1035 | case 'P': | |
1036 | if (GET_CODE (op) == CONST_INT | |
1037 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1038 | win = 1; | |
1039 | break; | |
1040 | ||
1041 | case 'X': | |
1042 | win = 1; | |
1043 | break; | |
54dac99e | 1044 | |
54dac99e | 1045 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1046 | case 'Q': |
1047 | case 'R': | |
1048 | case 'S': | |
1049 | case 'T': | |
1050 | case 'U': | |
1051 | if (EXTRA_CONSTRAINT (op, c)) | |
1052 | win = 1; | |
1053 | break; | |
1054 | #endif | |
1055 | ||
1056 | case 'g': | |
1057 | if (GET_CODE (op) == MEM | |
1058 | || (CONSTANT_P (op) | |
1059 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1060 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1061 | #endif |
e4600702 RK |
1062 | )) |
1063 | win = 1; | |
1064 | allows_mem = 1; | |
1065 | case 'r': | |
1066 | classes[i] | |
1067 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1068 | break; | |
1069 | ||
1070 | default: | |
1071 | classes[i] | |
1072 | = reg_class_subunion[(int) classes[i]] | |
1073 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1074 | } | |
1075 | ||
1076 | constraints[i] = p; | |
1077 | ||
1078 | /* How we account for this operand now depends on whether it is a | |
1079 | pseudo register or not. If it is, we first check if any | |
1080 | register classes are valid. If not, we ignore this alternative, | |
1081 | since we want to assume that all pseudos get allocated for | |
1082 | register preferencing. If some register class is valid, compute | |
1083 | the costs of moving the pseudo into that class. */ | |
1084 | ||
1085 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1086 | { |
e4600702 RK |
1087 | if (classes[i] == NO_REGS) |
1088 | alt_fail = 1; | |
1089 | else | |
1090 | { | |
1091 | struct costs *pp = &this_op_costs[i]; | |
1092 | ||
1093 | for (class = 0; class < N_REG_CLASSES; class++) | |
1094 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1095 | ||
1096 | /* If the alternative actually allows memory, make things | |
1097 | a bit cheaper since we won't need an extra insn to | |
1098 | load it. */ | |
1099 | ||
1100 | pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem; | |
1101 | ||
1102 | /* If we have assigned a class to this register in our | |
1103 | first pass, add a cost to this alternative corresponding | |
1104 | to what we would add if this register were not in the | |
1105 | appropriate class. */ | |
1106 | ||
1107 | if (prefclass) | |
1108 | alt_cost | |
1109 | += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; | |
1110 | } | |
4db18574 | 1111 | } |
54dac99e | 1112 | |
e4600702 RK |
1113 | /* Otherwise, if this alternative wins, either because we |
1114 | have already determined that or if we have a hard register of | |
1115 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1116 | |
e4600702 RK |
1117 | else if (win |
1118 | || (GET_CODE (op) == REG | |
1119 | && reg_fits_class_p (op, classes[i], 0, mode))) | |
1120 | ; | |
54dac99e | 1121 | |
e4600702 RK |
1122 | /* If registers are valid, the cost of this alternative includes |
1123 | copying the object to and/or from a register. */ | |
54dac99e | 1124 | |
e4600702 RK |
1125 | else if (classes[i] != NO_REGS) |
1126 | { | |
1127 | if (op_types[i] != OP_WRITE) | |
1128 | alt_cost += copy_cost (op, mode, classes[i], 1); | |
54dac99e | 1129 | |
e4600702 RK |
1130 | if (op_types[i] != OP_READ) |
1131 | alt_cost += copy_cost (op, mode, classes[i], 0); | |
1132 | } | |
54dac99e | 1133 | |
e4600702 RK |
1134 | /* The only other way this alternative can be used is if this is a |
1135 | constant that could be placed into memory. */ | |
1136 | ||
1137 | else if (CONSTANT_P (op) && allows_mem) | |
1138 | alt_cost += MEMORY_MOVE_COST (mode); | |
1139 | else | |
1140 | alt_fail = 1; | |
1141 | } | |
1142 | ||
1143 | if (alt_fail) | |
1144 | continue; | |
1145 | ||
1146 | /* Finally, update the costs with the information we've calculated | |
1147 | about this alternative. */ | |
1148 | ||
1149 | for (i = 0; i < n_ops; i++) | |
1150 | if (GET_CODE (ops[i]) == REG | |
1151 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1152 | { |
e4600702 RK |
1153 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1154 | int scale = 1 + (op_types[i] == OP_READ_WRITE); | |
54dac99e | 1155 | |
e4600702 RK |
1156 | pp->mem_cost = MIN (pp->mem_cost, |
1157 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1158 | |
e4600702 RK |
1159 | for (class = 0; class < N_REG_CLASSES; class++) |
1160 | pp->cost[class] = MIN (pp->cost[class], | |
1161 | (qq->cost[class] + alt_cost) * scale); | |
1162 | } | |
1163 | } | |
54dac99e | 1164 | } |
e4600702 RK |
1165 | \f |
1166 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1167 | TO_P is zero) a register of class CLASS in mode MODE. | |
1168 | ||
1169 | X must not be a pseudo. */ | |
1170 | ||
1171 | static int | |
1172 | copy_cost (x, mode, class, to_p) | |
1173 | rtx x; | |
1174 | enum machine_mode mode; | |
1175 | enum reg_class class; | |
1176 | int to_p; | |
1177 | { | |
1178 | enum reg_class secondary_class = NO_REGS; | |
1179 | ||
1180 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1181 | assuming optimal allocation. */ | |
1182 | ||
1183 | if (GET_CODE (x) == SCRATCH) | |
1184 | return 0; | |
1185 | ||
1186 | /* Get the class we will actually use for a reload. */ | |
1187 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1188 | ||
1189 | #ifdef HAVE_SECONDARY_RELOADS | |
1190 | /* If we need a secondary reload (we assume here that we are using | |
1191 | the secondary reload as an intermediate, not a scratch register), the | |
1192 | cost is that to load the input into the intermediate register, then | |
1193 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1194 | ||
1195 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1196 | if (to_p == 1) | |
1197 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1198 | #endif | |
1199 | ||
1200 | #ifdef SECONARY_OUTPUT_RELOAD_CLASS | |
1201 | if (! to_p) | |
1202 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1203 | #endif | |
1204 | ||
1205 | if (secondary_class != NO_REGS) | |
1206 | return (move_cost[(int) secondary_class][(int) class] | |
1207 | + copy_cost (x, mode, secondary_class, 2)); | |
1208 | #endif /* HAVE_SECONARY_RELOADS */ | |
1209 | ||
1210 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1211 | cost to move between the register classes, and use 2 for everything | |
1212 | else (constants). */ | |
1213 | ||
1214 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
1215 | return MEMORY_MOVE_COST (mode); | |
54dac99e | 1216 | |
e4600702 RK |
1217 | else if (GET_CODE (x) == REG) |
1218 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1219 | ||
1220 | else | |
1221 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1222 | return 2; | |
1223 | } | |
1224 | \f | |
54dac99e RK |
1225 | /* Record the pseudo registers we must reload into hard registers |
1226 | in a subexpression of a memory address, X. | |
e4600702 RK |
1227 | |
1228 | CLASS is the class that the register needs to be in and is either | |
1229 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1230 | ||
1231 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1232 | can represent half-cost adjustments). */ | |
54dac99e | 1233 | |
197d6480 | 1234 | static void |
e4600702 | 1235 | record_address_regs (x, class, scale) |
54dac99e | 1236 | rtx x; |
e4600702 RK |
1237 | enum reg_class class; |
1238 | int scale; | |
54dac99e RK |
1239 | { |
1240 | register enum rtx_code code = GET_CODE (x); | |
1241 | ||
1242 | switch (code) | |
1243 | { | |
1244 | case CONST_INT: | |
1245 | case CONST: | |
1246 | case CC0: | |
1247 | case PC: | |
1248 | case SYMBOL_REF: | |
1249 | case LABEL_REF: | |
1250 | return; | |
1251 | ||
1252 | case PLUS: | |
1253 | /* When we have an address that is a sum, | |
1254 | we must determine whether registers are "base" or "index" regs. | |
1255 | If there is a sum of two registers, we must choose one to be | |
1256 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1257 | to make a good choice most of the time. We only need to do this |
1258 | on machines that can have two registers in an address and where | |
1259 | the base and index register classes are different. | |
1260 | ||
1261 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1262 | that seems bogus since it should only be set when we are sure | |
1263 | the register is being used as a pointer. */ | |
1264 | ||
54dac99e RK |
1265 | { |
1266 | rtx arg0 = XEXP (x, 0); | |
1267 | rtx arg1 = XEXP (x, 1); | |
1268 | register enum rtx_code code0 = GET_CODE (arg0); | |
1269 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1270 | |
1271 | /* Look inside subregs. */ | |
e4600702 | 1272 | if (code0 == SUBREG) |
54dac99e | 1273 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1274 | if (code1 == SUBREG) |
54dac99e RK |
1275 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1276 | ||
e4600702 RK |
1277 | /* If this machine only allows one register per address, it must |
1278 | be in the first operand. */ | |
1279 | ||
1280 | if (MAX_REGS_PER_ADDRESS == 1) | |
1281 | record_address_regs (arg0, class, scale); | |
1282 | ||
1283 | /* If index and base registers are the same on this machine, just | |
1284 | record registers in any non-constant operands. We assume here, | |
1285 | as well as in the tests below, that all addresses are in | |
1286 | canonical form. */ | |
1287 | ||
1288 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1289 | { |
e4600702 RK |
1290 | record_address_regs (arg0, class, scale); |
1291 | if (! CONSTANT_P (arg1)) | |
1292 | record_address_regs (arg1, class, scale); | |
54dac99e | 1293 | } |
e4600702 RK |
1294 | |
1295 | /* If the second operand is a constant integer, it doesn't change | |
1296 | what class the first operand must be. */ | |
1297 | ||
1298 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1299 | record_address_regs (arg0, class, scale); | |
1300 | ||
1301 | /* If the second operand is a symbolic constant, the first operand | |
1302 | must be an index register. */ | |
1303 | ||
1304 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1305 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1306 | ||
1307 | /* If this the sum of two registers where the first is known to be a | |
1308 | pointer, it must be a base register with the second an index. */ | |
1309 | ||
1310 | else if (code0 == REG && code1 == REG | |
1311 | && REGNO_POINTER_FLAG (REGNO (arg0))) | |
54dac99e | 1312 | { |
e4600702 RK |
1313 | record_address_regs (arg0, BASE_REG_CLASS, scale); |
1314 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
54dac99e | 1315 | } |
e4600702 RK |
1316 | |
1317 | /* If this is the sum of two registers and neither is known to | |
1318 | be a pointer, count equal chances that each might be a base | |
1319 | or index register. This case should be rare. */ | |
1320 | ||
1321 | else if (code0 == REG && code1 == REG | |
1322 | && ! REGNO_POINTER_FLAG (REGNO (arg0)) | |
1323 | && ! REGNO_POINTER_FLAG (REGNO (arg1))) | |
54dac99e | 1324 | { |
e4600702 RK |
1325 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1326 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1327 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1328 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e RK |
1329 | } |
1330 | ||
e4600702 RK |
1331 | /* In all other cases, the first operand is an index and the |
1332 | second is the base. */ | |
54dac99e | 1333 | |
e4600702 RK |
1334 | else |
1335 | { | |
1336 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1337 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1338 | } | |
54dac99e RK |
1339 | } |
1340 | break; | |
1341 | ||
1342 | case POST_INC: | |
1343 | case PRE_INC: | |
1344 | case POST_DEC: | |
1345 | case PRE_DEC: | |
1346 | /* Double the importance of a pseudo register that is incremented | |
1347 | or decremented, since it would take two extra insns | |
1348 | if it ends up in the wrong place. */ | |
e4600702 RK |
1349 | |
1350 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1351 | break; |
1352 | ||
1353 | case REG: | |
1354 | { | |
e4600702 RK |
1355 | register struct costs *pp = &costs[REGNO (x)]; |
1356 | register int i; | |
54dac99e | 1357 | |
e4600702 | 1358 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2; |
54dac99e | 1359 | |
e4600702 RK |
1360 | for (i = 0; i < N_REG_CLASSES; i++) |
1361 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1362 | } |
1363 | break; | |
1364 | ||
1365 | default: | |
1366 | { | |
1367 | register char *fmt = GET_RTX_FORMAT (code); | |
1368 | register int i; | |
1369 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1370 | if (fmt[i] == 'e') | |
e4600702 | 1371 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1372 | } |
1373 | } | |
1374 | } | |
1375 | #endif /* REGISTER_CONSTRAINTS */ | |
1376 | \f | |
1377 | /* This is the `regscan' pass of the compiler, run just before cse | |
1378 | and again just before loop. | |
1379 | ||
1380 | It finds the first and last use of each pseudo-register | |
1381 | and records them in the vectors regno_first_uid, regno_last_uid | |
1382 | and counts the number of sets in the vector reg_n_sets. | |
1383 | ||
1384 | REPEAT is nonzero the second time this is called. */ | |
1385 | ||
1386 | /* Indexed by pseudo register number, gives uid of first insn using the reg | |
1387 | (as of the time reg_scan is called). */ | |
1388 | ||
051e5bbf | 1389 | int *regno_first_uid; |
54dac99e RK |
1390 | |
1391 | /* Indexed by pseudo register number, gives uid of last insn using the reg | |
1392 | (as of the time reg_scan is called). */ | |
1393 | ||
051e5bbf | 1394 | int *regno_last_uid; |
54dac99e RK |
1395 | |
1396 | /* Record the number of registers we used when we allocated the above two | |
1397 | tables. If we are called again with more than this, we must re-allocate | |
1398 | the tables. */ | |
1399 | ||
1400 | static int highest_regno_in_uid_map; | |
1401 | ||
1402 | /* Maximum number of parallel sets and clobbers in any insn in this fn. | |
1403 | Always at least 3, since the combiner could put that many togetherm | |
1404 | and we want this to remain correct for all the remaining passes. */ | |
1405 | ||
1406 | int max_parallel; | |
1407 | ||
1408 | void reg_scan_mark_refs (); | |
1409 | ||
1410 | void | |
1411 | reg_scan (f, nregs, repeat) | |
1412 | rtx f; | |
1413 | int nregs; | |
1414 | int repeat; | |
1415 | { | |
1416 | register rtx insn; | |
1417 | ||
1418 | if (!repeat || nregs > highest_regno_in_uid_map) | |
1419 | { | |
1420 | /* Leave some spare space in case more regs are allocated. */ | |
1421 | highest_regno_in_uid_map = nregs + nregs / 20; | |
1422 | regno_first_uid | |
051e5bbf | 1423 | = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); |
54dac99e | 1424 | regno_last_uid |
051e5bbf | 1425 | = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); |
54dac99e RK |
1426 | reg_n_sets |
1427 | = (short *) oballoc (highest_regno_in_uid_map * sizeof (short)); | |
1428 | } | |
1429 | ||
051e5bbf RS |
1430 | bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (int)); |
1431 | bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (int)); | |
54dac99e RK |
1432 | bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short)); |
1433 | ||
1434 | max_parallel = 3; | |
1435 | ||
1436 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1437 | if (GET_CODE (insn) == INSN | |
1438 | || GET_CODE (insn) == CALL_INSN | |
1439 | || GET_CODE (insn) == JUMP_INSN) | |
1440 | { | |
1441 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1442 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1443 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
1444 | reg_scan_mark_refs (PATTERN (insn), INSN_UID (insn)); | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | void | |
1449 | reg_scan_mark_refs (x, uid) | |
1450 | rtx x; | |
1451 | int uid; | |
1452 | { | |
1453 | register enum rtx_code code = GET_CODE (x); | |
1454 | register rtx dest; | |
1455 | ||
1456 | switch (code) | |
1457 | { | |
1458 | case CONST_INT: | |
1459 | case CONST: | |
1460 | case CONST_DOUBLE: | |
1461 | case CC0: | |
1462 | case PC: | |
1463 | case SYMBOL_REF: | |
1464 | case LABEL_REF: | |
1465 | case ADDR_VEC: | |
1466 | case ADDR_DIFF_VEC: | |
1467 | return; | |
1468 | ||
1469 | case REG: | |
1470 | { | |
1471 | register int regno = REGNO (x); | |
1472 | ||
1473 | regno_last_uid[regno] = uid; | |
1474 | if (regno_first_uid[regno] == 0) | |
1475 | regno_first_uid[regno] = uid; | |
1476 | } | |
1477 | break; | |
1478 | ||
1479 | case SET: | |
1480 | /* Count a set of the destination if it is a register. */ | |
1481 | for (dest = SET_DEST (x); | |
1482 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
1483 | || GET_CODE (dest) == ZERO_EXTEND; | |
1484 | dest = XEXP (dest, 0)) | |
1485 | ; | |
1486 | ||
1487 | if (GET_CODE (dest) == REG) | |
1488 | reg_n_sets[REGNO (dest)]++; | |
1489 | ||
1490 | /* ... fall through ... */ | |
1491 | ||
1492 | default: | |
1493 | { | |
1494 | register char *fmt = GET_RTX_FORMAT (code); | |
1495 | register int i; | |
1496 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1497 | { | |
1498 | if (fmt[i] == 'e') | |
1499 | reg_scan_mark_refs (XEXP (x, i), uid); | |
1500 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) | |
1501 | { | |
1502 | register int j; | |
1503 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1504 | reg_scan_mark_refs (XVECEXP (x, i, j), uid); | |
1505 | } | |
1506 | } | |
1507 | } | |
1508 | } | |
1509 | } | |
1510 | \f | |
1511 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
1512 | is also in C2. */ | |
1513 | ||
1514 | int | |
1515 | reg_class_subset_p (c1, c2) | |
1516 | register enum reg_class c1; | |
1517 | register enum reg_class c2; | |
1518 | { | |
1519 | if (c1 == c2) return 1; | |
1520 | ||
1521 | if (c2 == ALL_REGS) | |
1522 | win: | |
1523 | return 1; | |
1524 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
1525 | reg_class_contents[(int)c2], | |
1526 | win); | |
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
1531 | ||
1532 | int | |
1533 | reg_classes_intersect_p (c1, c2) | |
1534 | register enum reg_class c1; | |
1535 | register enum reg_class c2; | |
1536 | { | |
1537 | #ifdef HARD_REG_SET | |
1538 | register | |
1539 | #endif | |
1540 | HARD_REG_SET c; | |
1541 | ||
1542 | if (c1 == c2) return 1; | |
1543 | ||
1544 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
1545 | return 1; | |
1546 | ||
1547 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
1548 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
1549 | ||
1550 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
1551 | return 1; | |
1552 | ||
1553 | lose: | |
1554 | return 0; | |
1555 | } | |
1556 |