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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
a5cad800 | 2 | Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
670ee920 | 27 | #include "system.h" |
54dac99e | 28 | #include "rtl.h" |
6baf1cc8 | 29 | #include "tm_p.h" |
54dac99e RK |
30 | #include "hard-reg-set.h" |
31 | #include "flags.h" | |
32 | #include "basic-block.h" | |
33 | #include "regs.h" | |
49ad7cfa | 34 | #include "function.h" |
54dac99e RK |
35 | #include "insn-config.h" |
36 | #include "recog.h" | |
e4600702 RK |
37 | #include "reload.h" |
38 | #include "real.h" | |
10f0ad3d | 39 | #include "toplev.h" |
d6f4ec51 | 40 | #include "output.h" |
8b0212ca | 41 | #include "ggc.h" |
54dac99e RK |
42 | |
43 | #ifndef REGISTER_MOVE_COST | |
44 | #define REGISTER_MOVE_COST(x, y) 2 | |
45 | #endif | |
46 | ||
24deb20a L |
47 | static void init_reg_sets_1 PROTO((void)); |
48 | static void init_reg_modes PROTO((void)); | |
49 | ||
533d0835 RK |
50 | /* If we have auto-increment or auto-decrement and we can have secondary |
51 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 52 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
53 | |
54 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 55 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
56 | #define FORBIDDEN_INC_DEC_CLASSES |
57 | #endif | |
58 | #endif | |
54dac99e RK |
59 | \f |
60 | /* Register tables used by many passes. */ | |
61 | ||
62 | /* Indexed by hard register number, contains 1 for registers | |
63 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
64 | These are the registers that cannot be used to allocate | |
252f342a | 65 | a pseudo reg for general use. */ |
54dac99e RK |
66 | |
67 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
68 | ||
69 | /* Same info as a HARD_REG_SET. */ | |
70 | ||
71 | HARD_REG_SET fixed_reg_set; | |
72 | ||
73 | /* Data for initializing the above. */ | |
74 | ||
75 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
76 | ||
77 | /* Indexed by hard register number, contains 1 for registers | |
78 | that are fixed use or are clobbered by function calls. | |
79 | These are the registers that cannot be used to allocate | |
252f342a MH |
80 | a pseudo reg whose life crosses calls unless we are able |
81 | to save/restore them across the calls. */ | |
54dac99e RK |
82 | |
83 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
84 | ||
85 | /* Same info as a HARD_REG_SET. */ | |
86 | ||
87 | HARD_REG_SET call_used_reg_set; | |
88 | ||
6cad67d2 JL |
89 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
90 | HARD_REG_SET losing_caller_save_reg_set; | |
91 | ||
54dac99e RK |
92 | /* Data for initializing the above. */ |
93 | ||
94 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
95 | ||
96 | /* Indexed by hard register number, contains 1 for registers that are | |
252f342a MH |
97 | fixed use or call used registers that cannot hold quantities across |
98 | calls even if we are willing to save and restore them. call fixed | |
99 | registers are a subset of call used registers. */ | |
54dac99e RK |
100 | |
101 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
102 | ||
103 | /* The same info as a HARD_REG_SET. */ | |
104 | ||
105 | HARD_REG_SET call_fixed_reg_set; | |
106 | ||
107 | /* Number of non-fixed registers. */ | |
108 | ||
109 | int n_non_fixed_regs; | |
110 | ||
111 | /* Indexed by hard register number, contains 1 for registers | |
112 | that are being used for global register decls. | |
113 | These must be exempt from ordinary flow analysis | |
114 | and are also considered fixed. */ | |
115 | ||
116 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
117 | ||
118 | /* Table of register numbers in the order in which to try to use them. */ | |
119 | #ifdef REG_ALLOC_ORDER | |
120 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
121 | #endif | |
122 | ||
123 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
124 | ||
2e0e2b76 CH |
125 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
126 | ||
089e575b RS |
127 | /* The same information, but as an array of unsigned ints. We copy from |
128 | these unsigned ints to the table above. We do this so the tm.h files | |
129 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
130 | |
131 | #define N_REG_INTS \ | |
132 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
133 | ||
089e575b | 134 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 135 | = REG_CLASS_CONTENTS; |
54dac99e RK |
136 | |
137 | /* For each reg class, number of regs it contains. */ | |
138 | ||
139 | int reg_class_size[N_REG_CLASSES]; | |
140 | ||
141 | /* For each reg class, table listing all the containing classes. */ | |
142 | ||
143 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
144 | ||
145 | /* For each reg class, table listing all the classes contained in it. */ | |
146 | ||
147 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
148 | ||
149 | /* For each pair of reg classes, | |
150 | a largest reg class contained in their union. */ | |
151 | ||
152 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
153 | ||
154 | /* For each pair of reg classes, | |
155 | the smallest reg class containing their union. */ | |
156 | ||
157 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
158 | ||
d05c8ee7 RS |
159 | /* Array containing all of the register names */ |
160 | ||
99f44eba | 161 | const char *reg_names[] = REGISTER_NAMES; |
d05c8ee7 | 162 | |
ca4aac00 DE |
163 | /* For each hard register, the widest mode object that it can contain. |
164 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
165 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
166 | register. */ | |
167 | ||
168 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
169 | ||
e4600702 RK |
170 | /* Maximum cost of moving from a register in one class to a register in |
171 | another class. Based on REGISTER_MOVE_COST. */ | |
172 | ||
173 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
174 | ||
175 | /* Similar, but here we don't have to move if the first index is a subset | |
176 | of the second so in that case the cost is zero. */ | |
177 | ||
ee59f29b JH |
178 | static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES]; |
179 | ||
180 | /* Similar, but here we don't have to move if the first index is a superset | |
181 | of the second so in that case the cost is zero. */ | |
182 | ||
183 | static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
e4600702 | 184 | |
533d0835 RK |
185 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
186 | ||
187 | /* These are the classes that regs which are auto-incremented or decremented | |
188 | cannot be put in. */ | |
189 | ||
190 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
191 | ||
192 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
193 | context. */ | |
194 | ||
195 | static char *in_inc_dec; | |
196 | ||
5fcb671c | 197 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 198 | |
473fe49b KR |
199 | #ifdef HAVE_SECONDARY_RELOADS |
200 | ||
201 | /* Sample MEM values for use by memory_move_secondary_cost. */ | |
202 | ||
203 | static rtx top_of_stack[MAX_MACHINE_MODE]; | |
204 | ||
205 | #endif /* HAVE_SECONDARY_RELOADS */ | |
206 | ||
6feacd09 MM |
207 | /* Linked list of reg_info structures allocated for reg_n_info array. |
208 | Grouping all of the allocated structures together in one lump | |
209 | means only one call to bzero to clear them, rather than n smaller | |
210 | calls. */ | |
211 | struct reg_info_data { | |
212 | struct reg_info_data *next; /* next set of reg_info structures */ | |
213 | size_t min_index; /* minimum index # */ | |
214 | size_t max_index; /* maximum index # */ | |
215 | char used_p; /* non-zero if this has been used previously */ | |
216 | reg_info data[1]; /* beginning of the reg_info data */ | |
217 | }; | |
218 | ||
219 | static struct reg_info_data *reg_info_head; | |
220 | ||
c07c7c9d | 221 | /* No more global register variables may be declared; true once |
6c85df69 AH |
222 | regclass has been initialized. */ |
223 | ||
224 | static int no_global_reg_vars = 0; | |
225 | ||
6feacd09 | 226 | |
54dac99e RK |
227 | /* Function called only once to initialize the above data on reg usage. |
228 | Once this is done, various switches may override. */ | |
229 | ||
230 | void | |
231 | init_reg_sets () | |
232 | { | |
233 | register int i, j; | |
234 | ||
2e0e2b76 CH |
235 | /* First copy the register information from the initial int form into |
236 | the regsets. */ | |
237 | ||
238 | for (i = 0; i < N_REG_CLASSES; i++) | |
239 | { | |
240 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
241 | ||
242 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
243 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 244 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
245 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
246 | } | |
247 | ||
54dac99e RK |
248 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
249 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
250 | bzero (global_regs, sizeof global_regs); | |
251 | ||
910bc42d R |
252 | /* Do any additional initialization regsets may need */ |
253 | INIT_ONCE_REG_SET (); | |
254 | } | |
255 | ||
256 | /* After switches have been processed, which perhaps alter | |
257 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
258 | ||
259 | static void | |
260 | init_reg_sets_1 () | |
261 | { | |
262 | register unsigned int i, j; | |
263 | ||
264 | /* This macro allows the fixed or call-used registers | |
265 | and the register classes to depend on target flags. */ | |
266 | ||
267 | #ifdef CONDITIONAL_REGISTER_USAGE | |
268 | CONDITIONAL_REGISTER_USAGE; | |
269 | #endif | |
270 | ||
54dac99e RK |
271 | /* Compute number of hard regs in each class. */ |
272 | ||
4c9a05bc | 273 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
274 | for (i = 0; i < N_REG_CLASSES; i++) |
275 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
276 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
277 | reg_class_size[i]++; | |
278 | ||
279 | /* Initialize the table of subunions. | |
280 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
281 | that is contained in the union of classes I and J. */ | |
282 | ||
283 | for (i = 0; i < N_REG_CLASSES; i++) | |
284 | { | |
285 | for (j = 0; j < N_REG_CLASSES; j++) | |
286 | { | |
287 | #ifdef HARD_REG_SET | |
288 | register /* Declare it register if it's a scalar. */ | |
289 | #endif | |
290 | HARD_REG_SET c; | |
291 | register int k; | |
292 | ||
293 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
294 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
295 | for (k = 0; k < N_REG_CLASSES; k++) | |
296 | { | |
297 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
298 | subclass1); | |
299 | continue; | |
300 | ||
301 | subclass1: | |
302 | /* keep the largest subclass */ /* SPEE 900308 */ | |
303 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
304 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
305 | subclass2); | |
306 | reg_class_subunion[i][j] = (enum reg_class) k; | |
307 | subclass2: | |
308 | ; | |
309 | } | |
310 | } | |
311 | } | |
312 | ||
313 | /* Initialize the table of superunions. | |
314 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
315 | containing the union of classes I and J. */ | |
316 | ||
317 | for (i = 0; i < N_REG_CLASSES; i++) | |
318 | { | |
319 | for (j = 0; j < N_REG_CLASSES; j++) | |
320 | { | |
321 | #ifdef HARD_REG_SET | |
322 | register /* Declare it register if it's a scalar. */ | |
323 | #endif | |
324 | HARD_REG_SET c; | |
325 | register int k; | |
326 | ||
327 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
328 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
329 | for (k = 0; k < N_REG_CLASSES; k++) | |
330 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
331 | ||
332 | superclass: | |
333 | reg_class_superunion[i][j] = (enum reg_class) k; | |
334 | } | |
335 | } | |
336 | ||
337 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
338 | First clear the whole table, then add the elements as they are found. */ | |
339 | ||
340 | for (i = 0; i < N_REG_CLASSES; i++) | |
341 | { | |
342 | for (j = 0; j < N_REG_CLASSES; j++) | |
343 | { | |
344 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
345 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
346 | } | |
347 | } | |
348 | ||
349 | for (i = 0; i < N_REG_CLASSES; i++) | |
350 | { | |
351 | if (i == (int) NO_REGS) | |
352 | continue; | |
353 | ||
354 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
355 | { | |
356 | enum reg_class *p; | |
357 | ||
358 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
359 | subclass); | |
360 | continue; | |
361 | subclass: | |
362 | /* Reg class I is a subclass of J. | |
363 | Add J to the table of superclasses of I. */ | |
364 | p = ®_class_superclasses[i][0]; | |
365 | while (*p != LIM_REG_CLASSES) p++; | |
366 | *p = (enum reg_class) j; | |
367 | /* Add I to the table of superclasses of J. */ | |
368 | p = ®_class_subclasses[j][0]; | |
369 | while (*p != LIM_REG_CLASSES) p++; | |
370 | *p = (enum reg_class) i; | |
371 | } | |
372 | } | |
e4600702 | 373 | |
54dac99e RK |
374 | /* Initialize "constant" tables. */ |
375 | ||
376 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
377 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
378 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
379 | ||
380 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
381 | |
382 | n_non_fixed_regs = 0; | |
383 | ||
384 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
385 | { | |
54dac99e RK |
386 | if (fixed_regs[i]) |
387 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
388 | else | |
389 | n_non_fixed_regs++; | |
390 | ||
391 | if (call_used_regs[i]) | |
392 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
393 | if (call_fixed_regs[i]) | |
394 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
395 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
396 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 397 | } |
acbce667 KR |
398 | |
399 | /* Initialize the move cost table. Find every subset of each class | |
400 | and take the maximum cost of moving any subset to any other. */ | |
401 | ||
402 | for (i = 0; i < N_REG_CLASSES; i++) | |
403 | for (j = 0; j < N_REG_CLASSES; j++) | |
404 | { | |
405 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
406 | enum reg_class *p1, *p2; | |
407 | ||
408 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
409 | if (*p2 != i) | |
410 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
411 | ||
412 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
413 | { | |
414 | if (*p1 != j) | |
415 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
416 | ||
417 | for (p2 = ®_class_subclasses[j][0]; | |
418 | *p2 != LIM_REG_CLASSES; p2++) | |
419 | if (*p1 != *p2) | |
420 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
421 | } | |
422 | ||
423 | move_cost[i][j] = cost; | |
424 | ||
425 | if (reg_class_subset_p (i, j)) | |
ee59f29b JH |
426 | may_move_in_cost[i][j] = 0; |
427 | else | |
428 | may_move_in_cost[i][j] = cost; | |
acbce667 | 429 | |
ee59f29b JH |
430 | if (reg_class_subset_p (j, i)) |
431 | may_move_out_cost[i][j] = 0; | |
432 | else | |
433 | may_move_out_cost[i][j] = cost; | |
acbce667 | 434 | } |
c27c5281 DE |
435 | } |
436 | ||
437 | /* Compute the table of register modes. | |
438 | These values are used to record death information for individual registers | |
439 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 440 | |
c27c5281 DE |
441 | static void |
442 | init_reg_modes () | |
443 | { | |
444 | register int i; | |
ca4aac00 DE |
445 | |
446 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
447 | { |
448 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
449 | ||
066c2fea | 450 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
451 | ??? One situation in which we need to do this is on the mips where |
452 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
453 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 454 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 455 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 456 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 457 | } |
ca4aac00 DE |
458 | } |
459 | ||
c27c5281 DE |
460 | /* Finish initializing the register sets and |
461 | initialize the register modes. */ | |
462 | ||
463 | void | |
464 | init_regs () | |
465 | { | |
466 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
467 | until after register usage was specified. */ | |
b93a436e | 468 | init_reg_sets_1 (); |
c27c5281 DE |
469 | |
470 | init_reg_modes (); | |
473fe49b KR |
471 | |
472 | #ifdef HAVE_SECONDARY_RELOADS | |
473 | { | |
474 | /* Make some fake stack-frame MEM references for use in | |
475 | memory_move_secondary_cost. */ | |
476 | int i; | |
477 | for (i = 0; i < MAX_MACHINE_MODE; i++) | |
9ec36da5 | 478 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
00d33cb2 | 479 | ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE); |
473fe49b KR |
480 | } |
481 | #endif | |
c27c5281 DE |
482 | } |
483 | ||
cbd5b9a2 | 484 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 485 | |
cbd5b9a2 KR |
486 | /* Compute extra cost of moving registers to/from memory due to reloads. |
487 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 488 | |
cbd5b9a2 KR |
489 | int |
490 | memory_move_secondary_cost (mode, class, in) | |
491 | enum machine_mode mode; | |
492 | enum reg_class class; | |
493 | int in; | |
494 | { | |
495 | enum reg_class altclass; | |
496 | int partial_cost = 0; | |
cbd5b9a2 | 497 | /* We need a memory reference to feed to SECONDARY... macros. */ |
473fe49b | 498 | rtx mem = top_of_stack[(int) mode]; |
cbd5b9a2 KR |
499 | |
500 | if (in) | |
473fe49b | 501 | { |
321c0828 | 502 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 503 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 504 | #else |
473fe49b | 505 | altclass = NO_REGS; |
321c0828 | 506 | #endif |
473fe49b | 507 | } |
cbd5b9a2 | 508 | else |
473fe49b | 509 | { |
321c0828 | 510 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 511 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 512 | #else |
473fe49b | 513 | altclass = NO_REGS; |
321c0828 | 514 | #endif |
473fe49b KR |
515 | } |
516 | ||
cbd5b9a2 KR |
517 | if (altclass == NO_REGS) |
518 | return 0; | |
519 | ||
520 | if (in) | |
521 | partial_cost = REGISTER_MOVE_COST (altclass, class); | |
522 | else | |
523 | partial_cost = REGISTER_MOVE_COST (class, altclass); | |
524 | ||
525 | if (class == altclass) | |
526 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
527 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
528 | here in that case. | |
529 | ||
530 | I'm tempted to put in an abort here, but returning this will | |
531 | probably only give poor estimates, which is what we would've | |
532 | had before this code anyways. */ | |
533 | return partial_cost; | |
534 | ||
535 | /* Check if the secondary reload register will also need a | |
536 | secondary reload. */ | |
537 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
538 | } | |
539 | #endif | |
540 | ||
ca4aac00 DE |
541 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
542 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
543 | ||
544 | enum machine_mode | |
545 | choose_hard_reg_mode (regno, nregs) | |
546 | int regno; | |
547 | int nregs; | |
548 | { | |
549 | enum machine_mode found_mode = VOIDmode, mode; | |
550 | ||
551 | /* We first look for the largest integer mode that can be validly | |
552 | held in REGNO. If none, we look for the largest floating-point mode. | |
553 | If we still didn't find a valid mode, try CCmode. */ | |
554 | ||
555 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
556 | mode != VOIDmode; | |
557 | mode = GET_MODE_WIDER_MODE (mode)) | |
558 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
559 | && HARD_REGNO_MODE_OK (regno, mode)) | |
560 | found_mode = mode; | |
561 | ||
562 | if (found_mode != VOIDmode) | |
563 | return found_mode; | |
564 | ||
565 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
566 | mode != VOIDmode; | |
567 | mode = GET_MODE_WIDER_MODE (mode)) | |
568 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
569 | && HARD_REGNO_MODE_OK (regno, mode)) | |
570 | found_mode = mode; | |
571 | ||
572 | if (found_mode != VOIDmode) | |
573 | return found_mode; | |
574 | ||
575 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
576 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
577 | return CCmode; | |
578 | ||
579 | /* We can't find a mode valid for this register. */ | |
580 | return VOIDmode; | |
54dac99e RK |
581 | } |
582 | ||
583 | /* Specify the usage characteristics of the register named NAME. | |
584 | It should be a fixed register if FIXED and a | |
585 | call-used register if CALL_USED. */ | |
586 | ||
587 | void | |
588 | fix_register (name, fixed, call_used) | |
ec0ce6e2 | 589 | const char *name; |
54dac99e RK |
590 | int fixed, call_used; |
591 | { | |
592 | int i; | |
593 | ||
594 | /* Decode the name and update the primary form of | |
595 | the register info. */ | |
596 | ||
e5c90c23 TW |
597 | if ((i = decode_reg_name (name)) >= 0) |
598 | { | |
cb2fdc84 GRK |
599 | if ((i == STACK_POINTER_REGNUM |
600 | #ifdef HARD_FRAME_POINTER_REGNUM | |
601 | || i == HARD_FRAME_POINTER_REGNUM | |
602 | #else | |
603 | || i == FRAME_POINTER_REGNUM | |
604 | #endif | |
605 | ) | |
606 | && (fixed == 0 || call_used == 0)) | |
607 | { | |
6f7d635c | 608 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
609 | { "call-saved", "call-used" }, |
610 | { "no-such-option", "fixed" }}; | |
cb2fdc84 GRK |
611 | |
612 | error ("can't use '%s' as a %s register", name, | |
613 | what_option[fixed][call_used]); | |
614 | } | |
615 | else | |
616 | { | |
617 | fixed_regs[i] = fixed; | |
618 | call_used_regs[i] = call_used; | |
619 | } | |
e5c90c23 TW |
620 | } |
621 | else | |
54dac99e RK |
622 | { |
623 | warning ("unknown register name: %s", name); | |
54dac99e RK |
624 | } |
625 | } | |
614f68e2 RK |
626 | |
627 | /* Mark register number I as global. */ | |
628 | ||
629 | void | |
630 | globalize_reg (i) | |
631 | int i; | |
632 | { | |
c07c7c9d | 633 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
634 | error ("global register variable follows a function definition"); |
635 | ||
614f68e2 RK |
636 | if (global_regs[i]) |
637 | { | |
638 | warning ("register used for two global register variables"); | |
639 | return; | |
640 | } | |
641 | ||
642 | if (call_used_regs[i] && ! fixed_regs[i]) | |
643 | warning ("call-clobbered register used for global register variable"); | |
644 | ||
645 | global_regs[i] = 1; | |
646 | ||
647 | /* If already fixed, nothing else to do. */ | |
648 | if (fixed_regs[i]) | |
649 | return; | |
650 | ||
651 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
652 | n_non_fixed_regs--; | |
653 | ||
654 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
655 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
656 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
657 | } | |
54dac99e RK |
658 | \f |
659 | /* Now the data and code for the `regclass' pass, which happens | |
660 | just before local-alloc. */ | |
661 | ||
e4600702 RK |
662 | /* The `costs' struct records the cost of using a hard register of each class |
663 | and of using memory for each pseudo. We use this data to set up | |
664 | register class preferences. */ | |
54dac99e | 665 | |
e4600702 | 666 | struct costs |
54dac99e | 667 | { |
e4600702 RK |
668 | int cost[N_REG_CLASSES]; |
669 | int mem_cost; | |
54dac99e RK |
670 | }; |
671 | ||
9ffc5a70 JH |
672 | /* Structure used to record preferrences of given pseudo. */ |
673 | struct reg_pref | |
674 | { | |
675 | /* (enum reg_class) prefclass is the preferred class. */ | |
676 | char prefclass; | |
677 | ||
678 | /* altclass is a register class that we should use for allocating | |
679 | pseudo if no register in the preferred class is available. | |
680 | If no register in this class is available, memory is preferred. | |
681 | ||
682 | It might appear to be more general to have a bitmask of classes here, | |
683 | but since it is recommended that there be a class corresponding to the | |
684 | union of most major pair of classes, that generality is not required. */ | |
685 | char altclass; | |
686 | }; | |
687 | ||
e4600702 RK |
688 | /* Record the cost of each class for each pseudo. */ |
689 | ||
690 | static struct costs *costs; | |
691 | ||
61719ba7 BS |
692 | /* Initialized once, and used to initialize cost values for each insn. */ |
693 | ||
694 | static struct costs init_cost; | |
695 | ||
e4600702 RK |
696 | /* Record the same data by operand number, accumulated for each alternative |
697 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
698 | alternative. */ | |
699 | ||
700 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e | 701 | |
9ffc5a70 | 702 | /* Record preferrences of each pseudo. |
54dac99e RK |
703 | This is available after `regclass' is run. */ |
704 | ||
9ffc5a70 | 705 | static struct reg_pref *reg_pref; |
54d23420 | 706 | |
9ffc5a70 | 707 | /* Allocated buffers for reg_pref. */ |
54dac99e | 708 | |
9ffc5a70 | 709 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 710 | |
54d23420 | 711 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
712 | |
713 | static int loop_depth; | |
714 | ||
54d23420 RK |
715 | /* Account for the fact that insns within a loop are executed very commonly, |
716 | but don't keep doing this as loops go too deep. */ | |
717 | ||
718 | static int loop_cost; | |
719 | ||
61719ba7 | 720 | static rtx scan_one_insn PROTO((rtx, int)); |
246fd41f | 721 | static void dump_regclass PROTO((FILE *)); |
08d95f91 | 722 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
7e7b6c19 | 723 | char *, const char **, rtx)); |
08d95f91 RK |
724 | static int copy_cost PROTO((rtx, enum machine_mode, |
725 | enum reg_class, int)); | |
726 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
727 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
728 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
729 | #endif | |
f903b91f | 730 | static void reg_scan_mark_refs PROTO((rtx, rtx, int, int)); |
54dac99e RK |
731 | |
732 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
733 | This function is sometimes called before the info has been computed. | |
734 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
735 | ||
736 | enum reg_class | |
737 | reg_preferred_class (regno) | |
738 | int regno; | |
739 | { | |
9ffc5a70 | 740 | if (reg_pref == 0) |
54dac99e | 741 | return GENERAL_REGS; |
9ffc5a70 | 742 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
743 | } |
744 | ||
e4600702 RK |
745 | enum reg_class |
746 | reg_alternate_class (regno) | |
b729186a | 747 | int regno; |
54dac99e | 748 | { |
9ffc5a70 | 749 | if (reg_pref == 0) |
e4600702 RK |
750 | return ALL_REGS; |
751 | ||
9ffc5a70 | 752 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
753 | } |
754 | ||
61719ba7 | 755 | /* Initialize some global data for this pass. */ |
54dac99e RK |
756 | |
757 | void | |
758 | regclass_init () | |
759 | { | |
61719ba7 BS |
760 | int i; |
761 | ||
762 | init_cost.mem_cost = 10000; | |
763 | for (i = 0; i < N_REG_CLASSES; i++) | |
764 | init_cost.cost[i] = 10000; | |
765 | ||
766 | /* This prevents dump_flow_info from losing if called | |
767 | before regclass is run. */ | |
9ffc5a70 | 768 | reg_pref = NULL; |
6c85df69 | 769 | |
c07c7c9d | 770 | /* No more global register variables may be declared. */ |
6c85df69 | 771 | no_global_reg_vars = 1; |
54dac99e | 772 | } |
246fd41f JH |
773 | \f |
774 | /* Dump register costs. */ | |
915b80ed | 775 | static void |
246fd41f JH |
776 | dump_regclass (dump) |
777 | FILE *dump; | |
778 | { | |
779 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
780 | int i; | |
781 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
782 | { | |
783 | enum reg_class class; | |
784 | if (REG_N_REFS (i)) | |
785 | { | |
786 | fprintf (dump, ";; Register %i costs:", i); | |
787 | for (class = 0; class < N_REG_CLASSES; class++) | |
788 | fprintf (dump, " %s:%i", reg_class_names[(int) class], | |
789 | costs[i].cost[class]); | |
790 | fprintf (dump, " MEM:%i\n\n", costs[i].mem_cost); | |
791 | } | |
792 | } | |
793 | } | |
794 | ||
54dac99e | 795 | \f |
61719ba7 BS |
796 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
797 | time it would save code to put a certain register in a certain class. | |
798 | PASS, when nonzero, inhibits some optimizations which need only be done | |
799 | once. | |
800 | Return the last insn processed, so that the scan can be continued from | |
801 | there. */ | |
802 | ||
803 | static rtx | |
804 | scan_one_insn (insn, pass) | |
805 | rtx insn; | |
806 | int pass; | |
807 | { | |
808 | enum rtx_code code = GET_CODE (insn); | |
809 | enum rtx_code pat_code; | |
9b3142b3 | 810 | const char *constraints[MAX_RECOG_OPERANDS]; |
61719ba7 | 811 | enum machine_mode modes[MAX_RECOG_OPERANDS]; |
7e7b6c19 | 812 | char subreg_changes_size[MAX_RECOG_OPERANDS]; |
0eadeb15 | 813 | rtx set, note; |
61719ba7 BS |
814 | int i, j; |
815 | ||
816 | /* Show that an insn inside a loop is likely to be executed three | |
817 | times more than insns outside a loop. This is much more aggressive | |
818 | than the assumptions made elsewhere and is being tried as an | |
819 | experiment. */ | |
820 | ||
821 | if (code == NOTE) | |
822 | { | |
823 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
824 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
825 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
826 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
827 | ||
828 | return insn; | |
829 | } | |
830 | ||
831 | if (GET_RTX_CLASS (code) != 'i') | |
832 | return insn; | |
833 | ||
834 | pat_code = GET_CODE (PATTERN (insn)); | |
835 | if (pat_code == USE | |
836 | || pat_code == CLOBBER | |
837 | || pat_code == ASM_INPUT | |
838 | || pat_code == ADDR_VEC | |
839 | || pat_code == ADDR_DIFF_VEC) | |
840 | return insn; | |
841 | ||
0eadeb15 BS |
842 | set = single_set (insn); |
843 | extract_insn (insn); | |
844 | ||
1ccbefce | 845 | for (i = 0; i < recog_data.n_operands; i++) |
61719ba7 | 846 | { |
1ccbefce RH |
847 | constraints[i] = recog_data.constraints[i]; |
848 | modes[i] = recog_data.operand_mode[i]; | |
61719ba7 | 849 | } |
7e7b6c19 | 850 | memset (subreg_changes_size, 0, sizeof (subreg_changes_size)); |
61719ba7 | 851 | |
0eadeb15 BS |
852 | /* If this insn loads a parameter from its stack slot, then |
853 | it represents a savings, rather than a cost, if the | |
854 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 855 | |
0eadeb15 BS |
856 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
857 | && GET_CODE (SET_SRC (set)) == MEM | |
858 | && (note = find_reg_note (insn, REG_EQUIV, | |
859 | NULL_RTX)) != 0 | |
860 | && GET_CODE (XEXP (note, 0)) == MEM) | |
861 | { | |
862 | costs[REGNO (SET_DEST (set))].mem_cost | |
863 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
864 | GENERAL_REGS, 1) | |
865 | * loop_cost); | |
866 | record_address_regs (XEXP (SET_SRC (set), 0), | |
867 | BASE_REG_CLASS, loop_cost * 2); | |
868 | return insn; | |
869 | } | |
61719ba7 | 870 | |
0eadeb15 BS |
871 | /* Improve handling of two-address insns such as |
872 | (set X (ashift CONST Y)) where CONST must be made to | |
873 | match X. Change it into two insns: (set X CONST) | |
874 | (set X (ashift X Y)). If we left this for reloading, it | |
875 | would probably get three insns because X and Y might go | |
876 | in the same place. This prevents X and Y from receiving | |
877 | the same hard reg. | |
878 | ||
879 | We can only do this if the modes of operands 0 and 1 | |
880 | (which might not be the same) are tieable and we only need | |
881 | do this during our first pass. */ | |
882 | ||
883 | if (pass == 0 && optimize | |
1ccbefce RH |
884 | && recog_data.n_operands >= 3 |
885 | && recog_data.constraints[1][0] == '0' | |
886 | && recog_data.constraints[1][1] == 0 | |
887 | && CONSTANT_P (recog_data.operand[1]) | |
888 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
889 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
890 | && GET_CODE (recog_data.operand[0]) == REG | |
891 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
892 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
893 | { |
894 | rtx previnsn = prev_real_insn (insn); | |
895 | rtx dest | |
1ccbefce RH |
896 | = gen_lowpart (recog_data.operand_mode[1], |
897 | recog_data.operand[0]); | |
0eadeb15 | 898 | rtx newinsn |
1ccbefce | 899 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 900 | |
0eadeb15 BS |
901 | /* If this insn was the start of a basic block, |
902 | include the new insn in that block. | |
903 | We need not check for code_label here; | |
904 | while a basic block can start with a code_label, | |
905 | INSN could not be at the beginning of that block. */ | |
906 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 907 | { |
0eadeb15 BS |
908 | int b; |
909 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 RH |
910 | if (insn == BLOCK_HEAD (b)) |
911 | BLOCK_HEAD (b) = newinsn; | |
61719ba7 BS |
912 | } |
913 | ||
0eadeb15 | 914 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 915 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
61719ba7 | 916 | |
1ccbefce RH |
917 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
918 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
919 | if (recog_data.dup_num[i] == 1) | |
920 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
61719ba7 | 921 | |
0eadeb15 | 922 | return PREV_INSN (newinsn); |
61719ba7 BS |
923 | } |
924 | ||
925 | /* If we get here, we are set up to record the costs of all the | |
926 | operands for this insn. Start by initializing the costs. | |
927 | Then handle any address registers. Finally record the desired | |
928 | classes for any pseudos, doing it twice if some pair of | |
929 | operands are commutative. */ | |
930 | ||
1ccbefce | 931 | for (i = 0; i < recog_data.n_operands; i++) |
61719ba7 BS |
932 | { |
933 | op_costs[i] = init_cost; | |
934 | ||
1ccbefce | 935 | if (GET_CODE (recog_data.operand[i]) == SUBREG) |
7e7b6c19 | 936 | { |
1ccbefce | 937 | rtx inner = SUBREG_REG (recog_data.operand[i]); |
7e7b6c19 RH |
938 | if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner))) |
939 | subreg_changes_size[i] = 1; | |
1ccbefce | 940 | recog_data.operand[i] = inner; |
7e7b6c19 | 941 | } |
61719ba7 | 942 | |
1ccbefce RH |
943 | if (GET_CODE (recog_data.operand[i]) == MEM) |
944 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
61719ba7 BS |
945 | BASE_REG_CLASS, loop_cost * 2); |
946 | else if (constraints[i][0] == 'p') | |
1ccbefce | 947 | record_address_regs (recog_data.operand[i], |
61719ba7 BS |
948 | BASE_REG_CLASS, loop_cost * 2); |
949 | } | |
950 | ||
951 | /* Check for commutative in a separate loop so everything will | |
952 | have been initialized. We must do this even if one operand | |
953 | is a constant--see addsi3 in m68k.md. */ | |
954 | ||
88e6fdcb | 955 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) |
61719ba7 BS |
956 | if (constraints[i][0] == '%') |
957 | { | |
9b3142b3 | 958 | const char *xconstraints[MAX_RECOG_OPERANDS]; |
61719ba7 BS |
959 | int j; |
960 | ||
961 | /* Handle commutative operands by swapping the constraints. | |
962 | We assume the modes are the same. */ | |
963 | ||
1ccbefce | 964 | for (j = 0; j < recog_data.n_operands; j++) |
61719ba7 BS |
965 | xconstraints[j] = constraints[j]; |
966 | ||
967 | xconstraints[i] = constraints[i+1]; | |
968 | xconstraints[i+1] = constraints[i]; | |
1ccbefce RH |
969 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, |
970 | recog_data.operand, modes, subreg_changes_size, | |
7e7b6c19 | 971 | xconstraints, insn); |
61719ba7 BS |
972 | } |
973 | ||
1ccbefce RH |
974 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, |
975 | recog_data.operand, modes, subreg_changes_size, | |
976 | constraints, insn); | |
61719ba7 BS |
977 | |
978 | /* Now add the cost for each operand to the total costs for | |
979 | its register. */ | |
980 | ||
1ccbefce RH |
981 | for (i = 0; i < recog_data.n_operands; i++) |
982 | if (GET_CODE (recog_data.operand[i]) == REG | |
983 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 984 | { |
1ccbefce | 985 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
986 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
987 | ||
988 | p->mem_cost += q->mem_cost * loop_cost; | |
989 | for (j = 0; j < N_REG_CLASSES; j++) | |
990 | p->cost[j] += q->cost[j] * loop_cost; | |
991 | } | |
992 | ||
993 | return insn; | |
994 | } | |
995 | ||
54dac99e RK |
996 | /* This is a pass of the compiler that scans all instructions |
997 | and calculates the preferred class for each pseudo-register. | |
998 | This information can be accessed later by calling `reg_preferred_class'. | |
999 | This pass comes just before local register allocation. */ | |
1000 | ||
1001 | void | |
246fd41f | 1002 | regclass (f, nregs, dump) |
54dac99e RK |
1003 | rtx f; |
1004 | int nregs; | |
246fd41f | 1005 | FILE *dump; |
54dac99e | 1006 | { |
54dac99e | 1007 | register rtx insn; |
61719ba7 | 1008 | register int i; |
e4600702 | 1009 | int pass; |
54dac99e RK |
1010 | |
1011 | init_recog (); | |
1012 | ||
56a65848 | 1013 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 RK |
1014 | |
1015 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1016 | ||
4da896b2 | 1017 | in_inc_dec = (char *) xmalloc (nregs); |
533d0835 RK |
1018 | |
1019 | /* Initialize information about which register classes can be used for | |
1020 | pseudos that are auto-incremented or auto-decremented. It would | |
1021 | seem better to put this in init_reg_sets, but we need to be able | |
1022 | to allocate rtx, which we can't do that early. */ | |
1023 | ||
1024 | for (i = 0; i < N_REG_CLASSES; i++) | |
1025 | { | |
38a448ca | 1026 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 | 1027 | enum machine_mode m; |
8c368ee2 | 1028 | register int j; |
533d0835 RK |
1029 | |
1030 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1031 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1032 | { | |
1033 | REGNO (r) = j; | |
1034 | ||
1035 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1036 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1037 | if (HARD_REGNO_MODE_OK (j, m)) |
1038 | { | |
1039 | PUT_MODE (r, m); | |
08d95f91 RK |
1040 | |
1041 | /* If a register is not directly suitable for an | |
1042 | auto-increment or decrement addressing mode and | |
1043 | requires secondary reloads, disallow its class from | |
1044 | being used in such addresses. */ | |
1045 | ||
1046 | if ((0 | |
041d7180 JL |
1047 | #ifdef SECONDARY_RELOAD_CLASS |
1048 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
1049 | != NO_REGS) | |
1050 | #else | |
533d0835 | 1051 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
1052 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1053 | != NO_REGS) | |
533d0835 RK |
1054 | #endif |
1055 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
1056 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
1057 | != NO_REGS) | |
041d7180 | 1058 | #endif |
533d0835 | 1059 | #endif |
08d95f91 RK |
1060 | ) |
1061 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1062 | forbidden_inc_dec_class[i] = 1; |
1063 | } | |
1064 | } | |
1065 | } | |
1066 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
1067 | ||
e4600702 RK |
1068 | /* Normally we scan the insns once and determine the best class to use for |
1069 | each register. However, if -fexpensive_optimizations are on, we do so | |
1070 | twice, the second time using the tentative best classes to guide the | |
1071 | selection. */ | |
54dac99e | 1072 | |
e4600702 RK |
1073 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1074 | { | |
1075 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 1076 | |
4c9a05bc | 1077 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 1078 | |
533d0835 RK |
1079 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1080 | bzero (in_inc_dec, nregs); | |
1081 | #endif | |
1082 | ||
e4600702 RK |
1083 | loop_depth = 0, loop_cost = 1; |
1084 | ||
1085 | /* Scan the instructions and record each time it would | |
1086 | save code to put a certain register in a certain class. */ | |
1087 | ||
1088 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 1089 | { |
61719ba7 | 1090 | insn = scan_one_insn (insn, pass); |
54dac99e | 1091 | } |
61719ba7 | 1092 | |
e4600702 RK |
1093 | /* Now for each register look at how desirable each class is |
1094 | and find which class is preferred. Store that in | |
9ffc5a70 | 1095 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1096 | class any of whose registers is better than memory. */ |
54dac99e | 1097 | |
e4600702 | 1098 | if (pass == 0) |
9ffc5a70 | 1099 | reg_pref = reg_pref_buffer; |
54dac99e | 1100 | |
e4600702 | 1101 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1102 | { |
ca3c6eae | 1103 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1104 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1105 | /* This is an enum reg_class, but we call it an int | |
1106 | to save lots of casts. */ | |
1107 | register int class; | |
1108 | register struct costs *p = &costs[i]; | |
1109 | ||
1110 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 1111 | { |
533d0835 RK |
1112 | /* Ignore classes that are too small for this operand or |
1113 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 1114 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
1115 | > reg_class_size[class] |
1116 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1117 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1118 | #endif | |
1119 | ) | |
e4600702 RK |
1120 | ; |
1121 | else if (p->cost[class] < best_cost) | |
1122 | { | |
1123 | best_cost = p->cost[class]; | |
1124 | best = (enum reg_class) class; | |
1125 | } | |
1126 | else if (p->cost[class] == best_cost) | |
1127 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 1128 | } |
54dac99e | 1129 | |
e4600702 RK |
1130 | /* Record the alternate register class; i.e., a class for which |
1131 | every register in it is better than using memory. If adding a | |
1132 | class would make a smaller class (i.e., no union of just those | |
1133 | classes exists), skip that class. The major unions of classes | |
1134 | should be provided as a register class. Don't do this if we | |
1135 | will be doing it again later. */ | |
1136 | ||
1137 | if (pass == 1 || ! flag_expensive_optimizations) | |
1138 | for (class = 0; class < N_REG_CLASSES; class++) | |
1139 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1140 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1141 | > reg_class_size[(int) alt]) |
1142 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1143 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1144 | #endif | |
1145 | ) | |
e4600702 RK |
1146 | alt = reg_class_subunion[(int) alt][class]; |
1147 | ||
1148 | /* If we don't add any classes, nothing to try. */ | |
1149 | if (alt == best) | |
995d54dd | 1150 | alt = NO_REGS; |
e4600702 RK |
1151 | |
1152 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
9ffc5a70 JH |
1153 | reg_pref[i].prefclass = (int) best; |
1154 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1155 | } |
54dac99e | 1156 | } |
56a65848 | 1157 | |
246fd41f JH |
1158 | if (dump) |
1159 | dump_regclass (dump); | |
4da896b2 MM |
1160 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1161 | free (in_inc_dec); | |
1162 | #endif | |
56a65848 | 1163 | free (costs); |
54dac99e RK |
1164 | } |
1165 | \f | |
e4600702 RK |
1166 | /* Record the cost of using memory or registers of various classes for |
1167 | the operands in INSN. | |
54dac99e | 1168 | |
e4600702 | 1169 | N_ALTS is the number of alternatives. |
54dac99e | 1170 | |
e4600702 RK |
1171 | N_OPS is the number of operands. |
1172 | ||
1173 | OPS is an array of the operands. | |
1174 | ||
1175 | MODES are the modes of the operands, in case any are VOIDmode. | |
1176 | ||
1177 | CONSTRAINTS are the constraints to use for the operands. This array | |
1178 | is modified by this procedure. | |
1179 | ||
1180 | This procedure works alternative by alternative. For each alternative | |
1181 | we assume that we will be able to allocate all pseudos to their ideal | |
1182 | register class and calculate the cost of using that alternative. Then | |
1183 | we compute for each operand that is a pseudo-register, the cost of | |
1184 | having the pseudo allocated to each register class and using it in that | |
1185 | alternative. To this cost is added the cost of the alternative. | |
1186 | ||
1187 | The cost of each class for this insn is its lowest cost among all the | |
1188 | alternatives. */ | |
1189 | ||
1190 | static void | |
7e7b6c19 RH |
1191 | record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size, |
1192 | constraints, insn) | |
e4600702 RK |
1193 | int n_alts; |
1194 | int n_ops; | |
1195 | rtx *ops; | |
1196 | enum machine_mode *modes; | |
7e7b6c19 | 1197 | char *subreg_changes_size; |
9b3142b3 | 1198 | const char **constraints; |
e4600702 | 1199 | rtx insn; |
54dac99e | 1200 | { |
e4600702 | 1201 | int alt; |
e4600702 | 1202 | int i, j; |
ec2d92af | 1203 | rtx set; |
e4600702 | 1204 | |
e4600702 RK |
1205 | /* Process each alternative, each time minimizing an operand's cost with |
1206 | the cost for each operand in that alternative. */ | |
54dac99e | 1207 | |
e4600702 | 1208 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1209 | { |
e4600702 RK |
1210 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1211 | int alt_fail = 0; | |
1212 | int alt_cost = 0; | |
1213 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1214 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1215 | int class; |
54dac99e | 1216 | |
e4600702 RK |
1217 | for (i = 0; i < n_ops; i++) |
1218 | { | |
9b3142b3 | 1219 | const char *p = constraints[i]; |
e4600702 RK |
1220 | rtx op = ops[i]; |
1221 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1222 | int allows_addr = 0; |
e4600702 | 1223 | int win = 0; |
e51712db | 1224 | unsigned char c; |
54dac99e | 1225 | |
7405d9a1 DE |
1226 | /* Initially show we know nothing about the register class. */ |
1227 | classes[i] = NO_REGS; | |
da2c0219 | 1228 | allows_mem[i] = 0; |
7405d9a1 | 1229 | |
e4600702 RK |
1230 | /* If this operand has no constraints at all, we can conclude |
1231 | nothing about it since anything is valid. */ | |
54dac99e | 1232 | |
e4600702 RK |
1233 | if (*p == 0) |
1234 | { | |
1235 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1236 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1237 | |
e4600702 RK |
1238 | continue; |
1239 | } | |
54dac99e | 1240 | |
7405d9a1 DE |
1241 | /* If this alternative is only relevant when this operand |
1242 | matches a previous operand, we do different things depending | |
1243 | on whether this operand is a pseudo-reg or not. We must process | |
1244 | any modifiers for the operand before we can make this test. */ | |
1245 | ||
8c368ee2 | 1246 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1247 | p++; |
8c368ee2 | 1248 | |
e4600702 RK |
1249 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1250 | { | |
da2c0219 RK |
1251 | /* Copy class and whether memory is allowed from the matching |
1252 | alternative. Then perform any needed cost computations | |
1253 | and/or adjustments. */ | |
e4600702 RK |
1254 | j = p[0] - '0'; |
1255 | classes[i] = classes[j]; | |
da2c0219 | 1256 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1257 | |
1258 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1259 | { | |
1260 | /* If this matches the other operand, we have no added | |
dc903608 | 1261 | cost and we win. */ |
e4600702 | 1262 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1263 | win = 1; |
e4600702 | 1264 | |
77e67eac RK |
1265 | /* If we can put the other operand into a register, add to |
1266 | the cost of this alternative the cost to copy this | |
1267 | operand to the register used for the other operand. */ | |
e4600702 | 1268 | |
dc903608 | 1269 | else if (classes[j] != NO_REGS) |
77e67eac | 1270 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1271 | } |
07d8ca2d RS |
1272 | else if (GET_CODE (ops[j]) != REG |
1273 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1274 | { | |
1275 | /* This op is a pseudo but the one it matches is not. */ | |
1276 | ||
1277 | /* If we can't put the other operand into a register, this | |
1278 | alternative can't be used. */ | |
1279 | ||
1280 | if (classes[j] == NO_REGS) | |
1281 | alt_fail = 1; | |
e4600702 | 1282 | |
07d8ca2d RS |
1283 | /* Otherwise, add to the cost of this alternative the cost |
1284 | to copy the other operand to the register used for this | |
1285 | operand. */ | |
1286 | ||
1287 | else | |
1288 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1289 | } | |
e4600702 RK |
1290 | else |
1291 | { | |
da2c0219 RK |
1292 | /* The costs of this operand are not the same as the other |
1293 | operand since move costs are not symmetric. Moreover, | |
1294 | if we cannot tie them, this alternative needs to do a | |
1295 | copy, which is one instruction. */ | |
1296 | ||
1297 | struct costs *pp = &this_op_costs[i]; | |
1298 | ||
1299 | for (class = 0; class < N_REG_CLASSES; class++) | |
1300 | pp->cost[class] | |
1301 | = (recog_data.operand_type[i] == OP_IN | |
ee59f29b JH |
1302 | ? may_move_in_cost[class][(int) classes[i]] |
1303 | : may_move_out_cost[(int) classes[i]][class]); | |
da2c0219 RK |
1304 | |
1305 | /* If the alternative actually allows memory, make things | |
1306 | a bit cheaper since we won't need an extra insn to | |
1307 | load it. */ | |
1308 | ||
1309 | pp->mem_cost | |
1310 | = (MEMORY_MOVE_COST (mode, classes[i], | |
1311 | recog_data.operand_type[i] == OP_IN) | |
1312 | - allows_mem[i]); | |
1313 | ||
1314 | /* If we have assigned a class to this register in our | |
1315 | first pass, add a cost to this alternative corresponding | |
1316 | to what we would add if this register were not in the | |
1317 | appropriate class. */ | |
1318 | ||
9ffc5a70 | 1319 | if (reg_pref) |
da2c0219 | 1320 | alt_cost |
9ffc5a70 | 1321 | += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass] |
da2c0219 | 1322 | [(int) classes[i]]); |
e4600702 | 1323 | |
37747c82 RK |
1324 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1325 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1326 | alt_cost += 2; | |
e4600702 | 1327 | |
347099d6 | 1328 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1329 | for this operand, so skip to the end of the |
1330 | alternative (should be just one character). */ | |
1331 | while (*p && *p++ != ',') | |
1332 | ; | |
1333 | ||
1334 | constraints[i] = p; | |
347099d6 RS |
1335 | continue; |
1336 | } | |
e4600702 RK |
1337 | } |
1338 | ||
1339 | /* Scan all the constraint letters. See if the operand matches | |
1340 | any of the constraints. Collect the valid register classes | |
1341 | and see if this operand accepts memory. */ | |
1342 | ||
e4600702 RK |
1343 | while (*p && (c = *p++) != ',') |
1344 | switch (c) | |
1345 | { | |
e4600702 RK |
1346 | case '*': |
1347 | /* Ignore the next letter for this pass. */ | |
1348 | p++; | |
1349 | break; | |
1350 | ||
812f2051 R |
1351 | case '?': |
1352 | alt_cost += 2; | |
8c368ee2 | 1353 | case '!': case '#': case '&': |
e4600702 | 1354 | case '0': case '1': case '2': case '3': case '4': |
8c368ee2 | 1355 | case '5': case '6': case '7': case '8': case '9': |
94e6f783 DE |
1356 | break; |
1357 | ||
e4600702 | 1358 | case 'p': |
94e6f783 DE |
1359 | allows_addr = 1; |
1360 | win = address_operand (op, GET_MODE (op)); | |
46f40127 JL |
1361 | /* We know this operand is an address, so we want it to be |
1362 | allocated to a register that can be the base of an | |
1363 | address, ie BASE_REG_CLASS. */ | |
1364 | classes[i] | |
1365 | = reg_class_subunion[(int) classes[i]] | |
1366 | [(int) BASE_REG_CLASS]; | |
e4600702 RK |
1367 | break; |
1368 | ||
1369 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1370 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 | 1371 | and non-offsettable addresses here. */ |
da2c0219 | 1372 | allows_mem[i] = 1; |
e4600702 RK |
1373 | if (GET_CODE (op) == MEM) |
1374 | win = 1; | |
1375 | break; | |
1376 | ||
1377 | case '<': | |
1378 | if (GET_CODE (op) == MEM | |
1379 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1380 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1381 | win = 1; | |
1382 | break; | |
1383 | ||
1384 | case '>': | |
1385 | if (GET_CODE (op) == MEM | |
1386 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1387 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1388 | win = 1; | |
1389 | break; | |
1390 | ||
1391 | case 'E': | |
7ac2547f | 1392 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1393 | /* Match any floating double constant, but only if |
1394 | we can examine the bits of it reliably. */ | |
1395 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1396 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1397 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1398 | break; | |
7ac2547f | 1399 | #endif |
e4600702 RK |
1400 | if (GET_CODE (op) == CONST_DOUBLE) |
1401 | win = 1; | |
1402 | break; | |
1403 | ||
1404 | case 'F': | |
1405 | if (GET_CODE (op) == CONST_DOUBLE) | |
1406 | win = 1; | |
1407 | break; | |
1408 | ||
1409 | case 'G': | |
1410 | case 'H': | |
1411 | if (GET_CODE (op) == CONST_DOUBLE | |
1412 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1413 | win = 1; | |
1414 | break; | |
1415 | ||
1416 | case 's': | |
1417 | if (GET_CODE (op) == CONST_INT | |
1418 | || (GET_CODE (op) == CONST_DOUBLE | |
1419 | && GET_MODE (op) == VOIDmode)) | |
1420 | break; | |
1421 | case 'i': | |
1422 | if (CONSTANT_P (op) | |
1423 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1424 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1425 | #endif | |
1426 | ) | |
1427 | win = 1; | |
1428 | break; | |
1429 | ||
1430 | case 'n': | |
1431 | if (GET_CODE (op) == CONST_INT | |
1432 | || (GET_CODE (op) == CONST_DOUBLE | |
1433 | && GET_MODE (op) == VOIDmode)) | |
1434 | win = 1; | |
1435 | break; | |
1436 | ||
1437 | case 'I': | |
1438 | case 'J': | |
1439 | case 'K': | |
1440 | case 'L': | |
1441 | case 'M': | |
1442 | case 'N': | |
1443 | case 'O': | |
1444 | case 'P': | |
1445 | if (GET_CODE (op) == CONST_INT | |
1446 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1447 | win = 1; | |
1448 | break; | |
1449 | ||
1450 | case 'X': | |
1451 | win = 1; | |
1452 | break; | |
54dac99e | 1453 | |
54dac99e | 1454 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1455 | case 'Q': |
1456 | case 'R': | |
1457 | case 'S': | |
1458 | case 'T': | |
1459 | case 'U': | |
1460 | if (EXTRA_CONSTRAINT (op, c)) | |
1461 | win = 1; | |
1462 | break; | |
1463 | #endif | |
1464 | ||
1465 | case 'g': | |
1466 | if (GET_CODE (op) == MEM | |
1467 | || (CONSTANT_P (op) | |
1468 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1469 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1470 | #endif |
e4600702 RK |
1471 | )) |
1472 | win = 1; | |
da2c0219 | 1473 | allows_mem[i] = 1; |
e4600702 RK |
1474 | case 'r': |
1475 | classes[i] | |
1476 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1477 | break; | |
1478 | ||
1479 | default: | |
1480 | classes[i] | |
1481 | = reg_class_subunion[(int) classes[i]] | |
1482 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1483 | } | |
1484 | ||
1485 | constraints[i] = p; | |
1486 | ||
7e7b6c19 RH |
1487 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
1488 | /* If we noted a subreg earlier, and the selected class is a | |
1489 | subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */ | |
1490 | if (subreg_changes_size[i] | |
1491 | && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE] | |
1492 | [(int) classes[i]] | |
1493 | == CLASS_CANNOT_CHANGE_SIZE)) | |
1494 | classes[i] = NO_REGS; | |
1495 | #endif | |
1496 | ||
e4600702 RK |
1497 | /* How we account for this operand now depends on whether it is a |
1498 | pseudo register or not. If it is, we first check if any | |
1499 | register classes are valid. If not, we ignore this alternative, | |
1500 | since we want to assume that all pseudos get allocated for | |
1501 | register preferencing. If some register class is valid, compute | |
1502 | the costs of moving the pseudo into that class. */ | |
1503 | ||
1504 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1505 | { |
e4600702 | 1506 | if (classes[i] == NO_REGS) |
94e6f783 | 1507 | { |
46f40127 JL |
1508 | /* We must always fail if the operand is a REG, but |
1509 | we did not find a suitable class. | |
1510 | ||
1511 | Otherwise we may perform an uninitialized read | |
1512 | from this_op_costs after the `continue' statement | |
1513 | below. */ | |
94e6f783 DE |
1514 | alt_fail = 1; |
1515 | } | |
e4600702 RK |
1516 | else |
1517 | { | |
1518 | struct costs *pp = &this_op_costs[i]; | |
1519 | ||
1520 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 RK |
1521 | pp->cost[class] |
1522 | = (recog_data.operand_type[i] == OP_IN | |
ee59f29b JH |
1523 | ? may_move_in_cost[class][(int) classes[i]] |
1524 | : may_move_out_cost[(int) classes[i]][class]); | |
e4600702 RK |
1525 | |
1526 | /* If the alternative actually allows memory, make things | |
1527 | a bit cheaper since we won't need an extra insn to | |
1528 | load it. */ | |
1529 | ||
14a774a9 RK |
1530 | pp->mem_cost |
1531 | = (MEMORY_MOVE_COST (mode, classes[i], | |
1532 | recog_data.operand_type[i] == OP_IN) | |
da2c0219 | 1533 | - allows_mem[i]); |
e4600702 RK |
1534 | |
1535 | /* If we have assigned a class to this register in our | |
1536 | first pass, add a cost to this alternative corresponding | |
1537 | to what we would add if this register were not in the | |
1538 | appropriate class. */ | |
1539 | ||
9ffc5a70 | 1540 | if (reg_pref) |
e4600702 | 1541 | alt_cost |
9ffc5a70 | 1542 | += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass] |
14a774a9 | 1543 | [(int) classes[i]]); |
e4600702 | 1544 | } |
4db18574 | 1545 | } |
54dac99e | 1546 | |
e4600702 RK |
1547 | /* Otherwise, if this alternative wins, either because we |
1548 | have already determined that or if we have a hard register of | |
1549 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1550 | |
e4600702 RK |
1551 | else if (win |
1552 | || (GET_CODE (op) == REG | |
6f654776 | 1553 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1554 | ; |
54dac99e | 1555 | |
e4600702 RK |
1556 | /* If registers are valid, the cost of this alternative includes |
1557 | copying the object to and/or from a register. */ | |
54dac99e | 1558 | |
e4600702 RK |
1559 | else if (classes[i] != NO_REGS) |
1560 | { | |
1ccbefce | 1561 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1562 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1563 | |
1ccbefce | 1564 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1565 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1566 | } | |
54dac99e | 1567 | |
e4600702 RK |
1568 | /* The only other way this alternative can be used is if this is a |
1569 | constant that could be placed into memory. */ | |
1570 | ||
da2c0219 | 1571 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1572 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1573 | else |
1574 | alt_fail = 1; | |
1575 | } | |
1576 | ||
1577 | if (alt_fail) | |
1578 | continue; | |
1579 | ||
1580 | /* Finally, update the costs with the information we've calculated | |
1581 | about this alternative. */ | |
1582 | ||
1583 | for (i = 0; i < n_ops; i++) | |
1584 | if (GET_CODE (ops[i]) == REG | |
1585 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1586 | { |
e4600702 | 1587 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1588 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1589 | |
e4600702 RK |
1590 | pp->mem_cost = MIN (pp->mem_cost, |
1591 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1592 | |
e4600702 RK |
1593 | for (class = 0; class < N_REG_CLASSES; class++) |
1594 | pp->cost[class] = MIN (pp->cost[class], | |
1595 | (qq->cost[class] + alt_cost) * scale); | |
1596 | } | |
1597 | } | |
ec2d92af RK |
1598 | |
1599 | /* If this insn is a single set copying operand 1 to operand 0 | |
1600 | and one is a pseudo with the other a hard reg that is in its | |
1601 | own register class, set the cost of that register class to -1. */ | |
1602 | ||
1603 | if ((set = single_set (insn)) != 0 | |
1604 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1605 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1606 | for (i = 0; i <= 1; i++) | |
1607 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1608 | { | |
1609 | int regno = REGNO (ops[!i]); | |
1610 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1611 | int class; | |
4841ba4b | 1612 | int nr; |
ec2d92af | 1613 | |
9ffc5a70 JH |
1614 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0 |
1615 | && (reg_class_size[(unsigned char) reg_pref[regno].prefclass] | |
1616 | == CLASS_MAX_NREGS (reg_pref[regno].prefclass, mode))) | |
1617 | op_costs[i].cost[(unsigned char) reg_pref[regno].prefclass] = -1; | |
ec2d92af RK |
1618 | else if (regno < FIRST_PSEUDO_REGISTER) |
1619 | for (class = 0; class < N_REG_CLASSES; class++) | |
1620 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1621 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1622 | { |
1623 | if (reg_class_size[class] == 1) | |
1624 | op_costs[i].cost[class] = -1; | |
1625 | else | |
1626 | { | |
1627 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1628 | { | |
1629 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1630 | break; | |
1631 | } | |
1632 | ||
1633 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1634 | op_costs[i].cost[class] = -1; | |
1635 | } | |
1636 | } | |
ec2d92af | 1637 | } |
54dac99e | 1638 | } |
e4600702 RK |
1639 | \f |
1640 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1641 | TO_P is zero) a register of class CLASS in mode MODE. | |
1642 | ||
1643 | X must not be a pseudo. */ | |
1644 | ||
1645 | static int | |
1646 | copy_cost (x, mode, class, to_p) | |
1647 | rtx x; | |
1648 | enum machine_mode mode; | |
1649 | enum reg_class class; | |
1650 | int to_p; | |
1651 | { | |
29a82058 | 1652 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1653 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1654 | #endif |
e4600702 RK |
1655 | |
1656 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1657 | assuming optimal allocation. */ | |
1658 | ||
1659 | if (GET_CODE (x) == SCRATCH) | |
1660 | return 0; | |
1661 | ||
1662 | /* Get the class we will actually use for a reload. */ | |
1663 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1664 | ||
1665 | #ifdef HAVE_SECONDARY_RELOADS | |
1666 | /* If we need a secondary reload (we assume here that we are using | |
1667 | the secondary reload as an intermediate, not a scratch register), the | |
1668 | cost is that to load the input into the intermediate register, then | |
1669 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1670 | ||
1671 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1672 | if (to_p == 1) | |
1673 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1674 | #endif | |
1675 | ||
dd9f0e8f | 1676 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1677 | if (! to_p) |
1678 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1679 | #endif | |
1680 | ||
1681 | if (secondary_class != NO_REGS) | |
1682 | return (move_cost[(int) secondary_class][(int) class] | |
1683 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1684 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1685 | |
1686 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1687 | cost to move between the register classes, and use 2 for everything | |
1688 | else (constants). */ | |
1689 | ||
1690 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1691 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1692 | |
e4600702 RK |
1693 | else if (GET_CODE (x) == REG) |
1694 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1695 | ||
1696 | else | |
1697 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1698 | return 2; | |
1699 | } | |
1700 | \f | |
54dac99e RK |
1701 | /* Record the pseudo registers we must reload into hard registers |
1702 | in a subexpression of a memory address, X. | |
e4600702 RK |
1703 | |
1704 | CLASS is the class that the register needs to be in and is either | |
1705 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1706 | ||
1707 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1708 | can represent half-cost adjustments). */ | |
54dac99e | 1709 | |
197d6480 | 1710 | static void |
e4600702 | 1711 | record_address_regs (x, class, scale) |
54dac99e | 1712 | rtx x; |
e4600702 RK |
1713 | enum reg_class class; |
1714 | int scale; | |
54dac99e RK |
1715 | { |
1716 | register enum rtx_code code = GET_CODE (x); | |
1717 | ||
1718 | switch (code) | |
1719 | { | |
1720 | case CONST_INT: | |
1721 | case CONST: | |
1722 | case CC0: | |
1723 | case PC: | |
1724 | case SYMBOL_REF: | |
1725 | case LABEL_REF: | |
1726 | return; | |
1727 | ||
1728 | case PLUS: | |
1729 | /* When we have an address that is a sum, | |
1730 | we must determine whether registers are "base" or "index" regs. | |
1731 | If there is a sum of two registers, we must choose one to be | |
1732 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1733 | to make a good choice most of the time. We only need to do this |
1734 | on machines that can have two registers in an address and where | |
1735 | the base and index register classes are different. | |
1736 | ||
1737 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1738 | that seems bogus since it should only be set when we are sure | |
1739 | the register is being used as a pointer. */ | |
1740 | ||
54dac99e RK |
1741 | { |
1742 | rtx arg0 = XEXP (x, 0); | |
1743 | rtx arg1 = XEXP (x, 1); | |
1744 | register enum rtx_code code0 = GET_CODE (arg0); | |
1745 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1746 | |
1747 | /* Look inside subregs. */ | |
e4600702 | 1748 | if (code0 == SUBREG) |
54dac99e | 1749 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1750 | if (code1 == SUBREG) |
54dac99e RK |
1751 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1752 | ||
e4600702 RK |
1753 | /* If this machine only allows one register per address, it must |
1754 | be in the first operand. */ | |
1755 | ||
1756 | if (MAX_REGS_PER_ADDRESS == 1) | |
1757 | record_address_regs (arg0, class, scale); | |
1758 | ||
1759 | /* If index and base registers are the same on this machine, just | |
1760 | record registers in any non-constant operands. We assume here, | |
1761 | as well as in the tests below, that all addresses are in | |
1762 | canonical form. */ | |
1763 | ||
1764 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1765 | { |
e4600702 RK |
1766 | record_address_regs (arg0, class, scale); |
1767 | if (! CONSTANT_P (arg1)) | |
1768 | record_address_regs (arg1, class, scale); | |
54dac99e | 1769 | } |
e4600702 RK |
1770 | |
1771 | /* If the second operand is a constant integer, it doesn't change | |
1772 | what class the first operand must be. */ | |
1773 | ||
1774 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1775 | record_address_regs (arg0, class, scale); | |
1776 | ||
1777 | /* If the second operand is a symbolic constant, the first operand | |
1778 | must be an index register. */ | |
1779 | ||
1780 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1781 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1782 | ||
956d6950 JL |
1783 | /* If both operands are registers but one is already a hard register |
1784 | of index or base class, give the other the class that the hard | |
1785 | register is not. */ | |
1786 | ||
3f9e9508 | 1787 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1788 | else if (code0 == REG && code1 == REG |
1789 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1790 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1791 | record_address_regs (arg1, | |
1792 | REG_OK_FOR_BASE_P (arg0) | |
1793 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1794 | scale); | |
1795 | else if (code0 == REG && code1 == REG | |
1796 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1797 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1798 | record_address_regs (arg0, | |
1799 | REG_OK_FOR_BASE_P (arg1) | |
1800 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1801 | scale); | |
3f9e9508 | 1802 | #endif |
956d6950 | 1803 | |
e9a25f70 JL |
1804 | /* If one operand is known to be a pointer, it must be the base |
1805 | with the other operand the index. Likewise if the other operand | |
1806 | is a MULT. */ | |
f22376c7 | 1807 | |
e9a25f70 JL |
1808 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1809 | || code1 == MULT) | |
f22376c7 CI |
1810 | { |
1811 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1812 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1813 | } | |
e9a25f70 JL |
1814 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1815 | || code0 == MULT) | |
f22376c7 CI |
1816 | { |
1817 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1818 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1819 | } | |
1820 | ||
e9a25f70 | 1821 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1822 | or index register. This case should be rare. */ |
1823 | ||
e9a25f70 | 1824 | else |
54dac99e | 1825 | { |
e4600702 RK |
1826 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1827 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1828 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1829 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1830 | } |
54dac99e RK |
1831 | } |
1832 | break; | |
1833 | ||
1834 | case POST_INC: | |
1835 | case PRE_INC: | |
1836 | case POST_DEC: | |
1837 | case PRE_DEC: | |
1838 | /* Double the importance of a pseudo register that is incremented | |
1839 | or decremented, since it would take two extra insns | |
533d0835 RK |
1840 | if it ends up in the wrong place. If the operand is a pseudo, |
1841 | show it is being used in an INC_DEC context. */ | |
1842 | ||
1843 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1844 | if (GET_CODE (XEXP (x, 0)) == REG | |
1845 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1846 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1847 | #endif | |
e4600702 RK |
1848 | |
1849 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1850 | break; |
1851 | ||
1852 | case REG: | |
1853 | { | |
e4600702 RK |
1854 | register struct costs *pp = &costs[REGNO (x)]; |
1855 | register int i; | |
54dac99e | 1856 | |
cbd5b9a2 | 1857 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1858 | |
e4600702 | 1859 | for (i = 0; i < N_REG_CLASSES; i++) |
ee59f29b | 1860 | pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2; |
54dac99e RK |
1861 | } |
1862 | break; | |
1863 | ||
1864 | default: | |
1865 | { | |
6f7d635c | 1866 | register const char *fmt = GET_RTX_FORMAT (code); |
54dac99e RK |
1867 | register int i; |
1868 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1869 | if (fmt[i] == 'e') | |
e4600702 | 1870 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1871 | } |
1872 | } | |
1873 | } | |
08d95f91 RK |
1874 | \f |
1875 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1876 | ||
1877 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1878 | to an object of MODE. */ | |
1879 | ||
1d300e19 | 1880 | static int |
08d95f91 RK |
1881 | auto_inc_dec_reg_p (reg, mode) |
1882 | rtx reg; | |
1883 | enum machine_mode mode; | |
1884 | { | |
940da324 JL |
1885 | if (HAVE_POST_INCREMENT |
1886 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 1887 | return 1; |
08d95f91 | 1888 | |
940da324 JL |
1889 | if (HAVE_POST_DECREMENT |
1890 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 1891 | return 1; |
08d95f91 | 1892 | |
940da324 JL |
1893 | if (HAVE_PRE_INCREMENT |
1894 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 1895 | return 1; |
08d95f91 | 1896 | |
940da324 JL |
1897 | if (HAVE_PRE_DECREMENT |
1898 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 1899 | return 1; |
08d95f91 RK |
1900 | |
1901 | return 0; | |
1902 | } | |
1903 | #endif | |
b1f21e0a | 1904 | \f |
ed396e68 BS |
1905 | static short *renumber = (short *)0; |
1906 | static size_t regno_allocated = 0; | |
1907 | ||
b1f21e0a MM |
1908 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
1909 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1910 | NEW_P is non zero, initialize all of the registers, otherwise only |
1911 | initialize the new registers allocated. The same table is kept from | |
1912 | function to function, only reallocating it when we need more room. If | |
1913 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1914 | |
1915 | void | |
39379e67 | 1916 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 1917 | size_t num_regs; |
b1f21e0a | 1918 | int new_p; |
39379e67 | 1919 | int renumber_p; |
b1f21e0a | 1920 | { |
6feacd09 MM |
1921 | size_t size_info; |
1922 | size_t size_renumber; | |
1923 | size_t min = (new_p) ? 0 : reg_n_max; | |
1924 | struct reg_info_data *reg_data; | |
1925 | struct reg_info_data *reg_next; | |
39379e67 | 1926 | |
b1f21e0a MM |
1927 | if (num_regs > regno_allocated) |
1928 | { | |
6feacd09 MM |
1929 | size_t old_allocated = regno_allocated; |
1930 | ||
b1f21e0a | 1931 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
1932 | size_renumber = regno_allocated * sizeof (short); |
1933 | ||
1934 | if (!reg_n_info) | |
1935 | { | |
6feacd09 | 1936 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 1937 | renumber = (short *) xmalloc (size_renumber); |
9ffc5a70 JH |
1938 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
1939 | * sizeof (struct reg_pref)); | |
39379e67 MM |
1940 | } |
1941 | ||
1942 | else | |
1943 | { | |
6feacd09 MM |
1944 | VARRAY_GROW (reg_n_info, regno_allocated); |
1945 | ||
1946 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
1947 | { | |
1948 | free ((char *)renumber); | |
9ffc5a70 | 1949 | free ((char *)reg_pref); |
6feacd09 | 1950 | renumber = (short *) xmalloc (size_renumber); |
9ffc5a70 JH |
1951 | reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated |
1952 | * sizeof (struct reg_pref)); | |
6feacd09 MM |
1953 | } |
1954 | ||
1955 | else | |
1956 | { | |
1957 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
9ffc5a70 JH |
1958 | reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer, |
1959 | regno_allocated | |
1960 | * sizeof (struct reg_pref)); | |
6feacd09 | 1961 | } |
39379e67 | 1962 | } |
6feacd09 MM |
1963 | |
1964 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
1965 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
1966 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
1967 | reg_data->min_index = old_allocated; | |
1968 | reg_data->max_index = regno_allocated - 1; | |
1969 | reg_data->next = reg_info_head; | |
1970 | reg_info_head = reg_data; | |
b1f21e0a MM |
1971 | } |
1972 | ||
6feacd09 | 1973 | reg_n_max = num_regs; |
b1f21e0a MM |
1974 | if (min < num_regs) |
1975 | { | |
6feacd09 MM |
1976 | /* Loop through each of the segments allocated for the actual |
1977 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
1978 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
39379e67 | 1979 | { |
6feacd09 MM |
1980 | size_t min_index = reg_data->min_index; |
1981 | size_t max_index = reg_data->max_index; | |
1982 | ||
1983 | reg_next = reg_data->next; | |
29f63881 | 1984 | if (min <= max_index) |
6feacd09 | 1985 | { |
eafdfea8 | 1986 | size_t max = max_index; |
29f63881 | 1987 | size_t local_min = min - min_index; |
7f7f8214 KG |
1988 | size_t i; |
1989 | ||
29f63881 RH |
1990 | if (min < min_index) |
1991 | local_min = 0; | |
6feacd09 MM |
1992 | if (!reg_data->used_p) /* page just allocated with calloc */ |
1993 | reg_data->used_p = 1; /* no need to zero */ | |
1994 | else | |
29f63881 RH |
1995 | bzero ((char *) ®_data->data[local_min], |
1996 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
6feacd09 | 1997 | |
29f63881 | 1998 | for (i = min_index+local_min; i <= max; i++) |
6feacd09 MM |
1999 | { |
2000 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2001 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2002 | renumber[i] = -1; | |
9ffc5a70 JH |
2003 | reg_pref_buffer[i].prefclass = (char) NO_REGS; |
2004 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 MM |
2005 | } |
2006 | } | |
39379e67 | 2007 | } |
b1f21e0a MM |
2008 | } |
2009 | ||
6feacd09 MM |
2010 | /* If {pref,alt}class have already been allocated, update the pointers to |
2011 | the newly realloced ones. */ | |
9ffc5a70 JH |
2012 | if (reg_pref) |
2013 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2014 | |
39379e67 MM |
2015 | if (renumber_p) |
2016 | reg_renumber = renumber; | |
2017 | ||
73b76448 RK |
2018 | /* Tell the regset code about the new number of registers */ |
2019 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
2020 | } |
2021 | ||
ed396e68 BS |
2022 | /* Free up the space allocated by allocate_reg_info. */ |
2023 | void | |
2024 | free_reg_info () | |
2025 | { | |
2026 | if (reg_n_info) | |
2027 | { | |
2028 | struct reg_info_data *reg_data; | |
2029 | struct reg_info_data *reg_next; | |
2030 | ||
2031 | VARRAY_FREE (reg_n_info); | |
2032 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2033 | { | |
2034 | reg_next = reg_data->next; | |
2035 | free ((char *)reg_data); | |
2036 | } | |
2037 | ||
9ffc5a70 JH |
2038 | free (reg_pref_buffer); |
2039 | reg_pref_buffer = (struct reg_pref *)0; | |
ed396e68 BS |
2040 | reg_info_head = (struct reg_info_data *)0; |
2041 | renumber = (short *)0; | |
2042 | } | |
2043 | regno_allocated = 0; | |
2044 | reg_n_max = 0; | |
2045 | } | |
54dac99e RK |
2046 | \f |
2047 | /* This is the `regscan' pass of the compiler, run just before cse | |
2048 | and again just before loop. | |
2049 | ||
2050 | It finds the first and last use of each pseudo-register | |
2051 | and records them in the vectors regno_first_uid, regno_last_uid | |
2052 | and counts the number of sets in the vector reg_n_sets. | |
2053 | ||
2054 | REPEAT is nonzero the second time this is called. */ | |
2055 | ||
54dac99e | 2056 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2057 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
2058 | and we want this to remain correct for all the remaining passes. */ |
2059 | ||
2060 | int max_parallel; | |
2061 | ||
54dac99e RK |
2062 | void |
2063 | reg_scan (f, nregs, repeat) | |
2064 | rtx f; | |
2065 | int nregs; | |
2066 | int repeat; | |
2067 | { | |
2068 | register rtx insn; | |
2069 | ||
39379e67 | 2070 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
2071 | max_parallel = 3; |
2072 | ||
2073 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2074 | if (GET_CODE (insn) == INSN | |
2075 | || GET_CODE (insn) == CALL_INSN | |
2076 | || GET_CODE (insn) == JUMP_INSN) | |
2077 | { | |
2078 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2079 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2080 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 2081 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
2082 | |
2083 | if (REG_NOTES (insn)) | |
f903b91f DM |
2084 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2085 | } | |
2086 | } | |
2087 | ||
2088 | /* Update 'regscan' information by looking at the insns | |
2089 | from FIRST to LAST. Some new REGs have been created, | |
2090 | and any REG with number greater than OLD_MAX_REGNO is | |
2091 | such a REG. We only update information for those. */ | |
2092 | ||
2093 | void | |
2094 | reg_scan_update(first, last, old_max_regno) | |
2095 | rtx first; | |
2096 | rtx last; | |
2097 | int old_max_regno; | |
2098 | { | |
2099 | register rtx insn; | |
2100 | ||
2101 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2102 | ||
2103 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
2104 | if (GET_CODE (insn) == INSN | |
2105 | || GET_CODE (insn) == CALL_INSN | |
2106 | || GET_CODE (insn) == JUMP_INSN) | |
2107 | { | |
2108 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
2109 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
2110 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
2111 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
2112 | ||
2113 | if (REG_NOTES (insn)) | |
2114 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2115 | } |
2116 | } | |
2117 | ||
1ebecb64 | 2118 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2119 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2120 | We should only record information for REGs with numbers | |
2121 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2122 | |
08d95f91 | 2123 | static void |
f903b91f | 2124 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 2125 | rtx x; |
be8dcd74 | 2126 | rtx insn; |
1ebecb64 | 2127 | int note_flag; |
f903b91f | 2128 | int min_regno; |
54dac99e | 2129 | { |
fa23c636 | 2130 | register enum rtx_code code; |
54dac99e | 2131 | register rtx dest; |
be8dcd74 | 2132 | register rtx note; |
54dac99e | 2133 | |
fa23c636 | 2134 | code = GET_CODE (x); |
54dac99e RK |
2135 | switch (code) |
2136 | { | |
54dac99e | 2137 | case CONST: |
185ebd6c | 2138 | case CONST_INT: |
54dac99e RK |
2139 | case CONST_DOUBLE: |
2140 | case CC0: | |
2141 | case PC: | |
2142 | case SYMBOL_REF: | |
2143 | case LABEL_REF: | |
2144 | case ADDR_VEC: | |
2145 | case ADDR_DIFF_VEC: | |
2146 | return; | |
2147 | ||
2148 | case REG: | |
2149 | { | |
2150 | register int regno = REGNO (x); | |
2151 | ||
f903b91f DM |
2152 | if (regno >= min_regno) |
2153 | { | |
2154 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2155 | if (!note_flag) | |
2156 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2157 | if (REGNO_FIRST_UID (regno) == 0) | |
2158 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
2159 | } | |
54dac99e RK |
2160 | } |
2161 | break; | |
2162 | ||
01565a55 | 2163 | case EXPR_LIST: |
7b18c3db | 2164 | if (XEXP (x, 0)) |
f903b91f | 2165 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2166 | if (XEXP (x, 1)) |
f903b91f | 2167 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2168 | break; |
2169 | ||
2170 | case INSN_LIST: | |
2171 | if (XEXP (x, 1)) | |
f903b91f | 2172 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2173 | break; |
2174 | ||
54dac99e RK |
2175 | case SET: |
2176 | /* Count a set of the destination if it is a register. */ | |
2177 | for (dest = SET_DEST (x); | |
2178 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2179 | || GET_CODE (dest) == ZERO_EXTEND; | |
2180 | dest = XEXP (dest, 0)) | |
2181 | ; | |
2182 | ||
f903b91f DM |
2183 | if (GET_CODE (dest) == REG |
2184 | && REGNO (dest) >= min_regno) | |
b1f21e0a | 2185 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 2186 | |
be8dcd74 RK |
2187 | /* If this is setting a pseudo from another pseudo or the sum of a |
2188 | pseudo and a constant integer and the other pseudo is known to be | |
2189 | a pointer, set the destination to be a pointer as well. | |
2190 | ||
2191 | Likewise if it is setting the destination from an address or from a | |
2192 | value equivalent to an address or to the sum of an address and | |
2193 | something else. | |
2194 | ||
2195 | But don't do any of this if the pseudo corresponds to a user | |
2196 | variable since it should have already been set as a pointer based | |
2197 | on the type. */ | |
2198 | ||
2199 | if (GET_CODE (SET_DEST (x)) == REG | |
2200 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2201 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2202 | /* If the destination pseudo is set more than once, then other |
2203 | sets might not be to a pointer value (consider access to a | |
2204 | union in two threads of control in the presense of global | |
2205 | optimizations). So only set REGNO_POINTER_FLAG on the destination | |
2206 | pseudo if this is the only set of that pseudo. */ | |
2207 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 RK |
2208 | && ! REG_USERVAR_P (SET_DEST (x)) |
2209 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
2210 | && ((GET_CODE (SET_SRC (x)) == REG | |
2211 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
2212 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2213 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2214 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2215 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
2216 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
2217 | || GET_CODE (SET_SRC (x)) == CONST | |
2218 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2219 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2220 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2221 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2222 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2223 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2224 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2225 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2226 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2227 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2228 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2229 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2230 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2231 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2232 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
2233 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
2234 | ||
0f41302f | 2235 | /* ... fall through ... */ |
54dac99e RK |
2236 | |
2237 | default: | |
2238 | { | |
6f7d635c | 2239 | register const char *fmt = GET_RTX_FORMAT (code); |
54dac99e RK |
2240 | register int i; |
2241 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2242 | { | |
2243 | if (fmt[i] == 'e') | |
f903b91f | 2244 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2245 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2246 | { | |
2247 | register int j; | |
2248 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f903b91f | 2249 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2250 | } |
2251 | } | |
2252 | } | |
2253 | } | |
2254 | } | |
2255 | \f | |
2256 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2257 | is also in C2. */ | |
2258 | ||
2259 | int | |
2260 | reg_class_subset_p (c1, c2) | |
2261 | register enum reg_class c1; | |
2262 | register enum reg_class c2; | |
2263 | { | |
2264 | if (c1 == c2) return 1; | |
2265 | ||
2266 | if (c2 == ALL_REGS) | |
2267 | win: | |
2268 | return 1; | |
2269 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
2270 | reg_class_contents[(int)c2], | |
2271 | win); | |
2272 | return 0; | |
2273 | } | |
2274 | ||
2275 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2276 | ||
2277 | int | |
2278 | reg_classes_intersect_p (c1, c2) | |
2279 | register enum reg_class c1; | |
2280 | register enum reg_class c2; | |
2281 | { | |
2282 | #ifdef HARD_REG_SET | |
2283 | register | |
2284 | #endif | |
2285 | HARD_REG_SET c; | |
2286 | ||
2287 | if (c1 == c2) return 1; | |
2288 | ||
2289 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2290 | return 1; | |
2291 | ||
2292 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2293 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2294 | ||
2295 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2296 | return 1; | |
2297 | ||
2298 | lose: | |
2299 | return 0; | |
2300 | } | |
2301 | ||
73b76448 RK |
2302 | /* Release any memory allocated by register sets. */ |
2303 | ||
2304 | void | |
2305 | regset_release_memory () | |
2306 | { | |
73b76448 RK |
2307 | bitmap_release_memory (); |
2308 | } |