]>
Commit | Line | Data |
---|---|---|
54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
778f72f2 | 3 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
e146f815 | 4 | Free Software Foundation, Inc. |
54dac99e | 5 | |
1322177d | 6 | This file is part of GCC. |
54dac99e | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 2, or (at your option) any later | |
11 | version. | |
54dac99e | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
54dac99e RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
1322177d | 19 | along with GCC; see the file COPYING. If not, write to the Free |
366ccddb KC |
20 | Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
54dac99e RK |
22 | |
23 | ||
24 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
25 | It also defines some tables of information about the hardware registers | |
26 | and a function init_reg_sets to initialize the tables. */ | |
27 | ||
28 | #include "config.h" | |
670ee920 | 29 | #include "system.h" |
4977bab6 ZW |
30 | #include "coretypes.h" |
31 | #include "tm.h" | |
cff9f8d5 | 32 | #include "hard-reg-set.h" |
54dac99e | 33 | #include "rtl.h" |
0829d244 | 34 | #include "expr.h" |
6baf1cc8 | 35 | #include "tm_p.h" |
54dac99e RK |
36 | #include "flags.h" |
37 | #include "basic-block.h" | |
38 | #include "regs.h" | |
c4963a0a | 39 | #include "addresses.h" |
49ad7cfa | 40 | #include "function.h" |
54dac99e RK |
41 | #include "insn-config.h" |
42 | #include "recog.h" | |
e4600702 RK |
43 | #include "reload.h" |
44 | #include "real.h" | |
10f0ad3d | 45 | #include "toplev.h" |
d6f4ec51 | 46 | #include "output.h" |
8b0212ca | 47 | #include "ggc.h" |
0d446150 | 48 | #include "timevar.h" |
41bf2a8b | 49 | #include "hashtab.h" |
8a99f6f9 | 50 | #include "target.h" |
54dac99e | 51 | |
0c20a65f | 52 | static void init_reg_sets_1 (void); |
0c20a65f | 53 | static void init_reg_autoinc (void); |
24deb20a | 54 | |
533d0835 RK |
55 | /* If we have auto-increment or auto-decrement and we can have secondary |
56 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 57 | reloads for pseudos auto-incremented since reload can't handle it. */ |
8a99f6f9 R |
58 | /* We leave it to target hooks to decide if we have secondary reloads, so |
59 | assume that we might have them. */ | |
60 | #if defined(AUTO_INC_DEC) /* */ | |
533d0835 RK |
61 | #define FORBIDDEN_INC_DEC_CLASSES |
62 | #endif | |
54dac99e RK |
63 | \f |
64 | /* Register tables used by many passes. */ | |
65 | ||
66 | /* Indexed by hard register number, contains 1 for registers | |
67 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
68 | These are the registers that cannot be used to allocate | |
252f342a | 69 | a pseudo reg for general use. */ |
54dac99e RK |
70 | |
71 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
72 | ||
73 | /* Same info as a HARD_REG_SET. */ | |
74 | ||
75 | HARD_REG_SET fixed_reg_set; | |
76 | ||
77 | /* Data for initializing the above. */ | |
78 | ||
8b60264b | 79 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
54dac99e RK |
80 | |
81 | /* Indexed by hard register number, contains 1 for registers | |
82 | that are fixed use or are clobbered by function calls. | |
83 | These are the registers that cannot be used to allocate | |
252f342a MH |
84 | a pseudo reg whose life crosses calls unless we are able |
85 | to save/restore them across the calls. */ | |
54dac99e RK |
86 | |
87 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
88 | ||
89 | /* Same info as a HARD_REG_SET. */ | |
90 | ||
91 | HARD_REG_SET call_used_reg_set; | |
92 | ||
6cad67d2 JL |
93 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
94 | HARD_REG_SET losing_caller_save_reg_set; | |
95 | ||
54dac99e RK |
96 | /* Data for initializing the above. */ |
97 | ||
8b60264b | 98 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
fc1296b7 AM |
99 | |
100 | /* This is much like call_used_regs, except it doesn't have to | |
101 | be a superset of FIXED_REGISTERS. This vector indicates | |
a6a2274a | 102 | what is really call clobbered, and is used when defining |
fc1296b7 AM |
103 | regs_invalidated_by_call. */ |
104 | ||
fc1296b7 | 105 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa | 106 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
fc1296b7 | 107 | #endif |
a6a2274a | 108 | |
f6ae6c51 RS |
109 | #ifdef CALL_REALLY_USED_REGISTERS |
110 | #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X] | |
111 | #else | |
112 | #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X] | |
113 | #endif | |
114 | ||
115 | ||
54dac99e | 116 | /* Indexed by hard register number, contains 1 for registers that are |
252f342a MH |
117 | fixed use or call used registers that cannot hold quantities across |
118 | calls even if we are willing to save and restore them. call fixed | |
119 | registers are a subset of call used registers. */ | |
54dac99e RK |
120 | |
121 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
122 | ||
123 | /* The same info as a HARD_REG_SET. */ | |
124 | ||
125 | HARD_REG_SET call_fixed_reg_set; | |
126 | ||
54dac99e RK |
127 | /* Indexed by hard register number, contains 1 for registers |
128 | that are being used for global register decls. | |
129 | These must be exempt from ordinary flow analysis | |
130 | and are also considered fixed. */ | |
131 | ||
132 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
4e2db584 RH |
133 | |
134 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
135 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
136 | for someone's bright idea to have call_used_regs strictly include | |
137 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
138 | that are actually preserved. We know for sure that those associated | |
139 | with the local stack frame are safe, but scant others. */ | |
140 | ||
141 | HARD_REG_SET regs_invalidated_by_call; | |
142 | ||
54dac99e RK |
143 | /* Table of register numbers in the order in which to try to use them. */ |
144 | #ifdef REG_ALLOC_ORDER | |
145 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
146 | |
147 | /* The inverse of reg_alloc_order. */ | |
148 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
149 | #endif |
150 | ||
151 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
152 | ||
2e0e2b76 CH |
153 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
154 | ||
089e575b RS |
155 | /* The same information, but as an array of unsigned ints. We copy from |
156 | these unsigned ints to the table above. We do this so the tm.h files | |
d4845339 RH |
157 | do not have to be aware of the wordsize for machines with <= 64 regs. |
158 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
2e0e2b76 CH |
159 | |
160 | #define N_REG_INTS \ | |
d4845339 | 161 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
2e0e2b76 | 162 | |
a6a2274a | 163 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 164 | = REG_CLASS_CONTENTS; |
54dac99e RK |
165 | |
166 | /* For each reg class, number of regs it contains. */ | |
167 | ||
770ae6cc | 168 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
169 | |
170 | /* For each reg class, table listing all the containing classes. */ | |
171 | ||
1b28cd06 | 172 | static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; |
54dac99e RK |
173 | |
174 | /* For each reg class, table listing all the classes contained in it. */ | |
175 | ||
1b28cd06 | 176 | static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; |
54dac99e RK |
177 | |
178 | /* For each pair of reg classes, | |
179 | a largest reg class contained in their union. */ | |
180 | ||
181 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
182 | ||
183 | /* For each pair of reg classes, | |
184 | the smallest reg class containing their union. */ | |
185 | ||
186 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
187 | ||
94134f42 | 188 | /* Array containing all of the register names. */ |
d05c8ee7 | 189 | |
e087aeb2 | 190 | const char * reg_names[] = REGISTER_NAMES; |
d05c8ee7 | 191 | |
778f72f2 RS |
192 | /* Array containing all of the register class names. */ |
193 | ||
194 | const char * reg_class_names[] = REG_CLASS_NAMES; | |
195 | ||
ca4aac00 DE |
196 | /* For each hard register, the widest mode object that it can contain. |
197 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
198 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
199 | register. */ | |
200 | ||
201 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
202 | ||
26277d41 PB |
203 | /* 1 if there is a register of given mode. */ |
204 | ||
205 | bool have_regs_of_mode [MAX_MACHINE_MODE]; | |
206 | ||
6df26b8f JH |
207 | /* 1 if class does contain register of given mode. */ |
208 | ||
209 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
210 | ||
e4600702 RK |
211 | /* Maximum cost of moving from a register in one class to a register in |
212 | another class. Based on REGISTER_MOVE_COST. */ | |
213 | ||
e56b4594 | 214 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
215 | |
216 | /* Similar, but here we don't have to move if the first index is a subset | |
217 | of the second so in that case the cost is zero. */ | |
218 | ||
e56b4594 | 219 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
220 | |
221 | /* Similar, but here we don't have to move if the first index is a superset | |
222 | of the second so in that case the cost is zero. */ | |
223 | ||
e56b4594 | 224 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 225 | |
533d0835 RK |
226 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
227 | ||
228 | /* These are the classes that regs which are auto-incremented or decremented | |
229 | cannot be put in. */ | |
230 | ||
231 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
232 | ||
40f03658 | 233 | /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec |
533d0835 RK |
234 | context. */ |
235 | ||
236 | static char *in_inc_dec; | |
237 | ||
5fcb671c | 238 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 239 | |
473fe49b KR |
240 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
241 | ||
e2500fed | 242 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
473fe49b | 243 | |
6feacd09 MM |
244 | /* Linked list of reg_info structures allocated for reg_n_info array. |
245 | Grouping all of the allocated structures together in one lump | |
246 | means only one call to bzero to clear them, rather than n smaller | |
247 | calls. */ | |
248 | struct reg_info_data { | |
249 | struct reg_info_data *next; /* next set of reg_info structures */ | |
250 | size_t min_index; /* minimum index # */ | |
251 | size_t max_index; /* maximum index # */ | |
40f03658 | 252 | char used_p; /* nonzero if this has been used previously */ |
6feacd09 MM |
253 | reg_info data[1]; /* beginning of the reg_info data */ |
254 | }; | |
255 | ||
256 | static struct reg_info_data *reg_info_head; | |
257 | ||
c07c7c9d | 258 | /* No more global register variables may be declared; true once |
dc297297 | 259 | regclass has been initialized. */ |
6c85df69 AH |
260 | |
261 | static int no_global_reg_vars = 0; | |
262 | ||
66fd46b6 JH |
263 | /* Specify number of hard registers given machine mode occupy. */ |
264 | unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE]; | |
6feacd09 | 265 | |
54dac99e RK |
266 | /* Function called only once to initialize the above data on reg usage. |
267 | Once this is done, various switches may override. */ | |
268 | ||
269 | void | |
0c20a65f | 270 | init_reg_sets (void) |
54dac99e | 271 | { |
b3694847 | 272 | int i, j; |
54dac99e | 273 | |
2e0e2b76 CH |
274 | /* First copy the register information from the initial int form into |
275 | the regsets. */ | |
276 | ||
277 | for (i = 0; i < N_REG_CLASSES; i++) | |
278 | { | |
279 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
280 | ||
b85946fc | 281 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
2e0e2b76 | 282 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
b85946fc RH |
283 | if (int_reg_class_contents[i][j / 32] |
284 | & ((unsigned) 1 << (j % 32))) | |
2e0e2b76 CH |
285 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
286 | } | |
287 | ||
1ee19633 BI |
288 | /* Sanity check: make sure the target macros FIXED_REGISTERS and |
289 | CALL_USED_REGISTERS had the right number of initializers. */ | |
41374e13 NS |
290 | gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs); |
291 | gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs); | |
1ee19633 | 292 | |
4e135bdd KG |
293 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
294 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 295 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 296 | |
f5d8c9f4 BS |
297 | #ifdef REG_ALLOC_ORDER |
298 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
299 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
300 | #endif | |
910bc42d R |
301 | } |
302 | ||
303 | /* After switches have been processed, which perhaps alter | |
304 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
305 | ||
306 | static void | |
0c20a65f | 307 | init_reg_sets_1 (void) |
910bc42d | 308 | { |
b3694847 SS |
309 | unsigned int i, j; |
310 | unsigned int /* enum machine_mode */ m; | |
910bc42d R |
311 | |
312 | /* This macro allows the fixed or call-used registers | |
313 | and the register classes to depend on target flags. */ | |
314 | ||
315 | #ifdef CONDITIONAL_REGISTER_USAGE | |
316 | CONDITIONAL_REGISTER_USAGE; | |
317 | #endif | |
318 | ||
54dac99e RK |
319 | /* Compute number of hard regs in each class. */ |
320 | ||
703ad42b | 321 | memset (reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
322 | for (i = 0; i < N_REG_CLASSES; i++) |
323 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
324 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
325 | reg_class_size[i]++; | |
326 | ||
327 | /* Initialize the table of subunions. | |
328 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
329 | that is contained in the union of classes I and J. */ | |
330 | ||
331 | for (i = 0; i < N_REG_CLASSES; i++) | |
332 | { | |
333 | for (j = 0; j < N_REG_CLASSES; j++) | |
334 | { | |
49a27995 | 335 | HARD_REG_SET c; |
b3694847 | 336 | int k; |
54dac99e RK |
337 | |
338 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
339 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
340 | for (k = 0; k < N_REG_CLASSES; k++) | |
341 | { | |
342 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
343 | subclass1); | |
344 | continue; | |
345 | ||
346 | subclass1: | |
938d968e | 347 | /* Keep the largest subclass. */ /* SPEE 900308 */ |
54dac99e RK |
348 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], |
349 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
350 | subclass2); | |
351 | reg_class_subunion[i][j] = (enum reg_class) k; | |
352 | subclass2: | |
353 | ; | |
354 | } | |
355 | } | |
356 | } | |
357 | ||
358 | /* Initialize the table of superunions. | |
359 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
360 | containing the union of classes I and J. */ | |
361 | ||
362 | for (i = 0; i < N_REG_CLASSES; i++) | |
363 | { | |
364 | for (j = 0; j < N_REG_CLASSES; j++) | |
365 | { | |
49a27995 | 366 | HARD_REG_SET c; |
b3694847 | 367 | int k; |
54dac99e RK |
368 | |
369 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
370 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
371 | for (k = 0; k < N_REG_CLASSES; k++) | |
372 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
373 | ||
374 | superclass: | |
375 | reg_class_superunion[i][j] = (enum reg_class) k; | |
376 | } | |
377 | } | |
378 | ||
379 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
380 | First clear the whole table, then add the elements as they are found. */ | |
381 | ||
382 | for (i = 0; i < N_REG_CLASSES; i++) | |
383 | { | |
384 | for (j = 0; j < N_REG_CLASSES; j++) | |
385 | { | |
386 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
387 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
388 | } | |
389 | } | |
390 | ||
391 | for (i = 0; i < N_REG_CLASSES; i++) | |
392 | { | |
393 | if (i == (int) NO_REGS) | |
394 | continue; | |
395 | ||
396 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
397 | { | |
398 | enum reg_class *p; | |
399 | ||
400 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
401 | subclass); | |
402 | continue; | |
403 | subclass: | |
404 | /* Reg class I is a subclass of J. | |
405 | Add J to the table of superclasses of I. */ | |
406 | p = ®_class_superclasses[i][0]; | |
407 | while (*p != LIM_REG_CLASSES) p++; | |
408 | *p = (enum reg_class) j; | |
409 | /* Add I to the table of superclasses of J. */ | |
410 | p = ®_class_subclasses[j][0]; | |
411 | while (*p != LIM_REG_CLASSES) p++; | |
412 | *p = (enum reg_class) i; | |
413 | } | |
414 | } | |
e4600702 | 415 | |
54dac99e RK |
416 | /* Initialize "constant" tables. */ |
417 | ||
418 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
419 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
420 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
4e2db584 | 421 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
54dac99e | 422 | |
4e135bdd | 423 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e | 424 | |
54dac99e RK |
425 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
426 | { | |
e3cadb61 | 427 | /* call_used_regs must include fixed_regs. */ |
41374e13 | 428 | gcc_assert (!fixed_regs[i] || call_used_regs[i]); |
e3cadb61 RS |
429 | #ifdef CALL_REALLY_USED_REGISTERS |
430 | /* call_used_regs must include call_really_used_regs. */ | |
41374e13 | 431 | gcc_assert (!call_really_used_regs[i] || call_used_regs[i]); |
e3cadb61 RS |
432 | #endif |
433 | ||
54dac99e RK |
434 | if (fixed_regs[i]) |
435 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
54dac99e RK |
436 | |
437 | if (call_used_regs[i]) | |
438 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
439 | if (call_fixed_regs[i]) | |
440 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
441 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
442 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
4e2db584 RH |
443 | |
444 | /* There are a couple of fixed registers that we know are safe to | |
445 | exclude from being clobbered by calls: | |
446 | ||
447 | The frame pointer is always preserved across calls. The arg pointer | |
448 | is if it is fixed. The stack pointer usually is, unless | |
449 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
450 | If we are generating PIC code, the PIC offset table register is | |
451 | preserved across calls, though the target can override that. */ | |
a6a2274a | 452 | |
f6ae6c51 RS |
453 | if (i == STACK_POINTER_REGNUM) |
454 | ; | |
455 | else if (global_regs[i]) | |
456 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
457 | else if (i == FRAME_POINTER_REGNUM) | |
4e2db584 RH |
458 | ; |
459 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
460 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
461 | ; | |
462 | #endif | |
463 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
464 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
465 | ; | |
466 | #endif | |
467 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
fc555370 | 468 | else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
4e2db584 RH |
469 | ; |
470 | #endif | |
f6ae6c51 | 471 | else if (CALL_REALLY_USED_REGNO_P (i)) |
4e2db584 | 472 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
54dac99e | 473 | } |
4e2db584 | 474 | |
26277d41 | 475 | memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode)); |
6836e024 | 476 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
dbbbbf3b | 477 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 | 478 | for (i = 0; i < N_REG_CLASSES; i++) |
f7043461 | 479 | if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
6df26b8f JH |
480 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
481 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
482 | && HARD_REGNO_MODE_OK (j, m)) | |
483 | { | |
484 | contains_reg_of_mode [i][m] = 1; | |
26277d41 | 485 | have_regs_of_mode [m] = 1; |
6df26b8f JH |
486 | break; |
487 | } | |
acbce667 KR |
488 | |
489 | /* Initialize the move cost table. Find every subset of each class | |
490 | and take the maximum cost of moving any subset to any other. */ | |
491 | ||
dbbbbf3b | 492 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
26277d41 | 493 | if (have_regs_of_mode [m]) |
6836e024 JH |
494 | { |
495 | for (i = 0; i < N_REG_CLASSES; i++) | |
496 | if (contains_reg_of_mode [i][m]) | |
497 | for (j = 0; j < N_REG_CLASSES; j++) | |
498 | { | |
499 | int cost; | |
500 | enum reg_class *p1, *p2; | |
501 | ||
502 | if (!contains_reg_of_mode [j][m]) | |
503 | { | |
504 | move_cost[m][i][j] = 65536; | |
505 | may_move_in_cost[m][i][j] = 65536; | |
506 | may_move_out_cost[m][i][j] = 65536; | |
507 | } | |
508 | else | |
509 | { | |
26a952a8 | 510 | cost = REGISTER_MOVE_COST (m, i, j); |
6836e024 JH |
511 | |
512 | for (p2 = ®_class_subclasses[j][0]; | |
513 | *p2 != LIM_REG_CLASSES; | |
514 | p2++) | |
515 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
516 | cost = MAX (cost, move_cost [m][i][*p2]); | |
517 | ||
518 | for (p1 = ®_class_subclasses[i][0]; | |
519 | *p1 != LIM_REG_CLASSES; | |
520 | p1++) | |
521 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
522 | cost = MAX (cost, move_cost [m][*p1][j]); | |
523 | ||
524 | move_cost[m][i][j] = cost; | |
525 | ||
526 | if (reg_class_subset_p (i, j)) | |
527 | may_move_in_cost[m][i][j] = 0; | |
528 | else | |
529 | may_move_in_cost[m][i][j] = cost; | |
530 | ||
531 | if (reg_class_subset_p (j, i)) | |
532 | may_move_out_cost[m][i][j] = 0; | |
533 | else | |
534 | may_move_out_cost[m][i][j] = cost; | |
535 | } | |
536 | } | |
1464632b | 537 | else |
6836e024 JH |
538 | for (j = 0; j < N_REG_CLASSES; j++) |
539 | { | |
540 | move_cost[m][i][j] = 65536; | |
541 | may_move_in_cost[m][i][j] = 65536; | |
542 | may_move_out_cost[m][i][j] = 65536; | |
543 | } | |
544 | } | |
c27c5281 DE |
545 | } |
546 | ||
547 | /* Compute the table of register modes. | |
548 | These values are used to record death information for individual registers | |
549 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 550 | |
28420116 PB |
551 | void |
552 | init_reg_modes_once (void) | |
c27c5281 | 553 | { |
66fd46b6 JH |
554 | int i, j; |
555 | ||
556 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
557 | for (j = 0; j < MAX_MACHINE_MODE; j++) | |
558 | hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j); | |
ca4aac00 DE |
559 | |
560 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 | 561 | { |
fee226d2 | 562 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); |
7f21d440 | 563 | |
066c2fea | 564 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
565 | ??? One situation in which we need to do this is on the mips where |
566 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
567 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 568 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 569 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 570 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 571 | } |
ca4aac00 DE |
572 | } |
573 | ||
c27c5281 DE |
574 | /* Finish initializing the register sets and |
575 | initialize the register modes. */ | |
576 | ||
577 | void | |
0c20a65f | 578 | init_regs (void) |
c27c5281 DE |
579 | { |
580 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
581 | until after register usage was specified. */ | |
b93a436e | 582 | init_reg_sets_1 (); |
c27c5281 | 583 | |
1f80c9ef | 584 | init_reg_autoinc (); |
6cde4876 JL |
585 | } |
586 | ||
587 | /* Initialize some fake stack-frame MEM references for use in | |
588 | memory_move_secondary_cost. */ | |
473fe49b | 589 | |
6cde4876 | 590 | void |
0c20a65f | 591 | init_fake_stack_mems (void) |
6cde4876 | 592 | { |
473fe49b | 593 | { |
473fe49b | 594 | int i; |
d067e2aa | 595 | |
473fe49b | 596 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 597 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b | 598 | } |
c27c5281 DE |
599 | } |
600 | ||
473fe49b | 601 | |
cbd5b9a2 KR |
602 | /* Compute extra cost of moving registers to/from memory due to reloads. |
603 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 604 | |
cbd5b9a2 | 605 | int |
0c20a65f | 606 | memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in) |
cbd5b9a2 KR |
607 | { |
608 | enum reg_class altclass; | |
609 | int partial_cost = 0; | |
cbd5b9a2 | 610 | /* We need a memory reference to feed to SECONDARY... macros. */ |
dc297297 | 611 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
272df862 KG |
612 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
613 | ||
cbd5b9a2 | 614 | |
8a99f6f9 | 615 | altclass = secondary_reload_class (in ? 1 : 0, class, mode, mem); |
473fe49b | 616 | |
cbd5b9a2 KR |
617 | if (altclass == NO_REGS) |
618 | return 0; | |
619 | ||
620 | if (in) | |
e56b4594 | 621 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 622 | else |
e56b4594 | 623 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
624 | |
625 | if (class == altclass) | |
626 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
627 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
628 | here in that case. | |
629 | ||
41374e13 | 630 | I'm tempted to put in an assert here, but returning this will |
cbd5b9a2 KR |
631 | probably only give poor estimates, which is what we would've |
632 | had before this code anyways. */ | |
633 | return partial_cost; | |
634 | ||
635 | /* Check if the secondary reload register will also need a | |
636 | secondary reload. */ | |
637 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
638 | } | |
cbd5b9a2 | 639 | |
ca4aac00 | 640 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
fee226d2 R |
641 | enough to save nregs. If we can't find one, return VOIDmode. |
642 | If CALL_SAVED is true, only consider modes that are call saved. */ | |
ca4aac00 DE |
643 | |
644 | enum machine_mode | |
0c20a65f | 645 | choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, |
fee226d2 | 646 | unsigned int nregs, bool call_saved) |
ca4aac00 | 647 | { |
dbbbbf3b | 648 | unsigned int /* enum machine_mode */ m; |
ca4aac00 DE |
649 | enum machine_mode found_mode = VOIDmode, mode; |
650 | ||
651 | /* We first look for the largest integer mode that can be validly | |
652 | held in REGNO. If none, we look for the largest floating-point mode. | |
653 | If we still didn't find a valid mode, try CCmode. */ | |
654 | ||
655 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
656 | mode != VOIDmode; | |
657 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 658 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
659 | && HARD_REGNO_MODE_OK (regno, mode) |
660 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
ca4aac00 DE |
661 | found_mode = mode; |
662 | ||
663 | if (found_mode != VOIDmode) | |
664 | return found_mode; | |
665 | ||
666 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
667 | mode != VOIDmode; | |
668 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 669 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
670 | && HARD_REGNO_MODE_OK (regno, mode) |
671 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
ca4aac00 DE |
672 | found_mode = mode; |
673 | ||
674 | if (found_mode != VOIDmode) | |
675 | return found_mode; | |
676 | ||
78b583fe AH |
677 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
678 | mode != VOIDmode; | |
679 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 680 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
681 | && HARD_REGNO_MODE_OK (regno, mode) |
682 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
78b583fe AH |
683 | found_mode = mode; |
684 | ||
685 | if (found_mode != VOIDmode) | |
686 | return found_mode; | |
687 | ||
688 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
689 | mode != VOIDmode; | |
690 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 691 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
692 | && HARD_REGNO_MODE_OK (regno, mode) |
693 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
78b583fe AH |
694 | found_mode = mode; |
695 | ||
696 | if (found_mode != VOIDmode) | |
697 | return found_mode; | |
698 | ||
0548a9df | 699 | /* Iterate over all of the CCmodes. */ |
dbbbbf3b JDA |
700 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
701 | { | |
702 | mode = (enum machine_mode) m; | |
66fd46b6 | 703 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
704 | && HARD_REGNO_MODE_OK (regno, mode) |
705 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
dbbbbf3b JDA |
706 | return mode; |
707 | } | |
ca4aac00 DE |
708 | |
709 | /* We can't find a mode valid for this register. */ | |
710 | return VOIDmode; | |
54dac99e RK |
711 | } |
712 | ||
713 | /* Specify the usage characteristics of the register named NAME. | |
714 | It should be a fixed register if FIXED and a | |
715 | call-used register if CALL_USED. */ | |
716 | ||
717 | void | |
0c20a65f | 718 | fix_register (const char *name, int fixed, int call_used) |
54dac99e RK |
719 | { |
720 | int i; | |
721 | ||
722 | /* Decode the name and update the primary form of | |
723 | the register info. */ | |
724 | ||
e5c90c23 TW |
725 | if ((i = decode_reg_name (name)) >= 0) |
726 | { | |
cb2fdc84 GRK |
727 | if ((i == STACK_POINTER_REGNUM |
728 | #ifdef HARD_FRAME_POINTER_REGNUM | |
729 | || i == HARD_FRAME_POINTER_REGNUM | |
730 | #else | |
731 | || i == FRAME_POINTER_REGNUM | |
732 | #endif | |
733 | ) | |
734 | && (fixed == 0 || call_used == 0)) | |
735 | { | |
6f7d635c | 736 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
737 | { "call-saved", "call-used" }, |
738 | { "no-such-option", "fixed" }}; | |
a6a2274a KH |
739 | |
740 | error ("can't use '%s' as a %s register", name, | |
cb2fdc84 GRK |
741 | what_option[fixed][call_used]); |
742 | } | |
743 | else | |
744 | { | |
745 | fixed_regs[i] = fixed; | |
746 | call_used_regs[i] = call_used; | |
ec523c2f | 747 | #ifdef CALL_REALLY_USED_REGISTERS |
fc1296b7 AM |
748 | if (fixed == 0) |
749 | call_really_used_regs[i] = call_used; | |
d3259baa | 750 | #endif |
cb2fdc84 | 751 | } |
e5c90c23 TW |
752 | } |
753 | else | |
54dac99e | 754 | { |
d4ee4d25 | 755 | warning (0, "unknown register name: %s", name); |
54dac99e RK |
756 | } |
757 | } | |
614f68e2 RK |
758 | |
759 | /* Mark register number I as global. */ | |
760 | ||
761 | void | |
0c20a65f | 762 | globalize_reg (int i) |
614f68e2 | 763 | { |
c07c7c9d | 764 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
765 | error ("global register variable follows a function definition"); |
766 | ||
614f68e2 RK |
767 | if (global_regs[i]) |
768 | { | |
d4ee4d25 | 769 | warning (0, "register used for two global register variables"); |
614f68e2 RK |
770 | return; |
771 | } | |
772 | ||
773 | if (call_used_regs[i] && ! fixed_regs[i]) | |
d4ee4d25 | 774 | warning (0, "call-clobbered register used for global register variable"); |
614f68e2 RK |
775 | |
776 | global_regs[i] = 1; | |
777 | ||
f6ae6c51 RS |
778 | /* If we're globalizing the frame pointer, we need to set the |
779 | appropriate regs_invalidated_by_call bit, even if it's already | |
780 | set in fixed_regs. */ | |
781 | if (i != STACK_POINTER_REGNUM) | |
782 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
783 | ||
614f68e2 RK |
784 | /* If already fixed, nothing else to do. */ |
785 | if (fixed_regs[i]) | |
786 | return; | |
787 | ||
788 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
74ae207d R |
789 | #ifdef CALL_REALLY_USED_REGISTERS |
790 | call_really_used_regs[i] = 1; | |
791 | #endif | |
614f68e2 RK |
792 | |
793 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
794 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
795 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
796 | } | |
54dac99e RK |
797 | \f |
798 | /* Now the data and code for the `regclass' pass, which happens | |
799 | just before local-alloc. */ | |
800 | ||
e4600702 RK |
801 | /* The `costs' struct records the cost of using a hard register of each class |
802 | and of using memory for each pseudo. We use this data to set up | |
803 | register class preferences. */ | |
54dac99e | 804 | |
e4600702 | 805 | struct costs |
54dac99e | 806 | { |
e4600702 RK |
807 | int cost[N_REG_CLASSES]; |
808 | int mem_cost; | |
54dac99e RK |
809 | }; |
810 | ||
d55d8fc7 | 811 | /* Structure used to record preferences of given pseudo. */ |
9ffc5a70 JH |
812 | struct reg_pref |
813 | { | |
b5c82fa1 PB |
814 | /* (enum reg_class) prefclass is the preferred class. May be |
815 | NO_REGS if no class is better than memory. */ | |
9ffc5a70 JH |
816 | char prefclass; |
817 | ||
818 | /* altclass is a register class that we should use for allocating | |
819 | pseudo if no register in the preferred class is available. | |
820 | If no register in this class is available, memory is preferred. | |
821 | ||
822 | It might appear to be more general to have a bitmask of classes here, | |
823 | but since it is recommended that there be a class corresponding to the | |
824 | union of most major pair of classes, that generality is not required. */ | |
825 | char altclass; | |
826 | }; | |
827 | ||
e4600702 RK |
828 | /* Record the cost of each class for each pseudo. */ |
829 | ||
830 | static struct costs *costs; | |
831 | ||
61719ba7 BS |
832 | /* Initialized once, and used to initialize cost values for each insn. */ |
833 | ||
834 | static struct costs init_cost; | |
835 | ||
d55d8fc7 | 836 | /* Record preferences of each pseudo. |
54dac99e RK |
837 | This is available after `regclass' is run. */ |
838 | ||
9ffc5a70 | 839 | static struct reg_pref *reg_pref; |
54d23420 | 840 | |
dc297297 | 841 | /* Allocated buffers for reg_pref. */ |
54dac99e | 842 | |
9ffc5a70 | 843 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 844 | |
9401afe3 | 845 | /* Frequency of executions of current insn. */ |
54d23420 | 846 | |
9401afe3 | 847 | static int frequency; |
54d23420 | 848 | |
0c20a65f AJ |
849 | static rtx scan_one_insn (rtx, int); |
850 | static void record_operand_costs (rtx, struct costs *, struct reg_pref *); | |
851 | static void dump_regclass (FILE *); | |
852 | static void record_reg_classes (int, int, rtx *, enum machine_mode *, | |
853 | const char **, rtx, struct costs *, | |
854 | struct reg_pref *); | |
8a99f6f9 R |
855 | static int copy_cost (rtx, enum machine_mode, enum reg_class, int, |
856 | secondary_reload_info *); | |
c4963a0a BS |
857 | static void record_address_regs (enum machine_mode, rtx, int, enum rtx_code, |
858 | enum rtx_code, int); | |
1d300e19 | 859 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
0c20a65f | 860 | static int auto_inc_dec_reg_p (rtx, enum machine_mode); |
1d300e19 | 861 | #endif |
3c491cab | 862 | static void reg_scan_mark_refs (rtx, rtx, int); |
54dac99e | 863 | |
c4963a0a BS |
864 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ |
865 | ||
866 | static inline bool | |
867 | ok_for_index_p_nonstrict (rtx reg) | |
868 | { | |
869 | unsigned regno = REGNO (reg); | |
870 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
871 | } | |
872 | ||
873 | /* A version of regno_ok_for_base_p for use during regclass, when all pseudos | |
874 | should count as OK. Arguments as for regno_ok_for_base_p. */ | |
875 | ||
876 | static inline bool | |
877 | ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, | |
878 | enum rtx_code outer_code, enum rtx_code index_code) | |
879 | { | |
880 | unsigned regno = REGNO (reg); | |
881 | if (regno >= FIRST_PSEUDO_REGISTER) | |
882 | return true; | |
883 | ||
884 | return ok_for_base_p_1 (regno, mode, outer_code, index_code); | |
885 | } | |
886 | ||
54dac99e RK |
887 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. |
888 | This function is sometimes called before the info has been computed. | |
889 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
890 | ||
891 | enum reg_class | |
0c20a65f | 892 | reg_preferred_class (int regno) |
54dac99e | 893 | { |
9ffc5a70 | 894 | if (reg_pref == 0) |
54dac99e | 895 | return GENERAL_REGS; |
9ffc5a70 | 896 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
897 | } |
898 | ||
e4600702 | 899 | enum reg_class |
0c20a65f | 900 | reg_alternate_class (int regno) |
54dac99e | 901 | { |
9ffc5a70 | 902 | if (reg_pref == 0) |
e4600702 RK |
903 | return ALL_REGS; |
904 | ||
9ffc5a70 | 905 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
906 | } |
907 | ||
61719ba7 | 908 | /* Initialize some global data for this pass. */ |
54dac99e RK |
909 | |
910 | void | |
0c20a65f | 911 | regclass_init (void) |
54dac99e | 912 | { |
61719ba7 BS |
913 | int i; |
914 | ||
915 | init_cost.mem_cost = 10000; | |
916 | for (i = 0; i < N_REG_CLASSES; i++) | |
917 | init_cost.cost[i] = 10000; | |
918 | ||
919 | /* This prevents dump_flow_info from losing if called | |
920 | before regclass is run. */ | |
9ffc5a70 | 921 | reg_pref = NULL; |
6c85df69 | 922 | |
dc297297 | 923 | /* No more global register variables may be declared. */ |
6c85df69 | 924 | no_global_reg_vars = 1; |
54dac99e | 925 | } |
246fd41f JH |
926 | \f |
927 | /* Dump register costs. */ | |
915b80ed | 928 | static void |
0c20a65f | 929 | dump_regclass (FILE *dump) |
246fd41f | 930 | { |
246fd41f JH |
931 | int i; |
932 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
933 | { | |
dbbbbf3b | 934 | int /* enum reg_class */ class; |
246fd41f JH |
935 | if (REG_N_REFS (i)) |
936 | { | |
f741a71c | 937 | fprintf (dump, " Register %i costs:", i); |
dbbbbf3b JDA |
938 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
939 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
6df26b8f | 940 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
dbbbbf3b JDA |
941 | && (!in_inc_dec[i] |
942 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
6df26b8f | 943 | #endif |
cff9f8d5 AH |
944 | #ifdef CANNOT_CHANGE_MODE_CLASS |
945 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
946 | PSEUDO_REGNO_MODE (i)) | |
6df26b8f JH |
947 | #endif |
948 | ) | |
dbbbbf3b JDA |
949 | fprintf (dump, " %s:%i", reg_class_names[class], |
950 | costs[i].cost[(enum reg_class) class]); | |
f741a71c | 951 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
952 | } |
953 | } | |
954 | } | |
f741a71c JH |
955 | \f |
956 | ||
957 | /* Calculate the costs of insn operands. */ | |
958 | ||
959 | static void | |
0c20a65f AJ |
960 | record_operand_costs (rtx insn, struct costs *op_costs, |
961 | struct reg_pref *reg_pref) | |
f741a71c JH |
962 | { |
963 | const char *constraints[MAX_RECOG_OPERANDS]; | |
964 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
965 | int i; |
966 | ||
967 | for (i = 0; i < recog_data.n_operands; i++) | |
968 | { | |
969 | constraints[i] = recog_data.constraints[i]; | |
970 | modes[i] = recog_data.operand_mode[i]; | |
971 | } | |
f741a71c JH |
972 | |
973 | /* If we get here, we are set up to record the costs of all the | |
974 | operands for this insn. Start by initializing the costs. | |
975 | Then handle any address registers. Finally record the desired | |
976 | classes for any pseudos, doing it twice if some pair of | |
977 | operands are commutative. */ | |
a6a2274a | 978 | |
f741a71c JH |
979 | for (i = 0; i < recog_data.n_operands; i++) |
980 | { | |
981 | op_costs[i] = init_cost; | |
982 | ||
983 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
cff9f8d5 | 984 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
f741a71c | 985 | |
3c0cb5de | 986 | if (MEM_P (recog_data.operand[i])) |
c4963a0a BS |
987 | record_address_regs (GET_MODE (recog_data.operand[i]), |
988 | XEXP (recog_data.operand[i], 0), | |
989 | 0, MEM, SCRATCH, frequency * 2); | |
ccfc6cc8 | 990 | else if (constraints[i][0] == 'p' |
97488870 | 991 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
c4963a0a BS |
992 | record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS, |
993 | SCRATCH, frequency * 2); | |
f741a71c JH |
994 | } |
995 | ||
996 | /* Check for commutative in a separate loop so everything will | |
997 | have been initialized. We must do this even if one operand | |
998 | is a constant--see addsi3 in m68k.md. */ | |
999 | ||
1000 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
1001 | if (constraints[i][0] == '%') | |
1002 | { | |
1003 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1004 | int j; | |
246fd41f | 1005 | |
f741a71c JH |
1006 | /* Handle commutative operands by swapping the constraints. |
1007 | We assume the modes are the same. */ | |
1008 | ||
1009 | for (j = 0; j < recog_data.n_operands; j++) | |
1010 | xconstraints[j] = constraints[j]; | |
1011 | ||
1012 | xconstraints[i] = constraints[i+1]; | |
1013 | xconstraints[i+1] = constraints[i]; | |
1014 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1015 | recog_data.operand, modes, |
f741a71c JH |
1016 | xconstraints, insn, op_costs, reg_pref); |
1017 | } | |
1018 | ||
1019 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 1020 | recog_data.operand, modes, |
f741a71c JH |
1021 | constraints, insn, op_costs, reg_pref); |
1022 | } | |
54dac99e | 1023 | \f |
61719ba7 BS |
1024 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1025 | time it would save code to put a certain register in a certain class. | |
1026 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1027 | once. | |
1028 | Return the last insn processed, so that the scan can be continued from | |
1029 | there. */ | |
1030 | ||
1031 | static rtx | |
0c20a65f | 1032 | scan_one_insn (rtx insn, int pass) |
61719ba7 | 1033 | { |
61719ba7 | 1034 | enum rtx_code pat_code; |
0eadeb15 | 1035 | rtx set, note; |
61719ba7 | 1036 | int i, j; |
f741a71c | 1037 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 1038 | |
ec8e098d | 1039 | if (!INSN_P (insn)) |
61719ba7 BS |
1040 | return insn; |
1041 | ||
1042 | pat_code = GET_CODE (PATTERN (insn)); | |
1043 | if (pat_code == USE | |
1044 | || pat_code == CLOBBER | |
1045 | || pat_code == ASM_INPUT | |
1046 | || pat_code == ADDR_VEC | |
1047 | || pat_code == ADDR_DIFF_VEC) | |
1048 | return insn; | |
1049 | ||
0eadeb15 BS |
1050 | set = single_set (insn); |
1051 | extract_insn (insn); | |
1052 | ||
0eadeb15 BS |
1053 | /* If this insn loads a parameter from its stack slot, then |
1054 | it represents a savings, rather than a cost, if the | |
1055 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 1056 | |
f8cfc6aa | 1057 | if (set != 0 && REG_P (SET_DEST (set)) |
3c0cb5de | 1058 | && MEM_P (SET_SRC (set)) |
0eadeb15 BS |
1059 | && (note = find_reg_note (insn, REG_EQUIV, |
1060 | NULL_RTX)) != 0 | |
3c0cb5de | 1061 | && MEM_P (XEXP (note, 0))) |
0eadeb15 BS |
1062 | { |
1063 | costs[REGNO (SET_DEST (set))].mem_cost | |
1064 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1065 | GENERAL_REGS, 1) | |
9401afe3 | 1066 | * frequency); |
c4963a0a BS |
1067 | record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0), |
1068 | 0, MEM, SCRATCH, frequency * 2); | |
0eadeb15 BS |
1069 | return insn; |
1070 | } | |
61719ba7 | 1071 | |
0eadeb15 BS |
1072 | /* Improve handling of two-address insns such as |
1073 | (set X (ashift CONST Y)) where CONST must be made to | |
1074 | match X. Change it into two insns: (set X CONST) | |
1075 | (set X (ashift X Y)). If we left this for reloading, it | |
1076 | would probably get three insns because X and Y might go | |
1077 | in the same place. This prevents X and Y from receiving | |
1078 | the same hard reg. | |
1079 | ||
1080 | We can only do this if the modes of operands 0 and 1 | |
1081 | (which might not be the same) are tieable and we only need | |
1082 | do this during our first pass. */ | |
1083 | ||
1084 | if (pass == 0 && optimize | |
1ccbefce RH |
1085 | && recog_data.n_operands >= 3 |
1086 | && recog_data.constraints[1][0] == '0' | |
1087 | && recog_data.constraints[1][1] == 0 | |
1088 | && CONSTANT_P (recog_data.operand[1]) | |
1089 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1090 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
f8cfc6aa | 1091 | && REG_P (recog_data.operand[0]) |
1ccbefce RH |
1092 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), |
1093 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
1094 | { |
1095 | rtx previnsn = prev_real_insn (insn); | |
1096 | rtx dest | |
1ccbefce RH |
1097 | = gen_lowpart (recog_data.operand_mode[1], |
1098 | recog_data.operand[0]); | |
0eadeb15 | 1099 | rtx newinsn |
1ccbefce | 1100 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 1101 | |
0eadeb15 BS |
1102 | /* If this insn was the start of a basic block, |
1103 | include the new insn in that block. | |
1104 | We need not check for code_label here; | |
1105 | while a basic block can start with a code_label, | |
1106 | INSN could not be at the beginning of that block. */ | |
4b4bf941 | 1107 | if (previnsn == 0 || JUMP_P (previnsn)) |
61719ba7 | 1108 | { |
e0082a72 ZD |
1109 | basic_block b; |
1110 | FOR_EACH_BB (b) | |
a813c111 SB |
1111 | if (insn == BB_HEAD (b)) |
1112 | BB_HEAD (b) = newinsn; | |
61719ba7 BS |
1113 | } |
1114 | ||
0eadeb15 | 1115 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1116 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d3c7d45e | 1117 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1118 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
61719ba7 | 1119 | |
1ccbefce | 1120 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d3c7d45e | 1121 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1122 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
1ccbefce RH |
1123 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1124 | if (recog_data.dup_num[i] == 1) | |
d3c7d45e AO |
1125 | { |
1126 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1127 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
9401afe3 | 1128 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d3c7d45e | 1129 | } |
61719ba7 | 1130 | |
0eadeb15 | 1131 | return PREV_INSN (newinsn); |
61719ba7 BS |
1132 | } |
1133 | ||
4963c995 | 1134 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1135 | |
1136 | /* Now add the cost for each operand to the total costs for | |
1137 | its register. */ | |
1138 | ||
1ccbefce | 1139 | for (i = 0; i < recog_data.n_operands; i++) |
f8cfc6aa | 1140 | if (REG_P (recog_data.operand[i]) |
1ccbefce | 1141 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) |
61719ba7 | 1142 | { |
1ccbefce | 1143 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1144 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1145 | ||
9401afe3 | 1146 | p->mem_cost += q->mem_cost * frequency; |
61719ba7 | 1147 | for (j = 0; j < N_REG_CLASSES; j++) |
9401afe3 | 1148 | p->cost[j] += q->cost[j] * frequency; |
61719ba7 BS |
1149 | } |
1150 | ||
1151 | return insn; | |
1152 | } | |
1153 | ||
1f80c9ef MS |
1154 | /* Initialize information about which register classes can be used for |
1155 | pseudos that are auto-incremented or auto-decremented. */ | |
54dac99e | 1156 | |
1f80c9ef | 1157 | static void |
0c20a65f | 1158 | init_reg_autoinc (void) |
54dac99e | 1159 | { |
533d0835 | 1160 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1f80c9ef | 1161 | int i; |
533d0835 RK |
1162 | |
1163 | for (i = 0; i < N_REG_CLASSES; i++) | |
1164 | { | |
1f80c9ef | 1165 | rtx r = gen_rtx_raw_REG (VOIDmode, 0); |
533d0835 | 1166 | enum machine_mode m; |
b3694847 | 1167 | int j; |
533d0835 RK |
1168 | |
1169 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1170 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1171 | { | |
1172 | REGNO (r) = j; | |
1173 | ||
1174 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1175 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1176 | if (HARD_REGNO_MODE_OK (j, m)) |
1177 | { | |
c4963a0a BS |
1178 | /* ??? There are two assumptions here; that the base class does not |
1179 | depend on the exact outer code (POST_INC vs. PRE_INC etc.), and | |
1180 | that it does not depend on the machine mode of the memory | |
1181 | reference. */ | |
1182 | enum reg_class base_class | |
1183 | = base_reg_class (VOIDmode, POST_INC, SCRATCH); | |
8a99f6f9 | 1184 | |
533d0835 | 1185 | PUT_MODE (r, m); |
08d95f91 RK |
1186 | |
1187 | /* If a register is not directly suitable for an | |
1188 | auto-increment or decrement addressing mode and | |
1189 | requires secondary reloads, disallow its class from | |
1190 | being used in such addresses. */ | |
1191 | ||
8a99f6f9 R |
1192 | if ((secondary_reload_class (1, base_class, m, r) |
1193 | || secondary_reload_class (1, base_class, m, r)) | |
08d95f91 | 1194 | && ! auto_inc_dec_reg_p (r, m)) |
533d0835 RK |
1195 | forbidden_inc_dec_class[i] = 1; |
1196 | } | |
1197 | } | |
1198 | } | |
1f80c9ef MS |
1199 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1200 | } | |
1201 | ||
1202 | /* This is a pass of the compiler that scans all instructions | |
1203 | and calculates the preferred class for each pseudo-register. | |
1204 | This information can be accessed later by calling `reg_preferred_class'. | |
1205 | This pass comes just before local register allocation. */ | |
1206 | ||
1207 | void | |
10d22567 | 1208 | regclass (rtx f, int nregs) |
1f80c9ef MS |
1209 | { |
1210 | rtx insn; | |
1211 | int i; | |
1212 | int pass; | |
1213 | ||
1214 | init_recog (); | |
1215 | ||
5ed6ace5 | 1216 | costs = XNEWVEC (struct costs, nregs); |
1f80c9ef MS |
1217 | |
1218 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1219 | ||
5ed6ace5 | 1220 | in_inc_dec = XNEWVEC (char, nregs); |
1f80c9ef | 1221 | |
533d0835 RK |
1222 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1223 | ||
e4600702 RK |
1224 | /* Normally we scan the insns once and determine the best class to use for |
1225 | each register. However, if -fexpensive_optimizations are on, we do so | |
1226 | twice, the second time using the tentative best classes to guide the | |
1227 | selection. */ | |
54dac99e | 1228 | |
e4600702 RK |
1229 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1230 | { | |
e0082a72 | 1231 | basic_block bb; |
f741a71c | 1232 | |
10d22567 ZD |
1233 | if (dump_file) |
1234 | fprintf (dump_file, "\n\nPass %i\n\n",pass); | |
e4600702 | 1235 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1236 | |
703ad42b | 1237 | memset (costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1238 | |
533d0835 | 1239 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1240 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1241 | #endif |
1242 | ||
e4600702 RK |
1243 | /* Scan the instructions and record each time it would |
1244 | save code to put a certain register in a certain class. */ | |
1245 | ||
1f01879e | 1246 | if (!optimize) |
54dac99e | 1247 | { |
a08b2604 | 1248 | frequency = REG_FREQ_MAX; |
1f01879e JH |
1249 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1250 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1251 | } |
1f01879e | 1252 | else |
e0082a72 | 1253 | FOR_EACH_BB (bb) |
1f01879e | 1254 | { |
1f01879e | 1255 | /* Show that an insn inside a loop is likely to be executed three |
9b15c17f RH |
1256 | times more than insns outside a loop. This is much more |
1257 | aggressive than the assumptions made elsewhere and is being | |
1258 | tried as an experiment. */ | |
a08b2604 | 1259 | frequency = REG_FREQ_FROM_BB (bb); |
a813c111 | 1260 | for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) |
1f01879e JH |
1261 | { |
1262 | insn = scan_one_insn (insn, pass); | |
a813c111 | 1263 | if (insn == BB_END (bb)) |
1f01879e JH |
1264 | break; |
1265 | } | |
1266 | } | |
a6a2274a | 1267 | |
e4600702 RK |
1268 | /* Now for each register look at how desirable each class is |
1269 | and find which class is preferred. Store that in | |
9ffc5a70 | 1270 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1271 | class any of whose registers is better than memory. */ |
a6a2274a | 1272 | |
e4600702 | 1273 | if (pass == 0) |
9ffc5a70 | 1274 | reg_pref = reg_pref_buffer; |
54dac99e | 1275 | |
10d22567 | 1276 | if (dump_file) |
a6a2274a | 1277 | { |
10d22567 ZD |
1278 | dump_regclass (dump_file); |
1279 | fprintf (dump_file,"\n"); | |
f741a71c | 1280 | } |
e4600702 | 1281 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1282 | { |
b3694847 | 1283 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1284 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1285 | /* This is an enum reg_class, but we call it an int | |
1286 | to save lots of casts. */ | |
b3694847 SS |
1287 | int class; |
1288 | struct costs *p = &costs[i]; | |
e4600702 | 1289 | |
64615302 JH |
1290 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1291 | yet. */ | |
ed8d2920 | 1292 | if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) |
f741a71c JH |
1293 | continue; |
1294 | ||
e4600702 | 1295 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1296 | { |
533d0835 | 1297 | /* Ignore classes that are too small for this operand or |
4fe9b91c | 1298 | invalid for an operand that was auto-incremented. */ |
6df26b8f | 1299 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
533d0835 RK |
1300 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1301 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1302 | #endif |
cff9f8d5 AH |
1303 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1304 | || invalid_mode_change_p (i, (enum reg_class) class, | |
1305 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1306 | #endif |
1307 | ) | |
e4600702 RK |
1308 | ; |
1309 | else if (p->cost[class] < best_cost) | |
1310 | { | |
1311 | best_cost = p->cost[class]; | |
1312 | best = (enum reg_class) class; | |
1313 | } | |
1314 | else if (p->cost[class] == best_cost) | |
8e2e89f7 | 1315 | best = reg_class_subunion[(int) best][class]; |
54dac99e | 1316 | } |
54dac99e | 1317 | |
b5c82fa1 PB |
1318 | /* If no register class is better than memory, use memory. */ |
1319 | if (p->mem_cost < best_cost) | |
1320 | best = NO_REGS; | |
1321 | ||
e4600702 RK |
1322 | /* Record the alternate register class; i.e., a class for which |
1323 | every register in it is better than using memory. If adding a | |
1324 | class would make a smaller class (i.e., no union of just those | |
1325 | classes exists), skip that class. The major unions of classes | |
1326 | should be provided as a register class. Don't do this if we | |
1327 | will be doing it again later. */ | |
1328 | ||
10d22567 | 1329 | if ((pass == 1 || dump_file) || ! flag_expensive_optimizations) |
e4600702 RK |
1330 | for (class = 0; class < N_REG_CLASSES; class++) |
1331 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1332 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1333 | > reg_class_size[(int) alt]) |
1334 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1335 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1336 | #endif |
cff9f8d5 AH |
1337 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1338 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
1339 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1340 | #endif |
1341 | ) | |
e4600702 | 1342 | alt = reg_class_subunion[(int) alt][class]; |
a6a2274a | 1343 | |
e4600702 RK |
1344 | /* If we don't add any classes, nothing to try. */ |
1345 | if (alt == best) | |
995d54dd | 1346 | alt = NO_REGS; |
e4600702 | 1347 | |
10d22567 | 1348 | if (dump_file |
f741a71c JH |
1349 | && (reg_pref[i].prefclass != (int) best |
1350 | || reg_pref[i].altclass != (int) alt)) | |
1351 | { | |
10d22567 | 1352 | fprintf (dump_file, " Register %i", i); |
f741a71c | 1353 | if (alt == ALL_REGS || best == ALL_REGS) |
10d22567 | 1354 | fprintf (dump_file, " pref %s\n", reg_class_names[(int) best]); |
f741a71c | 1355 | else if (alt == NO_REGS) |
10d22567 | 1356 | fprintf (dump_file, " pref %s or none\n", reg_class_names[(int) best]); |
f741a71c | 1357 | else |
10d22567 | 1358 | fprintf (dump_file, " pref %s, else %s\n", |
f741a71c JH |
1359 | reg_class_names[(int) best], |
1360 | reg_class_names[(int) alt]); | |
1361 | } | |
1362 | ||
e4600702 | 1363 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1364 | reg_pref[i].prefclass = (int) best; |
1365 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1366 | } |
54dac99e | 1367 | } |
56a65848 | 1368 | |
4da896b2 MM |
1369 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1370 | free (in_inc_dec); | |
1371 | #endif | |
56a65848 | 1372 | free (costs); |
54dac99e RK |
1373 | } |
1374 | \f | |
e4600702 RK |
1375 | /* Record the cost of using memory or registers of various classes for |
1376 | the operands in INSN. | |
54dac99e | 1377 | |
e4600702 | 1378 | N_ALTS is the number of alternatives. |
54dac99e | 1379 | |
e4600702 RK |
1380 | N_OPS is the number of operands. |
1381 | ||
1382 | OPS is an array of the operands. | |
1383 | ||
1384 | MODES are the modes of the operands, in case any are VOIDmode. | |
1385 | ||
1386 | CONSTRAINTS are the constraints to use for the operands. This array | |
1387 | is modified by this procedure. | |
1388 | ||
1389 | This procedure works alternative by alternative. For each alternative | |
1390 | we assume that we will be able to allocate all pseudos to their ideal | |
1391 | register class and calculate the cost of using that alternative. Then | |
a6a2274a | 1392 | we compute for each operand that is a pseudo-register, the cost of |
e4600702 RK |
1393 | having the pseudo allocated to each register class and using it in that |
1394 | alternative. To this cost is added the cost of the alternative. | |
1395 | ||
1396 | The cost of each class for this insn is its lowest cost among all the | |
1397 | alternatives. */ | |
1398 | ||
1399 | static void | |
0c20a65f AJ |
1400 | record_reg_classes (int n_alts, int n_ops, rtx *ops, |
1401 | enum machine_mode *modes, const char **constraints, | |
1402 | rtx insn, struct costs *op_costs, | |
1403 | struct reg_pref *reg_pref) | |
54dac99e | 1404 | { |
e4600702 | 1405 | int alt; |
e4600702 | 1406 | int i, j; |
ec2d92af | 1407 | rtx set; |
e4600702 | 1408 | |
e4600702 RK |
1409 | /* Process each alternative, each time minimizing an operand's cost with |
1410 | the cost for each operand in that alternative. */ | |
54dac99e | 1411 | |
e4600702 | 1412 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1413 | { |
e4600702 RK |
1414 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1415 | int alt_fail = 0; | |
1416 | int alt_cost = 0; | |
1417 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1418 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1419 | int class; |
54dac99e | 1420 | |
e4600702 RK |
1421 | for (i = 0; i < n_ops; i++) |
1422 | { | |
9b3142b3 | 1423 | const char *p = constraints[i]; |
e4600702 RK |
1424 | rtx op = ops[i]; |
1425 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1426 | int allows_addr = 0; |
e4600702 | 1427 | int win = 0; |
e51712db | 1428 | unsigned char c; |
54dac99e | 1429 | |
7405d9a1 DE |
1430 | /* Initially show we know nothing about the register class. */ |
1431 | classes[i] = NO_REGS; | |
da2c0219 | 1432 | allows_mem[i] = 0; |
7405d9a1 | 1433 | |
a6a2274a | 1434 | /* If this operand has no constraints at all, we can conclude |
e4600702 | 1435 | nothing about it since anything is valid. */ |
54dac99e | 1436 | |
e4600702 RK |
1437 | if (*p == 0) |
1438 | { | |
f8cfc6aa | 1439 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
703ad42b | 1440 | memset (&this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1441 | |
e4600702 RK |
1442 | continue; |
1443 | } | |
54dac99e | 1444 | |
7405d9a1 DE |
1445 | /* If this alternative is only relevant when this operand |
1446 | matches a previous operand, we do different things depending | |
1447 | on whether this operand is a pseudo-reg or not. We must process | |
1448 | any modifiers for the operand before we can make this test. */ | |
1449 | ||
8c368ee2 | 1450 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1451 | p++; |
8c368ee2 | 1452 | |
e4600702 RK |
1453 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1454 | { | |
da2c0219 RK |
1455 | /* Copy class and whether memory is allowed from the matching |
1456 | alternative. Then perform any needed cost computations | |
1457 | and/or adjustments. */ | |
e4600702 RK |
1458 | j = p[0] - '0'; |
1459 | classes[i] = classes[j]; | |
da2c0219 | 1460 | allows_mem[i] = allows_mem[j]; |
e4600702 | 1461 | |
f8cfc6aa | 1462 | if (!REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
e4600702 RK |
1463 | { |
1464 | /* If this matches the other operand, we have no added | |
dc903608 | 1465 | cost and we win. */ |
e4600702 | 1466 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1467 | win = 1; |
e4600702 | 1468 | |
77e67eac RK |
1469 | /* If we can put the other operand into a register, add to |
1470 | the cost of this alternative the cost to copy this | |
1471 | operand to the register used for the other operand. */ | |
e4600702 | 1472 | |
dc903608 | 1473 | else if (classes[j] != NO_REGS) |
8a99f6f9 R |
1474 | { |
1475 | alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
1476 | win = 1; | |
1477 | } | |
e4600702 | 1478 | } |
f8cfc6aa | 1479 | else if (!REG_P (ops[j]) |
07d8ca2d RS |
1480 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) |
1481 | { | |
1482 | /* This op is a pseudo but the one it matches is not. */ | |
a6a2274a | 1483 | |
07d8ca2d RS |
1484 | /* If we can't put the other operand into a register, this |
1485 | alternative can't be used. */ | |
1486 | ||
1487 | if (classes[j] == NO_REGS) | |
1488 | alt_fail = 1; | |
e4600702 | 1489 | |
07d8ca2d RS |
1490 | /* Otherwise, add to the cost of this alternative the cost |
1491 | to copy the other operand to the register used for this | |
1492 | operand. */ | |
1493 | ||
1494 | else | |
8a99f6f9 | 1495 | alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); |
07d8ca2d | 1496 | } |
e4600702 RK |
1497 | else |
1498 | { | |
da2c0219 RK |
1499 | /* The costs of this operand are not the same as the other |
1500 | operand since move costs are not symmetric. Moreover, | |
1501 | if we cannot tie them, this alternative needs to do a | |
1502 | copy, which is one instruction. */ | |
1503 | ||
1504 | struct costs *pp = &this_op_costs[i]; | |
1505 | ||
1506 | for (class = 0; class < N_REG_CLASSES; class++) | |
1507 | pp->cost[class] | |
d5e2075d | 1508 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1509 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1510 | : 0) |
1511 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1512 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1513 | : 0)); |
a6a2274a | 1514 | |
da2c0219 RK |
1515 | /* If the alternative actually allows memory, make things |
1516 | a bit cheaper since we won't need an extra insn to | |
1517 | load it. */ | |
1518 | ||
1519 | pp->mem_cost | |
d5e2075d JH |
1520 | = ((recog_data.operand_type[i] != OP_IN |
1521 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1522 | : 0) | |
1523 | + (recog_data.operand_type[i] != OP_OUT | |
1524 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1525 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1526 | |
1527 | /* If we have assigned a class to this register in our | |
1528 | first pass, add a cost to this alternative corresponding | |
1529 | to what we would add if this register were not in the | |
1530 | appropriate class. */ | |
1531 | ||
b5c82fa1 | 1532 | if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS) |
da2c0219 | 1533 | alt_cost |
e56b4594 AO |
1534 | += (may_move_in_cost[mode] |
1535 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1536 | [(int) classes[i]]); |
e4600702 | 1537 | |
37747c82 RK |
1538 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1539 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1540 | alt_cost += 2; | |
e4600702 | 1541 | |
347099d6 | 1542 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1543 | for this operand, so skip to the end of the |
1544 | alternative (should be just one character). */ | |
1545 | while (*p && *p++ != ',') | |
1546 | ; | |
1547 | ||
1548 | constraints[i] = p; | |
347099d6 RS |
1549 | continue; |
1550 | } | |
e4600702 RK |
1551 | } |
1552 | ||
1553 | /* Scan all the constraint letters. See if the operand matches | |
1554 | any of the constraints. Collect the valid register classes | |
1555 | and see if this operand accepts memory. */ | |
1556 | ||
97488870 R |
1557 | while ((c = *p)) |
1558 | { | |
1559 | switch (c) | |
1560 | { | |
1561 | case ',': | |
1562 | break; | |
1563 | case '*': | |
1564 | /* Ignore the next letter for this pass. */ | |
1565 | c = *++p; | |
1566 | break; | |
94e6f783 | 1567 | |
97488870 R |
1568 | case '?': |
1569 | alt_cost += 2; | |
1570 | case '!': case '#': case '&': | |
1571 | case '0': case '1': case '2': case '3': case '4': | |
1572 | case '5': case '6': case '7': case '8': case '9': | |
1573 | break; | |
e4600702 | 1574 | |
97488870 R |
1575 | case 'p': |
1576 | allows_addr = 1; | |
1577 | win = address_operand (op, GET_MODE (op)); | |
1578 | /* We know this operand is an address, so we want it to be | |
1579 | allocated to a register that can be the base of an | |
454ff5cb | 1580 | address, i.e. BASE_REG_CLASS. */ |
97488870 R |
1581 | classes[i] |
1582 | = reg_class_subunion[(int) classes[i]] | |
c4963a0a | 1583 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
97488870 | 1584 | break; |
e4600702 | 1585 | |
97488870 R |
1586 | case 'm': case 'o': case 'V': |
1587 | /* It doesn't seem worth distinguishing between offsettable | |
1588 | and non-offsettable addresses here. */ | |
1589 | allows_mem[i] = 1; | |
3c0cb5de | 1590 | if (MEM_P (op)) |
97488870 R |
1591 | win = 1; |
1592 | break; | |
e4600702 | 1593 | |
97488870 | 1594 | case '<': |
3c0cb5de | 1595 | if (MEM_P (op) |
97488870 R |
1596 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC |
1597 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1598 | win = 1; | |
1599 | break; | |
e4600702 | 1600 | |
97488870 | 1601 | case '>': |
3c0cb5de | 1602 | if (MEM_P (op) |
97488870 R |
1603 | && (GET_CODE (XEXP (op, 0)) == PRE_INC |
1604 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1605 | win = 1; | |
1606 | break; | |
e4600702 | 1607 | |
97488870 R |
1608 | case 'E': |
1609 | case 'F': | |
1610 | if (GET_CODE (op) == CONST_DOUBLE | |
1611 | || (GET_CODE (op) == CONST_VECTOR | |
1612 | && (GET_MODE_CLASS (GET_MODE (op)) | |
1613 | == MODE_VECTOR_FLOAT))) | |
1614 | win = 1; | |
1615 | break; | |
e4600702 | 1616 | |
97488870 R |
1617 | case 'G': |
1618 | case 'H': | |
1619 | if (GET_CODE (op) == CONST_DOUBLE | |
1620 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
1621 | win = 1; | |
e4600702 | 1622 | break; |
97488870 R |
1623 | |
1624 | case 's': | |
1625 | if (GET_CODE (op) == CONST_INT | |
1626 | || (GET_CODE (op) == CONST_DOUBLE | |
1627 | && GET_MODE (op) == VOIDmode)) | |
1628 | break; | |
1629 | case 'i': | |
1630 | if (CONSTANT_P (op) | |
2e4e72b1 | 1631 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))) |
97488870 R |
1632 | win = 1; |
1633 | break; | |
e4600702 | 1634 | |
97488870 R |
1635 | case 'n': |
1636 | if (GET_CODE (op) == CONST_INT | |
1637 | || (GET_CODE (op) == CONST_DOUBLE | |
1638 | && GET_MODE (op) == VOIDmode)) | |
1639 | win = 1; | |
1640 | break; | |
e4600702 | 1641 | |
97488870 R |
1642 | case 'I': |
1643 | case 'J': | |
1644 | case 'K': | |
1645 | case 'L': | |
1646 | case 'M': | |
1647 | case 'N': | |
1648 | case 'O': | |
1649 | case 'P': | |
1650 | if (GET_CODE (op) == CONST_INT | |
1651 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1652 | win = 1; | |
1653 | break; | |
e4600702 | 1654 | |
97488870 R |
1655 | case 'X': |
1656 | win = 1; | |
1657 | break; | |
54dac99e | 1658 | |
97488870 | 1659 | case 'g': |
3c0cb5de | 1660 | if (MEM_P (op) |
97488870 | 1661 | || (CONSTANT_P (op) |
2e4e72b1 | 1662 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) |
97488870 R |
1663 | win = 1; |
1664 | allows_mem[i] = 1; | |
1665 | case 'r': | |
c2cba7a9 | 1666 | classes[i] |
97488870 R |
1667 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; |
1668 | break; | |
ccfc6cc8 | 1669 | |
97488870 R |
1670 | default: |
1671 | if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
ccfc6cc8 UW |
1672 | classes[i] |
1673 | = reg_class_subunion[(int) classes[i]] | |
97488870 R |
1674 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
1675 | #ifdef EXTRA_CONSTRAINT_STR | |
1676 | else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1677 | win = 1; | |
1678 | ||
1679 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1680 | { | |
1681 | /* Every MEM can be reloaded to fit. */ | |
1682 | allows_mem[i] = 1; | |
3c0cb5de | 1683 | if (MEM_P (op)) |
97488870 R |
1684 | win = 1; |
1685 | } | |
1686 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1687 | { | |
1688 | /* Every address can be reloaded to fit. */ | |
1689 | allows_addr = 1; | |
1690 | if (address_operand (op, GET_MODE (op))) | |
1691 | win = 1; | |
1692 | /* We know this operand is an address, so we want it to | |
1693 | be allocated to a register that can be the base of an | |
454ff5cb | 1694 | address, i.e. BASE_REG_CLASS. */ |
97488870 R |
1695 | classes[i] |
1696 | = reg_class_subunion[(int) classes[i]] | |
c4963a0a | 1697 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
97488870 | 1698 | } |
c2cba7a9 | 1699 | #endif |
97488870 R |
1700 | break; |
1701 | } | |
1702 | p += CONSTRAINT_LEN (c, p); | |
1703 | if (c == ',') | |
c2cba7a9 | 1704 | break; |
97488870 | 1705 | } |
e4600702 RK |
1706 | |
1707 | constraints[i] = p; | |
1708 | ||
1709 | /* How we account for this operand now depends on whether it is a | |
1710 | pseudo register or not. If it is, we first check if any | |
1711 | register classes are valid. If not, we ignore this alternative, | |
1712 | since we want to assume that all pseudos get allocated for | |
1713 | register preferencing. If some register class is valid, compute | |
1714 | the costs of moving the pseudo into that class. */ | |
1715 | ||
f8cfc6aa | 1716 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
4db18574 | 1717 | { |
e4600702 | 1718 | if (classes[i] == NO_REGS) |
94e6f783 | 1719 | { |
e79f71f7 GK |
1720 | /* We must always fail if the operand is a REG, but |
1721 | we did not find a suitable class. | |
a6a2274a | 1722 | |
e79f71f7 GK |
1723 | Otherwise we may perform an uninitialized read |
1724 | from this_op_costs after the `continue' statement | |
1725 | below. */ | |
1726 | alt_fail = 1; | |
94e6f783 | 1727 | } |
e4600702 RK |
1728 | else |
1729 | { | |
1730 | struct costs *pp = &this_op_costs[i]; | |
1731 | ||
1732 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1733 | pp->cost[class] |
d5e2075d | 1734 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1735 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1736 | : 0) |
1737 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1738 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1739 | : 0)); |
e4600702 RK |
1740 | |
1741 | /* If the alternative actually allows memory, make things | |
1742 | a bit cheaper since we won't need an extra insn to | |
1743 | load it. */ | |
1744 | ||
14a774a9 | 1745 | pp->mem_cost |
d5e2075d JH |
1746 | = ((recog_data.operand_type[i] != OP_IN |
1747 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1748 | : 0) | |
1749 | + (recog_data.operand_type[i] != OP_OUT | |
1750 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1751 | : 0) - allows_mem[i]); | |
e4600702 RK |
1752 | |
1753 | /* If we have assigned a class to this register in our | |
1754 | first pass, add a cost to this alternative corresponding | |
1755 | to what we would add if this register were not in the | |
1756 | appropriate class. */ | |
1757 | ||
b5c82fa1 | 1758 | if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS) |
e4600702 | 1759 | alt_cost |
e56b4594 AO |
1760 | += (may_move_in_cost[mode] |
1761 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1762 | [(int) classes[i]]); |
e4600702 | 1763 | } |
4db18574 | 1764 | } |
54dac99e | 1765 | |
e4600702 RK |
1766 | /* Otherwise, if this alternative wins, either because we |
1767 | have already determined that or if we have a hard register of | |
1768 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1769 | |
e4600702 | 1770 | else if (win |
f8cfc6aa | 1771 | || (REG_P (op) |
6f654776 | 1772 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1773 | ; |
54dac99e | 1774 | |
e4600702 RK |
1775 | /* If registers are valid, the cost of this alternative includes |
1776 | copying the object to and/or from a register. */ | |
54dac99e | 1777 | |
e4600702 RK |
1778 | else if (classes[i] != NO_REGS) |
1779 | { | |
1ccbefce | 1780 | if (recog_data.operand_type[i] != OP_OUT) |
8a99f6f9 | 1781 | alt_cost += copy_cost (op, mode, classes[i], 1, NULL); |
54dac99e | 1782 | |
1ccbefce | 1783 | if (recog_data.operand_type[i] != OP_IN) |
8a99f6f9 | 1784 | alt_cost += copy_cost (op, mode, classes[i], 0, NULL); |
e4600702 | 1785 | } |
54dac99e | 1786 | |
e4600702 RK |
1787 | /* The only other way this alternative can be used is if this is a |
1788 | constant that could be placed into memory. */ | |
1789 | ||
da2c0219 | 1790 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1791 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1792 | else |
1793 | alt_fail = 1; | |
1794 | } | |
1795 | ||
1796 | if (alt_fail) | |
1797 | continue; | |
1798 | ||
1799 | /* Finally, update the costs with the information we've calculated | |
1800 | about this alternative. */ | |
1801 | ||
1802 | for (i = 0; i < n_ops; i++) | |
f8cfc6aa | 1803 | if (REG_P (ops[i]) |
e4600702 | 1804 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) |
54dac99e | 1805 | { |
e4600702 | 1806 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1807 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1808 | |
e4600702 RK |
1809 | pp->mem_cost = MIN (pp->mem_cost, |
1810 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1811 | |
e4600702 RK |
1812 | for (class = 0; class < N_REG_CLASSES; class++) |
1813 | pp->cost[class] = MIN (pp->cost[class], | |
1814 | (qq->cost[class] + alt_cost) * scale); | |
1815 | } | |
1816 | } | |
ec2d92af RK |
1817 | |
1818 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1819 | and one operand is a pseudo with the other a hard reg or a pseudo |
1820 | that prefers a register that is in its own register class then | |
1821 | we may want to adjust the cost of that register class to -1. | |
a6a2274a | 1822 | |
accef103 | 1823 | Avoid the adjustment if the source does not die to avoid stressing of |
4d6922ee | 1824 | register allocator by preferrencing two colliding registers into single |
accef103 JL |
1825 | class. |
1826 | ||
1827 | Also avoid the adjustment if a copy between registers of the class | |
1828 | is expensive (ten times the cost of a default copy is considered | |
1829 | arbitrarily expensive). This avoids losing when the preferred class | |
1830 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1831 | |
1832 | if ((set = single_set (insn)) != 0 | |
1833 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
f8cfc6aa | 1834 | && REG_P (ops[0]) && REG_P (ops[1]) |
0dc0641b | 1835 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) |
ec2d92af RK |
1836 | for (i = 0; i <= 1; i++) |
1837 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1838 | { | |
770ae6cc | 1839 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1840 | enum machine_mode mode = GET_MODE (ops[!i]); |
1841 | int class; | |
770ae6cc | 1842 | unsigned int nr; |
ec2d92af | 1843 | |
b5c82fa1 PB |
1844 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0 |
1845 | && reg_pref[regno].prefclass != NO_REGS) | |
accef103 JL |
1846 | { |
1847 | enum reg_class pref = reg_pref[regno].prefclass; | |
1848 | ||
1849 | if ((reg_class_size[(unsigned char) pref] | |
f7043461 | 1850 | == (unsigned) CLASS_MAX_NREGS (pref, mode)) |
e56b4594 | 1851 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1852 | op_costs[i].cost[(unsigned char) pref] = -1; |
1853 | } | |
ec2d92af RK |
1854 | else if (regno < FIRST_PSEUDO_REGISTER) |
1855 | for (class = 0; class < N_REG_CLASSES; class++) | |
1856 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
f7043461 | 1857 | && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) |
4841ba4b RK |
1858 | { |
1859 | if (reg_class_size[class] == 1) | |
1860 | op_costs[i].cost[class] = -1; | |
1861 | else | |
1862 | { | |
66fd46b6 | 1863 | for (nr = 0; nr < (unsigned) hard_regno_nregs[regno][mode]; nr++) |
4841ba4b | 1864 | { |
770ae6cc RK |
1865 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1866 | regno + nr)) | |
4841ba4b RK |
1867 | break; |
1868 | } | |
1869 | ||
66fd46b6 | 1870 | if (nr == (unsigned) hard_regno_nregs[regno][mode]) |
4841ba4b RK |
1871 | op_costs[i].cost[class] = -1; |
1872 | } | |
1873 | } | |
ec2d92af | 1874 | } |
54dac99e | 1875 | } |
e4600702 | 1876 | \f |
40f03658 | 1877 | /* Compute the cost of loading X into (if TO_P is nonzero) or from (if |
e4600702 RK |
1878 | TO_P is zero) a register of class CLASS in mode MODE. |
1879 | ||
1880 | X must not be a pseudo. */ | |
1881 | ||
1882 | static int | |
8a99f6f9 R |
1883 | copy_cost (rtx x, enum machine_mode mode, enum reg_class class, int to_p, |
1884 | secondary_reload_info *prev_sri) | |
e4600702 RK |
1885 | { |
1886 | enum reg_class secondary_class = NO_REGS; | |
8a99f6f9 | 1887 | secondary_reload_info sri; |
e4600702 RK |
1888 | |
1889 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1890 | assuming optimal allocation. */ | |
1891 | ||
1892 | if (GET_CODE (x) == SCRATCH) | |
1893 | return 0; | |
1894 | ||
1895 | /* Get the class we will actually use for a reload. */ | |
1896 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1897 | ||
8a99f6f9 | 1898 | /* If we need a secondary reload for an intermediate, the |
e4600702 | 1899 | cost is that to load the input into the intermediate register, then |
8a99f6f9 | 1900 | to copy it. */ |
e4600702 | 1901 | |
8a99f6f9 R |
1902 | sri.prev_sri = prev_sri; |
1903 | sri.extra_cost = 0; | |
1904 | secondary_class = targetm.secondary_reload (to_p, x, class, mode, &sri); | |
e4600702 RK |
1905 | |
1906 | if (secondary_class != NO_REGS) | |
e56b4594 | 1907 | return (move_cost[mode][(int) secondary_class][(int) class] |
8a99f6f9 R |
1908 | + sri.extra_cost |
1909 | + copy_cost (x, mode, secondary_class, to_p, &sri)); | |
e4600702 RK |
1910 | |
1911 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1912 | cost to move between the register classes, and use 2 for everything | |
1913 | else (constants). */ | |
1914 | ||
3c0cb5de | 1915 | if (MEM_P (x) || class == NO_REGS) |
8a99f6f9 | 1916 | return sri.extra_cost + MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1917 | |
f8cfc6aa | 1918 | else if (REG_P (x)) |
8a99f6f9 R |
1919 | return (sri.extra_cost |
1920 | + move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]); | |
e4600702 RK |
1921 | |
1922 | else | |
1923 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
8a99f6f9 | 1924 | return sri.extra_cost + COSTS_N_INSNS (1); |
e4600702 RK |
1925 | } |
1926 | \f | |
54dac99e RK |
1927 | /* Record the pseudo registers we must reload into hard registers |
1928 | in a subexpression of a memory address, X. | |
e4600702 | 1929 | |
c4963a0a BS |
1930 | If CONTEXT is 0, we are looking at the base part of an address, otherwise we |
1931 | are looking at the index part. | |
1932 | ||
1933 | MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE | |
1934 | give the context that the rtx appears in. These three arguments are | |
1935 | passed down to base_reg_class. | |
e4600702 RK |
1936 | |
1937 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1938 | can represent half-cost adjustments). */ | |
54dac99e | 1939 | |
197d6480 | 1940 | static void |
c4963a0a BS |
1941 | record_address_regs (enum machine_mode mode, rtx x, int context, |
1942 | enum rtx_code outer_code, enum rtx_code index_code, | |
1943 | int scale) | |
54dac99e | 1944 | { |
b3694847 | 1945 | enum rtx_code code = GET_CODE (x); |
c4963a0a BS |
1946 | enum reg_class class; |
1947 | ||
1948 | if (context == 1) | |
1949 | class = INDEX_REG_CLASS; | |
1950 | else | |
1951 | class = base_reg_class (mode, outer_code, index_code); | |
54dac99e RK |
1952 | |
1953 | switch (code) | |
1954 | { | |
1955 | case CONST_INT: | |
1956 | case CONST: | |
1957 | case CC0: | |
1958 | case PC: | |
1959 | case SYMBOL_REF: | |
1960 | case LABEL_REF: | |
1961 | return; | |
1962 | ||
1963 | case PLUS: | |
1964 | /* When we have an address that is a sum, | |
1965 | we must determine whether registers are "base" or "index" regs. | |
1966 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1967 | the "base". Luckily, we can use the REG_POINTER to make a good |
1968 | choice most of the time. We only need to do this on machines | |
1969 | that can have two registers in an address and where the base | |
1970 | and index register classes are different. | |
e4600702 RK |
1971 | |
1972 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1973 | that seems bogus since it should only be set when we are sure | |
1974 | the register is being used as a pointer. */ | |
1975 | ||
54dac99e RK |
1976 | { |
1977 | rtx arg0 = XEXP (x, 0); | |
1978 | rtx arg1 = XEXP (x, 1); | |
b3694847 SS |
1979 | enum rtx_code code0 = GET_CODE (arg0); |
1980 | enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1981 | |
1982 | /* Look inside subregs. */ | |
e4600702 | 1983 | if (code0 == SUBREG) |
54dac99e | 1984 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1985 | if (code1 == SUBREG) |
54dac99e RK |
1986 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1987 | ||
e4600702 RK |
1988 | /* If this machine only allows one register per address, it must |
1989 | be in the first operand. */ | |
1990 | ||
1991 | if (MAX_REGS_PER_ADDRESS == 1) | |
c4963a0a | 1992 | record_address_regs (mode, arg0, 0, PLUS, code1, scale); |
e4600702 RK |
1993 | |
1994 | /* If index and base registers are the same on this machine, just | |
1995 | record registers in any non-constant operands. We assume here, | |
a6a2274a | 1996 | as well as in the tests below, that all addresses are in |
e4600702 RK |
1997 | canonical form. */ |
1998 | ||
c4963a0a | 1999 | else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH)) |
54dac99e | 2000 | { |
c4963a0a | 2001 | record_address_regs (mode, arg0, context, PLUS, code1, scale); |
e4600702 | 2002 | if (! CONSTANT_P (arg1)) |
c4963a0a | 2003 | record_address_regs (mode, arg1, context, PLUS, code0, scale); |
54dac99e | 2004 | } |
e4600702 RK |
2005 | |
2006 | /* If the second operand is a constant integer, it doesn't change | |
2007 | what class the first operand must be. */ | |
2008 | ||
2009 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
c4963a0a | 2010 | record_address_regs (mode, arg0, context, PLUS, code1, scale); |
e4600702 RK |
2011 | |
2012 | /* If the second operand is a symbolic constant, the first operand | |
2013 | must be an index register. */ | |
2014 | ||
2015 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
c4963a0a | 2016 | record_address_regs (mode, arg0, 1, PLUS, code1, scale); |
e4600702 | 2017 | |
956d6950 | 2018 | /* If both operands are registers but one is already a hard register |
888d2cd6 DJ |
2019 | of index or reg-base class, give the other the class that the |
2020 | hard register is not. */ | |
956d6950 JL |
2021 | |
2022 | else if (code0 == REG && code1 == REG | |
2023 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
c4963a0a BS |
2024 | && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) |
2025 | || ok_for_index_p_nonstrict (arg0))) | |
2026 | record_address_regs (mode, arg1, | |
2027 | ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
2028 | ? 1 : 0, | |
2029 | PLUS, REG, scale); | |
956d6950 JL |
2030 | else if (code0 == REG && code1 == REG |
2031 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
c4963a0a BS |
2032 | && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) |
2033 | || ok_for_index_p_nonstrict (arg1))) | |
2034 | record_address_regs (mode, arg0, | |
2035 | ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
2036 | ? 1 : 0, | |
2037 | PLUS, REG, scale); | |
956d6950 | 2038 | |
e9a25f70 JL |
2039 | /* If one operand is known to be a pointer, it must be the base |
2040 | with the other operand the index. Likewise if the other operand | |
2041 | is a MULT. */ | |
f22376c7 | 2042 | |
3502dc9c | 2043 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 2044 | || code1 == MULT) |
f22376c7 | 2045 | { |
c4963a0a BS |
2046 | record_address_regs (mode, arg0, 0, PLUS, code1, scale); |
2047 | record_address_regs (mode, arg1, 1, PLUS, code0, scale); | |
f22376c7 | 2048 | } |
3502dc9c | 2049 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 2050 | || code0 == MULT) |
f22376c7 | 2051 | { |
c4963a0a BS |
2052 | record_address_regs (mode, arg0, 1, PLUS, code1, scale); |
2053 | record_address_regs (mode, arg1, 0, PLUS, code0, scale); | |
f22376c7 CI |
2054 | } |
2055 | ||
e9a25f70 | 2056 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
2057 | or index register. This case should be rare. */ |
2058 | ||
e9a25f70 | 2059 | else |
54dac99e | 2060 | { |
c4963a0a BS |
2061 | record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2); |
2062 | record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2); | |
2063 | record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2); | |
2064 | record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2); | |
54dac99e | 2065 | } |
54dac99e RK |
2066 | } |
2067 | break; | |
2068 | ||
4b983fdc RH |
2069 | /* Double the importance of a pseudo register that is incremented |
2070 | or decremented, since it would take two extra insns | |
2071 | if it ends up in the wrong place. */ | |
2072 | case POST_MODIFY: | |
2073 | case PRE_MODIFY: | |
c4963a0a BS |
2074 | record_address_regs (mode, XEXP (x, 0), 0, code, |
2075 | GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); | |
4b983fdc | 2076 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
c4963a0a BS |
2077 | record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG, |
2078 | 2 * scale); | |
4b983fdc RH |
2079 | break; |
2080 | ||
54dac99e RK |
2081 | case POST_INC: |
2082 | case PRE_INC: | |
2083 | case POST_DEC: | |
2084 | case PRE_DEC: | |
2085 | /* Double the importance of a pseudo register that is incremented | |
2086 | or decremented, since it would take two extra insns | |
533d0835 RK |
2087 | if it ends up in the wrong place. If the operand is a pseudo, |
2088 | show it is being used in an INC_DEC context. */ | |
2089 | ||
2090 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
f8cfc6aa | 2091 | if (REG_P (XEXP (x, 0)) |
533d0835 RK |
2092 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) |
2093 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2094 | #endif | |
e4600702 | 2095 | |
c4963a0a | 2096 | record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); |
54dac99e RK |
2097 | break; |
2098 | ||
2099 | case REG: | |
2100 | { | |
b3694847 SS |
2101 | struct costs *pp = &costs[REGNO (x)]; |
2102 | int i; | |
54dac99e | 2103 | |
cbd5b9a2 | 2104 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 2105 | |
e4600702 | 2106 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 2107 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
2108 | } |
2109 | break; | |
2110 | ||
2111 | default: | |
2112 | { | |
b3694847 SS |
2113 | const char *fmt = GET_RTX_FORMAT (code); |
2114 | int i; | |
54dac99e RK |
2115 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2116 | if (fmt[i] == 'e') | |
c4963a0a BS |
2117 | record_address_regs (mode, XEXP (x, i), context, code, SCRATCH, |
2118 | scale); | |
54dac99e RK |
2119 | } |
2120 | } | |
2121 | } | |
08d95f91 RK |
2122 | \f |
2123 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2124 | ||
2125 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2126 | to an object of MODE. */ | |
2127 | ||
1d300e19 | 2128 | static int |
0c20a65f | 2129 | auto_inc_dec_reg_p (rtx reg, enum machine_mode mode) |
08d95f91 | 2130 | { |
940da324 JL |
2131 | if (HAVE_POST_INCREMENT |
2132 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2133 | return 1; |
08d95f91 | 2134 | |
940da324 JL |
2135 | if (HAVE_POST_DECREMENT |
2136 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2137 | return 1; |
08d95f91 | 2138 | |
940da324 JL |
2139 | if (HAVE_PRE_INCREMENT |
2140 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2141 | return 1; |
08d95f91 | 2142 | |
940da324 JL |
2143 | if (HAVE_PRE_DECREMENT |
2144 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2145 | return 1; |
08d95f91 RK |
2146 | |
2147 | return 0; | |
2148 | } | |
2149 | #endif | |
b1f21e0a | 2150 | \f |
da668e9c MM |
2151 | static short *renumber; |
2152 | static size_t regno_allocated; | |
2153 | static unsigned int reg_n_max; | |
ed396e68 | 2154 | |
b1f21e0a MM |
2155 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2156 | reg_scan and flow_analysis that are indexed by the register number. If | |
88cad84b | 2157 | NEW_P is nonzero, initialize all of the registers, otherwise only |
39379e67 MM |
2158 | initialize the new registers allocated. The same table is kept from |
2159 | function to function, only reallocating it when we need more room. If | |
88cad84b | 2160 | RENUMBER_P is nonzero, allocate the reg_renumber array also. */ |
b1f21e0a MM |
2161 | |
2162 | void | |
0c20a65f | 2163 | allocate_reg_info (size_t num_regs, int new_p, int renumber_p) |
b1f21e0a | 2164 | { |
6feacd09 MM |
2165 | size_t size_info; |
2166 | size_t size_renumber; | |
2167 | size_t min = (new_p) ? 0 : reg_n_max; | |
2168 | struct reg_info_data *reg_data; | |
39379e67 | 2169 | |
b1f21e0a MM |
2170 | if (num_regs > regno_allocated) |
2171 | { | |
6feacd09 MM |
2172 | size_t old_allocated = regno_allocated; |
2173 | ||
938d968e | 2174 | regno_allocated = num_regs + (num_regs / 20); /* Add some slop space. */ |
39379e67 MM |
2175 | size_renumber = regno_allocated * sizeof (short); |
2176 | ||
2177 | if (!reg_n_info) | |
2178 | { | |
1935e8a8 KH |
2179 | reg_n_info = VEC_alloc (reg_info_p, heap, regno_allocated); |
2180 | VEC_safe_grow (reg_info_p, heap, reg_n_info, regno_allocated); | |
2181 | memset (VEC_address (reg_info_p, reg_n_info), 0, | |
2182 | sizeof (reg_info_p) * regno_allocated); | |
703ad42b | 2183 | renumber = xmalloc (size_renumber); |
5ed6ace5 | 2184 | reg_pref_buffer = XNEWVEC (struct reg_pref, regno_allocated); |
39379e67 | 2185 | } |
39379e67 MM |
2186 | else |
2187 | { | |
1935e8a8 KH |
2188 | size_t old_length = VEC_length (reg_info_p, reg_n_info); |
2189 | if (old_length < regno_allocated) | |
2190 | { | |
2191 | reg_info_p *addr; | |
2192 | VEC_safe_grow (reg_info_p, heap, reg_n_info, regno_allocated); | |
2193 | addr = VEC_address (reg_info_p, reg_n_info); | |
2194 | memset (&addr[old_length], 0, | |
2195 | sizeof (reg_info_p) * (regno_allocated - old_length)); | |
2196 | } | |
2197 | else if (regno_allocated < old_length) | |
2198 | { | |
2199 | VEC_truncate (reg_info_p, reg_n_info, regno_allocated); | |
2200 | } | |
6feacd09 | 2201 | |
938d968e | 2202 | if (new_p) /* If we're zapping everything, no need to realloc. */ |
6feacd09 | 2203 | { |
8e2e89f7 KH |
2204 | free ((char *) renumber); |
2205 | free ((char *) reg_pref); | |
703ad42b | 2206 | renumber = xmalloc (size_renumber); |
5ed6ace5 | 2207 | reg_pref_buffer = XNEWVEC (struct reg_pref, regno_allocated); |
6feacd09 MM |
2208 | } |
2209 | ||
2210 | else | |
2211 | { | |
703ad42b | 2212 | renumber = xrealloc (renumber, size_renumber); |
5ed6ace5 | 2213 | reg_pref_buffer = (struct reg_pref *) xrealloc (reg_pref_buffer, |
703ad42b KG |
2214 | regno_allocated |
2215 | * sizeof (struct reg_pref)); | |
6feacd09 | 2216 | } |
39379e67 | 2217 | } |
6feacd09 MM |
2218 | |
2219 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2220 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
703ad42b | 2221 | reg_data = xcalloc (size_info, 1); |
6feacd09 MM |
2222 | reg_data->min_index = old_allocated; |
2223 | reg_data->max_index = regno_allocated - 1; | |
2224 | reg_data->next = reg_info_head; | |
2225 | reg_info_head = reg_data; | |
b1f21e0a MM |
2226 | } |
2227 | ||
6feacd09 | 2228 | reg_n_max = num_regs; |
b1f21e0a MM |
2229 | if (min < num_regs) |
2230 | { | |
6feacd09 MM |
2231 | /* Loop through each of the segments allocated for the actual |
2232 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
a6a2274a | 2233 | for (reg_data = reg_info_head; |
da668e9c MM |
2234 | reg_data && reg_data->max_index >= min; |
2235 | reg_data = reg_data->next) | |
39379e67 | 2236 | { |
6feacd09 MM |
2237 | size_t min_index = reg_data->min_index; |
2238 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2239 | size_t max = MIN (max_index, num_regs); |
2240 | size_t local_min = min - min_index; | |
2241 | size_t i; | |
6feacd09 | 2242 | |
da668e9c MM |
2243 | if (reg_data->min_index > num_regs) |
2244 | continue; | |
6feacd09 | 2245 | |
da668e9c MM |
2246 | if (min < min_index) |
2247 | local_min = 0; | |
2248 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2249 | reg_data->used_p = 1; /* no need to zero */ | |
2250 | else | |
703ad42b KG |
2251 | memset (®_data->data[local_min], 0, |
2252 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
da668e9c MM |
2253 | |
2254 | for (i = min_index+local_min; i <= max; i++) | |
2255 | { | |
1935e8a8 KH |
2256 | VEC_replace (reg_info_p, reg_n_info, i, |
2257 | ®_data->data[i-min_index]); | |
da668e9c MM |
2258 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; |
2259 | renumber[i] = -1; | |
2260 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2261 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2262 | } |
39379e67 | 2263 | } |
b1f21e0a MM |
2264 | } |
2265 | ||
6feacd09 MM |
2266 | /* If {pref,alt}class have already been allocated, update the pointers to |
2267 | the newly realloced ones. */ | |
9ffc5a70 JH |
2268 | if (reg_pref) |
2269 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2270 | |
39379e67 MM |
2271 | if (renumber_p) |
2272 | reg_renumber = renumber; | |
b1f21e0a MM |
2273 | } |
2274 | ||
ed396e68 BS |
2275 | /* Free up the space allocated by allocate_reg_info. */ |
2276 | void | |
0c20a65f | 2277 | free_reg_info (void) |
ed396e68 BS |
2278 | { |
2279 | if (reg_n_info) | |
2280 | { | |
2281 | struct reg_info_data *reg_data; | |
2282 | struct reg_info_data *reg_next; | |
2283 | ||
1935e8a8 | 2284 | VEC_free (reg_info_p, heap, reg_n_info); |
ed396e68 BS |
2285 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) |
2286 | { | |
2287 | reg_next = reg_data->next; | |
8e2e89f7 | 2288 | free ((char *) reg_data); |
ed396e68 BS |
2289 | } |
2290 | ||
9ffc5a70 | 2291 | free (reg_pref_buffer); |
f4f4d0f8 KH |
2292 | reg_pref_buffer = (struct reg_pref *) 0; |
2293 | reg_info_head = (struct reg_info_data *) 0; | |
2294 | renumber = (short *) 0; | |
ed396e68 BS |
2295 | } |
2296 | regno_allocated = 0; | |
2297 | reg_n_max = 0; | |
2298 | } | |
54dac99e RK |
2299 | \f |
2300 | /* This is the `regscan' pass of the compiler, run just before cse | |
2301 | and again just before loop. | |
2302 | ||
2303 | It finds the first and last use of each pseudo-register | |
2304 | and records them in the vectors regno_first_uid, regno_last_uid | |
2305 | and counts the number of sets in the vector reg_n_sets. | |
2306 | ||
2307 | REPEAT is nonzero the second time this is called. */ | |
2308 | ||
54dac99e | 2309 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2310 | Always at least 3, since the combiner could put that many together |
79b9ec0d RK |
2311 | and we want this to remain correct for all the remaining passes. |
2312 | This corresponds to the maximum number of times note_stores will call | |
2313 | a function for any insn. */ | |
54dac99e RK |
2314 | |
2315 | int max_parallel; | |
2316 | ||
a6a2274a | 2317 | /* Used as a temporary to record the largest number of registers in |
79b9ec0d RK |
2318 | PARALLEL in a SET_DEST. This is added to max_parallel. */ |
2319 | ||
2320 | static int max_set_parallel; | |
2321 | ||
54dac99e | 2322 | void |
c80a0f26 | 2323 | reg_scan (rtx f, unsigned int nregs) |
54dac99e | 2324 | { |
b3694847 | 2325 | rtx insn; |
54dac99e | 2326 | |
28cb2b14 RS |
2327 | timevar_push (TV_REG_SCAN); |
2328 | ||
39379e67 | 2329 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e | 2330 | max_parallel = 3; |
79b9ec0d | 2331 | max_set_parallel = 0; |
54dac99e RK |
2332 | |
2333 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
28cb2b14 | 2334 | if (INSN_P (insn)) |
54dac99e | 2335 | { |
28cb2b14 RS |
2336 | rtx pat = PATTERN (insn); |
2337 | if (GET_CODE (pat) == PARALLEL | |
2338 | && XVECLEN (pat, 0) > max_parallel) | |
2339 | max_parallel = XVECLEN (pat, 0); | |
3c491cab | 2340 | reg_scan_mark_refs (pat, insn, 0); |
01565a55 RK |
2341 | |
2342 | if (REG_NOTES (insn)) | |
3c491cab | 2343 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1); |
f903b91f | 2344 | } |
79b9ec0d RK |
2345 | |
2346 | max_parallel += max_set_parallel; | |
0d446150 JH |
2347 | |
2348 | timevar_pop (TV_REG_SCAN); | |
f903b91f DM |
2349 | } |
2350 | ||
1ebecb64 | 2351 | /* X is the expression to scan. INSN is the insn it appears in. |
3c491cab | 2352 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ |
1ebecb64 | 2353 | |
08d95f91 | 2354 | static void |
3c491cab | 2355 | reg_scan_mark_refs (rtx x, rtx insn, int note_flag) |
54dac99e | 2356 | { |
b3694847 SS |
2357 | enum rtx_code code; |
2358 | rtx dest; | |
2359 | rtx note; | |
54dac99e | 2360 | |
ed8d2920 MM |
2361 | if (!x) |
2362 | return; | |
fa23c636 | 2363 | code = GET_CODE (x); |
54dac99e RK |
2364 | switch (code) |
2365 | { | |
54dac99e | 2366 | case CONST: |
185ebd6c | 2367 | case CONST_INT: |
54dac99e | 2368 | case CONST_DOUBLE: |
69ef87e2 | 2369 | case CONST_VECTOR: |
54dac99e RK |
2370 | case CC0: |
2371 | case PC: | |
2372 | case SYMBOL_REF: | |
2373 | case LABEL_REF: | |
2374 | case ADDR_VEC: | |
2375 | case ADDR_DIFF_VEC: | |
2376 | return; | |
2377 | ||
2378 | case REG: | |
2379 | { | |
770ae6cc | 2380 | unsigned int regno = REGNO (x); |
54dac99e | 2381 | |
3c491cab KH |
2382 | if (!note_flag) |
2383 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2384 | if (REGNO_FIRST_UID (regno) == 0) | |
2385 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
54dac99e RK |
2386 | } |
2387 | break; | |
2388 | ||
01565a55 | 2389 | case EXPR_LIST: |
7b18c3db | 2390 | if (XEXP (x, 0)) |
3c491cab | 2391 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); |
01565a55 | 2392 | if (XEXP (x, 1)) |
3c491cab | 2393 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); |
01565a55 RK |
2394 | break; |
2395 | ||
2396 | case INSN_LIST: | |
2397 | if (XEXP (x, 1)) | |
3c491cab | 2398 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); |
01565a55 RK |
2399 | break; |
2400 | ||
ed8d2920 MM |
2401 | case CLOBBER: |
2402 | { | |
2403 | rtx reg = XEXP (x, 0); | |
3c491cab | 2404 | if (REG_P (reg)) |
ed8d2920 MM |
2405 | { |
2406 | REG_N_SETS (REGNO (reg))++; | |
2407 | REG_N_REFS (REGNO (reg))++; | |
2408 | } | |
3c0cb5de | 2409 | else if (MEM_P (reg)) |
3c491cab | 2410 | reg_scan_mark_refs (XEXP (reg, 0), insn, note_flag); |
ed8d2920 MM |
2411 | } |
2412 | break; | |
2413 | ||
54dac99e RK |
2414 | case SET: |
2415 | /* Count a set of the destination if it is a register. */ | |
2416 | for (dest = SET_DEST (x); | |
2417 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2418 | || GET_CODE (dest) == ZERO_EXTEND; | |
2419 | dest = XEXP (dest, 0)) | |
2420 | ; | |
2421 | ||
79b9ec0d RK |
2422 | /* For a PARALLEL, record the number of things (less the usual one for a |
2423 | SET) that are set. */ | |
2424 | if (GET_CODE (dest) == PARALLEL) | |
2425 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2426 | ||
3c491cab | 2427 | if (REG_P (dest)) |
b2d57793 DB |
2428 | { |
2429 | REG_N_SETS (REGNO (dest))++; | |
2430 | REG_N_REFS (REGNO (dest))++; | |
2431 | } | |
54dac99e | 2432 | |
be8dcd74 RK |
2433 | /* If this is setting a pseudo from another pseudo or the sum of a |
2434 | pseudo and a constant integer and the other pseudo is known to be | |
2435 | a pointer, set the destination to be a pointer as well. | |
2436 | ||
2437 | Likewise if it is setting the destination from an address or from a | |
2438 | value equivalent to an address or to the sum of an address and | |
2439 | something else. | |
a6a2274a | 2440 | |
be8dcd74 RK |
2441 | But don't do any of this if the pseudo corresponds to a user |
2442 | variable since it should have already been set as a pointer based | |
2443 | on the type. */ | |
2444 | ||
f8cfc6aa | 2445 | if (REG_P (SET_DEST (x)) |
be8dcd74 | 2446 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER |
64d3b4ca JL |
2447 | /* If the destination pseudo is set more than once, then other |
2448 | sets might not be to a pointer value (consider access to a | |
d55d8fc7 | 2449 | union in two threads of control in the presence of global |
3502dc9c | 2450 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2451 | pseudo if this is the only set of that pseudo. */ |
2452 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2453 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2454 | && ! REG_POINTER (SET_DEST (x)) |
f8cfc6aa | 2455 | && ((REG_P (SET_SRC (x)) |
3502dc9c | 2456 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2457 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2458 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2459 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
f8cfc6aa | 2460 | && REG_P (XEXP (SET_SRC (x), 0)) |
3502dc9c | 2461 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2462 | || GET_CODE (SET_SRC (x)) == CONST |
2463 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2464 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2465 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2466 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2467 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2468 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2469 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2470 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2471 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2472 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2473 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2474 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2475 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2476 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2477 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2478 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2479 | |
0d4903b8 | 2480 | /* If this is setting a register from a register or from a simple |
a560d4d4 | 2481 | conversion of a register, propagate REG_EXPR. */ |
f8cfc6aa | 2482 | if (REG_P (dest)) |
0d4903b8 RK |
2483 | { |
2484 | rtx src = SET_SRC (x); | |
2485 | ||
2486 | while (GET_CODE (src) == SIGN_EXTEND | |
2487 | || GET_CODE (src) == ZERO_EXTEND | |
2488 | || GET_CODE (src) == TRUNCATE | |
2489 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2490 | src = XEXP (src, 0); | |
2491 | ||
a560d4d4 JH |
2492 | if (!REG_ATTRS (dest) && REG_P (src)) |
2493 | REG_ATTRS (dest) = REG_ATTRS (src); | |
3c0cb5de | 2494 | if (!REG_ATTRS (dest) && MEM_P (src)) |
a560d4d4 | 2495 | set_reg_attrs_from_mem (dest, src); |
0d4903b8 RK |
2496 | } |
2497 | ||
0f41302f | 2498 | /* ... fall through ... */ |
54dac99e RK |
2499 | |
2500 | default: | |
2501 | { | |
b3694847 SS |
2502 | const char *fmt = GET_RTX_FORMAT (code); |
2503 | int i; | |
54dac99e RK |
2504 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2505 | { | |
2506 | if (fmt[i] == 'e') | |
3c491cab | 2507 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag); |
54dac99e RK |
2508 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2509 | { | |
b3694847 | 2510 | int j; |
54dac99e | 2511 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
3c491cab | 2512 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); |
54dac99e RK |
2513 | } |
2514 | } | |
2515 | } | |
2516 | } | |
2517 | } | |
2518 | \f | |
2519 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2520 | is also in C2. */ | |
2521 | ||
2522 | int | |
0c20a65f | 2523 | reg_class_subset_p (enum reg_class c1, enum reg_class c2) |
54dac99e RK |
2524 | { |
2525 | if (c1 == c2) return 1; | |
2526 | ||
2527 | if (c2 == ALL_REGS) | |
2528 | win: | |
2529 | return 1; | |
8e2e89f7 KH |
2530 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], |
2531 | reg_class_contents[(int) c2], | |
54dac99e RK |
2532 | win); |
2533 | return 0; | |
2534 | } | |
2535 | ||
2536 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2537 | ||
2538 | int | |
0c20a65f | 2539 | reg_classes_intersect_p (enum reg_class c1, enum reg_class c2) |
54dac99e | 2540 | { |
49a27995 | 2541 | HARD_REG_SET c; |
54dac99e RK |
2542 | |
2543 | if (c1 == c2) return 1; | |
2544 | ||
2545 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2546 | return 1; | |
2547 | ||
2548 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2549 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2550 | ||
2551 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2552 | return 1; | |
2553 | ||
2554 | lose: | |
2555 | return 0; | |
2556 | } | |
2557 | ||
cff9f8d5 | 2558 | #ifdef CANNOT_CHANGE_MODE_CLASS |
41bf2a8b RH |
2559 | |
2560 | struct subregs_of_mode_node | |
2561 | { | |
2562 | unsigned int block; | |
2563 | unsigned char modes[MAX_MACHINE_MODE]; | |
2564 | }; | |
2565 | ||
2566 | static htab_t subregs_of_mode; | |
2567 | ||
2568 | static hashval_t | |
2569 | som_hash (const void *x) | |
2570 | { | |
2571 | const struct subregs_of_mode_node *a = x; | |
2572 | return a->block; | |
2573 | } | |
2574 | ||
2575 | static int | |
2576 | som_eq (const void *x, const void *y) | |
2577 | { | |
2578 | const struct subregs_of_mode_node *a = x; | |
2579 | const struct subregs_of_mode_node *b = y; | |
2580 | return a->block == b->block; | |
2581 | } | |
2582 | ||
2583 | void | |
2584 | init_subregs_of_mode (void) | |
2585 | { | |
2586 | if (subregs_of_mode) | |
2587 | htab_empty (subregs_of_mode); | |
2588 | else | |
2589 | subregs_of_mode = htab_create (100, som_hash, som_eq, free); | |
2590 | } | |
2591 | ||
2592 | void | |
2593 | record_subregs_of_mode (rtx subreg) | |
2594 | { | |
2595 | struct subregs_of_mode_node dummy, *node; | |
2596 | enum machine_mode mode; | |
2597 | unsigned int regno; | |
2598 | void **slot; | |
2599 | ||
2600 | if (!REG_P (SUBREG_REG (subreg))) | |
2601 | return; | |
2602 | ||
2603 | regno = REGNO (SUBREG_REG (subreg)); | |
2604 | mode = GET_MODE (subreg); | |
2605 | ||
2606 | if (regno < FIRST_PSEUDO_REGISTER) | |
2607 | return; | |
2608 | ||
2609 | dummy.block = regno & -8; | |
2610 | slot = htab_find_slot_with_hash (subregs_of_mode, &dummy, | |
2611 | dummy.block, INSERT); | |
2612 | node = *slot; | |
2613 | if (node == NULL) | |
2614 | { | |
5ed6ace5 | 2615 | node = XCNEW (struct subregs_of_mode_node); |
41bf2a8b RH |
2616 | node->block = regno & -8; |
2617 | *slot = node; | |
2618 | } | |
2619 | ||
2620 | node->modes[mode] |= 1 << (regno & 7); | |
2621 | } | |
2622 | ||
cff9f8d5 AH |
2623 | /* Set bits in *USED which correspond to registers which can't change |
2624 | their mode from FROM to any mode in which REGNO was encountered. */ | |
2625 | ||
2626 | void | |
0c20a65f AJ |
2627 | cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from, |
2628 | unsigned int regno) | |
cff9f8d5 | 2629 | { |
41bf2a8b | 2630 | struct subregs_of_mode_node dummy, *node; |
cff9f8d5 | 2631 | enum machine_mode to; |
41bf2a8b RH |
2632 | unsigned char mask; |
2633 | unsigned int i; | |
cff9f8d5 | 2634 | |
41bf2a8b RH |
2635 | dummy.block = regno & -8; |
2636 | node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); | |
2637 | if (node == NULL) | |
2638 | return; | |
2639 | ||
2640 | mask = 1 << (regno & 7); | |
2641 | for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) | |
2642 | if (node->modes[to] & mask) | |
2643 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2644 | if (!TEST_HARD_REG_BIT (*used, i) | |
2645 | && REG_CANNOT_CHANGE_MODE_P (i, from, to)) | |
2646 | SET_HARD_REG_BIT (*used, i); | |
cff9f8d5 AH |
2647 | } |
2648 | ||
2649 | /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM | |
2650 | mode. */ | |
2651 | ||
2652 | bool | |
0c20a65f | 2653 | invalid_mode_change_p (unsigned int regno, enum reg_class class, |
41bf2a8b | 2654 | enum machine_mode from) |
cff9f8d5 | 2655 | { |
41bf2a8b RH |
2656 | struct subregs_of_mode_node dummy, *node; |
2657 | enum machine_mode to; | |
2658 | unsigned char mask; | |
2659 | ||
2660 | dummy.block = regno & -8; | |
2661 | node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); | |
2662 | if (node == NULL) | |
2663 | return false; | |
2664 | ||
2665 | mask = 1 << (regno & 7); | |
2666 | for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) | |
2667 | if (node->modes[to] & mask) | |
2668 | if (CANNOT_CHANGE_MODE_CLASS (from, to, class)) | |
2669 | return true; | |
2670 | ||
2671 | return false; | |
cff9f8d5 AH |
2672 | } |
2673 | #endif /* CANNOT_CHANGE_MODE_CLASS */ | |
2674 | ||
e2500fed | 2675 | #include "gt-regclass.h" |