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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
73b76448 | 2 | Copyright (C) 1987, 88, 91-96, 1997 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
e9a25f70 | 27 | #include <stdio.h> |
54dac99e RK |
28 | #include "rtl.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "flags.h" | |
31 | #include "basic-block.h" | |
32 | #include "regs.h" | |
33 | #include "insn-config.h" | |
34 | #include "recog.h" | |
e4600702 RK |
35 | #include "reload.h" |
36 | #include "real.h" | |
ca695ac9 | 37 | #include "bytecode.h" |
54dac99e RK |
38 | |
39 | #ifndef REGISTER_MOVE_COST | |
40 | #define REGISTER_MOVE_COST(x, y) 2 | |
41 | #endif | |
42 | ||
43 | #ifndef MEMORY_MOVE_COST | |
e4600702 | 44 | #define MEMORY_MOVE_COST(x) 4 |
54dac99e | 45 | #endif |
533d0835 RK |
46 | |
47 | /* If we have auto-increment or auto-decrement and we can have secondary | |
48 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 49 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
50 | |
51 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 52 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
53 | #define FORBIDDEN_INC_DEC_CLASSES |
54 | #endif | |
55 | #endif | |
54dac99e RK |
56 | \f |
57 | /* Register tables used by many passes. */ | |
58 | ||
59 | /* Indexed by hard register number, contains 1 for registers | |
60 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
61 | These are the registers that cannot be used to allocate | |
62 | a pseudo reg whose life does not cross calls. */ | |
63 | ||
64 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
65 | ||
66 | /* Same info as a HARD_REG_SET. */ | |
67 | ||
68 | HARD_REG_SET fixed_reg_set; | |
69 | ||
70 | /* Data for initializing the above. */ | |
71 | ||
72 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
73 | ||
74 | /* Indexed by hard register number, contains 1 for registers | |
75 | that are fixed use or are clobbered by function calls. | |
76 | These are the registers that cannot be used to allocate | |
77 | a pseudo reg whose life crosses calls. */ | |
78 | ||
79 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
80 | ||
81 | /* Same info as a HARD_REG_SET. */ | |
82 | ||
83 | HARD_REG_SET call_used_reg_set; | |
84 | ||
6cad67d2 JL |
85 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
86 | HARD_REG_SET losing_caller_save_reg_set; | |
87 | ||
54dac99e RK |
88 | /* Data for initializing the above. */ |
89 | ||
90 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
91 | ||
92 | /* Indexed by hard register number, contains 1 for registers that are | |
93 | fixed use -- i.e. in fixed_regs -- or a function value return register | |
94 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the | |
95 | registers that cannot hold quantities across calls even if we are | |
96 | willing to save and restore them. */ | |
97 | ||
98 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
99 | ||
100 | /* The same info as a HARD_REG_SET. */ | |
101 | ||
102 | HARD_REG_SET call_fixed_reg_set; | |
103 | ||
104 | /* Number of non-fixed registers. */ | |
105 | ||
106 | int n_non_fixed_regs; | |
107 | ||
108 | /* Indexed by hard register number, contains 1 for registers | |
109 | that are being used for global register decls. | |
110 | These must be exempt from ordinary flow analysis | |
111 | and are also considered fixed. */ | |
112 | ||
113 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
114 | ||
115 | /* Table of register numbers in the order in which to try to use them. */ | |
116 | #ifdef REG_ALLOC_ORDER | |
117 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
118 | #endif | |
119 | ||
120 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
121 | ||
2e0e2b76 CH |
122 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
123 | ||
089e575b RS |
124 | /* The same information, but as an array of unsigned ints. We copy from |
125 | these unsigned ints to the table above. We do this so the tm.h files | |
126 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
127 | |
128 | #define N_REG_INTS \ | |
129 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
130 | ||
089e575b | 131 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 132 | = REG_CLASS_CONTENTS; |
54dac99e RK |
133 | |
134 | /* For each reg class, number of regs it contains. */ | |
135 | ||
136 | int reg_class_size[N_REG_CLASSES]; | |
137 | ||
138 | /* For each reg class, table listing all the containing classes. */ | |
139 | ||
140 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
141 | ||
142 | /* For each reg class, table listing all the classes contained in it. */ | |
143 | ||
144 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
145 | ||
146 | /* For each pair of reg classes, | |
147 | a largest reg class contained in their union. */ | |
148 | ||
149 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
150 | ||
151 | /* For each pair of reg classes, | |
152 | the smallest reg class containing their union. */ | |
153 | ||
154 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
155 | ||
d05c8ee7 RS |
156 | /* Array containing all of the register names */ |
157 | ||
158 | char *reg_names[] = REGISTER_NAMES; | |
159 | ||
ca4aac00 DE |
160 | /* For each hard register, the widest mode object that it can contain. |
161 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
162 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
163 | register. */ | |
164 | ||
165 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
166 | ||
e4600702 RK |
167 | /* Maximum cost of moving from a register in one class to a register in |
168 | another class. Based on REGISTER_MOVE_COST. */ | |
169 | ||
170 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
171 | ||
172 | /* Similar, but here we don't have to move if the first index is a subset | |
173 | of the second so in that case the cost is zero. */ | |
174 | ||
175 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
176 | ||
533d0835 RK |
177 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
178 | ||
179 | /* These are the classes that regs which are auto-incremented or decremented | |
180 | cannot be put in. */ | |
181 | ||
182 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
183 | ||
184 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
185 | context. */ | |
186 | ||
187 | static char *in_inc_dec; | |
188 | ||
5fcb671c | 189 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 190 | |
54dac99e RK |
191 | /* Function called only once to initialize the above data on reg usage. |
192 | Once this is done, various switches may override. */ | |
193 | ||
194 | void | |
195 | init_reg_sets () | |
196 | { | |
197 | register int i, j; | |
198 | ||
2e0e2b76 CH |
199 | /* First copy the register information from the initial int form into |
200 | the regsets. */ | |
201 | ||
202 | for (i = 0; i < N_REG_CLASSES; i++) | |
203 | { | |
204 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
205 | ||
206 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
207 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 208 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
209 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
210 | } | |
211 | ||
54dac99e RK |
212 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
213 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
214 | bzero (global_regs, sizeof global_regs); | |
215 | ||
216 | /* Compute number of hard regs in each class. */ | |
217 | ||
4c9a05bc | 218 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
219 | for (i = 0; i < N_REG_CLASSES; i++) |
220 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
221 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
222 | reg_class_size[i]++; | |
223 | ||
224 | /* Initialize the table of subunions. | |
225 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
226 | that is contained in the union of classes I and J. */ | |
227 | ||
228 | for (i = 0; i < N_REG_CLASSES; i++) | |
229 | { | |
230 | for (j = 0; j < N_REG_CLASSES; j++) | |
231 | { | |
232 | #ifdef HARD_REG_SET | |
233 | register /* Declare it register if it's a scalar. */ | |
234 | #endif | |
235 | HARD_REG_SET c; | |
236 | register int k; | |
237 | ||
238 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
239 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
240 | for (k = 0; k < N_REG_CLASSES; k++) | |
241 | { | |
242 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
243 | subclass1); | |
244 | continue; | |
245 | ||
246 | subclass1: | |
247 | /* keep the largest subclass */ /* SPEE 900308 */ | |
248 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
249 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
250 | subclass2); | |
251 | reg_class_subunion[i][j] = (enum reg_class) k; | |
252 | subclass2: | |
253 | ; | |
254 | } | |
255 | } | |
256 | } | |
257 | ||
258 | /* Initialize the table of superunions. | |
259 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
260 | containing the union of classes I and J. */ | |
261 | ||
262 | for (i = 0; i < N_REG_CLASSES; i++) | |
263 | { | |
264 | for (j = 0; j < N_REG_CLASSES; j++) | |
265 | { | |
266 | #ifdef HARD_REG_SET | |
267 | register /* Declare it register if it's a scalar. */ | |
268 | #endif | |
269 | HARD_REG_SET c; | |
270 | register int k; | |
271 | ||
272 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
273 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
274 | for (k = 0; k < N_REG_CLASSES; k++) | |
275 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
276 | ||
277 | superclass: | |
278 | reg_class_superunion[i][j] = (enum reg_class) k; | |
279 | } | |
280 | } | |
281 | ||
282 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
283 | First clear the whole table, then add the elements as they are found. */ | |
284 | ||
285 | for (i = 0; i < N_REG_CLASSES; i++) | |
286 | { | |
287 | for (j = 0; j < N_REG_CLASSES; j++) | |
288 | { | |
289 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
290 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
291 | } | |
292 | } | |
293 | ||
294 | for (i = 0; i < N_REG_CLASSES; i++) | |
295 | { | |
296 | if (i == (int) NO_REGS) | |
297 | continue; | |
298 | ||
299 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
300 | { | |
301 | enum reg_class *p; | |
302 | ||
303 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
304 | subclass); | |
305 | continue; | |
306 | subclass: | |
307 | /* Reg class I is a subclass of J. | |
308 | Add J to the table of superclasses of I. */ | |
309 | p = ®_class_superclasses[i][0]; | |
310 | while (*p != LIM_REG_CLASSES) p++; | |
311 | *p = (enum reg_class) j; | |
312 | /* Add I to the table of superclasses of J. */ | |
313 | p = ®_class_subclasses[j][0]; | |
314 | while (*p != LIM_REG_CLASSES) p++; | |
315 | *p = (enum reg_class) i; | |
316 | } | |
317 | } | |
e4600702 RK |
318 | |
319 | /* Initialize the move cost table. Find every subset of each class | |
320 | and take the maximum cost of moving any subset to any other. */ | |
321 | ||
322 | for (i = 0; i < N_REG_CLASSES; i++) | |
323 | for (j = 0; j < N_REG_CLASSES; j++) | |
324 | { | |
325 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
326 | enum reg_class *p1, *p2; | |
327 | ||
328 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
329 | if (*p2 != i) | |
330 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
331 | ||
332 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
333 | { | |
334 | if (*p1 != j) | |
335 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
336 | ||
337 | for (p2 = ®_class_subclasses[j][0]; | |
338 | *p2 != LIM_REG_CLASSES; p2++) | |
339 | if (*p1 != *p2) | |
340 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
341 | } | |
342 | ||
343 | move_cost[i][j] = cost; | |
344 | ||
345 | if (reg_class_subset_p (i, j)) | |
346 | cost = 0; | |
347 | ||
348 | may_move_cost[i][j] = cost; | |
349 | } | |
73b76448 RK |
350 | |
351 | /* Do any additional initialization regsets may need */ | |
352 | INIT_ONCE_REG_SET (); | |
54dac99e RK |
353 | } |
354 | ||
355 | /* After switches have been processed, which perhaps alter | |
356 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
357 | ||
c27c5281 | 358 | static void |
54dac99e RK |
359 | init_reg_sets_1 () |
360 | { | |
361 | register int i; | |
362 | ||
363 | /* This macro allows the fixed or call-used registers | |
364 | to depend on target flags. */ | |
365 | ||
366 | #ifdef CONDITIONAL_REGISTER_USAGE | |
367 | CONDITIONAL_REGISTER_USAGE; | |
368 | #endif | |
369 | ||
54dac99e RK |
370 | /* Initialize "constant" tables. */ |
371 | ||
372 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
373 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
374 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
375 | ||
376 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
377 | |
378 | n_non_fixed_regs = 0; | |
379 | ||
380 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
381 | { | |
54dac99e RK |
382 | if (fixed_regs[i]) |
383 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
384 | else | |
385 | n_non_fixed_regs++; | |
386 | ||
387 | if (call_used_regs[i]) | |
388 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
389 | if (call_fixed_regs[i]) | |
390 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
391 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
392 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 393 | } |
c27c5281 DE |
394 | } |
395 | ||
396 | /* Compute the table of register modes. | |
397 | These values are used to record death information for individual registers | |
398 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 399 | |
c27c5281 DE |
400 | static void |
401 | init_reg_modes () | |
402 | { | |
403 | register int i; | |
ca4aac00 DE |
404 | |
405 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
406 | { |
407 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
408 | ||
066c2fea | 409 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
410 | ??? One situation in which we need to do this is on the mips where |
411 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
412 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 413 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 414 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 415 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 416 | } |
ca4aac00 DE |
417 | } |
418 | ||
c27c5281 DE |
419 | /* Finish initializing the register sets and |
420 | initialize the register modes. */ | |
421 | ||
422 | void | |
423 | init_regs () | |
424 | { | |
425 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
426 | until after register usage was specified. */ | |
427 | if (!output_bytecode) | |
428 | init_reg_sets_1 (); | |
429 | ||
430 | init_reg_modes (); | |
431 | } | |
432 | ||
ca4aac00 DE |
433 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
434 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
435 | ||
436 | enum machine_mode | |
437 | choose_hard_reg_mode (regno, nregs) | |
438 | int regno; | |
439 | int nregs; | |
440 | { | |
441 | enum machine_mode found_mode = VOIDmode, mode; | |
442 | ||
443 | /* We first look for the largest integer mode that can be validly | |
444 | held in REGNO. If none, we look for the largest floating-point mode. | |
445 | If we still didn't find a valid mode, try CCmode. */ | |
446 | ||
447 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
448 | mode != VOIDmode; | |
449 | mode = GET_MODE_WIDER_MODE (mode)) | |
450 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
451 | && HARD_REGNO_MODE_OK (regno, mode)) | |
452 | found_mode = mode; | |
453 | ||
454 | if (found_mode != VOIDmode) | |
455 | return found_mode; | |
456 | ||
457 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
458 | mode != VOIDmode; | |
459 | mode = GET_MODE_WIDER_MODE (mode)) | |
460 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
461 | && HARD_REGNO_MODE_OK (regno, mode)) | |
462 | found_mode = mode; | |
463 | ||
464 | if (found_mode != VOIDmode) | |
465 | return found_mode; | |
466 | ||
467 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
468 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
469 | return CCmode; | |
470 | ||
471 | /* We can't find a mode valid for this register. */ | |
472 | return VOIDmode; | |
54dac99e RK |
473 | } |
474 | ||
475 | /* Specify the usage characteristics of the register named NAME. | |
476 | It should be a fixed register if FIXED and a | |
477 | call-used register if CALL_USED. */ | |
478 | ||
479 | void | |
480 | fix_register (name, fixed, call_used) | |
481 | char *name; | |
482 | int fixed, call_used; | |
483 | { | |
484 | int i; | |
485 | ||
ca695ac9 JB |
486 | if (output_bytecode) |
487 | { | |
488 | warning ("request to mark `%s' as %s ignored by bytecode compiler", | |
489 | name, call_used ? "call-used" : "fixed"); | |
490 | return; | |
491 | } | |
492 | ||
54dac99e RK |
493 | /* Decode the name and update the primary form of |
494 | the register info. */ | |
495 | ||
e5c90c23 TW |
496 | if ((i = decode_reg_name (name)) >= 0) |
497 | { | |
498 | fixed_regs[i] = fixed; | |
499 | call_used_regs[i] = call_used; | |
500 | } | |
501 | else | |
54dac99e RK |
502 | { |
503 | warning ("unknown register name: %s", name); | |
54dac99e RK |
504 | } |
505 | } | |
614f68e2 RK |
506 | |
507 | /* Mark register number I as global. */ | |
508 | ||
509 | void | |
510 | globalize_reg (i) | |
511 | int i; | |
512 | { | |
513 | if (global_regs[i]) | |
514 | { | |
515 | warning ("register used for two global register variables"); | |
516 | return; | |
517 | } | |
518 | ||
519 | if (call_used_regs[i] && ! fixed_regs[i]) | |
520 | warning ("call-clobbered register used for global register variable"); | |
521 | ||
522 | global_regs[i] = 1; | |
523 | ||
524 | /* If already fixed, nothing else to do. */ | |
525 | if (fixed_regs[i]) | |
526 | return; | |
527 | ||
528 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
529 | n_non_fixed_regs--; | |
530 | ||
531 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
532 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
533 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
534 | } | |
54dac99e RK |
535 | \f |
536 | /* Now the data and code for the `regclass' pass, which happens | |
537 | just before local-alloc. */ | |
538 | ||
e4600702 RK |
539 | /* The `costs' struct records the cost of using a hard register of each class |
540 | and of using memory for each pseudo. We use this data to set up | |
541 | register class preferences. */ | |
54dac99e | 542 | |
e4600702 | 543 | struct costs |
54dac99e | 544 | { |
e4600702 RK |
545 | int cost[N_REG_CLASSES]; |
546 | int mem_cost; | |
54dac99e RK |
547 | }; |
548 | ||
e4600702 RK |
549 | /* Record the cost of each class for each pseudo. */ |
550 | ||
551 | static struct costs *costs; | |
552 | ||
553 | /* Record the same data by operand number, accumulated for each alternative | |
554 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
555 | alternative. */ | |
556 | ||
557 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
558 | |
559 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
560 | This is available after `regclass' is run. */ | |
561 | ||
562 | static char *prefclass; | |
563 | ||
54d23420 RK |
564 | /* altclass[R] is a register class that we should use for allocating |
565 | pseudo number R if no register in the preferred class is available. | |
566 | If no register in this class is available, memory is preferred. | |
567 | ||
568 | It might appear to be more general to have a bitmask of classes here, | |
569 | but since it is recommended that there be a class corresponding to the | |
570 | union of most major pair of classes, that generality is not required. | |
571 | ||
54dac99e RK |
572 | This is available after `regclass' is run. */ |
573 | ||
54d23420 | 574 | static char *altclass; |
54dac99e | 575 | |
54d23420 | 576 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
577 | |
578 | static int loop_depth; | |
579 | ||
54d23420 RK |
580 | /* Account for the fact that insns within a loop are executed very commonly, |
581 | but don't keep doing this as loops go too deep. */ | |
582 | ||
583 | static int loop_cost; | |
584 | ||
08d95f91 RK |
585 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
586 | char **, rtx)); | |
587 | static int copy_cost PROTO((rtx, enum machine_mode, | |
588 | enum reg_class, int)); | |
589 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
590 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
591 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
592 | #endif | |
08d95f91 | 593 | static void reg_scan_mark_refs PROTO((rtx, rtx, int)); |
54dac99e RK |
594 | |
595 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
596 | This function is sometimes called before the info has been computed. | |
597 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
598 | ||
599 | enum reg_class | |
600 | reg_preferred_class (regno) | |
601 | int regno; | |
602 | { | |
603 | if (prefclass == 0) | |
604 | return GENERAL_REGS; | |
605 | return (enum reg_class) prefclass[regno]; | |
606 | } | |
607 | ||
e4600702 RK |
608 | enum reg_class |
609 | reg_alternate_class (regno) | |
54dac99e RK |
610 | { |
611 | if (prefclass == 0) | |
e4600702 RK |
612 | return ALL_REGS; |
613 | ||
614 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
615 | } |
616 | ||
617 | /* This prevents dump_flow_info from losing if called | |
618 | before regclass is run. */ | |
619 | ||
620 | void | |
621 | regclass_init () | |
622 | { | |
623 | prefclass = 0; | |
624 | } | |
625 | \f | |
626 | /* This is a pass of the compiler that scans all instructions | |
627 | and calculates the preferred class for each pseudo-register. | |
628 | This information can be accessed later by calling `reg_preferred_class'. | |
629 | This pass comes just before local register allocation. */ | |
630 | ||
631 | void | |
632 | regclass (f, nregs) | |
633 | rtx f; | |
634 | int nregs; | |
635 | { | |
636 | #ifdef REGISTER_CONSTRAINTS | |
637 | register rtx insn; | |
e4600702 RK |
638 | register int i, j; |
639 | struct costs init_cost; | |
640 | rtx set; | |
641 | int pass; | |
54dac99e RK |
642 | |
643 | init_recog (); | |
644 | ||
533d0835 RK |
645 | costs = (struct costs *) alloca (nregs * sizeof (struct costs)); |
646 | ||
647 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
648 | ||
649 | in_inc_dec = (char *) alloca (nregs); | |
650 | ||
651 | /* Initialize information about which register classes can be used for | |
652 | pseudos that are auto-incremented or auto-decremented. It would | |
653 | seem better to put this in init_reg_sets, but we need to be able | |
654 | to allocate rtx, which we can't do that early. */ | |
655 | ||
656 | for (i = 0; i < N_REG_CLASSES; i++) | |
657 | { | |
658 | rtx r = gen_rtx (REG, VOIDmode, 0); | |
659 | enum machine_mode m; | |
660 | ||
661 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
662 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
663 | { | |
664 | REGNO (r) = j; | |
665 | ||
666 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 667 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
668 | if (HARD_REGNO_MODE_OK (j, m)) |
669 | { | |
670 | PUT_MODE (r, m); | |
08d95f91 RK |
671 | |
672 | /* If a register is not directly suitable for an | |
673 | auto-increment or decrement addressing mode and | |
674 | requires secondary reloads, disallow its class from | |
675 | being used in such addresses. */ | |
676 | ||
677 | if ((0 | |
041d7180 JL |
678 | #ifdef SECONDARY_RELOAD_CLASS |
679 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
680 | != NO_REGS) | |
681 | #else | |
533d0835 | 682 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
683 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
684 | != NO_REGS) | |
533d0835 RK |
685 | #endif |
686 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
687 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
688 | != NO_REGS) | |
041d7180 | 689 | #endif |
533d0835 | 690 | #endif |
08d95f91 RK |
691 | ) |
692 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
693 | forbidden_inc_dec_class[i] = 1; |
694 | } | |
695 | } | |
696 | } | |
697 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
698 | ||
e4600702 RK |
699 | init_cost.mem_cost = 10000; |
700 | for (i = 0; i < N_REG_CLASSES; i++) | |
701 | init_cost.cost[i] = 10000; | |
54dac99e | 702 | |
e4600702 RK |
703 | /* Normally we scan the insns once and determine the best class to use for |
704 | each register. However, if -fexpensive_optimizations are on, we do so | |
705 | twice, the second time using the tentative best classes to guide the | |
706 | selection. */ | |
54dac99e | 707 | |
e4600702 RK |
708 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
709 | { | |
710 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 711 | |
4c9a05bc | 712 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 713 | |
533d0835 RK |
714 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
715 | bzero (in_inc_dec, nregs); | |
716 | #endif | |
717 | ||
e4600702 RK |
718 | loop_depth = 0, loop_cost = 1; |
719 | ||
720 | /* Scan the instructions and record each time it would | |
721 | save code to put a certain register in a certain class. */ | |
722 | ||
723 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 724 | { |
e4600702 RK |
725 | char *constraints[MAX_RECOG_OPERANDS]; |
726 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
727 | int nalternatives; | |
728 | int noperands; | |
729 | ||
730 | /* Show that an insn inside a loop is likely to be executed three | |
ac2a9454 | 731 | times more than insns outside a loop. This is much more aggressive |
e4600702 RK |
732 | than the assumptions made elsewhere and is being tried as an |
733 | experiment. */ | |
734 | ||
735 | if (GET_CODE (insn) == NOTE | |
736 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
737 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
738 | else if (GET_CODE (insn) == NOTE | |
739 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
740 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
741 | ||
742 | else if ((GET_CODE (insn) == INSN | |
743 | && GET_CODE (PATTERN (insn)) != USE | |
744 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
745 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) | |
746 | || (GET_CODE (insn) == JUMP_INSN | |
747 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
748 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
749 | || GET_CODE (insn) == CALL_INSN) | |
54dac99e | 750 | { |
e4600702 RK |
751 | if (GET_CODE (insn) == INSN |
752 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) | |
753 | { | |
37366632 | 754 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, |
e4600702 | 755 | constraints, modes); |
e5ed2155 TW |
756 | nalternatives = (noperands == 0 ? 0 |
757 | : n_occurrences (',', constraints[0]) + 1); | |
e4600702 RK |
758 | } |
759 | else | |
760 | { | |
761 | int insn_code_number = recog_memoized (insn); | |
762 | rtx note; | |
54dac99e | 763 | |
e4600702 RK |
764 | set = single_set (insn); |
765 | insn_extract (insn); | |
54dac99e | 766 | |
e4600702 RK |
767 | nalternatives = insn_n_alternatives[insn_code_number]; |
768 | noperands = insn_n_operands[insn_code_number]; | |
54dac99e | 769 | |
e4600702 RK |
770 | /* If this insn loads a parameter from its stack slot, then |
771 | it represents a savings, rather than a cost, if the | |
772 | parameter is stored in memory. Record this fact. */ | |
54dac99e | 773 | |
e4600702 RK |
774 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
775 | && GET_CODE (SET_SRC (set)) == MEM | |
37366632 RK |
776 | && (note = find_reg_note (insn, REG_EQUIV, |
777 | NULL_RTX)) != 0 | |
e4600702 RK |
778 | && GET_CODE (XEXP (note, 0)) == MEM) |
779 | { | |
780 | costs[REGNO (SET_DEST (set))].mem_cost | |
781 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set))) | |
782 | * loop_cost); | |
783 | record_address_regs (XEXP (SET_SRC (set), 0), | |
784 | BASE_REG_CLASS, loop_cost * 2); | |
785 | continue; | |
786 | } | |
787 | ||
788 | /* Improve handling of two-address insns such as | |
789 | (set X (ashift CONST Y)) where CONST must be made to | |
790 | match X. Change it into two insns: (set X CONST) | |
791 | (set X (ashift X Y)). If we left this for reloading, it | |
792 | would probably get three insns because X and Y might go | |
793 | in the same place. This prevents X and Y from receiving | |
794 | the same hard reg. | |
795 | ||
796 | We can only do this if the modes of operands 0 and 1 | |
797 | (which might not be the same) are tieable and we only need | |
798 | do this during our first pass. */ | |
799 | ||
800 | if (pass == 0 && optimize | |
801 | && noperands >= 3 | |
802 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
803 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
804 | && CONSTANT_P (recog_operand[1]) | |
805 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
806 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
807 | && GET_CODE (recog_operand[0]) == REG | |
808 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
809 | insn_operand_mode[insn_code_number][1])) | |
810 | { | |
811 | rtx previnsn = prev_real_insn (insn); | |
812 | rtx dest | |
813 | = gen_lowpart (insn_operand_mode[insn_code_number][1], | |
814 | recog_operand[0]); | |
815 | rtx newinsn | |
816 | = emit_insn_before (gen_move_insn (dest, | |
817 | recog_operand[1]), | |
818 | insn); | |
819 | ||
820 | /* If this insn was the start of a basic block, | |
61b01243 RS |
821 | include the new insn in that block. |
822 | We need not check for code_label here; | |
823 | while a basic block can start with a code_label, | |
824 | INSN could not be at the beginning of that block. */ | |
e4600702 RK |
825 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) |
826 | { | |
827 | int b; | |
828 | for (b = 0; b < n_basic_blocks; b++) | |
829 | if (insn == basic_block_head[b]) | |
830 | basic_block_head[b] = newinsn; | |
831 | } | |
832 | ||
0f41302f | 833 | /* This makes one more setting of new insns's dest. */ |
b1f21e0a | 834 | REG_N_SETS (REGNO (recog_operand[0]))++; |
e4600702 | 835 | |
20912ad0 RK |
836 | *recog_operand_loc[1] = recog_operand[0]; |
837 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
838 | if (recog_dup_num[i] == 1) | |
839 | *recog_dup_loc[i] = recog_operand[0]; | |
840 | ||
e4600702 RK |
841 | insn = PREV_INSN (newinsn); |
842 | continue; | |
843 | } | |
54dac99e | 844 | |
e4600702 RK |
845 | for (i = 0; i < noperands; i++) |
846 | { | |
847 | constraints[i] | |
848 | = insn_operand_constraint[insn_code_number][i]; | |
849 | modes[i] = insn_operand_mode[insn_code_number][i]; | |
850 | } | |
851 | } | |
54dac99e | 852 | |
e4600702 RK |
853 | /* If we get here, we are set up to record the costs of all the |
854 | operands for this insn. Start by initializing the costs. | |
855 | Then handle any address registers. Finally record the desired | |
856 | classes for any pseudos, doing it twice if some pair of | |
857 | operands are commutative. */ | |
858 | ||
859 | for (i = 0; i < noperands; i++) | |
54dac99e | 860 | { |
e4600702 RK |
861 | op_costs[i] = init_cost; |
862 | ||
863 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
864 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
865 | ||
866 | if (GET_CODE (recog_operand[i]) == MEM) | |
867 | record_address_regs (XEXP (recog_operand[i], 0), | |
868 | BASE_REG_CLASS, loop_cost * 2); | |
869 | else if (constraints[i][0] == 'p') | |
870 | record_address_regs (recog_operand[i], | |
871 | BASE_REG_CLASS, loop_cost * 2); | |
54dac99e | 872 | } |
e4600702 RK |
873 | |
874 | /* Check for commutative in a separate loop so everything will | |
cc4c133a RS |
875 | have been initialized. We must do this even if one operand |
876 | is a constant--see addsi3 in m68k.md. */ | |
54dac99e | 877 | |
e5ed2155 | 878 | for (i = 0; i < noperands - 1; i++) |
cc4c133a | 879 | if (constraints[i][0] == '%') |
e4600702 RK |
880 | { |
881 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
882 | int j; | |
883 | ||
884 | /* Handle commutative operands by swapping the constraints. | |
885 | We assume the modes are the same. */ | |
886 | ||
887 | for (j = 0; j < noperands; j++) | |
888 | xconstraints[j] = constraints[j]; | |
889 | ||
890 | xconstraints[i] = constraints[i+1]; | |
891 | xconstraints[i+1] = constraints[i]; | |
892 | record_reg_classes (nalternatives, noperands, | |
893 | recog_operand, modes, xconstraints, | |
54dac99e | 894 | insn); |
e4600702 | 895 | } |
54dac99e | 896 | |
e4600702 RK |
897 | record_reg_classes (nalternatives, noperands, recog_operand, |
898 | modes, constraints, insn); | |
54dac99e | 899 | |
e4600702 RK |
900 | /* Now add the cost for each operand to the total costs for |
901 | its register. */ | |
54dac99e | 902 | |
e4600702 RK |
903 | for (i = 0; i < noperands; i++) |
904 | if (GET_CODE (recog_operand[i]) == REG | |
905 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
906 | { | |
907 | int regno = REGNO (recog_operand[i]); | |
908 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
909 | ||
910 | p->mem_cost += q->mem_cost * loop_cost; | |
911 | for (j = 0; j < N_REG_CLASSES; j++) | |
912 | p->cost[j] += q->cost[j] * loop_cost; | |
913 | } | |
54dac99e RK |
914 | } |
915 | } | |
54dac99e | 916 | |
e4600702 RK |
917 | /* Now for each register look at how desirable each class is |
918 | and find which class is preferred. Store that in | |
919 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
920 | class any of whose registers is better than memory. */ | |
54dac99e | 921 | |
e4600702 RK |
922 | if (pass == 0) |
923 | { | |
924 | prefclass = (char *) oballoc (nregs); | |
925 | altclass = (char *) oballoc (nregs); | |
926 | } | |
54dac99e | 927 | |
e4600702 | 928 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 929 | { |
ca3c6eae | 930 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
931 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
932 | /* This is an enum reg_class, but we call it an int | |
933 | to save lots of casts. */ | |
934 | register int class; | |
935 | register struct costs *p = &costs[i]; | |
936 | ||
937 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 938 | { |
533d0835 RK |
939 | /* Ignore classes that are too small for this operand or |
940 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 941 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
942 | > reg_class_size[class] |
943 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
944 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
945 | #endif | |
946 | ) | |
e4600702 RK |
947 | ; |
948 | else if (p->cost[class] < best_cost) | |
949 | { | |
950 | best_cost = p->cost[class]; | |
951 | best = (enum reg_class) class; | |
952 | } | |
953 | else if (p->cost[class] == best_cost) | |
954 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 955 | } |
54dac99e | 956 | |
e4600702 RK |
957 | /* Record the alternate register class; i.e., a class for which |
958 | every register in it is better than using memory. If adding a | |
959 | class would make a smaller class (i.e., no union of just those | |
960 | classes exists), skip that class. The major unions of classes | |
961 | should be provided as a register class. Don't do this if we | |
962 | will be doing it again later. */ | |
963 | ||
964 | if (pass == 1 || ! flag_expensive_optimizations) | |
965 | for (class = 0; class < N_REG_CLASSES; class++) | |
966 | if (p->cost[class] < p->mem_cost | |
77edb222 | 967 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
968 | > reg_class_size[(int) alt]) |
969 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
970 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
971 | #endif | |
972 | ) | |
e4600702 RK |
973 | alt = reg_class_subunion[(int) alt][class]; |
974 | ||
975 | /* If we don't add any classes, nothing to try. */ | |
976 | if (alt == best) | |
995d54dd | 977 | alt = NO_REGS; |
e4600702 RK |
978 | |
979 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
980 | prefclass[i] = (int) best; | |
981 | altclass[i] = (int) alt; | |
982 | } | |
54dac99e RK |
983 | } |
984 | #endif /* REGISTER_CONSTRAINTS */ | |
985 | } | |
986 | \f | |
987 | #ifdef REGISTER_CONSTRAINTS | |
988 | ||
e4600702 RK |
989 | /* Record the cost of using memory or registers of various classes for |
990 | the operands in INSN. | |
54dac99e | 991 | |
e4600702 | 992 | N_ALTS is the number of alternatives. |
54dac99e | 993 | |
e4600702 RK |
994 | N_OPS is the number of operands. |
995 | ||
996 | OPS is an array of the operands. | |
997 | ||
998 | MODES are the modes of the operands, in case any are VOIDmode. | |
999 | ||
1000 | CONSTRAINTS are the constraints to use for the operands. This array | |
1001 | is modified by this procedure. | |
1002 | ||
1003 | This procedure works alternative by alternative. For each alternative | |
1004 | we assume that we will be able to allocate all pseudos to their ideal | |
1005 | register class and calculate the cost of using that alternative. Then | |
1006 | we compute for each operand that is a pseudo-register, the cost of | |
1007 | having the pseudo allocated to each register class and using it in that | |
1008 | alternative. To this cost is added the cost of the alternative. | |
1009 | ||
1010 | The cost of each class for this insn is its lowest cost among all the | |
1011 | alternatives. */ | |
1012 | ||
1013 | static void | |
1014 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
1015 | int n_alts; | |
1016 | int n_ops; | |
1017 | rtx *ops; | |
1018 | enum machine_mode *modes; | |
54dac99e | 1019 | char **constraints; |
e4600702 | 1020 | rtx insn; |
54dac99e | 1021 | { |
e4600702 RK |
1022 | int alt; |
1023 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; | |
1024 | int i, j; | |
ec2d92af | 1025 | rtx set; |
e4600702 RK |
1026 | |
1027 | /* By default, each operand is an input operand. */ | |
1028 | ||
1029 | for (i = 0; i < n_ops; i++) | |
1030 | op_types[i] = OP_READ; | |
54dac99e | 1031 | |
e4600702 RK |
1032 | /* Process each alternative, each time minimizing an operand's cost with |
1033 | the cost for each operand in that alternative. */ | |
54dac99e | 1034 | |
e4600702 | 1035 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1036 | { |
e4600702 RK |
1037 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1038 | int alt_fail = 0; | |
1039 | int alt_cost = 0; | |
1040 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
1041 | int class; | |
54dac99e | 1042 | |
e4600702 RK |
1043 | for (i = 0; i < n_ops; i++) |
1044 | { | |
1045 | char *p = constraints[i]; | |
1046 | rtx op = ops[i]; | |
1047 | enum machine_mode mode = modes[i]; | |
1048 | int allows_mem = 0; | |
1049 | int win = 0; | |
1050 | char c; | |
54dac99e | 1051 | |
e4600702 RK |
1052 | /* If this operand has no constraints at all, we can conclude |
1053 | nothing about it since anything is valid. */ | |
54dac99e | 1054 | |
e4600702 RK |
1055 | if (*p == 0) |
1056 | { | |
1057 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1058 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1059 | |
e4600702 RK |
1060 | continue; |
1061 | } | |
54dac99e | 1062 | |
347099d6 RS |
1063 | if (*p == '%') |
1064 | p++; | |
1065 | ||
e4600702 RK |
1066 | /* If this alternative is only relevant when this operand |
1067 | matches a previous operand, we do different things depending | |
1068 | on whether this operand is a pseudo-reg or not. */ | |
54dac99e | 1069 | |
e4600702 RK |
1070 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1071 | { | |
1072 | j = p[0] - '0'; | |
1073 | classes[i] = classes[j]; | |
1074 | ||
1075 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1076 | { | |
1077 | /* If this matches the other operand, we have no added | |
dc903608 | 1078 | cost and we win. */ |
e4600702 | 1079 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1080 | win = 1; |
e4600702 | 1081 | |
77e67eac RK |
1082 | /* If we can put the other operand into a register, add to |
1083 | the cost of this alternative the cost to copy this | |
1084 | operand to the register used for the other operand. */ | |
e4600702 | 1085 | |
dc903608 | 1086 | else if (classes[j] != NO_REGS) |
77e67eac | 1087 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1088 | } |
07d8ca2d RS |
1089 | else if (GET_CODE (ops[j]) != REG |
1090 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1091 | { | |
1092 | /* This op is a pseudo but the one it matches is not. */ | |
1093 | ||
1094 | /* If we can't put the other operand into a register, this | |
1095 | alternative can't be used. */ | |
1096 | ||
1097 | if (classes[j] == NO_REGS) | |
1098 | alt_fail = 1; | |
e4600702 | 1099 | |
07d8ca2d RS |
1100 | /* Otherwise, add to the cost of this alternative the cost |
1101 | to copy the other operand to the register used for this | |
1102 | operand. */ | |
1103 | ||
1104 | else | |
1105 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1106 | } | |
e4600702 RK |
1107 | else |
1108 | { | |
1109 | /* The costs of this operand are the same as that of the | |
1110 | other operand. However, if we cannot tie them, this | |
1111 | alternative needs to do a copy, which is one | |
1112 | instruction. */ | |
1113 | ||
1114 | this_op_costs[i] = this_op_costs[j]; | |
37747c82 RK |
1115 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1116 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1117 | alt_cost += 2; | |
e4600702 | 1118 | |
347099d6 | 1119 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1120 | for this operand, so skip to the end of the |
1121 | alternative (should be just one character). */ | |
1122 | while (*p && *p++ != ',') | |
1123 | ; | |
1124 | ||
1125 | constraints[i] = p; | |
347099d6 RS |
1126 | continue; |
1127 | } | |
e4600702 RK |
1128 | } |
1129 | ||
1130 | /* Scan all the constraint letters. See if the operand matches | |
1131 | any of the constraints. Collect the valid register classes | |
1132 | and see if this operand accepts memory. */ | |
1133 | ||
1134 | classes[i] = NO_REGS; | |
1135 | while (*p && (c = *p++) != ',') | |
1136 | switch (c) | |
1137 | { | |
1138 | case '=': | |
1139 | op_types[i] = OP_WRITE; | |
1140 | break; | |
1141 | ||
1142 | case '+': | |
1143 | op_types[i] = OP_READ_WRITE; | |
1144 | break; | |
1145 | ||
1146 | case '*': | |
1147 | /* Ignore the next letter for this pass. */ | |
1148 | p++; | |
1149 | break; | |
1150 | ||
1151 | case '%': | |
1152 | case '?': case '!': case '#': | |
1153 | case '&': | |
1154 | case '0': case '1': case '2': case '3': case '4': | |
1155 | case 'p': | |
1156 | break; | |
1157 | ||
1158 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1159 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 RK |
1160 | and non-offsettable addresses here. */ |
1161 | allows_mem = 1; | |
1162 | if (GET_CODE (op) == MEM) | |
1163 | win = 1; | |
1164 | break; | |
1165 | ||
1166 | case '<': | |
1167 | if (GET_CODE (op) == MEM | |
1168 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1169 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1170 | win = 1; | |
1171 | break; | |
1172 | ||
1173 | case '>': | |
1174 | if (GET_CODE (op) == MEM | |
1175 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1176 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1177 | win = 1; | |
1178 | break; | |
1179 | ||
1180 | case 'E': | |
7ac2547f | 1181 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1182 | /* Match any floating double constant, but only if |
1183 | we can examine the bits of it reliably. */ | |
1184 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1185 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1186 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1187 | break; | |
7ac2547f | 1188 | #endif |
e4600702 RK |
1189 | if (GET_CODE (op) == CONST_DOUBLE) |
1190 | win = 1; | |
1191 | break; | |
1192 | ||
1193 | case 'F': | |
1194 | if (GET_CODE (op) == CONST_DOUBLE) | |
1195 | win = 1; | |
1196 | break; | |
1197 | ||
1198 | case 'G': | |
1199 | case 'H': | |
1200 | if (GET_CODE (op) == CONST_DOUBLE | |
1201 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1202 | win = 1; | |
1203 | break; | |
1204 | ||
1205 | case 's': | |
1206 | if (GET_CODE (op) == CONST_INT | |
1207 | || (GET_CODE (op) == CONST_DOUBLE | |
1208 | && GET_MODE (op) == VOIDmode)) | |
1209 | break; | |
1210 | case 'i': | |
1211 | if (CONSTANT_P (op) | |
1212 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1213 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1214 | #endif | |
1215 | ) | |
1216 | win = 1; | |
1217 | break; | |
1218 | ||
1219 | case 'n': | |
1220 | if (GET_CODE (op) == CONST_INT | |
1221 | || (GET_CODE (op) == CONST_DOUBLE | |
1222 | && GET_MODE (op) == VOIDmode)) | |
1223 | win = 1; | |
1224 | break; | |
1225 | ||
1226 | case 'I': | |
1227 | case 'J': | |
1228 | case 'K': | |
1229 | case 'L': | |
1230 | case 'M': | |
1231 | case 'N': | |
1232 | case 'O': | |
1233 | case 'P': | |
1234 | if (GET_CODE (op) == CONST_INT | |
1235 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1236 | win = 1; | |
1237 | break; | |
1238 | ||
1239 | case 'X': | |
1240 | win = 1; | |
1241 | break; | |
54dac99e | 1242 | |
54dac99e | 1243 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1244 | case 'Q': |
1245 | case 'R': | |
1246 | case 'S': | |
1247 | case 'T': | |
1248 | case 'U': | |
1249 | if (EXTRA_CONSTRAINT (op, c)) | |
1250 | win = 1; | |
1251 | break; | |
1252 | #endif | |
1253 | ||
1254 | case 'g': | |
1255 | if (GET_CODE (op) == MEM | |
1256 | || (CONSTANT_P (op) | |
1257 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1258 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1259 | #endif |
e4600702 RK |
1260 | )) |
1261 | win = 1; | |
1262 | allows_mem = 1; | |
1263 | case 'r': | |
1264 | classes[i] | |
1265 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1266 | break; | |
1267 | ||
1268 | default: | |
1269 | classes[i] | |
1270 | = reg_class_subunion[(int) classes[i]] | |
1271 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1272 | } | |
1273 | ||
1274 | constraints[i] = p; | |
1275 | ||
1276 | /* How we account for this operand now depends on whether it is a | |
1277 | pseudo register or not. If it is, we first check if any | |
1278 | register classes are valid. If not, we ignore this alternative, | |
1279 | since we want to assume that all pseudos get allocated for | |
1280 | register preferencing. If some register class is valid, compute | |
1281 | the costs of moving the pseudo into that class. */ | |
1282 | ||
1283 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1284 | { |
e4600702 RK |
1285 | if (classes[i] == NO_REGS) |
1286 | alt_fail = 1; | |
1287 | else | |
1288 | { | |
1289 | struct costs *pp = &this_op_costs[i]; | |
1290 | ||
1291 | for (class = 0; class < N_REG_CLASSES; class++) | |
1292 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1293 | ||
1294 | /* If the alternative actually allows memory, make things | |
1295 | a bit cheaper since we won't need an extra insn to | |
1296 | load it. */ | |
1297 | ||
1298 | pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem; | |
1299 | ||
1300 | /* If we have assigned a class to this register in our | |
1301 | first pass, add a cost to this alternative corresponding | |
1302 | to what we would add if this register were not in the | |
1303 | appropriate class. */ | |
1304 | ||
1305 | if (prefclass) | |
1306 | alt_cost | |
1307 | += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; | |
1308 | } | |
4db18574 | 1309 | } |
54dac99e | 1310 | |
e4600702 RK |
1311 | /* Otherwise, if this alternative wins, either because we |
1312 | have already determined that or if we have a hard register of | |
1313 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1314 | |
e4600702 RK |
1315 | else if (win |
1316 | || (GET_CODE (op) == REG | |
6f654776 | 1317 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1318 | ; |
54dac99e | 1319 | |
e4600702 RK |
1320 | /* If registers are valid, the cost of this alternative includes |
1321 | copying the object to and/or from a register. */ | |
54dac99e | 1322 | |
e4600702 RK |
1323 | else if (classes[i] != NO_REGS) |
1324 | { | |
1325 | if (op_types[i] != OP_WRITE) | |
1326 | alt_cost += copy_cost (op, mode, classes[i], 1); | |
54dac99e | 1327 | |
e4600702 RK |
1328 | if (op_types[i] != OP_READ) |
1329 | alt_cost += copy_cost (op, mode, classes[i], 0); | |
1330 | } | |
54dac99e | 1331 | |
e4600702 RK |
1332 | /* The only other way this alternative can be used is if this is a |
1333 | constant that could be placed into memory. */ | |
1334 | ||
1335 | else if (CONSTANT_P (op) && allows_mem) | |
1336 | alt_cost += MEMORY_MOVE_COST (mode); | |
1337 | else | |
1338 | alt_fail = 1; | |
1339 | } | |
1340 | ||
1341 | if (alt_fail) | |
1342 | continue; | |
1343 | ||
1344 | /* Finally, update the costs with the information we've calculated | |
1345 | about this alternative. */ | |
1346 | ||
1347 | for (i = 0; i < n_ops; i++) | |
1348 | if (GET_CODE (ops[i]) == REG | |
1349 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1350 | { |
e4600702 RK |
1351 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1352 | int scale = 1 + (op_types[i] == OP_READ_WRITE); | |
54dac99e | 1353 | |
e4600702 RK |
1354 | pp->mem_cost = MIN (pp->mem_cost, |
1355 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1356 | |
e4600702 RK |
1357 | for (class = 0; class < N_REG_CLASSES; class++) |
1358 | pp->cost[class] = MIN (pp->cost[class], | |
1359 | (qq->cost[class] + alt_cost) * scale); | |
1360 | } | |
1361 | } | |
ec2d92af RK |
1362 | |
1363 | /* If this insn is a single set copying operand 1 to operand 0 | |
1364 | and one is a pseudo with the other a hard reg that is in its | |
1365 | own register class, set the cost of that register class to -1. */ | |
1366 | ||
1367 | if ((set = single_set (insn)) != 0 | |
1368 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1369 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1370 | for (i = 0; i <= 1; i++) | |
1371 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1372 | { | |
1373 | int regno = REGNO (ops[!i]); | |
1374 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1375 | int class; | |
4841ba4b | 1376 | int nr; |
ec2d92af RK |
1377 | |
1378 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 | |
1379 | && (reg_class_size[prefclass[regno]] | |
1380 | == CLASS_MAX_NREGS (prefclass[regno], mode))) | |
1381 | op_costs[i].cost[prefclass[regno]] = -1; | |
1382 | else if (regno < FIRST_PSEUDO_REGISTER) | |
1383 | for (class = 0; class < N_REG_CLASSES; class++) | |
1384 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1385 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1386 | { |
1387 | if (reg_class_size[class] == 1) | |
1388 | op_costs[i].cost[class] = -1; | |
1389 | else | |
1390 | { | |
1391 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1392 | { | |
1393 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1394 | break; | |
1395 | } | |
1396 | ||
1397 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1398 | op_costs[i].cost[class] = -1; | |
1399 | } | |
1400 | } | |
ec2d92af | 1401 | } |
54dac99e | 1402 | } |
e4600702 RK |
1403 | \f |
1404 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1405 | TO_P is zero) a register of class CLASS in mode MODE. | |
1406 | ||
1407 | X must not be a pseudo. */ | |
1408 | ||
1409 | static int | |
1410 | copy_cost (x, mode, class, to_p) | |
1411 | rtx x; | |
1412 | enum machine_mode mode; | |
1413 | enum reg_class class; | |
1414 | int to_p; | |
1415 | { | |
1416 | enum reg_class secondary_class = NO_REGS; | |
1417 | ||
1418 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1419 | assuming optimal allocation. */ | |
1420 | ||
1421 | if (GET_CODE (x) == SCRATCH) | |
1422 | return 0; | |
1423 | ||
1424 | /* Get the class we will actually use for a reload. */ | |
1425 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1426 | ||
1427 | #ifdef HAVE_SECONDARY_RELOADS | |
1428 | /* If we need a secondary reload (we assume here that we are using | |
1429 | the secondary reload as an intermediate, not a scratch register), the | |
1430 | cost is that to load the input into the intermediate register, then | |
1431 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1432 | ||
1433 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1434 | if (to_p == 1) | |
1435 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1436 | #endif | |
1437 | ||
dd9f0e8f | 1438 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1439 | if (! to_p) |
1440 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1441 | #endif | |
1442 | ||
1443 | if (secondary_class != NO_REGS) | |
1444 | return (move_cost[(int) secondary_class][(int) class] | |
1445 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1446 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1447 | |
1448 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1449 | cost to move between the register classes, and use 2 for everything | |
1450 | else (constants). */ | |
1451 | ||
1452 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
1453 | return MEMORY_MOVE_COST (mode); | |
54dac99e | 1454 | |
e4600702 RK |
1455 | else if (GET_CODE (x) == REG) |
1456 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1457 | ||
1458 | else | |
1459 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1460 | return 2; | |
1461 | } | |
1462 | \f | |
54dac99e RK |
1463 | /* Record the pseudo registers we must reload into hard registers |
1464 | in a subexpression of a memory address, X. | |
e4600702 RK |
1465 | |
1466 | CLASS is the class that the register needs to be in and is either | |
1467 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1468 | ||
1469 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1470 | can represent half-cost adjustments). */ | |
54dac99e | 1471 | |
197d6480 | 1472 | static void |
e4600702 | 1473 | record_address_regs (x, class, scale) |
54dac99e | 1474 | rtx x; |
e4600702 RK |
1475 | enum reg_class class; |
1476 | int scale; | |
54dac99e RK |
1477 | { |
1478 | register enum rtx_code code = GET_CODE (x); | |
1479 | ||
1480 | switch (code) | |
1481 | { | |
1482 | case CONST_INT: | |
1483 | case CONST: | |
1484 | case CC0: | |
1485 | case PC: | |
1486 | case SYMBOL_REF: | |
1487 | case LABEL_REF: | |
1488 | return; | |
1489 | ||
1490 | case PLUS: | |
1491 | /* When we have an address that is a sum, | |
1492 | we must determine whether registers are "base" or "index" regs. | |
1493 | If there is a sum of two registers, we must choose one to be | |
1494 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1495 | to make a good choice most of the time. We only need to do this |
1496 | on machines that can have two registers in an address and where | |
1497 | the base and index register classes are different. | |
1498 | ||
1499 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1500 | that seems bogus since it should only be set when we are sure | |
1501 | the register is being used as a pointer. */ | |
1502 | ||
54dac99e RK |
1503 | { |
1504 | rtx arg0 = XEXP (x, 0); | |
1505 | rtx arg1 = XEXP (x, 1); | |
1506 | register enum rtx_code code0 = GET_CODE (arg0); | |
1507 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1508 | |
1509 | /* Look inside subregs. */ | |
e4600702 | 1510 | if (code0 == SUBREG) |
54dac99e | 1511 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1512 | if (code1 == SUBREG) |
54dac99e RK |
1513 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1514 | ||
e4600702 RK |
1515 | /* If this machine only allows one register per address, it must |
1516 | be in the first operand. */ | |
1517 | ||
1518 | if (MAX_REGS_PER_ADDRESS == 1) | |
1519 | record_address_regs (arg0, class, scale); | |
1520 | ||
1521 | /* If index and base registers are the same on this machine, just | |
1522 | record registers in any non-constant operands. We assume here, | |
1523 | as well as in the tests below, that all addresses are in | |
1524 | canonical form. */ | |
1525 | ||
1526 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1527 | { |
e4600702 RK |
1528 | record_address_regs (arg0, class, scale); |
1529 | if (! CONSTANT_P (arg1)) | |
1530 | record_address_regs (arg1, class, scale); | |
54dac99e | 1531 | } |
e4600702 RK |
1532 | |
1533 | /* If the second operand is a constant integer, it doesn't change | |
1534 | what class the first operand must be. */ | |
1535 | ||
1536 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1537 | record_address_regs (arg0, class, scale); | |
1538 | ||
1539 | /* If the second operand is a symbolic constant, the first operand | |
1540 | must be an index register. */ | |
1541 | ||
1542 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1543 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1544 | ||
956d6950 JL |
1545 | /* If both operands are registers but one is already a hard register |
1546 | of index or base class, give the other the class that the hard | |
1547 | register is not. */ | |
1548 | ||
1549 | else if (code0 == REG && code1 == REG | |
1550 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1551 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1552 | record_address_regs (arg1, | |
1553 | REG_OK_FOR_BASE_P (arg0) | |
1554 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1555 | scale); | |
1556 | else if (code0 == REG && code1 == REG | |
1557 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1558 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1559 | record_address_regs (arg0, | |
1560 | REG_OK_FOR_BASE_P (arg1) | |
1561 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1562 | scale); | |
1563 | ||
e9a25f70 JL |
1564 | /* If one operand is known to be a pointer, it must be the base |
1565 | with the other operand the index. Likewise if the other operand | |
1566 | is a MULT. */ | |
f22376c7 | 1567 | |
e9a25f70 JL |
1568 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1569 | || code1 == MULT) | |
f22376c7 CI |
1570 | { |
1571 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1572 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1573 | } | |
e9a25f70 JL |
1574 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1575 | || code0 == MULT) | |
f22376c7 CI |
1576 | { |
1577 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1578 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1579 | } | |
1580 | ||
e9a25f70 | 1581 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1582 | or index register. This case should be rare. */ |
1583 | ||
e9a25f70 | 1584 | else |
54dac99e | 1585 | { |
e4600702 RK |
1586 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1587 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1588 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1589 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1590 | } |
54dac99e RK |
1591 | } |
1592 | break; | |
1593 | ||
1594 | case POST_INC: | |
1595 | case PRE_INC: | |
1596 | case POST_DEC: | |
1597 | case PRE_DEC: | |
1598 | /* Double the importance of a pseudo register that is incremented | |
1599 | or decremented, since it would take two extra insns | |
533d0835 RK |
1600 | if it ends up in the wrong place. If the operand is a pseudo, |
1601 | show it is being used in an INC_DEC context. */ | |
1602 | ||
1603 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1604 | if (GET_CODE (XEXP (x, 0)) == REG | |
1605 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1606 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1607 | #endif | |
e4600702 RK |
1608 | |
1609 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1610 | break; |
1611 | ||
1612 | case REG: | |
1613 | { | |
e4600702 RK |
1614 | register struct costs *pp = &costs[REGNO (x)]; |
1615 | register int i; | |
54dac99e | 1616 | |
e4600702 | 1617 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2; |
54dac99e | 1618 | |
e4600702 RK |
1619 | for (i = 0; i < N_REG_CLASSES; i++) |
1620 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1621 | } |
1622 | break; | |
1623 | ||
1624 | default: | |
1625 | { | |
1626 | register char *fmt = GET_RTX_FORMAT (code); | |
1627 | register int i; | |
1628 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1629 | if (fmt[i] == 'e') | |
e4600702 | 1630 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1631 | } |
1632 | } | |
1633 | } | |
08d95f91 RK |
1634 | \f |
1635 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1636 | ||
1637 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1638 | to an object of MODE. */ | |
1639 | ||
1d300e19 | 1640 | static int |
08d95f91 RK |
1641 | auto_inc_dec_reg_p (reg, mode) |
1642 | rtx reg; | |
1643 | enum machine_mode mode; | |
1644 | { | |
1645 | #ifdef HAVE_POST_INCREMENT | |
1646 | if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg))) | |
1647 | return 1; | |
1648 | #endif | |
1649 | ||
1650 | #ifdef HAVE_POST_DECREMENT | |
1651 | if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg))) | |
1652 | return 1; | |
1653 | #endif | |
1654 | ||
1655 | #ifdef HAVE_PRE_INCREMENT | |
1656 | if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg))) | |
1657 | return 1; | |
1658 | #endif | |
1659 | ||
1660 | #ifdef HAVE_PRE_DECREMENT | |
1661 | if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg))) | |
1662 | return 1; | |
1663 | #endif | |
1664 | ||
1665 | return 0; | |
1666 | } | |
1667 | #endif | |
1668 | ||
54dac99e | 1669 | #endif /* REGISTER_CONSTRAINTS */ |
b1f21e0a MM |
1670 | \f |
1671 | /* Allocate enough space to hold NUM_REGS registers for the tables used for | |
1672 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1673 | NEW_P is non zero, initialize all of the registers, otherwise only |
1674 | initialize the new registers allocated. The same table is kept from | |
1675 | function to function, only reallocating it when we need more room. If | |
1676 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1677 | |
1678 | void | |
39379e67 | 1679 | allocate_reg_info (num_regs, new_p, renumber_p) |
b1f21e0a MM |
1680 | int num_regs; |
1681 | int new_p; | |
39379e67 | 1682 | int renumber_p; |
b1f21e0a MM |
1683 | { |
1684 | static int regno_allocated = 0; | |
1685 | static int regno_max = 0; | |
39379e67 | 1686 | static short *renumber = (short *)0; |
b1f21e0a | 1687 | int i; |
39379e67 MM |
1688 | int size_info; |
1689 | int size_renumber; | |
7ec189f2 | 1690 | int min = (new_p) ? 0 : regno_max; |
b1f21e0a | 1691 | |
39379e67 MM |
1692 | /* If this message come up, and you want to fix it, then all of the tables |
1693 | like reg_renumber, etc. that use short will have to be found and lengthed | |
1694 | to int or HOST_WIDE_INT. */ | |
1695 | ||
1696 | /* Free up all storage allocated */ | |
1697 | if (num_regs < 0) | |
1698 | { | |
1699 | if (reg_n_info) | |
1700 | { | |
1701 | free ((char *)reg_n_info); | |
1702 | free ((char *)renumber); | |
1703 | reg_n_info = (reg_info *)0; | |
1704 | renumber = (short *)0; | |
1705 | } | |
1706 | regno_allocated = 0; | |
1707 | regno_max = 0; | |
1708 | return; | |
1709 | } | |
1710 | ||
b1f21e0a MM |
1711 | if (num_regs > regno_allocated) |
1712 | { | |
1713 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ | |
39379e67 MM |
1714 | size_info = regno_allocated * sizeof (reg_info); |
1715 | size_renumber = regno_allocated * sizeof (short); | |
1716 | ||
1717 | if (!reg_n_info) | |
1718 | { | |
1719 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1720 | renumber = (short *) xmalloc (size_renumber); | |
1721 | } | |
1722 | ||
1723 | else if (new_p) /* if we're zapping everything, no need to realloc */ | |
1724 | { | |
1725 | free ((char *)reg_n_info); | |
1726 | free ((char *)renumber); | |
1727 | reg_n_info = (reg_info *) xmalloc (size_info); | |
1728 | renumber = (short *) xmalloc (size_renumber); | |
1729 | } | |
1730 | ||
1731 | else | |
1732 | { | |
1733 | reg_n_info = (reg_info *) xrealloc ((char *)reg_n_info, size_info); | |
1734 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
1735 | } | |
b1f21e0a MM |
1736 | } |
1737 | ||
1738 | if (min < num_regs) | |
1739 | { | |
1740 | bzero ((char *) ®_n_info[min], (num_regs - min) * sizeof (reg_info)); | |
1741 | for (i = min; i < num_regs; i++) | |
39379e67 MM |
1742 | { |
1743 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
1744 | renumber[i] = -1; | |
1745 | } | |
b1f21e0a MM |
1746 | } |
1747 | ||
39379e67 MM |
1748 | if (renumber_p) |
1749 | reg_renumber = renumber; | |
1750 | ||
73b76448 RK |
1751 | /* Tell the regset code about the new number of registers */ |
1752 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
1753 | ||
b1f21e0a MM |
1754 | regno_max = num_regs; |
1755 | } | |
1756 | ||
54dac99e RK |
1757 | \f |
1758 | /* This is the `regscan' pass of the compiler, run just before cse | |
1759 | and again just before loop. | |
1760 | ||
1761 | It finds the first and last use of each pseudo-register | |
1762 | and records them in the vectors regno_first_uid, regno_last_uid | |
1763 | and counts the number of sets in the vector reg_n_sets. | |
1764 | ||
1765 | REPEAT is nonzero the second time this is called. */ | |
1766 | ||
54dac99e | 1767 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 1768 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
1769 | and we want this to remain correct for all the remaining passes. */ |
1770 | ||
1771 | int max_parallel; | |
1772 | ||
54dac99e RK |
1773 | void |
1774 | reg_scan (f, nregs, repeat) | |
1775 | rtx f; | |
1776 | int nregs; | |
1777 | int repeat; | |
1778 | { | |
1779 | register rtx insn; | |
1780 | ||
39379e67 | 1781 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
1782 | max_parallel = 3; |
1783 | ||
1784 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1785 | if (GET_CODE (insn) == INSN | |
1786 | || GET_CODE (insn) == CALL_INSN | |
1787 | || GET_CODE (insn) == JUMP_INSN) | |
1788 | { | |
1789 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1790 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1791 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
1ebecb64 | 1792 | reg_scan_mark_refs (PATTERN (insn), insn, 0); |
01565a55 RK |
1793 | |
1794 | if (REG_NOTES (insn)) | |
1795 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1); | |
54dac99e RK |
1796 | } |
1797 | } | |
1798 | ||
1ebecb64 RS |
1799 | /* X is the expression to scan. INSN is the insn it appears in. |
1800 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ | |
1801 | ||
08d95f91 | 1802 | static void |
1ebecb64 | 1803 | reg_scan_mark_refs (x, insn, note_flag) |
54dac99e | 1804 | rtx x; |
be8dcd74 | 1805 | rtx insn; |
1ebecb64 | 1806 | int note_flag; |
54dac99e RK |
1807 | { |
1808 | register enum rtx_code code = GET_CODE (x); | |
1809 | register rtx dest; | |
be8dcd74 | 1810 | register rtx note; |
54dac99e RK |
1811 | |
1812 | switch (code) | |
1813 | { | |
1814 | case CONST_INT: | |
1815 | case CONST: | |
1816 | case CONST_DOUBLE: | |
1817 | case CC0: | |
1818 | case PC: | |
1819 | case SYMBOL_REF: | |
1820 | case LABEL_REF: | |
1821 | case ADDR_VEC: | |
1822 | case ADDR_DIFF_VEC: | |
1823 | return; | |
1824 | ||
1825 | case REG: | |
1826 | { | |
1827 | register int regno = REGNO (x); | |
1828 | ||
b1f21e0a | 1829 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); |
1ebecb64 | 1830 | if (!note_flag) |
b1f21e0a MM |
1831 | REGNO_LAST_UID (regno) = INSN_UID (insn); |
1832 | if (REGNO_FIRST_UID (regno) == 0) | |
1833 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
54dac99e RK |
1834 | } |
1835 | break; | |
1836 | ||
01565a55 | 1837 | case EXPR_LIST: |
7b18c3db RS |
1838 | if (XEXP (x, 0)) |
1839 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); | |
01565a55 RK |
1840 | if (XEXP (x, 1)) |
1841 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1842 | break; | |
1843 | ||
1844 | case INSN_LIST: | |
1845 | if (XEXP (x, 1)) | |
1846 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); | |
1847 | break; | |
1848 | ||
54dac99e RK |
1849 | case SET: |
1850 | /* Count a set of the destination if it is a register. */ | |
1851 | for (dest = SET_DEST (x); | |
1852 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
1853 | || GET_CODE (dest) == ZERO_EXTEND; | |
1854 | dest = XEXP (dest, 0)) | |
1855 | ; | |
1856 | ||
1857 | if (GET_CODE (dest) == REG) | |
b1f21e0a | 1858 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 1859 | |
be8dcd74 RK |
1860 | /* If this is setting a pseudo from another pseudo or the sum of a |
1861 | pseudo and a constant integer and the other pseudo is known to be | |
1862 | a pointer, set the destination to be a pointer as well. | |
1863 | ||
1864 | Likewise if it is setting the destination from an address or from a | |
1865 | value equivalent to an address or to the sum of an address and | |
1866 | something else. | |
1867 | ||
1868 | But don't do any of this if the pseudo corresponds to a user | |
1869 | variable since it should have already been set as a pointer based | |
1870 | on the type. */ | |
1871 | ||
1872 | if (GET_CODE (SET_DEST (x)) == REG | |
1873 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
1874 | && ! REG_USERVAR_P (SET_DEST (x)) | |
1875 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
1876 | && ((GET_CODE (SET_SRC (x)) == REG | |
1877 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
1878 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1879 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1880 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
1881 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
1882 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
1883 | || GET_CODE (SET_SRC (x)) == CONST | |
1884 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
1885 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
1886 | || (GET_CODE (SET_SRC (x)) == HIGH | |
1887 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
1888 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
1889 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
1890 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
1891 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
1892 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
1893 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
1894 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
1895 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
1896 | && (GET_CODE (XEXP (note, 0)) == CONST | |
1897 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
1898 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
1899 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
1900 | ||
0f41302f | 1901 | /* ... fall through ... */ |
54dac99e RK |
1902 | |
1903 | default: | |
1904 | { | |
1905 | register char *fmt = GET_RTX_FORMAT (code); | |
1906 | register int i; | |
1907 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1908 | { | |
1909 | if (fmt[i] == 'e') | |
1ebecb64 | 1910 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag); |
54dac99e RK |
1911 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
1912 | { | |
1913 | register int j; | |
1914 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1ebecb64 | 1915 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); |
54dac99e RK |
1916 | } |
1917 | } | |
1918 | } | |
1919 | } | |
1920 | } | |
1921 | \f | |
1922 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
1923 | is also in C2. */ | |
1924 | ||
1925 | int | |
1926 | reg_class_subset_p (c1, c2) | |
1927 | register enum reg_class c1; | |
1928 | register enum reg_class c2; | |
1929 | { | |
1930 | if (c1 == c2) return 1; | |
1931 | ||
1932 | if (c2 == ALL_REGS) | |
1933 | win: | |
1934 | return 1; | |
1935 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
1936 | reg_class_contents[(int)c2], | |
1937 | win); | |
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
1942 | ||
1943 | int | |
1944 | reg_classes_intersect_p (c1, c2) | |
1945 | register enum reg_class c1; | |
1946 | register enum reg_class c2; | |
1947 | { | |
1948 | #ifdef HARD_REG_SET | |
1949 | register | |
1950 | #endif | |
1951 | HARD_REG_SET c; | |
1952 | ||
1953 | if (c1 == c2) return 1; | |
1954 | ||
1955 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
1956 | return 1; | |
1957 | ||
1958 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
1959 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
1960 | ||
1961 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
1962 | return 1; | |
1963 | ||
1964 | lose: | |
1965 | return 0; | |
1966 | } | |
1967 | ||
73b76448 RK |
1968 | /* Release any memory allocated by register sets. */ |
1969 | ||
1970 | void | |
1971 | regset_release_memory () | |
1972 | { | |
1973 | if (basic_block_live_at_start) | |
1974 | { | |
1975 | free_regset_vector (basic_block_live_at_start, n_basic_blocks); | |
1976 | basic_block_live_at_start = 0; | |
1977 | } | |
1978 | ||
1979 | FREE_REG_SET (regs_live_at_setjmp); | |
1980 | bitmap_release_memory (); | |
1981 | } |