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2055cea7 | 1 | /* Subroutines used by or related to instruction recognition. |
af841dbd JL |
2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 |
3 | 1999, 2000 Free Software Foundation, Inc. | |
2055cea7 RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
2055cea7 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
38a448ca | 25 | #include "rtl.h" |
6baf1cc8 | 26 | #include "tm_p.h" |
2055cea7 RK |
27 | #include "insn-config.h" |
28 | #include "insn-attr.h" | |
29 | #include "insn-flags.h" | |
30 | #include "insn-codes.h" | |
31 | #include "recog.h" | |
32 | #include "regs.h" | |
33 | #include "hard-reg-set.h" | |
49ad7cfa | 34 | #include "function.h" |
2055cea7 RK |
35 | #include "flags.h" |
36 | #include "real.h" | |
7f7f8214 | 37 | #include "toplev.h" |
ca545bb5 | 38 | #include "basic-block.h" |
ede7cd44 RH |
39 | #include "output.h" |
40 | #include "resource.h" | |
2055cea7 RK |
41 | |
42 | #ifndef STACK_PUSH_CODE | |
43 | #ifdef STACK_GROWS_DOWNWARD | |
44 | #define STACK_PUSH_CODE PRE_DEC | |
45 | #else | |
46 | #define STACK_PUSH_CODE PRE_INC | |
47 | #endif | |
48 | #endif | |
49 | ||
6fbe9bd8 RH |
50 | #ifndef STACK_POP_CODE |
51 | #ifdef STACK_GROWS_DOWNWARD | |
52 | #define STACK_POP_CODE POST_INC | |
53 | #else | |
54 | #define STACK_POP_CODE POST_DEC | |
55 | #endif | |
56 | #endif | |
57 | ||
13536812 KG |
58 | static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx)); |
59 | static rtx *find_single_use_1 PARAMS ((rtx, rtx *)); | |
60 | static rtx *find_constant_term_loc PARAMS ((rtx *)); | |
61 | static int insn_invalid_p PARAMS ((rtx)); | |
2055cea7 RK |
62 | |
63 | /* Nonzero means allow operands to be volatile. | |
64 | This should be 0 if you are generating rtl, such as if you are calling | |
65 | the functions in optabs.c and expmed.c (most of the time). | |
66 | This should be 1 if all valid insns need to be recognized, | |
67 | such as in regclass.c and final.c and reload.c. | |
68 | ||
69 | init_recog and init_recog_no_volatile are responsible for setting this. */ | |
70 | ||
71 | int volatile_ok; | |
72 | ||
1ccbefce | 73 | struct recog_data recog_data; |
0a578fee | 74 | |
f62a15e3 BS |
75 | /* Contains a vector of operand_alternative structures for every operand. |
76 | Set up by preprocess_constraints. */ | |
77 | struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES]; | |
78 | ||
2055cea7 RK |
79 | /* On return from `constrain_operands', indicate which alternative |
80 | was satisfied. */ | |
81 | ||
82 | int which_alternative; | |
83 | ||
84 | /* Nonzero after end of reload pass. | |
85 | Set to 1 or 0 by toplev.c. | |
86 | Controls the significance of (SUBREG (MEM)). */ | |
87 | ||
88 | int reload_completed; | |
89 | ||
90 | /* Initialize data used by the function `recog'. | |
91 | This must be called once in the compilation of a function | |
92 | before any insn recognition may be done in the function. */ | |
93 | ||
94 | void | |
95 | init_recog_no_volatile () | |
96 | { | |
97 | volatile_ok = 0; | |
98 | } | |
99 | ||
e0069e43 | 100 | void |
2055cea7 RK |
101 | init_recog () |
102 | { | |
103 | volatile_ok = 1; | |
104 | } | |
105 | ||
106 | /* Try recognizing the instruction INSN, | |
107 | and return the code number that results. | |
9faa82d8 | 108 | Remember the code so that repeated calls do not |
2055cea7 RK |
109 | need to spend the time for actual rerecognition. |
110 | ||
111 | This function is the normal interface to instruction recognition. | |
112 | The automatically-generated function `recog' is normally called | |
113 | through this one. (The only exception is in combine.c.) */ | |
114 | ||
115 | int | |
116 | recog_memoized (insn) | |
117 | rtx insn; | |
118 | { | |
119 | if (INSN_CODE (insn) < 0) | |
9e4223f2 | 120 | INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR); |
2055cea7 RK |
121 | return INSN_CODE (insn); |
122 | } | |
123 | \f | |
124 | /* Check that X is an insn-body for an `asm' with operands | |
125 | and that the operands mentioned in it are legitimate. */ | |
126 | ||
127 | int | |
128 | check_asm_operands (x) | |
129 | rtx x; | |
130 | { | |
1f06ee8d | 131 | int noperands; |
2055cea7 | 132 | rtx *operands; |
9b3142b3 | 133 | const char **constraints; |
2055cea7 RK |
134 | int i; |
135 | ||
1f06ee8d RH |
136 | /* Post-reload, be more strict with things. */ |
137 | if (reload_completed) | |
138 | { | |
139 | /* ??? Doh! We've not got the wrapping insn. Cook one up. */ | |
140 | extract_insn (make_insn_raw (x)); | |
141 | constrain_operands (1); | |
142 | return which_alternative >= 0; | |
143 | } | |
144 | ||
145 | noperands = asm_noperands (x); | |
2055cea7 RK |
146 | if (noperands < 0) |
147 | return 0; | |
148 | if (noperands == 0) | |
149 | return 1; | |
150 | ||
151 | operands = (rtx *) alloca (noperands * sizeof (rtx)); | |
9b3142b3 | 152 | constraints = (const char **) alloca (noperands * sizeof (char *)); |
1f06ee8d RH |
153 | |
154 | decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR); | |
2055cea7 RK |
155 | |
156 | for (i = 0; i < noperands; i++) | |
1f06ee8d | 157 | { |
9b3142b3 | 158 | const char *c = constraints[i]; |
1afbe1c4 RH |
159 | if (c[0] == '%') |
160 | c++; | |
161 | if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0') | |
1f06ee8d RH |
162 | c = constraints[c[0] - '0']; |
163 | ||
164 | if (! asm_operand_ok (operands[i], c)) | |
165 | return 0; | |
166 | } | |
2055cea7 RK |
167 | |
168 | return 1; | |
169 | } | |
170 | \f | |
41a972a9 | 171 | /* Static data for the next two routines. */ |
2055cea7 | 172 | |
41a972a9 MM |
173 | typedef struct change_t |
174 | { | |
175 | rtx object; | |
176 | int old_code; | |
177 | rtx *loc; | |
178 | rtx old; | |
179 | } change_t; | |
2055cea7 | 180 | |
41a972a9 MM |
181 | static change_t *changes; |
182 | static int changes_allocated; | |
2055cea7 RK |
183 | |
184 | static int num_changes = 0; | |
185 | ||
186 | /* Validate a proposed change to OBJECT. LOC is the location in the rtl for | |
187 | at which NEW will be placed. If OBJECT is zero, no validation is done, | |
188 | the change is simply made. | |
189 | ||
190 | Two types of objects are supported: If OBJECT is a MEM, memory_address_p | |
191 | will be called with the address and mode as parameters. If OBJECT is | |
192 | an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with | |
193 | the change in place. | |
194 | ||
195 | IN_GROUP is non-zero if this is part of a group of changes that must be | |
196 | performed as a group. In that case, the changes will be stored. The | |
197 | function `apply_change_group' will validate and apply the changes. | |
198 | ||
199 | If IN_GROUP is zero, this is a single change. Try to recognize the insn | |
200 | or validate the memory reference with the change applied. If the result | |
201 | is not valid for the machine, suppress the change and return zero. | |
202 | Otherwise, perform the change and return 1. */ | |
203 | ||
204 | int | |
205 | validate_change (object, loc, new, in_group) | |
206 | rtx object; | |
207 | rtx *loc; | |
208 | rtx new; | |
209 | int in_group; | |
210 | { | |
211 | rtx old = *loc; | |
212 | ||
213 | if (old == new || rtx_equal_p (old, new)) | |
214 | return 1; | |
215 | ||
41a972a9 | 216 | if (in_group == 0 && num_changes != 0) |
2055cea7 RK |
217 | abort (); |
218 | ||
219 | *loc = new; | |
220 | ||
221 | /* Save the information describing this change. */ | |
41a972a9 MM |
222 | if (num_changes >= changes_allocated) |
223 | { | |
224 | if (changes_allocated == 0) | |
225 | /* This value allows for repeated substitutions inside complex | |
226 | indexed addresses, or changes in up to 5 insns. */ | |
227 | changes_allocated = MAX_RECOG_OPERANDS * 5; | |
228 | else | |
229 | changes_allocated *= 2; | |
230 | ||
231 | changes = | |
232 | (change_t*) xrealloc (changes, | |
233 | sizeof (change_t) * changes_allocated); | |
234 | } | |
235 | ||
236 | changes[num_changes].object = object; | |
237 | changes[num_changes].loc = loc; | |
238 | changes[num_changes].old = old; | |
2055cea7 RK |
239 | |
240 | if (object && GET_CODE (object) != MEM) | |
241 | { | |
242 | /* Set INSN_CODE to force rerecognition of insn. Save old code in | |
243 | case invalid. */ | |
41a972a9 | 244 | changes[num_changes].old_code = INSN_CODE (object); |
2055cea7 RK |
245 | INSN_CODE (object) = -1; |
246 | } | |
247 | ||
248 | num_changes++; | |
249 | ||
250 | /* If we are making a group of changes, return 1. Otherwise, validate the | |
251 | change group we made. */ | |
252 | ||
253 | if (in_group) | |
254 | return 1; | |
255 | else | |
256 | return apply_change_group (); | |
257 | } | |
258 | ||
61719ba7 BS |
259 | /* This subroutine of apply_change_group verifies whether the changes to INSN |
260 | were valid; i.e. whether INSN can still be recognized. */ | |
261 | ||
262 | static int | |
263 | insn_invalid_p (insn) | |
264 | rtx insn; | |
265 | { | |
266 | int icode = recog_memoized (insn); | |
267 | int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; | |
268 | ||
0eadeb15 BS |
269 | if (is_asm && ! check_asm_operands (PATTERN (insn))) |
270 | return 1; | |
271 | if (! is_asm && icode < 0) | |
61719ba7 BS |
272 | return 1; |
273 | ||
274 | /* After reload, verify that all constraints are satisfied. */ | |
275 | if (reload_completed) | |
276 | { | |
0eadeb15 | 277 | extract_insn (insn); |
61719ba7 | 278 | |
0eadeb15 | 279 | if (! constrain_operands (1)) |
61719ba7 BS |
280 | return 1; |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
2055cea7 RK |
286 | /* Apply a group of changes previously issued with `validate_change'. |
287 | Return 1 if all changes are valid, zero otherwise. */ | |
288 | ||
289 | int | |
290 | apply_change_group () | |
291 | { | |
292 | int i; | |
293 | ||
294 | /* The changes have been applied and all INSN_CODEs have been reset to force | |
295 | rerecognition. | |
296 | ||
297 | The changes are valid if we aren't given an object, or if we are | |
298 | given a MEM and it still is a valid address, or if this is in insn | |
299 | and it is recognized. In the latter case, if reload has completed, | |
300 | we also require that the operands meet the constraints for | |
0eadeb15 | 301 | the insn. */ |
2055cea7 RK |
302 | |
303 | for (i = 0; i < num_changes; i++) | |
304 | { | |
41a972a9 | 305 | rtx object = changes[i].object; |
2055cea7 RK |
306 | |
307 | if (object == 0) | |
308 | continue; | |
309 | ||
310 | if (GET_CODE (object) == MEM) | |
311 | { | |
312 | if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) | |
313 | break; | |
314 | } | |
61719ba7 | 315 | else if (insn_invalid_p (object)) |
2055cea7 RK |
316 | { |
317 | rtx pat = PATTERN (object); | |
318 | ||
319 | /* Perhaps we couldn't recognize the insn because there were | |
320 | extra CLOBBERs at the end. If so, try to re-recognize | |
321 | without the last CLOBBER (later iterations will cause each of | |
322 | them to be eliminated, in turn). But don't do this if we | |
323 | have an ASM_OPERAND. */ | |
324 | if (GET_CODE (pat) == PARALLEL | |
325 | && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER | |
326 | && asm_noperands (PATTERN (object)) < 0) | |
327 | { | |
328 | rtx newpat; | |
329 | ||
330 | if (XVECLEN (pat, 0) == 2) | |
331 | newpat = XVECEXP (pat, 0, 0); | |
332 | else | |
333 | { | |
334 | int j; | |
335 | ||
c5c76735 JL |
336 | newpat |
337 | = gen_rtx_PARALLEL (VOIDmode, | |
338 | gen_rtvec (XVECLEN (pat, 0) - 1)); | |
2055cea7 RK |
339 | for (j = 0; j < XVECLEN (newpat, 0); j++) |
340 | XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); | |
341 | } | |
342 | ||
343 | /* Add a new change to this group to replace the pattern | |
344 | with this new pattern. Then consider this change | |
345 | as having succeeded. The change we added will | |
346 | cause the entire call to fail if things remain invalid. | |
347 | ||
348 | Note that this can lose if a later change than the one | |
349 | we are processing specified &XVECEXP (PATTERN (object), 0, X) | |
350 | but this shouldn't occur. */ | |
351 | ||
352 | validate_change (object, &PATTERN (object), newpat, 1); | |
353 | } | |
354 | else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) | |
355 | /* If this insn is a CLOBBER or USE, it is always valid, but is | |
356 | never recognized. */ | |
357 | continue; | |
358 | else | |
359 | break; | |
360 | } | |
361 | } | |
362 | ||
363 | if (i == num_changes) | |
364 | { | |
365 | num_changes = 0; | |
366 | return 1; | |
367 | } | |
368 | else | |
369 | { | |
370 | cancel_changes (0); | |
371 | return 0; | |
372 | } | |
373 | } | |
374 | ||
375 | /* Return the number of changes so far in the current group. */ | |
376 | ||
377 | int | |
378 | num_validated_changes () | |
379 | { | |
380 | return num_changes; | |
381 | } | |
382 | ||
383 | /* Retract the changes numbered NUM and up. */ | |
384 | ||
385 | void | |
386 | cancel_changes (num) | |
387 | int num; | |
388 | { | |
389 | int i; | |
390 | ||
391 | /* Back out all the changes. Do this in the opposite order in which | |
392 | they were made. */ | |
393 | for (i = num_changes - 1; i >= num; i--) | |
394 | { | |
41a972a9 MM |
395 | *changes[i].loc = changes[i].old; |
396 | if (changes[i].object && GET_CODE (changes[i].object) != MEM) | |
397 | INSN_CODE (changes[i].object) = changes[i].old_code; | |
2055cea7 RK |
398 | } |
399 | num_changes = num; | |
400 | } | |
401 | ||
402 | /* Replace every occurrence of FROM in X with TO. Mark each change with | |
403 | validate_change passing OBJECT. */ | |
404 | ||
405 | static void | |
406 | validate_replace_rtx_1 (loc, from, to, object) | |
407 | rtx *loc; | |
408 | rtx from, to, object; | |
409 | { | |
410 | register int i, j; | |
6f7d635c | 411 | register const char *fmt; |
2055cea7 RK |
412 | register rtx x = *loc; |
413 | enum rtx_code code = GET_CODE (x); | |
414 | ||
415 | /* X matches FROM if it is the same rtx or they are both referring to the | |
416 | same register in the same mode. Avoid calling rtx_equal_p unless the | |
417 | operands look similar. */ | |
418 | ||
419 | if (x == from | |
420 | || (GET_CODE (x) == REG && GET_CODE (from) == REG | |
421 | && GET_MODE (x) == GET_MODE (from) | |
422 | && REGNO (x) == REGNO (from)) | |
423 | || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) | |
424 | && rtx_equal_p (x, from))) | |
425 | { | |
426 | validate_change (object, loc, to, 1); | |
427 | return; | |
428 | } | |
429 | ||
430 | /* For commutative or comparison operations, try replacing each argument | |
431 | separately and seeing if we made any changes. If so, put a constant | |
432 | argument last.*/ | |
433 | if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') | |
434 | { | |
435 | int prev_changes = num_changes; | |
436 | ||
437 | validate_replace_rtx_1 (&XEXP (x, 0), from, to, object); | |
438 | validate_replace_rtx_1 (&XEXP (x, 1), from, to, object); | |
439 | if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0))) | |
440 | { | |
441 | validate_change (object, loc, | |
38a448ca RH |
442 | gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code |
443 | : swap_condition (code), | |
444 | GET_MODE (x), XEXP (x, 1), | |
445 | XEXP (x, 0)), | |
2055cea7 RK |
446 | 1); |
447 | x = *loc; | |
448 | code = GET_CODE (x); | |
449 | } | |
450 | } | |
451 | ||
06140bdf RK |
452 | /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already |
453 | done the substitution, otherwise we won't. */ | |
454 | ||
2055cea7 RK |
455 | switch (code) |
456 | { | |
457 | case PLUS: | |
38e01259 | 458 | /* If we have a PLUS whose second operand is now a CONST_INT, use |
2055cea7 RK |
459 | plus_constant to try to simplify it. */ |
460 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to) | |
06140bdf RK |
461 | validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)), |
462 | 1); | |
2055cea7 | 463 | return; |
06140bdf RK |
464 | |
465 | case MINUS: | |
466 | if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from) | |
467 | { | |
468 | validate_change (object, loc, | |
469 | plus_constant (XEXP (x, 0), - INTVAL (to)), | |
470 | 1); | |
471 | return; | |
472 | } | |
473 | break; | |
2055cea7 RK |
474 | |
475 | case ZERO_EXTEND: | |
476 | case SIGN_EXTEND: | |
477 | /* In these cases, the operation to be performed depends on the mode | |
478 | of the operand. If we are replacing the operand with a VOIDmode | |
479 | constant, we lose the information. So try to simplify the operation | |
480 | in that case. If it fails, substitute in something that we know | |
6dc42e49 | 481 | won't be recognized. */ |
2055cea7 RK |
482 | if (GET_MODE (to) == VOIDmode |
483 | && (XEXP (x, 0) == from | |
484 | || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG | |
485 | && GET_MODE (XEXP (x, 0)) == GET_MODE (from) | |
486 | && REGNO (XEXP (x, 0)) == REGNO (from)))) | |
487 | { | |
488 | rtx new = simplify_unary_operation (code, GET_MODE (x), to, | |
489 | GET_MODE (from)); | |
490 | if (new == 0) | |
38a448ca | 491 | new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
2055cea7 RK |
492 | |
493 | validate_change (object, loc, new, 1); | |
494 | return; | |
495 | } | |
496 | break; | |
497 | ||
498 | case SUBREG: | |
499 | /* If we have a SUBREG of a register that we are replacing and we are | |
500 | replacing it with a MEM, make a new MEM and try replacing the | |
501 | SUBREG with it. Don't do this if the MEM has a mode-dependent address | |
502 | or if we would be widening it. */ | |
503 | ||
504 | if (SUBREG_REG (x) == from | |
505 | && GET_CODE (from) == REG | |
506 | && GET_CODE (to) == MEM | |
507 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
508 | && ! MEM_VOLATILE_P (to) | |
509 | && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to))) | |
510 | { | |
511 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
512 | enum machine_mode mode = GET_MODE (x); | |
513 | rtx new; | |
514 | ||
f76b9db2 ILT |
515 | if (BYTES_BIG_ENDIAN) |
516 | offset += (MIN (UNITS_PER_WORD, | |
517 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
518 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
2055cea7 | 519 | |
38a448ca | 520 | new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset)); |
c6df88cb | 521 | MEM_COPY_ATTRIBUTES (new, to); |
2055cea7 RK |
522 | validate_change (object, loc, new, 1); |
523 | return; | |
524 | } | |
525 | break; | |
526 | ||
527 | case ZERO_EXTRACT: | |
528 | case SIGN_EXTRACT: | |
529 | /* If we are replacing a register with memory, try to change the memory | |
530 | to be the mode required for memory in extract operations (this isn't | |
531 | likely to be an insertion operation; if it was, nothing bad will | |
532 | happen, we might just fail in some cases). */ | |
533 | ||
534 | if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM | |
535 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
536 | && GET_CODE (XEXP (x, 2)) == CONST_INT | |
537 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
538 | && ! MEM_VOLATILE_P (to)) | |
539 | { | |
540 | enum machine_mode wanted_mode = VOIDmode; | |
541 | enum machine_mode is_mode = GET_MODE (to); | |
2055cea7 RK |
542 | int pos = INTVAL (XEXP (x, 2)); |
543 | ||
544 | #ifdef HAVE_extzv | |
545 | if (code == ZERO_EXTRACT) | |
0d8e55d8 | 546 | { |
a995e389 | 547 | wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode; |
0d8e55d8 JL |
548 | if (wanted_mode == VOIDmode) |
549 | wanted_mode = word_mode; | |
550 | } | |
2055cea7 RK |
551 | #endif |
552 | #ifdef HAVE_extv | |
553 | if (code == SIGN_EXTRACT) | |
0d8e55d8 | 554 | { |
a995e389 | 555 | wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode; |
0d8e55d8 JL |
556 | if (wanted_mode == VOIDmode) |
557 | wanted_mode = word_mode; | |
558 | } | |
2055cea7 RK |
559 | #endif |
560 | ||
6dc42e49 | 561 | /* If we have a narrower mode, we can do something. */ |
2055cea7 RK |
562 | if (wanted_mode != VOIDmode |
563 | && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) | |
564 | { | |
565 | int offset = pos / BITS_PER_UNIT; | |
566 | rtx newmem; | |
567 | ||
568 | /* If the bytes and bits are counted differently, we | |
569 | must adjust the offset. */ | |
f76b9db2 ILT |
570 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) |
571 | offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) | |
572 | - offset); | |
2055cea7 RK |
573 | |
574 | pos %= GET_MODE_BITSIZE (wanted_mode); | |
575 | ||
38a448ca RH |
576 | newmem = gen_rtx_MEM (wanted_mode, |
577 | plus_constant (XEXP (to, 0), offset)); | |
c6df88cb | 578 | MEM_COPY_ATTRIBUTES (newmem, to); |
2055cea7 | 579 | |
9e4223f2 | 580 | validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); |
2055cea7 RK |
581 | validate_change (object, &XEXP (x, 0), newmem, 1); |
582 | } | |
583 | } | |
584 | ||
585 | break; | |
38a448ca RH |
586 | |
587 | default: | |
588 | break; | |
2055cea7 RK |
589 | } |
590 | ||
f745c7a2 AB |
591 | /* For commutative or comparison operations we've already performed |
592 | replacements. Don't try to perform them again. */ | |
593 | if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c') | |
2055cea7 | 594 | { |
f745c7a2 AB |
595 | fmt = GET_RTX_FORMAT (code); |
596 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
597 | { | |
598 | if (fmt[i] == 'e') | |
599 | validate_replace_rtx_1 (&XEXP (x, i), from, to, object); | |
600 | else if (fmt[i] == 'E') | |
601 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
602 | validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); | |
603 | } | |
2055cea7 RK |
604 | } |
605 | } | |
606 | ||
607 | /* Try replacing every occurrence of FROM in INSN with TO. After all | |
608 | changes have been made, validate by seeing if INSN is still valid. */ | |
609 | ||
610 | int | |
611 | validate_replace_rtx (from, to, insn) | |
612 | rtx from, to, insn; | |
613 | { | |
614 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
615 | return apply_change_group (); | |
616 | } | |
7506f491 | 617 | |
edfac33e JL |
618 | /* Try replacing every occurrence of FROM in INSN with TO. After all |
619 | changes have been made, validate by seeing if INSN is still valid. */ | |
620 | ||
621 | void | |
622 | validate_replace_rtx_group (from, to, insn) | |
623 | rtx from, to, insn; | |
624 | { | |
625 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
626 | } | |
627 | ||
7506f491 DE |
628 | /* Try replacing every occurrence of FROM in INSN with TO, avoiding |
629 | SET_DESTs. After all changes have been made, validate by seeing if | |
630 | INSN is still valid. */ | |
631 | ||
632 | int | |
633 | validate_replace_src (from, to, insn) | |
634 | rtx from, to, insn; | |
635 | { | |
636 | if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
637 | || GET_CODE (PATTERN (insn)) != SET) | |
638 | abort (); | |
639 | ||
640 | validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn); | |
641 | if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM) | |
642 | validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0), | |
643 | from, to, insn); | |
644 | return apply_change_group (); | |
645 | } | |
2055cea7 RK |
646 | \f |
647 | #ifdef HAVE_cc0 | |
648 | /* Return 1 if the insn using CC0 set by INSN does not contain | |
649 | any ordered tests applied to the condition codes. | |
650 | EQ and NE tests do not count. */ | |
651 | ||
652 | int | |
653 | next_insn_tests_no_inequality (insn) | |
654 | rtx insn; | |
655 | { | |
656 | register rtx next = next_cc0_user (insn); | |
657 | ||
658 | /* If there is no next insn, we have to take the conservative choice. */ | |
659 | if (next == 0) | |
660 | return 0; | |
661 | ||
662 | return ((GET_CODE (next) == JUMP_INSN | |
663 | || GET_CODE (next) == INSN | |
664 | || GET_CODE (next) == CALL_INSN) | |
665 | && ! inequality_comparisons_p (PATTERN (next))); | |
666 | } | |
667 | ||
668 | #if 0 /* This is useless since the insn that sets the cc's | |
669 | must be followed immediately by the use of them. */ | |
670 | /* Return 1 if the CC value set up by INSN is not used. */ | |
671 | ||
672 | int | |
673 | next_insns_test_no_inequality (insn) | |
674 | rtx insn; | |
675 | { | |
676 | register rtx next = NEXT_INSN (insn); | |
677 | ||
678 | for (; next != 0; next = NEXT_INSN (next)) | |
679 | { | |
680 | if (GET_CODE (next) == CODE_LABEL | |
681 | || GET_CODE (next) == BARRIER) | |
682 | return 1; | |
683 | if (GET_CODE (next) == NOTE) | |
684 | continue; | |
685 | if (inequality_comparisons_p (PATTERN (next))) | |
686 | return 0; | |
687 | if (sets_cc0_p (PATTERN (next)) == 1) | |
688 | return 1; | |
689 | if (! reg_mentioned_p (cc0_rtx, PATTERN (next))) | |
690 | return 1; | |
691 | } | |
692 | return 1; | |
693 | } | |
694 | #endif | |
695 | #endif | |
696 | \f | |
697 | /* This is used by find_single_use to locate an rtx that contains exactly one | |
698 | use of DEST, which is typically either a REG or CC0. It returns a | |
699 | pointer to the innermost rtx expression containing DEST. Appearances of | |
700 | DEST that are being used to totally replace it are not counted. */ | |
701 | ||
702 | static rtx * | |
703 | find_single_use_1 (dest, loc) | |
704 | rtx dest; | |
705 | rtx *loc; | |
706 | { | |
707 | rtx x = *loc; | |
708 | enum rtx_code code = GET_CODE (x); | |
709 | rtx *result = 0; | |
710 | rtx *this_result; | |
711 | int i; | |
6f7d635c | 712 | const char *fmt; |
2055cea7 RK |
713 | |
714 | switch (code) | |
715 | { | |
716 | case CONST_INT: | |
717 | case CONST: | |
718 | case LABEL_REF: | |
719 | case SYMBOL_REF: | |
720 | case CONST_DOUBLE: | |
721 | case CLOBBER: | |
722 | return 0; | |
723 | ||
724 | case SET: | |
725 | /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
726 | of a REG that occupies all of the REG, the insn uses DEST if | |
727 | it is mentioned in the destination or the source. Otherwise, we | |
728 | need just check the source. */ | |
729 | if (GET_CODE (SET_DEST (x)) != CC0 | |
730 | && GET_CODE (SET_DEST (x)) != PC | |
731 | && GET_CODE (SET_DEST (x)) != REG | |
732 | && ! (GET_CODE (SET_DEST (x)) == SUBREG | |
733 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
734 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
735 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
736 | == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
737 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
738 | break; | |
739 | ||
740 | return find_single_use_1 (dest, &SET_SRC (x)); | |
741 | ||
742 | case MEM: | |
743 | case SUBREG: | |
744 | return find_single_use_1 (dest, &XEXP (x, 0)); | |
38a448ca RH |
745 | |
746 | default: | |
747 | break; | |
2055cea7 RK |
748 | } |
749 | ||
750 | /* If it wasn't one of the common cases above, check each expression and | |
751 | vector of this code. Look for a unique usage of DEST. */ | |
752 | ||
753 | fmt = GET_RTX_FORMAT (code); | |
754 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
755 | { | |
756 | if (fmt[i] == 'e') | |
757 | { | |
758 | if (dest == XEXP (x, i) | |
759 | || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG | |
760 | && REGNO (dest) == REGNO (XEXP (x, i)))) | |
761 | this_result = loc; | |
762 | else | |
763 | this_result = find_single_use_1 (dest, &XEXP (x, i)); | |
764 | ||
765 | if (result == 0) | |
766 | result = this_result; | |
767 | else if (this_result) | |
768 | /* Duplicate usage. */ | |
769 | return 0; | |
770 | } | |
771 | else if (fmt[i] == 'E') | |
772 | { | |
773 | int j; | |
774 | ||
775 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
776 | { | |
777 | if (XVECEXP (x, i, j) == dest | |
778 | || (GET_CODE (dest) == REG | |
779 | && GET_CODE (XVECEXP (x, i, j)) == REG | |
780 | && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) | |
781 | this_result = loc; | |
782 | else | |
783 | this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); | |
784 | ||
785 | if (result == 0) | |
786 | result = this_result; | |
787 | else if (this_result) | |
788 | return 0; | |
789 | } | |
790 | } | |
791 | } | |
792 | ||
793 | return result; | |
794 | } | |
795 | \f | |
796 | /* See if DEST, produced in INSN, is used only a single time in the | |
797 | sequel. If so, return a pointer to the innermost rtx expression in which | |
798 | it is used. | |
799 | ||
800 | If PLOC is non-zero, *PLOC is set to the insn containing the single use. | |
801 | ||
802 | This routine will return usually zero either before flow is called (because | |
803 | there will be no LOG_LINKS notes) or after reload (because the REG_DEAD | |
804 | note can't be trusted). | |
805 | ||
806 | If DEST is cc0_rtx, we look only at the next insn. In that case, we don't | |
807 | care about REG_DEAD notes or LOG_LINKS. | |
808 | ||
809 | Otherwise, we find the single use by finding an insn that has a | |
810 | LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is | |
811 | only referenced once in that insn, we know that it must be the first | |
812 | and last insn referencing DEST. */ | |
813 | ||
814 | rtx * | |
815 | find_single_use (dest, insn, ploc) | |
816 | rtx dest; | |
817 | rtx insn; | |
818 | rtx *ploc; | |
819 | { | |
820 | rtx next; | |
821 | rtx *result; | |
822 | rtx link; | |
823 | ||
824 | #ifdef HAVE_cc0 | |
825 | if (dest == cc0_rtx) | |
826 | { | |
827 | next = NEXT_INSN (insn); | |
828 | if (next == 0 | |
829 | || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN)) | |
830 | return 0; | |
831 | ||
832 | result = find_single_use_1 (dest, &PATTERN (next)); | |
833 | if (result && ploc) | |
834 | *ploc = next; | |
835 | return result; | |
836 | } | |
837 | #endif | |
838 | ||
839 | if (reload_completed || reload_in_progress || GET_CODE (dest) != REG) | |
840 | return 0; | |
841 | ||
842 | for (next = next_nonnote_insn (insn); | |
843 | next != 0 && GET_CODE (next) != CODE_LABEL; | |
844 | next = next_nonnote_insn (next)) | |
845 | if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest)) | |
846 | { | |
847 | for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) | |
848 | if (XEXP (link, 0) == insn) | |
849 | break; | |
850 | ||
851 | if (link) | |
852 | { | |
853 | result = find_single_use_1 (dest, &PATTERN (next)); | |
854 | if (ploc) | |
855 | *ploc = next; | |
856 | return result; | |
857 | } | |
858 | } | |
859 | ||
860 | return 0; | |
861 | } | |
862 | \f | |
863 | /* Return 1 if OP is a valid general operand for machine mode MODE. | |
864 | This is either a register reference, a memory reference, | |
865 | or a constant. In the case of a memory reference, the address | |
866 | is checked for general validity for the target machine. | |
867 | ||
868 | Register and memory references must have mode MODE in order to be valid, | |
869 | but some constants have no machine mode and are valid for any mode. | |
870 | ||
871 | If MODE is VOIDmode, OP is checked for validity for whatever mode | |
872 | it has. | |
873 | ||
874 | The main use of this function is as a predicate in match_operand | |
875 | expressions in the machine description. | |
876 | ||
6dc42e49 | 877 | For an explanation of this function's behavior for registers of |
2055cea7 RK |
878 | class NO_REGS, see the comment for `register_operand'. */ |
879 | ||
880 | int | |
881 | general_operand (op, mode) | |
882 | register rtx op; | |
883 | enum machine_mode mode; | |
884 | { | |
885 | register enum rtx_code code = GET_CODE (op); | |
886 | int mode_altering_drug = 0; | |
887 | ||
888 | if (mode == VOIDmode) | |
889 | mode = GET_MODE (op); | |
890 | ||
891 | /* Don't accept CONST_INT or anything similar | |
892 | if the caller wants something floating. */ | |
893 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
894 | && GET_MODE_CLASS (mode) != MODE_INT |
895 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
896 | return 0; |
897 | ||
898 | if (CONSTANT_P (op)) | |
899 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
900 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
901 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
902 | #endif | |
903 | && LEGITIMATE_CONSTANT_P (op)); | |
904 | ||
905 | /* Except for certain constants with VOIDmode, already checked for, | |
906 | OP's mode must match MODE if MODE specifies a mode. */ | |
907 | ||
908 | if (GET_MODE (op) != mode) | |
909 | return 0; | |
910 | ||
911 | if (code == SUBREG) | |
912 | { | |
913 | #ifdef INSN_SCHEDULING | |
914 | /* On machines that have insn scheduling, we want all memory | |
915 | reference to be explicit, so outlaw paradoxical SUBREGs. */ | |
916 | if (GET_CODE (SUBREG_REG (op)) == MEM | |
917 | && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) | |
918 | return 0; | |
919 | #endif | |
920 | ||
921 | op = SUBREG_REG (op); | |
922 | code = GET_CODE (op); | |
923 | #if 0 | |
924 | /* No longer needed, since (SUBREG (MEM...)) | |
925 | will load the MEM into a reload reg in the MEM's own mode. */ | |
926 | mode_altering_drug = 1; | |
927 | #endif | |
928 | } | |
929 | ||
930 | if (code == REG) | |
931 | /* A register whose class is NO_REGS is not a general operand. */ | |
932 | return (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
933 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); | |
934 | ||
935 | if (code == MEM) | |
936 | { | |
937 | register rtx y = XEXP (op, 0); | |
938 | if (! volatile_ok && MEM_VOLATILE_P (op)) | |
939 | return 0; | |
38a448ca RH |
940 | if (GET_CODE (y) == ADDRESSOF) |
941 | return 1; | |
2055cea7 RK |
942 | /* Use the mem's mode, since it will be reloaded thus. */ |
943 | mode = GET_MODE (op); | |
944 | GO_IF_LEGITIMATE_ADDRESS (mode, y, win); | |
945 | } | |
38a448ca RH |
946 | |
947 | /* Pretend this is an operand for now; we'll run force_operand | |
948 | on its replacement in fixup_var_refs_1. */ | |
949 | if (code == ADDRESSOF) | |
950 | return 1; | |
951 | ||
2055cea7 RK |
952 | return 0; |
953 | ||
954 | win: | |
955 | if (mode_altering_drug) | |
956 | return ! mode_dependent_address_p (XEXP (op, 0)); | |
957 | return 1; | |
958 | } | |
959 | \f | |
960 | /* Return 1 if OP is a valid memory address for a memory reference | |
961 | of mode MODE. | |
962 | ||
963 | The main use of this function is as a predicate in match_operand | |
964 | expressions in the machine description. */ | |
965 | ||
966 | int | |
967 | address_operand (op, mode) | |
968 | register rtx op; | |
969 | enum machine_mode mode; | |
970 | { | |
971 | return memory_address_p (mode, op); | |
972 | } | |
973 | ||
974 | /* Return 1 if OP is a register reference of mode MODE. | |
975 | If MODE is VOIDmode, accept a register in any mode. | |
976 | ||
977 | The main use of this function is as a predicate in match_operand | |
978 | expressions in the machine description. | |
979 | ||
980 | As a special exception, registers whose class is NO_REGS are | |
981 | not accepted by `register_operand'. The reason for this change | |
982 | is to allow the representation of special architecture artifacts | |
983 | (such as a condition code register) without extending the rtl | |
984 | definitions. Since registers of class NO_REGS cannot be used | |
985 | as registers in any case where register classes are examined, | |
986 | it is most consistent to keep this function from accepting them. */ | |
987 | ||
988 | int | |
989 | register_operand (op, mode) | |
990 | register rtx op; | |
991 | enum machine_mode mode; | |
992 | { | |
993 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
994 | return 0; | |
995 | ||
996 | if (GET_CODE (op) == SUBREG) | |
997 | { | |
998 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
999 | because it is guaranteed to be reloaded into one. | |
1000 | Just make sure the MEM is valid in itself. | |
1001 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1002 | but currently it does result from (SUBREG (REG)...) where the | |
1003 | reg went on the stack.) */ | |
1004 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
1005 | return general_operand (op, mode); | |
cba057ed RK |
1006 | |
1007 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
1008 | if (GET_CODE (SUBREG_REG (op)) == REG | |
1009 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER | |
1010 | && TEST_HARD_REG_BIT (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
1011 | REGNO (SUBREG_REG (op))) | |
1012 | && (GET_MODE_SIZE (mode) | |
50dc6373 RK |
1013 | != GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) |
1014 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT | |
1015 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT) | |
cba057ed RK |
1016 | return 0; |
1017 | #endif | |
1018 | ||
2055cea7 RK |
1019 | op = SUBREG_REG (op); |
1020 | } | |
1021 | ||
14a774a9 RK |
1022 | /* If we have an ADDRESSOF, consider it valid since it will be |
1023 | converted into something that will not be a MEM. */ | |
1024 | if (GET_CODE (op) == ADDRESSOF) | |
1025 | return 1; | |
1026 | ||
2055cea7 RK |
1027 | /* We don't consider registers whose class is NO_REGS |
1028 | to be a register operand. */ | |
1029 | return (GET_CODE (op) == REG | |
1030 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1031 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1032 | } | |
1033 | ||
556ffcc5 RH |
1034 | /* Return 1 for a register in Pmode; ignore the tested mode. */ |
1035 | ||
1036 | int | |
1037 | pmode_register_operand (op, mode) | |
1038 | rtx op; | |
1039 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1040 | { | |
1041 | return register_operand (op, Pmode); | |
1042 | } | |
1043 | ||
2055cea7 RK |
1044 | /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH |
1045 | or a hard register. */ | |
1046 | ||
1047 | int | |
1048 | scratch_operand (op, mode) | |
1049 | register rtx op; | |
1050 | enum machine_mode mode; | |
1051 | { | |
a05924f9 JH |
1052 | if (GET_MODE (op) != mode && mode != VOIDmode) |
1053 | return 0; | |
1054 | ||
1055 | return (GET_CODE (op) == SCRATCH | |
1056 | || (GET_CODE (op) == REG | |
1057 | && REGNO (op) < FIRST_PSEUDO_REGISTER)); | |
2055cea7 RK |
1058 | } |
1059 | ||
1060 | /* Return 1 if OP is a valid immediate operand for mode MODE. | |
1061 | ||
1062 | The main use of this function is as a predicate in match_operand | |
1063 | expressions in the machine description. */ | |
1064 | ||
1065 | int | |
1066 | immediate_operand (op, mode) | |
1067 | register rtx op; | |
1068 | enum machine_mode mode; | |
1069 | { | |
1070 | /* Don't accept CONST_INT or anything similar | |
1071 | if the caller wants something floating. */ | |
1072 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1073 | && GET_MODE_CLASS (mode) != MODE_INT |
1074 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1075 | return 0; |
1076 | ||
ee5332b8 RH |
1077 | /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and |
1078 | result in 0/1. It seems a safe assumption that this is | |
1079 | in range for everyone. */ | |
1080 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
1081 | return 1; | |
1082 | ||
2055cea7 RK |
1083 | return (CONSTANT_P (op) |
1084 | && (GET_MODE (op) == mode || mode == VOIDmode | |
1085 | || GET_MODE (op) == VOIDmode) | |
1086 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1087 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1088 | #endif | |
1089 | && LEGITIMATE_CONSTANT_P (op)); | |
1090 | } | |
1091 | ||
1092 | /* Returns 1 if OP is an operand that is a CONST_INT. */ | |
1093 | ||
1094 | int | |
1095 | const_int_operand (op, mode) | |
1096 | register rtx op; | |
e51712db | 1097 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2055cea7 RK |
1098 | { |
1099 | return GET_CODE (op) == CONST_INT; | |
1100 | } | |
1101 | ||
1102 | /* Returns 1 if OP is an operand that is a constant integer or constant | |
1103 | floating-point number. */ | |
1104 | ||
1105 | int | |
1106 | const_double_operand (op, mode) | |
1107 | register rtx op; | |
1108 | enum machine_mode mode; | |
1109 | { | |
1110 | /* Don't accept CONST_INT or anything similar | |
1111 | if the caller wants something floating. */ | |
1112 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1113 | && GET_MODE_CLASS (mode) != MODE_INT |
1114 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1115 | return 0; |
1116 | ||
1117 | return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) | |
1118 | && (mode == VOIDmode || GET_MODE (op) == mode | |
1119 | || GET_MODE (op) == VOIDmode)); | |
1120 | } | |
1121 | ||
1122 | /* Return 1 if OP is a general operand that is not an immediate operand. */ | |
1123 | ||
1124 | int | |
1125 | nonimmediate_operand (op, mode) | |
1126 | register rtx op; | |
1127 | enum machine_mode mode; | |
1128 | { | |
1129 | return (general_operand (op, mode) && ! CONSTANT_P (op)); | |
1130 | } | |
1131 | ||
1132 | /* Return 1 if OP is a register reference or immediate value of mode MODE. */ | |
1133 | ||
1134 | int | |
1135 | nonmemory_operand (op, mode) | |
1136 | register rtx op; | |
1137 | enum machine_mode mode; | |
1138 | { | |
1139 | if (CONSTANT_P (op)) | |
1140 | { | |
1141 | /* Don't accept CONST_INT or anything similar | |
1142 | if the caller wants something floating. */ | |
1143 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1144 | && GET_MODE_CLASS (mode) != MODE_INT |
1145 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1146 | return 0; |
1147 | ||
1148 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
1149 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1150 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1151 | #endif | |
1152 | && LEGITIMATE_CONSTANT_P (op)); | |
1153 | } | |
1154 | ||
1155 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1156 | return 0; | |
1157 | ||
1158 | if (GET_CODE (op) == SUBREG) | |
1159 | { | |
1160 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
1161 | because it is guaranteed to be reloaded into one. | |
1162 | Just make sure the MEM is valid in itself. | |
1163 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1164 | but currently it does result from (SUBREG (REG)...) where the | |
1165 | reg went on the stack.) */ | |
1166 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
1167 | return general_operand (op, mode); | |
1168 | op = SUBREG_REG (op); | |
1169 | } | |
1170 | ||
1171 | /* We don't consider registers whose class is NO_REGS | |
1172 | to be a register operand. */ | |
1173 | return (GET_CODE (op) == REG | |
1174 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1175 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1176 | } | |
1177 | ||
1178 | /* Return 1 if OP is a valid operand that stands for pushing a | |
1179 | value of mode MODE onto the stack. | |
1180 | ||
1181 | The main use of this function is as a predicate in match_operand | |
1182 | expressions in the machine description. */ | |
1183 | ||
1184 | int | |
1185 | push_operand (op, mode) | |
1186 | rtx op; | |
1187 | enum machine_mode mode; | |
1188 | { | |
1189 | if (GET_CODE (op) != MEM) | |
1190 | return 0; | |
1191 | ||
aeb7ff68 | 1192 | if (mode != VOIDmode && GET_MODE (op) != mode) |
2055cea7 RK |
1193 | return 0; |
1194 | ||
1195 | op = XEXP (op, 0); | |
1196 | ||
1197 | if (GET_CODE (op) != STACK_PUSH_CODE) | |
1198 | return 0; | |
1199 | ||
1200 | return XEXP (op, 0) == stack_pointer_rtx; | |
1201 | } | |
1202 | ||
6fbe9bd8 RH |
1203 | /* Return 1 if OP is a valid operand that stands for popping a |
1204 | value of mode MODE off the stack. | |
1205 | ||
1206 | The main use of this function is as a predicate in match_operand | |
1207 | expressions in the machine description. */ | |
1208 | ||
1209 | int | |
1210 | pop_operand (op, mode) | |
1211 | rtx op; | |
1212 | enum machine_mode mode; | |
1213 | { | |
1214 | if (GET_CODE (op) != MEM) | |
1215 | return 0; | |
1216 | ||
aeb7ff68 | 1217 | if (mode != VOIDmode && GET_MODE (op) != mode) |
6fbe9bd8 RH |
1218 | return 0; |
1219 | ||
1220 | op = XEXP (op, 0); | |
1221 | ||
1222 | if (GET_CODE (op) != STACK_POP_CODE) | |
1223 | return 0; | |
1224 | ||
1225 | return XEXP (op, 0) == stack_pointer_rtx; | |
1226 | } | |
1227 | ||
2055cea7 RK |
1228 | /* Return 1 if ADDR is a valid memory address for mode MODE. */ |
1229 | ||
1230 | int | |
1231 | memory_address_p (mode, addr) | |
80cca0e1 | 1232 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2055cea7 RK |
1233 | register rtx addr; |
1234 | { | |
38a448ca RH |
1235 | if (GET_CODE (addr) == ADDRESSOF) |
1236 | return 1; | |
1237 | ||
2055cea7 RK |
1238 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); |
1239 | return 0; | |
1240 | ||
1241 | win: | |
1242 | return 1; | |
1243 | } | |
1244 | ||
1245 | /* Return 1 if OP is a valid memory reference with mode MODE, | |
1246 | including a valid address. | |
1247 | ||
1248 | The main use of this function is as a predicate in match_operand | |
1249 | expressions in the machine description. */ | |
1250 | ||
1251 | int | |
1252 | memory_operand (op, mode) | |
1253 | register rtx op; | |
1254 | enum machine_mode mode; | |
1255 | { | |
1256 | rtx inner; | |
1257 | ||
1258 | if (! reload_completed) | |
1259 | /* Note that no SUBREG is a memory operand before end of reload pass, | |
1260 | because (SUBREG (MEM...)) forces reloading into a register. */ | |
1261 | return GET_CODE (op) == MEM && general_operand (op, mode); | |
1262 | ||
1263 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1264 | return 0; | |
1265 | ||
1266 | inner = op; | |
1267 | if (GET_CODE (inner) == SUBREG) | |
1268 | inner = SUBREG_REG (inner); | |
1269 | ||
1270 | return (GET_CODE (inner) == MEM && general_operand (op, mode)); | |
1271 | } | |
1272 | ||
1273 | /* Return 1 if OP is a valid indirect memory reference with mode MODE; | |
1274 | that is, a memory reference whose address is a general_operand. */ | |
1275 | ||
1276 | int | |
1277 | indirect_operand (op, mode) | |
1278 | register rtx op; | |
1279 | enum machine_mode mode; | |
1280 | { | |
1281 | /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ | |
1282 | if (! reload_completed | |
1283 | && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) | |
1284 | { | |
1285 | register int offset = SUBREG_WORD (op) * UNITS_PER_WORD; | |
1286 | rtx inner = SUBREG_REG (op); | |
1287 | ||
f76b9db2 ILT |
1288 | if (BYTES_BIG_ENDIAN) |
1289 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op))) | |
1290 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner)))); | |
2055cea7 | 1291 | |
b0e0a0f9 RK |
1292 | if (mode != VOIDmode && GET_MODE (op) != mode) |
1293 | return 0; | |
1294 | ||
2055cea7 RK |
1295 | /* The only way that we can have a general_operand as the resulting |
1296 | address is if OFFSET is zero and the address already is an operand | |
1297 | or if the address is (plus Y (const_int -OFFSET)) and Y is an | |
1298 | operand. */ | |
1299 | ||
1300 | return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode)) | |
1301 | || (GET_CODE (XEXP (inner, 0)) == PLUS | |
1302 | && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT | |
1303 | && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset | |
1304 | && general_operand (XEXP (XEXP (inner, 0), 0), Pmode))); | |
1305 | } | |
1306 | ||
1307 | return (GET_CODE (op) == MEM | |
1308 | && memory_operand (op, mode) | |
1309 | && general_operand (XEXP (op, 0), Pmode)); | |
1310 | } | |
1311 | ||
1312 | /* Return 1 if this is a comparison operator. This allows the use of | |
1313 | MATCH_OPERATOR to recognize all the branch insns. */ | |
1314 | ||
1315 | int | |
1316 | comparison_operator (op, mode) | |
1317 | register rtx op; | |
1318 | enum machine_mode mode; | |
1319 | { | |
1320 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
1321 | && GET_RTX_CLASS (GET_CODE (op)) == '<'); | |
1322 | } | |
1323 | \f | |
1324 | /* If BODY is an insn body that uses ASM_OPERANDS, | |
1325 | return the number of operands (both input and output) in the insn. | |
1326 | Otherwise return -1. */ | |
1327 | ||
1328 | int | |
1329 | asm_noperands (body) | |
1330 | rtx body; | |
1331 | { | |
1332 | if (GET_CODE (body) == ASM_OPERANDS) | |
1333 | /* No output operands: return number of input operands. */ | |
1334 | return ASM_OPERANDS_INPUT_LENGTH (body); | |
1335 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1336 | /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ | |
1337 | return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; | |
1338 | else if (GET_CODE (body) == PARALLEL | |
1339 | && GET_CODE (XVECEXP (body, 0, 0)) == SET | |
1340 | && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) | |
1341 | { | |
1342 | /* Multiple output operands, or 1 output plus some clobbers: | |
1343 | body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ | |
1344 | int i; | |
1345 | int n_sets; | |
1346 | ||
1347 | /* Count backwards through CLOBBERs to determine number of SETs. */ | |
1348 | for (i = XVECLEN (body, 0); i > 0; i--) | |
1349 | { | |
1350 | if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) | |
1351 | break; | |
1352 | if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) | |
1353 | return -1; | |
1354 | } | |
1355 | ||
1356 | /* N_SETS is now number of output operands. */ | |
1357 | n_sets = i; | |
1358 | ||
1359 | /* Verify that all the SETs we have | |
1360 | came from a single original asm_operands insn | |
1361 | (so that invalid combinations are blocked). */ | |
1362 | for (i = 0; i < n_sets; i++) | |
1363 | { | |
1364 | rtx elt = XVECEXP (body, 0, i); | |
1365 | if (GET_CODE (elt) != SET) | |
1366 | return -1; | |
1367 | if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) | |
1368 | return -1; | |
1369 | /* If these ASM_OPERANDS rtx's came from different original insns | |
1370 | then they aren't allowed together. */ | |
1371 | if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) | |
1372 | != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) | |
1373 | return -1; | |
1374 | } | |
1375 | return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) | |
1376 | + n_sets); | |
1377 | } | |
1378 | else if (GET_CODE (body) == PARALLEL | |
1379 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1380 | { | |
1381 | /* 0 outputs, but some clobbers: | |
1382 | body is [(asm_operands ...) (clobber (reg ...))...]. */ | |
1383 | int i; | |
1384 | ||
1385 | /* Make sure all the other parallel things really are clobbers. */ | |
1386 | for (i = XVECLEN (body, 0) - 1; i > 0; i--) | |
1387 | if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) | |
1388 | return -1; | |
1389 | ||
1390 | return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); | |
1391 | } | |
1392 | else | |
1393 | return -1; | |
1394 | } | |
1395 | ||
1396 | /* Assuming BODY is an insn body that uses ASM_OPERANDS, | |
1397 | copy its operands (both input and output) into the vector OPERANDS, | |
1398 | the locations of the operands within the insn into the vector OPERAND_LOCS, | |
1399 | and the constraints for the operands into CONSTRAINTS. | |
1400 | Write the modes of the operands into MODES. | |
1401 | Return the assembler-template. | |
1402 | ||
1403 | If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, | |
1404 | we don't store that info. */ | |
1405 | ||
3cce094d | 1406 | const char * |
2055cea7 RK |
1407 | decode_asm_operands (body, operands, operand_locs, constraints, modes) |
1408 | rtx body; | |
1409 | rtx *operands; | |
1410 | rtx **operand_locs; | |
9b3142b3 | 1411 | const char **constraints; |
2055cea7 RK |
1412 | enum machine_mode *modes; |
1413 | { | |
1414 | register int i; | |
1415 | int noperands; | |
3cce094d | 1416 | const char *template = 0; |
2055cea7 RK |
1417 | |
1418 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1419 | { | |
1420 | rtx asmop = SET_SRC (body); | |
1421 | /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */ | |
1422 | ||
1423 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1; | |
1424 | ||
1425 | for (i = 1; i < noperands; i++) | |
1426 | { | |
1427 | if (operand_locs) | |
1428 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1); | |
1429 | if (operands) | |
1430 | operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1); | |
1431 | if (constraints) | |
1432 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1); | |
1433 | if (modes) | |
1434 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1); | |
1435 | } | |
1436 | ||
1437 | /* The output is in the SET. | |
1438 | Its constraint is in the ASM_OPERANDS itself. */ | |
1439 | if (operands) | |
1440 | operands[0] = SET_DEST (body); | |
1441 | if (operand_locs) | |
1442 | operand_locs[0] = &SET_DEST (body); | |
1443 | if (constraints) | |
1444 | constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); | |
1445 | if (modes) | |
1446 | modes[0] = GET_MODE (SET_DEST (body)); | |
1447 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1448 | } | |
1449 | else if (GET_CODE (body) == ASM_OPERANDS) | |
1450 | { | |
1451 | rtx asmop = body; | |
1452 | /* No output operands: BODY is (asm_operands ....). */ | |
1453 | ||
1454 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1455 | ||
1456 | /* The input operands are found in the 1st element vector. */ | |
1457 | /* Constraints for inputs are in the 2nd element vector. */ | |
1458 | for (i = 0; i < noperands; i++) | |
1459 | { | |
1460 | if (operand_locs) | |
1461 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1462 | if (operands) | |
1463 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1464 | if (constraints) | |
1465 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1466 | if (modes) | |
1467 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1468 | } | |
1469 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1470 | } | |
1471 | else if (GET_CODE (body) == PARALLEL | |
1472 | && GET_CODE (XVECEXP (body, 0, 0)) == SET) | |
1473 | { | |
1474 | rtx asmop = SET_SRC (XVECEXP (body, 0, 0)); | |
1475 | int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ | |
1476 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1477 | int nout = 0; /* Does not include CLOBBERs. */ | |
1478 | ||
1479 | /* At least one output, plus some CLOBBERs. */ | |
1480 | ||
1481 | /* The outputs are in the SETs. | |
1482 | Their constraints are in the ASM_OPERANDS itself. */ | |
1483 | for (i = 0; i < nparallel; i++) | |
1484 | { | |
1485 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
1486 | break; /* Past last SET */ | |
1487 | ||
1488 | if (operands) | |
1489 | operands[i] = SET_DEST (XVECEXP (body, 0, i)); | |
1490 | if (operand_locs) | |
1491 | operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); | |
1492 | if (constraints) | |
1493 | constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); | |
1494 | if (modes) | |
1495 | modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); | |
1496 | nout++; | |
1497 | } | |
1498 | ||
1499 | for (i = 0; i < nin; i++) | |
1500 | { | |
1501 | if (operand_locs) | |
1502 | operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i); | |
1503 | if (operands) | |
1504 | operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i); | |
1505 | if (constraints) | |
1506 | constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1507 | if (modes) | |
1508 | modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1509 | } | |
1510 | ||
1511 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1512 | } | |
1513 | else if (GET_CODE (body) == PARALLEL | |
1514 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1515 | { | |
1516 | /* No outputs, but some CLOBBERs. */ | |
1517 | ||
1518 | rtx asmop = XVECEXP (body, 0, 0); | |
1519 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1520 | ||
1521 | for (i = 0; i < nin; i++) | |
1522 | { | |
1523 | if (operand_locs) | |
1524 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1525 | if (operands) | |
1526 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1527 | if (constraints) | |
1528 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1529 | if (modes) | |
1530 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1531 | } | |
1532 | ||
1533 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1534 | } | |
1535 | ||
1536 | return template; | |
1537 | } | |
1f06ee8d | 1538 | |
1afbe1c4 RH |
1539 | /* Check if an asm_operand matches it's constraints. |
1540 | Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ | |
1f06ee8d RH |
1541 | |
1542 | int | |
1543 | asm_operand_ok (op, constraint) | |
1544 | rtx op; | |
1545 | const char *constraint; | |
1546 | { | |
1afbe1c4 RH |
1547 | int result = 0; |
1548 | ||
1f06ee8d RH |
1549 | /* Use constrain_operands after reload. */ |
1550 | if (reload_completed) | |
1551 | abort (); | |
1552 | ||
1553 | while (*constraint) | |
1554 | { | |
1555 | switch (*constraint++) | |
1556 | { | |
1557 | case '=': | |
1558 | case '+': | |
1559 | case '*': | |
1560 | case '%': | |
1561 | case '?': | |
1562 | case '!': | |
1563 | case '#': | |
1564 | case '&': | |
1565 | case ',': | |
1566 | break; | |
1567 | ||
1568 | case '0': case '1': case '2': case '3': case '4': | |
1569 | case '5': case '6': case '7': case '8': case '9': | |
1afbe1c4 RH |
1570 | /* For best results, our caller should have given us the |
1571 | proper matching constraint, but we can't actually fail | |
1572 | the check if they didn't. Indicate that results are | |
1573 | inconclusive. */ | |
1574 | result = -1; | |
1f06ee8d RH |
1575 | break; |
1576 | ||
1577 | case 'p': | |
1578 | if (address_operand (op, VOIDmode)) | |
1579 | return 1; | |
1580 | break; | |
1581 | ||
1582 | case 'm': | |
1583 | case 'V': /* non-offsettable */ | |
1584 | if (memory_operand (op, VOIDmode)) | |
1585 | return 1; | |
1586 | break; | |
1587 | ||
1588 | case 'o': /* offsettable */ | |
1589 | if (offsettable_nonstrict_memref_p (op)) | |
1590 | return 1; | |
1591 | break; | |
1592 | ||
1593 | case '<': | |
1afbe1c4 RH |
1594 | /* ??? Before flow, auto inc/dec insns are not supposed to exist, |
1595 | excepting those that expand_call created. Further, on some | |
1596 | machines which do not have generalized auto inc/dec, an inc/dec | |
1597 | is not a memory_operand. | |
1598 | ||
1599 | Match any memory and hope things are resolved after reload. */ | |
1600 | ||
1f06ee8d | 1601 | if (GET_CODE (op) == MEM |
1afbe1c4 RH |
1602 | && (1 |
1603 | || GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1f06ee8d RH |
1604 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) |
1605 | return 1; | |
1606 | break; | |
1607 | ||
1608 | case '>': | |
1609 | if (GET_CODE (op) == MEM | |
1afbe1c4 RH |
1610 | && (1 |
1611 | || GET_CODE (XEXP (op, 0)) == PRE_INC | |
1f06ee8d RH |
1612 | || GET_CODE (XEXP (op, 0)) == POST_INC)) |
1613 | return 1; | |
1614 | break; | |
1615 | ||
1616 | case 'E': | |
1617 | #ifndef REAL_ARITHMETIC | |
1618 | /* Match any floating double constant, but only if | |
1619 | we can examine the bits of it reliably. */ | |
1620 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
1621 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) | |
1622 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) | |
1623 | break; | |
1624 | #endif | |
1625 | /* FALLTHRU */ | |
1626 | ||
1627 | case 'F': | |
1628 | if (GET_CODE (op) == CONST_DOUBLE) | |
1629 | return 1; | |
1630 | break; | |
1631 | ||
1632 | case 'G': | |
1633 | if (GET_CODE (op) == CONST_DOUBLE | |
1634 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G')) | |
1635 | return 1; | |
1636 | break; | |
1637 | case 'H': | |
1638 | if (GET_CODE (op) == CONST_DOUBLE | |
1639 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H')) | |
1640 | return 1; | |
1641 | break; | |
1642 | ||
1643 | case 's': | |
1644 | if (GET_CODE (op) == CONST_INT | |
1645 | || (GET_CODE (op) == CONST_DOUBLE | |
1646 | && GET_MODE (op) == VOIDmode)) | |
1647 | break; | |
1648 | /* FALLTHRU */ | |
1649 | ||
1650 | case 'i': | |
1651 | if (CONSTANT_P (op) | |
1652 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1653 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1654 | #endif | |
1655 | ) | |
1656 | return 1; | |
1657 | break; | |
1658 | ||
1659 | case 'n': | |
1660 | if (GET_CODE (op) == CONST_INT | |
1661 | || (GET_CODE (op) == CONST_DOUBLE | |
1662 | && GET_MODE (op) == VOIDmode)) | |
1663 | return 1; | |
1664 | break; | |
1665 | ||
1666 | case 'I': | |
1667 | if (GET_CODE (op) == CONST_INT | |
1668 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')) | |
1669 | return 1; | |
1670 | break; | |
1671 | case 'J': | |
1672 | if (GET_CODE (op) == CONST_INT | |
1673 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J')) | |
1674 | return 1; | |
1675 | break; | |
1676 | case 'K': | |
1677 | if (GET_CODE (op) == CONST_INT | |
1678 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')) | |
1679 | return 1; | |
1680 | break; | |
1681 | case 'L': | |
1682 | if (GET_CODE (op) == CONST_INT | |
1683 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')) | |
1684 | return 1; | |
1685 | break; | |
1686 | case 'M': | |
1687 | if (GET_CODE (op) == CONST_INT | |
1688 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M')) | |
1689 | return 1; | |
1690 | break; | |
1691 | case 'N': | |
1692 | if (GET_CODE (op) == CONST_INT | |
1693 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N')) | |
1694 | return 1; | |
1695 | break; | |
1696 | case 'O': | |
1697 | if (GET_CODE (op) == CONST_INT | |
1698 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')) | |
1699 | return 1; | |
1700 | break; | |
1701 | case 'P': | |
1702 | if (GET_CODE (op) == CONST_INT | |
1703 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')) | |
1704 | return 1; | |
1705 | break; | |
1706 | ||
1707 | case 'X': | |
1708 | return 1; | |
1709 | ||
1710 | case 'g': | |
1711 | if (general_operand (op, VOIDmode)) | |
1712 | return 1; | |
1713 | break; | |
1714 | ||
1715 | #ifdef EXTRA_CONSTRAINT | |
1716 | case 'Q': | |
1717 | if (EXTRA_CONSTRAINT (op, 'Q')) | |
1718 | return 1; | |
1719 | break; | |
1720 | case 'R': | |
1721 | if (EXTRA_CONSTRAINT (op, 'R')) | |
1722 | return 1; | |
1723 | break; | |
1724 | case 'S': | |
1725 | if (EXTRA_CONSTRAINT (op, 'S')) | |
1726 | return 1; | |
1727 | break; | |
1728 | case 'T': | |
1729 | if (EXTRA_CONSTRAINT (op, 'T')) | |
1730 | return 1; | |
1731 | break; | |
1732 | case 'U': | |
1733 | if (EXTRA_CONSTRAINT (op, 'U')) | |
1734 | return 1; | |
1735 | break; | |
1736 | #endif | |
1737 | ||
1738 | case 'r': | |
1739 | default: | |
1740 | if (GET_MODE (op) == BLKmode) | |
1741 | break; | |
1742 | if (register_operand (op, VOIDmode)) | |
1743 | return 1; | |
1744 | break; | |
1745 | } | |
1746 | } | |
1747 | ||
1afbe1c4 | 1748 | return result; |
1f06ee8d | 1749 | } |
2055cea7 | 1750 | \f |
2055cea7 RK |
1751 | /* Given an rtx *P, if it is a sum containing an integer constant term, |
1752 | return the location (type rtx *) of the pointer to that constant term. | |
1753 | Otherwise, return a null pointer. */ | |
1754 | ||
1755 | static rtx * | |
1756 | find_constant_term_loc (p) | |
1757 | rtx *p; | |
1758 | { | |
1759 | register rtx *tem; | |
1760 | register enum rtx_code code = GET_CODE (*p); | |
1761 | ||
1762 | /* If *P IS such a constant term, P is its location. */ | |
1763 | ||
1764 | if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF | |
1765 | || code == CONST) | |
1766 | return p; | |
1767 | ||
1768 | /* Otherwise, if not a sum, it has no constant term. */ | |
1769 | ||
1770 | if (GET_CODE (*p) != PLUS) | |
1771 | return 0; | |
1772 | ||
1773 | /* If one of the summands is constant, return its location. */ | |
1774 | ||
1775 | if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) | |
1776 | && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) | |
1777 | return p; | |
1778 | ||
1779 | /* Otherwise, check each summand for containing a constant term. */ | |
1780 | ||
1781 | if (XEXP (*p, 0) != 0) | |
1782 | { | |
1783 | tem = find_constant_term_loc (&XEXP (*p, 0)); | |
1784 | if (tem != 0) | |
1785 | return tem; | |
1786 | } | |
1787 | ||
1788 | if (XEXP (*p, 1) != 0) | |
1789 | { | |
1790 | tem = find_constant_term_loc (&XEXP (*p, 1)); | |
1791 | if (tem != 0) | |
1792 | return tem; | |
1793 | } | |
1794 | ||
1795 | return 0; | |
1796 | } | |
1797 | \f | |
1798 | /* Return 1 if OP is a memory reference | |
1799 | whose address contains no side effects | |
1800 | and remains valid after the addition | |
1801 | of a positive integer less than the | |
1802 | size of the object being referenced. | |
1803 | ||
1804 | We assume that the original address is valid and do not check it. | |
1805 | ||
1806 | This uses strict_memory_address_p as a subroutine, so | |
1807 | don't use it before reload. */ | |
1808 | ||
1809 | int | |
1810 | offsettable_memref_p (op) | |
1811 | rtx op; | |
1812 | { | |
1813 | return ((GET_CODE (op) == MEM) | |
1814 | && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); | |
1815 | } | |
1816 | ||
1817 | /* Similar, but don't require a strictly valid mem ref: | |
1818 | consider pseudo-regs valid as index or base regs. */ | |
1819 | ||
1820 | int | |
1821 | offsettable_nonstrict_memref_p (op) | |
1822 | rtx op; | |
1823 | { | |
1824 | return ((GET_CODE (op) == MEM) | |
1825 | && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); | |
1826 | } | |
1827 | ||
1828 | /* Return 1 if Y is a memory address which contains no side effects | |
1829 | and would remain valid after the addition of a positive integer | |
1830 | less than the size of that mode. | |
1831 | ||
1832 | We assume that the original address is valid and do not check it. | |
1833 | We do check that it is valid for narrower modes. | |
1834 | ||
1835 | If STRICTP is nonzero, we require a strictly valid address, | |
1836 | for the sake of use in reload.c. */ | |
1837 | ||
1838 | int | |
1839 | offsettable_address_p (strictp, mode, y) | |
1840 | int strictp; | |
1841 | enum machine_mode mode; | |
1842 | register rtx y; | |
1843 | { | |
1844 | register enum rtx_code ycode = GET_CODE (y); | |
1845 | register rtx z; | |
1846 | rtx y1 = y; | |
1847 | rtx *y2; | |
13536812 | 1848 | int (*addressp) PARAMS ((enum machine_mode, rtx)) = |
341a243e | 1849 | (strictp ? strict_memory_address_p : memory_address_p); |
2055cea7 RK |
1850 | |
1851 | if (CONSTANT_ADDRESS_P (y)) | |
1852 | return 1; | |
1853 | ||
1854 | /* Adjusting an offsettable address involves changing to a narrower mode. | |
1855 | Make sure that's OK. */ | |
1856 | ||
1857 | if (mode_dependent_address_p (y)) | |
1858 | return 0; | |
1859 | ||
1860 | /* If the expression contains a constant term, | |
1861 | see if it remains valid when max possible offset is added. */ | |
1862 | ||
1863 | if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) | |
1864 | { | |
1865 | int good; | |
1866 | ||
1867 | y1 = *y2; | |
1868 | *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1); | |
1869 | /* Use QImode because an odd displacement may be automatically invalid | |
1870 | for any wider mode. But it should be valid for a single byte. */ | |
1871 | good = (*addressp) (QImode, y); | |
1872 | ||
1873 | /* In any case, restore old contents of memory. */ | |
1874 | *y2 = y1; | |
1875 | return good; | |
1876 | } | |
1877 | ||
1878 | if (ycode == PRE_DEC || ycode == PRE_INC | |
1879 | || ycode == POST_DEC || ycode == POST_INC) | |
1880 | return 0; | |
1881 | ||
1882 | /* The offset added here is chosen as the maximum offset that | |
1883 | any instruction could need to add when operating on something | |
1884 | of the specified mode. We assume that if Y and Y+c are | |
1885 | valid addresses then so is Y+d for all 0<d<c. */ | |
1886 | ||
1887 | z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1); | |
1888 | ||
1889 | /* Use QImode because an odd displacement may be automatically invalid | |
1890 | for any wider mode. But it should be valid for a single byte. */ | |
1891 | return (*addressp) (QImode, z); | |
1892 | } | |
1893 | ||
1894 | /* Return 1 if ADDR is an address-expression whose effect depends | |
1895 | on the mode of the memory reference it is used in. | |
1896 | ||
1897 | Autoincrement addressing is a typical example of mode-dependence | |
1898 | because the amount of the increment depends on the mode. */ | |
1899 | ||
1900 | int | |
1901 | mode_dependent_address_p (addr) | |
47c3ed98 | 1902 | rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */ |
2055cea7 RK |
1903 | { |
1904 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, win); | |
1905 | return 0; | |
47c3ed98 KG |
1906 | /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ |
1907 | win: ATTRIBUTE_UNUSED_LABEL | |
2055cea7 RK |
1908 | return 1; |
1909 | } | |
1910 | ||
1911 | /* Return 1 if OP is a general operand | |
1912 | other than a memory ref with a mode dependent address. */ | |
1913 | ||
1914 | int | |
1915 | mode_independent_operand (op, mode) | |
1916 | enum machine_mode mode; | |
1917 | rtx op; | |
1918 | { | |
1919 | rtx addr; | |
1920 | ||
1921 | if (! general_operand (op, mode)) | |
1922 | return 0; | |
1923 | ||
1924 | if (GET_CODE (op) != MEM) | |
1925 | return 1; | |
1926 | ||
1927 | addr = XEXP (op, 0); | |
1928 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose); | |
1929 | return 1; | |
47c3ed98 KG |
1930 | /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ |
1931 | lose: ATTRIBUTE_UNUSED_LABEL | |
2055cea7 RK |
1932 | return 0; |
1933 | } | |
1934 | ||
1935 | /* Given an operand OP that is a valid memory reference | |
1936 | which satisfies offsettable_memref_p, | |
1937 | return a new memory reference whose address has been adjusted by OFFSET. | |
1938 | OFFSET should be positive and less than the size of the object referenced. | |
1939 | */ | |
1940 | ||
1941 | rtx | |
1942 | adj_offsettable_operand (op, offset) | |
1943 | rtx op; | |
1944 | int offset; | |
1945 | { | |
1946 | register enum rtx_code code = GET_CODE (op); | |
1947 | ||
1948 | if (code == MEM) | |
1949 | { | |
1950 | register rtx y = XEXP (op, 0); | |
1951 | register rtx new; | |
1952 | ||
1953 | if (CONSTANT_ADDRESS_P (y)) | |
1954 | { | |
c5c76735 JL |
1955 | new = gen_rtx_MEM (GET_MODE (op), |
1956 | plus_constant_for_output (y, offset)); | |
2055cea7 RK |
1957 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); |
1958 | return new; | |
1959 | } | |
1960 | ||
1961 | if (GET_CODE (y) == PLUS) | |
1962 | { | |
1963 | rtx z = y; | |
1964 | register rtx *const_loc; | |
1965 | ||
1966 | op = copy_rtx (op); | |
1967 | z = XEXP (op, 0); | |
1968 | const_loc = find_constant_term_loc (&z); | |
1969 | if (const_loc) | |
1970 | { | |
1971 | *const_loc = plus_constant_for_output (*const_loc, offset); | |
1972 | return op; | |
1973 | } | |
1974 | } | |
1975 | ||
38a448ca | 1976 | new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset)); |
2055cea7 RK |
1977 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); |
1978 | return new; | |
1979 | } | |
1980 | abort (); | |
1981 | } | |
1982 | \f | |
1ccbefce RH |
1983 | /* Analyze INSN and fill in recog_data. */ |
1984 | ||
0a578fee BS |
1985 | void |
1986 | extract_insn (insn) | |
1987 | rtx insn; | |
1988 | { | |
1989 | int i; | |
1990 | int icode; | |
1991 | int noperands; | |
1992 | rtx body = PATTERN (insn); | |
1993 | ||
1ccbefce RH |
1994 | recog_data.n_operands = 0; |
1995 | recog_data.n_alternatives = 0; | |
1996 | recog_data.n_dups = 0; | |
0a578fee BS |
1997 | |
1998 | switch (GET_CODE (body)) | |
1999 | { | |
2000 | case USE: | |
2001 | case CLOBBER: | |
2002 | case ASM_INPUT: | |
2003 | case ADDR_VEC: | |
2004 | case ADDR_DIFF_VEC: | |
2005 | return; | |
2006 | ||
2007 | case SET: | |
2008 | case PARALLEL: | |
2009 | case ASM_OPERANDS: | |
1ccbefce | 2010 | recog_data.n_operands = noperands = asm_noperands (body); |
0a578fee BS |
2011 | if (noperands >= 0) |
2012 | { | |
0a578fee BS |
2013 | /* This insn is an `asm' with operands. */ |
2014 | ||
2015 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
2016 | if (noperands > MAX_RECOG_OPERANDS) | |
2017 | abort (); | |
2018 | ||
2019 | /* Now get the operand values and constraints out of the insn. */ | |
1ccbefce RH |
2020 | decode_asm_operands (body, recog_data.operand, |
2021 | recog_data.operand_loc, | |
2022 | recog_data.constraints, | |
2023 | recog_data.operand_mode); | |
0a578fee BS |
2024 | if (noperands > 0) |
2025 | { | |
1ccbefce RH |
2026 | const char *p = recog_data.constraints[0]; |
2027 | recog_data.n_alternatives = 1; | |
0a578fee | 2028 | while (*p) |
1ccbefce | 2029 | recog_data.n_alternatives += (*p++ == ','); |
0a578fee | 2030 | } |
0a578fee BS |
2031 | break; |
2032 | } | |
2033 | ||
2034 | /* FALLTHROUGH */ | |
2035 | ||
2036 | default: | |
2037 | /* Ordinary insn: recognize it, get the operands via insn_extract | |
2038 | and get the constraints. */ | |
2039 | ||
2040 | icode = recog_memoized (insn); | |
2041 | if (icode < 0) | |
2042 | fatal_insn_not_found (insn); | |
2043 | ||
a995e389 RH |
2044 | recog_data.n_operands = noperands = insn_data[icode].n_operands; |
2045 | recog_data.n_alternatives = insn_data[icode].n_alternatives; | |
2046 | recog_data.n_dups = insn_data[icode].n_dups; | |
0a578fee BS |
2047 | |
2048 | insn_extract (insn); | |
2049 | ||
2050 | for (i = 0; i < noperands; i++) | |
2051 | { | |
a995e389 | 2052 | recog_data.constraints[i] = insn_data[icode].operand[i].constraint; |
a995e389 | 2053 | recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; |
0a578fee BS |
2054 | } |
2055 | } | |
0eadeb15 | 2056 | for (i = 0; i < noperands; i++) |
1ccbefce RH |
2057 | recog_data.operand_type[i] |
2058 | = (recog_data.constraints[i][0] == '=' ? OP_OUT | |
2059 | : recog_data.constraints[i][0] == '+' ? OP_INOUT | |
2060 | : OP_IN); | |
f62a15e3 | 2061 | |
1ccbefce | 2062 | if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES) |
f62a15e3 | 2063 | abort (); |
0a578fee BS |
2064 | } |
2065 | ||
f62a15e3 BS |
2066 | /* After calling extract_insn, you can use this function to extract some |
2067 | information from the constraint strings into a more usable form. | |
2068 | The collected data is stored in recog_op_alt. */ | |
2069 | void | |
2070 | preprocess_constraints () | |
2071 | { | |
2072 | int i; | |
2073 | ||
341a243e | 2074 | memset (recog_op_alt, 0, sizeof recog_op_alt); |
1ccbefce | 2075 | for (i = 0; i < recog_data.n_operands; i++) |
f62a15e3 BS |
2076 | { |
2077 | int j; | |
2078 | struct operand_alternative *op_alt; | |
1ccbefce | 2079 | const char *p = recog_data.constraints[i]; |
f62a15e3 BS |
2080 | |
2081 | op_alt = recog_op_alt[i]; | |
2082 | ||
1ccbefce | 2083 | for (j = 0; j < recog_data.n_alternatives; j++) |
f62a15e3 BS |
2084 | { |
2085 | op_alt[j].class = NO_REGS; | |
2086 | op_alt[j].constraint = p; | |
2087 | op_alt[j].matches = -1; | |
2088 | op_alt[j].matched = -1; | |
2089 | ||
2090 | if (*p == '\0' || *p == ',') | |
2091 | { | |
2092 | op_alt[j].anything_ok = 1; | |
2093 | continue; | |
2094 | } | |
2095 | ||
2096 | for (;;) | |
2097 | { | |
2098 | char c = *p++; | |
2099 | if (c == '#') | |
2100 | do | |
2101 | c = *p++; | |
2102 | while (c != ',' && c != '\0'); | |
2103 | if (c == ',' || c == '\0') | |
2104 | break; | |
2105 | ||
2106 | switch (c) | |
2107 | { | |
2108 | case '=': case '+': case '*': case '%': | |
2109 | case 'E': case 'F': case 'G': case 'H': | |
2110 | case 's': case 'i': case 'n': | |
2111 | case 'I': case 'J': case 'K': case 'L': | |
2112 | case 'M': case 'N': case 'O': case 'P': | |
2113 | #ifdef EXTRA_CONSTRAINT | |
2114 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
2115 | #endif | |
2116 | /* These don't say anything we care about. */ | |
2117 | break; | |
2118 | ||
2119 | case '?': | |
2120 | op_alt[j].reject += 6; | |
2121 | break; | |
2122 | case '!': | |
2123 | op_alt[j].reject += 600; | |
2124 | break; | |
2125 | case '&': | |
2126 | op_alt[j].earlyclobber = 1; | |
2127 | break; | |
2128 | ||
2129 | case '0': case '1': case '2': case '3': case '4': | |
2130 | case '5': case '6': case '7': case '8': case '9': | |
2131 | op_alt[j].matches = c - '0'; | |
37c5269a | 2132 | recog_op_alt[op_alt[j].matches][j].matched = i; |
f62a15e3 BS |
2133 | break; |
2134 | ||
2135 | case 'm': | |
2136 | op_alt[j].memory_ok = 1; | |
2137 | break; | |
2138 | case '<': | |
2139 | op_alt[j].decmem_ok = 1; | |
2140 | break; | |
2141 | case '>': | |
2142 | op_alt[j].incmem_ok = 1; | |
2143 | break; | |
2144 | case 'V': | |
2145 | op_alt[j].nonoffmem_ok = 1; | |
2146 | break; | |
2147 | case 'o': | |
2148 | op_alt[j].offmem_ok = 1; | |
2149 | break; | |
2150 | case 'X': | |
2151 | op_alt[j].anything_ok = 1; | |
2152 | break; | |
2153 | ||
2154 | case 'p': | |
2155 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS]; | |
2156 | break; | |
2157 | ||
2158 | case 'g': case 'r': | |
2159 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS]; | |
2160 | break; | |
2161 | ||
2162 | default: | |
973838fd | 2163 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
f62a15e3 BS |
2164 | break; |
2165 | } | |
2166 | } | |
2167 | } | |
2168 | } | |
2169 | } | |
2170 | ||
0eadeb15 | 2171 | /* Check the operands of an insn against the insn's operand constraints |
2055cea7 | 2172 | and return 1 if they are valid. |
0eadeb15 BS |
2173 | The information about the insn's operands, constraints, operand modes |
2174 | etc. is obtained from the global variables set up by extract_insn. | |
2055cea7 RK |
2175 | |
2176 | WHICH_ALTERNATIVE is set to a number which indicates which | |
2177 | alternative of constraints was matched: 0 for the first alternative, | |
2178 | 1 for the next, etc. | |
2179 | ||
2180 | In addition, when two operands are match | |
2181 | and it happens that the output operand is (reg) while the | |
2182 | input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), | |
2183 | make the output operand look like the input. | |
2184 | This is because the output operand is the one the template will print. | |
2185 | ||
2186 | This is used in final, just before printing the assembler code and by | |
2187 | the routines that determine an insn's attribute. | |
2188 | ||
2189 | If STRICT is a positive non-zero value, it means that we have been | |
2190 | called after reload has been completed. In that case, we must | |
2191 | do all checks strictly. If it is zero, it means that we have been called | |
2192 | before reload has completed. In that case, we first try to see if we can | |
2193 | find an alternative that matches strictly. If not, we try again, this | |
2194 | time assuming that reload will fix up the insn. This provides a "best | |
2195 | guess" for the alternative and is used to compute attributes of insns prior | |
2196 | to reload. A negative value of STRICT is used for this internal call. */ | |
2197 | ||
2198 | struct funny_match | |
2199 | { | |
2200 | int this, other; | |
2201 | }; | |
2202 | ||
2203 | int | |
0eadeb15 | 2204 | constrain_operands (strict) |
2055cea7 RK |
2205 | int strict; |
2206 | { | |
9b3142b3 | 2207 | const char *constraints[MAX_RECOG_OPERANDS]; |
9e21be9d | 2208 | int matching_operands[MAX_RECOG_OPERANDS]; |
9e21be9d | 2209 | int earlyclobber[MAX_RECOG_OPERANDS]; |
2055cea7 | 2210 | register int c; |
2055cea7 RK |
2211 | |
2212 | struct funny_match funny_match[MAX_RECOG_OPERANDS]; | |
2213 | int funny_match_index; | |
2055cea7 | 2214 | |
1ccbefce | 2215 | if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0) |
2055cea7 RK |
2216 | return 1; |
2217 | ||
1ccbefce | 2218 | for (c = 0; c < recog_data.n_operands; c++) |
9e21be9d | 2219 | { |
1ccbefce | 2220 | constraints[c] = recog_data.constraints[c]; |
9e21be9d | 2221 | matching_operands[c] = -1; |
9e21be9d | 2222 | } |
2055cea7 RK |
2223 | |
2224 | which_alternative = 0; | |
2225 | ||
1ccbefce | 2226 | while (which_alternative < recog_data.n_alternatives) |
2055cea7 RK |
2227 | { |
2228 | register int opno; | |
2229 | int lose = 0; | |
2230 | funny_match_index = 0; | |
2231 | ||
1ccbefce | 2232 | for (opno = 0; opno < recog_data.n_operands; opno++) |
2055cea7 | 2233 | { |
1ccbefce | 2234 | register rtx op = recog_data.operand[opno]; |
2055cea7 | 2235 | enum machine_mode mode = GET_MODE (op); |
9b3142b3 | 2236 | register const char *p = constraints[opno]; |
2055cea7 RK |
2237 | int offset = 0; |
2238 | int win = 0; | |
2239 | int val; | |
2240 | ||
9e21be9d RK |
2241 | earlyclobber[opno] = 0; |
2242 | ||
b85f21c0 | 2243 | /* A unary operator may be accepted by the predicate, but it |
38a448ca | 2244 | is irrelevant for matching constraints. */ |
b85f21c0 ILT |
2245 | if (GET_RTX_CLASS (GET_CODE (op)) == '1') |
2246 | op = XEXP (op, 0); | |
2247 | ||
2055cea7 RK |
2248 | if (GET_CODE (op) == SUBREG) |
2249 | { | |
2250 | if (GET_CODE (SUBREG_REG (op)) == REG | |
2251 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) | |
2252 | offset = SUBREG_WORD (op); | |
2253 | op = SUBREG_REG (op); | |
2254 | } | |
2255 | ||
2256 | /* An empty constraint or empty alternative | |
2257 | allows anything which matched the pattern. */ | |
2258 | if (*p == 0 || *p == ',') | |
2259 | win = 1; | |
2260 | ||
2261 | while (*p && (c = *p++) != ',') | |
2262 | switch (c) | |
2263 | { | |
c5c76735 JL |
2264 | case '?': case '!': case '*': case '%': |
2265 | case '=': case '+': | |
2055cea7 RK |
2266 | break; |
2267 | ||
4d3067db RK |
2268 | case '#': |
2269 | /* Ignore rest of this alternative as far as | |
2270 | constraint checking is concerned. */ | |
2271 | while (*p && *p != ',') | |
2272 | p++; | |
2273 | break; | |
2274 | ||
9e21be9d RK |
2275 | case '&': |
2276 | earlyclobber[opno] = 1; | |
2277 | break; | |
2278 | ||
c5c76735 JL |
2279 | case '0': case '1': case '2': case '3': case '4': |
2280 | case '5': case '6': case '7': case '8': case '9': | |
2281 | ||
2055cea7 RK |
2282 | /* This operand must be the same as a previous one. |
2283 | This kind of constraint is used for instructions such | |
2284 | as add when they take only two operands. | |
2285 | ||
2286 | Note that the lower-numbered operand is passed first. | |
2287 | ||
2288 | If we are not testing strictly, assume that this constraint | |
2289 | will be satisfied. */ | |
2290 | if (strict < 0) | |
2291 | val = 1; | |
2292 | else | |
62674ffe | 2293 | { |
1ccbefce RH |
2294 | rtx op1 = recog_data.operand[c - '0']; |
2295 | rtx op2 = recog_data.operand[opno]; | |
62674ffe JH |
2296 | |
2297 | /* A unary operator may be accepted by the predicate, | |
2298 | but it is irrelevant for matching constraints. */ | |
2299 | if (GET_RTX_CLASS (GET_CODE (op1)) == '1') | |
2300 | op1 = XEXP (op1, 0); | |
2301 | if (GET_RTX_CLASS (GET_CODE (op2)) == '1') | |
2302 | op2 = XEXP (op2, 0); | |
2303 | ||
2304 | val = operands_match_p (op1, op2); | |
2305 | } | |
2055cea7 | 2306 | |
9e21be9d RK |
2307 | matching_operands[opno] = c - '0'; |
2308 | matching_operands[c - '0'] = opno; | |
2309 | ||
2055cea7 RK |
2310 | if (val != 0) |
2311 | win = 1; | |
2312 | /* If output is *x and input is *--x, | |
2313 | arrange later to change the output to *--x as well, | |
2314 | since the output op is the one that will be printed. */ | |
2315 | if (val == 2 && strict > 0) | |
2316 | { | |
2317 | funny_match[funny_match_index].this = opno; | |
2318 | funny_match[funny_match_index++].other = c - '0'; | |
2319 | } | |
2320 | break; | |
2321 | ||
2322 | case 'p': | |
2323 | /* p is used for address_operands. When we are called by | |
a8647766 RK |
2324 | gen_reload, no one will have checked that the address is |
2325 | strictly valid, i.e., that all pseudos requiring hard regs | |
2326 | have gotten them. */ | |
2055cea7 | 2327 | if (strict <= 0 |
1ccbefce | 2328 | || (strict_memory_address_p (recog_data.operand_mode[opno], |
0eadeb15 | 2329 | op))) |
2055cea7 RK |
2330 | win = 1; |
2331 | break; | |
2332 | ||
2333 | /* No need to check general_operand again; | |
2334 | it was done in insn-recog.c. */ | |
2335 | case 'g': | |
2336 | /* Anything goes unless it is a REG and really has a hard reg | |
2337 | but the hard reg is not in the class GENERAL_REGS. */ | |
2338 | if (strict < 0 | |
2339 | || GENERAL_REGS == ALL_REGS | |
2340 | || GET_CODE (op) != REG | |
3c3eeea6 RK |
2341 | || (reload_in_progress |
2342 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2055cea7 RK |
2343 | || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) |
2344 | win = 1; | |
2345 | break; | |
2346 | ||
2347 | case 'r': | |
2348 | if (strict < 0 | |
2349 | || (strict == 0 | |
2350 | && GET_CODE (op) == REG | |
2351 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2352 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
2353 | || (GET_CODE (op) == REG | |
5a19ad3f RK |
2354 | && ((GENERAL_REGS == ALL_REGS |
2355 | && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
2055cea7 RK |
2356 | || reg_fits_class_p (op, GENERAL_REGS, |
2357 | offset, mode)))) | |
2358 | win = 1; | |
2359 | break; | |
2360 | ||
2361 | case 'X': | |
0f41302f MS |
2362 | /* This is used for a MATCH_SCRATCH in the cases when |
2363 | we don't actually need anything. So anything goes | |
2364 | any time. */ | |
2055cea7 RK |
2365 | win = 1; |
2366 | break; | |
2367 | ||
2368 | case 'm': | |
2369 | if (GET_CODE (op) == MEM | |
2370 | /* Before reload, accept what reload can turn into mem. */ | |
3c3eeea6 RK |
2371 | || (strict < 0 && CONSTANT_P (op)) |
2372 | /* During reload, accept a pseudo */ | |
2373 | || (reload_in_progress && GET_CODE (op) == REG | |
2374 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2375 | win = 1; |
2376 | break; | |
2377 | ||
2378 | case '<': | |
2379 | if (GET_CODE (op) == MEM | |
2380 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
2381 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
2382 | win = 1; | |
2383 | break; | |
2384 | ||
2385 | case '>': | |
2386 | if (GET_CODE (op) == MEM | |
2387 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
2388 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
2389 | win = 1; | |
2390 | break; | |
2391 | ||
2392 | case 'E': | |
b990f635 | 2393 | #ifndef REAL_ARITHMETIC |
2055cea7 RK |
2394 | /* Match any CONST_DOUBLE, but only if |
2395 | we can examine the bits of it reliably. */ | |
2396 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
9e4223f2 | 2397 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
d1b765a5 | 2398 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
2055cea7 | 2399 | break; |
b990f635 | 2400 | #endif |
2055cea7 RK |
2401 | if (GET_CODE (op) == CONST_DOUBLE) |
2402 | win = 1; | |
2403 | break; | |
2404 | ||
2405 | case 'F': | |
2406 | if (GET_CODE (op) == CONST_DOUBLE) | |
2407 | win = 1; | |
2408 | break; | |
2409 | ||
2410 | case 'G': | |
2411 | case 'H': | |
2412 | if (GET_CODE (op) == CONST_DOUBLE | |
2413 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
2414 | win = 1; | |
2415 | break; | |
2416 | ||
2417 | case 's': | |
2418 | if (GET_CODE (op) == CONST_INT | |
2419 | || (GET_CODE (op) == CONST_DOUBLE | |
2420 | && GET_MODE (op) == VOIDmode)) | |
2421 | break; | |
2422 | case 'i': | |
2423 | if (CONSTANT_P (op)) | |
2424 | win = 1; | |
2425 | break; | |
2426 | ||
2427 | case 'n': | |
2428 | if (GET_CODE (op) == CONST_INT | |
2429 | || (GET_CODE (op) == CONST_DOUBLE | |
2430 | && GET_MODE (op) == VOIDmode)) | |
2431 | win = 1; | |
2432 | break; | |
2433 | ||
2434 | case 'I': | |
2435 | case 'J': | |
2436 | case 'K': | |
2437 | case 'L': | |
2438 | case 'M': | |
2439 | case 'N': | |
2440 | case 'O': | |
2441 | case 'P': | |
2442 | if (GET_CODE (op) == CONST_INT | |
2443 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
2444 | win = 1; | |
2445 | break; | |
2446 | ||
2447 | #ifdef EXTRA_CONSTRAINT | |
2448 | case 'Q': | |
2449 | case 'R': | |
2450 | case 'S': | |
2451 | case 'T': | |
2452 | case 'U': | |
2453 | if (EXTRA_CONSTRAINT (op, c)) | |
2454 | win = 1; | |
2455 | break; | |
2456 | #endif | |
2457 | ||
2458 | case 'V': | |
2459 | if (GET_CODE (op) == MEM | |
69f724c0 JL |
2460 | && ((strict > 0 && ! offsettable_memref_p (op)) |
2461 | || (strict < 0 | |
2462 | && !(CONSTANT_P (op) || GET_CODE (op) == MEM)) | |
2463 | || (reload_in_progress | |
2464 | && !(GET_CODE (op) == REG | |
2465 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))) | |
2055cea7 RK |
2466 | win = 1; |
2467 | break; | |
2468 | ||
2469 | case 'o': | |
2470 | if ((strict > 0 && offsettable_memref_p (op)) | |
2471 | || (strict == 0 && offsettable_nonstrict_memref_p (op)) | |
2472 | /* Before reload, accept what reload can handle. */ | |
2473 | || (strict < 0 | |
3c3eeea6 RK |
2474 | && (CONSTANT_P (op) || GET_CODE (op) == MEM)) |
2475 | /* During reload, accept a pseudo */ | |
2476 | || (reload_in_progress && GET_CODE (op) == REG | |
2477 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2478 | win = 1; |
2479 | break; | |
2480 | ||
2481 | default: | |
2482 | if (strict < 0 | |
2483 | || (strict == 0 | |
2484 | && GET_CODE (op) == REG | |
2485 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2486 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
2487 | || (GET_CODE (op) == REG | |
2488 | && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c), | |
2489 | offset, mode))) | |
2490 | win = 1; | |
2491 | } | |
2492 | ||
2493 | constraints[opno] = p; | |
2494 | /* If this operand did not win somehow, | |
2495 | this alternative loses. */ | |
2496 | if (! win) | |
2497 | lose = 1; | |
2498 | } | |
2499 | /* This alternative won; the operands are ok. | |
2500 | Change whichever operands this alternative says to change. */ | |
2501 | if (! lose) | |
2502 | { | |
9e21be9d RK |
2503 | int opno, eopno; |
2504 | ||
2505 | /* See if any earlyclobber operand conflicts with some other | |
2506 | operand. */ | |
2507 | ||
2508 | if (strict > 0) | |
1ccbefce | 2509 | for (eopno = 0; eopno < recog_data.n_operands; eopno++) |
62946075 RS |
2510 | /* Ignore earlyclobber operands now in memory, |
2511 | because we would often report failure when we have | |
2512 | two memory operands, one of which was formerly a REG. */ | |
2513 | if (earlyclobber[eopno] | |
1ccbefce RH |
2514 | && GET_CODE (recog_data.operand[eopno]) == REG) |
2515 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
2516 | if ((GET_CODE (recog_data.operand[opno]) == MEM | |
2517 | || recog_data.operand_type[opno] != OP_OUT) | |
9e21be9d | 2518 | && opno != eopno |
0f41302f | 2519 | /* Ignore things like match_operator operands. */ |
1ccbefce | 2520 | && *recog_data.constraints[opno] != 0 |
9e21be9d | 2521 | && ! (matching_operands[opno] == eopno |
1ccbefce RH |
2522 | && operands_match_p (recog_data.operand[opno], |
2523 | recog_data.operand[eopno])) | |
2524 | && ! safe_from_earlyclobber (recog_data.operand[opno], | |
2525 | recog_data.operand[eopno])) | |
9e21be9d RK |
2526 | lose = 1; |
2527 | ||
2528 | if (! lose) | |
2055cea7 | 2529 | { |
9e21be9d RK |
2530 | while (--funny_match_index >= 0) |
2531 | { | |
1ccbefce RH |
2532 | recog_data.operand[funny_match[funny_match_index].other] |
2533 | = recog_data.operand[funny_match[funny_match_index].this]; | |
9e21be9d RK |
2534 | } |
2535 | ||
2536 | return 1; | |
2055cea7 | 2537 | } |
2055cea7 RK |
2538 | } |
2539 | ||
2540 | which_alternative++; | |
2541 | } | |
2542 | ||
2543 | /* If we are about to reject this, but we are not to test strictly, | |
2544 | try a very loose test. Only return failure if it fails also. */ | |
2545 | if (strict == 0) | |
0eadeb15 | 2546 | return constrain_operands (-1); |
2055cea7 RK |
2547 | else |
2548 | return 0; | |
2549 | } | |
2550 | ||
2551 | /* Return 1 iff OPERAND (assumed to be a REG rtx) | |
38a448ca | 2552 | is a hard reg in class CLASS when its regno is offset by OFFSET |
2055cea7 RK |
2553 | and changed to mode MODE. |
2554 | If REG occupies multiple hard regs, all of them must be in CLASS. */ | |
2555 | ||
2556 | int | |
2557 | reg_fits_class_p (operand, class, offset, mode) | |
2558 | rtx operand; | |
2559 | register enum reg_class class; | |
2560 | int offset; | |
2561 | enum machine_mode mode; | |
2562 | { | |
2563 | register int regno = REGNO (operand); | |
2564 | if (regno < FIRST_PSEUDO_REGISTER | |
2565 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2566 | regno + offset)) | |
2567 | { | |
2568 | register int sr; | |
2569 | regno += offset; | |
2570 | for (sr = HARD_REGNO_NREGS (regno, mode) - 1; | |
2571 | sr > 0; sr--) | |
2572 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2573 | regno + sr)) | |
2574 | break; | |
2575 | return sr == 0; | |
2576 | } | |
2577 | ||
2578 | return 0; | |
2579 | } | |
ca545bb5 | 2580 | \f |
d3a923ee | 2581 | /* Split all insns in the function. If UPD_LIFE, update life info after. */ |
ca545bb5 BM |
2582 | |
2583 | void | |
d3a923ee RH |
2584 | split_all_insns (upd_life) |
2585 | int upd_life; | |
ca545bb5 | 2586 | { |
d3a923ee RH |
2587 | sbitmap blocks; |
2588 | int changed; | |
2589 | int i; | |
2590 | ||
2591 | blocks = sbitmap_alloc (n_basic_blocks); | |
2592 | sbitmap_zero (blocks); | |
2593 | changed = 0; | |
ca545bb5 | 2594 | |
d3a923ee | 2595 | for (i = n_basic_blocks - 1; i >= 0; --i) |
ca545bb5 | 2596 | { |
d3a923ee RH |
2597 | basic_block bb = BASIC_BLOCK (i); |
2598 | rtx insn, next; | |
ca545bb5 | 2599 | |
d3a923ee | 2600 | for (insn = bb->head; insn ; insn = next) |
ca545bb5 | 2601 | { |
d3a923ee | 2602 | rtx set; |
ca545bb5 | 2603 | |
d3a923ee RH |
2604 | /* Can't use `next_real_insn' because that might go across |
2605 | CODE_LABELS and short-out basic blocks. */ | |
2606 | next = NEXT_INSN (insn); | |
2607 | if (GET_CODE (insn) != INSN) | |
2608 | ; | |
ca545bb5 | 2609 | |
d3a923ee RH |
2610 | /* Don't split no-op move insns. These should silently |
2611 | disappear later in final. Splitting such insns would | |
2612 | break the code that handles REG_NO_CONFLICT blocks. */ | |
ca545bb5 | 2613 | |
d3a923ee RH |
2614 | else if ((set = single_set (insn)) != NULL |
2615 | && rtx_equal_p (SET_SRC (set), SET_DEST (set))) | |
ca545bb5 | 2616 | { |
d3a923ee RH |
2617 | /* Nops get in the way while scheduling, so delete them |
2618 | now if register allocation has already been done. It | |
2619 | is too risky to try to do this before register | |
2620 | allocation, and there are unlikely to be very many | |
2621 | nops then anyways. */ | |
2622 | if (reload_completed) | |
2623 | { | |
2624 | PUT_CODE (insn, NOTE); | |
2625 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2626 | NOTE_SOURCE_FILE (insn) = 0; | |
2627 | } | |
ca545bb5 | 2628 | } |
d3a923ee | 2629 | else |
ca545bb5 | 2630 | { |
d3a923ee RH |
2631 | /* Split insns here to get max fine-grain parallelism. */ |
2632 | rtx first = PREV_INSN (insn); | |
2633 | rtx last = try_split (PATTERN (insn), insn, 1); | |
2634 | ||
2635 | if (last != insn) | |
ca545bb5 | 2636 | { |
d3a923ee RH |
2637 | SET_BIT (blocks, i); |
2638 | changed = 1; | |
2639 | ||
2640 | /* try_split returns the NOTE that INSN became. */ | |
2641 | first = NEXT_INSN (first); | |
2642 | PUT_CODE (insn, NOTE); | |
2643 | NOTE_SOURCE_FILE (insn) = 0; | |
2644 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2645 | ||
2646 | if (insn == bb->end) | |
2647 | { | |
2648 | bb->end = last; | |
2649 | break; | |
2650 | } | |
ca545bb5 BM |
2651 | } |
2652 | } | |
d3a923ee RH |
2653 | |
2654 | if (insn == bb->end) | |
2655 | break; | |
ca545bb5 BM |
2656 | } |
2657 | ||
d3a923ee RH |
2658 | /* ??? When we're called from just after reload, the CFG is in bad |
2659 | shape, and we may have fallen off the end. This could be fixed | |
2660 | by having reload not try to delete unreachable code. Otherwise | |
2661 | assert we found the end insn. */ | |
2662 | if (insn == NULL && upd_life) | |
2663 | abort (); | |
ca545bb5 | 2664 | } |
d3a923ee RH |
2665 | |
2666 | if (changed && upd_life) | |
2667 | { | |
c88e8206 | 2668 | compute_bb_for_insn (get_max_uid ()); |
d3a923ee | 2669 | count_or_remove_death_notes (blocks, 1); |
49c3bb12 | 2670 | update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES); |
d3a923ee RH |
2671 | } |
2672 | ||
2673 | sbitmap_free (blocks); | |
ca545bb5 | 2674 | } |
ede7cd44 RH |
2675 | \f |
2676 | #ifdef HAVE_peephole2 | |
d3a923ee RH |
2677 | /* This is the last insn we'll allow recog_next_insn to consider. */ |
2678 | static rtx recog_last_allowed_insn; | |
2679 | ||
ede7cd44 RH |
2680 | /* Return the Nth non-note insn after INSN, or return NULL_RTX if it does |
2681 | not exist. Used by the recognizer to find the next insn to match in a | |
2682 | multi-insn pattern. */ | |
2683 | rtx | |
2684 | recog_next_insn (insn, n) | |
2685 | rtx insn; | |
2686 | int n; | |
2687 | { | |
d3a923ee | 2688 | if (insn != NULL_RTX) |
ede7cd44 | 2689 | { |
d3a923ee RH |
2690 | while (n > 0) |
2691 | { | |
2692 | if (insn == recog_last_allowed_insn) | |
2693 | return NULL_RTX; | |
ede7cd44 | 2694 | |
d3a923ee RH |
2695 | insn = NEXT_INSN (insn); |
2696 | if (insn == NULL_RTX) | |
2697 | break; | |
ede7cd44 | 2698 | |
d3a923ee RH |
2699 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') |
2700 | n -= 1; | |
2701 | } | |
ede7cd44 RH |
2702 | } |
2703 | ||
2704 | return insn; | |
2705 | } | |
2706 | ||
2707 | /* Perform the peephole2 optimization pass. */ | |
2708 | void | |
2709 | peephole2_optimize (dump_file) | |
2710 | FILE *dump_file ATTRIBUTE_UNUSED; | |
2711 | { | |
d3a923ee RH |
2712 | rtx insn, prev; |
2713 | int i, changed; | |
2714 | sbitmap blocks; | |
ede7cd44 | 2715 | |
d3a923ee RH |
2716 | /* ??? TODO: Arrange with resource.c to start at bb->global_live_at_end |
2717 | and backtrack insn by insn as we proceed through the block. In this | |
2718 | way we'll not need to keep searching forward from the beginning of | |
2719 | basic blocks to find register life info. */ | |
ede7cd44 | 2720 | |
d3a923ee | 2721 | init_resource_info (NULL); |
ede7cd44 | 2722 | |
d3a923ee RH |
2723 | blocks = sbitmap_alloc (n_basic_blocks); |
2724 | sbitmap_zero (blocks); | |
2725 | changed = 0; | |
2726 | ||
2727 | for (i = n_basic_blocks - 1; i >= 0; --i) | |
ede7cd44 | 2728 | { |
d3a923ee RH |
2729 | basic_block bb = BASIC_BLOCK (i); |
2730 | ||
2731 | /* Since we don't update life info until the very end, we can't | |
2732 | allow matching instructions that we've replaced before. Walk | |
2733 | backward through the basic block so that we don't have to | |
2734 | care about subsequent life info; recog_last_allowed_insn to | |
2735 | restrict how far forward we will allow the match to proceed. */ | |
ede7cd44 | 2736 | |
3071fab5 | 2737 | recog_last_allowed_insn = NEXT_INSN (bb->end); |
d3a923ee RH |
2738 | for (insn = bb->end; ; insn = prev) |
2739 | { | |
2740 | prev = PREV_INSN (insn); | |
2741 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
ede7cd44 | 2742 | { |
d3a923ee RH |
2743 | rtx try, last_insn; |
2744 | ||
2745 | try = peephole2_insns (PATTERN (insn), insn, &last_insn); | |
2746 | if (try != NULL) | |
2747 | { | |
2748 | flow_delete_insn_chain (insn, last_insn); | |
2749 | try = emit_insn_after (try, prev); | |
2750 | ||
2751 | if (last_insn == bb->end) | |
2752 | bb->end = try; | |
2753 | if (insn == bb->head) | |
2754 | bb->head = NEXT_INSN (prev); | |
2755 | ||
3071fab5 | 2756 | recog_last_allowed_insn = NEXT_INSN (prev); |
d3a923ee RH |
2757 | SET_BIT (blocks, i); |
2758 | changed = 1; | |
2759 | } | |
ede7cd44 | 2760 | } |
d3a923ee RH |
2761 | |
2762 | if (insn == bb->head) | |
2763 | break; | |
ede7cd44 RH |
2764 | } |
2765 | } | |
2766 | ||
2767 | free_resource_info (); | |
d3a923ee | 2768 | |
c88e8206 | 2769 | compute_bb_for_insn (get_max_uid ()); |
d3a923ee | 2770 | count_or_remove_death_notes (blocks, 1); |
49c3bb12 | 2771 | update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES); |
ede7cd44 RH |
2772 | } |
2773 | #endif |