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2055cea7 | 1 | /* Subroutines used by or related to instruction recognition. |
1f06ee8d | 2 | Copyright (C) 1987, 1988, 91-98, 1999 Free Software Foundation, Inc. |
2055cea7 RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
2055cea7 RK |
20 | |
21 | ||
22 | #include "config.h" | |
670ee920 | 23 | #include "system.h" |
38a448ca | 24 | #include "rtl.h" |
2055cea7 RK |
25 | #include "insn-config.h" |
26 | #include "insn-attr.h" | |
27 | #include "insn-flags.h" | |
28 | #include "insn-codes.h" | |
29 | #include "recog.h" | |
30 | #include "regs.h" | |
31 | #include "hard-reg-set.h" | |
49ad7cfa | 32 | #include "function.h" |
2055cea7 RK |
33 | #include "flags.h" |
34 | #include "real.h" | |
7f7f8214 | 35 | #include "toplev.h" |
ca545bb5 | 36 | #include "basic-block.h" |
2055cea7 RK |
37 | |
38 | #ifndef STACK_PUSH_CODE | |
39 | #ifdef STACK_GROWS_DOWNWARD | |
40 | #define STACK_PUSH_CODE PRE_DEC | |
41 | #else | |
42 | #define STACK_PUSH_CODE PRE_INC | |
43 | #endif | |
44 | #endif | |
45 | ||
6fbe9bd8 RH |
46 | #ifndef STACK_POP_CODE |
47 | #ifdef STACK_GROWS_DOWNWARD | |
48 | #define STACK_POP_CODE POST_INC | |
49 | #else | |
50 | #define STACK_POP_CODE POST_DEC | |
51 | #endif | |
52 | #endif | |
53 | ||
61719ba7 BS |
54 | static void validate_replace_rtx_1 PROTO((rtx *, rtx, rtx, rtx)); |
55 | static rtx *find_single_use_1 PROTO((rtx, rtx *)); | |
56 | static rtx *find_constant_term_loc PROTO((rtx *)); | |
57 | static int insn_invalid_p PROTO((rtx)); | |
2055cea7 RK |
58 | |
59 | /* Nonzero means allow operands to be volatile. | |
60 | This should be 0 if you are generating rtl, such as if you are calling | |
61 | the functions in optabs.c and expmed.c (most of the time). | |
62 | This should be 1 if all valid insns need to be recognized, | |
63 | such as in regclass.c and final.c and reload.c. | |
64 | ||
65 | init_recog and init_recog_no_volatile are responsible for setting this. */ | |
66 | ||
67 | int volatile_ok; | |
68 | ||
0eadeb15 BS |
69 | /* The next variables are set up by extract_insn. The first four of them |
70 | are also set up during insn_extract. */ | |
0a578fee BS |
71 | |
72 | /* Indexed by N, gives value of operand N. */ | |
73 | rtx recog_operand[MAX_RECOG_OPERANDS]; | |
74 | ||
75 | /* Indexed by N, gives location where operand N was found. */ | |
76 | rtx *recog_operand_loc[MAX_RECOG_OPERANDS]; | |
77 | ||
78 | /* Indexed by N, gives location where the Nth duplicate-appearance of | |
79 | an operand was found. This is something that matched MATCH_DUP. */ | |
80 | rtx *recog_dup_loc[MAX_RECOG_OPERANDS]; | |
81 | ||
82 | /* Indexed by N, gives the operand number that was duplicated in the | |
83 | Nth duplicate-appearance of an operand. */ | |
84 | char recog_dup_num[MAX_RECOG_OPERANDS]; | |
85 | ||
0a578fee BS |
86 | /* The number of operands of the insn. */ |
87 | int recog_n_operands; | |
88 | ||
89 | /* The number of MATCH_DUPs in the insn. */ | |
90 | int recog_n_dups; | |
91 | ||
92 | /* The number of alternatives in the constraints for the insn. */ | |
93 | int recog_n_alternatives; | |
94 | ||
95 | /* Indexed by N, gives the mode of operand N. */ | |
96 | enum machine_mode recog_operand_mode[MAX_RECOG_OPERANDS]; | |
97 | ||
98 | /* Indexed by N, gives the constraint string for operand N. */ | |
9b3142b3 | 99 | const char *recog_constraints[MAX_RECOG_OPERANDS]; |
0a578fee | 100 | |
0eadeb15 BS |
101 | /* Indexed by N, gives the type (in, out, inout) for operand N. */ |
102 | enum op_type recog_op_type[MAX_RECOG_OPERANDS]; | |
103 | ||
0a578fee BS |
104 | #ifndef REGISTER_CONSTRAINTS |
105 | /* Indexed by N, nonzero if operand N should be an address. */ | |
106 | char recog_operand_address_p[MAX_RECOG_OPERANDS]; | |
107 | #endif | |
108 | ||
f62a15e3 BS |
109 | /* Contains a vector of operand_alternative structures for every operand. |
110 | Set up by preprocess_constraints. */ | |
111 | struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES]; | |
112 | ||
2055cea7 RK |
113 | /* On return from `constrain_operands', indicate which alternative |
114 | was satisfied. */ | |
115 | ||
116 | int which_alternative; | |
117 | ||
118 | /* Nonzero after end of reload pass. | |
119 | Set to 1 or 0 by toplev.c. | |
120 | Controls the significance of (SUBREG (MEM)). */ | |
121 | ||
122 | int reload_completed; | |
123 | ||
124 | /* Initialize data used by the function `recog'. | |
125 | This must be called once in the compilation of a function | |
126 | before any insn recognition may be done in the function. */ | |
127 | ||
128 | void | |
129 | init_recog_no_volatile () | |
130 | { | |
131 | volatile_ok = 0; | |
132 | } | |
133 | ||
e0069e43 | 134 | void |
2055cea7 RK |
135 | init_recog () |
136 | { | |
137 | volatile_ok = 1; | |
138 | } | |
139 | ||
140 | /* Try recognizing the instruction INSN, | |
141 | and return the code number that results. | |
9faa82d8 | 142 | Remember the code so that repeated calls do not |
2055cea7 RK |
143 | need to spend the time for actual rerecognition. |
144 | ||
145 | This function is the normal interface to instruction recognition. | |
146 | The automatically-generated function `recog' is normally called | |
147 | through this one. (The only exception is in combine.c.) */ | |
148 | ||
149 | int | |
150 | recog_memoized (insn) | |
151 | rtx insn; | |
152 | { | |
153 | if (INSN_CODE (insn) < 0) | |
9e4223f2 | 154 | INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR); |
2055cea7 RK |
155 | return INSN_CODE (insn); |
156 | } | |
157 | \f | |
158 | /* Check that X is an insn-body for an `asm' with operands | |
159 | and that the operands mentioned in it are legitimate. */ | |
160 | ||
161 | int | |
162 | check_asm_operands (x) | |
163 | rtx x; | |
164 | { | |
1f06ee8d | 165 | int noperands; |
2055cea7 | 166 | rtx *operands; |
9b3142b3 | 167 | const char **constraints; |
2055cea7 RK |
168 | int i; |
169 | ||
1f06ee8d RH |
170 | /* Post-reload, be more strict with things. */ |
171 | if (reload_completed) | |
172 | { | |
173 | /* ??? Doh! We've not got the wrapping insn. Cook one up. */ | |
174 | extract_insn (make_insn_raw (x)); | |
175 | constrain_operands (1); | |
176 | return which_alternative >= 0; | |
177 | } | |
178 | ||
179 | noperands = asm_noperands (x); | |
2055cea7 RK |
180 | if (noperands < 0) |
181 | return 0; | |
182 | if (noperands == 0) | |
183 | return 1; | |
184 | ||
185 | operands = (rtx *) alloca (noperands * sizeof (rtx)); | |
9b3142b3 | 186 | constraints = (const char **) alloca (noperands * sizeof (char *)); |
1f06ee8d RH |
187 | |
188 | decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR); | |
2055cea7 RK |
189 | |
190 | for (i = 0; i < noperands; i++) | |
1f06ee8d | 191 | { |
9b3142b3 | 192 | const char *c = constraints[i]; |
1afbe1c4 RH |
193 | if (c[0] == '%') |
194 | c++; | |
195 | if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0') | |
1f06ee8d RH |
196 | c = constraints[c[0] - '0']; |
197 | ||
198 | if (! asm_operand_ok (operands[i], c)) | |
199 | return 0; | |
200 | } | |
2055cea7 RK |
201 | |
202 | return 1; | |
203 | } | |
204 | \f | |
41a972a9 | 205 | /* Static data for the next two routines. */ |
2055cea7 | 206 | |
41a972a9 MM |
207 | typedef struct change_t |
208 | { | |
209 | rtx object; | |
210 | int old_code; | |
211 | rtx *loc; | |
212 | rtx old; | |
213 | } change_t; | |
2055cea7 | 214 | |
41a972a9 MM |
215 | static change_t *changes; |
216 | static int changes_allocated; | |
2055cea7 RK |
217 | |
218 | static int num_changes = 0; | |
219 | ||
220 | /* Validate a proposed change to OBJECT. LOC is the location in the rtl for | |
221 | at which NEW will be placed. If OBJECT is zero, no validation is done, | |
222 | the change is simply made. | |
223 | ||
224 | Two types of objects are supported: If OBJECT is a MEM, memory_address_p | |
225 | will be called with the address and mode as parameters. If OBJECT is | |
226 | an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with | |
227 | the change in place. | |
228 | ||
229 | IN_GROUP is non-zero if this is part of a group of changes that must be | |
230 | performed as a group. In that case, the changes will be stored. The | |
231 | function `apply_change_group' will validate and apply the changes. | |
232 | ||
233 | If IN_GROUP is zero, this is a single change. Try to recognize the insn | |
234 | or validate the memory reference with the change applied. If the result | |
235 | is not valid for the machine, suppress the change and return zero. | |
236 | Otherwise, perform the change and return 1. */ | |
237 | ||
238 | int | |
239 | validate_change (object, loc, new, in_group) | |
240 | rtx object; | |
241 | rtx *loc; | |
242 | rtx new; | |
243 | int in_group; | |
244 | { | |
245 | rtx old = *loc; | |
246 | ||
247 | if (old == new || rtx_equal_p (old, new)) | |
248 | return 1; | |
249 | ||
41a972a9 | 250 | if (in_group == 0 && num_changes != 0) |
2055cea7 RK |
251 | abort (); |
252 | ||
253 | *loc = new; | |
254 | ||
255 | /* Save the information describing this change. */ | |
41a972a9 MM |
256 | if (num_changes >= changes_allocated) |
257 | { | |
258 | if (changes_allocated == 0) | |
259 | /* This value allows for repeated substitutions inside complex | |
260 | indexed addresses, or changes in up to 5 insns. */ | |
261 | changes_allocated = MAX_RECOG_OPERANDS * 5; | |
262 | else | |
263 | changes_allocated *= 2; | |
264 | ||
265 | changes = | |
266 | (change_t*) xrealloc (changes, | |
267 | sizeof (change_t) * changes_allocated); | |
268 | } | |
269 | ||
270 | changes[num_changes].object = object; | |
271 | changes[num_changes].loc = loc; | |
272 | changes[num_changes].old = old; | |
2055cea7 RK |
273 | |
274 | if (object && GET_CODE (object) != MEM) | |
275 | { | |
276 | /* Set INSN_CODE to force rerecognition of insn. Save old code in | |
277 | case invalid. */ | |
41a972a9 | 278 | changes[num_changes].old_code = INSN_CODE (object); |
2055cea7 RK |
279 | INSN_CODE (object) = -1; |
280 | } | |
281 | ||
282 | num_changes++; | |
283 | ||
284 | /* If we are making a group of changes, return 1. Otherwise, validate the | |
285 | change group we made. */ | |
286 | ||
287 | if (in_group) | |
288 | return 1; | |
289 | else | |
290 | return apply_change_group (); | |
291 | } | |
292 | ||
61719ba7 BS |
293 | /* This subroutine of apply_change_group verifies whether the changes to INSN |
294 | were valid; i.e. whether INSN can still be recognized. */ | |
295 | ||
296 | static int | |
297 | insn_invalid_p (insn) | |
298 | rtx insn; | |
299 | { | |
300 | int icode = recog_memoized (insn); | |
301 | int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; | |
302 | ||
0eadeb15 BS |
303 | if (is_asm && ! check_asm_operands (PATTERN (insn))) |
304 | return 1; | |
305 | if (! is_asm && icode < 0) | |
61719ba7 BS |
306 | return 1; |
307 | ||
308 | /* After reload, verify that all constraints are satisfied. */ | |
309 | if (reload_completed) | |
310 | { | |
0eadeb15 | 311 | extract_insn (insn); |
61719ba7 | 312 | |
0eadeb15 | 313 | if (! constrain_operands (1)) |
61719ba7 BS |
314 | return 1; |
315 | } | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
2055cea7 RK |
320 | /* Apply a group of changes previously issued with `validate_change'. |
321 | Return 1 if all changes are valid, zero otherwise. */ | |
322 | ||
323 | int | |
324 | apply_change_group () | |
325 | { | |
326 | int i; | |
327 | ||
328 | /* The changes have been applied and all INSN_CODEs have been reset to force | |
329 | rerecognition. | |
330 | ||
331 | The changes are valid if we aren't given an object, or if we are | |
332 | given a MEM and it still is a valid address, or if this is in insn | |
333 | and it is recognized. In the latter case, if reload has completed, | |
334 | we also require that the operands meet the constraints for | |
0eadeb15 | 335 | the insn. */ |
2055cea7 RK |
336 | |
337 | for (i = 0; i < num_changes; i++) | |
338 | { | |
41a972a9 | 339 | rtx object = changes[i].object; |
2055cea7 RK |
340 | |
341 | if (object == 0) | |
342 | continue; | |
343 | ||
344 | if (GET_CODE (object) == MEM) | |
345 | { | |
346 | if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) | |
347 | break; | |
348 | } | |
61719ba7 | 349 | else if (insn_invalid_p (object)) |
2055cea7 RK |
350 | { |
351 | rtx pat = PATTERN (object); | |
352 | ||
353 | /* Perhaps we couldn't recognize the insn because there were | |
354 | extra CLOBBERs at the end. If so, try to re-recognize | |
355 | without the last CLOBBER (later iterations will cause each of | |
356 | them to be eliminated, in turn). But don't do this if we | |
357 | have an ASM_OPERAND. */ | |
358 | if (GET_CODE (pat) == PARALLEL | |
359 | && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER | |
360 | && asm_noperands (PATTERN (object)) < 0) | |
361 | { | |
362 | rtx newpat; | |
363 | ||
364 | if (XVECLEN (pat, 0) == 2) | |
365 | newpat = XVECEXP (pat, 0, 0); | |
366 | else | |
367 | { | |
368 | int j; | |
369 | ||
38a448ca RH |
370 | newpat = gen_rtx_PARALLEL (VOIDmode, |
371 | gen_rtvec (XVECLEN (pat, 0) - 1)); | |
2055cea7 RK |
372 | for (j = 0; j < XVECLEN (newpat, 0); j++) |
373 | XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); | |
374 | } | |
375 | ||
376 | /* Add a new change to this group to replace the pattern | |
377 | with this new pattern. Then consider this change | |
378 | as having succeeded. The change we added will | |
379 | cause the entire call to fail if things remain invalid. | |
380 | ||
381 | Note that this can lose if a later change than the one | |
382 | we are processing specified &XVECEXP (PATTERN (object), 0, X) | |
383 | but this shouldn't occur. */ | |
384 | ||
385 | validate_change (object, &PATTERN (object), newpat, 1); | |
386 | } | |
387 | else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) | |
388 | /* If this insn is a CLOBBER or USE, it is always valid, but is | |
389 | never recognized. */ | |
390 | continue; | |
391 | else | |
392 | break; | |
393 | } | |
394 | } | |
395 | ||
396 | if (i == num_changes) | |
397 | { | |
398 | num_changes = 0; | |
399 | return 1; | |
400 | } | |
401 | else | |
402 | { | |
403 | cancel_changes (0); | |
404 | return 0; | |
405 | } | |
406 | } | |
407 | ||
408 | /* Return the number of changes so far in the current group. */ | |
409 | ||
410 | int | |
411 | num_validated_changes () | |
412 | { | |
413 | return num_changes; | |
414 | } | |
415 | ||
416 | /* Retract the changes numbered NUM and up. */ | |
417 | ||
418 | void | |
419 | cancel_changes (num) | |
420 | int num; | |
421 | { | |
422 | int i; | |
423 | ||
424 | /* Back out all the changes. Do this in the opposite order in which | |
425 | they were made. */ | |
426 | for (i = num_changes - 1; i >= num; i--) | |
427 | { | |
41a972a9 MM |
428 | *changes[i].loc = changes[i].old; |
429 | if (changes[i].object && GET_CODE (changes[i].object) != MEM) | |
430 | INSN_CODE (changes[i].object) = changes[i].old_code; | |
2055cea7 RK |
431 | } |
432 | num_changes = num; | |
433 | } | |
434 | ||
435 | /* Replace every occurrence of FROM in X with TO. Mark each change with | |
436 | validate_change passing OBJECT. */ | |
437 | ||
438 | static void | |
439 | validate_replace_rtx_1 (loc, from, to, object) | |
440 | rtx *loc; | |
441 | rtx from, to, object; | |
442 | { | |
443 | register int i, j; | |
444 | register char *fmt; | |
445 | register rtx x = *loc; | |
446 | enum rtx_code code = GET_CODE (x); | |
447 | ||
448 | /* X matches FROM if it is the same rtx or they are both referring to the | |
449 | same register in the same mode. Avoid calling rtx_equal_p unless the | |
450 | operands look similar. */ | |
451 | ||
452 | if (x == from | |
453 | || (GET_CODE (x) == REG && GET_CODE (from) == REG | |
454 | && GET_MODE (x) == GET_MODE (from) | |
455 | && REGNO (x) == REGNO (from)) | |
456 | || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) | |
457 | && rtx_equal_p (x, from))) | |
458 | { | |
459 | validate_change (object, loc, to, 1); | |
460 | return; | |
461 | } | |
462 | ||
463 | /* For commutative or comparison operations, try replacing each argument | |
464 | separately and seeing if we made any changes. If so, put a constant | |
465 | argument last.*/ | |
466 | if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') | |
467 | { | |
468 | int prev_changes = num_changes; | |
469 | ||
470 | validate_replace_rtx_1 (&XEXP (x, 0), from, to, object); | |
471 | validate_replace_rtx_1 (&XEXP (x, 1), from, to, object); | |
472 | if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0))) | |
473 | { | |
474 | validate_change (object, loc, | |
38a448ca RH |
475 | gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code |
476 | : swap_condition (code), | |
477 | GET_MODE (x), XEXP (x, 1), | |
478 | XEXP (x, 0)), | |
2055cea7 RK |
479 | 1); |
480 | x = *loc; | |
481 | code = GET_CODE (x); | |
482 | } | |
483 | } | |
484 | ||
06140bdf RK |
485 | /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already |
486 | done the substitution, otherwise we won't. */ | |
487 | ||
2055cea7 RK |
488 | switch (code) |
489 | { | |
490 | case PLUS: | |
38e01259 | 491 | /* If we have a PLUS whose second operand is now a CONST_INT, use |
2055cea7 RK |
492 | plus_constant to try to simplify it. */ |
493 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to) | |
06140bdf RK |
494 | validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)), |
495 | 1); | |
2055cea7 | 496 | return; |
06140bdf RK |
497 | |
498 | case MINUS: | |
499 | if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from) | |
500 | { | |
501 | validate_change (object, loc, | |
502 | plus_constant (XEXP (x, 0), - INTVAL (to)), | |
503 | 1); | |
504 | return; | |
505 | } | |
506 | break; | |
2055cea7 RK |
507 | |
508 | case ZERO_EXTEND: | |
509 | case SIGN_EXTEND: | |
510 | /* In these cases, the operation to be performed depends on the mode | |
511 | of the operand. If we are replacing the operand with a VOIDmode | |
512 | constant, we lose the information. So try to simplify the operation | |
513 | in that case. If it fails, substitute in something that we know | |
6dc42e49 | 514 | won't be recognized. */ |
2055cea7 RK |
515 | if (GET_MODE (to) == VOIDmode |
516 | && (XEXP (x, 0) == from | |
517 | || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG | |
518 | && GET_MODE (XEXP (x, 0)) == GET_MODE (from) | |
519 | && REGNO (XEXP (x, 0)) == REGNO (from)))) | |
520 | { | |
521 | rtx new = simplify_unary_operation (code, GET_MODE (x), to, | |
522 | GET_MODE (from)); | |
523 | if (new == 0) | |
38a448ca | 524 | new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
2055cea7 RK |
525 | |
526 | validate_change (object, loc, new, 1); | |
527 | return; | |
528 | } | |
529 | break; | |
530 | ||
531 | case SUBREG: | |
532 | /* If we have a SUBREG of a register that we are replacing and we are | |
533 | replacing it with a MEM, make a new MEM and try replacing the | |
534 | SUBREG with it. Don't do this if the MEM has a mode-dependent address | |
535 | or if we would be widening it. */ | |
536 | ||
537 | if (SUBREG_REG (x) == from | |
538 | && GET_CODE (from) == REG | |
539 | && GET_CODE (to) == MEM | |
540 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
541 | && ! MEM_VOLATILE_P (to) | |
542 | && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to))) | |
543 | { | |
544 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
545 | enum machine_mode mode = GET_MODE (x); | |
546 | rtx new; | |
547 | ||
f76b9db2 ILT |
548 | if (BYTES_BIG_ENDIAN) |
549 | offset += (MIN (UNITS_PER_WORD, | |
550 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
551 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
2055cea7 | 552 | |
38a448ca | 553 | new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset)); |
2055cea7 | 554 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to); |
c6df88cb | 555 | MEM_COPY_ATTRIBUTES (new, to); |
2055cea7 RK |
556 | validate_change (object, loc, new, 1); |
557 | return; | |
558 | } | |
559 | break; | |
560 | ||
561 | case ZERO_EXTRACT: | |
562 | case SIGN_EXTRACT: | |
563 | /* If we are replacing a register with memory, try to change the memory | |
564 | to be the mode required for memory in extract operations (this isn't | |
565 | likely to be an insertion operation; if it was, nothing bad will | |
566 | happen, we might just fail in some cases). */ | |
567 | ||
568 | if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM | |
569 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
570 | && GET_CODE (XEXP (x, 2)) == CONST_INT | |
571 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
572 | && ! MEM_VOLATILE_P (to)) | |
573 | { | |
574 | enum machine_mode wanted_mode = VOIDmode; | |
575 | enum machine_mode is_mode = GET_MODE (to); | |
2055cea7 RK |
576 | int pos = INTVAL (XEXP (x, 2)); |
577 | ||
578 | #ifdef HAVE_extzv | |
579 | if (code == ZERO_EXTRACT) | |
0d8e55d8 JL |
580 | { |
581 | wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; | |
582 | if (wanted_mode == VOIDmode) | |
583 | wanted_mode = word_mode; | |
584 | } | |
2055cea7 RK |
585 | #endif |
586 | #ifdef HAVE_extv | |
587 | if (code == SIGN_EXTRACT) | |
0d8e55d8 JL |
588 | { |
589 | wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; | |
590 | if (wanted_mode == VOIDmode) | |
591 | wanted_mode = word_mode; | |
592 | } | |
2055cea7 RK |
593 | #endif |
594 | ||
6dc42e49 | 595 | /* If we have a narrower mode, we can do something. */ |
2055cea7 RK |
596 | if (wanted_mode != VOIDmode |
597 | && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) | |
598 | { | |
599 | int offset = pos / BITS_PER_UNIT; | |
600 | rtx newmem; | |
601 | ||
602 | /* If the bytes and bits are counted differently, we | |
603 | must adjust the offset. */ | |
f76b9db2 ILT |
604 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) |
605 | offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) | |
606 | - offset); | |
2055cea7 RK |
607 | |
608 | pos %= GET_MODE_BITSIZE (wanted_mode); | |
609 | ||
38a448ca RH |
610 | newmem = gen_rtx_MEM (wanted_mode, |
611 | plus_constant (XEXP (to, 0), offset)); | |
2055cea7 | 612 | RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to); |
c6df88cb | 613 | MEM_COPY_ATTRIBUTES (newmem, to); |
2055cea7 | 614 | |
9e4223f2 | 615 | validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); |
2055cea7 RK |
616 | validate_change (object, &XEXP (x, 0), newmem, 1); |
617 | } | |
618 | } | |
619 | ||
620 | break; | |
38a448ca RH |
621 | |
622 | default: | |
623 | break; | |
2055cea7 RK |
624 | } |
625 | ||
f745c7a2 AB |
626 | /* For commutative or comparison operations we've already performed |
627 | replacements. Don't try to perform them again. */ | |
628 | if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c') | |
2055cea7 | 629 | { |
f745c7a2 AB |
630 | fmt = GET_RTX_FORMAT (code); |
631 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
632 | { | |
633 | if (fmt[i] == 'e') | |
634 | validate_replace_rtx_1 (&XEXP (x, i), from, to, object); | |
635 | else if (fmt[i] == 'E') | |
636 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
637 | validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); | |
638 | } | |
2055cea7 RK |
639 | } |
640 | } | |
641 | ||
642 | /* Try replacing every occurrence of FROM in INSN with TO. After all | |
643 | changes have been made, validate by seeing if INSN is still valid. */ | |
644 | ||
645 | int | |
646 | validate_replace_rtx (from, to, insn) | |
647 | rtx from, to, insn; | |
648 | { | |
649 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
650 | return apply_change_group (); | |
651 | } | |
7506f491 | 652 | |
edfac33e JL |
653 | /* Try replacing every occurrence of FROM in INSN with TO. After all |
654 | changes have been made, validate by seeing if INSN is still valid. */ | |
655 | ||
656 | void | |
657 | validate_replace_rtx_group (from, to, insn) | |
658 | rtx from, to, insn; | |
659 | { | |
660 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
661 | } | |
662 | ||
7506f491 DE |
663 | /* Try replacing every occurrence of FROM in INSN with TO, avoiding |
664 | SET_DESTs. After all changes have been made, validate by seeing if | |
665 | INSN is still valid. */ | |
666 | ||
667 | int | |
668 | validate_replace_src (from, to, insn) | |
669 | rtx from, to, insn; | |
670 | { | |
671 | if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
672 | || GET_CODE (PATTERN (insn)) != SET) | |
673 | abort (); | |
674 | ||
675 | validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn); | |
676 | if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM) | |
677 | validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0), | |
678 | from, to, insn); | |
679 | return apply_change_group (); | |
680 | } | |
2055cea7 RK |
681 | \f |
682 | #ifdef HAVE_cc0 | |
683 | /* Return 1 if the insn using CC0 set by INSN does not contain | |
684 | any ordered tests applied to the condition codes. | |
685 | EQ and NE tests do not count. */ | |
686 | ||
687 | int | |
688 | next_insn_tests_no_inequality (insn) | |
689 | rtx insn; | |
690 | { | |
691 | register rtx next = next_cc0_user (insn); | |
692 | ||
693 | /* If there is no next insn, we have to take the conservative choice. */ | |
694 | if (next == 0) | |
695 | return 0; | |
696 | ||
697 | return ((GET_CODE (next) == JUMP_INSN | |
698 | || GET_CODE (next) == INSN | |
699 | || GET_CODE (next) == CALL_INSN) | |
700 | && ! inequality_comparisons_p (PATTERN (next))); | |
701 | } | |
702 | ||
703 | #if 0 /* This is useless since the insn that sets the cc's | |
704 | must be followed immediately by the use of them. */ | |
705 | /* Return 1 if the CC value set up by INSN is not used. */ | |
706 | ||
707 | int | |
708 | next_insns_test_no_inequality (insn) | |
709 | rtx insn; | |
710 | { | |
711 | register rtx next = NEXT_INSN (insn); | |
712 | ||
713 | for (; next != 0; next = NEXT_INSN (next)) | |
714 | { | |
715 | if (GET_CODE (next) == CODE_LABEL | |
716 | || GET_CODE (next) == BARRIER) | |
717 | return 1; | |
718 | if (GET_CODE (next) == NOTE) | |
719 | continue; | |
720 | if (inequality_comparisons_p (PATTERN (next))) | |
721 | return 0; | |
722 | if (sets_cc0_p (PATTERN (next)) == 1) | |
723 | return 1; | |
724 | if (! reg_mentioned_p (cc0_rtx, PATTERN (next))) | |
725 | return 1; | |
726 | } | |
727 | return 1; | |
728 | } | |
729 | #endif | |
730 | #endif | |
731 | \f | |
732 | /* This is used by find_single_use to locate an rtx that contains exactly one | |
733 | use of DEST, which is typically either a REG or CC0. It returns a | |
734 | pointer to the innermost rtx expression containing DEST. Appearances of | |
735 | DEST that are being used to totally replace it are not counted. */ | |
736 | ||
737 | static rtx * | |
738 | find_single_use_1 (dest, loc) | |
739 | rtx dest; | |
740 | rtx *loc; | |
741 | { | |
742 | rtx x = *loc; | |
743 | enum rtx_code code = GET_CODE (x); | |
744 | rtx *result = 0; | |
745 | rtx *this_result; | |
746 | int i; | |
747 | char *fmt; | |
748 | ||
749 | switch (code) | |
750 | { | |
751 | case CONST_INT: | |
752 | case CONST: | |
753 | case LABEL_REF: | |
754 | case SYMBOL_REF: | |
755 | case CONST_DOUBLE: | |
756 | case CLOBBER: | |
757 | return 0; | |
758 | ||
759 | case SET: | |
760 | /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
761 | of a REG that occupies all of the REG, the insn uses DEST if | |
762 | it is mentioned in the destination or the source. Otherwise, we | |
763 | need just check the source. */ | |
764 | if (GET_CODE (SET_DEST (x)) != CC0 | |
765 | && GET_CODE (SET_DEST (x)) != PC | |
766 | && GET_CODE (SET_DEST (x)) != REG | |
767 | && ! (GET_CODE (SET_DEST (x)) == SUBREG | |
768 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
769 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
770 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
771 | == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
772 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
773 | break; | |
774 | ||
775 | return find_single_use_1 (dest, &SET_SRC (x)); | |
776 | ||
777 | case MEM: | |
778 | case SUBREG: | |
779 | return find_single_use_1 (dest, &XEXP (x, 0)); | |
38a448ca RH |
780 | |
781 | default: | |
782 | break; | |
2055cea7 RK |
783 | } |
784 | ||
785 | /* If it wasn't one of the common cases above, check each expression and | |
786 | vector of this code. Look for a unique usage of DEST. */ | |
787 | ||
788 | fmt = GET_RTX_FORMAT (code); | |
789 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
790 | { | |
791 | if (fmt[i] == 'e') | |
792 | { | |
793 | if (dest == XEXP (x, i) | |
794 | || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG | |
795 | && REGNO (dest) == REGNO (XEXP (x, i)))) | |
796 | this_result = loc; | |
797 | else | |
798 | this_result = find_single_use_1 (dest, &XEXP (x, i)); | |
799 | ||
800 | if (result == 0) | |
801 | result = this_result; | |
802 | else if (this_result) | |
803 | /* Duplicate usage. */ | |
804 | return 0; | |
805 | } | |
806 | else if (fmt[i] == 'E') | |
807 | { | |
808 | int j; | |
809 | ||
810 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
811 | { | |
812 | if (XVECEXP (x, i, j) == dest | |
813 | || (GET_CODE (dest) == REG | |
814 | && GET_CODE (XVECEXP (x, i, j)) == REG | |
815 | && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) | |
816 | this_result = loc; | |
817 | else | |
818 | this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); | |
819 | ||
820 | if (result == 0) | |
821 | result = this_result; | |
822 | else if (this_result) | |
823 | return 0; | |
824 | } | |
825 | } | |
826 | } | |
827 | ||
828 | return result; | |
829 | } | |
830 | \f | |
831 | /* See if DEST, produced in INSN, is used only a single time in the | |
832 | sequel. If so, return a pointer to the innermost rtx expression in which | |
833 | it is used. | |
834 | ||
835 | If PLOC is non-zero, *PLOC is set to the insn containing the single use. | |
836 | ||
837 | This routine will return usually zero either before flow is called (because | |
838 | there will be no LOG_LINKS notes) or after reload (because the REG_DEAD | |
839 | note can't be trusted). | |
840 | ||
841 | If DEST is cc0_rtx, we look only at the next insn. In that case, we don't | |
842 | care about REG_DEAD notes or LOG_LINKS. | |
843 | ||
844 | Otherwise, we find the single use by finding an insn that has a | |
845 | LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is | |
846 | only referenced once in that insn, we know that it must be the first | |
847 | and last insn referencing DEST. */ | |
848 | ||
849 | rtx * | |
850 | find_single_use (dest, insn, ploc) | |
851 | rtx dest; | |
852 | rtx insn; | |
853 | rtx *ploc; | |
854 | { | |
855 | rtx next; | |
856 | rtx *result; | |
857 | rtx link; | |
858 | ||
859 | #ifdef HAVE_cc0 | |
860 | if (dest == cc0_rtx) | |
861 | { | |
862 | next = NEXT_INSN (insn); | |
863 | if (next == 0 | |
864 | || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN)) | |
865 | return 0; | |
866 | ||
867 | result = find_single_use_1 (dest, &PATTERN (next)); | |
868 | if (result && ploc) | |
869 | *ploc = next; | |
870 | return result; | |
871 | } | |
872 | #endif | |
873 | ||
874 | if (reload_completed || reload_in_progress || GET_CODE (dest) != REG) | |
875 | return 0; | |
876 | ||
877 | for (next = next_nonnote_insn (insn); | |
878 | next != 0 && GET_CODE (next) != CODE_LABEL; | |
879 | next = next_nonnote_insn (next)) | |
880 | if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest)) | |
881 | { | |
882 | for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) | |
883 | if (XEXP (link, 0) == insn) | |
884 | break; | |
885 | ||
886 | if (link) | |
887 | { | |
888 | result = find_single_use_1 (dest, &PATTERN (next)); | |
889 | if (ploc) | |
890 | *ploc = next; | |
891 | return result; | |
892 | } | |
893 | } | |
894 | ||
895 | return 0; | |
896 | } | |
897 | \f | |
898 | /* Return 1 if OP is a valid general operand for machine mode MODE. | |
899 | This is either a register reference, a memory reference, | |
900 | or a constant. In the case of a memory reference, the address | |
901 | is checked for general validity for the target machine. | |
902 | ||
903 | Register and memory references must have mode MODE in order to be valid, | |
904 | but some constants have no machine mode and are valid for any mode. | |
905 | ||
906 | If MODE is VOIDmode, OP is checked for validity for whatever mode | |
907 | it has. | |
908 | ||
909 | The main use of this function is as a predicate in match_operand | |
910 | expressions in the machine description. | |
911 | ||
6dc42e49 | 912 | For an explanation of this function's behavior for registers of |
2055cea7 RK |
913 | class NO_REGS, see the comment for `register_operand'. */ |
914 | ||
915 | int | |
916 | general_operand (op, mode) | |
917 | register rtx op; | |
918 | enum machine_mode mode; | |
919 | { | |
920 | register enum rtx_code code = GET_CODE (op); | |
921 | int mode_altering_drug = 0; | |
922 | ||
923 | if (mode == VOIDmode) | |
924 | mode = GET_MODE (op); | |
925 | ||
926 | /* Don't accept CONST_INT or anything similar | |
927 | if the caller wants something floating. */ | |
928 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
929 | && GET_MODE_CLASS (mode) != MODE_INT |
930 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
931 | return 0; |
932 | ||
933 | if (CONSTANT_P (op)) | |
934 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
935 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
936 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
937 | #endif | |
938 | && LEGITIMATE_CONSTANT_P (op)); | |
939 | ||
940 | /* Except for certain constants with VOIDmode, already checked for, | |
941 | OP's mode must match MODE if MODE specifies a mode. */ | |
942 | ||
943 | if (GET_MODE (op) != mode) | |
944 | return 0; | |
945 | ||
946 | if (code == SUBREG) | |
947 | { | |
948 | #ifdef INSN_SCHEDULING | |
949 | /* On machines that have insn scheduling, we want all memory | |
950 | reference to be explicit, so outlaw paradoxical SUBREGs. */ | |
951 | if (GET_CODE (SUBREG_REG (op)) == MEM | |
952 | && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) | |
953 | return 0; | |
954 | #endif | |
955 | ||
956 | op = SUBREG_REG (op); | |
957 | code = GET_CODE (op); | |
958 | #if 0 | |
959 | /* No longer needed, since (SUBREG (MEM...)) | |
960 | will load the MEM into a reload reg in the MEM's own mode. */ | |
961 | mode_altering_drug = 1; | |
962 | #endif | |
963 | } | |
964 | ||
965 | if (code == REG) | |
966 | /* A register whose class is NO_REGS is not a general operand. */ | |
967 | return (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
968 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); | |
969 | ||
970 | if (code == MEM) | |
971 | { | |
972 | register rtx y = XEXP (op, 0); | |
973 | if (! volatile_ok && MEM_VOLATILE_P (op)) | |
974 | return 0; | |
38a448ca RH |
975 | if (GET_CODE (y) == ADDRESSOF) |
976 | return 1; | |
2055cea7 RK |
977 | /* Use the mem's mode, since it will be reloaded thus. */ |
978 | mode = GET_MODE (op); | |
979 | GO_IF_LEGITIMATE_ADDRESS (mode, y, win); | |
980 | } | |
38a448ca RH |
981 | |
982 | /* Pretend this is an operand for now; we'll run force_operand | |
983 | on its replacement in fixup_var_refs_1. */ | |
984 | if (code == ADDRESSOF) | |
985 | return 1; | |
986 | ||
2055cea7 RK |
987 | return 0; |
988 | ||
989 | win: | |
990 | if (mode_altering_drug) | |
991 | return ! mode_dependent_address_p (XEXP (op, 0)); | |
992 | return 1; | |
993 | } | |
994 | \f | |
995 | /* Return 1 if OP is a valid memory address for a memory reference | |
996 | of mode MODE. | |
997 | ||
998 | The main use of this function is as a predicate in match_operand | |
999 | expressions in the machine description. */ | |
1000 | ||
1001 | int | |
1002 | address_operand (op, mode) | |
1003 | register rtx op; | |
1004 | enum machine_mode mode; | |
1005 | { | |
1006 | return memory_address_p (mode, op); | |
1007 | } | |
1008 | ||
1009 | /* Return 1 if OP is a register reference of mode MODE. | |
1010 | If MODE is VOIDmode, accept a register in any mode. | |
1011 | ||
1012 | The main use of this function is as a predicate in match_operand | |
1013 | expressions in the machine description. | |
1014 | ||
1015 | As a special exception, registers whose class is NO_REGS are | |
1016 | not accepted by `register_operand'. The reason for this change | |
1017 | is to allow the representation of special architecture artifacts | |
1018 | (such as a condition code register) without extending the rtl | |
1019 | definitions. Since registers of class NO_REGS cannot be used | |
1020 | as registers in any case where register classes are examined, | |
1021 | it is most consistent to keep this function from accepting them. */ | |
1022 | ||
1023 | int | |
1024 | register_operand (op, mode) | |
1025 | register rtx op; | |
1026 | enum machine_mode mode; | |
1027 | { | |
1028 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1029 | return 0; | |
1030 | ||
1031 | if (GET_CODE (op) == SUBREG) | |
1032 | { | |
1033 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
1034 | because it is guaranteed to be reloaded into one. | |
1035 | Just make sure the MEM is valid in itself. | |
1036 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1037 | but currently it does result from (SUBREG (REG)...) where the | |
1038 | reg went on the stack.) */ | |
1039 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
1040 | return general_operand (op, mode); | |
cba057ed RK |
1041 | |
1042 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
1043 | if (GET_CODE (SUBREG_REG (op)) == REG | |
1044 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER | |
1045 | && TEST_HARD_REG_BIT (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
1046 | REGNO (SUBREG_REG (op))) | |
1047 | && (GET_MODE_SIZE (mode) | |
50dc6373 RK |
1048 | != GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) |
1049 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT | |
1050 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT) | |
cba057ed RK |
1051 | return 0; |
1052 | #endif | |
1053 | ||
2055cea7 RK |
1054 | op = SUBREG_REG (op); |
1055 | } | |
1056 | ||
1057 | /* We don't consider registers whose class is NO_REGS | |
1058 | to be a register operand. */ | |
1059 | return (GET_CODE (op) == REG | |
1060 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1061 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1062 | } | |
1063 | ||
1064 | /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH | |
1065 | or a hard register. */ | |
1066 | ||
1067 | int | |
1068 | scratch_operand (op, mode) | |
1069 | register rtx op; | |
1070 | enum machine_mode mode; | |
1071 | { | |
1072 | return (GET_MODE (op) == mode | |
1073 | && (GET_CODE (op) == SCRATCH | |
1074 | || (GET_CODE (op) == REG | |
1075 | && REGNO (op) < FIRST_PSEUDO_REGISTER))); | |
1076 | } | |
1077 | ||
1078 | /* Return 1 if OP is a valid immediate operand for mode MODE. | |
1079 | ||
1080 | The main use of this function is as a predicate in match_operand | |
1081 | expressions in the machine description. */ | |
1082 | ||
1083 | int | |
1084 | immediate_operand (op, mode) | |
1085 | register rtx op; | |
1086 | enum machine_mode mode; | |
1087 | { | |
1088 | /* Don't accept CONST_INT or anything similar | |
1089 | if the caller wants something floating. */ | |
1090 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1091 | && GET_MODE_CLASS (mode) != MODE_INT |
1092 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1093 | return 0; |
1094 | ||
ee5332b8 RH |
1095 | /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and |
1096 | result in 0/1. It seems a safe assumption that this is | |
1097 | in range for everyone. */ | |
1098 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
1099 | return 1; | |
1100 | ||
2055cea7 RK |
1101 | return (CONSTANT_P (op) |
1102 | && (GET_MODE (op) == mode || mode == VOIDmode | |
1103 | || GET_MODE (op) == VOIDmode) | |
1104 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1105 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1106 | #endif | |
1107 | && LEGITIMATE_CONSTANT_P (op)); | |
1108 | } | |
1109 | ||
1110 | /* Returns 1 if OP is an operand that is a CONST_INT. */ | |
1111 | ||
1112 | int | |
1113 | const_int_operand (op, mode) | |
1114 | register rtx op; | |
e51712db | 1115 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2055cea7 RK |
1116 | { |
1117 | return GET_CODE (op) == CONST_INT; | |
1118 | } | |
1119 | ||
1120 | /* Returns 1 if OP is an operand that is a constant integer or constant | |
1121 | floating-point number. */ | |
1122 | ||
1123 | int | |
1124 | const_double_operand (op, mode) | |
1125 | register rtx op; | |
1126 | enum machine_mode mode; | |
1127 | { | |
1128 | /* Don't accept CONST_INT or anything similar | |
1129 | if the caller wants something floating. */ | |
1130 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1131 | && GET_MODE_CLASS (mode) != MODE_INT |
1132 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1133 | return 0; |
1134 | ||
1135 | return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) | |
1136 | && (mode == VOIDmode || GET_MODE (op) == mode | |
1137 | || GET_MODE (op) == VOIDmode)); | |
1138 | } | |
1139 | ||
1140 | /* Return 1 if OP is a general operand that is not an immediate operand. */ | |
1141 | ||
1142 | int | |
1143 | nonimmediate_operand (op, mode) | |
1144 | register rtx op; | |
1145 | enum machine_mode mode; | |
1146 | { | |
1147 | return (general_operand (op, mode) && ! CONSTANT_P (op)); | |
1148 | } | |
1149 | ||
1150 | /* Return 1 if OP is a register reference or immediate value of mode MODE. */ | |
1151 | ||
1152 | int | |
1153 | nonmemory_operand (op, mode) | |
1154 | register rtx op; | |
1155 | enum machine_mode mode; | |
1156 | { | |
1157 | if (CONSTANT_P (op)) | |
1158 | { | |
1159 | /* Don't accept CONST_INT or anything similar | |
1160 | if the caller wants something floating. */ | |
1161 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1162 | && GET_MODE_CLASS (mode) != MODE_INT |
1163 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1164 | return 0; |
1165 | ||
1166 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
1167 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1168 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1169 | #endif | |
1170 | && LEGITIMATE_CONSTANT_P (op)); | |
1171 | } | |
1172 | ||
1173 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1174 | return 0; | |
1175 | ||
1176 | if (GET_CODE (op) == SUBREG) | |
1177 | { | |
1178 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
1179 | because it is guaranteed to be reloaded into one. | |
1180 | Just make sure the MEM is valid in itself. | |
1181 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1182 | but currently it does result from (SUBREG (REG)...) where the | |
1183 | reg went on the stack.) */ | |
1184 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
1185 | return general_operand (op, mode); | |
1186 | op = SUBREG_REG (op); | |
1187 | } | |
1188 | ||
1189 | /* We don't consider registers whose class is NO_REGS | |
1190 | to be a register operand. */ | |
1191 | return (GET_CODE (op) == REG | |
1192 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1193 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1194 | } | |
1195 | ||
1196 | /* Return 1 if OP is a valid operand that stands for pushing a | |
1197 | value of mode MODE onto the stack. | |
1198 | ||
1199 | The main use of this function is as a predicate in match_operand | |
1200 | expressions in the machine description. */ | |
1201 | ||
1202 | int | |
1203 | push_operand (op, mode) | |
1204 | rtx op; | |
1205 | enum machine_mode mode; | |
1206 | { | |
1207 | if (GET_CODE (op) != MEM) | |
1208 | return 0; | |
1209 | ||
aeb7ff68 | 1210 | if (mode != VOIDmode && GET_MODE (op) != mode) |
2055cea7 RK |
1211 | return 0; |
1212 | ||
1213 | op = XEXP (op, 0); | |
1214 | ||
1215 | if (GET_CODE (op) != STACK_PUSH_CODE) | |
1216 | return 0; | |
1217 | ||
1218 | return XEXP (op, 0) == stack_pointer_rtx; | |
1219 | } | |
1220 | ||
6fbe9bd8 RH |
1221 | /* Return 1 if OP is a valid operand that stands for popping a |
1222 | value of mode MODE off the stack. | |
1223 | ||
1224 | The main use of this function is as a predicate in match_operand | |
1225 | expressions in the machine description. */ | |
1226 | ||
1227 | int | |
1228 | pop_operand (op, mode) | |
1229 | rtx op; | |
1230 | enum machine_mode mode; | |
1231 | { | |
1232 | if (GET_CODE (op) != MEM) | |
1233 | return 0; | |
1234 | ||
aeb7ff68 | 1235 | if (mode != VOIDmode && GET_MODE (op) != mode) |
6fbe9bd8 RH |
1236 | return 0; |
1237 | ||
1238 | op = XEXP (op, 0); | |
1239 | ||
1240 | if (GET_CODE (op) != STACK_POP_CODE) | |
1241 | return 0; | |
1242 | ||
1243 | return XEXP (op, 0) == stack_pointer_rtx; | |
1244 | } | |
1245 | ||
2055cea7 RK |
1246 | /* Return 1 if ADDR is a valid memory address for mode MODE. */ |
1247 | ||
1248 | int | |
1249 | memory_address_p (mode, addr) | |
1250 | enum machine_mode mode; | |
1251 | register rtx addr; | |
1252 | { | |
38a448ca RH |
1253 | if (GET_CODE (addr) == ADDRESSOF) |
1254 | return 1; | |
1255 | ||
2055cea7 RK |
1256 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); |
1257 | return 0; | |
1258 | ||
1259 | win: | |
1260 | return 1; | |
1261 | } | |
1262 | ||
1263 | /* Return 1 if OP is a valid memory reference with mode MODE, | |
1264 | including a valid address. | |
1265 | ||
1266 | The main use of this function is as a predicate in match_operand | |
1267 | expressions in the machine description. */ | |
1268 | ||
1269 | int | |
1270 | memory_operand (op, mode) | |
1271 | register rtx op; | |
1272 | enum machine_mode mode; | |
1273 | { | |
1274 | rtx inner; | |
1275 | ||
1276 | if (! reload_completed) | |
1277 | /* Note that no SUBREG is a memory operand before end of reload pass, | |
1278 | because (SUBREG (MEM...)) forces reloading into a register. */ | |
1279 | return GET_CODE (op) == MEM && general_operand (op, mode); | |
1280 | ||
1281 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1282 | return 0; | |
1283 | ||
1284 | inner = op; | |
1285 | if (GET_CODE (inner) == SUBREG) | |
1286 | inner = SUBREG_REG (inner); | |
1287 | ||
1288 | return (GET_CODE (inner) == MEM && general_operand (op, mode)); | |
1289 | } | |
1290 | ||
1291 | /* Return 1 if OP is a valid indirect memory reference with mode MODE; | |
1292 | that is, a memory reference whose address is a general_operand. */ | |
1293 | ||
1294 | int | |
1295 | indirect_operand (op, mode) | |
1296 | register rtx op; | |
1297 | enum machine_mode mode; | |
1298 | { | |
1299 | /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ | |
1300 | if (! reload_completed | |
1301 | && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) | |
1302 | { | |
1303 | register int offset = SUBREG_WORD (op) * UNITS_PER_WORD; | |
1304 | rtx inner = SUBREG_REG (op); | |
1305 | ||
f76b9db2 ILT |
1306 | if (BYTES_BIG_ENDIAN) |
1307 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op))) | |
1308 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner)))); | |
2055cea7 | 1309 | |
b0e0a0f9 RK |
1310 | if (mode != VOIDmode && GET_MODE (op) != mode) |
1311 | return 0; | |
1312 | ||
2055cea7 RK |
1313 | /* The only way that we can have a general_operand as the resulting |
1314 | address is if OFFSET is zero and the address already is an operand | |
1315 | or if the address is (plus Y (const_int -OFFSET)) and Y is an | |
1316 | operand. */ | |
1317 | ||
1318 | return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode)) | |
1319 | || (GET_CODE (XEXP (inner, 0)) == PLUS | |
1320 | && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT | |
1321 | && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset | |
1322 | && general_operand (XEXP (XEXP (inner, 0), 0), Pmode))); | |
1323 | } | |
1324 | ||
1325 | return (GET_CODE (op) == MEM | |
1326 | && memory_operand (op, mode) | |
1327 | && general_operand (XEXP (op, 0), Pmode)); | |
1328 | } | |
1329 | ||
1330 | /* Return 1 if this is a comparison operator. This allows the use of | |
1331 | MATCH_OPERATOR to recognize all the branch insns. */ | |
1332 | ||
1333 | int | |
1334 | comparison_operator (op, mode) | |
1335 | register rtx op; | |
1336 | enum machine_mode mode; | |
1337 | { | |
1338 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
1339 | && GET_RTX_CLASS (GET_CODE (op)) == '<'); | |
1340 | } | |
1341 | \f | |
1342 | /* If BODY is an insn body that uses ASM_OPERANDS, | |
1343 | return the number of operands (both input and output) in the insn. | |
1344 | Otherwise return -1. */ | |
1345 | ||
1346 | int | |
1347 | asm_noperands (body) | |
1348 | rtx body; | |
1349 | { | |
1350 | if (GET_CODE (body) == ASM_OPERANDS) | |
1351 | /* No output operands: return number of input operands. */ | |
1352 | return ASM_OPERANDS_INPUT_LENGTH (body); | |
1353 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1354 | /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ | |
1355 | return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; | |
1356 | else if (GET_CODE (body) == PARALLEL | |
1357 | && GET_CODE (XVECEXP (body, 0, 0)) == SET | |
1358 | && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) | |
1359 | { | |
1360 | /* Multiple output operands, or 1 output plus some clobbers: | |
1361 | body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ | |
1362 | int i; | |
1363 | int n_sets; | |
1364 | ||
1365 | /* Count backwards through CLOBBERs to determine number of SETs. */ | |
1366 | for (i = XVECLEN (body, 0); i > 0; i--) | |
1367 | { | |
1368 | if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) | |
1369 | break; | |
1370 | if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) | |
1371 | return -1; | |
1372 | } | |
1373 | ||
1374 | /* N_SETS is now number of output operands. */ | |
1375 | n_sets = i; | |
1376 | ||
1377 | /* Verify that all the SETs we have | |
1378 | came from a single original asm_operands insn | |
1379 | (so that invalid combinations are blocked). */ | |
1380 | for (i = 0; i < n_sets; i++) | |
1381 | { | |
1382 | rtx elt = XVECEXP (body, 0, i); | |
1383 | if (GET_CODE (elt) != SET) | |
1384 | return -1; | |
1385 | if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) | |
1386 | return -1; | |
1387 | /* If these ASM_OPERANDS rtx's came from different original insns | |
1388 | then they aren't allowed together. */ | |
1389 | if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) | |
1390 | != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) | |
1391 | return -1; | |
1392 | } | |
1393 | return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) | |
1394 | + n_sets); | |
1395 | } | |
1396 | else if (GET_CODE (body) == PARALLEL | |
1397 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1398 | { | |
1399 | /* 0 outputs, but some clobbers: | |
1400 | body is [(asm_operands ...) (clobber (reg ...))...]. */ | |
1401 | int i; | |
1402 | ||
1403 | /* Make sure all the other parallel things really are clobbers. */ | |
1404 | for (i = XVECLEN (body, 0) - 1; i > 0; i--) | |
1405 | if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) | |
1406 | return -1; | |
1407 | ||
1408 | return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); | |
1409 | } | |
1410 | else | |
1411 | return -1; | |
1412 | } | |
1413 | ||
1414 | /* Assuming BODY is an insn body that uses ASM_OPERANDS, | |
1415 | copy its operands (both input and output) into the vector OPERANDS, | |
1416 | the locations of the operands within the insn into the vector OPERAND_LOCS, | |
1417 | and the constraints for the operands into CONSTRAINTS. | |
1418 | Write the modes of the operands into MODES. | |
1419 | Return the assembler-template. | |
1420 | ||
1421 | If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, | |
1422 | we don't store that info. */ | |
1423 | ||
1424 | char * | |
1425 | decode_asm_operands (body, operands, operand_locs, constraints, modes) | |
1426 | rtx body; | |
1427 | rtx *operands; | |
1428 | rtx **operand_locs; | |
9b3142b3 | 1429 | const char **constraints; |
2055cea7 RK |
1430 | enum machine_mode *modes; |
1431 | { | |
1432 | register int i; | |
1433 | int noperands; | |
1434 | char *template = 0; | |
1435 | ||
1436 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1437 | { | |
1438 | rtx asmop = SET_SRC (body); | |
1439 | /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */ | |
1440 | ||
1441 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1; | |
1442 | ||
1443 | for (i = 1; i < noperands; i++) | |
1444 | { | |
1445 | if (operand_locs) | |
1446 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1); | |
1447 | if (operands) | |
1448 | operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1); | |
1449 | if (constraints) | |
1450 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1); | |
1451 | if (modes) | |
1452 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1); | |
1453 | } | |
1454 | ||
1455 | /* The output is in the SET. | |
1456 | Its constraint is in the ASM_OPERANDS itself. */ | |
1457 | if (operands) | |
1458 | operands[0] = SET_DEST (body); | |
1459 | if (operand_locs) | |
1460 | operand_locs[0] = &SET_DEST (body); | |
1461 | if (constraints) | |
1462 | constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); | |
1463 | if (modes) | |
1464 | modes[0] = GET_MODE (SET_DEST (body)); | |
1465 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1466 | } | |
1467 | else if (GET_CODE (body) == ASM_OPERANDS) | |
1468 | { | |
1469 | rtx asmop = body; | |
1470 | /* No output operands: BODY is (asm_operands ....). */ | |
1471 | ||
1472 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1473 | ||
1474 | /* The input operands are found in the 1st element vector. */ | |
1475 | /* Constraints for inputs are in the 2nd element vector. */ | |
1476 | for (i = 0; i < noperands; i++) | |
1477 | { | |
1478 | if (operand_locs) | |
1479 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1480 | if (operands) | |
1481 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1482 | if (constraints) | |
1483 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1484 | if (modes) | |
1485 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1486 | } | |
1487 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1488 | } | |
1489 | else if (GET_CODE (body) == PARALLEL | |
1490 | && GET_CODE (XVECEXP (body, 0, 0)) == SET) | |
1491 | { | |
1492 | rtx asmop = SET_SRC (XVECEXP (body, 0, 0)); | |
1493 | int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ | |
1494 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1495 | int nout = 0; /* Does not include CLOBBERs. */ | |
1496 | ||
1497 | /* At least one output, plus some CLOBBERs. */ | |
1498 | ||
1499 | /* The outputs are in the SETs. | |
1500 | Their constraints are in the ASM_OPERANDS itself. */ | |
1501 | for (i = 0; i < nparallel; i++) | |
1502 | { | |
1503 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
1504 | break; /* Past last SET */ | |
1505 | ||
1506 | if (operands) | |
1507 | operands[i] = SET_DEST (XVECEXP (body, 0, i)); | |
1508 | if (operand_locs) | |
1509 | operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); | |
1510 | if (constraints) | |
1511 | constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); | |
1512 | if (modes) | |
1513 | modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); | |
1514 | nout++; | |
1515 | } | |
1516 | ||
1517 | for (i = 0; i < nin; i++) | |
1518 | { | |
1519 | if (operand_locs) | |
1520 | operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i); | |
1521 | if (operands) | |
1522 | operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i); | |
1523 | if (constraints) | |
1524 | constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1525 | if (modes) | |
1526 | modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1527 | } | |
1528 | ||
1529 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1530 | } | |
1531 | else if (GET_CODE (body) == PARALLEL | |
1532 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1533 | { | |
1534 | /* No outputs, but some CLOBBERs. */ | |
1535 | ||
1536 | rtx asmop = XVECEXP (body, 0, 0); | |
1537 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1538 | ||
1539 | for (i = 0; i < nin; i++) | |
1540 | { | |
1541 | if (operand_locs) | |
1542 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1543 | if (operands) | |
1544 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1545 | if (constraints) | |
1546 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1547 | if (modes) | |
1548 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1549 | } | |
1550 | ||
1551 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1552 | } | |
1553 | ||
1554 | return template; | |
1555 | } | |
1f06ee8d | 1556 | |
1afbe1c4 RH |
1557 | /* Check if an asm_operand matches it's constraints. |
1558 | Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ | |
1f06ee8d RH |
1559 | |
1560 | int | |
1561 | asm_operand_ok (op, constraint) | |
1562 | rtx op; | |
1563 | const char *constraint; | |
1564 | { | |
1afbe1c4 RH |
1565 | int result = 0; |
1566 | ||
1f06ee8d RH |
1567 | /* Use constrain_operands after reload. */ |
1568 | if (reload_completed) | |
1569 | abort (); | |
1570 | ||
1571 | while (*constraint) | |
1572 | { | |
1573 | switch (*constraint++) | |
1574 | { | |
1575 | case '=': | |
1576 | case '+': | |
1577 | case '*': | |
1578 | case '%': | |
1579 | case '?': | |
1580 | case '!': | |
1581 | case '#': | |
1582 | case '&': | |
1583 | case ',': | |
1584 | break; | |
1585 | ||
1586 | case '0': case '1': case '2': case '3': case '4': | |
1587 | case '5': case '6': case '7': case '8': case '9': | |
1afbe1c4 RH |
1588 | /* For best results, our caller should have given us the |
1589 | proper matching constraint, but we can't actually fail | |
1590 | the check if they didn't. Indicate that results are | |
1591 | inconclusive. */ | |
1592 | result = -1; | |
1f06ee8d RH |
1593 | break; |
1594 | ||
1595 | case 'p': | |
1596 | if (address_operand (op, VOIDmode)) | |
1597 | return 1; | |
1598 | break; | |
1599 | ||
1600 | case 'm': | |
1601 | case 'V': /* non-offsettable */ | |
1602 | if (memory_operand (op, VOIDmode)) | |
1603 | return 1; | |
1604 | break; | |
1605 | ||
1606 | case 'o': /* offsettable */ | |
1607 | if (offsettable_nonstrict_memref_p (op)) | |
1608 | return 1; | |
1609 | break; | |
1610 | ||
1611 | case '<': | |
1afbe1c4 RH |
1612 | /* ??? Before flow, auto inc/dec insns are not supposed to exist, |
1613 | excepting those that expand_call created. Further, on some | |
1614 | machines which do not have generalized auto inc/dec, an inc/dec | |
1615 | is not a memory_operand. | |
1616 | ||
1617 | Match any memory and hope things are resolved after reload. */ | |
1618 | ||
1f06ee8d | 1619 | if (GET_CODE (op) == MEM |
1afbe1c4 RH |
1620 | && (1 |
1621 | || GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1f06ee8d RH |
1622 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) |
1623 | return 1; | |
1624 | break; | |
1625 | ||
1626 | case '>': | |
1627 | if (GET_CODE (op) == MEM | |
1afbe1c4 RH |
1628 | && (1 |
1629 | || GET_CODE (XEXP (op, 0)) == PRE_INC | |
1f06ee8d RH |
1630 | || GET_CODE (XEXP (op, 0)) == POST_INC)) |
1631 | return 1; | |
1632 | break; | |
1633 | ||
1634 | case 'E': | |
1635 | #ifndef REAL_ARITHMETIC | |
1636 | /* Match any floating double constant, but only if | |
1637 | we can examine the bits of it reliably. */ | |
1638 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
1639 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) | |
1640 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) | |
1641 | break; | |
1642 | #endif | |
1643 | /* FALLTHRU */ | |
1644 | ||
1645 | case 'F': | |
1646 | if (GET_CODE (op) == CONST_DOUBLE) | |
1647 | return 1; | |
1648 | break; | |
1649 | ||
1650 | case 'G': | |
1651 | if (GET_CODE (op) == CONST_DOUBLE | |
1652 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G')) | |
1653 | return 1; | |
1654 | break; | |
1655 | case 'H': | |
1656 | if (GET_CODE (op) == CONST_DOUBLE | |
1657 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H')) | |
1658 | return 1; | |
1659 | break; | |
1660 | ||
1661 | case 's': | |
1662 | if (GET_CODE (op) == CONST_INT | |
1663 | || (GET_CODE (op) == CONST_DOUBLE | |
1664 | && GET_MODE (op) == VOIDmode)) | |
1665 | break; | |
1666 | /* FALLTHRU */ | |
1667 | ||
1668 | case 'i': | |
1669 | if (CONSTANT_P (op) | |
1670 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1671 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1672 | #endif | |
1673 | ) | |
1674 | return 1; | |
1675 | break; | |
1676 | ||
1677 | case 'n': | |
1678 | if (GET_CODE (op) == CONST_INT | |
1679 | || (GET_CODE (op) == CONST_DOUBLE | |
1680 | && GET_MODE (op) == VOIDmode)) | |
1681 | return 1; | |
1682 | break; | |
1683 | ||
1684 | case 'I': | |
1685 | if (GET_CODE (op) == CONST_INT | |
1686 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')) | |
1687 | return 1; | |
1688 | break; | |
1689 | case 'J': | |
1690 | if (GET_CODE (op) == CONST_INT | |
1691 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J')) | |
1692 | return 1; | |
1693 | break; | |
1694 | case 'K': | |
1695 | if (GET_CODE (op) == CONST_INT | |
1696 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')) | |
1697 | return 1; | |
1698 | break; | |
1699 | case 'L': | |
1700 | if (GET_CODE (op) == CONST_INT | |
1701 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')) | |
1702 | return 1; | |
1703 | break; | |
1704 | case 'M': | |
1705 | if (GET_CODE (op) == CONST_INT | |
1706 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M')) | |
1707 | return 1; | |
1708 | break; | |
1709 | case 'N': | |
1710 | if (GET_CODE (op) == CONST_INT | |
1711 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N')) | |
1712 | return 1; | |
1713 | break; | |
1714 | case 'O': | |
1715 | if (GET_CODE (op) == CONST_INT | |
1716 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')) | |
1717 | return 1; | |
1718 | break; | |
1719 | case 'P': | |
1720 | if (GET_CODE (op) == CONST_INT | |
1721 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')) | |
1722 | return 1; | |
1723 | break; | |
1724 | ||
1725 | case 'X': | |
1726 | return 1; | |
1727 | ||
1728 | case 'g': | |
1729 | if (general_operand (op, VOIDmode)) | |
1730 | return 1; | |
1731 | break; | |
1732 | ||
1733 | #ifdef EXTRA_CONSTRAINT | |
1734 | case 'Q': | |
1735 | if (EXTRA_CONSTRAINT (op, 'Q')) | |
1736 | return 1; | |
1737 | break; | |
1738 | case 'R': | |
1739 | if (EXTRA_CONSTRAINT (op, 'R')) | |
1740 | return 1; | |
1741 | break; | |
1742 | case 'S': | |
1743 | if (EXTRA_CONSTRAINT (op, 'S')) | |
1744 | return 1; | |
1745 | break; | |
1746 | case 'T': | |
1747 | if (EXTRA_CONSTRAINT (op, 'T')) | |
1748 | return 1; | |
1749 | break; | |
1750 | case 'U': | |
1751 | if (EXTRA_CONSTRAINT (op, 'U')) | |
1752 | return 1; | |
1753 | break; | |
1754 | #endif | |
1755 | ||
1756 | case 'r': | |
1757 | default: | |
1758 | if (GET_MODE (op) == BLKmode) | |
1759 | break; | |
1760 | if (register_operand (op, VOIDmode)) | |
1761 | return 1; | |
1762 | break; | |
1763 | } | |
1764 | } | |
1765 | ||
1afbe1c4 | 1766 | return result; |
1f06ee8d | 1767 | } |
2055cea7 | 1768 | \f |
2055cea7 RK |
1769 | /* Given an rtx *P, if it is a sum containing an integer constant term, |
1770 | return the location (type rtx *) of the pointer to that constant term. | |
1771 | Otherwise, return a null pointer. */ | |
1772 | ||
1773 | static rtx * | |
1774 | find_constant_term_loc (p) | |
1775 | rtx *p; | |
1776 | { | |
1777 | register rtx *tem; | |
1778 | register enum rtx_code code = GET_CODE (*p); | |
1779 | ||
1780 | /* If *P IS such a constant term, P is its location. */ | |
1781 | ||
1782 | if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF | |
1783 | || code == CONST) | |
1784 | return p; | |
1785 | ||
1786 | /* Otherwise, if not a sum, it has no constant term. */ | |
1787 | ||
1788 | if (GET_CODE (*p) != PLUS) | |
1789 | return 0; | |
1790 | ||
1791 | /* If one of the summands is constant, return its location. */ | |
1792 | ||
1793 | if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) | |
1794 | && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) | |
1795 | return p; | |
1796 | ||
1797 | /* Otherwise, check each summand for containing a constant term. */ | |
1798 | ||
1799 | if (XEXP (*p, 0) != 0) | |
1800 | { | |
1801 | tem = find_constant_term_loc (&XEXP (*p, 0)); | |
1802 | if (tem != 0) | |
1803 | return tem; | |
1804 | } | |
1805 | ||
1806 | if (XEXP (*p, 1) != 0) | |
1807 | { | |
1808 | tem = find_constant_term_loc (&XEXP (*p, 1)); | |
1809 | if (tem != 0) | |
1810 | return tem; | |
1811 | } | |
1812 | ||
1813 | return 0; | |
1814 | } | |
1815 | \f | |
1816 | /* Return 1 if OP is a memory reference | |
1817 | whose address contains no side effects | |
1818 | and remains valid after the addition | |
1819 | of a positive integer less than the | |
1820 | size of the object being referenced. | |
1821 | ||
1822 | We assume that the original address is valid and do not check it. | |
1823 | ||
1824 | This uses strict_memory_address_p as a subroutine, so | |
1825 | don't use it before reload. */ | |
1826 | ||
1827 | int | |
1828 | offsettable_memref_p (op) | |
1829 | rtx op; | |
1830 | { | |
1831 | return ((GET_CODE (op) == MEM) | |
1832 | && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); | |
1833 | } | |
1834 | ||
1835 | /* Similar, but don't require a strictly valid mem ref: | |
1836 | consider pseudo-regs valid as index or base regs. */ | |
1837 | ||
1838 | int | |
1839 | offsettable_nonstrict_memref_p (op) | |
1840 | rtx op; | |
1841 | { | |
1842 | return ((GET_CODE (op) == MEM) | |
1843 | && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); | |
1844 | } | |
1845 | ||
1846 | /* Return 1 if Y is a memory address which contains no side effects | |
1847 | and would remain valid after the addition of a positive integer | |
1848 | less than the size of that mode. | |
1849 | ||
1850 | We assume that the original address is valid and do not check it. | |
1851 | We do check that it is valid for narrower modes. | |
1852 | ||
1853 | If STRICTP is nonzero, we require a strictly valid address, | |
1854 | for the sake of use in reload.c. */ | |
1855 | ||
1856 | int | |
1857 | offsettable_address_p (strictp, mode, y) | |
1858 | int strictp; | |
1859 | enum machine_mode mode; | |
1860 | register rtx y; | |
1861 | { | |
1862 | register enum rtx_code ycode = GET_CODE (y); | |
1863 | register rtx z; | |
1864 | rtx y1 = y; | |
1865 | rtx *y2; | |
1866 | int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p); | |
1867 | ||
1868 | if (CONSTANT_ADDRESS_P (y)) | |
1869 | return 1; | |
1870 | ||
1871 | /* Adjusting an offsettable address involves changing to a narrower mode. | |
1872 | Make sure that's OK. */ | |
1873 | ||
1874 | if (mode_dependent_address_p (y)) | |
1875 | return 0; | |
1876 | ||
1877 | /* If the expression contains a constant term, | |
1878 | see if it remains valid when max possible offset is added. */ | |
1879 | ||
1880 | if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) | |
1881 | { | |
1882 | int good; | |
1883 | ||
1884 | y1 = *y2; | |
1885 | *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1); | |
1886 | /* Use QImode because an odd displacement may be automatically invalid | |
1887 | for any wider mode. But it should be valid for a single byte. */ | |
1888 | good = (*addressp) (QImode, y); | |
1889 | ||
1890 | /* In any case, restore old contents of memory. */ | |
1891 | *y2 = y1; | |
1892 | return good; | |
1893 | } | |
1894 | ||
1895 | if (ycode == PRE_DEC || ycode == PRE_INC | |
1896 | || ycode == POST_DEC || ycode == POST_INC) | |
1897 | return 0; | |
1898 | ||
1899 | /* The offset added here is chosen as the maximum offset that | |
1900 | any instruction could need to add when operating on something | |
1901 | of the specified mode. We assume that if Y and Y+c are | |
1902 | valid addresses then so is Y+d for all 0<d<c. */ | |
1903 | ||
1904 | z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1); | |
1905 | ||
1906 | /* Use QImode because an odd displacement may be automatically invalid | |
1907 | for any wider mode. But it should be valid for a single byte. */ | |
1908 | return (*addressp) (QImode, z); | |
1909 | } | |
1910 | ||
1911 | /* Return 1 if ADDR is an address-expression whose effect depends | |
1912 | on the mode of the memory reference it is used in. | |
1913 | ||
1914 | Autoincrement addressing is a typical example of mode-dependence | |
1915 | because the amount of the increment depends on the mode. */ | |
1916 | ||
1917 | int | |
1918 | mode_dependent_address_p (addr) | |
47c3ed98 | 1919 | rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */ |
2055cea7 RK |
1920 | { |
1921 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, win); | |
1922 | return 0; | |
47c3ed98 KG |
1923 | /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ |
1924 | win: ATTRIBUTE_UNUSED_LABEL | |
2055cea7 RK |
1925 | return 1; |
1926 | } | |
1927 | ||
1928 | /* Return 1 if OP is a general operand | |
1929 | other than a memory ref with a mode dependent address. */ | |
1930 | ||
1931 | int | |
1932 | mode_independent_operand (op, mode) | |
1933 | enum machine_mode mode; | |
1934 | rtx op; | |
1935 | { | |
1936 | rtx addr; | |
1937 | ||
1938 | if (! general_operand (op, mode)) | |
1939 | return 0; | |
1940 | ||
1941 | if (GET_CODE (op) != MEM) | |
1942 | return 1; | |
1943 | ||
1944 | addr = XEXP (op, 0); | |
1945 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose); | |
1946 | return 1; | |
47c3ed98 KG |
1947 | /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ |
1948 | lose: ATTRIBUTE_UNUSED_LABEL | |
2055cea7 RK |
1949 | return 0; |
1950 | } | |
1951 | ||
1952 | /* Given an operand OP that is a valid memory reference | |
1953 | which satisfies offsettable_memref_p, | |
1954 | return a new memory reference whose address has been adjusted by OFFSET. | |
1955 | OFFSET should be positive and less than the size of the object referenced. | |
1956 | */ | |
1957 | ||
1958 | rtx | |
1959 | adj_offsettable_operand (op, offset) | |
1960 | rtx op; | |
1961 | int offset; | |
1962 | { | |
1963 | register enum rtx_code code = GET_CODE (op); | |
1964 | ||
1965 | if (code == MEM) | |
1966 | { | |
1967 | register rtx y = XEXP (op, 0); | |
1968 | register rtx new; | |
1969 | ||
1970 | if (CONSTANT_ADDRESS_P (y)) | |
1971 | { | |
38a448ca | 1972 | new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset)); |
2055cea7 RK |
1973 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); |
1974 | return new; | |
1975 | } | |
1976 | ||
1977 | if (GET_CODE (y) == PLUS) | |
1978 | { | |
1979 | rtx z = y; | |
1980 | register rtx *const_loc; | |
1981 | ||
1982 | op = copy_rtx (op); | |
1983 | z = XEXP (op, 0); | |
1984 | const_loc = find_constant_term_loc (&z); | |
1985 | if (const_loc) | |
1986 | { | |
1987 | *const_loc = plus_constant_for_output (*const_loc, offset); | |
1988 | return op; | |
1989 | } | |
1990 | } | |
1991 | ||
38a448ca | 1992 | new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset)); |
2055cea7 RK |
1993 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); |
1994 | return new; | |
1995 | } | |
1996 | abort (); | |
1997 | } | |
1998 | \f | |
0a578fee BS |
1999 | /* Analyze INSN and compute the variables recog_n_operands, recog_n_dups, |
2000 | recog_n_alternatives, recog_operand, recog_operand_loc, recog_constraints, | |
2001 | recog_operand_mode, recog_dup_loc and recog_dup_num. | |
2002 | If REGISTER_CONSTRAINTS is not defined, also compute | |
2003 | recog_operand_address_p. */ | |
2004 | void | |
2005 | extract_insn (insn) | |
2006 | rtx insn; | |
2007 | { | |
2008 | int i; | |
2009 | int icode; | |
2010 | int noperands; | |
2011 | rtx body = PATTERN (insn); | |
2012 | ||
2013 | recog_n_operands = 0; | |
2014 | recog_n_alternatives = 0; | |
2015 | recog_n_dups = 0; | |
2016 | ||
2017 | switch (GET_CODE (body)) | |
2018 | { | |
2019 | case USE: | |
2020 | case CLOBBER: | |
2021 | case ASM_INPUT: | |
2022 | case ADDR_VEC: | |
2023 | case ADDR_DIFF_VEC: | |
2024 | return; | |
2025 | ||
2026 | case SET: | |
2027 | case PARALLEL: | |
2028 | case ASM_OPERANDS: | |
2029 | recog_n_operands = noperands = asm_noperands (body); | |
2030 | if (noperands >= 0) | |
2031 | { | |
0a578fee BS |
2032 | /* This insn is an `asm' with operands. */ |
2033 | ||
2034 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
2035 | if (noperands > MAX_RECOG_OPERANDS) | |
2036 | abort (); | |
2037 | ||
2038 | /* Now get the operand values and constraints out of the insn. */ | |
2039 | decode_asm_operands (body, recog_operand, recog_operand_loc, | |
2040 | recog_constraints, recog_operand_mode); | |
2041 | if (noperands > 0) | |
2042 | { | |
9b3142b3 | 2043 | const char *p = recog_constraints[0]; |
0a578fee BS |
2044 | recog_n_alternatives = 1; |
2045 | while (*p) | |
2046 | recog_n_alternatives += (*p++ == ','); | |
2047 | } | |
2048 | #ifndef REGISTER_CONSTRAINTS | |
2049 | bzero (recog_operand_address_p, sizeof recog_operand_address_p); | |
2050 | #endif | |
2051 | break; | |
2052 | } | |
2053 | ||
2054 | /* FALLTHROUGH */ | |
2055 | ||
2056 | default: | |
2057 | /* Ordinary insn: recognize it, get the operands via insn_extract | |
2058 | and get the constraints. */ | |
2059 | ||
2060 | icode = recog_memoized (insn); | |
2061 | if (icode < 0) | |
2062 | fatal_insn_not_found (insn); | |
2063 | ||
2064 | recog_n_operands = noperands = insn_n_operands[icode]; | |
2065 | recog_n_alternatives = insn_n_alternatives[icode]; | |
2066 | recog_n_dups = insn_n_dups[icode]; | |
2067 | ||
2068 | insn_extract (insn); | |
2069 | ||
2070 | for (i = 0; i < noperands; i++) | |
2071 | { | |
2072 | #ifdef REGISTER_CONSTRAINTS | |
2073 | recog_constraints[i] = insn_operand_constraint[icode][i]; | |
2074 | #else | |
2075 | recog_operand_address_p[i] = insn_operand_address_p[icode][i]; | |
2076 | #endif | |
2077 | recog_operand_mode[i] = insn_operand_mode[icode][i]; | |
2078 | } | |
2079 | } | |
0eadeb15 BS |
2080 | for (i = 0; i < noperands; i++) |
2081 | recog_op_type[i] = (recog_constraints[i][0] == '=' ? OP_OUT | |
2082 | : recog_constraints[i][0] == '+' ? OP_INOUT | |
2083 | : OP_IN); | |
f62a15e3 BS |
2084 | |
2085 | if (recog_n_alternatives > MAX_RECOG_ALTERNATIVES) | |
2086 | abort (); | |
0a578fee BS |
2087 | } |
2088 | ||
f62a15e3 BS |
2089 | /* After calling extract_insn, you can use this function to extract some |
2090 | information from the constraint strings into a more usable form. | |
2091 | The collected data is stored in recog_op_alt. */ | |
2092 | void | |
2093 | preprocess_constraints () | |
2094 | { | |
2095 | int i; | |
2096 | ||
cc3dea85 | 2097 | bzero (recog_op_alt, sizeof recog_op_alt); |
f62a15e3 BS |
2098 | for (i = 0; i < recog_n_operands; i++) |
2099 | { | |
2100 | int j; | |
2101 | struct operand_alternative *op_alt; | |
9b3142b3 | 2102 | const char *p = recog_constraints[i]; |
f62a15e3 BS |
2103 | |
2104 | op_alt = recog_op_alt[i]; | |
2105 | ||
2106 | for (j = 0; j < recog_n_alternatives; j++) | |
2107 | { | |
2108 | op_alt[j].class = NO_REGS; | |
2109 | op_alt[j].constraint = p; | |
2110 | op_alt[j].matches = -1; | |
2111 | op_alt[j].matched = -1; | |
2112 | ||
2113 | if (*p == '\0' || *p == ',') | |
2114 | { | |
2115 | op_alt[j].anything_ok = 1; | |
2116 | continue; | |
2117 | } | |
2118 | ||
2119 | for (;;) | |
2120 | { | |
2121 | char c = *p++; | |
2122 | if (c == '#') | |
2123 | do | |
2124 | c = *p++; | |
2125 | while (c != ',' && c != '\0'); | |
2126 | if (c == ',' || c == '\0') | |
2127 | break; | |
2128 | ||
2129 | switch (c) | |
2130 | { | |
2131 | case '=': case '+': case '*': case '%': | |
2132 | case 'E': case 'F': case 'G': case 'H': | |
2133 | case 's': case 'i': case 'n': | |
2134 | case 'I': case 'J': case 'K': case 'L': | |
2135 | case 'M': case 'N': case 'O': case 'P': | |
2136 | #ifdef EXTRA_CONSTRAINT | |
2137 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
2138 | #endif | |
2139 | /* These don't say anything we care about. */ | |
2140 | break; | |
2141 | ||
2142 | case '?': | |
2143 | op_alt[j].reject += 6; | |
2144 | break; | |
2145 | case '!': | |
2146 | op_alt[j].reject += 600; | |
2147 | break; | |
2148 | case '&': | |
2149 | op_alt[j].earlyclobber = 1; | |
2150 | break; | |
2151 | ||
2152 | case '0': case '1': case '2': case '3': case '4': | |
2153 | case '5': case '6': case '7': case '8': case '9': | |
2154 | op_alt[j].matches = c - '0'; | |
2155 | op_alt[op_alt[j].matches].matched = i; | |
2156 | break; | |
2157 | ||
2158 | case 'm': | |
2159 | op_alt[j].memory_ok = 1; | |
2160 | break; | |
2161 | case '<': | |
2162 | op_alt[j].decmem_ok = 1; | |
2163 | break; | |
2164 | case '>': | |
2165 | op_alt[j].incmem_ok = 1; | |
2166 | break; | |
2167 | case 'V': | |
2168 | op_alt[j].nonoffmem_ok = 1; | |
2169 | break; | |
2170 | case 'o': | |
2171 | op_alt[j].offmem_ok = 1; | |
2172 | break; | |
2173 | case 'X': | |
2174 | op_alt[j].anything_ok = 1; | |
2175 | break; | |
2176 | ||
2177 | case 'p': | |
2178 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS]; | |
2179 | break; | |
2180 | ||
2181 | case 'g': case 'r': | |
2182 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS]; | |
2183 | break; | |
2184 | ||
2185 | default: | |
973838fd | 2186 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
f62a15e3 BS |
2187 | break; |
2188 | } | |
2189 | } | |
2190 | } | |
2191 | } | |
2192 | } | |
2193 | ||
2055cea7 RK |
2194 | #ifdef REGISTER_CONSTRAINTS |
2195 | ||
0eadeb15 | 2196 | /* Check the operands of an insn against the insn's operand constraints |
2055cea7 | 2197 | and return 1 if they are valid. |
0eadeb15 BS |
2198 | The information about the insn's operands, constraints, operand modes |
2199 | etc. is obtained from the global variables set up by extract_insn. | |
2055cea7 RK |
2200 | |
2201 | WHICH_ALTERNATIVE is set to a number which indicates which | |
2202 | alternative of constraints was matched: 0 for the first alternative, | |
2203 | 1 for the next, etc. | |
2204 | ||
2205 | In addition, when two operands are match | |
2206 | and it happens that the output operand is (reg) while the | |
2207 | input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), | |
2208 | make the output operand look like the input. | |
2209 | This is because the output operand is the one the template will print. | |
2210 | ||
2211 | This is used in final, just before printing the assembler code and by | |
2212 | the routines that determine an insn's attribute. | |
2213 | ||
2214 | If STRICT is a positive non-zero value, it means that we have been | |
2215 | called after reload has been completed. In that case, we must | |
2216 | do all checks strictly. If it is zero, it means that we have been called | |
2217 | before reload has completed. In that case, we first try to see if we can | |
2218 | find an alternative that matches strictly. If not, we try again, this | |
2219 | time assuming that reload will fix up the insn. This provides a "best | |
2220 | guess" for the alternative and is used to compute attributes of insns prior | |
2221 | to reload. A negative value of STRICT is used for this internal call. */ | |
2222 | ||
2223 | struct funny_match | |
2224 | { | |
2225 | int this, other; | |
2226 | }; | |
2227 | ||
2228 | int | |
0eadeb15 | 2229 | constrain_operands (strict) |
2055cea7 RK |
2230 | int strict; |
2231 | { | |
9b3142b3 | 2232 | const char *constraints[MAX_RECOG_OPERANDS]; |
9e21be9d | 2233 | int matching_operands[MAX_RECOG_OPERANDS]; |
9e21be9d | 2234 | int earlyclobber[MAX_RECOG_OPERANDS]; |
2055cea7 | 2235 | register int c; |
2055cea7 RK |
2236 | |
2237 | struct funny_match funny_match[MAX_RECOG_OPERANDS]; | |
2238 | int funny_match_index; | |
2055cea7 | 2239 | |
0eadeb15 | 2240 | if (recog_n_operands == 0 || recog_n_alternatives == 0) |
2055cea7 RK |
2241 | return 1; |
2242 | ||
0eadeb15 | 2243 | for (c = 0; c < recog_n_operands; c++) |
9e21be9d | 2244 | { |
0eadeb15 | 2245 | constraints[c] = recog_constraints[c]; |
9e21be9d | 2246 | matching_operands[c] = -1; |
9e21be9d | 2247 | } |
2055cea7 RK |
2248 | |
2249 | which_alternative = 0; | |
2250 | ||
0eadeb15 | 2251 | while (which_alternative < recog_n_alternatives) |
2055cea7 RK |
2252 | { |
2253 | register int opno; | |
2254 | int lose = 0; | |
2255 | funny_match_index = 0; | |
2256 | ||
0eadeb15 | 2257 | for (opno = 0; opno < recog_n_operands; opno++) |
2055cea7 RK |
2258 | { |
2259 | register rtx op = recog_operand[opno]; | |
2260 | enum machine_mode mode = GET_MODE (op); | |
9b3142b3 | 2261 | register const char *p = constraints[opno]; |
2055cea7 RK |
2262 | int offset = 0; |
2263 | int win = 0; | |
2264 | int val; | |
2265 | ||
9e21be9d RK |
2266 | earlyclobber[opno] = 0; |
2267 | ||
b85f21c0 | 2268 | /* A unary operator may be accepted by the predicate, but it |
38a448ca | 2269 | is irrelevant for matching constraints. */ |
b85f21c0 ILT |
2270 | if (GET_RTX_CLASS (GET_CODE (op)) == '1') |
2271 | op = XEXP (op, 0); | |
2272 | ||
2055cea7 RK |
2273 | if (GET_CODE (op) == SUBREG) |
2274 | { | |
2275 | if (GET_CODE (SUBREG_REG (op)) == REG | |
2276 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) | |
2277 | offset = SUBREG_WORD (op); | |
2278 | op = SUBREG_REG (op); | |
2279 | } | |
2280 | ||
2281 | /* An empty constraint or empty alternative | |
2282 | allows anything which matched the pattern. */ | |
2283 | if (*p == 0 || *p == ',') | |
2284 | win = 1; | |
2285 | ||
2286 | while (*p && (c = *p++) != ',') | |
2287 | switch (c) | |
2288 | { | |
2055cea7 | 2289 | case '?': |
2055cea7 RK |
2290 | case '!': |
2291 | case '*': | |
2292 | case '%': | |
0eadeb15 BS |
2293 | case '=': |
2294 | case '+': | |
2055cea7 RK |
2295 | break; |
2296 | ||
4d3067db RK |
2297 | case '#': |
2298 | /* Ignore rest of this alternative as far as | |
2299 | constraint checking is concerned. */ | |
2300 | while (*p && *p != ',') | |
2301 | p++; | |
2302 | break; | |
2303 | ||
9e21be9d RK |
2304 | case '&': |
2305 | earlyclobber[opno] = 1; | |
2306 | break; | |
2307 | ||
62674ffe JH |
2308 | case '0': case '1': case '2': case '3': case '4': |
2309 | case '5': case '6': case '7': case '8': case '9': | |
2055cea7 RK |
2310 | /* This operand must be the same as a previous one. |
2311 | This kind of constraint is used for instructions such | |
2312 | as add when they take only two operands. | |
2313 | ||
2314 | Note that the lower-numbered operand is passed first. | |
2315 | ||
2316 | If we are not testing strictly, assume that this constraint | |
2317 | will be satisfied. */ | |
2318 | if (strict < 0) | |
2319 | val = 1; | |
2320 | else | |
62674ffe JH |
2321 | { |
2322 | rtx op1 = recog_operand[c - '0']; | |
2323 | rtx op2 = recog_operand[opno]; | |
2324 | ||
2325 | /* A unary operator may be accepted by the predicate, | |
2326 | but it is irrelevant for matching constraints. */ | |
2327 | if (GET_RTX_CLASS (GET_CODE (op1)) == '1') | |
2328 | op1 = XEXP (op1, 0); | |
2329 | if (GET_RTX_CLASS (GET_CODE (op2)) == '1') | |
2330 | op2 = XEXP (op2, 0); | |
2331 | ||
2332 | val = operands_match_p (op1, op2); | |
2333 | } | |
2055cea7 | 2334 | |
9e21be9d RK |
2335 | matching_operands[opno] = c - '0'; |
2336 | matching_operands[c - '0'] = opno; | |
2337 | ||
2055cea7 RK |
2338 | if (val != 0) |
2339 | win = 1; | |
2340 | /* If output is *x and input is *--x, | |
2341 | arrange later to change the output to *--x as well, | |
2342 | since the output op is the one that will be printed. */ | |
2343 | if (val == 2 && strict > 0) | |
2344 | { | |
2345 | funny_match[funny_match_index].this = opno; | |
2346 | funny_match[funny_match_index++].other = c - '0'; | |
2347 | } | |
2348 | break; | |
2349 | ||
2350 | case 'p': | |
2351 | /* p is used for address_operands. When we are called by | |
a8647766 RK |
2352 | gen_reload, no one will have checked that the address is |
2353 | strictly valid, i.e., that all pseudos requiring hard regs | |
2354 | have gotten them. */ | |
2055cea7 | 2355 | if (strict <= 0 |
0eadeb15 BS |
2356 | || (strict_memory_address_p (recog_operand_mode[opno], |
2357 | op))) | |
2055cea7 RK |
2358 | win = 1; |
2359 | break; | |
2360 | ||
2361 | /* No need to check general_operand again; | |
2362 | it was done in insn-recog.c. */ | |
2363 | case 'g': | |
2364 | /* Anything goes unless it is a REG and really has a hard reg | |
2365 | but the hard reg is not in the class GENERAL_REGS. */ | |
2366 | if (strict < 0 | |
2367 | || GENERAL_REGS == ALL_REGS | |
2368 | || GET_CODE (op) != REG | |
3c3eeea6 RK |
2369 | || (reload_in_progress |
2370 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2055cea7 RK |
2371 | || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) |
2372 | win = 1; | |
2373 | break; | |
2374 | ||
2375 | case 'r': | |
2376 | if (strict < 0 | |
2377 | || (strict == 0 | |
2378 | && GET_CODE (op) == REG | |
2379 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2380 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
2381 | || (GET_CODE (op) == REG | |
5a19ad3f RK |
2382 | && ((GENERAL_REGS == ALL_REGS |
2383 | && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
2055cea7 RK |
2384 | || reg_fits_class_p (op, GENERAL_REGS, |
2385 | offset, mode)))) | |
2386 | win = 1; | |
2387 | break; | |
2388 | ||
2389 | case 'X': | |
0f41302f MS |
2390 | /* This is used for a MATCH_SCRATCH in the cases when |
2391 | we don't actually need anything. So anything goes | |
2392 | any time. */ | |
2055cea7 RK |
2393 | win = 1; |
2394 | break; | |
2395 | ||
2396 | case 'm': | |
2397 | if (GET_CODE (op) == MEM | |
2398 | /* Before reload, accept what reload can turn into mem. */ | |
3c3eeea6 RK |
2399 | || (strict < 0 && CONSTANT_P (op)) |
2400 | /* During reload, accept a pseudo */ | |
2401 | || (reload_in_progress && GET_CODE (op) == REG | |
2402 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2403 | win = 1; |
2404 | break; | |
2405 | ||
2406 | case '<': | |
2407 | if (GET_CODE (op) == MEM | |
2408 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
2409 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
2410 | win = 1; | |
2411 | break; | |
2412 | ||
2413 | case '>': | |
2414 | if (GET_CODE (op) == MEM | |
2415 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
2416 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
2417 | win = 1; | |
2418 | break; | |
2419 | ||
2420 | case 'E': | |
b990f635 | 2421 | #ifndef REAL_ARITHMETIC |
2055cea7 RK |
2422 | /* Match any CONST_DOUBLE, but only if |
2423 | we can examine the bits of it reliably. */ | |
2424 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
9e4223f2 | 2425 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
d1b765a5 | 2426 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
2055cea7 | 2427 | break; |
b990f635 | 2428 | #endif |
2055cea7 RK |
2429 | if (GET_CODE (op) == CONST_DOUBLE) |
2430 | win = 1; | |
2431 | break; | |
2432 | ||
2433 | case 'F': | |
2434 | if (GET_CODE (op) == CONST_DOUBLE) | |
2435 | win = 1; | |
2436 | break; | |
2437 | ||
2438 | case 'G': | |
2439 | case 'H': | |
2440 | if (GET_CODE (op) == CONST_DOUBLE | |
2441 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
2442 | win = 1; | |
2443 | break; | |
2444 | ||
2445 | case 's': | |
2446 | if (GET_CODE (op) == CONST_INT | |
2447 | || (GET_CODE (op) == CONST_DOUBLE | |
2448 | && GET_MODE (op) == VOIDmode)) | |
2449 | break; | |
2450 | case 'i': | |
2451 | if (CONSTANT_P (op)) | |
2452 | win = 1; | |
2453 | break; | |
2454 | ||
2455 | case 'n': | |
2456 | if (GET_CODE (op) == CONST_INT | |
2457 | || (GET_CODE (op) == CONST_DOUBLE | |
2458 | && GET_MODE (op) == VOIDmode)) | |
2459 | win = 1; | |
2460 | break; | |
2461 | ||
2462 | case 'I': | |
2463 | case 'J': | |
2464 | case 'K': | |
2465 | case 'L': | |
2466 | case 'M': | |
2467 | case 'N': | |
2468 | case 'O': | |
2469 | case 'P': | |
2470 | if (GET_CODE (op) == CONST_INT | |
2471 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
2472 | win = 1; | |
2473 | break; | |
2474 | ||
2475 | #ifdef EXTRA_CONSTRAINT | |
2476 | case 'Q': | |
2477 | case 'R': | |
2478 | case 'S': | |
2479 | case 'T': | |
2480 | case 'U': | |
2481 | if (EXTRA_CONSTRAINT (op, c)) | |
2482 | win = 1; | |
2483 | break; | |
2484 | #endif | |
2485 | ||
2486 | case 'V': | |
2487 | if (GET_CODE (op) == MEM | |
69f724c0 JL |
2488 | && ((strict > 0 && ! offsettable_memref_p (op)) |
2489 | || (strict < 0 | |
2490 | && !(CONSTANT_P (op) || GET_CODE (op) == MEM)) | |
2491 | || (reload_in_progress | |
2492 | && !(GET_CODE (op) == REG | |
2493 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))) | |
2055cea7 RK |
2494 | win = 1; |
2495 | break; | |
2496 | ||
2497 | case 'o': | |
2498 | if ((strict > 0 && offsettable_memref_p (op)) | |
2499 | || (strict == 0 && offsettable_nonstrict_memref_p (op)) | |
2500 | /* Before reload, accept what reload can handle. */ | |
2501 | || (strict < 0 | |
3c3eeea6 RK |
2502 | && (CONSTANT_P (op) || GET_CODE (op) == MEM)) |
2503 | /* During reload, accept a pseudo */ | |
2504 | || (reload_in_progress && GET_CODE (op) == REG | |
2505 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2506 | win = 1; |
2507 | break; | |
2508 | ||
2509 | default: | |
2510 | if (strict < 0 | |
2511 | || (strict == 0 | |
2512 | && GET_CODE (op) == REG | |
2513 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2514 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
2515 | || (GET_CODE (op) == REG | |
2516 | && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c), | |
2517 | offset, mode))) | |
2518 | win = 1; | |
2519 | } | |
2520 | ||
2521 | constraints[opno] = p; | |
2522 | /* If this operand did not win somehow, | |
2523 | this alternative loses. */ | |
2524 | if (! win) | |
2525 | lose = 1; | |
2526 | } | |
2527 | /* This alternative won; the operands are ok. | |
2528 | Change whichever operands this alternative says to change. */ | |
2529 | if (! lose) | |
2530 | { | |
9e21be9d RK |
2531 | int opno, eopno; |
2532 | ||
2533 | /* See if any earlyclobber operand conflicts with some other | |
2534 | operand. */ | |
2535 | ||
2536 | if (strict > 0) | |
0eadeb15 | 2537 | for (eopno = 0; eopno < recog_n_operands; eopno++) |
62946075 RS |
2538 | /* Ignore earlyclobber operands now in memory, |
2539 | because we would often report failure when we have | |
2540 | two memory operands, one of which was formerly a REG. */ | |
2541 | if (earlyclobber[eopno] | |
2542 | && GET_CODE (recog_operand[eopno]) == REG) | |
0eadeb15 | 2543 | for (opno = 0; opno < recog_n_operands; opno++) |
9e21be9d | 2544 | if ((GET_CODE (recog_operand[opno]) == MEM |
0eadeb15 | 2545 | || recog_op_type[opno] != OP_OUT) |
9e21be9d | 2546 | && opno != eopno |
0f41302f | 2547 | /* Ignore things like match_operator operands. */ |
0eadeb15 | 2548 | && *recog_constraints[opno] != 0 |
9e21be9d | 2549 | && ! (matching_operands[opno] == eopno |
011063bd JW |
2550 | && operands_match_p (recog_operand[opno], |
2551 | recog_operand[eopno])) | |
9e21be9d RK |
2552 | && ! safe_from_earlyclobber (recog_operand[opno], |
2553 | recog_operand[eopno])) | |
2554 | lose = 1; | |
2555 | ||
2556 | if (! lose) | |
2055cea7 | 2557 | { |
9e21be9d RK |
2558 | while (--funny_match_index >= 0) |
2559 | { | |
2560 | recog_operand[funny_match[funny_match_index].other] | |
2561 | = recog_operand[funny_match[funny_match_index].this]; | |
2562 | } | |
2563 | ||
2564 | return 1; | |
2055cea7 | 2565 | } |
2055cea7 RK |
2566 | } |
2567 | ||
2568 | which_alternative++; | |
2569 | } | |
2570 | ||
2571 | /* If we are about to reject this, but we are not to test strictly, | |
2572 | try a very loose test. Only return failure if it fails also. */ | |
2573 | if (strict == 0) | |
0eadeb15 | 2574 | return constrain_operands (-1); |
2055cea7 RK |
2575 | else |
2576 | return 0; | |
2577 | } | |
2578 | ||
2579 | /* Return 1 iff OPERAND (assumed to be a REG rtx) | |
38a448ca | 2580 | is a hard reg in class CLASS when its regno is offset by OFFSET |
2055cea7 RK |
2581 | and changed to mode MODE. |
2582 | If REG occupies multiple hard regs, all of them must be in CLASS. */ | |
2583 | ||
2584 | int | |
2585 | reg_fits_class_p (operand, class, offset, mode) | |
2586 | rtx operand; | |
2587 | register enum reg_class class; | |
2588 | int offset; | |
2589 | enum machine_mode mode; | |
2590 | { | |
2591 | register int regno = REGNO (operand); | |
2592 | if (regno < FIRST_PSEUDO_REGISTER | |
2593 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2594 | regno + offset)) | |
2595 | { | |
2596 | register int sr; | |
2597 | regno += offset; | |
2598 | for (sr = HARD_REGNO_NREGS (regno, mode) - 1; | |
2599 | sr > 0; sr--) | |
2600 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2601 | regno + sr)) | |
2602 | break; | |
2603 | return sr == 0; | |
2604 | } | |
2605 | ||
2606 | return 0; | |
2607 | } | |
2608 | ||
2609 | #endif /* REGISTER_CONSTRAINTS */ | |
ca545bb5 BM |
2610 | \f |
2611 | /* Do the splitting of insns in the block B. Only try to actually split if | |
2612 | DO_SPLIT is true; otherwise, just remove nops. */ | |
2613 | ||
2614 | void | |
2615 | split_block_insns (b, do_split) | |
2616 | int b; | |
2617 | int do_split; | |
2618 | { | |
2619 | rtx insn, next; | |
2620 | ||
2621 | for (insn = BLOCK_HEAD (b);; insn = next) | |
2622 | { | |
2623 | rtx set; | |
2624 | ||
2625 | /* Can't use `next_real_insn' because that | |
2626 | might go across CODE_LABELS and short-out basic blocks. */ | |
2627 | next = NEXT_INSN (insn); | |
2628 | if (GET_CODE (insn) != INSN) | |
2629 | { | |
2630 | if (insn == BLOCK_END (b)) | |
2631 | break; | |
2632 | ||
2633 | continue; | |
2634 | } | |
2635 | ||
2636 | /* Don't split no-op move insns. These should silently disappear | |
2637 | later in final. Splitting such insns would break the code | |
2638 | that handles REG_NO_CONFLICT blocks. */ | |
2639 | set = single_set (insn); | |
2640 | if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set))) | |
2641 | { | |
2642 | if (insn == BLOCK_END (b)) | |
2643 | break; | |
2644 | ||
2645 | /* Nops get in the way while scheduling, so delete them now if | |
2646 | register allocation has already been done. It is too risky | |
2647 | to try to do this before register allocation, and there are | |
2648 | unlikely to be very many nops then anyways. */ | |
2649 | if (reload_completed) | |
2650 | { | |
2651 | ||
2652 | PUT_CODE (insn, NOTE); | |
2653 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2654 | NOTE_SOURCE_FILE (insn) = 0; | |
2655 | } | |
2656 | ||
2657 | continue; | |
2658 | } | |
2659 | ||
2660 | if (do_split) | |
2661 | { | |
2662 | /* Split insns here to get max fine-grain parallelism. */ | |
2663 | rtx first = PREV_INSN (insn); | |
2664 | rtx notes = REG_NOTES (insn); | |
2665 | rtx last = try_split (PATTERN (insn), insn, 1); | |
2666 | ||
2667 | if (last != insn) | |
2668 | { | |
2669 | /* try_split returns the NOTE that INSN became. */ | |
2670 | first = NEXT_INSN (first); | |
3c4fc1cc | 2671 | #ifdef INSN_SCHEDULING |
ca545bb5 | 2672 | update_flow_info (notes, first, last, insn); |
bbf9d88c | 2673 | #endif |
ca545bb5 BM |
2674 | PUT_CODE (insn, NOTE); |
2675 | NOTE_SOURCE_FILE (insn) = 0; | |
2676 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2677 | if (insn == BLOCK_HEAD (b)) | |
2678 | BLOCK_HEAD (b) = first; | |
2679 | if (insn == BLOCK_END (b)) | |
2680 | { | |
2681 | BLOCK_END (b) = last; | |
2682 | break; | |
2683 | } | |
2684 | } | |
2685 | } | |
2686 | ||
2687 | if (insn == BLOCK_END (b)) | |
2688 | break; | |
2689 | } | |
2690 | } |