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2055cea7 | 1 | /* Subroutines used by or related to instruction recognition. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 |
58b23af8 | 3 | 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
2055cea7 | 4 | |
1322177d | 5 | This file is part of GCC. |
2055cea7 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
2055cea7 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
2055cea7 RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
2055cea7 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
38a448ca | 27 | #include "rtl.h" |
6baf1cc8 | 28 | #include "tm_p.h" |
2055cea7 RK |
29 | #include "insn-config.h" |
30 | #include "insn-attr.h" | |
d80eb1e1 | 31 | #include "hard-reg-set.h" |
2055cea7 RK |
32 | #include "recog.h" |
33 | #include "regs.h" | |
f1ec5147 | 34 | #include "expr.h" |
49ad7cfa | 35 | #include "function.h" |
2055cea7 RK |
36 | #include "flags.h" |
37 | #include "real.h" | |
7f7f8214 | 38 | #include "toplev.h" |
ca545bb5 | 39 | #include "basic-block.h" |
ede7cd44 | 40 | #include "output.h" |
0e9295cf | 41 | #include "reload.h" |
2055cea7 RK |
42 | |
43 | #ifndef STACK_PUSH_CODE | |
44 | #ifdef STACK_GROWS_DOWNWARD | |
45 | #define STACK_PUSH_CODE PRE_DEC | |
46 | #else | |
47 | #define STACK_PUSH_CODE PRE_INC | |
48 | #endif | |
49 | #endif | |
50 | ||
6fbe9bd8 RH |
51 | #ifndef STACK_POP_CODE |
52 | #ifdef STACK_GROWS_DOWNWARD | |
53 | #define STACK_POP_CODE POST_INC | |
54 | #else | |
55 | #define STACK_POP_CODE POST_DEC | |
56 | #endif | |
57 | #endif | |
58 | ||
0c20a65f AJ |
59 | static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx); |
60 | static rtx *find_single_use_1 (rtx, rtx *); | |
61 | static void validate_replace_src_1 (rtx *, void *); | |
62 | static rtx split_insn (rtx); | |
2055cea7 RK |
63 | |
64 | /* Nonzero means allow operands to be volatile. | |
65 | This should be 0 if you are generating rtl, such as if you are calling | |
66 | the functions in optabs.c and expmed.c (most of the time). | |
67 | This should be 1 if all valid insns need to be recognized, | |
68 | such as in regclass.c and final.c and reload.c. | |
69 | ||
70 | init_recog and init_recog_no_volatile are responsible for setting this. */ | |
71 | ||
72 | int volatile_ok; | |
73 | ||
1ccbefce | 74 | struct recog_data recog_data; |
0a578fee | 75 | |
f62a15e3 BS |
76 | /* Contains a vector of operand_alternative structures for every operand. |
77 | Set up by preprocess_constraints. */ | |
78 | struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES]; | |
79 | ||
2055cea7 RK |
80 | /* On return from `constrain_operands', indicate which alternative |
81 | was satisfied. */ | |
82 | ||
83 | int which_alternative; | |
84 | ||
85 | /* Nonzero after end of reload pass. | |
86 | Set to 1 or 0 by toplev.c. | |
87 | Controls the significance of (SUBREG (MEM)). */ | |
88 | ||
89 | int reload_completed; | |
90 | ||
fe3ad572 SC |
91 | /* Nonzero after thread_prologue_and_epilogue_insns has run. */ |
92 | int epilogue_completed; | |
93 | ||
2055cea7 RK |
94 | /* Initialize data used by the function `recog'. |
95 | This must be called once in the compilation of a function | |
96 | before any insn recognition may be done in the function. */ | |
97 | ||
98 | void | |
0c20a65f | 99 | init_recog_no_volatile (void) |
2055cea7 RK |
100 | { |
101 | volatile_ok = 0; | |
102 | } | |
103 | ||
e0069e43 | 104 | void |
0c20a65f | 105 | init_recog (void) |
2055cea7 RK |
106 | { |
107 | volatile_ok = 1; | |
108 | } | |
109 | ||
110 | /* Try recognizing the instruction INSN, | |
111 | and return the code number that results. | |
9faa82d8 | 112 | Remember the code so that repeated calls do not |
2055cea7 RK |
113 | need to spend the time for actual rerecognition. |
114 | ||
115 | This function is the normal interface to instruction recognition. | |
116 | The automatically-generated function `recog' is normally called | |
117 | through this one. (The only exception is in combine.c.) */ | |
118 | ||
119 | int | |
0c20a65f | 120 | recog_memoized_1 (rtx insn) |
2055cea7 RK |
121 | { |
122 | if (INSN_CODE (insn) < 0) | |
6496a589 | 123 | INSN_CODE (insn) = recog (PATTERN (insn), insn, 0); |
2055cea7 RK |
124 | return INSN_CODE (insn); |
125 | } | |
126 | \f | |
127 | /* Check that X is an insn-body for an `asm' with operands | |
128 | and that the operands mentioned in it are legitimate. */ | |
129 | ||
130 | int | |
0c20a65f | 131 | check_asm_operands (rtx x) |
2055cea7 | 132 | { |
1f06ee8d | 133 | int noperands; |
2055cea7 | 134 | rtx *operands; |
9b3142b3 | 135 | const char **constraints; |
2055cea7 RK |
136 | int i; |
137 | ||
1f06ee8d RH |
138 | /* Post-reload, be more strict with things. */ |
139 | if (reload_completed) | |
140 | { | |
141 | /* ??? Doh! We've not got the wrapping insn. Cook one up. */ | |
142 | extract_insn (make_insn_raw (x)); | |
143 | constrain_operands (1); | |
144 | return which_alternative >= 0; | |
145 | } | |
146 | ||
147 | noperands = asm_noperands (x); | |
2055cea7 RK |
148 | if (noperands < 0) |
149 | return 0; | |
150 | if (noperands == 0) | |
151 | return 1; | |
152 | ||
703ad42b KG |
153 | operands = alloca (noperands * sizeof (rtx)); |
154 | constraints = alloca (noperands * sizeof (char *)); | |
1f06ee8d | 155 | |
df4ae160 | 156 | decode_asm_operands (x, operands, NULL, constraints, NULL); |
2055cea7 RK |
157 | |
158 | for (i = 0; i < noperands; i++) | |
1f06ee8d | 159 | { |
9b3142b3 | 160 | const char *c = constraints[i]; |
1afbe1c4 RH |
161 | if (c[0] == '%') |
162 | c++; | |
8e2e89f7 | 163 | if (ISDIGIT ((unsigned char) c[0]) && c[1] == '\0') |
1f06ee8d RH |
164 | c = constraints[c[0] - '0']; |
165 | ||
166 | if (! asm_operand_ok (operands[i], c)) | |
a6a2274a | 167 | return 0; |
1f06ee8d | 168 | } |
2055cea7 RK |
169 | |
170 | return 1; | |
171 | } | |
172 | \f | |
41a972a9 | 173 | /* Static data for the next two routines. */ |
2055cea7 | 174 | |
41a972a9 MM |
175 | typedef struct change_t |
176 | { | |
177 | rtx object; | |
178 | int old_code; | |
179 | rtx *loc; | |
180 | rtx old; | |
181 | } change_t; | |
2055cea7 | 182 | |
41a972a9 MM |
183 | static change_t *changes; |
184 | static int changes_allocated; | |
2055cea7 RK |
185 | |
186 | static int num_changes = 0; | |
187 | ||
4d893612 | 188 | /* Validate a proposed change to OBJECT. LOC is the location in the rtl |
2055cea7 RK |
189 | at which NEW will be placed. If OBJECT is zero, no validation is done, |
190 | the change is simply made. | |
191 | ||
192 | Two types of objects are supported: If OBJECT is a MEM, memory_address_p | |
193 | will be called with the address and mode as parameters. If OBJECT is | |
194 | an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with | |
195 | the change in place. | |
196 | ||
40f03658 | 197 | IN_GROUP is nonzero if this is part of a group of changes that must be |
2055cea7 RK |
198 | performed as a group. In that case, the changes will be stored. The |
199 | function `apply_change_group' will validate and apply the changes. | |
200 | ||
201 | If IN_GROUP is zero, this is a single change. Try to recognize the insn | |
202 | or validate the memory reference with the change applied. If the result | |
203 | is not valid for the machine, suppress the change and return zero. | |
204 | Otherwise, perform the change and return 1. */ | |
205 | ||
206 | int | |
0c20a65f | 207 | validate_change (rtx object, rtx *loc, rtx new, int in_group) |
2055cea7 RK |
208 | { |
209 | rtx old = *loc; | |
210 | ||
211 | if (old == new || rtx_equal_p (old, new)) | |
212 | return 1; | |
213 | ||
41a972a9 | 214 | if (in_group == 0 && num_changes != 0) |
2055cea7 RK |
215 | abort (); |
216 | ||
ffb5e2e2 | 217 | *loc = new; |
2055cea7 RK |
218 | |
219 | /* Save the information describing this change. */ | |
41a972a9 MM |
220 | if (num_changes >= changes_allocated) |
221 | { | |
222 | if (changes_allocated == 0) | |
223 | /* This value allows for repeated substitutions inside complex | |
224 | indexed addresses, or changes in up to 5 insns. */ | |
225 | changes_allocated = MAX_RECOG_OPERANDS * 5; | |
226 | else | |
227 | changes_allocated *= 2; | |
228 | ||
703ad42b | 229 | changes = xrealloc (changes, sizeof (change_t) * changes_allocated); |
41a972a9 | 230 | } |
a6a2274a | 231 | |
41a972a9 MM |
232 | changes[num_changes].object = object; |
233 | changes[num_changes].loc = loc; | |
234 | changes[num_changes].old = old; | |
2055cea7 RK |
235 | |
236 | if (object && GET_CODE (object) != MEM) | |
237 | { | |
238 | /* Set INSN_CODE to force rerecognition of insn. Save old code in | |
239 | case invalid. */ | |
41a972a9 | 240 | changes[num_changes].old_code = INSN_CODE (object); |
2055cea7 RK |
241 | INSN_CODE (object) = -1; |
242 | } | |
243 | ||
244 | num_changes++; | |
245 | ||
246 | /* If we are making a group of changes, return 1. Otherwise, validate the | |
247 | change group we made. */ | |
248 | ||
249 | if (in_group) | |
250 | return 1; | |
251 | else | |
252 | return apply_change_group (); | |
253 | } | |
254 | ||
61719ba7 BS |
255 | /* This subroutine of apply_change_group verifies whether the changes to INSN |
256 | were valid; i.e. whether INSN can still be recognized. */ | |
257 | ||
fb0c0a12 | 258 | int |
0c20a65f | 259 | insn_invalid_p (rtx insn) |
61719ba7 | 260 | { |
fb0c0a12 RK |
261 | rtx pat = PATTERN (insn); |
262 | int num_clobbers = 0; | |
263 | /* If we are before reload and the pattern is a SET, see if we can add | |
264 | clobbers. */ | |
265 | int icode = recog (pat, insn, | |
266 | (GET_CODE (pat) == SET | |
267 | && ! reload_completed && ! reload_in_progress) | |
6496a589 | 268 | ? &num_clobbers : 0); |
61719ba7 BS |
269 | int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; |
270 | ||
a6a2274a | 271 | |
fb0c0a12 RK |
272 | /* If this is an asm and the operand aren't legal, then fail. Likewise if |
273 | this is not an asm and the insn wasn't recognized. */ | |
274 | if ((is_asm && ! check_asm_operands (PATTERN (insn))) | |
275 | || (!is_asm && icode < 0)) | |
61719ba7 BS |
276 | return 1; |
277 | ||
fb0c0a12 RK |
278 | /* If we have to add CLOBBERs, fail if we have to add ones that reference |
279 | hard registers since our callers can't know if they are live or not. | |
280 | Otherwise, add them. */ | |
281 | if (num_clobbers > 0) | |
282 | { | |
283 | rtx newpat; | |
284 | ||
285 | if (added_clobbers_hard_reg_p (icode)) | |
286 | return 1; | |
287 | ||
288 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1)); | |
289 | XVECEXP (newpat, 0, 0) = pat; | |
290 | add_clobbers (newpat, icode); | |
291 | PATTERN (insn) = pat = newpat; | |
292 | } | |
293 | ||
61719ba7 BS |
294 | /* After reload, verify that all constraints are satisfied. */ |
295 | if (reload_completed) | |
296 | { | |
0eadeb15 | 297 | extract_insn (insn); |
61719ba7 | 298 | |
0eadeb15 | 299 | if (! constrain_operands (1)) |
61719ba7 BS |
300 | return 1; |
301 | } | |
302 | ||
fb0c0a12 | 303 | INSN_CODE (insn) = icode; |
61719ba7 BS |
304 | return 0; |
305 | } | |
306 | ||
2b773ee2 JH |
307 | /* Return number of changes made and not validated yet. */ |
308 | int | |
0c20a65f | 309 | num_changes_pending (void) |
2b773ee2 JH |
310 | { |
311 | return num_changes; | |
312 | } | |
313 | ||
2055cea7 RK |
314 | /* Apply a group of changes previously issued with `validate_change'. |
315 | Return 1 if all changes are valid, zero otherwise. */ | |
316 | ||
317 | int | |
0c20a65f | 318 | apply_change_group (void) |
2055cea7 RK |
319 | { |
320 | int i; | |
66aa2d30 | 321 | rtx last_validated = NULL_RTX; |
2055cea7 RK |
322 | |
323 | /* The changes have been applied and all INSN_CODEs have been reset to force | |
324 | rerecognition. | |
325 | ||
326 | The changes are valid if we aren't given an object, or if we are | |
327 | given a MEM and it still is a valid address, or if this is in insn | |
328 | and it is recognized. In the latter case, if reload has completed, | |
329 | we also require that the operands meet the constraints for | |
0eadeb15 | 330 | the insn. */ |
2055cea7 RK |
331 | |
332 | for (i = 0; i < num_changes; i++) | |
333 | { | |
41a972a9 | 334 | rtx object = changes[i].object; |
2055cea7 | 335 | |
66aa2d30 JH |
336 | /* if there is no object to test or if it is the same as the one we |
337 | already tested, ignore it. */ | |
338 | if (object == 0 || object == last_validated) | |
2055cea7 RK |
339 | continue; |
340 | ||
341 | if (GET_CODE (object) == MEM) | |
342 | { | |
343 | if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) | |
344 | break; | |
345 | } | |
61719ba7 | 346 | else if (insn_invalid_p (object)) |
2055cea7 RK |
347 | { |
348 | rtx pat = PATTERN (object); | |
349 | ||
350 | /* Perhaps we couldn't recognize the insn because there were | |
351 | extra CLOBBERs at the end. If so, try to re-recognize | |
352 | without the last CLOBBER (later iterations will cause each of | |
353 | them to be eliminated, in turn). But don't do this if we | |
354 | have an ASM_OPERAND. */ | |
355 | if (GET_CODE (pat) == PARALLEL | |
356 | && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER | |
357 | && asm_noperands (PATTERN (object)) < 0) | |
358 | { | |
ffb5e2e2 AM |
359 | rtx newpat; |
360 | ||
361 | if (XVECLEN (pat, 0) == 2) | |
362 | newpat = XVECEXP (pat, 0, 0); | |
363 | else | |
364 | { | |
365 | int j; | |
366 | ||
367 | newpat | |
a6a2274a | 368 | = gen_rtx_PARALLEL (VOIDmode, |
ffb5e2e2 AM |
369 | rtvec_alloc (XVECLEN (pat, 0) - 1)); |
370 | for (j = 0; j < XVECLEN (newpat, 0); j++) | |
371 | XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); | |
372 | } | |
373 | ||
374 | /* Add a new change to this group to replace the pattern | |
375 | with this new pattern. Then consider this change | |
376 | as having succeeded. The change we added will | |
377 | cause the entire call to fail if things remain invalid. | |
378 | ||
379 | Note that this can lose if a later change than the one | |
380 | we are processing specified &XVECEXP (PATTERN (object), 0, X) | |
381 | but this shouldn't occur. */ | |
382 | ||
383 | validate_change (object, &PATTERN (object), newpat, 1); | |
384 | continue; | |
385 | } | |
2055cea7 RK |
386 | else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) |
387 | /* If this insn is a CLOBBER or USE, it is always valid, but is | |
388 | never recognized. */ | |
389 | continue; | |
390 | else | |
391 | break; | |
392 | } | |
66aa2d30 | 393 | last_validated = object; |
2055cea7 RK |
394 | } |
395 | ||
396 | if (i == num_changes) | |
397 | { | |
38c1593d JH |
398 | basic_block bb; |
399 | ||
400 | for (i = 0; i < num_changes; i++) | |
401 | if (changes[i].object | |
402 | && INSN_P (changes[i].object) | |
38c1593d | 403 | && (bb = BLOCK_FOR_INSN (changes[i].object))) |
a6a2274a | 404 | bb->flags |= BB_DIRTY; |
38c1593d | 405 | |
2055cea7 RK |
406 | num_changes = 0; |
407 | return 1; | |
408 | } | |
409 | else | |
410 | { | |
411 | cancel_changes (0); | |
412 | return 0; | |
413 | } | |
414 | } | |
415 | ||
6d2f8887 | 416 | /* Return the number of changes so far in the current group. */ |
2055cea7 RK |
417 | |
418 | int | |
0c20a65f | 419 | num_validated_changes (void) |
2055cea7 RK |
420 | { |
421 | return num_changes; | |
422 | } | |
423 | ||
424 | /* Retract the changes numbered NUM and up. */ | |
425 | ||
426 | void | |
0c20a65f | 427 | cancel_changes (int num) |
2055cea7 RK |
428 | { |
429 | int i; | |
430 | ||
431 | /* Back out all the changes. Do this in the opposite order in which | |
432 | they were made. */ | |
433 | for (i = num_changes - 1; i >= num; i--) | |
434 | { | |
41a972a9 MM |
435 | *changes[i].loc = changes[i].old; |
436 | if (changes[i].object && GET_CODE (changes[i].object) != MEM) | |
437 | INSN_CODE (changes[i].object) = changes[i].old_code; | |
2055cea7 RK |
438 | } |
439 | num_changes = num; | |
440 | } | |
441 | ||
442 | /* Replace every occurrence of FROM in X with TO. Mark each change with | |
443 | validate_change passing OBJECT. */ | |
444 | ||
445 | static void | |
0c20a65f | 446 | validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx object) |
2055cea7 | 447 | { |
b3694847 SS |
448 | int i, j; |
449 | const char *fmt; | |
450 | rtx x = *loc; | |
22251f80 | 451 | enum rtx_code code; |
30cf266f JH |
452 | enum machine_mode op0_mode = VOIDmode; |
453 | int prev_changes = num_changes; | |
454 | rtx new; | |
2055cea7 | 455 | |
22251f80 JH |
456 | if (!x) |
457 | return; | |
30cf266f | 458 | |
22251f80 | 459 | code = GET_CODE (x); |
30cf266f JH |
460 | fmt = GET_RTX_FORMAT (code); |
461 | if (fmt[0] == 'e') | |
462 | op0_mode = GET_MODE (XEXP (x, 0)); | |
463 | ||
2055cea7 RK |
464 | /* X matches FROM if it is the same rtx or they are both referring to the |
465 | same register in the same mode. Avoid calling rtx_equal_p unless the | |
466 | operands look similar. */ | |
467 | ||
468 | if (x == from | |
469 | || (GET_CODE (x) == REG && GET_CODE (from) == REG | |
470 | && GET_MODE (x) == GET_MODE (from) | |
471 | && REGNO (x) == REGNO (from)) | |
472 | || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) | |
473 | && rtx_equal_p (x, from))) | |
474 | { | |
475 | validate_change (object, loc, to, 1); | |
476 | return; | |
477 | } | |
478 | ||
ffb5e2e2 | 479 | /* Call ourself recursively to perform the replacements. */ |
2055cea7 | 480 | |
30cf266f JH |
481 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
482 | { | |
483 | if (fmt[i] == 'e') | |
484 | validate_replace_rtx_1 (&XEXP (x, i), from, to, object); | |
485 | else if (fmt[i] == 'E') | |
486 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
487 | validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); | |
2055cea7 RK |
488 | } |
489 | ||
ffb5e2e2 | 490 | /* If we didn't substitute, there is nothing more to do. */ |
30cf266f JH |
491 | if (num_changes == prev_changes) |
492 | return; | |
493 | ||
494 | /* Allow substituted expression to have different mode. This is used by | |
495 | regmove to change mode of pseudo register. */ | |
496 | if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode) | |
497 | op0_mode = GET_MODE (XEXP (x, 0)); | |
498 | ||
499 | /* Do changes needed to keep rtx consistent. Don't do any other | |
500 | simplifications, as it is not our job. */ | |
501 | ||
502 | if ((GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') | |
503 | && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) | |
504 | { | |
505 | validate_change (object, loc, | |
506 | gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code | |
507 | : swap_condition (code), | |
508 | GET_MODE (x), XEXP (x, 1), | |
509 | XEXP (x, 0)), 1); | |
510 | x = *loc; | |
511 | code = GET_CODE (x); | |
512 | } | |
06140bdf | 513 | |
2055cea7 RK |
514 | switch (code) |
515 | { | |
516 | case PLUS: | |
38e01259 | 517 | /* If we have a PLUS whose second operand is now a CONST_INT, use |
45ed7228 | 518 | simplify_gen_binary to try to simplify it. |
30cf266f JH |
519 | ??? We may want later to remove this, once simplification is |
520 | separated from this function. */ | |
45ed7228 | 521 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to) |
30cf266f | 522 | validate_change (object, loc, |
aff8a8d5 CM |
523 | simplify_gen_binary |
524 | (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1); | |
30cf266f | 525 | break; |
06140bdf | 526 | case MINUS: |
30cf266f JH |
527 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
528 | || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE) | |
529 | validate_change (object, loc, | |
530 | simplify_gen_binary | |
531 | (PLUS, GET_MODE (x), XEXP (x, 0), | |
532 | simplify_gen_unary (NEG, | |
0068fd96 JH |
533 | GET_MODE (x), XEXP (x, 1), |
534 | GET_MODE (x))), 1); | |
06140bdf | 535 | break; |
2055cea7 RK |
536 | case ZERO_EXTEND: |
537 | case SIGN_EXTEND: | |
30cf266f | 538 | if (GET_MODE (XEXP (x, 0)) == VOIDmode) |
2055cea7 | 539 | { |
30cf266f JH |
540 | new = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0), |
541 | op0_mode); | |
c0e3f87d RH |
542 | /* If any of the above failed, substitute in something that |
543 | we know won't be recognized. */ | |
544 | if (!new) | |
38a448ca | 545 | new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
2055cea7 | 546 | validate_change (object, loc, new, 1); |
2055cea7 RK |
547 | } |
548 | break; | |
2055cea7 | 549 | case SUBREG: |
30cf266f JH |
550 | /* All subregs possible to simplify should be simplified. */ |
551 | new = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode, | |
552 | SUBREG_BYTE (x)); | |
553 | ||
ffb5e2e2 | 554 | /* Subregs of VOIDmode operands are incorrect. */ |
30cf266f JH |
555 | if (!new && GET_MODE (SUBREG_REG (x)) == VOIDmode) |
556 | new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); | |
557 | if (new) | |
558 | validate_change (object, loc, new, 1); | |
2055cea7 | 559 | break; |
2055cea7 RK |
560 | case ZERO_EXTRACT: |
561 | case SIGN_EXTRACT: | |
562 | /* If we are replacing a register with memory, try to change the memory | |
30cf266f JH |
563 | to be the mode required for memory in extract operations (this isn't |
564 | likely to be an insertion operation; if it was, nothing bad will | |
565 | happen, we might just fail in some cases). */ | |
2055cea7 | 566 | |
30cf266f | 567 | if (GET_CODE (XEXP (x, 0)) == MEM |
2055cea7 RK |
568 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
569 | && GET_CODE (XEXP (x, 2)) == CONST_INT | |
30cf266f JH |
570 | && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0)) |
571 | && !MEM_VOLATILE_P (XEXP (x, 0))) | |
2055cea7 RK |
572 | { |
573 | enum machine_mode wanted_mode = VOIDmode; | |
30cf266f | 574 | enum machine_mode is_mode = GET_MODE (XEXP (x, 0)); |
2055cea7 RK |
575 | int pos = INTVAL (XEXP (x, 2)); |
576 | ||
da920570 | 577 | if (GET_CODE (x) == ZERO_EXTRACT) |
0d8e55d8 | 578 | { |
da920570 ZW |
579 | enum machine_mode new_mode |
580 | = mode_for_extraction (EP_extzv, 1); | |
581 | if (new_mode != MAX_MACHINE_MODE) | |
582 | wanted_mode = new_mode; | |
0d8e55d8 | 583 | } |
da920570 | 584 | else if (GET_CODE (x) == SIGN_EXTRACT) |
0d8e55d8 | 585 | { |
da920570 ZW |
586 | enum machine_mode new_mode |
587 | = mode_for_extraction (EP_extv, 1); | |
588 | if (new_mode != MAX_MACHINE_MODE) | |
589 | wanted_mode = new_mode; | |
0d8e55d8 | 590 | } |
2055cea7 | 591 | |
6dc42e49 | 592 | /* If we have a narrower mode, we can do something. */ |
2055cea7 RK |
593 | if (wanted_mode != VOIDmode |
594 | && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) | |
595 | { | |
596 | int offset = pos / BITS_PER_UNIT; | |
597 | rtx newmem; | |
598 | ||
ddef6bc7 | 599 | /* If the bytes and bits are counted differently, we |
30cf266f | 600 | must adjust the offset. */ |
f76b9db2 | 601 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) |
30cf266f JH |
602 | offset = |
603 | (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) - | |
604 | offset); | |
2055cea7 RK |
605 | |
606 | pos %= GET_MODE_BITSIZE (wanted_mode); | |
607 | ||
f1ec5147 | 608 | newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset); |
2055cea7 | 609 | |
9e4223f2 | 610 | validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); |
2055cea7 RK |
611 | validate_change (object, &XEXP (x, 0), newmem, 1); |
612 | } | |
613 | } | |
614 | ||
615 | break; | |
30cf266f | 616 | |
38a448ca RH |
617 | default: |
618 | break; | |
2055cea7 | 619 | } |
2055cea7 RK |
620 | } |
621 | ||
e251e2a2 JH |
622 | /* Try replacing every occurrence of FROM in subexpression LOC of INSN |
623 | with TO. After all changes have been made, validate by seeing | |
624 | if INSN is still valid. */ | |
625 | ||
626 | int | |
0c20a65f | 627 | validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc) |
e251e2a2 JH |
628 | { |
629 | validate_replace_rtx_1 (loc, from, to, insn); | |
630 | return apply_change_group (); | |
631 | } | |
632 | ||
2055cea7 RK |
633 | /* Try replacing every occurrence of FROM in INSN with TO. After all |
634 | changes have been made, validate by seeing if INSN is still valid. */ | |
635 | ||
636 | int | |
0c20a65f | 637 | validate_replace_rtx (rtx from, rtx to, rtx insn) |
2055cea7 RK |
638 | { |
639 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
640 | return apply_change_group (); | |
641 | } | |
7506f491 | 642 | |
b71e8e84 | 643 | /* Try replacing every occurrence of FROM in INSN with TO. */ |
edfac33e JL |
644 | |
645 | void | |
0c20a65f | 646 | validate_replace_rtx_group (rtx from, rtx to, rtx insn) |
edfac33e JL |
647 | { |
648 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
649 | } | |
650 | ||
e2373f95 RK |
651 | /* Function called by note_uses to replace used subexpressions. */ |
652 | struct validate_replace_src_data | |
fb0c0a12 RK |
653 | { |
654 | rtx from; /* Old RTX */ | |
655 | rtx to; /* New RTX */ | |
656 | rtx insn; /* Insn in which substitution is occurring. */ | |
657 | }; | |
e2373f95 RK |
658 | |
659 | static void | |
0c20a65f | 660 | validate_replace_src_1 (rtx *x, void *data) |
e2373f95 RK |
661 | { |
662 | struct validate_replace_src_data *d | |
663 | = (struct validate_replace_src_data *) data; | |
664 | ||
665 | validate_replace_rtx_1 (x, d->from, d->to, d->insn); | |
666 | } | |
667 | ||
7506f491 | 668 | /* Try replacing every occurrence of FROM in INSN with TO, avoiding |
2b773ee2 | 669 | SET_DESTs. */ |
7506f491 | 670 | |
2b773ee2 | 671 | void |
0c20a65f | 672 | validate_replace_src_group (rtx from, rtx to, rtx insn) |
7506f491 | 673 | { |
e2373f95 | 674 | struct validate_replace_src_data d; |
b71e8e84 | 675 | |
e2373f95 RK |
676 | d.from = from; |
677 | d.to = to; | |
678 | d.insn = insn; | |
679 | note_uses (&PATTERN (insn), validate_replace_src_1, &d); | |
2b773ee2 JH |
680 | } |
681 | ||
d55d8fc7 | 682 | /* Same as validate_replace_src_group, but validate by seeing if |
2b773ee2 JH |
683 | INSN is still valid. */ |
684 | int | |
0c20a65f | 685 | validate_replace_src (rtx from, rtx to, rtx insn) |
2b773ee2 JH |
686 | { |
687 | validate_replace_src_group (from, to, insn); | |
7506f491 DE |
688 | return apply_change_group (); |
689 | } | |
2055cea7 RK |
690 | \f |
691 | #ifdef HAVE_cc0 | |
692 | /* Return 1 if the insn using CC0 set by INSN does not contain | |
693 | any ordered tests applied to the condition codes. | |
694 | EQ and NE tests do not count. */ | |
695 | ||
696 | int | |
0c20a65f | 697 | next_insn_tests_no_inequality (rtx insn) |
2055cea7 | 698 | { |
b3694847 | 699 | rtx next = next_cc0_user (insn); |
2055cea7 RK |
700 | |
701 | /* If there is no next insn, we have to take the conservative choice. */ | |
702 | if (next == 0) | |
703 | return 0; | |
704 | ||
705 | return ((GET_CODE (next) == JUMP_INSN | |
706 | || GET_CODE (next) == INSN | |
707 | || GET_CODE (next) == CALL_INSN) | |
708 | && ! inequality_comparisons_p (PATTERN (next))); | |
709 | } | |
2055cea7 RK |
710 | #endif |
711 | \f | |
712 | /* This is used by find_single_use to locate an rtx that contains exactly one | |
713 | use of DEST, which is typically either a REG or CC0. It returns a | |
714 | pointer to the innermost rtx expression containing DEST. Appearances of | |
715 | DEST that are being used to totally replace it are not counted. */ | |
716 | ||
717 | static rtx * | |
0c20a65f | 718 | find_single_use_1 (rtx dest, rtx *loc) |
2055cea7 RK |
719 | { |
720 | rtx x = *loc; | |
721 | enum rtx_code code = GET_CODE (x); | |
722 | rtx *result = 0; | |
723 | rtx *this_result; | |
724 | int i; | |
6f7d635c | 725 | const char *fmt; |
2055cea7 RK |
726 | |
727 | switch (code) | |
728 | { | |
729 | case CONST_INT: | |
730 | case CONST: | |
731 | case LABEL_REF: | |
732 | case SYMBOL_REF: | |
733 | case CONST_DOUBLE: | |
69ef87e2 | 734 | case CONST_VECTOR: |
2055cea7 RK |
735 | case CLOBBER: |
736 | return 0; | |
737 | ||
738 | case SET: | |
739 | /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
740 | of a REG that occupies all of the REG, the insn uses DEST if | |
741 | it is mentioned in the destination or the source. Otherwise, we | |
742 | need just check the source. */ | |
743 | if (GET_CODE (SET_DEST (x)) != CC0 | |
744 | && GET_CODE (SET_DEST (x)) != PC | |
745 | && GET_CODE (SET_DEST (x)) != REG | |
746 | && ! (GET_CODE (SET_DEST (x)) == SUBREG | |
747 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
748 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
749 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
750 | == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
751 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
752 | break; | |
753 | ||
754 | return find_single_use_1 (dest, &SET_SRC (x)); | |
755 | ||
756 | case MEM: | |
757 | case SUBREG: | |
758 | return find_single_use_1 (dest, &XEXP (x, 0)); | |
a6a2274a | 759 | |
38a448ca RH |
760 | default: |
761 | break; | |
2055cea7 RK |
762 | } |
763 | ||
764 | /* If it wasn't one of the common cases above, check each expression and | |
765 | vector of this code. Look for a unique usage of DEST. */ | |
766 | ||
767 | fmt = GET_RTX_FORMAT (code); | |
768 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
769 | { | |
770 | if (fmt[i] == 'e') | |
771 | { | |
772 | if (dest == XEXP (x, i) | |
773 | || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG | |
774 | && REGNO (dest) == REGNO (XEXP (x, i)))) | |
775 | this_result = loc; | |
776 | else | |
777 | this_result = find_single_use_1 (dest, &XEXP (x, i)); | |
778 | ||
779 | if (result == 0) | |
780 | result = this_result; | |
781 | else if (this_result) | |
782 | /* Duplicate usage. */ | |
783 | return 0; | |
784 | } | |
785 | else if (fmt[i] == 'E') | |
786 | { | |
787 | int j; | |
788 | ||
789 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
790 | { | |
791 | if (XVECEXP (x, i, j) == dest | |
792 | || (GET_CODE (dest) == REG | |
793 | && GET_CODE (XVECEXP (x, i, j)) == REG | |
794 | && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) | |
795 | this_result = loc; | |
796 | else | |
797 | this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); | |
798 | ||
799 | if (result == 0) | |
800 | result = this_result; | |
801 | else if (this_result) | |
802 | return 0; | |
803 | } | |
804 | } | |
805 | } | |
806 | ||
807 | return result; | |
808 | } | |
809 | \f | |
810 | /* See if DEST, produced in INSN, is used only a single time in the | |
811 | sequel. If so, return a pointer to the innermost rtx expression in which | |
812 | it is used. | |
813 | ||
40f03658 | 814 | If PLOC is nonzero, *PLOC is set to the insn containing the single use. |
2055cea7 RK |
815 | |
816 | This routine will return usually zero either before flow is called (because | |
817 | there will be no LOG_LINKS notes) or after reload (because the REG_DEAD | |
818 | note can't be trusted). | |
819 | ||
820 | If DEST is cc0_rtx, we look only at the next insn. In that case, we don't | |
821 | care about REG_DEAD notes or LOG_LINKS. | |
822 | ||
823 | Otherwise, we find the single use by finding an insn that has a | |
824 | LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is | |
825 | only referenced once in that insn, we know that it must be the first | |
826 | and last insn referencing DEST. */ | |
827 | ||
828 | rtx * | |
0c20a65f | 829 | find_single_use (rtx dest, rtx insn, rtx *ploc) |
2055cea7 RK |
830 | { |
831 | rtx next; | |
832 | rtx *result; | |
833 | rtx link; | |
834 | ||
835 | #ifdef HAVE_cc0 | |
836 | if (dest == cc0_rtx) | |
837 | { | |
838 | next = NEXT_INSN (insn); | |
839 | if (next == 0 | |
840 | || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN)) | |
841 | return 0; | |
842 | ||
843 | result = find_single_use_1 (dest, &PATTERN (next)); | |
844 | if (result && ploc) | |
845 | *ploc = next; | |
846 | return result; | |
847 | } | |
848 | #endif | |
849 | ||
850 | if (reload_completed || reload_in_progress || GET_CODE (dest) != REG) | |
851 | return 0; | |
852 | ||
853 | for (next = next_nonnote_insn (insn); | |
854 | next != 0 && GET_CODE (next) != CODE_LABEL; | |
855 | next = next_nonnote_insn (next)) | |
2c3c49de | 856 | if (INSN_P (next) && dead_or_set_p (next, dest)) |
2055cea7 RK |
857 | { |
858 | for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) | |
859 | if (XEXP (link, 0) == insn) | |
860 | break; | |
861 | ||
862 | if (link) | |
863 | { | |
864 | result = find_single_use_1 (dest, &PATTERN (next)); | |
865 | if (ploc) | |
866 | *ploc = next; | |
867 | return result; | |
868 | } | |
869 | } | |
870 | ||
871 | return 0; | |
872 | } | |
873 | \f | |
874 | /* Return 1 if OP is a valid general operand for machine mode MODE. | |
875 | This is either a register reference, a memory reference, | |
876 | or a constant. In the case of a memory reference, the address | |
877 | is checked for general validity for the target machine. | |
878 | ||
879 | Register and memory references must have mode MODE in order to be valid, | |
880 | but some constants have no machine mode and are valid for any mode. | |
881 | ||
882 | If MODE is VOIDmode, OP is checked for validity for whatever mode | |
883 | it has. | |
884 | ||
885 | The main use of this function is as a predicate in match_operand | |
886 | expressions in the machine description. | |
887 | ||
6dc42e49 | 888 | For an explanation of this function's behavior for registers of |
2055cea7 RK |
889 | class NO_REGS, see the comment for `register_operand'. */ |
890 | ||
891 | int | |
0c20a65f | 892 | general_operand (rtx op, enum machine_mode mode) |
2055cea7 | 893 | { |
b3694847 | 894 | enum rtx_code code = GET_CODE (op); |
2055cea7 RK |
895 | |
896 | if (mode == VOIDmode) | |
897 | mode = GET_MODE (op); | |
898 | ||
899 | /* Don't accept CONST_INT or anything similar | |
900 | if the caller wants something floating. */ | |
901 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
902 | && GET_MODE_CLASS (mode) != MODE_INT |
903 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
904 | return 0; |
905 | ||
c033e268 | 906 | if (GET_CODE (op) == CONST_INT |
71012d97 | 907 | && mode != VOIDmode |
c033e268 AO |
908 | && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) |
909 | return 0; | |
910 | ||
2055cea7 | 911 | if (CONSTANT_P (op)) |
8acb2f24 JH |
912 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode |
913 | || mode == VOIDmode) | |
2055cea7 RK |
914 | #ifdef LEGITIMATE_PIC_OPERAND_P |
915 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
916 | #endif | |
917 | && LEGITIMATE_CONSTANT_P (op)); | |
918 | ||
919 | /* Except for certain constants with VOIDmode, already checked for, | |
920 | OP's mode must match MODE if MODE specifies a mode. */ | |
921 | ||
922 | if (GET_MODE (op) != mode) | |
923 | return 0; | |
924 | ||
925 | if (code == SUBREG) | |
926 | { | |
53501a19 BS |
927 | rtx sub = SUBREG_REG (op); |
928 | ||
2055cea7 RK |
929 | #ifdef INSN_SCHEDULING |
930 | /* On machines that have insn scheduling, we want all memory | |
931 | reference to be explicit, so outlaw paradoxical SUBREGs. */ | |
53501a19 BS |
932 | if (GET_CODE (sub) == MEM |
933 | && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub))) | |
2055cea7 RK |
934 | return 0; |
935 | #endif | |
30cf266f JH |
936 | /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory |
937 | may result in incorrect reference. We should simplify all valid | |
e86f9f32 | 938 | subregs of MEM anyway. But allow this after reload because we |
a6a2274a | 939 | might be called from cleanup_subreg_operands. |
e86f9f32 RK |
940 | |
941 | ??? This is a kludge. */ | |
942 | if (!reload_completed && SUBREG_BYTE (op) != 0 | |
53501a19 BS |
943 | && GET_CODE (sub) == MEM) |
944 | return 0; | |
945 | ||
946 | /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally | |
0c20a65f | 947 | create such rtl, and we must reject it. */ |
53501a19 BS |
948 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT |
949 | && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub))) | |
a6a2274a | 950 | return 0; |
2055cea7 | 951 | |
53501a19 | 952 | op = sub; |
2055cea7 | 953 | code = GET_CODE (op); |
2055cea7 RK |
954 | } |
955 | ||
956 | if (code == REG) | |
957 | /* A register whose class is NO_REGS is not a general operand. */ | |
958 | return (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
959 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); | |
960 | ||
961 | if (code == MEM) | |
962 | { | |
b3694847 | 963 | rtx y = XEXP (op, 0); |
4eeaee5d | 964 | |
2055cea7 RK |
965 | if (! volatile_ok && MEM_VOLATILE_P (op)) |
966 | return 0; | |
4eeaee5d | 967 | |
38a448ca RH |
968 | if (GET_CODE (y) == ADDRESSOF) |
969 | return 1; | |
4eeaee5d | 970 | |
2055cea7 RK |
971 | /* Use the mem's mode, since it will be reloaded thus. */ |
972 | mode = GET_MODE (op); | |
973 | GO_IF_LEGITIMATE_ADDRESS (mode, y, win); | |
974 | } | |
38a448ca RH |
975 | |
976 | /* Pretend this is an operand for now; we'll run force_operand | |
977 | on its replacement in fixup_var_refs_1. */ | |
978 | if (code == ADDRESSOF) | |
979 | return 1; | |
980 | ||
2055cea7 RK |
981 | return 0; |
982 | ||
983 | win: | |
2055cea7 RK |
984 | return 1; |
985 | } | |
986 | \f | |
987 | /* Return 1 if OP is a valid memory address for a memory reference | |
988 | of mode MODE. | |
989 | ||
990 | The main use of this function is as a predicate in match_operand | |
991 | expressions in the machine description. */ | |
992 | ||
993 | int | |
0c20a65f | 994 | address_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
995 | { |
996 | return memory_address_p (mode, op); | |
997 | } | |
998 | ||
999 | /* Return 1 if OP is a register reference of mode MODE. | |
1000 | If MODE is VOIDmode, accept a register in any mode. | |
1001 | ||
1002 | The main use of this function is as a predicate in match_operand | |
1003 | expressions in the machine description. | |
1004 | ||
1005 | As a special exception, registers whose class is NO_REGS are | |
1006 | not accepted by `register_operand'. The reason for this change | |
1007 | is to allow the representation of special architecture artifacts | |
1008 | (such as a condition code register) without extending the rtl | |
1009 | definitions. Since registers of class NO_REGS cannot be used | |
1010 | as registers in any case where register classes are examined, | |
1011 | it is most consistent to keep this function from accepting them. */ | |
1012 | ||
1013 | int | |
0c20a65f | 1014 | register_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
1015 | { |
1016 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1017 | return 0; | |
1018 | ||
1019 | if (GET_CODE (op) == SUBREG) | |
1020 | { | |
53501a19 BS |
1021 | rtx sub = SUBREG_REG (op); |
1022 | ||
2055cea7 RK |
1023 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand |
1024 | because it is guaranteed to be reloaded into one. | |
1025 | Just make sure the MEM is valid in itself. | |
1026 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1027 | but currently it does result from (SUBREG (REG)...) where the | |
1028 | reg went on the stack.) */ | |
53501a19 | 1029 | if (! reload_completed && GET_CODE (sub) == MEM) |
2055cea7 | 1030 | return general_operand (op, mode); |
cba057ed | 1031 | |
cff9f8d5 | 1032 | #ifdef CANNOT_CHANGE_MODE_CLASS |
53501a19 BS |
1033 | if (GET_CODE (sub) == REG |
1034 | && REGNO (sub) < FIRST_PSEUDO_REGISTER | |
b0c42aed | 1035 | && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode) |
53501a19 BS |
1036 | && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT |
1037 | && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT) | |
cba057ed RK |
1038 | return 0; |
1039 | #endif | |
1040 | ||
53501a19 BS |
1041 | /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally |
1042 | create such rtl, and we must reject it. */ | |
1043 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT | |
1044 | && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub))) | |
1045 | return 0; | |
1046 | ||
1047 | op = sub; | |
2055cea7 RK |
1048 | } |
1049 | ||
14a774a9 | 1050 | /* If we have an ADDRESSOF, consider it valid since it will be |
dc297297 | 1051 | converted into something that will not be a MEM. */ |
14a774a9 RK |
1052 | if (GET_CODE (op) == ADDRESSOF) |
1053 | return 1; | |
1054 | ||
2055cea7 RK |
1055 | /* We don't consider registers whose class is NO_REGS |
1056 | to be a register operand. */ | |
1057 | return (GET_CODE (op) == REG | |
1058 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1059 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1060 | } | |
1061 | ||
556ffcc5 RH |
1062 | /* Return 1 for a register in Pmode; ignore the tested mode. */ |
1063 | ||
1064 | int | |
0c20a65f | 1065 | pmode_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
556ffcc5 RH |
1066 | { |
1067 | return register_operand (op, Pmode); | |
1068 | } | |
1069 | ||
2055cea7 RK |
1070 | /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH |
1071 | or a hard register. */ | |
1072 | ||
1073 | int | |
0c20a65f | 1074 | scratch_operand (rtx op, enum machine_mode mode) |
2055cea7 | 1075 | { |
a05924f9 JH |
1076 | if (GET_MODE (op) != mode && mode != VOIDmode) |
1077 | return 0; | |
1078 | ||
1079 | return (GET_CODE (op) == SCRATCH | |
1080 | || (GET_CODE (op) == REG | |
1081 | && REGNO (op) < FIRST_PSEUDO_REGISTER)); | |
2055cea7 RK |
1082 | } |
1083 | ||
1084 | /* Return 1 if OP is a valid immediate operand for mode MODE. | |
1085 | ||
1086 | The main use of this function is as a predicate in match_operand | |
1087 | expressions in the machine description. */ | |
1088 | ||
1089 | int | |
0c20a65f | 1090 | immediate_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
1091 | { |
1092 | /* Don't accept CONST_INT or anything similar | |
1093 | if the caller wants something floating. */ | |
1094 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1095 | && GET_MODE_CLASS (mode) != MODE_INT |
1096 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1097 | return 0; |
1098 | ||
c033e268 | 1099 | if (GET_CODE (op) == CONST_INT |
71012d97 | 1100 | && mode != VOIDmode |
c033e268 AO |
1101 | && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) |
1102 | return 0; | |
1103 | ||
ee5332b8 RH |
1104 | /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and |
1105 | result in 0/1. It seems a safe assumption that this is | |
1106 | in range for everyone. */ | |
1107 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
1108 | return 1; | |
1109 | ||
2055cea7 RK |
1110 | return (CONSTANT_P (op) |
1111 | && (GET_MODE (op) == mode || mode == VOIDmode | |
1112 | || GET_MODE (op) == VOIDmode) | |
1113 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1114 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1115 | #endif | |
1116 | && LEGITIMATE_CONSTANT_P (op)); | |
1117 | } | |
1118 | ||
1119 | /* Returns 1 if OP is an operand that is a CONST_INT. */ | |
1120 | ||
1121 | int | |
0c20a65f | 1122 | const_int_operand (rtx op, enum machine_mode mode) |
2055cea7 | 1123 | { |
b4fbaca7 RH |
1124 | if (GET_CODE (op) != CONST_INT) |
1125 | return 0; | |
1126 | ||
1127 | if (mode != VOIDmode | |
1128 | && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) | |
1129 | return 0; | |
1130 | ||
1131 | return 1; | |
2055cea7 RK |
1132 | } |
1133 | ||
1134 | /* Returns 1 if OP is an operand that is a constant integer or constant | |
1135 | floating-point number. */ | |
1136 | ||
1137 | int | |
0c20a65f | 1138 | const_double_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
1139 | { |
1140 | /* Don't accept CONST_INT or anything similar | |
1141 | if the caller wants something floating. */ | |
1142 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1143 | && GET_MODE_CLASS (mode) != MODE_INT |
1144 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1145 | return 0; |
1146 | ||
1147 | return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) | |
1148 | && (mode == VOIDmode || GET_MODE (op) == mode | |
1149 | || GET_MODE (op) == VOIDmode)); | |
1150 | } | |
1151 | ||
1152 | /* Return 1 if OP is a general operand that is not an immediate operand. */ | |
1153 | ||
1154 | int | |
0c20a65f | 1155 | nonimmediate_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
1156 | { |
1157 | return (general_operand (op, mode) && ! CONSTANT_P (op)); | |
1158 | } | |
1159 | ||
1160 | /* Return 1 if OP is a register reference or immediate value of mode MODE. */ | |
1161 | ||
1162 | int | |
0c20a65f | 1163 | nonmemory_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
1164 | { |
1165 | if (CONSTANT_P (op)) | |
1166 | { | |
1167 | /* Don't accept CONST_INT or anything similar | |
1168 | if the caller wants something floating. */ | |
1169 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1170 | && GET_MODE_CLASS (mode) != MODE_INT |
1171 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1172 | return 0; |
1173 | ||
c033e268 | 1174 | if (GET_CODE (op) == CONST_INT |
71012d97 | 1175 | && mode != VOIDmode |
c033e268 AO |
1176 | && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) |
1177 | return 0; | |
1178 | ||
8acb2f24 | 1179 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode |
ffb5e2e2 | 1180 | || mode == VOIDmode) |
2055cea7 RK |
1181 | #ifdef LEGITIMATE_PIC_OPERAND_P |
1182 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1183 | #endif | |
1184 | && LEGITIMATE_CONSTANT_P (op)); | |
1185 | } | |
1186 | ||
1187 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1188 | return 0; | |
1189 | ||
1190 | if (GET_CODE (op) == SUBREG) | |
1191 | { | |
1192 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
1193 | because it is guaranteed to be reloaded into one. | |
1194 | Just make sure the MEM is valid in itself. | |
1195 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1196 | but currently it does result from (SUBREG (REG)...) where the | |
1197 | reg went on the stack.) */ | |
1198 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
1199 | return general_operand (op, mode); | |
1200 | op = SUBREG_REG (op); | |
1201 | } | |
1202 | ||
1203 | /* We don't consider registers whose class is NO_REGS | |
1204 | to be a register operand. */ | |
1205 | return (GET_CODE (op) == REG | |
1206 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1207 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1208 | } | |
1209 | ||
1210 | /* Return 1 if OP is a valid operand that stands for pushing a | |
1211 | value of mode MODE onto the stack. | |
1212 | ||
1213 | The main use of this function is as a predicate in match_operand | |
1214 | expressions in the machine description. */ | |
1215 | ||
1216 | int | |
0c20a65f | 1217 | push_operand (rtx op, enum machine_mode mode) |
2055cea7 | 1218 | { |
a8d19608 RK |
1219 | unsigned int rounded_size = GET_MODE_SIZE (mode); |
1220 | ||
1221 | #ifdef PUSH_ROUNDING | |
1222 | rounded_size = PUSH_ROUNDING (rounded_size); | |
1223 | #endif | |
1224 | ||
2055cea7 RK |
1225 | if (GET_CODE (op) != MEM) |
1226 | return 0; | |
1227 | ||
aeb7ff68 | 1228 | if (mode != VOIDmode && GET_MODE (op) != mode) |
2055cea7 RK |
1229 | return 0; |
1230 | ||
1231 | op = XEXP (op, 0); | |
1232 | ||
a8d19608 | 1233 | if (rounded_size == GET_MODE_SIZE (mode)) |
70a32495 JH |
1234 | { |
1235 | if (GET_CODE (op) != STACK_PUSH_CODE) | |
1236 | return 0; | |
1237 | } | |
1238 | else | |
1239 | { | |
70a32495 JH |
1240 | if (GET_CODE (op) != PRE_MODIFY |
1241 | || GET_CODE (XEXP (op, 1)) != PLUS | |
1242 | || XEXP (XEXP (op, 1), 0) != XEXP (op, 0) | |
1243 | || GET_CODE (XEXP (XEXP (op, 1), 1)) != CONST_INT | |
1244 | #ifdef STACK_GROWS_DOWNWARD | |
a8d19608 | 1245 | || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size |
70a32495 | 1246 | #else |
fc555370 | 1247 | || INTVAL (XEXP (XEXP (op, 1), 1)) != (int) rounded_size |
70a32495 JH |
1248 | #endif |
1249 | ) | |
1250 | return 0; | |
1251 | } | |
2055cea7 RK |
1252 | |
1253 | return XEXP (op, 0) == stack_pointer_rtx; | |
1254 | } | |
1255 | ||
6fbe9bd8 RH |
1256 | /* Return 1 if OP is a valid operand that stands for popping a |
1257 | value of mode MODE off the stack. | |
1258 | ||
1259 | The main use of this function is as a predicate in match_operand | |
1260 | expressions in the machine description. */ | |
1261 | ||
1262 | int | |
0c20a65f | 1263 | pop_operand (rtx op, enum machine_mode mode) |
6fbe9bd8 RH |
1264 | { |
1265 | if (GET_CODE (op) != MEM) | |
1266 | return 0; | |
1267 | ||
aeb7ff68 | 1268 | if (mode != VOIDmode && GET_MODE (op) != mode) |
6fbe9bd8 RH |
1269 | return 0; |
1270 | ||
1271 | op = XEXP (op, 0); | |
1272 | ||
1273 | if (GET_CODE (op) != STACK_POP_CODE) | |
1274 | return 0; | |
1275 | ||
1276 | return XEXP (op, 0) == stack_pointer_rtx; | |
1277 | } | |
1278 | ||
2055cea7 RK |
1279 | /* Return 1 if ADDR is a valid memory address for mode MODE. */ |
1280 | ||
1281 | int | |
0c20a65f | 1282 | memory_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx addr) |
2055cea7 | 1283 | { |
38a448ca RH |
1284 | if (GET_CODE (addr) == ADDRESSOF) |
1285 | return 1; | |
a6a2274a | 1286 | |
2055cea7 RK |
1287 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); |
1288 | return 0; | |
1289 | ||
1290 | win: | |
1291 | return 1; | |
1292 | } | |
1293 | ||
1294 | /* Return 1 if OP is a valid memory reference with mode MODE, | |
1295 | including a valid address. | |
1296 | ||
1297 | The main use of this function is as a predicate in match_operand | |
1298 | expressions in the machine description. */ | |
1299 | ||
1300 | int | |
0c20a65f | 1301 | memory_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
1302 | { |
1303 | rtx inner; | |
1304 | ||
1305 | if (! reload_completed) | |
1306 | /* Note that no SUBREG is a memory operand before end of reload pass, | |
1307 | because (SUBREG (MEM...)) forces reloading into a register. */ | |
1308 | return GET_CODE (op) == MEM && general_operand (op, mode); | |
1309 | ||
1310 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1311 | return 0; | |
1312 | ||
1313 | inner = op; | |
1314 | if (GET_CODE (inner) == SUBREG) | |
1315 | inner = SUBREG_REG (inner); | |
1316 | ||
1317 | return (GET_CODE (inner) == MEM && general_operand (op, mode)); | |
1318 | } | |
1319 | ||
1320 | /* Return 1 if OP is a valid indirect memory reference with mode MODE; | |
1321 | that is, a memory reference whose address is a general_operand. */ | |
1322 | ||
1323 | int | |
0c20a65f | 1324 | indirect_operand (rtx op, enum machine_mode mode) |
2055cea7 RK |
1325 | { |
1326 | /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ | |
1327 | if (! reload_completed | |
1328 | && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) | |
1329 | { | |
b3694847 | 1330 | int offset = SUBREG_BYTE (op); |
2055cea7 RK |
1331 | rtx inner = SUBREG_REG (op); |
1332 | ||
b0e0a0f9 RK |
1333 | if (mode != VOIDmode && GET_MODE (op) != mode) |
1334 | return 0; | |
1335 | ||
2055cea7 RK |
1336 | /* The only way that we can have a general_operand as the resulting |
1337 | address is if OFFSET is zero and the address already is an operand | |
1338 | or if the address is (plus Y (const_int -OFFSET)) and Y is an | |
1339 | operand. */ | |
1340 | ||
1341 | return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode)) | |
1342 | || (GET_CODE (XEXP (inner, 0)) == PLUS | |
1343 | && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT | |
1344 | && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset | |
1345 | && general_operand (XEXP (XEXP (inner, 0), 0), Pmode))); | |
1346 | } | |
1347 | ||
1348 | return (GET_CODE (op) == MEM | |
1349 | && memory_operand (op, mode) | |
1350 | && general_operand (XEXP (op, 0), Pmode)); | |
1351 | } | |
1352 | ||
1353 | /* Return 1 if this is a comparison operator. This allows the use of | |
1354 | MATCH_OPERATOR to recognize all the branch insns. */ | |
1355 | ||
1356 | int | |
0c20a65f | 1357 | comparison_operator (rtx op, enum machine_mode mode) |
2055cea7 RK |
1358 | { |
1359 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
1360 | && GET_RTX_CLASS (GET_CODE (op)) == '<'); | |
1361 | } | |
1362 | \f | |
1363 | /* If BODY is an insn body that uses ASM_OPERANDS, | |
1364 | return the number of operands (both input and output) in the insn. | |
1365 | Otherwise return -1. */ | |
1366 | ||
1367 | int | |
0c20a65f | 1368 | asm_noperands (rtx body) |
2055cea7 | 1369 | { |
6c698a6d | 1370 | switch (GET_CODE (body)) |
2055cea7 | 1371 | { |
6c698a6d JH |
1372 | case ASM_OPERANDS: |
1373 | /* No output operands: return number of input operands. */ | |
1374 | return ASM_OPERANDS_INPUT_LENGTH (body); | |
1375 | case SET: | |
1376 | if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1377 | /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ | |
1378 | return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; | |
1379 | else | |
1380 | return -1; | |
1381 | case PARALLEL: | |
1382 | if (GET_CODE (XVECEXP (body, 0, 0)) == SET | |
1383 | && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) | |
2055cea7 | 1384 | { |
6c698a6d JH |
1385 | /* Multiple output operands, or 1 output plus some clobbers: |
1386 | body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ | |
1387 | int i; | |
1388 | int n_sets; | |
2055cea7 | 1389 | |
6c698a6d JH |
1390 | /* Count backwards through CLOBBERs to determine number of SETs. */ |
1391 | for (i = XVECLEN (body, 0); i > 0; i--) | |
1392 | { | |
1393 | if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) | |
1394 | break; | |
1395 | if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) | |
1396 | return -1; | |
1397 | } | |
2055cea7 | 1398 | |
6c698a6d JH |
1399 | /* N_SETS is now number of output operands. */ |
1400 | n_sets = i; | |
1401 | ||
1402 | /* Verify that all the SETs we have | |
1403 | came from a single original asm_operands insn | |
1404 | (so that invalid combinations are blocked). */ | |
1405 | for (i = 0; i < n_sets; i++) | |
1406 | { | |
1407 | rtx elt = XVECEXP (body, 0, i); | |
1408 | if (GET_CODE (elt) != SET) | |
1409 | return -1; | |
1410 | if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) | |
1411 | return -1; | |
1412 | /* If these ASM_OPERANDS rtx's came from different original insns | |
1413 | then they aren't allowed together. */ | |
1414 | if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) | |
1415 | != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) | |
1416 | return -1; | |
1417 | } | |
1418 | return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) | |
1419 | + n_sets); | |
2055cea7 | 1420 | } |
6c698a6d JH |
1421 | else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) |
1422 | { | |
1423 | /* 0 outputs, but some clobbers: | |
1424 | body is [(asm_operands ...) (clobber (reg ...))...]. */ | |
1425 | int i; | |
2055cea7 | 1426 | |
6c698a6d JH |
1427 | /* Make sure all the other parallel things really are clobbers. */ |
1428 | for (i = XVECLEN (body, 0) - 1; i > 0; i--) | |
1429 | if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) | |
1430 | return -1; | |
2055cea7 | 1431 | |
6c698a6d JH |
1432 | return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); |
1433 | } | |
1434 | else | |
1435 | return -1; | |
1436 | default: | |
1437 | return -1; | |
2055cea7 | 1438 | } |
2055cea7 RK |
1439 | } |
1440 | ||
1441 | /* Assuming BODY is an insn body that uses ASM_OPERANDS, | |
1442 | copy its operands (both input and output) into the vector OPERANDS, | |
1443 | the locations of the operands within the insn into the vector OPERAND_LOCS, | |
1444 | and the constraints for the operands into CONSTRAINTS. | |
1445 | Write the modes of the operands into MODES. | |
1446 | Return the assembler-template. | |
1447 | ||
1448 | If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, | |
1449 | we don't store that info. */ | |
1450 | ||
3cce094d | 1451 | const char * |
0c20a65f AJ |
1452 | decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs, |
1453 | const char **constraints, enum machine_mode *modes) | |
2055cea7 | 1454 | { |
b3694847 | 1455 | int i; |
2055cea7 | 1456 | int noperands; |
3cce094d | 1457 | const char *template = 0; |
2055cea7 RK |
1458 | |
1459 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1460 | { | |
1461 | rtx asmop = SET_SRC (body); | |
1462 | /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */ | |
1463 | ||
1464 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1; | |
1465 | ||
1466 | for (i = 1; i < noperands; i++) | |
1467 | { | |
1468 | if (operand_locs) | |
1469 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1); | |
1470 | if (operands) | |
1471 | operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1); | |
1472 | if (constraints) | |
1473 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1); | |
1474 | if (modes) | |
1475 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1); | |
1476 | } | |
1477 | ||
1478 | /* The output is in the SET. | |
1479 | Its constraint is in the ASM_OPERANDS itself. */ | |
1480 | if (operands) | |
1481 | operands[0] = SET_DEST (body); | |
1482 | if (operand_locs) | |
1483 | operand_locs[0] = &SET_DEST (body); | |
1484 | if (constraints) | |
1485 | constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); | |
1486 | if (modes) | |
1487 | modes[0] = GET_MODE (SET_DEST (body)); | |
1488 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1489 | } | |
1490 | else if (GET_CODE (body) == ASM_OPERANDS) | |
1491 | { | |
1492 | rtx asmop = body; | |
1493 | /* No output operands: BODY is (asm_operands ....). */ | |
1494 | ||
1495 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1496 | ||
1497 | /* The input operands are found in the 1st element vector. */ | |
1498 | /* Constraints for inputs are in the 2nd element vector. */ | |
1499 | for (i = 0; i < noperands; i++) | |
1500 | { | |
1501 | if (operand_locs) | |
1502 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1503 | if (operands) | |
1504 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1505 | if (constraints) | |
1506 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1507 | if (modes) | |
1508 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1509 | } | |
1510 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1511 | } | |
1512 | else if (GET_CODE (body) == PARALLEL | |
f5a5ea4a GS |
1513 | && GET_CODE (XVECEXP (body, 0, 0)) == SET |
1514 | && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) | |
2055cea7 RK |
1515 | { |
1516 | rtx asmop = SET_SRC (XVECEXP (body, 0, 0)); | |
1517 | int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ | |
1518 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1519 | int nout = 0; /* Does not include CLOBBERs. */ | |
1520 | ||
1521 | /* At least one output, plus some CLOBBERs. */ | |
1522 | ||
1523 | /* The outputs are in the SETs. | |
1524 | Their constraints are in the ASM_OPERANDS itself. */ | |
1525 | for (i = 0; i < nparallel; i++) | |
1526 | { | |
1527 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
1528 | break; /* Past last SET */ | |
a6a2274a | 1529 | |
2055cea7 RK |
1530 | if (operands) |
1531 | operands[i] = SET_DEST (XVECEXP (body, 0, i)); | |
1532 | if (operand_locs) | |
1533 | operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); | |
1534 | if (constraints) | |
1535 | constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); | |
1536 | if (modes) | |
1537 | modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); | |
1538 | nout++; | |
1539 | } | |
1540 | ||
1541 | for (i = 0; i < nin; i++) | |
1542 | { | |
1543 | if (operand_locs) | |
1544 | operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i); | |
1545 | if (operands) | |
1546 | operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i); | |
1547 | if (constraints) | |
1548 | constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1549 | if (modes) | |
1550 | modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1551 | } | |
1552 | ||
1553 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1554 | } | |
1555 | else if (GET_CODE (body) == PARALLEL | |
1556 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1557 | { | |
1558 | /* No outputs, but some CLOBBERs. */ | |
1559 | ||
1560 | rtx asmop = XVECEXP (body, 0, 0); | |
1561 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1562 | ||
1563 | for (i = 0; i < nin; i++) | |
1564 | { | |
1565 | if (operand_locs) | |
1566 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1567 | if (operands) | |
1568 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1569 | if (constraints) | |
1570 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1571 | if (modes) | |
1572 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1573 | } | |
1574 | ||
1575 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1576 | } | |
1577 | ||
1578 | return template; | |
1579 | } | |
1f06ee8d | 1580 | |
a6a2274a | 1581 | /* Check if an asm_operand matches it's constraints. |
1afbe1c4 | 1582 | Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ |
1f06ee8d RH |
1583 | |
1584 | int | |
0c20a65f | 1585 | asm_operand_ok (rtx op, const char *constraint) |
1f06ee8d | 1586 | { |
1afbe1c4 RH |
1587 | int result = 0; |
1588 | ||
1f06ee8d RH |
1589 | /* Use constrain_operands after reload. */ |
1590 | if (reload_completed) | |
1591 | abort (); | |
1592 | ||
1593 | while (*constraint) | |
1594 | { | |
97488870 R |
1595 | char c = *constraint; |
1596 | int len; | |
c2cba7a9 | 1597 | switch (c) |
1f06ee8d | 1598 | { |
97488870 R |
1599 | case ',': |
1600 | constraint++; | |
1601 | continue; | |
1f06ee8d RH |
1602 | case '=': |
1603 | case '+': | |
1604 | case '*': | |
1605 | case '%': | |
1f06ee8d RH |
1606 | case '!': |
1607 | case '#': | |
1608 | case '&': | |
97488870 | 1609 | case '?': |
1f06ee8d RH |
1610 | break; |
1611 | ||
1612 | case '0': case '1': case '2': case '3': case '4': | |
1613 | case '5': case '6': case '7': case '8': case '9': | |
1afbe1c4 RH |
1614 | /* For best results, our caller should have given us the |
1615 | proper matching constraint, but we can't actually fail | |
1616 | the check if they didn't. Indicate that results are | |
1617 | inconclusive. */ | |
97488870 | 1618 | do |
84b72302 | 1619 | constraint++; |
97488870 R |
1620 | while (ISDIGIT (*constraint)); |
1621 | if (! result) | |
1622 | result = -1; | |
1623 | continue; | |
1f06ee8d RH |
1624 | |
1625 | case 'p': | |
1626 | if (address_operand (op, VOIDmode)) | |
97488870 | 1627 | result = 1; |
1f06ee8d RH |
1628 | break; |
1629 | ||
1630 | case 'm': | |
1631 | case 'V': /* non-offsettable */ | |
1632 | if (memory_operand (op, VOIDmode)) | |
97488870 | 1633 | result = 1; |
1f06ee8d RH |
1634 | break; |
1635 | ||
1636 | case 'o': /* offsettable */ | |
1637 | if (offsettable_nonstrict_memref_p (op)) | |
97488870 | 1638 | result = 1; |
1f06ee8d RH |
1639 | break; |
1640 | ||
1641 | case '<': | |
1afbe1c4 RH |
1642 | /* ??? Before flow, auto inc/dec insns are not supposed to exist, |
1643 | excepting those that expand_call created. Further, on some | |
1644 | machines which do not have generalized auto inc/dec, an inc/dec | |
1645 | is not a memory_operand. | |
1646 | ||
1647 | Match any memory and hope things are resolved after reload. */ | |
1648 | ||
1f06ee8d | 1649 | if (GET_CODE (op) == MEM |
1afbe1c4 RH |
1650 | && (1 |
1651 | || GET_CODE (XEXP (op, 0)) == PRE_DEC | |
a6a2274a | 1652 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) |
97488870 | 1653 | result = 1; |
1f06ee8d RH |
1654 | break; |
1655 | ||
1656 | case '>': | |
1657 | if (GET_CODE (op) == MEM | |
1afbe1c4 RH |
1658 | && (1 |
1659 | || GET_CODE (XEXP (op, 0)) == PRE_INC | |
a6a2274a | 1660 | || GET_CODE (XEXP (op, 0)) == POST_INC)) |
97488870 | 1661 | result = 1; |
1f06ee8d RH |
1662 | break; |
1663 | ||
1664 | case 'E': | |
1f06ee8d | 1665 | case 'F': |
bf7cd754 R |
1666 | if (GET_CODE (op) == CONST_DOUBLE |
1667 | || (GET_CODE (op) == CONST_VECTOR | |
1668 | && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT)) | |
97488870 | 1669 | result = 1; |
1f06ee8d RH |
1670 | break; |
1671 | ||
1672 | case 'G': | |
1673 | if (GET_CODE (op) == CONST_DOUBLE | |
97488870 R |
1674 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', constraint)) |
1675 | result = 1; | |
1f06ee8d RH |
1676 | break; |
1677 | case 'H': | |
1678 | if (GET_CODE (op) == CONST_DOUBLE | |
97488870 R |
1679 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'H', constraint)) |
1680 | result = 1; | |
1f06ee8d RH |
1681 | break; |
1682 | ||
1683 | case 's': | |
1684 | if (GET_CODE (op) == CONST_INT | |
1685 | || (GET_CODE (op) == CONST_DOUBLE | |
1686 | && GET_MODE (op) == VOIDmode)) | |
1687 | break; | |
1688 | /* FALLTHRU */ | |
1689 | ||
1690 | case 'i': | |
1691 | if (CONSTANT_P (op) | |
1692 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1693 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1694 | #endif | |
1695 | ) | |
97488870 | 1696 | result = 1; |
1f06ee8d RH |
1697 | break; |
1698 | ||
1699 | case 'n': | |
1700 | if (GET_CODE (op) == CONST_INT | |
1701 | || (GET_CODE (op) == CONST_DOUBLE | |
1702 | && GET_MODE (op) == VOIDmode)) | |
97488870 | 1703 | result = 1; |
1f06ee8d RH |
1704 | break; |
1705 | ||
1706 | case 'I': | |
1707 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1708 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'I', constraint)) |
1709 | result = 1; | |
1f06ee8d RH |
1710 | break; |
1711 | case 'J': | |
1712 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1713 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'J', constraint)) |
1714 | result = 1; | |
1f06ee8d RH |
1715 | break; |
1716 | case 'K': | |
1717 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1718 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'K', constraint)) |
1719 | result = 1; | |
1f06ee8d RH |
1720 | break; |
1721 | case 'L': | |
1722 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1723 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'L', constraint)) |
1724 | result = 1; | |
1f06ee8d RH |
1725 | break; |
1726 | case 'M': | |
1727 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1728 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'M', constraint)) |
1729 | result = 1; | |
1f06ee8d RH |
1730 | break; |
1731 | case 'N': | |
1732 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1733 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'N', constraint)) |
1734 | result = 1; | |
1f06ee8d RH |
1735 | break; |
1736 | case 'O': | |
1737 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1738 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'O', constraint)) |
1739 | result = 1; | |
1f06ee8d RH |
1740 | break; |
1741 | case 'P': | |
1742 | if (GET_CODE (op) == CONST_INT | |
97488870 R |
1743 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'P', constraint)) |
1744 | result = 1; | |
1f06ee8d RH |
1745 | break; |
1746 | ||
1747 | case 'X': | |
97488870 | 1748 | result = 1; |
1f06ee8d RH |
1749 | |
1750 | case 'g': | |
1751 | if (general_operand (op, VOIDmode)) | |
97488870 | 1752 | result = 1; |
1f06ee8d RH |
1753 | break; |
1754 | ||
c2cba7a9 RH |
1755 | default: |
1756 | /* For all other letters, we first check for a register class, | |
1757 | otherwise it is an EXTRA_CONSTRAINT. */ | |
97488870 | 1758 | if (REG_CLASS_FROM_CONSTRAINT (c, constraint) != NO_REGS) |
c2cba7a9 RH |
1759 | { |
1760 | case 'r': | |
1761 | if (GET_MODE (op) == BLKmode) | |
1762 | break; | |
1763 | if (register_operand (op, VOIDmode)) | |
97488870 | 1764 | result = 1; |
c2cba7a9 | 1765 | } |
97488870 R |
1766 | #ifdef EXTRA_CONSTRAINT_STR |
1767 | if (EXTRA_CONSTRAINT_STR (op, c, constraint)) | |
1768 | result = 1; | |
1769 | if (EXTRA_MEMORY_CONSTRAINT (c, constraint)) | |
ccfc6cc8 UW |
1770 | { |
1771 | /* Every memory operand can be reloaded to fit. */ | |
1772 | if (memory_operand (op, VOIDmode)) | |
97488870 | 1773 | result = 1; |
ccfc6cc8 | 1774 | } |
97488870 | 1775 | if (EXTRA_ADDRESS_CONSTRAINT (c, constraint)) |
ccfc6cc8 UW |
1776 | { |
1777 | /* Every address operand can be reloaded to fit. */ | |
1778 | if (address_operand (op, VOIDmode)) | |
97488870 | 1779 | result = 1; |
ccfc6cc8 | 1780 | } |
1f06ee8d | 1781 | #endif |
1f06ee8d RH |
1782 | break; |
1783 | } | |
97488870 R |
1784 | len = CONSTRAINT_LEN (c, constraint); |
1785 | do | |
1786 | constraint++; | |
1787 | while (--len && *constraint); | |
1788 | if (len) | |
1789 | return 0; | |
1f06ee8d RH |
1790 | } |
1791 | ||
1afbe1c4 | 1792 | return result; |
1f06ee8d | 1793 | } |
2055cea7 | 1794 | \f |
2055cea7 RK |
1795 | /* Given an rtx *P, if it is a sum containing an integer constant term, |
1796 | return the location (type rtx *) of the pointer to that constant term. | |
1797 | Otherwise, return a null pointer. */ | |
1798 | ||
b72f00af | 1799 | rtx * |
0c20a65f | 1800 | find_constant_term_loc (rtx *p) |
2055cea7 | 1801 | { |
b3694847 SS |
1802 | rtx *tem; |
1803 | enum rtx_code code = GET_CODE (*p); | |
2055cea7 RK |
1804 | |
1805 | /* If *P IS such a constant term, P is its location. */ | |
1806 | ||
1807 | if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF | |
1808 | || code == CONST) | |
1809 | return p; | |
1810 | ||
1811 | /* Otherwise, if not a sum, it has no constant term. */ | |
1812 | ||
1813 | if (GET_CODE (*p) != PLUS) | |
1814 | return 0; | |
1815 | ||
1816 | /* If one of the summands is constant, return its location. */ | |
1817 | ||
1818 | if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) | |
1819 | && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) | |
1820 | return p; | |
1821 | ||
1822 | /* Otherwise, check each summand for containing a constant term. */ | |
1823 | ||
1824 | if (XEXP (*p, 0) != 0) | |
1825 | { | |
1826 | tem = find_constant_term_loc (&XEXP (*p, 0)); | |
1827 | if (tem != 0) | |
1828 | return tem; | |
1829 | } | |
1830 | ||
1831 | if (XEXP (*p, 1) != 0) | |
1832 | { | |
1833 | tem = find_constant_term_loc (&XEXP (*p, 1)); | |
1834 | if (tem != 0) | |
1835 | return tem; | |
1836 | } | |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | \f | |
1841 | /* Return 1 if OP is a memory reference | |
1842 | whose address contains no side effects | |
1843 | and remains valid after the addition | |
1844 | of a positive integer less than the | |
1845 | size of the object being referenced. | |
1846 | ||
1847 | We assume that the original address is valid and do not check it. | |
1848 | ||
1849 | This uses strict_memory_address_p as a subroutine, so | |
1850 | don't use it before reload. */ | |
1851 | ||
1852 | int | |
0c20a65f | 1853 | offsettable_memref_p (rtx op) |
2055cea7 RK |
1854 | { |
1855 | return ((GET_CODE (op) == MEM) | |
1856 | && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); | |
1857 | } | |
1858 | ||
1859 | /* Similar, but don't require a strictly valid mem ref: | |
1860 | consider pseudo-regs valid as index or base regs. */ | |
1861 | ||
1862 | int | |
0c20a65f | 1863 | offsettable_nonstrict_memref_p (rtx op) |
2055cea7 RK |
1864 | { |
1865 | return ((GET_CODE (op) == MEM) | |
1866 | && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); | |
1867 | } | |
1868 | ||
1869 | /* Return 1 if Y is a memory address which contains no side effects | |
1870 | and would remain valid after the addition of a positive integer | |
1871 | less than the size of that mode. | |
1872 | ||
1873 | We assume that the original address is valid and do not check it. | |
1874 | We do check that it is valid for narrower modes. | |
1875 | ||
1876 | If STRICTP is nonzero, we require a strictly valid address, | |
1877 | for the sake of use in reload.c. */ | |
1878 | ||
1879 | int | |
0c20a65f | 1880 | offsettable_address_p (int strictp, enum machine_mode mode, rtx y) |
2055cea7 | 1881 | { |
b3694847 SS |
1882 | enum rtx_code ycode = GET_CODE (y); |
1883 | rtx z; | |
2055cea7 RK |
1884 | rtx y1 = y; |
1885 | rtx *y2; | |
0c20a65f | 1886 | int (*addressp) (enum machine_mode, rtx) = |
341a243e | 1887 | (strictp ? strict_memory_address_p : memory_address_p); |
7bdebc3a | 1888 | unsigned int mode_sz = GET_MODE_SIZE (mode); |
2055cea7 RK |
1889 | |
1890 | if (CONSTANT_ADDRESS_P (y)) | |
1891 | return 1; | |
1892 | ||
1893 | /* Adjusting an offsettable address involves changing to a narrower mode. | |
1894 | Make sure that's OK. */ | |
1895 | ||
1896 | if (mode_dependent_address_p (y)) | |
1897 | return 0; | |
1898 | ||
7bdebc3a RH |
1899 | /* ??? How much offset does an offsettable BLKmode reference need? |
1900 | Clearly that depends on the situation in which it's being used. | |
1901 | However, the current situation in which we test 0xffffffff is | |
1902 | less than ideal. Caveat user. */ | |
1903 | if (mode_sz == 0) | |
1904 | mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT; | |
1905 | ||
2055cea7 RK |
1906 | /* If the expression contains a constant term, |
1907 | see if it remains valid when max possible offset is added. */ | |
1908 | ||
1909 | if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) | |
1910 | { | |
1911 | int good; | |
1912 | ||
1913 | y1 = *y2; | |
7bdebc3a | 1914 | *y2 = plus_constant (*y2, mode_sz - 1); |
2055cea7 RK |
1915 | /* Use QImode because an odd displacement may be automatically invalid |
1916 | for any wider mode. But it should be valid for a single byte. */ | |
1917 | good = (*addressp) (QImode, y); | |
1918 | ||
1919 | /* In any case, restore old contents of memory. */ | |
1920 | *y2 = y1; | |
1921 | return good; | |
1922 | } | |
1923 | ||
4b983fdc | 1924 | if (GET_RTX_CLASS (ycode) == 'a') |
2055cea7 RK |
1925 | return 0; |
1926 | ||
1927 | /* The offset added here is chosen as the maximum offset that | |
1928 | any instruction could need to add when operating on something | |
1929 | of the specified mode. We assume that if Y and Y+c are | |
07217645 RK |
1930 | valid addresses then so is Y+d for all 0<d<c. adjust_address will |
1931 | go inside a LO_SUM here, so we do so as well. */ | |
2f15e255 RH |
1932 | if (GET_CODE (y) == LO_SUM |
1933 | && mode != BLKmode | |
1934 | && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT) | |
07217645 RK |
1935 | z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0), |
1936 | plus_constant (XEXP (y, 1), mode_sz - 1)); | |
1937 | else | |
1938 | z = plus_constant (y, mode_sz - 1); | |
2055cea7 RK |
1939 | |
1940 | /* Use QImode because an odd displacement may be automatically invalid | |
1941 | for any wider mode. But it should be valid for a single byte. */ | |
1942 | return (*addressp) (QImode, z); | |
1943 | } | |
1944 | ||
1945 | /* Return 1 if ADDR is an address-expression whose effect depends | |
1946 | on the mode of the memory reference it is used in. | |
1947 | ||
1948 | Autoincrement addressing is a typical example of mode-dependence | |
1949 | because the amount of the increment depends on the mode. */ | |
1950 | ||
1951 | int | |
0c20a65f | 1952 | mode_dependent_address_p (rtx addr ATTRIBUTE_UNUSED /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */) |
2055cea7 RK |
1953 | { |
1954 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, win); | |
1955 | return 0; | |
dc297297 | 1956 | /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ |
47c3ed98 | 1957 | win: ATTRIBUTE_UNUSED_LABEL |
2055cea7 RK |
1958 | return 1; |
1959 | } | |
2055cea7 | 1960 | \f |
d90ffc8d JH |
1961 | /* Like extract_insn, but save insn extracted and don't extract again, when |
1962 | called again for the same insn expecting that recog_data still contain the | |
1963 | valid information. This is used primary by gen_attr infrastructure that | |
1964 | often does extract insn again and again. */ | |
1965 | void | |
0c20a65f | 1966 | extract_insn_cached (rtx insn) |
d90ffc8d JH |
1967 | { |
1968 | if (recog_data.insn == insn && INSN_CODE (insn) >= 0) | |
1969 | return; | |
1970 | extract_insn (insn); | |
1971 | recog_data.insn = insn; | |
1972 | } | |
1973 | /* Do cached extract_insn, constrain_operand and complain about failures. | |
1974 | Used by insn_attrtab. */ | |
1975 | void | |
0c20a65f | 1976 | extract_constrain_insn_cached (rtx insn) |
d90ffc8d JH |
1977 | { |
1978 | extract_insn_cached (insn); | |
1979 | if (which_alternative == -1 | |
1980 | && !constrain_operands (reload_completed)) | |
1981 | fatal_insn_not_found (insn); | |
1982 | } | |
6c698a6d JH |
1983 | /* Do cached constrain_operand and complain about failures. */ |
1984 | int | |
0c20a65f | 1985 | constrain_operands_cached (int strict) |
6c698a6d JH |
1986 | { |
1987 | if (which_alternative == -1) | |
1988 | return constrain_operands (strict); | |
1989 | else | |
1990 | return 1; | |
1991 | } | |
d90ffc8d | 1992 | \f |
1ccbefce RH |
1993 | /* Analyze INSN and fill in recog_data. */ |
1994 | ||
0a578fee | 1995 | void |
0c20a65f | 1996 | extract_insn (rtx insn) |
0a578fee BS |
1997 | { |
1998 | int i; | |
1999 | int icode; | |
2000 | int noperands; | |
2001 | rtx body = PATTERN (insn); | |
2002 | ||
d90ffc8d | 2003 | recog_data.insn = NULL; |
1ccbefce RH |
2004 | recog_data.n_operands = 0; |
2005 | recog_data.n_alternatives = 0; | |
2006 | recog_data.n_dups = 0; | |
d90ffc8d | 2007 | which_alternative = -1; |
0a578fee BS |
2008 | |
2009 | switch (GET_CODE (body)) | |
2010 | { | |
2011 | case USE: | |
2012 | case CLOBBER: | |
2013 | case ASM_INPUT: | |
2014 | case ADDR_VEC: | |
2015 | case ADDR_DIFF_VEC: | |
2016 | return; | |
2017 | ||
2018 | case SET: | |
6c698a6d JH |
2019 | if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) |
2020 | goto asm_insn; | |
2021 | else | |
2022 | goto normal_insn; | |
0a578fee | 2023 | case PARALLEL: |
6c698a6d JH |
2024 | if ((GET_CODE (XVECEXP (body, 0, 0)) == SET |
2025 | && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) | |
2026 | || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
2027 | goto asm_insn; | |
2028 | else | |
2029 | goto normal_insn; | |
0a578fee | 2030 | case ASM_OPERANDS: |
6c698a6d | 2031 | asm_insn: |
1ccbefce | 2032 | recog_data.n_operands = noperands = asm_noperands (body); |
0a578fee BS |
2033 | if (noperands >= 0) |
2034 | { | |
0a578fee BS |
2035 | /* This insn is an `asm' with operands. */ |
2036 | ||
2037 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
2038 | if (noperands > MAX_RECOG_OPERANDS) | |
2039 | abort (); | |
2040 | ||
2041 | /* Now get the operand values and constraints out of the insn. */ | |
1ccbefce RH |
2042 | decode_asm_operands (body, recog_data.operand, |
2043 | recog_data.operand_loc, | |
2044 | recog_data.constraints, | |
2045 | recog_data.operand_mode); | |
0a578fee BS |
2046 | if (noperands > 0) |
2047 | { | |
1ccbefce RH |
2048 | const char *p = recog_data.constraints[0]; |
2049 | recog_data.n_alternatives = 1; | |
0a578fee | 2050 | while (*p) |
1ccbefce | 2051 | recog_data.n_alternatives += (*p++ == ','); |
0a578fee | 2052 | } |
0a578fee BS |
2053 | break; |
2054 | } | |
6c698a6d | 2055 | fatal_insn_not_found (insn); |
0a578fee BS |
2056 | |
2057 | default: | |
6c698a6d | 2058 | normal_insn: |
0a578fee BS |
2059 | /* Ordinary insn: recognize it, get the operands via insn_extract |
2060 | and get the constraints. */ | |
2061 | ||
2062 | icode = recog_memoized (insn); | |
2063 | if (icode < 0) | |
2064 | fatal_insn_not_found (insn); | |
2065 | ||
a995e389 RH |
2066 | recog_data.n_operands = noperands = insn_data[icode].n_operands; |
2067 | recog_data.n_alternatives = insn_data[icode].n_alternatives; | |
2068 | recog_data.n_dups = insn_data[icode].n_dups; | |
0a578fee BS |
2069 | |
2070 | insn_extract (insn); | |
2071 | ||
2072 | for (i = 0; i < noperands; i++) | |
2073 | { | |
a995e389 | 2074 | recog_data.constraints[i] = insn_data[icode].operand[i].constraint; |
a995e389 | 2075 | recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; |
e7adb6fb JH |
2076 | /* VOIDmode match_operands gets mode from their real operand. */ |
2077 | if (recog_data.operand_mode[i] == VOIDmode) | |
2078 | recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]); | |
0a578fee BS |
2079 | } |
2080 | } | |
0eadeb15 | 2081 | for (i = 0; i < noperands; i++) |
1ccbefce RH |
2082 | recog_data.operand_type[i] |
2083 | = (recog_data.constraints[i][0] == '=' ? OP_OUT | |
2084 | : recog_data.constraints[i][0] == '+' ? OP_INOUT | |
2085 | : OP_IN); | |
f62a15e3 | 2086 | |
1ccbefce | 2087 | if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES) |
f62a15e3 | 2088 | abort (); |
0a578fee BS |
2089 | } |
2090 | ||
f62a15e3 BS |
2091 | /* After calling extract_insn, you can use this function to extract some |
2092 | information from the constraint strings into a more usable form. | |
2093 | The collected data is stored in recog_op_alt. */ | |
2094 | void | |
0c20a65f | 2095 | preprocess_constraints (void) |
f62a15e3 BS |
2096 | { |
2097 | int i; | |
2098 | ||
341a243e | 2099 | memset (recog_op_alt, 0, sizeof recog_op_alt); |
1ccbefce | 2100 | for (i = 0; i < recog_data.n_operands; i++) |
f62a15e3 BS |
2101 | { |
2102 | int j; | |
2103 | struct operand_alternative *op_alt; | |
1ccbefce | 2104 | const char *p = recog_data.constraints[i]; |
f62a15e3 BS |
2105 | |
2106 | op_alt = recog_op_alt[i]; | |
2107 | ||
1ccbefce | 2108 | for (j = 0; j < recog_data.n_alternatives; j++) |
f62a15e3 BS |
2109 | { |
2110 | op_alt[j].class = NO_REGS; | |
2111 | op_alt[j].constraint = p; | |
2112 | op_alt[j].matches = -1; | |
2113 | op_alt[j].matched = -1; | |
2114 | ||
2115 | if (*p == '\0' || *p == ',') | |
2116 | { | |
2117 | op_alt[j].anything_ok = 1; | |
2118 | continue; | |
2119 | } | |
2120 | ||
2121 | for (;;) | |
2122 | { | |
97488870 | 2123 | char c = *p; |
f62a15e3 BS |
2124 | if (c == '#') |
2125 | do | |
97488870 | 2126 | c = *++p; |
f62a15e3 BS |
2127 | while (c != ',' && c != '\0'); |
2128 | if (c == ',' || c == '\0') | |
97488870 R |
2129 | { |
2130 | p++; | |
2131 | break; | |
2132 | } | |
f62a15e3 BS |
2133 | |
2134 | switch (c) | |
2135 | { | |
2136 | case '=': case '+': case '*': case '%': | |
2137 | case 'E': case 'F': case 'G': case 'H': | |
2138 | case 's': case 'i': case 'n': | |
2139 | case 'I': case 'J': case 'K': case 'L': | |
2140 | case 'M': case 'N': case 'O': case 'P': | |
f62a15e3 BS |
2141 | /* These don't say anything we care about. */ |
2142 | break; | |
2143 | ||
2144 | case '?': | |
2145 | op_alt[j].reject += 6; | |
2146 | break; | |
2147 | case '!': | |
2148 | op_alt[j].reject += 600; | |
2149 | break; | |
2150 | case '&': | |
2151 | op_alt[j].earlyclobber = 1; | |
a6a2274a | 2152 | break; |
f62a15e3 BS |
2153 | |
2154 | case '0': case '1': case '2': case '3': case '4': | |
2155 | case '5': case '6': case '7': case '8': case '9': | |
84b72302 RH |
2156 | { |
2157 | char *end; | |
97488870 | 2158 | op_alt[j].matches = strtoul (p, &end, 10); |
84b72302 RH |
2159 | recog_op_alt[op_alt[j].matches][j].matched = i; |
2160 | p = end; | |
2161 | } | |
97488870 | 2162 | continue; |
f62a15e3 BS |
2163 | |
2164 | case 'm': | |
2165 | op_alt[j].memory_ok = 1; | |
2166 | break; | |
2167 | case '<': | |
2168 | op_alt[j].decmem_ok = 1; | |
2169 | break; | |
2170 | case '>': | |
2171 | op_alt[j].incmem_ok = 1; | |
2172 | break; | |
2173 | case 'V': | |
2174 | op_alt[j].nonoffmem_ok = 1; | |
2175 | break; | |
2176 | case 'o': | |
2177 | op_alt[j].offmem_ok = 1; | |
2178 | break; | |
2179 | case 'X': | |
2180 | op_alt[j].anything_ok = 1; | |
2181 | break; | |
2182 | ||
2183 | case 'p': | |
541f7d56 | 2184 | op_alt[j].is_address = 1; |
3dcc68a4 NC |
2185 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class] |
2186 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
f62a15e3 BS |
2187 | break; |
2188 | ||
2189 | case 'g': case 'r': | |
2190 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS]; | |
2191 | break; | |
2192 | ||
2193 | default: | |
97488870 | 2194 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) |
ccfc6cc8 UW |
2195 | { |
2196 | op_alt[j].memory_ok = 1; | |
2197 | break; | |
2198 | } | |
97488870 | 2199 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 UW |
2200 | { |
2201 | op_alt[j].is_address = 1; | |
97488870 R |
2202 | op_alt[j].class |
2203 | = (reg_class_subunion | |
2204 | [(int) op_alt[j].class] | |
2205 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]); | |
ccfc6cc8 UW |
2206 | break; |
2207 | } | |
2208 | ||
97488870 R |
2209 | op_alt[j].class |
2210 | = (reg_class_subunion | |
2211 | [(int) op_alt[j].class] | |
2212 | [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]); | |
f62a15e3 BS |
2213 | break; |
2214 | } | |
97488870 | 2215 | p += CONSTRAINT_LEN (c, p); |
f62a15e3 BS |
2216 | } |
2217 | } | |
2218 | } | |
2219 | } | |
a6a2274a | 2220 | |
0eadeb15 | 2221 | /* Check the operands of an insn against the insn's operand constraints |
2055cea7 | 2222 | and return 1 if they are valid. |
0eadeb15 BS |
2223 | The information about the insn's operands, constraints, operand modes |
2224 | etc. is obtained from the global variables set up by extract_insn. | |
2055cea7 RK |
2225 | |
2226 | WHICH_ALTERNATIVE is set to a number which indicates which | |
2227 | alternative of constraints was matched: 0 for the first alternative, | |
2228 | 1 for the next, etc. | |
2229 | ||
97488870 | 2230 | In addition, when two operands are required to match |
2055cea7 RK |
2231 | and it happens that the output operand is (reg) while the |
2232 | input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), | |
2233 | make the output operand look like the input. | |
2234 | This is because the output operand is the one the template will print. | |
2235 | ||
2236 | This is used in final, just before printing the assembler code and by | |
2237 | the routines that determine an insn's attribute. | |
2238 | ||
40f03658 | 2239 | If STRICT is a positive nonzero value, it means that we have been |
2055cea7 RK |
2240 | called after reload has been completed. In that case, we must |
2241 | do all checks strictly. If it is zero, it means that we have been called | |
2242 | before reload has completed. In that case, we first try to see if we can | |
2243 | find an alternative that matches strictly. If not, we try again, this | |
2244 | time assuming that reload will fix up the insn. This provides a "best | |
2245 | guess" for the alternative and is used to compute attributes of insns prior | |
2246 | to reload. A negative value of STRICT is used for this internal call. */ | |
2247 | ||
2248 | struct funny_match | |
2249 | { | |
2250 | int this, other; | |
2251 | }; | |
2252 | ||
2253 | int | |
0c20a65f | 2254 | constrain_operands (int strict) |
2055cea7 | 2255 | { |
9b3142b3 | 2256 | const char *constraints[MAX_RECOG_OPERANDS]; |
9e21be9d | 2257 | int matching_operands[MAX_RECOG_OPERANDS]; |
9e21be9d | 2258 | int earlyclobber[MAX_RECOG_OPERANDS]; |
b3694847 | 2259 | int c; |
2055cea7 RK |
2260 | |
2261 | struct funny_match funny_match[MAX_RECOG_OPERANDS]; | |
2262 | int funny_match_index; | |
2055cea7 | 2263 | |
4667f705 | 2264 | which_alternative = 0; |
1ccbefce | 2265 | if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0) |
2055cea7 RK |
2266 | return 1; |
2267 | ||
1ccbefce | 2268 | for (c = 0; c < recog_data.n_operands; c++) |
9e21be9d | 2269 | { |
1ccbefce | 2270 | constraints[c] = recog_data.constraints[c]; |
9e21be9d | 2271 | matching_operands[c] = -1; |
9e21be9d | 2272 | } |
2055cea7 | 2273 | |
4667f705 | 2274 | do |
2055cea7 | 2275 | { |
b3694847 | 2276 | int opno; |
2055cea7 RK |
2277 | int lose = 0; |
2278 | funny_match_index = 0; | |
2279 | ||
1ccbefce | 2280 | for (opno = 0; opno < recog_data.n_operands; opno++) |
2055cea7 | 2281 | { |
b3694847 | 2282 | rtx op = recog_data.operand[opno]; |
2055cea7 | 2283 | enum machine_mode mode = GET_MODE (op); |
b3694847 | 2284 | const char *p = constraints[opno]; |
2055cea7 RK |
2285 | int offset = 0; |
2286 | int win = 0; | |
2287 | int val; | |
97488870 | 2288 | int len; |
2055cea7 | 2289 | |
9e21be9d RK |
2290 | earlyclobber[opno] = 0; |
2291 | ||
b85f21c0 | 2292 | /* A unary operator may be accepted by the predicate, but it |
38a448ca | 2293 | is irrelevant for matching constraints. */ |
b85f21c0 ILT |
2294 | if (GET_RTX_CLASS (GET_CODE (op)) == '1') |
2295 | op = XEXP (op, 0); | |
2296 | ||
2055cea7 RK |
2297 | if (GET_CODE (op) == SUBREG) |
2298 | { | |
2299 | if (GET_CODE (SUBREG_REG (op)) == REG | |
2300 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) | |
ddef6bc7 JJ |
2301 | offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), |
2302 | GET_MODE (SUBREG_REG (op)), | |
2303 | SUBREG_BYTE (op), | |
2304 | GET_MODE (op)); | |
2055cea7 RK |
2305 | op = SUBREG_REG (op); |
2306 | } | |
2307 | ||
2308 | /* An empty constraint or empty alternative | |
2309 | allows anything which matched the pattern. */ | |
2310 | if (*p == 0 || *p == ',') | |
2311 | win = 1; | |
2312 | ||
97488870 R |
2313 | do |
2314 | switch (c = *p, len = CONSTRAINT_LEN (c, p), c) | |
2055cea7 | 2315 | { |
97488870 R |
2316 | case '\0': |
2317 | len = 0; | |
2318 | break; | |
2319 | case ',': | |
2320 | c = '\0'; | |
2321 | break; | |
2322 | ||
c5c76735 JL |
2323 | case '?': case '!': case '*': case '%': |
2324 | case '=': case '+': | |
2055cea7 RK |
2325 | break; |
2326 | ||
4d3067db RK |
2327 | case '#': |
2328 | /* Ignore rest of this alternative as far as | |
2329 | constraint checking is concerned. */ | |
97488870 | 2330 | do |
4d3067db | 2331 | p++; |
97488870 R |
2332 | while (*p && *p != ','); |
2333 | len = 0; | |
4d3067db RK |
2334 | break; |
2335 | ||
9e21be9d RK |
2336 | case '&': |
2337 | earlyclobber[opno] = 1; | |
2338 | break; | |
2339 | ||
c5c76735 JL |
2340 | case '0': case '1': case '2': case '3': case '4': |
2341 | case '5': case '6': case '7': case '8': case '9': | |
84b72302 RH |
2342 | { |
2343 | /* This operand must be the same as a previous one. | |
2344 | This kind of constraint is used for instructions such | |
2345 | as add when they take only two operands. | |
2346 | ||
2347 | Note that the lower-numbered operand is passed first. | |
2348 | ||
2349 | If we are not testing strictly, assume that this | |
2350 | constraint will be satisfied. */ | |
2351 | ||
2352 | char *end; | |
2353 | int match; | |
2354 | ||
97488870 | 2355 | match = strtoul (p, &end, 10); |
84b72302 RH |
2356 | p = end; |
2357 | ||
2358 | if (strict < 0) | |
2359 | val = 1; | |
2360 | else | |
2361 | { | |
2362 | rtx op1 = recog_data.operand[match]; | |
2363 | rtx op2 = recog_data.operand[opno]; | |
2364 | ||
2365 | /* A unary operator may be accepted by the predicate, | |
2366 | but it is irrelevant for matching constraints. */ | |
2367 | if (GET_RTX_CLASS (GET_CODE (op1)) == '1') | |
2368 | op1 = XEXP (op1, 0); | |
2369 | if (GET_RTX_CLASS (GET_CODE (op2)) == '1') | |
2370 | op2 = XEXP (op2, 0); | |
2371 | ||
2372 | val = operands_match_p (op1, op2); | |
2373 | } | |
2374 | ||
2375 | matching_operands[opno] = match; | |
2376 | matching_operands[match] = opno; | |
2377 | ||
2378 | if (val != 0) | |
2379 | win = 1; | |
2380 | ||
2381 | /* If output is *x and input is *--x, arrange later | |
2382 | to change the output to *--x as well, since the | |
2383 | output op is the one that will be printed. */ | |
2384 | if (val == 2 && strict > 0) | |
2385 | { | |
2386 | funny_match[funny_match_index].this = opno; | |
2387 | funny_match[funny_match_index++].other = match; | |
2388 | } | |
2389 | } | |
97488870 | 2390 | len = 0; |
2055cea7 RK |
2391 | break; |
2392 | ||
2393 | case 'p': | |
2394 | /* p is used for address_operands. When we are called by | |
a8647766 RK |
2395 | gen_reload, no one will have checked that the address is |
2396 | strictly valid, i.e., that all pseudos requiring hard regs | |
2397 | have gotten them. */ | |
2055cea7 | 2398 | if (strict <= 0 |
1ccbefce | 2399 | || (strict_memory_address_p (recog_data.operand_mode[opno], |
0eadeb15 | 2400 | op))) |
2055cea7 RK |
2401 | win = 1; |
2402 | break; | |
2403 | ||
2404 | /* No need to check general_operand again; | |
2405 | it was done in insn-recog.c. */ | |
2406 | case 'g': | |
2407 | /* Anything goes unless it is a REG and really has a hard reg | |
2408 | but the hard reg is not in the class GENERAL_REGS. */ | |
2409 | if (strict < 0 | |
2410 | || GENERAL_REGS == ALL_REGS | |
2411 | || GET_CODE (op) != REG | |
3c3eeea6 RK |
2412 | || (reload_in_progress |
2413 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2055cea7 RK |
2414 | || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) |
2415 | win = 1; | |
2416 | break; | |
2417 | ||
2055cea7 | 2418 | case 'X': |
0f41302f MS |
2419 | /* This is used for a MATCH_SCRATCH in the cases when |
2420 | we don't actually need anything. So anything goes | |
2421 | any time. */ | |
2055cea7 RK |
2422 | win = 1; |
2423 | break; | |
2424 | ||
2425 | case 'm': | |
2426 | if (GET_CODE (op) == MEM | |
2427 | /* Before reload, accept what reload can turn into mem. */ | |
3c3eeea6 RK |
2428 | || (strict < 0 && CONSTANT_P (op)) |
2429 | /* During reload, accept a pseudo */ | |
2430 | || (reload_in_progress && GET_CODE (op) == REG | |
2431 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2432 | win = 1; |
2433 | break; | |
2434 | ||
2435 | case '<': | |
2436 | if (GET_CODE (op) == MEM | |
2437 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
2438 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
2439 | win = 1; | |
2440 | break; | |
2441 | ||
2442 | case '>': | |
2443 | if (GET_CODE (op) == MEM | |
2444 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
2445 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
2446 | win = 1; | |
2447 | break; | |
2448 | ||
2449 | case 'E': | |
2055cea7 | 2450 | case 'F': |
bf7cd754 R |
2451 | if (GET_CODE (op) == CONST_DOUBLE |
2452 | || (GET_CODE (op) == CONST_VECTOR | |
2453 | && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT)) | |
2055cea7 RK |
2454 | win = 1; |
2455 | break; | |
2456 | ||
2457 | case 'G': | |
2458 | case 'H': | |
2459 | if (GET_CODE (op) == CONST_DOUBLE | |
97488870 | 2460 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) |
2055cea7 RK |
2461 | win = 1; |
2462 | break; | |
2463 | ||
2464 | case 's': | |
2465 | if (GET_CODE (op) == CONST_INT | |
2466 | || (GET_CODE (op) == CONST_DOUBLE | |
2467 | && GET_MODE (op) == VOIDmode)) | |
2468 | break; | |
2469 | case 'i': | |
2470 | if (CONSTANT_P (op)) | |
2471 | win = 1; | |
2472 | break; | |
2473 | ||
2474 | case 'n': | |
2475 | if (GET_CODE (op) == CONST_INT | |
2476 | || (GET_CODE (op) == CONST_DOUBLE | |
2477 | && GET_MODE (op) == VOIDmode)) | |
2478 | win = 1; | |
2479 | break; | |
2480 | ||
2481 | case 'I': | |
2482 | case 'J': | |
2483 | case 'K': | |
2484 | case 'L': | |
2485 | case 'M': | |
2486 | case 'N': | |
2487 | case 'O': | |
2488 | case 'P': | |
2489 | if (GET_CODE (op) == CONST_INT | |
97488870 | 2490 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) |
2055cea7 RK |
2491 | win = 1; |
2492 | break; | |
2493 | ||
2055cea7 RK |
2494 | case 'V': |
2495 | if (GET_CODE (op) == MEM | |
69f724c0 JL |
2496 | && ((strict > 0 && ! offsettable_memref_p (op)) |
2497 | || (strict < 0 | |
2498 | && !(CONSTANT_P (op) || GET_CODE (op) == MEM)) | |
2499 | || (reload_in_progress | |
2500 | && !(GET_CODE (op) == REG | |
2501 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))) | |
2055cea7 RK |
2502 | win = 1; |
2503 | break; | |
2504 | ||
2505 | case 'o': | |
2506 | if ((strict > 0 && offsettable_memref_p (op)) | |
2507 | || (strict == 0 && offsettable_nonstrict_memref_p (op)) | |
2508 | /* Before reload, accept what reload can handle. */ | |
2509 | || (strict < 0 | |
3c3eeea6 RK |
2510 | && (CONSTANT_P (op) || GET_CODE (op) == MEM)) |
2511 | /* During reload, accept a pseudo */ | |
2512 | || (reload_in_progress && GET_CODE (op) == REG | |
2513 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2514 | win = 1; |
2515 | break; | |
2516 | ||
2517 | default: | |
c2cba7a9 RH |
2518 | { |
2519 | enum reg_class class; | |
2520 | ||
97488870 R |
2521 | class = (c == 'r' |
2522 | ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p)); | |
c2cba7a9 RH |
2523 | if (class != NO_REGS) |
2524 | { | |
2525 | if (strict < 0 | |
2526 | || (strict == 0 | |
2527 | && GET_CODE (op) == REG | |
2528 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2529 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
2530 | || (GET_CODE (op) == REG | |
2531 | && reg_fits_class_p (op, class, offset, mode))) | |
2532 | win = 1; | |
2533 | } | |
97488870 R |
2534 | #ifdef EXTRA_CONSTRAINT_STR |
2535 | else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
c2cba7a9 | 2536 | win = 1; |
ccfc6cc8 | 2537 | |
97488870 | 2538 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) |
ccfc6cc8 | 2539 | { |
3ba2436a UW |
2540 | /* Every memory operand can be reloaded to fit. */ |
2541 | if (strict < 0 && GET_CODE (op) == MEM) | |
2542 | win = 1; | |
0c20a65f | 2543 | |
3ba2436a UW |
2544 | /* Before reload, accept what reload can turn into mem. */ |
2545 | if (strict < 0 && CONSTANT_P (op)) | |
2546 | win = 1; | |
2547 | ||
2548 | /* During reload, accept a pseudo */ | |
2549 | if (reload_in_progress && GET_CODE (op) == REG | |
2550 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
ccfc6cc8 UW |
2551 | win = 1; |
2552 | } | |
97488870 | 2553 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 | 2554 | { |
3ba2436a UW |
2555 | /* Every address operand can be reloaded to fit. */ |
2556 | if (strict < 0) | |
ccfc6cc8 UW |
2557 | win = 1; |
2558 | } | |
c2cba7a9 RH |
2559 | #endif |
2560 | break; | |
2561 | } | |
2055cea7 | 2562 | } |
97488870 | 2563 | while (p += len, c); |
2055cea7 RK |
2564 | |
2565 | constraints[opno] = p; | |
2566 | /* If this operand did not win somehow, | |
2567 | this alternative loses. */ | |
2568 | if (! win) | |
2569 | lose = 1; | |
2570 | } | |
2571 | /* This alternative won; the operands are ok. | |
2572 | Change whichever operands this alternative says to change. */ | |
2573 | if (! lose) | |
2574 | { | |
9e21be9d RK |
2575 | int opno, eopno; |
2576 | ||
2577 | /* See if any earlyclobber operand conflicts with some other | |
2578 | operand. */ | |
2579 | ||
2580 | if (strict > 0) | |
1ccbefce | 2581 | for (eopno = 0; eopno < recog_data.n_operands; eopno++) |
62946075 RS |
2582 | /* Ignore earlyclobber operands now in memory, |
2583 | because we would often report failure when we have | |
2584 | two memory operands, one of which was formerly a REG. */ | |
2585 | if (earlyclobber[eopno] | |
1ccbefce RH |
2586 | && GET_CODE (recog_data.operand[eopno]) == REG) |
2587 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
2588 | if ((GET_CODE (recog_data.operand[opno]) == MEM | |
2589 | || recog_data.operand_type[opno] != OP_OUT) | |
9e21be9d | 2590 | && opno != eopno |
0f41302f | 2591 | /* Ignore things like match_operator operands. */ |
1ccbefce | 2592 | && *recog_data.constraints[opno] != 0 |
9e21be9d | 2593 | && ! (matching_operands[opno] == eopno |
1ccbefce RH |
2594 | && operands_match_p (recog_data.operand[opno], |
2595 | recog_data.operand[eopno])) | |
2596 | && ! safe_from_earlyclobber (recog_data.operand[opno], | |
2597 | recog_data.operand[eopno])) | |
9e21be9d RK |
2598 | lose = 1; |
2599 | ||
2600 | if (! lose) | |
2055cea7 | 2601 | { |
9e21be9d RK |
2602 | while (--funny_match_index >= 0) |
2603 | { | |
1ccbefce RH |
2604 | recog_data.operand[funny_match[funny_match_index].other] |
2605 | = recog_data.operand[funny_match[funny_match_index].this]; | |
9e21be9d RK |
2606 | } |
2607 | ||
2608 | return 1; | |
2055cea7 | 2609 | } |
2055cea7 RK |
2610 | } |
2611 | ||
2612 | which_alternative++; | |
2613 | } | |
4667f705 | 2614 | while (which_alternative < recog_data.n_alternatives); |
2055cea7 | 2615 | |
d90ffc8d | 2616 | which_alternative = -1; |
2055cea7 RK |
2617 | /* If we are about to reject this, but we are not to test strictly, |
2618 | try a very loose test. Only return failure if it fails also. */ | |
2619 | if (strict == 0) | |
0eadeb15 | 2620 | return constrain_operands (-1); |
2055cea7 RK |
2621 | else |
2622 | return 0; | |
2623 | } | |
2624 | ||
2625 | /* Return 1 iff OPERAND (assumed to be a REG rtx) | |
38a448ca | 2626 | is a hard reg in class CLASS when its regno is offset by OFFSET |
2055cea7 RK |
2627 | and changed to mode MODE. |
2628 | If REG occupies multiple hard regs, all of them must be in CLASS. */ | |
2629 | ||
2630 | int | |
0c20a65f AJ |
2631 | reg_fits_class_p (rtx operand, enum reg_class class, int offset, |
2632 | enum machine_mode mode) | |
2055cea7 | 2633 | { |
b3694847 | 2634 | int regno = REGNO (operand); |
2055cea7 RK |
2635 | if (regno < FIRST_PSEUDO_REGISTER |
2636 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2637 | regno + offset)) | |
2638 | { | |
b3694847 | 2639 | int sr; |
2055cea7 RK |
2640 | regno += offset; |
2641 | for (sr = HARD_REGNO_NREGS (regno, mode) - 1; | |
2642 | sr > 0; sr--) | |
2643 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2644 | regno + sr)) | |
2645 | break; | |
2646 | return sr == 0; | |
2647 | } | |
2648 | ||
2649 | return 0; | |
2650 | } | |
ca545bb5 | 2651 | \f |
d58d4c12 | 2652 | /* Split single instruction. Helper function for split_all_insns. |
ffb5e2e2 | 2653 | Return last insn in the sequence if successful, or NULL if unsuccessful. */ |
d58d4c12 | 2654 | static rtx |
0c20a65f | 2655 | split_insn (rtx insn) |
d58d4c12 JH |
2656 | { |
2657 | rtx set; | |
2658 | if (!INSN_P (insn)) | |
2659 | ; | |
2660 | /* Don't split no-op move insns. These should silently | |
2661 | disappear later in final. Splitting such insns would | |
2662 | break the code that handles REG_NO_CONFLICT blocks. */ | |
2663 | ||
2664 | else if ((set = single_set (insn)) != NULL && set_noop_p (set)) | |
2665 | { | |
2666 | /* Nops get in the way while scheduling, so delete them | |
2667 | now if register allocation has already been done. It | |
2668 | is too risky to try to do this before register | |
2669 | allocation, and there are unlikely to be very many | |
2670 | nops then anyways. */ | |
2671 | if (reload_completed) | |
1e3881c2 | 2672 | delete_insn_and_edges (insn); |
d58d4c12 JH |
2673 | } |
2674 | else | |
2675 | { | |
2676 | /* Split insns here to get max fine-grain parallelism. */ | |
2677 | rtx first = PREV_INSN (insn); | |
2678 | rtx last = try_split (PATTERN (insn), insn, 1); | |
2679 | ||
2680 | if (last != insn) | |
2681 | { | |
2682 | /* try_split returns the NOTE that INSN became. */ | |
2683 | PUT_CODE (insn, NOTE); | |
2684 | NOTE_SOURCE_FILE (insn) = 0; | |
2685 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2686 | ||
2687 | /* ??? Coddle to md files that generate subregs in post- | |
a6a2274a | 2688 | reload splitters instead of computing the proper |
d58d4c12 JH |
2689 | hard register. */ |
2690 | if (reload_completed && first != last) | |
2691 | { | |
2692 | first = NEXT_INSN (first); | |
2693 | while (1) | |
2694 | { | |
2695 | if (INSN_P (first)) | |
2696 | cleanup_subreg_operands (first); | |
2697 | if (first == last) | |
2698 | break; | |
2699 | first = NEXT_INSN (first); | |
2700 | } | |
2701 | } | |
2702 | return last; | |
2703 | } | |
2704 | } | |
2705 | return NULL_RTX; | |
2706 | } | |
d3a923ee | 2707 | /* Split all insns in the function. If UPD_LIFE, update life info after. */ |
ca545bb5 BM |
2708 | |
2709 | void | |
0c20a65f | 2710 | split_all_insns (int upd_life) |
ca545bb5 | 2711 | { |
d3a923ee | 2712 | sbitmap blocks; |
9381bbc9 | 2713 | bool changed; |
e0082a72 | 2714 | basic_block bb; |
d3a923ee | 2715 | |
d55bc081 | 2716 | blocks = sbitmap_alloc (last_basic_block); |
d3a923ee | 2717 | sbitmap_zero (blocks); |
9381bbc9 | 2718 | changed = false; |
ca545bb5 | 2719 | |
e0082a72 | 2720 | FOR_EACH_BB_REVERSE (bb) |
ca545bb5 | 2721 | { |
d3a923ee | 2722 | rtx insn, next; |
83a49407 | 2723 | bool finish = false; |
ca545bb5 | 2724 | |
83a49407 | 2725 | for (insn = bb->head; !finish ; insn = next) |
ca545bb5 | 2726 | { |
d58d4c12 | 2727 | rtx last; |
ca545bb5 | 2728 | |
d3a923ee RH |
2729 | /* Can't use `next_real_insn' because that might go across |
2730 | CODE_LABELS and short-out basic blocks. */ | |
2731 | next = NEXT_INSN (insn); | |
83a49407 | 2732 | finish = (insn == bb->end); |
d58d4c12 JH |
2733 | last = split_insn (insn); |
2734 | if (last) | |
ca545bb5 | 2735 | { |
3c030e88 JH |
2736 | /* The split sequence may include barrier, but the |
2737 | BB boundary we are interested in will be set to previous | |
2738 | one. */ | |
2739 | ||
2740 | while (GET_CODE (last) == BARRIER) | |
2741 | last = PREV_INSN (last); | |
e0082a72 | 2742 | SET_BIT (blocks, bb->index); |
9381bbc9 | 2743 | changed = true; |
d58d4c12 | 2744 | insn = last; |
ca545bb5 BM |
2745 | } |
2746 | } | |
ca545bb5 | 2747 | } |
d3a923ee | 2748 | |
0005550b | 2749 | if (changed) |
d3a923ee | 2750 | { |
9381bbc9 RH |
2751 | int old_last_basic_block = last_basic_block; |
2752 | ||
b932f770 | 2753 | find_many_sub_basic_blocks (blocks); |
9381bbc9 | 2754 | |
35a3fa09 | 2755 | if (old_last_basic_block != last_basic_block && upd_life) |
e360ab39 | 2756 | blocks = sbitmap_resize (blocks, last_basic_block, 1); |
0005550b JH |
2757 | } |
2758 | ||
2759 | if (changed && upd_life) | |
9381bbc9 RH |
2760 | update_life_info (blocks, UPDATE_LIFE_GLOBAL_RM_NOTES, |
2761 | PROP_DEATH_NOTES | PROP_REG_INFO); | |
2762 | ||
0005550b JH |
2763 | #ifdef ENABLE_CHECKING |
2764 | verify_flow_info (); | |
2765 | #endif | |
d3a923ee RH |
2766 | |
2767 | sbitmap_free (blocks); | |
ca545bb5 | 2768 | } |
6f862f2f | 2769 | |
a6a2274a | 2770 | /* Same as split_all_insns, but do not expect CFG to be available. |
d55d8fc7 | 2771 | Used by machine dependent reorg passes. */ |
6f862f2f JH |
2772 | |
2773 | void | |
0c20a65f | 2774 | split_all_insns_noflow (void) |
6f862f2f JH |
2775 | { |
2776 | rtx next, insn; | |
2777 | ||
2778 | for (insn = get_insns (); insn; insn = next) | |
2779 | { | |
2780 | next = NEXT_INSN (insn); | |
2781 | split_insn (insn); | |
2782 | } | |
2783 | return; | |
2784 | } | |
ede7cd44 RH |
2785 | \f |
2786 | #ifdef HAVE_peephole2 | |
23280139 RH |
2787 | struct peep2_insn_data |
2788 | { | |
2789 | rtx insn; | |
2790 | regset live_before; | |
2791 | }; | |
2792 | ||
2793 | static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; | |
2794 | static int peep2_current; | |
2795 | ||
2796 | /* A non-insn marker indicating the last insn of the block. | |
2797 | The live_before regset for this element is correct, indicating | |
2798 | global_live_at_end for the block. */ | |
2799 | #define PEEP2_EOB pc_rtx | |
2800 | ||
2801 | /* Return the Nth non-note insn after `current', or return NULL_RTX if it | |
2802 | does not exist. Used by the recognizer to find the next insn to match | |
2803 | in a multi-insn pattern. */ | |
d3a923ee | 2804 | |
ede7cd44 | 2805 | rtx |
0c20a65f | 2806 | peep2_next_insn (int n) |
ede7cd44 | 2807 | { |
23280139 RH |
2808 | if (n >= MAX_INSNS_PER_PEEP2 + 1) |
2809 | abort (); | |
2810 | ||
2811 | n += peep2_current; | |
2812 | if (n >= MAX_INSNS_PER_PEEP2 + 1) | |
2813 | n -= MAX_INSNS_PER_PEEP2 + 1; | |
2814 | ||
2815 | if (peep2_insn_data[n].insn == PEEP2_EOB) | |
2816 | return NULL_RTX; | |
2817 | return peep2_insn_data[n].insn; | |
2818 | } | |
2819 | ||
2820 | /* Return true if REGNO is dead before the Nth non-note insn | |
2821 | after `current'. */ | |
2822 | ||
2823 | int | |
0c20a65f | 2824 | peep2_regno_dead_p (int ofs, int regno) |
23280139 RH |
2825 | { |
2826 | if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | |
2827 | abort (); | |
2828 | ||
2829 | ofs += peep2_current; | |
2830 | if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | |
2831 | ofs -= MAX_INSNS_PER_PEEP2 + 1; | |
2832 | ||
2833 | if (peep2_insn_data[ofs].insn == NULL_RTX) | |
2834 | abort (); | |
2835 | ||
2836 | return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno); | |
2837 | } | |
2838 | ||
2839 | /* Similarly for a REG. */ | |
2840 | ||
2841 | int | |
0c20a65f | 2842 | peep2_reg_dead_p (int ofs, rtx reg) |
23280139 RH |
2843 | { |
2844 | int regno, n; | |
2845 | ||
2846 | if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | |
2847 | abort (); | |
2848 | ||
2849 | ofs += peep2_current; | |
2850 | if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | |
2851 | ofs -= MAX_INSNS_PER_PEEP2 + 1; | |
2852 | ||
2853 | if (peep2_insn_data[ofs].insn == NULL_RTX) | |
2854 | abort (); | |
2855 | ||
2856 | regno = REGNO (reg); | |
2857 | n = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2858 | while (--n >= 0) | |
2859 | if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n)) | |
2860 | return 0; | |
2861 | return 1; | |
2862 | } | |
2863 | ||
2864 | /* Try to find a hard register of mode MODE, matching the register class in | |
2865 | CLASS_STR, which is available at the beginning of insn CURRENT_INSN and | |
2866 | remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX, | |
2867 | in which case the only condition is that the register must be available | |
2868 | before CURRENT_INSN. | |
2869 | Registers that already have bits set in REG_SET will not be considered. | |
2870 | ||
2871 | If an appropriate register is available, it will be returned and the | |
2872 | corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is | |
2873 | returned. */ | |
2874 | ||
2875 | rtx | |
0c20a65f AJ |
2876 | peep2_find_free_register (int from, int to, const char *class_str, |
2877 | enum machine_mode mode, HARD_REG_SET *reg_set) | |
23280139 RH |
2878 | { |
2879 | static int search_ofs; | |
2880 | enum reg_class class; | |
2881 | HARD_REG_SET live; | |
2882 | int i; | |
2883 | ||
2884 | if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1) | |
2885 | abort (); | |
2886 | ||
2887 | from += peep2_current; | |
2888 | if (from >= MAX_INSNS_PER_PEEP2 + 1) | |
2889 | from -= MAX_INSNS_PER_PEEP2 + 1; | |
2890 | to += peep2_current; | |
2891 | if (to >= MAX_INSNS_PER_PEEP2 + 1) | |
2892 | to -= MAX_INSNS_PER_PEEP2 + 1; | |
2893 | ||
2894 | if (peep2_insn_data[from].insn == NULL_RTX) | |
2895 | abort (); | |
2896 | REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); | |
2897 | ||
2898 | while (from != to) | |
ede7cd44 | 2899 | { |
23280139 RH |
2900 | HARD_REG_SET this_live; |
2901 | ||
2902 | if (++from >= MAX_INSNS_PER_PEEP2 + 1) | |
2903 | from = 0; | |
2904 | if (peep2_insn_data[from].insn == NULL_RTX) | |
2905 | abort (); | |
2906 | REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); | |
2907 | IOR_HARD_REG_SET (live, this_live); | |
2908 | } | |
2909 | ||
2910 | class = (class_str[0] == 'r' ? GENERAL_REGS | |
97488870 | 2911 | : REG_CLASS_FROM_CONSTRAINT (class_str[0], class_str)); |
23280139 RH |
2912 | |
2913 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2914 | { | |
2915 | int raw_regno, regno, success, j; | |
2916 | ||
2917 | /* Distribute the free registers as much as possible. */ | |
2918 | raw_regno = search_ofs + i; | |
2919 | if (raw_regno >= FIRST_PSEUDO_REGISTER) | |
2920 | raw_regno -= FIRST_PSEUDO_REGISTER; | |
2921 | #ifdef REG_ALLOC_ORDER | |
2922 | regno = reg_alloc_order[raw_regno]; | |
2923 | #else | |
2924 | regno = raw_regno; | |
2925 | #endif | |
2926 | ||
2927 | /* Don't allocate fixed registers. */ | |
2928 | if (fixed_regs[regno]) | |
2929 | continue; | |
2930 | /* Make sure the register is of the right class. */ | |
2931 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno)) | |
2932 | continue; | |
2933 | /* And can support the mode we need. */ | |
2934 | if (! HARD_REGNO_MODE_OK (regno, mode)) | |
2935 | continue; | |
2936 | /* And that we don't create an extra save/restore. */ | |
2937 | if (! call_used_regs[regno] && ! regs_ever_live[regno]) | |
2938 | continue; | |
2939 | /* And we don't clobber traceback for noreturn functions. */ | |
2940 | if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM) | |
2941 | && (! reload_completed || frame_pointer_needed)) | |
2942 | continue; | |
2943 | ||
2944 | success = 1; | |
2945 | for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--) | |
2946 | { | |
2947 | if (TEST_HARD_REG_BIT (*reg_set, regno + j) | |
2948 | || TEST_HARD_REG_BIT (live, regno + j)) | |
2949 | { | |
2950 | success = 0; | |
2951 | break; | |
2952 | } | |
2953 | } | |
2954 | if (success) | |
d3a923ee | 2955 | { |
23280139 RH |
2956 | for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--) |
2957 | SET_HARD_REG_BIT (*reg_set, regno + j); | |
ede7cd44 | 2958 | |
23280139 RH |
2959 | /* Start the next search with the next register. */ |
2960 | if (++raw_regno >= FIRST_PSEUDO_REGISTER) | |
2961 | raw_regno = 0; | |
2962 | search_ofs = raw_regno; | |
ede7cd44 | 2963 | |
23280139 | 2964 | return gen_rtx_REG (mode, regno); |
d3a923ee | 2965 | } |
ede7cd44 RH |
2966 | } |
2967 | ||
23280139 RH |
2968 | search_ofs = 0; |
2969 | return NULL_RTX; | |
ede7cd44 RH |
2970 | } |
2971 | ||
dc297297 | 2972 | /* Perform the peephole2 optimization pass. */ |
23280139 | 2973 | |
ede7cd44 | 2974 | void |
0c20a65f | 2975 | peephole2_optimize (FILE *dump_file ATTRIBUTE_UNUSED) |
ede7cd44 | 2976 | { |
23280139 | 2977 | regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2]; |
d3a923ee | 2978 | rtx insn, prev; |
23280139 | 2979 | regset live; |
e0082a72 ZD |
2980 | int i; |
2981 | basic_block bb; | |
23280139 | 2982 | #ifdef HAVE_conditional_execution |
d3a923ee | 2983 | sbitmap blocks; |
b29afcf8 | 2984 | bool changed; |
23280139 | 2985 | #endif |
b29afcf8 | 2986 | bool do_cleanup_cfg = false; |
9be40833 | 2987 | bool do_rebuild_jump_labels = false; |
ede7cd44 | 2988 | |
23280139 RH |
2989 | /* Initialize the regsets we're going to use. */ |
2990 | for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) | |
2991 | peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]); | |
2992 | live = INITIALIZE_REG_SET (rs_heads[i]); | |
ede7cd44 | 2993 | |
23280139 | 2994 | #ifdef HAVE_conditional_execution |
d55bc081 | 2995 | blocks = sbitmap_alloc (last_basic_block); |
d3a923ee | 2996 | sbitmap_zero (blocks); |
b29afcf8 | 2997 | changed = false; |
23280139 RH |
2998 | #else |
2999 | count_or_remove_death_notes (NULL, 1); | |
3000 | #endif | |
d3a923ee | 3001 | |
e0082a72 | 3002 | FOR_EACH_BB_REVERSE (bb) |
ede7cd44 | 3003 | { |
23280139 RH |
3004 | struct propagate_block_info *pbi; |
3005 | ||
3006 | /* Indicate that all slots except the last holds invalid data. */ | |
3007 | for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i) | |
3008 | peep2_insn_data[i].insn = NULL_RTX; | |
3009 | ||
3010 | /* Indicate that the last slot contains live_after data. */ | |
3011 | peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB; | |
3012 | peep2_current = MAX_INSNS_PER_PEEP2; | |
d3a923ee | 3013 | |
23280139 RH |
3014 | /* Start up propagation. */ |
3015 | COPY_REG_SET (live, bb->global_live_at_end); | |
3016 | COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); | |
3017 | ||
3018 | #ifdef HAVE_conditional_execution | |
7dfc0fbe | 3019 | pbi = init_propagate_block_info (bb, live, NULL, NULL, 0); |
23280139 | 3020 | #else |
7dfc0fbe | 3021 | pbi = init_propagate_block_info (bb, live, NULL, NULL, PROP_DEATH_NOTES); |
23280139 | 3022 | #endif |
ede7cd44 | 3023 | |
d3a923ee RH |
3024 | for (insn = bb->end; ; insn = prev) |
3025 | { | |
3026 | prev = PREV_INSN (insn); | |
88741818 | 3027 | if (INSN_P (insn)) |
ede7cd44 | 3028 | { |
9be40833 | 3029 | rtx try, before_try, x; |
23280139 | 3030 | int match_len; |
189ae0f4 | 3031 | rtx note; |
546c093e | 3032 | bool was_call = false; |
23280139 RH |
3033 | |
3034 | /* Record this insn. */ | |
3035 | if (--peep2_current < 0) | |
3036 | peep2_current = MAX_INSNS_PER_PEEP2; | |
3037 | peep2_insn_data[peep2_current].insn = insn; | |
3038 | propagate_one_insn (pbi, insn); | |
3039 | COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live); | |
3040 | ||
3041 | /* Match the peephole. */ | |
3042 | try = peephole2_insns (PATTERN (insn), insn, &match_len); | |
d3a923ee RH |
3043 | if (try != NULL) |
3044 | { | |
33593de7 RH |
3045 | /* If we are splitting a CALL_INSN, look for the CALL_INSN |
3046 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other | |
3047 | cfg-related call notes. */ | |
3048 | for (i = 0; i <= match_len; ++i) | |
3049 | { | |
2f937369 | 3050 | int j; |
33593de7 RH |
3051 | rtx old_insn, new_insn, note; |
3052 | ||
3053 | j = i + peep2_current; | |
3054 | if (j >= MAX_INSNS_PER_PEEP2 + 1) | |
3055 | j -= MAX_INSNS_PER_PEEP2 + 1; | |
3056 | old_insn = peep2_insn_data[j].insn; | |
3057 | if (GET_CODE (old_insn) != CALL_INSN) | |
3058 | continue; | |
546c093e | 3059 | was_call = true; |
33593de7 | 3060 | |
2f937369 DM |
3061 | new_insn = try; |
3062 | while (new_insn != NULL_RTX) | |
3063 | { | |
3064 | if (GET_CODE (new_insn) == CALL_INSN) | |
3065 | break; | |
3066 | new_insn = NEXT_INSN (new_insn); | |
3067 | } | |
3068 | ||
3069 | if (new_insn == NULL_RTX) | |
33593de7 RH |
3070 | abort (); |
3071 | ||
3072 | CALL_INSN_FUNCTION_USAGE (new_insn) | |
3073 | = CALL_INSN_FUNCTION_USAGE (old_insn); | |
3074 | ||
3075 | for (note = REG_NOTES (old_insn); | |
3076 | note; | |
3077 | note = XEXP (note, 1)) | |
3078 | switch (REG_NOTE_KIND (note)) | |
3079 | { | |
33593de7 RH |
3080 | case REG_NORETURN: |
3081 | case REG_SETJMP: | |
3082 | case REG_ALWAYS_RETURN: | |
3083 | REG_NOTES (new_insn) | |
3084 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), | |
3085 | XEXP (note, 0), | |
3086 | REG_NOTES (new_insn)); | |
001d2740 | 3087 | default: |
e5837c07 | 3088 | /* Discard all other reg notes. */ |
33593de7 RH |
3089 | break; |
3090 | } | |
3091 | ||
3092 | /* Croak if there is another call in the sequence. */ | |
3093 | while (++i <= match_len) | |
3094 | { | |
3095 | j = i + peep2_current; | |
3096 | if (j >= MAX_INSNS_PER_PEEP2 + 1) | |
3097 | j -= MAX_INSNS_PER_PEEP2 + 1; | |
3098 | old_insn = peep2_insn_data[j].insn; | |
3099 | if (GET_CODE (old_insn) == CALL_INSN) | |
3100 | abort (); | |
3101 | } | |
3102 | break; | |
3103 | } | |
3104 | ||
23280139 RH |
3105 | i = match_len + peep2_current; |
3106 | if (i >= MAX_INSNS_PER_PEEP2 + 1) | |
3107 | i -= MAX_INSNS_PER_PEEP2 + 1; | |
3108 | ||
a6a2274a | 3109 | note = find_reg_note (peep2_insn_data[i].insn, |
6b2e80b7 RH |
3110 | REG_EH_REGION, NULL_RTX); |
3111 | ||
23280139 | 3112 | /* Replace the old sequence with the new. */ |
0435312e JH |
3113 | try = emit_insn_after_setloc (try, peep2_insn_data[i].insn, |
3114 | INSN_LOCATOR (peep2_insn_data[i].insn)); | |
6b2e80b7 | 3115 | before_try = PREV_INSN (insn); |
53c17031 | 3116 | delete_insn_chain (insn, peep2_insn_data[i].insn); |
d3a923ee | 3117 | |
189ae0f4 | 3118 | /* Re-insert the EH_REGION notes. */ |
546c093e | 3119 | if (note || (was_call && nonlocal_goto_handler_labels)) |
189ae0f4 | 3120 | { |
b29afcf8 RH |
3121 | edge eh_edge; |
3122 | ||
3123 | for (eh_edge = bb->succ; eh_edge | |
3124 | ; eh_edge = eh_edge->succ_next) | |
546c093e | 3125 | if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) |
b29afcf8 RH |
3126 | break; |
3127 | ||
6b2e80b7 | 3128 | for (x = try ; x != before_try ; x = PREV_INSN (x)) |
189ae0f4 JH |
3129 | if (GET_CODE (x) == CALL_INSN |
3130 | || (flag_non_call_exceptions | |
6b2e80b7 RH |
3131 | && may_trap_p (PATTERN (x)) |
3132 | && !find_reg_note (x, REG_EH_REGION, NULL))) | |
b29afcf8 | 3133 | { |
546c093e RH |
3134 | if (note) |
3135 | REG_NOTES (x) | |
3136 | = gen_rtx_EXPR_LIST (REG_EH_REGION, | |
3137 | XEXP (note, 0), | |
3138 | REG_NOTES (x)); | |
b29afcf8 | 3139 | |
7654db1b | 3140 | if (x != bb->end && eh_edge) |
b29afcf8 | 3141 | { |
6b2e80b7 RH |
3142 | edge nfte, nehe; |
3143 | int flags; | |
3144 | ||
3145 | nfte = split_block (bb, x); | |
546c093e RH |
3146 | flags = (eh_edge->flags |
3147 | & (EDGE_EH | EDGE_ABNORMAL)); | |
6b2e80b7 RH |
3148 | if (GET_CODE (x) == CALL_INSN) |
3149 | flags |= EDGE_ABNORMAL_CALL; | |
3150 | nehe = make_edge (nfte->src, eh_edge->dest, | |
3151 | flags); | |
3152 | ||
b29afcf8 RH |
3153 | nehe->probability = eh_edge->probability; |
3154 | nfte->probability | |
3155 | = REG_BR_PROB_BASE - nehe->probability; | |
3156 | ||
3157 | do_cleanup_cfg |= purge_dead_edges (nfte->dest); | |
3158 | #ifdef HAVE_conditional_execution | |
3159 | SET_BIT (blocks, nfte->dest->index); | |
3160 | changed = true; | |
3161 | #endif | |
3162 | bb = nfte->src; | |
6b2e80b7 | 3163 | eh_edge = nehe; |
b29afcf8 RH |
3164 | } |
3165 | } | |
3166 | ||
3167 | /* Converting possibly trapping insn to non-trapping is | |
3168 | possible. Zap dummy outgoing edges. */ | |
3169 | do_cleanup_cfg |= purge_dead_edges (bb); | |
189ae0f4 | 3170 | } |
189ae0f4 | 3171 | |
23280139 RH |
3172 | #ifdef HAVE_conditional_execution |
3173 | /* With conditional execution, we cannot back up the | |
3174 | live information so easily, since the conditional | |
3175 | death data structures are not so self-contained. | |
3176 | So record that we've made a modification to this | |
3177 | block and update life information at the end. */ | |
e0082a72 | 3178 | SET_BIT (blocks, bb->index); |
b29afcf8 | 3179 | changed = true; |
23280139 RH |
3180 | |
3181 | for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) | |
3182 | peep2_insn_data[i].insn = NULL_RTX; | |
3183 | peep2_insn_data[peep2_current].insn = PEEP2_EOB; | |
3184 | #else | |
3185 | /* Back up lifetime information past the end of the | |
3186 | newly created sequence. */ | |
3187 | if (++i >= MAX_INSNS_PER_PEEP2 + 1) | |
3188 | i = 0; | |
3189 | COPY_REG_SET (live, peep2_insn_data[i].live_before); | |
3190 | ||
3191 | /* Update life information for the new sequence. */ | |
9be40833 | 3192 | x = try; |
23280139 RH |
3193 | do |
3194 | { | |
9be40833 | 3195 | if (INSN_P (x)) |
23280139 RH |
3196 | { |
3197 | if (--i < 0) | |
3198 | i = MAX_INSNS_PER_PEEP2; | |
9be40833 RH |
3199 | peep2_insn_data[i].insn = x; |
3200 | propagate_one_insn (pbi, x); | |
23280139 RH |
3201 | COPY_REG_SET (peep2_insn_data[i].live_before, live); |
3202 | } | |
9be40833 | 3203 | x = PREV_INSN (x); |
23280139 | 3204 | } |
9be40833 | 3205 | while (x != prev); |
23280139 RH |
3206 | |
3207 | /* ??? Should verify that LIVE now matches what we | |
3208 | had before the new sequence. */ | |
3209 | ||
3210 | peep2_current = i; | |
3211 | #endif | |
9be40833 RH |
3212 | |
3213 | /* If we generated a jump instruction, it won't have | |
3214 | JUMP_LABEL set. Recompute after we're done. */ | |
3215 | for (x = try; x != before_try; x = PREV_INSN (x)) | |
3216 | if (GET_CODE (x) == JUMP_INSN) | |
3217 | { | |
3218 | do_rebuild_jump_labels = true; | |
3219 | break; | |
3220 | } | |
d3a923ee | 3221 | } |
ede7cd44 | 3222 | } |
d3a923ee RH |
3223 | |
3224 | if (insn == bb->head) | |
3225 | break; | |
ede7cd44 | 3226 | } |
23280139 RH |
3227 | |
3228 | free_propagate_block_info (pbi); | |
ede7cd44 RH |
3229 | } |
3230 | ||
23280139 RH |
3231 | for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) |
3232 | FREE_REG_SET (peep2_insn_data[i].live_before); | |
3233 | FREE_REG_SET (live); | |
d3a923ee | 3234 | |
9be40833 RH |
3235 | if (do_rebuild_jump_labels) |
3236 | rebuild_jump_labels (get_insns ()); | |
3237 | ||
b29afcf8 RH |
3238 | /* If we eliminated EH edges, we may be able to merge blocks. Further, |
3239 | we've changed global life since exception handlers are no longer | |
3240 | reachable. */ | |
3241 | if (do_cleanup_cfg) | |
3242 | { | |
3243 | cleanup_cfg (0); | |
3244 | update_life_info (0, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES); | |
3245 | } | |
23280139 | 3246 | #ifdef HAVE_conditional_execution |
b29afcf8 RH |
3247 | else |
3248 | { | |
3249 | count_or_remove_death_notes (blocks, 1); | |
3250 | update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES); | |
3251 | } | |
23280139 | 3252 | sbitmap_free (blocks); |
ede7cd44 | 3253 | #endif |
23280139 RH |
3254 | } |
3255 | #endif /* HAVE_peephole2 */ | |
b37c2614 RH |
3256 | |
3257 | /* Common predicates for use with define_bypass. */ | |
3258 | ||
3259 | /* True if the dependency between OUT_INSN and IN_INSN is on the store | |
091fb516 DM |
3260 | data not the address operand(s) of the store. IN_INSN must be |
3261 | single_set. OUT_INSN must be either a single_set or a PARALLEL with | |
3262 | SETs inside. */ | |
b37c2614 RH |
3263 | |
3264 | int | |
0c20a65f | 3265 | store_data_bypass_p (rtx out_insn, rtx in_insn) |
b37c2614 RH |
3266 | { |
3267 | rtx out_set, in_set; | |
3268 | ||
b37c2614 RH |
3269 | in_set = single_set (in_insn); |
3270 | if (! in_set) | |
3271 | abort (); | |
3272 | ||
3273 | if (GET_CODE (SET_DEST (in_set)) != MEM) | |
3274 | return false; | |
3275 | ||
091fb516 DM |
3276 | out_set = single_set (out_insn); |
3277 | if (out_set) | |
3278 | { | |
3279 | if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set))) | |
3280 | return false; | |
3281 | } | |
3282 | else | |
3283 | { | |
3284 | rtx out_pat; | |
3285 | int i; | |
3286 | ||
3287 | out_pat = PATTERN (out_insn); | |
3288 | if (GET_CODE (out_pat) != PARALLEL) | |
3289 | abort (); | |
3290 | ||
3291 | for (i = 0; i < XVECLEN (out_pat, 0); i++) | |
3292 | { | |
3293 | rtx exp = XVECEXP (out_pat, 0, i); | |
3294 | ||
309527ce DM |
3295 | if (GET_CODE (exp) == CLOBBER) |
3296 | continue; | |
3297 | ||
091fb516 DM |
3298 | if (GET_CODE (exp) != SET) |
3299 | abort (); | |
3300 | ||
3301 | if (reg_mentioned_p (SET_DEST (exp), SET_DEST (in_set))) | |
3302 | return false; | |
3303 | } | |
3304 | } | |
b37c2614 RH |
3305 | |
3306 | return true; | |
3307 | } | |
3308 | ||
688ec718 RH |
3309 | /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE |
3310 | condition, and not the THEN or ELSE branch. OUT_INSN may be either a single | |
3311 | or multiple set; IN_INSN should be single_set for truth, but for convenience | |
3312 | of insn categorization may be any JUMP or CALL insn. */ | |
b37c2614 RH |
3313 | |
3314 | int | |
0c20a65f | 3315 | if_test_bypass_p (rtx out_insn, rtx in_insn) |
b37c2614 RH |
3316 | { |
3317 | rtx out_set, in_set; | |
3318 | ||
b37c2614 RH |
3319 | in_set = single_set (in_insn); |
3320 | if (! in_set) | |
688ec718 RH |
3321 | { |
3322 | if (GET_CODE (in_insn) == JUMP_INSN || GET_CODE (in_insn) == CALL_INSN) | |
3323 | return false; | |
3324 | abort (); | |
3325 | } | |
b37c2614 RH |
3326 | |
3327 | if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE) | |
3328 | return false; | |
688ec718 | 3329 | in_set = SET_SRC (in_set); |
b37c2614 | 3330 | |
688ec718 RH |
3331 | out_set = single_set (out_insn); |
3332 | if (out_set) | |
3333 | { | |
3334 | if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1)) | |
3335 | || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2))) | |
a6a2274a | 3336 | return false; |
688ec718 RH |
3337 | } |
3338 | else | |
3339 | { | |
3340 | rtx out_pat; | |
3341 | int i; | |
3342 | ||
3343 | out_pat = PATTERN (out_insn); | |
3344 | if (GET_CODE (out_pat) != PARALLEL) | |
3345 | abort (); | |
3346 | ||
3347 | for (i = 0; i < XVECLEN (out_pat, 0); i++) | |
3348 | { | |
3349 | rtx exp = XVECEXP (out_pat, 0, i); | |
3350 | ||
3351 | if (GET_CODE (exp) == CLOBBER) | |
3352 | continue; | |
3353 | ||
3354 | if (GET_CODE (exp) != SET) | |
3355 | abort (); | |
3356 | ||
3357 | if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1)) | |
3358 | || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2))) | |
3359 | return false; | |
3360 | } | |
3361 | } | |
b37c2614 RH |
3362 | |
3363 | return true; | |
3364 | } |