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2055cea7 RK |
1 | /* Subroutines used by or related to instruction recognition. |
2 | Copyright (C) 1987-1991 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | #include "config.h" | |
22 | #include "rtl.h" | |
23 | #include <stdio.h> | |
24 | #include "insn-config.h" | |
25 | #include "insn-attr.h" | |
26 | #include "insn-flags.h" | |
27 | #include "insn-codes.h" | |
28 | #include "recog.h" | |
29 | #include "regs.h" | |
30 | #include "hard-reg-set.h" | |
31 | #include "flags.h" | |
32 | #include "real.h" | |
33 | ||
34 | #ifndef STACK_PUSH_CODE | |
35 | #ifdef STACK_GROWS_DOWNWARD | |
36 | #define STACK_PUSH_CODE PRE_DEC | |
37 | #else | |
38 | #define STACK_PUSH_CODE PRE_INC | |
39 | #endif | |
40 | #endif | |
41 | ||
42 | /* Import from final.c: */ | |
43 | extern rtx alter_subreg (); | |
44 | ||
45 | int strict_memory_address_p (); | |
46 | int memory_address_p (); | |
47 | ||
48 | /* Nonzero means allow operands to be volatile. | |
49 | This should be 0 if you are generating rtl, such as if you are calling | |
50 | the functions in optabs.c and expmed.c (most of the time). | |
51 | This should be 1 if all valid insns need to be recognized, | |
52 | such as in regclass.c and final.c and reload.c. | |
53 | ||
54 | init_recog and init_recog_no_volatile are responsible for setting this. */ | |
55 | ||
56 | int volatile_ok; | |
57 | ||
58 | /* On return from `constrain_operands', indicate which alternative | |
59 | was satisfied. */ | |
60 | ||
61 | int which_alternative; | |
62 | ||
63 | /* Nonzero after end of reload pass. | |
64 | Set to 1 or 0 by toplev.c. | |
65 | Controls the significance of (SUBREG (MEM)). */ | |
66 | ||
67 | int reload_completed; | |
68 | ||
69 | /* Initialize data used by the function `recog'. | |
70 | This must be called once in the compilation of a function | |
71 | before any insn recognition may be done in the function. */ | |
72 | ||
73 | void | |
74 | init_recog_no_volatile () | |
75 | { | |
76 | volatile_ok = 0; | |
77 | } | |
78 | ||
79 | init_recog () | |
80 | { | |
81 | volatile_ok = 1; | |
82 | } | |
83 | ||
84 | /* Try recognizing the instruction INSN, | |
85 | and return the code number that results. | |
86 | Remeber the code so that repeated calls do not | |
87 | need to spend the time for actual rerecognition. | |
88 | ||
89 | This function is the normal interface to instruction recognition. | |
90 | The automatically-generated function `recog' is normally called | |
91 | through this one. (The only exception is in combine.c.) */ | |
92 | ||
93 | int | |
94 | recog_memoized (insn) | |
95 | rtx insn; | |
96 | { | |
97 | if (INSN_CODE (insn) < 0) | |
98 | INSN_CODE (insn) = recog (PATTERN (insn), insn, 0); | |
99 | return INSN_CODE (insn); | |
100 | } | |
101 | \f | |
102 | /* Check that X is an insn-body for an `asm' with operands | |
103 | and that the operands mentioned in it are legitimate. */ | |
104 | ||
105 | int | |
106 | check_asm_operands (x) | |
107 | rtx x; | |
108 | { | |
109 | int noperands = asm_noperands (x); | |
110 | rtx *operands; | |
111 | int i; | |
112 | ||
113 | if (noperands < 0) | |
114 | return 0; | |
115 | if (noperands == 0) | |
116 | return 1; | |
117 | ||
118 | operands = (rtx *) alloca (noperands * sizeof (rtx)); | |
119 | decode_asm_operands (x, operands, 0, 0, 0); | |
120 | ||
121 | for (i = 0; i < noperands; i++) | |
122 | if (!general_operand (operands[i], VOIDmode)) | |
123 | return 0; | |
124 | ||
125 | return 1; | |
126 | } | |
127 | \f | |
128 | /* Static data for the next two routines. | |
129 | ||
130 | The maximum number of changes supported is defined as the maximum | |
131 | number of operands times 5. This allows for repeated substitutions | |
132 | inside complex indexed address, or, alternatively, changes in up | |
133 | to 5 insns. */ | |
134 | ||
135 | #define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5) | |
136 | ||
137 | static rtx change_objects[MAX_CHANGE_LOCS]; | |
138 | static int change_old_codes[MAX_CHANGE_LOCS]; | |
139 | static rtx *change_locs[MAX_CHANGE_LOCS]; | |
140 | static rtx change_olds[MAX_CHANGE_LOCS]; | |
141 | ||
142 | static int num_changes = 0; | |
143 | ||
144 | /* Validate a proposed change to OBJECT. LOC is the location in the rtl for | |
145 | at which NEW will be placed. If OBJECT is zero, no validation is done, | |
146 | the change is simply made. | |
147 | ||
148 | Two types of objects are supported: If OBJECT is a MEM, memory_address_p | |
149 | will be called with the address and mode as parameters. If OBJECT is | |
150 | an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with | |
151 | the change in place. | |
152 | ||
153 | IN_GROUP is non-zero if this is part of a group of changes that must be | |
154 | performed as a group. In that case, the changes will be stored. The | |
155 | function `apply_change_group' will validate and apply the changes. | |
156 | ||
157 | If IN_GROUP is zero, this is a single change. Try to recognize the insn | |
158 | or validate the memory reference with the change applied. If the result | |
159 | is not valid for the machine, suppress the change and return zero. | |
160 | Otherwise, perform the change and return 1. */ | |
161 | ||
162 | int | |
163 | validate_change (object, loc, new, in_group) | |
164 | rtx object; | |
165 | rtx *loc; | |
166 | rtx new; | |
167 | int in_group; | |
168 | { | |
169 | rtx old = *loc; | |
170 | ||
171 | if (old == new || rtx_equal_p (old, new)) | |
172 | return 1; | |
173 | ||
174 | if (num_changes >= MAX_CHANGE_LOCS | |
175 | || (in_group == 0 && num_changes != 0)) | |
176 | abort (); | |
177 | ||
178 | *loc = new; | |
179 | ||
180 | /* Save the information describing this change. */ | |
181 | change_objects[num_changes] = object; | |
182 | change_locs[num_changes] = loc; | |
183 | change_olds[num_changes] = old; | |
184 | ||
185 | if (object && GET_CODE (object) != MEM) | |
186 | { | |
187 | /* Set INSN_CODE to force rerecognition of insn. Save old code in | |
188 | case invalid. */ | |
189 | change_old_codes[num_changes] = INSN_CODE (object); | |
190 | INSN_CODE (object) = -1; | |
191 | } | |
192 | ||
193 | num_changes++; | |
194 | ||
195 | /* If we are making a group of changes, return 1. Otherwise, validate the | |
196 | change group we made. */ | |
197 | ||
198 | if (in_group) | |
199 | return 1; | |
200 | else | |
201 | return apply_change_group (); | |
202 | } | |
203 | ||
204 | /* Apply a group of changes previously issued with `validate_change'. | |
205 | Return 1 if all changes are valid, zero otherwise. */ | |
206 | ||
207 | int | |
208 | apply_change_group () | |
209 | { | |
210 | int i; | |
211 | ||
212 | /* The changes have been applied and all INSN_CODEs have been reset to force | |
213 | rerecognition. | |
214 | ||
215 | The changes are valid if we aren't given an object, or if we are | |
216 | given a MEM and it still is a valid address, or if this is in insn | |
217 | and it is recognized. In the latter case, if reload has completed, | |
218 | we also require that the operands meet the constraints for | |
219 | the insn. We do not allow modifying an ASM_OPERANDS after reload | |
220 | has completed because verifying the constraints is too difficult. */ | |
221 | ||
222 | for (i = 0; i < num_changes; i++) | |
223 | { | |
224 | rtx object = change_objects[i]; | |
225 | ||
226 | if (object == 0) | |
227 | continue; | |
228 | ||
229 | if (GET_CODE (object) == MEM) | |
230 | { | |
231 | if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) | |
232 | break; | |
233 | } | |
234 | else if ((recog_memoized (object) < 0 | |
235 | && (asm_noperands (PATTERN (object)) < 0 | |
236 | || ! check_asm_operands (PATTERN (object)) | |
237 | || reload_completed)) | |
238 | || (reload_completed | |
239 | && (insn_extract (object), | |
240 | ! constrain_operands (INSN_CODE (object), 1)))) | |
241 | { | |
242 | rtx pat = PATTERN (object); | |
243 | ||
244 | /* Perhaps we couldn't recognize the insn because there were | |
245 | extra CLOBBERs at the end. If so, try to re-recognize | |
246 | without the last CLOBBER (later iterations will cause each of | |
247 | them to be eliminated, in turn). But don't do this if we | |
248 | have an ASM_OPERAND. */ | |
249 | if (GET_CODE (pat) == PARALLEL | |
250 | && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER | |
251 | && asm_noperands (PATTERN (object)) < 0) | |
252 | { | |
253 | rtx newpat; | |
254 | ||
255 | if (XVECLEN (pat, 0) == 2) | |
256 | newpat = XVECEXP (pat, 0, 0); | |
257 | else | |
258 | { | |
259 | int j; | |
260 | ||
261 | newpat = gen_rtx (PARALLEL, VOIDmode, | |
262 | gen_rtvec (XVECLEN (pat, 0) - 1)); | |
263 | for (j = 0; j < XVECLEN (newpat, 0); j++) | |
264 | XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); | |
265 | } | |
266 | ||
267 | /* Add a new change to this group to replace the pattern | |
268 | with this new pattern. Then consider this change | |
269 | as having succeeded. The change we added will | |
270 | cause the entire call to fail if things remain invalid. | |
271 | ||
272 | Note that this can lose if a later change than the one | |
273 | we are processing specified &XVECEXP (PATTERN (object), 0, X) | |
274 | but this shouldn't occur. */ | |
275 | ||
276 | validate_change (object, &PATTERN (object), newpat, 1); | |
277 | } | |
278 | else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) | |
279 | /* If this insn is a CLOBBER or USE, it is always valid, but is | |
280 | never recognized. */ | |
281 | continue; | |
282 | else | |
283 | break; | |
284 | } | |
285 | } | |
286 | ||
287 | if (i == num_changes) | |
288 | { | |
289 | num_changes = 0; | |
290 | return 1; | |
291 | } | |
292 | else | |
293 | { | |
294 | cancel_changes (0); | |
295 | return 0; | |
296 | } | |
297 | } | |
298 | ||
299 | /* Return the number of changes so far in the current group. */ | |
300 | ||
301 | int | |
302 | num_validated_changes () | |
303 | { | |
304 | return num_changes; | |
305 | } | |
306 | ||
307 | /* Retract the changes numbered NUM and up. */ | |
308 | ||
309 | void | |
310 | cancel_changes (num) | |
311 | int num; | |
312 | { | |
313 | int i; | |
314 | ||
315 | /* Back out all the changes. Do this in the opposite order in which | |
316 | they were made. */ | |
317 | for (i = num_changes - 1; i >= num; i--) | |
318 | { | |
319 | *change_locs[i] = change_olds[i]; | |
320 | if (change_objects[i] && GET_CODE (change_objects[i]) != MEM) | |
321 | INSN_CODE (change_objects[i]) = change_old_codes[i]; | |
322 | } | |
323 | num_changes = num; | |
324 | } | |
325 | ||
326 | /* Replace every occurrence of FROM in X with TO. Mark each change with | |
327 | validate_change passing OBJECT. */ | |
328 | ||
329 | static void | |
330 | validate_replace_rtx_1 (loc, from, to, object) | |
331 | rtx *loc; | |
332 | rtx from, to, object; | |
333 | { | |
334 | register int i, j; | |
335 | register char *fmt; | |
336 | register rtx x = *loc; | |
337 | enum rtx_code code = GET_CODE (x); | |
338 | ||
339 | /* X matches FROM if it is the same rtx or they are both referring to the | |
340 | same register in the same mode. Avoid calling rtx_equal_p unless the | |
341 | operands look similar. */ | |
342 | ||
343 | if (x == from | |
344 | || (GET_CODE (x) == REG && GET_CODE (from) == REG | |
345 | && GET_MODE (x) == GET_MODE (from) | |
346 | && REGNO (x) == REGNO (from)) | |
347 | || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) | |
348 | && rtx_equal_p (x, from))) | |
349 | { | |
350 | validate_change (object, loc, to, 1); | |
351 | return; | |
352 | } | |
353 | ||
354 | /* For commutative or comparison operations, try replacing each argument | |
355 | separately and seeing if we made any changes. If so, put a constant | |
356 | argument last.*/ | |
357 | if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') | |
358 | { | |
359 | int prev_changes = num_changes; | |
360 | ||
361 | validate_replace_rtx_1 (&XEXP (x, 0), from, to, object); | |
362 | validate_replace_rtx_1 (&XEXP (x, 1), from, to, object); | |
363 | if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0))) | |
364 | { | |
365 | validate_change (object, loc, | |
366 | gen_rtx (GET_RTX_CLASS (code) == 'c' ? code | |
367 | : swap_condition (code), | |
368 | GET_MODE (x), XEXP (x, 1), XEXP (x, 0)), | |
369 | 1); | |
370 | x = *loc; | |
371 | code = GET_CODE (x); | |
372 | } | |
373 | } | |
374 | ||
375 | switch (code) | |
376 | { | |
377 | case PLUS: | |
378 | /* If we have have a PLUS whose second operand is now a CONST_INT, use | |
379 | plus_constant to try to simplify it. */ | |
380 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to) | |
381 | validate_change (object, loc, | |
382 | plus_constant (XEXP (x, 0), INTVAL (XEXP (x, 1))), 1); | |
383 | return; | |
384 | ||
385 | case ZERO_EXTEND: | |
386 | case SIGN_EXTEND: | |
387 | /* In these cases, the operation to be performed depends on the mode | |
388 | of the operand. If we are replacing the operand with a VOIDmode | |
389 | constant, we lose the information. So try to simplify the operation | |
390 | in that case. If it fails, substitute in something that we know | |
391 | won't be recogized. */ | |
392 | if (GET_MODE (to) == VOIDmode | |
393 | && (XEXP (x, 0) == from | |
394 | || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG | |
395 | && GET_MODE (XEXP (x, 0)) == GET_MODE (from) | |
396 | && REGNO (XEXP (x, 0)) == REGNO (from)))) | |
397 | { | |
398 | rtx new = simplify_unary_operation (code, GET_MODE (x), to, | |
399 | GET_MODE (from)); | |
400 | if (new == 0) | |
401 | new = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); | |
402 | ||
403 | validate_change (object, loc, new, 1); | |
404 | return; | |
405 | } | |
406 | break; | |
407 | ||
408 | case SUBREG: | |
409 | /* If we have a SUBREG of a register that we are replacing and we are | |
410 | replacing it with a MEM, make a new MEM and try replacing the | |
411 | SUBREG with it. Don't do this if the MEM has a mode-dependent address | |
412 | or if we would be widening it. */ | |
413 | ||
414 | if (SUBREG_REG (x) == from | |
415 | && GET_CODE (from) == REG | |
416 | && GET_CODE (to) == MEM | |
417 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
418 | && ! MEM_VOLATILE_P (to) | |
419 | && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to))) | |
420 | { | |
421 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
422 | enum machine_mode mode = GET_MODE (x); | |
423 | rtx new; | |
424 | ||
425 | #if BYTES_BIG_ENDIAN | |
426 | offset += (MIN (UNITS_PER_WORD, | |
427 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
428 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
429 | #endif | |
430 | ||
431 | new = gen_rtx (MEM, mode, plus_constant (XEXP (to, 0), offset)); | |
432 | MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to); | |
433 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to); | |
434 | MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to); | |
435 | validate_change (object, loc, new, 1); | |
436 | return; | |
437 | } | |
438 | break; | |
439 | ||
440 | case ZERO_EXTRACT: | |
441 | case SIGN_EXTRACT: | |
442 | /* If we are replacing a register with memory, try to change the memory | |
443 | to be the mode required for memory in extract operations (this isn't | |
444 | likely to be an insertion operation; if it was, nothing bad will | |
445 | happen, we might just fail in some cases). */ | |
446 | ||
447 | if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM | |
448 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
449 | && GET_CODE (XEXP (x, 2)) == CONST_INT | |
450 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
451 | && ! MEM_VOLATILE_P (to)) | |
452 | { | |
453 | enum machine_mode wanted_mode = VOIDmode; | |
454 | enum machine_mode is_mode = GET_MODE (to); | |
455 | int width = INTVAL (XEXP (x, 1)); | |
456 | int pos = INTVAL (XEXP (x, 2)); | |
457 | ||
458 | #ifdef HAVE_extzv | |
459 | if (code == ZERO_EXTRACT) | |
460 | wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; | |
461 | #endif | |
462 | #ifdef HAVE_extv | |
463 | if (code == SIGN_EXTRACT) | |
464 | wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; | |
465 | #endif | |
466 | ||
467 | /* If we have a narrower mode, we can do someting. */ | |
468 | if (wanted_mode != VOIDmode | |
469 | && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) | |
470 | { | |
471 | int offset = pos / BITS_PER_UNIT; | |
472 | rtx newmem; | |
473 | ||
474 | /* If the bytes and bits are counted differently, we | |
475 | must adjust the offset. */ | |
476 | #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN | |
477 | offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) | |
478 | - offset); | |
479 | #endif | |
480 | ||
481 | pos %= GET_MODE_BITSIZE (wanted_mode); | |
482 | ||
483 | newmem = gen_rtx (MEM, wanted_mode, | |
484 | plus_constant (XEXP (to, 0), offset)); | |
485 | RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to); | |
486 | MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (to); | |
487 | MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (to); | |
488 | ||
489 | validate_change (object, &XEXP (x, 2), | |
490 | gen_rtx (CONST_INT, VOIDmode, pos), 1); | |
491 | validate_change (object, &XEXP (x, 0), newmem, 1); | |
492 | } | |
493 | } | |
494 | ||
495 | break; | |
496 | } | |
497 | ||
498 | fmt = GET_RTX_FORMAT (code); | |
499 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
500 | { | |
501 | if (fmt[i] == 'e') | |
502 | validate_replace_rtx_1 (&XEXP (x, i), from, to, object); | |
503 | else if (fmt[i] == 'E') | |
504 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
505 | validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); | |
506 | } | |
507 | } | |
508 | ||
509 | /* Try replacing every occurrence of FROM in INSN with TO. After all | |
510 | changes have been made, validate by seeing if INSN is still valid. */ | |
511 | ||
512 | int | |
513 | validate_replace_rtx (from, to, insn) | |
514 | rtx from, to, insn; | |
515 | { | |
516 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
517 | return apply_change_group (); | |
518 | } | |
519 | \f | |
520 | #ifdef HAVE_cc0 | |
521 | /* Return 1 if the insn using CC0 set by INSN does not contain | |
522 | any ordered tests applied to the condition codes. | |
523 | EQ and NE tests do not count. */ | |
524 | ||
525 | int | |
526 | next_insn_tests_no_inequality (insn) | |
527 | rtx insn; | |
528 | { | |
529 | register rtx next = next_cc0_user (insn); | |
530 | ||
531 | /* If there is no next insn, we have to take the conservative choice. */ | |
532 | if (next == 0) | |
533 | return 0; | |
534 | ||
535 | return ((GET_CODE (next) == JUMP_INSN | |
536 | || GET_CODE (next) == INSN | |
537 | || GET_CODE (next) == CALL_INSN) | |
538 | && ! inequality_comparisons_p (PATTERN (next))); | |
539 | } | |
540 | ||
541 | #if 0 /* This is useless since the insn that sets the cc's | |
542 | must be followed immediately by the use of them. */ | |
543 | /* Return 1 if the CC value set up by INSN is not used. */ | |
544 | ||
545 | int | |
546 | next_insns_test_no_inequality (insn) | |
547 | rtx insn; | |
548 | { | |
549 | register rtx next = NEXT_INSN (insn); | |
550 | ||
551 | for (; next != 0; next = NEXT_INSN (next)) | |
552 | { | |
553 | if (GET_CODE (next) == CODE_LABEL | |
554 | || GET_CODE (next) == BARRIER) | |
555 | return 1; | |
556 | if (GET_CODE (next) == NOTE) | |
557 | continue; | |
558 | if (inequality_comparisons_p (PATTERN (next))) | |
559 | return 0; | |
560 | if (sets_cc0_p (PATTERN (next)) == 1) | |
561 | return 1; | |
562 | if (! reg_mentioned_p (cc0_rtx, PATTERN (next))) | |
563 | return 1; | |
564 | } | |
565 | return 1; | |
566 | } | |
567 | #endif | |
568 | #endif | |
569 | \f | |
570 | /* This is used by find_single_use to locate an rtx that contains exactly one | |
571 | use of DEST, which is typically either a REG or CC0. It returns a | |
572 | pointer to the innermost rtx expression containing DEST. Appearances of | |
573 | DEST that are being used to totally replace it are not counted. */ | |
574 | ||
575 | static rtx * | |
576 | find_single_use_1 (dest, loc) | |
577 | rtx dest; | |
578 | rtx *loc; | |
579 | { | |
580 | rtx x = *loc; | |
581 | enum rtx_code code = GET_CODE (x); | |
582 | rtx *result = 0; | |
583 | rtx *this_result; | |
584 | int i; | |
585 | char *fmt; | |
586 | ||
587 | switch (code) | |
588 | { | |
589 | case CONST_INT: | |
590 | case CONST: | |
591 | case LABEL_REF: | |
592 | case SYMBOL_REF: | |
593 | case CONST_DOUBLE: | |
594 | case CLOBBER: | |
595 | return 0; | |
596 | ||
597 | case SET: | |
598 | /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
599 | of a REG that occupies all of the REG, the insn uses DEST if | |
600 | it is mentioned in the destination or the source. Otherwise, we | |
601 | need just check the source. */ | |
602 | if (GET_CODE (SET_DEST (x)) != CC0 | |
603 | && GET_CODE (SET_DEST (x)) != PC | |
604 | && GET_CODE (SET_DEST (x)) != REG | |
605 | && ! (GET_CODE (SET_DEST (x)) == SUBREG | |
606 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
607 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
608 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
609 | == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
610 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
611 | break; | |
612 | ||
613 | return find_single_use_1 (dest, &SET_SRC (x)); | |
614 | ||
615 | case MEM: | |
616 | case SUBREG: | |
617 | return find_single_use_1 (dest, &XEXP (x, 0)); | |
618 | } | |
619 | ||
620 | /* If it wasn't one of the common cases above, check each expression and | |
621 | vector of this code. Look for a unique usage of DEST. */ | |
622 | ||
623 | fmt = GET_RTX_FORMAT (code); | |
624 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
625 | { | |
626 | if (fmt[i] == 'e') | |
627 | { | |
628 | if (dest == XEXP (x, i) | |
629 | || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG | |
630 | && REGNO (dest) == REGNO (XEXP (x, i)))) | |
631 | this_result = loc; | |
632 | else | |
633 | this_result = find_single_use_1 (dest, &XEXP (x, i)); | |
634 | ||
635 | if (result == 0) | |
636 | result = this_result; | |
637 | else if (this_result) | |
638 | /* Duplicate usage. */ | |
639 | return 0; | |
640 | } | |
641 | else if (fmt[i] == 'E') | |
642 | { | |
643 | int j; | |
644 | ||
645 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
646 | { | |
647 | if (XVECEXP (x, i, j) == dest | |
648 | || (GET_CODE (dest) == REG | |
649 | && GET_CODE (XVECEXP (x, i, j)) == REG | |
650 | && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) | |
651 | this_result = loc; | |
652 | else | |
653 | this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); | |
654 | ||
655 | if (result == 0) | |
656 | result = this_result; | |
657 | else if (this_result) | |
658 | return 0; | |
659 | } | |
660 | } | |
661 | } | |
662 | ||
663 | return result; | |
664 | } | |
665 | \f | |
666 | /* See if DEST, produced in INSN, is used only a single time in the | |
667 | sequel. If so, return a pointer to the innermost rtx expression in which | |
668 | it is used. | |
669 | ||
670 | If PLOC is non-zero, *PLOC is set to the insn containing the single use. | |
671 | ||
672 | This routine will return usually zero either before flow is called (because | |
673 | there will be no LOG_LINKS notes) or after reload (because the REG_DEAD | |
674 | note can't be trusted). | |
675 | ||
676 | If DEST is cc0_rtx, we look only at the next insn. In that case, we don't | |
677 | care about REG_DEAD notes or LOG_LINKS. | |
678 | ||
679 | Otherwise, we find the single use by finding an insn that has a | |
680 | LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is | |
681 | only referenced once in that insn, we know that it must be the first | |
682 | and last insn referencing DEST. */ | |
683 | ||
684 | rtx * | |
685 | find_single_use (dest, insn, ploc) | |
686 | rtx dest; | |
687 | rtx insn; | |
688 | rtx *ploc; | |
689 | { | |
690 | rtx next; | |
691 | rtx *result; | |
692 | rtx link; | |
693 | ||
694 | #ifdef HAVE_cc0 | |
695 | if (dest == cc0_rtx) | |
696 | { | |
697 | next = NEXT_INSN (insn); | |
698 | if (next == 0 | |
699 | || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN)) | |
700 | return 0; | |
701 | ||
702 | result = find_single_use_1 (dest, &PATTERN (next)); | |
703 | if (result && ploc) | |
704 | *ploc = next; | |
705 | return result; | |
706 | } | |
707 | #endif | |
708 | ||
709 | if (reload_completed || reload_in_progress || GET_CODE (dest) != REG) | |
710 | return 0; | |
711 | ||
712 | for (next = next_nonnote_insn (insn); | |
713 | next != 0 && GET_CODE (next) != CODE_LABEL; | |
714 | next = next_nonnote_insn (next)) | |
715 | if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest)) | |
716 | { | |
717 | for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) | |
718 | if (XEXP (link, 0) == insn) | |
719 | break; | |
720 | ||
721 | if (link) | |
722 | { | |
723 | result = find_single_use_1 (dest, &PATTERN (next)); | |
724 | if (ploc) | |
725 | *ploc = next; | |
726 | return result; | |
727 | } | |
728 | } | |
729 | ||
730 | return 0; | |
731 | } | |
732 | \f | |
733 | /* Return 1 if OP is a valid general operand for machine mode MODE. | |
734 | This is either a register reference, a memory reference, | |
735 | or a constant. In the case of a memory reference, the address | |
736 | is checked for general validity for the target machine. | |
737 | ||
738 | Register and memory references must have mode MODE in order to be valid, | |
739 | but some constants have no machine mode and are valid for any mode. | |
740 | ||
741 | If MODE is VOIDmode, OP is checked for validity for whatever mode | |
742 | it has. | |
743 | ||
744 | The main use of this function is as a predicate in match_operand | |
745 | expressions in the machine description. | |
746 | ||
747 | For an explaination of this function's behavior for registers of | |
748 | class NO_REGS, see the comment for `register_operand'. */ | |
749 | ||
750 | int | |
751 | general_operand (op, mode) | |
752 | register rtx op; | |
753 | enum machine_mode mode; | |
754 | { | |
755 | register enum rtx_code code = GET_CODE (op); | |
756 | int mode_altering_drug = 0; | |
757 | ||
758 | if (mode == VOIDmode) | |
759 | mode = GET_MODE (op); | |
760 | ||
761 | /* Don't accept CONST_INT or anything similar | |
762 | if the caller wants something floating. */ | |
763 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
764 | && GET_MODE_CLASS (mode) != MODE_INT) | |
765 | return 0; | |
766 | ||
767 | if (CONSTANT_P (op)) | |
768 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
769 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
770 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
771 | #endif | |
772 | && LEGITIMATE_CONSTANT_P (op)); | |
773 | ||
774 | /* Except for certain constants with VOIDmode, already checked for, | |
775 | OP's mode must match MODE if MODE specifies a mode. */ | |
776 | ||
777 | if (GET_MODE (op) != mode) | |
778 | return 0; | |
779 | ||
780 | if (code == SUBREG) | |
781 | { | |
782 | #ifdef INSN_SCHEDULING | |
783 | /* On machines that have insn scheduling, we want all memory | |
784 | reference to be explicit, so outlaw paradoxical SUBREGs. */ | |
785 | if (GET_CODE (SUBREG_REG (op)) == MEM | |
786 | && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) | |
787 | return 0; | |
788 | #endif | |
789 | ||
790 | op = SUBREG_REG (op); | |
791 | code = GET_CODE (op); | |
792 | #if 0 | |
793 | /* No longer needed, since (SUBREG (MEM...)) | |
794 | will load the MEM into a reload reg in the MEM's own mode. */ | |
795 | mode_altering_drug = 1; | |
796 | #endif | |
797 | } | |
798 | ||
799 | if (code == REG) | |
800 | /* A register whose class is NO_REGS is not a general operand. */ | |
801 | return (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
802 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); | |
803 | ||
804 | if (code == MEM) | |
805 | { | |
806 | register rtx y = XEXP (op, 0); | |
807 | if (! volatile_ok && MEM_VOLATILE_P (op)) | |
808 | return 0; | |
809 | /* Use the mem's mode, since it will be reloaded thus. */ | |
810 | mode = GET_MODE (op); | |
811 | GO_IF_LEGITIMATE_ADDRESS (mode, y, win); | |
812 | } | |
813 | return 0; | |
814 | ||
815 | win: | |
816 | if (mode_altering_drug) | |
817 | return ! mode_dependent_address_p (XEXP (op, 0)); | |
818 | return 1; | |
819 | } | |
820 | \f | |
821 | /* Return 1 if OP is a valid memory address for a memory reference | |
822 | of mode MODE. | |
823 | ||
824 | The main use of this function is as a predicate in match_operand | |
825 | expressions in the machine description. */ | |
826 | ||
827 | int | |
828 | address_operand (op, mode) | |
829 | register rtx op; | |
830 | enum machine_mode mode; | |
831 | { | |
832 | return memory_address_p (mode, op); | |
833 | } | |
834 | ||
835 | /* Return 1 if OP is a register reference of mode MODE. | |
836 | If MODE is VOIDmode, accept a register in any mode. | |
837 | ||
838 | The main use of this function is as a predicate in match_operand | |
839 | expressions in the machine description. | |
840 | ||
841 | As a special exception, registers whose class is NO_REGS are | |
842 | not accepted by `register_operand'. The reason for this change | |
843 | is to allow the representation of special architecture artifacts | |
844 | (such as a condition code register) without extending the rtl | |
845 | definitions. Since registers of class NO_REGS cannot be used | |
846 | as registers in any case where register classes are examined, | |
847 | it is most consistent to keep this function from accepting them. */ | |
848 | ||
849 | int | |
850 | register_operand (op, mode) | |
851 | register rtx op; | |
852 | enum machine_mode mode; | |
853 | { | |
854 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
855 | return 0; | |
856 | ||
857 | if (GET_CODE (op) == SUBREG) | |
858 | { | |
859 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
860 | because it is guaranteed to be reloaded into one. | |
861 | Just make sure the MEM is valid in itself. | |
862 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
863 | but currently it does result from (SUBREG (REG)...) where the | |
864 | reg went on the stack.) */ | |
865 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
866 | return general_operand (op, mode); | |
867 | op = SUBREG_REG (op); | |
868 | } | |
869 | ||
870 | /* We don't consider registers whose class is NO_REGS | |
871 | to be a register operand. */ | |
872 | return (GET_CODE (op) == REG | |
873 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
874 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
875 | } | |
876 | ||
877 | /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH | |
878 | or a hard register. */ | |
879 | ||
880 | int | |
881 | scratch_operand (op, mode) | |
882 | register rtx op; | |
883 | enum machine_mode mode; | |
884 | { | |
885 | return (GET_MODE (op) == mode | |
886 | && (GET_CODE (op) == SCRATCH | |
887 | || (GET_CODE (op) == REG | |
888 | && REGNO (op) < FIRST_PSEUDO_REGISTER))); | |
889 | } | |
890 | ||
891 | /* Return 1 if OP is a valid immediate operand for mode MODE. | |
892 | ||
893 | The main use of this function is as a predicate in match_operand | |
894 | expressions in the machine description. */ | |
895 | ||
896 | int | |
897 | immediate_operand (op, mode) | |
898 | register rtx op; | |
899 | enum machine_mode mode; | |
900 | { | |
901 | /* Don't accept CONST_INT or anything similar | |
902 | if the caller wants something floating. */ | |
903 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
904 | && GET_MODE_CLASS (mode) != MODE_INT) | |
905 | return 0; | |
906 | ||
907 | return (CONSTANT_P (op) | |
908 | && (GET_MODE (op) == mode || mode == VOIDmode | |
909 | || GET_MODE (op) == VOIDmode) | |
910 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
911 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
912 | #endif | |
913 | && LEGITIMATE_CONSTANT_P (op)); | |
914 | } | |
915 | ||
916 | /* Returns 1 if OP is an operand that is a CONST_INT. */ | |
917 | ||
918 | int | |
919 | const_int_operand (op, mode) | |
920 | register rtx op; | |
921 | enum machine_mode mode; | |
922 | { | |
923 | return GET_CODE (op) == CONST_INT; | |
924 | } | |
925 | ||
926 | /* Returns 1 if OP is an operand that is a constant integer or constant | |
927 | floating-point number. */ | |
928 | ||
929 | int | |
930 | const_double_operand (op, mode) | |
931 | register rtx op; | |
932 | enum machine_mode mode; | |
933 | { | |
934 | /* Don't accept CONST_INT or anything similar | |
935 | if the caller wants something floating. */ | |
936 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
937 | && GET_MODE_CLASS (mode) != MODE_INT) | |
938 | return 0; | |
939 | ||
940 | return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) | |
941 | && (mode == VOIDmode || GET_MODE (op) == mode | |
942 | || GET_MODE (op) == VOIDmode)); | |
943 | } | |
944 | ||
945 | /* Return 1 if OP is a general operand that is not an immediate operand. */ | |
946 | ||
947 | int | |
948 | nonimmediate_operand (op, mode) | |
949 | register rtx op; | |
950 | enum machine_mode mode; | |
951 | { | |
952 | return (general_operand (op, mode) && ! CONSTANT_P (op)); | |
953 | } | |
954 | ||
955 | /* Return 1 if OP is a register reference or immediate value of mode MODE. */ | |
956 | ||
957 | int | |
958 | nonmemory_operand (op, mode) | |
959 | register rtx op; | |
960 | enum machine_mode mode; | |
961 | { | |
962 | if (CONSTANT_P (op)) | |
963 | { | |
964 | /* Don't accept CONST_INT or anything similar | |
965 | if the caller wants something floating. */ | |
966 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
967 | && GET_MODE_CLASS (mode) != MODE_INT) | |
968 | return 0; | |
969 | ||
970 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
971 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
972 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
973 | #endif | |
974 | && LEGITIMATE_CONSTANT_P (op)); | |
975 | } | |
976 | ||
977 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
978 | return 0; | |
979 | ||
980 | if (GET_CODE (op) == SUBREG) | |
981 | { | |
982 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
983 | because it is guaranteed to be reloaded into one. | |
984 | Just make sure the MEM is valid in itself. | |
985 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
986 | but currently it does result from (SUBREG (REG)...) where the | |
987 | reg went on the stack.) */ | |
988 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
989 | return general_operand (op, mode); | |
990 | op = SUBREG_REG (op); | |
991 | } | |
992 | ||
993 | /* We don't consider registers whose class is NO_REGS | |
994 | to be a register operand. */ | |
995 | return (GET_CODE (op) == REG | |
996 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
997 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
998 | } | |
999 | ||
1000 | /* Return 1 if OP is a valid operand that stands for pushing a | |
1001 | value of mode MODE onto the stack. | |
1002 | ||
1003 | The main use of this function is as a predicate in match_operand | |
1004 | expressions in the machine description. */ | |
1005 | ||
1006 | int | |
1007 | push_operand (op, mode) | |
1008 | rtx op; | |
1009 | enum machine_mode mode; | |
1010 | { | |
1011 | if (GET_CODE (op) != MEM) | |
1012 | return 0; | |
1013 | ||
1014 | if (GET_MODE (op) != mode) | |
1015 | return 0; | |
1016 | ||
1017 | op = XEXP (op, 0); | |
1018 | ||
1019 | if (GET_CODE (op) != STACK_PUSH_CODE) | |
1020 | return 0; | |
1021 | ||
1022 | return XEXP (op, 0) == stack_pointer_rtx; | |
1023 | } | |
1024 | ||
1025 | /* Return 1 if ADDR is a valid memory address for mode MODE. */ | |
1026 | ||
1027 | int | |
1028 | memory_address_p (mode, addr) | |
1029 | enum machine_mode mode; | |
1030 | register rtx addr; | |
1031 | { | |
1032 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
1033 | return 0; | |
1034 | ||
1035 | win: | |
1036 | return 1; | |
1037 | } | |
1038 | ||
1039 | /* Return 1 if OP is a valid memory reference with mode MODE, | |
1040 | including a valid address. | |
1041 | ||
1042 | The main use of this function is as a predicate in match_operand | |
1043 | expressions in the machine description. */ | |
1044 | ||
1045 | int | |
1046 | memory_operand (op, mode) | |
1047 | register rtx op; | |
1048 | enum machine_mode mode; | |
1049 | { | |
1050 | rtx inner; | |
1051 | ||
1052 | if (! reload_completed) | |
1053 | /* Note that no SUBREG is a memory operand before end of reload pass, | |
1054 | because (SUBREG (MEM...)) forces reloading into a register. */ | |
1055 | return GET_CODE (op) == MEM && general_operand (op, mode); | |
1056 | ||
1057 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1058 | return 0; | |
1059 | ||
1060 | inner = op; | |
1061 | if (GET_CODE (inner) == SUBREG) | |
1062 | inner = SUBREG_REG (inner); | |
1063 | ||
1064 | return (GET_CODE (inner) == MEM && general_operand (op, mode)); | |
1065 | } | |
1066 | ||
1067 | /* Return 1 if OP is a valid indirect memory reference with mode MODE; | |
1068 | that is, a memory reference whose address is a general_operand. */ | |
1069 | ||
1070 | int | |
1071 | indirect_operand (op, mode) | |
1072 | register rtx op; | |
1073 | enum machine_mode mode; | |
1074 | { | |
1075 | /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ | |
1076 | if (! reload_completed | |
1077 | && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) | |
1078 | { | |
1079 | register int offset = SUBREG_WORD (op) * UNITS_PER_WORD; | |
1080 | rtx inner = SUBREG_REG (op); | |
1081 | ||
1082 | #if BYTES_BIG_ENDIAN | |
1083 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op))) | |
1084 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner)))); | |
1085 | #endif | |
1086 | ||
1087 | /* The only way that we can have a general_operand as the resulting | |
1088 | address is if OFFSET is zero and the address already is an operand | |
1089 | or if the address is (plus Y (const_int -OFFSET)) and Y is an | |
1090 | operand. */ | |
1091 | ||
1092 | return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode)) | |
1093 | || (GET_CODE (XEXP (inner, 0)) == PLUS | |
1094 | && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT | |
1095 | && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset | |
1096 | && general_operand (XEXP (XEXP (inner, 0), 0), Pmode))); | |
1097 | } | |
1098 | ||
1099 | return (GET_CODE (op) == MEM | |
1100 | && memory_operand (op, mode) | |
1101 | && general_operand (XEXP (op, 0), Pmode)); | |
1102 | } | |
1103 | ||
1104 | /* Return 1 if this is a comparison operator. This allows the use of | |
1105 | MATCH_OPERATOR to recognize all the branch insns. */ | |
1106 | ||
1107 | int | |
1108 | comparison_operator (op, mode) | |
1109 | register rtx op; | |
1110 | enum machine_mode mode; | |
1111 | { | |
1112 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
1113 | && GET_RTX_CLASS (GET_CODE (op)) == '<'); | |
1114 | } | |
1115 | \f | |
1116 | /* If BODY is an insn body that uses ASM_OPERANDS, | |
1117 | return the number of operands (both input and output) in the insn. | |
1118 | Otherwise return -1. */ | |
1119 | ||
1120 | int | |
1121 | asm_noperands (body) | |
1122 | rtx body; | |
1123 | { | |
1124 | if (GET_CODE (body) == ASM_OPERANDS) | |
1125 | /* No output operands: return number of input operands. */ | |
1126 | return ASM_OPERANDS_INPUT_LENGTH (body); | |
1127 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1128 | /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ | |
1129 | return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; | |
1130 | else if (GET_CODE (body) == PARALLEL | |
1131 | && GET_CODE (XVECEXP (body, 0, 0)) == SET | |
1132 | && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) | |
1133 | { | |
1134 | /* Multiple output operands, or 1 output plus some clobbers: | |
1135 | body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ | |
1136 | int i; | |
1137 | int n_sets; | |
1138 | ||
1139 | /* Count backwards through CLOBBERs to determine number of SETs. */ | |
1140 | for (i = XVECLEN (body, 0); i > 0; i--) | |
1141 | { | |
1142 | if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) | |
1143 | break; | |
1144 | if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) | |
1145 | return -1; | |
1146 | } | |
1147 | ||
1148 | /* N_SETS is now number of output operands. */ | |
1149 | n_sets = i; | |
1150 | ||
1151 | /* Verify that all the SETs we have | |
1152 | came from a single original asm_operands insn | |
1153 | (so that invalid combinations are blocked). */ | |
1154 | for (i = 0; i < n_sets; i++) | |
1155 | { | |
1156 | rtx elt = XVECEXP (body, 0, i); | |
1157 | if (GET_CODE (elt) != SET) | |
1158 | return -1; | |
1159 | if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) | |
1160 | return -1; | |
1161 | /* If these ASM_OPERANDS rtx's came from different original insns | |
1162 | then they aren't allowed together. */ | |
1163 | if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) | |
1164 | != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) | |
1165 | return -1; | |
1166 | } | |
1167 | return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) | |
1168 | + n_sets); | |
1169 | } | |
1170 | else if (GET_CODE (body) == PARALLEL | |
1171 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1172 | { | |
1173 | /* 0 outputs, but some clobbers: | |
1174 | body is [(asm_operands ...) (clobber (reg ...))...]. */ | |
1175 | int i; | |
1176 | ||
1177 | /* Make sure all the other parallel things really are clobbers. */ | |
1178 | for (i = XVECLEN (body, 0) - 1; i > 0; i--) | |
1179 | if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) | |
1180 | return -1; | |
1181 | ||
1182 | return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); | |
1183 | } | |
1184 | else | |
1185 | return -1; | |
1186 | } | |
1187 | ||
1188 | /* Assuming BODY is an insn body that uses ASM_OPERANDS, | |
1189 | copy its operands (both input and output) into the vector OPERANDS, | |
1190 | the locations of the operands within the insn into the vector OPERAND_LOCS, | |
1191 | and the constraints for the operands into CONSTRAINTS. | |
1192 | Write the modes of the operands into MODES. | |
1193 | Return the assembler-template. | |
1194 | ||
1195 | If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, | |
1196 | we don't store that info. */ | |
1197 | ||
1198 | char * | |
1199 | decode_asm_operands (body, operands, operand_locs, constraints, modes) | |
1200 | rtx body; | |
1201 | rtx *operands; | |
1202 | rtx **operand_locs; | |
1203 | char **constraints; | |
1204 | enum machine_mode *modes; | |
1205 | { | |
1206 | register int i; | |
1207 | int noperands; | |
1208 | char *template = 0; | |
1209 | ||
1210 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1211 | { | |
1212 | rtx asmop = SET_SRC (body); | |
1213 | /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */ | |
1214 | ||
1215 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1; | |
1216 | ||
1217 | for (i = 1; i < noperands; i++) | |
1218 | { | |
1219 | if (operand_locs) | |
1220 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1); | |
1221 | if (operands) | |
1222 | operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1); | |
1223 | if (constraints) | |
1224 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1); | |
1225 | if (modes) | |
1226 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1); | |
1227 | } | |
1228 | ||
1229 | /* The output is in the SET. | |
1230 | Its constraint is in the ASM_OPERANDS itself. */ | |
1231 | if (operands) | |
1232 | operands[0] = SET_DEST (body); | |
1233 | if (operand_locs) | |
1234 | operand_locs[0] = &SET_DEST (body); | |
1235 | if (constraints) | |
1236 | constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); | |
1237 | if (modes) | |
1238 | modes[0] = GET_MODE (SET_DEST (body)); | |
1239 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1240 | } | |
1241 | else if (GET_CODE (body) == ASM_OPERANDS) | |
1242 | { | |
1243 | rtx asmop = body; | |
1244 | /* No output operands: BODY is (asm_operands ....). */ | |
1245 | ||
1246 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1247 | ||
1248 | /* The input operands are found in the 1st element vector. */ | |
1249 | /* Constraints for inputs are in the 2nd element vector. */ | |
1250 | for (i = 0; i < noperands; i++) | |
1251 | { | |
1252 | if (operand_locs) | |
1253 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1254 | if (operands) | |
1255 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1256 | if (constraints) | |
1257 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1258 | if (modes) | |
1259 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1260 | } | |
1261 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1262 | } | |
1263 | else if (GET_CODE (body) == PARALLEL | |
1264 | && GET_CODE (XVECEXP (body, 0, 0)) == SET) | |
1265 | { | |
1266 | rtx asmop = SET_SRC (XVECEXP (body, 0, 0)); | |
1267 | int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ | |
1268 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1269 | int nout = 0; /* Does not include CLOBBERs. */ | |
1270 | ||
1271 | /* At least one output, plus some CLOBBERs. */ | |
1272 | ||
1273 | /* The outputs are in the SETs. | |
1274 | Their constraints are in the ASM_OPERANDS itself. */ | |
1275 | for (i = 0; i < nparallel; i++) | |
1276 | { | |
1277 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
1278 | break; /* Past last SET */ | |
1279 | ||
1280 | if (operands) | |
1281 | operands[i] = SET_DEST (XVECEXP (body, 0, i)); | |
1282 | if (operand_locs) | |
1283 | operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); | |
1284 | if (constraints) | |
1285 | constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); | |
1286 | if (modes) | |
1287 | modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); | |
1288 | nout++; | |
1289 | } | |
1290 | ||
1291 | for (i = 0; i < nin; i++) | |
1292 | { | |
1293 | if (operand_locs) | |
1294 | operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i); | |
1295 | if (operands) | |
1296 | operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i); | |
1297 | if (constraints) | |
1298 | constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1299 | if (modes) | |
1300 | modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1301 | } | |
1302 | ||
1303 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1304 | } | |
1305 | else if (GET_CODE (body) == PARALLEL | |
1306 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1307 | { | |
1308 | /* No outputs, but some CLOBBERs. */ | |
1309 | ||
1310 | rtx asmop = XVECEXP (body, 0, 0); | |
1311 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1312 | ||
1313 | for (i = 0; i < nin; i++) | |
1314 | { | |
1315 | if (operand_locs) | |
1316 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1317 | if (operands) | |
1318 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1319 | if (constraints) | |
1320 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1321 | if (modes) | |
1322 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1323 | } | |
1324 | ||
1325 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1326 | } | |
1327 | ||
1328 | return template; | |
1329 | } | |
1330 | \f | |
1331 | extern rtx plus_constant_for_output (); | |
1332 | extern rtx copy_rtx (); | |
1333 | ||
1334 | /* Given an rtx *P, if it is a sum containing an integer constant term, | |
1335 | return the location (type rtx *) of the pointer to that constant term. | |
1336 | Otherwise, return a null pointer. */ | |
1337 | ||
1338 | static rtx * | |
1339 | find_constant_term_loc (p) | |
1340 | rtx *p; | |
1341 | { | |
1342 | register rtx *tem; | |
1343 | register enum rtx_code code = GET_CODE (*p); | |
1344 | ||
1345 | /* If *P IS such a constant term, P is its location. */ | |
1346 | ||
1347 | if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF | |
1348 | || code == CONST) | |
1349 | return p; | |
1350 | ||
1351 | /* Otherwise, if not a sum, it has no constant term. */ | |
1352 | ||
1353 | if (GET_CODE (*p) != PLUS) | |
1354 | return 0; | |
1355 | ||
1356 | /* If one of the summands is constant, return its location. */ | |
1357 | ||
1358 | if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) | |
1359 | && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) | |
1360 | return p; | |
1361 | ||
1362 | /* Otherwise, check each summand for containing a constant term. */ | |
1363 | ||
1364 | if (XEXP (*p, 0) != 0) | |
1365 | { | |
1366 | tem = find_constant_term_loc (&XEXP (*p, 0)); | |
1367 | if (tem != 0) | |
1368 | return tem; | |
1369 | } | |
1370 | ||
1371 | if (XEXP (*p, 1) != 0) | |
1372 | { | |
1373 | tem = find_constant_term_loc (&XEXP (*p, 1)); | |
1374 | if (tem != 0) | |
1375 | return tem; | |
1376 | } | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | \f | |
1381 | /* Return 1 if OP is a memory reference | |
1382 | whose address contains no side effects | |
1383 | and remains valid after the addition | |
1384 | of a positive integer less than the | |
1385 | size of the object being referenced. | |
1386 | ||
1387 | We assume that the original address is valid and do not check it. | |
1388 | ||
1389 | This uses strict_memory_address_p as a subroutine, so | |
1390 | don't use it before reload. */ | |
1391 | ||
1392 | int | |
1393 | offsettable_memref_p (op) | |
1394 | rtx op; | |
1395 | { | |
1396 | return ((GET_CODE (op) == MEM) | |
1397 | && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); | |
1398 | } | |
1399 | ||
1400 | /* Similar, but don't require a strictly valid mem ref: | |
1401 | consider pseudo-regs valid as index or base regs. */ | |
1402 | ||
1403 | int | |
1404 | offsettable_nonstrict_memref_p (op) | |
1405 | rtx op; | |
1406 | { | |
1407 | return ((GET_CODE (op) == MEM) | |
1408 | && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); | |
1409 | } | |
1410 | ||
1411 | /* Return 1 if Y is a memory address which contains no side effects | |
1412 | and would remain valid after the addition of a positive integer | |
1413 | less than the size of that mode. | |
1414 | ||
1415 | We assume that the original address is valid and do not check it. | |
1416 | We do check that it is valid for narrower modes. | |
1417 | ||
1418 | If STRICTP is nonzero, we require a strictly valid address, | |
1419 | for the sake of use in reload.c. */ | |
1420 | ||
1421 | int | |
1422 | offsettable_address_p (strictp, mode, y) | |
1423 | int strictp; | |
1424 | enum machine_mode mode; | |
1425 | register rtx y; | |
1426 | { | |
1427 | register enum rtx_code ycode = GET_CODE (y); | |
1428 | register rtx z; | |
1429 | rtx y1 = y; | |
1430 | rtx *y2; | |
1431 | int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p); | |
1432 | ||
1433 | if (CONSTANT_ADDRESS_P (y)) | |
1434 | return 1; | |
1435 | ||
1436 | /* Adjusting an offsettable address involves changing to a narrower mode. | |
1437 | Make sure that's OK. */ | |
1438 | ||
1439 | if (mode_dependent_address_p (y)) | |
1440 | return 0; | |
1441 | ||
1442 | /* If the expression contains a constant term, | |
1443 | see if it remains valid when max possible offset is added. */ | |
1444 | ||
1445 | if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) | |
1446 | { | |
1447 | int good; | |
1448 | ||
1449 | y1 = *y2; | |
1450 | *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1); | |
1451 | /* Use QImode because an odd displacement may be automatically invalid | |
1452 | for any wider mode. But it should be valid for a single byte. */ | |
1453 | good = (*addressp) (QImode, y); | |
1454 | ||
1455 | /* In any case, restore old contents of memory. */ | |
1456 | *y2 = y1; | |
1457 | return good; | |
1458 | } | |
1459 | ||
1460 | if (ycode == PRE_DEC || ycode == PRE_INC | |
1461 | || ycode == POST_DEC || ycode == POST_INC) | |
1462 | return 0; | |
1463 | ||
1464 | /* The offset added here is chosen as the maximum offset that | |
1465 | any instruction could need to add when operating on something | |
1466 | of the specified mode. We assume that if Y and Y+c are | |
1467 | valid addresses then so is Y+d for all 0<d<c. */ | |
1468 | ||
1469 | z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1); | |
1470 | ||
1471 | /* Use QImode because an odd displacement may be automatically invalid | |
1472 | for any wider mode. But it should be valid for a single byte. */ | |
1473 | return (*addressp) (QImode, z); | |
1474 | } | |
1475 | ||
1476 | /* Return 1 if ADDR is an address-expression whose effect depends | |
1477 | on the mode of the memory reference it is used in. | |
1478 | ||
1479 | Autoincrement addressing is a typical example of mode-dependence | |
1480 | because the amount of the increment depends on the mode. */ | |
1481 | ||
1482 | int | |
1483 | mode_dependent_address_p (addr) | |
1484 | rtx addr; | |
1485 | { | |
1486 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, win); | |
1487 | return 0; | |
1488 | win: | |
1489 | return 1; | |
1490 | } | |
1491 | ||
1492 | /* Return 1 if OP is a general operand | |
1493 | other than a memory ref with a mode dependent address. */ | |
1494 | ||
1495 | int | |
1496 | mode_independent_operand (op, mode) | |
1497 | enum machine_mode mode; | |
1498 | rtx op; | |
1499 | { | |
1500 | rtx addr; | |
1501 | ||
1502 | if (! general_operand (op, mode)) | |
1503 | return 0; | |
1504 | ||
1505 | if (GET_CODE (op) != MEM) | |
1506 | return 1; | |
1507 | ||
1508 | addr = XEXP (op, 0); | |
1509 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose); | |
1510 | return 1; | |
1511 | lose: | |
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | /* Given an operand OP that is a valid memory reference | |
1516 | which satisfies offsettable_memref_p, | |
1517 | return a new memory reference whose address has been adjusted by OFFSET. | |
1518 | OFFSET should be positive and less than the size of the object referenced. | |
1519 | */ | |
1520 | ||
1521 | rtx | |
1522 | adj_offsettable_operand (op, offset) | |
1523 | rtx op; | |
1524 | int offset; | |
1525 | { | |
1526 | register enum rtx_code code = GET_CODE (op); | |
1527 | ||
1528 | if (code == MEM) | |
1529 | { | |
1530 | register rtx y = XEXP (op, 0); | |
1531 | register rtx new; | |
1532 | ||
1533 | if (CONSTANT_ADDRESS_P (y)) | |
1534 | { | |
1535 | new = gen_rtx (MEM, GET_MODE (op), plus_constant_for_output (y, offset)); | |
1536 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); | |
1537 | return new; | |
1538 | } | |
1539 | ||
1540 | if (GET_CODE (y) == PLUS) | |
1541 | { | |
1542 | rtx z = y; | |
1543 | register rtx *const_loc; | |
1544 | ||
1545 | op = copy_rtx (op); | |
1546 | z = XEXP (op, 0); | |
1547 | const_loc = find_constant_term_loc (&z); | |
1548 | if (const_loc) | |
1549 | { | |
1550 | *const_loc = plus_constant_for_output (*const_loc, offset); | |
1551 | return op; | |
1552 | } | |
1553 | } | |
1554 | ||
1555 | new = gen_rtx (MEM, GET_MODE (op), plus_constant_for_output (y, offset)); | |
1556 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); | |
1557 | return new; | |
1558 | } | |
1559 | abort (); | |
1560 | } | |
1561 | \f | |
1562 | #ifdef REGISTER_CONSTRAINTS | |
1563 | ||
1564 | /* Check the operands of an insn (found in recog_operands) | |
1565 | against the insn's operand constraints (found via INSN_CODE_NUM) | |
1566 | and return 1 if they are valid. | |
1567 | ||
1568 | WHICH_ALTERNATIVE is set to a number which indicates which | |
1569 | alternative of constraints was matched: 0 for the first alternative, | |
1570 | 1 for the next, etc. | |
1571 | ||
1572 | In addition, when two operands are match | |
1573 | and it happens that the output operand is (reg) while the | |
1574 | input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), | |
1575 | make the output operand look like the input. | |
1576 | This is because the output operand is the one the template will print. | |
1577 | ||
1578 | This is used in final, just before printing the assembler code and by | |
1579 | the routines that determine an insn's attribute. | |
1580 | ||
1581 | If STRICT is a positive non-zero value, it means that we have been | |
1582 | called after reload has been completed. In that case, we must | |
1583 | do all checks strictly. If it is zero, it means that we have been called | |
1584 | before reload has completed. In that case, we first try to see if we can | |
1585 | find an alternative that matches strictly. If not, we try again, this | |
1586 | time assuming that reload will fix up the insn. This provides a "best | |
1587 | guess" for the alternative and is used to compute attributes of insns prior | |
1588 | to reload. A negative value of STRICT is used for this internal call. */ | |
1589 | ||
1590 | struct funny_match | |
1591 | { | |
1592 | int this, other; | |
1593 | }; | |
1594 | ||
1595 | int | |
1596 | constrain_operands (insn_code_num, strict) | |
1597 | int insn_code_num; | |
1598 | int strict; | |
1599 | { | |
1600 | char *constraints[MAX_RECOG_OPERANDS]; | |
1601 | register int c; | |
1602 | int noperands = insn_n_operands[insn_code_num]; | |
1603 | ||
1604 | struct funny_match funny_match[MAX_RECOG_OPERANDS]; | |
1605 | int funny_match_index; | |
1606 | int nalternatives = insn_n_alternatives[insn_code_num]; | |
1607 | ||
1608 | if (noperands == 0 || nalternatives == 0) | |
1609 | return 1; | |
1610 | ||
1611 | for (c = 0; c < noperands; c++) | |
1612 | constraints[c] = insn_operand_constraint[insn_code_num][c]; | |
1613 | ||
1614 | which_alternative = 0; | |
1615 | ||
1616 | while (which_alternative < nalternatives) | |
1617 | { | |
1618 | register int opno; | |
1619 | int lose = 0; | |
1620 | funny_match_index = 0; | |
1621 | ||
1622 | for (opno = 0; opno < noperands; opno++) | |
1623 | { | |
1624 | register rtx op = recog_operand[opno]; | |
1625 | enum machine_mode mode = GET_MODE (op); | |
1626 | register char *p = constraints[opno]; | |
1627 | int offset = 0; | |
1628 | int win = 0; | |
1629 | int val; | |
1630 | ||
1631 | if (GET_CODE (op) == SUBREG) | |
1632 | { | |
1633 | if (GET_CODE (SUBREG_REG (op)) == REG | |
1634 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) | |
1635 | offset = SUBREG_WORD (op); | |
1636 | op = SUBREG_REG (op); | |
1637 | } | |
1638 | ||
1639 | /* An empty constraint or empty alternative | |
1640 | allows anything which matched the pattern. */ | |
1641 | if (*p == 0 || *p == ',') | |
1642 | win = 1; | |
1643 | ||
1644 | while (*p && (c = *p++) != ',') | |
1645 | switch (c) | |
1646 | { | |
1647 | case '=': | |
1648 | case '+': | |
1649 | case '?': | |
1650 | case '#': | |
1651 | case '&': | |
1652 | case '!': | |
1653 | case '*': | |
1654 | case '%': | |
1655 | break; | |
1656 | ||
1657 | case '0': | |
1658 | case '1': | |
1659 | case '2': | |
1660 | case '3': | |
1661 | case '4': | |
1662 | /* This operand must be the same as a previous one. | |
1663 | This kind of constraint is used for instructions such | |
1664 | as add when they take only two operands. | |
1665 | ||
1666 | Note that the lower-numbered operand is passed first. | |
1667 | ||
1668 | If we are not testing strictly, assume that this constraint | |
1669 | will be satisfied. */ | |
1670 | if (strict < 0) | |
1671 | val = 1; | |
1672 | else | |
1673 | val = operands_match_p (recog_operand[c - '0'], | |
1674 | recog_operand[opno]); | |
1675 | ||
1676 | if (val != 0) | |
1677 | win = 1; | |
1678 | /* If output is *x and input is *--x, | |
1679 | arrange later to change the output to *--x as well, | |
1680 | since the output op is the one that will be printed. */ | |
1681 | if (val == 2 && strict > 0) | |
1682 | { | |
1683 | funny_match[funny_match_index].this = opno; | |
1684 | funny_match[funny_match_index++].other = c - '0'; | |
1685 | } | |
1686 | break; | |
1687 | ||
1688 | case 'p': | |
1689 | /* p is used for address_operands. When we are called by | |
1690 | gen_input_reload, no one will have checked that the | |
1691 | address is strictly valid, i.e., that all pseudos | |
1692 | requiring hard regs have gotten them. */ | |
1693 | if (strict <= 0 | |
1694 | || (strict_memory_address_p | |
1695 | (insn_operand_mode[insn_code_num][opno], op))) | |
1696 | win = 1; | |
1697 | break; | |
1698 | ||
1699 | /* No need to check general_operand again; | |
1700 | it was done in insn-recog.c. */ | |
1701 | case 'g': | |
1702 | /* Anything goes unless it is a REG and really has a hard reg | |
1703 | but the hard reg is not in the class GENERAL_REGS. */ | |
1704 | if (strict < 0 | |
1705 | || GENERAL_REGS == ALL_REGS | |
1706 | || GET_CODE (op) != REG | |
1707 | || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) | |
1708 | win = 1; | |
1709 | break; | |
1710 | ||
1711 | case 'r': | |
1712 | if (strict < 0 | |
1713 | || (strict == 0 | |
1714 | && GET_CODE (op) == REG | |
1715 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1716 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
1717 | || (GET_CODE (op) == REG | |
1718 | && (GENERAL_REGS == ALL_REGS | |
1719 | || reg_fits_class_p (op, GENERAL_REGS, | |
1720 | offset, mode)))) | |
1721 | win = 1; | |
1722 | break; | |
1723 | ||
1724 | case 'X': | |
1725 | /* This is used for a MATCH_SCRATCH in the cases when we | |
1726 | don't actually need anything. So anything goes any time. */ | |
1727 | win = 1; | |
1728 | break; | |
1729 | ||
1730 | case 'm': | |
1731 | if (GET_CODE (op) == MEM | |
1732 | /* Before reload, accept what reload can turn into mem. */ | |
1733 | || (strict < 0 && CONSTANT_P (op))) | |
1734 | win = 1; | |
1735 | break; | |
1736 | ||
1737 | case '<': | |
1738 | if (GET_CODE (op) == MEM | |
1739 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1740 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1741 | win = 1; | |
1742 | break; | |
1743 | ||
1744 | case '>': | |
1745 | if (GET_CODE (op) == MEM | |
1746 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1747 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1748 | win = 1; | |
1749 | break; | |
1750 | ||
1751 | case 'E': | |
1752 | /* Match any CONST_DOUBLE, but only if | |
1753 | we can examine the bits of it reliably. */ | |
1754 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
1755 | || HOST_BITS_PER_INT != BITS_PER_WORD) | |
1756 | && GET_CODE (op) != VOIDmode && ! flag_pretend_float) | |
1757 | break; | |
1758 | if (GET_CODE (op) == CONST_DOUBLE) | |
1759 | win = 1; | |
1760 | break; | |
1761 | ||
1762 | case 'F': | |
1763 | if (GET_CODE (op) == CONST_DOUBLE) | |
1764 | win = 1; | |
1765 | break; | |
1766 | ||
1767 | case 'G': | |
1768 | case 'H': | |
1769 | if (GET_CODE (op) == CONST_DOUBLE | |
1770 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1771 | win = 1; | |
1772 | break; | |
1773 | ||
1774 | case 's': | |
1775 | if (GET_CODE (op) == CONST_INT | |
1776 | || (GET_CODE (op) == CONST_DOUBLE | |
1777 | && GET_MODE (op) == VOIDmode)) | |
1778 | break; | |
1779 | case 'i': | |
1780 | if (CONSTANT_P (op)) | |
1781 | win = 1; | |
1782 | break; | |
1783 | ||
1784 | case 'n': | |
1785 | if (GET_CODE (op) == CONST_INT | |
1786 | || (GET_CODE (op) == CONST_DOUBLE | |
1787 | && GET_MODE (op) == VOIDmode)) | |
1788 | win = 1; | |
1789 | break; | |
1790 | ||
1791 | case 'I': | |
1792 | case 'J': | |
1793 | case 'K': | |
1794 | case 'L': | |
1795 | case 'M': | |
1796 | case 'N': | |
1797 | case 'O': | |
1798 | case 'P': | |
1799 | if (GET_CODE (op) == CONST_INT | |
1800 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1801 | win = 1; | |
1802 | break; | |
1803 | ||
1804 | #ifdef EXTRA_CONSTRAINT | |
1805 | case 'Q': | |
1806 | case 'R': | |
1807 | case 'S': | |
1808 | case 'T': | |
1809 | case 'U': | |
1810 | if (EXTRA_CONSTRAINT (op, c)) | |
1811 | win = 1; | |
1812 | break; | |
1813 | #endif | |
1814 | ||
1815 | case 'V': | |
1816 | if (GET_CODE (op) == MEM | |
1817 | && ! offsettable_memref_p (op)) | |
1818 | win = 1; | |
1819 | break; | |
1820 | ||
1821 | case 'o': | |
1822 | if ((strict > 0 && offsettable_memref_p (op)) | |
1823 | || (strict == 0 && offsettable_nonstrict_memref_p (op)) | |
1824 | /* Before reload, accept what reload can handle. */ | |
1825 | || (strict < 0 | |
1826 | && (CONSTANT_P (op) || GET_CODE (op) == MEM))) | |
1827 | win = 1; | |
1828 | break; | |
1829 | ||
1830 | default: | |
1831 | if (strict < 0 | |
1832 | || (strict == 0 | |
1833 | && GET_CODE (op) == REG | |
1834 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1835 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
1836 | || (GET_CODE (op) == REG | |
1837 | && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c), | |
1838 | offset, mode))) | |
1839 | win = 1; | |
1840 | } | |
1841 | ||
1842 | constraints[opno] = p; | |
1843 | /* If this operand did not win somehow, | |
1844 | this alternative loses. */ | |
1845 | if (! win) | |
1846 | lose = 1; | |
1847 | } | |
1848 | /* This alternative won; the operands are ok. | |
1849 | Change whichever operands this alternative says to change. */ | |
1850 | if (! lose) | |
1851 | { | |
1852 | while (--funny_match_index >= 0) | |
1853 | { | |
1854 | recog_operand[funny_match[funny_match_index].other] | |
1855 | = recog_operand[funny_match[funny_match_index].this]; | |
1856 | } | |
1857 | return 1; | |
1858 | } | |
1859 | ||
1860 | which_alternative++; | |
1861 | } | |
1862 | ||
1863 | /* If we are about to reject this, but we are not to test strictly, | |
1864 | try a very loose test. Only return failure if it fails also. */ | |
1865 | if (strict == 0) | |
1866 | return constrain_operands (insn_code_num, -1); | |
1867 | else | |
1868 | return 0; | |
1869 | } | |
1870 | ||
1871 | /* Return 1 iff OPERAND (assumed to be a REG rtx) | |
1872 | is a hard reg in class CLASS when its regno is offsetted by OFFSET | |
1873 | and changed to mode MODE. | |
1874 | If REG occupies multiple hard regs, all of them must be in CLASS. */ | |
1875 | ||
1876 | int | |
1877 | reg_fits_class_p (operand, class, offset, mode) | |
1878 | rtx operand; | |
1879 | register enum reg_class class; | |
1880 | int offset; | |
1881 | enum machine_mode mode; | |
1882 | { | |
1883 | register int regno = REGNO (operand); | |
1884 | if (regno < FIRST_PSEUDO_REGISTER | |
1885 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1886 | regno + offset)) | |
1887 | { | |
1888 | register int sr; | |
1889 | regno += offset; | |
1890 | for (sr = HARD_REGNO_NREGS (regno, mode) - 1; | |
1891 | sr > 0; sr--) | |
1892 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1893 | regno + sr)) | |
1894 | break; | |
1895 | return sr == 0; | |
1896 | } | |
1897 | ||
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | #endif /* REGISTER_CONSTRAINTS */ |