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15e35479 | 1 | /* Perform simple optimizations to clean up the result of reload. |
818ab71a | 2 | Copyright (C) 1987-2016 Free Software Foundation, Inc. |
15e35479 KH |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
15e35479 KH |
9 | version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
15e35479 KH |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
c7131fb2 | 23 | #include "backend.h" |
957060b5 | 24 | #include "target.h" |
15e35479 | 25 | #include "rtl.h" |
957060b5 AM |
26 | #include "tree.h" |
27 | #include "predict.h" | |
c7131fb2 | 28 | #include "df.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
15e35479 | 30 | #include "tm_p.h" |
957060b5 AM |
31 | #include "optabs.h" |
32 | #include "regs.h" | |
33 | #include "emit-rtl.h" | |
34 | #include "recog.h" | |
957060b5 | 35 | |
60393bbc AM |
36 | #include "cfgrtl.h" |
37 | #include "cfgbuild.h" | |
38 | #include "cfgcleanup.h" | |
15e35479 | 39 | #include "reload.h" |
15e35479 | 40 | #include "cselib.h" |
ef330312 | 41 | #include "tree-pass.h" |
6fb5fa3c | 42 | #include "dbgcnt.h" |
15e35479 | 43 | |
0c20a65f | 44 | static int reload_cse_noop_set_p (rtx); |
f90af2e0 | 45 | static bool reload_cse_simplify (rtx_insn *, rtx); |
3a15c2cf | 46 | static void reload_cse_regs_1 (void); |
f90af2e0 DM |
47 | static int reload_cse_simplify_set (rtx, rtx_insn *); |
48 | static int reload_cse_simplify_operands (rtx_insn *, rtx); | |
15e35479 | 49 | |
0c20a65f | 50 | static void reload_combine (void); |
f90af2e0 | 51 | static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx); |
7bc980e1 | 52 | static void reload_combine_note_store (rtx, const_rtx, void *); |
15e35479 | 53 | |
f90af2e0 | 54 | static bool reload_cse_move2add (rtx_insn *); |
7bc980e1 | 55 | static void move2add_note_store (rtx, const_rtx, void *); |
15e35479 KH |
56 | |
57 | /* Call cse / combine like post-reload optimization phases. | |
58 | FIRST is the first instruction. */ | |
8bb91f49 SB |
59 | |
60 | static void | |
f90af2e0 | 61 | reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED) |
15e35479 | 62 | { |
dc0d5a57 | 63 | bool moves_converted; |
3a15c2cf | 64 | reload_cse_regs_1 (); |
15e35479 | 65 | reload_combine (); |
dc0d5a57 | 66 | moves_converted = reload_cse_move2add (first); |
15e35479 | 67 | if (flag_expensive_optimizations) |
dc0d5a57 BS |
68 | { |
69 | if (moves_converted) | |
70 | reload_combine (); | |
3a15c2cf | 71 | reload_cse_regs_1 (); |
dc0d5a57 | 72 | } |
15e35479 KH |
73 | } |
74 | ||
75 | /* See whether a single set SET is a noop. */ | |
76 | static int | |
0c20a65f | 77 | reload_cse_noop_set_p (rtx set) |
15e35479 KH |
78 | { |
79 | if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) | |
80 | return 0; | |
81 | ||
82 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); | |
83 | } | |
84 | ||
3a15c2cf SB |
85 | /* Try to simplify INSN. Return true if the CFG may have changed. */ |
86 | static bool | |
f90af2e0 | 87 | reload_cse_simplify (rtx_insn *insn, rtx testreg) |
15e35479 KH |
88 | { |
89 | rtx body = PATTERN (insn); | |
3a15c2cf SB |
90 | basic_block insn_bb = BLOCK_FOR_INSN (insn); |
91 | unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs); | |
15e35479 KH |
92 | |
93 | if (GET_CODE (body) == SET) | |
94 | { | |
95 | int count = 0; | |
96 | ||
97 | /* Simplify even if we may think it is a no-op. | |
98 | We may think a memory load of a value smaller than WORD_SIZE | |
99 | is redundant because we haven't taken into account possible | |
100 | implicit extension. reload_cse_simplify_set() will bring | |
101 | this out, so it's safer to simplify before we delete. */ | |
102 | count += reload_cse_simplify_set (body, insn); | |
103 | ||
104 | if (!count && reload_cse_noop_set_p (body)) | |
105 | { | |
9e582b1d JR |
106 | if (check_for_inc_dec (insn)) |
107 | delete_insn_and_edges (insn); | |
3a15c2cf SB |
108 | /* We're done with this insn. */ |
109 | goto done; | |
15e35479 KH |
110 | } |
111 | ||
112 | if (count > 0) | |
113 | apply_change_group (); | |
114 | else | |
115 | reload_cse_simplify_operands (insn, testreg); | |
116 | } | |
117 | else if (GET_CODE (body) == PARALLEL) | |
118 | { | |
119 | int i; | |
120 | int count = 0; | |
121 | rtx value = NULL_RTX; | |
122 | ||
0d87c765 RH |
123 | /* Registers mentioned in the clobber list for an asm cannot be reused |
124 | within the body of the asm. Invalidate those registers now so that | |
125 | we don't try to substitute values for them. */ | |
126 | if (asm_noperands (body) >= 0) | |
127 | { | |
128 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
129 | { | |
130 | rtx part = XVECEXP (body, 0, i); | |
131 | if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) | |
132 | cselib_invalidate_rtx (XEXP (part, 0)); | |
133 | } | |
134 | } | |
135 | ||
15e35479 KH |
136 | /* If every action in a PARALLEL is a noop, we can delete |
137 | the entire PARALLEL. */ | |
138 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
139 | { | |
140 | rtx part = XVECEXP (body, 0, i); | |
141 | if (GET_CODE (part) == SET) | |
142 | { | |
143 | if (! reload_cse_noop_set_p (part)) | |
144 | break; | |
145 | if (REG_P (SET_DEST (part)) | |
146 | && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
147 | { | |
148 | if (value) | |
149 | break; | |
150 | value = SET_DEST (part); | |
151 | } | |
152 | } | |
c6a26179 JH |
153 | else if (GET_CODE (part) != CLOBBER |
154 | && GET_CODE (part) != USE) | |
15e35479 KH |
155 | break; |
156 | } | |
157 | ||
158 | if (i < 0) | |
159 | { | |
9e582b1d JR |
160 | if (check_for_inc_dec (insn)) |
161 | delete_insn_and_edges (insn); | |
15e35479 | 162 | /* We're done with this insn. */ |
3a15c2cf | 163 | goto done; |
15e35479 KH |
164 | } |
165 | ||
166 | /* It's not a no-op, but we can try to simplify it. */ | |
167 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
168 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
169 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
170 | ||
171 | if (count > 0) | |
172 | apply_change_group (); | |
173 | else | |
174 | reload_cse_simplify_operands (insn, testreg); | |
175 | } | |
3a15c2cf SB |
176 | |
177 | done: | |
178 | return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs); | |
15e35479 KH |
179 | } |
180 | ||
181 | /* Do a very simple CSE pass over the hard registers. | |
182 | ||
183 | This function detects no-op moves where we happened to assign two | |
184 | different pseudo-registers to the same hard register, and then | |
185 | copied one to the other. Reload will generate a useless | |
186 | instruction copying a register to itself. | |
187 | ||
188 | This function also detects cases where we load a value from memory | |
189 | into two different registers, and (if memory is more expensive than | |
190 | registers) changes it to simply copy the first register into the | |
191 | second register. | |
192 | ||
193 | Another optimization is performed that scans the operands of each | |
194 | instruction to see whether the value is already available in a | |
195 | hard register. It then replaces the operand with the hard register | |
196 | if possible, much like an optional reload would. */ | |
197 | ||
198 | static void | |
3a15c2cf | 199 | reload_cse_regs_1 (void) |
15e35479 | 200 | { |
3a15c2cf SB |
201 | bool cfg_changed = false; |
202 | basic_block bb; | |
f90af2e0 | 203 | rtx_insn *insn; |
c3dc5e66 | 204 | rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
15e35479 | 205 | |
457eeaae | 206 | cselib_init (CSELIB_RECORD_MEMORY); |
15e35479 KH |
207 | init_alias_analysis (); |
208 | ||
11cd3bed | 209 | FOR_EACH_BB_FN (bb, cfun) |
3a15c2cf SB |
210 | FOR_BB_INSNS (bb, insn) |
211 | { | |
212 | if (INSN_P (insn)) | |
213 | cfg_changed |= reload_cse_simplify (insn, testreg); | |
15e35479 | 214 | |
3a15c2cf SB |
215 | cselib_process_insn (insn); |
216 | } | |
15e35479 KH |
217 | |
218 | /* Clean up. */ | |
219 | end_alias_analysis (); | |
220 | cselib_finish (); | |
3a15c2cf SB |
221 | if (cfg_changed) |
222 | cleanup_cfg (0); | |
15e35479 KH |
223 | } |
224 | ||
225 | /* Try to simplify a single SET instruction. SET is the set pattern. | |
226 | INSN is the instruction it came from. | |
227 | This function only handles one case: if we set a register to a value | |
228 | which is not a register, we try to find that value in some other register | |
229 | and change the set into a register copy. */ | |
230 | ||
231 | static int | |
f90af2e0 | 232 | reload_cse_simplify_set (rtx set, rtx_insn *insn) |
15e35479 KH |
233 | { |
234 | int did_change = 0; | |
235 | int dreg; | |
236 | rtx src; | |
6f76a878 | 237 | reg_class_t dclass; |
15e35479 KH |
238 | int old_cost; |
239 | cselib_val *val; | |
240 | struct elt_loc_list *l; | |
f822d252 | 241 | enum rtx_code extend_op = UNKNOWN; |
f40751dd | 242 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
15e35479 KH |
243 | |
244 | dreg = true_regnum (SET_DEST (set)); | |
245 | if (dreg < 0) | |
246 | return 0; | |
247 | ||
248 | src = SET_SRC (set); | |
249 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
250 | return 0; | |
251 | ||
252 | dclass = REGNO_REG_CLASS (dreg); | |
253 | ||
15e35479 KH |
254 | /* When replacing a memory with a register, we need to honor assumptions |
255 | that combine made wrt the contents of sign bits. We'll do this by | |
256 | generating an extend instruction instead of a reg->reg copy. Thus | |
257 | the destination must be a register that we can widen. */ | |
3c0cb5de | 258 | if (MEM_P (src) |
3712c7a3 | 259 | && (extend_op = load_extend_op (GET_MODE (src))) != UNKNOWN |
f8cfc6aa | 260 | && !REG_P (SET_DEST (set))) |
15e35479 | 261 | return 0; |
15e35479 | 262 | |
4deef538 | 263 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); |
b2948a2c KH |
264 | if (! val) |
265 | return 0; | |
266 | ||
15e35479 | 267 | /* If memory loads are cheaper than register copies, don't change them. */ |
3c0cb5de | 268 | if (MEM_P (src)) |
f5c21ef3 | 269 | old_cost = memory_move_cost (GET_MODE (src), dclass, true); |
f8cfc6aa | 270 | else if (REG_P (src)) |
de8f4b07 | 271 | old_cost = register_move_cost (GET_MODE (src), |
15e35479 KH |
272 | REGNO_REG_CLASS (REGNO (src)), dclass); |
273 | else | |
e548c9df | 274 | old_cost = set_src_cost (src, GET_MODE (SET_DEST (set)), speed); |
15e35479 | 275 | |
15e35479 KH |
276 | for (l = val->locs; l; l = l->next) |
277 | { | |
278 | rtx this_rtx = l->loc; | |
279 | int this_cost; | |
280 | ||
281 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
282 | { | |
f822d252 | 283 | if (extend_op != UNKNOWN) |
15e35479 | 284 | { |
807e902e | 285 | wide_int result; |
15e35479 | 286 | |
807e902e | 287 | if (!CONST_SCALAR_INT_P (this_rtx)) |
15e35479 KH |
288 | continue; |
289 | ||
15e35479 KH |
290 | switch (extend_op) |
291 | { | |
292 | case ZERO_EXTEND: | |
807e902e KZ |
293 | result = wide_int::from (std::make_pair (this_rtx, |
294 | GET_MODE (src)), | |
295 | BITS_PER_WORD, UNSIGNED); | |
15e35479 KH |
296 | break; |
297 | case SIGN_EXTEND: | |
807e902e KZ |
298 | result = wide_int::from (std::make_pair (this_rtx, |
299 | GET_MODE (src)), | |
300 | BITS_PER_WORD, SIGNED); | |
301 | break; | |
15e35479 | 302 | default: |
e16acfcd | 303 | gcc_unreachable (); |
15e35479 | 304 | } |
807e902e | 305 | this_rtx = immed_wide_int_const (result, word_mode); |
15e35479 | 306 | } |
f1657f05 | 307 | |
e548c9df | 308 | this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed); |
15e35479 | 309 | } |
f8cfc6aa | 310 | else if (REG_P (this_rtx)) |
15e35479 | 311 | { |
f822d252 | 312 | if (extend_op != UNKNOWN) |
15e35479 KH |
313 | { |
314 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
e548c9df | 315 | this_cost = set_src_cost (this_rtx, word_mode, speed); |
15e35479 KH |
316 | } |
317 | else | |
de8f4b07 | 318 | this_cost = register_move_cost (GET_MODE (this_rtx), |
15e35479 KH |
319 | REGNO_REG_CLASS (REGNO (this_rtx)), |
320 | dclass); | |
321 | } | |
322 | else | |
323 | continue; | |
324 | ||
325 | /* If equal costs, prefer registers over anything else. That | |
326 | tends to lead to smaller instructions on some machines. */ | |
327 | if (this_cost < old_cost | |
328 | || (this_cost == old_cost | |
f8cfc6aa JQ |
329 | && REG_P (this_rtx) |
330 | && !REG_P (SET_SRC (set)))) | |
15e35479 | 331 | { |
3712c7a3 | 332 | if (extend_op != UNKNOWN |
15e35479 KH |
333 | #ifdef CANNOT_CHANGE_MODE_CLASS |
334 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), | |
335 | word_mode, | |
336 | REGNO_REG_CLASS (REGNO (SET_DEST (set)))) | |
337 | #endif | |
338 | ) | |
339 | { | |
340 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
341 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
342 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
343 | } | |
15e35479 | 344 | |
95e88efd | 345 | validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); |
15e35479 KH |
346 | old_cost = this_cost, did_change = 1; |
347 | } | |
348 | } | |
349 | ||
350 | return did_change; | |
351 | } | |
352 | ||
353 | /* Try to replace operands in INSN with equivalent values that are already | |
354 | in registers. This can be viewed as optional reloading. | |
355 | ||
356 | For each non-register operand in the insn, see if any hard regs are | |
357 | known to be equivalent to that operand. Record the alternatives which | |
358 | can accept these hard registers. Among all alternatives, select the | |
359 | ones which are better or equal to the one currently matching, where | |
360 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
361 | alternatives, select the one which replaces most operands with | |
362 | hard registers. */ | |
363 | ||
364 | static int | |
f90af2e0 | 365 | reload_cse_simplify_operands (rtx_insn *insn, rtx testreg) |
15e35479 KH |
366 | { |
367 | int i, j; | |
368 | ||
369 | /* For each operand, all registers that are equivalent to it. */ | |
370 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
371 | ||
372 | const char *constraints[MAX_RECOG_OPERANDS]; | |
373 | ||
374 | /* Vector recording how bad an alternative is. */ | |
375 | int *alternative_reject; | |
376 | /* Vector recording how many registers can be introduced by choosing | |
377 | this alternative. */ | |
378 | int *alternative_nregs; | |
379 | /* Array of vectors recording, for each operand and each alternative, | |
380 | which hard register to substitute, or -1 if the operand should be | |
381 | left as it is. */ | |
382 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
383 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
384 | int *alternative_order; | |
385 | ||
75d25a02 | 386 | extract_constrain_insn (insn); |
15e35479 KH |
387 | |
388 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) | |
389 | return 0; | |
390 | ||
d3bfe4de KG |
391 | alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); |
392 | alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); | |
393 | alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); | |
703ad42b KG |
394 | memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
395 | memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
15e35479 KH |
396 | |
397 | /* For each operand, find out which regs are equivalent. */ | |
398 | for (i = 0; i < recog_data.n_operands; i++) | |
399 | { | |
400 | cselib_val *v; | |
401 | struct elt_loc_list *l; | |
115df136 | 402 | rtx op; |
15e35479 KH |
403 | |
404 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
405 | ||
406 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
407 | right, so avoid the problem here. Likewise if we have a constant | |
408 | and the insn pattern doesn't tell us the mode we need. */ | |
4b4bf941 | 409 | if (LABEL_P (recog_data.operand[i]) |
15e35479 KH |
410 | || (CONSTANT_P (recog_data.operand[i]) |
411 | && recog_data.operand_mode[i] == VOIDmode)) | |
412 | continue; | |
413 | ||
115df136 | 414 | op = recog_data.operand[i]; |
3712c7a3 | 415 | if (MEM_P (op) && load_extend_op (GET_MODE (op)) != UNKNOWN) |
115df136 R |
416 | { |
417 | rtx set = single_set (insn); | |
418 | ||
1f52178b | 419 | /* We might have multiple sets, some of which do implicit |
115df136 R |
420 | extension. Punt on this for now. */ |
421 | if (! set) | |
422 | continue; | |
1f838355 | 423 | /* If the destination is also a MEM or a STRICT_LOW_PART, no |
115df136 R |
424 | extension applies. |
425 | Also, if there is an explicit extension, we don't have to | |
426 | worry about an implicit one. */ | |
3c0cb5de | 427 | else if (MEM_P (SET_DEST (set)) |
115df136 R |
428 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART |
429 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND | |
430 | || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) | |
431 | ; /* Continue ordinary processing. */ | |
7be4d808 R |
432 | #ifdef CANNOT_CHANGE_MODE_CLASS |
433 | /* If the register cannot change mode to word_mode, it follows that | |
434 | it cannot have been used in word_mode. */ | |
f8cfc6aa | 435 | else if (REG_P (SET_DEST (set)) |
7be4d808 R |
436 | && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), |
437 | word_mode, | |
438 | REGNO_REG_CLASS (REGNO (SET_DEST (set))))) | |
439 | ; /* Continue ordinary processing. */ | |
440 | #endif | |
115df136 | 441 | /* If this is a straight load, make the extension explicit. */ |
f8cfc6aa | 442 | else if (REG_P (SET_DEST (set)) |
115df136 R |
443 | && recog_data.n_operands == 2 |
444 | && SET_SRC (set) == op | |
445 | && SET_DEST (set) == recog_data.operand[1-i]) | |
446 | { | |
447 | validate_change (insn, recog_data.operand_loc[i], | |
3712c7a3 | 448 | gen_rtx_fmt_e (load_extend_op (GET_MODE (op)), |
115df136 R |
449 | word_mode, op), |
450 | 1); | |
451 | validate_change (insn, recog_data.operand_loc[1-i], | |
452 | gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), | |
453 | 1); | |
454 | if (! apply_change_group ()) | |
455 | return 0; | |
456 | return reload_cse_simplify_operands (insn, testreg); | |
457 | } | |
458 | else | |
459 | /* ??? There might be arithmetic operations with memory that are | |
460 | safe to optimize, but is it worth the trouble? */ | |
461 | continue; | |
462 | } | |
f1657f05 | 463 | |
3f82421f PH |
464 | if (side_effects_p (op)) |
465 | continue; | |
4deef538 | 466 | v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); |
15e35479 KH |
467 | if (! v) |
468 | continue; | |
469 | ||
470 | for (l = v->locs; l; l = l->next) | |
f8cfc6aa | 471 | if (REG_P (l->loc)) |
15e35479 KH |
472 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); |
473 | } | |
474 | ||
9840b2fa | 475 | alternative_mask preferred = get_preferred_alternatives (insn); |
15e35479 KH |
476 | for (i = 0; i < recog_data.n_operands; i++) |
477 | { | |
ef4bddc2 | 478 | machine_mode mode; |
15e35479 KH |
479 | int regno; |
480 | const char *p; | |
481 | ||
d3bfe4de | 482 | op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); |
15e35479 KH |
483 | for (j = 0; j < recog_data.n_alternatives; j++) |
484 | op_alt_regno[i][j] = -1; | |
485 | ||
486 | p = constraints[i] = recog_data.constraints[i]; | |
487 | mode = recog_data.operand_mode[i]; | |
488 | ||
489 | /* Add the reject values for each alternative given by the constraints | |
490 | for this operand. */ | |
491 | j = 0; | |
492 | while (*p != '\0') | |
493 | { | |
494 | char c = *p++; | |
495 | if (c == ',') | |
496 | j++; | |
497 | else if (c == '?') | |
498 | alternative_reject[j] += 3; | |
499 | else if (c == '!') | |
500 | alternative_reject[j] += 300; | |
501 | } | |
502 | ||
503 | /* We won't change operands which are already registers. We | |
504 | also don't want to modify output operands. */ | |
505 | regno = true_regnum (recog_data.operand[i]); | |
506 | if (regno >= 0 | |
507 | || constraints[i][0] == '=' | |
508 | || constraints[i][0] == '+') | |
509 | continue; | |
510 | ||
511 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
512 | { | |
bbbbb16a | 513 | enum reg_class rclass = NO_REGS; |
15e35479 KH |
514 | |
515 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) | |
516 | continue; | |
517 | ||
8deccbb7 | 518 | set_mode_and_regno (testreg, mode, regno); |
15e35479 KH |
519 | |
520 | /* We found a register equal to this operand. Now look for all | |
521 | alternatives that can accept this register and have not been | |
522 | assigned a register they can use yet. */ | |
523 | j = 0; | |
524 | p = constraints[i]; | |
525 | for (;;) | |
526 | { | |
527 | char c = *p; | |
528 | ||
529 | switch (c) | |
530 | { | |
8677664e RS |
531 | case 'g': |
532 | rclass = reg_class_subunion[rclass][GENERAL_REGS]; | |
15e35479 KH |
533 | break; |
534 | ||
535 | default: | |
d858f359 | 536 | rclass |
15e35479 | 537 | = (reg_class_subunion |
777e635f RS |
538 | [rclass] |
539 | [reg_class_for_constraint (lookup_constraint (p))]); | |
15e35479 KH |
540 | break; |
541 | ||
542 | case ',': case '\0': | |
543 | /* See if REGNO fits this alternative, and set it up as the | |
544 | replacement register if we don't have one for this | |
545 | alternative yet and the operand being replaced is not | |
546 | a cheap CONST_INT. */ | |
547 | if (op_alt_regno[i][j] == -1 | |
9840b2fa | 548 | && TEST_BIT (preferred, j) |
d858f359 | 549 | && reg_fits_class_p (testreg, rclass, 0, mode) |
481683e1 | 550 | && (!CONST_INT_P (recog_data.operand[i]) |
e548c9df | 551 | || (set_src_cost (recog_data.operand[i], mode, |
5e8f01f4 RS |
552 | optimize_bb_for_speed_p |
553 | (BLOCK_FOR_INSN (insn))) | |
e548c9df | 554 | > set_src_cost (testreg, mode, |
5e8f01f4 RS |
555 | optimize_bb_for_speed_p |
556 | (BLOCK_FOR_INSN (insn)))))) | |
15e35479 KH |
557 | { |
558 | alternative_nregs[j]++; | |
559 | op_alt_regno[i][j] = regno; | |
560 | } | |
561 | j++; | |
bbbbb16a | 562 | rclass = NO_REGS; |
15e35479 KH |
563 | break; |
564 | } | |
565 | p += CONSTRAINT_LEN (c, p); | |
566 | ||
567 | if (c == '\0') | |
568 | break; | |
569 | } | |
570 | } | |
571 | } | |
572 | ||
573 | /* Record all alternatives which are better or equal to the currently | |
574 | matching one in the alternative_order array. */ | |
575 | for (i = j = 0; i < recog_data.n_alternatives; i++) | |
576 | if (alternative_reject[i] <= alternative_reject[which_alternative]) | |
577 | alternative_order[j++] = i; | |
578 | recog_data.n_alternatives = j; | |
579 | ||
580 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
581 | won't hurt too much. */ | |
582 | for (i = 0; i < recog_data.n_alternatives - 1; i++) | |
583 | { | |
584 | int best = i; | |
585 | int best_reject = alternative_reject[alternative_order[i]]; | |
586 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
15e35479 KH |
587 | |
588 | for (j = i + 1; j < recog_data.n_alternatives; j++) | |
589 | { | |
590 | int this_reject = alternative_reject[alternative_order[j]]; | |
591 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
592 | ||
593 | if (this_reject < best_reject | |
8a4c09c8 | 594 | || (this_reject == best_reject && this_nregs > best_nregs)) |
15e35479 KH |
595 | { |
596 | best = j; | |
597 | best_reject = this_reject; | |
598 | best_nregs = this_nregs; | |
599 | } | |
600 | } | |
601 | ||
fab27f52 | 602 | std::swap (alternative_order[best], alternative_order[i]); |
15e35479 KH |
603 | } |
604 | ||
605 | /* Substitute the operands as determined by op_alt_regno for the best | |
606 | alternative. */ | |
607 | j = alternative_order[0]; | |
608 | ||
609 | for (i = 0; i < recog_data.n_operands; i++) | |
610 | { | |
ef4bddc2 | 611 | machine_mode mode = recog_data.operand_mode[i]; |
15e35479 KH |
612 | if (op_alt_regno[i][j] == -1) |
613 | continue; | |
614 | ||
615 | validate_change (insn, recog_data.operand_loc[i], | |
616 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); | |
617 | } | |
618 | ||
619 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
620 | { | |
621 | int op = recog_data.dup_num[i]; | |
ef4bddc2 | 622 | machine_mode mode = recog_data.operand_mode[op]; |
15e35479 KH |
623 | |
624 | if (op_alt_regno[op][j] == -1) | |
625 | continue; | |
626 | ||
627 | validate_change (insn, recog_data.dup_loc[i], | |
628 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); | |
629 | } | |
630 | ||
631 | return apply_change_group (); | |
632 | } | |
633 | \f | |
634 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
635 | addressing now. | |
636 | This code might also be useful when reload gave up on reg+reg addressing | |
637 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
638 | ||
639 | /* The maximum number of uses of a register we can keep track of to | |
640 | replace them with reg+reg addressing. */ | |
dc0d5a57 | 641 | #define RELOAD_COMBINE_MAX_USES 16 |
15e35479 | 642 | |
dc0d5a57 BS |
643 | /* Describes a recorded use of a register. */ |
644 | struct reg_use | |
645 | { | |
646 | /* The insn where a register has been used. */ | |
f90af2e0 | 647 | rtx_insn *insn; |
dc0d5a57 BS |
648 | /* Points to the memory reference enclosing the use, if any, NULL_RTX |
649 | otherwise. */ | |
650 | rtx containing_mem; | |
073a8998 | 651 | /* Location of the register within INSN. */ |
dc0d5a57 BS |
652 | rtx *usep; |
653 | /* The reverse uid of the insn. */ | |
654 | int ruid; | |
655 | }; | |
15e35479 KH |
656 | |
657 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
658 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
dc0d5a57 | 659 | indicates where it is first set or clobbered. |
15e35479 | 660 | Otherwise, USE_INDEX is the index of the last encountered use of the |
dc0d5a57 BS |
661 | register (which is first among these we have seen since we scan backwards). |
662 | USE_RUID indicates the first encountered, i.e. last, of these uses. | |
663 | If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | |
664 | with a constant offset; OFFSET contains this constant in that case. | |
15e35479 KH |
665 | STORE_RUID is always meaningful if we only want to use a value in a |
666 | register in a different place: it denotes the next insn in the insn | |
dc0d5a57 BS |
667 | stream (i.e. the last encountered) that sets or clobbers the register. |
668 | REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ | |
15e35479 KH |
669 | static struct |
670 | { | |
671 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
15e35479 | 672 | rtx offset; |
dc0d5a57 | 673 | int use_index; |
15e35479 | 674 | int store_ruid; |
dc0d5a57 | 675 | int real_store_ruid; |
15e35479 | 676 | int use_ruid; |
dc0d5a57 | 677 | bool all_offsets_match; |
15e35479 KH |
678 | } reg_state[FIRST_PSEUDO_REGISTER]; |
679 | ||
680 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
681 | the instructions from last to first. It is used to set last_label_ruid | |
682 | and the store_ruid / use_ruid fields in reg_state. */ | |
683 | static int reload_combine_ruid; | |
684 | ||
67bb0206 BS |
685 | /* The RUID of the last label we encountered in reload_combine. */ |
686 | static int last_label_ruid; | |
687 | ||
dc0d5a57 BS |
688 | /* The RUID of the last jump we encountered in reload_combine. */ |
689 | static int last_jump_ruid; | |
690 | ||
67bb0206 BS |
691 | /* The register numbers of the first and last index register. A value of |
692 | -1 in LAST_INDEX_REG indicates that we've previously computed these | |
693 | values and found no suitable index registers. */ | |
694 | static int first_index_reg = -1; | |
695 | static int last_index_reg; | |
696 | ||
15e35479 KH |
697 | #define LABEL_LIVE(LABEL) \ |
698 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
699 | ||
dc0d5a57 BS |
700 | /* Subroutine of reload_combine_split_ruids, called to fix up a single |
701 | ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | |
702 | ||
703 | static inline void | |
704 | reload_combine_split_one_ruid (int *pruid, int split_ruid) | |
705 | { | |
706 | if (*pruid > split_ruid) | |
707 | (*pruid)++; | |
708 | } | |
709 | ||
710 | /* Called when we insert a new insn in a position we've already passed in | |
711 | the scan. Examine all our state, increasing all ruids that are higher | |
712 | than SPLIT_RUID by one in order to make room for a new insn. */ | |
713 | ||
714 | static void | |
715 | reload_combine_split_ruids (int split_ruid) | |
716 | { | |
717 | unsigned i; | |
718 | ||
719 | reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | |
720 | reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | |
721 | reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | |
722 | ||
723 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
724 | { | |
725 | int j, idx = reg_state[i].use_index; | |
726 | reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | |
727 | reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | |
728 | reload_combine_split_one_ruid (®_state[i].real_store_ruid, | |
729 | split_ruid); | |
730 | if (idx < 0) | |
731 | continue; | |
732 | for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | |
733 | { | |
734 | reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | |
735 | split_ruid); | |
736 | } | |
737 | } | |
738 | } | |
739 | ||
740 | /* Called when we are about to rescan a previously encountered insn with | |
741 | reload_combine_note_use after modifying some part of it. This clears all | |
742 | information about uses in that particular insn. */ | |
743 | ||
744 | static void | |
f90af2e0 | 745 | reload_combine_purge_insn_uses (rtx_insn *insn) |
dc0d5a57 BS |
746 | { |
747 | unsigned i; | |
748 | ||
749 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
750 | { | |
751 | int j, k, idx = reg_state[i].use_index; | |
752 | if (idx < 0) | |
753 | continue; | |
754 | j = k = RELOAD_COMBINE_MAX_USES; | |
755 | while (j-- > idx) | |
756 | { | |
757 | if (reg_state[i].reg_use[j].insn != insn) | |
758 | { | |
759 | k--; | |
760 | if (k != j) | |
761 | reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | |
762 | } | |
763 | } | |
764 | reg_state[i].use_index = k; | |
765 | } | |
766 | } | |
767 | ||
768 | /* Called when we need to forget about all uses of REGNO after an insn | |
769 | which is identified by RUID. */ | |
770 | ||
771 | static void | |
772 | reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | |
773 | { | |
774 | int j, k, idx = reg_state[regno].use_index; | |
775 | if (idx < 0) | |
776 | return; | |
777 | j = k = RELOAD_COMBINE_MAX_USES; | |
778 | while (j-- > idx) | |
779 | { | |
780 | if (reg_state[regno].reg_use[j].ruid >= ruid) | |
781 | { | |
782 | k--; | |
783 | if (k != j) | |
784 | reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | |
785 | } | |
786 | } | |
787 | reg_state[regno].use_index = k; | |
788 | } | |
789 | ||
790 | /* Find the use of REGNO with the ruid that is highest among those | |
791 | lower than RUID_LIMIT, and return it if it is the only use of this | |
08bd6876 | 792 | reg in the insn. Return NULL otherwise. */ |
dc0d5a57 BS |
793 | |
794 | static struct reg_use * | |
795 | reload_combine_closest_single_use (unsigned regno, int ruid_limit) | |
796 | { | |
797 | int i, best_ruid = 0; | |
798 | int use_idx = reg_state[regno].use_index; | |
799 | struct reg_use *retval; | |
800 | ||
801 | if (use_idx < 0) | |
802 | return NULL; | |
803 | retval = NULL; | |
804 | for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | |
805 | { | |
b1d5eee8 BS |
806 | struct reg_use *use = reg_state[regno].reg_use + i; |
807 | int this_ruid = use->ruid; | |
dc0d5a57 BS |
808 | if (this_ruid >= ruid_limit) |
809 | continue; | |
810 | if (this_ruid > best_ruid) | |
811 | { | |
812 | best_ruid = this_ruid; | |
08bd6876 | 813 | retval = use; |
dc0d5a57 | 814 | } |
08bd6876 | 815 | else if (this_ruid == best_ruid) |
dc0d5a57 BS |
816 | retval = NULL; |
817 | } | |
818 | if (last_label_ruid >= best_ruid) | |
819 | return NULL; | |
820 | return retval; | |
821 | } | |
822 | ||
caa4a250 BS |
823 | /* After we've moved an add insn, fix up any debug insns that occur |
824 | between the old location of the add and the new location. REG is | |
825 | the destination register of the add insn; REPLACEMENT is the | |
826 | SET_SRC of the add. FROM and TO specify the range in which we | |
827 | should make this change on debug insns. */ | |
b1d5eee8 BS |
828 | |
829 | static void | |
f90af2e0 | 830 | fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to) |
b1d5eee8 | 831 | { |
f90af2e0 | 832 | rtx_insn *insn; |
caa4a250 | 833 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) |
b1d5eee8 BS |
834 | { |
835 | rtx t; | |
caa4a250 BS |
836 | |
837 | if (!DEBUG_INSN_P (insn)) | |
b1d5eee8 | 838 | continue; |
caa4a250 BS |
839 | |
840 | t = INSN_VAR_LOCATION_LOC (insn); | |
08bd6876 | 841 | t = simplify_replace_rtx (t, reg, replacement); |
caa4a250 | 842 | validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); |
b1d5eee8 BS |
843 | } |
844 | } | |
845 | ||
a78e242c BS |
846 | /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG |
847 | with SRC in the insn described by USE, taking costs into account. Return | |
848 | true if we made the replacement. */ | |
849 | ||
850 | static bool | |
851 | try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | |
852 | { | |
f90af2e0 | 853 | rtx_insn *use_insn = use->insn; |
a78e242c BS |
854 | rtx mem = use->containing_mem; |
855 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | |
856 | ||
857 | if (mem != NULL_RTX) | |
858 | { | |
859 | addr_space_t as = MEM_ADDR_SPACE (mem); | |
860 | rtx oldaddr = XEXP (mem, 0); | |
861 | rtx newaddr = NULL_RTX; | |
862 | int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | |
863 | int new_cost; | |
864 | ||
865 | newaddr = simplify_replace_rtx (oldaddr, reg, src); | |
866 | if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | |
867 | { | |
868 | XEXP (mem, 0) = newaddr; | |
869 | new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | |
870 | XEXP (mem, 0) = oldaddr; | |
871 | if (new_cost <= old_cost | |
872 | && validate_change (use_insn, | |
873 | &XEXP (mem, 0), newaddr, 0)) | |
874 | return true; | |
875 | } | |
876 | } | |
877 | else | |
878 | { | |
879 | rtx new_set = single_set (use_insn); | |
880 | if (new_set | |
881 | && REG_P (SET_DEST (new_set)) | |
882 | && GET_CODE (SET_SRC (new_set)) == PLUS | |
883 | && REG_P (XEXP (SET_SRC (new_set), 0)) | |
884 | && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | |
885 | { | |
886 | rtx new_src; | |
e548c9df AM |
887 | machine_mode mode = GET_MODE (SET_DEST (new_set)); |
888 | int old_cost = set_src_cost (SET_SRC (new_set), mode, speed); | |
a78e242c BS |
889 | |
890 | gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | |
891 | new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | |
892 | ||
e548c9df | 893 | if (set_src_cost (new_src, mode, speed) <= old_cost |
a78e242c BS |
894 | && validate_change (use_insn, &SET_SRC (new_set), |
895 | new_src, 0)) | |
896 | return true; | |
897 | } | |
898 | } | |
899 | return false; | |
900 | } | |
901 | ||
dc0d5a57 BS |
902 | /* Called by reload_combine when scanning INSN. This function tries to detect |
903 | patterns where a constant is added to a register, and the result is used | |
904 | in an address. | |
905 | Return true if no further processing is needed on INSN; false if it wasn't | |
906 | recognized and should be handled normally. */ | |
907 | ||
908 | static bool | |
f90af2e0 | 909 | reload_combine_recognize_const_pattern (rtx_insn *insn) |
dc0d5a57 BS |
910 | { |
911 | int from_ruid = reload_combine_ruid; | |
912 | rtx set, pat, reg, src, addreg; | |
913 | unsigned int regno; | |
914 | struct reg_use *use; | |
915 | bool must_move_add; | |
f90af2e0 | 916 | rtx_insn *add_moved_after_insn = NULL; |
dc0d5a57 BS |
917 | int add_moved_after_ruid = 0; |
918 | int clobbered_regno = -1; | |
919 | ||
920 | set = single_set (insn); | |
921 | if (set == NULL_RTX) | |
922 | return false; | |
923 | ||
924 | reg = SET_DEST (set); | |
925 | src = SET_SRC (set); | |
926 | if (!REG_P (reg) | |
dc8afb70 | 927 | || REG_NREGS (reg) != 1 |
dc0d5a57 BS |
928 | || GET_MODE (reg) != Pmode |
929 | || reg == stack_pointer_rtx) | |
930 | return false; | |
931 | ||
932 | regno = REGNO (reg); | |
933 | ||
934 | /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | |
935 | uses of REG1 inside an address, or inside another add insn. If | |
936 | possible and profitable, merge the addition into subsequent | |
937 | uses. */ | |
938 | if (GET_CODE (src) != PLUS | |
939 | || !REG_P (XEXP (src, 0)) | |
940 | || !CONSTANT_P (XEXP (src, 1))) | |
941 | return false; | |
942 | ||
943 | addreg = XEXP (src, 0); | |
944 | must_move_add = rtx_equal_p (reg, addreg); | |
945 | ||
946 | pat = PATTERN (insn); | |
947 | if (must_move_add && set != pat) | |
948 | { | |
949 | /* We have to be careful when moving the add; apart from the | |
950 | single_set there may also be clobbers. Recognize one special | |
951 | case, that of one clobber alongside the set (likely a clobber | |
952 | of the CC register). */ | |
953 | gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | |
954 | if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | |
955 | || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | |
956 | || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | |
957 | return false; | |
958 | clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | |
959 | } | |
960 | ||
961 | do | |
962 | { | |
963 | use = reload_combine_closest_single_use (regno, from_ruid); | |
964 | ||
965 | if (use) | |
966 | /* Start the search for the next use from here. */ | |
967 | from_ruid = use->ruid; | |
968 | ||
969 | if (use && GET_MODE (*use->usep) == Pmode) | |
970 | { | |
a78e242c | 971 | bool delete_add = false; |
f90af2e0 | 972 | rtx_insn *use_insn = use->insn; |
dc0d5a57 | 973 | int use_ruid = use->ruid; |
dc0d5a57 BS |
974 | |
975 | /* Avoid moving the add insn past a jump. */ | |
b1d5eee8 | 976 | if (must_move_add && use_ruid <= last_jump_ruid) |
dc0d5a57 BS |
977 | break; |
978 | ||
979 | /* If the add clobbers another hard reg in parallel, don't move | |
980 | it past a real set of this hard reg. */ | |
981 | if (must_move_add && clobbered_regno >= 0 | |
982 | && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | |
983 | break; | |
984 | ||
3b8ff89f | 985 | /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ |
058eb3b0 | 986 | if (HAVE_cc0 && must_move_add && sets_cc0_p (PATTERN (use_insn))) |
3b8ff89f | 987 | break; |
3b8ff89f | 988 | |
62036819 BS |
989 | gcc_assert (reg_state[regno].store_ruid <= use_ruid); |
990 | /* Avoid moving a use of ADDREG past a point where it is stored. */ | |
a78e242c | 991 | if (reg_state[REGNO (addreg)].store_ruid > use_ruid) |
dc0d5a57 BS |
992 | break; |
993 | ||
a78e242c BS |
994 | /* We also must not move the addition past an insn that sets |
995 | the same register, unless we can combine two add insns. */ | |
996 | if (must_move_add && reg_state[regno].store_ruid == use_ruid) | |
dc0d5a57 | 997 | { |
a78e242c BS |
998 | if (use->containing_mem == NULL_RTX) |
999 | delete_add = true; | |
1000 | else | |
1001 | break; | |
dc0d5a57 | 1002 | } |
dc0d5a57 | 1003 | |
a78e242c BS |
1004 | if (try_replace_in_use (use, reg, src)) |
1005 | { | |
1006 | reload_combine_purge_insn_uses (use_insn); | |
1007 | reload_combine_note_use (&PATTERN (use_insn), use_insn, | |
1008 | use_ruid, NULL_RTX); | |
dc0d5a57 | 1009 | |
a78e242c BS |
1010 | if (delete_add) |
1011 | { | |
1012 | fixup_debug_insns (reg, src, insn, use_insn); | |
1013 | delete_insn (insn); | |
1014 | return true; | |
1015 | } | |
1016 | if (must_move_add) | |
1017 | { | |
1018 | add_moved_after_insn = use_insn; | |
1019 | add_moved_after_ruid = use_ruid; | |
dc0d5a57 | 1020 | } |
a78e242c | 1021 | continue; |
dc0d5a57 | 1022 | } |
dc0d5a57 | 1023 | } |
62036819 BS |
1024 | /* If we get here, we couldn't handle this use. */ |
1025 | if (must_move_add) | |
1026 | break; | |
dc0d5a57 BS |
1027 | } |
1028 | while (use); | |
1029 | ||
1030 | if (!must_move_add || add_moved_after_insn == NULL_RTX) | |
1031 | /* Process the add normally. */ | |
1032 | return false; | |
1033 | ||
caa4a250 BS |
1034 | fixup_debug_insns (reg, src, insn, add_moved_after_insn); |
1035 | ||
dc0d5a57 BS |
1036 | reorder_insns (insn, insn, add_moved_after_insn); |
1037 | reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | |
1038 | reload_combine_split_ruids (add_moved_after_ruid - 1); | |
1039 | reload_combine_note_use (&PATTERN (insn), insn, | |
1040 | add_moved_after_ruid, NULL_RTX); | |
1041 | reg_state[regno].store_ruid = add_moved_after_ruid; | |
1042 | ||
1043 | return true; | |
1044 | } | |
1045 | ||
67bb0206 BS |
1046 | /* Called by reload_combine when scanning INSN. Try to detect a pattern we |
1047 | can handle and improve. Return true if no further processing is needed on | |
1048 | INSN; false if it wasn't recognized and should be handled normally. */ | |
1049 | ||
1050 | static bool | |
f90af2e0 | 1051 | reload_combine_recognize_pattern (rtx_insn *insn) |
67bb0206 BS |
1052 | { |
1053 | rtx set, reg, src; | |
67bb0206 | 1054 | |
dc0d5a57 BS |
1055 | set = single_set (insn); |
1056 | if (set == NULL_RTX) | |
1057 | return false; | |
1058 | ||
1059 | reg = SET_DEST (set); | |
1060 | src = SET_SRC (set); | |
dc8afb70 | 1061 | if (!REG_P (reg) || REG_NREGS (reg) != 1) |
dc0d5a57 BS |
1062 | return false; |
1063 | ||
201d49e9 BS |
1064 | unsigned int regno = REGNO (reg); |
1065 | machine_mode mode = GET_MODE (reg); | |
1066 | ||
1067 | if (reg_state[regno].use_index < 0 | |
1068 | || reg_state[regno].use_index >= RELOAD_COMBINE_MAX_USES) | |
1069 | return false; | |
1070 | ||
1071 | for (int i = reg_state[regno].use_index; | |
1072 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1073 | { | |
1074 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1075 | if (GET_MODE (*use->usep) != mode) | |
1076 | return false; | |
1077 | } | |
dc0d5a57 | 1078 | |
67bb0206 BS |
1079 | /* Look for (set (REGX) (CONST_INT)) |
1080 | (set (REGX) (PLUS (REGX) (REGY))) | |
1081 | ... | |
1082 | ... (MEM (REGX)) ... | |
1083 | and convert it to | |
1084 | (set (REGZ) (CONST_INT)) | |
1085 | ... | |
1086 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
1087 | ||
1088 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
1089 | and that we know all uses of REGX before it dies. | |
1090 | Also, explicitly check that REGX != REGY; our life information | |
1091 | does not yet show whether REGY changes in this insn. */ | |
67bb0206 BS |
1092 | |
1093 | if (GET_CODE (src) == PLUS | |
dc0d5a57 BS |
1094 | && reg_state[regno].all_offsets_match |
1095 | && last_index_reg != -1 | |
67bb0206 BS |
1096 | && REG_P (XEXP (src, 1)) |
1097 | && rtx_equal_p (XEXP (src, 0), reg) | |
1098 | && !rtx_equal_p (XEXP (src, 1), reg) | |
1099 | && last_label_ruid < reg_state[regno].use_ruid) | |
1100 | { | |
1101 | rtx base = XEXP (src, 1); | |
f90af2e0 | 1102 | rtx_insn *prev = prev_nonnote_nondebug_insn (insn); |
67bb0206 BS |
1103 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; |
1104 | rtx index_reg = NULL_RTX; | |
1105 | rtx reg_sum = NULL_RTX; | |
1106 | int i; | |
1107 | ||
1108 | /* Now we need to set INDEX_REG to an index register (denoted as | |
1109 | REGZ in the illustration above) and REG_SUM to the expression | |
1110 | register+register that we want to use to substitute uses of REG | |
1111 | (typically in MEMs) with. First check REG and BASE for being | |
1112 | index registers; we can use them even if they are not dead. */ | |
1113 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
1114 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
1115 | REGNO (base))) | |
1116 | { | |
1117 | index_reg = reg; | |
1118 | reg_sum = src; | |
1119 | } | |
1120 | else | |
1121 | { | |
1122 | /* Otherwise, look for a free index register. Since we have | |
1123 | checked above that neither REG nor BASE are index registers, | |
1124 | if we find anything at all, it will be different from these | |
1125 | two registers. */ | |
1126 | for (i = first_index_reg; i <= last_index_reg; i++) | |
1127 | { | |
1128 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | |
1129 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | |
1130 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
08bd6876 BS |
1131 | && (call_used_regs[i] || df_regs_ever_live_p (i)) |
1132 | && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) | |
1133 | && !fixed_regs[i] && !global_regs[i] | |
1134 | && hard_regno_nregs[i][GET_MODE (reg)] == 1 | |
1135 | && targetm.hard_regno_scratch_ok (i)) | |
67bb0206 BS |
1136 | { |
1137 | index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
1138 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
1139 | break; | |
1140 | } | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | |
1145 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
1146 | create. */ | |
1147 | if (reg_sum | |
1148 | && prev_set | |
1149 | && CONST_INT_P (SET_SRC (prev_set)) | |
1150 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
67bb0206 BS |
1151 | && (reg_state[REGNO (base)].store_ruid |
1152 | <= reg_state[regno].use_ruid)) | |
1153 | { | |
1154 | /* Change destination register and, if necessary, the constant | |
1155 | value in PREV, the constant loading instruction. */ | |
1156 | validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | |
1157 | if (reg_state[regno].offset != const0_rtx) | |
1158 | validate_change (prev, | |
1159 | &SET_SRC (prev_set), | |
1160 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
1161 | + INTVAL (reg_state[regno].offset)), | |
1162 | 1); | |
1163 | ||
1164 | /* Now for every use of REG that we have recorded, replace REG | |
1165 | with REG_SUM. */ | |
1166 | for (i = reg_state[regno].use_index; | |
1167 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1168 | validate_unshare_change (reg_state[regno].reg_use[i].insn, | |
1169 | reg_state[regno].reg_use[i].usep, | |
1170 | /* Each change must have its own | |
1171 | replacement. */ | |
1172 | reg_sum, 1); | |
1173 | ||
1174 | if (apply_change_group ()) | |
1175 | { | |
caa4a250 BS |
1176 | struct reg_use *lowest_ruid = NULL; |
1177 | ||
67bb0206 BS |
1178 | /* For every new use of REG_SUM, we have to record the use |
1179 | of BASE therein, i.e. operand 1. */ | |
1180 | for (i = reg_state[regno].use_index; | |
1181 | i < RELOAD_COMBINE_MAX_USES; i++) | |
caa4a250 BS |
1182 | { |
1183 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1184 | reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | |
1185 | use->ruid, use->containing_mem); | |
1186 | if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | |
1187 | lowest_ruid = use; | |
1188 | } | |
1189 | ||
1190 | fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | |
67bb0206 | 1191 | |
67bb0206 BS |
1192 | /* Delete the reg-reg addition. */ |
1193 | delete_insn (insn); | |
1194 | ||
1195 | if (reg_state[regno].offset != const0_rtx) | |
1196 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV | |
1197 | are now invalid. */ | |
1198 | remove_reg_equal_equiv_notes (prev); | |
1199 | ||
1200 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
67bb0206 BS |
1201 | return true; |
1202 | } | |
1203 | } | |
1204 | } | |
1205 | return false; | |
1206 | } | |
1207 | ||
15e35479 | 1208 | static void |
0c20a65f | 1209 | reload_combine (void) |
15e35479 | 1210 | { |
f90af2e0 | 1211 | rtx_insn *insn, *prev; |
15e35479 KH |
1212 | basic_block bb; |
1213 | unsigned int r; | |
15e35479 KH |
1214 | int min_labelno, n_labels; |
1215 | HARD_REG_SET ever_live_at_start, *label_live; | |
1216 | ||
15e35479 KH |
1217 | /* To avoid wasting too much time later searching for an index register, |
1218 | determine the minimum and maximum index register numbers. */ | |
67bb0206 BS |
1219 | if (INDEX_REG_CLASS == NO_REGS) |
1220 | last_index_reg = -1; | |
1221 | else if (first_index_reg == -1 && last_index_reg == 0) | |
1222 | { | |
1223 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1224 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
1225 | { | |
1226 | if (first_index_reg == -1) | |
1227 | first_index_reg = r; | |
1228 | ||
1229 | last_index_reg = r; | |
1230 | } | |
1231 | ||
1232 | /* If no index register is available, we can quit now. Set LAST_INDEX_REG | |
1233 | to -1 so we'll know to quit early the next time we get here. */ | |
1234 | if (first_index_reg == -1) | |
1235 | { | |
1236 | last_index_reg = -1; | |
1237 | return; | |
1238 | } | |
1239 | } | |
15e35479 | 1240 | |
15e35479 KH |
1241 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
1242 | information is a bit fuzzy immediately after reload, but it's | |
1243 | still good enough to determine which registers are live at a jump | |
1244 | destination. */ | |
1245 | min_labelno = get_first_label_num (); | |
1246 | n_labels = max_label_num () - min_labelno; | |
5ed6ace5 | 1247 | label_live = XNEWVEC (HARD_REG_SET, n_labels); |
15e35479 KH |
1248 | CLEAR_HARD_REG_SET (ever_live_at_start); |
1249 | ||
4f42035e | 1250 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
15e35479 | 1251 | { |
a813c111 | 1252 | insn = BB_HEAD (bb); |
4b4bf941 | 1253 | if (LABEL_P (insn)) |
15e35479 KH |
1254 | { |
1255 | HARD_REG_SET live; | |
89a95777 | 1256 | bitmap live_in = df_get_live_in (bb); |
15e35479 | 1257 | |
89a95777 KZ |
1258 | REG_SET_TO_HARD_REG_SET (live, live_in); |
1259 | compute_use_by_pseudos (&live, live_in); | |
15e35479 KH |
1260 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
1261 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | |
dc0d5a57 | 1266 | last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; |
15e35479 KH |
1267 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
1268 | { | |
dc0d5a57 BS |
1269 | reg_state[r].store_ruid = 0; |
1270 | reg_state[r].real_store_ruid = 0; | |
15e35479 KH |
1271 | if (fixed_regs[r]) |
1272 | reg_state[r].use_index = -1; | |
1273 | else | |
1274 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1275 | } | |
1276 | ||
dc0d5a57 | 1277 | for (insn = get_last_insn (); insn; insn = prev) |
15e35479 | 1278 | { |
7ad93142 | 1279 | bool control_flow_insn; |
15e35479 KH |
1280 | rtx note; |
1281 | ||
dc0d5a57 BS |
1282 | prev = PREV_INSN (insn); |
1283 | ||
15e35479 KH |
1284 | /* We cannot do our optimization across labels. Invalidating all the use |
1285 | information we have would be costly, so we just note where the label | |
1286 | is and then later disable any optimization that would cross it. */ | |
4b4bf941 | 1287 | if (LABEL_P (insn)) |
15e35479 | 1288 | last_label_ruid = reload_combine_ruid; |
2195c9be AK |
1289 | else if (BARRIER_P (insn)) |
1290 | { | |
1291 | /* Crossing a barrier resets all the use information. */ | |
1292 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1293 | if (! fixed_regs[r]) | |
15e35479 | 1294 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
2195c9be AK |
1295 | } |
1296 | else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn))) | |
1297 | /* Optimizations across insns being marked as volatile must be | |
1298 | prevented. All the usage information is invalidated | |
1299 | here. */ | |
1300 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1301 | if (! fixed_regs[r] | |
1302 | && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES) | |
1303 | reg_state[r].use_index = -1; | |
15e35479 | 1304 | |
caa4a250 | 1305 | if (! NONDEBUG_INSN_P (insn)) |
15e35479 KH |
1306 | continue; |
1307 | ||
1308 | reload_combine_ruid++; | |
1309 | ||
7ad93142 EB |
1310 | control_flow_insn = control_flow_insn_p (insn); |
1311 | if (control_flow_insn) | |
dc0d5a57 BS |
1312 | last_jump_ruid = reload_combine_ruid; |
1313 | ||
1314 | if (reload_combine_recognize_const_pattern (insn) | |
1315 | || reload_combine_recognize_pattern (insn)) | |
67bb0206 | 1316 | continue; |
15e35479 KH |
1317 | |
1318 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | |
1319 | ||
4b4bf941 | 1320 | if (CALL_P (insn)) |
15e35479 KH |
1321 | { |
1322 | rtx link; | |
97ded4cd TV |
1323 | HARD_REG_SET used_regs; |
1324 | ||
1325 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); | |
15e35479 KH |
1326 | |
1327 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
97ded4cd | 1328 | if (TEST_HARD_REG_BIT (used_regs, r)) |
15e35479 KH |
1329 | { |
1330 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1331 | reg_state[r].store_ruid = reload_combine_ruid; | |
1332 | } | |
1333 | ||
1334 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
1335 | link = XEXP (link, 1)) | |
1336 | { | |
e384e6b5 BS |
1337 | rtx setuse = XEXP (link, 0); |
1338 | rtx usage_rtx = XEXP (setuse, 0); | |
1339 | if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER) | |
1340 | && REG_P (usage_rtx)) | |
15e35479 | 1341 | { |
53d1bae9 RS |
1342 | unsigned int end_regno = END_REGNO (usage_rtx); |
1343 | for (unsigned int i = REGNO (usage_rtx); i < end_regno; ++i) | |
15e35479 KH |
1344 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) |
1345 | { | |
1346 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
1347 | reg_state[i].store_ruid = reload_combine_ruid; | |
1348 | } | |
1349 | else | |
1350 | reg_state[i].use_index = -1; | |
1351 | } | |
1352 | } | |
15e35479 | 1353 | } |
18c33e03 | 1354 | |
57895947 | 1355 | if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn))) |
15e35479 KH |
1356 | { |
1357 | /* Non-spill registers might be used at the call destination in | |
1358 | some unknown fashion, so we have to mark the unknown use. */ | |
1359 | HARD_REG_SET *live; | |
1360 | ||
1361 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
1362 | && JUMP_LABEL (insn)) | |
57895947 EB |
1363 | { |
1364 | if (ANY_RETURN_P (JUMP_LABEL (insn))) | |
1365 | live = NULL; | |
1366 | else | |
1367 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
1368 | } | |
15e35479 KH |
1369 | else |
1370 | live = &ever_live_at_start; | |
1371 | ||
57895947 EB |
1372 | if (live) |
1373 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1374 | if (TEST_HARD_REG_BIT (*live, r)) | |
1375 | reg_state[r].use_index = -1; | |
15e35479 KH |
1376 | } |
1377 | ||
7ad93142 EB |
1378 | reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, |
1379 | NULL_RTX); | |
1380 | ||
15e35479 KH |
1381 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1382 | { | |
7ad93142 | 1383 | if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) |
15e35479 KH |
1384 | { |
1385 | int regno = REGNO (XEXP (note, 0)); | |
15e35479 | 1386 | reg_state[regno].store_ruid = reload_combine_ruid; |
dc0d5a57 | 1387 | reg_state[regno].real_store_ruid = reload_combine_ruid; |
15e35479 KH |
1388 | reg_state[regno].use_index = -1; |
1389 | } | |
1390 | } | |
1391 | } | |
1392 | ||
1393 | free (label_live); | |
1394 | } | |
1395 | ||
1396 | /* Check if DST is a register or a subreg of a register; if it is, | |
dc0d5a57 BS |
1397 | update store_ruid, real_store_ruid and use_index in the reg_state |
1398 | structure accordingly. Called via note_stores from reload_combine. */ | |
15e35479 KH |
1399 | |
1400 | static void | |
7bc980e1 | 1401 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) |
15e35479 KH |
1402 | { |
1403 | int regno = 0; | |
1404 | int i; | |
ef4bddc2 | 1405 | machine_mode mode = GET_MODE (dst); |
15e35479 KH |
1406 | |
1407 | if (GET_CODE (dst) == SUBREG) | |
1408 | { | |
1409 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
1410 | GET_MODE (SUBREG_REG (dst)), | |
1411 | SUBREG_BYTE (dst), | |
1412 | GET_MODE (dst)); | |
1413 | dst = SUBREG_REG (dst); | |
1414 | } | |
12c2b0ad JL |
1415 | |
1416 | /* Some targets do argument pushes without adding REG_INC notes. */ | |
1417 | ||
1418 | if (MEM_P (dst)) | |
1419 | { | |
1420 | dst = XEXP (dst, 0); | |
1421 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
96676a5d JJ |
1422 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC |
1423 | || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) | |
12c2b0ad | 1424 | { |
53d1bae9 RS |
1425 | unsigned int end_regno = END_REGNO (XEXP (dst, 0)); |
1426 | for (unsigned int i = REGNO (XEXP (dst, 0)); i < end_regno; ++i) | |
12c2b0ad JL |
1427 | { |
1428 | /* We could probably do better, but for now mark the register | |
1429 | as used in an unknown fashion and set/clobbered at this | |
1430 | insn. */ | |
1431 | reg_state[i].use_index = -1; | |
1432 | reg_state[i].store_ruid = reload_combine_ruid; | |
1433 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
1434 | } | |
1435 | } | |
1436 | else | |
1437 | return; | |
1438 | } | |
1439 | ||
f8cfc6aa | 1440 | if (!REG_P (dst)) |
15e35479 KH |
1441 | return; |
1442 | regno += REGNO (dst); | |
1443 | ||
1444 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | |
1445 | careful with registers / register parts that are not full words. | |
46d096a3 | 1446 | Similarly for ZERO_EXTRACT. */ |
dc0d5a57 | 1447 | if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT |
15e35479 KH |
1448 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) |
1449 | { | |
66fd46b6 | 1450 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
15e35479 KH |
1451 | { |
1452 | reg_state[i].use_index = -1; | |
1453 | reg_state[i].store_ruid = reload_combine_ruid; | |
dc0d5a57 | 1454 | reg_state[i].real_store_ruid = reload_combine_ruid; |
15e35479 KH |
1455 | } |
1456 | } | |
1457 | else | |
1458 | { | |
66fd46b6 | 1459 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
15e35479 KH |
1460 | { |
1461 | reg_state[i].store_ruid = reload_combine_ruid; | |
dc0d5a57 BS |
1462 | if (GET_CODE (set) == SET) |
1463 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
15e35479 KH |
1464 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
1465 | } | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | /* XP points to a piece of rtl that has to be checked for any uses of | |
1470 | registers. | |
1471 | *XP is the pattern of INSN, or a part of it. | |
1472 | Called from reload_combine, and recursively by itself. */ | |
1473 | static void | |
f90af2e0 | 1474 | reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem) |
15e35479 KH |
1475 | { |
1476 | rtx x = *xp; | |
1477 | enum rtx_code code = x->code; | |
1478 | const char *fmt; | |
1479 | int i, j; | |
1480 | rtx offset = const0_rtx; /* For the REG case below. */ | |
1481 | ||
1482 | switch (code) | |
1483 | { | |
1484 | case SET: | |
f8cfc6aa | 1485 | if (REG_P (SET_DEST (x))) |
15e35479 | 1486 | { |
dc0d5a57 | 1487 | reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); |
15e35479 KH |
1488 | return; |
1489 | } | |
1490 | break; | |
1491 | ||
1492 | case USE: | |
1493 | /* If this is the USE of a return value, we can't change it. */ | |
f8cfc6aa | 1494 | if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) |
15e35479 | 1495 | { |
53d1bae9 | 1496 | /* Mark the return register as used in an unknown fashion. */ |
15e35479 | 1497 | rtx reg = XEXP (x, 0); |
53d1bae9 RS |
1498 | unsigned int end_regno = END_REGNO (reg); |
1499 | for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno) | |
1500 | reg_state[regno].use_index = -1; | |
15e35479 KH |
1501 | return; |
1502 | } | |
1503 | break; | |
1504 | ||
1505 | case CLOBBER: | |
f8cfc6aa | 1506 | if (REG_P (SET_DEST (x))) |
15e35479 KH |
1507 | { |
1508 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
e16acfcd | 1509 | gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); |
15e35479 KH |
1510 | return; |
1511 | } | |
1512 | break; | |
1513 | ||
1514 | case PLUS: | |
1515 | /* We are interested in (plus (reg) (const_int)) . */ | |
f8cfc6aa | 1516 | if (!REG_P (XEXP (x, 0)) |
481683e1 | 1517 | || !CONST_INT_P (XEXP (x, 1))) |
15e35479 KH |
1518 | break; |
1519 | offset = XEXP (x, 1); | |
1520 | x = XEXP (x, 0); | |
1521 | /* Fall through. */ | |
1522 | case REG: | |
1523 | { | |
1524 | int regno = REGNO (x); | |
1525 | int use_index; | |
1526 | int nregs; | |
1527 | ||
1528 | /* No spurious USEs of pseudo registers may remain. */ | |
e16acfcd | 1529 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); |
15e35479 | 1530 | |
dc8afb70 | 1531 | nregs = REG_NREGS (x); |
15e35479 KH |
1532 | |
1533 | /* We can't substitute into multi-hard-reg uses. */ | |
1534 | if (nregs > 1) | |
1535 | { | |
1536 | while (--nregs >= 0) | |
1537 | reg_state[regno + nregs].use_index = -1; | |
1538 | return; | |
1539 | } | |
1540 | ||
08bd6876 BS |
1541 | /* We may be called to update uses in previously seen insns. |
1542 | Don't add uses beyond the last store we saw. */ | |
1543 | if (ruid < reg_state[regno].store_ruid) | |
1544 | return; | |
1545 | ||
15e35479 KH |
1546 | /* If this register is already used in some unknown fashion, we |
1547 | can't do anything. | |
1548 | If we decrement the index from zero to -1, we can't store more | |
1549 | uses, so this register becomes used in an unknown fashion. */ | |
1550 | use_index = --reg_state[regno].use_index; | |
1551 | if (use_index < 0) | |
1552 | return; | |
1553 | ||
dc0d5a57 | 1554 | if (use_index == RELOAD_COMBINE_MAX_USES - 1) |
15e35479 KH |
1555 | { |
1556 | /* This is the first use of this register we have seen since we | |
1557 | marked it as dead. */ | |
1558 | reg_state[regno].offset = offset; | |
dc0d5a57 BS |
1559 | reg_state[regno].all_offsets_match = true; |
1560 | reg_state[regno].use_ruid = ruid; | |
15e35479 | 1561 | } |
b1d5eee8 BS |
1562 | else |
1563 | { | |
1564 | if (reg_state[regno].use_ruid > ruid) | |
1565 | reg_state[regno].use_ruid = ruid; | |
1566 | ||
1567 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
1568 | reg_state[regno].all_offsets_match = false; | |
1569 | } | |
dc0d5a57 | 1570 | |
15e35479 | 1571 | reg_state[regno].reg_use[use_index].insn = insn; |
dc0d5a57 BS |
1572 | reg_state[regno].reg_use[use_index].ruid = ruid; |
1573 | reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | |
15e35479 KH |
1574 | reg_state[regno].reg_use[use_index].usep = xp; |
1575 | return; | |
1576 | } | |
1577 | ||
dc0d5a57 BS |
1578 | case MEM: |
1579 | containing_mem = x; | |
1580 | break; | |
1581 | ||
15e35479 KH |
1582 | default: |
1583 | break; | |
1584 | } | |
1585 | ||
1586 | /* Recursively process the components of X. */ | |
1587 | fmt = GET_RTX_FORMAT (code); | |
1588 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1589 | { | |
1590 | if (fmt[i] == 'e') | |
dc0d5a57 | 1591 | reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); |
15e35479 KH |
1592 | else if (fmt[i] == 'E') |
1593 | { | |
1594 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
dc0d5a57 BS |
1595 | reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, |
1596 | containing_mem); | |
15e35479 KH |
1597 | } |
1598 | } | |
1599 | } | |
1600 | \f | |
1601 | /* See if we can reduce the cost of a constant by replacing a move | |
1602 | with an add. We track situations in which a register is set to a | |
1603 | constant or to a register plus a constant. */ | |
1604 | /* We cannot do our optimization across labels. Invalidating all the | |
1605 | information about register contents we have would be costly, so we | |
1606 | use move2add_last_label_luid to note where the label is and then | |
1607 | later disable any optimization that would cross it. | |
7beb0596 JZ |
1608 | reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] |
1609 | are only valid if reg_set_luid[n] is greater than | |
7894bc6b JR |
1610 | move2add_last_label_luid. |
1611 | For a set that established a new (potential) base register with | |
1612 | non-constant value, we use move2add_luid from the place where the | |
1613 | setting insn is encountered; registers based off that base then | |
1614 | get the same reg_set_luid. Constants all get | |
1615 | move2add_last_label_luid + 1 as their reg_set_luid. */ | |
15e35479 KH |
1616 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
1617 | ||
1618 | /* If reg_base_reg[n] is negative, register n has been set to | |
7beb0596 | 1619 | reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. |
15e35479 KH |
1620 | If reg_base_reg[n] is non-negative, register n has been set to the |
1621 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
7894bc6b JR |
1622 | before reg_set_luid[n], calculated in mode reg_mode[n] . |
1623 | For multi-hard-register registers, all but the first one are | |
1624 | recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode | |
1625 | marks it as invalid. */ | |
15e35479 KH |
1626 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
1627 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
7beb0596 | 1628 | static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; |
ef4bddc2 | 1629 | static machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; |
15e35479 KH |
1630 | |
1631 | /* move2add_luid is linearly increased while scanning the instructions | |
1632 | from first to last. It is used to set reg_set_luid in | |
1633 | reload_cse_move2add and move2add_note_store. */ | |
1634 | static int move2add_luid; | |
1635 | ||
1636 | /* move2add_last_label_luid is set whenever a label is found. Labels | |
1637 | invalidate all previously collected reg_offset data. */ | |
1638 | static int move2add_last_label_luid; | |
1639 | ||
1640 | /* ??? We don't know how zero / sign extension is handled, hence we | |
1641 | can't go from a narrower to a wider mode. */ | |
1642 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
1643 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
1644 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
d0edd768 | 1645 | && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE))) |
15e35479 | 1646 | |
7894bc6b JR |
1647 | /* Record that REG is being set to a value with the mode of REG. */ |
1648 | ||
1649 | static void | |
1650 | move2add_record_mode (rtx reg) | |
1651 | { | |
1652 | int regno, nregs; | |
ef4bddc2 | 1653 | machine_mode mode = GET_MODE (reg); |
7894bc6b JR |
1654 | |
1655 | if (GET_CODE (reg) == SUBREG) | |
1656 | { | |
1657 | regno = subreg_regno (reg); | |
1658 | nregs = subreg_nregs (reg); | |
1659 | } | |
1660 | else if (REG_P (reg)) | |
1661 | { | |
1662 | regno = REGNO (reg); | |
dc8afb70 | 1663 | nregs = REG_NREGS (reg); |
7894bc6b JR |
1664 | } |
1665 | else | |
1666 | gcc_unreachable (); | |
1667 | for (int i = nregs - 1; i > 0; i--) | |
1668 | reg_mode[regno + i] = BLKmode; | |
1669 | reg_mode[regno] = mode; | |
1670 | } | |
1671 | ||
1672 | /* Record that REG is being set to the sum of SYM and OFF. */ | |
1673 | ||
1674 | static void | |
1675 | move2add_record_sym_value (rtx reg, rtx sym, rtx off) | |
1676 | { | |
1677 | int regno = REGNO (reg); | |
1678 | ||
1679 | move2add_record_mode (reg); | |
1680 | reg_set_luid[regno] = move2add_luid; | |
1681 | reg_base_reg[regno] = -1; | |
1682 | reg_symbol_ref[regno] = sym; | |
1683 | reg_offset[regno] = INTVAL (off); | |
1684 | } | |
1685 | ||
1686 | /* Check if REGNO contains a valid value in MODE. */ | |
1687 | ||
1688 | static bool | |
ef4bddc2 | 1689 | move2add_valid_value_p (int regno, machine_mode mode) |
7894bc6b | 1690 | { |
ca035367 | 1691 | if (reg_set_luid[regno] <= move2add_last_label_luid) |
7894bc6b JR |
1692 | return false; |
1693 | ||
ca035367 JR |
1694 | if (mode != reg_mode[regno]) |
1695 | { | |
1696 | if (!MODES_OK_FOR_MOVE2ADD (mode, reg_mode[regno])) | |
1697 | return false; | |
1698 | /* The value loaded into regno in reg_mode[regno] is also valid in | |
1699 | mode after truncation only if (REG:mode regno) is the lowpart of | |
1700 | (REG:reg_mode[regno] regno). Now, for big endian, the starting | |
1701 | regno of the lowpart might be different. */ | |
1702 | int s_off = subreg_lowpart_offset (mode, reg_mode[regno]); | |
1703 | s_off = subreg_regno_offset (regno, reg_mode[regno], s_off, mode); | |
1704 | if (s_off != 0) | |
1705 | /* We could in principle adjust regno, check reg_mode[regno] to be | |
1706 | BLKmode, and return s_off to the caller (vs. -1 for failure), | |
1707 | but we currently have no callers that could make use of this | |
1708 | information. */ | |
1709 | return false; | |
1710 | } | |
1711 | ||
7894bc6b JR |
1712 | for (int i = hard_regno_nregs[regno][mode] - 1; i > 0; i--) |
1713 | if (reg_mode[regno + i] != BLKmode) | |
1714 | return false; | |
1715 | return true; | |
1716 | } | |
1717 | ||
7beb0596 JZ |
1718 | /* This function is called with INSN that sets REG to (SYM + OFF), |
1719 | while REG is known to already have value (SYM + offset). | |
1720 | This function tries to change INSN into an add instruction | |
1721 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | |
dc0d5a57 BS |
1722 | It also updates the information about REG's known value. |
1723 | Return true if we made a change. */ | |
7beb0596 | 1724 | |
dc0d5a57 | 1725 | static bool |
f90af2e0 | 1726 | move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) |
7beb0596 JZ |
1727 | { |
1728 | rtx pat = PATTERN (insn); | |
1729 | rtx src = SET_SRC (pat); | |
1730 | int regno = REGNO (reg); | |
e15eb172 | 1731 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], |
7beb0596 JZ |
1732 | GET_MODE (reg)); |
1733 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
dc0d5a57 | 1734 | bool changed = false; |
7beb0596 JZ |
1735 | |
1736 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1737 | use (set (reg) (reg)) instead. | |
1738 | We don't delete this insn, nor do we convert it into a | |
1739 | note, to avoid losing register notes or the return | |
1740 | value flag. jump2 already knows how to get rid of | |
1741 | no-op moves. */ | |
1742 | if (new_src == const0_rtx) | |
1743 | { | |
1744 | /* If the constants are different, this is a | |
1745 | truncation, that, if turned into (set (reg) | |
1746 | (reg)), would be discarded. Maybe we should | |
1747 | try a truncMN pattern? */ | |
1748 | if (INTVAL (off) == reg_offset [regno]) | |
dc0d5a57 | 1749 | changed = validate_change (insn, &SET_SRC (pat), reg, 0); |
7beb0596 | 1750 | } |
22939744 | 1751 | else |
7beb0596 | 1752 | { |
22939744 | 1753 | struct full_rtx_costs oldcst, newcst; |
7beb0596 | 1754 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); |
22939744 | 1755 | |
d51102f3 | 1756 | get_full_set_rtx_cost (pat, &oldcst); |
22939744 | 1757 | SET_SRC (pat) = tem; |
d51102f3 | 1758 | get_full_set_rtx_cost (pat, &newcst); |
22939744 BS |
1759 | SET_SRC (pat) = src; |
1760 | ||
1761 | if (costs_lt_p (&newcst, &oldcst, speed) | |
1762 | && have_add2_insn (reg, new_src)) | |
1763 | changed = validate_change (insn, &SET_SRC (pat), tem, 0); | |
1764 | else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | |
7beb0596 | 1765 | { |
ef4bddc2 | 1766 | machine_mode narrow_mode; |
22939744 BS |
1767 | for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
1768 | narrow_mode != VOIDmode | |
1769 | && narrow_mode != GET_MODE (reg); | |
1770 | narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) | |
7beb0596 | 1771 | { |
22939744 BS |
1772 | if (have_insn_for (STRICT_LOW_PART, narrow_mode) |
1773 | && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) | |
1774 | == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) | |
1775 | { | |
b49eefa5 | 1776 | rtx narrow_reg = gen_lowpart_common (narrow_mode, reg); |
22939744 BS |
1777 | rtx narrow_src = gen_int_mode (INTVAL (off), |
1778 | narrow_mode); | |
1779 | rtx new_set | |
f7df4a84 | 1780 | = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode, |
22939744 BS |
1781 | narrow_reg), |
1782 | narrow_src); | |
a0f37b26 AS |
1783 | get_full_set_rtx_cost (new_set, &newcst); |
1784 | if (costs_lt_p (&newcst, &oldcst, speed)) | |
1785 | { | |
1786 | changed = validate_change (insn, &PATTERN (insn), | |
1787 | new_set, 0); | |
1788 | if (changed) | |
1789 | break; | |
1790 | } | |
22939744 | 1791 | } |
7beb0596 JZ |
1792 | } |
1793 | } | |
1794 | } | |
7894bc6b | 1795 | move2add_record_sym_value (reg, sym, off); |
dc0d5a57 | 1796 | return changed; |
7beb0596 JZ |
1797 | } |
1798 | ||
1799 | ||
1800 | /* This function is called with INSN that sets REG to (SYM + OFF), | |
1801 | but REG doesn't have known value (SYM + offset). This function | |
1802 | tries to find another register which is known to already have | |
1803 | value (SYM + offset) and change INSN into an add instruction | |
1804 | (set (REG) (plus (the found register) (OFF - offset))) if such | |
1805 | a register is found. It also updates the information about | |
dc0d5a57 BS |
1806 | REG's known value. |
1807 | Return true iff we made a change. */ | |
7beb0596 | 1808 | |
dc0d5a57 | 1809 | static bool |
f90af2e0 | 1810 | move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) |
7beb0596 JZ |
1811 | { |
1812 | rtx pat = PATTERN (insn); | |
1813 | rtx src = SET_SRC (pat); | |
1814 | int regno = REGNO (reg); | |
5676e87d | 1815 | int min_regno = 0; |
7beb0596 JZ |
1816 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
1817 | int i; | |
dc0d5a57 | 1818 | bool changed = false; |
22939744 BS |
1819 | struct full_rtx_costs oldcst, newcst, mincst; |
1820 | rtx plus_expr; | |
1821 | ||
1822 | init_costs_to_max (&mincst); | |
d51102f3 | 1823 | get_full_set_rtx_cost (pat, &oldcst); |
22939744 BS |
1824 | |
1825 | plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); | |
1826 | SET_SRC (pat) = plus_expr; | |
7beb0596 JZ |
1827 | |
1828 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7894bc6b | 1829 | if (move2add_valid_value_p (i, GET_MODE (reg)) |
7beb0596 JZ |
1830 | && reg_base_reg[i] < 0 |
1831 | && reg_symbol_ref[i] != NULL_RTX | |
1832 | && rtx_equal_p (sym, reg_symbol_ref[i])) | |
1833 | { | |
e15eb172 | 1834 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i], |
7beb0596 JZ |
1835 | GET_MODE (reg)); |
1836 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1837 | use (set (reg) (reg)) instead. | |
1838 | We don't delete this insn, nor do we convert it into a | |
1839 | note, to avoid losing register notes or the return | |
1840 | value flag. jump2 already knows how to get rid of | |
1841 | no-op moves. */ | |
1842 | if (new_src == const0_rtx) | |
1843 | { | |
22939744 | 1844 | init_costs_to_zero (&mincst); |
7beb0596 JZ |
1845 | min_regno = i; |
1846 | break; | |
1847 | } | |
1848 | else | |
1849 | { | |
22939744 | 1850 | XEXP (plus_expr, 1) = new_src; |
d51102f3 | 1851 | get_full_set_rtx_cost (pat, &newcst); |
22939744 BS |
1852 | |
1853 | if (costs_lt_p (&newcst, &mincst, speed)) | |
7beb0596 | 1854 | { |
22939744 | 1855 | mincst = newcst; |
7beb0596 JZ |
1856 | min_regno = i; |
1857 | } | |
1858 | } | |
1859 | } | |
22939744 | 1860 | SET_SRC (pat) = src; |
7beb0596 | 1861 | |
22939744 | 1862 | if (costs_lt_p (&mincst, &oldcst, speed)) |
7beb0596 JZ |
1863 | { |
1864 | rtx tem; | |
1865 | ||
1866 | tem = gen_rtx_REG (GET_MODE (reg), min_regno); | |
1867 | if (i != min_regno) | |
1868 | { | |
e15eb172 | 1869 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno], |
7beb0596 JZ |
1870 | GET_MODE (reg)); |
1871 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | |
1872 | } | |
dc0d5a57 BS |
1873 | if (validate_change (insn, &SET_SRC (pat), tem, 0)) |
1874 | changed = true; | |
7beb0596 JZ |
1875 | } |
1876 | reg_set_luid[regno] = move2add_luid; | |
7894bc6b | 1877 | move2add_record_sym_value (reg, sym, off); |
dc0d5a57 | 1878 | return changed; |
7beb0596 JZ |
1879 | } |
1880 | ||
dc0d5a57 BS |
1881 | /* Convert move insns with constant inputs to additions if they are cheaper. |
1882 | Return true if any changes were made. */ | |
1883 | static bool | |
f90af2e0 | 1884 | reload_cse_move2add (rtx_insn *first) |
15e35479 KH |
1885 | { |
1886 | int i; | |
f90af2e0 | 1887 | rtx_insn *insn; |
dc0d5a57 | 1888 | bool changed = false; |
15e35479 KH |
1889 | |
1890 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
7beb0596 JZ |
1891 | { |
1892 | reg_set_luid[i] = 0; | |
1893 | reg_offset[i] = 0; | |
1894 | reg_base_reg[i] = 0; | |
1895 | reg_symbol_ref[i] = NULL_RTX; | |
1896 | reg_mode[i] = VOIDmode; | |
1897 | } | |
15e35479 KH |
1898 | |
1899 | move2add_last_label_luid = 0; | |
1900 | move2add_luid = 2; | |
1901 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
1902 | { | |
1903 | rtx pat, note; | |
1904 | ||
4b4bf941 | 1905 | if (LABEL_P (insn)) |
15e35479 KH |
1906 | { |
1907 | move2add_last_label_luid = move2add_luid; | |
1908 | /* We're going to increment move2add_luid twice after a | |
1909 | label, so that we can use move2add_last_label_luid + 1 as | |
1910 | the luid for constants. */ | |
1911 | move2add_luid++; | |
1912 | continue; | |
1913 | } | |
1914 | if (! INSN_P (insn)) | |
1915 | continue; | |
1916 | pat = PATTERN (insn); | |
1917 | /* For simplicity, we only perform this optimization on | |
1918 | straightforward SETs. */ | |
1919 | if (GET_CODE (pat) == SET | |
f8cfc6aa | 1920 | && REG_P (SET_DEST (pat))) |
15e35479 KH |
1921 | { |
1922 | rtx reg = SET_DEST (pat); | |
1923 | int regno = REGNO (reg); | |
1924 | rtx src = SET_SRC (pat); | |
1925 | ||
1926 | /* Check if we have valid information on the contents of this | |
1927 | register in the mode of REG. */ | |
7894bc6b | 1928 | if (move2add_valid_value_p (regno, GET_MODE (reg)) |
6fb5fa3c | 1929 | && dbg_cnt (cse2_move2add)) |
15e35479 KH |
1930 | { |
1931 | /* Try to transform (set (REGX) (CONST_INT A)) | |
1932 | ... | |
1933 | (set (REGX) (CONST_INT B)) | |
1934 | to | |
1935 | (set (REGX) (CONST_INT A)) | |
1936 | ... | |
1937 | (set (REGX) (plus (REGX) (CONST_INT B-A))) | |
1938 | or | |
1939 | (set (REGX) (CONST_INT A)) | |
1940 | ... | |
1941 | (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | |
1942 | */ | |
1943 | ||
7beb0596 JZ |
1944 | if (CONST_INT_P (src) |
1945 | && reg_base_reg[regno] < 0 | |
1946 | && reg_symbol_ref[regno] == NULL_RTX) | |
15e35479 | 1947 | { |
dc0d5a57 | 1948 | changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); |
15e35479 KH |
1949 | continue; |
1950 | } | |
1951 | ||
1952 | /* Try to transform (set (REGX) (REGY)) | |
1953 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1954 | ... | |
1955 | (set (REGX) (REGY)) | |
1956 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
1957 | to | |
1958 | (set (REGX) (REGY)) | |
1959 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1960 | ... | |
1961 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
f8cfc6aa | 1962 | else if (REG_P (src) |
15e35479 KH |
1963 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
1964 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
7894bc6b | 1965 | && move2add_valid_value_p (REGNO (src), GET_MODE (reg))) |
15e35479 | 1966 | { |
f90af2e0 | 1967 | rtx_insn *next = next_nonnote_nondebug_insn (insn); |
15e35479 KH |
1968 | rtx set = NULL_RTX; |
1969 | if (next) | |
1970 | set = single_set (next); | |
1971 | if (set | |
1972 | && SET_DEST (set) == reg | |
1973 | && GET_CODE (SET_SRC (set)) == PLUS | |
1974 | && XEXP (SET_SRC (set), 0) == reg | |
481683e1 | 1975 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) |
15e35479 KH |
1976 | { |
1977 | rtx src3 = XEXP (SET_SRC (set), 1); | |
e15eb172 | 1978 | unsigned HOST_WIDE_INT added_offset = UINTVAL (src3); |
15e35479 KH |
1979 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; |
1980 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
1981 | rtx new_src = | |
bb80db7b KH |
1982 | gen_int_mode (added_offset |
1983 | + base_offset | |
1984 | - regno_offset, | |
1985 | GET_MODE (reg)); | |
f40751dd JH |
1986 | bool success = false; |
1987 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
15e35479 KH |
1988 | |
1989 | if (new_src == const0_rtx) | |
1990 | /* See above why we create (set (reg) (reg)) here. */ | |
1991 | success | |
1992 | = validate_change (next, &SET_SRC (set), reg, 0); | |
22939744 | 1993 | else |
15e35479 | 1994 | { |
22939744 BS |
1995 | rtx old_src = SET_SRC (set); |
1996 | struct full_rtx_costs oldcst, newcst; | |
1997 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | |
1998 | ||
d51102f3 | 1999 | get_full_set_rtx_cost (set, &oldcst); |
22939744 | 2000 | SET_SRC (set) = tem; |
e548c9df | 2001 | get_full_set_src_cost (tem, GET_MODE (reg), &newcst); |
22939744 BS |
2002 | SET_SRC (set) = old_src; |
2003 | costs_add_n_insns (&oldcst, 1); | |
2004 | ||
2005 | if (costs_lt_p (&newcst, &oldcst, speed) | |
2006 | && have_add2_insn (reg, new_src)) | |
2007 | { | |
f7df4a84 | 2008 | rtx newpat = gen_rtx_SET (reg, tem); |
22939744 BS |
2009 | success |
2010 | = validate_change (next, &PATTERN (next), | |
2011 | newpat, 0); | |
2012 | } | |
15e35479 KH |
2013 | } |
2014 | if (success) | |
2015 | delete_insn (insn); | |
dc0d5a57 | 2016 | changed |= success; |
15e35479 | 2017 | insn = next; |
7894bc6b JR |
2018 | move2add_record_mode (reg); |
2019 | reg_offset[regno] | |
2020 | = trunc_int_for_mode (added_offset + base_offset, | |
2021 | GET_MODE (reg)); | |
15e35479 KH |
2022 | continue; |
2023 | } | |
2024 | } | |
2025 | } | |
7beb0596 JZ |
2026 | |
2027 | /* Try to transform | |
2028 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2029 | ... | |
2030 | (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) | |
2031 | to | |
2032 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2033 | ... | |
2034 | (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ | |
2035 | if ((GET_CODE (src) == SYMBOL_REF | |
2036 | || (GET_CODE (src) == CONST | |
2037 | && GET_CODE (XEXP (src, 0)) == PLUS | |
2038 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF | |
2039 | && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) | |
2040 | && dbg_cnt (cse2_move2add)) | |
2041 | { | |
2042 | rtx sym, off; | |
2043 | ||
2044 | if (GET_CODE (src) == SYMBOL_REF) | |
2045 | { | |
2046 | sym = src; | |
2047 | off = const0_rtx; | |
2048 | } | |
2049 | else | |
2050 | { | |
2051 | sym = XEXP (XEXP (src, 0), 0); | |
2052 | off = XEXP (XEXP (src, 0), 1); | |
2053 | } | |
2054 | ||
2055 | /* If the reg already contains the value which is sum of | |
2056 | sym and some constant value, we can use an add2 insn. */ | |
7894bc6b | 2057 | if (move2add_valid_value_p (regno, GET_MODE (reg)) |
7beb0596 JZ |
2058 | && reg_base_reg[regno] < 0 |
2059 | && reg_symbol_ref[regno] != NULL_RTX | |
2060 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | |
dc0d5a57 | 2061 | changed |= move2add_use_add2_insn (reg, sym, off, insn); |
7beb0596 JZ |
2062 | |
2063 | /* Otherwise, we have to find a register whose value is sum | |
2064 | of sym and some constant value. */ | |
2065 | else | |
dc0d5a57 | 2066 | changed |= move2add_use_add3_insn (reg, sym, off, insn); |
7beb0596 JZ |
2067 | |
2068 | continue; | |
2069 | } | |
15e35479 KH |
2070 | } |
2071 | ||
2072 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2073 | { | |
2074 | if (REG_NOTE_KIND (note) == REG_INC | |
f8cfc6aa | 2075 | && REG_P (XEXP (note, 0))) |
15e35479 KH |
2076 | { |
2077 | /* Reset the information about this register. */ | |
2078 | int regno = REGNO (XEXP (note, 0)); | |
2079 | if (regno < FIRST_PSEUDO_REGISTER) | |
7894bc6b JR |
2080 | { |
2081 | move2add_record_mode (XEXP (note, 0)); | |
2082 | reg_mode[regno] = VOIDmode; | |
2083 | } | |
15e35479 KH |
2084 | } |
2085 | } | |
7beb0596 | 2086 | note_stores (PATTERN (insn), move2add_note_store, insn); |
15e35479 KH |
2087 | |
2088 | /* If INSN is a conditional branch, we try to extract an | |
2089 | implicit set out of it. */ | |
c4cdb8e1 | 2090 | if (any_condjump_p (insn)) |
15e35479 KH |
2091 | { |
2092 | rtx cnd = fis_get_condition (insn); | |
2093 | ||
2094 | if (cnd != NULL_RTX | |
2095 | && GET_CODE (cnd) == NE | |
f8cfc6aa | 2096 | && REG_P (XEXP (cnd, 0)) |
c4cdb8e1 | 2097 | && !reg_set_p (XEXP (cnd, 0), insn) |
15e35479 KH |
2098 | /* The following two checks, which are also in |
2099 | move2add_note_store, are intended to reduce the | |
2100 | number of calls to gen_rtx_SET to avoid memory | |
2101 | allocation if possible. */ | |
2102 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) | |
dc8afb70 | 2103 | && REG_NREGS (XEXP (cnd, 0)) == 1 |
481683e1 | 2104 | && CONST_INT_P (XEXP (cnd, 1))) |
15e35479 KH |
2105 | { |
2106 | rtx implicit_set = | |
f7df4a84 | 2107 | gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1)); |
7beb0596 | 2108 | move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); |
15e35479 KH |
2109 | } |
2110 | } | |
2111 | ||
2112 | /* If this is a CALL_INSN, all call used registers are stored with | |
2113 | unknown values. */ | |
4b4bf941 | 2114 | if (CALL_P (insn)) |
15e35479 | 2115 | { |
7a708f68 UB |
2116 | rtx link; |
2117 | ||
15e35479 KH |
2118 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
2119 | { | |
2120 | if (call_used_regs[i]) | |
2121 | /* Reset the information about this register. */ | |
7894bc6b | 2122 | reg_mode[i] = VOIDmode; |
15e35479 | 2123 | } |
7a708f68 UB |
2124 | |
2125 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
2126 | link = XEXP (link, 1)) | |
2127 | { | |
2128 | rtx setuse = XEXP (link, 0); | |
2129 | rtx usage_rtx = XEXP (setuse, 0); | |
2130 | if (GET_CODE (setuse) == CLOBBER | |
2131 | && REG_P (usage_rtx)) | |
2132 | { | |
2133 | unsigned int end_regno = END_REGNO (usage_rtx); | |
2134 | for (unsigned int r = REGNO (usage_rtx); r < end_regno; ++r) | |
2135 | /* Reset the information about this register. */ | |
2136 | reg_mode[r] = VOIDmode; | |
2137 | } | |
2138 | } | |
15e35479 KH |
2139 | } |
2140 | } | |
dc0d5a57 | 2141 | return changed; |
15e35479 KH |
2142 | } |
2143 | ||
7beb0596 JZ |
2144 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which |
2145 | contains SET. | |
15e35479 KH |
2146 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. |
2147 | Called from reload_cse_move2add via note_stores. */ | |
2148 | ||
2149 | static void | |
7beb0596 | 2150 | move2add_note_store (rtx dst, const_rtx set, void *data) |
15e35479 | 2151 | { |
f90af2e0 | 2152 | rtx_insn *insn = (rtx_insn *) data; |
15e35479 | 2153 | unsigned int regno = 0; |
ef4bddc2 | 2154 | machine_mode mode = GET_MODE (dst); |
15e35479 | 2155 | |
15e35479 KH |
2156 | /* Some targets do argument pushes without adding REG_INC notes. */ |
2157 | ||
3c0cb5de | 2158 | if (MEM_P (dst)) |
15e35479 KH |
2159 | { |
2160 | dst = XEXP (dst, 0); | |
2161 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
2162 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) | |
7894bc6b | 2163 | reg_mode[REGNO (XEXP (dst, 0))] = VOIDmode; |
15e35479 KH |
2164 | return; |
2165 | } | |
15e35479 | 2166 | |
7894bc6b JR |
2167 | if (GET_CODE (dst) == SUBREG) |
2168 | regno = subreg_regno (dst); | |
2169 | else if (REG_P (dst)) | |
2170 | regno = REGNO (dst); | |
2171 | else | |
2172 | return; | |
15e35479 | 2173 | |
7894bc6b JR |
2174 | if (SCALAR_INT_MODE_P (mode) |
2175 | && GET_CODE (set) == SET) | |
7beb0596 JZ |
2176 | { |
2177 | rtx note, sym = NULL_RTX; | |
7894bc6b | 2178 | rtx off; |
7beb0596 JZ |
2179 | |
2180 | note = find_reg_equal_equiv_note (insn); | |
2181 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
2182 | { | |
2183 | sym = XEXP (note, 0); | |
7894bc6b | 2184 | off = const0_rtx; |
7beb0596 JZ |
2185 | } |
2186 | else if (note && GET_CODE (XEXP (note, 0)) == CONST | |
2187 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
2188 | && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF | |
2189 | && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) | |
2190 | { | |
2191 | sym = XEXP (XEXP (XEXP (note, 0), 0), 0); | |
7894bc6b | 2192 | off = XEXP (XEXP (XEXP (note, 0), 0), 1); |
7beb0596 JZ |
2193 | } |
2194 | ||
2195 | if (sym != NULL_RTX) | |
2196 | { | |
7894bc6b | 2197 | move2add_record_sym_value (dst, sym, off); |
7beb0596 JZ |
2198 | return; |
2199 | } | |
2200 | } | |
2201 | ||
7894bc6b JR |
2202 | if (SCALAR_INT_MODE_P (mode) |
2203 | && GET_CODE (set) == SET | |
15e35479 | 2204 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT |
15e35479 KH |
2205 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) |
2206 | { | |
2207 | rtx src = SET_SRC (set); | |
2208 | rtx base_reg; | |
e15eb172 | 2209 | unsigned HOST_WIDE_INT offset; |
15e35479 | 2210 | int base_regno; |
15e35479 KH |
2211 | |
2212 | switch (GET_CODE (src)) | |
2213 | { | |
2214 | case PLUS: | |
f8cfc6aa | 2215 | if (REG_P (XEXP (src, 0))) |
15e35479 KH |
2216 | { |
2217 | base_reg = XEXP (src, 0); | |
2218 | ||
481683e1 | 2219 | if (CONST_INT_P (XEXP (src, 1))) |
e15eb172 | 2220 | offset = UINTVAL (XEXP (src, 1)); |
f8cfc6aa | 2221 | else if (REG_P (XEXP (src, 1)) |
7894bc6b | 2222 | && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode)) |
15e35479 | 2223 | { |
27d5e204 CLT |
2224 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 |
2225 | && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) | |
15e35479 KH |
2226 | offset = reg_offset[REGNO (XEXP (src, 1))]; |
2227 | /* Maybe the first register is known to be a | |
2228 | constant. */ | |
7894bc6b | 2229 | else if (move2add_valid_value_p (REGNO (base_reg), mode) |
27d5e204 CLT |
2230 | && reg_base_reg[REGNO (base_reg)] < 0 |
2231 | && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) | |
15e35479 KH |
2232 | { |
2233 | offset = reg_offset[REGNO (base_reg)]; | |
2234 | base_reg = XEXP (src, 1); | |
2235 | } | |
2236 | else | |
2237 | goto invalidate; | |
2238 | } | |
2239 | else | |
2240 | goto invalidate; | |
2241 | ||
2242 | break; | |
2243 | } | |
2244 | ||
2245 | goto invalidate; | |
2246 | ||
2247 | case REG: | |
2248 | base_reg = src; | |
2249 | offset = 0; | |
2250 | break; | |
2251 | ||
2252 | case CONST_INT: | |
2253 | /* Start tracking the register as a constant. */ | |
2254 | reg_base_reg[regno] = -1; | |
7beb0596 | 2255 | reg_symbol_ref[regno] = NULL_RTX; |
15e35479 KH |
2256 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
2257 | /* We assign the same luid to all registers set to constants. */ | |
2258 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
7894bc6b | 2259 | move2add_record_mode (dst); |
15e35479 KH |
2260 | return; |
2261 | ||
2262 | default: | |
7894bc6b | 2263 | goto invalidate; |
15e35479 KH |
2264 | } |
2265 | ||
2266 | base_regno = REGNO (base_reg); | |
2267 | /* If information about the base register is not valid, set it | |
2268 | up as a new base register, pretending its value is known | |
2269 | starting from the current insn. */ | |
7894bc6b | 2270 | if (!move2add_valid_value_p (base_regno, mode)) |
15e35479 KH |
2271 | { |
2272 | reg_base_reg[base_regno] = base_regno; | |
7beb0596 | 2273 | reg_symbol_ref[base_regno] = NULL_RTX; |
15e35479 KH |
2274 | reg_offset[base_regno] = 0; |
2275 | reg_set_luid[base_regno] = move2add_luid; | |
7894bc6b JR |
2276 | gcc_assert (GET_MODE (base_reg) == mode); |
2277 | move2add_record_mode (base_reg); | |
15e35479 | 2278 | } |
15e35479 KH |
2279 | |
2280 | /* Copy base information from our base register. */ | |
2281 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
2282 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
7beb0596 | 2283 | reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; |
15e35479 KH |
2284 | |
2285 | /* Compute the sum of the offsets or constants. */ | |
7894bc6b JR |
2286 | reg_offset[regno] |
2287 | = trunc_int_for_mode (offset + reg_offset[base_regno], mode); | |
2288 | ||
2289 | move2add_record_mode (dst); | |
15e35479 KH |
2290 | } |
2291 | else | |
2292 | { | |
7894bc6b JR |
2293 | invalidate: |
2294 | /* Invalidate the contents of the register. */ | |
2295 | move2add_record_mode (dst); | |
2296 | reg_mode[regno] = VOIDmode; | |
15e35479 KH |
2297 | } |
2298 | } | |
ef330312 | 2299 | \f |
27a4cd48 DM |
2300 | namespace { |
2301 | ||
2302 | const pass_data pass_data_postreload_cse = | |
ef330312 | 2303 | { |
27a4cd48 DM |
2304 | RTL_PASS, /* type */ |
2305 | "postreload", /* name */ | |
2306 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
2307 | TV_RELOAD_CSE_REGS, /* tv_id */ |
2308 | 0, /* properties_required */ | |
2309 | 0, /* properties_provided */ | |
2310 | 0, /* properties_destroyed */ | |
2311 | 0, /* todo_flags_start */ | |
3bea341f | 2312 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 | 2313 | }; |
27a4cd48 DM |
2314 | |
2315 | class pass_postreload_cse : public rtl_opt_pass | |
2316 | { | |
2317 | public: | |
c3284718 RS |
2318 | pass_postreload_cse (gcc::context *ctxt) |
2319 | : rtl_opt_pass (pass_data_postreload_cse, ctxt) | |
27a4cd48 DM |
2320 | {} |
2321 | ||
2322 | /* opt_pass methods: */ | |
1a3d085c TS |
2323 | virtual bool gate (function *) { return (optimize > 0 && reload_completed); } |
2324 | ||
be55bfe6 | 2325 | virtual unsigned int execute (function *); |
27a4cd48 DM |
2326 | |
2327 | }; // class pass_postreload_cse | |
2328 | ||
be55bfe6 TS |
2329 | unsigned int |
2330 | pass_postreload_cse::execute (function *fun) | |
2331 | { | |
2332 | if (!dbg_cnt (postreload_cse)) | |
2333 | return 0; | |
2334 | ||
2335 | /* Do a very simple CSE pass over just the hard registers. */ | |
2336 | reload_cse_regs (get_insns ()); | |
2337 | /* Reload_cse_regs can eliminate potentially-trapping MEMs. | |
2338 | Remove any EH edges associated with them. */ | |
2339 | if (fun->can_throw_non_call_exceptions | |
2340 | && purge_all_dead_edges ()) | |
2341 | cleanup_cfg (0); | |
2342 | ||
2343 | return 0; | |
2344 | } | |
2345 | ||
27a4cd48 DM |
2346 | } // anon namespace |
2347 | ||
2348 | rtl_opt_pass * | |
2349 | make_pass_postreload_cse (gcc::context *ctxt) | |
2350 | { | |
2351 | return new pass_postreload_cse (ctxt); | |
2352 | } |