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77c9c6c2 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
cc8d36a1 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
eeef0e45 | 4 | Free Software Foundation, Inc. |
77c9c6c2 | 5 | |
1322177d | 6 | This file is part of GCC. |
77c9c6c2 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
77c9c6c2 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
77c9c6c2 RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
77c9c6c2 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
01198c2f | 27 | #include "toplev.h" |
dff01034 KG |
28 | |
29 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
dc297297 | 30 | is properly defined. */ |
dff01034 | 31 | #include "insn-config.h" |
77c9c6c2 RK |
32 | #include "rtl.h" |
33 | #include "tree.h" | |
6baf1cc8 | 34 | #include "tm_p.h" |
77c9c6c2 | 35 | #include "flags.h" |
49ad7cfa | 36 | #include "function.h" |
52a11cbf | 37 | #include "except.h" |
77c9c6c2 | 38 | #include "expr.h" |
e78d8e51 ZW |
39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
77c9c6c2 | 41 | #include "recog.h" |
2829c155 | 42 | #include "reload.h" |
87ff9c8e | 43 | #include "ggc.h" |
7bdb32b9 | 44 | #include "real.h" |
4a69cf79 | 45 | #include "basic-block.h" |
c15c90bb | 46 | #include "target.h" |
77c9c6c2 RK |
47 | |
48 | /* Each optab contains info on how this target machine | |
49 | can perform a particular operation | |
50 | for all sizes and kinds of operands. | |
51 | ||
52 | The operation to be performed is often specified | |
53 | by passing one of these optabs as an argument. | |
54 | ||
55 | See expr.h for documentation of these optabs. */ | |
56 | ||
33727b5e JJ |
57 | #if GCC_VERSION >= 4000 |
58 | __extension__ struct optab optab_table[OTI_MAX] | |
59 | = { [0 ... OTI_MAX - 1].handlers[0 ... NUM_MACHINE_MODES - 1].insn_code | |
60 | = CODE_FOR_nothing }; | |
61 | #else | |
c0742514 | 62 | /* init_insn_codes will do runtime initialization otherwise. */ |
33727b5e JJ |
63 | struct optab optab_table[OTI_MAX]; |
64 | #endif | |
34220a12 BS |
65 | |
66 | rtx libfunc_table[LTI_MAX]; | |
19c3fc24 | 67 | |
85363ca0 | 68 | /* Tables of patterns for converting one mode to another. */ |
33727b5e JJ |
69 | #if GCC_VERSION >= 4000 |
70 | __extension__ struct convert_optab convert_optab_table[COI_MAX] | |
71 | = { [0 ... COI_MAX - 1].handlers[0 ... NUM_MACHINE_MODES - 1] | |
72 | [0 ... NUM_MACHINE_MODES - 1].insn_code | |
73 | = CODE_FOR_nothing }; | |
74 | #else | |
75 | /* init_convert_optab will do runtime initialization otherwise. */ | |
76 | struct convert_optab convert_optab_table[COI_MAX]; | |
77 | #endif | |
5d81dc5b | 78 | |
377017c4 RK |
79 | /* Contains the optab used for each rtx code. */ |
80 | optab code_to_optab[NUM_RTX_CODE + 1]; | |
81 | ||
77c9c6c2 RK |
82 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) |
83 | gives the gen_function to make a branch to test that condition. */ | |
84 | ||
85 | rtxfun bcc_gen_fctn[NUM_RTX_CODE]; | |
86 | ||
87 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) | |
88 | gives the insn code to make a store-condition insn | |
89 | to test that condition. */ | |
90 | ||
91 | enum insn_code setcc_gen_code[NUM_RTX_CODE]; | |
92 | ||
49c4584c DE |
93 | #ifdef HAVE_conditional_move |
94 | /* Indexed by the machine mode, gives the insn code to make a conditional | |
95 | move insn. This is not indexed by the rtx-code like bcc_gen_fctn and | |
96 | setcc_gen_code to cut down on the number of named patterns. Consider a day | |
97 | when a lot more rtx codes are conditional (eg: for the ARM). */ | |
98 | ||
99 | enum insn_code movcc_gen_code[NUM_MACHINE_MODES]; | |
100 | #endif | |
101 | ||
7ce67fbe DP |
102 | /* Indexed by the machine mode, gives the insn code for vector conditional |
103 | operation. */ | |
104 | ||
105 | enum insn_code vcond_gen_code[NUM_MACHINE_MODES]; | |
106 | enum insn_code vcondu_gen_code[NUM_MACHINE_MODES]; | |
107 | ||
842a431a DM |
108 | /* The insn generating function can not take an rtx_code argument. |
109 | TRAP_RTX is used as an rtx argument. Its code is replaced with | |
110 | the code to be used in the trap insn and all other fields are ignored. */ | |
111 | static GTY(()) rtx trap_rtx; | |
112 | ||
0c20a65f AJ |
113 | static void prepare_float_lib_cmp (rtx *, rtx *, enum rtx_code *, |
114 | enum machine_mode *, int *); | |
9cce5b20 | 115 | static rtx expand_unop_direct (enum machine_mode, optab, rtx, rtx, int); |
842a431a | 116 | |
8a33f100 JH |
117 | /* Debug facility for use in GDB. */ |
118 | void debug_optab_libfuncs (void); | |
119 | ||
842a431a DM |
120 | #ifndef HAVE_conditional_trap |
121 | #define HAVE_conditional_trap 0 | |
de3eb46f | 122 | #define gen_conditional_trap(a,b) (gcc_unreachable (), NULL_RTX) |
842a431a | 123 | #endif |
79b87c74 MM |
124 | |
125 | /* Prefixes for the current version of decimal floating point (BID vs. DPD) */ | |
126 | #if ENABLE_DECIMAL_BID_FORMAT | |
127 | #define DECIMAL_PREFIX "bid_" | |
128 | #else | |
129 | #define DECIMAL_PREFIX "dpd_" | |
130 | #endif | |
8a33f100 JH |
131 | \f |
132 | ||
133 | /* Info about libfunc. We use same hashtable for normal optabs and conversion | |
134 | optab. In the first case mode2 is unused. */ | |
135 | struct libfunc_entry GTY(()) | |
136 | { | |
a48b501c | 137 | size_t optab; |
8a33f100 JH |
138 | enum machine_mode mode1, mode2; |
139 | rtx libfunc; | |
140 | }; | |
141 | ||
142 | /* Hash table used to convert declarations into nodes. */ | |
143 | static GTY((param_is (struct libfunc_entry))) htab_t libfunc_hash; | |
144 | ||
145 | /* Used for attribute_hash. */ | |
146 | ||
147 | static hashval_t | |
148 | hash_libfunc (const void *p) | |
149 | { | |
150 | const struct libfunc_entry *const e = (const struct libfunc_entry *) p; | |
151 | ||
152 | return (((int) e->mode1 + (int) e->mode2 * NUM_MACHINE_MODES) | |
a48b501c | 153 | ^ e->optab); |
8a33f100 JH |
154 | } |
155 | ||
156 | /* Used for optab_hash. */ | |
157 | ||
158 | static int | |
159 | eq_libfunc (const void *p, const void *q) | |
160 | { | |
161 | const struct libfunc_entry *const e1 = (const struct libfunc_entry *) p; | |
162 | const struct libfunc_entry *const e2 = (const struct libfunc_entry *) q; | |
163 | ||
164 | return (e1->optab == e2->optab | |
165 | && e1->mode1 == e2->mode1 | |
166 | && e1->mode2 == e2->mode2); | |
167 | } | |
168 | ||
169 | /* Return libfunc corresponding operation defined by OPTAB converting | |
170 | from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL | |
171 | if no libfunc is available. */ | |
172 | rtx | |
173 | convert_optab_libfunc (convert_optab optab, enum machine_mode mode1, | |
174 | enum machine_mode mode2) | |
175 | { | |
176 | struct libfunc_entry e; | |
177 | struct libfunc_entry **slot; | |
178 | ||
33727b5e | 179 | e.optab = (size_t) (optab - &convert_optab_table[0]); |
8a33f100 JH |
180 | e.mode1 = mode1; |
181 | e.mode2 = mode2; | |
182 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
183 | if (!slot) | |
184 | { | |
185 | if (optab->libcall_gen) | |
186 | { | |
187 | optab->libcall_gen (optab, optab->libcall_basename, mode1, mode2); | |
188 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
189 | if (slot) | |
190 | return (*slot)->libfunc; | |
191 | else | |
192 | return NULL; | |
193 | } | |
194 | return NULL; | |
195 | } | |
196 | return (*slot)->libfunc; | |
197 | } | |
198 | ||
199 | /* Return libfunc corresponding operation defined by OPTAB in MODE. | |
200 | Trigger lazy initialization if needed, return NULL if no libfunc is | |
201 | available. */ | |
202 | rtx | |
203 | optab_libfunc (optab optab, enum machine_mode mode) | |
204 | { | |
205 | struct libfunc_entry e; | |
206 | struct libfunc_entry **slot; | |
207 | ||
33727b5e | 208 | e.optab = (size_t) (optab - &optab_table[0]); |
8a33f100 JH |
209 | e.mode1 = mode; |
210 | e.mode2 = VOIDmode; | |
211 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
212 | if (!slot) | |
213 | { | |
214 | if (optab->libcall_gen) | |
215 | { | |
216 | optab->libcall_gen (optab, optab->libcall_basename, | |
217 | optab->libcall_suffix, mode); | |
218 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, | |
219 | &e, NO_INSERT); | |
220 | if (slot) | |
221 | return (*slot)->libfunc; | |
222 | else | |
223 | return NULL; | |
224 | } | |
225 | return NULL; | |
226 | } | |
227 | return (*slot)->libfunc; | |
228 | } | |
79b87c74 | 229 | |
77c9c6c2 | 230 | \f |
2f937369 | 231 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
77c9c6c2 RK |
232 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
233 | operation). | |
234 | ||
235 | If the last insn does not set TARGET, don't do anything, but return 1. | |
236 | ||
237 | If a previous insn sets TARGET and TARGET is one of OP0 or OP1, | |
238 | don't add the REG_EQUAL note but return 0. Our caller can then try | |
239 | again, ensuring that TARGET is not one of the operands. */ | |
240 | ||
241 | static int | |
0c20a65f | 242 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
77c9c6c2 | 243 | { |
2f937369 | 244 | rtx last_insn, insn, set; |
77c9c6c2 RK |
245 | rtx note; |
246 | ||
e3feb571 | 247 | gcc_assert (insns && INSN_P (insns) && NEXT_INSN (insns)); |
2f937369 | 248 | |
ec8e098d PB |
249 | if (GET_RTX_CLASS (code) != RTX_COMM_ARITH |
250 | && GET_RTX_CLASS (code) != RTX_BIN_ARITH | |
251 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE | |
252 | && GET_RTX_CLASS (code) != RTX_COMPARE | |
253 | && GET_RTX_CLASS (code) != RTX_UNARY) | |
2f937369 DM |
254 | return 1; |
255 | ||
256 | if (GET_CODE (target) == ZERO_EXTRACT) | |
257 | return 1; | |
258 | ||
259 | for (last_insn = insns; | |
260 | NEXT_INSN (last_insn) != NULL_RTX; | |
261 | last_insn = NEXT_INSN (last_insn)) | |
262 | ; | |
263 | ||
264 | set = single_set (last_insn); | |
265 | if (set == NULL_RTX) | |
266 | return 1; | |
267 | ||
268 | if (! rtx_equal_p (SET_DEST (set), target) | |
f9d36a92 | 269 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
2f937369 | 270 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
f9d36a92 | 271 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
77c9c6c2 RK |
272 | return 1; |
273 | ||
274 | /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET | |
275 | besides the last insn. */ | |
276 | if (reg_overlap_mentioned_p (target, op0) | |
277 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
2f937369 DM |
278 | { |
279 | insn = PREV_INSN (last_insn); | |
280 | while (insn != NULL_RTX) | |
281 | { | |
282 | if (reg_set_p (target, insn)) | |
283 | return 0; | |
284 | ||
285 | insn = PREV_INSN (insn); | |
286 | } | |
287 | } | |
77c9c6c2 | 288 | |
ec8e098d | 289 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
9e6a5703 | 290 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); |
77c9c6c2 | 291 | else |
9e6a5703 | 292 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
77c9c6c2 | 293 | |
2f937369 | 294 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
77c9c6c2 RK |
295 | |
296 | return 1; | |
297 | } | |
298 | \f | |
835532b8 RK |
299 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
300 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
0c20a65f | 301 | not actually do a sign-extend or zero-extend, but can leave the |
835532b8 RK |
302 | higher-order bits of the result rtx undefined, for example, in the case |
303 | of logical operations, but not right shifts. */ | |
304 | ||
305 | static rtx | |
0c20a65f AJ |
306 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
307 | int unsignedp, int no_extend) | |
835532b8 RK |
308 | { |
309 | rtx result; | |
310 | ||
8041889f RK |
311 | /* If we don't have to extend and this is a constant, return it. */ |
312 | if (no_extend && GET_MODE (op) == VOIDmode) | |
313 | return op; | |
314 | ||
315 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
316 | extend since it will be more efficient to do so unless the signedness of | |
317 | a promoted object differs from our extension. */ | |
835532b8 | 318 | if (! no_extend |
cb8f73be RK |
319 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
320 | && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp)) | |
0661a3de | 321 | return convert_modes (mode, oldmode, op, unsignedp); |
835532b8 RK |
322 | |
323 | /* If MODE is no wider than a single word, we return a paradoxical | |
324 | SUBREG. */ | |
325 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
9e6a5703 | 326 | return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0); |
835532b8 RK |
327 | |
328 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
329 | part to OP. */ | |
330 | ||
331 | result = gen_reg_rtx (mode); | |
c41c1387 | 332 | emit_clobber (result); |
835532b8 RK |
333 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
334 | return result; | |
335 | } | |
336 | \f | |
71d46ca5 MM |
337 | /* Return the optab used for computing the operation given by the tree code, |
338 | CODE and the tree EXP. This function is not always usable (for example, it | |
339 | cannot give complete results for multiplication or division) but probably | |
340 | ought to be relied on more widely throughout the expander. */ | |
26277d41 | 341 | optab |
71d46ca5 MM |
342 | optab_for_tree_code (enum tree_code code, const_tree type, |
343 | enum optab_subtype subtype) | |
26277d41 PB |
344 | { |
345 | bool trapv; | |
346 | switch (code) | |
347 | { | |
348 | case BIT_AND_EXPR: | |
349 | return and_optab; | |
350 | ||
351 | case BIT_IOR_EXPR: | |
352 | return ior_optab; | |
353 | ||
354 | case BIT_NOT_EXPR: | |
355 | return one_cmpl_optab; | |
356 | ||
357 | case BIT_XOR_EXPR: | |
358 | return xor_optab; | |
359 | ||
360 | case TRUNC_MOD_EXPR: | |
361 | case CEIL_MOD_EXPR: | |
362 | case FLOOR_MOD_EXPR: | |
363 | case ROUND_MOD_EXPR: | |
364 | return TYPE_UNSIGNED (type) ? umod_optab : smod_optab; | |
365 | ||
366 | case RDIV_EXPR: | |
367 | case TRUNC_DIV_EXPR: | |
368 | case CEIL_DIV_EXPR: | |
369 | case FLOOR_DIV_EXPR: | |
370 | case ROUND_DIV_EXPR: | |
371 | case EXACT_DIV_EXPR: | |
0f996086 CF |
372 | if (TYPE_SATURATING(type)) |
373 | return TYPE_UNSIGNED(type) ? usdiv_optab : ssdiv_optab; | |
26277d41 PB |
374 | return TYPE_UNSIGNED (type) ? udiv_optab : sdiv_optab; |
375 | ||
376 | case LSHIFT_EXPR: | |
71d46ca5 MM |
377 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
378 | { | |
379 | if (subtype == optab_vector) | |
380 | return TYPE_SATURATING (type) ? NULL : vashl_optab; | |
381 | ||
382 | gcc_assert (subtype == optab_scalar); | |
383 | } | |
0f996086 CF |
384 | if (TYPE_SATURATING(type)) |
385 | return TYPE_UNSIGNED(type) ? usashl_optab : ssashl_optab; | |
26277d41 PB |
386 | return ashl_optab; |
387 | ||
388 | case RSHIFT_EXPR: | |
71d46ca5 MM |
389 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
390 | { | |
391 | if (subtype == optab_vector) | |
392 | return TYPE_UNSIGNED (type) ? vlshr_optab : vashr_optab; | |
393 | ||
394 | gcc_assert (subtype == optab_scalar); | |
395 | } | |
26277d41 PB |
396 | return TYPE_UNSIGNED (type) ? lshr_optab : ashr_optab; |
397 | ||
398 | case LROTATE_EXPR: | |
71d46ca5 MM |
399 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
400 | { | |
401 | if (subtype == optab_vector) | |
402 | return vrotl_optab; | |
403 | ||
404 | gcc_assert (subtype == optab_scalar); | |
405 | } | |
26277d41 PB |
406 | return rotl_optab; |
407 | ||
408 | case RROTATE_EXPR: | |
71d46ca5 MM |
409 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
410 | { | |
411 | if (subtype == optab_vector) | |
412 | return vrotr_optab; | |
413 | ||
414 | gcc_assert (subtype == optab_scalar); | |
415 | } | |
26277d41 PB |
416 | return rotr_optab; |
417 | ||
418 | case MAX_EXPR: | |
419 | return TYPE_UNSIGNED (type) ? umax_optab : smax_optab; | |
420 | ||
421 | case MIN_EXPR: | |
422 | return TYPE_UNSIGNED (type) ? umin_optab : smin_optab; | |
423 | ||
7ccf35ed DN |
424 | case REALIGN_LOAD_EXPR: |
425 | return vec_realign_load_optab; | |
426 | ||
20f06221 DN |
427 | case WIDEN_SUM_EXPR: |
428 | return TYPE_UNSIGNED (type) ? usum_widen_optab : ssum_widen_optab; | |
429 | ||
430 | case DOT_PROD_EXPR: | |
431 | return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; | |
432 | ||
61d3cdbb DN |
433 | case REDUC_MAX_EXPR: |
434 | return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; | |
435 | ||
436 | case REDUC_MIN_EXPR: | |
437 | return TYPE_UNSIGNED (type) ? reduc_umin_optab : reduc_smin_optab; | |
438 | ||
439 | case REDUC_PLUS_EXPR: | |
a6b46ba2 DN |
440 | return TYPE_UNSIGNED (type) ? reduc_uplus_optab : reduc_splus_optab; |
441 | ||
442 | case VEC_LSHIFT_EXPR: | |
443 | return vec_shl_optab; | |
444 | ||
445 | case VEC_RSHIFT_EXPR: | |
446 | return vec_shr_optab; | |
61d3cdbb | 447 | |
89d67cca DN |
448 | case VEC_WIDEN_MULT_HI_EXPR: |
449 | return TYPE_UNSIGNED (type) ? | |
450 | vec_widen_umult_hi_optab : vec_widen_smult_hi_optab; | |
451 | ||
452 | case VEC_WIDEN_MULT_LO_EXPR: | |
453 | return TYPE_UNSIGNED (type) ? | |
454 | vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; | |
455 | ||
456 | case VEC_UNPACK_HI_EXPR: | |
8115817b | 457 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
458 | vec_unpacku_hi_optab : vec_unpacks_hi_optab; |
459 | ||
460 | case VEC_UNPACK_LO_EXPR: | |
461 | return TYPE_UNSIGNED (type) ? | |
462 | vec_unpacku_lo_optab : vec_unpacks_lo_optab; | |
463 | ||
d9987fb4 UB |
464 | case VEC_UNPACK_FLOAT_HI_EXPR: |
465 | /* The signedness is determined from input operand. */ | |
466 | return TYPE_UNSIGNED (type) ? | |
467 | vec_unpacku_float_hi_optab : vec_unpacks_float_hi_optab; | |
468 | ||
469 | case VEC_UNPACK_FLOAT_LO_EXPR: | |
470 | /* The signedness is determined from input operand. */ | |
471 | return TYPE_UNSIGNED (type) ? | |
472 | vec_unpacku_float_lo_optab : vec_unpacks_float_lo_optab; | |
473 | ||
8115817b UB |
474 | case VEC_PACK_TRUNC_EXPR: |
475 | return vec_pack_trunc_optab; | |
476 | ||
89d67cca DN |
477 | case VEC_PACK_SAT_EXPR: |
478 | return TYPE_UNSIGNED (type) ? vec_pack_usat_optab : vec_pack_ssat_optab; | |
8115817b | 479 | |
d9987fb4 | 480 | case VEC_PACK_FIX_TRUNC_EXPR: |
9f106823 | 481 | /* The signedness is determined from output operand. */ |
d9987fb4 UB |
482 | return TYPE_UNSIGNED (type) ? |
483 | vec_pack_ufix_trunc_optab : vec_pack_sfix_trunc_optab; | |
484 | ||
26277d41 PB |
485 | default: |
486 | break; | |
487 | } | |
488 | ||
eeef0e45 | 489 | trapv = INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_TRAPS (type); |
26277d41 PB |
490 | switch (code) |
491 | { | |
5be014d5 | 492 | case POINTER_PLUS_EXPR: |
26277d41 | 493 | case PLUS_EXPR: |
0f996086 CF |
494 | if (TYPE_SATURATING(type)) |
495 | return TYPE_UNSIGNED(type) ? usadd_optab : ssadd_optab; | |
26277d41 PB |
496 | return trapv ? addv_optab : add_optab; |
497 | ||
498 | case MINUS_EXPR: | |
0f996086 CF |
499 | if (TYPE_SATURATING(type)) |
500 | return TYPE_UNSIGNED(type) ? ussub_optab : sssub_optab; | |
26277d41 PB |
501 | return trapv ? subv_optab : sub_optab; |
502 | ||
503 | case MULT_EXPR: | |
0f996086 CF |
504 | if (TYPE_SATURATING(type)) |
505 | return TYPE_UNSIGNED(type) ? usmul_optab : ssmul_optab; | |
26277d41 PB |
506 | return trapv ? smulv_optab : smul_optab; |
507 | ||
508 | case NEGATE_EXPR: | |
0f996086 CF |
509 | if (TYPE_SATURATING(type)) |
510 | return TYPE_UNSIGNED(type) ? usneg_optab : ssneg_optab; | |
26277d41 PB |
511 | return trapv ? negv_optab : neg_optab; |
512 | ||
513 | case ABS_EXPR: | |
514 | return trapv ? absv_optab : abs_optab; | |
515 | ||
98b44b0e IR |
516 | case VEC_EXTRACT_EVEN_EXPR: |
517 | return vec_extract_even_optab; | |
518 | ||
519 | case VEC_EXTRACT_ODD_EXPR: | |
520 | return vec_extract_odd_optab; | |
521 | ||
522 | case VEC_INTERLEAVE_HIGH_EXPR: | |
523 | return vec_interleave_high_optab; | |
524 | ||
525 | case VEC_INTERLEAVE_LOW_EXPR: | |
526 | return vec_interleave_low_optab; | |
527 | ||
26277d41 PB |
528 | default: |
529 | return NULL; | |
530 | } | |
531 | } | |
273a2526 | 532 | \f |
7ccf35ed | 533 | |
20f06221 DN |
534 | /* Expand vector widening operations. |
535 | ||
536 | There are two different classes of operations handled here: | |
537 | 1) Operations whose result is wider than all the arguments to the operation. | |
538 | Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR | |
539 | In this case OP0 and optionally OP1 would be initialized, | |
540 | but WIDE_OP wouldn't (not relevant for this case). | |
541 | 2) Operations whose result is of the same size as the last argument to the | |
542 | operation, but wider than all the other arguments to the operation. | |
543 | Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR. | |
544 | In the case WIDE_OP, OP0 and optionally OP1 would be initialized. | |
545 | ||
546 | E.g, when called to expand the following operations, this is how | |
547 | the arguments will be initialized: | |
548 | nops OP0 OP1 WIDE_OP | |
549 | widening-sum 2 oprnd0 - oprnd1 | |
550 | widening-dot-product 3 oprnd0 oprnd1 oprnd2 | |
551 | widening-mult 2 oprnd0 oprnd1 - | |
552 | type-promotion (vec-unpack) 1 oprnd0 - - */ | |
553 | ||
554 | rtx | |
555 | expand_widen_pattern_expr (tree exp, rtx op0, rtx op1, rtx wide_op, rtx target, | |
556 | int unsignedp) | |
557 | { | |
558 | tree oprnd0, oprnd1, oprnd2; | |
559 | enum machine_mode wmode = 0, tmode0, tmode1 = 0; | |
560 | optab widen_pattern_optab; | |
561 | int icode; | |
562 | enum machine_mode xmode0, xmode1 = 0, wxmode = 0; | |
563 | rtx temp; | |
564 | rtx pat; | |
565 | rtx xop0, xop1, wxop; | |
5039610b | 566 | int nops = TREE_OPERAND_LENGTH (exp); |
20f06221 DN |
567 | |
568 | oprnd0 = TREE_OPERAND (exp, 0); | |
569 | tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); | |
570 | widen_pattern_optab = | |
71d46ca5 | 571 | optab_for_tree_code (TREE_CODE (exp), TREE_TYPE (oprnd0), optab_default); |
166cdb08 | 572 | icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; |
20f06221 DN |
573 | gcc_assert (icode != CODE_FOR_nothing); |
574 | xmode0 = insn_data[icode].operand[1].mode; | |
575 | ||
576 | if (nops >= 2) | |
577 | { | |
578 | oprnd1 = TREE_OPERAND (exp, 1); | |
579 | tmode1 = TYPE_MODE (TREE_TYPE (oprnd1)); | |
580 | xmode1 = insn_data[icode].operand[2].mode; | |
581 | } | |
582 | ||
583 | /* The last operand is of a wider mode than the rest of the operands. */ | |
584 | if (nops == 2) | |
585 | { | |
586 | wmode = tmode1; | |
587 | wxmode = xmode1; | |
588 | } | |
589 | else if (nops == 3) | |
590 | { | |
591 | gcc_assert (tmode1 == tmode0); | |
592 | gcc_assert (op1); | |
593 | oprnd2 = TREE_OPERAND (exp, 2); | |
594 | wmode = TYPE_MODE (TREE_TYPE (oprnd2)); | |
595 | wxmode = insn_data[icode].operand[3].mode; | |
596 | } | |
597 | ||
598 | if (!wide_op) | |
599 | wmode = wxmode = insn_data[icode].operand[0].mode; | |
600 | ||
601 | if (!target | |
602 | || ! (*insn_data[icode].operand[0].predicate) (target, wmode)) | |
603 | temp = gen_reg_rtx (wmode); | |
604 | else | |
605 | temp = target; | |
606 | ||
607 | xop0 = op0; | |
608 | xop1 = op1; | |
609 | wxop = wide_op; | |
610 | ||
611 | /* In case the insn wants input operands in modes different from | |
612 | those of the actual operands, convert the operands. It would | |
613 | seem that we don't need to convert CONST_INTs, but we do, so | |
614 | that they're properly zero-extended, sign-extended or truncated | |
615 | for their mode. */ | |
616 | ||
617 | if (GET_MODE (op0) != xmode0 && xmode0 != VOIDmode) | |
618 | xop0 = convert_modes (xmode0, | |
619 | GET_MODE (op0) != VOIDmode | |
620 | ? GET_MODE (op0) | |
621 | : tmode0, | |
622 | xop0, unsignedp); | |
623 | ||
624 | if (op1) | |
625 | if (GET_MODE (op1) != xmode1 && xmode1 != VOIDmode) | |
626 | xop1 = convert_modes (xmode1, | |
627 | GET_MODE (op1) != VOIDmode | |
628 | ? GET_MODE (op1) | |
629 | : tmode1, | |
630 | xop1, unsignedp); | |
631 | ||
632 | if (wide_op) | |
633 | if (GET_MODE (wide_op) != wxmode && wxmode != VOIDmode) | |
634 | wxop = convert_modes (wxmode, | |
635 | GET_MODE (wide_op) != VOIDmode | |
636 | ? GET_MODE (wide_op) | |
637 | : wmode, | |
638 | wxop, unsignedp); | |
639 | ||
640 | /* Now, if insn's predicates don't allow our operands, put them into | |
641 | pseudo regs. */ | |
642 | ||
643 | if (! (*insn_data[icode].operand[1].predicate) (xop0, xmode0) | |
644 | && xmode0 != VOIDmode) | |
645 | xop0 = copy_to_mode_reg (xmode0, xop0); | |
646 | ||
647 | if (op1) | |
648 | { | |
649 | if (! (*insn_data[icode].operand[2].predicate) (xop1, xmode1) | |
650 | && xmode1 != VOIDmode) | |
651 | xop1 = copy_to_mode_reg (xmode1, xop1); | |
652 | ||
653 | if (wide_op) | |
654 | { | |
655 | if (! (*insn_data[icode].operand[3].predicate) (wxop, wxmode) | |
656 | && wxmode != VOIDmode) | |
657 | wxop = copy_to_mode_reg (wxmode, wxop); | |
658 | ||
659 | pat = GEN_FCN (icode) (temp, xop0, xop1, wxop); | |
660 | } | |
661 | else | |
662 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
663 | } | |
664 | else | |
665 | { | |
666 | if (wide_op) | |
667 | { | |
668 | if (! (*insn_data[icode].operand[2].predicate) (wxop, wxmode) | |
669 | && wxmode != VOIDmode) | |
670 | wxop = copy_to_mode_reg (wxmode, wxop); | |
671 | ||
672 | pat = GEN_FCN (icode) (temp, xop0, wxop); | |
673 | } | |
674 | else | |
675 | pat = GEN_FCN (icode) (temp, xop0); | |
676 | } | |
677 | ||
678 | emit_insn (pat); | |
679 | return temp; | |
680 | } | |
681 | ||
7ccf35ed DN |
682 | /* Generate code to perform an operation specified by TERNARY_OPTAB |
683 | on operands OP0, OP1 and OP2, with result having machine-mode MODE. | |
684 | ||
685 | UNSIGNEDP is for the case where we have to widen the operands | |
686 | to perform the operation. It says to use zero-extension. | |
687 | ||
688 | If TARGET is nonzero, the value | |
689 | is generated there, if it is convenient to do so. | |
690 | In all cases an rtx is returned for the locus of the value; | |
691 | this may or may not be TARGET. */ | |
692 | ||
693 | rtx | |
c414ac1d EC |
694 | expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, |
695 | rtx op1, rtx op2, rtx target, int unsignedp) | |
7ccf35ed | 696 | { |
166cdb08 | 697 | int icode = (int) optab_handler (ternary_optab, mode)->insn_code; |
7ccf35ed DN |
698 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
699 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
700 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
701 | rtx temp; | |
702 | rtx pat; | |
703 | rtx xop0 = op0, xop1 = op1, xop2 = op2; | |
704 | ||
166cdb08 | 705 | gcc_assert (optab_handler (ternary_optab, mode)->insn_code |
e3feb571 | 706 | != CODE_FOR_nothing); |
7ccf35ed | 707 | |
e3feb571 | 708 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) |
7ccf35ed DN |
709 | temp = gen_reg_rtx (mode); |
710 | else | |
711 | temp = target; | |
712 | ||
713 | /* In case the insn wants input operands in modes different from | |
714 | those of the actual operands, convert the operands. It would | |
715 | seem that we don't need to convert CONST_INTs, but we do, so | |
716 | that they're properly zero-extended, sign-extended or truncated | |
717 | for their mode. */ | |
718 | ||
719 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) | |
720 | xop0 = convert_modes (mode0, | |
721 | GET_MODE (op0) != VOIDmode | |
c414ac1d | 722 | ? GET_MODE (op0) |
7ccf35ed DN |
723 | : mode, |
724 | xop0, unsignedp); | |
725 | ||
726 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
727 | xop1 = convert_modes (mode1, | |
728 | GET_MODE (op1) != VOIDmode | |
729 | ? GET_MODE (op1) | |
730 | : mode, | |
731 | xop1, unsignedp); | |
732 | ||
733 | if (GET_MODE (op2) != mode2 && mode2 != VOIDmode) | |
734 | xop2 = convert_modes (mode2, | |
735 | GET_MODE (op2) != VOIDmode | |
736 | ? GET_MODE (op2) | |
737 | : mode, | |
738 | xop2, unsignedp); | |
739 | ||
740 | /* Now, if insn's predicates don't allow our operands, put them into | |
741 | pseudo regs. */ | |
c414ac1d | 742 | |
e3feb571 | 743 | if (!insn_data[icode].operand[1].predicate (xop0, mode0) |
c414ac1d | 744 | && mode0 != VOIDmode) |
7ccf35ed | 745 | xop0 = copy_to_mode_reg (mode0, xop0); |
c414ac1d | 746 | |
e3feb571 | 747 | if (!insn_data[icode].operand[2].predicate (xop1, mode1) |
7ccf35ed DN |
748 | && mode1 != VOIDmode) |
749 | xop1 = copy_to_mode_reg (mode1, xop1); | |
c414ac1d | 750 | |
e3feb571 | 751 | if (!insn_data[icode].operand[3].predicate (xop2, mode2) |
7ccf35ed DN |
752 | && mode2 != VOIDmode) |
753 | xop2 = copy_to_mode_reg (mode2, xop2); | |
c414ac1d | 754 | |
7ccf35ed | 755 | pat = GEN_FCN (icode) (temp, xop0, xop1, xop2); |
c414ac1d | 756 | |
7ccf35ed | 757 | emit_insn (pat); |
c414ac1d | 758 | return temp; |
7ccf35ed DN |
759 | } |
760 | ||
761 | ||
273a2526 RS |
762 | /* Like expand_binop, but return a constant rtx if the result can be |
763 | calculated at compile time. The arguments and return value are | |
764 | otherwise the same as for expand_binop. */ | |
765 | ||
766 | static rtx | |
767 | simplify_expand_binop (enum machine_mode mode, optab binoptab, | |
768 | rtx op0, rtx op1, rtx target, int unsignedp, | |
769 | enum optab_methods methods) | |
770 | { | |
771 | if (CONSTANT_P (op0) && CONSTANT_P (op1)) | |
68162a97 ILT |
772 | { |
773 | rtx x = simplify_binary_operation (binoptab->code, mode, op0, op1); | |
774 | ||
775 | if (x) | |
776 | return x; | |
777 | } | |
778 | ||
779 | return expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods); | |
273a2526 RS |
780 | } |
781 | ||
782 | /* Like simplify_expand_binop, but always put the result in TARGET. | |
783 | Return true if the expansion succeeded. */ | |
784 | ||
bef5d8b6 | 785 | bool |
273a2526 RS |
786 | force_expand_binop (enum machine_mode mode, optab binoptab, |
787 | rtx op0, rtx op1, rtx target, int unsignedp, | |
788 | enum optab_methods methods) | |
789 | { | |
790 | rtx x = simplify_expand_binop (mode, binoptab, op0, op1, | |
791 | target, unsignedp, methods); | |
792 | if (x == 0) | |
793 | return false; | |
794 | if (x != target) | |
795 | emit_move_insn (target, x); | |
796 | return true; | |
797 | } | |
798 | ||
a6b46ba2 DN |
799 | /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */ |
800 | ||
801 | rtx | |
802 | expand_vec_shift_expr (tree vec_shift_expr, rtx target) | |
803 | { | |
804 | enum insn_code icode; | |
805 | rtx rtx_op1, rtx_op2; | |
806 | enum machine_mode mode1; | |
807 | enum machine_mode mode2; | |
808 | enum machine_mode mode = TYPE_MODE (TREE_TYPE (vec_shift_expr)); | |
809 | tree vec_oprnd = TREE_OPERAND (vec_shift_expr, 0); | |
810 | tree shift_oprnd = TREE_OPERAND (vec_shift_expr, 1); | |
811 | optab shift_optab; | |
812 | rtx pat; | |
813 | ||
814 | switch (TREE_CODE (vec_shift_expr)) | |
815 | { | |
816 | case VEC_RSHIFT_EXPR: | |
817 | shift_optab = vec_shr_optab; | |
818 | break; | |
819 | case VEC_LSHIFT_EXPR: | |
820 | shift_optab = vec_shl_optab; | |
821 | break; | |
822 | default: | |
823 | gcc_unreachable (); | |
824 | } | |
825 | ||
166cdb08 | 826 | icode = (int) optab_handler (shift_optab, mode)->insn_code; |
a6b46ba2 DN |
827 | gcc_assert (icode != CODE_FOR_nothing); |
828 | ||
829 | mode1 = insn_data[icode].operand[1].mode; | |
830 | mode2 = insn_data[icode].operand[2].mode; | |
831 | ||
49452c07 | 832 | rtx_op1 = expand_normal (vec_oprnd); |
a6b46ba2 DN |
833 | if (!(*insn_data[icode].operand[1].predicate) (rtx_op1, mode1) |
834 | && mode1 != VOIDmode) | |
835 | rtx_op1 = force_reg (mode1, rtx_op1); | |
836 | ||
49452c07 | 837 | rtx_op2 = expand_normal (shift_oprnd); |
a6b46ba2 DN |
838 | if (!(*insn_data[icode].operand[2].predicate) (rtx_op2, mode2) |
839 | && mode2 != VOIDmode) | |
840 | rtx_op2 = force_reg (mode2, rtx_op2); | |
841 | ||
842 | if (!target | |
843 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
844 | target = gen_reg_rtx (mode); | |
845 | ||
846 | /* Emit instruction */ | |
847 | pat = GEN_FCN (icode) (target, rtx_op1, rtx_op2); | |
848 | gcc_assert (pat); | |
849 | emit_insn (pat); | |
850 | ||
851 | return target; | |
852 | } | |
853 | ||
273a2526 RS |
854 | /* This subroutine of expand_doubleword_shift handles the cases in which |
855 | the effective shift value is >= BITS_PER_WORD. The arguments and return | |
856 | value are the same as for the parent routine, except that SUPERWORD_OP1 | |
857 | is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET. | |
858 | INTO_TARGET may be null if the caller has decided to calculate it. */ | |
859 | ||
860 | static bool | |
861 | expand_superword_shift (optab binoptab, rtx outof_input, rtx superword_op1, | |
862 | rtx outof_target, rtx into_target, | |
863 | int unsignedp, enum optab_methods methods) | |
864 | { | |
865 | if (into_target != 0) | |
866 | if (!force_expand_binop (word_mode, binoptab, outof_input, superword_op1, | |
867 | into_target, unsignedp, methods)) | |
868 | return false; | |
869 | ||
870 | if (outof_target != 0) | |
871 | { | |
872 | /* For a signed right shift, we must fill OUTOF_TARGET with copies | |
873 | of the sign bit, otherwise we must fill it with zeros. */ | |
874 | if (binoptab != ashr_optab) | |
875 | emit_move_insn (outof_target, CONST0_RTX (word_mode)); | |
876 | else | |
877 | if (!force_expand_binop (word_mode, binoptab, | |
878 | outof_input, GEN_INT (BITS_PER_WORD - 1), | |
879 | outof_target, unsignedp, methods)) | |
880 | return false; | |
881 | } | |
882 | return true; | |
883 | } | |
884 | ||
885 | /* This subroutine of expand_doubleword_shift handles the cases in which | |
886 | the effective shift value is < BITS_PER_WORD. The arguments and return | |
887 | value are the same as for the parent routine. */ | |
888 | ||
889 | static bool | |
890 | expand_subword_shift (enum machine_mode op1_mode, optab binoptab, | |
891 | rtx outof_input, rtx into_input, rtx op1, | |
892 | rtx outof_target, rtx into_target, | |
893 | int unsignedp, enum optab_methods methods, | |
894 | unsigned HOST_WIDE_INT shift_mask) | |
895 | { | |
896 | optab reverse_unsigned_shift, unsigned_shift; | |
897 | rtx tmp, carries; | |
898 | ||
899 | reverse_unsigned_shift = (binoptab == ashl_optab ? lshr_optab : ashl_optab); | |
900 | unsigned_shift = (binoptab == ashl_optab ? ashl_optab : lshr_optab); | |
901 | ||
902 | /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT. | |
903 | We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in | |
904 | the opposite direction to BINOPTAB. */ | |
905 | if (CONSTANT_P (op1) || shift_mask >= BITS_PER_WORD) | |
906 | { | |
907 | carries = outof_input; | |
908 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
909 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
910 | 0, true, methods); | |
911 | } | |
912 | else | |
913 | { | |
914 | /* We must avoid shifting by BITS_PER_WORD bits since that is either | |
915 | the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or | |
b01d837f | 916 | has unknown behavior. Do a single shift first, then shift by the |
273a2526 RS |
917 | remainder. It's OK to use ~OP1 as the remainder if shift counts |
918 | are truncated to the mode size. */ | |
919 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
920 | outof_input, const1_rtx, 0, unsignedp, methods); | |
921 | if (shift_mask == BITS_PER_WORD - 1) | |
922 | { | |
923 | tmp = immed_double_const (-1, -1, op1_mode); | |
924 | tmp = simplify_expand_binop (op1_mode, xor_optab, op1, tmp, | |
925 | 0, true, methods); | |
926 | } | |
927 | else | |
928 | { | |
929 | tmp = immed_double_const (BITS_PER_WORD - 1, 0, op1_mode); | |
930 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
931 | 0, true, methods); | |
932 | } | |
933 | } | |
934 | if (tmp == 0 || carries == 0) | |
935 | return false; | |
936 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
937 | carries, tmp, 0, unsignedp, methods); | |
938 | if (carries == 0) | |
939 | return false; | |
940 | ||
941 | /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT | |
942 | so the result can go directly into INTO_TARGET if convenient. */ | |
943 | tmp = expand_binop (word_mode, unsigned_shift, into_input, op1, | |
944 | into_target, unsignedp, methods); | |
945 | if (tmp == 0) | |
946 | return false; | |
947 | ||
948 | /* Now OR in the bits carried over from OUTOF_INPUT. */ | |
949 | if (!force_expand_binop (word_mode, ior_optab, tmp, carries, | |
950 | into_target, unsignedp, methods)) | |
951 | return false; | |
952 | ||
953 | /* Use a standard word_mode shift for the out-of half. */ | |
954 | if (outof_target != 0) | |
955 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
956 | outof_target, unsignedp, methods)) | |
957 | return false; | |
958 | ||
959 | return true; | |
960 | } | |
961 | ||
962 | ||
963 | #ifdef HAVE_conditional_move | |
964 | /* Try implementing expand_doubleword_shift using conditional moves. | |
965 | The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true, | |
966 | otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1 | |
967 | are the shift counts to use in the former and latter case. All other | |
968 | arguments are the same as the parent routine. */ | |
969 | ||
970 | static bool | |
971 | expand_doubleword_shift_condmove (enum machine_mode op1_mode, optab binoptab, | |
972 | enum rtx_code cmp_code, rtx cmp1, rtx cmp2, | |
973 | rtx outof_input, rtx into_input, | |
974 | rtx subword_op1, rtx superword_op1, | |
975 | rtx outof_target, rtx into_target, | |
976 | int unsignedp, enum optab_methods methods, | |
977 | unsigned HOST_WIDE_INT shift_mask) | |
978 | { | |
979 | rtx outof_superword, into_superword; | |
980 | ||
981 | /* Put the superword version of the output into OUTOF_SUPERWORD and | |
982 | INTO_SUPERWORD. */ | |
983 | outof_superword = outof_target != 0 ? gen_reg_rtx (word_mode) : 0; | |
984 | if (outof_target != 0 && subword_op1 == superword_op1) | |
985 | { | |
986 | /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in | |
987 | OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */ | |
988 | into_superword = outof_target; | |
989 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
990 | outof_superword, 0, unsignedp, methods)) | |
991 | return false; | |
992 | } | |
993 | else | |
994 | { | |
995 | into_superword = gen_reg_rtx (word_mode); | |
996 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
997 | outof_superword, into_superword, | |
998 | unsignedp, methods)) | |
999 | return false; | |
1000 | } | |
26277d41 | 1001 | |
273a2526 RS |
1002 | /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */ |
1003 | if (!expand_subword_shift (op1_mode, binoptab, | |
1004 | outof_input, into_input, subword_op1, | |
1005 | outof_target, into_target, | |
1006 | unsignedp, methods, shift_mask)) | |
1007 | return false; | |
1008 | ||
1009 | /* Select between them. Do the INTO half first because INTO_SUPERWORD | |
1010 | might be the current value of OUTOF_TARGET. */ | |
1011 | if (!emit_conditional_move (into_target, cmp_code, cmp1, cmp2, op1_mode, | |
1012 | into_target, into_superword, word_mode, false)) | |
1013 | return false; | |
1014 | ||
1015 | if (outof_target != 0) | |
1016 | if (!emit_conditional_move (outof_target, cmp_code, cmp1, cmp2, op1_mode, | |
1017 | outof_target, outof_superword, | |
1018 | word_mode, false)) | |
1019 | return false; | |
1020 | ||
1021 | return true; | |
1022 | } | |
1023 | #endif | |
1024 | ||
1025 | /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts. | |
1026 | OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first | |
1027 | input operand; the shift moves bits in the direction OUTOF_INPUT-> | |
1028 | INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words | |
1029 | of the target. OP1 is the shift count and OP1_MODE is its mode. | |
1030 | If OP1 is constant, it will have been truncated as appropriate | |
1031 | and is known to be nonzero. | |
1032 | ||
1033 | If SHIFT_MASK is zero, the result of word shifts is undefined when the | |
1034 | shift count is outside the range [0, BITS_PER_WORD). This routine must | |
1035 | avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2). | |
1036 | ||
1037 | If SHIFT_MASK is nonzero, all word-mode shift counts are effectively | |
1038 | masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will | |
1039 | fill with zeros or sign bits as appropriate. | |
1040 | ||
2a7e31df | 1041 | If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize |
273a2526 RS |
1042 | a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1. |
1043 | Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED. | |
1044 | In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2) | |
1045 | are undefined. | |
1046 | ||
1047 | BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function | |
1048 | may not use INTO_INPUT after modifying INTO_TARGET, and similarly for | |
1049 | OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent | |
1050 | function wants to calculate it itself. | |
1051 | ||
1052 | Return true if the shift could be successfully synthesized. */ | |
1053 | ||
1054 | static bool | |
1055 | expand_doubleword_shift (enum machine_mode op1_mode, optab binoptab, | |
1056 | rtx outof_input, rtx into_input, rtx op1, | |
1057 | rtx outof_target, rtx into_target, | |
1058 | int unsignedp, enum optab_methods methods, | |
1059 | unsigned HOST_WIDE_INT shift_mask) | |
1060 | { | |
1061 | rtx superword_op1, tmp, cmp1, cmp2; | |
1062 | rtx subword_label, done_label; | |
1063 | enum rtx_code cmp_code; | |
1064 | ||
1065 | /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will | |
1066 | fill the result with sign or zero bits as appropriate. If so, the value | |
1067 | of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call | |
1068 | this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT | |
1069 | and INTO_INPUT), then emit code to set up OUTOF_TARGET. | |
1070 | ||
1071 | This isn't worthwhile for constant shifts since the optimizers will | |
1072 | cope better with in-range shift counts. */ | |
1073 | if (shift_mask >= BITS_PER_WORD | |
1074 | && outof_target != 0 | |
1075 | && !CONSTANT_P (op1)) | |
1076 | { | |
1077 | if (!expand_doubleword_shift (op1_mode, binoptab, | |
1078 | outof_input, into_input, op1, | |
1079 | 0, into_target, | |
1080 | unsignedp, methods, shift_mask)) | |
1081 | return false; | |
1082 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
1083 | outof_target, unsignedp, methods)) | |
1084 | return false; | |
1085 | return true; | |
1086 | } | |
1087 | ||
1088 | /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2) | |
1089 | is true when the effective shift value is less than BITS_PER_WORD. | |
1090 | Set SUPERWORD_OP1 to the shift count that should be used to shift | |
1091 | OUTOF_INPUT into INTO_TARGET when the condition is false. */ | |
1092 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
1093 | if (!CONSTANT_P (op1) && shift_mask == BITS_PER_WORD - 1) | |
1094 | { | |
1095 | /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1 | |
1096 | is a subword shift count. */ | |
1097 | cmp1 = simplify_expand_binop (op1_mode, and_optab, op1, tmp, | |
1098 | 0, true, methods); | |
1099 | cmp2 = CONST0_RTX (op1_mode); | |
1100 | cmp_code = EQ; | |
1101 | superword_op1 = op1; | |
1102 | } | |
1103 | else | |
1104 | { | |
1105 | /* Set CMP1 to OP1 - BITS_PER_WORD. */ | |
1106 | cmp1 = simplify_expand_binop (op1_mode, sub_optab, op1, tmp, | |
1107 | 0, true, methods); | |
1108 | cmp2 = CONST0_RTX (op1_mode); | |
1109 | cmp_code = LT; | |
1110 | superword_op1 = cmp1; | |
1111 | } | |
1112 | if (cmp1 == 0) | |
1113 | return false; | |
1114 | ||
1115 | /* If we can compute the condition at compile time, pick the | |
1116 | appropriate subroutine. */ | |
1117 | tmp = simplify_relational_operation (cmp_code, SImode, op1_mode, cmp1, cmp2); | |
1118 | if (tmp != 0 && GET_CODE (tmp) == CONST_INT) | |
1119 | { | |
1120 | if (tmp == const0_rtx) | |
1121 | return expand_superword_shift (binoptab, outof_input, superword_op1, | |
1122 | outof_target, into_target, | |
1123 | unsignedp, methods); | |
1124 | else | |
1125 | return expand_subword_shift (op1_mode, binoptab, | |
1126 | outof_input, into_input, op1, | |
1127 | outof_target, into_target, | |
1128 | unsignedp, methods, shift_mask); | |
1129 | } | |
1130 | ||
1131 | #ifdef HAVE_conditional_move | |
1132 | /* Try using conditional moves to generate straight-line code. */ | |
1133 | { | |
1134 | rtx start = get_last_insn (); | |
1135 | if (expand_doubleword_shift_condmove (op1_mode, binoptab, | |
1136 | cmp_code, cmp1, cmp2, | |
1137 | outof_input, into_input, | |
1138 | op1, superword_op1, | |
1139 | outof_target, into_target, | |
1140 | unsignedp, methods, shift_mask)) | |
1141 | return true; | |
1142 | delete_insns_since (start); | |
1143 | } | |
1144 | #endif | |
1145 | ||
1146 | /* As a last resort, use branches to select the correct alternative. */ | |
1147 | subword_label = gen_label_rtx (); | |
1148 | done_label = gen_label_rtx (); | |
1149 | ||
2763a67e | 1150 | NO_DEFER_POP; |
273a2526 RS |
1151 | do_compare_rtx_and_jump (cmp1, cmp2, cmp_code, false, op1_mode, |
1152 | 0, 0, subword_label); | |
2763a67e | 1153 | OK_DEFER_POP; |
273a2526 RS |
1154 | |
1155 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
1156 | outof_target, into_target, | |
1157 | unsignedp, methods)) | |
1158 | return false; | |
1159 | ||
1160 | emit_jump_insn (gen_jump (done_label)); | |
1161 | emit_barrier (); | |
1162 | emit_label (subword_label); | |
1163 | ||
1164 | if (!expand_subword_shift (op1_mode, binoptab, | |
1165 | outof_input, into_input, op1, | |
1166 | outof_target, into_target, | |
1167 | unsignedp, methods, shift_mask)) | |
1168 | return false; | |
1169 | ||
1170 | emit_label (done_label); | |
1171 | return true; | |
1172 | } | |
c64f913e | 1173 | \f |
f927760b RS |
1174 | /* Subroutine of expand_binop. Perform a double word multiplication of |
1175 | operands OP0 and OP1 both of mode MODE, which is exactly twice as wide | |
1176 | as the target's word_mode. This function return NULL_RTX if anything | |
1177 | goes wrong, in which case it may have already emitted instructions | |
1178 | which need to be deleted. | |
1179 | ||
1180 | If we want to multiply two two-word values and have normal and widening | |
1181 | multiplies of single-word values, we can do this with three smaller | |
d70dcf29 | 1182 | multiplications. |
f927760b RS |
1183 | |
1184 | The multiplication proceeds as follows: | |
1185 | _______________________ | |
1186 | [__op0_high_|__op0_low__] | |
1187 | _______________________ | |
1188 | * [__op1_high_|__op1_low__] | |
1189 | _______________________________________________ | |
1190 | _______________________ | |
1191 | (1) [__op0_low__*__op1_low__] | |
1192 | _______________________ | |
1193 | (2a) [__op0_low__*__op1_high_] | |
1194 | _______________________ | |
1195 | (2b) [__op0_high_*__op1_low__] | |
1196 | _______________________ | |
1197 | (3) [__op0_high_*__op1_high_] | |
1198 | ||
1199 | ||
1200 | This gives a 4-word result. Since we are only interested in the | |
1201 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1202 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1203 | calculated using non-widening multiplication. | |
1204 | ||
1205 | (1), however, needs to be calculated with an unsigned widening | |
1206 | multiplication. If this operation is not directly supported we | |
1207 | try using a signed widening multiplication and adjust the result. | |
1208 | This adjustment works as follows: | |
1209 | ||
1210 | If both operands are positive then no adjustment is needed. | |
1211 | ||
1212 | If the operands have different signs, for example op0_low < 0 and | |
1213 | op1_low >= 0, the instruction treats the most significant bit of | |
1214 | op0_low as a sign bit instead of a bit with significance | |
1215 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1216 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1217 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1218 | the result. | |
1219 | ||
1220 | Similarly, if both operands are negative, we need to add | |
1221 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1222 | ||
1223 | We use a trick to adjust quickly. We logically shift op0_low right | |
1224 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1225 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1226 | logical shift exists, we do an arithmetic right shift and subtract | |
1227 | the 0 or -1. */ | |
1228 | ||
1229 | static rtx | |
1230 | expand_doubleword_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
1231 | bool umulp, enum optab_methods methods) | |
1232 | { | |
1233 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1234 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1235 | rtx wordm1 = umulp ? NULL_RTX : GEN_INT (BITS_PER_WORD - 1); | |
1236 | rtx product, adjust, product_high, temp; | |
1237 | ||
1238 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1239 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1240 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1241 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1242 | ||
1243 | /* If we're using an unsigned multiply to directly compute the product | |
1244 | of the low-order words of the operands and perform any required | |
1245 | adjustments of the operands, we begin by trying two more multiplications | |
1246 | and then computing the appropriate sum. | |
1247 | ||
1248 | We have checked above that the required addition is provided. | |
1249 | Full-word addition will normally always succeed, especially if | |
1250 | it is provided at all, so we don't worry about its failure. The | |
1251 | multiplication may well fail, however, so we do handle that. */ | |
1252 | ||
1253 | if (!umulp) | |
1254 | { | |
1255 | /* ??? This could be done with emit_store_flag where available. */ | |
1256 | temp = expand_binop (word_mode, lshr_optab, op0_low, wordm1, | |
1257 | NULL_RTX, 1, methods); | |
1258 | if (temp) | |
1259 | op0_high = expand_binop (word_mode, add_optab, op0_high, temp, | |
69f39b11 | 1260 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1261 | else |
1262 | { | |
1263 | temp = expand_binop (word_mode, ashr_optab, op0_low, wordm1, | |
1264 | NULL_RTX, 0, methods); | |
1265 | if (!temp) | |
1266 | return NULL_RTX; | |
1267 | op0_high = expand_binop (word_mode, sub_optab, op0_high, temp, | |
69f39b11 | 1268 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1269 | } |
1270 | ||
1271 | if (!op0_high) | |
1272 | return NULL_RTX; | |
1273 | } | |
1274 | ||
1275 | adjust = expand_binop (word_mode, smul_optab, op0_high, op1_low, | |
1276 | NULL_RTX, 0, OPTAB_DIRECT); | |
1277 | if (!adjust) | |
1278 | return NULL_RTX; | |
1279 | ||
1280 | /* OP0_HIGH should now be dead. */ | |
1281 | ||
1282 | if (!umulp) | |
1283 | { | |
1284 | /* ??? This could be done with emit_store_flag where available. */ | |
1285 | temp = expand_binop (word_mode, lshr_optab, op1_low, wordm1, | |
1286 | NULL_RTX, 1, methods); | |
1287 | if (temp) | |
1288 | op1_high = expand_binop (word_mode, add_optab, op1_high, temp, | |
69f39b11 | 1289 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1290 | else |
1291 | { | |
1292 | temp = expand_binop (word_mode, ashr_optab, op1_low, wordm1, | |
1293 | NULL_RTX, 0, methods); | |
1294 | if (!temp) | |
1295 | return NULL_RTX; | |
1296 | op1_high = expand_binop (word_mode, sub_optab, op1_high, temp, | |
69f39b11 | 1297 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1298 | } |
1299 | ||
1300 | if (!op1_high) | |
1301 | return NULL_RTX; | |
1302 | } | |
1303 | ||
1304 | temp = expand_binop (word_mode, smul_optab, op1_high, op0_low, | |
1305 | NULL_RTX, 0, OPTAB_DIRECT); | |
1306 | if (!temp) | |
1307 | return NULL_RTX; | |
1308 | ||
1309 | /* OP1_HIGH should now be dead. */ | |
1310 | ||
1311 | adjust = expand_binop (word_mode, add_optab, adjust, temp, | |
1312 | adjust, 0, OPTAB_DIRECT); | |
1313 | ||
1314 | if (target && !REG_P (target)) | |
1315 | target = NULL_RTX; | |
1316 | ||
1317 | if (umulp) | |
1318 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1319 | target, 1, OPTAB_DIRECT); | |
1320 | else | |
1321 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, | |
1322 | target, 1, OPTAB_DIRECT); | |
1323 | ||
1324 | if (!product) | |
1325 | return NULL_RTX; | |
1326 | ||
1327 | product_high = operand_subword (product, high, 1, mode); | |
1328 | adjust = expand_binop (word_mode, add_optab, product_high, adjust, | |
1329 | REG_P (product_high) ? product_high : adjust, | |
1330 | 0, OPTAB_DIRECT); | |
1331 | emit_move_insn (product_high, adjust); | |
1332 | return product; | |
1333 | } | |
1334 | \f | |
ef89d648 ZW |
1335 | /* Wrapper around expand_binop which takes an rtx code to specify |
1336 | the operation to perform, not an optab pointer. All other | |
1337 | arguments are the same. */ | |
1338 | rtx | |
0c20a65f AJ |
1339 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
1340 | rtx op1, rtx target, int unsignedp, | |
1341 | enum optab_methods methods) | |
ef89d648 | 1342 | { |
7e1a450d | 1343 | optab binop = code_to_optab[(int) code]; |
e3feb571 | 1344 | gcc_assert (binop); |
ef89d648 ZW |
1345 | |
1346 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
1347 | } | |
1348 | ||
665d18c6 PB |
1349 | /* Return whether OP0 and OP1 should be swapped when expanding a commutative |
1350 | binop. Order them according to commutative_operand_precedence and, if | |
1351 | possible, try to put TARGET or a pseudo first. */ | |
1352 | static bool | |
1353 | swap_commutative_operands_with_target (rtx target, rtx op0, rtx op1) | |
1354 | { | |
1355 | int op0_prec = commutative_operand_precedence (op0); | |
1356 | int op1_prec = commutative_operand_precedence (op1); | |
1357 | ||
1358 | if (op0_prec < op1_prec) | |
1359 | return true; | |
1360 | ||
1361 | if (op0_prec > op1_prec) | |
1362 | return false; | |
1363 | ||
1364 | /* With equal precedence, both orders are ok, but it is better if the | |
1365 | first operand is TARGET, or if both TARGET and OP0 are pseudos. */ | |
1366 | if (target == 0 || REG_P (target)) | |
1367 | return (REG_P (op1) && !REG_P (op0)) || target == op1; | |
1368 | else | |
1369 | return rtx_equal_p (op1, target); | |
1370 | } | |
1371 | ||
62442ab9 RS |
1372 | /* Return true if BINOPTAB implements a shift operation. */ |
1373 | ||
1374 | static bool | |
1375 | shift_optab_p (optab binoptab) | |
1376 | { | |
1377 | switch (binoptab->code) | |
1378 | { | |
1379 | case ASHIFT: | |
0f996086 CF |
1380 | case SS_ASHIFT: |
1381 | case US_ASHIFT: | |
62442ab9 RS |
1382 | case ASHIFTRT: |
1383 | case LSHIFTRT: | |
1384 | case ROTATE: | |
1385 | case ROTATERT: | |
1386 | return true; | |
1387 | ||
1388 | default: | |
1389 | return false; | |
1390 | } | |
1391 | } | |
1392 | ||
15dc95cb | 1393 | /* Return true if BINOPTAB implements a commutative binary operation. */ |
62442ab9 RS |
1394 | |
1395 | static bool | |
1396 | commutative_optab_p (optab binoptab) | |
1397 | { | |
1398 | return (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH | |
1399 | || binoptab == smul_widen_optab | |
1400 | || binoptab == umul_widen_optab | |
1401 | || binoptab == smul_highpart_optab | |
1402 | || binoptab == umul_highpart_optab); | |
1403 | } | |
1404 | ||
1405 | /* X is to be used in mode MODE as an operand to BINOPTAB. If we're | |
1406 | optimizing, and if the operand is a constant that costs more than | |
1407 | 1 instruction, force the constant into a register and return that | |
1408 | register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */ | |
1409 | ||
1410 | static rtx | |
1411 | avoid_expensive_constant (enum machine_mode mode, optab binoptab, | |
1412 | rtx x, bool unsignedp) | |
1413 | { | |
47de45c6 RS |
1414 | if (mode != VOIDmode |
1415 | && optimize | |
62442ab9 RS |
1416 | && CONSTANT_P (x) |
1417 | && rtx_cost (x, binoptab->code) > COSTS_N_INSNS (1)) | |
1418 | { | |
c722c7da RS |
1419 | if (GET_CODE (x) == CONST_INT) |
1420 | { | |
1421 | HOST_WIDE_INT intval = trunc_int_for_mode (INTVAL (x), mode); | |
1422 | if (intval != INTVAL (x)) | |
1423 | x = GEN_INT (intval); | |
1424 | } | |
1425 | else | |
62442ab9 RS |
1426 | x = convert_modes (mode, VOIDmode, x, unsignedp); |
1427 | x = force_reg (mode, x); | |
1428 | } | |
1429 | return x; | |
1430 | } | |
665d18c6 | 1431 | |
0aa222d1 SL |
1432 | /* Helper function for expand_binop: handle the case where there |
1433 | is an insn that directly implements the indicated operation. | |
1434 | Returns null if this is not possible. */ | |
1435 | static rtx | |
1436 | expand_binop_directly (enum machine_mode mode, optab binoptab, | |
1437 | rtx op0, rtx op1, | |
1438 | rtx target, int unsignedp, enum optab_methods methods, | |
62442ab9 | 1439 | rtx last) |
0aa222d1 | 1440 | { |
166cdb08 | 1441 | int icode = (int) optab_handler (binoptab, mode)->insn_code; |
0aa222d1 SL |
1442 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
1443 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
1444 | enum machine_mode tmp_mode; | |
62442ab9 | 1445 | bool commutative_p; |
0aa222d1 SL |
1446 | rtx pat; |
1447 | rtx xop0 = op0, xop1 = op1; | |
1448 | rtx temp; | |
62442ab9 | 1449 | rtx swap; |
0aa222d1 SL |
1450 | |
1451 | if (target) | |
1452 | temp = target; | |
1453 | else | |
1454 | temp = gen_reg_rtx (mode); | |
62442ab9 | 1455 | |
0aa222d1 SL |
1456 | /* If it is a commutative operator and the modes would match |
1457 | if we would swap the operands, we can save the conversions. */ | |
62442ab9 RS |
1458 | commutative_p = commutative_optab_p (binoptab); |
1459 | if (commutative_p | |
1460 | && GET_MODE (xop0) != mode0 && GET_MODE (xop1) != mode1 | |
1461 | && GET_MODE (xop0) == mode1 && GET_MODE (xop1) == mode1) | |
0aa222d1 | 1462 | { |
62442ab9 RS |
1463 | swap = xop0; |
1464 | xop0 = xop1; | |
1465 | xop1 = swap; | |
0aa222d1 SL |
1466 | } |
1467 | ||
62442ab9 RS |
1468 | /* If we are optimizing, force expensive constants into a register. */ |
1469 | xop0 = avoid_expensive_constant (mode0, binoptab, xop0, unsignedp); | |
1470 | if (!shift_optab_p (binoptab)) | |
1471 | xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp); | |
1472 | ||
0aa222d1 SL |
1473 | /* In case the insn wants input operands in modes different from |
1474 | those of the actual operands, convert the operands. It would | |
1475 | seem that we don't need to convert CONST_INTs, but we do, so | |
1476 | that they're properly zero-extended, sign-extended or truncated | |
1477 | for their mode. */ | |
1478 | ||
62442ab9 | 1479 | if (GET_MODE (xop0) != mode0 && mode0 != VOIDmode) |
0aa222d1 | 1480 | xop0 = convert_modes (mode0, |
62442ab9 RS |
1481 | GET_MODE (xop0) != VOIDmode |
1482 | ? GET_MODE (xop0) | |
0aa222d1 SL |
1483 | : mode, |
1484 | xop0, unsignedp); | |
1485 | ||
62442ab9 | 1486 | if (GET_MODE (xop1) != mode1 && mode1 != VOIDmode) |
0aa222d1 | 1487 | xop1 = convert_modes (mode1, |
62442ab9 RS |
1488 | GET_MODE (xop1) != VOIDmode |
1489 | ? GET_MODE (xop1) | |
0aa222d1 SL |
1490 | : mode, |
1491 | xop1, unsignedp); | |
1492 | ||
62442ab9 RS |
1493 | /* If operation is commutative, |
1494 | try to make the first operand a register. | |
1495 | Even better, try to make it the same as the target. | |
1496 | Also try to make the last operand a constant. */ | |
1497 | if (commutative_p | |
1498 | && swap_commutative_operands_with_target (target, xop0, xop1)) | |
1499 | { | |
1500 | swap = xop1; | |
1501 | xop1 = xop0; | |
1502 | xop0 = swap; | |
1503 | } | |
1504 | ||
0aa222d1 SL |
1505 | /* Now, if insn's predicates don't allow our operands, put them into |
1506 | pseudo regs. */ | |
1507 | ||
1508 | if (!insn_data[icode].operand[1].predicate (xop0, mode0) | |
1509 | && mode0 != VOIDmode) | |
1510 | xop0 = copy_to_mode_reg (mode0, xop0); | |
1511 | ||
1512 | if (!insn_data[icode].operand[2].predicate (xop1, mode1) | |
1513 | && mode1 != VOIDmode) | |
1514 | xop1 = copy_to_mode_reg (mode1, xop1); | |
1515 | ||
1516 | if (binoptab == vec_pack_trunc_optab | |
1517 | || binoptab == vec_pack_usat_optab | |
1518 | || binoptab == vec_pack_ssat_optab | |
1519 | || binoptab == vec_pack_ufix_trunc_optab | |
1520 | || binoptab == vec_pack_sfix_trunc_optab) | |
1521 | { | |
1522 | /* The mode of the result is different then the mode of the | |
1523 | arguments. */ | |
1524 | tmp_mode = insn_data[icode].operand[0].mode; | |
1525 | if (GET_MODE_NUNITS (tmp_mode) != 2 * GET_MODE_NUNITS (mode)) | |
1526 | return 0; | |
1527 | } | |
1528 | else | |
1529 | tmp_mode = mode; | |
1530 | ||
1531 | if (!insn_data[icode].operand[0].predicate (temp, tmp_mode)) | |
1532 | temp = gen_reg_rtx (tmp_mode); | |
1533 | ||
1534 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
1535 | if (pat) | |
1536 | { | |
1537 | /* If PAT is composed of more than one insn, try to add an appropriate | |
1538 | REG_EQUAL note to it. If we can't because TEMP conflicts with an | |
1539 | operand, call expand_binop again, this time without a target. */ | |
1540 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX | |
1541 | && ! add_equal_note (pat, temp, binoptab->code, xop0, xop1)) | |
1542 | { | |
1543 | delete_insns_since (last); | |
1544 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, | |
1545 | unsignedp, methods); | |
1546 | } | |
1547 | ||
1548 | emit_insn (pat); | |
1549 | return temp; | |
1550 | } | |
1551 | ||
1552 | delete_insns_since (last); | |
1553 | return NULL_RTX; | |
1554 | } | |
1555 | ||
77c9c6c2 RK |
1556 | /* Generate code to perform an operation specified by BINOPTAB |
1557 | on operands OP0 and OP1, with result having machine-mode MODE. | |
1558 | ||
1559 | UNSIGNEDP is for the case where we have to widen the operands | |
1560 | to perform the operation. It says to use zero-extension. | |
1561 | ||
1562 | If TARGET is nonzero, the value | |
1563 | is generated there, if it is convenient to do so. | |
1564 | In all cases an rtx is returned for the locus of the value; | |
1565 | this may or may not be TARGET. */ | |
1566 | ||
1567 | rtx | |
0c20a65f AJ |
1568 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
1569 | rtx target, int unsignedp, enum optab_methods methods) | |
77c9c6c2 | 1570 | { |
70864443 RK |
1571 | enum optab_methods next_methods |
1572 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
1573 | ? OPTAB_WIDEN : methods); | |
77c9c6c2 RK |
1574 | enum mode_class class; |
1575 | enum machine_mode wider_mode; | |
8a33f100 | 1576 | rtx libfunc; |
b3694847 | 1577 | rtx temp; |
abd418d3 | 1578 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
1579 | rtx last; |
1580 | ||
1581 | class = GET_MODE_CLASS (mode); | |
1582 | ||
8aecce0a RK |
1583 | /* If subtracting an integer constant, convert this into an addition of |
1584 | the negated constant. */ | |
1585 | ||
1586 | if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT) | |
1587 | { | |
1588 | op1 = negate_rtx (mode, op1); | |
1589 | binoptab = add_optab; | |
1590 | } | |
1591 | ||
77c9c6c2 RK |
1592 | /* Record where to delete back to if we backtrack. */ |
1593 | last = get_last_insn (); | |
1594 | ||
77c9c6c2 RK |
1595 | /* If we can do it with a three-operand insn, do so. */ |
1596 | ||
1597 | if (methods != OPTAB_MUST_WIDEN | |
166cdb08 | 1598 | && optab_handler (binoptab, mode)->insn_code != CODE_FOR_nothing) |
77c9c6c2 | 1599 | { |
0aa222d1 | 1600 | temp = expand_binop_directly (mode, binoptab, op0, op1, target, |
62442ab9 | 1601 | unsignedp, methods, last); |
0aa222d1 SL |
1602 | if (temp) |
1603 | return temp; | |
77c9c6c2 RK |
1604 | } |
1605 | ||
0aa222d1 SL |
1606 | /* If we were trying to rotate, and that didn't work, try rotating |
1607 | the other direction before falling back to shifts and bitwise-or. */ | |
1608 | if (((binoptab == rotl_optab | |
166cdb08 | 1609 | && optab_handler (rotr_optab, mode)->insn_code != CODE_FOR_nothing) |
0aa222d1 | 1610 | || (binoptab == rotr_optab |
166cdb08 | 1611 | && optab_handler (rotl_optab, mode)->insn_code != CODE_FOR_nothing)) |
0aa222d1 | 1612 | && class == MODE_INT) |
0f8594ee | 1613 | { |
0aa222d1 SL |
1614 | optab otheroptab = (binoptab == rotl_optab ? rotr_optab : rotl_optab); |
1615 | rtx newop1; | |
9ee34274 | 1616 | unsigned int bits = GET_MODE_BITSIZE (mode); |
0aa222d1 SL |
1617 | |
1618 | if (GET_CODE (op1) == CONST_INT) | |
1619 | newop1 = GEN_INT (bits - INTVAL (op1)); | |
1620 | else if (targetm.shift_truncation_mask (mode) == bits - 1) | |
1621 | newop1 = negate_rtx (mode, op1); | |
1622 | else | |
1623 | newop1 = expand_binop (mode, sub_optab, | |
1624 | GEN_INT (bits), op1, | |
1625 | NULL_RTX, unsignedp, OPTAB_DIRECT); | |
1626 | ||
1627 | temp = expand_binop_directly (mode, otheroptab, op0, newop1, | |
62442ab9 | 1628 | target, unsignedp, methods, last); |
0aa222d1 SL |
1629 | if (temp) |
1630 | return temp; | |
0f8594ee MM |
1631 | } |
1632 | ||
5a5064dc RK |
1633 | /* If this is a multiply, see if we can do a widening operation that |
1634 | takes operands of this mode and makes a wider mode. */ | |
1635 | ||
86556d87 BE |
1636 | if (binoptab == smul_optab |
1637 | && GET_MODE_WIDER_MODE (mode) != VOIDmode | |
166cdb08 JH |
1638 | && ((optab_handler ((unsignedp ? umul_widen_optab : smul_widen_optab), |
1639 | GET_MODE_WIDER_MODE (mode))->insn_code) | |
5a5064dc RK |
1640 | != CODE_FOR_nothing)) |
1641 | { | |
1642 | temp = expand_binop (GET_MODE_WIDER_MODE (mode), | |
1643 | unsignedp ? umul_widen_optab : smul_widen_optab, | |
73d9a835 | 1644 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
5a5064dc | 1645 | |
70864443 RK |
1646 | if (temp != 0) |
1647 | { | |
28f52a4d R |
1648 | if (GET_MODE_CLASS (mode) == MODE_INT |
1649 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
1650 | GET_MODE_BITSIZE (GET_MODE (temp)))) | |
70864443 RK |
1651 | return gen_lowpart (mode, temp); |
1652 | else | |
1653 | return convert_to_mode (mode, temp, unsignedp); | |
1654 | } | |
5a5064dc RK |
1655 | } |
1656 | ||
9a856ec7 | 1657 | /* Look for a wider mode of the same class for which we think we |
5a5064dc RK |
1658 | can open-code the operation. Check for a widening multiply at the |
1659 | wider mode as well. */ | |
9a856ec7 | 1660 | |
86556d87 | 1661 | if (CLASS_HAS_WIDER_MODES_P (class) |
6f43c157 | 1662 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
86556d87 BE |
1663 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
1664 | wider_mode != VOIDmode; | |
9a856ec7 RK |
1665 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1666 | { | |
166cdb08 | 1667 | if (optab_handler (binoptab, wider_mode)->insn_code != CODE_FOR_nothing |
5a5064dc RK |
1668 | || (binoptab == smul_optab |
1669 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
166cdb08 JH |
1670 | && ((optab_handler ((unsignedp ? umul_widen_optab |
1671 | : smul_widen_optab), | |
1672 | GET_MODE_WIDER_MODE (wider_mode))->insn_code) | |
5a5064dc | 1673 | != CODE_FOR_nothing))) |
9a856ec7 RK |
1674 | { |
1675 | rtx xop0 = op0, xop1 = op1; | |
1676 | int no_extend = 0; | |
1677 | ||
1678 | /* For certain integer operations, we need not actually extend | |
1679 | the narrow operands, as long as we will truncate | |
6d2f8887 | 1680 | the results to the same narrowness. */ |
9a856ec7 RK |
1681 | |
1682 | if ((binoptab == ior_optab || binoptab == and_optab | |
1683 | || binoptab == xor_optab | |
1684 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 1685 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 1686 | && class == MODE_INT) |
62442ab9 RS |
1687 | { |
1688 | no_extend = 1; | |
1689 | xop0 = avoid_expensive_constant (mode, binoptab, | |
1690 | xop0, unsignedp); | |
1691 | if (binoptab != ashl_optab) | |
1692 | xop1 = avoid_expensive_constant (mode, binoptab, | |
1693 | xop1, unsignedp); | |
1694 | } | |
9a856ec7 | 1695 | |
0661a3de | 1696 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
943cc242 RK |
1697 | |
1698 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 1699 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 1700 | no_extend && binoptab != ashl_optab); |
943cc242 | 1701 | |
b1ec3c92 | 1702 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
9a856ec7 RK |
1703 | unsignedp, OPTAB_DIRECT); |
1704 | if (temp) | |
1705 | { | |
28f52a4d R |
1706 | if (class != MODE_INT |
1707 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
1708 | GET_MODE_BITSIZE (wider_mode))) | |
9a856ec7 RK |
1709 | { |
1710 | if (target == 0) | |
1711 | target = gen_reg_rtx (mode); | |
1712 | convert_move (target, temp, 0); | |
1713 | return target; | |
1714 | } | |
1715 | else | |
1716 | return gen_lowpart (mode, temp); | |
1717 | } | |
1718 | else | |
1719 | delete_insns_since (last); | |
1720 | } | |
1721 | } | |
1722 | ||
62442ab9 RS |
1723 | /* If operation is commutative, |
1724 | try to make the first operand a register. | |
1725 | Even better, try to make it the same as the target. | |
1726 | Also try to make the last operand a constant. */ | |
1727 | if (commutative_optab_p (binoptab) | |
1728 | && swap_commutative_operands_with_target (target, op0, op1)) | |
1729 | { | |
1730 | temp = op1; | |
1731 | op1 = op0; | |
1732 | op0 = temp; | |
1733 | } | |
1734 | ||
77c9c6c2 RK |
1735 | /* These can be done a word at a time. */ |
1736 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
1737 | && class == MODE_INT | |
1738 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
166cdb08 | 1739 | && optab_handler (binoptab, word_mode)->insn_code != CODE_FOR_nothing) |
77c9c6c2 | 1740 | { |
bb93b973 | 1741 | int i; |
77c9c6c2 RK |
1742 | rtx insns; |
1743 | rtx equiv_value; | |
1744 | ||
1745 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
1746 | won't be accurate, so use a new target. */ | |
1747 | if (target == 0 || target == op0 || target == op1) | |
1748 | target = gen_reg_rtx (mode); | |
1749 | ||
1750 | start_sequence (); | |
1751 | ||
1752 | /* Do the actual arithmetic. */ | |
1753 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
1754 | { | |
1755 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 1756 | rtx x = expand_binop (word_mode, binoptab, |
77c9c6c2 RK |
1757 | operand_subword_force (op0, i, mode), |
1758 | operand_subword_force (op1, i, mode), | |
70864443 RK |
1759 | target_piece, unsignedp, next_methods); |
1760 | ||
1761 | if (x == 0) | |
1762 | break; | |
1763 | ||
77c9c6c2 RK |
1764 | if (target_piece != x) |
1765 | emit_move_insn (target_piece, x); | |
1766 | } | |
1767 | ||
1768 | insns = get_insns (); | |
1769 | end_sequence (); | |
1770 | ||
70864443 RK |
1771 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
1772 | { | |
1773 | if (binoptab->code != UNKNOWN) | |
1774 | equiv_value | |
9e6a5703 JC |
1775 | = gen_rtx_fmt_ee (binoptab->code, mode, |
1776 | copy_rtx (op0), copy_rtx (op1)); | |
70864443 RK |
1777 | else |
1778 | equiv_value = 0; | |
77c9c6c2 | 1779 | |
d70dcf29 | 1780 | emit_insn (insns); |
70864443 RK |
1781 | return target; |
1782 | } | |
77c9c6c2 RK |
1783 | } |
1784 | ||
8c597270 | 1785 | /* Synthesize double word shifts from single word shifts. */ |
e5df894b RK |
1786 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
1787 | || binoptab == ashr_optab) | |
8c597270 | 1788 | && class == MODE_INT |
273a2526 | 1789 | && (GET_CODE (op1) == CONST_INT || !optimize_size) |
8c597270 | 1790 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
166cdb08 JH |
1791 | && optab_handler (binoptab, word_mode)->insn_code != CODE_FOR_nothing |
1792 | && optab_handler (ashl_optab, word_mode)->insn_code != CODE_FOR_nothing | |
1793 | && optab_handler (lshr_optab, word_mode)->insn_code != CODE_FOR_nothing) | |
8c597270 | 1794 | { |
273a2526 RS |
1795 | unsigned HOST_WIDE_INT shift_mask, double_shift_mask; |
1796 | enum machine_mode op1_mode; | |
8c597270 | 1797 | |
273a2526 RS |
1798 | double_shift_mask = targetm.shift_truncation_mask (mode); |
1799 | shift_mask = targetm.shift_truncation_mask (word_mode); | |
1800 | op1_mode = GET_MODE (op1) != VOIDmode ? GET_MODE (op1) : word_mode; | |
8c597270 | 1801 | |
273a2526 RS |
1802 | /* Apply the truncation to constant shifts. */ |
1803 | if (double_shift_mask > 0 && GET_CODE (op1) == CONST_INT) | |
1804 | op1 = GEN_INT (INTVAL (op1) & double_shift_mask); | |
8c597270 | 1805 | |
273a2526 RS |
1806 | if (op1 == CONST0_RTX (op1_mode)) |
1807 | return op0; | |
8c597270 | 1808 | |
273a2526 RS |
1809 | /* Make sure that this is a combination that expand_doubleword_shift |
1810 | can handle. See the comments there for details. */ | |
1811 | if (double_shift_mask == 0 | |
1812 | || (shift_mask == BITS_PER_WORD - 1 | |
1813 | && double_shift_mask == BITS_PER_WORD * 2 - 1)) | |
8c597270 | 1814 | { |
d70dcf29 | 1815 | rtx insns; |
273a2526 RS |
1816 | rtx into_target, outof_target; |
1817 | rtx into_input, outof_input; | |
1818 | int left_shift, outof_word; | |
8c597270 | 1819 | |
273a2526 RS |
1820 | /* If TARGET is the same as one of the operands, the REG_EQUAL note |
1821 | won't be accurate, so use a new target. */ | |
1822 | if (target == 0 || target == op0 || target == op1) | |
1823 | target = gen_reg_rtx (mode); | |
8c597270 | 1824 | |
273a2526 | 1825 | start_sequence (); |
8c597270 | 1826 | |
273a2526 RS |
1827 | /* OUTOF_* is the word we are shifting bits away from, and |
1828 | INTO_* is the word that we are shifting bits towards, thus | |
1829 | they differ depending on the direction of the shift and | |
1830 | WORDS_BIG_ENDIAN. */ | |
70864443 | 1831 | |
273a2526 RS |
1832 | left_shift = binoptab == ashl_optab; |
1833 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
70864443 | 1834 | |
273a2526 RS |
1835 | outof_target = operand_subword (target, outof_word, 1, mode); |
1836 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
cf2f7113 | 1837 | |
273a2526 RS |
1838 | outof_input = operand_subword_force (op0, outof_word, mode); |
1839 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
0c20a65f | 1840 | |
273a2526 RS |
1841 | if (expand_doubleword_shift (op1_mode, binoptab, |
1842 | outof_input, into_input, op1, | |
1843 | outof_target, into_target, | |
f8bdb931 | 1844 | unsignedp, next_methods, shift_mask)) |
273a2526 RS |
1845 | { |
1846 | insns = get_insns (); | |
1847 | end_sequence (); | |
8c597270 | 1848 | |
d70dcf29 | 1849 | emit_insn (insns); |
273a2526 RS |
1850 | return target; |
1851 | } | |
1852 | end_sequence (); | |
70864443 | 1853 | } |
8c597270 JW |
1854 | } |
1855 | ||
1856 | /* Synthesize double word rotates from single word shifts. */ | |
1857 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
1858 | && class == MODE_INT | |
1859 | && GET_CODE (op1) == CONST_INT | |
1860 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
166cdb08 JH |
1861 | && optab_handler (ashl_optab, word_mode)->insn_code != CODE_FOR_nothing |
1862 | && optab_handler (lshr_optab, word_mode)->insn_code != CODE_FOR_nothing) | |
8c597270 | 1863 | { |
ebd8b60d | 1864 | rtx insns; |
8c597270 JW |
1865 | rtx into_target, outof_target; |
1866 | rtx into_input, outof_input; | |
70864443 | 1867 | rtx inter; |
8c597270 JW |
1868 | int shift_count, left_shift, outof_word; |
1869 | ||
1870 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
0c0ab0f1 OH |
1871 | won't be accurate, so use a new target. Do this also if target is not |
1872 | a REG, first because having a register instead may open optimization | |
1ae58c30 | 1873 | opportunities, and second because if target and op0 happen to be MEMs |
0c0ab0f1 OH |
1874 | designating the same location, we would risk clobbering it too early |
1875 | in the code sequence we generate below. */ | |
1876 | if (target == 0 || target == op0 || target == op1 || ! REG_P (target)) | |
8c597270 JW |
1877 | target = gen_reg_rtx (mode); |
1878 | ||
1879 | start_sequence (); | |
1880 | ||
1881 | shift_count = INTVAL (op1); | |
1882 | ||
1883 | /* OUTOF_* is the word we are shifting bits away from, and | |
1884 | INTO_* is the word that we are shifting bits towards, thus | |
1885 | they differ depending on the direction of the shift and | |
1886 | WORDS_BIG_ENDIAN. */ | |
1887 | ||
1888 | left_shift = (binoptab == rotl_optab); | |
1889 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1890 | ||
1891 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1892 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1893 | ||
1894 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1895 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1896 | ||
1897 | if (shift_count == BITS_PER_WORD) | |
1898 | { | |
1899 | /* This is just a word swap. */ | |
1900 | emit_move_insn (outof_target, into_input); | |
1901 | emit_move_insn (into_target, outof_input); | |
70864443 | 1902 | inter = const0_rtx; |
8c597270 JW |
1903 | } |
1904 | else | |
1905 | { | |
1906 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1907 | rtx first_shift_count, second_shift_count; | |
1908 | optab reverse_unsigned_shift, unsigned_shift; | |
1909 | ||
1910 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1911 | ? lshr_optab : ashl_optab); | |
1912 | ||
1913 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1914 | ? ashl_optab : lshr_optab); | |
1915 | ||
1916 | if (shift_count > BITS_PER_WORD) | |
1917 | { | |
1918 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
7e1a450d | 1919 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
8c597270 JW |
1920 | } |
1921 | else | |
1922 | { | |
1923 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1924 | second_shift_count = GEN_INT (shift_count); | |
1925 | } | |
1926 | ||
1927 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1928 | outof_input, first_shift_count, | |
70864443 | 1929 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1930 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1931 | into_input, second_shift_count, | |
5be5c8d4 | 1932 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1933 | |
1934 | if (into_temp1 != 0 && into_temp2 != 0) | |
1935 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1936 | into_target, unsignedp, next_methods); | |
1937 | else | |
1938 | inter = 0; | |
1939 | ||
cb5b00cf | 1940 | if (inter != 0 && inter != into_target) |
70864443 | 1941 | emit_move_insn (into_target, inter); |
8c597270 JW |
1942 | |
1943 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1944 | into_input, first_shift_count, | |
70864443 | 1945 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1946 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1947 | outof_input, second_shift_count, | |
5be5c8d4 | 1948 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1949 | |
1950 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1951 | inter = expand_binop (word_mode, ior_optab, | |
1952 | outof_temp1, outof_temp2, | |
1953 | outof_target, unsignedp, next_methods); | |
1954 | ||
cb5b00cf | 1955 | if (inter != 0 && inter != outof_target) |
70864443 | 1956 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1957 | } |
1958 | ||
1959 | insns = get_insns (); | |
1960 | end_sequence (); | |
1961 | ||
70864443 RK |
1962 | if (inter != 0) |
1963 | { | |
ebd8b60d | 1964 | emit_insn (insns); |
70864443 RK |
1965 | return target; |
1966 | } | |
8c597270 JW |
1967 | } |
1968 | ||
77c9c6c2 RK |
1969 | /* These can be done a word at a time by propagating carries. */ |
1970 | if ((binoptab == add_optab || binoptab == sub_optab) | |
1971 | && class == MODE_INT | |
1972 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD | |
166cdb08 | 1973 | && optab_handler (binoptab, word_mode)->insn_code != CODE_FOR_nothing) |
77c9c6c2 | 1974 | { |
e2500fed | 1975 | unsigned int i; |
77c9c6c2 | 1976 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
a4b5414c | 1977 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
07444f1d | 1978 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
64de6c0a | 1979 | rtx xop0, xop1, xtarget; |
77c9c6c2 RK |
1980 | |
1981 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1982 | value is one of those, use it. Otherwise, use 1 since it is the | |
1983 | one easiest to get. */ | |
1984 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1985 | int normalizep = STORE_FLAG_VALUE; | |
1986 | #else | |
1987 | int normalizep = 1; | |
1988 | #endif | |
1989 | ||
1990 | /* Prepare the operands. */ | |
cee85023 RS |
1991 | xop0 = force_reg (mode, op0); |
1992 | xop1 = force_reg (mode, op1); | |
77c9c6c2 | 1993 | |
64de6c0a DE |
1994 | xtarget = gen_reg_rtx (mode); |
1995 | ||
f8cfc6aa | 1996 | if (target == 0 || !REG_P (target)) |
64de6c0a | 1997 | target = xtarget; |
77c9c6c2 | 1998 | |
af2cc4dd | 1999 | /* Indicate for flow that the entire target reg is being set. */ |
f8cfc6aa | 2000 | if (REG_P (target)) |
c41c1387 | 2001 | emit_clobber (xtarget); |
af2cc4dd | 2002 | |
77c9c6c2 RK |
2003 | /* Do the actual arithmetic. */ |
2004 | for (i = 0; i < nwords; i++) | |
2005 | { | |
2006 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
64de6c0a | 2007 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
cee85023 RS |
2008 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
2009 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
77c9c6c2 RK |
2010 | rtx x; |
2011 | ||
2012 | /* Main add/subtract of the input operands. */ | |
34e56753 | 2013 | x = expand_binop (word_mode, binoptab, |
77c9c6c2 | 2014 | op0_piece, op1_piece, |
70864443 | 2015 | target_piece, unsignedp, next_methods); |
77c9c6c2 RK |
2016 | if (x == 0) |
2017 | break; | |
2018 | ||
2019 | if (i + 1 < nwords) | |
2020 | { | |
2021 | /* Store carry from main add/subtract. */ | |
34e56753 | 2022 | carry_out = gen_reg_rtx (word_mode); |
23357404 TG |
2023 | carry_out = emit_store_flag_force (carry_out, |
2024 | (binoptab == add_optab | |
b30f05db | 2025 | ? LT : GT), |
23357404 TG |
2026 | x, op0_piece, |
2027 | word_mode, 1, normalizep); | |
77c9c6c2 RK |
2028 | } |
2029 | ||
2030 | if (i > 0) | |
2031 | { | |
859cb4d8 | 2032 | rtx newx; |
0c20a65f | 2033 | |
77c9c6c2 | 2034 | /* Add/subtract previous carry to main result. */ |
859cb4d8 GK |
2035 | newx = expand_binop (word_mode, |
2036 | normalizep == 1 ? binoptab : otheroptab, | |
2037 | x, carry_in, | |
2038 | NULL_RTX, 1, next_methods); | |
77c9c6c2 RK |
2039 | |
2040 | if (i + 1 < nwords) | |
2041 | { | |
77c9c6c2 | 2042 | /* Get out carry from adding/subtracting carry in. */ |
859cb4d8 | 2043 | rtx carry_tmp = gen_reg_rtx (word_mode); |
23357404 | 2044 | carry_tmp = emit_store_flag_force (carry_tmp, |
859cb4d8 GK |
2045 | (binoptab == add_optab |
2046 | ? LT : GT), | |
2047 | newx, x, | |
23357404 | 2048 | word_mode, 1, normalizep); |
70864443 | 2049 | |
77c9c6c2 | 2050 | /* Logical-ior the two poss. carry together. */ |
34e56753 | 2051 | carry_out = expand_binop (word_mode, ior_optab, |
77c9c6c2 | 2052 | carry_out, carry_tmp, |
70864443 RK |
2053 | carry_out, 0, next_methods); |
2054 | if (carry_out == 0) | |
77c9c6c2 RK |
2055 | break; |
2056 | } | |
859cb4d8 | 2057 | emit_move_insn (target_piece, newx); |
77c9c6c2 | 2058 | } |
06cd9d72 DD |
2059 | else |
2060 | { | |
2061 | if (x != target_piece) | |
2062 | emit_move_insn (target_piece, x); | |
2063 | } | |
77c9c6c2 RK |
2064 | |
2065 | carry_in = carry_out; | |
0c20a65f | 2066 | } |
77c9c6c2 | 2067 | |
e2500fed | 2068 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
77c9c6c2 | 2069 | { |
166cdb08 | 2070 | if (optab_handler (mov_optab, mode)->insn_code != CODE_FOR_nothing |
d0ccc658 | 2071 | || ! rtx_equal_p (target, xtarget)) |
02214a5c | 2072 | { |
64de6c0a | 2073 | rtx temp = emit_move_insn (target, xtarget); |
70864443 | 2074 | |
5fa671cf | 2075 | set_unique_reg_note (temp, |
0c20a65f | 2076 | REG_EQUAL, |
5fa671cf AM |
2077 | gen_rtx_fmt_ee (binoptab->code, mode, |
2078 | copy_rtx (xop0), | |
2079 | copy_rtx (xop1))); | |
02214a5c | 2080 | } |
2cd622c3 AO |
2081 | else |
2082 | target = xtarget; | |
c5c76735 | 2083 | |
77c9c6c2 RK |
2084 | return target; |
2085 | } | |
c5c76735 | 2086 | |
77c9c6c2 RK |
2087 | else |
2088 | delete_insns_since (last); | |
2089 | } | |
2090 | ||
f927760b RS |
2091 | /* Attempt to synthesize double word multiplies using a sequence of word |
2092 | mode multiplications. We first attempt to generate a sequence using a | |
2093 | more efficient unsigned widening multiply, and if that fails we then | |
2094 | try using a signed widening multiply. */ | |
77c9c6c2 RK |
2095 | |
2096 | if (binoptab == smul_optab | |
2097 | && class == MODE_INT | |
2098 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
166cdb08 JH |
2099 | && optab_handler (smul_optab, word_mode)->insn_code != CODE_FOR_nothing |
2100 | && optab_handler (add_optab, word_mode)->insn_code != CODE_FOR_nothing) | |
77c9c6c2 | 2101 | { |
f927760b | 2102 | rtx product = NULL_RTX; |
77c9c6c2 | 2103 | |
166cdb08 | 2104 | if (optab_handler (umul_widen_optab, mode)->insn_code |
f927760b RS |
2105 | != CODE_FOR_nothing) |
2106 | { | |
2107 | product = expand_doubleword_mult (mode, op0, op1, target, | |
2108 | true, methods); | |
2109 | if (!product) | |
77c9c6c2 | 2110 | delete_insns_since (last); |
77c9c6c2 RK |
2111 | } |
2112 | ||
f927760b | 2113 | if (product == NULL_RTX |
166cdb08 | 2114 | && optab_handler (smul_widen_optab, mode)->insn_code |
f927760b | 2115 | != CODE_FOR_nothing) |
77c9c6c2 | 2116 | { |
f927760b RS |
2117 | product = expand_doubleword_mult (mode, op0, op1, target, |
2118 | false, methods); | |
2119 | if (!product) | |
2120 | delete_insns_since (last); | |
77c9c6c2 RK |
2121 | } |
2122 | ||
f927760b | 2123 | if (product != NULL_RTX) |
77c9c6c2 | 2124 | { |
166cdb08 | 2125 | if (optab_handler (mov_optab, mode)->insn_code != CODE_FOR_nothing) |
70864443 | 2126 | { |
f927760b RS |
2127 | temp = emit_move_insn (target ? target : product, product); |
2128 | set_unique_reg_note (temp, | |
2129 | REG_EQUAL, | |
2130 | gen_rtx_fmt_ee (MULT, mode, | |
2131 | copy_rtx (op0), | |
2132 | copy_rtx (op1))); | |
77c9c6c2 | 2133 | } |
f927760b | 2134 | return product; |
77c9c6c2 | 2135 | } |
77c9c6c2 RK |
2136 | } |
2137 | ||
2138 | /* It can't be open-coded in this mode. | |
2139 | Use a library call if one is available and caller says that's ok. */ | |
2140 | ||
8a33f100 JH |
2141 | libfunc = optab_libfunc (binoptab, mode); |
2142 | if (libfunc | |
77c9c6c2 RK |
2143 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) |
2144 | { | |
2145 | rtx insns; | |
0bbb7f4d RS |
2146 | rtx op1x = op1; |
2147 | enum machine_mode op1_mode = mode; | |
9a7f678c | 2148 | rtx value; |
77c9c6c2 RK |
2149 | |
2150 | start_sequence (); | |
2151 | ||
62442ab9 | 2152 | if (shift_optab_p (binoptab)) |
0bbb7f4d | 2153 | { |
c7ff6e7a | 2154 | op1_mode = targetm.libgcc_shift_count_mode (); |
0bbb7f4d RS |
2155 | /* Specify unsigned here, |
2156 | since negative shift counts are meaningless. */ | |
c7ff6e7a | 2157 | op1x = convert_to_mode (op1_mode, op1, 1); |
0bbb7f4d RS |
2158 | } |
2159 | ||
82f0e2cc RK |
2160 | if (GET_MODE (op0) != VOIDmode |
2161 | && GET_MODE (op0) != mode) | |
5035bbfe TG |
2162 | op0 = convert_to_mode (mode, op0, unsignedp); |
2163 | ||
77c9c6c2 RK |
2164 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
2165 | if the libcall is cse'd or moved. */ | |
8a33f100 | 2166 | value = emit_library_call_value (libfunc, |
ebb1b59a | 2167 | NULL_RTX, LCT_CONST, mode, 2, |
9a7f678c | 2168 | op0, mode, op1x, op1_mode); |
77c9c6c2 RK |
2169 | |
2170 | insns = get_insns (); | |
2171 | end_sequence (); | |
2172 | ||
2173 | target = gen_reg_rtx (mode); | |
9a7f678c | 2174 | emit_libcall_block (insns, target, value, |
9e6a5703 | 2175 | gen_rtx_fmt_ee (binoptab->code, mode, op0, op1)); |
77c9c6c2 RK |
2176 | |
2177 | return target; | |
2178 | } | |
2179 | ||
2180 | delete_insns_since (last); | |
2181 | ||
2182 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2183 | ||
2184 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
2185 | || methods == OPTAB_MUST_WIDEN)) | |
abd418d3 RS |
2186 | { |
2187 | /* Caller says, don't even try. */ | |
2188 | delete_insns_since (entry_last); | |
2189 | return 0; | |
2190 | } | |
77c9c6c2 RK |
2191 | |
2192 | /* Compute the value of METHODS to pass to recursive calls. | |
2193 | Don't allow widening to be tried recursively. */ | |
2194 | ||
2195 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
2196 | ||
34e56753 RS |
2197 | /* Look for a wider mode of the same class for which it appears we can do |
2198 | the operation. */ | |
77c9c6c2 | 2199 | |
86556d87 | 2200 | if (CLASS_HAS_WIDER_MODES_P (class)) |
77c9c6c2 | 2201 | { |
86556d87 BE |
2202 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2203 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
2204 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2205 | { | |
166cdb08 | 2206 | if ((optab_handler (binoptab, wider_mode)->insn_code |
77c9c6c2 RK |
2207 | != CODE_FOR_nothing) |
2208 | || (methods == OPTAB_LIB | |
8a33f100 | 2209 | && optab_libfunc (binoptab, wider_mode))) |
77c9c6c2 RK |
2210 | { |
2211 | rtx xop0 = op0, xop1 = op1; | |
2212 | int no_extend = 0; | |
2213 | ||
34e56753 | 2214 | /* For certain integer operations, we need not actually extend |
77c9c6c2 | 2215 | the narrow operands, as long as we will truncate |
835532b8 | 2216 | the results to the same narrowness. */ |
77c9c6c2 | 2217 | |
34e56753 RS |
2218 | if ((binoptab == ior_optab || binoptab == and_optab |
2219 | || binoptab == xor_optab | |
2220 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 2221 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 2222 | && class == MODE_INT) |
77c9c6c2 RK |
2223 | no_extend = 1; |
2224 | ||
0661a3de RS |
2225 | xop0 = widen_operand (xop0, wider_mode, mode, |
2226 | unsignedp, no_extend); | |
943cc242 RK |
2227 | |
2228 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 2229 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 2230 | no_extend && binoptab != ashl_optab); |
77c9c6c2 | 2231 | |
b1ec3c92 | 2232 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
77c9c6c2 RK |
2233 | unsignedp, methods); |
2234 | if (temp) | |
2235 | { | |
28f52a4d R |
2236 | if (class != MODE_INT |
2237 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
2238 | GET_MODE_BITSIZE (wider_mode))) | |
77c9c6c2 RK |
2239 | { |
2240 | if (target == 0) | |
2241 | target = gen_reg_rtx (mode); | |
2242 | convert_move (target, temp, 0); | |
2243 | return target; | |
2244 | } | |
2245 | else | |
2246 | return gen_lowpart (mode, temp); | |
2247 | } | |
2248 | else | |
2249 | delete_insns_since (last); | |
2250 | } | |
2251 | } | |
2252 | } | |
2253 | ||
abd418d3 | 2254 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2255 | return 0; |
2256 | } | |
2257 | \f | |
2258 | /* Expand a binary operator which has both signed and unsigned forms. | |
2259 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2260 | signed operations. | |
2261 | ||
2262 | If we widen unsigned operands, we may use a signed wider operation instead | |
2263 | of an unsigned wider operation, since the result would be the same. */ | |
2264 | ||
2265 | rtx | |
0c20a65f AJ |
2266 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2267 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2268 | enum optab_methods methods) | |
77c9c6c2 | 2269 | { |
b3694847 | 2270 | rtx temp; |
77c9c6c2 RK |
2271 | optab direct_optab = unsignedp ? uoptab : soptab; |
2272 | struct optab wide_soptab; | |
2273 | ||
2274 | /* Do it without widening, if possible. */ | |
2275 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2276 | unsignedp, OPTAB_DIRECT); | |
2277 | if (temp || methods == OPTAB_DIRECT) | |
2278 | return temp; | |
2279 | ||
2280 | /* Try widening to a signed int. Make a fake signed optab that | |
2281 | hides any signed insn for direct use. */ | |
2282 | wide_soptab = *soptab; | |
166cdb08 | 2283 | optab_handler (&wide_soptab, mode)->insn_code = CODE_FOR_nothing; |
ae2bd7d2 AH |
2284 | /* We don't want to generate new hash table entries from this fake |
2285 | optab. */ | |
2286 | wide_soptab.libcall_gen = NULL; | |
77c9c6c2 RK |
2287 | |
2288 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2289 | unsignedp, OPTAB_WIDEN); | |
2290 | ||
2291 | /* For unsigned operands, try widening to an unsigned int. */ | |
2292 | if (temp == 0 && unsignedp) | |
2293 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
2294 | unsignedp, OPTAB_WIDEN); | |
2295 | if (temp || methods == OPTAB_WIDEN) | |
2296 | return temp; | |
2297 | ||
2298 | /* Use the right width lib call if that exists. */ | |
2299 | temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); | |
2300 | if (temp || methods == OPTAB_LIB) | |
2301 | return temp; | |
2302 | ||
2303 | /* Must widen and use a lib call, use either signed or unsigned. */ | |
2304 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2305 | unsignedp, methods); | |
2306 | if (temp != 0) | |
2307 | return temp; | |
2308 | if (unsignedp) | |
2309 | return expand_binop (mode, uoptab, op0, op1, target, | |
2310 | unsignedp, methods); | |
2311 | return 0; | |
2312 | } | |
2313 | \f | |
6c7cf1f0 UB |
2314 | /* Generate code to perform an operation specified by UNOPPTAB |
2315 | on operand OP0, with two results to TARG0 and TARG1. | |
2316 | We assume that the order of the operands for the instruction | |
2317 | is TARG0, TARG1, OP0. | |
2318 | ||
2319 | Either TARG0 or TARG1 may be zero, but what that means is that | |
2320 | the result is not actually wanted. We will generate it into | |
2321 | a dummy pseudo-reg and discard it. They may not both be zero. | |
2322 | ||
2323 | Returns 1 if this operation can be performed; 0 if not. */ | |
2324 | ||
2325 | int | |
a072d43b | 2326 | expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1, |
6c7cf1f0 UB |
2327 | int unsignedp) |
2328 | { | |
2329 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
2330 | enum mode_class class; | |
2331 | enum machine_mode wider_mode; | |
2332 | rtx entry_last = get_last_insn (); | |
2333 | rtx last; | |
2334 | ||
2335 | class = GET_MODE_CLASS (mode); | |
2336 | ||
ad76cef8 | 2337 | if (!targ0) |
6c7cf1f0 | 2338 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2339 | if (!targ1) |
6c7cf1f0 UB |
2340 | targ1 = gen_reg_rtx (mode); |
2341 | ||
2342 | /* Record where to go back to if we fail. */ | |
2343 | last = get_last_insn (); | |
2344 | ||
166cdb08 | 2345 | if (optab_handler (unoptab, mode)->insn_code != CODE_FOR_nothing) |
6c7cf1f0 | 2346 | { |
166cdb08 | 2347 | int icode = (int) optab_handler (unoptab, mode)->insn_code; |
6c7cf1f0 UB |
2348 | enum machine_mode mode0 = insn_data[icode].operand[2].mode; |
2349 | rtx pat; | |
2350 | rtx xop0 = op0; | |
2351 | ||
2352 | if (GET_MODE (xop0) != VOIDmode | |
2353 | && GET_MODE (xop0) != mode0) | |
2354 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2355 | ||
2356 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
e3feb571 | 2357 | if (!insn_data[icode].operand[2].predicate (xop0, mode0)) |
6c7cf1f0 UB |
2358 | xop0 = copy_to_mode_reg (mode0, xop0); |
2359 | ||
2360 | /* We could handle this, but we should always be called with a pseudo | |
2361 | for our targets and all insns should take them as outputs. */ | |
e3feb571 NS |
2362 | gcc_assert (insn_data[icode].operand[0].predicate (targ0, mode)); |
2363 | gcc_assert (insn_data[icode].operand[1].predicate (targ1, mode)); | |
6c7cf1f0 UB |
2364 | |
2365 | pat = GEN_FCN (icode) (targ0, targ1, xop0); | |
2366 | if (pat) | |
2367 | { | |
2368 | emit_insn (pat); | |
2369 | return 1; | |
2370 | } | |
2371 | else | |
2372 | delete_insns_since (last); | |
2373 | } | |
2374 | ||
2375 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2376 | ||
86556d87 | 2377 | if (CLASS_HAS_WIDER_MODES_P (class)) |
6c7cf1f0 | 2378 | { |
86556d87 BE |
2379 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2380 | wider_mode != VOIDmode; | |
6c7cf1f0 UB |
2381 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2382 | { | |
166cdb08 | 2383 | if (optab_handler (unoptab, wider_mode)->insn_code |
6c7cf1f0 UB |
2384 | != CODE_FOR_nothing) |
2385 | { | |
2386 | rtx t0 = gen_reg_rtx (wider_mode); | |
2387 | rtx t1 = gen_reg_rtx (wider_mode); | |
2388 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); | |
2389 | ||
a072d43b | 2390 | if (expand_twoval_unop (unoptab, cop0, t0, t1, unsignedp)) |
6c7cf1f0 UB |
2391 | { |
2392 | convert_move (targ0, t0, unsignedp); | |
2393 | convert_move (targ1, t1, unsignedp); | |
2394 | return 1; | |
2395 | } | |
2396 | else | |
2397 | delete_insns_since (last); | |
2398 | } | |
2399 | } | |
2400 | } | |
2401 | ||
2402 | delete_insns_since (entry_last); | |
2403 | return 0; | |
2404 | } | |
2405 | \f | |
77c9c6c2 RK |
2406 | /* Generate code to perform an operation specified by BINOPTAB |
2407 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2408 | We assume that the order of the operands for the instruction | |
2409 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2410 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2411 | ||
2412 | Either TARG0 or TARG1 may be zero, but what that means is that | |
38e01259 | 2413 | the result is not actually wanted. We will generate it into |
77c9c6c2 RK |
2414 | a dummy pseudo-reg and discard it. They may not both be zero. |
2415 | ||
2416 | Returns 1 if this operation can be performed; 0 if not. */ | |
2417 | ||
2418 | int | |
0c20a65f AJ |
2419 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2420 | int unsignedp) | |
77c9c6c2 RK |
2421 | { |
2422 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
2423 | enum mode_class class; | |
2424 | enum machine_mode wider_mode; | |
abd418d3 | 2425 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
2426 | rtx last; |
2427 | ||
2428 | class = GET_MODE_CLASS (mode); | |
2429 | ||
ad76cef8 | 2430 | if (!targ0) |
77c9c6c2 | 2431 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2432 | if (!targ1) |
77c9c6c2 RK |
2433 | targ1 = gen_reg_rtx (mode); |
2434 | ||
2435 | /* Record where to go back to if we fail. */ | |
2436 | last = get_last_insn (); | |
2437 | ||
166cdb08 | 2438 | if (optab_handler (binoptab, mode)->insn_code != CODE_FOR_nothing) |
77c9c6c2 | 2439 | { |
166cdb08 | 2440 | int icode = (int) optab_handler (binoptab, mode)->insn_code; |
a995e389 RH |
2441 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2442 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
2443 | rtx pat; |
2444 | rtx xop0 = op0, xop1 = op1; | |
2445 | ||
62442ab9 RS |
2446 | /* If we are optimizing, force expensive constants into a register. */ |
2447 | xop0 = avoid_expensive_constant (mode0, binoptab, xop0, unsignedp); | |
2448 | xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp); | |
2449 | ||
874f6a6d EB |
2450 | /* In case the insn wants input operands in modes different from |
2451 | those of the actual operands, convert the operands. It would | |
2452 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
2453 | that they're properly zero-extended, sign-extended or truncated |
2454 | for their mode. */ | |
77c9c6c2 | 2455 | |
874f6a6d EB |
2456 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
2457 | xop0 = convert_modes (mode0, | |
2458 | GET_MODE (op0) != VOIDmode | |
2459 | ? GET_MODE (op0) | |
2460 | : mode, | |
2461 | xop0, unsignedp); | |
2462 | ||
2463 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
2464 | xop1 = convert_modes (mode1, | |
2465 | GET_MODE (op1) != VOIDmode | |
2466 | ? GET_MODE (op1) | |
2467 | : mode, | |
2468 | xop1, unsignedp); | |
77c9c6c2 RK |
2469 | |
2470 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
e3feb571 | 2471 | if (!insn_data[icode].operand[1].predicate (xop0, mode0)) |
77c9c6c2 RK |
2472 | xop0 = copy_to_mode_reg (mode0, xop0); |
2473 | ||
e3feb571 | 2474 | if (!insn_data[icode].operand[2].predicate (xop1, mode1)) |
77c9c6c2 RK |
2475 | xop1 = copy_to_mode_reg (mode1, xop1); |
2476 | ||
2477 | /* We could handle this, but we should always be called with a pseudo | |
2478 | for our targets and all insns should take them as outputs. */ | |
e3feb571 NS |
2479 | gcc_assert (insn_data[icode].operand[0].predicate (targ0, mode)); |
2480 | gcc_assert (insn_data[icode].operand[3].predicate (targ1, mode)); | |
0c20a65f | 2481 | |
77c9c6c2 RK |
2482 | pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1); |
2483 | if (pat) | |
2484 | { | |
2485 | emit_insn (pat); | |
2486 | return 1; | |
2487 | } | |
2488 | else | |
2489 | delete_insns_since (last); | |
2490 | } | |
2491 | ||
2492 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2493 | ||
86556d87 | 2494 | if (CLASS_HAS_WIDER_MODES_P (class)) |
77c9c6c2 | 2495 | { |
86556d87 BE |
2496 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2497 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
2498 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2499 | { | |
166cdb08 | 2500 | if (optab_handler (binoptab, wider_mode)->insn_code |
77c9c6c2 RK |
2501 | != CODE_FOR_nothing) |
2502 | { | |
b3694847 SS |
2503 | rtx t0 = gen_reg_rtx (wider_mode); |
2504 | rtx t1 = gen_reg_rtx (wider_mode); | |
76791f3d JH |
2505 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2506 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
77c9c6c2 | 2507 | |
76791f3d | 2508 | if (expand_twoval_binop (binoptab, cop0, cop1, |
77c9c6c2 RK |
2509 | t0, t1, unsignedp)) |
2510 | { | |
2511 | convert_move (targ0, t0, unsignedp); | |
2512 | convert_move (targ1, t1, unsignedp); | |
2513 | return 1; | |
2514 | } | |
2515 | else | |
2516 | delete_insns_since (last); | |
2517 | } | |
2518 | } | |
2519 | } | |
2520 | ||
abd418d3 | 2521 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2522 | return 0; |
2523 | } | |
b3f8d95d MM |
2524 | |
2525 | /* Expand the two-valued library call indicated by BINOPTAB, but | |
2526 | preserve only one of the values. If TARG0 is non-NULL, the first | |
2527 | value is placed into TARG0; otherwise the second value is placed | |
2528 | into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The | |
2529 | value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1). | |
2530 | This routine assumes that the value returned by the library call is | |
2531 | as if the return value was of an integral mode twice as wide as the | |
2532 | mode of OP0. Returns 1 if the call was successful. */ | |
2533 | ||
2534 | bool | |
5906d013 | 2535 | expand_twoval_binop_libfunc (optab binoptab, rtx op0, rtx op1, |
b3f8d95d MM |
2536 | rtx targ0, rtx targ1, enum rtx_code code) |
2537 | { | |
2538 | enum machine_mode mode; | |
2539 | enum machine_mode libval_mode; | |
2540 | rtx libval; | |
2541 | rtx insns; | |
8a33f100 | 2542 | rtx libfunc; |
5906d013 | 2543 | |
b3f8d95d | 2544 | /* Exactly one of TARG0 or TARG1 should be non-NULL. */ |
e3feb571 | 2545 | gcc_assert (!targ0 != !targ1); |
b3f8d95d MM |
2546 | |
2547 | mode = GET_MODE (op0); | |
8a33f100 JH |
2548 | libfunc = optab_libfunc (binoptab, mode); |
2549 | if (!libfunc) | |
b3f8d95d MM |
2550 | return false; |
2551 | ||
2552 | /* The value returned by the library function will have twice as | |
2553 | many bits as the nominal MODE. */ | |
5906d013 | 2554 | libval_mode = smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode), |
b3f8d95d MM |
2555 | MODE_INT); |
2556 | start_sequence (); | |
8a33f100 | 2557 | libval = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
b3f8d95d | 2558 | libval_mode, 2, |
5906d013 | 2559 | op0, mode, |
b3f8d95d MM |
2560 | op1, mode); |
2561 | /* Get the part of VAL containing the value that we want. */ | |
2562 | libval = simplify_gen_subreg (mode, libval, libval_mode, | |
2563 | targ0 ? 0 : GET_MODE_SIZE (mode)); | |
2564 | insns = get_insns (); | |
2565 | end_sequence (); | |
2566 | /* Move the into the desired location. */ | |
5906d013 | 2567 | emit_libcall_block (insns, targ0 ? targ0 : targ1, libval, |
b3f8d95d | 2568 | gen_rtx_fmt_ee (code, mode, op0, op1)); |
5906d013 | 2569 | |
b3f8d95d MM |
2570 | return true; |
2571 | } | |
2572 | ||
77c9c6c2 | 2573 | \f |
ef89d648 ZW |
2574 | /* Wrapper around expand_unop which takes an rtx code to specify |
2575 | the operation to perform, not an optab pointer. All other | |
2576 | arguments are the same. */ | |
2577 | rtx | |
0c20a65f AJ |
2578 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2579 | rtx target, int unsignedp) | |
ef89d648 | 2580 | { |
7e1a450d | 2581 | optab unop = code_to_optab[(int) code]; |
e3feb571 | 2582 | gcc_assert (unop); |
ef89d648 ZW |
2583 | |
2584 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2585 | } | |
2586 | ||
2928cd7a RH |
2587 | /* Try calculating |
2588 | (clz:narrow x) | |
2589 | as | |
2590 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */ | |
2591 | static rtx | |
0c20a65f | 2592 | widen_clz (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2593 | { |
2594 | enum mode_class class = GET_MODE_CLASS (mode); | |
86556d87 | 2595 | if (CLASS_HAS_WIDER_MODES_P (class)) |
2928cd7a RH |
2596 | { |
2597 | enum machine_mode wider_mode; | |
86556d87 BE |
2598 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2599 | wider_mode != VOIDmode; | |
2928cd7a RH |
2600 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2601 | { | |
166cdb08 | 2602 | if (optab_handler (clz_optab, wider_mode)->insn_code |
2928cd7a RH |
2603 | != CODE_FOR_nothing) |
2604 | { | |
2605 | rtx xop0, temp, last; | |
2606 | ||
2607 | last = get_last_insn (); | |
2608 | ||
2609 | if (target == 0) | |
2610 | target = gen_reg_rtx (mode); | |
2611 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2612 | temp = expand_unop (wider_mode, clz_optab, xop0, NULL_RTX, true); | |
2613 | if (temp != 0) | |
2614 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2615 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2616 | - GET_MODE_BITSIZE (mode)), | |
2617 | target, true, OPTAB_DIRECT); | |
2618 | if (temp == 0) | |
2619 | delete_insns_since (last); | |
2620 | ||
2621 | return temp; | |
2622 | } | |
2623 | } | |
2624 | } | |
2625 | return 0; | |
2626 | } | |
2627 | ||
9cce5b20 ZW |
2628 | /* Try calculating clz of a double-word quantity as two clz's of word-sized |
2629 | quantities, choosing which based on whether the high word is nonzero. */ | |
2630 | static rtx | |
2631 | expand_doubleword_clz (enum machine_mode mode, rtx op0, rtx target) | |
2632 | { | |
2633 | rtx xop0 = force_reg (mode, op0); | |
2634 | rtx subhi = gen_highpart (word_mode, xop0); | |
2635 | rtx sublo = gen_lowpart (word_mode, xop0); | |
2636 | rtx hi0_label = gen_label_rtx (); | |
2637 | rtx after_label = gen_label_rtx (); | |
2638 | rtx seq, temp, result; | |
2639 | ||
2640 | /* If we were not given a target, use a word_mode register, not a | |
2641 | 'mode' register. The result will fit, and nobody is expecting | |
2642 | anything bigger (the return type of __builtin_clz* is int). */ | |
2643 | if (!target) | |
2644 | target = gen_reg_rtx (word_mode); | |
2645 | ||
2646 | /* In any case, write to a word_mode scratch in both branches of the | |
2647 | conditional, so we can ensure there is a single move insn setting | |
2648 | 'target' to tag a REG_EQUAL note on. */ | |
2649 | result = gen_reg_rtx (word_mode); | |
2650 | ||
2651 | start_sequence (); | |
2652 | ||
2653 | /* If the high word is not equal to zero, | |
2654 | then clz of the full value is clz of the high word. */ | |
2655 | emit_cmp_and_jump_insns (subhi, CONST0_RTX (word_mode), EQ, 0, | |
2656 | word_mode, true, hi0_label); | |
2657 | ||
2658 | temp = expand_unop_direct (word_mode, clz_optab, subhi, result, true); | |
2659 | if (!temp) | |
2660 | goto fail; | |
2661 | ||
2662 | if (temp != result) | |
2663 | convert_move (result, temp, true); | |
2664 | ||
2665 | emit_jump_insn (gen_jump (after_label)); | |
2666 | emit_barrier (); | |
2667 | ||
2668 | /* Else clz of the full value is clz of the low word plus the number | |
2669 | of bits in the high word. */ | |
2670 | emit_label (hi0_label); | |
2671 | ||
2672 | temp = expand_unop_direct (word_mode, clz_optab, sublo, 0, true); | |
2673 | if (!temp) | |
2674 | goto fail; | |
2675 | temp = expand_binop (word_mode, add_optab, temp, | |
2676 | GEN_INT (GET_MODE_BITSIZE (word_mode)), | |
2677 | result, true, OPTAB_DIRECT); | |
2678 | if (!temp) | |
2679 | goto fail; | |
2680 | if (temp != result) | |
2681 | convert_move (result, temp, true); | |
2682 | ||
2683 | emit_label (after_label); | |
2684 | convert_move (target, result, true); | |
2685 | ||
2686 | seq = get_insns (); | |
2687 | end_sequence (); | |
2688 | ||
2689 | add_equal_note (seq, target, CLZ, xop0, 0); | |
2690 | emit_insn (seq); | |
2691 | return target; | |
2692 | ||
2693 | fail: | |
2694 | end_sequence (); | |
2695 | return 0; | |
2696 | } | |
2697 | ||
2e6834d3 RH |
2698 | /* Try calculating |
2699 | (bswap:narrow x) | |
2700 | as | |
2701 | (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */ | |
2702 | static rtx | |
2703 | widen_bswap (enum machine_mode mode, rtx op0, rtx target) | |
2704 | { | |
2705 | enum mode_class class = GET_MODE_CLASS (mode); | |
2706 | enum machine_mode wider_mode; | |
2707 | rtx x, last; | |
2708 | ||
2709 | if (!CLASS_HAS_WIDER_MODES_P (class)) | |
2710 | return NULL_RTX; | |
2711 | ||
2712 | for (wider_mode = GET_MODE_WIDER_MODE (mode); | |
2713 | wider_mode != VOIDmode; | |
2714 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
166cdb08 | 2715 | if (optab_handler (bswap_optab, wider_mode)->insn_code != CODE_FOR_nothing) |
2e6834d3 RH |
2716 | goto found; |
2717 | return NULL_RTX; | |
2718 | ||
2719 | found: | |
2720 | last = get_last_insn (); | |
2721 | ||
2722 | x = widen_operand (op0, wider_mode, mode, true, true); | |
2723 | x = expand_unop (wider_mode, bswap_optab, x, NULL_RTX, true); | |
2724 | ||
2725 | if (x != 0) | |
2726 | x = expand_shift (RSHIFT_EXPR, wider_mode, x, | |
2727 | size_int (GET_MODE_BITSIZE (wider_mode) | |
2728 | - GET_MODE_BITSIZE (mode)), | |
2729 | NULL_RTX, true); | |
2730 | ||
2731 | if (x != 0) | |
2732 | { | |
2733 | if (target == 0) | |
2734 | target = gen_reg_rtx (mode); | |
2735 | emit_move_insn (target, gen_lowpart (mode, x)); | |
2736 | } | |
2737 | else | |
2738 | delete_insns_since (last); | |
2739 | ||
2740 | return target; | |
2741 | } | |
2742 | ||
2743 | /* Try calculating bswap as two bswaps of two word-sized operands. */ | |
2744 | ||
2745 | static rtx | |
2746 | expand_doubleword_bswap (enum machine_mode mode, rtx op, rtx target) | |
2747 | { | |
2748 | rtx t0, t1; | |
2749 | ||
2750 | t1 = expand_unop (word_mode, bswap_optab, | |
2751 | operand_subword_force (op, 0, mode), NULL_RTX, true); | |
2752 | t0 = expand_unop (word_mode, bswap_optab, | |
2753 | operand_subword_force (op, 1, mode), NULL_RTX, true); | |
2754 | ||
2755 | if (target == 0) | |
2756 | target = gen_reg_rtx (mode); | |
2757 | if (REG_P (target)) | |
c41c1387 | 2758 | emit_clobber (target); |
2e6834d3 RH |
2759 | emit_move_insn (operand_subword (target, 0, 1, mode), t0); |
2760 | emit_move_insn (operand_subword (target, 1, 1, mode), t1); | |
2761 | ||
2762 | return target; | |
2763 | } | |
2764 | ||
2928cd7a RH |
2765 | /* Try calculating (parity x) as (and (popcount x) 1), where |
2766 | popcount can also be done in a wider mode. */ | |
2767 | static rtx | |
0c20a65f | 2768 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2769 | { |
2770 | enum mode_class class = GET_MODE_CLASS (mode); | |
86556d87 | 2771 | if (CLASS_HAS_WIDER_MODES_P (class)) |
2928cd7a RH |
2772 | { |
2773 | enum machine_mode wider_mode; | |
2774 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2775 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2776 | { | |
166cdb08 | 2777 | if (optab_handler (popcount_optab, wider_mode)->insn_code |
2928cd7a RH |
2778 | != CODE_FOR_nothing) |
2779 | { | |
2780 | rtx xop0, temp, last; | |
2781 | ||
2782 | last = get_last_insn (); | |
2783 | ||
2784 | if (target == 0) | |
2785 | target = gen_reg_rtx (mode); | |
2786 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2787 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2788 | true); | |
2789 | if (temp != 0) | |
60c81c89 | 2790 | temp = expand_binop (wider_mode, and_optab, temp, const1_rtx, |
2928cd7a RH |
2791 | target, true, OPTAB_DIRECT); |
2792 | if (temp == 0) | |
2793 | delete_insns_since (last); | |
2794 | ||
2795 | return temp; | |
2796 | } | |
2797 | } | |
2798 | } | |
2799 | return 0; | |
2800 | } | |
2801 | ||
9cce5b20 ZW |
2802 | /* Try calculating ctz(x) as K - clz(x & -x) , |
2803 | where K is GET_MODE_BITSIZE(mode) - 1. | |
2804 | ||
2805 | Both __builtin_ctz and __builtin_clz are undefined at zero, so we | |
2806 | don't have to worry about what the hardware does in that case. (If | |
2807 | the clz instruction produces the usual value at 0, which is K, the | |
2808 | result of this code sequence will be -1; expand_ffs, below, relies | |
2809 | on this. It might be nice to have it be K instead, for consistency | |
2810 | with the (very few) processors that provide a ctz with a defined | |
2811 | value, but that would take one more instruction, and it would be | |
2812 | less convenient for expand_ffs anyway. */ | |
2813 | ||
14670a74 | 2814 | static rtx |
9cce5b20 | 2815 | expand_ctz (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2816 | { |
9cce5b20 ZW |
2817 | rtx seq, temp; |
2818 | ||
2819 | if (optab_handler (clz_optab, mode)->insn_code == CODE_FOR_nothing) | |
2820 | return 0; | |
2821 | ||
2822 | start_sequence (); | |
14670a74 | 2823 | |
9cce5b20 ZW |
2824 | temp = expand_unop_direct (mode, neg_optab, op0, NULL_RTX, true); |
2825 | if (temp) | |
2826 | temp = expand_binop (mode, and_optab, op0, temp, NULL_RTX, | |
2827 | true, OPTAB_DIRECT); | |
2828 | if (temp) | |
2829 | temp = expand_unop_direct (mode, clz_optab, temp, NULL_RTX, true); | |
2830 | if (temp) | |
2831 | temp = expand_binop (mode, sub_optab, GEN_INT (GET_MODE_BITSIZE (mode) - 1), | |
2832 | temp, target, | |
2833 | true, OPTAB_DIRECT); | |
2834 | if (temp == 0) | |
2835 | { | |
2836 | end_sequence (); | |
2837 | return 0; | |
14670a74 | 2838 | } |
9cce5b20 ZW |
2839 | |
2840 | seq = get_insns (); | |
2841 | end_sequence (); | |
2842 | ||
2843 | add_equal_note (seq, temp, CTZ, op0, 0); | |
2844 | emit_insn (seq); | |
2845 | return temp; | |
14670a74 SL |
2846 | } |
2847 | ||
9cce5b20 ZW |
2848 | |
2849 | /* Try calculating ffs(x) using ctz(x) if we have that instruction, or | |
2850 | else with the sequence used by expand_clz. | |
2851 | ||
2852 | The ffs builtin promises to return zero for a zero value and ctz/clz | |
2853 | may have an undefined value in that case. If they do not give us a | |
2854 | convenient value, we have to generate a test and branch. */ | |
14670a74 | 2855 | static rtx |
9cce5b20 | 2856 | expand_ffs (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2857 | { |
a3324f26 ZW |
2858 | HOST_WIDE_INT val = 0; |
2859 | bool defined_at_zero = false; | |
9cce5b20 ZW |
2860 | rtx temp, seq; |
2861 | ||
2862 | if (optab_handler (ctz_optab, mode)->insn_code != CODE_FOR_nothing) | |
14670a74 | 2863 | { |
9cce5b20 | 2864 | start_sequence (); |
14670a74 | 2865 | |
9cce5b20 ZW |
2866 | temp = expand_unop_direct (mode, ctz_optab, op0, 0, true); |
2867 | if (!temp) | |
2868 | goto fail; | |
2869 | ||
2870 | defined_at_zero = (CTZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2); | |
14670a74 | 2871 | } |
9cce5b20 ZW |
2872 | else if (optab_handler (clz_optab, mode)->insn_code != CODE_FOR_nothing) |
2873 | { | |
2874 | start_sequence (); | |
2875 | temp = expand_ctz (mode, op0, 0); | |
2876 | if (!temp) | |
2877 | goto fail; | |
2878 | ||
2879 | if (CLZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2) | |
2880 | { | |
2881 | defined_at_zero = true; | |
2882 | val = (GET_MODE_BITSIZE (mode) - 1) - val; | |
2883 | } | |
2884 | } | |
2885 | else | |
2886 | return 0; | |
2887 | ||
2888 | if (defined_at_zero && val == -1) | |
2889 | /* No correction needed at zero. */; | |
2890 | else | |
2891 | { | |
2892 | /* We don't try to do anything clever with the situation found | |
2893 | on some processors (eg Alpha) where ctz(0:mode) == | |
2894 | bitsize(mode). If someone can think of a way to send N to -1 | |
2895 | and leave alone all values in the range 0..N-1 (where N is a | |
2896 | power of two), cheaper than this test-and-branch, please add it. | |
2897 | ||
2898 | The test-and-branch is done after the operation itself, in case | |
2899 | the operation sets condition codes that can be recycled for this. | |
2900 | (This is true on i386, for instance.) */ | |
2901 | ||
2902 | rtx nonzero_label = gen_label_rtx (); | |
2903 | emit_cmp_and_jump_insns (op0, CONST0_RTX (mode), NE, 0, | |
2904 | mode, true, nonzero_label); | |
2905 | ||
2906 | convert_move (temp, GEN_INT (-1), false); | |
2907 | emit_label (nonzero_label); | |
2908 | } | |
2909 | ||
2910 | /* temp now has a value in the range -1..bitsize-1. ffs is supposed | |
2911 | to produce a value in the range 0..bitsize. */ | |
2912 | temp = expand_binop (mode, add_optab, temp, GEN_INT (1), | |
2913 | target, false, OPTAB_DIRECT); | |
2914 | if (!temp) | |
2915 | goto fail; | |
2916 | ||
2917 | seq = get_insns (); | |
2918 | end_sequence (); | |
2919 | ||
2920 | add_equal_note (seq, temp, FFS, op0, 0); | |
2921 | emit_insn (seq); | |
2922 | return temp; | |
2923 | ||
2924 | fail: | |
2925 | end_sequence (); | |
14670a74 SL |
2926 | return 0; |
2927 | } | |
2928 | ||
c414ac1d | 2929 | /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain |
6b132673 RH |
2930 | conditions, VAL may already be a SUBREG against which we cannot generate |
2931 | a further SUBREG. In this case, we expect forcing the value into a | |
2932 | register will work around the situation. */ | |
2933 | ||
2934 | static rtx | |
2935 | lowpart_subreg_maybe_copy (enum machine_mode omode, rtx val, | |
2936 | enum machine_mode imode) | |
2937 | { | |
2938 | rtx ret; | |
2939 | ret = lowpart_subreg (omode, val, imode); | |
2940 | if (ret == NULL) | |
2941 | { | |
2942 | val = force_reg (imode, val); | |
2943 | ret = lowpart_subreg (omode, val, imode); | |
2944 | gcc_assert (ret != NULL); | |
2945 | } | |
2946 | return ret; | |
2947 | } | |
2948 | ||
8c55a142 RH |
2949 | /* Expand a floating point absolute value or negation operation via a |
2950 | logical operation on the sign bit. */ | |
2951 | ||
2952 | static rtx | |
2953 | expand_absneg_bit (enum rtx_code code, enum machine_mode mode, | |
2954 | rtx op0, rtx target) | |
2955 | { | |
2956 | const struct real_format *fmt; | |
2957 | int bitpos, word, nwords, i; | |
2958 | enum machine_mode imode; | |
2959 | HOST_WIDE_INT hi, lo; | |
2960 | rtx temp, insns; | |
2961 | ||
2962 | /* The format has to have a simple sign bit. */ | |
2963 | fmt = REAL_MODE_FORMAT (mode); | |
2964 | if (fmt == NULL) | |
2965 | return NULL_RTX; | |
2966 | ||
b87a0206 | 2967 | bitpos = fmt->signbit_rw; |
8c55a142 RH |
2968 | if (bitpos < 0) |
2969 | return NULL_RTX; | |
2970 | ||
2971 | /* Don't create negative zeros if the format doesn't support them. */ | |
2972 | if (code == NEG && !fmt->has_signed_zero) | |
2973 | return NULL_RTX; | |
2974 | ||
2975 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
2976 | { | |
2977 | imode = int_mode_for_mode (mode); | |
2978 | if (imode == BLKmode) | |
2979 | return NULL_RTX; | |
2980 | word = 0; | |
2981 | nwords = 1; | |
2982 | } | |
2983 | else | |
2984 | { | |
2985 | imode = word_mode; | |
2986 | ||
2987 | if (FLOAT_WORDS_BIG_ENDIAN) | |
2988 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
2989 | else | |
2990 | word = bitpos / BITS_PER_WORD; | |
2991 | bitpos = bitpos % BITS_PER_WORD; | |
2992 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
2993 | } | |
2994 | ||
2995 | if (bitpos < HOST_BITS_PER_WIDE_INT) | |
2996 | { | |
2997 | hi = 0; | |
2998 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2999 | } | |
3000 | else | |
3001 | { | |
3002 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
3003 | lo = 0; | |
3004 | } | |
3005 | if (code == ABS) | |
3006 | lo = ~lo, hi = ~hi; | |
3007 | ||
3008 | if (target == 0 || target == op0) | |
3009 | target = gen_reg_rtx (mode); | |
3010 | ||
3011 | if (nwords > 1) | |
3012 | { | |
3013 | start_sequence (); | |
3014 | ||
3015 | for (i = 0; i < nwords; ++i) | |
3016 | { | |
3017 | rtx targ_piece = operand_subword (target, i, 1, mode); | |
3018 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 3019 | |
8c55a142 RH |
3020 | if (i == word) |
3021 | { | |
3022 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
3023 | op0_piece, | |
3024 | immed_double_const (lo, hi, imode), | |
3025 | targ_piece, 1, OPTAB_LIB_WIDEN); | |
3026 | if (temp != targ_piece) | |
3027 | emit_move_insn (targ_piece, temp); | |
3028 | } | |
3029 | else | |
3030 | emit_move_insn (targ_piece, op0_piece); | |
3031 | } | |
3032 | ||
3033 | insns = get_insns (); | |
3034 | end_sequence (); | |
3035 | ||
d70dcf29 | 3036 | emit_insn (insns); |
8c55a142 RH |
3037 | } |
3038 | else | |
3039 | { | |
3040 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
3041 | gen_lowpart (imode, op0), | |
3042 | immed_double_const (lo, hi, imode), | |
3043 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); | |
3044 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
3045 | ||
3046 | set_unique_reg_note (get_last_insn (), REG_EQUAL, | |
3047 | gen_rtx_fmt_e (code, mode, copy_rtx (op0))); | |
3048 | } | |
3049 | ||
3050 | return target; | |
3051 | } | |
3052 | ||
9cce5b20 ZW |
3053 | /* As expand_unop, but will fail rather than attempt the operation in a |
3054 | different mode or with a libcall. */ | |
3055 | static rtx | |
3056 | expand_unop_direct (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
0c20a65f | 3057 | int unsignedp) |
77c9c6c2 | 3058 | { |
166cdb08 | 3059 | if (optab_handler (unoptab, mode)->insn_code != CODE_FOR_nothing) |
77c9c6c2 | 3060 | { |
166cdb08 | 3061 | int icode = (int) optab_handler (unoptab, mode)->insn_code; |
a995e389 | 3062 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 | 3063 | rtx xop0 = op0; |
9cce5b20 ZW |
3064 | rtx last = get_last_insn (); |
3065 | rtx pat, temp; | |
77c9c6c2 RK |
3066 | |
3067 | if (target) | |
3068 | temp = target; | |
3069 | else | |
3070 | temp = gen_reg_rtx (mode); | |
3071 | ||
3072 | if (GET_MODE (xop0) != VOIDmode | |
3073 | && GET_MODE (xop0) != mode0) | |
3074 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
3075 | ||
3076 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
3077 | ||
e3feb571 | 3078 | if (!insn_data[icode].operand[1].predicate (xop0, mode0)) |
77c9c6c2 RK |
3079 | xop0 = copy_to_mode_reg (mode0, xop0); |
3080 | ||
e3feb571 | 3081 | if (!insn_data[icode].operand[0].predicate (temp, mode)) |
77c9c6c2 RK |
3082 | temp = gen_reg_rtx (mode); |
3083 | ||
3084 | pat = GEN_FCN (icode) (temp, xop0); | |
3085 | if (pat) | |
3086 | { | |
2f937369 | 3087 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
b1ec3c92 | 3088 | && ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX)) |
77c9c6c2 RK |
3089 | { |
3090 | delete_insns_since (last); | |
b1ec3c92 | 3091 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
77c9c6c2 RK |
3092 | } |
3093 | ||
3094 | emit_insn (pat); | |
0c20a65f | 3095 | |
77c9c6c2 RK |
3096 | return temp; |
3097 | } | |
3098 | else | |
3099 | delete_insns_since (last); | |
3100 | } | |
9cce5b20 ZW |
3101 | return 0; |
3102 | } | |
3103 | ||
3104 | /* Generate code to perform an operation specified by UNOPTAB | |
3105 | on operand OP0, with result having machine-mode MODE. | |
3106 | ||
3107 | UNSIGNEDP is for the case where we have to widen the operands | |
3108 | to perform the operation. It says to use zero-extension. | |
3109 | ||
3110 | If TARGET is nonzero, the value | |
3111 | is generated there, if it is convenient to do so. | |
3112 | In all cases an rtx is returned for the locus of the value; | |
3113 | this may or may not be TARGET. */ | |
3114 | ||
3115 | rtx | |
3116 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
3117 | int unsignedp) | |
3118 | { | |
3119 | enum mode_class class = GET_MODE_CLASS (mode); | |
3120 | enum machine_mode wider_mode; | |
3121 | rtx temp; | |
8a33f100 | 3122 | rtx libfunc; |
9cce5b20 ZW |
3123 | |
3124 | temp = expand_unop_direct (mode, unoptab, op0, target, unsignedp); | |
3125 | if (temp) | |
3126 | return temp; | |
77c9c6c2 | 3127 | |
9a856ec7 RK |
3128 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
3129 | ||
9cce5b20 | 3130 | /* Widening (or narrowing) clz needs special treatment. */ |
2928cd7a RH |
3131 | if (unoptab == clz_optab) |
3132 | { | |
3133 | temp = widen_clz (mode, op0, target); | |
3134 | if (temp) | |
3135 | return temp; | |
9cce5b20 ZW |
3136 | |
3137 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
3138 | && optab_handler (unoptab, word_mode)->insn_code != CODE_FOR_nothing) | |
3139 | { | |
3140 | temp = expand_doubleword_clz (mode, op0, target); | |
3141 | if (temp) | |
3142 | return temp; | |
3143 | } | |
3144 | ||
2928cd7a RH |
3145 | goto try_libcall; |
3146 | } | |
3147 | ||
2e6834d3 | 3148 | /* Widening (or narrowing) bswap needs special treatment. */ |
167fa32c | 3149 | if (unoptab == bswap_optab) |
2e6834d3 RH |
3150 | { |
3151 | temp = widen_bswap (mode, op0, target); | |
3152 | if (temp) | |
3153 | return temp; | |
3154 | ||
3155 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
166cdb08 | 3156 | && optab_handler (unoptab, word_mode)->insn_code != CODE_FOR_nothing) |
2e6834d3 RH |
3157 | { |
3158 | temp = expand_doubleword_bswap (mode, op0, target); | |
3159 | if (temp) | |
3160 | return temp; | |
3161 | } | |
3162 | ||
3163 | goto try_libcall; | |
3164 | } | |
167fa32c | 3165 | |
86556d87 BE |
3166 | if (CLASS_HAS_WIDER_MODES_P (class)) |
3167 | for (wider_mode = GET_MODE_WIDER_MODE (mode); | |
3168 | wider_mode != VOIDmode; | |
9a856ec7 RK |
3169 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3170 | { | |
166cdb08 | 3171 | if (optab_handler (unoptab, wider_mode)->insn_code != CODE_FOR_nothing) |
9a856ec7 RK |
3172 | { |
3173 | rtx xop0 = op0; | |
9cce5b20 | 3174 | rtx last = get_last_insn (); |
9a856ec7 RK |
3175 | |
3176 | /* For certain operations, we need not actually extend | |
3177 | the narrow operand, as long as we will truncate the | |
835532b8 RK |
3178 | results to the same narrowness. */ |
3179 | ||
0661a3de | 3180 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
3181 | (unoptab == neg_optab |
3182 | || unoptab == one_cmpl_optab) | |
3183 | && class == MODE_INT); | |
0c20a65f | 3184 | |
b1ec3c92 CH |
3185 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3186 | unsignedp); | |
9a856ec7 RK |
3187 | |
3188 | if (temp) | |
3189 | { | |
cd7ec127 R |
3190 | if (class != MODE_INT |
3191 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
3192 | GET_MODE_BITSIZE (wider_mode))) | |
9a856ec7 RK |
3193 | { |
3194 | if (target == 0) | |
3195 | target = gen_reg_rtx (mode); | |
3196 | convert_move (target, temp, 0); | |
3197 | return target; | |
3198 | } | |
3199 | else | |
3200 | return gen_lowpart (mode, temp); | |
3201 | } | |
3202 | else | |
3203 | delete_insns_since (last); | |
3204 | } | |
3205 | } | |
3206 | ||
77c9c6c2 RK |
3207 | /* These can be done a word at a time. */ |
3208 | if (unoptab == one_cmpl_optab | |
3209 | && class == MODE_INT | |
3210 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
166cdb08 | 3211 | && optab_handler (unoptab, word_mode)->insn_code != CODE_FOR_nothing) |
77c9c6c2 | 3212 | { |
bb93b973 | 3213 | int i; |
77c9c6c2 RK |
3214 | rtx insns; |
3215 | ||
3216 | if (target == 0 || target == op0) | |
3217 | target = gen_reg_rtx (mode); | |
3218 | ||
3219 | start_sequence (); | |
3220 | ||
3221 | /* Do the actual arithmetic. */ | |
3222 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
3223 | { | |
3224 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 3225 | rtx x = expand_unop (word_mode, unoptab, |
77c9c6c2 RK |
3226 | operand_subword_force (op0, i, mode), |
3227 | target_piece, unsignedp); | |
bb93b973 | 3228 | |
77c9c6c2 RK |
3229 | if (target_piece != x) |
3230 | emit_move_insn (target_piece, x); | |
3231 | } | |
3232 | ||
3233 | insns = get_insns (); | |
3234 | end_sequence (); | |
3235 | ||
d70dcf29 | 3236 | emit_insn (insns); |
77c9c6c2 RK |
3237 | return target; |
3238 | } | |
3239 | ||
8c55a142 | 3240 | if (unoptab->code == NEG) |
4977bab6 | 3241 | { |
8c55a142 | 3242 | /* Try negating floating point values by flipping the sign bit. */ |
74b14698 | 3243 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 3244 | { |
8c55a142 RH |
3245 | temp = expand_absneg_bit (NEG, mode, op0, target); |
3246 | if (temp) | |
3247 | return temp; | |
3248 | } | |
9ee0a442 | 3249 | |
8c55a142 RH |
3250 | /* If there is no negation pattern, and we have no negative zero, |
3251 | try subtracting from zero. */ | |
3252 | if (!HONOR_SIGNED_ZEROS (mode)) | |
3253 | { | |
3254 | temp = expand_binop (mode, (unoptab == negv_optab | |
3255 | ? subv_optab : sub_optab), | |
3256 | CONST0_RTX (mode), op0, target, | |
3257 | unsignedp, OPTAB_DIRECT); | |
3258 | if (temp) | |
3259 | return temp; | |
3260 | } | |
4977bab6 ZW |
3261 | } |
3262 | ||
2928cd7a RH |
3263 | /* Try calculating parity (x) as popcount (x) % 2. */ |
3264 | if (unoptab == parity_optab) | |
3265 | { | |
3266 | temp = expand_parity (mode, op0, target); | |
3267 | if (temp) | |
3268 | return temp; | |
3269 | } | |
3270 | ||
14670a74 SL |
3271 | /* Try implementing ffs (x) in terms of clz (x). */ |
3272 | if (unoptab == ffs_optab) | |
3273 | { | |
3274 | temp = expand_ffs (mode, op0, target); | |
3275 | if (temp) | |
3276 | return temp; | |
3277 | } | |
3278 | ||
3279 | /* Try implementing ctz (x) in terms of clz (x). */ | |
3280 | if (unoptab == ctz_optab) | |
3281 | { | |
3282 | temp = expand_ctz (mode, op0, target); | |
3283 | if (temp) | |
3284 | return temp; | |
3285 | } | |
3286 | ||
2928cd7a | 3287 | try_libcall: |
139e5e08 | 3288 | /* Now try a library call in this mode. */ |
8a33f100 JH |
3289 | libfunc = optab_libfunc (unoptab, mode); |
3290 | if (libfunc) | |
77c9c6c2 RK |
3291 | { |
3292 | rtx insns; | |
9a7f678c | 3293 | rtx value; |
1230d7f8 | 3294 | rtx eq_value; |
2928cd7a RH |
3295 | enum machine_mode outmode = mode; |
3296 | ||
3297 | /* All of these functions return small values. Thus we choose to | |
3298 | have them return something that isn't a double-word. */ | |
3299 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
3300 | || unoptab == popcount_optab || unoptab == parity_optab) | |
cd2ac05b FH |
3301 | outmode |
3302 | = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node))); | |
77c9c6c2 RK |
3303 | |
3304 | start_sequence (); | |
3305 | ||
3306 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3307 | if the libcall is cse'd or moved. */ | |
8a33f100 | 3308 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, outmode, |
2928cd7a | 3309 | 1, op0, mode); |
77c9c6c2 RK |
3310 | insns = get_insns (); |
3311 | end_sequence (); | |
3312 | ||
2928cd7a | 3313 | target = gen_reg_rtx (outmode); |
1230d7f8 RS |
3314 | eq_value = gen_rtx_fmt_e (unoptab->code, mode, op0); |
3315 | if (GET_MODE_SIZE (outmode) < GET_MODE_SIZE (mode)) | |
3316 | eq_value = simplify_gen_unary (TRUNCATE, outmode, eq_value, mode); | |
3317 | else if (GET_MODE_SIZE (outmode) > GET_MODE_SIZE (mode)) | |
3318 | eq_value = simplify_gen_unary (ZERO_EXTEND, outmode, eq_value, mode); | |
3319 | emit_libcall_block (insns, target, value, eq_value); | |
77c9c6c2 RK |
3320 | |
3321 | return target; | |
3322 | } | |
3323 | ||
3324 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3325 | ||
86556d87 | 3326 | if (CLASS_HAS_WIDER_MODES_P (class)) |
77c9c6c2 | 3327 | { |
86556d87 BE |
3328 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3329 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
3330 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3331 | { | |
166cdb08 | 3332 | if ((optab_handler (unoptab, wider_mode)->insn_code |
77c9c6c2 | 3333 | != CODE_FOR_nothing) |
8a33f100 | 3334 | || optab_libfunc (unoptab, wider_mode)) |
77c9c6c2 | 3335 | { |
34e56753 | 3336 | rtx xop0 = op0; |
9cce5b20 | 3337 | rtx last = get_last_insn (); |
34e56753 RS |
3338 | |
3339 | /* For certain operations, we need not actually extend | |
3340 | the narrow operand, as long as we will truncate the | |
3341 | results to the same narrowness. */ | |
3342 | ||
0661a3de | 3343 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
3344 | (unoptab == neg_optab |
3345 | || unoptab == one_cmpl_optab) | |
3346 | && class == MODE_INT); | |
0c20a65f | 3347 | |
b1ec3c92 CH |
3348 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3349 | unsignedp); | |
34e56753 | 3350 | |
c117dddc KH |
3351 | /* If we are generating clz using wider mode, adjust the |
3352 | result. */ | |
3353 | if (unoptab == clz_optab && temp != 0) | |
3354 | temp = expand_binop (wider_mode, sub_optab, temp, | |
3355 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
3356 | - GET_MODE_BITSIZE (mode)), | |
3357 | target, true, OPTAB_DIRECT); | |
3358 | ||
34e56753 | 3359 | if (temp) |
77c9c6c2 | 3360 | { |
34e56753 RS |
3361 | if (class != MODE_INT) |
3362 | { | |
3363 | if (target == 0) | |
3364 | target = gen_reg_rtx (mode); | |
3365 | convert_move (target, temp, 0); | |
3366 | return target; | |
3367 | } | |
3368 | else | |
3369 | return gen_lowpart (mode, temp); | |
77c9c6c2 RK |
3370 | } |
3371 | else | |
34e56753 | 3372 | delete_insns_since (last); |
77c9c6c2 RK |
3373 | } |
3374 | } | |
3375 | } | |
3376 | ||
8c55a142 RH |
3377 | /* One final attempt at implementing negation via subtraction, |
3378 | this time allowing widening of the operand. */ | |
3379 | if (unoptab->code == NEG && !HONOR_SIGNED_ZEROS (mode)) | |
0c20a65f | 3380 | { |
b82b6eea | 3381 | rtx temp; |
91ce572a CC |
3382 | temp = expand_binop (mode, |
3383 | unoptab == negv_optab ? subv_optab : sub_optab, | |
3384 | CONST0_RTX (mode), op0, | |
3385 | target, unsignedp, OPTAB_LIB_WIDEN); | |
b82b6eea | 3386 | if (temp) |
8c55a142 | 3387 | return temp; |
b82b6eea | 3388 | } |
0c20a65f | 3389 | |
77c9c6c2 RK |
3390 | return 0; |
3391 | } | |
3392 | \f | |
decdfa82 RS |
3393 | /* Emit code to compute the absolute value of OP0, with result to |
3394 | TARGET if convenient. (TARGET may be 0.) The return value says | |
3395 | where the result actually is to be found. | |
3396 | ||
3397 | MODE is the mode of the operand; the mode of the result is | |
3398 | different but can be deduced from MODE. | |
3399 | ||
91813b28 | 3400 | */ |
7fd01431 RK |
3401 | |
3402 | rtx | |
0c20a65f AJ |
3403 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
3404 | int result_unsignedp) | |
7fd01431 | 3405 | { |
2ef0a555 | 3406 | rtx temp; |
7fd01431 | 3407 | |
91ce572a CC |
3408 | if (! flag_trapv) |
3409 | result_unsignedp = 1; | |
3410 | ||
7fd01431 | 3411 | /* First try to do it with a special abs instruction. */ |
91ce572a CC |
3412 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
3413 | op0, target, 0); | |
7fd01431 RK |
3414 | if (temp != 0) |
3415 | return temp; | |
3416 | ||
4977bab6 | 3417 | /* For floating point modes, try clearing the sign bit. */ |
3d8bf70f | 3418 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 3419 | { |
8c55a142 RH |
3420 | temp = expand_absneg_bit (ABS, mode, op0, target); |
3421 | if (temp) | |
3422 | return temp; | |
4977bab6 ZW |
3423 | } |
3424 | ||
14a774a9 | 3425 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
166cdb08 | 3426 | if (optab_handler (smax_optab, mode)->insn_code != CODE_FOR_nothing |
8c55a142 | 3427 | && !HONOR_SIGNED_ZEROS (mode)) |
14a774a9 RK |
3428 | { |
3429 | rtx last = get_last_insn (); | |
3430 | ||
3431 | temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); | |
3432 | if (temp != 0) | |
3433 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3434 | OPTAB_WIDEN); | |
3435 | ||
3436 | if (temp != 0) | |
3437 | return temp; | |
3438 | ||
3439 | delete_insns_since (last); | |
3440 | } | |
3441 | ||
7fd01431 RK |
3442 | /* If this machine has expensive jumps, we can do integer absolute |
3443 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
e1078cfc | 3444 | where W is the width of MODE. */ |
7fd01431 RK |
3445 | |
3446 | if (GET_MODE_CLASS (mode) == MODE_INT && BRANCH_COST >= 2) | |
3447 | { | |
3448 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
3449 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3450 | NULL_RTX, 0); | |
3451 | ||
3452 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3453 | OPTAB_LIB_WIDEN); | |
3454 | if (temp != 0) | |
91ce572a CC |
3455 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
3456 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
7fd01431 RK |
3457 | |
3458 | if (temp != 0) | |
3459 | return temp; | |
3460 | } | |
3461 | ||
2ef0a555 RH |
3462 | return NULL_RTX; |
3463 | } | |
3464 | ||
3465 | rtx | |
0c20a65f AJ |
3466 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
3467 | int result_unsignedp, int safe) | |
2ef0a555 RH |
3468 | { |
3469 | rtx temp, op1; | |
3470 | ||
77173bbe KH |
3471 | if (! flag_trapv) |
3472 | result_unsignedp = 1; | |
3473 | ||
2ef0a555 RH |
3474 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
3475 | if (temp != 0) | |
3476 | return temp; | |
3477 | ||
7fd01431 | 3478 | /* If that does not win, use conditional jump and negate. */ |
5c0bf747 RK |
3479 | |
3480 | /* It is safe to use the target if it is the same | |
3481 | as the source if this is also a pseudo register */ | |
f8cfc6aa | 3482 | if (op0 == target && REG_P (op0) |
5c0bf747 RK |
3483 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) |
3484 | safe = 1; | |
3485 | ||
7fd01431 RK |
3486 | op1 = gen_label_rtx (); |
3487 | if (target == 0 || ! safe | |
3488 | || GET_MODE (target) != mode | |
3c0cb5de | 3489 | || (MEM_P (target) && MEM_VOLATILE_P (target)) |
f8cfc6aa | 3490 | || (REG_P (target) |
7fd01431 RK |
3491 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) |
3492 | target = gen_reg_rtx (mode); | |
3493 | ||
3494 | emit_move_insn (target, op0); | |
3495 | NO_DEFER_POP; | |
3496 | ||
3bf78d3b RS |
3497 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
3498 | NULL_RTX, NULL_RTX, op1); | |
7fd01431 | 3499 | |
91ce572a CC |
3500 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
3501 | target, target, 0); | |
7fd01431 RK |
3502 | if (op0 != target) |
3503 | emit_move_insn (target, op0); | |
3504 | emit_label (op1); | |
3505 | OK_DEFER_POP; | |
3506 | return target; | |
3507 | } | |
046625fa | 3508 | |
ae394659 RH |
3509 | /* A subroutine of expand_copysign, perform the copysign operation using the |
3510 | abs and neg primitives advertised to exist on the target. The assumption | |
3511 | is that we have a split register file, and leaving op0 in fp registers, | |
3512 | and not playing with subregs so much, will help the register allocator. */ | |
046625fa | 3513 | |
9abd1955 | 3514 | static rtx |
ae394659 RH |
3515 | expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target, |
3516 | int bitpos, bool op0_is_abs) | |
046625fa | 3517 | { |
046625fa | 3518 | enum machine_mode imode; |
d0c9d431 UB |
3519 | int icode; |
3520 | rtx sign, label; | |
046625fa | 3521 | |
ae394659 RH |
3522 | if (target == op1) |
3523 | target = NULL_RTX; | |
046625fa | 3524 | |
d0c9d431 UB |
3525 | /* Check if the back end provides an insn that handles signbit for the |
3526 | argument's mode. */ | |
3527 | icode = (int) signbit_optab->handlers [(int) mode].insn_code; | |
3528 | if (icode != CODE_FOR_nothing) | |
ae394659 | 3529 | { |
d0c9d431 UB |
3530 | imode = insn_data[icode].operand[0].mode; |
3531 | sign = gen_reg_rtx (imode); | |
3532 | emit_unop_insn (icode, sign, op1, UNKNOWN); | |
ae394659 RH |
3533 | } |
3534 | else | |
3535 | { | |
d0c9d431 UB |
3536 | HOST_WIDE_INT hi, lo; |
3537 | ||
3538 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
3539 | { | |
3540 | imode = int_mode_for_mode (mode); | |
3541 | if (imode == BLKmode) | |
3542 | return NULL_RTX; | |
3543 | op1 = gen_lowpart (imode, op1); | |
3544 | } | |
ae394659 | 3545 | else |
d0c9d431 UB |
3546 | { |
3547 | int word; | |
046625fa | 3548 | |
d0c9d431 UB |
3549 | imode = word_mode; |
3550 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3551 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3552 | else | |
3553 | word = bitpos / BITS_PER_WORD; | |
3554 | bitpos = bitpos % BITS_PER_WORD; | |
3555 | op1 = operand_subword_force (op1, word, mode); | |
3556 | } | |
3557 | ||
3558 | if (bitpos < HOST_BITS_PER_WIDE_INT) | |
3559 | { | |
3560 | hi = 0; | |
3561 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
3562 | } | |
ae394659 | 3563 | else |
d0c9d431 UB |
3564 | { |
3565 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
3566 | lo = 0; | |
3567 | } | |
3568 | ||
3569 | sign = gen_reg_rtx (imode); | |
3570 | sign = expand_binop (imode, and_optab, op1, | |
3571 | immed_double_const (lo, hi, imode), | |
3572 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
ae394659 | 3573 | } |
046625fa | 3574 | |
d0c9d431 | 3575 | if (!op0_is_abs) |
8c55a142 | 3576 | { |
d0c9d431 UB |
3577 | op0 = expand_unop (mode, abs_optab, op0, target, 0); |
3578 | if (op0 == NULL) | |
3579 | return NULL_RTX; | |
3580 | target = op0; | |
8c55a142 | 3581 | } |
ae394659 RH |
3582 | else |
3583 | { | |
d0c9d431 UB |
3584 | if (target == NULL_RTX) |
3585 | target = copy_to_reg (op0); | |
3586 | else | |
3587 | emit_move_insn (target, op0); | |
ae394659 RH |
3588 | } |
3589 | ||
ae394659 | 3590 | label = gen_label_rtx (); |
d0c9d431 | 3591 | emit_cmp_and_jump_insns (sign, const0_rtx, EQ, NULL_RTX, imode, 1, label); |
ae394659 RH |
3592 | |
3593 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3594 | op0 = simplify_unary_operation (NEG, mode, op0, mode); | |
3595 | else | |
3596 | op0 = expand_unop (mode, neg_optab, op0, target, 0); | |
3597 | if (op0 != target) | |
3598 | emit_move_insn (target, op0); | |
3599 | ||
3600 | emit_label (label); | |
3601 | ||
3602 | return target; | |
3603 | } | |
3604 | ||
3605 | ||
3606 | /* A subroutine of expand_copysign, perform the entire copysign operation | |
3607 | with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS | |
3608 | is true if op0 is known to have its sign bit clear. */ | |
3609 | ||
3610 | static rtx | |
3611 | expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
3612 | int bitpos, bool op0_is_abs) | |
3613 | { | |
3614 | enum machine_mode imode; | |
3615 | HOST_WIDE_INT hi, lo; | |
3616 | int word, nwords, i; | |
3617 | rtx temp, insns; | |
046625fa | 3618 | |
8c55a142 | 3619 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) |
046625fa | 3620 | { |
8c55a142 RH |
3621 | imode = int_mode_for_mode (mode); |
3622 | if (imode == BLKmode) | |
3623 | return NULL_RTX; | |
3624 | word = 0; | |
3625 | nwords = 1; | |
3626 | } | |
3627 | else | |
3628 | { | |
3629 | imode = word_mode; | |
3630 | ||
3631 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3632 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3633 | else | |
3634 | word = bitpos / BITS_PER_WORD; | |
3635 | bitpos = bitpos % BITS_PER_WORD; | |
3636 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
046625fa RH |
3637 | } |
3638 | ||
3639 | if (bitpos < HOST_BITS_PER_WIDE_INT) | |
3640 | { | |
3641 | hi = 0; | |
3642 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
3643 | } | |
3644 | else | |
3645 | { | |
3646 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
3647 | lo = 0; | |
3648 | } | |
3649 | ||
8c55a142 RH |
3650 | if (target == 0 || target == op0 || target == op1) |
3651 | target = gen_reg_rtx (mode); | |
3652 | ||
3653 | if (nwords > 1) | |
046625fa | 3654 | { |
8c55a142 RH |
3655 | start_sequence (); |
3656 | ||
3657 | for (i = 0; i < nwords; ++i) | |
046625fa | 3658 | { |
8c55a142 RH |
3659 | rtx targ_piece = operand_subword (target, i, 1, mode); |
3660 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 3661 | |
8c55a142 RH |
3662 | if (i == word) |
3663 | { | |
ae394659 | 3664 | if (!op0_is_abs) |
8c55a142 RH |
3665 | op0_piece = expand_binop (imode, and_optab, op0_piece, |
3666 | immed_double_const (~lo, ~hi, imode), | |
3667 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3668 | ||
3669 | op1 = expand_binop (imode, and_optab, | |
3670 | operand_subword_force (op1, i, mode), | |
3671 | immed_double_const (lo, hi, imode), | |
3672 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3673 | ||
3674 | temp = expand_binop (imode, ior_optab, op0_piece, op1, | |
3675 | targ_piece, 1, OPTAB_LIB_WIDEN); | |
3676 | if (temp != targ_piece) | |
3677 | emit_move_insn (targ_piece, temp); | |
3678 | } | |
3679 | else | |
3680 | emit_move_insn (targ_piece, op0_piece); | |
046625fa | 3681 | } |
8c55a142 RH |
3682 | |
3683 | insns = get_insns (); | |
3684 | end_sequence (); | |
3685 | ||
d70dcf29 | 3686 | emit_insn (insns); |
046625fa RH |
3687 | } |
3688 | else | |
8c55a142 RH |
3689 | { |
3690 | op1 = expand_binop (imode, and_optab, gen_lowpart (imode, op1), | |
3691 | immed_double_const (lo, hi, imode), | |
3692 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3693 | ||
3694 | op0 = gen_lowpart (imode, op0); | |
ae394659 | 3695 | if (!op0_is_abs) |
8c55a142 RH |
3696 | op0 = expand_binop (imode, and_optab, op0, |
3697 | immed_double_const (~lo, ~hi, imode), | |
3698 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3699 | ||
3700 | temp = expand_binop (imode, ior_optab, op0, op1, | |
3701 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); | |
3702 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
3703 | } | |
046625fa RH |
3704 | |
3705 | return target; | |
3706 | } | |
ae394659 | 3707 | |
c414ac1d | 3708 | /* Expand the C99 copysign operation. OP0 and OP1 must be the same |
ae394659 RH |
3709 | scalar floating point mode. Return NULL if we do not know how to |
3710 | expand the operation inline. */ | |
3711 | ||
3712 | rtx | |
3713 | expand_copysign (rtx op0, rtx op1, rtx target) | |
3714 | { | |
3715 | enum machine_mode mode = GET_MODE (op0); | |
3716 | const struct real_format *fmt; | |
ae394659 RH |
3717 | bool op0_is_abs; |
3718 | rtx temp; | |
3719 | ||
3720 | gcc_assert (SCALAR_FLOAT_MODE_P (mode)); | |
3721 | gcc_assert (GET_MODE (op1) == mode); | |
3722 | ||
3723 | /* First try to do it with a special instruction. */ | |
3724 | temp = expand_binop (mode, copysign_optab, op0, op1, | |
3725 | target, 0, OPTAB_DIRECT); | |
3726 | if (temp) | |
3727 | return temp; | |
3728 | ||
3729 | fmt = REAL_MODE_FORMAT (mode); | |
3730 | if (fmt == NULL || !fmt->has_signed_zero) | |
3731 | return NULL_RTX; | |
3732 | ||
ae394659 RH |
3733 | op0_is_abs = false; |
3734 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3735 | { | |
3736 | if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) | |
3737 | op0 = simplify_unary_operation (ABS, mode, op0, mode); | |
3738 | op0_is_abs = true; | |
3739 | } | |
3740 | ||
c064fde5 RS |
3741 | if (fmt->signbit_ro >= 0 |
3742 | && (GET_CODE (op0) == CONST_DOUBLE | |
166cdb08 JH |
3743 | || (optab_handler (neg_optab, mode)->insn_code != CODE_FOR_nothing |
3744 | && optab_handler (abs_optab, mode)->insn_code != CODE_FOR_nothing))) | |
ae394659 RH |
3745 | { |
3746 | temp = expand_copysign_absneg (mode, op0, op1, target, | |
c064fde5 | 3747 | fmt->signbit_ro, op0_is_abs); |
ae394659 RH |
3748 | if (temp) |
3749 | return temp; | |
3750 | } | |
3751 | ||
c064fde5 RS |
3752 | if (fmt->signbit_rw < 0) |
3753 | return NULL_RTX; | |
3754 | return expand_copysign_bit (mode, op0, op1, target, | |
3755 | fmt->signbit_rw, op0_is_abs); | |
ae394659 | 3756 | } |
7fd01431 | 3757 | \f |
77c9c6c2 RK |
3758 | /* Generate an instruction whose insn-code is INSN_CODE, |
3759 | with two operands: an output TARGET and an input OP0. | |
3760 | TARGET *must* be nonzero, and the output is always stored there. | |
3761 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3762 | the value that is stored into TARGET. */ | |
3763 | ||
3764 | void | |
0c20a65f | 3765 | emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) |
77c9c6c2 | 3766 | { |
b3694847 | 3767 | rtx temp; |
a995e389 | 3768 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 RK |
3769 | rtx pat; |
3770 | ||
ad76cef8 | 3771 | temp = target; |
77c9c6c2 | 3772 | |
77c9c6c2 RK |
3773 | /* Now, if insn does not accept our operands, put them into pseudos. */ |
3774 | ||
e3feb571 | 3775 | if (!insn_data[icode].operand[1].predicate (op0, mode0)) |
77c9c6c2 RK |
3776 | op0 = copy_to_mode_reg (mode0, op0); |
3777 | ||
1d8eeb63 | 3778 | if (!insn_data[icode].operand[0].predicate (temp, GET_MODE (temp))) |
77c9c6c2 RK |
3779 | temp = gen_reg_rtx (GET_MODE (temp)); |
3780 | ||
3781 | pat = GEN_FCN (icode) (temp, op0); | |
3782 | ||
2f937369 | 3783 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
b1ec3c92 | 3784 | add_equal_note (pat, temp, code, op0, NULL_RTX); |
0c20a65f | 3785 | |
77c9c6c2 RK |
3786 | emit_insn (pat); |
3787 | ||
3788 | if (temp != target) | |
3789 | emit_move_insn (target, temp); | |
3790 | } | |
3791 | \f | |
326a31e9 R |
3792 | struct no_conflict_data |
3793 | { | |
3794 | rtx target, first, insn; | |
3795 | bool must_stay; | |
3796 | }; | |
3797 | ||
d70dcf29 KZ |
3798 | /* Called via note_stores by emit_libcall_block. Set P->must_stay if |
3799 | the currently examined clobber / store has to stay in the list of | |
3800 | insns that constitute the actual libcall block. */ | |
326a31e9 | 3801 | static void |
7bc980e1 | 3802 | no_conflict_move_test (rtx dest, const_rtx set, void *p0) |
326a31e9 | 3803 | { |
d3bfe4de | 3804 | struct no_conflict_data *p= (struct no_conflict_data *) p0; |
326a31e9 R |
3805 | |
3806 | /* If this inns directly contributes to setting the target, it must stay. */ | |
3807 | if (reg_overlap_mentioned_p (p->target, dest)) | |
3808 | p->must_stay = true; | |
3809 | /* If we haven't committed to keeping any other insns in the list yet, | |
3810 | there is nothing more to check. */ | |
3811 | else if (p->insn == p->first) | |
3812 | return; | |
3813 | /* If this insn sets / clobbers a register that feeds one of the insns | |
3814 | already in the list, this insn has to stay too. */ | |
9617ccfd R |
3815 | else if (reg_overlap_mentioned_p (dest, PATTERN (p->first)) |
3816 | || (CALL_P (p->first) && (find_reg_fusage (p->first, USE, dest))) | |
326a31e9 R |
3817 | || reg_used_between_p (dest, p->first, p->insn) |
3818 | /* Likewise if this insn depends on a register set by a previous | |
ca7a5aec R |
3819 | insn in the list, or if it sets a result (presumably a hard |
3820 | register) that is set or clobbered by a previous insn. | |
3821 | N.B. the modified_*_p (SET_DEST...) tests applied to a MEM | |
3822 | SET_DEST perform the former check on the address, and the latter | |
3823 | check on the MEM. */ | |
326a31e9 R |
3824 | || (GET_CODE (set) == SET |
3825 | && (modified_in_p (SET_SRC (set), p->first) | |
ca7a5aec R |
3826 | || modified_in_p (SET_DEST (set), p->first) |
3827 | || modified_between_p (SET_SRC (set), p->first, p->insn) | |
3828 | || modified_between_p (SET_DEST (set), p->first, p->insn)))) | |
326a31e9 R |
3829 | p->must_stay = true; |
3830 | } | |
3831 | ||
77c9c6c2 RK |
3832 | \f |
3833 | /* Emit code to make a call to a constant function or a library call. | |
3834 | ||
3835 | INSNS is a list containing all insns emitted in the call. | |
3836 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3837 | to TARGET, which is logically equivalent to EQUIV. | |
3838 | ||
3839 | We first emit any insns that set a pseudo on the assumption that these are | |
3840 | loading constants into registers; doing so allows them to be safely cse'ed | |
3841 | between blocks. Then we emit all the other insns in the block, followed by | |
3842 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
856905c2 SB |
3843 | note with an operand of EQUIV. */ |
3844 | ||
77c9c6c2 | 3845 | void |
0c20a65f | 3846 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) |
77c9c6c2 | 3847 | { |
aff2c2d3 | 3848 | rtx final_dest = target; |
856905c2 | 3849 | rtx prev, next, last, insn; |
77c9c6c2 | 3850 | |
aff2c2d3 BS |
3851 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3852 | into a MEM later. Protect the libcall block from this change. */ | |
3853 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3854 | target = gen_reg_rtx (GET_MODE (target)); | |
0c20a65f | 3855 | |
5154e79a AH |
3856 | /* If we're using non-call exceptions, a libcall corresponding to an |
3857 | operation that may trap may also trap. */ | |
3858 | if (flag_non_call_exceptions && may_trap_p (equiv)) | |
3859 | { | |
3860 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
4b4bf941 | 3861 | if (CALL_P (insn)) |
5154e79a AH |
3862 | { |
3863 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3864 | |
5154e79a AH |
3865 | if (note != 0 && INTVAL (XEXP (note, 0)) <= 0) |
3866 | remove_note (insn, note); | |
3867 | } | |
3868 | } | |
3869 | else | |
b472794d | 3870 | /* look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION |
c29ea88a | 3871 | reg note to indicate that this call cannot throw or execute a nonlocal |
cf67d231 | 3872 | goto (unless there is already a REG_EH_REGION note, in which case |
897aa57f | 3873 | we update it). */ |
5154e79a | 3874 | for (insn = insns; insn; insn = NEXT_INSN (insn)) |
4b4bf941 | 3875 | if (CALL_P (insn)) |
5154e79a AH |
3876 | { |
3877 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3878 | |
5154e79a | 3879 | if (note != 0) |
60c81c89 | 3880 | XEXP (note, 0) = constm1_rtx; |
5154e79a | 3881 | else |
60c81c89 | 3882 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, |
5154e79a AH |
3883 | REG_NOTES (insn)); |
3884 | } | |
b472794d | 3885 | |
77c9c6c2 | 3886 | /* First emit all insns that set pseudos. Remove them from the list as |
ccf5f342 | 3887 | we go. Avoid insns that set pseudos which were referenced in previous |
29ebe69a | 3888 | insns. These can be generated by move_by_pieces, for example, |
ccf5f342 RK |
3889 | to update an address. Similarly, avoid insns that reference things |
3890 | set in previous insns. */ | |
77c9c6c2 RK |
3891 | |
3892 | for (insn = insns; insn; insn = next) | |
3893 | { | |
3894 | rtx set = single_set (insn); | |
3895 | ||
3896 | next = NEXT_INSN (insn); | |
3897 | ||
f8cfc6aa | 3898 | if (set != 0 && REG_P (SET_DEST (set)) |
748ebfc7 | 3899 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) |
77c9c6c2 | 3900 | { |
748ebfc7 R |
3901 | struct no_conflict_data data; |
3902 | ||
3903 | data.target = const0_rtx; | |
3904 | data.first = insns; | |
3905 | data.insn = insn; | |
3906 | data.must_stay = 0; | |
3907 | note_stores (PATTERN (insn), no_conflict_move_test, &data); | |
3908 | if (! data.must_stay) | |
3909 | { | |
3910 | if (PREV_INSN (insn)) | |
3911 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3912 | else | |
3913 | insns = next; | |
77c9c6c2 | 3914 | |
748ebfc7 R |
3915 | if (next) |
3916 | PREV_INSN (next) = PREV_INSN (insn); | |
77c9c6c2 | 3917 | |
748ebfc7 R |
3918 | add_insn (insn); |
3919 | } | |
77c9c6c2 | 3920 | } |
695a94b3 RS |
3921 | |
3922 | /* Some ports use a loop to copy large arguments onto the stack. | |
3923 | Don't move anything outside such a loop. */ | |
4b4bf941 | 3924 | if (LABEL_P (insn)) |
695a94b3 | 3925 | break; |
77c9c6c2 RK |
3926 | } |
3927 | ||
3928 | prev = get_last_insn (); | |
3929 | ||
3930 | /* Write the remaining insns followed by the final copy. */ | |
3931 | ||
3932 | for (insn = insns; insn; insn = next) | |
3933 | { | |
3934 | next = NEXT_INSN (insn); | |
3935 | ||
3936 | add_insn (insn); | |
3937 | } | |
3938 | ||
3939 | last = emit_move_insn (target, result); | |
166cdb08 | 3940 | if (optab_handler (mov_optab, GET_MODE (target))->insn_code |
02214a5c | 3941 | != CODE_FOR_nothing) |
5fa671cf | 3942 | set_unique_reg_note (last, REG_EQUAL, copy_rtx (equiv)); |
77c9c6c2 | 3943 | |
e85427f9 BS |
3944 | if (final_dest != target) |
3945 | emit_move_insn (final_dest, target); | |
77c9c6c2 RK |
3946 | } |
3947 | \f | |
1c0290ea | 3948 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
1eb8759b RH |
3949 | PURPOSE describes how this comparison will be used. CODE is the rtx |
3950 | comparison code we will be using. | |
3951 | ||
3952 | ??? Actually, CODE is slightly weaker than that. A target is still | |
0c20a65f | 3953 | required to implement all of the normal bcc operations, but not |
1eb8759b | 3954 | required to implement all (or any) of the unordered bcc operations. */ |
0c20a65f | 3955 | |
1c0290ea | 3956 | int |
0c20a65f AJ |
3957 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
3958 | enum can_compare_purpose purpose) | |
b30f05db BS |
3959 | { |
3960 | do | |
3961 | { | |
166cdb08 | 3962 | if (optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing) |
1eb8759b RH |
3963 | { |
3964 | if (purpose == ccp_jump) | |
7e1a450d | 3965 | return bcc_gen_fctn[(int) code] != NULL; |
1eb8759b | 3966 | else if (purpose == ccp_store_flag) |
7e1a450d | 3967 | return setcc_gen_code[(int) code] != CODE_FOR_nothing; |
1eb8759b RH |
3968 | else |
3969 | /* There's only one cmov entry point, and it's allowed to fail. */ | |
3970 | return 1; | |
3971 | } | |
1c0290ea | 3972 | if (purpose == ccp_jump |
166cdb08 | 3973 | && optab_handler (cbranch_optab, mode)->insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3974 | return 1; |
3975 | if (purpose == ccp_cmov | |
166cdb08 | 3976 | && optab_handler (cmov_optab, mode)->insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3977 | return 1; |
3978 | if (purpose == ccp_store_flag | |
166cdb08 | 3979 | && optab_handler (cstore_optab, mode)->insn_code != CODE_FOR_nothing) |
1c0290ea | 3980 | return 1; |
b30f05db | 3981 | mode = GET_MODE_WIDER_MODE (mode); |
1c0290ea BS |
3982 | } |
3983 | while (mode != VOIDmode); | |
b30f05db BS |
3984 | |
3985 | return 0; | |
3986 | } | |
3987 | ||
3988 | /* This function is called when we are going to emit a compare instruction that | |
3989 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
3990 | ||
3991 | *PMODE is the mode of the inputs (in case they are const_int). | |
3992 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
77c9c6c2 RK |
3993 | this matters if they need to be widened. |
3994 | ||
a06ef755 | 3995 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
77c9c6c2 | 3996 | |
b30f05db BS |
3997 | This function performs all the setup necessary so that the caller only has |
3998 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
3999 | comparison or emitting a library call to perform the comparison if no insn | |
4000 | is available to handle it. | |
4001 | The values which are passed in through pointers can be modified; the caller | |
0e61db61 NS |
4002 | should perform the comparison on the modified values. Constant |
4003 | comparisons must have already been folded. */ | |
77c9c6c2 | 4004 | |
a06ef755 | 4005 | static void |
0c20a65f AJ |
4006 | prepare_cmp_insn (rtx *px, rtx *py, enum rtx_code *pcomparison, rtx size, |
4007 | enum machine_mode *pmode, int *punsignedp, | |
4008 | enum can_compare_purpose purpose) | |
77c9c6c2 | 4009 | { |
b30f05db BS |
4010 | enum machine_mode mode = *pmode; |
4011 | rtx x = *px, y = *py; | |
4012 | int unsignedp = *punsignedp; | |
8a33f100 | 4013 | rtx libfunc; |
77c9c6c2 | 4014 | |
7c27e184 PB |
4015 | /* If we are inside an appropriately-short loop and we are optimizing, |
4016 | force expensive constants into a register. */ | |
4017 | if (CONSTANT_P (x) && optimize | |
b437f1a7 | 4018 | && rtx_cost (x, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
4019 | x = force_reg (mode, x); |
4020 | ||
7c27e184 | 4021 | if (CONSTANT_P (y) && optimize |
b437f1a7 | 4022 | && rtx_cost (y, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
4023 | y = force_reg (mode, y); |
4024 | ||
362cc3d4 | 4025 | #ifdef HAVE_cc0 |
0e61db61 NS |
4026 | /* Make sure if we have a canonical comparison. The RTL |
4027 | documentation states that canonical comparisons are required only | |
4028 | for targets which have cc0. */ | |
e3feb571 | 4029 | gcc_assert (!CONSTANT_P (x) || CONSTANT_P (y)); |
362cc3d4 MH |
4030 | #endif |
4031 | ||
77c9c6c2 RK |
4032 | /* Don't let both operands fail to indicate the mode. */ |
4033 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
4034 | x = force_reg (mode, x); | |
4035 | ||
4036 | /* Handle all BLKmode compares. */ | |
4037 | ||
4038 | if (mode == BLKmode) | |
4039 | { | |
118355a0 ZW |
4040 | enum machine_mode cmp_mode, result_mode; |
4041 | enum insn_code cmp_code; | |
4042 | tree length_type; | |
4043 | rtx libfunc; | |
b30f05db | 4044 | rtx result; |
118355a0 | 4045 | rtx opalign |
f4dc10d1 | 4046 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); |
b30f05db | 4047 | |
e3feb571 | 4048 | gcc_assert (size); |
118355a0 | 4049 | |
118355a0 ZW |
4050 | /* Try to use a memory block compare insn - either cmpstr |
4051 | or cmpmem will do. */ | |
4052 | for (cmp_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
4053 | cmp_mode != VOIDmode; | |
4054 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode)) | |
358b8f01 | 4055 | { |
118355a0 ZW |
4056 | cmp_code = cmpmem_optab[cmp_mode]; |
4057 | if (cmp_code == CODE_FOR_nothing) | |
4058 | cmp_code = cmpstr_optab[cmp_mode]; | |
40c1d5f8 AS |
4059 | if (cmp_code == CODE_FOR_nothing) |
4060 | cmp_code = cmpstrn_optab[cmp_mode]; | |
118355a0 ZW |
4061 | if (cmp_code == CODE_FOR_nothing) |
4062 | continue; | |
4063 | ||
4064 | /* Must make sure the size fits the insn's mode. */ | |
4065 | if ((GET_CODE (size) == CONST_INT | |
4066 | && INTVAL (size) >= (1 << GET_MODE_BITSIZE (cmp_mode))) | |
4067 | || (GET_MODE_BITSIZE (GET_MODE (size)) | |
4068 | > GET_MODE_BITSIZE (cmp_mode))) | |
4069 | continue; | |
4070 | ||
4071 | result_mode = insn_data[cmp_code].operand[0].mode; | |
358b8f01 | 4072 | result = gen_reg_rtx (result_mode); |
118355a0 ZW |
4073 | size = convert_to_mode (cmp_mode, size, 1); |
4074 | emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign)); | |
4075 | ||
4076 | *px = result; | |
4077 | *py = const0_rtx; | |
4078 | *pmode = result_mode; | |
4079 | return; | |
77c9c6c2 | 4080 | } |
118355a0 | 4081 | |
8f99553f | 4082 | /* Otherwise call a library function, memcmp. */ |
118355a0 ZW |
4083 | libfunc = memcmp_libfunc; |
4084 | length_type = sizetype; | |
118355a0 ZW |
4085 | result_mode = TYPE_MODE (integer_type_node); |
4086 | cmp_mode = TYPE_MODE (length_type); | |
4087 | size = convert_to_mode (TYPE_MODE (length_type), size, | |
8df83eae | 4088 | TYPE_UNSIGNED (length_type)); |
118355a0 | 4089 | |
84b8030f | 4090 | result = emit_library_call_value (libfunc, 0, LCT_PURE, |
118355a0 ZW |
4091 | result_mode, 3, |
4092 | XEXP (x, 0), Pmode, | |
4093 | XEXP (y, 0), Pmode, | |
4094 | size, cmp_mode); | |
b30f05db BS |
4095 | *px = result; |
4096 | *py = const0_rtx; | |
4097 | *pmode = result_mode; | |
77c9c6c2 RK |
4098 | return; |
4099 | } | |
4100 | ||
27ab3e91 RH |
4101 | /* Don't allow operands to the compare to trap, as that can put the |
4102 | compare and branch in different basic blocks. */ | |
4103 | if (flag_non_call_exceptions) | |
4104 | { | |
4105 | if (may_trap_p (x)) | |
4106 | x = force_reg (mode, x); | |
4107 | if (may_trap_p (y)) | |
4108 | y = force_reg (mode, y); | |
4109 | } | |
4110 | ||
b30f05db BS |
4111 | *px = x; |
4112 | *py = y; | |
1eb8759b | 4113 | if (can_compare_p (*pcomparison, mode, purpose)) |
b30f05db | 4114 | return; |
77c9c6c2 RK |
4115 | |
4116 | /* Handle a lib call just for the mode we are using. */ | |
4117 | ||
8a33f100 JH |
4118 | libfunc = optab_libfunc (cmp_optab, mode); |
4119 | if (libfunc && !SCALAR_FLOAT_MODE_P (mode)) | |
77c9c6c2 | 4120 | { |
9725066d JL |
4121 | rtx result; |
4122 | ||
77c9c6c2 RK |
4123 | /* If we want unsigned, and this mode has a distinct unsigned |
4124 | comparison routine, use that. */ | |
8a33f100 JH |
4125 | if (unsignedp) |
4126 | { | |
ba8a73e9 EB |
4127 | rtx ulibfunc = optab_libfunc (ucmp_optab, mode); |
4128 | if (ulibfunc) | |
4129 | libfunc = ulibfunc; | |
8a33f100 | 4130 | } |
77c9c6c2 | 4131 | |
84b8030f | 4132 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
c7ff6e7a AK |
4133 | targetm.libgcc_cmp_return_mode (), |
4134 | 2, x, mode, y, mode); | |
9725066d | 4135 | |
f34312c2 CD |
4136 | /* There are two kinds of comparison routines. Biased routines |
4137 | return 0/1/2, and unbiased routines return -1/0/1. Other parts | |
4138 | of gcc expect that the comparison operation is equivalent | |
4139 | to the modified comparison. For signed comparisons compare the | |
4140 | result against 1 in the biased case, and zero in the unbiased | |
4141 | case. For unsigned comparisons always compare against 1 after | |
917f1b7e | 4142 | biasing the unbiased result by adding 1. This gives us a way to |
f34312c2 | 4143 | represent LTU. */ |
b30f05db | 4144 | *px = result; |
b30f05db | 4145 | *pmode = word_mode; |
f34312c2 CD |
4146 | *py = const1_rtx; |
4147 | ||
4148 | if (!TARGET_LIB_INT_CMP_BIASED) | |
b3f8d95d | 4149 | { |
f34312c2 CD |
4150 | if (*punsignedp) |
4151 | *px = plus_constant (result, 1); | |
4152 | else | |
4153 | *py = const0_rtx; | |
b3f8d95d | 4154 | } |
77c9c6c2 RK |
4155 | return; |
4156 | } | |
4157 | ||
74b14698 | 4158 | gcc_assert (SCALAR_FLOAT_MODE_P (mode)); |
e3feb571 | 4159 | prepare_float_lib_cmp (px, py, pcomparison, pmode, punsignedp); |
77c9c6c2 RK |
4160 | } |
4161 | ||
b30f05db BS |
4162 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
4163 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
4fe9b91c | 4164 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
b30f05db | 4165 | that it is accepted by the operand predicate. Return the new value. */ |
749a2da1 | 4166 | |
6db0fb0e | 4167 | static rtx |
0c20a65f AJ |
4168 | prepare_operand (int icode, rtx x, int opnum, enum machine_mode mode, |
4169 | enum machine_mode wider_mode, int unsignedp) | |
b30f05db | 4170 | { |
b30f05db BS |
4171 | if (mode != wider_mode) |
4172 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
4173 | ||
e3feb571 | 4174 | if (!insn_data[icode].operand[opnum].predicate |
a995e389 | 4175 | (x, insn_data[icode].operand[opnum].mode)) |
d893ccde | 4176 | { |
ef4375b2 | 4177 | if (reload_completed) |
d893ccde RH |
4178 | return NULL_RTX; |
4179 | x = copy_to_mode_reg (insn_data[icode].operand[opnum].mode, x); | |
4180 | } | |
4181 | ||
b30f05db BS |
4182 | return x; |
4183 | } | |
4184 | ||
4185 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
4186 | we can do the comparison. | |
4187 | The arguments are the same as for emit_cmp_and_jump_insns; but LABEL may | |
4188 | be NULL_RTX which indicates that only a comparison is to be generated. */ | |
4189 | ||
4190 | static void | |
0c20a65f AJ |
4191 | emit_cmp_and_jump_insn_1 (rtx x, rtx y, enum machine_mode mode, |
4192 | enum rtx_code comparison, int unsignedp, rtx label) | |
b30f05db BS |
4193 | { |
4194 | rtx test = gen_rtx_fmt_ee (comparison, mode, x, y); | |
4195 | enum mode_class class = GET_MODE_CLASS (mode); | |
4196 | enum machine_mode wider_mode = mode; | |
4197 | ||
4198 | /* Try combined insns first. */ | |
8127d0e0 | 4199 | do |
b30f05db BS |
4200 | { |
4201 | enum insn_code icode; | |
4202 | PUT_MODE (test, wider_mode); | |
4203 | ||
1c0290ea | 4204 | if (label) |
0c20a65f | 4205 | { |
166cdb08 | 4206 | icode = optab_handler (cbranch_optab, wider_mode)->insn_code; |
0c20a65f | 4207 | |
1c0290ea | 4208 | if (icode != CODE_FOR_nothing |
e3feb571 | 4209 | && insn_data[icode].operand[0].predicate (test, wider_mode)) |
1c0290ea BS |
4210 | { |
4211 | x = prepare_operand (icode, x, 1, mode, wider_mode, unsignedp); | |
4212 | y = prepare_operand (icode, y, 2, mode, wider_mode, unsignedp); | |
4213 | emit_jump_insn (GEN_FCN (icode) (test, x, y, label)); | |
4214 | return; | |
4215 | } | |
4216 | } | |
4217 | ||
b30f05db | 4218 | /* Handle some compares against zero. */ |
166cdb08 | 4219 | icode = (int) optab_handler (tst_optab, wider_mode)->insn_code; |
b30f05db BS |
4220 | if (y == CONST0_RTX (mode) && icode != CODE_FOR_nothing) |
4221 | { | |
4222 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
4223 | emit_insn (GEN_FCN (icode) (x)); | |
4224 | if (label) | |
e3feb571 | 4225 | emit_jump_insn (bcc_gen_fctn[(int) comparison] (label)); |
b30f05db BS |
4226 | return; |
4227 | } | |
4228 | ||
4229 | /* Handle compares for which there is a directly suitable insn. */ | |
4230 | ||
166cdb08 | 4231 | icode = (int) optab_handler (cmp_optab, wider_mode)->insn_code; |
b30f05db BS |
4232 | if (icode != CODE_FOR_nothing) |
4233 | { | |
4234 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
4235 | y = prepare_operand (icode, y, 1, mode, wider_mode, unsignedp); | |
4236 | emit_insn (GEN_FCN (icode) (x, y)); | |
4237 | if (label) | |
e3feb571 | 4238 | emit_jump_insn (bcc_gen_fctn[(int) comparison] (label)); |
b30f05db BS |
4239 | return; |
4240 | } | |
4241 | ||
86556d87 | 4242 | if (!CLASS_HAS_WIDER_MODES_P (class)) |
8127d0e0 | 4243 | break; |
b30f05db BS |
4244 | |
4245 | wider_mode = GET_MODE_WIDER_MODE (wider_mode); | |
7e1a450d | 4246 | } |
8127d0e0 NS |
4247 | while (wider_mode != VOIDmode); |
4248 | ||
e3feb571 | 4249 | gcc_unreachable (); |
b30f05db BS |
4250 | } |
4251 | ||
362cc3d4 MH |
4252 | /* Generate code to compare X with Y so that the condition codes are |
4253 | set and to jump to LABEL if the condition is true. If X is a | |
4254 | constant and Y is not a constant, then the comparison is swapped to | |
4255 | ensure that the comparison RTL has the canonical form. | |
4256 | ||
c5d5d461 JL |
4257 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
4258 | need to be widened by emit_cmp_insn. UNSIGNEDP is also used to select | |
4259 | the proper branch condition code. | |
362cc3d4 | 4260 | |
a06ef755 | 4261 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
362cc3d4 | 4262 | |
c5d5d461 JL |
4263 | MODE is the mode of the inputs (in case they are const_int). |
4264 | ||
4265 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). It will | |
4266 | be passed unchanged to emit_cmp_insn, then potentially converted into an | |
4267 | unsigned variant based on UNSIGNEDP to select a proper jump instruction. */ | |
362cc3d4 MH |
4268 | |
4269 | void | |
0c20a65f AJ |
4270 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
4271 | enum machine_mode mode, int unsignedp, rtx label) | |
362cc3d4 | 4272 | { |
8c9864f3 JH |
4273 | rtx op0 = x, op1 = y; |
4274 | ||
4275 | /* Swap operands and condition to ensure canonical RTL. */ | |
4276 | if (swap_commutative_operands_p (x, y)) | |
362cc3d4 | 4277 | { |
7e0b4eae PB |
4278 | /* If we're not emitting a branch, callers are required to pass |
4279 | operands in an order conforming to canonical RTL. We relax this | |
cea618ac | 4280 | for commutative comparisons so callers using EQ don't need to do |
7e0b4eae PB |
4281 | swapping by hand. */ |
4282 | gcc_assert (label || (comparison == swap_condition (comparison))); | |
8c9864f3 JH |
4283 | |
4284 | op0 = y, op1 = x; | |
4285 | comparison = swap_condition (comparison); | |
362cc3d4 | 4286 | } |
0ca40216 JL |
4287 | |
4288 | #ifdef HAVE_cc0 | |
0e61db61 NS |
4289 | /* If OP0 is still a constant, then both X and Y must be constants. |
4290 | Force X into a register to create canonical RTL. */ | |
0ca40216 JL |
4291 | if (CONSTANT_P (op0)) |
4292 | op0 = force_reg (mode, op0); | |
4293 | #endif | |
4294 | ||
c5d5d461 JL |
4295 | if (unsignedp) |
4296 | comparison = unsigned_condition (comparison); | |
a06ef755 RK |
4297 | |
4298 | prepare_cmp_insn (&op0, &op1, &comparison, size, &mode, &unsignedp, | |
1c0290ea | 4299 | ccp_jump); |
b30f05db BS |
4300 | emit_cmp_and_jump_insn_1 (op0, op1, mode, comparison, unsignedp, label); |
4301 | } | |
4302 | ||
4303 | /* Like emit_cmp_and_jump_insns, but generate only the comparison. */ | |
19caa751 | 4304 | |
b30f05db | 4305 | void |
0c20a65f AJ |
4306 | emit_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
4307 | enum machine_mode mode, int unsignedp) | |
b30f05db | 4308 | { |
a06ef755 | 4309 | emit_cmp_and_jump_insns (x, y, comparison, size, mode, unsignedp, 0); |
362cc3d4 | 4310 | } |
77c9c6c2 RK |
4311 | \f |
4312 | /* Emit a library call comparison between floating point X and Y. | |
4313 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
4314 | ||
c5c60e15 | 4315 | static void |
0c20a65f AJ |
4316 | prepare_float_lib_cmp (rtx *px, rtx *py, enum rtx_code *pcomparison, |
4317 | enum machine_mode *pmode, int *punsignedp) | |
77c9c6c2 | 4318 | { |
c5c60e15 | 4319 | enum rtx_code comparison = *pcomparison; |
c9034561 | 4320 | enum rtx_code swapped = swap_condition (comparison); |
b3f8d95d | 4321 | enum rtx_code reversed = reverse_condition_maybe_unordered (comparison); |
ad76cef8 PB |
4322 | rtx x = *px; |
4323 | rtx y = *py; | |
c9034561 | 4324 | enum machine_mode orig_mode = GET_MODE (x); |
7fecf2c7 | 4325 | enum machine_mode mode, cmp_mode; |
37bf20ee | 4326 | rtx value, target, insns, equiv; |
0a300065 | 4327 | rtx libfunc = 0; |
b3f8d95d | 4328 | bool reversed_p = false; |
7fecf2c7 | 4329 | cmp_mode = targetm.libgcc_cmp_return_mode (); |
77c9c6c2 | 4330 | |
86556d87 BE |
4331 | for (mode = orig_mode; |
4332 | mode != VOIDmode; | |
4333 | mode = GET_MODE_WIDER_MODE (mode)) | |
77c9c6c2 | 4334 | { |
8a33f100 | 4335 | if ((libfunc = optab_libfunc (code_to_optab[comparison], mode))) |
c9034561 | 4336 | break; |
77c9c6c2 | 4337 | |
8a33f100 | 4338 | if ((libfunc = optab_libfunc (code_to_optab[swapped] , mode))) |
77c9c6c2 | 4339 | { |
c9034561 ZW |
4340 | rtx tmp; |
4341 | tmp = x; x = y; y = tmp; | |
4342 | comparison = swapped; | |
4343 | break; | |
77c9c6c2 | 4344 | } |
77c9c6c2 | 4345 | |
8a33f100 | 4346 | if ((libfunc = optab_libfunc (code_to_optab[reversed], mode)) |
b3f8d95d MM |
4347 | && FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, reversed)) |
4348 | { | |
4349 | comparison = reversed; | |
4350 | reversed_p = true; | |
4351 | break; | |
4352 | } | |
4353 | } | |
5906d013 | 4354 | |
e3feb571 | 4355 | gcc_assert (mode != VOIDmode); |
0a300065 | 4356 | |
c9034561 ZW |
4357 | if (mode != orig_mode) |
4358 | { | |
4359 | x = convert_to_mode (mode, x, 0); | |
4360 | y = convert_to_mode (mode, y, 0); | |
4361 | } | |
4362 | ||
17796a89 RS |
4363 | /* Attach a REG_EQUAL note describing the semantics of the libcall to |
4364 | the RTL. The allows the RTL optimizers to delete the libcall if the | |
4365 | condition can be determined at compile-time. */ | |
4366 | if (comparison == UNORDERED) | |
4367 | { | |
7fecf2c7 AP |
4368 | rtx temp = simplify_gen_relational (NE, cmp_mode, mode, x, x); |
4369 | equiv = simplify_gen_relational (NE, cmp_mode, mode, y, y); | |
4370 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, | |
17796a89 RS |
4371 | temp, const_true_rtx, equiv); |
4372 | } | |
4373 | else | |
4374 | { | |
7fecf2c7 | 4375 | equiv = simplify_gen_relational (comparison, cmp_mode, mode, x, y); |
17796a89 | 4376 | if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) |
bd831d5c | 4377 | { |
17796a89 | 4378 | rtx true_rtx, false_rtx; |
37bf20ee | 4379 | |
17796a89 RS |
4380 | switch (comparison) |
4381 | { | |
4382 | case EQ: | |
4383 | true_rtx = const0_rtx; | |
4384 | false_rtx = const_true_rtx; | |
4385 | break; | |
4386 | ||
4387 | case NE: | |
4388 | true_rtx = const_true_rtx; | |
4389 | false_rtx = const0_rtx; | |
4390 | break; | |
4391 | ||
4392 | case GT: | |
4393 | true_rtx = const1_rtx; | |
4394 | false_rtx = const0_rtx; | |
4395 | break; | |
4396 | ||
4397 | case GE: | |
4398 | true_rtx = const0_rtx; | |
4399 | false_rtx = constm1_rtx; | |
4400 | break; | |
4401 | ||
4402 | case LT: | |
4403 | true_rtx = constm1_rtx; | |
4404 | false_rtx = const0_rtx; | |
4405 | break; | |
4406 | ||
4407 | case LE: | |
4408 | true_rtx = const0_rtx; | |
4409 | false_rtx = const1_rtx; | |
4410 | break; | |
4411 | ||
4412 | default: | |
e3feb571 | 4413 | gcc_unreachable (); |
bd831d5c | 4414 | } |
7fecf2c7 | 4415 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, |
17796a89 | 4416 | equiv, true_rtx, false_rtx); |
bd831d5c RS |
4417 | } |
4418 | } | |
37bf20ee RS |
4419 | |
4420 | start_sequence (); | |
4421 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, | |
7fecf2c7 | 4422 | cmp_mode, 2, x, mode, y, mode); |
37bf20ee RS |
4423 | insns = get_insns (); |
4424 | end_sequence (); | |
4425 | ||
7fecf2c7 | 4426 | target = gen_reg_rtx (cmp_mode); |
37bf20ee RS |
4427 | emit_libcall_block (insns, target, value, equiv); |
4428 | ||
c9034561 ZW |
4429 | if (comparison == UNORDERED |
4430 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
b3f8d95d | 4431 | comparison = reversed_p ? EQ : NE; |
c9034561 | 4432 | |
37bf20ee | 4433 | *px = target; |
b30f05db | 4434 | *py = const0_rtx; |
7fecf2c7 | 4435 | *pmode = cmp_mode; |
c9034561 | 4436 | *pcomparison = comparison; |
b30f05db | 4437 | *punsignedp = 0; |
77c9c6c2 RK |
4438 | } |
4439 | \f | |
4440 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4441 | ||
4442 | void | |
0c20a65f | 4443 | emit_indirect_jump (rtx loc) |
77c9c6c2 | 4444 | { |
e3feb571 NS |
4445 | if (!insn_data[(int) CODE_FOR_indirect_jump].operand[0].predicate |
4446 | (loc, Pmode)) | |
f2de2775 | 4447 | loc = copy_to_mode_reg (Pmode, loc); |
77c9c6c2 RK |
4448 | |
4449 | emit_jump_insn (gen_indirect_jump (loc)); | |
9649fb4d | 4450 | emit_barrier (); |
77c9c6c2 RK |
4451 | } |
4452 | \f | |
49c4584c DE |
4453 | #ifdef HAVE_conditional_move |
4454 | ||
4455 | /* Emit a conditional move instruction if the machine supports one for that | |
4456 | condition and machine mode. | |
4457 | ||
4458 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4459 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4460 | both be constants. | |
4461 | ||
4462 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4463 | should be stored there. MODE is the mode to use should they be constants. | |
4464 | If it is VOIDmode, they cannot both be constants. | |
4465 | ||
4466 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4467 | is not supported. */ | |
4468 | ||
4469 | rtx | |
0c20a65f AJ |
4470 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4471 | enum machine_mode cmode, rtx op2, rtx op3, | |
4472 | enum machine_mode mode, int unsignedp) | |
49c4584c DE |
4473 | { |
4474 | rtx tem, subtarget, comparison, insn; | |
4475 | enum insn_code icode; | |
e5c56fd9 | 4476 | enum rtx_code reversed; |
49c4584c DE |
4477 | |
4478 | /* If one operand is constant, make it the second one. Only do this | |
4479 | if the other operand is not constant as well. */ | |
4480 | ||
e5c56fd9 | 4481 | if (swap_commutative_operands_p (op0, op1)) |
49c4584c DE |
4482 | { |
4483 | tem = op0; | |
4484 | op0 = op1; | |
4485 | op1 = tem; | |
4486 | code = swap_condition (code); | |
4487 | } | |
4488 | ||
c5c76735 JL |
4489 | /* get_condition will prefer to generate LT and GT even if the old |
4490 | comparison was against zero, so undo that canonicalization here since | |
4491 | comparisons against zero are cheaper. */ | |
87d9741e | 4492 | if (code == LT && op1 == const1_rtx) |
c5c76735 | 4493 | code = LE, op1 = const0_rtx; |
87d9741e | 4494 | else if (code == GT && op1 == constm1_rtx) |
c5c76735 JL |
4495 | code = GE, op1 = const0_rtx; |
4496 | ||
49c4584c DE |
4497 | if (cmode == VOIDmode) |
4498 | cmode = GET_MODE (op0); | |
4499 | ||
e5c56fd9 JH |
4500 | if (swap_commutative_operands_p (op2, op3) |
4501 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4502 | != UNKNOWN)) | |
49c4584c DE |
4503 | { |
4504 | tem = op2; | |
4505 | op2 = op3; | |
4506 | op3 = tem; | |
e5c56fd9 | 4507 | code = reversed; |
49c4584c DE |
4508 | } |
4509 | ||
4510 | if (mode == VOIDmode) | |
4511 | mode = GET_MODE (op2); | |
4512 | ||
4513 | icode = movcc_gen_code[mode]; | |
4514 | ||
4515 | if (icode == CODE_FOR_nothing) | |
4516 | return 0; | |
4517 | ||
ad76cef8 | 4518 | if (!target) |
49c4584c DE |
4519 | target = gen_reg_rtx (mode); |
4520 | ||
4521 | subtarget = target; | |
4522 | ||
49c4584c DE |
4523 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4524 | ||
e3feb571 | 4525 | if (!insn_data[icode].operand[0].predicate |
a995e389 RH |
4526 | (subtarget, insn_data[icode].operand[0].mode)) |
4527 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
49c4584c | 4528 | |
e3feb571 | 4529 | if (!insn_data[icode].operand[2].predicate |
a995e389 RH |
4530 | (op2, insn_data[icode].operand[2].mode)) |
4531 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
49c4584c | 4532 | |
e3feb571 | 4533 | if (!insn_data[icode].operand[3].predicate |
a995e389 RH |
4534 | (op3, insn_data[icode].operand[3].mode)) |
4535 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
49c4584c DE |
4536 | |
4537 | /* Everything should now be in the suitable form, so emit the compare insn | |
4538 | and then the conditional move. */ | |
4539 | ||
0c20a65f | 4540 | comparison |
a06ef755 | 4541 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
49c4584c DE |
4542 | |
4543 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
144a5f9d JL |
4544 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4545 | return NULL and let the caller figure out how best to deal with this | |
4546 | situation. */ | |
49c4584c | 4547 | if (GET_CODE (comparison) != code) |
144a5f9d | 4548 | return NULL_RTX; |
0c20a65f | 4549 | |
49c4584c DE |
4550 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4551 | ||
4552 | /* If that failed, then give up. */ | |
4553 | if (insn == 0) | |
4554 | return 0; | |
4555 | ||
4556 | emit_insn (insn); | |
4557 | ||
4558 | if (subtarget != target) | |
4559 | convert_move (target, subtarget, 0); | |
4560 | ||
4561 | return target; | |
4562 | } | |
4563 | ||
40f03658 | 4564 | /* Return nonzero if a conditional move of mode MODE is supported. |
49c4584c DE |
4565 | |
4566 | This function is for combine so it can tell whether an insn that looks | |
4567 | like a conditional move is actually supported by the hardware. If we | |
4568 | guess wrong we lose a bit on optimization, but that's it. */ | |
4569 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4570 | comparisons, and vice versa. How do we handle them? */ | |
4571 | ||
4572 | int | |
0c20a65f | 4573 | can_conditionally_move_p (enum machine_mode mode) |
49c4584c DE |
4574 | { |
4575 | if (movcc_gen_code[mode] != CODE_FOR_nothing) | |
4576 | return 1; | |
4577 | ||
4578 | return 0; | |
4579 | } | |
4580 | ||
4581 | #endif /* HAVE_conditional_move */ | |
068f5dea JH |
4582 | |
4583 | /* Emit a conditional addition instruction if the machine supports one for that | |
4584 | condition and machine mode. | |
4585 | ||
4586 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4587 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4588 | both be constants. | |
4589 | ||
4590 | OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3 | |
4591 | should be stored there. MODE is the mode to use should they be constants. | |
4592 | If it is VOIDmode, they cannot both be constants. | |
4593 | ||
4594 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4595 | is not supported. */ | |
4596 | ||
4597 | rtx | |
0c20a65f AJ |
4598 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4599 | enum machine_mode cmode, rtx op2, rtx op3, | |
4600 | enum machine_mode mode, int unsignedp) | |
068f5dea JH |
4601 | { |
4602 | rtx tem, subtarget, comparison, insn; | |
4603 | enum insn_code icode; | |
4604 | enum rtx_code reversed; | |
4605 | ||
4606 | /* If one operand is constant, make it the second one. Only do this | |
4607 | if the other operand is not constant as well. */ | |
4608 | ||
4609 | if (swap_commutative_operands_p (op0, op1)) | |
4610 | { | |
4611 | tem = op0; | |
4612 | op0 = op1; | |
4613 | op1 = tem; | |
4614 | code = swap_condition (code); | |
4615 | } | |
4616 | ||
4617 | /* get_condition will prefer to generate LT and GT even if the old | |
4618 | comparison was against zero, so undo that canonicalization here since | |
4619 | comparisons against zero are cheaper. */ | |
87d9741e | 4620 | if (code == LT && op1 == const1_rtx) |
068f5dea | 4621 | code = LE, op1 = const0_rtx; |
87d9741e | 4622 | else if (code == GT && op1 == constm1_rtx) |
068f5dea JH |
4623 | code = GE, op1 = const0_rtx; |
4624 | ||
4625 | if (cmode == VOIDmode) | |
4626 | cmode = GET_MODE (op0); | |
4627 | ||
4628 | if (swap_commutative_operands_p (op2, op3) | |
4629 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4630 | != UNKNOWN)) | |
4631 | { | |
4632 | tem = op2; | |
4633 | op2 = op3; | |
4634 | op3 = tem; | |
4635 | code = reversed; | |
4636 | } | |
4637 | ||
4638 | if (mode == VOIDmode) | |
4639 | mode = GET_MODE (op2); | |
4640 | ||
166cdb08 | 4641 | icode = optab_handler (addcc_optab, mode)->insn_code; |
068f5dea JH |
4642 | |
4643 | if (icode == CODE_FOR_nothing) | |
4644 | return 0; | |
4645 | ||
ad76cef8 | 4646 | if (!target) |
068f5dea JH |
4647 | target = gen_reg_rtx (mode); |
4648 | ||
068f5dea JH |
4649 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4650 | ||
e3feb571 | 4651 | if (!insn_data[icode].operand[0].predicate |
ad76cef8 | 4652 | (target, insn_data[icode].operand[0].mode)) |
068f5dea | 4653 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); |
ad76cef8 PB |
4654 | else |
4655 | subtarget = target; | |
068f5dea | 4656 | |
e3feb571 | 4657 | if (!insn_data[icode].operand[2].predicate |
068f5dea JH |
4658 | (op2, insn_data[icode].operand[2].mode)) |
4659 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
4660 | ||
e3feb571 | 4661 | if (!insn_data[icode].operand[3].predicate |
068f5dea JH |
4662 | (op3, insn_data[icode].operand[3].mode)) |
4663 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
4664 | ||
4665 | /* Everything should now be in the suitable form, so emit the compare insn | |
4666 | and then the conditional move. */ | |
4667 | ||
0c20a65f | 4668 | comparison |
068f5dea JH |
4669 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
4670 | ||
4671 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
4672 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just | |
4673 | return NULL and let the caller figure out how best to deal with this | |
4674 | situation. */ | |
4675 | if (GET_CODE (comparison) != code) | |
4676 | return NULL_RTX; | |
0c20a65f | 4677 | |
068f5dea JH |
4678 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4679 | ||
4680 | /* If that failed, then give up. */ | |
4681 | if (insn == 0) | |
4682 | return 0; | |
4683 | ||
4684 | emit_insn (insn); | |
4685 | ||
4686 | if (subtarget != target) | |
4687 | convert_move (target, subtarget, 0); | |
4688 | ||
4689 | return target; | |
4690 | } | |
49c4584c | 4691 | \f |
0913e4b4 AO |
4692 | /* These functions attempt to generate an insn body, rather than |
4693 | emitting the insn, but if the gen function already emits them, we | |
ad76cef8 | 4694 | make no attempt to turn them back into naked patterns. */ |
77c9c6c2 RK |
4695 | |
4696 | /* Generate and return an insn body to add Y to X. */ | |
4697 | ||
4698 | rtx | |
0c20a65f | 4699 | gen_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4700 | { |
166cdb08 | 4701 | int icode = (int) optab_handler (add_optab, GET_MODE (x))->insn_code; |
77c9c6c2 | 4702 | |
e3feb571 NS |
4703 | gcc_assert (insn_data[icode].operand[0].predicate |
4704 | (x, insn_data[icode].operand[0].mode)); | |
4705 | gcc_assert (insn_data[icode].operand[1].predicate | |
4706 | (x, insn_data[icode].operand[1].mode)); | |
4707 | gcc_assert (insn_data[icode].operand[2].predicate | |
4708 | (y, insn_data[icode].operand[2].mode)); | |
77c9c6c2 | 4709 | |
e3feb571 | 4710 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4711 | } |
4712 | ||
e78d8e51 ZW |
4713 | /* Generate and return an insn body to add r1 and c, |
4714 | storing the result in r0. */ | |
8a33f100 | 4715 | |
e78d8e51 | 4716 | rtx |
0c20a65f | 4717 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
e78d8e51 | 4718 | { |
166cdb08 | 4719 | int icode = (int) optab_handler (add_optab, GET_MODE (r0))->insn_code; |
e78d8e51 | 4720 | |
7e1a450d | 4721 | if (icode == CODE_FOR_nothing |
e3feb571 NS |
4722 | || !(insn_data[icode].operand[0].predicate |
4723 | (r0, insn_data[icode].operand[0].mode)) | |
4724 | || !(insn_data[icode].operand[1].predicate | |
4725 | (r1, insn_data[icode].operand[1].mode)) | |
4726 | || !(insn_data[icode].operand[2].predicate | |
4727 | (c, insn_data[icode].operand[2].mode))) | |
e78d8e51 ZW |
4728 | return NULL_RTX; |
4729 | ||
e3feb571 | 4730 | return GEN_FCN (icode) (r0, r1, c); |
e78d8e51 ZW |
4731 | } |
4732 | ||
77c9c6c2 | 4733 | int |
0c20a65f | 4734 | have_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4735 | { |
fb7e77d7 TM |
4736 | int icode; |
4737 | ||
e3feb571 | 4738 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4739 | |
166cdb08 | 4740 | icode = (int) optab_handler (add_optab, GET_MODE (x))->insn_code; |
fb7e77d7 TM |
4741 | |
4742 | if (icode == CODE_FOR_nothing) | |
4743 | return 0; | |
4744 | ||
e3feb571 NS |
4745 | if (!(insn_data[icode].operand[0].predicate |
4746 | (x, insn_data[icode].operand[0].mode)) | |
4747 | || !(insn_data[icode].operand[1].predicate | |
4748 | (x, insn_data[icode].operand[1].mode)) | |
4749 | || !(insn_data[icode].operand[2].predicate | |
4750 | (y, insn_data[icode].operand[2].mode))) | |
fb7e77d7 TM |
4751 | return 0; |
4752 | ||
4753 | return 1; | |
77c9c6c2 RK |
4754 | } |
4755 | ||
4756 | /* Generate and return an insn body to subtract Y from X. */ | |
4757 | ||
4758 | rtx | |
0c20a65f | 4759 | gen_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4760 | { |
166cdb08 | 4761 | int icode = (int) optab_handler (sub_optab, GET_MODE (x))->insn_code; |
77c9c6c2 | 4762 | |
e3feb571 NS |
4763 | gcc_assert (insn_data[icode].operand[0].predicate |
4764 | (x, insn_data[icode].operand[0].mode)); | |
4765 | gcc_assert (insn_data[icode].operand[1].predicate | |
4766 | (x, insn_data[icode].operand[1].mode)); | |
4767 | gcc_assert (insn_data[icode].operand[2].predicate | |
4768 | (y, insn_data[icode].operand[2].mode)); | |
77c9c6c2 | 4769 | |
e3feb571 | 4770 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4771 | } |
4772 | ||
ef89d648 ZW |
4773 | /* Generate and return an insn body to subtract r1 and c, |
4774 | storing the result in r0. */ | |
8a33f100 | 4775 | |
ef89d648 | 4776 | rtx |
0c20a65f | 4777 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ef89d648 | 4778 | { |
166cdb08 | 4779 | int icode = (int) optab_handler (sub_optab, GET_MODE (r0))->insn_code; |
ef89d648 | 4780 | |
7e1a450d | 4781 | if (icode == CODE_FOR_nothing |
e3feb571 NS |
4782 | || !(insn_data[icode].operand[0].predicate |
4783 | (r0, insn_data[icode].operand[0].mode)) | |
4784 | || !(insn_data[icode].operand[1].predicate | |
4785 | (r1, insn_data[icode].operand[1].mode)) | |
4786 | || !(insn_data[icode].operand[2].predicate | |
4787 | (c, insn_data[icode].operand[2].mode))) | |
ef89d648 ZW |
4788 | return NULL_RTX; |
4789 | ||
e3feb571 | 4790 | return GEN_FCN (icode) (r0, r1, c); |
ef89d648 ZW |
4791 | } |
4792 | ||
77c9c6c2 | 4793 | int |
0c20a65f | 4794 | have_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4795 | { |
fb7e77d7 TM |
4796 | int icode; |
4797 | ||
e3feb571 | 4798 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4799 | |
166cdb08 | 4800 | icode = (int) optab_handler (sub_optab, GET_MODE (x))->insn_code; |
fb7e77d7 TM |
4801 | |
4802 | if (icode == CODE_FOR_nothing) | |
4803 | return 0; | |
4804 | ||
e3feb571 NS |
4805 | if (!(insn_data[icode].operand[0].predicate |
4806 | (x, insn_data[icode].operand[0].mode)) | |
4807 | || !(insn_data[icode].operand[1].predicate | |
4808 | (x, insn_data[icode].operand[1].mode)) | |
4809 | || !(insn_data[icode].operand[2].predicate | |
4810 | (y, insn_data[icode].operand[2].mode))) | |
fb7e77d7 TM |
4811 | return 0; |
4812 | ||
4813 | return 1; | |
77c9c6c2 RK |
4814 | } |
4815 | ||
e3654226 | 4816 | /* Generate the body of an instruction to copy Y into X. |
2f937369 | 4817 | It may be a list of insns, if one insn isn't enough. */ |
77c9c6c2 RK |
4818 | |
4819 | rtx | |
0c20a65f | 4820 | gen_move_insn (rtx x, rtx y) |
77c9c6c2 | 4821 | { |
e3654226 | 4822 | rtx seq; |
77c9c6c2 | 4823 | |
e3654226 RS |
4824 | start_sequence (); |
4825 | emit_move_insn_1 (x, y); | |
2f937369 | 4826 | seq = get_insns (); |
e3654226 RS |
4827 | end_sequence (); |
4828 | return seq; | |
77c9c6c2 RK |
4829 | } |
4830 | \f | |
34e56753 RS |
4831 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4832 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4833 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
77c9c6c2 | 4834 | |
34e56753 | 4835 | enum insn_code |
0c20a65f AJ |
4836 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4837 | int unsignedp) | |
77c9c6c2 | 4838 | { |
85363ca0 | 4839 | convert_optab tab; |
6dd12198 SE |
4840 | #ifdef HAVE_ptr_extend |
4841 | if (unsignedp < 0) | |
4842 | return CODE_FOR_ptr_extend; | |
6dd12198 | 4843 | #endif |
85363ca0 ZW |
4844 | |
4845 | tab = unsignedp ? zext_optab : sext_optab; | |
166cdb08 | 4846 | return convert_optab_handler (tab, to_mode, from_mode)->insn_code; |
77c9c6c2 RK |
4847 | } |
4848 | ||
4849 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4850 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4851 | ||
4852 | rtx | |
0c20a65f AJ |
4853 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4854 | enum machine_mode mfrom, int unsignedp) | |
77c9c6c2 | 4855 | { |
85363ca0 ZW |
4856 | enum insn_code icode = can_extend_p (mto, mfrom, unsignedp); |
4857 | return GEN_FCN (icode) (x, y); | |
77c9c6c2 | 4858 | } |
77c9c6c2 RK |
4859 | \f |
4860 | /* can_fix_p and can_float_p say whether the target machine | |
4861 | can directly convert a given fixed point type to | |
4862 | a given floating point type, or vice versa. | |
4863 | The returned value is the CODE_FOR_... value to use, | |
5d81dc5b | 4864 | or CODE_FOR_nothing if these modes cannot be directly converted. |
77c9c6c2 | 4865 | |
5d81dc5b | 4866 | *TRUNCP_PTR is set to 1 if it is necessary to output |
77c9c6c2 RK |
4867 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4868 | ||
4869 | static enum insn_code | |
0c20a65f AJ |
4870 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4871 | int unsignedp, int *truncp_ptr) | |
77c9c6c2 | 4872 | { |
85363ca0 ZW |
4873 | convert_optab tab; |
4874 | enum insn_code icode; | |
4875 | ||
4876 | tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab; | |
166cdb08 | 4877 | icode = convert_optab_handler (tab, fixmode, fltmode)->insn_code; |
85363ca0 ZW |
4878 | if (icode != CODE_FOR_nothing) |
4879 | { | |
4880 | *truncp_ptr = 0; | |
4881 | return icode; | |
4882 | } | |
77c9c6c2 | 4883 | |
0e1d7f32 AH |
4884 | /* FIXME: This requires a port to define both FIX and FTRUNC pattern |
4885 | for this to work. We need to rework the fix* and ftrunc* patterns | |
4886 | and documentation. */ | |
85363ca0 | 4887 | tab = unsignedp ? ufix_optab : sfix_optab; |
166cdb08 | 4888 | icode = convert_optab_handler (tab, fixmode, fltmode)->insn_code; |
85363ca0 | 4889 | if (icode != CODE_FOR_nothing |
166cdb08 | 4890 | && optab_handler (ftrunc_optab, fltmode)->insn_code != CODE_FOR_nothing) |
77c9c6c2 RK |
4891 | { |
4892 | *truncp_ptr = 1; | |
85363ca0 | 4893 | return icode; |
77c9c6c2 | 4894 | } |
85363ca0 ZW |
4895 | |
4896 | *truncp_ptr = 0; | |
77c9c6c2 RK |
4897 | return CODE_FOR_nothing; |
4898 | } | |
4899 | ||
4900 | static enum insn_code | |
0c20a65f AJ |
4901 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4902 | int unsignedp) | |
77c9c6c2 | 4903 | { |
85363ca0 ZW |
4904 | convert_optab tab; |
4905 | ||
4906 | tab = unsignedp ? ufloat_optab : sfloat_optab; | |
166cdb08 | 4907 | return convert_optab_handler (tab, fltmode, fixmode)->insn_code; |
77c9c6c2 | 4908 | } |
77c9c6c2 RK |
4909 | \f |
4910 | /* Generate code to convert FROM to floating point | |
34e56753 | 4911 | and store in TO. FROM must be fixed point and not VOIDmode. |
77c9c6c2 RK |
4912 | UNSIGNEDP nonzero means regard FROM as unsigned. |
4913 | Normally this is done by correcting the final value | |
4914 | if it is negative. */ | |
4915 | ||
4916 | void | |
0c20a65f | 4917 | expand_float (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4918 | { |
4919 | enum insn_code icode; | |
b3694847 | 4920 | rtx target = to; |
77c9c6c2 | 4921 | enum machine_mode fmode, imode; |
d7735880 | 4922 | bool can_do_signed = false; |
77c9c6c2 | 4923 | |
34e56753 | 4924 | /* Crash now, because we won't be able to decide which mode to use. */ |
e3feb571 | 4925 | gcc_assert (GET_MODE (from) != VOIDmode); |
34e56753 | 4926 | |
77c9c6c2 RK |
4927 | /* Look for an insn to do the conversion. Do it in the specified |
4928 | modes if possible; otherwise convert either input, output or both to | |
4929 | wider mode. If the integer mode is wider than the mode of FROM, | |
4930 | we can do the conversion signed even if the input is unsigned. */ | |
4931 | ||
7bf0a593 AP |
4932 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4933 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4934 | for (imode = GET_MODE (from); imode != VOIDmode; | |
4935 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4936 | { |
4937 | int doing_unsigned = unsignedp; | |
4938 | ||
5ba02ca6 GK |
4939 | if (fmode != GET_MODE (to) |
4940 | && significand_size (fmode) < GET_MODE_BITSIZE (GET_MODE (from))) | |
4941 | continue; | |
4942 | ||
77c9c6c2 | 4943 | icode = can_float_p (fmode, imode, unsignedp); |
d7735880 JM |
4944 | if (icode == CODE_FOR_nothing && unsignedp) |
4945 | { | |
4946 | enum insn_code scode = can_float_p (fmode, imode, 0); | |
4947 | if (scode != CODE_FOR_nothing) | |
4948 | can_do_signed = true; | |
4949 | if (imode != GET_MODE (from)) | |
4950 | icode = scode, doing_unsigned = 0; | |
4951 | } | |
77c9c6c2 RK |
4952 | |
4953 | if (icode != CODE_FOR_nothing) | |
4954 | { | |
77c9c6c2 RK |
4955 | if (imode != GET_MODE (from)) |
4956 | from = convert_to_mode (imode, from, unsignedp); | |
77c9c6c2 RK |
4957 | |
4958 | if (fmode != GET_MODE (to)) | |
4959 | target = gen_reg_rtx (fmode); | |
4960 | ||
4961 | emit_unop_insn (icode, target, from, | |
4962 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
4963 | ||
4964 | if (target != to) | |
4965 | convert_move (to, target, 0); | |
4966 | return; | |
4967 | } | |
7e1a450d | 4968 | } |
77c9c6c2 | 4969 | |
6ef9a246 | 4970 | /* Unsigned integer, and no way to convert directly. Convert as signed, |
cc8d36a1 UB |
4971 | then unconditionally adjust the result. */ |
4972 | if (unsignedp && can_do_signed) | |
77c9c6c2 RK |
4973 | { |
4974 | rtx label = gen_label_rtx (); | |
4975 | rtx temp; | |
4976 | REAL_VALUE_TYPE offset; | |
4977 | ||
c95c47f3 PE |
4978 | /* Look for a usable floating mode FMODE wider than the source and at |
4979 | least as wide as the target. Using FMODE will avoid rounding woes | |
4980 | with unsigned values greater than the signed maximum value. */ | |
70864443 | 4981 | |
c95c47f3 PE |
4982 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4983 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4984 | if (GET_MODE_BITSIZE (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) | |
4985 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) | |
4986 | break; | |
a48fb61b | 4987 | |
c95c47f3 PE |
4988 | if (fmode == VOIDmode) |
4989 | { | |
a48fb61b | 4990 | /* There is no such mode. Pretend the target is wide enough. */ |
c95c47f3 | 4991 | fmode = GET_MODE (to); |
a48fb61b | 4992 | |
0f41302f | 4993 | /* Avoid double-rounding when TO is narrower than FROM. */ |
a48fb61b RK |
4994 | if ((significand_size (fmode) + 1) |
4995 | < GET_MODE_BITSIZE (GET_MODE (from))) | |
4996 | { | |
4997 | rtx temp1; | |
4998 | rtx neglabel = gen_label_rtx (); | |
4999 | ||
0c20a65f | 5000 | /* Don't use TARGET if it isn't a register, is a hard register, |
70864443 | 5001 | or is the wrong mode. */ |
f8cfc6aa | 5002 | if (!REG_P (target) |
70864443 RK |
5003 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
5004 | || GET_MODE (target) != fmode) | |
44f51d4a RK |
5005 | target = gen_reg_rtx (fmode); |
5006 | ||
a48fb61b RK |
5007 | imode = GET_MODE (from); |
5008 | do_pending_stack_adjust (); | |
5009 | ||
5010 | /* Test whether the sign bit is set. */ | |
1c0290ea | 5011 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
a06ef755 | 5012 | 0, neglabel); |
a48fb61b RK |
5013 | |
5014 | /* The sign bit is not set. Convert as signed. */ | |
5015 | expand_float (target, from, 0); | |
5016 | emit_jump_insn (gen_jump (label)); | |
2ad79487 | 5017 | emit_barrier (); |
a48fb61b RK |
5018 | |
5019 | /* The sign bit is set. | |
5020 | Convert to a usable (positive signed) value by shifting right | |
5021 | one bit, while remembering if a nonzero bit was shifted | |
5022 | out; i.e., compute (from & 1) | (from >> 1). */ | |
5023 | ||
5024 | emit_label (neglabel); | |
5025 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
70864443 | 5026 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
73d9a835 RK |
5027 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, integer_one_node, |
5028 | NULL_RTX, 1); | |
0c20a65f | 5029 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
70864443 | 5030 | OPTAB_LIB_WIDEN); |
a48fb61b RK |
5031 | expand_float (target, temp, 0); |
5032 | ||
5033 | /* Multiply by 2 to undo the shift above. */ | |
a93738eb | 5034 | temp = expand_binop (fmode, add_optab, target, target, |
7e1a450d | 5035 | target, 0, OPTAB_LIB_WIDEN); |
a93738eb RK |
5036 | if (temp != target) |
5037 | emit_move_insn (target, temp); | |
5038 | ||
a48fb61b RK |
5039 | do_pending_stack_adjust (); |
5040 | emit_label (label); | |
5041 | goto done; | |
5042 | } | |
c95c47f3 PE |
5043 | } |
5044 | ||
77c9c6c2 RK |
5045 | /* If we are about to do some arithmetic to correct for an |
5046 | unsigned operand, do it in a pseudo-register. */ | |
5047 | ||
c95c47f3 | 5048 | if (GET_MODE (to) != fmode |
f8cfc6aa | 5049 | || !REG_P (to) || REGNO (to) < FIRST_PSEUDO_REGISTER) |
c95c47f3 | 5050 | target = gen_reg_rtx (fmode); |
77c9c6c2 RK |
5051 | |
5052 | /* Convert as signed integer to floating. */ | |
5053 | expand_float (target, from, 0); | |
5054 | ||
5055 | /* If FROM is negative (and therefore TO is negative), | |
5056 | correct its value by 2**bitwidth. */ | |
5057 | ||
5058 | do_pending_stack_adjust (); | |
c5d5d461 | 5059 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 5060 | 0, label); |
70864443 | 5061 | |
0c20a65f | 5062 | |
6ef9a246 | 5063 | real_2expN (&offset, GET_MODE_BITSIZE (GET_MODE (from)), fmode); |
c95c47f3 | 5064 | temp = expand_binop (fmode, add_optab, target, |
30d88916 | 5065 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
77c9c6c2 RK |
5066 | target, 0, OPTAB_LIB_WIDEN); |
5067 | if (temp != target) | |
5068 | emit_move_insn (target, temp); | |
a48fb61b | 5069 | |
77c9c6c2 RK |
5070 | do_pending_stack_adjust (); |
5071 | emit_label (label); | |
70864443 | 5072 | goto done; |
77c9c6c2 | 5073 | } |
77c9c6c2 | 5074 | |
85363ca0 | 5075 | /* No hardware instruction available; call a library routine. */ |
77c9c6c2 | 5076 | { |
85363ca0 | 5077 | rtx libfunc; |
77c9c6c2 | 5078 | rtx insns; |
9a7f678c | 5079 | rtx value; |
85363ca0 | 5080 | convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab; |
77c9c6c2 | 5081 | |
77c9c6c2 RK |
5082 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) |
5083 | from = convert_to_mode (SImode, from, unsignedp); | |
77c9c6c2 | 5084 | |
8a33f100 | 5085 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 5086 | gcc_assert (libfunc); |
77c9c6c2 RK |
5087 | |
5088 | start_sequence (); | |
5089 | ||
85363ca0 | 5090 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
5091 | GET_MODE (to), 1, from, |
5092 | GET_MODE (from)); | |
77c9c6c2 RK |
5093 | insns = get_insns (); |
5094 | end_sequence (); | |
5095 | ||
9a7f678c | 5096 | emit_libcall_block (insns, target, value, |
d1163987 BW |
5097 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FLOAT : FLOAT, |
5098 | GET_MODE (to), from)); | |
77c9c6c2 RK |
5099 | } |
5100 | ||
a48fb61b RK |
5101 | done: |
5102 | ||
77c9c6c2 RK |
5103 | /* Copy result to requested destination |
5104 | if we have been computing in a temp location. */ | |
5105 | ||
5106 | if (target != to) | |
5107 | { | |
5108 | if (GET_MODE (target) == GET_MODE (to)) | |
5109 | emit_move_insn (to, target); | |
5110 | else | |
5111 | convert_move (to, target, 0); | |
5112 | } | |
5113 | } | |
5114 | \f | |
0e1d7f32 AH |
5115 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5116 | must be floating point. */ | |
77c9c6c2 RK |
5117 | |
5118 | void | |
0c20a65f | 5119 | expand_fix (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
5120 | { |
5121 | enum insn_code icode; | |
b3694847 | 5122 | rtx target = to; |
77c9c6c2 RK |
5123 | enum machine_mode fmode, imode; |
5124 | int must_trunc = 0; | |
77c9c6c2 RK |
5125 | |
5126 | /* We first try to find a pair of modes, one real and one integer, at | |
5127 | least as wide as FROM and TO, respectively, in which we can open-code | |
5128 | this conversion. If the integer mode is wider than the mode of TO, | |
5129 | we can do the conversion either signed or unsigned. */ | |
5130 | ||
3987b9db JH |
5131 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5132 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5133 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5134 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
5135 | { |
5136 | int doing_unsigned = unsignedp; | |
5137 | ||
5138 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
5139 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
5140 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
5141 | ||
5142 | if (icode != CODE_FOR_nothing) | |
5143 | { | |
77c9c6c2 RK |
5144 | if (fmode != GET_MODE (from)) |
5145 | from = convert_to_mode (fmode, from, 0); | |
77c9c6c2 RK |
5146 | |
5147 | if (must_trunc) | |
0e1d7f32 AH |
5148 | { |
5149 | rtx temp = gen_reg_rtx (GET_MODE (from)); | |
5150 | from = expand_unop (GET_MODE (from), ftrunc_optab, from, | |
5151 | temp, 0); | |
5152 | } | |
77c9c6c2 RK |
5153 | |
5154 | if (imode != GET_MODE (to)) | |
5155 | target = gen_reg_rtx (imode); | |
5156 | ||
5157 | emit_unop_insn (icode, target, from, | |
5158 | doing_unsigned ? UNSIGNED_FIX : FIX); | |
5159 | if (target != to) | |
5160 | convert_move (to, target, unsignedp); | |
5161 | return; | |
5162 | } | |
5163 | } | |
5164 | ||
77c9c6c2 RK |
5165 | /* For an unsigned conversion, there is one more way to do it. |
5166 | If we have a signed conversion, we generate code that compares | |
5167 | the real value to the largest representable positive number. If if | |
5168 | is smaller, the conversion is done normally. Otherwise, subtract | |
5169 | one plus the highest signed number, convert, and add it back. | |
5170 | ||
5171 | We only need to check all real modes, since we know we didn't find | |
0c20a65f | 5172 | anything with a wider integer mode. |
0d446150 JH |
5173 | |
5174 | This code used to extend FP value into mode wider than the destination. | |
6ef9a246 JJ |
5175 | This is needed for decimal float modes which cannot accurately |
5176 | represent one plus the highest signed number of the same size, but | |
5177 | not for binary modes. Consider, for instance conversion from SFmode | |
0d446150 JH |
5178 | into DImode. |
5179 | ||
6fc0bb99 | 5180 | The hot path through the code is dealing with inputs smaller than 2^63 |
0d446150 JH |
5181 | and doing just the conversion, so there is no bits to lose. |
5182 | ||
5183 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
6ef9a246 | 5184 | inclusive. (as for other input overflow happens and result is undefined) |
e0bb17a8 | 5185 | So we know that the most important bit set in mantissa corresponds to |
0d446150 JH |
5186 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
5187 | simply clears out that bit. The rest is trivial. */ | |
77c9c6c2 | 5188 | |
b1ec3c92 | 5189 | if (unsignedp && GET_MODE_BITSIZE (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
77c9c6c2 RK |
5190 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5191 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
6ef9a246 JJ |
5192 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, &must_trunc) |
5193 | && (!DECIMAL_FLOAT_MODE_P (fmode) | |
5194 | || GET_MODE_BITSIZE (fmode) > GET_MODE_BITSIZE (GET_MODE (to)))) | |
77c9c6c2 | 5195 | { |
e9f7ae44 RS |
5196 | int bitsize; |
5197 | REAL_VALUE_TYPE offset; | |
5198 | rtx limit, lab1, lab2, insn; | |
5199 | ||
5200 | bitsize = GET_MODE_BITSIZE (GET_MODE (to)); | |
6ef9a246 | 5201 | real_2expN (&offset, bitsize - 1, fmode); |
30d88916 | 5202 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
e9f7ae44 RS |
5203 | lab1 = gen_label_rtx (); |
5204 | lab2 = gen_label_rtx (); | |
77c9c6c2 | 5205 | |
77c9c6c2 RK |
5206 | if (fmode != GET_MODE (from)) |
5207 | from = convert_to_mode (fmode, from, 0); | |
5208 | ||
5209 | /* See if we need to do the subtraction. */ | |
5210 | do_pending_stack_adjust (); | |
c5d5d461 | 5211 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 5212 | 0, lab1); |
77c9c6c2 RK |
5213 | |
5214 | /* If not, do the signed "fix" and branch around fixup code. */ | |
5215 | expand_fix (to, from, 0); | |
5216 | emit_jump_insn (gen_jump (lab2)); | |
5217 | emit_barrier (); | |
5218 | ||
5219 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
5220 | then add 2**(N-1). Do the addition using XOR since this | |
5221 | will often generate better code. */ | |
5222 | emit_label (lab1); | |
5223 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
b1ec3c92 | 5224 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
77c9c6c2 RK |
5225 | expand_fix (to, target, 0); |
5226 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2496c7bd LB |
5227 | gen_int_mode |
5228 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
5229 | GET_MODE (to)), | |
77c9c6c2 RK |
5230 | to, 1, OPTAB_LIB_WIDEN); |
5231 | ||
5232 | if (target != to) | |
5233 | emit_move_insn (to, target); | |
5234 | ||
5235 | emit_label (lab2); | |
5236 | ||
166cdb08 | 5237 | if (optab_handler (mov_optab, GET_MODE (to))->insn_code |
02214a5c RK |
5238 | != CODE_FOR_nothing) |
5239 | { | |
5240 | /* Make a place for a REG_NOTE and add it. */ | |
5241 | insn = emit_move_insn (to, to); | |
5fa671cf AM |
5242 | set_unique_reg_note (insn, |
5243 | REG_EQUAL, | |
5244 | gen_rtx_fmt_e (UNSIGNED_FIX, | |
5245 | GET_MODE (to), | |
5246 | copy_rtx (from))); | |
02214a5c | 5247 | } |
c5c76735 | 5248 | |
77c9c6c2 RK |
5249 | return; |
5250 | } | |
77c9c6c2 RK |
5251 | |
5252 | /* We can't do it with an insn, so use a library call. But first ensure | |
5253 | that the mode of TO is at least as wide as SImode, since those are the | |
5254 | only library calls we know about. */ | |
5255 | ||
5256 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
5257 | { | |
5258 | target = gen_reg_rtx (SImode); | |
5259 | ||
5260 | expand_fix (target, from, unsignedp); | |
5261 | } | |
77c9c6c2 | 5262 | else |
77c9c6c2 RK |
5263 | { |
5264 | rtx insns; | |
560f3f8a | 5265 | rtx value; |
85363ca0 | 5266 | rtx libfunc; |
5906d013 | 5267 | |
85363ca0 | 5268 | convert_optab tab = unsignedp ? ufix_optab : sfix_optab; |
8a33f100 | 5269 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 5270 | gcc_assert (libfunc); |
77c9c6c2 | 5271 | |
77c9c6c2 RK |
5272 | start_sequence (); |
5273 | ||
85363ca0 | 5274 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
5275 | GET_MODE (to), 1, from, |
5276 | GET_MODE (from)); | |
77c9c6c2 RK |
5277 | insns = get_insns (); |
5278 | end_sequence (); | |
5279 | ||
560f3f8a | 5280 | emit_libcall_block (insns, target, value, |
9e6a5703 JC |
5281 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
5282 | GET_MODE (to), from)); | |
77c9c6c2 | 5283 | } |
0c20a65f | 5284 | |
3e53ea48 RK |
5285 | if (target != to) |
5286 | { | |
5287 | if (GET_MODE (to) == GET_MODE (target)) | |
5288 | emit_move_insn (to, target); | |
5289 | else | |
5290 | convert_move (to, target, 0); | |
5291 | } | |
77c9c6c2 | 5292 | } |
bb7f0423 | 5293 | |
0f996086 CF |
5294 | /* Generate code to convert FROM or TO a fixed-point. |
5295 | If UINTP is true, either TO or FROM is an unsigned integer. | |
5296 | If SATP is true, we need to saturate the result. */ | |
5297 | ||
5298 | void | |
5299 | expand_fixed_convert (rtx to, rtx from, int uintp, int satp) | |
5300 | { | |
5301 | enum machine_mode to_mode = GET_MODE (to); | |
5302 | enum machine_mode from_mode = GET_MODE (from); | |
5303 | convert_optab tab; | |
5304 | enum rtx_code this_code; | |
5305 | enum insn_code code; | |
5306 | rtx insns, value; | |
5307 | rtx libfunc; | |
5308 | ||
5309 | if (to_mode == from_mode) | |
5310 | { | |
5311 | emit_move_insn (to, from); | |
5312 | return; | |
5313 | } | |
5314 | ||
5315 | if (uintp) | |
5316 | { | |
5317 | tab = satp ? satfractuns_optab : fractuns_optab; | |
5318 | this_code = satp ? UNSIGNED_SAT_FRACT : UNSIGNED_FRACT_CONVERT; | |
5319 | } | |
5320 | else | |
5321 | { | |
5322 | tab = satp ? satfract_optab : fract_optab; | |
5323 | this_code = satp ? SAT_FRACT : FRACT_CONVERT; | |
5324 | } | |
5325 | code = tab->handlers[to_mode][from_mode].insn_code; | |
5326 | if (code != CODE_FOR_nothing) | |
5327 | { | |
5328 | emit_unop_insn (code, to, from, this_code); | |
5329 | return; | |
5330 | } | |
5331 | ||
5332 | libfunc = convert_optab_libfunc (tab, to_mode, from_mode); | |
5333 | gcc_assert (libfunc); | |
5334 | ||
5335 | start_sequence (); | |
5336 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, to_mode, | |
5337 | 1, from, from_mode); | |
5338 | insns = get_insns (); | |
5339 | end_sequence (); | |
5340 | ||
5341 | emit_libcall_block (insns, to, value, | |
5342 | gen_rtx_fmt_e (tab->code, to_mode, from)); | |
5343 | } | |
5344 | ||
bb7f0423 RG |
5345 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5346 | must be floating point, TO must be signed. Use the conversion optab | |
5347 | TAB to do the conversion. */ | |
5348 | ||
5349 | bool | |
5350 | expand_sfix_optab (rtx to, rtx from, convert_optab tab) | |
5351 | { | |
5352 | enum insn_code icode; | |
5353 | rtx target = to; | |
5354 | enum machine_mode fmode, imode; | |
5355 | ||
5356 | /* We first try to find a pair of modes, one real and one integer, at | |
5357 | least as wide as FROM and TO, respectively, in which we can open-code | |
5358 | this conversion. If the integer mode is wider than the mode of TO, | |
5359 | we can do the conversion either signed or unsigned. */ | |
5360 | ||
5361 | for (fmode = GET_MODE (from); fmode != VOIDmode; | |
5362 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5363 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5364 | imode = GET_MODE_WIDER_MODE (imode)) | |
5365 | { | |
166cdb08 | 5366 | icode = convert_optab_handler (tab, imode, fmode)->insn_code; |
bb7f0423 RG |
5367 | if (icode != CODE_FOR_nothing) |
5368 | { | |
5369 | if (fmode != GET_MODE (from)) | |
5370 | from = convert_to_mode (fmode, from, 0); | |
5371 | ||
5372 | if (imode != GET_MODE (to)) | |
5373 | target = gen_reg_rtx (imode); | |
5374 | ||
5375 | emit_unop_insn (icode, target, from, UNKNOWN); | |
5376 | if (target != to) | |
5377 | convert_move (to, target, 0); | |
5378 | return true; | |
5379 | } | |
5380 | } | |
5381 | ||
5382 | return false; | |
5383 | } | |
77c9c6c2 | 5384 | \f |
ef89d648 ZW |
5385 | /* Report whether we have an instruction to perform the operation |
5386 | specified by CODE on operands of mode MODE. */ | |
5387 | int | |
0c20a65f | 5388 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ef89d648 ZW |
5389 | { |
5390 | return (code_to_optab[(int) code] != 0 | |
166cdb08 | 5391 | && (optab_handler (code_to_optab[(int) code], mode)->insn_code |
ef89d648 ZW |
5392 | != CODE_FOR_nothing)); |
5393 | } | |
5394 | ||
c0742514 JJ |
5395 | /* Set all insn_code fields to CODE_FOR_nothing. */ |
5396 | ||
33727b5e | 5397 | static void |
c0742514 | 5398 | init_insn_codes (void) |
85363ca0 | 5399 | { |
c0742514 | 5400 | unsigned int i; |
8a33f100 | 5401 | |
c0742514 JJ |
5402 | for (i = 0; i < (unsigned int) OTI_MAX; i++) |
5403 | { | |
5404 | unsigned int j; | |
5405 | optab op; | |
5406 | ||
5407 | op = &optab_table[i]; | |
5408 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
5409 | optab_handler (op, j)->insn_code = CODE_FOR_nothing; | |
5410 | } | |
5411 | for (i = 0; i < (unsigned int) COI_MAX; i++) | |
5412 | { | |
5413 | unsigned int j, k; | |
5414 | convert_optab op; | |
5415 | ||
5416 | op = &convert_optab_table[i]; | |
5417 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
5418 | for (k = 0; k < NUM_MACHINE_MODES; k++) | |
5419 | convert_optab_handler (op, j, k)->insn_code = CODE_FOR_nothing; | |
5420 | } | |
85363ca0 ZW |
5421 | } |
5422 | ||
c0742514 | 5423 | /* Initialize OP's code to CODE, and write it into the code_to_optab table. */ |
33727b5e JJ |
5424 | static inline void |
5425 | init_optab (optab op, enum rtx_code code) | |
ef89d648 | 5426 | { |
ef89d648 ZW |
5427 | op->code = code; |
5428 | code_to_optab[(int) code] = op; | |
ef89d648 ZW |
5429 | } |
5430 | ||
5431 | /* Same, but fill in its code as CODE, and do _not_ write it into | |
5432 | the code_to_optab table. */ | |
33727b5e JJ |
5433 | static inline void |
5434 | init_optabv (optab op, enum rtx_code code) | |
ef89d648 | 5435 | { |
ef89d648 | 5436 | op->code = code; |
77c9c6c2 RK |
5437 | } |
5438 | ||
85363ca0 | 5439 | /* Conversion optabs never go in the code_to_optab table. */ |
33727b5e JJ |
5440 | static void |
5441 | init_convert_optab (convert_optab op, enum rtx_code code) | |
85363ca0 | 5442 | { |
85363ca0 | 5443 | op->code = code; |
85363ca0 ZW |
5444 | } |
5445 | ||
b092b471 JW |
5446 | /* Initialize the libfunc fields of an entire group of entries in some |
5447 | optab. Each entry is set equal to a string consisting of a leading | |
5448 | pair of underscores followed by a generic operation name followed by | |
7ef0daad | 5449 | a mode name (downshifted to lowercase) followed by a single character |
b092b471 JW |
5450 | representing the number of operands for the given operation (which is |
5451 | usually one of the characters '2', '3', or '4'). | |
5452 | ||
5453 | OPTABLE is the table in which libfunc fields are to be initialized. | |
b092b471 JW |
5454 | OPNAME is the generic (string) name of the operation. |
5455 | SUFFIX is the character which specifies the number of operands for | |
5456 | the given generic operation. | |
8a33f100 | 5457 | MODE is the mode to generate for. |
b092b471 JW |
5458 | */ |
5459 | ||
5460 | static void | |
8a33f100 | 5461 | gen_libfunc (optab optable, const char *opname, int suffix, enum machine_mode mode) |
b092b471 | 5462 | { |
b3694847 | 5463 | unsigned opname_len = strlen (opname); |
8a33f100 JH |
5464 | const char *mname = GET_MODE_NAME (mode); |
5465 | unsigned mname_len = strlen (mname); | |
d3bfe4de | 5466 | char *libfunc_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
8a33f100 JH |
5467 | char *p; |
5468 | const char *q; | |
b092b471 | 5469 | |
8a33f100 JH |
5470 | p = libfunc_name; |
5471 | *p++ = '_'; | |
5472 | *p++ = '_'; | |
5473 | for (q = opname; *q; ) | |
5474 | *p++ = *q++; | |
5475 | for (q = mname; *q; q++) | |
5476 | *p++ = TOLOWER (*q); | |
5477 | *p++ = suffix; | |
5478 | *p = '\0'; | |
5479 | ||
5480 | set_optab_libfunc (optable, mode, | |
5481 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
b092b471 JW |
5482 | } |
5483 | ||
8a33f100 | 5484 | /* Like gen_libfunc, but verify that integer operation is involved. */ |
b092b471 JW |
5485 | |
5486 | static void | |
8a33f100 JH |
5487 | gen_int_libfunc (optab optable, const char *opname, char suffix, |
5488 | enum machine_mode mode) | |
b092b471 | 5489 | { |
8a33f100 JH |
5490 | int maxsize = 2 * BITS_PER_WORD; |
5491 | ||
5492 | if (GET_MODE_CLASS (mode) != MODE_INT) | |
5493 | return; | |
c0510d84 DD |
5494 | if (maxsize < LONG_LONG_TYPE_SIZE) |
5495 | maxsize = LONG_LONG_TYPE_SIZE; | |
8a33f100 JH |
5496 | if (GET_MODE_CLASS (mode) != MODE_INT |
5497 | || mode < word_mode || GET_MODE_BITSIZE (mode) > maxsize) | |
5498 | return; | |
5499 | gen_libfunc (optable, opname, suffix, mode); | |
b092b471 JW |
5500 | } |
5501 | ||
8a33f100 | 5502 | /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */ |
b092b471 JW |
5503 | |
5504 | static void | |
8a33f100 JH |
5505 | gen_fp_libfunc (optab optable, const char *opname, char suffix, |
5506 | enum machine_mode mode) | |
b092b471 | 5507 | { |
8a33f100 | 5508 | char *dec_opname; |
79b87c74 | 5509 | |
8a33f100 JH |
5510 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
5511 | gen_libfunc (optable, opname, suffix, mode); | |
5512 | if (DECIMAL_FLOAT_MODE_P (mode)) | |
5513 | { | |
d3bfe4de | 5514 | dec_opname = XALLOCAVEC (char, sizeof (DECIMAL_PREFIX) + strlen (opname)); |
8a33f100 JH |
5515 | /* For BID support, change the name to have either a bid_ or dpd_ prefix |
5516 | depending on the low level floating format used. */ | |
5517 | memcpy (dec_opname, DECIMAL_PREFIX, sizeof (DECIMAL_PREFIX) - 1); | |
5518 | strcpy (dec_opname + sizeof (DECIMAL_PREFIX) - 1, opname); | |
5519 | gen_libfunc (optable, dec_opname, suffix, mode); | |
5520 | } | |
5521 | } | |
79b87c74 | 5522 | |
0f996086 CF |
5523 | /* Like gen_libfunc, but verify that fixed-point operation is involved. */ |
5524 | ||
5525 | static void | |
5526 | gen_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5527 | enum machine_mode mode) | |
5528 | { | |
5529 | if (!ALL_FIXED_POINT_MODE_P (mode)) | |
5530 | return; | |
5531 | gen_libfunc (optable, opname, suffix, mode); | |
5532 | } | |
5533 | ||
5534 | /* Like gen_libfunc, but verify that signed fixed-point operation is | |
5535 | involved. */ | |
5536 | ||
5537 | static void | |
5538 | gen_signed_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5539 | enum machine_mode mode) | |
5540 | { | |
5541 | if (!SIGNED_FIXED_POINT_MODE_P (mode)) | |
5542 | return; | |
5543 | gen_libfunc (optable, opname, suffix, mode); | |
5544 | } | |
5545 | ||
5546 | /* Like gen_libfunc, but verify that unsigned fixed-point operation is | |
5547 | involved. */ | |
5548 | ||
5549 | static void | |
5550 | gen_unsigned_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5551 | enum machine_mode mode) | |
5552 | { | |
5553 | if (!UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5554 | return; | |
5555 | gen_libfunc (optable, opname, suffix, mode); | |
5556 | } | |
5557 | ||
8a33f100 JH |
5558 | /* Like gen_libfunc, but verify that FP or INT operation is involved. */ |
5559 | ||
5560 | static void | |
5561 | gen_int_fp_libfunc (optab optable, const char *name, char suffix, | |
5562 | enum machine_mode mode) | |
5563 | { | |
5564 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5565 | gen_fp_libfunc (optable, name, suffix, mode); | |
5566 | if (INTEGRAL_MODE_P (mode)) | |
5567 | gen_int_libfunc (optable, name, suffix, mode); | |
5568 | } | |
5569 | ||
5570 | /* Like gen_libfunc, but verify that FP or INT operation is involved | |
5571 | and add 'v' suffix for integer operation. */ | |
5572 | ||
5573 | static void | |
5574 | gen_intv_fp_libfunc (optab optable, const char *name, char suffix, | |
5575 | enum machine_mode mode) | |
5576 | { | |
5577 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5578 | gen_fp_libfunc (optable, name, suffix, mode); | |
5579 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
5580 | { | |
5581 | int len = strlen (name); | |
d3bfe4de | 5582 | char *v_name = XALLOCAVEC (char, len + 2); |
8a33f100 JH |
5583 | strcpy (v_name, name); |
5584 | v_name[len] = 'v'; | |
5585 | v_name[len + 1] = 0; | |
5586 | gen_int_libfunc (optable, v_name, suffix, mode); | |
5587 | } | |
b092b471 JW |
5588 | } |
5589 | ||
0f996086 CF |
5590 | /* Like gen_libfunc, but verify that FP or INT or FIXED operation is |
5591 | involved. */ | |
5592 | ||
5593 | static void | |
5594 | gen_int_fp_fixed_libfunc (optab optable, const char *name, char suffix, | |
5595 | enum machine_mode mode) | |
5596 | { | |
5597 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5598 | gen_fp_libfunc (optable, name, suffix, mode); | |
5599 | if (INTEGRAL_MODE_P (mode)) | |
5600 | gen_int_libfunc (optable, name, suffix, mode); | |
5601 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5602 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5603 | } | |
5604 | ||
5605 | /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is | |
5606 | involved. */ | |
5607 | ||
5608 | static void | |
5609 | gen_int_fp_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5610 | enum machine_mode mode) | |
5611 | { | |
5612 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5613 | gen_fp_libfunc (optable, name, suffix, mode); | |
5614 | if (INTEGRAL_MODE_P (mode)) | |
5615 | gen_int_libfunc (optable, name, suffix, mode); | |
5616 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5617 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5618 | } | |
5619 | ||
5620 | /* Like gen_libfunc, but verify that INT or FIXED operation is | |
5621 | involved. */ | |
5622 | ||
5623 | static void | |
5624 | gen_int_fixed_libfunc (optab optable, const char *name, char suffix, | |
5625 | enum machine_mode mode) | |
5626 | { | |
5627 | if (INTEGRAL_MODE_P (mode)) | |
5628 | gen_int_libfunc (optable, name, suffix, mode); | |
5629 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5630 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5631 | } | |
5632 | ||
5633 | /* Like gen_libfunc, but verify that INT or signed FIXED operation is | |
5634 | involved. */ | |
5635 | ||
5636 | static void | |
5637 | gen_int_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5638 | enum machine_mode mode) | |
5639 | { | |
5640 | if (INTEGRAL_MODE_P (mode)) | |
5641 | gen_int_libfunc (optable, name, suffix, mode); | |
5642 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5643 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5644 | } | |
5645 | ||
5646 | /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is | |
5647 | involved. */ | |
5648 | ||
5649 | static void | |
5650 | gen_int_unsigned_fixed_libfunc (optab optable, const char *name, char suffix, | |
5651 | enum machine_mode mode) | |
5652 | { | |
5653 | if (INTEGRAL_MODE_P (mode)) | |
5654 | gen_int_libfunc (optable, name, suffix, mode); | |
5655 | if (UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5656 | gen_unsigned_fixed_libfunc (optable, name, suffix, mode); | |
5657 | } | |
5658 | ||
85363ca0 ZW |
5659 | /* Initialize the libfunc fields of an entire group of entries of an |
5660 | inter-mode-class conversion optab. The string formation rules are | |
5661 | similar to the ones for init_libfuncs, above, but instead of having | |
5662 | a mode name and an operand count these functions have two mode names | |
5663 | and no operand count. */ | |
8a33f100 | 5664 | |
85363ca0 | 5665 | static void |
8a33f100 JH |
5666 | gen_interclass_conv_libfunc (convert_optab tab, |
5667 | const char *opname, | |
5668 | enum machine_mode tmode, | |
5669 | enum machine_mode fmode) | |
85363ca0 | 5670 | { |
85363ca0 | 5671 | size_t opname_len = strlen (opname); |
8a33f100 | 5672 | size_t mname_len = 0; |
85363ca0 | 5673 | |
85363ca0 ZW |
5674 | const char *fname, *tname; |
5675 | const char *q; | |
5676 | char *libfunc_name, *suffix; | |
79b87c74 | 5677 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5678 | char *p; |
5679 | ||
79b87c74 MM |
5680 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5681 | depends on which underlying decimal floating point format is used. */ | |
5682 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5683 | ||
8a33f100 | 5684 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5685 | |
d3bfe4de | 5686 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5687 | nondec_name[0] = '_'; |
5688 | nondec_name[1] = '_'; | |
5689 | memcpy (&nondec_name[2], opname, opname_len); | |
5690 | nondec_suffix = nondec_name + opname_len + 2; | |
5691 | ||
d3bfe4de | 5692 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5693 | dec_name[0] = '_'; |
5694 | dec_name[1] = '_'; | |
5695 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5696 | memcpy (&dec_name[2+dec_len], opname, opname_len); | |
5697 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5698 | |
8a33f100 JH |
5699 | fname = GET_MODE_NAME (fmode); |
5700 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5701 | |
8a33f100 JH |
5702 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5703 | { | |
5704 | libfunc_name = dec_name; | |
5705 | suffix = dec_suffix; | |
5706 | } | |
5707 | else | |
5708 | { | |
5709 | libfunc_name = nondec_name; | |
5710 | suffix = nondec_suffix; | |
5711 | } | |
79b87c74 | 5712 | |
8a33f100 JH |
5713 | p = suffix; |
5714 | for (q = fname; *q; p++, q++) | |
5715 | *p = TOLOWER (*q); | |
5716 | for (q = tname; *q; p++, q++) | |
5717 | *p = TOLOWER (*q); | |
85363ca0 | 5718 | |
8a33f100 | 5719 | *p = '\0'; |
85363ca0 | 5720 | |
8a33f100 JH |
5721 | set_conv_libfunc (tab, tmode, fmode, |
5722 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5723 | } |
5724 | ||
8a33f100 JH |
5725 | /* Same as gen_interclass_conv_libfunc but verify that we are producing |
5726 | int->fp conversion. */ | |
5727 | ||
85363ca0 | 5728 | static void |
8a33f100 JH |
5729 | gen_int_to_fp_conv_libfunc (convert_optab tab, |
5730 | const char *opname, | |
5731 | enum machine_mode tmode, | |
5732 | enum machine_mode fmode) | |
5733 | { | |
5734 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5735 | return; | |
5736 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5737 | return; | |
5738 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5739 | } | |
5740 | ||
5741 | /* ufloat_optab is special by using floatun for FP and floatuns decimal fp | |
5742 | naming scheme. */ | |
5743 | ||
5744 | static void | |
5745 | gen_ufloat_conv_libfunc (convert_optab tab, | |
5746 | const char *opname ATTRIBUTE_UNUSED, | |
5747 | enum machine_mode tmode, | |
5748 | enum machine_mode fmode) | |
5749 | { | |
5750 | if (DECIMAL_FLOAT_MODE_P (tmode)) | |
5751 | gen_int_to_fp_conv_libfunc (tab, "floatuns", tmode, fmode); | |
5752 | else | |
5753 | gen_int_to_fp_conv_libfunc (tab, "floatun", tmode, fmode); | |
5754 | } | |
5755 | ||
5756 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5757 | fp->int conversion. */ | |
5758 | ||
5759 | static void | |
5760 | gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab, | |
5761 | const char *opname, | |
5762 | enum machine_mode tmode, | |
5763 | enum machine_mode fmode) | |
5764 | { | |
5765 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5766 | return; | |
5767 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT) | |
5768 | return; | |
5769 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5770 | } | |
5771 | ||
5772 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5773 | fp->int conversion with no decimal floating point involved. */ | |
5774 | ||
5775 | static void | |
5776 | gen_fp_to_int_conv_libfunc (convert_optab tab, | |
5777 | const char *opname, | |
5778 | enum machine_mode tmode, | |
5779 | enum machine_mode fmode) | |
5780 | { | |
5781 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5782 | return; | |
5783 | if (GET_MODE_CLASS (tmode) != MODE_INT) | |
5784 | return; | |
5785 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5786 | } | |
5787 | ||
fa10beec | 5788 | /* Initialize the libfunc fields of an of an intra-mode-class conversion optab. |
8a33f100 JH |
5789 | The string formation rules are |
5790 | similar to the ones for init_libfunc, above. */ | |
5791 | ||
5792 | static void | |
5793 | gen_intraclass_conv_libfunc (convert_optab tab, const char *opname, | |
5794 | enum machine_mode tmode, enum machine_mode fmode) | |
85363ca0 | 5795 | { |
85363ca0 | 5796 | size_t opname_len = strlen (opname); |
8a33f100 | 5797 | size_t mname_len = 0; |
85363ca0 | 5798 | |
8a33f100 | 5799 | const char *fname, *tname; |
85363ca0 | 5800 | const char *q; |
79b87c74 | 5801 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5802 | char *libfunc_name, *suffix; |
5803 | char *p; | |
5804 | ||
79b87c74 MM |
5805 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5806 | depends on which underlying decimal floating point format is used. */ | |
5807 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5808 | ||
8a33f100 | 5809 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5810 | |
d3bfe4de | 5811 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5812 | nondec_name[0] = '_'; |
5813 | nondec_name[1] = '_'; | |
5814 | memcpy (&nondec_name[2], opname, opname_len); | |
5815 | nondec_suffix = nondec_name + opname_len + 2; | |
5816 | ||
d3bfe4de | 5817 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5818 | dec_name[0] = '_'; |
5819 | dec_name[1] = '_'; | |
5820 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5821 | memcpy (&dec_name[2 + dec_len], opname, opname_len); | |
5822 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5823 | |
8a33f100 JH |
5824 | fname = GET_MODE_NAME (fmode); |
5825 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5826 | |
8a33f100 JH |
5827 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5828 | { | |
5829 | libfunc_name = dec_name; | |
5830 | suffix = dec_suffix; | |
5831 | } | |
5832 | else | |
5833 | { | |
5834 | libfunc_name = nondec_name; | |
5835 | suffix = nondec_suffix; | |
5836 | } | |
79b87c74 | 5837 | |
8a33f100 JH |
5838 | p = suffix; |
5839 | for (q = fname; *q; p++, q++) | |
5840 | *p = TOLOWER (*q); | |
5841 | for (q = tname; *q; p++, q++) | |
5842 | *p = TOLOWER (*q); | |
85363ca0 | 5843 | |
8a33f100 JH |
5844 | *p++ = '2'; |
5845 | *p = '\0'; | |
85363ca0 | 5846 | |
8a33f100 JH |
5847 | set_conv_libfunc (tab, tmode, fmode, |
5848 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5849 | } |
5850 | ||
8a33f100 JH |
5851 | /* Pick proper libcall for trunc_optab. We need to chose if we do |
5852 | truncation or extension and interclass or intraclass. */ | |
5853 | ||
5854 | static void | |
5855 | gen_trunc_conv_libfunc (convert_optab tab, | |
5856 | const char *opname, | |
5857 | enum machine_mode tmode, | |
5858 | enum machine_mode fmode) | |
5859 | { | |
5860 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5861 | return; | |
5862 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5863 | return; | |
5864 | if (tmode == fmode) | |
5865 | return; | |
5866 | ||
5867 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5868 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5869 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5870 | ||
5871 | if (GET_MODE_PRECISION (fmode) <= GET_MODE_PRECISION (tmode)) | |
5872 | return; | |
5873 | ||
5874 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5875 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5876 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5877 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5878 | } | |
5879 | ||
5880 | /* Pick proper libcall for extend_optab. We need to chose if we do | |
5881 | truncation or extension and interclass or intraclass. */ | |
5882 | ||
5883 | static void | |
5884 | gen_extend_conv_libfunc (convert_optab tab, | |
5885 | const char *opname ATTRIBUTE_UNUSED, | |
5886 | enum machine_mode tmode, | |
5887 | enum machine_mode fmode) | |
5888 | { | |
5889 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5890 | return; | |
5891 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5892 | return; | |
5893 | if (tmode == fmode) | |
5894 | return; | |
5895 | ||
5896 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5897 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5898 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5899 | ||
5900 | if (GET_MODE_PRECISION (fmode) > GET_MODE_PRECISION (tmode)) | |
5901 | return; | |
5902 | ||
5903 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5904 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5905 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5906 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5907 | } | |
85363ca0 | 5908 | |
0f996086 CF |
5909 | /* Pick proper libcall for fract_optab. We need to chose if we do |
5910 | interclass or intraclass. */ | |
5911 | ||
5912 | static void | |
5913 | gen_fract_conv_libfunc (convert_optab tab, | |
5914 | const char *opname, | |
5915 | enum machine_mode tmode, | |
5916 | enum machine_mode fmode) | |
5917 | { | |
5918 | if (tmode == fmode) | |
5919 | return; | |
5920 | if (!(ALL_FIXED_POINT_MODE_P (tmode) || ALL_FIXED_POINT_MODE_P (fmode))) | |
5921 | return; | |
5922 | ||
5923 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5924 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5925 | else | |
5926 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5927 | } | |
5928 | ||
5929 | /* Pick proper libcall for fractuns_optab. */ | |
5930 | ||
5931 | static void | |
5932 | gen_fractuns_conv_libfunc (convert_optab tab, | |
5933 | const char *opname, | |
5934 | enum machine_mode tmode, | |
5935 | enum machine_mode fmode) | |
5936 | { | |
5937 | if (tmode == fmode) | |
5938 | return; | |
5939 | /* One mode must be a fixed-point mode, and the other must be an integer | |
5940 | mode. */ | |
5941 | if (!((ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT) | |
5942 | || (ALL_FIXED_POINT_MODE_P (fmode) | |
5943 | && GET_MODE_CLASS (tmode) == MODE_INT))) | |
5944 | return; | |
5945 | ||
5946 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5947 | } | |
5948 | ||
5949 | /* Pick proper libcall for satfract_optab. We need to chose if we do | |
5950 | interclass or intraclass. */ | |
5951 | ||
5952 | static void | |
5953 | gen_satfract_conv_libfunc (convert_optab tab, | |
5954 | const char *opname, | |
5955 | enum machine_mode tmode, | |
5956 | enum machine_mode fmode) | |
5957 | { | |
5958 | if (tmode == fmode) | |
5959 | return; | |
5960 | /* TMODE must be a fixed-point mode. */ | |
5961 | if (!ALL_FIXED_POINT_MODE_P (tmode)) | |
5962 | return; | |
5963 | ||
5964 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5965 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5966 | else | |
5967 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5968 | } | |
5969 | ||
5970 | /* Pick proper libcall for satfractuns_optab. */ | |
5971 | ||
5972 | static void | |
5973 | gen_satfractuns_conv_libfunc (convert_optab tab, | |
5974 | const char *opname, | |
5975 | enum machine_mode tmode, | |
5976 | enum machine_mode fmode) | |
5977 | { | |
5978 | if (tmode == fmode) | |
5979 | return; | |
5980 | /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */ | |
5981 | if (!(ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT)) | |
5982 | return; | |
5983 | ||
5984 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5985 | } | |
5986 | ||
76095e2f | 5987 | rtx |
0c20a65f | 5988 | init_one_libfunc (const char *name) |
76095e2f | 5989 | { |
52859c77 RH |
5990 | rtx symbol; |
5991 | ||
fb49053f RH |
5992 | /* Create a FUNCTION_DECL that can be passed to |
5993 | targetm.encode_section_info. */ | |
ee1315aa | 5994 | /* ??? We don't have any type information except for this is |
9c2f7166 | 5995 | a function. Pretend this is "int foo()". */ |
ee1315aa | 5996 | tree decl = build_decl (FUNCTION_DECL, get_identifier (name), |
9c2f7166 | 5997 | build_function_type (integer_type_node, NULL_TREE)); |
ee1315aa RH |
5998 | DECL_ARTIFICIAL (decl) = 1; |
5999 | DECL_EXTERNAL (decl) = 1; | |
6000 | TREE_PUBLIC (decl) = 1; | |
6001 | ||
52859c77 RH |
6002 | symbol = XEXP (DECL_RTL (decl), 0); |
6003 | ||
6004 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
6005 | are the flags assigned by targetm.encode_section_info. */ | |
929e5e5b | 6006 | SET_SYMBOL_REF_DECL (symbol, 0); |
52859c77 RH |
6007 | |
6008 | return symbol; | |
76095e2f RH |
6009 | } |
6010 | ||
c15c90bb ZW |
6011 | /* Call this to reset the function entry for one optab (OPTABLE) in mode |
6012 | MODE to NAME, which should be either 0 or a string constant. */ | |
6013 | void | |
6014 | set_optab_libfunc (optab optable, enum machine_mode mode, const char *name) | |
6015 | { | |
8a33f100 JH |
6016 | rtx val; |
6017 | struct libfunc_entry e; | |
6018 | struct libfunc_entry **slot; | |
33727b5e | 6019 | e.optab = (size_t) (optable - &optab_table[0]); |
8a33f100 JH |
6020 | e.mode1 = mode; |
6021 | e.mode2 = VOIDmode; | |
6022 | ||
c15c90bb | 6023 | if (name) |
8a33f100 | 6024 | val = init_one_libfunc (name); |
c15c90bb | 6025 | else |
8a33f100 JH |
6026 | val = 0; |
6027 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6028 | if (*slot == NULL) | |
d3bfe4de | 6029 | *slot = GGC_NEW (struct libfunc_entry); |
33727b5e | 6030 | (*slot)->optab = (size_t) (optable - &optab_table[0]); |
8a33f100 JH |
6031 | (*slot)->mode1 = mode; |
6032 | (*slot)->mode2 = VOIDmode; | |
6033 | (*slot)->libfunc = val; | |
c15c90bb ZW |
6034 | } |
6035 | ||
85363ca0 ZW |
6036 | /* Call this to reset the function entry for one conversion optab |
6037 | (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be | |
6038 | either 0 or a string constant. */ | |
6039 | void | |
6040 | set_conv_libfunc (convert_optab optable, enum machine_mode tmode, | |
6041 | enum machine_mode fmode, const char *name) | |
6042 | { | |
8a33f100 JH |
6043 | rtx val; |
6044 | struct libfunc_entry e; | |
6045 | struct libfunc_entry **slot; | |
33727b5e | 6046 | e.optab = (size_t) (optable - &convert_optab_table[0]); |
8a33f100 JH |
6047 | e.mode1 = tmode; |
6048 | e.mode2 = fmode; | |
6049 | ||
85363ca0 | 6050 | if (name) |
8a33f100 | 6051 | val = init_one_libfunc (name); |
85363ca0 | 6052 | else |
8a33f100 JH |
6053 | val = 0; |
6054 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6055 | if (*slot == NULL) | |
d3bfe4de | 6056 | *slot = GGC_NEW (struct libfunc_entry); |
33727b5e | 6057 | (*slot)->optab = (size_t) (optable - &convert_optab_table[0]); |
8a33f100 JH |
6058 | (*slot)->mode1 = tmode; |
6059 | (*slot)->mode2 = fmode; | |
6060 | (*slot)->libfunc = val; | |
85363ca0 ZW |
6061 | } |
6062 | ||
b5deb7b6 | 6063 | /* Call this to initialize the contents of the optabs |
77c9c6c2 RK |
6064 | appropriately for the current target machine. */ |
6065 | ||
6066 | void | |
0c20a65f | 6067 | init_optabs (void) |
77c9c6c2 | 6068 | { |
85363ca0 | 6069 | unsigned int i; |
aeed4133 | 6070 | enum machine_mode int_mode; |
c0742514 | 6071 | static bool reinit; |
77c9c6c2 | 6072 | |
8a33f100 | 6073 | libfunc_hash = htab_create_ggc (10, hash_libfunc, eq_libfunc, NULL); |
5d81dc5b | 6074 | /* Start by initializing all tables to contain CODE_FOR_nothing. */ |
77c9c6c2 | 6075 | |
5d81dc5b RK |
6076 | for (i = 0; i < NUM_RTX_CODE; i++) |
6077 | setcc_gen_code[i] = CODE_FOR_nothing; | |
6078 | ||
49c4584c DE |
6079 | #ifdef HAVE_conditional_move |
6080 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
6081 | movcc_gen_code[i] = CODE_FOR_nothing; | |
6082 | #endif | |
6083 | ||
7ce67fbe DP |
6084 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
6085 | { | |
6086 | vcond_gen_code[i] = CODE_FOR_nothing; | |
6087 | vcondu_gen_code[i] = CODE_FOR_nothing; | |
6088 | } | |
6089 | ||
c0742514 JJ |
6090 | #if GCC_VERSION >= 4000 |
6091 | /* We statically initialize the insn_codes with CODE_FOR_nothing. */ | |
6092 | if (reinit) | |
6093 | init_insn_codes (); | |
6094 | #else | |
6095 | init_insn_codes (); | |
6096 | #endif | |
6097 | ||
33727b5e JJ |
6098 | init_optab (add_optab, PLUS); |
6099 | init_optabv (addv_optab, PLUS); | |
6100 | init_optab (sub_optab, MINUS); | |
6101 | init_optabv (subv_optab, MINUS); | |
6102 | init_optab (ssadd_optab, SS_PLUS); | |
6103 | init_optab (usadd_optab, US_PLUS); | |
6104 | init_optab (sssub_optab, SS_MINUS); | |
6105 | init_optab (ussub_optab, US_MINUS); | |
6106 | init_optab (smul_optab, MULT); | |
6107 | init_optab (ssmul_optab, SS_MULT); | |
6108 | init_optab (usmul_optab, US_MULT); | |
6109 | init_optabv (smulv_optab, MULT); | |
6110 | init_optab (smul_highpart_optab, UNKNOWN); | |
6111 | init_optab (umul_highpart_optab, UNKNOWN); | |
6112 | init_optab (smul_widen_optab, UNKNOWN); | |
6113 | init_optab (umul_widen_optab, UNKNOWN); | |
6114 | init_optab (usmul_widen_optab, UNKNOWN); | |
6115 | init_optab (smadd_widen_optab, UNKNOWN); | |
6116 | init_optab (umadd_widen_optab, UNKNOWN); | |
6117 | init_optab (ssmadd_widen_optab, UNKNOWN); | |
6118 | init_optab (usmadd_widen_optab, UNKNOWN); | |
6119 | init_optab (smsub_widen_optab, UNKNOWN); | |
6120 | init_optab (umsub_widen_optab, UNKNOWN); | |
6121 | init_optab (ssmsub_widen_optab, UNKNOWN); | |
6122 | init_optab (usmsub_widen_optab, UNKNOWN); | |
6123 | init_optab (sdiv_optab, DIV); | |
6124 | init_optab (ssdiv_optab, SS_DIV); | |
6125 | init_optab (usdiv_optab, US_DIV); | |
6126 | init_optabv (sdivv_optab, DIV); | |
6127 | init_optab (sdivmod_optab, UNKNOWN); | |
6128 | init_optab (udiv_optab, UDIV); | |
6129 | init_optab (udivmod_optab, UNKNOWN); | |
6130 | init_optab (smod_optab, MOD); | |
6131 | init_optab (umod_optab, UMOD); | |
6132 | init_optab (fmod_optab, UNKNOWN); | |
6133 | init_optab (remainder_optab, UNKNOWN); | |
6134 | init_optab (ftrunc_optab, UNKNOWN); | |
6135 | init_optab (and_optab, AND); | |
6136 | init_optab (ior_optab, IOR); | |
6137 | init_optab (xor_optab, XOR); | |
6138 | init_optab (ashl_optab, ASHIFT); | |
6139 | init_optab (ssashl_optab, SS_ASHIFT); | |
6140 | init_optab (usashl_optab, US_ASHIFT); | |
6141 | init_optab (ashr_optab, ASHIFTRT); | |
6142 | init_optab (lshr_optab, LSHIFTRT); | |
6143 | init_optab (rotl_optab, ROTATE); | |
6144 | init_optab (rotr_optab, ROTATERT); | |
6145 | init_optab (smin_optab, SMIN); | |
6146 | init_optab (smax_optab, SMAX); | |
6147 | init_optab (umin_optab, UMIN); | |
6148 | init_optab (umax_optab, UMAX); | |
6149 | init_optab (pow_optab, UNKNOWN); | |
6150 | init_optab (atan2_optab, UNKNOWN); | |
ef89d648 ZW |
6151 | |
6152 | /* These three have codes assigned exclusively for the sake of | |
6153 | have_insn_for. */ | |
33727b5e JJ |
6154 | init_optab (mov_optab, SET); |
6155 | init_optab (movstrict_optab, STRICT_LOW_PART); | |
6156 | init_optab (cmp_optab, COMPARE); | |
6157 | ||
6158 | init_optab (storent_optab, UNKNOWN); | |
6159 | ||
6160 | init_optab (ucmp_optab, UNKNOWN); | |
6161 | init_optab (tst_optab, UNKNOWN); | |
6162 | ||
6163 | init_optab (eq_optab, EQ); | |
6164 | init_optab (ne_optab, NE); | |
6165 | init_optab (gt_optab, GT); | |
6166 | init_optab (ge_optab, GE); | |
6167 | init_optab (lt_optab, LT); | |
6168 | init_optab (le_optab, LE); | |
6169 | init_optab (unord_optab, UNORDERED); | |
6170 | ||
6171 | init_optab (neg_optab, NEG); | |
6172 | init_optab (ssneg_optab, SS_NEG); | |
6173 | init_optab (usneg_optab, US_NEG); | |
6174 | init_optabv (negv_optab, NEG); | |
6175 | init_optab (abs_optab, ABS); | |
6176 | init_optabv (absv_optab, ABS); | |
6177 | init_optab (addcc_optab, UNKNOWN); | |
6178 | init_optab (one_cmpl_optab, NOT); | |
6179 | init_optab (bswap_optab, BSWAP); | |
6180 | init_optab (ffs_optab, FFS); | |
6181 | init_optab (clz_optab, CLZ); | |
6182 | init_optab (ctz_optab, CTZ); | |
6183 | init_optab (popcount_optab, POPCOUNT); | |
6184 | init_optab (parity_optab, PARITY); | |
6185 | init_optab (sqrt_optab, SQRT); | |
6186 | init_optab (floor_optab, UNKNOWN); | |
6187 | init_optab (ceil_optab, UNKNOWN); | |
6188 | init_optab (round_optab, UNKNOWN); | |
6189 | init_optab (btrunc_optab, UNKNOWN); | |
6190 | init_optab (nearbyint_optab, UNKNOWN); | |
6191 | init_optab (rint_optab, UNKNOWN); | |
6192 | init_optab (sincos_optab, UNKNOWN); | |
6193 | init_optab (sin_optab, UNKNOWN); | |
6194 | init_optab (asin_optab, UNKNOWN); | |
6195 | init_optab (cos_optab, UNKNOWN); | |
6196 | init_optab (acos_optab, UNKNOWN); | |
6197 | init_optab (exp_optab, UNKNOWN); | |
6198 | init_optab (exp10_optab, UNKNOWN); | |
6199 | init_optab (exp2_optab, UNKNOWN); | |
6200 | init_optab (expm1_optab, UNKNOWN); | |
6201 | init_optab (ldexp_optab, UNKNOWN); | |
6202 | init_optab (scalb_optab, UNKNOWN); | |
6203 | init_optab (logb_optab, UNKNOWN); | |
6204 | init_optab (ilogb_optab, UNKNOWN); | |
6205 | init_optab (log_optab, UNKNOWN); | |
6206 | init_optab (log10_optab, UNKNOWN); | |
6207 | init_optab (log2_optab, UNKNOWN); | |
6208 | init_optab (log1p_optab, UNKNOWN); | |
6209 | init_optab (tan_optab, UNKNOWN); | |
6210 | init_optab (atan_optab, UNKNOWN); | |
6211 | init_optab (copysign_optab, UNKNOWN); | |
6212 | init_optab (signbit_optab, UNKNOWN); | |
6213 | ||
6214 | init_optab (isinf_optab, UNKNOWN); | |
6215 | ||
6216 | init_optab (strlen_optab, UNKNOWN); | |
6217 | init_optab (cbranch_optab, UNKNOWN); | |
6218 | init_optab (cmov_optab, UNKNOWN); | |
6219 | init_optab (cstore_optab, UNKNOWN); | |
6220 | init_optab (push_optab, UNKNOWN); | |
6221 | ||
6222 | init_optab (reduc_smax_optab, UNKNOWN); | |
6223 | init_optab (reduc_umax_optab, UNKNOWN); | |
6224 | init_optab (reduc_smin_optab, UNKNOWN); | |
6225 | init_optab (reduc_umin_optab, UNKNOWN); | |
6226 | init_optab (reduc_splus_optab, UNKNOWN); | |
6227 | init_optab (reduc_uplus_optab, UNKNOWN); | |
6228 | ||
6229 | init_optab (ssum_widen_optab, UNKNOWN); | |
6230 | init_optab (usum_widen_optab, UNKNOWN); | |
6231 | init_optab (sdot_prod_optab, UNKNOWN); | |
6232 | init_optab (udot_prod_optab, UNKNOWN); | |
6233 | ||
6234 | init_optab (vec_extract_optab, UNKNOWN); | |
6235 | init_optab (vec_extract_even_optab, UNKNOWN); | |
6236 | init_optab (vec_extract_odd_optab, UNKNOWN); | |
6237 | init_optab (vec_interleave_high_optab, UNKNOWN); | |
6238 | init_optab (vec_interleave_low_optab, UNKNOWN); | |
6239 | init_optab (vec_set_optab, UNKNOWN); | |
6240 | init_optab (vec_init_optab, UNKNOWN); | |
6241 | init_optab (vec_shl_optab, UNKNOWN); | |
6242 | init_optab (vec_shr_optab, UNKNOWN); | |
6243 | init_optab (vec_realign_load_optab, UNKNOWN); | |
6244 | init_optab (movmisalign_optab, UNKNOWN); | |
6245 | init_optab (vec_widen_umult_hi_optab, UNKNOWN); | |
6246 | init_optab (vec_widen_umult_lo_optab, UNKNOWN); | |
6247 | init_optab (vec_widen_smult_hi_optab, UNKNOWN); | |
6248 | init_optab (vec_widen_smult_lo_optab, UNKNOWN); | |
6249 | init_optab (vec_unpacks_hi_optab, UNKNOWN); | |
6250 | init_optab (vec_unpacks_lo_optab, UNKNOWN); | |
6251 | init_optab (vec_unpacku_hi_optab, UNKNOWN); | |
6252 | init_optab (vec_unpacku_lo_optab, UNKNOWN); | |
6253 | init_optab (vec_unpacks_float_hi_optab, UNKNOWN); | |
6254 | init_optab (vec_unpacks_float_lo_optab, UNKNOWN); | |
6255 | init_optab (vec_unpacku_float_hi_optab, UNKNOWN); | |
6256 | init_optab (vec_unpacku_float_lo_optab, UNKNOWN); | |
6257 | init_optab (vec_pack_trunc_optab, UNKNOWN); | |
6258 | init_optab (vec_pack_usat_optab, UNKNOWN); | |
6259 | init_optab (vec_pack_ssat_optab, UNKNOWN); | |
6260 | init_optab (vec_pack_ufix_trunc_optab, UNKNOWN); | |
6261 | init_optab (vec_pack_sfix_trunc_optab, UNKNOWN); | |
6262 | ||
6263 | init_optab (powi_optab, UNKNOWN); | |
17684d46 | 6264 | |
85363ca0 | 6265 | /* Conversions. */ |
33727b5e JJ |
6266 | init_convert_optab (sext_optab, SIGN_EXTEND); |
6267 | init_convert_optab (zext_optab, ZERO_EXTEND); | |
6268 | init_convert_optab (trunc_optab, TRUNCATE); | |
6269 | init_convert_optab (sfix_optab, FIX); | |
6270 | init_convert_optab (ufix_optab, UNSIGNED_FIX); | |
6271 | init_convert_optab (sfixtrunc_optab, UNKNOWN); | |
6272 | init_convert_optab (ufixtrunc_optab, UNKNOWN); | |
6273 | init_convert_optab (sfloat_optab, FLOAT); | |
6274 | init_convert_optab (ufloat_optab, UNSIGNED_FLOAT); | |
6275 | init_convert_optab (lrint_optab, UNKNOWN); | |
6276 | init_convert_optab (lround_optab, UNKNOWN); | |
6277 | init_convert_optab (lfloor_optab, UNKNOWN); | |
6278 | init_convert_optab (lceil_optab, UNKNOWN); | |
6279 | ||
6280 | init_convert_optab (fract_optab, FRACT_CONVERT); | |
6281 | init_convert_optab (fractuns_optab, UNSIGNED_FRACT_CONVERT); | |
6282 | init_convert_optab (satfract_optab, SAT_FRACT); | |
6283 | init_convert_optab (satfractuns_optab, UNSIGNED_SAT_FRACT); | |
0f996086 | 6284 | |
5d81dc5b RK |
6285 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
6286 | { | |
70128ad9 | 6287 | movmem_optab[i] = CODE_FOR_nothing; |
118355a0 | 6288 | cmpstr_optab[i] = CODE_FOR_nothing; |
40c1d5f8 | 6289 | cmpstrn_optab[i] = CODE_FOR_nothing; |
118355a0 | 6290 | cmpmem_optab[i] = CODE_FOR_nothing; |
57e84f18 | 6291 | setmem_optab[i] = CODE_FOR_nothing; |
5d81dc5b | 6292 | |
48ae6c13 RH |
6293 | sync_add_optab[i] = CODE_FOR_nothing; |
6294 | sync_sub_optab[i] = CODE_FOR_nothing; | |
6295 | sync_ior_optab[i] = CODE_FOR_nothing; | |
6296 | sync_and_optab[i] = CODE_FOR_nothing; | |
6297 | sync_xor_optab[i] = CODE_FOR_nothing; | |
6298 | sync_nand_optab[i] = CODE_FOR_nothing; | |
6299 | sync_old_add_optab[i] = CODE_FOR_nothing; | |
6300 | sync_old_sub_optab[i] = CODE_FOR_nothing; | |
6301 | sync_old_ior_optab[i] = CODE_FOR_nothing; | |
6302 | sync_old_and_optab[i] = CODE_FOR_nothing; | |
6303 | sync_old_xor_optab[i] = CODE_FOR_nothing; | |
6304 | sync_old_nand_optab[i] = CODE_FOR_nothing; | |
6305 | sync_new_add_optab[i] = CODE_FOR_nothing; | |
6306 | sync_new_sub_optab[i] = CODE_FOR_nothing; | |
6307 | sync_new_ior_optab[i] = CODE_FOR_nothing; | |
6308 | sync_new_and_optab[i] = CODE_FOR_nothing; | |
6309 | sync_new_xor_optab[i] = CODE_FOR_nothing; | |
6310 | sync_new_nand_optab[i] = CODE_FOR_nothing; | |
6311 | sync_compare_and_swap[i] = CODE_FOR_nothing; | |
6312 | sync_compare_and_swap_cc[i] = CODE_FOR_nothing; | |
6313 | sync_lock_test_and_set[i] = CODE_FOR_nothing; | |
6314 | sync_lock_release[i] = CODE_FOR_nothing; | |
6315 | ||
5d81dc5b | 6316 | reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing; |
5d81dc5b RK |
6317 | } |
6318 | ||
6319 | /* Fill in the optabs with the insns we support. */ | |
6320 | init_all_optabs (); | |
6321 | ||
5d81dc5b | 6322 | /* Initialize the optabs with the names of the library functions. */ |
8a33f100 JH |
6323 | add_optab->libcall_basename = "add"; |
6324 | add_optab->libcall_suffix = '3'; | |
0f996086 | 6325 | add_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6326 | addv_optab->libcall_basename = "add"; |
6327 | addv_optab->libcall_suffix = '3'; | |
6328 | addv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6329 | ssadd_optab->libcall_basename = "ssadd"; |
6330 | ssadd_optab->libcall_suffix = '3'; | |
6331 | ssadd_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6332 | usadd_optab->libcall_basename = "usadd"; | |
6333 | usadd_optab->libcall_suffix = '3'; | |
6334 | usadd_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6335 | sub_optab->libcall_basename = "sub"; |
6336 | sub_optab->libcall_suffix = '3'; | |
0f996086 | 6337 | sub_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6338 | subv_optab->libcall_basename = "sub"; |
6339 | subv_optab->libcall_suffix = '3'; | |
6340 | subv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6341 | sssub_optab->libcall_basename = "sssub"; |
6342 | sssub_optab->libcall_suffix = '3'; | |
6343 | sssub_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6344 | ussub_optab->libcall_basename = "ussub"; | |
6345 | ussub_optab->libcall_suffix = '3'; | |
6346 | ussub_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6347 | smul_optab->libcall_basename = "mul"; |
6348 | smul_optab->libcall_suffix = '3'; | |
0f996086 | 6349 | smul_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6350 | smulv_optab->libcall_basename = "mul"; |
6351 | smulv_optab->libcall_suffix = '3'; | |
6352 | smulv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6353 | ssmul_optab->libcall_basename = "ssmul"; |
6354 | ssmul_optab->libcall_suffix = '3'; | |
6355 | ssmul_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6356 | usmul_optab->libcall_basename = "usmul"; | |
6357 | usmul_optab->libcall_suffix = '3'; | |
6358 | usmul_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6359 | sdiv_optab->libcall_basename = "div"; |
6360 | sdiv_optab->libcall_suffix = '3'; | |
0f996086 | 6361 | sdiv_optab->libcall_gen = gen_int_fp_signed_fixed_libfunc; |
8a33f100 JH |
6362 | sdivv_optab->libcall_basename = "divv"; |
6363 | sdivv_optab->libcall_suffix = '3'; | |
6364 | sdivv_optab->libcall_gen = gen_int_libfunc; | |
0f996086 CF |
6365 | ssdiv_optab->libcall_basename = "ssdiv"; |
6366 | ssdiv_optab->libcall_suffix = '3'; | |
6367 | ssdiv_optab->libcall_gen = gen_signed_fixed_libfunc; | |
8a33f100 JH |
6368 | udiv_optab->libcall_basename = "udiv"; |
6369 | udiv_optab->libcall_suffix = '3'; | |
0f996086 CF |
6370 | udiv_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
6371 | usdiv_optab->libcall_basename = "usdiv"; | |
6372 | usdiv_optab->libcall_suffix = '3'; | |
6373 | usdiv_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6374 | sdivmod_optab->libcall_basename = "divmod"; |
6375 | sdivmod_optab->libcall_suffix = '4'; | |
6376 | sdivmod_optab->libcall_gen = gen_int_libfunc; | |
6377 | udivmod_optab->libcall_basename = "udivmod"; | |
6378 | udivmod_optab->libcall_suffix = '4'; | |
6379 | udivmod_optab->libcall_gen = gen_int_libfunc; | |
6380 | smod_optab->libcall_basename = "mod"; | |
6381 | smod_optab->libcall_suffix = '3'; | |
6382 | smod_optab->libcall_gen = gen_int_libfunc; | |
6383 | umod_optab->libcall_basename = "umod"; | |
6384 | umod_optab->libcall_suffix = '3'; | |
6385 | umod_optab->libcall_gen = gen_int_libfunc; | |
6386 | ftrunc_optab->libcall_basename = "ftrunc"; | |
6387 | ftrunc_optab->libcall_suffix = '2'; | |
6388 | ftrunc_optab->libcall_gen = gen_fp_libfunc; | |
6389 | and_optab->libcall_basename = "and"; | |
6390 | and_optab->libcall_suffix = '3'; | |
6391 | and_optab->libcall_gen = gen_int_libfunc; | |
6392 | ior_optab->libcall_basename = "ior"; | |
6393 | ior_optab->libcall_suffix = '3'; | |
6394 | ior_optab->libcall_gen = gen_int_libfunc; | |
6395 | xor_optab->libcall_basename = "xor"; | |
6396 | xor_optab->libcall_suffix = '3'; | |
6397 | xor_optab->libcall_gen = gen_int_libfunc; | |
6398 | ashl_optab->libcall_basename = "ashl"; | |
6399 | ashl_optab->libcall_suffix = '3'; | |
0f996086 CF |
6400 | ashl_optab->libcall_gen = gen_int_fixed_libfunc; |
6401 | ssashl_optab->libcall_basename = "ssashl"; | |
6402 | ssashl_optab->libcall_suffix = '3'; | |
6403 | ssashl_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6404 | usashl_optab->libcall_basename = "usashl"; | |
6405 | usashl_optab->libcall_suffix = '3'; | |
6406 | usashl_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6407 | ashr_optab->libcall_basename = "ashr"; |
6408 | ashr_optab->libcall_suffix = '3'; | |
0f996086 | 6409 | ashr_optab->libcall_gen = gen_int_signed_fixed_libfunc; |
8a33f100 JH |
6410 | lshr_optab->libcall_basename = "lshr"; |
6411 | lshr_optab->libcall_suffix = '3'; | |
0f996086 | 6412 | lshr_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
8a33f100 JH |
6413 | smin_optab->libcall_basename = "min"; |
6414 | smin_optab->libcall_suffix = '3'; | |
6415 | smin_optab->libcall_gen = gen_int_fp_libfunc; | |
6416 | smax_optab->libcall_basename = "max"; | |
6417 | smax_optab->libcall_suffix = '3'; | |
6418 | smax_optab->libcall_gen = gen_int_fp_libfunc; | |
6419 | umin_optab->libcall_basename = "umin"; | |
6420 | umin_optab->libcall_suffix = '3'; | |
6421 | umin_optab->libcall_gen = gen_int_libfunc; | |
6422 | umax_optab->libcall_basename = "umax"; | |
6423 | umax_optab->libcall_suffix = '3'; | |
6424 | umax_optab->libcall_gen = gen_int_libfunc; | |
6425 | neg_optab->libcall_basename = "neg"; | |
6426 | neg_optab->libcall_suffix = '2'; | |
0f996086 CF |
6427 | neg_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
6428 | ssneg_optab->libcall_basename = "ssneg"; | |
6429 | ssneg_optab->libcall_suffix = '2'; | |
6430 | ssneg_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6431 | usneg_optab->libcall_basename = "usneg"; | |
6432 | usneg_optab->libcall_suffix = '2'; | |
6433 | usneg_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6434 | negv_optab->libcall_basename = "neg"; |
6435 | negv_optab->libcall_suffix = '2'; | |
6436 | negv_optab->libcall_gen = gen_intv_fp_libfunc; | |
6437 | one_cmpl_optab->libcall_basename = "one_cmpl"; | |
6438 | one_cmpl_optab->libcall_suffix = '2'; | |
6439 | one_cmpl_optab->libcall_gen = gen_int_libfunc; | |
6440 | ffs_optab->libcall_basename = "ffs"; | |
6441 | ffs_optab->libcall_suffix = '2'; | |
6442 | ffs_optab->libcall_gen = gen_int_libfunc; | |
6443 | clz_optab->libcall_basename = "clz"; | |
6444 | clz_optab->libcall_suffix = '2'; | |
6445 | clz_optab->libcall_gen = gen_int_libfunc; | |
6446 | ctz_optab->libcall_basename = "ctz"; | |
6447 | ctz_optab->libcall_suffix = '2'; | |
6448 | ctz_optab->libcall_gen = gen_int_libfunc; | |
6449 | popcount_optab->libcall_basename = "popcount"; | |
6450 | popcount_optab->libcall_suffix = '2'; | |
6451 | popcount_optab->libcall_gen = gen_int_libfunc; | |
6452 | parity_optab->libcall_basename = "parity"; | |
6453 | parity_optab->libcall_suffix = '2'; | |
6454 | parity_optab->libcall_gen = gen_int_libfunc; | |
d55ab31d MM |
6455 | |
6456 | /* Comparison libcalls for integers MUST come in pairs, | |
6457 | signed/unsigned. */ | |
8a33f100 JH |
6458 | cmp_optab->libcall_basename = "cmp"; |
6459 | cmp_optab->libcall_suffix = '2'; | |
0f996086 | 6460 | cmp_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6461 | ucmp_optab->libcall_basename = "ucmp"; |
6462 | ucmp_optab->libcall_suffix = '2'; | |
6463 | ucmp_optab->libcall_gen = gen_int_libfunc; | |
d55ab31d MM |
6464 | |
6465 | /* EQ etc are floating point only. */ | |
8a33f100 JH |
6466 | eq_optab->libcall_basename = "eq"; |
6467 | eq_optab->libcall_suffix = '2'; | |
6468 | eq_optab->libcall_gen = gen_fp_libfunc; | |
6469 | ne_optab->libcall_basename = "ne"; | |
6470 | ne_optab->libcall_suffix = '2'; | |
6471 | ne_optab->libcall_gen = gen_fp_libfunc; | |
6472 | gt_optab->libcall_basename = "gt"; | |
6473 | gt_optab->libcall_suffix = '2'; | |
6474 | gt_optab->libcall_gen = gen_fp_libfunc; | |
6475 | ge_optab->libcall_basename = "ge"; | |
6476 | ge_optab->libcall_suffix = '2'; | |
6477 | ge_optab->libcall_gen = gen_fp_libfunc; | |
6478 | lt_optab->libcall_basename = "lt"; | |
6479 | lt_optab->libcall_suffix = '2'; | |
6480 | lt_optab->libcall_gen = gen_fp_libfunc; | |
6481 | le_optab->libcall_basename = "le"; | |
6482 | le_optab->libcall_suffix = '2'; | |
6483 | le_optab->libcall_gen = gen_fp_libfunc; | |
6484 | unord_optab->libcall_basename = "unord"; | |
6485 | unord_optab->libcall_suffix = '2'; | |
6486 | unord_optab->libcall_gen = gen_fp_libfunc; | |
6487 | ||
6488 | powi_optab->libcall_basename = "powi"; | |
6489 | powi_optab->libcall_suffix = '2'; | |
6490 | powi_optab->libcall_gen = gen_fp_libfunc; | |
17684d46 | 6491 | |
d55ab31d | 6492 | /* Conversions. */ |
8a33f100 JH |
6493 | sfloat_optab->libcall_basename = "float"; |
6494 | sfloat_optab->libcall_gen = gen_int_to_fp_conv_libfunc; | |
6495 | ufloat_optab->libcall_gen = gen_ufloat_conv_libfunc; | |
6496 | sfix_optab->libcall_basename = "fix"; | |
6497 | sfix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6498 | ufix_optab->libcall_basename = "fixuns"; | |
6499 | ufix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6500 | lrint_optab->libcall_basename = "lrint"; | |
6501 | lrint_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6502 | lround_optab->libcall_basename = "lround"; | |
6503 | lround_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6504 | lfloor_optab->libcall_basename = "lfloor"; | |
6505 | lfloor_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6506 | lceil_optab->libcall_basename = "lceil"; | |
6507 | lceil_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6508 | ||
6509 | /* trunc_optab is also used for FLOAT_EXTEND. */ | |
6510 | sext_optab->libcall_basename = "extend"; | |
6511 | sext_optab->libcall_gen = gen_extend_conv_libfunc; | |
6512 | trunc_optab->libcall_basename = "trunc"; | |
6513 | trunc_optab->libcall_gen = gen_trunc_conv_libfunc; | |
6514 | ||
0f996086 CF |
6515 | /* Conversions for fixed-point modes and other modes. */ |
6516 | fract_optab->libcall_basename = "fract"; | |
6517 | fract_optab->libcall_gen = gen_fract_conv_libfunc; | |
6518 | satfract_optab->libcall_basename = "satfract"; | |
6519 | satfract_optab->libcall_gen = gen_satfract_conv_libfunc; | |
6520 | fractuns_optab->libcall_basename = "fractuns"; | |
6521 | fractuns_optab->libcall_gen = gen_fractuns_conv_libfunc; | |
6522 | satfractuns_optab->libcall_basename = "satfractuns"; | |
6523 | satfractuns_optab->libcall_gen = gen_satfractuns_conv_libfunc; | |
6524 | ||
8a33f100 JH |
6525 | /* The ffs function operates on `int'. Fall back on it if we do not |
6526 | have a libgcc2 function for that width. */ | |
6527 | if (INT_TYPE_SIZE < BITS_PER_WORD) | |
6528 | { | |
6529 | int_mode = mode_for_size (INT_TYPE_SIZE, MODE_INT, 0); | |
6530 | set_optab_libfunc (ffs_optab, mode_for_size (INT_TYPE_SIZE, MODE_INT, 0), | |
6531 | "ffs"); | |
6532 | } | |
76095e2f | 6533 | |
167fa32c EC |
6534 | /* Explicitly initialize the bswap libfuncs since we need them to be |
6535 | valid for things other than word_mode. */ | |
6536 | set_optab_libfunc (bswap_optab, SImode, "__bswapsi2"); | |
6537 | set_optab_libfunc (bswap_optab, DImode, "__bswapdi2"); | |
6538 | ||
85363ca0 ZW |
6539 | /* Use cabs for double complex abs, since systems generally have cabs. |
6540 | Don't define any libcall for float complex, so that cabs will be used. */ | |
6541 | if (complex_double_type_node) | |
8a33f100 | 6542 | set_optab_libfunc (abs_optab, TYPE_MODE (complex_double_type_node), "cabs"); |
76095e2f | 6543 | |
9602f5a0 | 6544 | abort_libfunc = init_one_libfunc ("abort"); |
76095e2f | 6545 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
b215b52e | 6546 | memmove_libfunc = init_one_libfunc ("memmove"); |
76095e2f | 6547 | memcmp_libfunc = init_one_libfunc ("memcmp"); |
76095e2f | 6548 | memset_libfunc = init_one_libfunc ("memset"); |
68d28100 | 6549 | setbits_libfunc = init_one_libfunc ("__setbits"); |
76095e2f | 6550 | |
6e6a07d2 | 6551 | #ifndef DONT_USE_BUILTIN_SETJMP |
76095e2f RH |
6552 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
6553 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
27a36778 | 6554 | #else |
76095e2f RH |
6555 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
6556 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
27a36778 | 6557 | #endif |
52a11cbf RH |
6558 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
6559 | unwind_sjlj_unregister_libfunc | |
6560 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
6adb4e3a | 6561 | |
07417085 KR |
6562 | /* For function entry/exit instrumentation. */ |
6563 | profile_function_entry_libfunc | |
76095e2f | 6564 | = init_one_libfunc ("__cyg_profile_func_enter"); |
07417085 | 6565 | profile_function_exit_libfunc |
76095e2f | 6566 | = init_one_libfunc ("__cyg_profile_func_exit"); |
07417085 | 6567 | |
68d28100 | 6568 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
68d28100 | 6569 | |
842a431a DM |
6570 | if (HAVE_conditional_trap) |
6571 | trap_rtx = gen_rtx_fmt_ee (EQ, VOIDmode, NULL_RTX, NULL_RTX); | |
e0cd0770 | 6572 | |
159c2aed | 6573 | /* Allow the target to add more libcalls or rename some, etc. */ |
c15c90bb | 6574 | targetm.init_libfuncs (); |
c0742514 JJ |
6575 | |
6576 | reinit = true; | |
77c9c6c2 | 6577 | } |
b3f8d95d | 6578 | |
b3f8d95d MM |
6579 | /* Print information about the current contents of the optabs on |
6580 | STDERR. */ | |
6581 | ||
8a33f100 | 6582 | void |
b3f8d95d MM |
6583 | debug_optab_libfuncs (void) |
6584 | { | |
6585 | int i; | |
6586 | int j; | |
6587 | int k; | |
6588 | ||
6589 | /* Dump the arithmetic optabs. */ | |
5906d013 | 6590 | for (i = 0; i != (int) OTI_MAX; i++) |
b3f8d95d MM |
6591 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6592 | { | |
6593 | optab o; | |
8a33f100 | 6594 | rtx l; |
b3f8d95d | 6595 | |
33727b5e JJ |
6596 | o = &optab_table[i]; |
6597 | l = optab_libfunc (o, j); | |
8a33f100 | 6598 | if (l) |
b3f8d95d | 6599 | { |
8a33f100 | 6600 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6601 | fprintf (stderr, "%s\t%s:\t%s\n", |
b3f8d95d MM |
6602 | GET_RTX_NAME (o->code), |
6603 | GET_MODE_NAME (j), | |
8a33f100 | 6604 | XSTR (l, 0)); |
b3f8d95d MM |
6605 | } |
6606 | } | |
6607 | ||
6608 | /* Dump the conversion optabs. */ | |
c414ac1d | 6609 | for (i = 0; i < (int) COI_MAX; ++i) |
b3f8d95d MM |
6610 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6611 | for (k = 0; k < NUM_MACHINE_MODES; ++k) | |
6612 | { | |
6613 | convert_optab o; | |
8a33f100 | 6614 | rtx l; |
b3f8d95d | 6615 | |
33727b5e | 6616 | o = &convert_optab_table[i]; |
8a33f100 JH |
6617 | l = convert_optab_libfunc (o, j, k); |
6618 | if (l) | |
b3f8d95d | 6619 | { |
8a33f100 | 6620 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6621 | fprintf (stderr, "%s\t%s\t%s:\t%s\n", |
b3f8d95d MM |
6622 | GET_RTX_NAME (o->code), |
6623 | GET_MODE_NAME (j), | |
6624 | GET_MODE_NAME (k), | |
8a33f100 | 6625 | XSTR (l, 0)); |
b3f8d95d MM |
6626 | } |
6627 | } | |
6628 | } | |
6629 | ||
7e1966ca | 6630 | \f |
e0cd0770 JC |
6631 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
6632 | CODE. Return 0 on failure. */ | |
6633 | ||
6634 | rtx | |
0c20a65f AJ |
6635 | gen_cond_trap (enum rtx_code code ATTRIBUTE_UNUSED, rtx op1, |
6636 | rtx op2 ATTRIBUTE_UNUSED, rtx tcode ATTRIBUTE_UNUSED) | |
e0cd0770 JC |
6637 | { |
6638 | enum machine_mode mode = GET_MODE (op1); | |
842a431a DM |
6639 | enum insn_code icode; |
6640 | rtx insn; | |
6641 | ||
6642 | if (!HAVE_conditional_trap) | |
6643 | return 0; | |
e0cd0770 JC |
6644 | |
6645 | if (mode == VOIDmode) | |
6646 | return 0; | |
6647 | ||
166cdb08 | 6648 | icode = optab_handler (cmp_optab, mode)->insn_code; |
842a431a DM |
6649 | if (icode == CODE_FOR_nothing) |
6650 | return 0; | |
6651 | ||
6652 | start_sequence (); | |
6653 | op1 = prepare_operand (icode, op1, 0, mode, mode, 0); | |
0310c414 | 6654 | op2 = prepare_operand (icode, op2, 1, mode, mode, 0); |
d893ccde RH |
6655 | if (!op1 || !op2) |
6656 | { | |
6657 | end_sequence (); | |
6658 | return 0; | |
6659 | } | |
842a431a DM |
6660 | emit_insn (GEN_FCN (icode) (op1, op2)); |
6661 | ||
6662 | PUT_CODE (trap_rtx, code); | |
e3feb571 | 6663 | gcc_assert (HAVE_conditional_trap); |
842a431a DM |
6664 | insn = gen_conditional_trap (trap_rtx, tcode); |
6665 | if (insn) | |
e0cd0770 | 6666 | { |
842a431a DM |
6667 | emit_insn (insn); |
6668 | insn = get_insns (); | |
e0cd0770 | 6669 | } |
842a431a | 6670 | end_sequence (); |
e0cd0770 | 6671 | |
842a431a | 6672 | return insn; |
e0cd0770 | 6673 | } |
e2500fed | 6674 | |
7ce67fbe DP |
6675 | /* Return rtx code for TCODE. Use UNSIGNEDP to select signed |
6676 | or unsigned operation code. */ | |
6677 | ||
6678 | static enum rtx_code | |
6679 | get_rtx_code (enum tree_code tcode, bool unsignedp) | |
6680 | { | |
6681 | enum rtx_code code; | |
6682 | switch (tcode) | |
6683 | { | |
6684 | case EQ_EXPR: | |
6685 | code = EQ; | |
6686 | break; | |
6687 | case NE_EXPR: | |
6688 | code = NE; | |
6689 | break; | |
6690 | case LT_EXPR: | |
6691 | code = unsignedp ? LTU : LT; | |
6692 | break; | |
6693 | case LE_EXPR: | |
6694 | code = unsignedp ? LEU : LE; | |
6695 | break; | |
6696 | case GT_EXPR: | |
6697 | code = unsignedp ? GTU : GT; | |
6698 | break; | |
6699 | case GE_EXPR: | |
6700 | code = unsignedp ? GEU : GE; | |
6701 | break; | |
c414ac1d | 6702 | |
7ce67fbe DP |
6703 | case UNORDERED_EXPR: |
6704 | code = UNORDERED; | |
6705 | break; | |
6706 | case ORDERED_EXPR: | |
6707 | code = ORDERED; | |
6708 | break; | |
6709 | case UNLT_EXPR: | |
6710 | code = UNLT; | |
6711 | break; | |
6712 | case UNLE_EXPR: | |
6713 | code = UNLE; | |
6714 | break; | |
6715 | case UNGT_EXPR: | |
6716 | code = UNGT; | |
6717 | break; | |
6718 | case UNGE_EXPR: | |
6719 | code = UNGE; | |
6720 | break; | |
6721 | case UNEQ_EXPR: | |
6722 | code = UNEQ; | |
6723 | break; | |
6724 | case LTGT_EXPR: | |
6725 | code = LTGT; | |
6726 | break; | |
6727 | ||
6728 | default: | |
e3feb571 | 6729 | gcc_unreachable (); |
7ce67fbe DP |
6730 | } |
6731 | return code; | |
6732 | } | |
6733 | ||
6734 | /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or | |
6735 | unsigned operators. Do not generate compare instruction. */ | |
6736 | ||
6737 | static rtx | |
6738 | vector_compare_rtx (tree cond, bool unsignedp, enum insn_code icode) | |
6739 | { | |
6740 | enum rtx_code rcode; | |
6741 | tree t_op0, t_op1; | |
6742 | rtx rtx_op0, rtx_op1; | |
6743 | ||
e3feb571 NS |
6744 | /* This is unlikely. While generating VEC_COND_EXPR, auto vectorizer |
6745 | ensures that condition is a relational operation. */ | |
6746 | gcc_assert (COMPARISON_CLASS_P (cond)); | |
7ce67fbe | 6747 | |
c414ac1d | 6748 | rcode = get_rtx_code (TREE_CODE (cond), unsignedp); |
e3feb571 NS |
6749 | t_op0 = TREE_OPERAND (cond, 0); |
6750 | t_op1 = TREE_OPERAND (cond, 1); | |
c414ac1d | 6751 | |
7ce67fbe | 6752 | /* Expand operands. */ |
49452c07 UB |
6753 | rtx_op0 = expand_expr (t_op0, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op0)), |
6754 | EXPAND_STACK_PARM); | |
6755 | rtx_op1 = expand_expr (t_op1, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op1)), | |
6756 | EXPAND_STACK_PARM); | |
7ce67fbe | 6757 | |
e3feb571 | 6758 | if (!insn_data[icode].operand[4].predicate (rtx_op0, GET_MODE (rtx_op0)) |
7ce67fbe DP |
6759 | && GET_MODE (rtx_op0) != VOIDmode) |
6760 | rtx_op0 = force_reg (GET_MODE (rtx_op0), rtx_op0); | |
c414ac1d | 6761 | |
e3feb571 | 6762 | if (!insn_data[icode].operand[5].predicate (rtx_op1, GET_MODE (rtx_op1)) |
7ce67fbe DP |
6763 | && GET_MODE (rtx_op1) != VOIDmode) |
6764 | rtx_op1 = force_reg (GET_MODE (rtx_op1), rtx_op1); | |
6765 | ||
6766 | return gen_rtx_fmt_ee (rcode, VOIDmode, rtx_op0, rtx_op1); | |
6767 | } | |
6768 | ||
6769 | /* Return insn code for VEC_COND_EXPR EXPR. */ | |
c414ac1d EC |
6770 | |
6771 | static inline enum insn_code | |
7ce67fbe DP |
6772 | get_vcond_icode (tree expr, enum machine_mode mode) |
6773 | { | |
6774 | enum insn_code icode = CODE_FOR_nothing; | |
6775 | ||
6776 | if (TYPE_UNSIGNED (TREE_TYPE (expr))) | |
6777 | icode = vcondu_gen_code[mode]; | |
6778 | else | |
6779 | icode = vcond_gen_code[mode]; | |
6780 | return icode; | |
6781 | } | |
6782 | ||
6783 | /* Return TRUE iff, appropriate vector insns are available | |
6784 | for vector cond expr expr in VMODE mode. */ | |
6785 | ||
6786 | bool | |
6787 | expand_vec_cond_expr_p (tree expr, enum machine_mode vmode) | |
6788 | { | |
6789 | if (get_vcond_icode (expr, vmode) == CODE_FOR_nothing) | |
6790 | return false; | |
6791 | return true; | |
6792 | } | |
6793 | ||
6794 | /* Generate insns for VEC_COND_EXPR. */ | |
6795 | ||
6796 | rtx | |
6797 | expand_vec_cond_expr (tree vec_cond_expr, rtx target) | |
6798 | { | |
6799 | enum insn_code icode; | |
6800 | rtx comparison, rtx_op1, rtx_op2, cc_op0, cc_op1; | |
6801 | enum machine_mode mode = TYPE_MODE (TREE_TYPE (vec_cond_expr)); | |
6802 | bool unsignedp = TYPE_UNSIGNED (TREE_TYPE (vec_cond_expr)); | |
6803 | ||
6804 | icode = get_vcond_icode (vec_cond_expr, mode); | |
6805 | if (icode == CODE_FOR_nothing) | |
6806 | return 0; | |
6807 | ||
3bc751bd | 6808 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) |
7ce67fbe DP |
6809 | target = gen_reg_rtx (mode); |
6810 | ||
6dbd43ba | 6811 | /* Get comparison rtx. First expand both cond expr operands. */ |
c414ac1d | 6812 | comparison = vector_compare_rtx (TREE_OPERAND (vec_cond_expr, 0), |
7ce67fbe DP |
6813 | unsignedp, icode); |
6814 | cc_op0 = XEXP (comparison, 0); | |
6815 | cc_op1 = XEXP (comparison, 1); | |
6816 | /* Expand both operands and force them in reg, if required. */ | |
49452c07 | 6817 | rtx_op1 = expand_normal (TREE_OPERAND (vec_cond_expr, 1)); |
e3feb571 | 6818 | if (!insn_data[icode].operand[1].predicate (rtx_op1, mode) |
7ce67fbe DP |
6819 | && mode != VOIDmode) |
6820 | rtx_op1 = force_reg (mode, rtx_op1); | |
6821 | ||
49452c07 | 6822 | rtx_op2 = expand_normal (TREE_OPERAND (vec_cond_expr, 2)); |
e3feb571 | 6823 | if (!insn_data[icode].operand[2].predicate (rtx_op2, mode) |
7ce67fbe DP |
6824 | && mode != VOIDmode) |
6825 | rtx_op2 = force_reg (mode, rtx_op2); | |
6826 | ||
6827 | /* Emit instruction! */ | |
c414ac1d | 6828 | emit_insn (GEN_FCN (icode) (target, rtx_op1, rtx_op2, |
7ce67fbe DP |
6829 | comparison, cc_op0, cc_op1)); |
6830 | ||
6831 | return target; | |
6832 | } | |
48ae6c13 RH |
6833 | |
6834 | \f | |
6835 | /* This is an internal subroutine of the other compare_and_swap expanders. | |
6836 | MEM, OLD_VAL and NEW_VAL are as you'd expect for a compare-and-swap | |
6837 | operation. TARGET is an optional place to store the value result of | |
6838 | the operation. ICODE is the particular instruction to expand. Return | |
6839 | the result of the operation. */ | |
6840 | ||
6841 | static rtx | |
6842 | expand_val_compare_and_swap_1 (rtx mem, rtx old_val, rtx new_val, | |
6843 | rtx target, enum insn_code icode) | |
6844 | { | |
6845 | enum machine_mode mode = GET_MODE (mem); | |
6846 | rtx insn; | |
6847 | ||
6848 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
6849 | target = gen_reg_rtx (mode); | |
6850 | ||
6851 | if (GET_MODE (old_val) != VOIDmode && GET_MODE (old_val) != mode) | |
6852 | old_val = convert_modes (mode, GET_MODE (old_val), old_val, 1); | |
6853 | if (!insn_data[icode].operand[2].predicate (old_val, mode)) | |
6854 | old_val = force_reg (mode, old_val); | |
6855 | ||
6856 | if (GET_MODE (new_val) != VOIDmode && GET_MODE (new_val) != mode) | |
6857 | new_val = convert_modes (mode, GET_MODE (new_val), new_val, 1); | |
6858 | if (!insn_data[icode].operand[3].predicate (new_val, mode)) | |
6859 | new_val = force_reg (mode, new_val); | |
6860 | ||
6861 | insn = GEN_FCN (icode) (target, mem, old_val, new_val); | |
6862 | if (insn == NULL_RTX) | |
6863 | return NULL_RTX; | |
6864 | emit_insn (insn); | |
6865 | ||
6866 | return target; | |
6867 | } | |
6868 | ||
6869 | /* Expand a compare-and-swap operation and return its value. */ | |
6870 | ||
6871 | rtx | |
6872 | expand_val_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6873 | { | |
6874 | enum machine_mode mode = GET_MODE (mem); | |
6875 | enum insn_code icode = sync_compare_and_swap[mode]; | |
6876 | ||
6877 | if (icode == CODE_FOR_nothing) | |
6878 | return NULL_RTX; | |
6879 | ||
6880 | return expand_val_compare_and_swap_1 (mem, old_val, new_val, target, icode); | |
6881 | } | |
6882 | ||
6883 | /* Expand a compare-and-swap operation and store true into the result if | |
6884 | the operation was successful and false otherwise. Return the result. | |
6885 | Unlike other routines, TARGET is not optional. */ | |
6886 | ||
6887 | rtx | |
6888 | expand_bool_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6889 | { | |
6890 | enum machine_mode mode = GET_MODE (mem); | |
6891 | enum insn_code icode; | |
6892 | rtx subtarget, label0, label1; | |
6893 | ||
6894 | /* If the target supports a compare-and-swap pattern that simultaneously | |
6895 | sets some flag for success, then use it. Otherwise use the regular | |
6896 | compare-and-swap and follow that immediately with a compare insn. */ | |
6897 | icode = sync_compare_and_swap_cc[mode]; | |
6898 | switch (icode) | |
6899 | { | |
6900 | default: | |
6901 | subtarget = expand_val_compare_and_swap_1 (mem, old_val, new_val, | |
6902 | NULL_RTX, icode); | |
6903 | if (subtarget != NULL_RTX) | |
6904 | break; | |
6905 | ||
6906 | /* FALLTHRU */ | |
6907 | case CODE_FOR_nothing: | |
6908 | icode = sync_compare_and_swap[mode]; | |
6909 | if (icode == CODE_FOR_nothing) | |
6910 | return NULL_RTX; | |
6911 | ||
f12b785d RH |
6912 | /* Ensure that if old_val == mem, that we're not comparing |
6913 | against an old value. */ | |
2ca202e7 | 6914 | if (MEM_P (old_val)) |
f12b785d RH |
6915 | old_val = force_reg (mode, old_val); |
6916 | ||
48ae6c13 RH |
6917 | subtarget = expand_val_compare_and_swap_1 (mem, old_val, new_val, |
6918 | NULL_RTX, icode); | |
6919 | if (subtarget == NULL_RTX) | |
6920 | return NULL_RTX; | |
6921 | ||
f12b785d | 6922 | emit_cmp_insn (subtarget, old_val, EQ, const0_rtx, mode, true); |
48ae6c13 RH |
6923 | } |
6924 | ||
6925 | /* If the target has a sane STORE_FLAG_VALUE, then go ahead and use a | |
6926 | setcc instruction from the beginning. We don't work too hard here, | |
6927 | but it's nice to not be stupid about initial code gen either. */ | |
6928 | if (STORE_FLAG_VALUE == 1) | |
6929 | { | |
6930 | icode = setcc_gen_code[EQ]; | |
6931 | if (icode != CODE_FOR_nothing) | |
6932 | { | |
6933 | enum machine_mode cmode = insn_data[icode].operand[0].mode; | |
6934 | rtx insn; | |
6935 | ||
6936 | subtarget = target; | |
6937 | if (!insn_data[icode].operand[0].predicate (target, cmode)) | |
6938 | subtarget = gen_reg_rtx (cmode); | |
6939 | ||
6940 | insn = GEN_FCN (icode) (subtarget); | |
6941 | if (insn) | |
6942 | { | |
6943 | emit_insn (insn); | |
6944 | if (GET_MODE (target) != GET_MODE (subtarget)) | |
6945 | { | |
6946 | convert_move (target, subtarget, 1); | |
6947 | subtarget = target; | |
6948 | } | |
6949 | return subtarget; | |
6950 | } | |
6951 | } | |
6952 | } | |
6953 | ||
c414ac1d EC |
6954 | /* Without an appropriate setcc instruction, use a set of branches to |
6955 | get 1 and 0 stored into target. Presumably if the target has a | |
48ae6c13 RH |
6956 | STORE_FLAG_VALUE that isn't 1, then this will get cleaned up by ifcvt. */ |
6957 | ||
6958 | label0 = gen_label_rtx (); | |
6959 | label1 = gen_label_rtx (); | |
6960 | ||
6961 | emit_jump_insn (bcc_gen_fctn[EQ] (label0)); | |
6962 | emit_move_insn (target, const0_rtx); | |
6963 | emit_jump_insn (gen_jump (label1)); | |
d9dfec3f | 6964 | emit_barrier (); |
48ae6c13 RH |
6965 | emit_label (label0); |
6966 | emit_move_insn (target, const1_rtx); | |
6967 | emit_label (label1); | |
6968 | ||
6969 | return target; | |
6970 | } | |
6971 | ||
6972 | /* This is a helper function for the other atomic operations. This function | |
6973 | emits a loop that contains SEQ that iterates until a compare-and-swap | |
6974 | operation at the end succeeds. MEM is the memory to be modified. SEQ is | |
6975 | a set of instructions that takes a value from OLD_REG as an input and | |
6976 | produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be | |
6977 | set to the current contents of MEM. After SEQ, a compare-and-swap will | |
6978 | attempt to update MEM with NEW_REG. The function returns true when the | |
6979 | loop was generated successfully. */ | |
6980 | ||
6981 | static bool | |
6982 | expand_compare_and_swap_loop (rtx mem, rtx old_reg, rtx new_reg, rtx seq) | |
6983 | { | |
6984 | enum machine_mode mode = GET_MODE (mem); | |
6985 | enum insn_code icode; | |
81ba4f39 | 6986 | rtx label, cmp_reg, subtarget; |
48ae6c13 RH |
6987 | |
6988 | /* The loop we want to generate looks like | |
6989 | ||
81ba4f39 | 6990 | cmp_reg = mem; |
48ae6c13 | 6991 | label: |
81ba4f39 | 6992 | old_reg = cmp_reg; |
48ae6c13 | 6993 | seq; |
81ba4f39 RH |
6994 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) |
6995 | if (cmp_reg != old_reg) | |
48ae6c13 RH |
6996 | goto label; |
6997 | ||
6998 | Note that we only do the plain load from memory once. Subsequent | |
6999 | iterations use the value loaded by the compare-and-swap pattern. */ | |
7000 | ||
7001 | label = gen_label_rtx (); | |
81ba4f39 | 7002 | cmp_reg = gen_reg_rtx (mode); |
48ae6c13 | 7003 | |
81ba4f39 | 7004 | emit_move_insn (cmp_reg, mem); |
48ae6c13 | 7005 | emit_label (label); |
81ba4f39 | 7006 | emit_move_insn (old_reg, cmp_reg); |
48ae6c13 RH |
7007 | if (seq) |
7008 | emit_insn (seq); | |
7009 | ||
7010 | /* If the target supports a compare-and-swap pattern that simultaneously | |
7011 | sets some flag for success, then use it. Otherwise use the regular | |
7012 | compare-and-swap and follow that immediately with a compare insn. */ | |
7013 | icode = sync_compare_and_swap_cc[mode]; | |
7014 | switch (icode) | |
7015 | { | |
7016 | default: | |
7017 | subtarget = expand_val_compare_and_swap_1 (mem, old_reg, new_reg, | |
81ba4f39 | 7018 | cmp_reg, icode); |
48ae6c13 | 7019 | if (subtarget != NULL_RTX) |
81ba4f39 RH |
7020 | { |
7021 | gcc_assert (subtarget == cmp_reg); | |
7022 | break; | |
7023 | } | |
48ae6c13 RH |
7024 | |
7025 | /* FALLTHRU */ | |
7026 | case CODE_FOR_nothing: | |
7027 | icode = sync_compare_and_swap[mode]; | |
7028 | if (icode == CODE_FOR_nothing) | |
7029 | return false; | |
7030 | ||
7031 | subtarget = expand_val_compare_and_swap_1 (mem, old_reg, new_reg, | |
81ba4f39 | 7032 | cmp_reg, icode); |
48ae6c13 RH |
7033 | if (subtarget == NULL_RTX) |
7034 | return false; | |
81ba4f39 RH |
7035 | if (subtarget != cmp_reg) |
7036 | emit_move_insn (cmp_reg, subtarget); | |
48ae6c13 | 7037 | |
81ba4f39 | 7038 | emit_cmp_insn (cmp_reg, old_reg, EQ, const0_rtx, mode, true); |
48ae6c13 RH |
7039 | } |
7040 | ||
7041 | /* ??? Mark this jump predicted not taken? */ | |
7042 | emit_jump_insn (bcc_gen_fctn[NE] (label)); | |
7043 | ||
7044 | return true; | |
7045 | } | |
7046 | ||
7047 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
c414ac1d | 7048 | case, we do not care about any resulting value. Returns NULL if we |
48ae6c13 RH |
7049 | cannot generate the operation. */ |
7050 | ||
7051 | rtx | |
7052 | expand_sync_operation (rtx mem, rtx val, enum rtx_code code) | |
7053 | { | |
7054 | enum machine_mode mode = GET_MODE (mem); | |
7055 | enum insn_code icode; | |
7056 | rtx insn; | |
7057 | ||
7058 | /* Look to see if the target supports the operation directly. */ | |
7059 | switch (code) | |
7060 | { | |
7061 | case PLUS: | |
7062 | icode = sync_add_optab[mode]; | |
7063 | break; | |
7064 | case IOR: | |
7065 | icode = sync_ior_optab[mode]; | |
7066 | break; | |
7067 | case XOR: | |
7068 | icode = sync_xor_optab[mode]; | |
7069 | break; | |
7070 | case AND: | |
7071 | icode = sync_and_optab[mode]; | |
7072 | break; | |
f12b785d RH |
7073 | case NOT: |
7074 | icode = sync_nand_optab[mode]; | |
7075 | break; | |
48ae6c13 RH |
7076 | |
7077 | case MINUS: | |
7078 | icode = sync_sub_optab[mode]; | |
3b010fe3 | 7079 | if (icode == CODE_FOR_nothing || CONST_INT_P (val)) |
48ae6c13 RH |
7080 | { |
7081 | icode = sync_add_optab[mode]; | |
7082 | if (icode != CODE_FOR_nothing) | |
7083 | { | |
7084 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
7085 | code = PLUS; | |
7086 | } | |
7087 | } | |
7088 | break; | |
7089 | ||
48ae6c13 RH |
7090 | default: |
7091 | gcc_unreachable (); | |
7092 | } | |
7093 | ||
7094 | /* Generate the direct operation, if present. */ | |
7095 | if (icode != CODE_FOR_nothing) | |
7096 | { | |
7097 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7098 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7099 | if (!insn_data[icode].operand[1].predicate (val, mode)) | |
7100 | val = force_reg (mode, val); | |
c414ac1d | 7101 | |
48ae6c13 RH |
7102 | insn = GEN_FCN (icode) (mem, val); |
7103 | if (insn) | |
7104 | { | |
7105 | emit_insn (insn); | |
7106 | return const0_rtx; | |
7107 | } | |
7108 | } | |
7109 | ||
7110 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
7111 | operation with normal arithmetic instructions. */ | |
7112 | if (sync_compare_and_swap[mode] != CODE_FOR_nothing) | |
7113 | { | |
7114 | rtx t0 = gen_reg_rtx (mode), t1; | |
7115 | ||
7116 | start_sequence (); | |
7117 | ||
f12b785d | 7118 | t1 = t0; |
48ae6c13 RH |
7119 | if (code == NOT) |
7120 | { | |
f12b785d | 7121 | t1 = expand_simple_unop (mode, NOT, t1, NULL_RTX, true); |
48ae6c13 RH |
7122 | code = AND; |
7123 | } | |
f12b785d | 7124 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, |
48ae6c13 RH |
7125 | true, OPTAB_LIB_WIDEN); |
7126 | ||
7127 | insn = get_insns (); | |
7128 | end_sequence (); | |
7129 | ||
7130 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
7131 | return const0_rtx; | |
7132 | } | |
7133 | ||
7134 | return NULL_RTX; | |
7135 | } | |
7136 | ||
7137 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
7138 | case, we do care about the resulting value: if AFTER is true then | |
c414ac1d | 7139 | return the value MEM holds after the operation, if AFTER is false |
48ae6c13 RH |
7140 | then return the value MEM holds before the operation. TARGET is an |
7141 | optional place for the result value to be stored. */ | |
7142 | ||
7143 | rtx | |
7144 | expand_sync_fetch_operation (rtx mem, rtx val, enum rtx_code code, | |
7145 | bool after, rtx target) | |
7146 | { | |
7147 | enum machine_mode mode = GET_MODE (mem); | |
7148 | enum insn_code old_code, new_code, icode; | |
7149 | bool compensate; | |
7150 | rtx insn; | |
7151 | ||
7152 | /* Look to see if the target supports the operation directly. */ | |
7153 | switch (code) | |
7154 | { | |
7155 | case PLUS: | |
7156 | old_code = sync_old_add_optab[mode]; | |
7157 | new_code = sync_new_add_optab[mode]; | |
7158 | break; | |
7159 | case IOR: | |
7160 | old_code = sync_old_ior_optab[mode]; | |
7161 | new_code = sync_new_ior_optab[mode]; | |
7162 | break; | |
7163 | case XOR: | |
7164 | old_code = sync_old_xor_optab[mode]; | |
7165 | new_code = sync_new_xor_optab[mode]; | |
7166 | break; | |
7167 | case AND: | |
7168 | old_code = sync_old_and_optab[mode]; | |
7169 | new_code = sync_new_and_optab[mode]; | |
7170 | break; | |
f12b785d RH |
7171 | case NOT: |
7172 | old_code = sync_old_nand_optab[mode]; | |
7173 | new_code = sync_new_nand_optab[mode]; | |
7174 | break; | |
48ae6c13 RH |
7175 | |
7176 | case MINUS: | |
7177 | old_code = sync_old_sub_optab[mode]; | |
7178 | new_code = sync_new_sub_optab[mode]; | |
3b010fe3 DD |
7179 | if ((old_code == CODE_FOR_nothing && new_code == CODE_FOR_nothing) |
7180 | || CONST_INT_P (val)) | |
48ae6c13 RH |
7181 | { |
7182 | old_code = sync_old_add_optab[mode]; | |
7183 | new_code = sync_new_add_optab[mode]; | |
7184 | if (old_code != CODE_FOR_nothing || new_code != CODE_FOR_nothing) | |
7185 | { | |
7186 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
7187 | code = PLUS; | |
7188 | } | |
7189 | } | |
7190 | break; | |
7191 | ||
48ae6c13 RH |
7192 | default: |
7193 | gcc_unreachable (); | |
7194 | } | |
7195 | ||
7196 | /* If the target does supports the proper new/old operation, great. But | |
7197 | if we only support the opposite old/new operation, check to see if we | |
7198 | can compensate. In the case in which the old value is supported, then | |
7199 | we can always perform the operation again with normal arithmetic. In | |
7200 | the case in which the new value is supported, then we can only handle | |
7201 | this in the case the operation is reversible. */ | |
7202 | compensate = false; | |
7203 | if (after) | |
7204 | { | |
7205 | icode = new_code; | |
7206 | if (icode == CODE_FOR_nothing) | |
7207 | { | |
7208 | icode = old_code; | |
7209 | if (icode != CODE_FOR_nothing) | |
7210 | compensate = true; | |
7211 | } | |
7212 | } | |
7213 | else | |
7214 | { | |
7215 | icode = old_code; | |
7216 | if (icode == CODE_FOR_nothing | |
7217 | && (code == PLUS || code == MINUS || code == XOR)) | |
7218 | { | |
7219 | icode = new_code; | |
7220 | if (icode != CODE_FOR_nothing) | |
7221 | compensate = true; | |
7222 | } | |
7223 | } | |
7224 | ||
7225 | /* If we found something supported, great. */ | |
7226 | if (icode != CODE_FOR_nothing) | |
7227 | { | |
7228 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
7229 | target = gen_reg_rtx (mode); | |
7230 | ||
7231 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7232 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7233 | if (!insn_data[icode].operand[2].predicate (val, mode)) | |
7234 | val = force_reg (mode, val); | |
c414ac1d | 7235 | |
48ae6c13 RH |
7236 | insn = GEN_FCN (icode) (target, mem, val); |
7237 | if (insn) | |
7238 | { | |
7239 | emit_insn (insn); | |
7240 | ||
7241 | /* If we need to compensate for using an operation with the | |
7242 | wrong return value, do so now. */ | |
7243 | if (compensate) | |
7244 | { | |
7245 | if (!after) | |
7246 | { | |
7247 | if (code == PLUS) | |
7248 | code = MINUS; | |
7249 | else if (code == MINUS) | |
7250 | code = PLUS; | |
7251 | } | |
f12b785d RH |
7252 | |
7253 | if (code == NOT) | |
7254 | target = expand_simple_unop (mode, NOT, target, NULL_RTX, true); | |
48ae6c13 RH |
7255 | target = expand_simple_binop (mode, code, target, val, NULL_RTX, |
7256 | true, OPTAB_LIB_WIDEN); | |
7257 | } | |
7258 | ||
7259 | return target; | |
7260 | } | |
7261 | } | |
7262 | ||
7263 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
7264 | operation with normal arithmetic instructions. */ | |
7265 | if (sync_compare_and_swap[mode] != CODE_FOR_nothing) | |
7266 | { | |
7267 | rtx t0 = gen_reg_rtx (mode), t1; | |
7268 | ||
7269 | if (!target || !register_operand (target, mode)) | |
7270 | target = gen_reg_rtx (mode); | |
7271 | ||
7272 | start_sequence (); | |
7273 | ||
f12b785d RH |
7274 | if (!after) |
7275 | emit_move_insn (target, t0); | |
7276 | t1 = t0; | |
48ae6c13 RH |
7277 | if (code == NOT) |
7278 | { | |
f12b785d | 7279 | t1 = expand_simple_unop (mode, NOT, t1, NULL_RTX, true); |
48ae6c13 RH |
7280 | code = AND; |
7281 | } | |
f12b785d | 7282 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, |
48ae6c13 RH |
7283 | true, OPTAB_LIB_WIDEN); |
7284 | if (after) | |
7285 | emit_move_insn (target, t1); | |
7286 | ||
7287 | insn = get_insns (); | |
7288 | end_sequence (); | |
7289 | ||
7290 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
7291 | return target; | |
7292 | } | |
7293 | ||
7294 | return NULL_RTX; | |
7295 | } | |
7296 | ||
7297 | /* This function expands a test-and-set operation. Ideally we atomically | |
7298 | store VAL in MEM and return the previous value in MEM. Some targets | |
7299 | may not support this operation and only support VAL with the constant 1; | |
c414ac1d | 7300 | in this case while the return value will be 0/1, but the exact value |
48ae6c13 RH |
7301 | stored in MEM is target defined. TARGET is an option place to stick |
7302 | the return value. */ | |
7303 | ||
7304 | rtx | |
7305 | expand_sync_lock_test_and_set (rtx mem, rtx val, rtx target) | |
7306 | { | |
7307 | enum machine_mode mode = GET_MODE (mem); | |
7308 | enum insn_code icode; | |
7309 | rtx insn; | |
7310 | ||
7311 | /* If the target supports the test-and-set directly, great. */ | |
7312 | icode = sync_lock_test_and_set[mode]; | |
7313 | if (icode != CODE_FOR_nothing) | |
7314 | { | |
7315 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
7316 | target = gen_reg_rtx (mode); | |
7317 | ||
7318 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7319 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7320 | if (!insn_data[icode].operand[2].predicate (val, mode)) | |
7321 | val = force_reg (mode, val); | |
7322 | ||
7323 | insn = GEN_FCN (icode) (target, mem, val); | |
7324 | if (insn) | |
7325 | { | |
7326 | emit_insn (insn); | |
7327 | return target; | |
7328 | } | |
7329 | } | |
7330 | ||
7331 | /* Otherwise, use a compare-and-swap loop for the exchange. */ | |
7332 | if (sync_compare_and_swap[mode] != CODE_FOR_nothing) | |
7333 | { | |
7334 | if (!target || !register_operand (target, mode)) | |
7335 | target = gen_reg_rtx (mode); | |
7336 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7337 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7338 | if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX)) | |
7339 | return target; | |
7340 | } | |
7341 | ||
7342 | return NULL_RTX; | |
7343 | } | |
7344 | ||
e2500fed | 7345 | #include "gt-optabs.h" |