]>
Commit | Line | Data |
---|---|---|
77c9c6c2 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
d9221e01 | 3 | 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
77c9c6c2 | 4 | |
1322177d | 5 | This file is part of GCC. |
77c9c6c2 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
77c9c6c2 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
77c9c6c2 RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
77c9c6c2 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
01198c2f | 27 | #include "toplev.h" |
dff01034 KG |
28 | |
29 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
dc297297 | 30 | is properly defined. */ |
dff01034 | 31 | #include "insn-config.h" |
77c9c6c2 RK |
32 | #include "rtl.h" |
33 | #include "tree.h" | |
6baf1cc8 | 34 | #include "tm_p.h" |
77c9c6c2 | 35 | #include "flags.h" |
49ad7cfa | 36 | #include "function.h" |
52a11cbf | 37 | #include "except.h" |
77c9c6c2 | 38 | #include "expr.h" |
e78d8e51 ZW |
39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
77c9c6c2 | 41 | #include "recog.h" |
2829c155 | 42 | #include "reload.h" |
87ff9c8e | 43 | #include "ggc.h" |
7bdb32b9 | 44 | #include "real.h" |
4a69cf79 | 45 | #include "basic-block.h" |
c15c90bb | 46 | #include "target.h" |
77c9c6c2 RK |
47 | |
48 | /* Each optab contains info on how this target machine | |
49 | can perform a particular operation | |
50 | for all sizes and kinds of operands. | |
51 | ||
52 | The operation to be performed is often specified | |
53 | by passing one of these optabs as an argument. | |
54 | ||
55 | See expr.h for documentation of these optabs. */ | |
56 | ||
34220a12 BS |
57 | optab optab_table[OTI_MAX]; |
58 | ||
59 | rtx libfunc_table[LTI_MAX]; | |
19c3fc24 | 60 | |
85363ca0 ZW |
61 | /* Tables of patterns for converting one mode to another. */ |
62 | convert_optab convert_optab_table[CTI_MAX]; | |
5d81dc5b | 63 | |
377017c4 RK |
64 | /* Contains the optab used for each rtx code. */ |
65 | optab code_to_optab[NUM_RTX_CODE + 1]; | |
66 | ||
77c9c6c2 RK |
67 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) |
68 | gives the gen_function to make a branch to test that condition. */ | |
69 | ||
70 | rtxfun bcc_gen_fctn[NUM_RTX_CODE]; | |
71 | ||
72 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) | |
73 | gives the insn code to make a store-condition insn | |
74 | to test that condition. */ | |
75 | ||
76 | enum insn_code setcc_gen_code[NUM_RTX_CODE]; | |
77 | ||
49c4584c DE |
78 | #ifdef HAVE_conditional_move |
79 | /* Indexed by the machine mode, gives the insn code to make a conditional | |
80 | move insn. This is not indexed by the rtx-code like bcc_gen_fctn and | |
81 | setcc_gen_code to cut down on the number of named patterns. Consider a day | |
82 | when a lot more rtx codes are conditional (eg: for the ARM). */ | |
83 | ||
84 | enum insn_code movcc_gen_code[NUM_MACHINE_MODES]; | |
85 | #endif | |
86 | ||
842a431a DM |
87 | /* The insn generating function can not take an rtx_code argument. |
88 | TRAP_RTX is used as an rtx argument. Its code is replaced with | |
89 | the code to be used in the trap insn and all other fields are ignored. */ | |
90 | static GTY(()) rtx trap_rtx; | |
91 | ||
0c20a65f AJ |
92 | static int add_equal_note (rtx, rtx, enum rtx_code, rtx, rtx); |
93 | static rtx widen_operand (rtx, enum machine_mode, enum machine_mode, int, | |
94 | int); | |
95 | static int expand_cmplxdiv_straight (rtx, rtx, rtx, rtx, rtx, rtx, | |
96 | enum machine_mode, int, | |
97 | enum optab_methods, enum mode_class, | |
98 | optab); | |
99 | static int expand_cmplxdiv_wide (rtx, rtx, rtx, rtx, rtx, rtx, | |
100 | enum machine_mode, int, enum optab_methods, | |
101 | enum mode_class, optab); | |
102 | static void prepare_cmp_insn (rtx *, rtx *, enum rtx_code *, rtx, | |
103 | enum machine_mode *, int *, | |
104 | enum can_compare_purpose); | |
105 | static enum insn_code can_fix_p (enum machine_mode, enum machine_mode, int, | |
106 | int *); | |
107 | static enum insn_code can_float_p (enum machine_mode, enum machine_mode, int); | |
0c20a65f | 108 | static optab new_optab (void); |
85363ca0 | 109 | static convert_optab new_convert_optab (void); |
0c20a65f AJ |
110 | static inline optab init_optab (enum rtx_code); |
111 | static inline optab init_optabv (enum rtx_code); | |
85363ca0 | 112 | static inline convert_optab init_convert_optab (enum rtx_code); |
0c20a65f AJ |
113 | static void init_libfuncs (optab, int, int, const char *, int); |
114 | static void init_integral_libfuncs (optab, const char *, int); | |
115 | static void init_floating_libfuncs (optab, const char *, int); | |
85363ca0 ZW |
116 | static void init_interclass_conv_libfuncs (convert_optab, const char *, |
117 | enum mode_class, enum mode_class); | |
118 | static void init_intraclass_conv_libfuncs (convert_optab, const char *, | |
119 | enum mode_class, bool); | |
0c20a65f AJ |
120 | static void emit_cmp_and_jump_insn_1 (rtx, rtx, enum machine_mode, |
121 | enum rtx_code, int, rtx); | |
122 | static void prepare_float_lib_cmp (rtx *, rtx *, enum rtx_code *, | |
123 | enum machine_mode *, int *); | |
124 | static rtx expand_vector_binop (enum machine_mode, optab, rtx, rtx, rtx, int, | |
125 | enum optab_methods); | |
126 | static rtx expand_vector_unop (enum machine_mode, optab, rtx, rtx, int); | |
127 | static rtx widen_clz (enum machine_mode, rtx, rtx); | |
128 | static rtx expand_parity (enum machine_mode, rtx, rtx); | |
842a431a DM |
129 | |
130 | #ifndef HAVE_conditional_trap | |
131 | #define HAVE_conditional_trap 0 | |
132 | #define gen_conditional_trap(a,b) (abort (), NULL_RTX) | |
133 | #endif | |
77c9c6c2 | 134 | \f |
2f937369 | 135 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
77c9c6c2 RK |
136 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
137 | operation). | |
138 | ||
139 | If the last insn does not set TARGET, don't do anything, but return 1. | |
140 | ||
141 | If a previous insn sets TARGET and TARGET is one of OP0 or OP1, | |
142 | don't add the REG_EQUAL note but return 0. Our caller can then try | |
143 | again, ensuring that TARGET is not one of the operands. */ | |
144 | ||
145 | static int | |
0c20a65f | 146 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
77c9c6c2 | 147 | { |
2f937369 | 148 | rtx last_insn, insn, set; |
77c9c6c2 RK |
149 | rtx note; |
150 | ||
2f937369 DM |
151 | if (! insns |
152 | || ! INSN_P (insns) | |
153 | || NEXT_INSN (insns) == NULL_RTX) | |
154 | abort (); | |
155 | ||
ec8e098d PB |
156 | if (GET_RTX_CLASS (code) != RTX_COMM_ARITH |
157 | && GET_RTX_CLASS (code) != RTX_BIN_ARITH | |
158 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE | |
159 | && GET_RTX_CLASS (code) != RTX_COMPARE | |
160 | && GET_RTX_CLASS (code) != RTX_UNARY) | |
2f937369 DM |
161 | return 1; |
162 | ||
163 | if (GET_CODE (target) == ZERO_EXTRACT) | |
164 | return 1; | |
165 | ||
166 | for (last_insn = insns; | |
167 | NEXT_INSN (last_insn) != NULL_RTX; | |
168 | last_insn = NEXT_INSN (last_insn)) | |
169 | ; | |
170 | ||
171 | set = single_set (last_insn); | |
172 | if (set == NULL_RTX) | |
173 | return 1; | |
174 | ||
175 | if (! rtx_equal_p (SET_DEST (set), target) | |
f9d36a92 | 176 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
2f937369 | 177 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
f9d36a92 | 178 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
77c9c6c2 RK |
179 | return 1; |
180 | ||
181 | /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET | |
182 | besides the last insn. */ | |
183 | if (reg_overlap_mentioned_p (target, op0) | |
184 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
2f937369 DM |
185 | { |
186 | insn = PREV_INSN (last_insn); | |
187 | while (insn != NULL_RTX) | |
188 | { | |
189 | if (reg_set_p (target, insn)) | |
190 | return 0; | |
191 | ||
192 | insn = PREV_INSN (insn); | |
193 | } | |
194 | } | |
77c9c6c2 | 195 | |
ec8e098d | 196 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
9e6a5703 | 197 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); |
77c9c6c2 | 198 | else |
9e6a5703 | 199 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
77c9c6c2 | 200 | |
2f937369 | 201 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
77c9c6c2 RK |
202 | |
203 | return 1; | |
204 | } | |
205 | \f | |
835532b8 RK |
206 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
207 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
0c20a65f | 208 | not actually do a sign-extend or zero-extend, but can leave the |
835532b8 RK |
209 | higher-order bits of the result rtx undefined, for example, in the case |
210 | of logical operations, but not right shifts. */ | |
211 | ||
212 | static rtx | |
0c20a65f AJ |
213 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
214 | int unsignedp, int no_extend) | |
835532b8 RK |
215 | { |
216 | rtx result; | |
217 | ||
8041889f RK |
218 | /* If we don't have to extend and this is a constant, return it. */ |
219 | if (no_extend && GET_MODE (op) == VOIDmode) | |
220 | return op; | |
221 | ||
222 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
223 | extend since it will be more efficient to do so unless the signedness of | |
224 | a promoted object differs from our extension. */ | |
835532b8 | 225 | if (! no_extend |
cb8f73be RK |
226 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
227 | && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp)) | |
0661a3de | 228 | return convert_modes (mode, oldmode, op, unsignedp); |
835532b8 RK |
229 | |
230 | /* If MODE is no wider than a single word, we return a paradoxical | |
231 | SUBREG. */ | |
232 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
9e6a5703 | 233 | return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0); |
835532b8 RK |
234 | |
235 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
236 | part to OP. */ | |
237 | ||
238 | result = gen_reg_rtx (mode); | |
9e6a5703 | 239 | emit_insn (gen_rtx_CLOBBER (VOIDmode, result)); |
835532b8 RK |
240 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
241 | return result; | |
242 | } | |
243 | \f | |
c64f913e CB |
244 | /* Generate code to perform a straightforward complex divide. */ |
245 | ||
246 | static int | |
0c20a65f AJ |
247 | expand_cmplxdiv_straight (rtx real0, rtx real1, rtx imag0, rtx imag1, |
248 | rtx realr, rtx imagr, enum machine_mode submode, | |
249 | int unsignedp, enum optab_methods methods, | |
250 | enum mode_class class, optab binoptab) | |
c64f913e CB |
251 | { |
252 | rtx divisor; | |
253 | rtx real_t, imag_t; | |
254 | rtx temp1, temp2; | |
255 | rtx res; | |
91ce572a CC |
256 | optab this_add_optab = add_optab; |
257 | optab this_sub_optab = sub_optab; | |
258 | optab this_neg_optab = neg_optab; | |
259 | optab this_mul_optab = smul_optab; | |
0c20a65f | 260 | |
91ce572a CC |
261 | if (binoptab == sdivv_optab) |
262 | { | |
263 | this_add_optab = addv_optab; | |
264 | this_sub_optab = subv_optab; | |
265 | this_neg_optab = negv_optab; | |
266 | this_mul_optab = smulv_optab; | |
267 | } | |
268 | ||
c64f913e CB |
269 | /* Don't fetch these from memory more than once. */ |
270 | real0 = force_reg (submode, real0); | |
271 | real1 = force_reg (submode, real1); | |
272 | ||
273 | if (imag0 != 0) | |
274 | imag0 = force_reg (submode, imag0); | |
275 | ||
276 | imag1 = force_reg (submode, imag1); | |
277 | ||
278 | /* Divisor: c*c + d*d. */ | |
91ce572a | 279 | temp1 = expand_binop (submode, this_mul_optab, real1, real1, |
c64f913e CB |
280 | NULL_RTX, unsignedp, methods); |
281 | ||
91ce572a | 282 | temp2 = expand_binop (submode, this_mul_optab, imag1, imag1, |
c64f913e CB |
283 | NULL_RTX, unsignedp, methods); |
284 | ||
285 | if (temp1 == 0 || temp2 == 0) | |
286 | return 0; | |
287 | ||
91ce572a | 288 | divisor = expand_binop (submode, this_add_optab, temp1, temp2, |
c64f913e CB |
289 | NULL_RTX, unsignedp, methods); |
290 | if (divisor == 0) | |
291 | return 0; | |
292 | ||
086bbd21 | 293 | if (imag0 == 0) |
c64f913e CB |
294 | { |
295 | /* Mathematically, ((a)(c-id))/divisor. */ | |
296 | /* Computationally, (a+i0) / (c+id) = (ac/(cc+dd)) + i(-ad/(cc+dd)). */ | |
297 | ||
298 | /* Calculate the dividend. */ | |
91ce572a | 299 | real_t = expand_binop (submode, this_mul_optab, real0, real1, |
c64f913e | 300 | NULL_RTX, unsignedp, methods); |
0c20a65f | 301 | |
91ce572a | 302 | imag_t = expand_binop (submode, this_mul_optab, real0, imag1, |
c64f913e CB |
303 | NULL_RTX, unsignedp, methods); |
304 | ||
305 | if (real_t == 0 || imag_t == 0) | |
306 | return 0; | |
307 | ||
91ce572a | 308 | imag_t = expand_unop (submode, this_neg_optab, imag_t, |
c64f913e CB |
309 | NULL_RTX, unsignedp); |
310 | } | |
311 | else | |
312 | { | |
313 | /* Mathematically, ((a+ib)(c-id))/divider. */ | |
314 | /* Calculate the dividend. */ | |
91ce572a | 315 | temp1 = expand_binop (submode, this_mul_optab, real0, real1, |
c64f913e CB |
316 | NULL_RTX, unsignedp, methods); |
317 | ||
91ce572a | 318 | temp2 = expand_binop (submode, this_mul_optab, imag0, imag1, |
c64f913e CB |
319 | NULL_RTX, unsignedp, methods); |
320 | ||
321 | if (temp1 == 0 || temp2 == 0) | |
322 | return 0; | |
323 | ||
91ce572a | 324 | real_t = expand_binop (submode, this_add_optab, temp1, temp2, |
c64f913e | 325 | NULL_RTX, unsignedp, methods); |
0c20a65f | 326 | |
91ce572a | 327 | temp1 = expand_binop (submode, this_mul_optab, imag0, real1, |
c64f913e CB |
328 | NULL_RTX, unsignedp, methods); |
329 | ||
91ce572a | 330 | temp2 = expand_binop (submode, this_mul_optab, real0, imag1, |
c64f913e CB |
331 | NULL_RTX, unsignedp, methods); |
332 | ||
333 | if (temp1 == 0 || temp2 == 0) | |
334 | return 0; | |
335 | ||
91ce572a | 336 | imag_t = expand_binop (submode, this_sub_optab, temp1, temp2, |
c64f913e CB |
337 | NULL_RTX, unsignedp, methods); |
338 | ||
339 | if (real_t == 0 || imag_t == 0) | |
340 | return 0; | |
341 | } | |
342 | ||
343 | if (class == MODE_COMPLEX_FLOAT) | |
344 | res = expand_binop (submode, binoptab, real_t, divisor, | |
345 | realr, unsignedp, methods); | |
346 | else | |
347 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
348 | real_t, divisor, realr, unsignedp); | |
349 | ||
350 | if (res == 0) | |
351 | return 0; | |
352 | ||
353 | if (res != realr) | |
354 | emit_move_insn (realr, res); | |
355 | ||
356 | if (class == MODE_COMPLEX_FLOAT) | |
357 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
358 | imagr, unsignedp, methods); | |
359 | else | |
360 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
361 | imag_t, divisor, imagr, unsignedp); | |
362 | ||
363 | if (res == 0) | |
364 | return 0; | |
365 | ||
366 | if (res != imagr) | |
367 | emit_move_insn (imagr, res); | |
368 | ||
369 | return 1; | |
370 | } | |
371 | \f | |
372 | /* Generate code to perform a wide-input-range-acceptable complex divide. */ | |
373 | ||
374 | static int | |
0c20a65f AJ |
375 | expand_cmplxdiv_wide (rtx real0, rtx real1, rtx imag0, rtx imag1, rtx realr, |
376 | rtx imagr, enum machine_mode submode, int unsignedp, | |
377 | enum optab_methods methods, enum mode_class class, | |
378 | optab binoptab) | |
c64f913e CB |
379 | { |
380 | rtx ratio, divisor; | |
381 | rtx real_t, imag_t; | |
382 | rtx temp1, temp2, lab1, lab2; | |
383 | enum machine_mode mode; | |
c64f913e | 384 | rtx res; |
91ce572a CC |
385 | optab this_add_optab = add_optab; |
386 | optab this_sub_optab = sub_optab; | |
387 | optab this_neg_optab = neg_optab; | |
388 | optab this_mul_optab = smul_optab; | |
389 | ||
390 | if (binoptab == sdivv_optab) | |
391 | { | |
392 | this_add_optab = addv_optab; | |
393 | this_sub_optab = subv_optab; | |
394 | this_neg_optab = negv_optab; | |
395 | this_mul_optab = smulv_optab; | |
396 | } | |
0c20a65f | 397 | |
c64f913e CB |
398 | /* Don't fetch these from memory more than once. */ |
399 | real0 = force_reg (submode, real0); | |
400 | real1 = force_reg (submode, real1); | |
401 | ||
402 | if (imag0 != 0) | |
403 | imag0 = force_reg (submode, imag0); | |
404 | ||
405 | imag1 = force_reg (submode, imag1); | |
406 | ||
a59a536c RE |
407 | /* XXX What's an "unsigned" complex number? */ |
408 | if (unsignedp) | |
409 | { | |
410 | temp1 = real1; | |
411 | temp2 = imag1; | |
412 | } | |
413 | else | |
414 | { | |
91ce572a CC |
415 | temp1 = expand_abs (submode, real1, NULL_RTX, unsignedp, 1); |
416 | temp2 = expand_abs (submode, imag1, NULL_RTX, unsignedp, 1); | |
a59a536c | 417 | } |
c64f913e CB |
418 | |
419 | if (temp1 == 0 || temp2 == 0) | |
420 | return 0; | |
421 | ||
422 | mode = GET_MODE (temp1); | |
c64f913e CB |
423 | lab1 = gen_label_rtx (); |
424 | emit_cmp_and_jump_insns (temp1, temp2, LT, NULL_RTX, | |
a06ef755 | 425 | mode, unsignedp, lab1); |
c64f913e CB |
426 | |
427 | /* |c| >= |d|; use ratio d/c to scale dividend and divisor. */ | |
428 | ||
429 | if (class == MODE_COMPLEX_FLOAT) | |
430 | ratio = expand_binop (submode, binoptab, imag1, real1, | |
431 | NULL_RTX, unsignedp, methods); | |
432 | else | |
433 | ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
434 | imag1, real1, NULL_RTX, unsignedp); | |
435 | ||
436 | if (ratio == 0) | |
437 | return 0; | |
438 | ||
439 | /* Calculate divisor. */ | |
440 | ||
91ce572a | 441 | temp1 = expand_binop (submode, this_mul_optab, imag1, ratio, |
c64f913e CB |
442 | NULL_RTX, unsignedp, methods); |
443 | ||
444 | if (temp1 == 0) | |
445 | return 0; | |
446 | ||
91ce572a | 447 | divisor = expand_binop (submode, this_add_optab, temp1, real1, |
c64f913e CB |
448 | NULL_RTX, unsignedp, methods); |
449 | ||
450 | if (divisor == 0) | |
451 | return 0; | |
452 | ||
453 | /* Calculate dividend. */ | |
454 | ||
086bbd21 | 455 | if (imag0 == 0) |
c64f913e CB |
456 | { |
457 | real_t = real0; | |
458 | ||
459 | /* Compute a / (c+id) as a / (c+d(d/c)) + i (-a(d/c)) / (c+d(d/c)). */ | |
460 | ||
91ce572a | 461 | imag_t = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
462 | NULL_RTX, unsignedp, methods); |
463 | ||
464 | if (imag_t == 0) | |
465 | return 0; | |
466 | ||
91ce572a | 467 | imag_t = expand_unop (submode, this_neg_optab, imag_t, |
c64f913e CB |
468 | NULL_RTX, unsignedp); |
469 | ||
470 | if (real_t == 0 || imag_t == 0) | |
471 | return 0; | |
472 | } | |
473 | else | |
474 | { | |
475 | /* Compute (a+ib)/(c+id) as | |
476 | (a+b(d/c))/(c+d(d/c) + i(b-a(d/c))/(c+d(d/c)). */ | |
477 | ||
91ce572a | 478 | temp1 = expand_binop (submode, this_mul_optab, imag0, ratio, |
c64f913e CB |
479 | NULL_RTX, unsignedp, methods); |
480 | ||
481 | if (temp1 == 0) | |
482 | return 0; | |
483 | ||
91ce572a | 484 | real_t = expand_binop (submode, this_add_optab, temp1, real0, |
c64f913e CB |
485 | NULL_RTX, unsignedp, methods); |
486 | ||
91ce572a | 487 | temp1 = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
488 | NULL_RTX, unsignedp, methods); |
489 | ||
490 | if (temp1 == 0) | |
491 | return 0; | |
492 | ||
91ce572a | 493 | imag_t = expand_binop (submode, this_sub_optab, imag0, temp1, |
c64f913e CB |
494 | NULL_RTX, unsignedp, methods); |
495 | ||
496 | if (real_t == 0 || imag_t == 0) | |
497 | return 0; | |
498 | } | |
499 | ||
500 | if (class == MODE_COMPLEX_FLOAT) | |
501 | res = expand_binop (submode, binoptab, real_t, divisor, | |
502 | realr, unsignedp, methods); | |
503 | else | |
504 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
505 | real_t, divisor, realr, unsignedp); | |
506 | ||
507 | if (res == 0) | |
508 | return 0; | |
509 | ||
510 | if (res != realr) | |
511 | emit_move_insn (realr, res); | |
512 | ||
513 | if (class == MODE_COMPLEX_FLOAT) | |
514 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
515 | imagr, unsignedp, methods); | |
516 | else | |
517 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
518 | imag_t, divisor, imagr, unsignedp); | |
519 | ||
520 | if (res == 0) | |
521 | return 0; | |
522 | ||
523 | if (res != imagr) | |
524 | emit_move_insn (imagr, res); | |
525 | ||
526 | lab2 = gen_label_rtx (); | |
527 | emit_jump_insn (gen_jump (lab2)); | |
528 | emit_barrier (); | |
529 | ||
530 | emit_label (lab1); | |
531 | ||
532 | /* |d| > |c|; use ratio c/d to scale dividend and divisor. */ | |
533 | ||
534 | if (class == MODE_COMPLEX_FLOAT) | |
535 | ratio = expand_binop (submode, binoptab, real1, imag1, | |
536 | NULL_RTX, unsignedp, methods); | |
537 | else | |
538 | ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
539 | real1, imag1, NULL_RTX, unsignedp); | |
540 | ||
541 | if (ratio == 0) | |
542 | return 0; | |
543 | ||
544 | /* Calculate divisor. */ | |
545 | ||
91ce572a | 546 | temp1 = expand_binop (submode, this_mul_optab, real1, ratio, |
c64f913e CB |
547 | NULL_RTX, unsignedp, methods); |
548 | ||
549 | if (temp1 == 0) | |
550 | return 0; | |
551 | ||
91ce572a | 552 | divisor = expand_binop (submode, this_add_optab, temp1, imag1, |
c64f913e CB |
553 | NULL_RTX, unsignedp, methods); |
554 | ||
555 | if (divisor == 0) | |
556 | return 0; | |
557 | ||
558 | /* Calculate dividend. */ | |
559 | ||
086bbd21 | 560 | if (imag0 == 0) |
c64f913e CB |
561 | { |
562 | /* Compute a / (c+id) as a(c/d) / (c(c/d)+d) + i (-a) / (c(c/d)+d). */ | |
563 | ||
91ce572a | 564 | real_t = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
565 | NULL_RTX, unsignedp, methods); |
566 | ||
91ce572a | 567 | imag_t = expand_unop (submode, this_neg_optab, real0, |
c64f913e CB |
568 | NULL_RTX, unsignedp); |
569 | ||
570 | if (real_t == 0 || imag_t == 0) | |
571 | return 0; | |
572 | } | |
573 | else | |
574 | { | |
575 | /* Compute (a+ib)/(c+id) as | |
576 | (a(c/d)+b)/(c(c/d)+d) + i (b(c/d)-a)/(c(c/d)+d). */ | |
577 | ||
91ce572a | 578 | temp1 = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
579 | NULL_RTX, unsignedp, methods); |
580 | ||
581 | if (temp1 == 0) | |
582 | return 0; | |
583 | ||
91ce572a | 584 | real_t = expand_binop (submode, this_add_optab, temp1, imag0, |
c64f913e CB |
585 | NULL_RTX, unsignedp, methods); |
586 | ||
91ce572a | 587 | temp1 = expand_binop (submode, this_mul_optab, imag0, ratio, |
c64f913e CB |
588 | NULL_RTX, unsignedp, methods); |
589 | ||
590 | if (temp1 == 0) | |
591 | return 0; | |
592 | ||
91ce572a | 593 | imag_t = expand_binop (submode, this_sub_optab, temp1, real0, |
c64f913e CB |
594 | NULL_RTX, unsignedp, methods); |
595 | ||
596 | if (real_t == 0 || imag_t == 0) | |
597 | return 0; | |
598 | } | |
599 | ||
600 | if (class == MODE_COMPLEX_FLOAT) | |
601 | res = expand_binop (submode, binoptab, real_t, divisor, | |
602 | realr, unsignedp, methods); | |
603 | else | |
604 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
605 | real_t, divisor, realr, unsignedp); | |
606 | ||
607 | if (res == 0) | |
608 | return 0; | |
609 | ||
610 | if (res != realr) | |
611 | emit_move_insn (realr, res); | |
612 | ||
613 | if (class == MODE_COMPLEX_FLOAT) | |
614 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
615 | imagr, unsignedp, methods); | |
616 | else | |
617 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
618 | imag_t, divisor, imagr, unsignedp); | |
619 | ||
620 | if (res == 0) | |
621 | return 0; | |
622 | ||
623 | if (res != imagr) | |
624 | emit_move_insn (imagr, res); | |
625 | ||
626 | emit_label (lab2); | |
627 | ||
628 | return 1; | |
629 | } | |
630 | \f | |
ef89d648 ZW |
631 | /* Wrapper around expand_binop which takes an rtx code to specify |
632 | the operation to perform, not an optab pointer. All other | |
633 | arguments are the same. */ | |
634 | rtx | |
0c20a65f AJ |
635 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
636 | rtx op1, rtx target, int unsignedp, | |
637 | enum optab_methods methods) | |
ef89d648 | 638 | { |
7e1a450d | 639 | optab binop = code_to_optab[(int) code]; |
ef89d648 ZW |
640 | if (binop == 0) |
641 | abort (); | |
642 | ||
643 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
644 | } | |
645 | ||
77c9c6c2 RK |
646 | /* Generate code to perform an operation specified by BINOPTAB |
647 | on operands OP0 and OP1, with result having machine-mode MODE. | |
648 | ||
649 | UNSIGNEDP is for the case where we have to widen the operands | |
650 | to perform the operation. It says to use zero-extension. | |
651 | ||
652 | If TARGET is nonzero, the value | |
653 | is generated there, if it is convenient to do so. | |
654 | In all cases an rtx is returned for the locus of the value; | |
655 | this may or may not be TARGET. */ | |
656 | ||
657 | rtx | |
0c20a65f AJ |
658 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
659 | rtx target, int unsignedp, enum optab_methods methods) | |
77c9c6c2 | 660 | { |
70864443 RK |
661 | enum optab_methods next_methods |
662 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
663 | ? OPTAB_WIDEN : methods); | |
77c9c6c2 RK |
664 | enum mode_class class; |
665 | enum machine_mode wider_mode; | |
b3694847 | 666 | rtx temp; |
77c9c6c2 | 667 | int commutative_op = 0; |
7e1a450d | 668 | int shift_op = (binoptab->code == ASHIFT |
77c9c6c2 | 669 | || binoptab->code == ASHIFTRT |
77c9c6c2 RK |
670 | || binoptab->code == LSHIFTRT |
671 | || binoptab->code == ROTATE | |
672 | || binoptab->code == ROTATERT); | |
abd418d3 | 673 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
674 | rtx last; |
675 | ||
676 | class = GET_MODE_CLASS (mode); | |
677 | ||
678 | op0 = protect_from_queue (op0, 0); | |
679 | op1 = protect_from_queue (op1, 0); | |
680 | if (target) | |
681 | target = protect_from_queue (target, 1); | |
682 | ||
683 | if (flag_force_mem) | |
684 | { | |
894207cf RS |
685 | /* Load duplicate non-volatile operands once. */ |
686 | if (rtx_equal_p (op0, op1) && ! volatile_refs_p (op0)) | |
687 | { | |
688 | op0 = force_not_mem (op0); | |
689 | op1 = op0; | |
690 | } | |
691 | else | |
692 | { | |
693 | op0 = force_not_mem (op0); | |
694 | op1 = force_not_mem (op1); | |
695 | } | |
77c9c6c2 RK |
696 | } |
697 | ||
8aecce0a RK |
698 | /* If subtracting an integer constant, convert this into an addition of |
699 | the negated constant. */ | |
700 | ||
701 | if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT) | |
702 | { | |
703 | op1 = negate_rtx (mode, op1); | |
704 | binoptab = add_optab; | |
705 | } | |
706 | ||
77c9c6c2 RK |
707 | /* If we are inside an appropriately-short loop and one operand is an |
708 | expensive constant, force it into a register. */ | |
aeedc93f | 709 | if (CONSTANT_P (op0) && preserve_subexpressions_p () |
b437f1a7 | 710 | && rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
711 | op0 = force_reg (mode, op0); |
712 | ||
aeedc93f | 713 | if (CONSTANT_P (op1) && preserve_subexpressions_p () |
b437f1a7 | 714 | && ! shift_op && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1)) |
4074220e | 715 | op1 = force_reg (mode, op1); |
77c9c6c2 | 716 | |
77c9c6c2 RK |
717 | /* Record where to delete back to if we backtrack. */ |
718 | last = get_last_insn (); | |
719 | ||
720 | /* If operation is commutative, | |
721 | try to make the first operand a register. | |
722 | Even better, try to make it the same as the target. | |
723 | Also try to make the last operand a constant. */ | |
ec8e098d | 724 | if (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH |
77c9c6c2 | 725 | || binoptab == smul_widen_optab |
5035bbfe TG |
726 | || binoptab == umul_widen_optab |
727 | || binoptab == smul_highpart_optab | |
728 | || binoptab == umul_highpart_optab) | |
77c9c6c2 RK |
729 | { |
730 | commutative_op = 1; | |
731 | ||
732 | if (((target == 0 || GET_CODE (target) == REG) | |
733 | ? ((GET_CODE (op1) == REG | |
734 | && GET_CODE (op0) != REG) | |
735 | || target == op1) | |
736 | : rtx_equal_p (op1, target)) | |
737 | || GET_CODE (op0) == CONST_INT) | |
738 | { | |
739 | temp = op1; | |
740 | op1 = op0; | |
741 | op0 = temp; | |
742 | } | |
743 | } | |
744 | ||
745 | /* If we can do it with a three-operand insn, do so. */ | |
746 | ||
747 | if (methods != OPTAB_MUST_WIDEN | |
748 | && binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
749 | { | |
750 | int icode = (int) binoptab->handlers[(int) mode].insn_code; | |
a995e389 RH |
751 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
752 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
753 | rtx pat; |
754 | rtx xop0 = op0, xop1 = op1; | |
755 | ||
756 | if (target) | |
757 | temp = target; | |
758 | else | |
759 | temp = gen_reg_rtx (mode); | |
760 | ||
761 | /* If it is a commutative operator and the modes would match | |
0f41302f | 762 | if we would swap the operands, we can save the conversions. */ |
77c9c6c2 RK |
763 | if (commutative_op) |
764 | { | |
765 | if (GET_MODE (op0) != mode0 && GET_MODE (op1) != mode1 | |
766 | && GET_MODE (op0) == mode1 && GET_MODE (op1) == mode0) | |
767 | { | |
b3694847 | 768 | rtx tmp; |
77c9c6c2 RK |
769 | |
770 | tmp = op0; op0 = op1; op1 = tmp; | |
771 | tmp = xop0; xop0 = xop1; xop1 = tmp; | |
772 | } | |
773 | } | |
774 | ||
775 | /* In case the insn wants input operands in modes different from | |
29984e05 EB |
776 | those of the actual operands, convert the operands. It would |
777 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
778 | that they're properly zero-extended, sign-extended or truncated |
779 | for their mode. */ | |
77c9c6c2 | 780 | |
874f6a6d | 781 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
69107307 AO |
782 | xop0 = convert_modes (mode0, |
783 | GET_MODE (op0) != VOIDmode | |
784 | ? GET_MODE (op0) | |
29984e05 | 785 | : mode, |
69107307 | 786 | xop0, unsignedp); |
77c9c6c2 | 787 | |
874f6a6d | 788 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) |
69107307 AO |
789 | xop1 = convert_modes (mode1, |
790 | GET_MODE (op1) != VOIDmode | |
791 | ? GET_MODE (op1) | |
35f1c975 | 792 | : mode, |
69107307 | 793 | xop1, unsignedp); |
77c9c6c2 RK |
794 | |
795 | /* Now, if insn's predicates don't allow our operands, put them into | |
796 | pseudo regs. */ | |
797 | ||
a995e389 | 798 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0) |
4074220e | 799 | && mode0 != VOIDmode) |
77c9c6c2 RK |
800 | xop0 = copy_to_mode_reg (mode0, xop0); |
801 | ||
a995e389 | 802 | if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1) |
4074220e | 803 | && mode1 != VOIDmode) |
77c9c6c2 RK |
804 | xop1 = copy_to_mode_reg (mode1, xop1); |
805 | ||
a995e389 | 806 | if (! (*insn_data[icode].operand[0].predicate) (temp, mode)) |
77c9c6c2 RK |
807 | temp = gen_reg_rtx (mode); |
808 | ||
809 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
810 | if (pat) | |
811 | { | |
2f937369 | 812 | /* If PAT is composed of more than one insn, try to add an appropriate |
77c9c6c2 RK |
813 | REG_EQUAL note to it. If we can't because TEMP conflicts with an |
814 | operand, call ourselves again, this time without a target. */ | |
2f937369 | 815 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
77c9c6c2 RK |
816 | && ! add_equal_note (pat, temp, binoptab->code, xop0, xop1)) |
817 | { | |
818 | delete_insns_since (last); | |
b1ec3c92 CH |
819 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, |
820 | unsignedp, methods); | |
77c9c6c2 RK |
821 | } |
822 | ||
823 | emit_insn (pat); | |
824 | return temp; | |
825 | } | |
826 | else | |
827 | delete_insns_since (last); | |
828 | } | |
829 | ||
5a5064dc RK |
830 | /* If this is a multiply, see if we can do a widening operation that |
831 | takes operands of this mode and makes a wider mode. */ | |
832 | ||
833 | if (binoptab == smul_optab && GET_MODE_WIDER_MODE (mode) != VOIDmode | |
834 | && (((unsignedp ? umul_widen_optab : smul_widen_optab) | |
835 | ->handlers[(int) GET_MODE_WIDER_MODE (mode)].insn_code) | |
836 | != CODE_FOR_nothing)) | |
837 | { | |
838 | temp = expand_binop (GET_MODE_WIDER_MODE (mode), | |
839 | unsignedp ? umul_widen_optab : smul_widen_optab, | |
73d9a835 | 840 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
5a5064dc | 841 | |
70864443 RK |
842 | if (temp != 0) |
843 | { | |
844 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
845 | return gen_lowpart (mode, temp); | |
846 | else | |
847 | return convert_to_mode (mode, temp, unsignedp); | |
848 | } | |
5a5064dc RK |
849 | } |
850 | ||
9a856ec7 | 851 | /* Look for a wider mode of the same class for which we think we |
5a5064dc RK |
852 | can open-code the operation. Check for a widening multiply at the |
853 | wider mode as well. */ | |
9a856ec7 RK |
854 | |
855 | if ((class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
6f43c157 | 856 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
9a856ec7 RK |
857 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
858 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
859 | { | |
5a5064dc RK |
860 | if (binoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing |
861 | || (binoptab == smul_optab | |
862 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
863 | && (((unsignedp ? umul_widen_optab : smul_widen_optab) | |
864 | ->handlers[(int) GET_MODE_WIDER_MODE (wider_mode)].insn_code) | |
865 | != CODE_FOR_nothing))) | |
9a856ec7 RK |
866 | { |
867 | rtx xop0 = op0, xop1 = op1; | |
868 | int no_extend = 0; | |
869 | ||
870 | /* For certain integer operations, we need not actually extend | |
871 | the narrow operands, as long as we will truncate | |
6d2f8887 | 872 | the results to the same narrowness. */ |
9a856ec7 RK |
873 | |
874 | if ((binoptab == ior_optab || binoptab == and_optab | |
875 | || binoptab == xor_optab | |
876 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 877 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 878 | && class == MODE_INT) |
9a856ec7 RK |
879 | no_extend = 1; |
880 | ||
0661a3de | 881 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
943cc242 RK |
882 | |
883 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 884 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 885 | no_extend && binoptab != ashl_optab); |
943cc242 | 886 | |
b1ec3c92 | 887 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
9a856ec7 RK |
888 | unsignedp, OPTAB_DIRECT); |
889 | if (temp) | |
890 | { | |
891 | if (class != MODE_INT) | |
892 | { | |
893 | if (target == 0) | |
894 | target = gen_reg_rtx (mode); | |
895 | convert_move (target, temp, 0); | |
896 | return target; | |
897 | } | |
898 | else | |
899 | return gen_lowpart (mode, temp); | |
900 | } | |
901 | else | |
902 | delete_insns_since (last); | |
903 | } | |
904 | } | |
905 | ||
77c9c6c2 RK |
906 | /* These can be done a word at a time. */ |
907 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
908 | && class == MODE_INT | |
909 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
34e56753 | 910 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 911 | { |
bb93b973 | 912 | int i; |
77c9c6c2 RK |
913 | rtx insns; |
914 | rtx equiv_value; | |
915 | ||
916 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
917 | won't be accurate, so use a new target. */ | |
918 | if (target == 0 || target == op0 || target == op1) | |
919 | target = gen_reg_rtx (mode); | |
920 | ||
921 | start_sequence (); | |
922 | ||
923 | /* Do the actual arithmetic. */ | |
924 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
925 | { | |
926 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 927 | rtx x = expand_binop (word_mode, binoptab, |
77c9c6c2 RK |
928 | operand_subword_force (op0, i, mode), |
929 | operand_subword_force (op1, i, mode), | |
70864443 RK |
930 | target_piece, unsignedp, next_methods); |
931 | ||
932 | if (x == 0) | |
933 | break; | |
934 | ||
77c9c6c2 RK |
935 | if (target_piece != x) |
936 | emit_move_insn (target_piece, x); | |
937 | } | |
938 | ||
939 | insns = get_insns (); | |
940 | end_sequence (); | |
941 | ||
70864443 RK |
942 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
943 | { | |
944 | if (binoptab->code != UNKNOWN) | |
945 | equiv_value | |
9e6a5703 JC |
946 | = gen_rtx_fmt_ee (binoptab->code, mode, |
947 | copy_rtx (op0), copy_rtx (op1)); | |
70864443 RK |
948 | else |
949 | equiv_value = 0; | |
77c9c6c2 | 950 | |
70864443 RK |
951 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); |
952 | return target; | |
953 | } | |
77c9c6c2 RK |
954 | } |
955 | ||
8c597270 | 956 | /* Synthesize double word shifts from single word shifts. */ |
e5df894b RK |
957 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
958 | || binoptab == ashr_optab) | |
8c597270 JW |
959 | && class == MODE_INT |
960 | && GET_CODE (op1) == CONST_INT | |
961 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
962 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
963 | && ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
964 | && lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) | |
965 | { | |
70864443 | 966 | rtx insns, inter, equiv_value; |
8c597270 JW |
967 | rtx into_target, outof_target; |
968 | rtx into_input, outof_input; | |
969 | int shift_count, left_shift, outof_word; | |
970 | ||
971 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
972 | won't be accurate, so use a new target. */ | |
973 | if (target == 0 || target == op0 || target == op1) | |
974 | target = gen_reg_rtx (mode); | |
975 | ||
976 | start_sequence (); | |
977 | ||
978 | shift_count = INTVAL (op1); | |
979 | ||
980 | /* OUTOF_* is the word we are shifting bits away from, and | |
981 | INTO_* is the word that we are shifting bits towards, thus | |
982 | they differ depending on the direction of the shift and | |
983 | WORDS_BIG_ENDIAN. */ | |
984 | ||
e5df894b | 985 | left_shift = binoptab == ashl_optab; |
8c597270 JW |
986 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; |
987 | ||
988 | outof_target = operand_subword (target, outof_word, 1, mode); | |
989 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
990 | ||
991 | outof_input = operand_subword_force (op0, outof_word, mode); | |
992 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
993 | ||
994 | if (shift_count >= BITS_PER_WORD) | |
995 | { | |
70864443 RK |
996 | inter = expand_binop (word_mode, binoptab, |
997 | outof_input, | |
998 | GEN_INT (shift_count - BITS_PER_WORD), | |
999 | into_target, unsignedp, next_methods); | |
1000 | ||
cb5b00cf | 1001 | if (inter != 0 && inter != into_target) |
70864443 | 1002 | emit_move_insn (into_target, inter); |
8c597270 JW |
1003 | |
1004 | /* For a signed right shift, we must fill the word we are shifting | |
1005 | out of with copies of the sign bit. Otherwise it is zeroed. */ | |
cb5b00cf RK |
1006 | if (inter != 0 && binoptab != ashr_optab) |
1007 | inter = CONST0_RTX (word_mode); | |
70864443 RK |
1008 | else if (inter != 0) |
1009 | inter = expand_binop (word_mode, binoptab, | |
1010 | outof_input, | |
1011 | GEN_INT (BITS_PER_WORD - 1), | |
1012 | outof_target, unsignedp, next_methods); | |
1013 | ||
cb5b00cf | 1014 | if (inter != 0 && inter != outof_target) |
70864443 | 1015 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1016 | } |
1017 | else | |
1018 | { | |
70864443 | 1019 | rtx carries; |
8c597270 JW |
1020 | optab reverse_unsigned_shift, unsigned_shift; |
1021 | ||
1022 | /* For a shift of less then BITS_PER_WORD, to compute the carry, | |
1023 | we must do a logical shift in the opposite direction of the | |
1024 | desired shift. */ | |
1025 | ||
8c597270 JW |
1026 | reverse_unsigned_shift = (left_shift ? lshr_optab : ashl_optab); |
1027 | ||
1028 | /* For a shift of less than BITS_PER_WORD, to compute the word | |
1029 | shifted towards, we need to unsigned shift the orig value of | |
1030 | that word. */ | |
1031 | ||
1032 | unsigned_shift = (left_shift ? ashl_optab : lshr_optab); | |
1033 | ||
1034 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
1035 | outof_input, | |
1036 | GEN_INT (BITS_PER_WORD - shift_count), | |
70864443 RK |
1037 | 0, unsignedp, next_methods); |
1038 | ||
1039 | if (carries == 0) | |
1040 | inter = 0; | |
1041 | else | |
70864443 RK |
1042 | inter = expand_binop (word_mode, unsigned_shift, into_input, |
1043 | op1, 0, unsignedp, next_methods); | |
1044 | ||
1045 | if (inter != 0) | |
1046 | inter = expand_binop (word_mode, ior_optab, carries, inter, | |
1047 | into_target, unsignedp, next_methods); | |
1048 | ||
cb5b00cf | 1049 | if (inter != 0 && inter != into_target) |
70864443 | 1050 | emit_move_insn (into_target, inter); |
cf2f7113 RE |
1051 | |
1052 | if (inter != 0) | |
1053 | inter = expand_binop (word_mode, binoptab, outof_input, | |
1054 | op1, outof_target, unsignedp, next_methods); | |
0c20a65f | 1055 | |
cf2f7113 RE |
1056 | if (inter != 0 && inter != outof_target) |
1057 | emit_move_insn (outof_target, inter); | |
8c597270 JW |
1058 | } |
1059 | ||
1060 | insns = get_insns (); | |
1061 | end_sequence (); | |
1062 | ||
70864443 RK |
1063 | if (inter != 0) |
1064 | { | |
1065 | if (binoptab->code != UNKNOWN) | |
9e6a5703 | 1066 | equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1); |
70864443 RK |
1067 | else |
1068 | equiv_value = 0; | |
8c597270 | 1069 | |
70864443 RK |
1070 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); |
1071 | return target; | |
1072 | } | |
8c597270 JW |
1073 | } |
1074 | ||
1075 | /* Synthesize double word rotates from single word shifts. */ | |
1076 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
1077 | && class == MODE_INT | |
1078 | && GET_CODE (op1) == CONST_INT | |
1079 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1080 | && ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
1081 | && lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) | |
1082 | { | |
1083 | rtx insns, equiv_value; | |
1084 | rtx into_target, outof_target; | |
1085 | rtx into_input, outof_input; | |
70864443 | 1086 | rtx inter; |
8c597270 JW |
1087 | int shift_count, left_shift, outof_word; |
1088 | ||
1089 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
0c0ab0f1 OH |
1090 | won't be accurate, so use a new target. Do this also if target is not |
1091 | a REG, first because having a register instead may open optimization | |
1092 | oportunities, and second because if target and op0 happen to be MEMs | |
1093 | designating the same location, we would risk clobbering it too early | |
1094 | in the code sequence we generate below. */ | |
1095 | if (target == 0 || target == op0 || target == op1 || ! REG_P (target)) | |
8c597270 JW |
1096 | target = gen_reg_rtx (mode); |
1097 | ||
1098 | start_sequence (); | |
1099 | ||
1100 | shift_count = INTVAL (op1); | |
1101 | ||
1102 | /* OUTOF_* is the word we are shifting bits away from, and | |
1103 | INTO_* is the word that we are shifting bits towards, thus | |
1104 | they differ depending on the direction of the shift and | |
1105 | WORDS_BIG_ENDIAN. */ | |
1106 | ||
1107 | left_shift = (binoptab == rotl_optab); | |
1108 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1109 | ||
1110 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1111 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1112 | ||
1113 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1114 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1115 | ||
1116 | if (shift_count == BITS_PER_WORD) | |
1117 | { | |
1118 | /* This is just a word swap. */ | |
1119 | emit_move_insn (outof_target, into_input); | |
1120 | emit_move_insn (into_target, outof_input); | |
70864443 | 1121 | inter = const0_rtx; |
8c597270 JW |
1122 | } |
1123 | else | |
1124 | { | |
1125 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1126 | rtx first_shift_count, second_shift_count; | |
1127 | optab reverse_unsigned_shift, unsigned_shift; | |
1128 | ||
1129 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1130 | ? lshr_optab : ashl_optab); | |
1131 | ||
1132 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1133 | ? ashl_optab : lshr_optab); | |
1134 | ||
1135 | if (shift_count > BITS_PER_WORD) | |
1136 | { | |
1137 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
7e1a450d | 1138 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
8c597270 JW |
1139 | } |
1140 | else | |
1141 | { | |
1142 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1143 | second_shift_count = GEN_INT (shift_count); | |
1144 | } | |
1145 | ||
1146 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1147 | outof_input, first_shift_count, | |
70864443 | 1148 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1149 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1150 | into_input, second_shift_count, | |
5be5c8d4 | 1151 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1152 | |
1153 | if (into_temp1 != 0 && into_temp2 != 0) | |
1154 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1155 | into_target, unsignedp, next_methods); | |
1156 | else | |
1157 | inter = 0; | |
1158 | ||
cb5b00cf | 1159 | if (inter != 0 && inter != into_target) |
70864443 | 1160 | emit_move_insn (into_target, inter); |
8c597270 JW |
1161 | |
1162 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1163 | into_input, first_shift_count, | |
70864443 | 1164 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1165 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1166 | outof_input, second_shift_count, | |
5be5c8d4 | 1167 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1168 | |
1169 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1170 | inter = expand_binop (word_mode, ior_optab, | |
1171 | outof_temp1, outof_temp2, | |
1172 | outof_target, unsignedp, next_methods); | |
1173 | ||
cb5b00cf | 1174 | if (inter != 0 && inter != outof_target) |
70864443 | 1175 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1176 | } |
1177 | ||
1178 | insns = get_insns (); | |
1179 | end_sequence (); | |
1180 | ||
70864443 RK |
1181 | if (inter != 0) |
1182 | { | |
1183 | if (binoptab->code != UNKNOWN) | |
9e6a5703 | 1184 | equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1); |
70864443 RK |
1185 | else |
1186 | equiv_value = 0; | |
8c597270 | 1187 | |
70864443 RK |
1188 | /* We can't make this a no conflict block if this is a word swap, |
1189 | because the word swap case fails if the input and output values | |
1190 | are in the same register. */ | |
1191 | if (shift_count != BITS_PER_WORD) | |
1192 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); | |
1193 | else | |
2f937369 | 1194 | emit_insn (insns); |
70864443 RK |
1195 | |
1196 | ||
1197 | return target; | |
1198 | } | |
8c597270 JW |
1199 | } |
1200 | ||
77c9c6c2 RK |
1201 | /* These can be done a word at a time by propagating carries. */ |
1202 | if ((binoptab == add_optab || binoptab == sub_optab) | |
1203 | && class == MODE_INT | |
1204 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD | |
34e56753 | 1205 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 1206 | { |
e2500fed | 1207 | unsigned int i; |
77c9c6c2 | 1208 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
a4b5414c | 1209 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
07444f1d | 1210 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
64de6c0a | 1211 | rtx xop0, xop1, xtarget; |
77c9c6c2 RK |
1212 | |
1213 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1214 | value is one of those, use it. Otherwise, use 1 since it is the | |
1215 | one easiest to get. */ | |
1216 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1217 | int normalizep = STORE_FLAG_VALUE; | |
1218 | #else | |
1219 | int normalizep = 1; | |
1220 | #endif | |
1221 | ||
1222 | /* Prepare the operands. */ | |
cee85023 RS |
1223 | xop0 = force_reg (mode, op0); |
1224 | xop1 = force_reg (mode, op1); | |
77c9c6c2 | 1225 | |
64de6c0a DE |
1226 | xtarget = gen_reg_rtx (mode); |
1227 | ||
1228 | if (target == 0 || GET_CODE (target) != REG) | |
1229 | target = xtarget; | |
77c9c6c2 | 1230 | |
af2cc4dd RS |
1231 | /* Indicate for flow that the entire target reg is being set. */ |
1232 | if (GET_CODE (target) == REG) | |
64de6c0a | 1233 | emit_insn (gen_rtx_CLOBBER (VOIDmode, xtarget)); |
af2cc4dd | 1234 | |
77c9c6c2 RK |
1235 | /* Do the actual arithmetic. */ |
1236 | for (i = 0; i < nwords; i++) | |
1237 | { | |
1238 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
64de6c0a | 1239 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
cee85023 RS |
1240 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
1241 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
77c9c6c2 RK |
1242 | rtx x; |
1243 | ||
1244 | /* Main add/subtract of the input operands. */ | |
34e56753 | 1245 | x = expand_binop (word_mode, binoptab, |
77c9c6c2 | 1246 | op0_piece, op1_piece, |
70864443 | 1247 | target_piece, unsignedp, next_methods); |
77c9c6c2 RK |
1248 | if (x == 0) |
1249 | break; | |
1250 | ||
1251 | if (i + 1 < nwords) | |
1252 | { | |
1253 | /* Store carry from main add/subtract. */ | |
34e56753 | 1254 | carry_out = gen_reg_rtx (word_mode); |
23357404 TG |
1255 | carry_out = emit_store_flag_force (carry_out, |
1256 | (binoptab == add_optab | |
b30f05db | 1257 | ? LT : GT), |
23357404 TG |
1258 | x, op0_piece, |
1259 | word_mode, 1, normalizep); | |
77c9c6c2 RK |
1260 | } |
1261 | ||
1262 | if (i > 0) | |
1263 | { | |
859cb4d8 | 1264 | rtx newx; |
0c20a65f | 1265 | |
77c9c6c2 | 1266 | /* Add/subtract previous carry to main result. */ |
859cb4d8 GK |
1267 | newx = expand_binop (word_mode, |
1268 | normalizep == 1 ? binoptab : otheroptab, | |
1269 | x, carry_in, | |
1270 | NULL_RTX, 1, next_methods); | |
77c9c6c2 RK |
1271 | |
1272 | if (i + 1 < nwords) | |
1273 | { | |
77c9c6c2 | 1274 | /* Get out carry from adding/subtracting carry in. */ |
859cb4d8 | 1275 | rtx carry_tmp = gen_reg_rtx (word_mode); |
23357404 | 1276 | carry_tmp = emit_store_flag_force (carry_tmp, |
859cb4d8 GK |
1277 | (binoptab == add_optab |
1278 | ? LT : GT), | |
1279 | newx, x, | |
23357404 | 1280 | word_mode, 1, normalizep); |
70864443 | 1281 | |
77c9c6c2 | 1282 | /* Logical-ior the two poss. carry together. */ |
34e56753 | 1283 | carry_out = expand_binop (word_mode, ior_optab, |
77c9c6c2 | 1284 | carry_out, carry_tmp, |
70864443 RK |
1285 | carry_out, 0, next_methods); |
1286 | if (carry_out == 0) | |
77c9c6c2 RK |
1287 | break; |
1288 | } | |
859cb4d8 | 1289 | emit_move_insn (target_piece, newx); |
77c9c6c2 RK |
1290 | } |
1291 | ||
1292 | carry_in = carry_out; | |
0c20a65f | 1293 | } |
77c9c6c2 | 1294 | |
e2500fed | 1295 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
77c9c6c2 | 1296 | { |
d0ccc658 RK |
1297 | if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing |
1298 | || ! rtx_equal_p (target, xtarget)) | |
02214a5c | 1299 | { |
64de6c0a | 1300 | rtx temp = emit_move_insn (target, xtarget); |
70864443 | 1301 | |
5fa671cf | 1302 | set_unique_reg_note (temp, |
0c20a65f | 1303 | REG_EQUAL, |
5fa671cf AM |
1304 | gen_rtx_fmt_ee (binoptab->code, mode, |
1305 | copy_rtx (xop0), | |
1306 | copy_rtx (xop1))); | |
02214a5c | 1307 | } |
2cd622c3 AO |
1308 | else |
1309 | target = xtarget; | |
c5c76735 | 1310 | |
77c9c6c2 RK |
1311 | return target; |
1312 | } | |
c5c76735 | 1313 | |
77c9c6c2 RK |
1314 | else |
1315 | delete_insns_since (last); | |
1316 | } | |
1317 | ||
1318 | /* If we want to multiply two two-word values and have normal and widening | |
1319 | multiplies of single-word values, we can do this with three smaller | |
1320 | multiplications. Note that we do not make a REG_NO_CONFLICT block here | |
0c20a65f | 1321 | because we are not operating on one word at a time. |
77c9c6c2 RK |
1322 | |
1323 | The multiplication proceeds as follows: | |
34e56753 RS |
1324 | _______________________ |
1325 | [__op0_high_|__op0_low__] | |
1326 | _______________________ | |
6ffe0821 | 1327 | * [__op1_high_|__op1_low__] |
34e56753 RS |
1328 | _______________________________________________ |
1329 | _______________________ | |
6ffe0821 | 1330 | (1) [__op0_low__*__op1_low__] |
34e56753 | 1331 | _______________________ |
6ffe0821 | 1332 | (2a) [__op0_low__*__op1_high_] |
34e56753 | 1333 | _______________________ |
6ffe0821 | 1334 | (2b) [__op0_high_*__op1_low__] |
34e56753 RS |
1335 | _______________________ |
1336 | (3) [__op0_high_*__op1_high_] | |
77c9c6c2 RK |
1337 | |
1338 | ||
1339 | This gives a 4-word result. Since we are only interested in the | |
1340 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1341 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1342 | calculated using non-widening multiplication. | |
1343 | ||
1344 | (1), however, needs to be calculated with an unsigned widening | |
1345 | multiplication. If this operation is not directly supported we | |
1346 | try using a signed widening multiplication and adjust the result. | |
1347 | This adjustment works as follows: | |
1348 | ||
1349 | If both operands are positive then no adjustment is needed. | |
1350 | ||
1351 | If the operands have different signs, for example op0_low < 0 and | |
1352 | op1_low >= 0, the instruction treats the most significant bit of | |
1353 | op0_low as a sign bit instead of a bit with significance | |
1354 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1355 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1356 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1357 | the result. | |
1358 | ||
1359 | Similarly, if both operands are negative, we need to add | |
1360 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1361 | ||
1362 | We use a trick to adjust quickly. We logically shift op0_low right | |
1363 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1364 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1365 | logical shift exists, we do an arithmetic right shift and subtract | |
1366 | the 0 or -1. */ | |
1367 | ||
1368 | if (binoptab == smul_optab | |
1369 | && class == MODE_INT | |
1370 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
34e56753 RS |
1371 | && smul_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing |
1372 | && add_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
77c9c6c2 RK |
1373 | && ((umul_widen_optab->handlers[(int) mode].insn_code |
1374 | != CODE_FOR_nothing) | |
1375 | || (smul_widen_optab->handlers[(int) mode].insn_code | |
1376 | != CODE_FOR_nothing))) | |
1377 | { | |
1378 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1379 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1380 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1381 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1382 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1383 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1384 | rtx product = 0; | |
07444f1d TM |
1385 | rtx op0_xhigh = NULL_RTX; |
1386 | rtx op1_xhigh = NULL_RTX; | |
77c9c6c2 RK |
1387 | |
1388 | /* If the target is the same as one of the inputs, don't use it. This | |
1389 | prevents problems with the REG_EQUAL note. */ | |
f96d689c RK |
1390 | if (target == op0 || target == op1 |
1391 | || (target != 0 && GET_CODE (target) != REG)) | |
77c9c6c2 RK |
1392 | target = 0; |
1393 | ||
1394 | /* Multiply the two lower words to get a double-word product. | |
1395 | If unsigned widening multiplication is available, use that; | |
1396 | otherwise use the signed form and compensate. */ | |
1397 | ||
1398 | if (umul_widen_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
1399 | { | |
1400 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1401 | target, 1, OPTAB_DIRECT); | |
1402 | ||
1403 | /* If we didn't succeed, delete everything we did so far. */ | |
1404 | if (product == 0) | |
1405 | delete_insns_since (last); | |
1406 | else | |
1407 | op0_xhigh = op0_high, op1_xhigh = op1_high; | |
1408 | } | |
1409 | ||
1410 | if (product == 0 | |
1411 | && smul_widen_optab->handlers[(int) mode].insn_code | |
1412 | != CODE_FOR_nothing) | |
1413 | { | |
b1ec3c92 | 1414 | rtx wordm1 = GEN_INT (BITS_PER_WORD - 1); |
77c9c6c2 RK |
1415 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, |
1416 | target, 1, OPTAB_DIRECT); | |
34e56753 | 1417 | op0_xhigh = expand_binop (word_mode, lshr_optab, op0_low, wordm1, |
70864443 | 1418 | NULL_RTX, 1, next_methods); |
77c9c6c2 | 1419 | if (op0_xhigh) |
34e56753 | 1420 | op0_xhigh = expand_binop (word_mode, add_optab, op0_high, |
70864443 | 1421 | op0_xhigh, op0_xhigh, 0, next_methods); |
77c9c6c2 RK |
1422 | else |
1423 | { | |
34e56753 | 1424 | op0_xhigh = expand_binop (word_mode, ashr_optab, op0_low, wordm1, |
70864443 | 1425 | NULL_RTX, 0, next_methods); |
77c9c6c2 | 1426 | if (op0_xhigh) |
34e56753 | 1427 | op0_xhigh = expand_binop (word_mode, sub_optab, op0_high, |
77c9c6c2 | 1428 | op0_xhigh, op0_xhigh, 0, |
70864443 | 1429 | next_methods); |
77c9c6c2 RK |
1430 | } |
1431 | ||
34e56753 | 1432 | op1_xhigh = expand_binop (word_mode, lshr_optab, op1_low, wordm1, |
70864443 | 1433 | NULL_RTX, 1, next_methods); |
77c9c6c2 | 1434 | if (op1_xhigh) |
34e56753 | 1435 | op1_xhigh = expand_binop (word_mode, add_optab, op1_high, |
70864443 | 1436 | op1_xhigh, op1_xhigh, 0, next_methods); |
77c9c6c2 RK |
1437 | else |
1438 | { | |
34e56753 | 1439 | op1_xhigh = expand_binop (word_mode, ashr_optab, op1_low, wordm1, |
70864443 | 1440 | NULL_RTX, 0, next_methods); |
77c9c6c2 | 1441 | if (op1_xhigh) |
34e56753 | 1442 | op1_xhigh = expand_binop (word_mode, sub_optab, op1_high, |
77c9c6c2 | 1443 | op1_xhigh, op1_xhigh, 0, |
70864443 | 1444 | next_methods); |
77c9c6c2 RK |
1445 | } |
1446 | } | |
1447 | ||
1448 | /* If we have been able to directly compute the product of the | |
1449 | low-order words of the operands and perform any required adjustments | |
1450 | of the operands, we proceed by trying two more multiplications | |
1451 | and then computing the appropriate sum. | |
1452 | ||
1453 | We have checked above that the required addition is provided. | |
1454 | Full-word addition will normally always succeed, especially if | |
1455 | it is provided at all, so we don't worry about its failure. The | |
1456 | multiplication may well fail, however, so we do handle that. */ | |
1457 | ||
1458 | if (product && op0_xhigh && op1_xhigh) | |
1459 | { | |
77c9c6c2 | 1460 | rtx product_high = operand_subword (product, high, 1, mode); |
b1ec3c92 CH |
1461 | rtx temp = expand_binop (word_mode, binoptab, op0_low, op1_xhigh, |
1462 | NULL_RTX, 0, OPTAB_DIRECT); | |
77c9c6c2 | 1463 | |
c7539aa0 JL |
1464 | if (!REG_P (product_high)) |
1465 | product_high = force_reg (word_mode, product_high); | |
1466 | ||
70864443 RK |
1467 | if (temp != 0) |
1468 | temp = expand_binop (word_mode, add_optab, temp, product_high, | |
1469 | product_high, 0, next_methods); | |
77c9c6c2 | 1470 | |
70864443 RK |
1471 | if (temp != 0 && temp != product_high) |
1472 | emit_move_insn (product_high, temp); | |
1473 | ||
1474 | if (temp != 0) | |
0c20a65f | 1475 | temp = expand_binop (word_mode, binoptab, op1_low, op0_xhigh, |
70864443 RK |
1476 | NULL_RTX, 0, OPTAB_DIRECT); |
1477 | ||
1478 | if (temp != 0) | |
1479 | temp = expand_binop (word_mode, add_optab, temp, | |
1480 | product_high, product_high, | |
1481 | 0, next_methods); | |
77c9c6c2 | 1482 | |
70864443 RK |
1483 | if (temp != 0 && temp != product_high) |
1484 | emit_move_insn (product_high, temp); | |
77c9c6c2 | 1485 | |
c7539aa0 JL |
1486 | emit_move_insn (operand_subword (product, high, 1, mode), product_high); |
1487 | ||
70864443 RK |
1488 | if (temp != 0) |
1489 | { | |
02214a5c RK |
1490 | if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1491 | { | |
1492 | temp = emit_move_insn (product, product); | |
5fa671cf | 1493 | set_unique_reg_note (temp, |
0c20a65f | 1494 | REG_EQUAL, |
5fa671cf AM |
1495 | gen_rtx_fmt_ee (MULT, mode, |
1496 | copy_rtx (op0), | |
1497 | copy_rtx (op1))); | |
02214a5c | 1498 | } |
c5c76735 | 1499 | |
77c9c6c2 RK |
1500 | return product; |
1501 | } | |
1502 | } | |
1503 | ||
1504 | /* If we get here, we couldn't do it for some reason even though we | |
1505 | originally thought we could. Delete anything we've emitted in | |
1506 | trying to do it. */ | |
1507 | ||
1508 | delete_insns_since (last); | |
1509 | } | |
1510 | ||
cb2a532e AH |
1511 | /* Open-code the vector operations if we have no hardware support |
1512 | for them. */ | |
1513 | if (class == MODE_VECTOR_INT || class == MODE_VECTOR_FLOAT) | |
1514 | return expand_vector_binop (mode, binoptab, op0, op1, target, | |
1515 | unsignedp, methods); | |
1516 | ||
b818abb0 RS |
1517 | /* We need to open-code the complex type operations: '+, -, * and /' */ |
1518 | ||
1519 | /* At this point we allow operations between two similar complex | |
1520 | numbers, and also if one of the operands is not a complex number | |
1521 | but rather of MODE_FLOAT or MODE_INT. However, the caller | |
1522 | must make sure that the MODE of the non-complex operand matches | |
6f43c157 | 1523 | the SUBMODE of the complex operand. */ |
b818abb0 RS |
1524 | |
1525 | if (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT) | |
6f43c157 | 1526 | { |
70864443 RK |
1527 | rtx real0 = 0, imag0 = 0; |
1528 | rtx real1 = 0, imag1 = 0; | |
1529 | rtx realr, imagr, res; | |
c7d91a94 | 1530 | rtx seq, result; |
70864443 | 1531 | int ok = 0; |
b818abb0 | 1532 | |
f9da5064 | 1533 | /* Find the correct mode for the real and imaginary parts. */ |
c7d91a94 | 1534 | enum machine_mode submode = GET_MODE_INNER (mode); |
b818abb0 RS |
1535 | |
1536 | if (submode == BLKmode) | |
1537 | abort (); | |
1538 | ||
b818abb0 RS |
1539 | start_sequence (); |
1540 | ||
b818abb0 RS |
1541 | if (GET_MODE (op0) == mode) |
1542 | { | |
c64f913e | 1543 | real0 = gen_realpart (submode, op0); |
decdfa82 | 1544 | imag0 = gen_imagpart (submode, op0); |
b818abb0 RS |
1545 | } |
1546 | else | |
1547 | real0 = op0; | |
1548 | ||
1549 | if (GET_MODE (op1) == mode) | |
1550 | { | |
c64f913e | 1551 | real1 = gen_realpart (submode, op1); |
decdfa82 | 1552 | imag1 = gen_imagpart (submode, op1); |
b818abb0 RS |
1553 | } |
1554 | else | |
1555 | real1 = op1; | |
1556 | ||
c0fe508e | 1557 | if (real0 == 0 || real1 == 0 || ! (imag0 != 0 || imag1 != 0)) |
b818abb0 RS |
1558 | abort (); |
1559 | ||
c7d91a94 RS |
1560 | result = gen_reg_rtx (mode); |
1561 | realr = gen_realpart (submode, result); | |
1562 | imagr = gen_imagpart (submode, result); | |
1563 | ||
6f43c157 RS |
1564 | switch (binoptab->code) |
1565 | { | |
1566 | case PLUS: | |
96f153da | 1567 | /* (a+ib) + (c+id) = (a+c) + i(b+d) */ |
6f43c157 | 1568 | case MINUS: |
96f153da | 1569 | /* (a+ib) - (c+id) = (a-c) + i(b-d) */ |
b818abb0 RS |
1570 | res = expand_binop (submode, binoptab, real0, real1, |
1571 | realr, unsignedp, methods); | |
70864443 RK |
1572 | |
1573 | if (res == 0) | |
1574 | break; | |
1575 | else if (res != realr) | |
b818abb0 RS |
1576 | emit_move_insn (realr, res); |
1577 | ||
086bbd21 | 1578 | if (imag0 != 0 && imag1 != 0) |
b818abb0 RS |
1579 | res = expand_binop (submode, binoptab, imag0, imag1, |
1580 | imagr, unsignedp, methods); | |
086bbd21 | 1581 | else if (imag0 != 0) |
b818abb0 RS |
1582 | res = imag0; |
1583 | else if (binoptab->code == MINUS) | |
91ce572a CC |
1584 | res = expand_unop (submode, |
1585 | binoptab == subv_optab ? negv_optab : neg_optab, | |
1586 | imag1, imagr, unsignedp); | |
b818abb0 RS |
1587 | else |
1588 | res = imag1; | |
1589 | ||
70864443 RK |
1590 | if (res == 0) |
1591 | break; | |
1592 | else if (res != imagr) | |
b818abb0 | 1593 | emit_move_insn (imagr, res); |
70864443 RK |
1594 | |
1595 | ok = 1; | |
b818abb0 | 1596 | break; |
6f43c157 RS |
1597 | |
1598 | case MULT: | |
b818abb0 RS |
1599 | /* (a+ib) * (c+id) = (ac-bd) + i(ad+cb) */ |
1600 | ||
086bbd21 | 1601 | if (imag0 != 0 && imag1 != 0) |
b818abb0 | 1602 | { |
70864443 RK |
1603 | rtx temp1, temp2; |
1604 | ||
54e7b5e6 RS |
1605 | /* Don't fetch these from memory more than once. */ |
1606 | real0 = force_reg (submode, real0); | |
1607 | real1 = force_reg (submode, real1); | |
1608 | imag0 = force_reg (submode, imag0); | |
1609 | imag1 = force_reg (submode, imag1); | |
1610 | ||
70864443 RK |
1611 | temp1 = expand_binop (submode, binoptab, real0, real1, NULL_RTX, |
1612 | unsignedp, methods); | |
1613 | ||
1614 | temp2 = expand_binop (submode, binoptab, imag0, imag1, NULL_RTX, | |
1615 | unsignedp, methods); | |
1616 | ||
1617 | if (temp1 == 0 || temp2 == 0) | |
1618 | break; | |
1619 | ||
91ce572a CC |
1620 | res = (expand_binop |
1621 | (submode, | |
1622 | binoptab == smulv_optab ? subv_optab : sub_optab, | |
1623 | temp1, temp2, realr, unsignedp, methods)); | |
b818abb0 | 1624 | |
70864443 RK |
1625 | if (res == 0) |
1626 | break; | |
1627 | else if (res != realr) | |
54e7b5e6 | 1628 | emit_move_insn (realr, res); |
b818abb0 | 1629 | |
70864443 RK |
1630 | temp1 = expand_binop (submode, binoptab, real0, imag1, |
1631 | NULL_RTX, unsignedp, methods); | |
1632 | ||
df8ca70e RS |
1633 | /* Avoid expanding redundant multiplication for the common |
1634 | case of squaring a complex number. */ | |
1635 | if (rtx_equal_p (real0, real1) && rtx_equal_p (imag0, imag1)) | |
1636 | temp2 = temp1; | |
1637 | else | |
1638 | temp2 = expand_binop (submode, binoptab, real1, imag0, | |
1639 | NULL_RTX, unsignedp, methods); | |
70864443 RK |
1640 | |
1641 | if (temp1 == 0 || temp2 == 0) | |
7e1a450d | 1642 | break; |
1c63cc82 | 1643 | |
91ce572a CC |
1644 | res = (expand_binop |
1645 | (submode, | |
1646 | binoptab == smulv_optab ? addv_optab : add_optab, | |
1647 | temp1, temp2, imagr, unsignedp, methods)); | |
70864443 RK |
1648 | |
1649 | if (res == 0) | |
1650 | break; | |
1651 | else if (res != imagr) | |
b818abb0 | 1652 | emit_move_insn (imagr, res); |
70864443 RK |
1653 | |
1654 | ok = 1; | |
b818abb0 RS |
1655 | } |
1656 | else | |
1657 | { | |
54e7b5e6 RS |
1658 | /* Don't fetch these from memory more than once. */ |
1659 | real0 = force_reg (submode, real0); | |
1660 | real1 = force_reg (submode, real1); | |
1661 | ||
96f153da RS |
1662 | res = expand_binop (submode, binoptab, real0, real1, |
1663 | realr, unsignedp, methods); | |
70864443 RK |
1664 | if (res == 0) |
1665 | break; | |
1666 | else if (res != realr) | |
b818abb0 RS |
1667 | emit_move_insn (realr, res); |
1668 | ||
086bbd21 | 1669 | if (imag0 != 0) |
b818abb0 RS |
1670 | res = expand_binop (submode, binoptab, |
1671 | real1, imag0, imagr, unsignedp, methods); | |
1672 | else | |
1673 | res = expand_binop (submode, binoptab, | |
1674 | real0, imag1, imagr, unsignedp, methods); | |
70864443 RK |
1675 | |
1676 | if (res == 0) | |
1677 | break; | |
1678 | else if (res != imagr) | |
b818abb0 | 1679 | emit_move_insn (imagr, res); |
70864443 RK |
1680 | |
1681 | ok = 1; | |
b818abb0 RS |
1682 | } |
1683 | break; | |
6f43c157 RS |
1684 | |
1685 | case DIV: | |
96f153da | 1686 | /* (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) */ |
0c20a65f | 1687 | |
086bbd21 | 1688 | if (imag1 == 0) |
70864443 RK |
1689 | { |
1690 | /* (a+ib) / (c+i0) = (a/c) + i(b/c) */ | |
54e7b5e6 RS |
1691 | |
1692 | /* Don't fetch these from memory more than once. */ | |
1693 | real1 = force_reg (submode, real1); | |
1694 | ||
96f153da | 1695 | /* Simply divide the real and imaginary parts by `c' */ |
2140ed5b RK |
1696 | if (class == MODE_COMPLEX_FLOAT) |
1697 | res = expand_binop (submode, binoptab, real0, real1, | |
1698 | realr, unsignedp, methods); | |
1699 | else | |
1700 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1701 | real0, real1, realr, unsignedp); | |
1702 | ||
70864443 RK |
1703 | if (res == 0) |
1704 | break; | |
1705 | else if (res != realr) | |
b818abb0 RS |
1706 | emit_move_insn (realr, res); |
1707 | ||
2140ed5b RK |
1708 | if (class == MODE_COMPLEX_FLOAT) |
1709 | res = expand_binop (submode, binoptab, imag0, real1, | |
1710 | imagr, unsignedp, methods); | |
1711 | else | |
1712 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1713 | imag0, real1, imagr, unsignedp); | |
1714 | ||
70864443 RK |
1715 | if (res == 0) |
1716 | break; | |
1717 | else if (res != imagr) | |
b818abb0 | 1718 | emit_move_insn (imagr, res); |
b818abb0 | 1719 | |
70864443 RK |
1720 | ok = 1; |
1721 | } | |
1722 | else | |
1723 | { | |
c64f913e | 1724 | switch (flag_complex_divide_method) |
70864443 | 1725 | { |
c64f913e CB |
1726 | case 0: |
1727 | ok = expand_cmplxdiv_straight (real0, real1, imag0, imag1, | |
1728 | realr, imagr, submode, | |
1729 | unsignedp, methods, | |
1730 | class, binoptab); | |
1731 | break; | |
41b19f3e | 1732 | |
c64f913e CB |
1733 | case 1: |
1734 | ok = expand_cmplxdiv_wide (real0, real1, imag0, imag1, | |
1735 | realr, imagr, submode, | |
1736 | unsignedp, methods, | |
1737 | class, binoptab); | |
1738 | break; | |
70864443 | 1739 | |
c64f913e CB |
1740 | default: |
1741 | abort (); | |
b818abb0 | 1742 | } |
b818abb0 RS |
1743 | } |
1744 | break; | |
0c20a65f | 1745 | |
b818abb0 RS |
1746 | default: |
1747 | abort (); | |
1748 | } | |
1749 | ||
c15886da | 1750 | seq = get_insns (); |
b818abb0 RS |
1751 | end_sequence (); |
1752 | ||
70864443 RK |
1753 | if (ok) |
1754 | { | |
c7d91a94 RS |
1755 | rtx equiv = gen_rtx_fmt_ee (binoptab->code, mode, |
1756 | copy_rtx (op0), copy_rtx (op1)); | |
1757 | emit_no_conflict_block (seq, result, op0, op1, equiv); | |
1758 | return result; | |
70864443 | 1759 | } |
b818abb0 | 1760 | } |
b818abb0 | 1761 | |
77c9c6c2 RK |
1762 | /* It can't be open-coded in this mode. |
1763 | Use a library call if one is available and caller says that's ok. */ | |
1764 | ||
1765 | if (binoptab->handlers[(int) mode].libfunc | |
1766 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) | |
1767 | { | |
1768 | rtx insns; | |
0bbb7f4d RS |
1769 | rtx op1x = op1; |
1770 | enum machine_mode op1_mode = mode; | |
9a7f678c | 1771 | rtx value; |
77c9c6c2 RK |
1772 | |
1773 | start_sequence (); | |
1774 | ||
0bbb7f4d RS |
1775 | if (shift_op) |
1776 | { | |
1777 | op1_mode = word_mode; | |
1778 | /* Specify unsigned here, | |
1779 | since negative shift counts are meaningless. */ | |
1780 | op1x = convert_to_mode (word_mode, op1, 1); | |
1781 | } | |
1782 | ||
82f0e2cc RK |
1783 | if (GET_MODE (op0) != VOIDmode |
1784 | && GET_MODE (op0) != mode) | |
5035bbfe TG |
1785 | op0 = convert_to_mode (mode, op0, unsignedp); |
1786 | ||
77c9c6c2 RK |
1787 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
1788 | if the libcall is cse'd or moved. */ | |
9a7f678c | 1789 | value = emit_library_call_value (binoptab->handlers[(int) mode].libfunc, |
ebb1b59a | 1790 | NULL_RTX, LCT_CONST, mode, 2, |
9a7f678c | 1791 | op0, mode, op1x, op1_mode); |
77c9c6c2 RK |
1792 | |
1793 | insns = get_insns (); | |
1794 | end_sequence (); | |
1795 | ||
1796 | target = gen_reg_rtx (mode); | |
9a7f678c | 1797 | emit_libcall_block (insns, target, value, |
9e6a5703 | 1798 | gen_rtx_fmt_ee (binoptab->code, mode, op0, op1)); |
77c9c6c2 RK |
1799 | |
1800 | return target; | |
1801 | } | |
1802 | ||
1803 | delete_insns_since (last); | |
1804 | ||
1805 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
1806 | ||
1807 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
1808 | || methods == OPTAB_MUST_WIDEN)) | |
abd418d3 RS |
1809 | { |
1810 | /* Caller says, don't even try. */ | |
1811 | delete_insns_since (entry_last); | |
1812 | return 0; | |
1813 | } | |
77c9c6c2 RK |
1814 | |
1815 | /* Compute the value of METHODS to pass to recursive calls. | |
1816 | Don't allow widening to be tried recursively. */ | |
1817 | ||
1818 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
1819 | ||
34e56753 RS |
1820 | /* Look for a wider mode of the same class for which it appears we can do |
1821 | the operation. */ | |
77c9c6c2 RK |
1822 | |
1823 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
1824 | { | |
34e56753 | 1825 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
1826 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1827 | { | |
1828 | if ((binoptab->handlers[(int) wider_mode].insn_code | |
1829 | != CODE_FOR_nothing) | |
1830 | || (methods == OPTAB_LIB | |
1831 | && binoptab->handlers[(int) wider_mode].libfunc)) | |
1832 | { | |
1833 | rtx xop0 = op0, xop1 = op1; | |
1834 | int no_extend = 0; | |
1835 | ||
34e56753 | 1836 | /* For certain integer operations, we need not actually extend |
77c9c6c2 | 1837 | the narrow operands, as long as we will truncate |
835532b8 | 1838 | the results to the same narrowness. */ |
77c9c6c2 | 1839 | |
34e56753 RS |
1840 | if ((binoptab == ior_optab || binoptab == and_optab |
1841 | || binoptab == xor_optab | |
1842 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 1843 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 1844 | && class == MODE_INT) |
77c9c6c2 RK |
1845 | no_extend = 1; |
1846 | ||
0661a3de RS |
1847 | xop0 = widen_operand (xop0, wider_mode, mode, |
1848 | unsignedp, no_extend); | |
943cc242 RK |
1849 | |
1850 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 1851 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 1852 | no_extend && binoptab != ashl_optab); |
77c9c6c2 | 1853 | |
b1ec3c92 | 1854 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
77c9c6c2 RK |
1855 | unsignedp, methods); |
1856 | if (temp) | |
1857 | { | |
34e56753 | 1858 | if (class != MODE_INT) |
77c9c6c2 RK |
1859 | { |
1860 | if (target == 0) | |
1861 | target = gen_reg_rtx (mode); | |
1862 | convert_move (target, temp, 0); | |
1863 | return target; | |
1864 | } | |
1865 | else | |
1866 | return gen_lowpart (mode, temp); | |
1867 | } | |
1868 | else | |
1869 | delete_insns_since (last); | |
1870 | } | |
1871 | } | |
1872 | } | |
1873 | ||
abd418d3 | 1874 | delete_insns_since (entry_last); |
77c9c6c2 RK |
1875 | return 0; |
1876 | } | |
cb2a532e AH |
1877 | |
1878 | /* Like expand_binop, but for open-coding vectors binops. */ | |
1879 | ||
1880 | static rtx | |
0c20a65f AJ |
1881 | expand_vector_binop (enum machine_mode mode, optab binoptab, rtx op0, |
1882 | rtx op1, rtx target, int unsignedp, | |
1883 | enum optab_methods methods) | |
cb2a532e | 1884 | { |
34a80643 R |
1885 | enum machine_mode submode, tmode; |
1886 | int size, elts, subsize, subbitsize, i; | |
cb2a532e AH |
1887 | rtx t, a, b, res, seq; |
1888 | enum mode_class class; | |
1889 | ||
1890 | class = GET_MODE_CLASS (mode); | |
1891 | ||
7e1a450d | 1892 | size = GET_MODE_SIZE (mode); |
cb2a532e | 1893 | submode = GET_MODE_INNER (mode); |
cb2a532e | 1894 | |
34a80643 R |
1895 | /* Search for the widest vector mode with the same inner mode that is |
1896 | still narrower than MODE and that allows to open-code this operator. | |
1897 | Note, if we find such a mode and the handler later decides it can't | |
1898 | do the expansion, we'll be called recursively with the narrower mode. */ | |
1899 | for (tmode = GET_CLASS_NARROWEST_MODE (class); | |
1900 | GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode); | |
1901 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
1902 | { | |
1903 | if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode) | |
1904 | && binoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) | |
1905 | submode = tmode; | |
1906 | } | |
cb2a532e AH |
1907 | |
1908 | switch (binoptab->code) | |
1909 | { | |
34a80643 R |
1910 | case AND: |
1911 | case IOR: | |
1912 | case XOR: | |
1913 | tmode = int_mode_for_mode (mode); | |
1914 | if (tmode != BLKmode) | |
1915 | submode = tmode; | |
cb2a532e AH |
1916 | case PLUS: |
1917 | case MINUS: | |
1918 | case MULT: | |
1919 | case DIV: | |
34a80643 R |
1920 | subsize = GET_MODE_SIZE (submode); |
1921 | subbitsize = GET_MODE_BITSIZE (submode); | |
1922 | elts = size / subsize; | |
1923 | ||
1924 | /* If METHODS is OPTAB_DIRECT, we don't insist on the exact mode, | |
1925 | but that we operate on more than one element at a time. */ | |
1926 | if (subsize == GET_MODE_UNIT_SIZE (mode) && methods == OPTAB_DIRECT) | |
1927 | return 0; | |
1928 | ||
1929 | start_sequence (); | |
1930 | ||
1931 | /* Errors can leave us with a const0_rtx as operand. */ | |
1932 | if (GET_MODE (op0) != mode) | |
1933 | op0 = copy_to_mode_reg (mode, op0); | |
1934 | if (GET_MODE (op1) != mode) | |
1935 | op1 = copy_to_mode_reg (mode, op1); | |
1936 | ||
1937 | if (!target) | |
1938 | target = gen_reg_rtx (mode); | |
1939 | ||
cb2a532e AH |
1940 | for (i = 0; i < elts; ++i) |
1941 | { | |
34a80643 R |
1942 | /* If this is part of a register, and not the first item in the |
1943 | word, we can't store using a SUBREG - that would clobber | |
1944 | previous results. | |
1945 | And storing with a SUBREG is only possible for the least | |
1946 | significant part, hence we can't do it for big endian | |
1947 | (unless we want to permute the evaluation order. */ | |
1948 | if (GET_CODE (target) == REG | |
1949 | && (BYTES_BIG_ENDIAN | |
1950 | ? subsize < UNITS_PER_WORD | |
1951 | : ((i * subsize) % UNITS_PER_WORD) != 0)) | |
1952 | t = NULL_RTX; | |
1953 | else | |
1954 | t = simplify_gen_subreg (submode, target, mode, i * subsize); | |
1955 | if (CONSTANT_P (op0)) | |
1956 | a = simplify_gen_subreg (submode, op0, mode, i * subsize); | |
1957 | else | |
1958 | a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp, | |
1959 | NULL_RTX, submode, submode, size); | |
1960 | if (CONSTANT_P (op1)) | |
1961 | b = simplify_gen_subreg (submode, op1, mode, i * subsize); | |
1962 | else | |
1963 | b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp, | |
1964 | NULL_RTX, submode, submode, size); | |
cb2a532e AH |
1965 | |
1966 | if (binoptab->code == DIV) | |
1967 | { | |
1968 | if (class == MODE_VECTOR_FLOAT) | |
1969 | res = expand_binop (submode, binoptab, a, b, t, | |
1970 | unsignedp, methods); | |
1971 | else | |
1972 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1973 | a, b, t, unsignedp); | |
1974 | } | |
1975 | else | |
1976 | res = expand_binop (submode, binoptab, a, b, t, | |
1977 | unsignedp, methods); | |
1978 | ||
1979 | if (res == 0) | |
1980 | break; | |
1981 | ||
34a80643 R |
1982 | if (t) |
1983 | emit_move_insn (t, res); | |
1984 | else | |
1985 | store_bit_field (target, subbitsize, i * subbitsize, submode, res, | |
1986 | size); | |
cb2a532e AH |
1987 | } |
1988 | break; | |
1989 | ||
1990 | default: | |
1991 | abort (); | |
1992 | } | |
1993 | ||
1994 | seq = get_insns (); | |
1995 | end_sequence (); | |
1996 | emit_insn (seq); | |
1997 | ||
1998 | return target; | |
1999 | } | |
2000 | ||
2001 | /* Like expand_unop but for open-coding vector unops. */ | |
2002 | ||
2003 | static rtx | |
0c20a65f AJ |
2004 | expand_vector_unop (enum machine_mode mode, optab unoptab, rtx op0, |
2005 | rtx target, int unsignedp) | |
cb2a532e | 2006 | { |
34a80643 R |
2007 | enum machine_mode submode, tmode; |
2008 | int size, elts, subsize, subbitsize, i; | |
cb2a532e AH |
2009 | rtx t, a, res, seq; |
2010 | ||
7e1a450d | 2011 | size = GET_MODE_SIZE (mode); |
cb2a532e | 2012 | submode = GET_MODE_INNER (mode); |
34a80643 R |
2013 | |
2014 | /* Search for the widest vector mode with the same inner mode that is | |
2015 | still narrower than MODE and that allows to open-code this operator. | |
2016 | Note, if we find such a mode and the handler later decides it can't | |
2017 | do the expansion, we'll be called recursively with the narrower mode. */ | |
2018 | for (tmode = GET_CLASS_NARROWEST_MODE (GET_MODE_CLASS (mode)); | |
2019 | GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode); | |
2020 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
2021 | { | |
2022 | if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode) | |
2023 | && unoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) | |
2024 | submode = tmode; | |
2025 | } | |
2026 | /* If there is no negate operation, try doing a subtract from zero. */ | |
0d541696 R |
2027 | if (unoptab == neg_optab && GET_MODE_CLASS (submode) == MODE_INT |
2028 | /* Avoid infinite recursion when an | |
2029 | error has left us with the wrong mode. */ | |
2030 | && GET_MODE (op0) == mode) | |
0c20a65f | 2031 | { |
34a80643 R |
2032 | rtx temp; |
2033 | temp = expand_binop (mode, sub_optab, CONST0_RTX (mode), op0, | |
2034 | target, unsignedp, OPTAB_DIRECT); | |
2035 | if (temp) | |
2036 | return temp; | |
2037 | } | |
2038 | ||
2039 | if (unoptab == one_cmpl_optab) | |
2040 | { | |
2041 | tmode = int_mode_for_mode (mode); | |
2042 | if (tmode != BLKmode) | |
2043 | submode = tmode; | |
2044 | } | |
2045 | ||
2046 | subsize = GET_MODE_SIZE (submode); | |
2047 | subbitsize = GET_MODE_BITSIZE (submode); | |
2048 | elts = size / subsize; | |
2049 | ||
2050 | /* Errors can leave us with a const0_rtx as operand. */ | |
2051 | if (GET_MODE (op0) != mode) | |
2052 | op0 = copy_to_mode_reg (mode, op0); | |
cb2a532e AH |
2053 | |
2054 | if (!target) | |
2055 | target = gen_reg_rtx (mode); | |
2056 | ||
2057 | start_sequence (); | |
2058 | ||
cb2a532e AH |
2059 | for (i = 0; i < elts; ++i) |
2060 | { | |
34a80643 R |
2061 | /* If this is part of a register, and not the first item in the |
2062 | word, we can't store using a SUBREG - that would clobber | |
2063 | previous results. | |
2064 | And storing with a SUBREG is only possible for the least | |
2065 | significant part, hence we can't do it for big endian | |
2066 | (unless we want to permute the evaluation order. */ | |
2067 | if (GET_CODE (target) == REG | |
2068 | && (BYTES_BIG_ENDIAN | |
2069 | ? subsize < UNITS_PER_WORD | |
2070 | : ((i * subsize) % UNITS_PER_WORD) != 0)) | |
2071 | t = NULL_RTX; | |
2072 | else | |
2073 | t = simplify_gen_subreg (submode, target, mode, i * subsize); | |
2074 | if (CONSTANT_P (op0)) | |
2075 | a = simplify_gen_subreg (submode, op0, mode, i * subsize); | |
2076 | else | |
2077 | a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp, | |
2078 | t, submode, submode, size); | |
cb2a532e AH |
2079 | |
2080 | res = expand_unop (submode, unoptab, a, t, unsignedp); | |
2081 | ||
34a80643 R |
2082 | if (t) |
2083 | emit_move_insn (t, res); | |
2084 | else | |
2085 | store_bit_field (target, subbitsize, i * subbitsize, submode, res, | |
2086 | size); | |
cb2a532e AH |
2087 | } |
2088 | ||
2089 | seq = get_insns (); | |
2090 | end_sequence (); | |
2091 | emit_insn (seq); | |
2092 | ||
2093 | return target; | |
2094 | } | |
77c9c6c2 RK |
2095 | \f |
2096 | /* Expand a binary operator which has both signed and unsigned forms. | |
2097 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2098 | signed operations. | |
2099 | ||
2100 | If we widen unsigned operands, we may use a signed wider operation instead | |
2101 | of an unsigned wider operation, since the result would be the same. */ | |
2102 | ||
2103 | rtx | |
0c20a65f AJ |
2104 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2105 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2106 | enum optab_methods methods) | |
77c9c6c2 | 2107 | { |
b3694847 | 2108 | rtx temp; |
77c9c6c2 RK |
2109 | optab direct_optab = unsignedp ? uoptab : soptab; |
2110 | struct optab wide_soptab; | |
2111 | ||
2112 | /* Do it without widening, if possible. */ | |
2113 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2114 | unsignedp, OPTAB_DIRECT); | |
2115 | if (temp || methods == OPTAB_DIRECT) | |
2116 | return temp; | |
2117 | ||
2118 | /* Try widening to a signed int. Make a fake signed optab that | |
2119 | hides any signed insn for direct use. */ | |
2120 | wide_soptab = *soptab; | |
2121 | wide_soptab.handlers[(int) mode].insn_code = CODE_FOR_nothing; | |
2122 | wide_soptab.handlers[(int) mode].libfunc = 0; | |
2123 | ||
2124 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2125 | unsignedp, OPTAB_WIDEN); | |
2126 | ||
2127 | /* For unsigned operands, try widening to an unsigned int. */ | |
2128 | if (temp == 0 && unsignedp) | |
2129 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
2130 | unsignedp, OPTAB_WIDEN); | |
2131 | if (temp || methods == OPTAB_WIDEN) | |
2132 | return temp; | |
2133 | ||
2134 | /* Use the right width lib call if that exists. */ | |
2135 | temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); | |
2136 | if (temp || methods == OPTAB_LIB) | |
2137 | return temp; | |
2138 | ||
2139 | /* Must widen and use a lib call, use either signed or unsigned. */ | |
2140 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2141 | unsignedp, methods); | |
2142 | if (temp != 0) | |
2143 | return temp; | |
2144 | if (unsignedp) | |
2145 | return expand_binop (mode, uoptab, op0, op1, target, | |
2146 | unsignedp, methods); | |
2147 | return 0; | |
2148 | } | |
2149 | \f | |
6c7cf1f0 UB |
2150 | /* Generate code to perform an operation specified by UNOPPTAB |
2151 | on operand OP0, with two results to TARG0 and TARG1. | |
2152 | We assume that the order of the operands for the instruction | |
2153 | is TARG0, TARG1, OP0. | |
2154 | ||
2155 | Either TARG0 or TARG1 may be zero, but what that means is that | |
2156 | the result is not actually wanted. We will generate it into | |
2157 | a dummy pseudo-reg and discard it. They may not both be zero. | |
2158 | ||
2159 | Returns 1 if this operation can be performed; 0 if not. */ | |
2160 | ||
2161 | int | |
2162 | expand_twoval_unop (optab unoptab, rtx targ0, rtx targ1, rtx op0, | |
2163 | int unsignedp) | |
2164 | { | |
2165 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
2166 | enum mode_class class; | |
2167 | enum machine_mode wider_mode; | |
2168 | rtx entry_last = get_last_insn (); | |
2169 | rtx last; | |
2170 | ||
2171 | class = GET_MODE_CLASS (mode); | |
2172 | ||
2173 | op0 = protect_from_queue (op0, 0); | |
2174 | ||
2175 | if (flag_force_mem) | |
2176 | { | |
2177 | op0 = force_not_mem (op0); | |
2178 | } | |
2179 | ||
2180 | if (targ0) | |
2181 | targ0 = protect_from_queue (targ0, 1); | |
2182 | else | |
2183 | targ0 = gen_reg_rtx (mode); | |
2184 | if (targ1) | |
2185 | targ1 = protect_from_queue (targ1, 1); | |
2186 | else | |
2187 | targ1 = gen_reg_rtx (mode); | |
2188 | ||
2189 | /* Record where to go back to if we fail. */ | |
2190 | last = get_last_insn (); | |
2191 | ||
2192 | if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2193 | { | |
2194 | int icode = (int) unoptab->handlers[(int) mode].insn_code; | |
2195 | enum machine_mode mode0 = insn_data[icode].operand[2].mode; | |
2196 | rtx pat; | |
2197 | rtx xop0 = op0; | |
2198 | ||
2199 | if (GET_MODE (xop0) != VOIDmode | |
2200 | && GET_MODE (xop0) != mode0) | |
2201 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2202 | ||
2203 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
2204 | if (! (*insn_data[icode].operand[2].predicate) (xop0, mode0)) | |
2205 | xop0 = copy_to_mode_reg (mode0, xop0); | |
2206 | ||
2207 | /* We could handle this, but we should always be called with a pseudo | |
2208 | for our targets and all insns should take them as outputs. */ | |
2209 | if (! (*insn_data[icode].operand[0].predicate) (targ0, mode) | |
2210 | || ! (*insn_data[icode].operand[1].predicate) (targ1, mode)) | |
2211 | abort (); | |
2212 | ||
2213 | pat = GEN_FCN (icode) (targ0, targ1, xop0); | |
2214 | if (pat) | |
2215 | { | |
2216 | emit_insn (pat); | |
2217 | return 1; | |
2218 | } | |
2219 | else | |
2220 | delete_insns_since (last); | |
2221 | } | |
2222 | ||
2223 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2224 | ||
2225 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2226 | { | |
2227 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2228 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2229 | { | |
2230 | if (unoptab->handlers[(int) wider_mode].insn_code | |
2231 | != CODE_FOR_nothing) | |
2232 | { | |
2233 | rtx t0 = gen_reg_rtx (wider_mode); | |
2234 | rtx t1 = gen_reg_rtx (wider_mode); | |
2235 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); | |
2236 | ||
2237 | if (expand_twoval_unop (unoptab, t0, t1, cop0, unsignedp)) | |
2238 | { | |
2239 | convert_move (targ0, t0, unsignedp); | |
2240 | convert_move (targ1, t1, unsignedp); | |
2241 | return 1; | |
2242 | } | |
2243 | else | |
2244 | delete_insns_since (last); | |
2245 | } | |
2246 | } | |
2247 | } | |
2248 | ||
2249 | delete_insns_since (entry_last); | |
2250 | return 0; | |
2251 | } | |
2252 | \f | |
77c9c6c2 RK |
2253 | /* Generate code to perform an operation specified by BINOPTAB |
2254 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2255 | We assume that the order of the operands for the instruction | |
2256 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2257 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2258 | ||
2259 | Either TARG0 or TARG1 may be zero, but what that means is that | |
38e01259 | 2260 | the result is not actually wanted. We will generate it into |
77c9c6c2 RK |
2261 | a dummy pseudo-reg and discard it. They may not both be zero. |
2262 | ||
2263 | Returns 1 if this operation can be performed; 0 if not. */ | |
2264 | ||
2265 | int | |
0c20a65f AJ |
2266 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2267 | int unsignedp) | |
77c9c6c2 RK |
2268 | { |
2269 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
2270 | enum mode_class class; | |
2271 | enum machine_mode wider_mode; | |
abd418d3 | 2272 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
2273 | rtx last; |
2274 | ||
2275 | class = GET_MODE_CLASS (mode); | |
2276 | ||
2277 | op0 = protect_from_queue (op0, 0); | |
2278 | op1 = protect_from_queue (op1, 0); | |
2279 | ||
2280 | if (flag_force_mem) | |
2281 | { | |
2282 | op0 = force_not_mem (op0); | |
2283 | op1 = force_not_mem (op1); | |
2284 | } | |
2285 | ||
2286 | /* If we are inside an appropriately-short loop and one operand is an | |
2287 | expensive constant, force it into a register. */ | |
aeedc93f | 2288 | if (CONSTANT_P (op0) && preserve_subexpressions_p () |
b437f1a7 | 2289 | && rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
2290 | op0 = force_reg (mode, op0); |
2291 | ||
aeedc93f | 2292 | if (CONSTANT_P (op1) && preserve_subexpressions_p () |
b437f1a7 | 2293 | && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
2294 | op1 = force_reg (mode, op1); |
2295 | ||
2296 | if (targ0) | |
2297 | targ0 = protect_from_queue (targ0, 1); | |
2298 | else | |
2299 | targ0 = gen_reg_rtx (mode); | |
2300 | if (targ1) | |
2301 | targ1 = protect_from_queue (targ1, 1); | |
2302 | else | |
2303 | targ1 = gen_reg_rtx (mode); | |
2304 | ||
2305 | /* Record where to go back to if we fail. */ | |
2306 | last = get_last_insn (); | |
2307 | ||
2308 | if (binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2309 | { | |
2310 | int icode = (int) binoptab->handlers[(int) mode].insn_code; | |
a995e389 RH |
2311 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2312 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
2313 | rtx pat; |
2314 | rtx xop0 = op0, xop1 = op1; | |
2315 | ||
874f6a6d EB |
2316 | /* In case the insn wants input operands in modes different from |
2317 | those of the actual operands, convert the operands. It would | |
2318 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
2319 | that they're properly zero-extended, sign-extended or truncated |
2320 | for their mode. */ | |
77c9c6c2 | 2321 | |
874f6a6d EB |
2322 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
2323 | xop0 = convert_modes (mode0, | |
2324 | GET_MODE (op0) != VOIDmode | |
2325 | ? GET_MODE (op0) | |
2326 | : mode, | |
2327 | xop0, unsignedp); | |
2328 | ||
2329 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
2330 | xop1 = convert_modes (mode1, | |
2331 | GET_MODE (op1) != VOIDmode | |
2332 | ? GET_MODE (op1) | |
2333 | : mode, | |
2334 | xop1, unsignedp); | |
77c9c6c2 RK |
2335 | |
2336 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
a995e389 | 2337 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
77c9c6c2 RK |
2338 | xop0 = copy_to_mode_reg (mode0, xop0); |
2339 | ||
a995e389 | 2340 | if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1)) |
77c9c6c2 RK |
2341 | xop1 = copy_to_mode_reg (mode1, xop1); |
2342 | ||
2343 | /* We could handle this, but we should always be called with a pseudo | |
2344 | for our targets and all insns should take them as outputs. */ | |
a995e389 RH |
2345 | if (! (*insn_data[icode].operand[0].predicate) (targ0, mode) |
2346 | || ! (*insn_data[icode].operand[3].predicate) (targ1, mode)) | |
77c9c6c2 | 2347 | abort (); |
0c20a65f | 2348 | |
77c9c6c2 RK |
2349 | pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1); |
2350 | if (pat) | |
2351 | { | |
2352 | emit_insn (pat); | |
2353 | return 1; | |
2354 | } | |
2355 | else | |
2356 | delete_insns_since (last); | |
2357 | } | |
2358 | ||
2359 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2360 | ||
2361 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2362 | { | |
34e56753 | 2363 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
2364 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2365 | { | |
2366 | if (binoptab->handlers[(int) wider_mode].insn_code | |
2367 | != CODE_FOR_nothing) | |
2368 | { | |
b3694847 SS |
2369 | rtx t0 = gen_reg_rtx (wider_mode); |
2370 | rtx t1 = gen_reg_rtx (wider_mode); | |
76791f3d JH |
2371 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2372 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
77c9c6c2 | 2373 | |
76791f3d | 2374 | if (expand_twoval_binop (binoptab, cop0, cop1, |
77c9c6c2 RK |
2375 | t0, t1, unsignedp)) |
2376 | { | |
2377 | convert_move (targ0, t0, unsignedp); | |
2378 | convert_move (targ1, t1, unsignedp); | |
2379 | return 1; | |
2380 | } | |
2381 | else | |
2382 | delete_insns_since (last); | |
2383 | } | |
2384 | } | |
2385 | } | |
2386 | ||
abd418d3 | 2387 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2388 | return 0; |
2389 | } | |
2390 | \f | |
ef89d648 ZW |
2391 | /* Wrapper around expand_unop which takes an rtx code to specify |
2392 | the operation to perform, not an optab pointer. All other | |
2393 | arguments are the same. */ | |
2394 | rtx | |
0c20a65f AJ |
2395 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2396 | rtx target, int unsignedp) | |
ef89d648 | 2397 | { |
7e1a450d | 2398 | optab unop = code_to_optab[(int) code]; |
ef89d648 ZW |
2399 | if (unop == 0) |
2400 | abort (); | |
2401 | ||
2402 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2403 | } | |
2404 | ||
2928cd7a RH |
2405 | /* Try calculating |
2406 | (clz:narrow x) | |
2407 | as | |
2408 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */ | |
2409 | static rtx | |
0c20a65f | 2410 | widen_clz (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2411 | { |
2412 | enum mode_class class = GET_MODE_CLASS (mode); | |
2413 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2414 | { | |
2415 | enum machine_mode wider_mode; | |
2416 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2417 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2418 | { | |
2419 | if (clz_optab->handlers[(int) wider_mode].insn_code | |
2420 | != CODE_FOR_nothing) | |
2421 | { | |
2422 | rtx xop0, temp, last; | |
2423 | ||
2424 | last = get_last_insn (); | |
2425 | ||
2426 | if (target == 0) | |
2427 | target = gen_reg_rtx (mode); | |
2428 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2429 | temp = expand_unop (wider_mode, clz_optab, xop0, NULL_RTX, true); | |
2430 | if (temp != 0) | |
2431 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2432 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2433 | - GET_MODE_BITSIZE (mode)), | |
2434 | target, true, OPTAB_DIRECT); | |
2435 | if (temp == 0) | |
2436 | delete_insns_since (last); | |
2437 | ||
2438 | return temp; | |
2439 | } | |
2440 | } | |
2441 | } | |
2442 | return 0; | |
2443 | } | |
2444 | ||
2445 | /* Try calculating (parity x) as (and (popcount x) 1), where | |
2446 | popcount can also be done in a wider mode. */ | |
2447 | static rtx | |
0c20a65f | 2448 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2449 | { |
2450 | enum mode_class class = GET_MODE_CLASS (mode); | |
2451 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2452 | { | |
2453 | enum machine_mode wider_mode; | |
2454 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2455 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2456 | { | |
2457 | if (popcount_optab->handlers[(int) wider_mode].insn_code | |
2458 | != CODE_FOR_nothing) | |
2459 | { | |
2460 | rtx xop0, temp, last; | |
2461 | ||
2462 | last = get_last_insn (); | |
2463 | ||
2464 | if (target == 0) | |
2465 | target = gen_reg_rtx (mode); | |
2466 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2467 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2468 | true); | |
2469 | if (temp != 0) | |
60c81c89 | 2470 | temp = expand_binop (wider_mode, and_optab, temp, const1_rtx, |
2928cd7a RH |
2471 | target, true, OPTAB_DIRECT); |
2472 | if (temp == 0) | |
2473 | delete_insns_since (last); | |
2474 | ||
2475 | return temp; | |
2476 | } | |
2477 | } | |
2478 | } | |
2479 | return 0; | |
2480 | } | |
2481 | ||
77c9c6c2 RK |
2482 | /* Generate code to perform an operation specified by UNOPTAB |
2483 | on operand OP0, with result having machine-mode MODE. | |
2484 | ||
2485 | UNSIGNEDP is for the case where we have to widen the operands | |
2486 | to perform the operation. It says to use zero-extension. | |
2487 | ||
2488 | If TARGET is nonzero, the value | |
2489 | is generated there, if it is convenient to do so. | |
2490 | In all cases an rtx is returned for the locus of the value; | |
2491 | this may or may not be TARGET. */ | |
2492 | ||
2493 | rtx | |
0c20a65f AJ |
2494 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, |
2495 | int unsignedp) | |
77c9c6c2 RK |
2496 | { |
2497 | enum mode_class class; | |
2498 | enum machine_mode wider_mode; | |
b3694847 | 2499 | rtx temp; |
77c9c6c2 RK |
2500 | rtx last = get_last_insn (); |
2501 | rtx pat; | |
2502 | ||
2503 | class = GET_MODE_CLASS (mode); | |
2504 | ||
2505 | op0 = protect_from_queue (op0, 0); | |
2506 | ||
2507 | if (flag_force_mem) | |
2508 | { | |
2509 | op0 = force_not_mem (op0); | |
2510 | } | |
2511 | ||
2512 | if (target) | |
2513 | target = protect_from_queue (target, 1); | |
2514 | ||
2515 | if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2516 | { | |
2517 | int icode = (int) unoptab->handlers[(int) mode].insn_code; | |
a995e389 | 2518 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 RK |
2519 | rtx xop0 = op0; |
2520 | ||
2521 | if (target) | |
2522 | temp = target; | |
2523 | else | |
2524 | temp = gen_reg_rtx (mode); | |
2525 | ||
2526 | if (GET_MODE (xop0) != VOIDmode | |
2527 | && GET_MODE (xop0) != mode0) | |
2528 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2529 | ||
2530 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
2531 | ||
a995e389 | 2532 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
77c9c6c2 RK |
2533 | xop0 = copy_to_mode_reg (mode0, xop0); |
2534 | ||
a995e389 | 2535 | if (! (*insn_data[icode].operand[0].predicate) (temp, mode)) |
77c9c6c2 RK |
2536 | temp = gen_reg_rtx (mode); |
2537 | ||
2538 | pat = GEN_FCN (icode) (temp, xop0); | |
2539 | if (pat) | |
2540 | { | |
2f937369 | 2541 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
b1ec3c92 | 2542 | && ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX)) |
77c9c6c2 RK |
2543 | { |
2544 | delete_insns_since (last); | |
b1ec3c92 | 2545 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
77c9c6c2 RK |
2546 | } |
2547 | ||
2548 | emit_insn (pat); | |
0c20a65f | 2549 | |
77c9c6c2 RK |
2550 | return temp; |
2551 | } | |
2552 | else | |
2553 | delete_insns_since (last); | |
2554 | } | |
2555 | ||
9a856ec7 RK |
2556 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
2557 | ||
2928cd7a RH |
2558 | /* Widening clz needs special treatment. */ |
2559 | if (unoptab == clz_optab) | |
2560 | { | |
2561 | temp = widen_clz (mode, op0, target); | |
2562 | if (temp) | |
2563 | return temp; | |
2564 | else | |
2565 | goto try_libcall; | |
2566 | } | |
2567 | ||
9a856ec7 RK |
2568 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) |
2569 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2570 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2571 | { | |
2572 | if (unoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing) | |
2573 | { | |
2574 | rtx xop0 = op0; | |
2575 | ||
2576 | /* For certain operations, we need not actually extend | |
2577 | the narrow operand, as long as we will truncate the | |
835532b8 RK |
2578 | results to the same narrowness. */ |
2579 | ||
0661a3de | 2580 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
2581 | (unoptab == neg_optab |
2582 | || unoptab == one_cmpl_optab) | |
2583 | && class == MODE_INT); | |
0c20a65f | 2584 | |
b1ec3c92 CH |
2585 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
2586 | unsignedp); | |
9a856ec7 RK |
2587 | |
2588 | if (temp) | |
2589 | { | |
2590 | if (class != MODE_INT) | |
2591 | { | |
2592 | if (target == 0) | |
2593 | target = gen_reg_rtx (mode); | |
2594 | convert_move (target, temp, 0); | |
2595 | return target; | |
2596 | } | |
2597 | else | |
2598 | return gen_lowpart (mode, temp); | |
2599 | } | |
2600 | else | |
2601 | delete_insns_since (last); | |
2602 | } | |
2603 | } | |
2604 | ||
77c9c6c2 RK |
2605 | /* These can be done a word at a time. */ |
2606 | if (unoptab == one_cmpl_optab | |
2607 | && class == MODE_INT | |
2608 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
34e56753 | 2609 | && unoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 2610 | { |
bb93b973 | 2611 | int i; |
77c9c6c2 RK |
2612 | rtx insns; |
2613 | ||
2614 | if (target == 0 || target == op0) | |
2615 | target = gen_reg_rtx (mode); | |
2616 | ||
2617 | start_sequence (); | |
2618 | ||
2619 | /* Do the actual arithmetic. */ | |
2620 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
2621 | { | |
2622 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 2623 | rtx x = expand_unop (word_mode, unoptab, |
77c9c6c2 RK |
2624 | operand_subword_force (op0, i, mode), |
2625 | target_piece, unsignedp); | |
bb93b973 | 2626 | |
77c9c6c2 RK |
2627 | if (target_piece != x) |
2628 | emit_move_insn (target_piece, x); | |
2629 | } | |
2630 | ||
2631 | insns = get_insns (); | |
2632 | end_sequence (); | |
2633 | ||
b1ec3c92 | 2634 | emit_no_conflict_block (insns, target, op0, NULL_RTX, |
9e6a5703 JC |
2635 | gen_rtx_fmt_e (unoptab->code, mode, |
2636 | copy_rtx (op0))); | |
77c9c6c2 RK |
2637 | return target; |
2638 | } | |
2639 | ||
139e5e08 | 2640 | /* Open-code the complex negation operation. */ |
91ce572a | 2641 | else if (unoptab->code == NEG |
139e5e08 RS |
2642 | && (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT)) |
2643 | { | |
2644 | rtx target_piece; | |
2645 | rtx x; | |
2646 | rtx seq; | |
2647 | ||
f9da5064 | 2648 | /* Find the correct mode for the real and imaginary parts. */ |
27e58a70 | 2649 | enum machine_mode submode = GET_MODE_INNER (mode); |
139e5e08 RS |
2650 | |
2651 | if (submode == BLKmode) | |
2652 | abort (); | |
2653 | ||
2654 | if (target == 0) | |
2655 | target = gen_reg_rtx (mode); | |
0c20a65f | 2656 | |
139e5e08 RS |
2657 | start_sequence (); |
2658 | ||
decdfa82 | 2659 | target_piece = gen_imagpart (submode, target); |
139e5e08 | 2660 | x = expand_unop (submode, unoptab, |
decdfa82 | 2661 | gen_imagpart (submode, op0), |
139e5e08 RS |
2662 | target_piece, unsignedp); |
2663 | if (target_piece != x) | |
2664 | emit_move_insn (target_piece, x); | |
2665 | ||
decdfa82 | 2666 | target_piece = gen_realpart (submode, target); |
139e5e08 | 2667 | x = expand_unop (submode, unoptab, |
decdfa82 | 2668 | gen_realpart (submode, op0), |
139e5e08 RS |
2669 | target_piece, unsignedp); |
2670 | if (target_piece != x) | |
2671 | emit_move_insn (target_piece, x); | |
2672 | ||
a29b481b | 2673 | seq = get_insns (); |
139e5e08 RS |
2674 | end_sequence (); |
2675 | ||
2676 | emit_no_conflict_block (seq, target, op0, 0, | |
9e6a5703 JC |
2677 | gen_rtx_fmt_e (unoptab->code, mode, |
2678 | copy_rtx (op0))); | |
139e5e08 RS |
2679 | return target; |
2680 | } | |
2681 | ||
4977bab6 ZW |
2682 | /* Try negating floating point values by flipping the sign bit. */ |
2683 | if (unoptab->code == NEG && class == MODE_FLOAT | |
2684 | && GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT) | |
2685 | { | |
70a01792 | 2686 | const struct real_format *fmt = REAL_MODE_FORMAT (mode); |
4977bab6 ZW |
2687 | enum machine_mode imode = int_mode_for_mode (mode); |
2688 | int bitpos = (fmt != 0) ? fmt->signbit : -1; | |
2689 | ||
2690 | if (imode != BLKmode && bitpos >= 0 && fmt->has_signed_zero) | |
2691 | { | |
2692 | HOST_WIDE_INT hi, lo; | |
2693 | rtx last = get_last_insn (); | |
2694 | ||
9ee0a442 RS |
2695 | /* Handle targets with different FP word orders. */ |
2696 | if (FLOAT_WORDS_BIG_ENDIAN != WORDS_BIG_ENDIAN) | |
2697 | { | |
2698 | int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
2699 | int word = nwords - (bitpos / BITS_PER_WORD) - 1; | |
2700 | bitpos = word * BITS_PER_WORD + bitpos % BITS_PER_WORD; | |
2701 | } | |
2702 | ||
4977bab6 ZW |
2703 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
2704 | { | |
2705 | hi = 0; | |
2706 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2707 | } | |
2708 | else | |
2709 | { | |
2710 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
2711 | lo = 0; | |
2712 | } | |
2713 | temp = expand_binop (imode, xor_optab, | |
2714 | gen_lowpart (imode, op0), | |
2715 | immed_double_const (lo, hi, imode), | |
2716 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
2717 | if (temp != 0) | |
dd0ba281 RS |
2718 | { |
2719 | rtx insn; | |
2720 | if (target == 0) | |
2721 | target = gen_reg_rtx (mode); | |
2722 | insn = emit_move_insn (target, gen_lowpart (mode, temp)); | |
2723 | set_unique_reg_note (insn, REG_EQUAL, | |
2724 | gen_rtx_fmt_e (NEG, mode, | |
2725 | copy_rtx (op0))); | |
2726 | return target; | |
2727 | } | |
4977bab6 ZW |
2728 | delete_insns_since (last); |
2729 | } | |
2730 | } | |
2731 | ||
2928cd7a RH |
2732 | /* Try calculating parity (x) as popcount (x) % 2. */ |
2733 | if (unoptab == parity_optab) | |
2734 | { | |
2735 | temp = expand_parity (mode, op0, target); | |
2736 | if (temp) | |
2737 | return temp; | |
2738 | } | |
2739 | ||
2740 | try_libcall: | |
139e5e08 | 2741 | /* Now try a library call in this mode. */ |
77c9c6c2 RK |
2742 | if (unoptab->handlers[(int) mode].libfunc) |
2743 | { | |
2744 | rtx insns; | |
9a7f678c | 2745 | rtx value; |
2928cd7a RH |
2746 | enum machine_mode outmode = mode; |
2747 | ||
2748 | /* All of these functions return small values. Thus we choose to | |
2749 | have them return something that isn't a double-word. */ | |
2750 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
2751 | || unoptab == popcount_optab || unoptab == parity_optab) | |
cd2ac05b FH |
2752 | outmode |
2753 | = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node))); | |
77c9c6c2 RK |
2754 | |
2755 | start_sequence (); | |
2756 | ||
2757 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
2758 | if the libcall is cse'd or moved. */ | |
9a7f678c | 2759 | value = emit_library_call_value (unoptab->handlers[(int) mode].libfunc, |
2928cd7a RH |
2760 | NULL_RTX, LCT_CONST, outmode, |
2761 | 1, op0, mode); | |
77c9c6c2 RK |
2762 | insns = get_insns (); |
2763 | end_sequence (); | |
2764 | ||
2928cd7a | 2765 | target = gen_reg_rtx (outmode); |
9a7f678c | 2766 | emit_libcall_block (insns, target, value, |
9e6a5703 | 2767 | gen_rtx_fmt_e (unoptab->code, mode, op0)); |
77c9c6c2 RK |
2768 | |
2769 | return target; | |
2770 | } | |
2771 | ||
cb2a532e AH |
2772 | if (class == MODE_VECTOR_FLOAT || class == MODE_VECTOR_INT) |
2773 | return expand_vector_unop (mode, unoptab, op0, target, unsignedp); | |
2774 | ||
77c9c6c2 RK |
2775 | /* It can't be done in this mode. Can we do it in a wider mode? */ |
2776 | ||
2777 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2778 | { | |
34e56753 | 2779 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
2780 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2781 | { | |
2782 | if ((unoptab->handlers[(int) wider_mode].insn_code | |
2783 | != CODE_FOR_nothing) | |
2784 | || unoptab->handlers[(int) wider_mode].libfunc) | |
2785 | { | |
34e56753 RS |
2786 | rtx xop0 = op0; |
2787 | ||
2788 | /* For certain operations, we need not actually extend | |
2789 | the narrow operand, as long as we will truncate the | |
2790 | results to the same narrowness. */ | |
2791 | ||
0661a3de | 2792 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
2793 | (unoptab == neg_optab |
2794 | || unoptab == one_cmpl_optab) | |
2795 | && class == MODE_INT); | |
0c20a65f | 2796 | |
b1ec3c92 CH |
2797 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
2798 | unsignedp); | |
34e56753 | 2799 | |
c117dddc KH |
2800 | /* If we are generating clz using wider mode, adjust the |
2801 | result. */ | |
2802 | if (unoptab == clz_optab && temp != 0) | |
2803 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2804 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2805 | - GET_MODE_BITSIZE (mode)), | |
2806 | target, true, OPTAB_DIRECT); | |
2807 | ||
34e56753 | 2808 | if (temp) |
77c9c6c2 | 2809 | { |
34e56753 RS |
2810 | if (class != MODE_INT) |
2811 | { | |
2812 | if (target == 0) | |
2813 | target = gen_reg_rtx (mode); | |
2814 | convert_move (target, temp, 0); | |
2815 | return target; | |
2816 | } | |
2817 | else | |
2818 | return gen_lowpart (mode, temp); | |
77c9c6c2 RK |
2819 | } |
2820 | else | |
34e56753 | 2821 | delete_insns_since (last); |
77c9c6c2 RK |
2822 | } |
2823 | } | |
2824 | } | |
2825 | ||
b82b6eea DE |
2826 | /* If there is no negate operation, try doing a subtract from zero. |
2827 | The US Software GOFAST library needs this. */ | |
91ce572a | 2828 | if (unoptab->code == NEG) |
0c20a65f | 2829 | { |
b82b6eea | 2830 | rtx temp; |
91ce572a CC |
2831 | temp = expand_binop (mode, |
2832 | unoptab == negv_optab ? subv_optab : sub_optab, | |
2833 | CONST0_RTX (mode), op0, | |
2834 | target, unsignedp, OPTAB_LIB_WIDEN); | |
b82b6eea DE |
2835 | if (temp) |
2836 | return temp; | |
2837 | } | |
0c20a65f | 2838 | |
77c9c6c2 RK |
2839 | return 0; |
2840 | } | |
2841 | \f | |
decdfa82 RS |
2842 | /* Emit code to compute the absolute value of OP0, with result to |
2843 | TARGET if convenient. (TARGET may be 0.) The return value says | |
2844 | where the result actually is to be found. | |
2845 | ||
2846 | MODE is the mode of the operand; the mode of the result is | |
2847 | different but can be deduced from MODE. | |
2848 | ||
91813b28 | 2849 | */ |
7fd01431 RK |
2850 | |
2851 | rtx | |
0c20a65f AJ |
2852 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
2853 | int result_unsignedp) | |
7fd01431 | 2854 | { |
2ef0a555 | 2855 | rtx temp; |
7fd01431 | 2856 | |
91ce572a CC |
2857 | if (! flag_trapv) |
2858 | result_unsignedp = 1; | |
2859 | ||
7fd01431 | 2860 | /* First try to do it with a special abs instruction. */ |
91ce572a CC |
2861 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
2862 | op0, target, 0); | |
7fd01431 RK |
2863 | if (temp != 0) |
2864 | return temp; | |
2865 | ||
4977bab6 ZW |
2866 | /* For floating point modes, try clearing the sign bit. */ |
2867 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2868 | && GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT) | |
2869 | { | |
70a01792 | 2870 | const struct real_format *fmt = REAL_MODE_FORMAT (mode); |
4977bab6 ZW |
2871 | enum machine_mode imode = int_mode_for_mode (mode); |
2872 | int bitpos = (fmt != 0) ? fmt->signbit : -1; | |
2873 | ||
2874 | if (imode != BLKmode && bitpos >= 0) | |
2875 | { | |
2876 | HOST_WIDE_INT hi, lo; | |
2877 | rtx last = get_last_insn (); | |
2878 | ||
9ee0a442 RS |
2879 | /* Handle targets with different FP word orders. */ |
2880 | if (FLOAT_WORDS_BIG_ENDIAN != WORDS_BIG_ENDIAN) | |
2881 | { | |
2882 | int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
2883 | int word = nwords - (bitpos / BITS_PER_WORD) - 1; | |
2884 | bitpos = word * BITS_PER_WORD + bitpos % BITS_PER_WORD; | |
2885 | } | |
2886 | ||
4977bab6 ZW |
2887 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
2888 | { | |
2889 | hi = 0; | |
2890 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2891 | } | |
2892 | else | |
2893 | { | |
2894 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
2895 | lo = 0; | |
2896 | } | |
2897 | temp = expand_binop (imode, and_optab, | |
2898 | gen_lowpart (imode, op0), | |
2899 | immed_double_const (~lo, ~hi, imode), | |
2900 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
2901 | if (temp != 0) | |
dd0ba281 RS |
2902 | { |
2903 | rtx insn; | |
2904 | if (target == 0) | |
2905 | target = gen_reg_rtx (mode); | |
2906 | insn = emit_move_insn (target, gen_lowpart (mode, temp)); | |
2907 | set_unique_reg_note (insn, REG_EQUAL, | |
2908 | gen_rtx_fmt_e (ABS, mode, | |
2909 | copy_rtx (op0))); | |
2910 | return target; | |
2911 | } | |
4977bab6 ZW |
2912 | delete_insns_since (last); |
2913 | } | |
2914 | } | |
2915 | ||
14a774a9 RK |
2916 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
2917 | if (smax_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2918 | { | |
2919 | rtx last = get_last_insn (); | |
2920 | ||
2921 | temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); | |
2922 | if (temp != 0) | |
2923 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
2924 | OPTAB_WIDEN); | |
2925 | ||
2926 | if (temp != 0) | |
2927 | return temp; | |
2928 | ||
2929 | delete_insns_since (last); | |
2930 | } | |
2931 | ||
7fd01431 RK |
2932 | /* If this machine has expensive jumps, we can do integer absolute |
2933 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
e1078cfc | 2934 | where W is the width of MODE. */ |
7fd01431 RK |
2935 | |
2936 | if (GET_MODE_CLASS (mode) == MODE_INT && BRANCH_COST >= 2) | |
2937 | { | |
2938 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
2939 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
2940 | NULL_RTX, 0); | |
2941 | ||
2942 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
2943 | OPTAB_LIB_WIDEN); | |
2944 | if (temp != 0) | |
91ce572a CC |
2945 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
2946 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
7fd01431 RK |
2947 | |
2948 | if (temp != 0) | |
2949 | return temp; | |
2950 | } | |
2951 | ||
2ef0a555 RH |
2952 | return NULL_RTX; |
2953 | } | |
2954 | ||
2955 | rtx | |
0c20a65f AJ |
2956 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
2957 | int result_unsignedp, int safe) | |
2ef0a555 RH |
2958 | { |
2959 | rtx temp, op1; | |
2960 | ||
77173bbe KH |
2961 | if (! flag_trapv) |
2962 | result_unsignedp = 1; | |
2963 | ||
2ef0a555 RH |
2964 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
2965 | if (temp != 0) | |
2966 | return temp; | |
2967 | ||
7fd01431 | 2968 | /* If that does not win, use conditional jump and negate. */ |
5c0bf747 RK |
2969 | |
2970 | /* It is safe to use the target if it is the same | |
2971 | as the source if this is also a pseudo register */ | |
2972 | if (op0 == target && GET_CODE (op0) == REG | |
2973 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) | |
2974 | safe = 1; | |
2975 | ||
7fd01431 RK |
2976 | op1 = gen_label_rtx (); |
2977 | if (target == 0 || ! safe | |
2978 | || GET_MODE (target) != mode | |
2979 | || (GET_CODE (target) == MEM && MEM_VOLATILE_P (target)) | |
2980 | || (GET_CODE (target) == REG | |
2981 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) | |
2982 | target = gen_reg_rtx (mode); | |
2983 | ||
2984 | emit_move_insn (target, op0); | |
2985 | NO_DEFER_POP; | |
2986 | ||
2987 | /* If this mode is an integer too wide to compare properly, | |
2988 | compare word by word. Rely on CSE to optimize constant cases. */ | |
1eb8759b RH |
2989 | if (GET_MODE_CLASS (mode) == MODE_INT |
2990 | && ! can_compare_p (GE, mode, ccp_jump)) | |
0c20a65f | 2991 | do_jump_by_parts_greater_rtx (mode, 0, target, const0_rtx, |
7fd01431 RK |
2992 | NULL_RTX, op1); |
2993 | else | |
b30f05db | 2994 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
a06ef755 | 2995 | NULL_RTX, NULL_RTX, op1); |
7fd01431 | 2996 | |
91ce572a CC |
2997 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
2998 | target, target, 0); | |
7fd01431 RK |
2999 | if (op0 != target) |
3000 | emit_move_insn (target, op0); | |
3001 | emit_label (op1); | |
3002 | OK_DEFER_POP; | |
3003 | return target; | |
3004 | } | |
3005 | \f | |
3006 | /* Emit code to compute the absolute value of OP0, with result to | |
3007 | TARGET if convenient. (TARGET may be 0.) The return value says | |
3008 | where the result actually is to be found. | |
3009 | ||
3010 | MODE is the mode of the operand; the mode of the result is | |
3011 | different but can be deduced from MODE. | |
3012 | ||
decdfa82 RS |
3013 | UNSIGNEDP is relevant for complex integer modes. */ |
3014 | ||
3015 | rtx | |
0c20a65f AJ |
3016 | expand_complex_abs (enum machine_mode mode, rtx op0, rtx target, |
3017 | int unsignedp) | |
decdfa82 RS |
3018 | { |
3019 | enum mode_class class = GET_MODE_CLASS (mode); | |
3020 | enum machine_mode wider_mode; | |
b3694847 | 3021 | rtx temp; |
abd418d3 RS |
3022 | rtx entry_last = get_last_insn (); |
3023 | rtx last; | |
decdfa82 | 3024 | rtx pat; |
91ce572a | 3025 | optab this_abs_optab; |
decdfa82 RS |
3026 | |
3027 | /* Find the correct mode for the real and imaginary parts. */ | |
27e58a70 | 3028 | enum machine_mode submode = GET_MODE_INNER (mode); |
decdfa82 RS |
3029 | |
3030 | if (submode == BLKmode) | |
3031 | abort (); | |
3032 | ||
3033 | op0 = protect_from_queue (op0, 0); | |
3034 | ||
3035 | if (flag_force_mem) | |
3036 | { | |
3037 | op0 = force_not_mem (op0); | |
3038 | } | |
3039 | ||
abd418d3 RS |
3040 | last = get_last_insn (); |
3041 | ||
decdfa82 RS |
3042 | if (target) |
3043 | target = protect_from_queue (target, 1); | |
3044 | ||
91ce572a CC |
3045 | this_abs_optab = ! unsignedp && flag_trapv |
3046 | && (GET_MODE_CLASS(mode) == MODE_INT) | |
3047 | ? absv_optab : abs_optab; | |
3048 | ||
3049 | if (this_abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
decdfa82 | 3050 | { |
91ce572a | 3051 | int icode = (int) this_abs_optab->handlers[(int) mode].insn_code; |
a995e389 | 3052 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
decdfa82 RS |
3053 | rtx xop0 = op0; |
3054 | ||
3055 | if (target) | |
3056 | temp = target; | |
3057 | else | |
3058 | temp = gen_reg_rtx (submode); | |
3059 | ||
3060 | if (GET_MODE (xop0) != VOIDmode | |
3061 | && GET_MODE (xop0) != mode0) | |
3062 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
3063 | ||
3064 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
3065 | ||
a995e389 | 3066 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
decdfa82 RS |
3067 | xop0 = copy_to_mode_reg (mode0, xop0); |
3068 | ||
a995e389 | 3069 | if (! (*insn_data[icode].operand[0].predicate) (temp, submode)) |
decdfa82 RS |
3070 | temp = gen_reg_rtx (submode); |
3071 | ||
3072 | pat = GEN_FCN (icode) (temp, xop0); | |
3073 | if (pat) | |
3074 | { | |
2f937369 | 3075 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
0c20a65f | 3076 | && ! add_equal_note (pat, temp, this_abs_optab->code, xop0, |
91ce572a | 3077 | NULL_RTX)) |
decdfa82 RS |
3078 | { |
3079 | delete_insns_since (last); | |
0c20a65f | 3080 | return expand_unop (mode, this_abs_optab, op0, NULL_RTX, |
91ce572a | 3081 | unsignedp); |
decdfa82 RS |
3082 | } |
3083 | ||
3084 | emit_insn (pat); | |
0c20a65f | 3085 | |
decdfa82 RS |
3086 | return temp; |
3087 | } | |
3088 | else | |
3089 | delete_insns_since (last); | |
3090 | } | |
3091 | ||
3092 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ | |
3093 | ||
3094 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
3095 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
3096 | { | |
0c20a65f | 3097 | if (this_abs_optab->handlers[(int) wider_mode].insn_code |
91ce572a | 3098 | != CODE_FOR_nothing) |
decdfa82 RS |
3099 | { |
3100 | rtx xop0 = op0; | |
3101 | ||
0661a3de | 3102 | xop0 = convert_modes (wider_mode, mode, xop0, unsignedp); |
decdfa82 RS |
3103 | temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); |
3104 | ||
3105 | if (temp) | |
3106 | { | |
3107 | if (class != MODE_COMPLEX_INT) | |
3108 | { | |
3109 | if (target == 0) | |
3110 | target = gen_reg_rtx (submode); | |
3111 | convert_move (target, temp, 0); | |
3112 | return target; | |
3113 | } | |
3114 | else | |
3115 | return gen_lowpart (submode, temp); | |
3116 | } | |
3117 | else | |
3118 | delete_insns_since (last); | |
3119 | } | |
3120 | } | |
3121 | ||
3122 | /* Open-code the complex absolute-value operation | |
3123 | if we can open-code sqrt. Otherwise it's not worth while. */ | |
10e927ef CC |
3124 | if (sqrt_optab->handlers[(int) submode].insn_code != CODE_FOR_nothing |
3125 | && ! flag_trapv) | |
decdfa82 RS |
3126 | { |
3127 | rtx real, imag, total; | |
3128 | ||
3129 | real = gen_realpart (submode, op0); | |
3130 | imag = gen_imagpart (submode, op0); | |
9061e4cd | 3131 | |
decdfa82 | 3132 | /* Square both parts. */ |
9061e4cd RK |
3133 | real = expand_mult (submode, real, real, NULL_RTX, 0); |
3134 | imag = expand_mult (submode, imag, imag, NULL_RTX, 0); | |
3135 | ||
decdfa82 | 3136 | /* Sum the parts. */ |
73d9a835 | 3137 | total = expand_binop (submode, add_optab, real, imag, NULL_RTX, |
decdfa82 | 3138 | 0, OPTAB_LIB_WIDEN); |
9061e4cd | 3139 | |
decdfa82 RS |
3140 | /* Get sqrt in TARGET. Set TARGET to where the result is. */ |
3141 | target = expand_unop (submode, sqrt_optab, total, target, 0); | |
3142 | if (target == 0) | |
3143 | delete_insns_since (last); | |
3144 | else | |
3145 | return target; | |
3146 | } | |
3147 | ||
3148 | /* Now try a library call in this mode. */ | |
91ce572a | 3149 | if (this_abs_optab->handlers[(int) mode].libfunc) |
decdfa82 RS |
3150 | { |
3151 | rtx insns; | |
a0bc0933 | 3152 | rtx value; |
decdfa82 RS |
3153 | |
3154 | start_sequence (); | |
3155 | ||
3156 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3157 | if the libcall is cse'd or moved. */ | |
9a7f678c | 3158 | value = emit_library_call_value (abs_optab->handlers[(int) mode].libfunc, |
ebb1b59a | 3159 | NULL_RTX, LCT_CONST, submode, 1, op0, mode); |
decdfa82 RS |
3160 | insns = get_insns (); |
3161 | end_sequence (); | |
3162 | ||
3163 | target = gen_reg_rtx (submode); | |
9a7f678c | 3164 | emit_libcall_block (insns, target, value, |
91ce572a | 3165 | gen_rtx_fmt_e (this_abs_optab->code, mode, op0)); |
decdfa82 RS |
3166 | |
3167 | return target; | |
3168 | } | |
3169 | ||
3170 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3171 | ||
3172 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
3173 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
3174 | { | |
91ce572a | 3175 | if ((this_abs_optab->handlers[(int) wider_mode].insn_code |
decdfa82 | 3176 | != CODE_FOR_nothing) |
91ce572a | 3177 | || this_abs_optab->handlers[(int) wider_mode].libfunc) |
decdfa82 RS |
3178 | { |
3179 | rtx xop0 = op0; | |
3180 | ||
0661a3de | 3181 | xop0 = convert_modes (wider_mode, mode, xop0, unsignedp); |
decdfa82 RS |
3182 | |
3183 | temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); | |
3184 | ||
3185 | if (temp) | |
3186 | { | |
3187 | if (class != MODE_COMPLEX_INT) | |
3188 | { | |
3189 | if (target == 0) | |
3190 | target = gen_reg_rtx (submode); | |
3191 | convert_move (target, temp, 0); | |
3192 | return target; | |
3193 | } | |
3194 | else | |
3195 | return gen_lowpart (submode, temp); | |
3196 | } | |
3197 | else | |
3198 | delete_insns_since (last); | |
3199 | } | |
3200 | } | |
3201 | ||
abd418d3 | 3202 | delete_insns_since (entry_last); |
decdfa82 RS |
3203 | return 0; |
3204 | } | |
3205 | \f | |
77c9c6c2 RK |
3206 | /* Generate an instruction whose insn-code is INSN_CODE, |
3207 | with two operands: an output TARGET and an input OP0. | |
3208 | TARGET *must* be nonzero, and the output is always stored there. | |
3209 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3210 | the value that is stored into TARGET. */ | |
3211 | ||
3212 | void | |
0c20a65f | 3213 | emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) |
77c9c6c2 | 3214 | { |
b3694847 | 3215 | rtx temp; |
a995e389 | 3216 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 RK |
3217 | rtx pat; |
3218 | ||
3219 | temp = target = protect_from_queue (target, 1); | |
3220 | ||
3221 | op0 = protect_from_queue (op0, 0); | |
3222 | ||
bd8c4b14 ILT |
3223 | /* Sign and zero extension from memory is often done specially on |
3224 | RISC machines, so forcing into a register here can pessimize | |
3225 | code. */ | |
3226 | if (flag_force_mem && code != SIGN_EXTEND && code != ZERO_EXTEND) | |
77c9c6c2 RK |
3227 | op0 = force_not_mem (op0); |
3228 | ||
3229 | /* Now, if insn does not accept our operands, put them into pseudos. */ | |
3230 | ||
a995e389 | 3231 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
77c9c6c2 RK |
3232 | op0 = copy_to_mode_reg (mode0, op0); |
3233 | ||
a995e389 | 3234 | if (! (*insn_data[icode].operand[0].predicate) (temp, GET_MODE (temp)) |
77c9c6c2 RK |
3235 | || (flag_force_mem && GET_CODE (temp) == MEM)) |
3236 | temp = gen_reg_rtx (GET_MODE (temp)); | |
3237 | ||
3238 | pat = GEN_FCN (icode) (temp, op0); | |
3239 | ||
2f937369 | 3240 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
b1ec3c92 | 3241 | add_equal_note (pat, temp, code, op0, NULL_RTX); |
0c20a65f | 3242 | |
77c9c6c2 RK |
3243 | emit_insn (pat); |
3244 | ||
3245 | if (temp != target) | |
3246 | emit_move_insn (target, temp); | |
3247 | } | |
3248 | \f | |
3249 | /* Emit code to perform a series of operations on a multi-word quantity, one | |
3250 | word at a time. | |
3251 | ||
d45cf215 | 3252 | Such a block is preceded by a CLOBBER of the output, consists of multiple |
77c9c6c2 RK |
3253 | insns, each setting one word of the output, and followed by a SET copying |
3254 | the output to itself. | |
3255 | ||
3256 | Each of the insns setting words of the output receives a REG_NO_CONFLICT | |
3257 | note indicating that it doesn't conflict with the (also multi-word) | |
3258 | inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL | |
3259 | notes. | |
3260 | ||
3261 | INSNS is a block of code generated to perform the operation, not including | |
3262 | the CLOBBER and final copy. All insns that compute intermediate values | |
0c20a65f | 3263 | are first emitted, followed by the block as described above. |
77c9c6c2 RK |
3264 | |
3265 | TARGET, OP0, and OP1 are the output and inputs of the operations, | |
3266 | respectively. OP1 may be zero for a unary operation. | |
3267 | ||
40f03658 | 3268 | EQUIV, if nonzero, is an expression to be placed into a REG_EQUAL note |
77c9c6c2 RK |
3269 | on the last insn. |
3270 | ||
3271 | If TARGET is not a register, INSNS is simply emitted with no special | |
dce39da6 RK |
3272 | processing. Likewise if anything in INSNS is not an INSN or if |
3273 | there is a libcall block inside INSNS. | |
77c9c6c2 RK |
3274 | |
3275 | The final insn emitted is returned. */ | |
3276 | ||
3277 | rtx | |
0c20a65f | 3278 | emit_no_conflict_block (rtx insns, rtx target, rtx op0, rtx op1, rtx equiv) |
77c9c6c2 RK |
3279 | { |
3280 | rtx prev, next, first, last, insn; | |
3281 | ||
3282 | if (GET_CODE (target) != REG || reload_in_progress) | |
2f937369 | 3283 | return emit_insn (insns); |
dce39da6 RK |
3284 | else |
3285 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
3286 | if (GET_CODE (insn) != INSN | |
3287 | || find_reg_note (insn, REG_LIBCALL, NULL_RTX)) | |
2f937369 | 3288 | return emit_insn (insns); |
77c9c6c2 RK |
3289 | |
3290 | /* First emit all insns that do not store into words of the output and remove | |
3291 | these from the list. */ | |
3292 | for (insn = insns; insn; insn = next) | |
3293 | { | |
218aa620 | 3294 | rtx set = 0, note; |
77c9c6c2 RK |
3295 | int i; |
3296 | ||
3297 | next = NEXT_INSN (insn); | |
3298 | ||
dcc24678 | 3299 | /* Some ports (cris) create a libcall regions at their own. We must |
218aa620 JH |
3300 | avoid any potential nesting of LIBCALLs. */ |
3301 | if ((note = find_reg_note (insn, REG_LIBCALL, NULL)) != NULL) | |
3302 | remove_note (insn, note); | |
3303 | if ((note = find_reg_note (insn, REG_RETVAL, NULL)) != NULL) | |
3304 | remove_note (insn, note); | |
3305 | ||
c5c76735 JL |
3306 | if (GET_CODE (PATTERN (insn)) == SET || GET_CODE (PATTERN (insn)) == USE |
3307 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
77c9c6c2 RK |
3308 | set = PATTERN (insn); |
3309 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
3310 | { | |
3311 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
3312 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET) | |
3313 | { | |
3314 | set = XVECEXP (PATTERN (insn), 0, i); | |
3315 | break; | |
3316 | } | |
3317 | } | |
3318 | ||
3319 | if (set == 0) | |
3320 | abort (); | |
3321 | ||
3322 | if (! reg_overlap_mentioned_p (target, SET_DEST (set))) | |
3323 | { | |
3324 | if (PREV_INSN (insn)) | |
3325 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3326 | else | |
3327 | insns = next; | |
3328 | ||
3329 | if (next) | |
3330 | PREV_INSN (next) = PREV_INSN (insn); | |
3331 | ||
3332 | add_insn (insn); | |
3333 | } | |
3334 | } | |
3335 | ||
3336 | prev = get_last_insn (); | |
3337 | ||
3338 | /* Now write the CLOBBER of the output, followed by the setting of each | |
3339 | of the words, followed by the final copy. */ | |
3340 | if (target != op0 && target != op1) | |
9e6a5703 | 3341 | emit_insn (gen_rtx_CLOBBER (VOIDmode, target)); |
77c9c6c2 RK |
3342 | |
3343 | for (insn = insns; insn; insn = next) | |
3344 | { | |
3345 | next = NEXT_INSN (insn); | |
3346 | add_insn (insn); | |
3347 | ||
3348 | if (op1 && GET_CODE (op1) == REG) | |
9e6a5703 JC |
3349 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op1, |
3350 | REG_NOTES (insn)); | |
77c9c6c2 RK |
3351 | |
3352 | if (op0 && GET_CODE (op0) == REG) | |
9e6a5703 JC |
3353 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op0, |
3354 | REG_NOTES (insn)); | |
77c9c6c2 RK |
3355 | } |
3356 | ||
54e7b5e6 RS |
3357 | if (mov_optab->handlers[(int) GET_MODE (target)].insn_code |
3358 | != CODE_FOR_nothing) | |
3359 | { | |
3360 | last = emit_move_insn (target, target); | |
3361 | if (equiv) | |
5fa671cf | 3362 | set_unique_reg_note (last, REG_EQUAL, equiv); |
54e7b5e6 RS |
3363 | } |
3364 | else | |
07edd4c5 HPN |
3365 | { |
3366 | last = get_last_insn (); | |
3367 | ||
3368 | /* Remove any existing REG_EQUAL note from "last", or else it will | |
3369 | be mistaken for a note referring to the full contents of the | |
3370 | alleged libcall value when found together with the REG_RETVAL | |
3371 | note added below. An existing note can come from an insn | |
3372 | expansion at "last". */ | |
3373 | remove_note (last, find_reg_note (last, REG_EQUAL, NULL_RTX)); | |
3374 | } | |
77c9c6c2 RK |
3375 | |
3376 | if (prev == 0) | |
3377 | first = get_insns (); | |
3378 | else | |
3379 | first = NEXT_INSN (prev); | |
3380 | ||
3381 | /* Encapsulate the block so it gets manipulated as a unit. */ | |
9e6a5703 JC |
3382 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, |
3383 | REG_NOTES (first)); | |
3384 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last)); | |
77c9c6c2 RK |
3385 | |
3386 | return last; | |
3387 | } | |
3388 | \f | |
3389 | /* Emit code to make a call to a constant function or a library call. | |
3390 | ||
3391 | INSNS is a list containing all insns emitted in the call. | |
3392 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3393 | to TARGET, which is logically equivalent to EQUIV. | |
3394 | ||
3395 | We first emit any insns that set a pseudo on the assumption that these are | |
3396 | loading constants into registers; doing so allows them to be safely cse'ed | |
3397 | between blocks. Then we emit all the other insns in the block, followed by | |
3398 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
3399 | note with an operand of EQUIV. | |
3400 | ||
29ebe69a RK |
3401 | Moving assignments to pseudos outside of the block is done to improve |
3402 | the generated code, but is not required to generate correct code, | |
3403 | hence being unable to move an assignment is not grounds for not making | |
3404 | a libcall block. There are two reasons why it is safe to leave these | |
3405 | insns inside the block: First, we know that these pseudos cannot be | |
3406 | used in generated RTL outside the block since they are created for | |
3407 | temporary purposes within the block. Second, CSE will not record the | |
3408 | values of anything set inside a libcall block, so we know they must | |
3409 | be dead at the end of the block. | |
3410 | ||
77c9c6c2 RK |
3411 | Except for the first group of insns (the ones setting pseudos), the |
3412 | block is delimited by REG_RETVAL and REG_LIBCALL notes. */ | |
3413 | ||
3414 | void | |
0c20a65f | 3415 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) |
77c9c6c2 | 3416 | { |
aff2c2d3 | 3417 | rtx final_dest = target; |
77c9c6c2 RK |
3418 | rtx prev, next, first, last, insn; |
3419 | ||
aff2c2d3 BS |
3420 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3421 | into a MEM later. Protect the libcall block from this change. */ | |
3422 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3423 | target = gen_reg_rtx (GET_MODE (target)); | |
0c20a65f | 3424 | |
5154e79a AH |
3425 | /* If we're using non-call exceptions, a libcall corresponding to an |
3426 | operation that may trap may also trap. */ | |
3427 | if (flag_non_call_exceptions && may_trap_p (equiv)) | |
3428 | { | |
3429 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
3430 | if (GET_CODE (insn) == CALL_INSN) | |
3431 | { | |
3432 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3433 | |
5154e79a AH |
3434 | if (note != 0 && INTVAL (XEXP (note, 0)) <= 0) |
3435 | remove_note (insn, note); | |
3436 | } | |
3437 | } | |
3438 | else | |
b472794d | 3439 | /* look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION |
c29ea88a | 3440 | reg note to indicate that this call cannot throw or execute a nonlocal |
cf67d231 | 3441 | goto (unless there is already a REG_EH_REGION note, in which case |
897aa57f | 3442 | we update it). */ |
5154e79a AH |
3443 | for (insn = insns; insn; insn = NEXT_INSN (insn)) |
3444 | if (GET_CODE (insn) == CALL_INSN) | |
3445 | { | |
3446 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3447 | |
5154e79a | 3448 | if (note != 0) |
60c81c89 | 3449 | XEXP (note, 0) = constm1_rtx; |
5154e79a | 3450 | else |
60c81c89 | 3451 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, |
5154e79a AH |
3452 | REG_NOTES (insn)); |
3453 | } | |
b472794d | 3454 | |
77c9c6c2 | 3455 | /* First emit all insns that set pseudos. Remove them from the list as |
ccf5f342 | 3456 | we go. Avoid insns that set pseudos which were referenced in previous |
29ebe69a | 3457 | insns. These can be generated by move_by_pieces, for example, |
ccf5f342 RK |
3458 | to update an address. Similarly, avoid insns that reference things |
3459 | set in previous insns. */ | |
77c9c6c2 RK |
3460 | |
3461 | for (insn = insns; insn; insn = next) | |
3462 | { | |
3463 | rtx set = single_set (insn); | |
218aa620 JH |
3464 | rtx note; |
3465 | ||
dcc24678 | 3466 | /* Some ports (cris) create a libcall regions at their own. We must |
218aa620 JH |
3467 | avoid any potential nesting of LIBCALLs. */ |
3468 | if ((note = find_reg_note (insn, REG_LIBCALL, NULL)) != NULL) | |
3469 | remove_note (insn, note); | |
3470 | if ((note = find_reg_note (insn, REG_RETVAL, NULL)) != NULL) | |
3471 | remove_note (insn, note); | |
77c9c6c2 RK |
3472 | |
3473 | next = NEXT_INSN (insn); | |
3474 | ||
3475 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG | |
29ebe69a | 3476 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER |
8d9e73cc | 3477 | && (insn == insns |
9485c46e DM |
3478 | || ((! INSN_P(insns) |
3479 | || ! reg_mentioned_p (SET_DEST (set), PATTERN (insns))) | |
ccf5f342 RK |
3480 | && ! reg_used_between_p (SET_DEST (set), insns, insn) |
3481 | && ! modified_in_p (SET_SRC (set), insns) | |
3482 | && ! modified_between_p (SET_SRC (set), insns, insn)))) | |
77c9c6c2 RK |
3483 | { |
3484 | if (PREV_INSN (insn)) | |
3485 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3486 | else | |
3487 | insns = next; | |
3488 | ||
3489 | if (next) | |
3490 | PREV_INSN (next) = PREV_INSN (insn); | |
3491 | ||
3492 | add_insn (insn); | |
3493 | } | |
695a94b3 RS |
3494 | |
3495 | /* Some ports use a loop to copy large arguments onto the stack. | |
3496 | Don't move anything outside such a loop. */ | |
3497 | if (GET_CODE (insn) == CODE_LABEL) | |
3498 | break; | |
77c9c6c2 RK |
3499 | } |
3500 | ||
3501 | prev = get_last_insn (); | |
3502 | ||
3503 | /* Write the remaining insns followed by the final copy. */ | |
3504 | ||
3505 | for (insn = insns; insn; insn = next) | |
3506 | { | |
3507 | next = NEXT_INSN (insn); | |
3508 | ||
3509 | add_insn (insn); | |
3510 | } | |
3511 | ||
3512 | last = emit_move_insn (target, result); | |
02214a5c RK |
3513 | if (mov_optab->handlers[(int) GET_MODE (target)].insn_code |
3514 | != CODE_FOR_nothing) | |
5fa671cf | 3515 | set_unique_reg_note (last, REG_EQUAL, copy_rtx (equiv)); |
07edd4c5 HPN |
3516 | else |
3517 | { | |
3518 | /* Remove any existing REG_EQUAL note from "last", or else it will | |
3519 | be mistaken for a note referring to the full contents of the | |
3520 | libcall value when found together with the REG_RETVAL note added | |
3521 | below. An existing note can come from an insn expansion at | |
3522 | "last". */ | |
3523 | remove_note (last, find_reg_note (last, REG_EQUAL, NULL_RTX)); | |
3524 | } | |
77c9c6c2 | 3525 | |
e85427f9 BS |
3526 | if (final_dest != target) |
3527 | emit_move_insn (final_dest, target); | |
aff2c2d3 | 3528 | |
77c9c6c2 RK |
3529 | if (prev == 0) |
3530 | first = get_insns (); | |
3531 | else | |
3532 | first = NEXT_INSN (prev); | |
3533 | ||
3534 | /* Encapsulate the block so it gets manipulated as a unit. */ | |
11e9ecc5 HB |
3535 | if (!flag_non_call_exceptions || !may_trap_p (equiv)) |
3536 | { | |
4a69cf79 JZ |
3537 | /* We can't attach the REG_LIBCALL and REG_RETVAL notes |
3538 | when the encapsulated region would not be in one basic block, | |
3539 | i.e. when there is a control_flow_insn_p insn between FIRST and LAST. | |
3540 | */ | |
3541 | bool attach_libcall_retval_notes = true; | |
3542 | next = NEXT_INSN (last); | |
3543 | for (insn = first; insn != next; insn = NEXT_INSN (insn)) | |
3544 | if (control_flow_insn_p (insn)) | |
3545 | { | |
3546 | attach_libcall_retval_notes = false; | |
3547 | break; | |
3548 | } | |
3549 | ||
3550 | if (attach_libcall_retval_notes) | |
3551 | { | |
3552 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3553 | REG_NOTES (first)); | |
3554 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3555 | REG_NOTES (last)); | |
3556 | } | |
11e9ecc5 | 3557 | } |
77c9c6c2 RK |
3558 | } |
3559 | \f | |
3560 | /* Generate code to store zero in X. */ | |
3561 | ||
3562 | void | |
0c20a65f | 3563 | emit_clr_insn (rtx x) |
77c9c6c2 RK |
3564 | { |
3565 | emit_move_insn (x, const0_rtx); | |
3566 | } | |
3567 | ||
3568 | /* Generate code to store 1 in X | |
3569 | assuming it contains zero beforehand. */ | |
3570 | ||
3571 | void | |
0c20a65f | 3572 | emit_0_to_1_insn (rtx x) |
77c9c6c2 RK |
3573 | { |
3574 | emit_move_insn (x, const1_rtx); | |
3575 | } | |
3576 | ||
1c0290ea | 3577 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
1eb8759b RH |
3578 | PURPOSE describes how this comparison will be used. CODE is the rtx |
3579 | comparison code we will be using. | |
3580 | ||
3581 | ??? Actually, CODE is slightly weaker than that. A target is still | |
0c20a65f | 3582 | required to implement all of the normal bcc operations, but not |
1eb8759b | 3583 | required to implement all (or any) of the unordered bcc operations. */ |
0c20a65f | 3584 | |
1c0290ea | 3585 | int |
0c20a65f AJ |
3586 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
3587 | enum can_compare_purpose purpose) | |
b30f05db BS |
3588 | { |
3589 | do | |
3590 | { | |
7e1a450d | 3591 | if (cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1eb8759b RH |
3592 | { |
3593 | if (purpose == ccp_jump) | |
7e1a450d | 3594 | return bcc_gen_fctn[(int) code] != NULL; |
1eb8759b | 3595 | else if (purpose == ccp_store_flag) |
7e1a450d | 3596 | return setcc_gen_code[(int) code] != CODE_FOR_nothing; |
1eb8759b RH |
3597 | else |
3598 | /* There's only one cmov entry point, and it's allowed to fail. */ | |
3599 | return 1; | |
3600 | } | |
1c0290ea | 3601 | if (purpose == ccp_jump |
7e1a450d | 3602 | && cbranch_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3603 | return 1; |
3604 | if (purpose == ccp_cmov | |
7e1a450d | 3605 | && cmov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3606 | return 1; |
3607 | if (purpose == ccp_store_flag | |
7e1a450d | 3608 | && cstore_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3609 | return 1; |
3610 | ||
b30f05db | 3611 | mode = GET_MODE_WIDER_MODE (mode); |
1c0290ea BS |
3612 | } |
3613 | while (mode != VOIDmode); | |
b30f05db BS |
3614 | |
3615 | return 0; | |
3616 | } | |
3617 | ||
3618 | /* This function is called when we are going to emit a compare instruction that | |
3619 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
3620 | ||
3621 | *PMODE is the mode of the inputs (in case they are const_int). | |
3622 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
77c9c6c2 RK |
3623 | this matters if they need to be widened. |
3624 | ||
a06ef755 | 3625 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
77c9c6c2 | 3626 | |
b30f05db BS |
3627 | This function performs all the setup necessary so that the caller only has |
3628 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
3629 | comparison or emitting a library call to perform the comparison if no insn | |
3630 | is available to handle it. | |
3631 | The values which are passed in through pointers can be modified; the caller | |
3632 | should perform the comparison on the modified values. */ | |
77c9c6c2 | 3633 | |
a06ef755 | 3634 | static void |
0c20a65f AJ |
3635 | prepare_cmp_insn (rtx *px, rtx *py, enum rtx_code *pcomparison, rtx size, |
3636 | enum machine_mode *pmode, int *punsignedp, | |
3637 | enum can_compare_purpose purpose) | |
77c9c6c2 | 3638 | { |
b30f05db BS |
3639 | enum machine_mode mode = *pmode; |
3640 | rtx x = *px, y = *py; | |
3641 | int unsignedp = *punsignedp; | |
77c9c6c2 | 3642 | enum mode_class class; |
77c9c6c2 RK |
3643 | |
3644 | class = GET_MODE_CLASS (mode); | |
3645 | ||
3646 | /* They could both be VOIDmode if both args are immediate constants, | |
3647 | but we should fold that at an earlier stage. | |
3648 | With no special code here, this will call abort, | |
3649 | reminding the programmer to implement such folding. */ | |
3650 | ||
3651 | if (mode != BLKmode && flag_force_mem) | |
3652 | { | |
894207cf RS |
3653 | /* Load duplicate non-volatile operands once. */ |
3654 | if (rtx_equal_p (x, y) && ! volatile_refs_p (x)) | |
3655 | { | |
3656 | x = force_not_mem (x); | |
3657 | y = x; | |
3658 | } | |
3659 | else | |
3660 | { | |
3661 | x = force_not_mem (x); | |
3662 | y = force_not_mem (y); | |
3663 | } | |
77c9c6c2 RK |
3664 | } |
3665 | ||
3666 | /* If we are inside an appropriately-short loop and one operand is an | |
3667 | expensive constant, force it into a register. */ | |
19caa751 | 3668 | if (CONSTANT_P (x) && preserve_subexpressions_p () |
b437f1a7 | 3669 | && rtx_cost (x, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
3670 | x = force_reg (mode, x); |
3671 | ||
19caa751 | 3672 | if (CONSTANT_P (y) && preserve_subexpressions_p () |
b437f1a7 | 3673 | && rtx_cost (y, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
3674 | y = force_reg (mode, y); |
3675 | ||
362cc3d4 MH |
3676 | #ifdef HAVE_cc0 |
3677 | /* Abort if we have a non-canonical comparison. The RTL documentation | |
3678 | states that canonical comparisons are required only for targets which | |
3679 | have cc0. */ | |
3680 | if (CONSTANT_P (x) && ! CONSTANT_P (y)) | |
7e1a450d | 3681 | abort (); |
362cc3d4 MH |
3682 | #endif |
3683 | ||
77c9c6c2 RK |
3684 | /* Don't let both operands fail to indicate the mode. */ |
3685 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
3686 | x = force_reg (mode, x); | |
3687 | ||
3688 | /* Handle all BLKmode compares. */ | |
3689 | ||
3690 | if (mode == BLKmode) | |
3691 | { | |
118355a0 ZW |
3692 | enum machine_mode cmp_mode, result_mode; |
3693 | enum insn_code cmp_code; | |
3694 | tree length_type; | |
3695 | rtx libfunc; | |
b30f05db | 3696 | rtx result; |
118355a0 | 3697 | rtx opalign |
f4dc10d1 | 3698 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); |
b30f05db | 3699 | |
118355a0 ZW |
3700 | if (size == 0) |
3701 | abort (); | |
3702 | ||
77c9c6c2 RK |
3703 | emit_queue (); |
3704 | x = protect_from_queue (x, 0); | |
3705 | y = protect_from_queue (y, 0); | |
118355a0 | 3706 | size = protect_from_queue (size, 0); |
77c9c6c2 | 3707 | |
118355a0 ZW |
3708 | /* Try to use a memory block compare insn - either cmpstr |
3709 | or cmpmem will do. */ | |
3710 | for (cmp_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
3711 | cmp_mode != VOIDmode; | |
3712 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode)) | |
358b8f01 | 3713 | { |
118355a0 ZW |
3714 | cmp_code = cmpmem_optab[cmp_mode]; |
3715 | if (cmp_code == CODE_FOR_nothing) | |
3716 | cmp_code = cmpstr_optab[cmp_mode]; | |
3717 | if (cmp_code == CODE_FOR_nothing) | |
3718 | continue; | |
3719 | ||
3720 | /* Must make sure the size fits the insn's mode. */ | |
3721 | if ((GET_CODE (size) == CONST_INT | |
3722 | && INTVAL (size) >= (1 << GET_MODE_BITSIZE (cmp_mode))) | |
3723 | || (GET_MODE_BITSIZE (GET_MODE (size)) | |
3724 | > GET_MODE_BITSIZE (cmp_mode))) | |
3725 | continue; | |
3726 | ||
3727 | result_mode = insn_data[cmp_code].operand[0].mode; | |
358b8f01 | 3728 | result = gen_reg_rtx (result_mode); |
118355a0 ZW |
3729 | size = convert_to_mode (cmp_mode, size, 1); |
3730 | emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign)); | |
3731 | ||
3732 | *px = result; | |
3733 | *py = const0_rtx; | |
3734 | *pmode = result_mode; | |
3735 | return; | |
77c9c6c2 | 3736 | } |
118355a0 ZW |
3737 | |
3738 | /* Otherwise call a library function, memcmp if we've got it, | |
3739 | bcmp otherwise. */ | |
77c9c6c2 | 3740 | #ifdef TARGET_MEM_FUNCTIONS |
118355a0 ZW |
3741 | libfunc = memcmp_libfunc; |
3742 | length_type = sizetype; | |
77c9c6c2 | 3743 | #else |
118355a0 ZW |
3744 | libfunc = bcmp_libfunc; |
3745 | length_type = integer_type_node; | |
77c9c6c2 | 3746 | #endif |
118355a0 ZW |
3747 | result_mode = TYPE_MODE (integer_type_node); |
3748 | cmp_mode = TYPE_MODE (length_type); | |
3749 | size = convert_to_mode (TYPE_MODE (length_type), size, | |
8df83eae | 3750 | TYPE_UNSIGNED (length_type)); |
118355a0 ZW |
3751 | |
3752 | result = emit_library_call_value (libfunc, 0, LCT_PURE_MAKE_BLOCK, | |
3753 | result_mode, 3, | |
3754 | XEXP (x, 0), Pmode, | |
3755 | XEXP (y, 0), Pmode, | |
3756 | size, cmp_mode); | |
b30f05db BS |
3757 | *px = result; |
3758 | *py = const0_rtx; | |
3759 | *pmode = result_mode; | |
77c9c6c2 RK |
3760 | return; |
3761 | } | |
3762 | ||
27ab3e91 RH |
3763 | /* Don't allow operands to the compare to trap, as that can put the |
3764 | compare and branch in different basic blocks. */ | |
3765 | if (flag_non_call_exceptions) | |
3766 | { | |
3767 | if (may_trap_p (x)) | |
3768 | x = force_reg (mode, x); | |
3769 | if (may_trap_p (y)) | |
3770 | y = force_reg (mode, y); | |
3771 | } | |
3772 | ||
b30f05db BS |
3773 | *px = x; |
3774 | *py = y; | |
1eb8759b | 3775 | if (can_compare_p (*pcomparison, mode, purpose)) |
b30f05db | 3776 | return; |
77c9c6c2 RK |
3777 | |
3778 | /* Handle a lib call just for the mode we are using. */ | |
3779 | ||
b30f05db | 3780 | if (cmp_optab->handlers[(int) mode].libfunc && class != MODE_FLOAT) |
77c9c6c2 RK |
3781 | { |
3782 | rtx libfunc = cmp_optab->handlers[(int) mode].libfunc; | |
9725066d JL |
3783 | rtx result; |
3784 | ||
77c9c6c2 RK |
3785 | /* If we want unsigned, and this mode has a distinct unsigned |
3786 | comparison routine, use that. */ | |
3787 | if (unsignedp && ucmp_optab->handlers[(int) mode].libfunc) | |
3788 | libfunc = ucmp_optab->handlers[(int) mode].libfunc; | |
3789 | ||
24491a09 KH |
3790 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST_MAKE_BLOCK, |
3791 | word_mode, 2, x, mode, y, mode); | |
9725066d | 3792 | |
77c9c6c2 RK |
3793 | /* Integer comparison returns a result that must be compared against 1, |
3794 | so that even if we do an unsigned compare afterward, | |
3795 | there is still a value that can represent the result "less than". */ | |
b30f05db BS |
3796 | *px = result; |
3797 | *py = const1_rtx; | |
3798 | *pmode = word_mode; | |
77c9c6c2 RK |
3799 | return; |
3800 | } | |
3801 | ||
3802 | if (class == MODE_FLOAT) | |
c5c60e15 | 3803 | prepare_float_lib_cmp (px, py, pcomparison, pmode, punsignedp); |
77c9c6c2 RK |
3804 | |
3805 | else | |
3806 | abort (); | |
3807 | } | |
3808 | ||
b30f05db BS |
3809 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
3810 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
4fe9b91c | 3811 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
b30f05db | 3812 | that it is accepted by the operand predicate. Return the new value. */ |
749a2da1 | 3813 | |
1c0290ea | 3814 | rtx |
0c20a65f AJ |
3815 | prepare_operand (int icode, rtx x, int opnum, enum machine_mode mode, |
3816 | enum machine_mode wider_mode, int unsignedp) | |
b30f05db BS |
3817 | { |
3818 | x = protect_from_queue (x, 0); | |
3819 | ||
3820 | if (mode != wider_mode) | |
3821 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
3822 | ||
a995e389 RH |
3823 | if (! (*insn_data[icode].operand[opnum].predicate) |
3824 | (x, insn_data[icode].operand[opnum].mode)) | |
d893ccde RH |
3825 | { |
3826 | if (no_new_pseudos) | |
3827 | return NULL_RTX; | |
3828 | x = copy_to_mode_reg (insn_data[icode].operand[opnum].mode, x); | |
3829 | } | |
3830 | ||
b30f05db BS |
3831 | return x; |
3832 | } | |
3833 | ||
3834 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
3835 | we can do the comparison. | |
3836 | The arguments are the same as for emit_cmp_and_jump_insns; but LABEL may | |
3837 | be NULL_RTX which indicates that only a comparison is to be generated. */ | |
3838 | ||
3839 | static void | |
0c20a65f AJ |
3840 | emit_cmp_and_jump_insn_1 (rtx x, rtx y, enum machine_mode mode, |
3841 | enum rtx_code comparison, int unsignedp, rtx label) | |
b30f05db BS |
3842 | { |
3843 | rtx test = gen_rtx_fmt_ee (comparison, mode, x, y); | |
3844 | enum mode_class class = GET_MODE_CLASS (mode); | |
3845 | enum machine_mode wider_mode = mode; | |
3846 | ||
3847 | /* Try combined insns first. */ | |
3848 | do | |
3849 | { | |
3850 | enum insn_code icode; | |
3851 | PUT_MODE (test, wider_mode); | |
3852 | ||
1c0290ea | 3853 | if (label) |
0c20a65f | 3854 | { |
7e1a450d | 3855 | icode = cbranch_optab->handlers[(int) wider_mode].insn_code; |
0c20a65f | 3856 | |
1c0290ea BS |
3857 | if (icode != CODE_FOR_nothing |
3858 | && (*insn_data[icode].operand[0].predicate) (test, wider_mode)) | |
3859 | { | |
3860 | x = prepare_operand (icode, x, 1, mode, wider_mode, unsignedp); | |
3861 | y = prepare_operand (icode, y, 2, mode, wider_mode, unsignedp); | |
3862 | emit_jump_insn (GEN_FCN (icode) (test, x, y, label)); | |
3863 | return; | |
3864 | } | |
3865 | } | |
3866 | ||
b30f05db BS |
3867 | /* Handle some compares against zero. */ |
3868 | icode = (int) tst_optab->handlers[(int) wider_mode].insn_code; | |
3869 | if (y == CONST0_RTX (mode) && icode != CODE_FOR_nothing) | |
3870 | { | |
3871 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
3872 | emit_insn (GEN_FCN (icode) (x)); | |
3873 | if (label) | |
3874 | emit_jump_insn ((*bcc_gen_fctn[(int) comparison]) (label)); | |
3875 | return; | |
3876 | } | |
3877 | ||
3878 | /* Handle compares for which there is a directly suitable insn. */ | |
3879 | ||
3880 | icode = (int) cmp_optab->handlers[(int) wider_mode].insn_code; | |
3881 | if (icode != CODE_FOR_nothing) | |
3882 | { | |
3883 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
3884 | y = prepare_operand (icode, y, 1, mode, wider_mode, unsignedp); | |
3885 | emit_insn (GEN_FCN (icode) (x, y)); | |
3886 | if (label) | |
3887 | emit_jump_insn ((*bcc_gen_fctn[(int) comparison]) (label)); | |
3888 | return; | |
3889 | } | |
3890 | ||
3891 | if (class != MODE_INT && class != MODE_FLOAT | |
3892 | && class != MODE_COMPLEX_FLOAT) | |
3893 | break; | |
3894 | ||
3895 | wider_mode = GET_MODE_WIDER_MODE (wider_mode); | |
7e1a450d KH |
3896 | } |
3897 | while (wider_mode != VOIDmode); | |
b30f05db BS |
3898 | |
3899 | abort (); | |
3900 | } | |
3901 | ||
362cc3d4 MH |
3902 | /* Generate code to compare X with Y so that the condition codes are |
3903 | set and to jump to LABEL if the condition is true. If X is a | |
3904 | constant and Y is not a constant, then the comparison is swapped to | |
3905 | ensure that the comparison RTL has the canonical form. | |
3906 | ||
c5d5d461 JL |
3907 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
3908 | need to be widened by emit_cmp_insn. UNSIGNEDP is also used to select | |
3909 | the proper branch condition code. | |
362cc3d4 | 3910 | |
a06ef755 | 3911 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
362cc3d4 | 3912 | |
c5d5d461 JL |
3913 | MODE is the mode of the inputs (in case they are const_int). |
3914 | ||
3915 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). It will | |
3916 | be passed unchanged to emit_cmp_insn, then potentially converted into an | |
3917 | unsigned variant based on UNSIGNEDP to select a proper jump instruction. */ | |
362cc3d4 MH |
3918 | |
3919 | void | |
0c20a65f AJ |
3920 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3921 | enum machine_mode mode, int unsignedp, rtx label) | |
362cc3d4 | 3922 | { |
8c9864f3 JH |
3923 | rtx op0 = x, op1 = y; |
3924 | ||
3925 | /* Swap operands and condition to ensure canonical RTL. */ | |
3926 | if (swap_commutative_operands_p (x, y)) | |
362cc3d4 | 3927 | { |
8c9864f3 JH |
3928 | /* If we're not emitting a branch, this means some caller |
3929 | is out of sync. */ | |
3930 | if (! label) | |
3931 | abort (); | |
3932 | ||
3933 | op0 = y, op1 = x; | |
3934 | comparison = swap_condition (comparison); | |
362cc3d4 | 3935 | } |
0ca40216 JL |
3936 | |
3937 | #ifdef HAVE_cc0 | |
3938 | /* If OP0 is still a constant, then both X and Y must be constants. Force | |
3939 | X into a register to avoid aborting in emit_cmp_insn due to non-canonical | |
3940 | RTL. */ | |
3941 | if (CONSTANT_P (op0)) | |
3942 | op0 = force_reg (mode, op0); | |
3943 | #endif | |
3944 | ||
b30f05db | 3945 | emit_queue (); |
c5d5d461 JL |
3946 | if (unsignedp) |
3947 | comparison = unsigned_condition (comparison); | |
a06ef755 RK |
3948 | |
3949 | prepare_cmp_insn (&op0, &op1, &comparison, size, &mode, &unsignedp, | |
1c0290ea | 3950 | ccp_jump); |
b30f05db BS |
3951 | emit_cmp_and_jump_insn_1 (op0, op1, mode, comparison, unsignedp, label); |
3952 | } | |
3953 | ||
3954 | /* Like emit_cmp_and_jump_insns, but generate only the comparison. */ | |
19caa751 | 3955 | |
b30f05db | 3956 | void |
0c20a65f AJ |
3957 | emit_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3958 | enum machine_mode mode, int unsignedp) | |
b30f05db | 3959 | { |
a06ef755 | 3960 | emit_cmp_and_jump_insns (x, y, comparison, size, mode, unsignedp, 0); |
362cc3d4 | 3961 | } |
77c9c6c2 RK |
3962 | \f |
3963 | /* Emit a library call comparison between floating point X and Y. | |
3964 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
3965 | ||
c5c60e15 | 3966 | static void |
0c20a65f AJ |
3967 | prepare_float_lib_cmp (rtx *px, rtx *py, enum rtx_code *pcomparison, |
3968 | enum machine_mode *pmode, int *punsignedp) | |
77c9c6c2 | 3969 | { |
c5c60e15 | 3970 | enum rtx_code comparison = *pcomparison; |
c9034561 ZW |
3971 | enum rtx_code swapped = swap_condition (comparison); |
3972 | rtx x = protect_from_queue (*px, 0); | |
3973 | rtx y = protect_from_queue (*py, 0); | |
3974 | enum machine_mode orig_mode = GET_MODE (x); | |
3975 | enum machine_mode mode; | |
37bf20ee | 3976 | rtx value, target, insns, equiv; |
0a300065 | 3977 | rtx libfunc = 0; |
77c9c6c2 | 3978 | |
c9034561 | 3979 | for (mode = orig_mode; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) |
77c9c6c2 | 3980 | { |
c9034561 ZW |
3981 | if ((libfunc = code_to_optab[comparison]->handlers[mode].libfunc)) |
3982 | break; | |
77c9c6c2 | 3983 | |
c9034561 | 3984 | if ((libfunc = code_to_optab[swapped]->handlers[mode].libfunc)) |
77c9c6c2 | 3985 | { |
c9034561 ZW |
3986 | rtx tmp; |
3987 | tmp = x; x = y; y = tmp; | |
3988 | comparison = swapped; | |
3989 | break; | |
77c9c6c2 | 3990 | } |
77c9c6c2 RK |
3991 | } |
3992 | ||
c9034561 | 3993 | if (mode == VOIDmode) |
0a300065 RK |
3994 | abort (); |
3995 | ||
c9034561 ZW |
3996 | if (mode != orig_mode) |
3997 | { | |
3998 | x = convert_to_mode (mode, x, 0); | |
3999 | y = convert_to_mode (mode, y, 0); | |
4000 | } | |
4001 | ||
17796a89 RS |
4002 | /* Attach a REG_EQUAL note describing the semantics of the libcall to |
4003 | the RTL. The allows the RTL optimizers to delete the libcall if the | |
4004 | condition can be determined at compile-time. */ | |
4005 | if (comparison == UNORDERED) | |
4006 | { | |
4007 | rtx temp = simplify_gen_relational (NE, word_mode, mode, x, x); | |
4008 | equiv = simplify_gen_relational (NE, word_mode, mode, y, y); | |
4009 | equiv = simplify_gen_ternary (IF_THEN_ELSE, word_mode, word_mode, | |
4010 | temp, const_true_rtx, equiv); | |
4011 | } | |
4012 | else | |
4013 | { | |
4014 | equiv = simplify_gen_relational (comparison, word_mode, mode, x, y); | |
4015 | if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
bd831d5c | 4016 | { |
17796a89 | 4017 | rtx true_rtx, false_rtx; |
37bf20ee | 4018 | |
17796a89 RS |
4019 | switch (comparison) |
4020 | { | |
4021 | case EQ: | |
4022 | true_rtx = const0_rtx; | |
4023 | false_rtx = const_true_rtx; | |
4024 | break; | |
4025 | ||
4026 | case NE: | |
4027 | true_rtx = const_true_rtx; | |
4028 | false_rtx = const0_rtx; | |
4029 | break; | |
4030 | ||
4031 | case GT: | |
4032 | true_rtx = const1_rtx; | |
4033 | false_rtx = const0_rtx; | |
4034 | break; | |
4035 | ||
4036 | case GE: | |
4037 | true_rtx = const0_rtx; | |
4038 | false_rtx = constm1_rtx; | |
4039 | break; | |
4040 | ||
4041 | case LT: | |
4042 | true_rtx = constm1_rtx; | |
4043 | false_rtx = const0_rtx; | |
4044 | break; | |
4045 | ||
4046 | case LE: | |
4047 | true_rtx = const0_rtx; | |
4048 | false_rtx = const1_rtx; | |
4049 | break; | |
4050 | ||
4051 | default: | |
4052 | abort (); | |
bd831d5c | 4053 | } |
17796a89 RS |
4054 | equiv = simplify_gen_ternary (IF_THEN_ELSE, word_mode, word_mode, |
4055 | equiv, true_rtx, false_rtx); | |
bd831d5c RS |
4056 | } |
4057 | } | |
37bf20ee RS |
4058 | |
4059 | start_sequence (); | |
4060 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, | |
4061 | word_mode, 2, x, mode, y, mode); | |
4062 | insns = get_insns (); | |
4063 | end_sequence (); | |
4064 | ||
4065 | target = gen_reg_rtx (word_mode); | |
4066 | emit_libcall_block (insns, target, value, equiv); | |
4067 | ||
bd831d5c | 4068 | |
c9034561 ZW |
4069 | if (comparison == UNORDERED |
4070 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
4071 | comparison = NE; | |
4072 | ||
37bf20ee | 4073 | *px = target; |
b30f05db BS |
4074 | *py = const0_rtx; |
4075 | *pmode = word_mode; | |
c9034561 | 4076 | *pcomparison = comparison; |
b30f05db | 4077 | *punsignedp = 0; |
77c9c6c2 RK |
4078 | } |
4079 | \f | |
4080 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4081 | ||
4082 | void | |
0c20a65f | 4083 | emit_indirect_jump (rtx loc) |
77c9c6c2 | 4084 | { |
7e1a450d | 4085 | if (! ((*insn_data[(int) CODE_FOR_indirect_jump].operand[0].predicate) |
f2de2775 JW |
4086 | (loc, Pmode))) |
4087 | loc = copy_to_mode_reg (Pmode, loc); | |
77c9c6c2 RK |
4088 | |
4089 | emit_jump_insn (gen_indirect_jump (loc)); | |
9649fb4d | 4090 | emit_barrier (); |
77c9c6c2 RK |
4091 | } |
4092 | \f | |
49c4584c DE |
4093 | #ifdef HAVE_conditional_move |
4094 | ||
4095 | /* Emit a conditional move instruction if the machine supports one for that | |
4096 | condition and machine mode. | |
4097 | ||
4098 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4099 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4100 | both be constants. | |
4101 | ||
4102 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4103 | should be stored there. MODE is the mode to use should they be constants. | |
4104 | If it is VOIDmode, they cannot both be constants. | |
4105 | ||
4106 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4107 | is not supported. */ | |
4108 | ||
4109 | rtx | |
0c20a65f AJ |
4110 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4111 | enum machine_mode cmode, rtx op2, rtx op3, | |
4112 | enum machine_mode mode, int unsignedp) | |
49c4584c DE |
4113 | { |
4114 | rtx tem, subtarget, comparison, insn; | |
4115 | enum insn_code icode; | |
e5c56fd9 | 4116 | enum rtx_code reversed; |
49c4584c DE |
4117 | |
4118 | /* If one operand is constant, make it the second one. Only do this | |
4119 | if the other operand is not constant as well. */ | |
4120 | ||
e5c56fd9 | 4121 | if (swap_commutative_operands_p (op0, op1)) |
49c4584c DE |
4122 | { |
4123 | tem = op0; | |
4124 | op0 = op1; | |
4125 | op1 = tem; | |
4126 | code = swap_condition (code); | |
4127 | } | |
4128 | ||
c5c76735 JL |
4129 | /* get_condition will prefer to generate LT and GT even if the old |
4130 | comparison was against zero, so undo that canonicalization here since | |
4131 | comparisons against zero are cheaper. */ | |
87d9741e | 4132 | if (code == LT && op1 == const1_rtx) |
c5c76735 | 4133 | code = LE, op1 = const0_rtx; |
87d9741e | 4134 | else if (code == GT && op1 == constm1_rtx) |
c5c76735 JL |
4135 | code = GE, op1 = const0_rtx; |
4136 | ||
49c4584c DE |
4137 | if (cmode == VOIDmode) |
4138 | cmode = GET_MODE (op0); | |
4139 | ||
e5c56fd9 JH |
4140 | if (swap_commutative_operands_p (op2, op3) |
4141 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4142 | != UNKNOWN)) | |
49c4584c DE |
4143 | { |
4144 | tem = op2; | |
4145 | op2 = op3; | |
4146 | op3 = tem; | |
e5c56fd9 | 4147 | code = reversed; |
49c4584c DE |
4148 | } |
4149 | ||
4150 | if (mode == VOIDmode) | |
4151 | mode = GET_MODE (op2); | |
4152 | ||
4153 | icode = movcc_gen_code[mode]; | |
4154 | ||
4155 | if (icode == CODE_FOR_nothing) | |
4156 | return 0; | |
4157 | ||
4158 | if (flag_force_mem) | |
4159 | { | |
4160 | op2 = force_not_mem (op2); | |
4161 | op3 = force_not_mem (op3); | |
4162 | } | |
4163 | ||
4164 | if (target) | |
4165 | target = protect_from_queue (target, 1); | |
4166 | else | |
4167 | target = gen_reg_rtx (mode); | |
4168 | ||
4169 | subtarget = target; | |
4170 | ||
4171 | emit_queue (); | |
4172 | ||
4173 | op2 = protect_from_queue (op2, 0); | |
4174 | op3 = protect_from_queue (op3, 0); | |
4175 | ||
4176 | /* If the insn doesn't accept these operands, put them in pseudos. */ | |
4177 | ||
a995e389 RH |
4178 | if (! (*insn_data[icode].operand[0].predicate) |
4179 | (subtarget, insn_data[icode].operand[0].mode)) | |
4180 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
49c4584c | 4181 | |
a995e389 RH |
4182 | if (! (*insn_data[icode].operand[2].predicate) |
4183 | (op2, insn_data[icode].operand[2].mode)) | |
4184 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
49c4584c | 4185 | |
a995e389 RH |
4186 | if (! (*insn_data[icode].operand[3].predicate) |
4187 | (op3, insn_data[icode].operand[3].mode)) | |
4188 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
49c4584c DE |
4189 | |
4190 | /* Everything should now be in the suitable form, so emit the compare insn | |
4191 | and then the conditional move. */ | |
4192 | ||
0c20a65f | 4193 | comparison |
a06ef755 | 4194 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
49c4584c DE |
4195 | |
4196 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
144a5f9d JL |
4197 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4198 | return NULL and let the caller figure out how best to deal with this | |
4199 | situation. */ | |
49c4584c | 4200 | if (GET_CODE (comparison) != code) |
144a5f9d | 4201 | return NULL_RTX; |
0c20a65f | 4202 | |
49c4584c DE |
4203 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4204 | ||
4205 | /* If that failed, then give up. */ | |
4206 | if (insn == 0) | |
4207 | return 0; | |
4208 | ||
4209 | emit_insn (insn); | |
4210 | ||
4211 | if (subtarget != target) | |
4212 | convert_move (target, subtarget, 0); | |
4213 | ||
4214 | return target; | |
4215 | } | |
4216 | ||
40f03658 | 4217 | /* Return nonzero if a conditional move of mode MODE is supported. |
49c4584c DE |
4218 | |
4219 | This function is for combine so it can tell whether an insn that looks | |
4220 | like a conditional move is actually supported by the hardware. If we | |
4221 | guess wrong we lose a bit on optimization, but that's it. */ | |
4222 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4223 | comparisons, and vice versa. How do we handle them? */ | |
4224 | ||
4225 | int | |
0c20a65f | 4226 | can_conditionally_move_p (enum machine_mode mode) |
49c4584c DE |
4227 | { |
4228 | if (movcc_gen_code[mode] != CODE_FOR_nothing) | |
4229 | return 1; | |
4230 | ||
4231 | return 0; | |
4232 | } | |
4233 | ||
4234 | #endif /* HAVE_conditional_move */ | |
068f5dea JH |
4235 | |
4236 | /* Emit a conditional addition instruction if the machine supports one for that | |
4237 | condition and machine mode. | |
4238 | ||
4239 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4240 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4241 | both be constants. | |
4242 | ||
4243 | OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3 | |
4244 | should be stored there. MODE is the mode to use should they be constants. | |
4245 | If it is VOIDmode, they cannot both be constants. | |
4246 | ||
4247 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4248 | is not supported. */ | |
4249 | ||
4250 | rtx | |
0c20a65f AJ |
4251 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4252 | enum machine_mode cmode, rtx op2, rtx op3, | |
4253 | enum machine_mode mode, int unsignedp) | |
068f5dea JH |
4254 | { |
4255 | rtx tem, subtarget, comparison, insn; | |
4256 | enum insn_code icode; | |
4257 | enum rtx_code reversed; | |
4258 | ||
4259 | /* If one operand is constant, make it the second one. Only do this | |
4260 | if the other operand is not constant as well. */ | |
4261 | ||
4262 | if (swap_commutative_operands_p (op0, op1)) | |
4263 | { | |
4264 | tem = op0; | |
4265 | op0 = op1; | |
4266 | op1 = tem; | |
4267 | code = swap_condition (code); | |
4268 | } | |
4269 | ||
4270 | /* get_condition will prefer to generate LT and GT even if the old | |
4271 | comparison was against zero, so undo that canonicalization here since | |
4272 | comparisons against zero are cheaper. */ | |
87d9741e | 4273 | if (code == LT && op1 == const1_rtx) |
068f5dea | 4274 | code = LE, op1 = const0_rtx; |
87d9741e | 4275 | else if (code == GT && op1 == constm1_rtx) |
068f5dea JH |
4276 | code = GE, op1 = const0_rtx; |
4277 | ||
4278 | if (cmode == VOIDmode) | |
4279 | cmode = GET_MODE (op0); | |
4280 | ||
4281 | if (swap_commutative_operands_p (op2, op3) | |
4282 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4283 | != UNKNOWN)) | |
4284 | { | |
4285 | tem = op2; | |
4286 | op2 = op3; | |
4287 | op3 = tem; | |
4288 | code = reversed; | |
4289 | } | |
4290 | ||
4291 | if (mode == VOIDmode) | |
4292 | mode = GET_MODE (op2); | |
4293 | ||
4294 | icode = addcc_optab->handlers[(int) mode].insn_code; | |
4295 | ||
4296 | if (icode == CODE_FOR_nothing) | |
4297 | return 0; | |
4298 | ||
4299 | if (flag_force_mem) | |
4300 | { | |
4301 | op2 = force_not_mem (op2); | |
4302 | op3 = force_not_mem (op3); | |
4303 | } | |
4304 | ||
4305 | if (target) | |
4306 | target = protect_from_queue (target, 1); | |
4307 | else | |
4308 | target = gen_reg_rtx (mode); | |
4309 | ||
4310 | subtarget = target; | |
4311 | ||
4312 | emit_queue (); | |
4313 | ||
4314 | op2 = protect_from_queue (op2, 0); | |
4315 | op3 = protect_from_queue (op3, 0); | |
4316 | ||
4317 | /* If the insn doesn't accept these operands, put them in pseudos. */ | |
4318 | ||
4319 | if (! (*insn_data[icode].operand[0].predicate) | |
4320 | (subtarget, insn_data[icode].operand[0].mode)) | |
4321 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
4322 | ||
4323 | if (! (*insn_data[icode].operand[2].predicate) | |
4324 | (op2, insn_data[icode].operand[2].mode)) | |
4325 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
4326 | ||
4327 | if (! (*insn_data[icode].operand[3].predicate) | |
4328 | (op3, insn_data[icode].operand[3].mode)) | |
4329 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
4330 | ||
4331 | /* Everything should now be in the suitable form, so emit the compare insn | |
4332 | and then the conditional move. */ | |
4333 | ||
0c20a65f | 4334 | comparison |
068f5dea JH |
4335 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
4336 | ||
4337 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
4338 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just | |
4339 | return NULL and let the caller figure out how best to deal with this | |
4340 | situation. */ | |
4341 | if (GET_CODE (comparison) != code) | |
4342 | return NULL_RTX; | |
0c20a65f | 4343 | |
068f5dea JH |
4344 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4345 | ||
4346 | /* If that failed, then give up. */ | |
4347 | if (insn == 0) | |
4348 | return 0; | |
4349 | ||
4350 | emit_insn (insn); | |
4351 | ||
4352 | if (subtarget != target) | |
4353 | convert_move (target, subtarget, 0); | |
4354 | ||
4355 | return target; | |
4356 | } | |
49c4584c | 4357 | \f |
0913e4b4 AO |
4358 | /* These functions attempt to generate an insn body, rather than |
4359 | emitting the insn, but if the gen function already emits them, we | |
4360 | make no attempt to turn them back into naked patterns. | |
77c9c6c2 RK |
4361 | |
4362 | They do not protect from queued increments, | |
4363 | because they may be used 1) in protect_from_queue itself | |
4364 | and 2) in other passes where there is no queue. */ | |
4365 | ||
4366 | /* Generate and return an insn body to add Y to X. */ | |
4367 | ||
4368 | rtx | |
0c20a65f | 4369 | gen_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4370 | { |
0c20a65f | 4371 | int icode = (int) add_optab->handlers[(int) GET_MODE (x)].insn_code; |
77c9c6c2 | 4372 | |
a995e389 RH |
4373 | if (! ((*insn_data[icode].operand[0].predicate) |
4374 | (x, insn_data[icode].operand[0].mode)) | |
4375 | || ! ((*insn_data[icode].operand[1].predicate) | |
4376 | (x, insn_data[icode].operand[1].mode)) | |
4377 | || ! ((*insn_data[icode].operand[2].predicate) | |
4378 | (y, insn_data[icode].operand[2].mode))) | |
77c9c6c2 RK |
4379 | abort (); |
4380 | ||
4381 | return (GEN_FCN (icode) (x, x, y)); | |
4382 | } | |
4383 | ||
e78d8e51 ZW |
4384 | /* Generate and return an insn body to add r1 and c, |
4385 | storing the result in r0. */ | |
4386 | rtx | |
0c20a65f | 4387 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
e78d8e51 ZW |
4388 | { |
4389 | int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
4390 | ||
7e1a450d | 4391 | if (icode == CODE_FOR_nothing |
e78d8e51 ZW |
4392 | || ! ((*insn_data[icode].operand[0].predicate) |
4393 | (r0, insn_data[icode].operand[0].mode)) | |
4394 | || ! ((*insn_data[icode].operand[1].predicate) | |
4395 | (r1, insn_data[icode].operand[1].mode)) | |
4396 | || ! ((*insn_data[icode].operand[2].predicate) | |
4397 | (c, insn_data[icode].operand[2].mode))) | |
4398 | return NULL_RTX; | |
4399 | ||
4400 | return (GEN_FCN (icode) (r0, r1, c)); | |
4401 | } | |
4402 | ||
77c9c6c2 | 4403 | int |
0c20a65f | 4404 | have_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4405 | { |
fb7e77d7 TM |
4406 | int icode; |
4407 | ||
4408 | if (GET_MODE (x) == VOIDmode) | |
4409 | abort (); | |
4410 | ||
0c20a65f | 4411 | icode = (int) add_optab->handlers[(int) GET_MODE (x)].insn_code; |
fb7e77d7 TM |
4412 | |
4413 | if (icode == CODE_FOR_nothing) | |
4414 | return 0; | |
4415 | ||
4416 | if (! ((*insn_data[icode].operand[0].predicate) | |
4417 | (x, insn_data[icode].operand[0].mode)) | |
4418 | || ! ((*insn_data[icode].operand[1].predicate) | |
4419 | (x, insn_data[icode].operand[1].mode)) | |
4420 | || ! ((*insn_data[icode].operand[2].predicate) | |
4421 | (y, insn_data[icode].operand[2].mode))) | |
4422 | return 0; | |
4423 | ||
4424 | return 1; | |
77c9c6c2 RK |
4425 | } |
4426 | ||
4427 | /* Generate and return an insn body to subtract Y from X. */ | |
4428 | ||
4429 | rtx | |
0c20a65f | 4430 | gen_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4431 | { |
0c20a65f | 4432 | int icode = (int) sub_optab->handlers[(int) GET_MODE (x)].insn_code; |
77c9c6c2 | 4433 | |
a995e389 RH |
4434 | if (! ((*insn_data[icode].operand[0].predicate) |
4435 | (x, insn_data[icode].operand[0].mode)) | |
4436 | || ! ((*insn_data[icode].operand[1].predicate) | |
4437 | (x, insn_data[icode].operand[1].mode)) | |
4438 | || ! ((*insn_data[icode].operand[2].predicate) | |
4439 | (y, insn_data[icode].operand[2].mode))) | |
77c9c6c2 RK |
4440 | abort (); |
4441 | ||
4442 | return (GEN_FCN (icode) (x, x, y)); | |
4443 | } | |
4444 | ||
ef89d648 ZW |
4445 | /* Generate and return an insn body to subtract r1 and c, |
4446 | storing the result in r0. */ | |
4447 | rtx | |
0c20a65f | 4448 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ef89d648 ZW |
4449 | { |
4450 | int icode = (int) sub_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
4451 | ||
7e1a450d | 4452 | if (icode == CODE_FOR_nothing |
ef89d648 ZW |
4453 | || ! ((*insn_data[icode].operand[0].predicate) |
4454 | (r0, insn_data[icode].operand[0].mode)) | |
4455 | || ! ((*insn_data[icode].operand[1].predicate) | |
4456 | (r1, insn_data[icode].operand[1].mode)) | |
4457 | || ! ((*insn_data[icode].operand[2].predicate) | |
4458 | (c, insn_data[icode].operand[2].mode))) | |
4459 | return NULL_RTX; | |
4460 | ||
4461 | return (GEN_FCN (icode) (r0, r1, c)); | |
4462 | } | |
4463 | ||
77c9c6c2 | 4464 | int |
0c20a65f | 4465 | have_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4466 | { |
fb7e77d7 TM |
4467 | int icode; |
4468 | ||
4469 | if (GET_MODE (x) == VOIDmode) | |
4470 | abort (); | |
4471 | ||
0c20a65f | 4472 | icode = (int) sub_optab->handlers[(int) GET_MODE (x)].insn_code; |
fb7e77d7 TM |
4473 | |
4474 | if (icode == CODE_FOR_nothing) | |
4475 | return 0; | |
4476 | ||
4477 | if (! ((*insn_data[icode].operand[0].predicate) | |
4478 | (x, insn_data[icode].operand[0].mode)) | |
4479 | || ! ((*insn_data[icode].operand[1].predicate) | |
4480 | (x, insn_data[icode].operand[1].mode)) | |
4481 | || ! ((*insn_data[icode].operand[2].predicate) | |
4482 | (y, insn_data[icode].operand[2].mode))) | |
4483 | return 0; | |
4484 | ||
4485 | return 1; | |
77c9c6c2 RK |
4486 | } |
4487 | ||
e3654226 | 4488 | /* Generate the body of an instruction to copy Y into X. |
2f937369 | 4489 | It may be a list of insns, if one insn isn't enough. */ |
77c9c6c2 RK |
4490 | |
4491 | rtx | |
0c20a65f | 4492 | gen_move_insn (rtx x, rtx y) |
77c9c6c2 | 4493 | { |
e3654226 | 4494 | rtx seq; |
77c9c6c2 | 4495 | |
e3654226 RS |
4496 | start_sequence (); |
4497 | emit_move_insn_1 (x, y); | |
2f937369 | 4498 | seq = get_insns (); |
e3654226 RS |
4499 | end_sequence (); |
4500 | return seq; | |
77c9c6c2 RK |
4501 | } |
4502 | \f | |
34e56753 RS |
4503 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4504 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4505 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
77c9c6c2 | 4506 | |
34e56753 | 4507 | enum insn_code |
0c20a65f AJ |
4508 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4509 | int unsignedp) | |
77c9c6c2 | 4510 | { |
85363ca0 | 4511 | convert_optab tab; |
6dd12198 SE |
4512 | #ifdef HAVE_ptr_extend |
4513 | if (unsignedp < 0) | |
4514 | return CODE_FOR_ptr_extend; | |
6dd12198 | 4515 | #endif |
85363ca0 ZW |
4516 | |
4517 | tab = unsignedp ? zext_optab : sext_optab; | |
4518 | return tab->handlers[to_mode][from_mode].insn_code; | |
77c9c6c2 RK |
4519 | } |
4520 | ||
4521 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4522 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4523 | ||
4524 | rtx | |
0c20a65f AJ |
4525 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4526 | enum machine_mode mfrom, int unsignedp) | |
77c9c6c2 | 4527 | { |
85363ca0 ZW |
4528 | enum insn_code icode = can_extend_p (mto, mfrom, unsignedp); |
4529 | return GEN_FCN (icode) (x, y); | |
77c9c6c2 | 4530 | } |
77c9c6c2 RK |
4531 | \f |
4532 | /* can_fix_p and can_float_p say whether the target machine | |
4533 | can directly convert a given fixed point type to | |
4534 | a given floating point type, or vice versa. | |
4535 | The returned value is the CODE_FOR_... value to use, | |
5d81dc5b | 4536 | or CODE_FOR_nothing if these modes cannot be directly converted. |
77c9c6c2 | 4537 | |
5d81dc5b | 4538 | *TRUNCP_PTR is set to 1 if it is necessary to output |
77c9c6c2 RK |
4539 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4540 | ||
4541 | static enum insn_code | |
0c20a65f AJ |
4542 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4543 | int unsignedp, int *truncp_ptr) | |
77c9c6c2 | 4544 | { |
85363ca0 ZW |
4545 | convert_optab tab; |
4546 | enum insn_code icode; | |
4547 | ||
4548 | tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab; | |
4549 | icode = tab->handlers[fixmode][fltmode].insn_code; | |
4550 | if (icode != CODE_FOR_nothing) | |
4551 | { | |
4552 | *truncp_ptr = 0; | |
4553 | return icode; | |
4554 | } | |
77c9c6c2 | 4555 | |
0e1d7f32 AH |
4556 | /* FIXME: This requires a port to define both FIX and FTRUNC pattern |
4557 | for this to work. We need to rework the fix* and ftrunc* patterns | |
4558 | and documentation. */ | |
85363ca0 ZW |
4559 | tab = unsignedp ? ufix_optab : sfix_optab; |
4560 | icode = tab->handlers[fixmode][fltmode].insn_code; | |
4561 | if (icode != CODE_FOR_nothing | |
4562 | && ftrunc_optab->handlers[fltmode].insn_code != CODE_FOR_nothing) | |
77c9c6c2 RK |
4563 | { |
4564 | *truncp_ptr = 1; | |
85363ca0 | 4565 | return icode; |
77c9c6c2 | 4566 | } |
85363ca0 ZW |
4567 | |
4568 | *truncp_ptr = 0; | |
77c9c6c2 RK |
4569 | return CODE_FOR_nothing; |
4570 | } | |
4571 | ||
4572 | static enum insn_code | |
0c20a65f AJ |
4573 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4574 | int unsignedp) | |
77c9c6c2 | 4575 | { |
85363ca0 ZW |
4576 | convert_optab tab; |
4577 | ||
4578 | tab = unsignedp ? ufloat_optab : sfloat_optab; | |
4579 | return tab->handlers[fltmode][fixmode].insn_code; | |
77c9c6c2 | 4580 | } |
77c9c6c2 RK |
4581 | \f |
4582 | /* Generate code to convert FROM to floating point | |
34e56753 | 4583 | and store in TO. FROM must be fixed point and not VOIDmode. |
77c9c6c2 RK |
4584 | UNSIGNEDP nonzero means regard FROM as unsigned. |
4585 | Normally this is done by correcting the final value | |
4586 | if it is negative. */ | |
4587 | ||
4588 | void | |
0c20a65f | 4589 | expand_float (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4590 | { |
4591 | enum insn_code icode; | |
b3694847 | 4592 | rtx target = to; |
77c9c6c2 RK |
4593 | enum machine_mode fmode, imode; |
4594 | ||
34e56753 RS |
4595 | /* Crash now, because we won't be able to decide which mode to use. */ |
4596 | if (GET_MODE (from) == VOIDmode) | |
4597 | abort (); | |
4598 | ||
77c9c6c2 RK |
4599 | /* Look for an insn to do the conversion. Do it in the specified |
4600 | modes if possible; otherwise convert either input, output or both to | |
4601 | wider mode. If the integer mode is wider than the mode of FROM, | |
4602 | we can do the conversion signed even if the input is unsigned. */ | |
4603 | ||
7bf0a593 AP |
4604 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4605 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4606 | for (imode = GET_MODE (from); imode != VOIDmode; | |
4607 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4608 | { |
4609 | int doing_unsigned = unsignedp; | |
4610 | ||
5ba02ca6 GK |
4611 | if (fmode != GET_MODE (to) |
4612 | && significand_size (fmode) < GET_MODE_BITSIZE (GET_MODE (from))) | |
4613 | continue; | |
4614 | ||
77c9c6c2 RK |
4615 | icode = can_float_p (fmode, imode, unsignedp); |
4616 | if (icode == CODE_FOR_nothing && imode != GET_MODE (from) && unsignedp) | |
4617 | icode = can_float_p (fmode, imode, 0), doing_unsigned = 0; | |
4618 | ||
4619 | if (icode != CODE_FOR_nothing) | |
4620 | { | |
4621 | to = protect_from_queue (to, 1); | |
06e40b26 | 4622 | from = protect_from_queue (from, 0); |
77c9c6c2 RK |
4623 | |
4624 | if (imode != GET_MODE (from)) | |
4625 | from = convert_to_mode (imode, from, unsignedp); | |
77c9c6c2 RK |
4626 | |
4627 | if (fmode != GET_MODE (to)) | |
4628 | target = gen_reg_rtx (fmode); | |
4629 | ||
4630 | emit_unop_insn (icode, target, from, | |
4631 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
4632 | ||
4633 | if (target != to) | |
4634 | convert_move (to, target, 0); | |
4635 | return; | |
4636 | } | |
7e1a450d | 4637 | } |
77c9c6c2 | 4638 | |
77c9c6c2 RK |
4639 | /* Unsigned integer, and no way to convert directly. |
4640 | Convert as signed, then conditionally adjust the result. */ | |
4641 | if (unsignedp) | |
4642 | { | |
4643 | rtx label = gen_label_rtx (); | |
4644 | rtx temp; | |
4645 | REAL_VALUE_TYPE offset; | |
4646 | ||
4647 | emit_queue (); | |
4648 | ||
4649 | to = protect_from_queue (to, 1); | |
4650 | from = protect_from_queue (from, 0); | |
4651 | ||
4652 | if (flag_force_mem) | |
4653 | from = force_not_mem (from); | |
4654 | ||
c95c47f3 PE |
4655 | /* Look for a usable floating mode FMODE wider than the source and at |
4656 | least as wide as the target. Using FMODE will avoid rounding woes | |
4657 | with unsigned values greater than the signed maximum value. */ | |
70864443 | 4658 | |
c95c47f3 PE |
4659 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4660 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4661 | if (GET_MODE_BITSIZE (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) | |
4662 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) | |
4663 | break; | |
a48fb61b | 4664 | |
c95c47f3 PE |
4665 | if (fmode == VOIDmode) |
4666 | { | |
a48fb61b | 4667 | /* There is no such mode. Pretend the target is wide enough. */ |
c95c47f3 | 4668 | fmode = GET_MODE (to); |
a48fb61b | 4669 | |
0f41302f | 4670 | /* Avoid double-rounding when TO is narrower than FROM. */ |
a48fb61b RK |
4671 | if ((significand_size (fmode) + 1) |
4672 | < GET_MODE_BITSIZE (GET_MODE (from))) | |
4673 | { | |
4674 | rtx temp1; | |
4675 | rtx neglabel = gen_label_rtx (); | |
4676 | ||
0c20a65f | 4677 | /* Don't use TARGET if it isn't a register, is a hard register, |
70864443 | 4678 | or is the wrong mode. */ |
44f51d4a | 4679 | if (GET_CODE (target) != REG |
70864443 RK |
4680 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
4681 | || GET_MODE (target) != fmode) | |
44f51d4a RK |
4682 | target = gen_reg_rtx (fmode); |
4683 | ||
a48fb61b RK |
4684 | imode = GET_MODE (from); |
4685 | do_pending_stack_adjust (); | |
4686 | ||
4687 | /* Test whether the sign bit is set. */ | |
1c0290ea | 4688 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
a06ef755 | 4689 | 0, neglabel); |
a48fb61b RK |
4690 | |
4691 | /* The sign bit is not set. Convert as signed. */ | |
4692 | expand_float (target, from, 0); | |
4693 | emit_jump_insn (gen_jump (label)); | |
2ad79487 | 4694 | emit_barrier (); |
a48fb61b RK |
4695 | |
4696 | /* The sign bit is set. | |
4697 | Convert to a usable (positive signed) value by shifting right | |
4698 | one bit, while remembering if a nonzero bit was shifted | |
4699 | out; i.e., compute (from & 1) | (from >> 1). */ | |
4700 | ||
4701 | emit_label (neglabel); | |
4702 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
70864443 | 4703 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
73d9a835 RK |
4704 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, integer_one_node, |
4705 | NULL_RTX, 1); | |
0c20a65f | 4706 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
70864443 | 4707 | OPTAB_LIB_WIDEN); |
a48fb61b RK |
4708 | expand_float (target, temp, 0); |
4709 | ||
4710 | /* Multiply by 2 to undo the shift above. */ | |
a93738eb | 4711 | temp = expand_binop (fmode, add_optab, target, target, |
7e1a450d | 4712 | target, 0, OPTAB_LIB_WIDEN); |
a93738eb RK |
4713 | if (temp != target) |
4714 | emit_move_insn (target, temp); | |
4715 | ||
a48fb61b RK |
4716 | do_pending_stack_adjust (); |
4717 | emit_label (label); | |
4718 | goto done; | |
4719 | } | |
c95c47f3 PE |
4720 | } |
4721 | ||
77c9c6c2 RK |
4722 | /* If we are about to do some arithmetic to correct for an |
4723 | unsigned operand, do it in a pseudo-register. */ | |
4724 | ||
c95c47f3 | 4725 | if (GET_MODE (to) != fmode |
70864443 | 4726 | || GET_CODE (to) != REG || REGNO (to) < FIRST_PSEUDO_REGISTER) |
c95c47f3 | 4727 | target = gen_reg_rtx (fmode); |
77c9c6c2 RK |
4728 | |
4729 | /* Convert as signed integer to floating. */ | |
4730 | expand_float (target, from, 0); | |
4731 | ||
4732 | /* If FROM is negative (and therefore TO is negative), | |
4733 | correct its value by 2**bitwidth. */ | |
4734 | ||
4735 | do_pending_stack_adjust (); | |
c5d5d461 | 4736 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 4737 | 0, label); |
70864443 | 4738 | |
0c20a65f | 4739 | |
efdc7e19 | 4740 | real_2expN (&offset, GET_MODE_BITSIZE (GET_MODE (from))); |
c95c47f3 | 4741 | temp = expand_binop (fmode, add_optab, target, |
30d88916 | 4742 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
77c9c6c2 RK |
4743 | target, 0, OPTAB_LIB_WIDEN); |
4744 | if (temp != target) | |
4745 | emit_move_insn (target, temp); | |
a48fb61b | 4746 | |
77c9c6c2 RK |
4747 | do_pending_stack_adjust (); |
4748 | emit_label (label); | |
70864443 | 4749 | goto done; |
77c9c6c2 | 4750 | } |
77c9c6c2 | 4751 | |
85363ca0 | 4752 | /* No hardware instruction available; call a library routine. */ |
77c9c6c2 | 4753 | { |
85363ca0 | 4754 | rtx libfunc; |
77c9c6c2 | 4755 | rtx insns; |
9a7f678c | 4756 | rtx value; |
85363ca0 | 4757 | convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab; |
77c9c6c2 RK |
4758 | |
4759 | to = protect_from_queue (to, 1); | |
06e40b26 | 4760 | from = protect_from_queue (from, 0); |
77c9c6c2 RK |
4761 | |
4762 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) | |
4763 | from = convert_to_mode (SImode, from, unsignedp); | |
77c9c6c2 RK |
4764 | |
4765 | if (flag_force_mem) | |
4766 | from = force_not_mem (from); | |
4767 | ||
85363ca0 ZW |
4768 | libfunc = tab->handlers[GET_MODE (to)][GET_MODE (from)].libfunc; |
4769 | if (!libfunc) | |
77c9c6c2 RK |
4770 | abort (); |
4771 | ||
4772 | start_sequence (); | |
4773 | ||
85363ca0 | 4774 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
4775 | GET_MODE (to), 1, from, |
4776 | GET_MODE (from)); | |
77c9c6c2 RK |
4777 | insns = get_insns (); |
4778 | end_sequence (); | |
4779 | ||
9a7f678c | 4780 | emit_libcall_block (insns, target, value, |
9e6a5703 | 4781 | gen_rtx_FLOAT (GET_MODE (to), from)); |
77c9c6c2 RK |
4782 | } |
4783 | ||
a48fb61b RK |
4784 | done: |
4785 | ||
77c9c6c2 RK |
4786 | /* Copy result to requested destination |
4787 | if we have been computing in a temp location. */ | |
4788 | ||
4789 | if (target != to) | |
4790 | { | |
4791 | if (GET_MODE (target) == GET_MODE (to)) | |
4792 | emit_move_insn (to, target); | |
4793 | else | |
4794 | convert_move (to, target, 0); | |
4795 | } | |
4796 | } | |
4797 | \f | |
0e1d7f32 AH |
4798 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
4799 | must be floating point. */ | |
77c9c6c2 RK |
4800 | |
4801 | void | |
0c20a65f | 4802 | expand_fix (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4803 | { |
4804 | enum insn_code icode; | |
b3694847 | 4805 | rtx target = to; |
77c9c6c2 RK |
4806 | enum machine_mode fmode, imode; |
4807 | int must_trunc = 0; | |
77c9c6c2 RK |
4808 | |
4809 | /* We first try to find a pair of modes, one real and one integer, at | |
4810 | least as wide as FROM and TO, respectively, in which we can open-code | |
4811 | this conversion. If the integer mode is wider than the mode of TO, | |
4812 | we can do the conversion either signed or unsigned. */ | |
4813 | ||
3987b9db JH |
4814 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
4815 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4816 | for (imode = GET_MODE (to); imode != VOIDmode; | |
4817 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4818 | { |
4819 | int doing_unsigned = unsignedp; | |
4820 | ||
4821 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
4822 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
4823 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
4824 | ||
4825 | if (icode != CODE_FOR_nothing) | |
4826 | { | |
4827 | to = protect_from_queue (to, 1); | |
06e40b26 | 4828 | from = protect_from_queue (from, 0); |
77c9c6c2 RK |
4829 | |
4830 | if (fmode != GET_MODE (from)) | |
4831 | from = convert_to_mode (fmode, from, 0); | |
77c9c6c2 RK |
4832 | |
4833 | if (must_trunc) | |
0e1d7f32 AH |
4834 | { |
4835 | rtx temp = gen_reg_rtx (GET_MODE (from)); | |
4836 | from = expand_unop (GET_MODE (from), ftrunc_optab, from, | |
4837 | temp, 0); | |
4838 | } | |
77c9c6c2 RK |
4839 | |
4840 | if (imode != GET_MODE (to)) | |
4841 | target = gen_reg_rtx (imode); | |
4842 | ||
4843 | emit_unop_insn (icode, target, from, | |
4844 | doing_unsigned ? UNSIGNED_FIX : FIX); | |
4845 | if (target != to) | |
4846 | convert_move (to, target, unsignedp); | |
4847 | return; | |
4848 | } | |
4849 | } | |
4850 | ||
77c9c6c2 RK |
4851 | /* For an unsigned conversion, there is one more way to do it. |
4852 | If we have a signed conversion, we generate code that compares | |
4853 | the real value to the largest representable positive number. If if | |
4854 | is smaller, the conversion is done normally. Otherwise, subtract | |
4855 | one plus the highest signed number, convert, and add it back. | |
4856 | ||
4857 | We only need to check all real modes, since we know we didn't find | |
0c20a65f | 4858 | anything with a wider integer mode. |
0d446150 JH |
4859 | |
4860 | This code used to extend FP value into mode wider than the destination. | |
4861 | This is not needed. Consider, for instance conversion from SFmode | |
4862 | into DImode. | |
4863 | ||
4864 | The hot path trought the code is dealing with inputs smaller than 2^63 | |
4865 | and doing just the conversion, so there is no bits to lose. | |
4866 | ||
4867 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
4868 | inclusive. (as for other imput overflow happens and result is undefined) | |
e0bb17a8 | 4869 | So we know that the most important bit set in mantissa corresponds to |
0d446150 JH |
4870 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
4871 | simply clears out that bit. The rest is trivial. */ | |
77c9c6c2 | 4872 | |
b1ec3c92 | 4873 | if (unsignedp && GET_MODE_BITSIZE (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
77c9c6c2 RK |
4874 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
4875 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
0d446150 JH |
4876 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, |
4877 | &must_trunc)) | |
77c9c6c2 | 4878 | { |
e9f7ae44 RS |
4879 | int bitsize; |
4880 | REAL_VALUE_TYPE offset; | |
4881 | rtx limit, lab1, lab2, insn; | |
4882 | ||
4883 | bitsize = GET_MODE_BITSIZE (GET_MODE (to)); | |
efdc7e19 | 4884 | real_2expN (&offset, bitsize - 1); |
30d88916 | 4885 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
e9f7ae44 RS |
4886 | lab1 = gen_label_rtx (); |
4887 | lab2 = gen_label_rtx (); | |
77c9c6c2 RK |
4888 | |
4889 | emit_queue (); | |
4890 | to = protect_from_queue (to, 1); | |
4891 | from = protect_from_queue (from, 0); | |
4892 | ||
4893 | if (flag_force_mem) | |
4894 | from = force_not_mem (from); | |
4895 | ||
4896 | if (fmode != GET_MODE (from)) | |
4897 | from = convert_to_mode (fmode, from, 0); | |
4898 | ||
4899 | /* See if we need to do the subtraction. */ | |
4900 | do_pending_stack_adjust (); | |
c5d5d461 | 4901 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 4902 | 0, lab1); |
77c9c6c2 RK |
4903 | |
4904 | /* If not, do the signed "fix" and branch around fixup code. */ | |
4905 | expand_fix (to, from, 0); | |
4906 | emit_jump_insn (gen_jump (lab2)); | |
4907 | emit_barrier (); | |
4908 | ||
4909 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
4910 | then add 2**(N-1). Do the addition using XOR since this | |
4911 | will often generate better code. */ | |
4912 | emit_label (lab1); | |
4913 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
b1ec3c92 | 4914 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
77c9c6c2 RK |
4915 | expand_fix (to, target, 0); |
4916 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2496c7bd LB |
4917 | gen_int_mode |
4918 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
4919 | GET_MODE (to)), | |
77c9c6c2 RK |
4920 | to, 1, OPTAB_LIB_WIDEN); |
4921 | ||
4922 | if (target != to) | |
4923 | emit_move_insn (to, target); | |
4924 | ||
4925 | emit_label (lab2); | |
4926 | ||
02214a5c RK |
4927 | if (mov_optab->handlers[(int) GET_MODE (to)].insn_code |
4928 | != CODE_FOR_nothing) | |
4929 | { | |
4930 | /* Make a place for a REG_NOTE and add it. */ | |
4931 | insn = emit_move_insn (to, to); | |
5fa671cf AM |
4932 | set_unique_reg_note (insn, |
4933 | REG_EQUAL, | |
4934 | gen_rtx_fmt_e (UNSIGNED_FIX, | |
4935 | GET_MODE (to), | |
4936 | copy_rtx (from))); | |
02214a5c | 4937 | } |
c5c76735 | 4938 | |
77c9c6c2 RK |
4939 | return; |
4940 | } | |
77c9c6c2 RK |
4941 | |
4942 | /* We can't do it with an insn, so use a library call. But first ensure | |
4943 | that the mode of TO is at least as wide as SImode, since those are the | |
4944 | only library calls we know about. */ | |
4945 | ||
4946 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
4947 | { | |
4948 | target = gen_reg_rtx (SImode); | |
4949 | ||
4950 | expand_fix (target, from, unsignedp); | |
4951 | } | |
77c9c6c2 | 4952 | else |
77c9c6c2 RK |
4953 | { |
4954 | rtx insns; | |
560f3f8a | 4955 | rtx value; |
85363ca0 ZW |
4956 | rtx libfunc; |
4957 | ||
4958 | convert_optab tab = unsignedp ? ufix_optab : sfix_optab; | |
4959 | libfunc = tab->handlers[GET_MODE (to)][GET_MODE (from)].libfunc; | |
4960 | if (!libfunc) | |
4961 | abort (); | |
77c9c6c2 RK |
4962 | |
4963 | to = protect_from_queue (to, 1); | |
4964 | from = protect_from_queue (from, 0); | |
4965 | ||
4966 | if (flag_force_mem) | |
4967 | from = force_not_mem (from); | |
4968 | ||
4969 | start_sequence (); | |
4970 | ||
85363ca0 | 4971 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
4972 | GET_MODE (to), 1, from, |
4973 | GET_MODE (from)); | |
77c9c6c2 RK |
4974 | insns = get_insns (); |
4975 | end_sequence (); | |
4976 | ||
560f3f8a | 4977 | emit_libcall_block (insns, target, value, |
9e6a5703 JC |
4978 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
4979 | GET_MODE (to), from)); | |
77c9c6c2 | 4980 | } |
0c20a65f | 4981 | |
3e53ea48 RK |
4982 | if (target != to) |
4983 | { | |
4984 | if (GET_MODE (to) == GET_MODE (target)) | |
4985 | emit_move_insn (to, target); | |
4986 | else | |
4987 | convert_move (to, target, 0); | |
4988 | } | |
77c9c6c2 RK |
4989 | } |
4990 | \f | |
ef89d648 ZW |
4991 | /* Report whether we have an instruction to perform the operation |
4992 | specified by CODE on operands of mode MODE. */ | |
4993 | int | |
0c20a65f | 4994 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ef89d648 ZW |
4995 | { |
4996 | return (code_to_optab[(int) code] != 0 | |
4997 | && (code_to_optab[(int) code]->handlers[(int) mode].insn_code | |
4998 | != CODE_FOR_nothing)); | |
4999 | } | |
5000 | ||
5001 | /* Create a blank optab. */ | |
5002 | static optab | |
0c20a65f | 5003 | new_optab (void) |
77c9c6c2 RK |
5004 | { |
5005 | int i; | |
703ad42b | 5006 | optab op = ggc_alloc (sizeof (struct optab)); |
77c9c6c2 RK |
5007 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
5008 | { | |
5009 | op->handlers[i].insn_code = CODE_FOR_nothing; | |
5010 | op->handlers[i].libfunc = 0; | |
5011 | } | |
377017c4 | 5012 | |
ef89d648 ZW |
5013 | return op; |
5014 | } | |
377017c4 | 5015 | |
85363ca0 ZW |
5016 | static convert_optab |
5017 | new_convert_optab (void) | |
5018 | { | |
5019 | int i, j; | |
5020 | convert_optab op = ggc_alloc (sizeof (struct convert_optab)); | |
5021 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
5022 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
5023 | { | |
5024 | op->handlers[i][j].insn_code = CODE_FOR_nothing; | |
5025 | op->handlers[i][j].libfunc = 0; | |
5026 | } | |
5027 | return op; | |
5028 | } | |
5029 | ||
ef89d648 ZW |
5030 | /* Same, but fill in its code as CODE, and write it into the |
5031 | code_to_optab table. */ | |
5032 | static inline optab | |
0c20a65f | 5033 | init_optab (enum rtx_code code) |
ef89d648 ZW |
5034 | { |
5035 | optab op = new_optab (); | |
5036 | op->code = code; | |
5037 | code_to_optab[(int) code] = op; | |
5038 | return op; | |
5039 | } | |
5040 | ||
5041 | /* Same, but fill in its code as CODE, and do _not_ write it into | |
5042 | the code_to_optab table. */ | |
5043 | static inline optab | |
0c20a65f | 5044 | init_optabv (enum rtx_code code) |
ef89d648 ZW |
5045 | { |
5046 | optab op = new_optab (); | |
5047 | op->code = code; | |
77c9c6c2 RK |
5048 | return op; |
5049 | } | |
5050 | ||
85363ca0 ZW |
5051 | /* Conversion optabs never go in the code_to_optab table. */ |
5052 | static inline convert_optab | |
5053 | init_convert_optab (enum rtx_code code) | |
5054 | { | |
5055 | convert_optab op = new_convert_optab (); | |
5056 | op->code = code; | |
5057 | return op; | |
5058 | } | |
5059 | ||
b092b471 JW |
5060 | /* Initialize the libfunc fields of an entire group of entries in some |
5061 | optab. Each entry is set equal to a string consisting of a leading | |
5062 | pair of underscores followed by a generic operation name followed by | |
7ef0daad | 5063 | a mode name (downshifted to lowercase) followed by a single character |
b092b471 JW |
5064 | representing the number of operands for the given operation (which is |
5065 | usually one of the characters '2', '3', or '4'). | |
5066 | ||
5067 | OPTABLE is the table in which libfunc fields are to be initialized. | |
5068 | FIRST_MODE is the first machine mode index in the given optab to | |
5069 | initialize. | |
5070 | LAST_MODE is the last machine mode index in the given optab to | |
5071 | initialize. | |
5072 | OPNAME is the generic (string) name of the operation. | |
5073 | SUFFIX is the character which specifies the number of operands for | |
5074 | the given generic operation. | |
5075 | */ | |
5076 | ||
5077 | static void | |
0c20a65f AJ |
5078 | init_libfuncs (optab optable, int first_mode, int last_mode, |
5079 | const char *opname, int suffix) | |
b092b471 | 5080 | { |
b3694847 SS |
5081 | int mode; |
5082 | unsigned opname_len = strlen (opname); | |
b092b471 | 5083 | |
fe0035ff RS |
5084 | for (mode = first_mode; (int) mode <= (int) last_mode; |
5085 | mode = (enum machine_mode) ((int) mode + 1)) | |
b092b471 | 5086 | { |
7e1a450d | 5087 | const char *mname = GET_MODE_NAME (mode); |
b3694847 SS |
5088 | unsigned mname_len = strlen (mname); |
5089 | char *libfunc_name = alloca (2 + opname_len + mname_len + 1 + 1); | |
5090 | char *p; | |
5091 | const char *q; | |
b092b471 JW |
5092 | |
5093 | p = libfunc_name; | |
5094 | *p++ = '_'; | |
5095 | *p++ = '_'; | |
5096 | for (q = opname; *q; ) | |
5097 | *p++ = *q++; | |
5098 | for (q = mname; *q; q++) | |
92a438d1 | 5099 | *p++ = TOLOWER (*q); |
b092b471 | 5100 | *p++ = suffix; |
520a57c8 | 5101 | *p = '\0'; |
76095e2f | 5102 | |
b092b471 | 5103 | optable->handlers[(int) mode].libfunc |
68d28100 | 5104 | = init_one_libfunc (ggc_alloc_string (libfunc_name, p - libfunc_name)); |
b092b471 JW |
5105 | } |
5106 | } | |
5107 | ||
5108 | /* Initialize the libfunc fields of an entire group of entries in some | |
5109 | optab which correspond to all integer mode operations. The parameters | |
5110 | have the same meaning as similarly named ones for the `init_libfuncs' | |
5111 | routine. (See above). */ | |
5112 | ||
5113 | static void | |
0c20a65f | 5114 | init_integral_libfuncs (optab optable, const char *opname, int suffix) |
b092b471 | 5115 | { |
c0510d84 DD |
5116 | int maxsize = 2*BITS_PER_WORD; |
5117 | if (maxsize < LONG_LONG_TYPE_SIZE) | |
5118 | maxsize = LONG_LONG_TYPE_SIZE; | |
8275b011 | 5119 | init_libfuncs (optable, word_mode, |
c0510d84 | 5120 | mode_for_size (maxsize, MODE_INT, 0), |
8275b011 | 5121 | opname, suffix); |
b092b471 JW |
5122 | } |
5123 | ||
5124 | /* Initialize the libfunc fields of an entire group of entries in some | |
5125 | optab which correspond to all real mode operations. The parameters | |
5126 | have the same meaning as similarly named ones for the `init_libfuncs' | |
5127 | routine. (See above). */ | |
5128 | ||
5129 | static void | |
0c20a65f | 5130 | init_floating_libfuncs (optab optable, const char *opname, int suffix) |
b092b471 | 5131 | { |
d1d3865f | 5132 | init_libfuncs (optable, MIN_MODE_FLOAT, MAX_MODE_FLOAT, opname, suffix); |
b092b471 JW |
5133 | } |
5134 | ||
85363ca0 ZW |
5135 | /* Initialize the libfunc fields of an entire group of entries of an |
5136 | inter-mode-class conversion optab. The string formation rules are | |
5137 | similar to the ones for init_libfuncs, above, but instead of having | |
5138 | a mode name and an operand count these functions have two mode names | |
5139 | and no operand count. */ | |
5140 | static void | |
5141 | init_interclass_conv_libfuncs (convert_optab tab, const char *opname, | |
5142 | enum mode_class from_class, | |
5143 | enum mode_class to_class) | |
5144 | { | |
5145 | enum machine_mode first_from_mode = GET_CLASS_NARROWEST_MODE (from_class); | |
5146 | enum machine_mode first_to_mode = GET_CLASS_NARROWEST_MODE (to_class); | |
5147 | size_t opname_len = strlen (opname); | |
5148 | size_t max_mname_len = 0; | |
5149 | ||
5150 | enum machine_mode fmode, tmode; | |
5151 | const char *fname, *tname; | |
5152 | const char *q; | |
5153 | char *libfunc_name, *suffix; | |
5154 | char *p; | |
5155 | ||
5156 | for (fmode = first_from_mode; | |
5157 | fmode != VOIDmode; | |
5158 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5159 | max_mname_len = MAX (max_mname_len, strlen (GET_MODE_NAME (fmode))); | |
5160 | ||
5161 | for (tmode = first_to_mode; | |
5162 | tmode != VOIDmode; | |
5163 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
5164 | max_mname_len = MAX (max_mname_len, strlen (GET_MODE_NAME (tmode))); | |
5165 | ||
5166 | libfunc_name = alloca (2 + opname_len + 2*max_mname_len + 1 + 1); | |
5167 | libfunc_name[0] = '_'; | |
5168 | libfunc_name[1] = '_'; | |
5169 | memcpy (&libfunc_name[2], opname, opname_len); | |
5170 | suffix = libfunc_name + opname_len + 2; | |
5171 | ||
5172 | for (fmode = first_from_mode; fmode != VOIDmode; | |
5173 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5174 | for (tmode = first_to_mode; tmode != VOIDmode; | |
5175 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
5176 | { | |
5177 | fname = GET_MODE_NAME (fmode); | |
5178 | tname = GET_MODE_NAME (tmode); | |
5179 | ||
5180 | p = suffix; | |
5181 | for (q = fname; *q; p++, q++) | |
5182 | *p = TOLOWER (*q); | |
5183 | for (q = tname; *q; p++, q++) | |
5184 | *p = TOLOWER (*q); | |
5185 | ||
5186 | *p = '\0'; | |
5187 | ||
5188 | tab->handlers[tmode][fmode].libfunc | |
5189 | = init_one_libfunc (ggc_alloc_string (libfunc_name, | |
5190 | p - libfunc_name)); | |
5191 | } | |
5192 | } | |
5193 | ||
5194 | /* Initialize the libfunc fields of an entire group of entries of an | |
5195 | intra-mode-class conversion optab. The string formation rules are | |
5196 | similar to the ones for init_libfunc, above. WIDENING says whether | |
5197 | the optab goes from narrow to wide modes or vice versa. These functions | |
5198 | have two mode names _and_ an operand count. */ | |
5199 | static void | |
5200 | init_intraclass_conv_libfuncs (convert_optab tab, const char *opname, | |
5201 | enum mode_class class, bool widening) | |
5202 | { | |
5203 | enum machine_mode first_mode = GET_CLASS_NARROWEST_MODE (class); | |
5204 | size_t opname_len = strlen (opname); | |
5205 | size_t max_mname_len = 0; | |
5206 | ||
5207 | enum machine_mode nmode, wmode; | |
5208 | const char *nname, *wname; | |
5209 | const char *q; | |
5210 | char *libfunc_name, *suffix; | |
5211 | char *p; | |
5212 | ||
5213 | for (nmode = first_mode; nmode != VOIDmode; | |
5214 | nmode = GET_MODE_WIDER_MODE (nmode)) | |
5215 | max_mname_len = MAX (max_mname_len, strlen (GET_MODE_NAME (nmode))); | |
5216 | ||
5217 | libfunc_name = alloca (2 + opname_len + 2*max_mname_len + 1 + 1); | |
5218 | libfunc_name[0] = '_'; | |
5219 | libfunc_name[1] = '_'; | |
5220 | memcpy (&libfunc_name[2], opname, opname_len); | |
5221 | suffix = libfunc_name + opname_len + 2; | |
5222 | ||
5223 | for (nmode = first_mode; nmode != VOIDmode; | |
5224 | nmode = GET_MODE_WIDER_MODE (nmode)) | |
5225 | for (wmode = GET_MODE_WIDER_MODE (nmode); wmode != VOIDmode; | |
5226 | wmode = GET_MODE_WIDER_MODE (wmode)) | |
5227 | { | |
5228 | nname = GET_MODE_NAME (nmode); | |
5229 | wname = GET_MODE_NAME (wmode); | |
5230 | ||
5231 | p = suffix; | |
5232 | for (q = widening ? nname : wname; *q; p++, q++) | |
5233 | *p = TOLOWER (*q); | |
5234 | for (q = widening ? wname : nname; *q; p++, q++) | |
5235 | *p = TOLOWER (*q); | |
5236 | ||
5237 | *p++ = '2'; | |
5238 | *p = '\0'; | |
5239 | ||
456bc4bb RE |
5240 | tab->handlers[widening ? wmode : nmode] |
5241 | [widening ? nmode : wmode].libfunc | |
85363ca0 ZW |
5242 | = init_one_libfunc (ggc_alloc_string (libfunc_name, |
5243 | p - libfunc_name)); | |
5244 | } | |
5245 | } | |
5246 | ||
5247 | ||
76095e2f | 5248 | rtx |
0c20a65f | 5249 | init_one_libfunc (const char *name) |
76095e2f | 5250 | { |
52859c77 RH |
5251 | rtx symbol; |
5252 | ||
fb49053f RH |
5253 | /* Create a FUNCTION_DECL that can be passed to |
5254 | targetm.encode_section_info. */ | |
ee1315aa | 5255 | /* ??? We don't have any type information except for this is |
9c2f7166 | 5256 | a function. Pretend this is "int foo()". */ |
ee1315aa | 5257 | tree decl = build_decl (FUNCTION_DECL, get_identifier (name), |
9c2f7166 | 5258 | build_function_type (integer_type_node, NULL_TREE)); |
ee1315aa RH |
5259 | DECL_ARTIFICIAL (decl) = 1; |
5260 | DECL_EXTERNAL (decl) = 1; | |
5261 | TREE_PUBLIC (decl) = 1; | |
5262 | ||
52859c77 RH |
5263 | symbol = XEXP (DECL_RTL (decl), 0); |
5264 | ||
5265 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
5266 | are the flags assigned by targetm.encode_section_info. */ | |
5267 | SYMBOL_REF_DECL (symbol) = 0; | |
5268 | ||
5269 | return symbol; | |
76095e2f RH |
5270 | } |
5271 | ||
c15c90bb ZW |
5272 | /* Call this to reset the function entry for one optab (OPTABLE) in mode |
5273 | MODE to NAME, which should be either 0 or a string constant. */ | |
5274 | void | |
5275 | set_optab_libfunc (optab optable, enum machine_mode mode, const char *name) | |
5276 | { | |
5277 | if (name) | |
5278 | optable->handlers[mode].libfunc = init_one_libfunc (name); | |
5279 | else | |
5280 | optable->handlers[mode].libfunc = 0; | |
5281 | } | |
5282 | ||
85363ca0 ZW |
5283 | /* Call this to reset the function entry for one conversion optab |
5284 | (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be | |
5285 | either 0 or a string constant. */ | |
5286 | void | |
5287 | set_conv_libfunc (convert_optab optable, enum machine_mode tmode, | |
5288 | enum machine_mode fmode, const char *name) | |
5289 | { | |
5290 | if (name) | |
5291 | optable->handlers[tmode][fmode].libfunc = init_one_libfunc (name); | |
5292 | else | |
5293 | optable->handlers[tmode][fmode].libfunc = 0; | |
5294 | } | |
5295 | ||
77c9c6c2 RK |
5296 | /* Call this once to initialize the contents of the optabs |
5297 | appropriately for the current target machine. */ | |
5298 | ||
5299 | void | |
0c20a65f | 5300 | init_optabs (void) |
77c9c6c2 | 5301 | { |
85363ca0 | 5302 | unsigned int i; |
77c9c6c2 | 5303 | |
5d81dc5b | 5304 | /* Start by initializing all tables to contain CODE_FOR_nothing. */ |
77c9c6c2 | 5305 | |
5d81dc5b RK |
5306 | for (i = 0; i < NUM_RTX_CODE; i++) |
5307 | setcc_gen_code[i] = CODE_FOR_nothing; | |
5308 | ||
49c4584c DE |
5309 | #ifdef HAVE_conditional_move |
5310 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
5311 | movcc_gen_code[i] = CODE_FOR_nothing; | |
5312 | #endif | |
5313 | ||
5d81dc5b | 5314 | add_optab = init_optab (PLUS); |
ef89d648 | 5315 | addv_optab = init_optabv (PLUS); |
5d81dc5b | 5316 | sub_optab = init_optab (MINUS); |
ef89d648 | 5317 | subv_optab = init_optabv (MINUS); |
5d81dc5b | 5318 | smul_optab = init_optab (MULT); |
ef89d648 | 5319 | smulv_optab = init_optabv (MULT); |
5035bbfe TG |
5320 | smul_highpart_optab = init_optab (UNKNOWN); |
5321 | umul_highpart_optab = init_optab (UNKNOWN); | |
5d81dc5b RK |
5322 | smul_widen_optab = init_optab (UNKNOWN); |
5323 | umul_widen_optab = init_optab (UNKNOWN); | |
5324 | sdiv_optab = init_optab (DIV); | |
ef89d648 | 5325 | sdivv_optab = init_optabv (DIV); |
5d81dc5b RK |
5326 | sdivmod_optab = init_optab (UNKNOWN); |
5327 | udiv_optab = init_optab (UDIV); | |
5328 | udivmod_optab = init_optab (UNKNOWN); | |
5329 | smod_optab = init_optab (MOD); | |
5330 | umod_optab = init_optab (UMOD); | |
77c9c6c2 RK |
5331 | ftrunc_optab = init_optab (UNKNOWN); |
5332 | and_optab = init_optab (AND); | |
5333 | ior_optab = init_optab (IOR); | |
5334 | xor_optab = init_optab (XOR); | |
5335 | ashl_optab = init_optab (ASHIFT); | |
5336 | ashr_optab = init_optab (ASHIFTRT); | |
77c9c6c2 RK |
5337 | lshr_optab = init_optab (LSHIFTRT); |
5338 | rotl_optab = init_optab (ROTATE); | |
5339 | rotr_optab = init_optab (ROTATERT); | |
5340 | smin_optab = init_optab (SMIN); | |
5341 | smax_optab = init_optab (SMAX); | |
5342 | umin_optab = init_optab (UMIN); | |
5343 | umax_optab = init_optab (UMAX); | |
b5e01d4b RS |
5344 | pow_optab = init_optab (UNKNOWN); |
5345 | atan2_optab = init_optab (UNKNOWN); | |
ef89d648 ZW |
5346 | |
5347 | /* These three have codes assigned exclusively for the sake of | |
5348 | have_insn_for. */ | |
5349 | mov_optab = init_optab (SET); | |
5350 | movstrict_optab = init_optab (STRICT_LOW_PART); | |
5351 | cmp_optab = init_optab (COMPARE); | |
5352 | ||
77c9c6c2 RK |
5353 | ucmp_optab = init_optab (UNKNOWN); |
5354 | tst_optab = init_optab (UNKNOWN); | |
c9034561 ZW |
5355 | |
5356 | eq_optab = init_optab (EQ); | |
5357 | ne_optab = init_optab (NE); | |
5358 | gt_optab = init_optab (GT); | |
5359 | ge_optab = init_optab (GE); | |
5360 | lt_optab = init_optab (LT); | |
5361 | le_optab = init_optab (LE); | |
5362 | unord_optab = init_optab (UNORDERED); | |
5363 | ||
77c9c6c2 | 5364 | neg_optab = init_optab (NEG); |
ef89d648 | 5365 | negv_optab = init_optabv (NEG); |
77c9c6c2 | 5366 | abs_optab = init_optab (ABS); |
ef89d648 | 5367 | absv_optab = init_optabv (ABS); |
068f5dea | 5368 | addcc_optab = init_optab (UNKNOWN); |
77c9c6c2 RK |
5369 | one_cmpl_optab = init_optab (NOT); |
5370 | ffs_optab = init_optab (FFS); | |
2928cd7a RH |
5371 | clz_optab = init_optab (CLZ); |
5372 | ctz_optab = init_optab (CTZ); | |
5373 | popcount_optab = init_optab (POPCOUNT); | |
5374 | parity_optab = init_optab (PARITY); | |
d45cf215 | 5375 | sqrt_optab = init_optab (SQRT); |
4977bab6 ZW |
5376 | floor_optab = init_optab (UNKNOWN); |
5377 | ceil_optab = init_optab (UNKNOWN); | |
5378 | round_optab = init_optab (UNKNOWN); | |
85363ca0 | 5379 | btrunc_optab = init_optab (UNKNOWN); |
4977bab6 | 5380 | nearbyint_optab = init_optab (UNKNOWN); |
6c7cf1f0 | 5381 | sincos_optab = init_optab (UNKNOWN); |
28cf078d JVA |
5382 | sin_optab = init_optab (UNKNOWN); |
5383 | cos_optab = init_optab (UNKNOWN); | |
e7b489c8 | 5384 | exp_optab = init_optab (UNKNOWN); |
a251102e UB |
5385 | exp10_optab = init_optab (UNKNOWN); |
5386 | exp2_optab = init_optab (UNKNOWN); | |
e7b489c8 | 5387 | log_optab = init_optab (UNKNOWN); |
3b8e0c91 UB |
5388 | log10_optab = init_optab (UNKNOWN); |
5389 | log2_optab = init_optab (UNKNOWN); | |
82d397c7 RS |
5390 | tan_optab = init_optab (UNKNOWN); |
5391 | atan_optab = init_optab (UNKNOWN); | |
19c3fc24 | 5392 | strlen_optab = init_optab (UNKNOWN); |
1c0290ea BS |
5393 | cbranch_optab = init_optab (UNKNOWN); |
5394 | cmov_optab = init_optab (UNKNOWN); | |
5395 | cstore_optab = init_optab (UNKNOWN); | |
371b8fc0 | 5396 | push_optab = init_optab (UNKNOWN); |
77c9c6c2 | 5397 | |
997404de JH |
5398 | vec_extract_optab = init_optab (UNKNOWN); |
5399 | vec_set_optab = init_optab (UNKNOWN); | |
5400 | vec_init_optab = init_optab (UNKNOWN); | |
85363ca0 ZW |
5401 | /* Conversions. */ |
5402 | sext_optab = init_convert_optab (SIGN_EXTEND); | |
5403 | zext_optab = init_convert_optab (ZERO_EXTEND); | |
5404 | trunc_optab = init_convert_optab (TRUNCATE); | |
5405 | sfix_optab = init_convert_optab (FIX); | |
5406 | ufix_optab = init_convert_optab (UNSIGNED_FIX); | |
5407 | sfixtrunc_optab = init_convert_optab (UNKNOWN); | |
5408 | ufixtrunc_optab = init_convert_optab (UNKNOWN); | |
5409 | sfloat_optab = init_convert_optab (FLOAT); | |
5410 | ufloat_optab = init_convert_optab (UNSIGNED_FLOAT); | |
5411 | ||
5d81dc5b RK |
5412 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
5413 | { | |
5414 | movstr_optab[i] = CODE_FOR_nothing; | |
45169d12 | 5415 | clrstr_optab[i] = CODE_FOR_nothing; |
118355a0 ZW |
5416 | cmpstr_optab[i] = CODE_FOR_nothing; |
5417 | cmpmem_optab[i] = CODE_FOR_nothing; | |
5d81dc5b RK |
5418 | |
5419 | #ifdef HAVE_SECONDARY_RELOADS | |
5420 | reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing; | |
77c9c6c2 | 5421 | #endif |
5d81dc5b RK |
5422 | } |
5423 | ||
5424 | /* Fill in the optabs with the insns we support. */ | |
5425 | init_all_optabs (); | |
5426 | ||
5d81dc5b | 5427 | /* Initialize the optabs with the names of the library functions. */ |
b092b471 JW |
5428 | init_integral_libfuncs (add_optab, "add", '3'); |
5429 | init_floating_libfuncs (add_optab, "add", '3'); | |
91ce572a CC |
5430 | init_integral_libfuncs (addv_optab, "addv", '3'); |
5431 | init_floating_libfuncs (addv_optab, "add", '3'); | |
b092b471 JW |
5432 | init_integral_libfuncs (sub_optab, "sub", '3'); |
5433 | init_floating_libfuncs (sub_optab, "sub", '3'); | |
91ce572a CC |
5434 | init_integral_libfuncs (subv_optab, "subv", '3'); |
5435 | init_floating_libfuncs (subv_optab, "sub", '3'); | |
b092b471 JW |
5436 | init_integral_libfuncs (smul_optab, "mul", '3'); |
5437 | init_floating_libfuncs (smul_optab, "mul", '3'); | |
91ce572a CC |
5438 | init_integral_libfuncs (smulv_optab, "mulv", '3'); |
5439 | init_floating_libfuncs (smulv_optab, "mul", '3'); | |
5d81dc5b | 5440 | init_integral_libfuncs (sdiv_optab, "div", '3'); |
ef89d648 | 5441 | init_floating_libfuncs (sdiv_optab, "div", '3'); |
91ce572a | 5442 | init_integral_libfuncs (sdivv_optab, "divv", '3'); |
5d81dc5b RK |
5443 | init_integral_libfuncs (udiv_optab, "udiv", '3'); |
5444 | init_integral_libfuncs (sdivmod_optab, "divmod", '4'); | |
5445 | init_integral_libfuncs (udivmod_optab, "udivmod", '4'); | |
5446 | init_integral_libfuncs (smod_optab, "mod", '3'); | |
5447 | init_integral_libfuncs (umod_optab, "umod", '3'); | |
5d81dc5b RK |
5448 | init_floating_libfuncs (ftrunc_optab, "ftrunc", '2'); |
5449 | init_integral_libfuncs (and_optab, "and", '3'); | |
5450 | init_integral_libfuncs (ior_optab, "ior", '3'); | |
5451 | init_integral_libfuncs (xor_optab, "xor", '3'); | |
5452 | init_integral_libfuncs (ashl_optab, "ashl", '3'); | |
5453 | init_integral_libfuncs (ashr_optab, "ashr", '3'); | |
5d81dc5b | 5454 | init_integral_libfuncs (lshr_optab, "lshr", '3'); |
5d81dc5b RK |
5455 | init_integral_libfuncs (smin_optab, "min", '3'); |
5456 | init_floating_libfuncs (smin_optab, "min", '3'); | |
5457 | init_integral_libfuncs (smax_optab, "max", '3'); | |
5458 | init_floating_libfuncs (smax_optab, "max", '3'); | |
5459 | init_integral_libfuncs (umin_optab, "umin", '3'); | |
5460 | init_integral_libfuncs (umax_optab, "umax", '3'); | |
5461 | init_integral_libfuncs (neg_optab, "neg", '2'); | |
5462 | init_floating_libfuncs (neg_optab, "neg", '2'); | |
91ce572a CC |
5463 | init_integral_libfuncs (negv_optab, "negv", '2'); |
5464 | init_floating_libfuncs (negv_optab, "neg", '2'); | |
5d81dc5b RK |
5465 | init_integral_libfuncs (one_cmpl_optab, "one_cmpl", '2'); |
5466 | init_integral_libfuncs (ffs_optab, "ffs", '2'); | |
2928cd7a RH |
5467 | init_integral_libfuncs (clz_optab, "clz", '2'); |
5468 | init_integral_libfuncs (ctz_optab, "ctz", '2'); | |
5469 | init_integral_libfuncs (popcount_optab, "popcount", '2'); | |
5470 | init_integral_libfuncs (parity_optab, "parity", '2'); | |
5d81dc5b RK |
5471 | |
5472 | /* Comparison libcalls for integers MUST come in pairs, signed/unsigned. */ | |
5473 | init_integral_libfuncs (cmp_optab, "cmp", '2'); | |
5474 | init_integral_libfuncs (ucmp_optab, "ucmp", '2'); | |
5475 | init_floating_libfuncs (cmp_optab, "cmp", '2'); | |
77c9c6c2 | 5476 | |
c9034561 ZW |
5477 | /* EQ etc are floating point only. */ |
5478 | init_floating_libfuncs (eq_optab, "eq", '2'); | |
5479 | init_floating_libfuncs (ne_optab, "ne", '2'); | |
5480 | init_floating_libfuncs (gt_optab, "gt", '2'); | |
5481 | init_floating_libfuncs (ge_optab, "ge", '2'); | |
5482 | init_floating_libfuncs (lt_optab, "lt", '2'); | |
5483 | init_floating_libfuncs (le_optab, "le", '2'); | |
5484 | init_floating_libfuncs (unord_optab, "unord", '2'); | |
5485 | ||
85363ca0 ZW |
5486 | /* Conversions. */ |
5487 | init_interclass_conv_libfuncs (sfloat_optab, "float", MODE_INT, MODE_FLOAT); | |
5488 | init_interclass_conv_libfuncs (sfix_optab, "fix", MODE_FLOAT, MODE_INT); | |
5489 | init_interclass_conv_libfuncs (ufix_optab, "fixuns", MODE_FLOAT, MODE_INT); | |
77c9c6c2 | 5490 | |
85363ca0 ZW |
5491 | /* sext_optab is also used for FLOAT_EXTEND. */ |
5492 | init_intraclass_conv_libfuncs (sext_optab, "extend", MODE_FLOAT, true); | |
5493 | init_intraclass_conv_libfuncs (trunc_optab, "trunc", MODE_FLOAT, false); | |
76095e2f | 5494 | |
85363ca0 ZW |
5495 | /* Use cabs for double complex abs, since systems generally have cabs. |
5496 | Don't define any libcall for float complex, so that cabs will be used. */ | |
5497 | if (complex_double_type_node) | |
5498 | abs_optab->handlers[TYPE_MODE (complex_double_type_node)].libfunc | |
5499 | = init_one_libfunc ("cabs"); | |
76095e2f | 5500 | |
d91edf86 | 5501 | /* The ffs function operates on `int'. */ |
85363ca0 ZW |
5502 | ffs_optab->handlers[(int) mode_for_size (INT_TYPE_SIZE, MODE_INT, 0)].libfunc |
5503 | = init_one_libfunc ("ffs"); | |
76095e2f | 5504 | |
9602f5a0 | 5505 | abort_libfunc = init_one_libfunc ("abort"); |
76095e2f | 5506 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
b215b52e | 5507 | memmove_libfunc = init_one_libfunc ("memmove"); |
76095e2f RH |
5508 | bcopy_libfunc = init_one_libfunc ("bcopy"); |
5509 | memcmp_libfunc = init_one_libfunc ("memcmp"); | |
5510 | bcmp_libfunc = init_one_libfunc ("__gcc_bcmp"); | |
5511 | memset_libfunc = init_one_libfunc ("memset"); | |
5512 | bzero_libfunc = init_one_libfunc ("bzero"); | |
68d28100 | 5513 | setbits_libfunc = init_one_libfunc ("__setbits"); |
76095e2f | 5514 | |
52a11cbf RH |
5515 | unwind_resume_libfunc = init_one_libfunc (USING_SJLJ_EXCEPTIONS |
5516 | ? "_Unwind_SjLj_Resume" | |
5517 | : "_Unwind_Resume"); | |
6e6a07d2 | 5518 | #ifndef DONT_USE_BUILTIN_SETJMP |
76095e2f RH |
5519 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
5520 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
27a36778 | 5521 | #else |
76095e2f RH |
5522 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
5523 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
27a36778 | 5524 | #endif |
52a11cbf RH |
5525 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
5526 | unwind_sjlj_unregister_libfunc | |
5527 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
6adb4e3a | 5528 | |
07417085 KR |
5529 | /* For function entry/exit instrumentation. */ |
5530 | profile_function_entry_libfunc | |
76095e2f | 5531 | = init_one_libfunc ("__cyg_profile_func_enter"); |
07417085 | 5532 | profile_function_exit_libfunc |
76095e2f | 5533 | = init_one_libfunc ("__cyg_profile_func_exit"); |
07417085 | 5534 | |
68d28100 RH |
5535 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
5536 | gcov_init_libfunc = init_one_libfunc ("__gcov_init"); | |
5537 | ||
842a431a DM |
5538 | if (HAVE_conditional_trap) |
5539 | trap_rtx = gen_rtx_fmt_ee (EQ, VOIDmode, NULL_RTX, NULL_RTX); | |
e0cd0770 | 5540 | |
159c2aed | 5541 | /* Allow the target to add more libcalls or rename some, etc. */ |
c15c90bb | 5542 | targetm.init_libfuncs (); |
77c9c6c2 | 5543 | } |
7e1966ca | 5544 | \f |
e0cd0770 JC |
5545 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
5546 | CODE. Return 0 on failure. */ | |
5547 | ||
5548 | rtx | |
0c20a65f AJ |
5549 | gen_cond_trap (enum rtx_code code ATTRIBUTE_UNUSED, rtx op1, |
5550 | rtx op2 ATTRIBUTE_UNUSED, rtx tcode ATTRIBUTE_UNUSED) | |
e0cd0770 JC |
5551 | { |
5552 | enum machine_mode mode = GET_MODE (op1); | |
842a431a DM |
5553 | enum insn_code icode; |
5554 | rtx insn; | |
5555 | ||
5556 | if (!HAVE_conditional_trap) | |
5557 | return 0; | |
e0cd0770 JC |
5558 | |
5559 | if (mode == VOIDmode) | |
5560 | return 0; | |
5561 | ||
842a431a DM |
5562 | icode = cmp_optab->handlers[(int) mode].insn_code; |
5563 | if (icode == CODE_FOR_nothing) | |
5564 | return 0; | |
5565 | ||
5566 | start_sequence (); | |
5567 | op1 = prepare_operand (icode, op1, 0, mode, mode, 0); | |
0310c414 | 5568 | op2 = prepare_operand (icode, op2, 1, mode, mode, 0); |
d893ccde RH |
5569 | if (!op1 || !op2) |
5570 | { | |
5571 | end_sequence (); | |
5572 | return 0; | |
5573 | } | |
842a431a DM |
5574 | emit_insn (GEN_FCN (icode) (op1, op2)); |
5575 | ||
5576 | PUT_CODE (trap_rtx, code); | |
5577 | insn = gen_conditional_trap (trap_rtx, tcode); | |
5578 | if (insn) | |
e0cd0770 | 5579 | { |
842a431a DM |
5580 | emit_insn (insn); |
5581 | insn = get_insns (); | |
e0cd0770 | 5582 | } |
842a431a | 5583 | end_sequence (); |
e0cd0770 | 5584 | |
842a431a | 5585 | return insn; |
e0cd0770 | 5586 | } |
e2500fed GK |
5587 | |
5588 | #include "gt-optabs.h" |