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77c9c6c2 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
9ee0a442 | 3 | 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
77c9c6c2 | 4 | |
1322177d | 5 | This file is part of GCC. |
77c9c6c2 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
77c9c6c2 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
77c9c6c2 RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
77c9c6c2 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
01198c2f | 27 | #include "toplev.h" |
dff01034 KG |
28 | |
29 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
dc297297 | 30 | is properly defined. */ |
dff01034 | 31 | #include "insn-config.h" |
77c9c6c2 RK |
32 | #include "rtl.h" |
33 | #include "tree.h" | |
6baf1cc8 | 34 | #include "tm_p.h" |
77c9c6c2 | 35 | #include "flags.h" |
49ad7cfa | 36 | #include "function.h" |
52a11cbf | 37 | #include "except.h" |
77c9c6c2 | 38 | #include "expr.h" |
e78d8e51 ZW |
39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
77c9c6c2 | 41 | #include "recog.h" |
2829c155 | 42 | #include "reload.h" |
87ff9c8e | 43 | #include "ggc.h" |
7bdb32b9 | 44 | #include "real.h" |
4a69cf79 | 45 | #include "basic-block.h" |
77c9c6c2 RK |
46 | |
47 | /* Each optab contains info on how this target machine | |
48 | can perform a particular operation | |
49 | for all sizes and kinds of operands. | |
50 | ||
51 | The operation to be performed is often specified | |
52 | by passing one of these optabs as an argument. | |
53 | ||
54 | See expr.h for documentation of these optabs. */ | |
55 | ||
34220a12 BS |
56 | optab optab_table[OTI_MAX]; |
57 | ||
58 | rtx libfunc_table[LTI_MAX]; | |
19c3fc24 | 59 | |
5d81dc5b RK |
60 | /* Tables of patterns for extending one integer mode to another. */ |
61 | enum insn_code extendtab[MAX_MACHINE_MODE][MAX_MACHINE_MODE][2]; | |
62 | ||
0f41302f | 63 | /* Tables of patterns for converting between fixed and floating point. */ |
5d81dc5b RK |
64 | enum insn_code fixtab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; |
65 | enum insn_code fixtrunctab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; | |
66 | enum insn_code floattab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2]; | |
67 | ||
377017c4 RK |
68 | /* Contains the optab used for each rtx code. */ |
69 | optab code_to_optab[NUM_RTX_CODE + 1]; | |
70 | ||
77c9c6c2 RK |
71 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) |
72 | gives the gen_function to make a branch to test that condition. */ | |
73 | ||
74 | rtxfun bcc_gen_fctn[NUM_RTX_CODE]; | |
75 | ||
76 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) | |
77 | gives the insn code to make a store-condition insn | |
78 | to test that condition. */ | |
79 | ||
80 | enum insn_code setcc_gen_code[NUM_RTX_CODE]; | |
81 | ||
49c4584c DE |
82 | #ifdef HAVE_conditional_move |
83 | /* Indexed by the machine mode, gives the insn code to make a conditional | |
84 | move insn. This is not indexed by the rtx-code like bcc_gen_fctn and | |
85 | setcc_gen_code to cut down on the number of named patterns. Consider a day | |
86 | when a lot more rtx codes are conditional (eg: for the ARM). */ | |
87 | ||
88 | enum insn_code movcc_gen_code[NUM_MACHINE_MODES]; | |
89 | #endif | |
90 | ||
842a431a DM |
91 | /* The insn generating function can not take an rtx_code argument. |
92 | TRAP_RTX is used as an rtx argument. Its code is replaced with | |
93 | the code to be used in the trap insn and all other fields are ignored. */ | |
94 | static GTY(()) rtx trap_rtx; | |
95 | ||
0c20a65f AJ |
96 | static int add_equal_note (rtx, rtx, enum rtx_code, rtx, rtx); |
97 | static rtx widen_operand (rtx, enum machine_mode, enum machine_mode, int, | |
98 | int); | |
99 | static int expand_cmplxdiv_straight (rtx, rtx, rtx, rtx, rtx, rtx, | |
100 | enum machine_mode, int, | |
101 | enum optab_methods, enum mode_class, | |
102 | optab); | |
103 | static int expand_cmplxdiv_wide (rtx, rtx, rtx, rtx, rtx, rtx, | |
104 | enum machine_mode, int, enum optab_methods, | |
105 | enum mode_class, optab); | |
106 | static void prepare_cmp_insn (rtx *, rtx *, enum rtx_code *, rtx, | |
107 | enum machine_mode *, int *, | |
108 | enum can_compare_purpose); | |
109 | static enum insn_code can_fix_p (enum machine_mode, enum machine_mode, int, | |
110 | int *); | |
111 | static enum insn_code can_float_p (enum machine_mode, enum machine_mode, int); | |
112 | static rtx ftruncify (rtx); | |
113 | static optab new_optab (void); | |
114 | static inline optab init_optab (enum rtx_code); | |
115 | static inline optab init_optabv (enum rtx_code); | |
116 | static void init_libfuncs (optab, int, int, const char *, int); | |
117 | static void init_integral_libfuncs (optab, const char *, int); | |
118 | static void init_floating_libfuncs (optab, const char *, int); | |
119 | static void emit_cmp_and_jump_insn_1 (rtx, rtx, enum machine_mode, | |
120 | enum rtx_code, int, rtx); | |
121 | static void prepare_float_lib_cmp (rtx *, rtx *, enum rtx_code *, | |
122 | enum machine_mode *, int *); | |
123 | static rtx expand_vector_binop (enum machine_mode, optab, rtx, rtx, rtx, int, | |
124 | enum optab_methods); | |
125 | static rtx expand_vector_unop (enum machine_mode, optab, rtx, rtx, int); | |
126 | static rtx widen_clz (enum machine_mode, rtx, rtx); | |
127 | static rtx expand_parity (enum machine_mode, rtx, rtx); | |
842a431a DM |
128 | |
129 | #ifndef HAVE_conditional_trap | |
130 | #define HAVE_conditional_trap 0 | |
131 | #define gen_conditional_trap(a,b) (abort (), NULL_RTX) | |
132 | #endif | |
77c9c6c2 | 133 | \f |
2f937369 | 134 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
77c9c6c2 RK |
135 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
136 | operation). | |
137 | ||
138 | If the last insn does not set TARGET, don't do anything, but return 1. | |
139 | ||
140 | If a previous insn sets TARGET and TARGET is one of OP0 or OP1, | |
141 | don't add the REG_EQUAL note but return 0. Our caller can then try | |
142 | again, ensuring that TARGET is not one of the operands. */ | |
143 | ||
144 | static int | |
0c20a65f | 145 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
77c9c6c2 | 146 | { |
2f937369 | 147 | rtx last_insn, insn, set; |
77c9c6c2 RK |
148 | rtx note; |
149 | ||
2f937369 DM |
150 | if (! insns |
151 | || ! INSN_P (insns) | |
152 | || NEXT_INSN (insns) == NULL_RTX) | |
153 | abort (); | |
154 | ||
155 | if (GET_RTX_CLASS (code) != '1' && GET_RTX_CLASS (code) != '2' | |
156 | && GET_RTX_CLASS (code) != 'c' && GET_RTX_CLASS (code) != '<') | |
157 | return 1; | |
158 | ||
159 | if (GET_CODE (target) == ZERO_EXTRACT) | |
160 | return 1; | |
161 | ||
162 | for (last_insn = insns; | |
163 | NEXT_INSN (last_insn) != NULL_RTX; | |
164 | last_insn = NEXT_INSN (last_insn)) | |
165 | ; | |
166 | ||
167 | set = single_set (last_insn); | |
168 | if (set == NULL_RTX) | |
169 | return 1; | |
170 | ||
171 | if (! rtx_equal_p (SET_DEST (set), target) | |
f9d36a92 | 172 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
2f937369 | 173 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
f9d36a92 | 174 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
77c9c6c2 RK |
175 | return 1; |
176 | ||
177 | /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET | |
178 | besides the last insn. */ | |
179 | if (reg_overlap_mentioned_p (target, op0) | |
180 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
2f937369 DM |
181 | { |
182 | insn = PREV_INSN (last_insn); | |
183 | while (insn != NULL_RTX) | |
184 | { | |
185 | if (reg_set_p (target, insn)) | |
186 | return 0; | |
187 | ||
188 | insn = PREV_INSN (insn); | |
189 | } | |
190 | } | |
77c9c6c2 RK |
191 | |
192 | if (GET_RTX_CLASS (code) == '1') | |
9e6a5703 | 193 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); |
77c9c6c2 | 194 | else |
9e6a5703 | 195 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
77c9c6c2 | 196 | |
2f937369 | 197 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
77c9c6c2 RK |
198 | |
199 | return 1; | |
200 | } | |
201 | \f | |
835532b8 RK |
202 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
203 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
0c20a65f | 204 | not actually do a sign-extend or zero-extend, but can leave the |
835532b8 RK |
205 | higher-order bits of the result rtx undefined, for example, in the case |
206 | of logical operations, but not right shifts. */ | |
207 | ||
208 | static rtx | |
0c20a65f AJ |
209 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
210 | int unsignedp, int no_extend) | |
835532b8 RK |
211 | { |
212 | rtx result; | |
213 | ||
8041889f RK |
214 | /* If we don't have to extend and this is a constant, return it. */ |
215 | if (no_extend && GET_MODE (op) == VOIDmode) | |
216 | return op; | |
217 | ||
218 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
219 | extend since it will be more efficient to do so unless the signedness of | |
220 | a promoted object differs from our extension. */ | |
835532b8 | 221 | if (! no_extend |
cb8f73be RK |
222 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
223 | && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp)) | |
0661a3de | 224 | return convert_modes (mode, oldmode, op, unsignedp); |
835532b8 RK |
225 | |
226 | /* If MODE is no wider than a single word, we return a paradoxical | |
227 | SUBREG. */ | |
228 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
9e6a5703 | 229 | return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0); |
835532b8 RK |
230 | |
231 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
232 | part to OP. */ | |
233 | ||
234 | result = gen_reg_rtx (mode); | |
9e6a5703 | 235 | emit_insn (gen_rtx_CLOBBER (VOIDmode, result)); |
835532b8 RK |
236 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
237 | return result; | |
238 | } | |
239 | \f | |
c64f913e CB |
240 | /* Generate code to perform a straightforward complex divide. */ |
241 | ||
242 | static int | |
0c20a65f AJ |
243 | expand_cmplxdiv_straight (rtx real0, rtx real1, rtx imag0, rtx imag1, |
244 | rtx realr, rtx imagr, enum machine_mode submode, | |
245 | int unsignedp, enum optab_methods methods, | |
246 | enum mode_class class, optab binoptab) | |
c64f913e CB |
247 | { |
248 | rtx divisor; | |
249 | rtx real_t, imag_t; | |
250 | rtx temp1, temp2; | |
251 | rtx res; | |
91ce572a CC |
252 | optab this_add_optab = add_optab; |
253 | optab this_sub_optab = sub_optab; | |
254 | optab this_neg_optab = neg_optab; | |
255 | optab this_mul_optab = smul_optab; | |
0c20a65f | 256 | |
91ce572a CC |
257 | if (binoptab == sdivv_optab) |
258 | { | |
259 | this_add_optab = addv_optab; | |
260 | this_sub_optab = subv_optab; | |
261 | this_neg_optab = negv_optab; | |
262 | this_mul_optab = smulv_optab; | |
263 | } | |
264 | ||
c64f913e CB |
265 | /* Don't fetch these from memory more than once. */ |
266 | real0 = force_reg (submode, real0); | |
267 | real1 = force_reg (submode, real1); | |
268 | ||
269 | if (imag0 != 0) | |
270 | imag0 = force_reg (submode, imag0); | |
271 | ||
272 | imag1 = force_reg (submode, imag1); | |
273 | ||
274 | /* Divisor: c*c + d*d. */ | |
91ce572a | 275 | temp1 = expand_binop (submode, this_mul_optab, real1, real1, |
c64f913e CB |
276 | NULL_RTX, unsignedp, methods); |
277 | ||
91ce572a | 278 | temp2 = expand_binop (submode, this_mul_optab, imag1, imag1, |
c64f913e CB |
279 | NULL_RTX, unsignedp, methods); |
280 | ||
281 | if (temp1 == 0 || temp2 == 0) | |
282 | return 0; | |
283 | ||
91ce572a | 284 | divisor = expand_binop (submode, this_add_optab, temp1, temp2, |
c64f913e CB |
285 | NULL_RTX, unsignedp, methods); |
286 | if (divisor == 0) | |
287 | return 0; | |
288 | ||
086bbd21 | 289 | if (imag0 == 0) |
c64f913e CB |
290 | { |
291 | /* Mathematically, ((a)(c-id))/divisor. */ | |
292 | /* Computationally, (a+i0) / (c+id) = (ac/(cc+dd)) + i(-ad/(cc+dd)). */ | |
293 | ||
294 | /* Calculate the dividend. */ | |
91ce572a | 295 | real_t = expand_binop (submode, this_mul_optab, real0, real1, |
c64f913e | 296 | NULL_RTX, unsignedp, methods); |
0c20a65f | 297 | |
91ce572a | 298 | imag_t = expand_binop (submode, this_mul_optab, real0, imag1, |
c64f913e CB |
299 | NULL_RTX, unsignedp, methods); |
300 | ||
301 | if (real_t == 0 || imag_t == 0) | |
302 | return 0; | |
303 | ||
91ce572a | 304 | imag_t = expand_unop (submode, this_neg_optab, imag_t, |
c64f913e CB |
305 | NULL_RTX, unsignedp); |
306 | } | |
307 | else | |
308 | { | |
309 | /* Mathematically, ((a+ib)(c-id))/divider. */ | |
310 | /* Calculate the dividend. */ | |
91ce572a | 311 | temp1 = expand_binop (submode, this_mul_optab, real0, real1, |
c64f913e CB |
312 | NULL_RTX, unsignedp, methods); |
313 | ||
91ce572a | 314 | temp2 = expand_binop (submode, this_mul_optab, imag0, imag1, |
c64f913e CB |
315 | NULL_RTX, unsignedp, methods); |
316 | ||
317 | if (temp1 == 0 || temp2 == 0) | |
318 | return 0; | |
319 | ||
91ce572a | 320 | real_t = expand_binop (submode, this_add_optab, temp1, temp2, |
c64f913e | 321 | NULL_RTX, unsignedp, methods); |
0c20a65f | 322 | |
91ce572a | 323 | temp1 = expand_binop (submode, this_mul_optab, imag0, real1, |
c64f913e CB |
324 | NULL_RTX, unsignedp, methods); |
325 | ||
91ce572a | 326 | temp2 = expand_binop (submode, this_mul_optab, real0, imag1, |
c64f913e CB |
327 | NULL_RTX, unsignedp, methods); |
328 | ||
329 | if (temp1 == 0 || temp2 == 0) | |
330 | return 0; | |
331 | ||
91ce572a | 332 | imag_t = expand_binop (submode, this_sub_optab, temp1, temp2, |
c64f913e CB |
333 | NULL_RTX, unsignedp, methods); |
334 | ||
335 | if (real_t == 0 || imag_t == 0) | |
336 | return 0; | |
337 | } | |
338 | ||
339 | if (class == MODE_COMPLEX_FLOAT) | |
340 | res = expand_binop (submode, binoptab, real_t, divisor, | |
341 | realr, unsignedp, methods); | |
342 | else | |
343 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
344 | real_t, divisor, realr, unsignedp); | |
345 | ||
346 | if (res == 0) | |
347 | return 0; | |
348 | ||
349 | if (res != realr) | |
350 | emit_move_insn (realr, res); | |
351 | ||
352 | if (class == MODE_COMPLEX_FLOAT) | |
353 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
354 | imagr, unsignedp, methods); | |
355 | else | |
356 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
357 | imag_t, divisor, imagr, unsignedp); | |
358 | ||
359 | if (res == 0) | |
360 | return 0; | |
361 | ||
362 | if (res != imagr) | |
363 | emit_move_insn (imagr, res); | |
364 | ||
365 | return 1; | |
366 | } | |
367 | \f | |
368 | /* Generate code to perform a wide-input-range-acceptable complex divide. */ | |
369 | ||
370 | static int | |
0c20a65f AJ |
371 | expand_cmplxdiv_wide (rtx real0, rtx real1, rtx imag0, rtx imag1, rtx realr, |
372 | rtx imagr, enum machine_mode submode, int unsignedp, | |
373 | enum optab_methods methods, enum mode_class class, | |
374 | optab binoptab) | |
c64f913e CB |
375 | { |
376 | rtx ratio, divisor; | |
377 | rtx real_t, imag_t; | |
378 | rtx temp1, temp2, lab1, lab2; | |
379 | enum machine_mode mode; | |
c64f913e | 380 | rtx res; |
91ce572a CC |
381 | optab this_add_optab = add_optab; |
382 | optab this_sub_optab = sub_optab; | |
383 | optab this_neg_optab = neg_optab; | |
384 | optab this_mul_optab = smul_optab; | |
385 | ||
386 | if (binoptab == sdivv_optab) | |
387 | { | |
388 | this_add_optab = addv_optab; | |
389 | this_sub_optab = subv_optab; | |
390 | this_neg_optab = negv_optab; | |
391 | this_mul_optab = smulv_optab; | |
392 | } | |
0c20a65f | 393 | |
c64f913e CB |
394 | /* Don't fetch these from memory more than once. */ |
395 | real0 = force_reg (submode, real0); | |
396 | real1 = force_reg (submode, real1); | |
397 | ||
398 | if (imag0 != 0) | |
399 | imag0 = force_reg (submode, imag0); | |
400 | ||
401 | imag1 = force_reg (submode, imag1); | |
402 | ||
a59a536c RE |
403 | /* XXX What's an "unsigned" complex number? */ |
404 | if (unsignedp) | |
405 | { | |
406 | temp1 = real1; | |
407 | temp2 = imag1; | |
408 | } | |
409 | else | |
410 | { | |
91ce572a CC |
411 | temp1 = expand_abs (submode, real1, NULL_RTX, unsignedp, 1); |
412 | temp2 = expand_abs (submode, imag1, NULL_RTX, unsignedp, 1); | |
a59a536c | 413 | } |
c64f913e CB |
414 | |
415 | if (temp1 == 0 || temp2 == 0) | |
416 | return 0; | |
417 | ||
418 | mode = GET_MODE (temp1); | |
c64f913e CB |
419 | lab1 = gen_label_rtx (); |
420 | emit_cmp_and_jump_insns (temp1, temp2, LT, NULL_RTX, | |
a06ef755 | 421 | mode, unsignedp, lab1); |
c64f913e CB |
422 | |
423 | /* |c| >= |d|; use ratio d/c to scale dividend and divisor. */ | |
424 | ||
425 | if (class == MODE_COMPLEX_FLOAT) | |
426 | ratio = expand_binop (submode, binoptab, imag1, real1, | |
427 | NULL_RTX, unsignedp, methods); | |
428 | else | |
429 | ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
430 | imag1, real1, NULL_RTX, unsignedp); | |
431 | ||
432 | if (ratio == 0) | |
433 | return 0; | |
434 | ||
435 | /* Calculate divisor. */ | |
436 | ||
91ce572a | 437 | temp1 = expand_binop (submode, this_mul_optab, imag1, ratio, |
c64f913e CB |
438 | NULL_RTX, unsignedp, methods); |
439 | ||
440 | if (temp1 == 0) | |
441 | return 0; | |
442 | ||
91ce572a | 443 | divisor = expand_binop (submode, this_add_optab, temp1, real1, |
c64f913e CB |
444 | NULL_RTX, unsignedp, methods); |
445 | ||
446 | if (divisor == 0) | |
447 | return 0; | |
448 | ||
449 | /* Calculate dividend. */ | |
450 | ||
086bbd21 | 451 | if (imag0 == 0) |
c64f913e CB |
452 | { |
453 | real_t = real0; | |
454 | ||
455 | /* Compute a / (c+id) as a / (c+d(d/c)) + i (-a(d/c)) / (c+d(d/c)). */ | |
456 | ||
91ce572a | 457 | imag_t = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
458 | NULL_RTX, unsignedp, methods); |
459 | ||
460 | if (imag_t == 0) | |
461 | return 0; | |
462 | ||
91ce572a | 463 | imag_t = expand_unop (submode, this_neg_optab, imag_t, |
c64f913e CB |
464 | NULL_RTX, unsignedp); |
465 | ||
466 | if (real_t == 0 || imag_t == 0) | |
467 | return 0; | |
468 | } | |
469 | else | |
470 | { | |
471 | /* Compute (a+ib)/(c+id) as | |
472 | (a+b(d/c))/(c+d(d/c) + i(b-a(d/c))/(c+d(d/c)). */ | |
473 | ||
91ce572a | 474 | temp1 = expand_binop (submode, this_mul_optab, imag0, ratio, |
c64f913e CB |
475 | NULL_RTX, unsignedp, methods); |
476 | ||
477 | if (temp1 == 0) | |
478 | return 0; | |
479 | ||
91ce572a | 480 | real_t = expand_binop (submode, this_add_optab, temp1, real0, |
c64f913e CB |
481 | NULL_RTX, unsignedp, methods); |
482 | ||
91ce572a | 483 | temp1 = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
484 | NULL_RTX, unsignedp, methods); |
485 | ||
486 | if (temp1 == 0) | |
487 | return 0; | |
488 | ||
91ce572a | 489 | imag_t = expand_binop (submode, this_sub_optab, imag0, temp1, |
c64f913e CB |
490 | NULL_RTX, unsignedp, methods); |
491 | ||
492 | if (real_t == 0 || imag_t == 0) | |
493 | return 0; | |
494 | } | |
495 | ||
496 | if (class == MODE_COMPLEX_FLOAT) | |
497 | res = expand_binop (submode, binoptab, real_t, divisor, | |
498 | realr, unsignedp, methods); | |
499 | else | |
500 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
501 | real_t, divisor, realr, unsignedp); | |
502 | ||
503 | if (res == 0) | |
504 | return 0; | |
505 | ||
506 | if (res != realr) | |
507 | emit_move_insn (realr, res); | |
508 | ||
509 | if (class == MODE_COMPLEX_FLOAT) | |
510 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
511 | imagr, unsignedp, methods); | |
512 | else | |
513 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
514 | imag_t, divisor, imagr, unsignedp); | |
515 | ||
516 | if (res == 0) | |
517 | return 0; | |
518 | ||
519 | if (res != imagr) | |
520 | emit_move_insn (imagr, res); | |
521 | ||
522 | lab2 = gen_label_rtx (); | |
523 | emit_jump_insn (gen_jump (lab2)); | |
524 | emit_barrier (); | |
525 | ||
526 | emit_label (lab1); | |
527 | ||
528 | /* |d| > |c|; use ratio c/d to scale dividend and divisor. */ | |
529 | ||
530 | if (class == MODE_COMPLEX_FLOAT) | |
531 | ratio = expand_binop (submode, binoptab, real1, imag1, | |
532 | NULL_RTX, unsignedp, methods); | |
533 | else | |
534 | ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
535 | real1, imag1, NULL_RTX, unsignedp); | |
536 | ||
537 | if (ratio == 0) | |
538 | return 0; | |
539 | ||
540 | /* Calculate divisor. */ | |
541 | ||
91ce572a | 542 | temp1 = expand_binop (submode, this_mul_optab, real1, ratio, |
c64f913e CB |
543 | NULL_RTX, unsignedp, methods); |
544 | ||
545 | if (temp1 == 0) | |
546 | return 0; | |
547 | ||
91ce572a | 548 | divisor = expand_binop (submode, this_add_optab, temp1, imag1, |
c64f913e CB |
549 | NULL_RTX, unsignedp, methods); |
550 | ||
551 | if (divisor == 0) | |
552 | return 0; | |
553 | ||
554 | /* Calculate dividend. */ | |
555 | ||
086bbd21 | 556 | if (imag0 == 0) |
c64f913e CB |
557 | { |
558 | /* Compute a / (c+id) as a(c/d) / (c(c/d)+d) + i (-a) / (c(c/d)+d). */ | |
559 | ||
91ce572a | 560 | real_t = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
561 | NULL_RTX, unsignedp, methods); |
562 | ||
91ce572a | 563 | imag_t = expand_unop (submode, this_neg_optab, real0, |
c64f913e CB |
564 | NULL_RTX, unsignedp); |
565 | ||
566 | if (real_t == 0 || imag_t == 0) | |
567 | return 0; | |
568 | } | |
569 | else | |
570 | { | |
571 | /* Compute (a+ib)/(c+id) as | |
572 | (a(c/d)+b)/(c(c/d)+d) + i (b(c/d)-a)/(c(c/d)+d). */ | |
573 | ||
91ce572a | 574 | temp1 = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
575 | NULL_RTX, unsignedp, methods); |
576 | ||
577 | if (temp1 == 0) | |
578 | return 0; | |
579 | ||
91ce572a | 580 | real_t = expand_binop (submode, this_add_optab, temp1, imag0, |
c64f913e CB |
581 | NULL_RTX, unsignedp, methods); |
582 | ||
91ce572a | 583 | temp1 = expand_binop (submode, this_mul_optab, imag0, ratio, |
c64f913e CB |
584 | NULL_RTX, unsignedp, methods); |
585 | ||
586 | if (temp1 == 0) | |
587 | return 0; | |
588 | ||
91ce572a | 589 | imag_t = expand_binop (submode, this_sub_optab, temp1, real0, |
c64f913e CB |
590 | NULL_RTX, unsignedp, methods); |
591 | ||
592 | if (real_t == 0 || imag_t == 0) | |
593 | return 0; | |
594 | } | |
595 | ||
596 | if (class == MODE_COMPLEX_FLOAT) | |
597 | res = expand_binop (submode, binoptab, real_t, divisor, | |
598 | realr, unsignedp, methods); | |
599 | else | |
600 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
601 | real_t, divisor, realr, unsignedp); | |
602 | ||
603 | if (res == 0) | |
604 | return 0; | |
605 | ||
606 | if (res != realr) | |
607 | emit_move_insn (realr, res); | |
608 | ||
609 | if (class == MODE_COMPLEX_FLOAT) | |
610 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
611 | imagr, unsignedp, methods); | |
612 | else | |
613 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
614 | imag_t, divisor, imagr, unsignedp); | |
615 | ||
616 | if (res == 0) | |
617 | return 0; | |
618 | ||
619 | if (res != imagr) | |
620 | emit_move_insn (imagr, res); | |
621 | ||
622 | emit_label (lab2); | |
623 | ||
624 | return 1; | |
625 | } | |
626 | \f | |
ef89d648 ZW |
627 | /* Wrapper around expand_binop which takes an rtx code to specify |
628 | the operation to perform, not an optab pointer. All other | |
629 | arguments are the same. */ | |
630 | rtx | |
0c20a65f AJ |
631 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
632 | rtx op1, rtx target, int unsignedp, | |
633 | enum optab_methods methods) | |
ef89d648 | 634 | { |
7e1a450d | 635 | optab binop = code_to_optab[(int) code]; |
ef89d648 ZW |
636 | if (binop == 0) |
637 | abort (); | |
638 | ||
639 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
640 | } | |
641 | ||
77c9c6c2 RK |
642 | /* Generate code to perform an operation specified by BINOPTAB |
643 | on operands OP0 and OP1, with result having machine-mode MODE. | |
644 | ||
645 | UNSIGNEDP is for the case where we have to widen the operands | |
646 | to perform the operation. It says to use zero-extension. | |
647 | ||
648 | If TARGET is nonzero, the value | |
649 | is generated there, if it is convenient to do so. | |
650 | In all cases an rtx is returned for the locus of the value; | |
651 | this may or may not be TARGET. */ | |
652 | ||
653 | rtx | |
0c20a65f AJ |
654 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
655 | rtx target, int unsignedp, enum optab_methods methods) | |
77c9c6c2 | 656 | { |
70864443 RK |
657 | enum optab_methods next_methods |
658 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
659 | ? OPTAB_WIDEN : methods); | |
77c9c6c2 RK |
660 | enum mode_class class; |
661 | enum machine_mode wider_mode; | |
b3694847 | 662 | rtx temp; |
77c9c6c2 | 663 | int commutative_op = 0; |
7e1a450d | 664 | int shift_op = (binoptab->code == ASHIFT |
77c9c6c2 | 665 | || binoptab->code == ASHIFTRT |
77c9c6c2 RK |
666 | || binoptab->code == LSHIFTRT |
667 | || binoptab->code == ROTATE | |
668 | || binoptab->code == ROTATERT); | |
abd418d3 | 669 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
670 | rtx last; |
671 | ||
672 | class = GET_MODE_CLASS (mode); | |
673 | ||
674 | op0 = protect_from_queue (op0, 0); | |
675 | op1 = protect_from_queue (op1, 0); | |
676 | if (target) | |
677 | target = protect_from_queue (target, 1); | |
678 | ||
679 | if (flag_force_mem) | |
680 | { | |
894207cf RS |
681 | /* Load duplicate non-volatile operands once. */ |
682 | if (rtx_equal_p (op0, op1) && ! volatile_refs_p (op0)) | |
683 | { | |
684 | op0 = force_not_mem (op0); | |
685 | op1 = op0; | |
686 | } | |
687 | else | |
688 | { | |
689 | op0 = force_not_mem (op0); | |
690 | op1 = force_not_mem (op1); | |
691 | } | |
77c9c6c2 RK |
692 | } |
693 | ||
8aecce0a RK |
694 | /* If subtracting an integer constant, convert this into an addition of |
695 | the negated constant. */ | |
696 | ||
697 | if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT) | |
698 | { | |
699 | op1 = negate_rtx (mode, op1); | |
700 | binoptab = add_optab; | |
701 | } | |
702 | ||
77c9c6c2 RK |
703 | /* If we are inside an appropriately-short loop and one operand is an |
704 | expensive constant, force it into a register. */ | |
aeedc93f | 705 | if (CONSTANT_P (op0) && preserve_subexpressions_p () |
b437f1a7 | 706 | && rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
707 | op0 = force_reg (mode, op0); |
708 | ||
aeedc93f | 709 | if (CONSTANT_P (op1) && preserve_subexpressions_p () |
b437f1a7 | 710 | && ! shift_op && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1)) |
4074220e | 711 | op1 = force_reg (mode, op1); |
77c9c6c2 | 712 | |
77c9c6c2 RK |
713 | /* Record where to delete back to if we backtrack. */ |
714 | last = get_last_insn (); | |
715 | ||
716 | /* If operation is commutative, | |
717 | try to make the first operand a register. | |
718 | Even better, try to make it the same as the target. | |
719 | Also try to make the last operand a constant. */ | |
720 | if (GET_RTX_CLASS (binoptab->code) == 'c' | |
721 | || binoptab == smul_widen_optab | |
5035bbfe TG |
722 | || binoptab == umul_widen_optab |
723 | || binoptab == smul_highpart_optab | |
724 | || binoptab == umul_highpart_optab) | |
77c9c6c2 RK |
725 | { |
726 | commutative_op = 1; | |
727 | ||
728 | if (((target == 0 || GET_CODE (target) == REG) | |
729 | ? ((GET_CODE (op1) == REG | |
730 | && GET_CODE (op0) != REG) | |
731 | || target == op1) | |
732 | : rtx_equal_p (op1, target)) | |
733 | || GET_CODE (op0) == CONST_INT) | |
734 | { | |
735 | temp = op1; | |
736 | op1 = op0; | |
737 | op0 = temp; | |
738 | } | |
739 | } | |
740 | ||
741 | /* If we can do it with a three-operand insn, do so. */ | |
742 | ||
743 | if (methods != OPTAB_MUST_WIDEN | |
744 | && binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
745 | { | |
746 | int icode = (int) binoptab->handlers[(int) mode].insn_code; | |
a995e389 RH |
747 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
748 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
749 | rtx pat; |
750 | rtx xop0 = op0, xop1 = op1; | |
751 | ||
752 | if (target) | |
753 | temp = target; | |
754 | else | |
755 | temp = gen_reg_rtx (mode); | |
756 | ||
757 | /* If it is a commutative operator and the modes would match | |
0f41302f | 758 | if we would swap the operands, we can save the conversions. */ |
77c9c6c2 RK |
759 | if (commutative_op) |
760 | { | |
761 | if (GET_MODE (op0) != mode0 && GET_MODE (op1) != mode1 | |
762 | && GET_MODE (op0) == mode1 && GET_MODE (op1) == mode0) | |
763 | { | |
b3694847 | 764 | rtx tmp; |
77c9c6c2 RK |
765 | |
766 | tmp = op0; op0 = op1; op1 = tmp; | |
767 | tmp = xop0; xop0 = xop1; xop1 = tmp; | |
768 | } | |
769 | } | |
770 | ||
771 | /* In case the insn wants input operands in modes different from | |
29984e05 EB |
772 | those of the actual operands, convert the operands. It would |
773 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
774 | that they're properly zero-extended, sign-extended or truncated |
775 | for their mode. */ | |
77c9c6c2 | 776 | |
874f6a6d | 777 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
69107307 AO |
778 | xop0 = convert_modes (mode0, |
779 | GET_MODE (op0) != VOIDmode | |
780 | ? GET_MODE (op0) | |
29984e05 | 781 | : mode, |
69107307 | 782 | xop0, unsignedp); |
77c9c6c2 | 783 | |
874f6a6d | 784 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) |
69107307 AO |
785 | xop1 = convert_modes (mode1, |
786 | GET_MODE (op1) != VOIDmode | |
787 | ? GET_MODE (op1) | |
35f1c975 | 788 | : mode, |
69107307 | 789 | xop1, unsignedp); |
77c9c6c2 RK |
790 | |
791 | /* Now, if insn's predicates don't allow our operands, put them into | |
792 | pseudo regs. */ | |
793 | ||
a995e389 | 794 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0) |
4074220e | 795 | && mode0 != VOIDmode) |
77c9c6c2 RK |
796 | xop0 = copy_to_mode_reg (mode0, xop0); |
797 | ||
a995e389 | 798 | if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1) |
4074220e | 799 | && mode1 != VOIDmode) |
77c9c6c2 RK |
800 | xop1 = copy_to_mode_reg (mode1, xop1); |
801 | ||
a995e389 | 802 | if (! (*insn_data[icode].operand[0].predicate) (temp, mode)) |
77c9c6c2 RK |
803 | temp = gen_reg_rtx (mode); |
804 | ||
805 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
806 | if (pat) | |
807 | { | |
2f937369 | 808 | /* If PAT is composed of more than one insn, try to add an appropriate |
77c9c6c2 RK |
809 | REG_EQUAL note to it. If we can't because TEMP conflicts with an |
810 | operand, call ourselves again, this time without a target. */ | |
2f937369 | 811 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
77c9c6c2 RK |
812 | && ! add_equal_note (pat, temp, binoptab->code, xop0, xop1)) |
813 | { | |
814 | delete_insns_since (last); | |
b1ec3c92 CH |
815 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, |
816 | unsignedp, methods); | |
77c9c6c2 RK |
817 | } |
818 | ||
819 | emit_insn (pat); | |
820 | return temp; | |
821 | } | |
822 | else | |
823 | delete_insns_since (last); | |
824 | } | |
825 | ||
5a5064dc RK |
826 | /* If this is a multiply, see if we can do a widening operation that |
827 | takes operands of this mode and makes a wider mode. */ | |
828 | ||
829 | if (binoptab == smul_optab && GET_MODE_WIDER_MODE (mode) != VOIDmode | |
830 | && (((unsignedp ? umul_widen_optab : smul_widen_optab) | |
831 | ->handlers[(int) GET_MODE_WIDER_MODE (mode)].insn_code) | |
832 | != CODE_FOR_nothing)) | |
833 | { | |
834 | temp = expand_binop (GET_MODE_WIDER_MODE (mode), | |
835 | unsignedp ? umul_widen_optab : smul_widen_optab, | |
73d9a835 | 836 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
5a5064dc | 837 | |
70864443 RK |
838 | if (temp != 0) |
839 | { | |
840 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
841 | return gen_lowpart (mode, temp); | |
842 | else | |
843 | return convert_to_mode (mode, temp, unsignedp); | |
844 | } | |
5a5064dc RK |
845 | } |
846 | ||
9a856ec7 | 847 | /* Look for a wider mode of the same class for which we think we |
5a5064dc RK |
848 | can open-code the operation. Check for a widening multiply at the |
849 | wider mode as well. */ | |
9a856ec7 RK |
850 | |
851 | if ((class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
6f43c157 | 852 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
9a856ec7 RK |
853 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
854 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
855 | { | |
5a5064dc RK |
856 | if (binoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing |
857 | || (binoptab == smul_optab | |
858 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
859 | && (((unsignedp ? umul_widen_optab : smul_widen_optab) | |
860 | ->handlers[(int) GET_MODE_WIDER_MODE (wider_mode)].insn_code) | |
861 | != CODE_FOR_nothing))) | |
9a856ec7 RK |
862 | { |
863 | rtx xop0 = op0, xop1 = op1; | |
864 | int no_extend = 0; | |
865 | ||
866 | /* For certain integer operations, we need not actually extend | |
867 | the narrow operands, as long as we will truncate | |
6d2f8887 | 868 | the results to the same narrowness. */ |
9a856ec7 RK |
869 | |
870 | if ((binoptab == ior_optab || binoptab == and_optab | |
871 | || binoptab == xor_optab | |
872 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 873 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 874 | && class == MODE_INT) |
9a856ec7 RK |
875 | no_extend = 1; |
876 | ||
0661a3de | 877 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
943cc242 RK |
878 | |
879 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 880 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 881 | no_extend && binoptab != ashl_optab); |
943cc242 | 882 | |
b1ec3c92 | 883 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
9a856ec7 RK |
884 | unsignedp, OPTAB_DIRECT); |
885 | if (temp) | |
886 | { | |
887 | if (class != MODE_INT) | |
888 | { | |
889 | if (target == 0) | |
890 | target = gen_reg_rtx (mode); | |
891 | convert_move (target, temp, 0); | |
892 | return target; | |
893 | } | |
894 | else | |
895 | return gen_lowpart (mode, temp); | |
896 | } | |
897 | else | |
898 | delete_insns_since (last); | |
899 | } | |
900 | } | |
901 | ||
77c9c6c2 RK |
902 | /* These can be done a word at a time. */ |
903 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
904 | && class == MODE_INT | |
905 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
34e56753 | 906 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 907 | { |
bb93b973 | 908 | int i; |
77c9c6c2 RK |
909 | rtx insns; |
910 | rtx equiv_value; | |
911 | ||
912 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
913 | won't be accurate, so use a new target. */ | |
914 | if (target == 0 || target == op0 || target == op1) | |
915 | target = gen_reg_rtx (mode); | |
916 | ||
917 | start_sequence (); | |
918 | ||
919 | /* Do the actual arithmetic. */ | |
920 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
921 | { | |
922 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 923 | rtx x = expand_binop (word_mode, binoptab, |
77c9c6c2 RK |
924 | operand_subword_force (op0, i, mode), |
925 | operand_subword_force (op1, i, mode), | |
70864443 RK |
926 | target_piece, unsignedp, next_methods); |
927 | ||
928 | if (x == 0) | |
929 | break; | |
930 | ||
77c9c6c2 RK |
931 | if (target_piece != x) |
932 | emit_move_insn (target_piece, x); | |
933 | } | |
934 | ||
935 | insns = get_insns (); | |
936 | end_sequence (); | |
937 | ||
70864443 RK |
938 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
939 | { | |
940 | if (binoptab->code != UNKNOWN) | |
941 | equiv_value | |
9e6a5703 JC |
942 | = gen_rtx_fmt_ee (binoptab->code, mode, |
943 | copy_rtx (op0), copy_rtx (op1)); | |
70864443 RK |
944 | else |
945 | equiv_value = 0; | |
77c9c6c2 | 946 | |
70864443 RK |
947 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); |
948 | return target; | |
949 | } | |
77c9c6c2 RK |
950 | } |
951 | ||
8c597270 | 952 | /* Synthesize double word shifts from single word shifts. */ |
e5df894b RK |
953 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
954 | || binoptab == ashr_optab) | |
8c597270 JW |
955 | && class == MODE_INT |
956 | && GET_CODE (op1) == CONST_INT | |
957 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
958 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
959 | && ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
960 | && lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) | |
961 | { | |
70864443 | 962 | rtx insns, inter, equiv_value; |
8c597270 JW |
963 | rtx into_target, outof_target; |
964 | rtx into_input, outof_input; | |
965 | int shift_count, left_shift, outof_word; | |
966 | ||
967 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
968 | won't be accurate, so use a new target. */ | |
969 | if (target == 0 || target == op0 || target == op1) | |
970 | target = gen_reg_rtx (mode); | |
971 | ||
972 | start_sequence (); | |
973 | ||
974 | shift_count = INTVAL (op1); | |
975 | ||
976 | /* OUTOF_* is the word we are shifting bits away from, and | |
977 | INTO_* is the word that we are shifting bits towards, thus | |
978 | they differ depending on the direction of the shift and | |
979 | WORDS_BIG_ENDIAN. */ | |
980 | ||
e5df894b | 981 | left_shift = binoptab == ashl_optab; |
8c597270 JW |
982 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; |
983 | ||
984 | outof_target = operand_subword (target, outof_word, 1, mode); | |
985 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
986 | ||
987 | outof_input = operand_subword_force (op0, outof_word, mode); | |
988 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
989 | ||
990 | if (shift_count >= BITS_PER_WORD) | |
991 | { | |
70864443 RK |
992 | inter = expand_binop (word_mode, binoptab, |
993 | outof_input, | |
994 | GEN_INT (shift_count - BITS_PER_WORD), | |
995 | into_target, unsignedp, next_methods); | |
996 | ||
cb5b00cf | 997 | if (inter != 0 && inter != into_target) |
70864443 | 998 | emit_move_insn (into_target, inter); |
8c597270 JW |
999 | |
1000 | /* For a signed right shift, we must fill the word we are shifting | |
1001 | out of with copies of the sign bit. Otherwise it is zeroed. */ | |
cb5b00cf RK |
1002 | if (inter != 0 && binoptab != ashr_optab) |
1003 | inter = CONST0_RTX (word_mode); | |
70864443 RK |
1004 | else if (inter != 0) |
1005 | inter = expand_binop (word_mode, binoptab, | |
1006 | outof_input, | |
1007 | GEN_INT (BITS_PER_WORD - 1), | |
1008 | outof_target, unsignedp, next_methods); | |
1009 | ||
cb5b00cf | 1010 | if (inter != 0 && inter != outof_target) |
70864443 | 1011 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1012 | } |
1013 | else | |
1014 | { | |
70864443 | 1015 | rtx carries; |
8c597270 JW |
1016 | optab reverse_unsigned_shift, unsigned_shift; |
1017 | ||
1018 | /* For a shift of less then BITS_PER_WORD, to compute the carry, | |
1019 | we must do a logical shift in the opposite direction of the | |
1020 | desired shift. */ | |
1021 | ||
8c597270 JW |
1022 | reverse_unsigned_shift = (left_shift ? lshr_optab : ashl_optab); |
1023 | ||
1024 | /* For a shift of less than BITS_PER_WORD, to compute the word | |
1025 | shifted towards, we need to unsigned shift the orig value of | |
1026 | that word. */ | |
1027 | ||
1028 | unsigned_shift = (left_shift ? ashl_optab : lshr_optab); | |
1029 | ||
1030 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
1031 | outof_input, | |
1032 | GEN_INT (BITS_PER_WORD - shift_count), | |
70864443 RK |
1033 | 0, unsignedp, next_methods); |
1034 | ||
1035 | if (carries == 0) | |
1036 | inter = 0; | |
1037 | else | |
70864443 RK |
1038 | inter = expand_binop (word_mode, unsigned_shift, into_input, |
1039 | op1, 0, unsignedp, next_methods); | |
1040 | ||
1041 | if (inter != 0) | |
1042 | inter = expand_binop (word_mode, ior_optab, carries, inter, | |
1043 | into_target, unsignedp, next_methods); | |
1044 | ||
cb5b00cf | 1045 | if (inter != 0 && inter != into_target) |
70864443 | 1046 | emit_move_insn (into_target, inter); |
cf2f7113 RE |
1047 | |
1048 | if (inter != 0) | |
1049 | inter = expand_binop (word_mode, binoptab, outof_input, | |
1050 | op1, outof_target, unsignedp, next_methods); | |
0c20a65f | 1051 | |
cf2f7113 RE |
1052 | if (inter != 0 && inter != outof_target) |
1053 | emit_move_insn (outof_target, inter); | |
8c597270 JW |
1054 | } |
1055 | ||
1056 | insns = get_insns (); | |
1057 | end_sequence (); | |
1058 | ||
70864443 RK |
1059 | if (inter != 0) |
1060 | { | |
1061 | if (binoptab->code != UNKNOWN) | |
9e6a5703 | 1062 | equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1); |
70864443 RK |
1063 | else |
1064 | equiv_value = 0; | |
8c597270 | 1065 | |
70864443 RK |
1066 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); |
1067 | return target; | |
1068 | } | |
8c597270 JW |
1069 | } |
1070 | ||
1071 | /* Synthesize double word rotates from single word shifts. */ | |
1072 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
1073 | && class == MODE_INT | |
1074 | && GET_CODE (op1) == CONST_INT | |
1075 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1076 | && ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
1077 | && lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) | |
1078 | { | |
1079 | rtx insns, equiv_value; | |
1080 | rtx into_target, outof_target; | |
1081 | rtx into_input, outof_input; | |
70864443 | 1082 | rtx inter; |
8c597270 JW |
1083 | int shift_count, left_shift, outof_word; |
1084 | ||
1085 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
1086 | won't be accurate, so use a new target. */ | |
1087 | if (target == 0 || target == op0 || target == op1) | |
1088 | target = gen_reg_rtx (mode); | |
1089 | ||
1090 | start_sequence (); | |
1091 | ||
1092 | shift_count = INTVAL (op1); | |
1093 | ||
1094 | /* OUTOF_* is the word we are shifting bits away from, and | |
1095 | INTO_* is the word that we are shifting bits towards, thus | |
1096 | they differ depending on the direction of the shift and | |
1097 | WORDS_BIG_ENDIAN. */ | |
1098 | ||
1099 | left_shift = (binoptab == rotl_optab); | |
1100 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1101 | ||
1102 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1103 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1104 | ||
1105 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1106 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1107 | ||
1108 | if (shift_count == BITS_PER_WORD) | |
1109 | { | |
1110 | /* This is just a word swap. */ | |
1111 | emit_move_insn (outof_target, into_input); | |
1112 | emit_move_insn (into_target, outof_input); | |
70864443 | 1113 | inter = const0_rtx; |
8c597270 JW |
1114 | } |
1115 | else | |
1116 | { | |
1117 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1118 | rtx first_shift_count, second_shift_count; | |
1119 | optab reverse_unsigned_shift, unsigned_shift; | |
1120 | ||
1121 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1122 | ? lshr_optab : ashl_optab); | |
1123 | ||
1124 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1125 | ? ashl_optab : lshr_optab); | |
1126 | ||
1127 | if (shift_count > BITS_PER_WORD) | |
1128 | { | |
1129 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
7e1a450d | 1130 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
8c597270 JW |
1131 | } |
1132 | else | |
1133 | { | |
1134 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1135 | second_shift_count = GEN_INT (shift_count); | |
1136 | } | |
1137 | ||
1138 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1139 | outof_input, first_shift_count, | |
70864443 | 1140 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1141 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1142 | into_input, second_shift_count, | |
5be5c8d4 | 1143 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1144 | |
1145 | if (into_temp1 != 0 && into_temp2 != 0) | |
1146 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1147 | into_target, unsignedp, next_methods); | |
1148 | else | |
1149 | inter = 0; | |
1150 | ||
cb5b00cf | 1151 | if (inter != 0 && inter != into_target) |
70864443 | 1152 | emit_move_insn (into_target, inter); |
8c597270 JW |
1153 | |
1154 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1155 | into_input, first_shift_count, | |
70864443 | 1156 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1157 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1158 | outof_input, second_shift_count, | |
5be5c8d4 | 1159 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1160 | |
1161 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1162 | inter = expand_binop (word_mode, ior_optab, | |
1163 | outof_temp1, outof_temp2, | |
1164 | outof_target, unsignedp, next_methods); | |
1165 | ||
cb5b00cf | 1166 | if (inter != 0 && inter != outof_target) |
70864443 | 1167 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1168 | } |
1169 | ||
1170 | insns = get_insns (); | |
1171 | end_sequence (); | |
1172 | ||
70864443 RK |
1173 | if (inter != 0) |
1174 | { | |
1175 | if (binoptab->code != UNKNOWN) | |
9e6a5703 | 1176 | equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1); |
70864443 RK |
1177 | else |
1178 | equiv_value = 0; | |
8c597270 | 1179 | |
70864443 RK |
1180 | /* We can't make this a no conflict block if this is a word swap, |
1181 | because the word swap case fails if the input and output values | |
1182 | are in the same register. */ | |
1183 | if (shift_count != BITS_PER_WORD) | |
1184 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); | |
1185 | else | |
2f937369 | 1186 | emit_insn (insns); |
70864443 RK |
1187 | |
1188 | ||
1189 | return target; | |
1190 | } | |
8c597270 JW |
1191 | } |
1192 | ||
77c9c6c2 RK |
1193 | /* These can be done a word at a time by propagating carries. */ |
1194 | if ((binoptab == add_optab || binoptab == sub_optab) | |
1195 | && class == MODE_INT | |
1196 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD | |
34e56753 | 1197 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 1198 | { |
e2500fed | 1199 | unsigned int i; |
77c9c6c2 | 1200 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
a4b5414c | 1201 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
07444f1d | 1202 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
64de6c0a | 1203 | rtx xop0, xop1, xtarget; |
77c9c6c2 RK |
1204 | |
1205 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1206 | value is one of those, use it. Otherwise, use 1 since it is the | |
1207 | one easiest to get. */ | |
1208 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1209 | int normalizep = STORE_FLAG_VALUE; | |
1210 | #else | |
1211 | int normalizep = 1; | |
1212 | #endif | |
1213 | ||
1214 | /* Prepare the operands. */ | |
cee85023 RS |
1215 | xop0 = force_reg (mode, op0); |
1216 | xop1 = force_reg (mode, op1); | |
77c9c6c2 | 1217 | |
64de6c0a DE |
1218 | xtarget = gen_reg_rtx (mode); |
1219 | ||
1220 | if (target == 0 || GET_CODE (target) != REG) | |
1221 | target = xtarget; | |
77c9c6c2 | 1222 | |
af2cc4dd RS |
1223 | /* Indicate for flow that the entire target reg is being set. */ |
1224 | if (GET_CODE (target) == REG) | |
64de6c0a | 1225 | emit_insn (gen_rtx_CLOBBER (VOIDmode, xtarget)); |
af2cc4dd | 1226 | |
77c9c6c2 RK |
1227 | /* Do the actual arithmetic. */ |
1228 | for (i = 0; i < nwords; i++) | |
1229 | { | |
1230 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
64de6c0a | 1231 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
cee85023 RS |
1232 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
1233 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
77c9c6c2 RK |
1234 | rtx x; |
1235 | ||
1236 | /* Main add/subtract of the input operands. */ | |
34e56753 | 1237 | x = expand_binop (word_mode, binoptab, |
77c9c6c2 | 1238 | op0_piece, op1_piece, |
70864443 | 1239 | target_piece, unsignedp, next_methods); |
77c9c6c2 RK |
1240 | if (x == 0) |
1241 | break; | |
1242 | ||
1243 | if (i + 1 < nwords) | |
1244 | { | |
1245 | /* Store carry from main add/subtract. */ | |
34e56753 | 1246 | carry_out = gen_reg_rtx (word_mode); |
23357404 TG |
1247 | carry_out = emit_store_flag_force (carry_out, |
1248 | (binoptab == add_optab | |
b30f05db | 1249 | ? LT : GT), |
23357404 TG |
1250 | x, op0_piece, |
1251 | word_mode, 1, normalizep); | |
77c9c6c2 RK |
1252 | } |
1253 | ||
1254 | if (i > 0) | |
1255 | { | |
859cb4d8 | 1256 | rtx newx; |
0c20a65f | 1257 | |
77c9c6c2 | 1258 | /* Add/subtract previous carry to main result. */ |
859cb4d8 GK |
1259 | newx = expand_binop (word_mode, |
1260 | normalizep == 1 ? binoptab : otheroptab, | |
1261 | x, carry_in, | |
1262 | NULL_RTX, 1, next_methods); | |
77c9c6c2 RK |
1263 | |
1264 | if (i + 1 < nwords) | |
1265 | { | |
77c9c6c2 | 1266 | /* Get out carry from adding/subtracting carry in. */ |
859cb4d8 | 1267 | rtx carry_tmp = gen_reg_rtx (word_mode); |
23357404 | 1268 | carry_tmp = emit_store_flag_force (carry_tmp, |
859cb4d8 GK |
1269 | (binoptab == add_optab |
1270 | ? LT : GT), | |
1271 | newx, x, | |
23357404 | 1272 | word_mode, 1, normalizep); |
70864443 | 1273 | |
77c9c6c2 | 1274 | /* Logical-ior the two poss. carry together. */ |
34e56753 | 1275 | carry_out = expand_binop (word_mode, ior_optab, |
77c9c6c2 | 1276 | carry_out, carry_tmp, |
70864443 RK |
1277 | carry_out, 0, next_methods); |
1278 | if (carry_out == 0) | |
77c9c6c2 RK |
1279 | break; |
1280 | } | |
859cb4d8 | 1281 | emit_move_insn (target_piece, newx); |
77c9c6c2 RK |
1282 | } |
1283 | ||
1284 | carry_in = carry_out; | |
0c20a65f | 1285 | } |
77c9c6c2 | 1286 | |
e2500fed | 1287 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
77c9c6c2 | 1288 | { |
d0ccc658 RK |
1289 | if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing |
1290 | || ! rtx_equal_p (target, xtarget)) | |
02214a5c | 1291 | { |
64de6c0a | 1292 | rtx temp = emit_move_insn (target, xtarget); |
70864443 | 1293 | |
5fa671cf | 1294 | set_unique_reg_note (temp, |
0c20a65f | 1295 | REG_EQUAL, |
5fa671cf AM |
1296 | gen_rtx_fmt_ee (binoptab->code, mode, |
1297 | copy_rtx (xop0), | |
1298 | copy_rtx (xop1))); | |
02214a5c | 1299 | } |
2cd622c3 AO |
1300 | else |
1301 | target = xtarget; | |
c5c76735 | 1302 | |
77c9c6c2 RK |
1303 | return target; |
1304 | } | |
c5c76735 | 1305 | |
77c9c6c2 RK |
1306 | else |
1307 | delete_insns_since (last); | |
1308 | } | |
1309 | ||
1310 | /* If we want to multiply two two-word values and have normal and widening | |
1311 | multiplies of single-word values, we can do this with three smaller | |
1312 | multiplications. Note that we do not make a REG_NO_CONFLICT block here | |
0c20a65f | 1313 | because we are not operating on one word at a time. |
77c9c6c2 RK |
1314 | |
1315 | The multiplication proceeds as follows: | |
34e56753 RS |
1316 | _______________________ |
1317 | [__op0_high_|__op0_low__] | |
1318 | _______________________ | |
6ffe0821 | 1319 | * [__op1_high_|__op1_low__] |
34e56753 RS |
1320 | _______________________________________________ |
1321 | _______________________ | |
6ffe0821 | 1322 | (1) [__op0_low__*__op1_low__] |
34e56753 | 1323 | _______________________ |
6ffe0821 | 1324 | (2a) [__op0_low__*__op1_high_] |
34e56753 | 1325 | _______________________ |
6ffe0821 | 1326 | (2b) [__op0_high_*__op1_low__] |
34e56753 RS |
1327 | _______________________ |
1328 | (3) [__op0_high_*__op1_high_] | |
77c9c6c2 RK |
1329 | |
1330 | ||
1331 | This gives a 4-word result. Since we are only interested in the | |
1332 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1333 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1334 | calculated using non-widening multiplication. | |
1335 | ||
1336 | (1), however, needs to be calculated with an unsigned widening | |
1337 | multiplication. If this operation is not directly supported we | |
1338 | try using a signed widening multiplication and adjust the result. | |
1339 | This adjustment works as follows: | |
1340 | ||
1341 | If both operands are positive then no adjustment is needed. | |
1342 | ||
1343 | If the operands have different signs, for example op0_low < 0 and | |
1344 | op1_low >= 0, the instruction treats the most significant bit of | |
1345 | op0_low as a sign bit instead of a bit with significance | |
1346 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1347 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1348 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1349 | the result. | |
1350 | ||
1351 | Similarly, if both operands are negative, we need to add | |
1352 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1353 | ||
1354 | We use a trick to adjust quickly. We logically shift op0_low right | |
1355 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1356 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1357 | logical shift exists, we do an arithmetic right shift and subtract | |
1358 | the 0 or -1. */ | |
1359 | ||
1360 | if (binoptab == smul_optab | |
1361 | && class == MODE_INT | |
1362 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
34e56753 RS |
1363 | && smul_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing |
1364 | && add_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
77c9c6c2 RK |
1365 | && ((umul_widen_optab->handlers[(int) mode].insn_code |
1366 | != CODE_FOR_nothing) | |
1367 | || (smul_widen_optab->handlers[(int) mode].insn_code | |
1368 | != CODE_FOR_nothing))) | |
1369 | { | |
1370 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1371 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1372 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1373 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1374 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1375 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1376 | rtx product = 0; | |
07444f1d TM |
1377 | rtx op0_xhigh = NULL_RTX; |
1378 | rtx op1_xhigh = NULL_RTX; | |
77c9c6c2 RK |
1379 | |
1380 | /* If the target is the same as one of the inputs, don't use it. This | |
1381 | prevents problems with the REG_EQUAL note. */ | |
f96d689c RK |
1382 | if (target == op0 || target == op1 |
1383 | || (target != 0 && GET_CODE (target) != REG)) | |
77c9c6c2 RK |
1384 | target = 0; |
1385 | ||
1386 | /* Multiply the two lower words to get a double-word product. | |
1387 | If unsigned widening multiplication is available, use that; | |
1388 | otherwise use the signed form and compensate. */ | |
1389 | ||
1390 | if (umul_widen_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
1391 | { | |
1392 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1393 | target, 1, OPTAB_DIRECT); | |
1394 | ||
1395 | /* If we didn't succeed, delete everything we did so far. */ | |
1396 | if (product == 0) | |
1397 | delete_insns_since (last); | |
1398 | else | |
1399 | op0_xhigh = op0_high, op1_xhigh = op1_high; | |
1400 | } | |
1401 | ||
1402 | if (product == 0 | |
1403 | && smul_widen_optab->handlers[(int) mode].insn_code | |
1404 | != CODE_FOR_nothing) | |
1405 | { | |
b1ec3c92 | 1406 | rtx wordm1 = GEN_INT (BITS_PER_WORD - 1); |
77c9c6c2 RK |
1407 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, |
1408 | target, 1, OPTAB_DIRECT); | |
34e56753 | 1409 | op0_xhigh = expand_binop (word_mode, lshr_optab, op0_low, wordm1, |
70864443 | 1410 | NULL_RTX, 1, next_methods); |
77c9c6c2 | 1411 | if (op0_xhigh) |
34e56753 | 1412 | op0_xhigh = expand_binop (word_mode, add_optab, op0_high, |
70864443 | 1413 | op0_xhigh, op0_xhigh, 0, next_methods); |
77c9c6c2 RK |
1414 | else |
1415 | { | |
34e56753 | 1416 | op0_xhigh = expand_binop (word_mode, ashr_optab, op0_low, wordm1, |
70864443 | 1417 | NULL_RTX, 0, next_methods); |
77c9c6c2 | 1418 | if (op0_xhigh) |
34e56753 | 1419 | op0_xhigh = expand_binop (word_mode, sub_optab, op0_high, |
77c9c6c2 | 1420 | op0_xhigh, op0_xhigh, 0, |
70864443 | 1421 | next_methods); |
77c9c6c2 RK |
1422 | } |
1423 | ||
34e56753 | 1424 | op1_xhigh = expand_binop (word_mode, lshr_optab, op1_low, wordm1, |
70864443 | 1425 | NULL_RTX, 1, next_methods); |
77c9c6c2 | 1426 | if (op1_xhigh) |
34e56753 | 1427 | op1_xhigh = expand_binop (word_mode, add_optab, op1_high, |
70864443 | 1428 | op1_xhigh, op1_xhigh, 0, next_methods); |
77c9c6c2 RK |
1429 | else |
1430 | { | |
34e56753 | 1431 | op1_xhigh = expand_binop (word_mode, ashr_optab, op1_low, wordm1, |
70864443 | 1432 | NULL_RTX, 0, next_methods); |
77c9c6c2 | 1433 | if (op1_xhigh) |
34e56753 | 1434 | op1_xhigh = expand_binop (word_mode, sub_optab, op1_high, |
77c9c6c2 | 1435 | op1_xhigh, op1_xhigh, 0, |
70864443 | 1436 | next_methods); |
77c9c6c2 RK |
1437 | } |
1438 | } | |
1439 | ||
1440 | /* If we have been able to directly compute the product of the | |
1441 | low-order words of the operands and perform any required adjustments | |
1442 | of the operands, we proceed by trying two more multiplications | |
1443 | and then computing the appropriate sum. | |
1444 | ||
1445 | We have checked above that the required addition is provided. | |
1446 | Full-word addition will normally always succeed, especially if | |
1447 | it is provided at all, so we don't worry about its failure. The | |
1448 | multiplication may well fail, however, so we do handle that. */ | |
1449 | ||
1450 | if (product && op0_xhigh && op1_xhigh) | |
1451 | { | |
77c9c6c2 | 1452 | rtx product_high = operand_subword (product, high, 1, mode); |
b1ec3c92 CH |
1453 | rtx temp = expand_binop (word_mode, binoptab, op0_low, op1_xhigh, |
1454 | NULL_RTX, 0, OPTAB_DIRECT); | |
77c9c6c2 | 1455 | |
c7539aa0 JL |
1456 | if (!REG_P (product_high)) |
1457 | product_high = force_reg (word_mode, product_high); | |
1458 | ||
70864443 RK |
1459 | if (temp != 0) |
1460 | temp = expand_binop (word_mode, add_optab, temp, product_high, | |
1461 | product_high, 0, next_methods); | |
77c9c6c2 | 1462 | |
70864443 RK |
1463 | if (temp != 0 && temp != product_high) |
1464 | emit_move_insn (product_high, temp); | |
1465 | ||
1466 | if (temp != 0) | |
0c20a65f | 1467 | temp = expand_binop (word_mode, binoptab, op1_low, op0_xhigh, |
70864443 RK |
1468 | NULL_RTX, 0, OPTAB_DIRECT); |
1469 | ||
1470 | if (temp != 0) | |
1471 | temp = expand_binop (word_mode, add_optab, temp, | |
1472 | product_high, product_high, | |
1473 | 0, next_methods); | |
77c9c6c2 | 1474 | |
70864443 RK |
1475 | if (temp != 0 && temp != product_high) |
1476 | emit_move_insn (product_high, temp); | |
77c9c6c2 | 1477 | |
c7539aa0 JL |
1478 | emit_move_insn (operand_subword (product, high, 1, mode), product_high); |
1479 | ||
70864443 RK |
1480 | if (temp != 0) |
1481 | { | |
02214a5c RK |
1482 | if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1483 | { | |
1484 | temp = emit_move_insn (product, product); | |
5fa671cf | 1485 | set_unique_reg_note (temp, |
0c20a65f | 1486 | REG_EQUAL, |
5fa671cf AM |
1487 | gen_rtx_fmt_ee (MULT, mode, |
1488 | copy_rtx (op0), | |
1489 | copy_rtx (op1))); | |
02214a5c | 1490 | } |
c5c76735 | 1491 | |
77c9c6c2 RK |
1492 | return product; |
1493 | } | |
1494 | } | |
1495 | ||
1496 | /* If we get here, we couldn't do it for some reason even though we | |
1497 | originally thought we could. Delete anything we've emitted in | |
1498 | trying to do it. */ | |
1499 | ||
1500 | delete_insns_since (last); | |
1501 | } | |
1502 | ||
cb2a532e AH |
1503 | /* Open-code the vector operations if we have no hardware support |
1504 | for them. */ | |
1505 | if (class == MODE_VECTOR_INT || class == MODE_VECTOR_FLOAT) | |
1506 | return expand_vector_binop (mode, binoptab, op0, op1, target, | |
1507 | unsignedp, methods); | |
1508 | ||
b818abb0 RS |
1509 | /* We need to open-code the complex type operations: '+, -, * and /' */ |
1510 | ||
1511 | /* At this point we allow operations between two similar complex | |
1512 | numbers, and also if one of the operands is not a complex number | |
1513 | but rather of MODE_FLOAT or MODE_INT. However, the caller | |
1514 | must make sure that the MODE of the non-complex operand matches | |
6f43c157 | 1515 | the SUBMODE of the complex operand. */ |
b818abb0 RS |
1516 | |
1517 | if (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT) | |
6f43c157 | 1518 | { |
70864443 RK |
1519 | rtx real0 = 0, imag0 = 0; |
1520 | rtx real1 = 0, imag1 = 0; | |
1521 | rtx realr, imagr, res; | |
b818abb0 RS |
1522 | rtx seq; |
1523 | rtx equiv_value; | |
70864443 | 1524 | int ok = 0; |
b818abb0 | 1525 | |
f9da5064 | 1526 | /* Find the correct mode for the real and imaginary parts. */ |
27e58a70 | 1527 | enum machine_mode submode = GET_MODE_INNER(mode); |
b818abb0 RS |
1528 | |
1529 | if (submode == BLKmode) | |
1530 | abort (); | |
1531 | ||
1532 | if (! target) | |
1533 | target = gen_reg_rtx (mode); | |
1534 | ||
1535 | start_sequence (); | |
1536 | ||
c64f913e | 1537 | realr = gen_realpart (submode, target); |
decdfa82 | 1538 | imagr = gen_imagpart (submode, target); |
b818abb0 RS |
1539 | |
1540 | if (GET_MODE (op0) == mode) | |
1541 | { | |
c64f913e | 1542 | real0 = gen_realpart (submode, op0); |
decdfa82 | 1543 | imag0 = gen_imagpart (submode, op0); |
b818abb0 RS |
1544 | } |
1545 | else | |
1546 | real0 = op0; | |
1547 | ||
1548 | if (GET_MODE (op1) == mode) | |
1549 | { | |
c64f913e | 1550 | real1 = gen_realpart (submode, op1); |
decdfa82 | 1551 | imag1 = gen_imagpart (submode, op1); |
b818abb0 RS |
1552 | } |
1553 | else | |
1554 | real1 = op1; | |
1555 | ||
c0fe508e | 1556 | if (real0 == 0 || real1 == 0 || ! (imag0 != 0 || imag1 != 0)) |
b818abb0 RS |
1557 | abort (); |
1558 | ||
6f43c157 RS |
1559 | switch (binoptab->code) |
1560 | { | |
1561 | case PLUS: | |
96f153da | 1562 | /* (a+ib) + (c+id) = (a+c) + i(b+d) */ |
6f43c157 | 1563 | case MINUS: |
96f153da | 1564 | /* (a+ib) - (c+id) = (a-c) + i(b-d) */ |
b818abb0 RS |
1565 | res = expand_binop (submode, binoptab, real0, real1, |
1566 | realr, unsignedp, methods); | |
70864443 RK |
1567 | |
1568 | if (res == 0) | |
1569 | break; | |
1570 | else if (res != realr) | |
b818abb0 RS |
1571 | emit_move_insn (realr, res); |
1572 | ||
086bbd21 | 1573 | if (imag0 != 0 && imag1 != 0) |
b818abb0 RS |
1574 | res = expand_binop (submode, binoptab, imag0, imag1, |
1575 | imagr, unsignedp, methods); | |
086bbd21 | 1576 | else if (imag0 != 0) |
b818abb0 RS |
1577 | res = imag0; |
1578 | else if (binoptab->code == MINUS) | |
91ce572a CC |
1579 | res = expand_unop (submode, |
1580 | binoptab == subv_optab ? negv_optab : neg_optab, | |
1581 | imag1, imagr, unsignedp); | |
b818abb0 RS |
1582 | else |
1583 | res = imag1; | |
1584 | ||
70864443 RK |
1585 | if (res == 0) |
1586 | break; | |
1587 | else if (res != imagr) | |
b818abb0 | 1588 | emit_move_insn (imagr, res); |
70864443 RK |
1589 | |
1590 | ok = 1; | |
b818abb0 | 1591 | break; |
6f43c157 RS |
1592 | |
1593 | case MULT: | |
b818abb0 RS |
1594 | /* (a+ib) * (c+id) = (ac-bd) + i(ad+cb) */ |
1595 | ||
086bbd21 | 1596 | if (imag0 != 0 && imag1 != 0) |
b818abb0 | 1597 | { |
70864443 RK |
1598 | rtx temp1, temp2; |
1599 | ||
54e7b5e6 RS |
1600 | /* Don't fetch these from memory more than once. */ |
1601 | real0 = force_reg (submode, real0); | |
1602 | real1 = force_reg (submode, real1); | |
1603 | imag0 = force_reg (submode, imag0); | |
1604 | imag1 = force_reg (submode, imag1); | |
1605 | ||
70864443 RK |
1606 | temp1 = expand_binop (submode, binoptab, real0, real1, NULL_RTX, |
1607 | unsignedp, methods); | |
1608 | ||
1609 | temp2 = expand_binop (submode, binoptab, imag0, imag1, NULL_RTX, | |
1610 | unsignedp, methods); | |
1611 | ||
1612 | if (temp1 == 0 || temp2 == 0) | |
1613 | break; | |
1614 | ||
91ce572a CC |
1615 | res = (expand_binop |
1616 | (submode, | |
1617 | binoptab == smulv_optab ? subv_optab : sub_optab, | |
1618 | temp1, temp2, realr, unsignedp, methods)); | |
b818abb0 | 1619 | |
70864443 RK |
1620 | if (res == 0) |
1621 | break; | |
1622 | else if (res != realr) | |
54e7b5e6 | 1623 | emit_move_insn (realr, res); |
b818abb0 | 1624 | |
70864443 RK |
1625 | temp1 = expand_binop (submode, binoptab, real0, imag1, |
1626 | NULL_RTX, unsignedp, methods); | |
1627 | ||
df8ca70e RS |
1628 | /* Avoid expanding redundant multiplication for the common |
1629 | case of squaring a complex number. */ | |
1630 | if (rtx_equal_p (real0, real1) && rtx_equal_p (imag0, imag1)) | |
1631 | temp2 = temp1; | |
1632 | else | |
1633 | temp2 = expand_binop (submode, binoptab, real1, imag0, | |
1634 | NULL_RTX, unsignedp, methods); | |
70864443 RK |
1635 | |
1636 | if (temp1 == 0 || temp2 == 0) | |
7e1a450d | 1637 | break; |
1c63cc82 | 1638 | |
91ce572a CC |
1639 | res = (expand_binop |
1640 | (submode, | |
1641 | binoptab == smulv_optab ? addv_optab : add_optab, | |
1642 | temp1, temp2, imagr, unsignedp, methods)); | |
70864443 RK |
1643 | |
1644 | if (res == 0) | |
1645 | break; | |
1646 | else if (res != imagr) | |
b818abb0 | 1647 | emit_move_insn (imagr, res); |
70864443 RK |
1648 | |
1649 | ok = 1; | |
b818abb0 RS |
1650 | } |
1651 | else | |
1652 | { | |
54e7b5e6 RS |
1653 | /* Don't fetch these from memory more than once. */ |
1654 | real0 = force_reg (submode, real0); | |
1655 | real1 = force_reg (submode, real1); | |
1656 | ||
96f153da RS |
1657 | res = expand_binop (submode, binoptab, real0, real1, |
1658 | realr, unsignedp, methods); | |
70864443 RK |
1659 | if (res == 0) |
1660 | break; | |
1661 | else if (res != realr) | |
b818abb0 RS |
1662 | emit_move_insn (realr, res); |
1663 | ||
086bbd21 | 1664 | if (imag0 != 0) |
b818abb0 RS |
1665 | res = expand_binop (submode, binoptab, |
1666 | real1, imag0, imagr, unsignedp, methods); | |
1667 | else | |
1668 | res = expand_binop (submode, binoptab, | |
1669 | real0, imag1, imagr, unsignedp, methods); | |
70864443 RK |
1670 | |
1671 | if (res == 0) | |
1672 | break; | |
1673 | else if (res != imagr) | |
b818abb0 | 1674 | emit_move_insn (imagr, res); |
70864443 RK |
1675 | |
1676 | ok = 1; | |
b818abb0 RS |
1677 | } |
1678 | break; | |
6f43c157 RS |
1679 | |
1680 | case DIV: | |
96f153da | 1681 | /* (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) */ |
0c20a65f | 1682 | |
086bbd21 | 1683 | if (imag1 == 0) |
70864443 RK |
1684 | { |
1685 | /* (a+ib) / (c+i0) = (a/c) + i(b/c) */ | |
54e7b5e6 RS |
1686 | |
1687 | /* Don't fetch these from memory more than once. */ | |
1688 | real1 = force_reg (submode, real1); | |
1689 | ||
96f153da | 1690 | /* Simply divide the real and imaginary parts by `c' */ |
2140ed5b RK |
1691 | if (class == MODE_COMPLEX_FLOAT) |
1692 | res = expand_binop (submode, binoptab, real0, real1, | |
1693 | realr, unsignedp, methods); | |
1694 | else | |
1695 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1696 | real0, real1, realr, unsignedp); | |
1697 | ||
70864443 RK |
1698 | if (res == 0) |
1699 | break; | |
1700 | else if (res != realr) | |
b818abb0 RS |
1701 | emit_move_insn (realr, res); |
1702 | ||
2140ed5b RK |
1703 | if (class == MODE_COMPLEX_FLOAT) |
1704 | res = expand_binop (submode, binoptab, imag0, real1, | |
1705 | imagr, unsignedp, methods); | |
1706 | else | |
1707 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1708 | imag0, real1, imagr, unsignedp); | |
1709 | ||
70864443 RK |
1710 | if (res == 0) |
1711 | break; | |
1712 | else if (res != imagr) | |
b818abb0 | 1713 | emit_move_insn (imagr, res); |
b818abb0 | 1714 | |
70864443 RK |
1715 | ok = 1; |
1716 | } | |
1717 | else | |
1718 | { | |
c64f913e | 1719 | switch (flag_complex_divide_method) |
70864443 | 1720 | { |
c64f913e CB |
1721 | case 0: |
1722 | ok = expand_cmplxdiv_straight (real0, real1, imag0, imag1, | |
1723 | realr, imagr, submode, | |
1724 | unsignedp, methods, | |
1725 | class, binoptab); | |
1726 | break; | |
41b19f3e | 1727 | |
c64f913e CB |
1728 | case 1: |
1729 | ok = expand_cmplxdiv_wide (real0, real1, imag0, imag1, | |
1730 | realr, imagr, submode, | |
1731 | unsignedp, methods, | |
1732 | class, binoptab); | |
1733 | break; | |
70864443 | 1734 | |
c64f913e CB |
1735 | default: |
1736 | abort (); | |
b818abb0 | 1737 | } |
b818abb0 RS |
1738 | } |
1739 | break; | |
0c20a65f | 1740 | |
b818abb0 RS |
1741 | default: |
1742 | abort (); | |
1743 | } | |
1744 | ||
c15886da | 1745 | seq = get_insns (); |
b818abb0 RS |
1746 | end_sequence (); |
1747 | ||
70864443 RK |
1748 | if (ok) |
1749 | { | |
1750 | if (binoptab->code != UNKNOWN) | |
1751 | equiv_value | |
9e6a5703 JC |
1752 | = gen_rtx_fmt_ee (binoptab->code, mode, |
1753 | copy_rtx (op0), copy_rtx (op1)); | |
70864443 RK |
1754 | else |
1755 | equiv_value = 0; | |
0c20a65f | 1756 | |
70864443 | 1757 | emit_no_conflict_block (seq, target, op0, op1, equiv_value); |
0c20a65f | 1758 | |
70864443 RK |
1759 | return target; |
1760 | } | |
b818abb0 | 1761 | } |
b818abb0 | 1762 | |
77c9c6c2 RK |
1763 | /* It can't be open-coded in this mode. |
1764 | Use a library call if one is available and caller says that's ok. */ | |
1765 | ||
1766 | if (binoptab->handlers[(int) mode].libfunc | |
1767 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) | |
1768 | { | |
1769 | rtx insns; | |
0bbb7f4d RS |
1770 | rtx op1x = op1; |
1771 | enum machine_mode op1_mode = mode; | |
9a7f678c | 1772 | rtx value; |
77c9c6c2 RK |
1773 | |
1774 | start_sequence (); | |
1775 | ||
0bbb7f4d RS |
1776 | if (shift_op) |
1777 | { | |
1778 | op1_mode = word_mode; | |
1779 | /* Specify unsigned here, | |
1780 | since negative shift counts are meaningless. */ | |
1781 | op1x = convert_to_mode (word_mode, op1, 1); | |
1782 | } | |
1783 | ||
82f0e2cc RK |
1784 | if (GET_MODE (op0) != VOIDmode |
1785 | && GET_MODE (op0) != mode) | |
5035bbfe TG |
1786 | op0 = convert_to_mode (mode, op0, unsignedp); |
1787 | ||
77c9c6c2 RK |
1788 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
1789 | if the libcall is cse'd or moved. */ | |
9a7f678c | 1790 | value = emit_library_call_value (binoptab->handlers[(int) mode].libfunc, |
ebb1b59a | 1791 | NULL_RTX, LCT_CONST, mode, 2, |
9a7f678c | 1792 | op0, mode, op1x, op1_mode); |
77c9c6c2 RK |
1793 | |
1794 | insns = get_insns (); | |
1795 | end_sequence (); | |
1796 | ||
1797 | target = gen_reg_rtx (mode); | |
9a7f678c | 1798 | emit_libcall_block (insns, target, value, |
9e6a5703 | 1799 | gen_rtx_fmt_ee (binoptab->code, mode, op0, op1)); |
77c9c6c2 RK |
1800 | |
1801 | return target; | |
1802 | } | |
1803 | ||
1804 | delete_insns_since (last); | |
1805 | ||
1806 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
1807 | ||
1808 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
1809 | || methods == OPTAB_MUST_WIDEN)) | |
abd418d3 RS |
1810 | { |
1811 | /* Caller says, don't even try. */ | |
1812 | delete_insns_since (entry_last); | |
1813 | return 0; | |
1814 | } | |
77c9c6c2 RK |
1815 | |
1816 | /* Compute the value of METHODS to pass to recursive calls. | |
1817 | Don't allow widening to be tried recursively. */ | |
1818 | ||
1819 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
1820 | ||
34e56753 RS |
1821 | /* Look for a wider mode of the same class for which it appears we can do |
1822 | the operation. */ | |
77c9c6c2 RK |
1823 | |
1824 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
1825 | { | |
34e56753 | 1826 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
1827 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1828 | { | |
1829 | if ((binoptab->handlers[(int) wider_mode].insn_code | |
1830 | != CODE_FOR_nothing) | |
1831 | || (methods == OPTAB_LIB | |
1832 | && binoptab->handlers[(int) wider_mode].libfunc)) | |
1833 | { | |
1834 | rtx xop0 = op0, xop1 = op1; | |
1835 | int no_extend = 0; | |
1836 | ||
34e56753 | 1837 | /* For certain integer operations, we need not actually extend |
77c9c6c2 | 1838 | the narrow operands, as long as we will truncate |
835532b8 | 1839 | the results to the same narrowness. */ |
77c9c6c2 | 1840 | |
34e56753 RS |
1841 | if ((binoptab == ior_optab || binoptab == and_optab |
1842 | || binoptab == xor_optab | |
1843 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 1844 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 1845 | && class == MODE_INT) |
77c9c6c2 RK |
1846 | no_extend = 1; |
1847 | ||
0661a3de RS |
1848 | xop0 = widen_operand (xop0, wider_mode, mode, |
1849 | unsignedp, no_extend); | |
943cc242 RK |
1850 | |
1851 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 1852 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 1853 | no_extend && binoptab != ashl_optab); |
77c9c6c2 | 1854 | |
b1ec3c92 | 1855 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
77c9c6c2 RK |
1856 | unsignedp, methods); |
1857 | if (temp) | |
1858 | { | |
34e56753 | 1859 | if (class != MODE_INT) |
77c9c6c2 RK |
1860 | { |
1861 | if (target == 0) | |
1862 | target = gen_reg_rtx (mode); | |
1863 | convert_move (target, temp, 0); | |
1864 | return target; | |
1865 | } | |
1866 | else | |
1867 | return gen_lowpart (mode, temp); | |
1868 | } | |
1869 | else | |
1870 | delete_insns_since (last); | |
1871 | } | |
1872 | } | |
1873 | } | |
1874 | ||
abd418d3 | 1875 | delete_insns_since (entry_last); |
77c9c6c2 RK |
1876 | return 0; |
1877 | } | |
cb2a532e AH |
1878 | |
1879 | /* Like expand_binop, but for open-coding vectors binops. */ | |
1880 | ||
1881 | static rtx | |
0c20a65f AJ |
1882 | expand_vector_binop (enum machine_mode mode, optab binoptab, rtx op0, |
1883 | rtx op1, rtx target, int unsignedp, | |
1884 | enum optab_methods methods) | |
cb2a532e | 1885 | { |
34a80643 R |
1886 | enum machine_mode submode, tmode; |
1887 | int size, elts, subsize, subbitsize, i; | |
cb2a532e AH |
1888 | rtx t, a, b, res, seq; |
1889 | enum mode_class class; | |
1890 | ||
1891 | class = GET_MODE_CLASS (mode); | |
1892 | ||
7e1a450d | 1893 | size = GET_MODE_SIZE (mode); |
cb2a532e | 1894 | submode = GET_MODE_INNER (mode); |
cb2a532e | 1895 | |
34a80643 R |
1896 | /* Search for the widest vector mode with the same inner mode that is |
1897 | still narrower than MODE and that allows to open-code this operator. | |
1898 | Note, if we find such a mode and the handler later decides it can't | |
1899 | do the expansion, we'll be called recursively with the narrower mode. */ | |
1900 | for (tmode = GET_CLASS_NARROWEST_MODE (class); | |
1901 | GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode); | |
1902 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
1903 | { | |
1904 | if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode) | |
1905 | && binoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) | |
1906 | submode = tmode; | |
1907 | } | |
cb2a532e AH |
1908 | |
1909 | switch (binoptab->code) | |
1910 | { | |
34a80643 R |
1911 | case AND: |
1912 | case IOR: | |
1913 | case XOR: | |
1914 | tmode = int_mode_for_mode (mode); | |
1915 | if (tmode != BLKmode) | |
1916 | submode = tmode; | |
cb2a532e AH |
1917 | case PLUS: |
1918 | case MINUS: | |
1919 | case MULT: | |
1920 | case DIV: | |
34a80643 R |
1921 | subsize = GET_MODE_SIZE (submode); |
1922 | subbitsize = GET_MODE_BITSIZE (submode); | |
1923 | elts = size / subsize; | |
1924 | ||
1925 | /* If METHODS is OPTAB_DIRECT, we don't insist on the exact mode, | |
1926 | but that we operate on more than one element at a time. */ | |
1927 | if (subsize == GET_MODE_UNIT_SIZE (mode) && methods == OPTAB_DIRECT) | |
1928 | return 0; | |
1929 | ||
1930 | start_sequence (); | |
1931 | ||
1932 | /* Errors can leave us with a const0_rtx as operand. */ | |
1933 | if (GET_MODE (op0) != mode) | |
1934 | op0 = copy_to_mode_reg (mode, op0); | |
1935 | if (GET_MODE (op1) != mode) | |
1936 | op1 = copy_to_mode_reg (mode, op1); | |
1937 | ||
1938 | if (!target) | |
1939 | target = gen_reg_rtx (mode); | |
1940 | ||
cb2a532e AH |
1941 | for (i = 0; i < elts; ++i) |
1942 | { | |
34a80643 R |
1943 | /* If this is part of a register, and not the first item in the |
1944 | word, we can't store using a SUBREG - that would clobber | |
1945 | previous results. | |
1946 | And storing with a SUBREG is only possible for the least | |
1947 | significant part, hence we can't do it for big endian | |
1948 | (unless we want to permute the evaluation order. */ | |
1949 | if (GET_CODE (target) == REG | |
1950 | && (BYTES_BIG_ENDIAN | |
1951 | ? subsize < UNITS_PER_WORD | |
1952 | : ((i * subsize) % UNITS_PER_WORD) != 0)) | |
1953 | t = NULL_RTX; | |
1954 | else | |
1955 | t = simplify_gen_subreg (submode, target, mode, i * subsize); | |
1956 | if (CONSTANT_P (op0)) | |
1957 | a = simplify_gen_subreg (submode, op0, mode, i * subsize); | |
1958 | else | |
1959 | a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp, | |
1960 | NULL_RTX, submode, submode, size); | |
1961 | if (CONSTANT_P (op1)) | |
1962 | b = simplify_gen_subreg (submode, op1, mode, i * subsize); | |
1963 | else | |
1964 | b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp, | |
1965 | NULL_RTX, submode, submode, size); | |
cb2a532e AH |
1966 | |
1967 | if (binoptab->code == DIV) | |
1968 | { | |
1969 | if (class == MODE_VECTOR_FLOAT) | |
1970 | res = expand_binop (submode, binoptab, a, b, t, | |
1971 | unsignedp, methods); | |
1972 | else | |
1973 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1974 | a, b, t, unsignedp); | |
1975 | } | |
1976 | else | |
1977 | res = expand_binop (submode, binoptab, a, b, t, | |
1978 | unsignedp, methods); | |
1979 | ||
1980 | if (res == 0) | |
1981 | break; | |
1982 | ||
34a80643 R |
1983 | if (t) |
1984 | emit_move_insn (t, res); | |
1985 | else | |
1986 | store_bit_field (target, subbitsize, i * subbitsize, submode, res, | |
1987 | size); | |
cb2a532e AH |
1988 | } |
1989 | break; | |
1990 | ||
1991 | default: | |
1992 | abort (); | |
1993 | } | |
1994 | ||
1995 | seq = get_insns (); | |
1996 | end_sequence (); | |
1997 | emit_insn (seq); | |
1998 | ||
1999 | return target; | |
2000 | } | |
2001 | ||
2002 | /* Like expand_unop but for open-coding vector unops. */ | |
2003 | ||
2004 | static rtx | |
0c20a65f AJ |
2005 | expand_vector_unop (enum machine_mode mode, optab unoptab, rtx op0, |
2006 | rtx target, int unsignedp) | |
cb2a532e | 2007 | { |
34a80643 R |
2008 | enum machine_mode submode, tmode; |
2009 | int size, elts, subsize, subbitsize, i; | |
cb2a532e AH |
2010 | rtx t, a, res, seq; |
2011 | ||
7e1a450d | 2012 | size = GET_MODE_SIZE (mode); |
cb2a532e | 2013 | submode = GET_MODE_INNER (mode); |
34a80643 R |
2014 | |
2015 | /* Search for the widest vector mode with the same inner mode that is | |
2016 | still narrower than MODE and that allows to open-code this operator. | |
2017 | Note, if we find such a mode and the handler later decides it can't | |
2018 | do the expansion, we'll be called recursively with the narrower mode. */ | |
2019 | for (tmode = GET_CLASS_NARROWEST_MODE (GET_MODE_CLASS (mode)); | |
2020 | GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode); | |
2021 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
2022 | { | |
2023 | if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode) | |
2024 | && unoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) | |
2025 | submode = tmode; | |
2026 | } | |
2027 | /* If there is no negate operation, try doing a subtract from zero. */ | |
0d541696 R |
2028 | if (unoptab == neg_optab && GET_MODE_CLASS (submode) == MODE_INT |
2029 | /* Avoid infinite recursion when an | |
2030 | error has left us with the wrong mode. */ | |
2031 | && GET_MODE (op0) == mode) | |
0c20a65f | 2032 | { |
34a80643 R |
2033 | rtx temp; |
2034 | temp = expand_binop (mode, sub_optab, CONST0_RTX (mode), op0, | |
2035 | target, unsignedp, OPTAB_DIRECT); | |
2036 | if (temp) | |
2037 | return temp; | |
2038 | } | |
2039 | ||
2040 | if (unoptab == one_cmpl_optab) | |
2041 | { | |
2042 | tmode = int_mode_for_mode (mode); | |
2043 | if (tmode != BLKmode) | |
2044 | submode = tmode; | |
2045 | } | |
2046 | ||
2047 | subsize = GET_MODE_SIZE (submode); | |
2048 | subbitsize = GET_MODE_BITSIZE (submode); | |
2049 | elts = size / subsize; | |
2050 | ||
2051 | /* Errors can leave us with a const0_rtx as operand. */ | |
2052 | if (GET_MODE (op0) != mode) | |
2053 | op0 = copy_to_mode_reg (mode, op0); | |
cb2a532e AH |
2054 | |
2055 | if (!target) | |
2056 | target = gen_reg_rtx (mode); | |
2057 | ||
2058 | start_sequence (); | |
2059 | ||
cb2a532e AH |
2060 | for (i = 0; i < elts; ++i) |
2061 | { | |
34a80643 R |
2062 | /* If this is part of a register, and not the first item in the |
2063 | word, we can't store using a SUBREG - that would clobber | |
2064 | previous results. | |
2065 | And storing with a SUBREG is only possible for the least | |
2066 | significant part, hence we can't do it for big endian | |
2067 | (unless we want to permute the evaluation order. */ | |
2068 | if (GET_CODE (target) == REG | |
2069 | && (BYTES_BIG_ENDIAN | |
2070 | ? subsize < UNITS_PER_WORD | |
2071 | : ((i * subsize) % UNITS_PER_WORD) != 0)) | |
2072 | t = NULL_RTX; | |
2073 | else | |
2074 | t = simplify_gen_subreg (submode, target, mode, i * subsize); | |
2075 | if (CONSTANT_P (op0)) | |
2076 | a = simplify_gen_subreg (submode, op0, mode, i * subsize); | |
2077 | else | |
2078 | a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp, | |
2079 | t, submode, submode, size); | |
cb2a532e AH |
2080 | |
2081 | res = expand_unop (submode, unoptab, a, t, unsignedp); | |
2082 | ||
34a80643 R |
2083 | if (t) |
2084 | emit_move_insn (t, res); | |
2085 | else | |
2086 | store_bit_field (target, subbitsize, i * subbitsize, submode, res, | |
2087 | size); | |
cb2a532e AH |
2088 | } |
2089 | ||
2090 | seq = get_insns (); | |
2091 | end_sequence (); | |
2092 | emit_insn (seq); | |
2093 | ||
2094 | return target; | |
2095 | } | |
77c9c6c2 RK |
2096 | \f |
2097 | /* Expand a binary operator which has both signed and unsigned forms. | |
2098 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2099 | signed operations. | |
2100 | ||
2101 | If we widen unsigned operands, we may use a signed wider operation instead | |
2102 | of an unsigned wider operation, since the result would be the same. */ | |
2103 | ||
2104 | rtx | |
0c20a65f AJ |
2105 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2106 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2107 | enum optab_methods methods) | |
77c9c6c2 | 2108 | { |
b3694847 | 2109 | rtx temp; |
77c9c6c2 RK |
2110 | optab direct_optab = unsignedp ? uoptab : soptab; |
2111 | struct optab wide_soptab; | |
2112 | ||
2113 | /* Do it without widening, if possible. */ | |
2114 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2115 | unsignedp, OPTAB_DIRECT); | |
2116 | if (temp || methods == OPTAB_DIRECT) | |
2117 | return temp; | |
2118 | ||
2119 | /* Try widening to a signed int. Make a fake signed optab that | |
2120 | hides any signed insn for direct use. */ | |
2121 | wide_soptab = *soptab; | |
2122 | wide_soptab.handlers[(int) mode].insn_code = CODE_FOR_nothing; | |
2123 | wide_soptab.handlers[(int) mode].libfunc = 0; | |
2124 | ||
2125 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2126 | unsignedp, OPTAB_WIDEN); | |
2127 | ||
2128 | /* For unsigned operands, try widening to an unsigned int. */ | |
2129 | if (temp == 0 && unsignedp) | |
2130 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
2131 | unsignedp, OPTAB_WIDEN); | |
2132 | if (temp || methods == OPTAB_WIDEN) | |
2133 | return temp; | |
2134 | ||
2135 | /* Use the right width lib call if that exists. */ | |
2136 | temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); | |
2137 | if (temp || methods == OPTAB_LIB) | |
2138 | return temp; | |
2139 | ||
2140 | /* Must widen and use a lib call, use either signed or unsigned. */ | |
2141 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2142 | unsignedp, methods); | |
2143 | if (temp != 0) | |
2144 | return temp; | |
2145 | if (unsignedp) | |
2146 | return expand_binop (mode, uoptab, op0, op1, target, | |
2147 | unsignedp, methods); | |
2148 | return 0; | |
2149 | } | |
2150 | \f | |
2151 | /* Generate code to perform an operation specified by BINOPTAB | |
2152 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2153 | We assume that the order of the operands for the instruction | |
2154 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2155 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2156 | ||
2157 | Either TARG0 or TARG1 may be zero, but what that means is that | |
38e01259 | 2158 | the result is not actually wanted. We will generate it into |
77c9c6c2 RK |
2159 | a dummy pseudo-reg and discard it. They may not both be zero. |
2160 | ||
2161 | Returns 1 if this operation can be performed; 0 if not. */ | |
2162 | ||
2163 | int | |
0c20a65f AJ |
2164 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2165 | int unsignedp) | |
77c9c6c2 RK |
2166 | { |
2167 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
2168 | enum mode_class class; | |
2169 | enum machine_mode wider_mode; | |
abd418d3 | 2170 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
2171 | rtx last; |
2172 | ||
2173 | class = GET_MODE_CLASS (mode); | |
2174 | ||
2175 | op0 = protect_from_queue (op0, 0); | |
2176 | op1 = protect_from_queue (op1, 0); | |
2177 | ||
2178 | if (flag_force_mem) | |
2179 | { | |
2180 | op0 = force_not_mem (op0); | |
2181 | op1 = force_not_mem (op1); | |
2182 | } | |
2183 | ||
2184 | /* If we are inside an appropriately-short loop and one operand is an | |
2185 | expensive constant, force it into a register. */ | |
aeedc93f | 2186 | if (CONSTANT_P (op0) && preserve_subexpressions_p () |
b437f1a7 | 2187 | && rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
2188 | op0 = force_reg (mode, op0); |
2189 | ||
aeedc93f | 2190 | if (CONSTANT_P (op1) && preserve_subexpressions_p () |
b437f1a7 | 2191 | && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
2192 | op1 = force_reg (mode, op1); |
2193 | ||
2194 | if (targ0) | |
2195 | targ0 = protect_from_queue (targ0, 1); | |
2196 | else | |
2197 | targ0 = gen_reg_rtx (mode); | |
2198 | if (targ1) | |
2199 | targ1 = protect_from_queue (targ1, 1); | |
2200 | else | |
2201 | targ1 = gen_reg_rtx (mode); | |
2202 | ||
2203 | /* Record where to go back to if we fail. */ | |
2204 | last = get_last_insn (); | |
2205 | ||
2206 | if (binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2207 | { | |
2208 | int icode = (int) binoptab->handlers[(int) mode].insn_code; | |
a995e389 RH |
2209 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2210 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
2211 | rtx pat; |
2212 | rtx xop0 = op0, xop1 = op1; | |
2213 | ||
874f6a6d EB |
2214 | /* In case the insn wants input operands in modes different from |
2215 | those of the actual operands, convert the operands. It would | |
2216 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
2217 | that they're properly zero-extended, sign-extended or truncated |
2218 | for their mode. */ | |
77c9c6c2 | 2219 | |
874f6a6d EB |
2220 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
2221 | xop0 = convert_modes (mode0, | |
2222 | GET_MODE (op0) != VOIDmode | |
2223 | ? GET_MODE (op0) | |
2224 | : mode, | |
2225 | xop0, unsignedp); | |
2226 | ||
2227 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
2228 | xop1 = convert_modes (mode1, | |
2229 | GET_MODE (op1) != VOIDmode | |
2230 | ? GET_MODE (op1) | |
2231 | : mode, | |
2232 | xop1, unsignedp); | |
77c9c6c2 RK |
2233 | |
2234 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
a995e389 | 2235 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
77c9c6c2 RK |
2236 | xop0 = copy_to_mode_reg (mode0, xop0); |
2237 | ||
a995e389 | 2238 | if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1)) |
77c9c6c2 RK |
2239 | xop1 = copy_to_mode_reg (mode1, xop1); |
2240 | ||
2241 | /* We could handle this, but we should always be called with a pseudo | |
2242 | for our targets and all insns should take them as outputs. */ | |
a995e389 RH |
2243 | if (! (*insn_data[icode].operand[0].predicate) (targ0, mode) |
2244 | || ! (*insn_data[icode].operand[3].predicate) (targ1, mode)) | |
77c9c6c2 | 2245 | abort (); |
0c20a65f | 2246 | |
77c9c6c2 RK |
2247 | pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1); |
2248 | if (pat) | |
2249 | { | |
2250 | emit_insn (pat); | |
2251 | return 1; | |
2252 | } | |
2253 | else | |
2254 | delete_insns_since (last); | |
2255 | } | |
2256 | ||
2257 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2258 | ||
2259 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2260 | { | |
34e56753 | 2261 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
2262 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2263 | { | |
2264 | if (binoptab->handlers[(int) wider_mode].insn_code | |
2265 | != CODE_FOR_nothing) | |
2266 | { | |
b3694847 SS |
2267 | rtx t0 = gen_reg_rtx (wider_mode); |
2268 | rtx t1 = gen_reg_rtx (wider_mode); | |
76791f3d JH |
2269 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2270 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
77c9c6c2 | 2271 | |
76791f3d | 2272 | if (expand_twoval_binop (binoptab, cop0, cop1, |
77c9c6c2 RK |
2273 | t0, t1, unsignedp)) |
2274 | { | |
2275 | convert_move (targ0, t0, unsignedp); | |
2276 | convert_move (targ1, t1, unsignedp); | |
2277 | return 1; | |
2278 | } | |
2279 | else | |
2280 | delete_insns_since (last); | |
2281 | } | |
2282 | } | |
2283 | } | |
2284 | ||
abd418d3 | 2285 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2286 | return 0; |
2287 | } | |
2288 | \f | |
ef89d648 ZW |
2289 | /* Wrapper around expand_unop which takes an rtx code to specify |
2290 | the operation to perform, not an optab pointer. All other | |
2291 | arguments are the same. */ | |
2292 | rtx | |
0c20a65f AJ |
2293 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2294 | rtx target, int unsignedp) | |
ef89d648 | 2295 | { |
7e1a450d | 2296 | optab unop = code_to_optab[(int) code]; |
ef89d648 ZW |
2297 | if (unop == 0) |
2298 | abort (); | |
2299 | ||
2300 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2301 | } | |
2302 | ||
2928cd7a RH |
2303 | /* Try calculating |
2304 | (clz:narrow x) | |
2305 | as | |
2306 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */ | |
2307 | static rtx | |
0c20a65f | 2308 | widen_clz (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2309 | { |
2310 | enum mode_class class = GET_MODE_CLASS (mode); | |
2311 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2312 | { | |
2313 | enum machine_mode wider_mode; | |
2314 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2315 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2316 | { | |
2317 | if (clz_optab->handlers[(int) wider_mode].insn_code | |
2318 | != CODE_FOR_nothing) | |
2319 | { | |
2320 | rtx xop0, temp, last; | |
2321 | ||
2322 | last = get_last_insn (); | |
2323 | ||
2324 | if (target == 0) | |
2325 | target = gen_reg_rtx (mode); | |
2326 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2327 | temp = expand_unop (wider_mode, clz_optab, xop0, NULL_RTX, true); | |
2328 | if (temp != 0) | |
2329 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2330 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2331 | - GET_MODE_BITSIZE (mode)), | |
2332 | target, true, OPTAB_DIRECT); | |
2333 | if (temp == 0) | |
2334 | delete_insns_since (last); | |
2335 | ||
2336 | return temp; | |
2337 | } | |
2338 | } | |
2339 | } | |
2340 | return 0; | |
2341 | } | |
2342 | ||
2343 | /* Try calculating (parity x) as (and (popcount x) 1), where | |
2344 | popcount can also be done in a wider mode. */ | |
2345 | static rtx | |
0c20a65f | 2346 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2347 | { |
2348 | enum mode_class class = GET_MODE_CLASS (mode); | |
2349 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2350 | { | |
2351 | enum machine_mode wider_mode; | |
2352 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2353 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2354 | { | |
2355 | if (popcount_optab->handlers[(int) wider_mode].insn_code | |
2356 | != CODE_FOR_nothing) | |
2357 | { | |
2358 | rtx xop0, temp, last; | |
2359 | ||
2360 | last = get_last_insn (); | |
2361 | ||
2362 | if (target == 0) | |
2363 | target = gen_reg_rtx (mode); | |
2364 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2365 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2366 | true); | |
2367 | if (temp != 0) | |
2368 | temp = expand_binop (wider_mode, and_optab, temp, GEN_INT (1), | |
2369 | target, true, OPTAB_DIRECT); | |
2370 | if (temp == 0) | |
2371 | delete_insns_since (last); | |
2372 | ||
2373 | return temp; | |
2374 | } | |
2375 | } | |
2376 | } | |
2377 | return 0; | |
2378 | } | |
2379 | ||
77c9c6c2 RK |
2380 | /* Generate code to perform an operation specified by UNOPTAB |
2381 | on operand OP0, with result having machine-mode MODE. | |
2382 | ||
2383 | UNSIGNEDP is for the case where we have to widen the operands | |
2384 | to perform the operation. It says to use zero-extension. | |
2385 | ||
2386 | If TARGET is nonzero, the value | |
2387 | is generated there, if it is convenient to do so. | |
2388 | In all cases an rtx is returned for the locus of the value; | |
2389 | this may or may not be TARGET. */ | |
2390 | ||
2391 | rtx | |
0c20a65f AJ |
2392 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, |
2393 | int unsignedp) | |
77c9c6c2 RK |
2394 | { |
2395 | enum mode_class class; | |
2396 | enum machine_mode wider_mode; | |
b3694847 | 2397 | rtx temp; |
77c9c6c2 RK |
2398 | rtx last = get_last_insn (); |
2399 | rtx pat; | |
2400 | ||
2401 | class = GET_MODE_CLASS (mode); | |
2402 | ||
2403 | op0 = protect_from_queue (op0, 0); | |
2404 | ||
2405 | if (flag_force_mem) | |
2406 | { | |
2407 | op0 = force_not_mem (op0); | |
2408 | } | |
2409 | ||
2410 | if (target) | |
2411 | target = protect_from_queue (target, 1); | |
2412 | ||
2413 | if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2414 | { | |
2415 | int icode = (int) unoptab->handlers[(int) mode].insn_code; | |
a995e389 | 2416 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 RK |
2417 | rtx xop0 = op0; |
2418 | ||
2419 | if (target) | |
2420 | temp = target; | |
2421 | else | |
2422 | temp = gen_reg_rtx (mode); | |
2423 | ||
2424 | if (GET_MODE (xop0) != VOIDmode | |
2425 | && GET_MODE (xop0) != mode0) | |
2426 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2427 | ||
2428 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
2429 | ||
a995e389 | 2430 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
77c9c6c2 RK |
2431 | xop0 = copy_to_mode_reg (mode0, xop0); |
2432 | ||
a995e389 | 2433 | if (! (*insn_data[icode].operand[0].predicate) (temp, mode)) |
77c9c6c2 RK |
2434 | temp = gen_reg_rtx (mode); |
2435 | ||
2436 | pat = GEN_FCN (icode) (temp, xop0); | |
2437 | if (pat) | |
2438 | { | |
2f937369 | 2439 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
b1ec3c92 | 2440 | && ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX)) |
77c9c6c2 RK |
2441 | { |
2442 | delete_insns_since (last); | |
b1ec3c92 | 2443 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
77c9c6c2 RK |
2444 | } |
2445 | ||
2446 | emit_insn (pat); | |
0c20a65f | 2447 | |
77c9c6c2 RK |
2448 | return temp; |
2449 | } | |
2450 | else | |
2451 | delete_insns_since (last); | |
2452 | } | |
2453 | ||
9a856ec7 RK |
2454 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
2455 | ||
2928cd7a RH |
2456 | /* Widening clz needs special treatment. */ |
2457 | if (unoptab == clz_optab) | |
2458 | { | |
2459 | temp = widen_clz (mode, op0, target); | |
2460 | if (temp) | |
2461 | return temp; | |
2462 | else | |
2463 | goto try_libcall; | |
2464 | } | |
2465 | ||
9a856ec7 RK |
2466 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) |
2467 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2468 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2469 | { | |
2470 | if (unoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing) | |
2471 | { | |
2472 | rtx xop0 = op0; | |
2473 | ||
2474 | /* For certain operations, we need not actually extend | |
2475 | the narrow operand, as long as we will truncate the | |
835532b8 RK |
2476 | results to the same narrowness. */ |
2477 | ||
0661a3de | 2478 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
2479 | (unoptab == neg_optab |
2480 | || unoptab == one_cmpl_optab) | |
2481 | && class == MODE_INT); | |
0c20a65f | 2482 | |
b1ec3c92 CH |
2483 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
2484 | unsignedp); | |
9a856ec7 RK |
2485 | |
2486 | if (temp) | |
2487 | { | |
2488 | if (class != MODE_INT) | |
2489 | { | |
2490 | if (target == 0) | |
2491 | target = gen_reg_rtx (mode); | |
2492 | convert_move (target, temp, 0); | |
2493 | return target; | |
2494 | } | |
2495 | else | |
2496 | return gen_lowpart (mode, temp); | |
2497 | } | |
2498 | else | |
2499 | delete_insns_since (last); | |
2500 | } | |
2501 | } | |
2502 | ||
77c9c6c2 RK |
2503 | /* These can be done a word at a time. */ |
2504 | if (unoptab == one_cmpl_optab | |
2505 | && class == MODE_INT | |
2506 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
34e56753 | 2507 | && unoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 2508 | { |
bb93b973 | 2509 | int i; |
77c9c6c2 RK |
2510 | rtx insns; |
2511 | ||
2512 | if (target == 0 || target == op0) | |
2513 | target = gen_reg_rtx (mode); | |
2514 | ||
2515 | start_sequence (); | |
2516 | ||
2517 | /* Do the actual arithmetic. */ | |
2518 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
2519 | { | |
2520 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 2521 | rtx x = expand_unop (word_mode, unoptab, |
77c9c6c2 RK |
2522 | operand_subword_force (op0, i, mode), |
2523 | target_piece, unsignedp); | |
bb93b973 | 2524 | |
77c9c6c2 RK |
2525 | if (target_piece != x) |
2526 | emit_move_insn (target_piece, x); | |
2527 | } | |
2528 | ||
2529 | insns = get_insns (); | |
2530 | end_sequence (); | |
2531 | ||
b1ec3c92 | 2532 | emit_no_conflict_block (insns, target, op0, NULL_RTX, |
9e6a5703 JC |
2533 | gen_rtx_fmt_e (unoptab->code, mode, |
2534 | copy_rtx (op0))); | |
77c9c6c2 RK |
2535 | return target; |
2536 | } | |
2537 | ||
139e5e08 | 2538 | /* Open-code the complex negation operation. */ |
91ce572a | 2539 | else if (unoptab->code == NEG |
139e5e08 RS |
2540 | && (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT)) |
2541 | { | |
2542 | rtx target_piece; | |
2543 | rtx x; | |
2544 | rtx seq; | |
2545 | ||
f9da5064 | 2546 | /* Find the correct mode for the real and imaginary parts. */ |
27e58a70 | 2547 | enum machine_mode submode = GET_MODE_INNER (mode); |
139e5e08 RS |
2548 | |
2549 | if (submode == BLKmode) | |
2550 | abort (); | |
2551 | ||
2552 | if (target == 0) | |
2553 | target = gen_reg_rtx (mode); | |
0c20a65f | 2554 | |
139e5e08 RS |
2555 | start_sequence (); |
2556 | ||
decdfa82 | 2557 | target_piece = gen_imagpart (submode, target); |
139e5e08 | 2558 | x = expand_unop (submode, unoptab, |
decdfa82 | 2559 | gen_imagpart (submode, op0), |
139e5e08 RS |
2560 | target_piece, unsignedp); |
2561 | if (target_piece != x) | |
2562 | emit_move_insn (target_piece, x); | |
2563 | ||
decdfa82 | 2564 | target_piece = gen_realpart (submode, target); |
139e5e08 | 2565 | x = expand_unop (submode, unoptab, |
decdfa82 | 2566 | gen_realpart (submode, op0), |
139e5e08 RS |
2567 | target_piece, unsignedp); |
2568 | if (target_piece != x) | |
2569 | emit_move_insn (target_piece, x); | |
2570 | ||
a29b481b | 2571 | seq = get_insns (); |
139e5e08 RS |
2572 | end_sequence (); |
2573 | ||
2574 | emit_no_conflict_block (seq, target, op0, 0, | |
9e6a5703 JC |
2575 | gen_rtx_fmt_e (unoptab->code, mode, |
2576 | copy_rtx (op0))); | |
139e5e08 RS |
2577 | return target; |
2578 | } | |
2579 | ||
4977bab6 ZW |
2580 | /* Try negating floating point values by flipping the sign bit. */ |
2581 | if (unoptab->code == NEG && class == MODE_FLOAT | |
2582 | && GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT) | |
2583 | { | |
2584 | const struct real_format *fmt = real_format_for_mode[mode - QFmode]; | |
2585 | enum machine_mode imode = int_mode_for_mode (mode); | |
2586 | int bitpos = (fmt != 0) ? fmt->signbit : -1; | |
2587 | ||
2588 | if (imode != BLKmode && bitpos >= 0 && fmt->has_signed_zero) | |
2589 | { | |
2590 | HOST_WIDE_INT hi, lo; | |
2591 | rtx last = get_last_insn (); | |
2592 | ||
9ee0a442 RS |
2593 | /* Handle targets with different FP word orders. */ |
2594 | if (FLOAT_WORDS_BIG_ENDIAN != WORDS_BIG_ENDIAN) | |
2595 | { | |
2596 | int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
2597 | int word = nwords - (bitpos / BITS_PER_WORD) - 1; | |
2598 | bitpos = word * BITS_PER_WORD + bitpos % BITS_PER_WORD; | |
2599 | } | |
2600 | ||
4977bab6 ZW |
2601 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
2602 | { | |
2603 | hi = 0; | |
2604 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2605 | } | |
2606 | else | |
2607 | { | |
2608 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
2609 | lo = 0; | |
2610 | } | |
2611 | temp = expand_binop (imode, xor_optab, | |
2612 | gen_lowpart (imode, op0), | |
2613 | immed_double_const (lo, hi, imode), | |
2614 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
2615 | if (temp != 0) | |
2616 | return gen_lowpart (mode, temp); | |
2617 | delete_insns_since (last); | |
2618 | } | |
2619 | } | |
2620 | ||
2928cd7a RH |
2621 | /* Try calculating parity (x) as popcount (x) % 2. */ |
2622 | if (unoptab == parity_optab) | |
2623 | { | |
2624 | temp = expand_parity (mode, op0, target); | |
2625 | if (temp) | |
2626 | return temp; | |
2627 | } | |
2628 | ||
2629 | try_libcall: | |
139e5e08 | 2630 | /* Now try a library call in this mode. */ |
77c9c6c2 RK |
2631 | if (unoptab->handlers[(int) mode].libfunc) |
2632 | { | |
2633 | rtx insns; | |
9a7f678c | 2634 | rtx value; |
2928cd7a RH |
2635 | enum machine_mode outmode = mode; |
2636 | ||
2637 | /* All of these functions return small values. Thus we choose to | |
2638 | have them return something that isn't a double-word. */ | |
2639 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
2640 | || unoptab == popcount_optab || unoptab == parity_optab) | |
dabb3f04 | 2641 | outmode = TYPE_MODE (integer_type_node); |
77c9c6c2 RK |
2642 | |
2643 | start_sequence (); | |
2644 | ||
2645 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
2646 | if the libcall is cse'd or moved. */ | |
9a7f678c | 2647 | value = emit_library_call_value (unoptab->handlers[(int) mode].libfunc, |
2928cd7a RH |
2648 | NULL_RTX, LCT_CONST, outmode, |
2649 | 1, op0, mode); | |
77c9c6c2 RK |
2650 | insns = get_insns (); |
2651 | end_sequence (); | |
2652 | ||
2928cd7a | 2653 | target = gen_reg_rtx (outmode); |
9a7f678c | 2654 | emit_libcall_block (insns, target, value, |
9e6a5703 | 2655 | gen_rtx_fmt_e (unoptab->code, mode, op0)); |
77c9c6c2 RK |
2656 | |
2657 | return target; | |
2658 | } | |
2659 | ||
cb2a532e AH |
2660 | if (class == MODE_VECTOR_FLOAT || class == MODE_VECTOR_INT) |
2661 | return expand_vector_unop (mode, unoptab, op0, target, unsignedp); | |
2662 | ||
77c9c6c2 RK |
2663 | /* It can't be done in this mode. Can we do it in a wider mode? */ |
2664 | ||
2665 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2666 | { | |
34e56753 | 2667 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
2668 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2669 | { | |
2670 | if ((unoptab->handlers[(int) wider_mode].insn_code | |
2671 | != CODE_FOR_nothing) | |
2672 | || unoptab->handlers[(int) wider_mode].libfunc) | |
2673 | { | |
34e56753 RS |
2674 | rtx xop0 = op0; |
2675 | ||
2676 | /* For certain operations, we need not actually extend | |
2677 | the narrow operand, as long as we will truncate the | |
2678 | results to the same narrowness. */ | |
2679 | ||
0661a3de | 2680 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
2681 | (unoptab == neg_optab |
2682 | || unoptab == one_cmpl_optab) | |
2683 | && class == MODE_INT); | |
0c20a65f | 2684 | |
b1ec3c92 CH |
2685 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
2686 | unsignedp); | |
34e56753 | 2687 | |
c117dddc KH |
2688 | /* If we are generating clz using wider mode, adjust the |
2689 | result. */ | |
2690 | if (unoptab == clz_optab && temp != 0) | |
2691 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2692 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2693 | - GET_MODE_BITSIZE (mode)), | |
2694 | target, true, OPTAB_DIRECT); | |
2695 | ||
34e56753 | 2696 | if (temp) |
77c9c6c2 | 2697 | { |
34e56753 RS |
2698 | if (class != MODE_INT) |
2699 | { | |
2700 | if (target == 0) | |
2701 | target = gen_reg_rtx (mode); | |
2702 | convert_move (target, temp, 0); | |
2703 | return target; | |
2704 | } | |
2705 | else | |
2706 | return gen_lowpart (mode, temp); | |
77c9c6c2 RK |
2707 | } |
2708 | else | |
34e56753 | 2709 | delete_insns_since (last); |
77c9c6c2 RK |
2710 | } |
2711 | } | |
2712 | } | |
2713 | ||
b82b6eea DE |
2714 | /* If there is no negate operation, try doing a subtract from zero. |
2715 | The US Software GOFAST library needs this. */ | |
91ce572a | 2716 | if (unoptab->code == NEG) |
0c20a65f | 2717 | { |
b82b6eea | 2718 | rtx temp; |
91ce572a CC |
2719 | temp = expand_binop (mode, |
2720 | unoptab == negv_optab ? subv_optab : sub_optab, | |
2721 | CONST0_RTX (mode), op0, | |
2722 | target, unsignedp, OPTAB_LIB_WIDEN); | |
b82b6eea DE |
2723 | if (temp) |
2724 | return temp; | |
2725 | } | |
0c20a65f | 2726 | |
77c9c6c2 RK |
2727 | return 0; |
2728 | } | |
2729 | \f | |
decdfa82 RS |
2730 | /* Emit code to compute the absolute value of OP0, with result to |
2731 | TARGET if convenient. (TARGET may be 0.) The return value says | |
2732 | where the result actually is to be found. | |
2733 | ||
2734 | MODE is the mode of the operand; the mode of the result is | |
2735 | different but can be deduced from MODE. | |
2736 | ||
91813b28 | 2737 | */ |
7fd01431 RK |
2738 | |
2739 | rtx | |
0c20a65f AJ |
2740 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
2741 | int result_unsignedp) | |
7fd01431 | 2742 | { |
2ef0a555 | 2743 | rtx temp; |
7fd01431 | 2744 | |
91ce572a CC |
2745 | if (! flag_trapv) |
2746 | result_unsignedp = 1; | |
2747 | ||
7fd01431 | 2748 | /* First try to do it with a special abs instruction. */ |
91ce572a CC |
2749 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
2750 | op0, target, 0); | |
7fd01431 RK |
2751 | if (temp != 0) |
2752 | return temp; | |
2753 | ||
4977bab6 ZW |
2754 | /* For floating point modes, try clearing the sign bit. */ |
2755 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2756 | && GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT) | |
2757 | { | |
2758 | const struct real_format *fmt = real_format_for_mode[mode - QFmode]; | |
2759 | enum machine_mode imode = int_mode_for_mode (mode); | |
2760 | int bitpos = (fmt != 0) ? fmt->signbit : -1; | |
2761 | ||
2762 | if (imode != BLKmode && bitpos >= 0) | |
2763 | { | |
2764 | HOST_WIDE_INT hi, lo; | |
2765 | rtx last = get_last_insn (); | |
2766 | ||
9ee0a442 RS |
2767 | /* Handle targets with different FP word orders. */ |
2768 | if (FLOAT_WORDS_BIG_ENDIAN != WORDS_BIG_ENDIAN) | |
2769 | { | |
2770 | int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
2771 | int word = nwords - (bitpos / BITS_PER_WORD) - 1; | |
2772 | bitpos = word * BITS_PER_WORD + bitpos % BITS_PER_WORD; | |
2773 | } | |
2774 | ||
4977bab6 ZW |
2775 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
2776 | { | |
2777 | hi = 0; | |
2778 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2779 | } | |
2780 | else | |
2781 | { | |
2782 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
2783 | lo = 0; | |
2784 | } | |
2785 | temp = expand_binop (imode, and_optab, | |
2786 | gen_lowpart (imode, op0), | |
2787 | immed_double_const (~lo, ~hi, imode), | |
2788 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
2789 | if (temp != 0) | |
2790 | return gen_lowpart (mode, temp); | |
2791 | delete_insns_since (last); | |
2792 | } | |
2793 | } | |
2794 | ||
14a774a9 RK |
2795 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
2796 | if (smax_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2797 | { | |
2798 | rtx last = get_last_insn (); | |
2799 | ||
2800 | temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); | |
2801 | if (temp != 0) | |
2802 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
2803 | OPTAB_WIDEN); | |
2804 | ||
2805 | if (temp != 0) | |
2806 | return temp; | |
2807 | ||
2808 | delete_insns_since (last); | |
2809 | } | |
2810 | ||
7fd01431 RK |
2811 | /* If this machine has expensive jumps, we can do integer absolute |
2812 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
e1078cfc | 2813 | where W is the width of MODE. */ |
7fd01431 RK |
2814 | |
2815 | if (GET_MODE_CLASS (mode) == MODE_INT && BRANCH_COST >= 2) | |
2816 | { | |
2817 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
2818 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
2819 | NULL_RTX, 0); | |
2820 | ||
2821 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
2822 | OPTAB_LIB_WIDEN); | |
2823 | if (temp != 0) | |
91ce572a CC |
2824 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
2825 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
7fd01431 RK |
2826 | |
2827 | if (temp != 0) | |
2828 | return temp; | |
2829 | } | |
2830 | ||
2ef0a555 RH |
2831 | return NULL_RTX; |
2832 | } | |
2833 | ||
2834 | rtx | |
0c20a65f AJ |
2835 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
2836 | int result_unsignedp, int safe) | |
2ef0a555 RH |
2837 | { |
2838 | rtx temp, op1; | |
2839 | ||
77173bbe KH |
2840 | if (! flag_trapv) |
2841 | result_unsignedp = 1; | |
2842 | ||
2ef0a555 RH |
2843 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
2844 | if (temp != 0) | |
2845 | return temp; | |
2846 | ||
7fd01431 | 2847 | /* If that does not win, use conditional jump and negate. */ |
5c0bf747 RK |
2848 | |
2849 | /* It is safe to use the target if it is the same | |
2850 | as the source if this is also a pseudo register */ | |
2851 | if (op0 == target && GET_CODE (op0) == REG | |
2852 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) | |
2853 | safe = 1; | |
2854 | ||
7fd01431 RK |
2855 | op1 = gen_label_rtx (); |
2856 | if (target == 0 || ! safe | |
2857 | || GET_MODE (target) != mode | |
2858 | || (GET_CODE (target) == MEM && MEM_VOLATILE_P (target)) | |
2859 | || (GET_CODE (target) == REG | |
2860 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) | |
2861 | target = gen_reg_rtx (mode); | |
2862 | ||
2863 | emit_move_insn (target, op0); | |
2864 | NO_DEFER_POP; | |
2865 | ||
2866 | /* If this mode is an integer too wide to compare properly, | |
2867 | compare word by word. Rely on CSE to optimize constant cases. */ | |
1eb8759b RH |
2868 | if (GET_MODE_CLASS (mode) == MODE_INT |
2869 | && ! can_compare_p (GE, mode, ccp_jump)) | |
0c20a65f | 2870 | do_jump_by_parts_greater_rtx (mode, 0, target, const0_rtx, |
7fd01431 RK |
2871 | NULL_RTX, op1); |
2872 | else | |
b30f05db | 2873 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
a06ef755 | 2874 | NULL_RTX, NULL_RTX, op1); |
7fd01431 | 2875 | |
91ce572a CC |
2876 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
2877 | target, target, 0); | |
7fd01431 RK |
2878 | if (op0 != target) |
2879 | emit_move_insn (target, op0); | |
2880 | emit_label (op1); | |
2881 | OK_DEFER_POP; | |
2882 | return target; | |
2883 | } | |
2884 | \f | |
2885 | /* Emit code to compute the absolute value of OP0, with result to | |
2886 | TARGET if convenient. (TARGET may be 0.) The return value says | |
2887 | where the result actually is to be found. | |
2888 | ||
2889 | MODE is the mode of the operand; the mode of the result is | |
2890 | different but can be deduced from MODE. | |
2891 | ||
decdfa82 RS |
2892 | UNSIGNEDP is relevant for complex integer modes. */ |
2893 | ||
2894 | rtx | |
0c20a65f AJ |
2895 | expand_complex_abs (enum machine_mode mode, rtx op0, rtx target, |
2896 | int unsignedp) | |
decdfa82 RS |
2897 | { |
2898 | enum mode_class class = GET_MODE_CLASS (mode); | |
2899 | enum machine_mode wider_mode; | |
b3694847 | 2900 | rtx temp; |
abd418d3 RS |
2901 | rtx entry_last = get_last_insn (); |
2902 | rtx last; | |
decdfa82 | 2903 | rtx pat; |
91ce572a | 2904 | optab this_abs_optab; |
decdfa82 RS |
2905 | |
2906 | /* Find the correct mode for the real and imaginary parts. */ | |
27e58a70 | 2907 | enum machine_mode submode = GET_MODE_INNER (mode); |
decdfa82 RS |
2908 | |
2909 | if (submode == BLKmode) | |
2910 | abort (); | |
2911 | ||
2912 | op0 = protect_from_queue (op0, 0); | |
2913 | ||
2914 | if (flag_force_mem) | |
2915 | { | |
2916 | op0 = force_not_mem (op0); | |
2917 | } | |
2918 | ||
abd418d3 RS |
2919 | last = get_last_insn (); |
2920 | ||
decdfa82 RS |
2921 | if (target) |
2922 | target = protect_from_queue (target, 1); | |
2923 | ||
91ce572a CC |
2924 | this_abs_optab = ! unsignedp && flag_trapv |
2925 | && (GET_MODE_CLASS(mode) == MODE_INT) | |
2926 | ? absv_optab : abs_optab; | |
2927 | ||
2928 | if (this_abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
decdfa82 | 2929 | { |
91ce572a | 2930 | int icode = (int) this_abs_optab->handlers[(int) mode].insn_code; |
a995e389 | 2931 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
decdfa82 RS |
2932 | rtx xop0 = op0; |
2933 | ||
2934 | if (target) | |
2935 | temp = target; | |
2936 | else | |
2937 | temp = gen_reg_rtx (submode); | |
2938 | ||
2939 | if (GET_MODE (xop0) != VOIDmode | |
2940 | && GET_MODE (xop0) != mode0) | |
2941 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2942 | ||
2943 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
2944 | ||
a995e389 | 2945 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
decdfa82 RS |
2946 | xop0 = copy_to_mode_reg (mode0, xop0); |
2947 | ||
a995e389 | 2948 | if (! (*insn_data[icode].operand[0].predicate) (temp, submode)) |
decdfa82 RS |
2949 | temp = gen_reg_rtx (submode); |
2950 | ||
2951 | pat = GEN_FCN (icode) (temp, xop0); | |
2952 | if (pat) | |
2953 | { | |
2f937369 | 2954 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
0c20a65f | 2955 | && ! add_equal_note (pat, temp, this_abs_optab->code, xop0, |
91ce572a | 2956 | NULL_RTX)) |
decdfa82 RS |
2957 | { |
2958 | delete_insns_since (last); | |
0c20a65f | 2959 | return expand_unop (mode, this_abs_optab, op0, NULL_RTX, |
91ce572a | 2960 | unsignedp); |
decdfa82 RS |
2961 | } |
2962 | ||
2963 | emit_insn (pat); | |
0c20a65f | 2964 | |
decdfa82 RS |
2965 | return temp; |
2966 | } | |
2967 | else | |
2968 | delete_insns_since (last); | |
2969 | } | |
2970 | ||
2971 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ | |
2972 | ||
2973 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2974 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2975 | { | |
0c20a65f | 2976 | if (this_abs_optab->handlers[(int) wider_mode].insn_code |
91ce572a | 2977 | != CODE_FOR_nothing) |
decdfa82 RS |
2978 | { |
2979 | rtx xop0 = op0; | |
2980 | ||
0661a3de | 2981 | xop0 = convert_modes (wider_mode, mode, xop0, unsignedp); |
decdfa82 RS |
2982 | temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); |
2983 | ||
2984 | if (temp) | |
2985 | { | |
2986 | if (class != MODE_COMPLEX_INT) | |
2987 | { | |
2988 | if (target == 0) | |
2989 | target = gen_reg_rtx (submode); | |
2990 | convert_move (target, temp, 0); | |
2991 | return target; | |
2992 | } | |
2993 | else | |
2994 | return gen_lowpart (submode, temp); | |
2995 | } | |
2996 | else | |
2997 | delete_insns_since (last); | |
2998 | } | |
2999 | } | |
3000 | ||
3001 | /* Open-code the complex absolute-value operation | |
3002 | if we can open-code sqrt. Otherwise it's not worth while. */ | |
10e927ef CC |
3003 | if (sqrt_optab->handlers[(int) submode].insn_code != CODE_FOR_nothing |
3004 | && ! flag_trapv) | |
decdfa82 RS |
3005 | { |
3006 | rtx real, imag, total; | |
3007 | ||
3008 | real = gen_realpart (submode, op0); | |
3009 | imag = gen_imagpart (submode, op0); | |
9061e4cd | 3010 | |
decdfa82 | 3011 | /* Square both parts. */ |
9061e4cd RK |
3012 | real = expand_mult (submode, real, real, NULL_RTX, 0); |
3013 | imag = expand_mult (submode, imag, imag, NULL_RTX, 0); | |
3014 | ||
decdfa82 | 3015 | /* Sum the parts. */ |
73d9a835 | 3016 | total = expand_binop (submode, add_optab, real, imag, NULL_RTX, |
decdfa82 | 3017 | 0, OPTAB_LIB_WIDEN); |
9061e4cd | 3018 | |
decdfa82 RS |
3019 | /* Get sqrt in TARGET. Set TARGET to where the result is. */ |
3020 | target = expand_unop (submode, sqrt_optab, total, target, 0); | |
3021 | if (target == 0) | |
3022 | delete_insns_since (last); | |
3023 | else | |
3024 | return target; | |
3025 | } | |
3026 | ||
3027 | /* Now try a library call in this mode. */ | |
91ce572a | 3028 | if (this_abs_optab->handlers[(int) mode].libfunc) |
decdfa82 RS |
3029 | { |
3030 | rtx insns; | |
a0bc0933 | 3031 | rtx value; |
decdfa82 RS |
3032 | |
3033 | start_sequence (); | |
3034 | ||
3035 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3036 | if the libcall is cse'd or moved. */ | |
9a7f678c | 3037 | value = emit_library_call_value (abs_optab->handlers[(int) mode].libfunc, |
ebb1b59a | 3038 | NULL_RTX, LCT_CONST, submode, 1, op0, mode); |
decdfa82 RS |
3039 | insns = get_insns (); |
3040 | end_sequence (); | |
3041 | ||
3042 | target = gen_reg_rtx (submode); | |
9a7f678c | 3043 | emit_libcall_block (insns, target, value, |
91ce572a | 3044 | gen_rtx_fmt_e (this_abs_optab->code, mode, op0)); |
decdfa82 RS |
3045 | |
3046 | return target; | |
3047 | } | |
3048 | ||
3049 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3050 | ||
3051 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
3052 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
3053 | { | |
91ce572a | 3054 | if ((this_abs_optab->handlers[(int) wider_mode].insn_code |
decdfa82 | 3055 | != CODE_FOR_nothing) |
91ce572a | 3056 | || this_abs_optab->handlers[(int) wider_mode].libfunc) |
decdfa82 RS |
3057 | { |
3058 | rtx xop0 = op0; | |
3059 | ||
0661a3de | 3060 | xop0 = convert_modes (wider_mode, mode, xop0, unsignedp); |
decdfa82 RS |
3061 | |
3062 | temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); | |
3063 | ||
3064 | if (temp) | |
3065 | { | |
3066 | if (class != MODE_COMPLEX_INT) | |
3067 | { | |
3068 | if (target == 0) | |
3069 | target = gen_reg_rtx (submode); | |
3070 | convert_move (target, temp, 0); | |
3071 | return target; | |
3072 | } | |
3073 | else | |
3074 | return gen_lowpart (submode, temp); | |
3075 | } | |
3076 | else | |
3077 | delete_insns_since (last); | |
3078 | } | |
3079 | } | |
3080 | ||
abd418d3 | 3081 | delete_insns_since (entry_last); |
decdfa82 RS |
3082 | return 0; |
3083 | } | |
3084 | \f | |
77c9c6c2 RK |
3085 | /* Generate an instruction whose insn-code is INSN_CODE, |
3086 | with two operands: an output TARGET and an input OP0. | |
3087 | TARGET *must* be nonzero, and the output is always stored there. | |
3088 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3089 | the value that is stored into TARGET. */ | |
3090 | ||
3091 | void | |
0c20a65f | 3092 | emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) |
77c9c6c2 | 3093 | { |
b3694847 | 3094 | rtx temp; |
a995e389 | 3095 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 RK |
3096 | rtx pat; |
3097 | ||
3098 | temp = target = protect_from_queue (target, 1); | |
3099 | ||
3100 | op0 = protect_from_queue (op0, 0); | |
3101 | ||
bd8c4b14 ILT |
3102 | /* Sign and zero extension from memory is often done specially on |
3103 | RISC machines, so forcing into a register here can pessimize | |
3104 | code. */ | |
3105 | if (flag_force_mem && code != SIGN_EXTEND && code != ZERO_EXTEND) | |
77c9c6c2 RK |
3106 | op0 = force_not_mem (op0); |
3107 | ||
3108 | /* Now, if insn does not accept our operands, put them into pseudos. */ | |
3109 | ||
a995e389 | 3110 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
77c9c6c2 RK |
3111 | op0 = copy_to_mode_reg (mode0, op0); |
3112 | ||
a995e389 | 3113 | if (! (*insn_data[icode].operand[0].predicate) (temp, GET_MODE (temp)) |
77c9c6c2 RK |
3114 | || (flag_force_mem && GET_CODE (temp) == MEM)) |
3115 | temp = gen_reg_rtx (GET_MODE (temp)); | |
3116 | ||
3117 | pat = GEN_FCN (icode) (temp, op0); | |
3118 | ||
2f937369 | 3119 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
b1ec3c92 | 3120 | add_equal_note (pat, temp, code, op0, NULL_RTX); |
0c20a65f | 3121 | |
77c9c6c2 RK |
3122 | emit_insn (pat); |
3123 | ||
3124 | if (temp != target) | |
3125 | emit_move_insn (target, temp); | |
3126 | } | |
3127 | \f | |
3128 | /* Emit code to perform a series of operations on a multi-word quantity, one | |
3129 | word at a time. | |
3130 | ||
d45cf215 | 3131 | Such a block is preceded by a CLOBBER of the output, consists of multiple |
77c9c6c2 RK |
3132 | insns, each setting one word of the output, and followed by a SET copying |
3133 | the output to itself. | |
3134 | ||
3135 | Each of the insns setting words of the output receives a REG_NO_CONFLICT | |
3136 | note indicating that it doesn't conflict with the (also multi-word) | |
3137 | inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL | |
3138 | notes. | |
3139 | ||
3140 | INSNS is a block of code generated to perform the operation, not including | |
3141 | the CLOBBER and final copy. All insns that compute intermediate values | |
0c20a65f | 3142 | are first emitted, followed by the block as described above. |
77c9c6c2 RK |
3143 | |
3144 | TARGET, OP0, and OP1 are the output and inputs of the operations, | |
3145 | respectively. OP1 may be zero for a unary operation. | |
3146 | ||
40f03658 | 3147 | EQUIV, if nonzero, is an expression to be placed into a REG_EQUAL note |
77c9c6c2 RK |
3148 | on the last insn. |
3149 | ||
3150 | If TARGET is not a register, INSNS is simply emitted with no special | |
dce39da6 RK |
3151 | processing. Likewise if anything in INSNS is not an INSN or if |
3152 | there is a libcall block inside INSNS. | |
77c9c6c2 RK |
3153 | |
3154 | The final insn emitted is returned. */ | |
3155 | ||
3156 | rtx | |
0c20a65f | 3157 | emit_no_conflict_block (rtx insns, rtx target, rtx op0, rtx op1, rtx equiv) |
77c9c6c2 RK |
3158 | { |
3159 | rtx prev, next, first, last, insn; | |
3160 | ||
3161 | if (GET_CODE (target) != REG || reload_in_progress) | |
2f937369 | 3162 | return emit_insn (insns); |
dce39da6 RK |
3163 | else |
3164 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
3165 | if (GET_CODE (insn) != INSN | |
3166 | || find_reg_note (insn, REG_LIBCALL, NULL_RTX)) | |
2f937369 | 3167 | return emit_insn (insns); |
77c9c6c2 RK |
3168 | |
3169 | /* First emit all insns that do not store into words of the output and remove | |
3170 | these from the list. */ | |
3171 | for (insn = insns; insn; insn = next) | |
3172 | { | |
218aa620 | 3173 | rtx set = 0, note; |
77c9c6c2 RK |
3174 | int i; |
3175 | ||
3176 | next = NEXT_INSN (insn); | |
3177 | ||
218aa620 JH |
3178 | /* Some ports (cris) create an libcall regions at their own. We must |
3179 | avoid any potential nesting of LIBCALLs. */ | |
3180 | if ((note = find_reg_note (insn, REG_LIBCALL, NULL)) != NULL) | |
3181 | remove_note (insn, note); | |
3182 | if ((note = find_reg_note (insn, REG_RETVAL, NULL)) != NULL) | |
3183 | remove_note (insn, note); | |
3184 | ||
c5c76735 JL |
3185 | if (GET_CODE (PATTERN (insn)) == SET || GET_CODE (PATTERN (insn)) == USE |
3186 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
77c9c6c2 RK |
3187 | set = PATTERN (insn); |
3188 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
3189 | { | |
3190 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
3191 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET) | |
3192 | { | |
3193 | set = XVECEXP (PATTERN (insn), 0, i); | |
3194 | break; | |
3195 | } | |
3196 | } | |
3197 | ||
3198 | if (set == 0) | |
3199 | abort (); | |
3200 | ||
3201 | if (! reg_overlap_mentioned_p (target, SET_DEST (set))) | |
3202 | { | |
3203 | if (PREV_INSN (insn)) | |
3204 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3205 | else | |
3206 | insns = next; | |
3207 | ||
3208 | if (next) | |
3209 | PREV_INSN (next) = PREV_INSN (insn); | |
3210 | ||
3211 | add_insn (insn); | |
3212 | } | |
3213 | } | |
3214 | ||
3215 | prev = get_last_insn (); | |
3216 | ||
3217 | /* Now write the CLOBBER of the output, followed by the setting of each | |
3218 | of the words, followed by the final copy. */ | |
3219 | if (target != op0 && target != op1) | |
9e6a5703 | 3220 | emit_insn (gen_rtx_CLOBBER (VOIDmode, target)); |
77c9c6c2 RK |
3221 | |
3222 | for (insn = insns; insn; insn = next) | |
3223 | { | |
3224 | next = NEXT_INSN (insn); | |
3225 | add_insn (insn); | |
3226 | ||
3227 | if (op1 && GET_CODE (op1) == REG) | |
9e6a5703 JC |
3228 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op1, |
3229 | REG_NOTES (insn)); | |
77c9c6c2 RK |
3230 | |
3231 | if (op0 && GET_CODE (op0) == REG) | |
9e6a5703 JC |
3232 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op0, |
3233 | REG_NOTES (insn)); | |
77c9c6c2 RK |
3234 | } |
3235 | ||
54e7b5e6 RS |
3236 | if (mov_optab->handlers[(int) GET_MODE (target)].insn_code |
3237 | != CODE_FOR_nothing) | |
3238 | { | |
3239 | last = emit_move_insn (target, target); | |
3240 | if (equiv) | |
5fa671cf | 3241 | set_unique_reg_note (last, REG_EQUAL, equiv); |
54e7b5e6 RS |
3242 | } |
3243 | else | |
07edd4c5 HPN |
3244 | { |
3245 | last = get_last_insn (); | |
3246 | ||
3247 | /* Remove any existing REG_EQUAL note from "last", or else it will | |
3248 | be mistaken for a note referring to the full contents of the | |
3249 | alleged libcall value when found together with the REG_RETVAL | |
3250 | note added below. An existing note can come from an insn | |
3251 | expansion at "last". */ | |
3252 | remove_note (last, find_reg_note (last, REG_EQUAL, NULL_RTX)); | |
3253 | } | |
77c9c6c2 RK |
3254 | |
3255 | if (prev == 0) | |
3256 | first = get_insns (); | |
3257 | else | |
3258 | first = NEXT_INSN (prev); | |
3259 | ||
3260 | /* Encapsulate the block so it gets manipulated as a unit. */ | |
9e6a5703 JC |
3261 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, |
3262 | REG_NOTES (first)); | |
3263 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last)); | |
77c9c6c2 RK |
3264 | |
3265 | return last; | |
3266 | } | |
3267 | \f | |
3268 | /* Emit code to make a call to a constant function or a library call. | |
3269 | ||
3270 | INSNS is a list containing all insns emitted in the call. | |
3271 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3272 | to TARGET, which is logically equivalent to EQUIV. | |
3273 | ||
3274 | We first emit any insns that set a pseudo on the assumption that these are | |
3275 | loading constants into registers; doing so allows them to be safely cse'ed | |
3276 | between blocks. Then we emit all the other insns in the block, followed by | |
3277 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
3278 | note with an operand of EQUIV. | |
3279 | ||
29ebe69a RK |
3280 | Moving assignments to pseudos outside of the block is done to improve |
3281 | the generated code, but is not required to generate correct code, | |
3282 | hence being unable to move an assignment is not grounds for not making | |
3283 | a libcall block. There are two reasons why it is safe to leave these | |
3284 | insns inside the block: First, we know that these pseudos cannot be | |
3285 | used in generated RTL outside the block since they are created for | |
3286 | temporary purposes within the block. Second, CSE will not record the | |
3287 | values of anything set inside a libcall block, so we know they must | |
3288 | be dead at the end of the block. | |
3289 | ||
77c9c6c2 RK |
3290 | Except for the first group of insns (the ones setting pseudos), the |
3291 | block is delimited by REG_RETVAL and REG_LIBCALL notes. */ | |
3292 | ||
3293 | void | |
0c20a65f | 3294 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) |
77c9c6c2 | 3295 | { |
aff2c2d3 | 3296 | rtx final_dest = target; |
77c9c6c2 RK |
3297 | rtx prev, next, first, last, insn; |
3298 | ||
aff2c2d3 BS |
3299 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3300 | into a MEM later. Protect the libcall block from this change. */ | |
3301 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3302 | target = gen_reg_rtx (GET_MODE (target)); | |
0c20a65f | 3303 | |
5154e79a AH |
3304 | /* If we're using non-call exceptions, a libcall corresponding to an |
3305 | operation that may trap may also trap. */ | |
3306 | if (flag_non_call_exceptions && may_trap_p (equiv)) | |
3307 | { | |
3308 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
3309 | if (GET_CODE (insn) == CALL_INSN) | |
3310 | { | |
3311 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3312 | |
5154e79a AH |
3313 | if (note != 0 && INTVAL (XEXP (note, 0)) <= 0) |
3314 | remove_note (insn, note); | |
3315 | } | |
3316 | } | |
3317 | else | |
b472794d | 3318 | /* look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION |
c29ea88a | 3319 | reg note to indicate that this call cannot throw or execute a nonlocal |
cf67d231 | 3320 | goto (unless there is already a REG_EH_REGION note, in which case |
897aa57f | 3321 | we update it). */ |
5154e79a AH |
3322 | for (insn = insns; insn; insn = NEXT_INSN (insn)) |
3323 | if (GET_CODE (insn) == CALL_INSN) | |
3324 | { | |
3325 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3326 | |
5154e79a AH |
3327 | if (note != 0) |
3328 | XEXP (note, 0) = GEN_INT (-1); | |
3329 | else | |
3330 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EH_REGION, GEN_INT (-1), | |
3331 | REG_NOTES (insn)); | |
3332 | } | |
b472794d | 3333 | |
77c9c6c2 | 3334 | /* First emit all insns that set pseudos. Remove them from the list as |
ccf5f342 | 3335 | we go. Avoid insns that set pseudos which were referenced in previous |
29ebe69a | 3336 | insns. These can be generated by move_by_pieces, for example, |
ccf5f342 RK |
3337 | to update an address. Similarly, avoid insns that reference things |
3338 | set in previous insns. */ | |
77c9c6c2 RK |
3339 | |
3340 | for (insn = insns; insn; insn = next) | |
3341 | { | |
3342 | rtx set = single_set (insn); | |
218aa620 JH |
3343 | rtx note; |
3344 | ||
3345 | /* Some ports (cris) create an libcall regions at their own. We must | |
3346 | avoid any potential nesting of LIBCALLs. */ | |
3347 | if ((note = find_reg_note (insn, REG_LIBCALL, NULL)) != NULL) | |
3348 | remove_note (insn, note); | |
3349 | if ((note = find_reg_note (insn, REG_RETVAL, NULL)) != NULL) | |
3350 | remove_note (insn, note); | |
77c9c6c2 RK |
3351 | |
3352 | next = NEXT_INSN (insn); | |
3353 | ||
3354 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG | |
29ebe69a | 3355 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER |
8d9e73cc | 3356 | && (insn == insns |
9485c46e DM |
3357 | || ((! INSN_P(insns) |
3358 | || ! reg_mentioned_p (SET_DEST (set), PATTERN (insns))) | |
ccf5f342 RK |
3359 | && ! reg_used_between_p (SET_DEST (set), insns, insn) |
3360 | && ! modified_in_p (SET_SRC (set), insns) | |
3361 | && ! modified_between_p (SET_SRC (set), insns, insn)))) | |
77c9c6c2 RK |
3362 | { |
3363 | if (PREV_INSN (insn)) | |
3364 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3365 | else | |
3366 | insns = next; | |
3367 | ||
3368 | if (next) | |
3369 | PREV_INSN (next) = PREV_INSN (insn); | |
3370 | ||
3371 | add_insn (insn); | |
3372 | } | |
695a94b3 RS |
3373 | |
3374 | /* Some ports use a loop to copy large arguments onto the stack. | |
3375 | Don't move anything outside such a loop. */ | |
3376 | if (GET_CODE (insn) == CODE_LABEL) | |
3377 | break; | |
77c9c6c2 RK |
3378 | } |
3379 | ||
3380 | prev = get_last_insn (); | |
3381 | ||
3382 | /* Write the remaining insns followed by the final copy. */ | |
3383 | ||
3384 | for (insn = insns; insn; insn = next) | |
3385 | { | |
3386 | next = NEXT_INSN (insn); | |
3387 | ||
3388 | add_insn (insn); | |
3389 | } | |
3390 | ||
3391 | last = emit_move_insn (target, result); | |
02214a5c RK |
3392 | if (mov_optab->handlers[(int) GET_MODE (target)].insn_code |
3393 | != CODE_FOR_nothing) | |
5fa671cf | 3394 | set_unique_reg_note (last, REG_EQUAL, copy_rtx (equiv)); |
07edd4c5 HPN |
3395 | else |
3396 | { | |
3397 | /* Remove any existing REG_EQUAL note from "last", or else it will | |
3398 | be mistaken for a note referring to the full contents of the | |
3399 | libcall value when found together with the REG_RETVAL note added | |
3400 | below. An existing note can come from an insn expansion at | |
3401 | "last". */ | |
3402 | remove_note (last, find_reg_note (last, REG_EQUAL, NULL_RTX)); | |
3403 | } | |
77c9c6c2 | 3404 | |
e85427f9 BS |
3405 | if (final_dest != target) |
3406 | emit_move_insn (final_dest, target); | |
aff2c2d3 | 3407 | |
77c9c6c2 RK |
3408 | if (prev == 0) |
3409 | first = get_insns (); | |
3410 | else | |
3411 | first = NEXT_INSN (prev); | |
3412 | ||
3413 | /* Encapsulate the block so it gets manipulated as a unit. */ | |
11e9ecc5 HB |
3414 | if (!flag_non_call_exceptions || !may_trap_p (equiv)) |
3415 | { | |
4a69cf79 JZ |
3416 | /* We can't attach the REG_LIBCALL and REG_RETVAL notes |
3417 | when the encapsulated region would not be in one basic block, | |
3418 | i.e. when there is a control_flow_insn_p insn between FIRST and LAST. | |
3419 | */ | |
3420 | bool attach_libcall_retval_notes = true; | |
3421 | next = NEXT_INSN (last); | |
3422 | for (insn = first; insn != next; insn = NEXT_INSN (insn)) | |
3423 | if (control_flow_insn_p (insn)) | |
3424 | { | |
3425 | attach_libcall_retval_notes = false; | |
3426 | break; | |
3427 | } | |
3428 | ||
3429 | if (attach_libcall_retval_notes) | |
3430 | { | |
3431 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3432 | REG_NOTES (first)); | |
3433 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3434 | REG_NOTES (last)); | |
3435 | } | |
11e9ecc5 | 3436 | } |
77c9c6c2 RK |
3437 | } |
3438 | \f | |
3439 | /* Generate code to store zero in X. */ | |
3440 | ||
3441 | void | |
0c20a65f | 3442 | emit_clr_insn (rtx x) |
77c9c6c2 RK |
3443 | { |
3444 | emit_move_insn (x, const0_rtx); | |
3445 | } | |
3446 | ||
3447 | /* Generate code to store 1 in X | |
3448 | assuming it contains zero beforehand. */ | |
3449 | ||
3450 | void | |
0c20a65f | 3451 | emit_0_to_1_insn (rtx x) |
77c9c6c2 RK |
3452 | { |
3453 | emit_move_insn (x, const1_rtx); | |
3454 | } | |
3455 | ||
1c0290ea | 3456 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
1eb8759b RH |
3457 | PURPOSE describes how this comparison will be used. CODE is the rtx |
3458 | comparison code we will be using. | |
3459 | ||
3460 | ??? Actually, CODE is slightly weaker than that. A target is still | |
0c20a65f | 3461 | required to implement all of the normal bcc operations, but not |
1eb8759b | 3462 | required to implement all (or any) of the unordered bcc operations. */ |
0c20a65f | 3463 | |
1c0290ea | 3464 | int |
0c20a65f AJ |
3465 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
3466 | enum can_compare_purpose purpose) | |
b30f05db BS |
3467 | { |
3468 | do | |
3469 | { | |
7e1a450d | 3470 | if (cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1eb8759b RH |
3471 | { |
3472 | if (purpose == ccp_jump) | |
7e1a450d | 3473 | return bcc_gen_fctn[(int) code] != NULL; |
1eb8759b | 3474 | else if (purpose == ccp_store_flag) |
7e1a450d | 3475 | return setcc_gen_code[(int) code] != CODE_FOR_nothing; |
1eb8759b RH |
3476 | else |
3477 | /* There's only one cmov entry point, and it's allowed to fail. */ | |
3478 | return 1; | |
3479 | } | |
1c0290ea | 3480 | if (purpose == ccp_jump |
7e1a450d | 3481 | && cbranch_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3482 | return 1; |
3483 | if (purpose == ccp_cmov | |
7e1a450d | 3484 | && cmov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3485 | return 1; |
3486 | if (purpose == ccp_store_flag | |
7e1a450d | 3487 | && cstore_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3488 | return 1; |
3489 | ||
b30f05db | 3490 | mode = GET_MODE_WIDER_MODE (mode); |
1c0290ea BS |
3491 | } |
3492 | while (mode != VOIDmode); | |
b30f05db BS |
3493 | |
3494 | return 0; | |
3495 | } | |
3496 | ||
3497 | /* This function is called when we are going to emit a compare instruction that | |
3498 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
3499 | ||
3500 | *PMODE is the mode of the inputs (in case they are const_int). | |
3501 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
77c9c6c2 RK |
3502 | this matters if they need to be widened. |
3503 | ||
a06ef755 | 3504 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
77c9c6c2 | 3505 | |
b30f05db BS |
3506 | This function performs all the setup necessary so that the caller only has |
3507 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
3508 | comparison or emitting a library call to perform the comparison if no insn | |
3509 | is available to handle it. | |
3510 | The values which are passed in through pointers can be modified; the caller | |
3511 | should perform the comparison on the modified values. */ | |
77c9c6c2 | 3512 | |
a06ef755 | 3513 | static void |
0c20a65f AJ |
3514 | prepare_cmp_insn (rtx *px, rtx *py, enum rtx_code *pcomparison, rtx size, |
3515 | enum machine_mode *pmode, int *punsignedp, | |
3516 | enum can_compare_purpose purpose) | |
77c9c6c2 | 3517 | { |
b30f05db BS |
3518 | enum machine_mode mode = *pmode; |
3519 | rtx x = *px, y = *py; | |
3520 | int unsignedp = *punsignedp; | |
77c9c6c2 | 3521 | enum mode_class class; |
77c9c6c2 RK |
3522 | |
3523 | class = GET_MODE_CLASS (mode); | |
3524 | ||
3525 | /* They could both be VOIDmode if both args are immediate constants, | |
3526 | but we should fold that at an earlier stage. | |
3527 | With no special code here, this will call abort, | |
3528 | reminding the programmer to implement such folding. */ | |
3529 | ||
3530 | if (mode != BLKmode && flag_force_mem) | |
3531 | { | |
894207cf RS |
3532 | /* Load duplicate non-volatile operands once. */ |
3533 | if (rtx_equal_p (x, y) && ! volatile_refs_p (x)) | |
3534 | { | |
3535 | x = force_not_mem (x); | |
3536 | y = x; | |
3537 | } | |
3538 | else | |
3539 | { | |
3540 | x = force_not_mem (x); | |
3541 | y = force_not_mem (y); | |
3542 | } | |
77c9c6c2 RK |
3543 | } |
3544 | ||
3545 | /* If we are inside an appropriately-short loop and one operand is an | |
3546 | expensive constant, force it into a register. */ | |
19caa751 | 3547 | if (CONSTANT_P (x) && preserve_subexpressions_p () |
b437f1a7 | 3548 | && rtx_cost (x, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
3549 | x = force_reg (mode, x); |
3550 | ||
19caa751 | 3551 | if (CONSTANT_P (y) && preserve_subexpressions_p () |
b437f1a7 | 3552 | && rtx_cost (y, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
3553 | y = force_reg (mode, y); |
3554 | ||
362cc3d4 MH |
3555 | #ifdef HAVE_cc0 |
3556 | /* Abort if we have a non-canonical comparison. The RTL documentation | |
3557 | states that canonical comparisons are required only for targets which | |
3558 | have cc0. */ | |
3559 | if (CONSTANT_P (x) && ! CONSTANT_P (y)) | |
7e1a450d | 3560 | abort (); |
362cc3d4 MH |
3561 | #endif |
3562 | ||
77c9c6c2 RK |
3563 | /* Don't let both operands fail to indicate the mode. */ |
3564 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
3565 | x = force_reg (mode, x); | |
3566 | ||
3567 | /* Handle all BLKmode compares. */ | |
3568 | ||
3569 | if (mode == BLKmode) | |
3570 | { | |
b30f05db BS |
3571 | rtx result; |
3572 | enum machine_mode result_mode; | |
f4dc10d1 GS |
3573 | rtx opalign ATTRIBUTE_UNUSED |
3574 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); | |
b30f05db | 3575 | |
77c9c6c2 RK |
3576 | emit_queue (); |
3577 | x = protect_from_queue (x, 0); | |
3578 | y = protect_from_queue (y, 0); | |
3579 | ||
3580 | if (size == 0) | |
3581 | abort (); | |
358b8f01 JJ |
3582 | #ifdef HAVE_cmpmemqi |
3583 | if (HAVE_cmpmemqi | |
3584 | && GET_CODE (size) == CONST_INT | |
3585 | && INTVAL (size) < (1 << GET_MODE_BITSIZE (QImode))) | |
3586 | { | |
3587 | result_mode = insn_data[(int) CODE_FOR_cmpmemqi].operand[0].mode; | |
3588 | result = gen_reg_rtx (result_mode); | |
3589 | emit_insn (gen_cmpmemqi (result, x, y, size, opalign)); | |
3590 | } | |
3591 | else | |
3592 | #endif | |
3593 | #ifdef HAVE_cmpmemhi | |
3594 | if (HAVE_cmpmemhi | |
3595 | && GET_CODE (size) == CONST_INT | |
3596 | && INTVAL (size) < (1 << GET_MODE_BITSIZE (HImode))) | |
3597 | { | |
3598 | result_mode = insn_data[(int) CODE_FOR_cmpmemhi].operand[0].mode; | |
3599 | result = gen_reg_rtx (result_mode); | |
3600 | emit_insn (gen_cmpmemhi (result, x, y, size, opalign)); | |
3601 | } | |
3602 | else | |
3603 | #endif | |
3604 | #ifdef HAVE_cmpmemsi | |
3605 | if (HAVE_cmpmemsi) | |
3606 | { | |
3607 | result_mode = insn_data[(int) CODE_FOR_cmpmemsi].operand[0].mode; | |
3608 | result = gen_reg_rtx (result_mode); | |
3609 | size = protect_from_queue (size, 0); | |
3610 | emit_insn (gen_cmpmemsi (result, x, y, | |
3611 | convert_to_mode (SImode, size, 1), | |
3612 | opalign)); | |
3613 | } | |
3614 | else | |
3615 | #endif | |
77c9c6c2 RK |
3616 | #ifdef HAVE_cmpstrqi |
3617 | if (HAVE_cmpstrqi | |
3618 | && GET_CODE (size) == CONST_INT | |
3619 | && INTVAL (size) < (1 << GET_MODE_BITSIZE (QImode))) | |
3620 | { | |
a995e389 | 3621 | result_mode = insn_data[(int) CODE_FOR_cmpstrqi].operand[0].mode; |
b30f05db | 3622 | result = gen_reg_rtx (result_mode); |
19caa751 | 3623 | emit_insn (gen_cmpstrqi (result, x, y, size, opalign)); |
77c9c6c2 RK |
3624 | } |
3625 | else | |
3626 | #endif | |
3627 | #ifdef HAVE_cmpstrhi | |
3628 | if (HAVE_cmpstrhi | |
3629 | && GET_CODE (size) == CONST_INT | |
3630 | && INTVAL (size) < (1 << GET_MODE_BITSIZE (HImode))) | |
3631 | { | |
a995e389 | 3632 | result_mode = insn_data[(int) CODE_FOR_cmpstrhi].operand[0].mode; |
b30f05db | 3633 | result = gen_reg_rtx (result_mode); |
19caa751 | 3634 | emit_insn (gen_cmpstrhi (result, x, y, size, opalign)); |
77c9c6c2 RK |
3635 | } |
3636 | else | |
3637 | #endif | |
3638 | #ifdef HAVE_cmpstrsi | |
3639 | if (HAVE_cmpstrsi) | |
3640 | { | |
a995e389 | 3641 | result_mode = insn_data[(int) CODE_FOR_cmpstrsi].operand[0].mode; |
b30f05db | 3642 | result = gen_reg_rtx (result_mode); |
06e40b26 | 3643 | size = protect_from_queue (size, 0); |
77c9c6c2 RK |
3644 | emit_insn (gen_cmpstrsi (result, x, y, |
3645 | convert_to_mode (SImode, size, 1), | |
19caa751 | 3646 | opalign)); |
77c9c6c2 RK |
3647 | } |
3648 | else | |
3649 | #endif | |
3650 | { | |
3651 | #ifdef TARGET_MEM_FUNCTIONS | |
24491a09 KH |
3652 | result = emit_library_call_value (memcmp_libfunc, NULL_RTX, LCT_PURE_MAKE_BLOCK, |
3653 | TYPE_MODE (integer_type_node), 3, | |
3654 | XEXP (x, 0), Pmode, XEXP (y, 0), Pmode, | |
3655 | convert_to_mode (TYPE_MODE (sizetype), size, | |
3656 | TREE_UNSIGNED (sizetype)), | |
3657 | TYPE_MODE (sizetype)); | |
77c9c6c2 | 3658 | #else |
24491a09 KH |
3659 | result = emit_library_call_value (bcmp_libfunc, NULL_RTX, LCT_PURE_MAKE_BLOCK, |
3660 | TYPE_MODE (integer_type_node), 3, | |
3661 | XEXP (x, 0), Pmode, XEXP (y, 0), Pmode, | |
3662 | convert_to_mode (TYPE_MODE (integer_type_node), | |
3663 | size, | |
3664 | TREE_UNSIGNED (integer_type_node)), | |
3665 | TYPE_MODE (integer_type_node)); | |
77c9c6c2 | 3666 | #endif |
9725066d | 3667 | |
b30f05db | 3668 | result_mode = TYPE_MODE (integer_type_node); |
77c9c6c2 | 3669 | } |
b30f05db BS |
3670 | *px = result; |
3671 | *py = const0_rtx; | |
3672 | *pmode = result_mode; | |
77c9c6c2 RK |
3673 | return; |
3674 | } | |
3675 | ||
b30f05db BS |
3676 | *px = x; |
3677 | *py = y; | |
1eb8759b | 3678 | if (can_compare_p (*pcomparison, mode, purpose)) |
b30f05db | 3679 | return; |
77c9c6c2 RK |
3680 | |
3681 | /* Handle a lib call just for the mode we are using. */ | |
3682 | ||
b30f05db | 3683 | if (cmp_optab->handlers[(int) mode].libfunc && class != MODE_FLOAT) |
77c9c6c2 RK |
3684 | { |
3685 | rtx libfunc = cmp_optab->handlers[(int) mode].libfunc; | |
9725066d JL |
3686 | rtx result; |
3687 | ||
77c9c6c2 RK |
3688 | /* If we want unsigned, and this mode has a distinct unsigned |
3689 | comparison routine, use that. */ | |
3690 | if (unsignedp && ucmp_optab->handlers[(int) mode].libfunc) | |
3691 | libfunc = ucmp_optab->handlers[(int) mode].libfunc; | |
3692 | ||
24491a09 KH |
3693 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST_MAKE_BLOCK, |
3694 | word_mode, 2, x, mode, y, mode); | |
9725066d | 3695 | |
77c9c6c2 RK |
3696 | /* Integer comparison returns a result that must be compared against 1, |
3697 | so that even if we do an unsigned compare afterward, | |
3698 | there is still a value that can represent the result "less than". */ | |
b30f05db BS |
3699 | *px = result; |
3700 | *py = const1_rtx; | |
3701 | *pmode = word_mode; | |
77c9c6c2 RK |
3702 | return; |
3703 | } | |
3704 | ||
3705 | if (class == MODE_FLOAT) | |
c5c60e15 | 3706 | prepare_float_lib_cmp (px, py, pcomparison, pmode, punsignedp); |
77c9c6c2 RK |
3707 | |
3708 | else | |
3709 | abort (); | |
3710 | } | |
3711 | ||
b30f05db BS |
3712 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
3713 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
4fe9b91c | 3714 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
b30f05db | 3715 | that it is accepted by the operand predicate. Return the new value. */ |
749a2da1 | 3716 | |
1c0290ea | 3717 | rtx |
0c20a65f AJ |
3718 | prepare_operand (int icode, rtx x, int opnum, enum machine_mode mode, |
3719 | enum machine_mode wider_mode, int unsignedp) | |
b30f05db BS |
3720 | { |
3721 | x = protect_from_queue (x, 0); | |
3722 | ||
3723 | if (mode != wider_mode) | |
3724 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
3725 | ||
a995e389 RH |
3726 | if (! (*insn_data[icode].operand[opnum].predicate) |
3727 | (x, insn_data[icode].operand[opnum].mode)) | |
d893ccde RH |
3728 | { |
3729 | if (no_new_pseudos) | |
3730 | return NULL_RTX; | |
3731 | x = copy_to_mode_reg (insn_data[icode].operand[opnum].mode, x); | |
3732 | } | |
3733 | ||
b30f05db BS |
3734 | return x; |
3735 | } | |
3736 | ||
3737 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
3738 | we can do the comparison. | |
3739 | The arguments are the same as for emit_cmp_and_jump_insns; but LABEL may | |
3740 | be NULL_RTX which indicates that only a comparison is to be generated. */ | |
3741 | ||
3742 | static void | |
0c20a65f AJ |
3743 | emit_cmp_and_jump_insn_1 (rtx x, rtx y, enum machine_mode mode, |
3744 | enum rtx_code comparison, int unsignedp, rtx label) | |
b30f05db BS |
3745 | { |
3746 | rtx test = gen_rtx_fmt_ee (comparison, mode, x, y); | |
3747 | enum mode_class class = GET_MODE_CLASS (mode); | |
3748 | enum machine_mode wider_mode = mode; | |
3749 | ||
3750 | /* Try combined insns first. */ | |
3751 | do | |
3752 | { | |
3753 | enum insn_code icode; | |
3754 | PUT_MODE (test, wider_mode); | |
3755 | ||
1c0290ea | 3756 | if (label) |
0c20a65f | 3757 | { |
7e1a450d | 3758 | icode = cbranch_optab->handlers[(int) wider_mode].insn_code; |
0c20a65f | 3759 | |
1c0290ea BS |
3760 | if (icode != CODE_FOR_nothing |
3761 | && (*insn_data[icode].operand[0].predicate) (test, wider_mode)) | |
3762 | { | |
3763 | x = prepare_operand (icode, x, 1, mode, wider_mode, unsignedp); | |
3764 | y = prepare_operand (icode, y, 2, mode, wider_mode, unsignedp); | |
3765 | emit_jump_insn (GEN_FCN (icode) (test, x, y, label)); | |
3766 | return; | |
3767 | } | |
3768 | } | |
3769 | ||
b30f05db BS |
3770 | /* Handle some compares against zero. */ |
3771 | icode = (int) tst_optab->handlers[(int) wider_mode].insn_code; | |
3772 | if (y == CONST0_RTX (mode) && icode != CODE_FOR_nothing) | |
3773 | { | |
3774 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
3775 | emit_insn (GEN_FCN (icode) (x)); | |
3776 | if (label) | |
3777 | emit_jump_insn ((*bcc_gen_fctn[(int) comparison]) (label)); | |
3778 | return; | |
3779 | } | |
3780 | ||
3781 | /* Handle compares for which there is a directly suitable insn. */ | |
3782 | ||
3783 | icode = (int) cmp_optab->handlers[(int) wider_mode].insn_code; | |
3784 | if (icode != CODE_FOR_nothing) | |
3785 | { | |
3786 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
3787 | y = prepare_operand (icode, y, 1, mode, wider_mode, unsignedp); | |
3788 | emit_insn (GEN_FCN (icode) (x, y)); | |
3789 | if (label) | |
3790 | emit_jump_insn ((*bcc_gen_fctn[(int) comparison]) (label)); | |
3791 | return; | |
3792 | } | |
3793 | ||
3794 | if (class != MODE_INT && class != MODE_FLOAT | |
3795 | && class != MODE_COMPLEX_FLOAT) | |
3796 | break; | |
3797 | ||
3798 | wider_mode = GET_MODE_WIDER_MODE (wider_mode); | |
7e1a450d KH |
3799 | } |
3800 | while (wider_mode != VOIDmode); | |
b30f05db BS |
3801 | |
3802 | abort (); | |
3803 | } | |
3804 | ||
362cc3d4 MH |
3805 | /* Generate code to compare X with Y so that the condition codes are |
3806 | set and to jump to LABEL if the condition is true. If X is a | |
3807 | constant and Y is not a constant, then the comparison is swapped to | |
3808 | ensure that the comparison RTL has the canonical form. | |
3809 | ||
c5d5d461 JL |
3810 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
3811 | need to be widened by emit_cmp_insn. UNSIGNEDP is also used to select | |
3812 | the proper branch condition code. | |
362cc3d4 | 3813 | |
a06ef755 | 3814 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
362cc3d4 | 3815 | |
c5d5d461 JL |
3816 | MODE is the mode of the inputs (in case they are const_int). |
3817 | ||
3818 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). It will | |
3819 | be passed unchanged to emit_cmp_insn, then potentially converted into an | |
3820 | unsigned variant based on UNSIGNEDP to select a proper jump instruction. */ | |
362cc3d4 MH |
3821 | |
3822 | void | |
0c20a65f AJ |
3823 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3824 | enum machine_mode mode, int unsignedp, rtx label) | |
362cc3d4 | 3825 | { |
8c9864f3 JH |
3826 | rtx op0 = x, op1 = y; |
3827 | ||
3828 | /* Swap operands and condition to ensure canonical RTL. */ | |
3829 | if (swap_commutative_operands_p (x, y)) | |
362cc3d4 | 3830 | { |
8c9864f3 JH |
3831 | /* If we're not emitting a branch, this means some caller |
3832 | is out of sync. */ | |
3833 | if (! label) | |
3834 | abort (); | |
3835 | ||
3836 | op0 = y, op1 = x; | |
3837 | comparison = swap_condition (comparison); | |
362cc3d4 | 3838 | } |
0ca40216 JL |
3839 | |
3840 | #ifdef HAVE_cc0 | |
3841 | /* If OP0 is still a constant, then both X and Y must be constants. Force | |
3842 | X into a register to avoid aborting in emit_cmp_insn due to non-canonical | |
3843 | RTL. */ | |
3844 | if (CONSTANT_P (op0)) | |
3845 | op0 = force_reg (mode, op0); | |
3846 | #endif | |
3847 | ||
b30f05db | 3848 | emit_queue (); |
c5d5d461 JL |
3849 | if (unsignedp) |
3850 | comparison = unsigned_condition (comparison); | |
a06ef755 RK |
3851 | |
3852 | prepare_cmp_insn (&op0, &op1, &comparison, size, &mode, &unsignedp, | |
1c0290ea | 3853 | ccp_jump); |
b30f05db BS |
3854 | emit_cmp_and_jump_insn_1 (op0, op1, mode, comparison, unsignedp, label); |
3855 | } | |
3856 | ||
3857 | /* Like emit_cmp_and_jump_insns, but generate only the comparison. */ | |
19caa751 | 3858 | |
b30f05db | 3859 | void |
0c20a65f AJ |
3860 | emit_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3861 | enum machine_mode mode, int unsignedp) | |
b30f05db | 3862 | { |
a06ef755 | 3863 | emit_cmp_and_jump_insns (x, y, comparison, size, mode, unsignedp, 0); |
362cc3d4 | 3864 | } |
77c9c6c2 RK |
3865 | \f |
3866 | /* Emit a library call comparison between floating point X and Y. | |
3867 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
3868 | ||
c5c60e15 | 3869 | static void |
0c20a65f AJ |
3870 | prepare_float_lib_cmp (rtx *px, rtx *py, enum rtx_code *pcomparison, |
3871 | enum machine_mode *pmode, int *punsignedp) | |
77c9c6c2 | 3872 | { |
c5c60e15 | 3873 | enum rtx_code comparison = *pcomparison; |
12f61e77 | 3874 | rtx tmp; |
885e80cc AO |
3875 | rtx x = *px = protect_from_queue (*px, 0); |
3876 | rtx y = *py = protect_from_queue (*py, 0); | |
77c9c6c2 | 3877 | enum machine_mode mode = GET_MODE (x); |
0a300065 | 3878 | rtx libfunc = 0; |
9725066d | 3879 | rtx result; |
77c9c6c2 | 3880 | |
842dcd1a RK |
3881 | if (mode == HFmode) |
3882 | switch (comparison) | |
3883 | { | |
3884 | case EQ: | |
3885 | libfunc = eqhf2_libfunc; | |
3886 | break; | |
3887 | ||
3888 | case NE: | |
3889 | libfunc = nehf2_libfunc; | |
3890 | break; | |
3891 | ||
3892 | case GT: | |
3893 | libfunc = gthf2_libfunc; | |
12f61e77 AO |
3894 | if (libfunc == NULL_RTX) |
3895 | { | |
3896 | tmp = x; x = y; y = tmp; | |
3897 | *pcomparison = LT; | |
3898 | libfunc = lthf2_libfunc; | |
3899 | } | |
842dcd1a RK |
3900 | break; |
3901 | ||
3902 | case GE: | |
3903 | libfunc = gehf2_libfunc; | |
12f61e77 AO |
3904 | if (libfunc == NULL_RTX) |
3905 | { | |
3906 | tmp = x; x = y; y = tmp; | |
3907 | *pcomparison = LE; | |
3908 | libfunc = lehf2_libfunc; | |
3909 | } | |
842dcd1a RK |
3910 | break; |
3911 | ||
3912 | case LT: | |
3913 | libfunc = lthf2_libfunc; | |
12f61e77 AO |
3914 | if (libfunc == NULL_RTX) |
3915 | { | |
3916 | tmp = x; x = y; y = tmp; | |
3917 | *pcomparison = GT; | |
3918 | libfunc = gthf2_libfunc; | |
3919 | } | |
842dcd1a RK |
3920 | break; |
3921 | ||
3922 | case LE: | |
3923 | libfunc = lehf2_libfunc; | |
12f61e77 AO |
3924 | if (libfunc == NULL_RTX) |
3925 | { | |
3926 | tmp = x; x = y; y = tmp; | |
3927 | *pcomparison = GE; | |
3928 | libfunc = gehf2_libfunc; | |
3929 | } | |
842dcd1a | 3930 | break; |
bb727b5a | 3931 | |
1eb8759b RH |
3932 | case UNORDERED: |
3933 | libfunc = unordhf2_libfunc; | |
3934 | break; | |
3935 | ||
bb727b5a JM |
3936 | default: |
3937 | break; | |
842dcd1a RK |
3938 | } |
3939 | else if (mode == SFmode) | |
77c9c6c2 RK |
3940 | switch (comparison) |
3941 | { | |
3942 | case EQ: | |
3943 | libfunc = eqsf2_libfunc; | |
3944 | break; | |
3945 | ||
3946 | case NE: | |
3947 | libfunc = nesf2_libfunc; | |
3948 | break; | |
3949 | ||
3950 | case GT: | |
3951 | libfunc = gtsf2_libfunc; | |
12f61e77 AO |
3952 | if (libfunc == NULL_RTX) |
3953 | { | |
3954 | tmp = x; x = y; y = tmp; | |
3955 | *pcomparison = LT; | |
3956 | libfunc = ltsf2_libfunc; | |
3957 | } | |
77c9c6c2 RK |
3958 | break; |
3959 | ||
3960 | case GE: | |
3961 | libfunc = gesf2_libfunc; | |
12f61e77 AO |
3962 | if (libfunc == NULL_RTX) |
3963 | { | |
3964 | tmp = x; x = y; y = tmp; | |
3965 | *pcomparison = LE; | |
3966 | libfunc = lesf2_libfunc; | |
3967 | } | |
77c9c6c2 RK |
3968 | break; |
3969 | ||
3970 | case LT: | |
3971 | libfunc = ltsf2_libfunc; | |
12f61e77 AO |
3972 | if (libfunc == NULL_RTX) |
3973 | { | |
3974 | tmp = x; x = y; y = tmp; | |
3975 | *pcomparison = GT; | |
3976 | libfunc = gtsf2_libfunc; | |
3977 | } | |
77c9c6c2 RK |
3978 | break; |
3979 | ||
3980 | case LE: | |
3981 | libfunc = lesf2_libfunc; | |
12f61e77 AO |
3982 | if (libfunc == NULL_RTX) |
3983 | { | |
3984 | tmp = x; x = y; y = tmp; | |
3985 | *pcomparison = GE; | |
3986 | libfunc = gesf2_libfunc; | |
3987 | } | |
77c9c6c2 | 3988 | break; |
bb727b5a | 3989 | |
1eb8759b RH |
3990 | case UNORDERED: |
3991 | libfunc = unordsf2_libfunc; | |
3992 | break; | |
3993 | ||
bb727b5a JM |
3994 | default: |
3995 | break; | |
77c9c6c2 RK |
3996 | } |
3997 | else if (mode == DFmode) | |
3998 | switch (comparison) | |
3999 | { | |
4000 | case EQ: | |
4001 | libfunc = eqdf2_libfunc; | |
4002 | break; | |
4003 | ||
4004 | case NE: | |
4005 | libfunc = nedf2_libfunc; | |
4006 | break; | |
4007 | ||
4008 | case GT: | |
4009 | libfunc = gtdf2_libfunc; | |
12f61e77 AO |
4010 | if (libfunc == NULL_RTX) |
4011 | { | |
4012 | tmp = x; x = y; y = tmp; | |
4013 | *pcomparison = LT; | |
4014 | libfunc = ltdf2_libfunc; | |
4015 | } | |
77c9c6c2 RK |
4016 | break; |
4017 | ||
4018 | case GE: | |
4019 | libfunc = gedf2_libfunc; | |
12f61e77 AO |
4020 | if (libfunc == NULL_RTX) |
4021 | { | |
4022 | tmp = x; x = y; y = tmp; | |
4023 | *pcomparison = LE; | |
4024 | libfunc = ledf2_libfunc; | |
4025 | } | |
77c9c6c2 RK |
4026 | break; |
4027 | ||
4028 | case LT: | |
4029 | libfunc = ltdf2_libfunc; | |
12f61e77 AO |
4030 | if (libfunc == NULL_RTX) |
4031 | { | |
4032 | tmp = x; x = y; y = tmp; | |
4033 | *pcomparison = GT; | |
4034 | libfunc = gtdf2_libfunc; | |
4035 | } | |
77c9c6c2 RK |
4036 | break; |
4037 | ||
4038 | case LE: | |
4039 | libfunc = ledf2_libfunc; | |
12f61e77 AO |
4040 | if (libfunc == NULL_RTX) |
4041 | { | |
4042 | tmp = x; x = y; y = tmp; | |
4043 | *pcomparison = GE; | |
4044 | libfunc = gedf2_libfunc; | |
4045 | } | |
77c9c6c2 | 4046 | break; |
bb727b5a | 4047 | |
1eb8759b RH |
4048 | case UNORDERED: |
4049 | libfunc = unorddf2_libfunc; | |
4050 | break; | |
4051 | ||
bb727b5a JM |
4052 | default: |
4053 | break; | |
77c9c6c2 | 4054 | } |
b092b471 JW |
4055 | else if (mode == XFmode) |
4056 | switch (comparison) | |
4057 | { | |
4058 | case EQ: | |
4059 | libfunc = eqxf2_libfunc; | |
4060 | break; | |
4061 | ||
4062 | case NE: | |
4063 | libfunc = nexf2_libfunc; | |
4064 | break; | |
4065 | ||
4066 | case GT: | |
4067 | libfunc = gtxf2_libfunc; | |
12f61e77 AO |
4068 | if (libfunc == NULL_RTX) |
4069 | { | |
4070 | tmp = x; x = y; y = tmp; | |
4071 | *pcomparison = LT; | |
4072 | libfunc = ltxf2_libfunc; | |
4073 | } | |
b092b471 JW |
4074 | break; |
4075 | ||
4076 | case GE: | |
4077 | libfunc = gexf2_libfunc; | |
12f61e77 AO |
4078 | if (libfunc == NULL_RTX) |
4079 | { | |
4080 | tmp = x; x = y; y = tmp; | |
4081 | *pcomparison = LE; | |
4082 | libfunc = lexf2_libfunc; | |
4083 | } | |
b092b471 JW |
4084 | break; |
4085 | ||
4086 | case LT: | |
4087 | libfunc = ltxf2_libfunc; | |
12f61e77 AO |
4088 | if (libfunc == NULL_RTX) |
4089 | { | |
4090 | tmp = x; x = y; y = tmp; | |
4091 | *pcomparison = GT; | |
4092 | libfunc = gtxf2_libfunc; | |
4093 | } | |
b092b471 JW |
4094 | break; |
4095 | ||
4096 | case LE: | |
4097 | libfunc = lexf2_libfunc; | |
12f61e77 AO |
4098 | if (libfunc == NULL_RTX) |
4099 | { | |
4100 | tmp = x; x = y; y = tmp; | |
4101 | *pcomparison = GE; | |
4102 | libfunc = gexf2_libfunc; | |
4103 | } | |
b092b471 | 4104 | break; |
bb727b5a | 4105 | |
1eb8759b RH |
4106 | case UNORDERED: |
4107 | libfunc = unordxf2_libfunc; | |
4108 | break; | |
4109 | ||
bb727b5a JM |
4110 | default: |
4111 | break; | |
b092b471 JW |
4112 | } |
4113 | else if (mode == TFmode) | |
4114 | switch (comparison) | |
4115 | { | |
4116 | case EQ: | |
4117 | libfunc = eqtf2_libfunc; | |
4118 | break; | |
4119 | ||
4120 | case NE: | |
4121 | libfunc = netf2_libfunc; | |
4122 | break; | |
4123 | ||
4124 | case GT: | |
4125 | libfunc = gttf2_libfunc; | |
12f61e77 AO |
4126 | if (libfunc == NULL_RTX) |
4127 | { | |
4128 | tmp = x; x = y; y = tmp; | |
4129 | *pcomparison = LT; | |
4130 | libfunc = lttf2_libfunc; | |
4131 | } | |
b092b471 JW |
4132 | break; |
4133 | ||
4134 | case GE: | |
4135 | libfunc = getf2_libfunc; | |
12f61e77 AO |
4136 | if (libfunc == NULL_RTX) |
4137 | { | |
4138 | tmp = x; x = y; y = tmp; | |
4139 | *pcomparison = LE; | |
4140 | libfunc = letf2_libfunc; | |
4141 | } | |
b092b471 JW |
4142 | break; |
4143 | ||
4144 | case LT: | |
4145 | libfunc = lttf2_libfunc; | |
12f61e77 AO |
4146 | if (libfunc == NULL_RTX) |
4147 | { | |
4148 | tmp = x; x = y; y = tmp; | |
4149 | *pcomparison = GT; | |
4150 | libfunc = gttf2_libfunc; | |
4151 | } | |
b092b471 JW |
4152 | break; |
4153 | ||
4154 | case LE: | |
4155 | libfunc = letf2_libfunc; | |
12f61e77 AO |
4156 | if (libfunc == NULL_RTX) |
4157 | { | |
4158 | tmp = x; x = y; y = tmp; | |
4159 | *pcomparison = GE; | |
4160 | libfunc = getf2_libfunc; | |
4161 | } | |
b092b471 | 4162 | break; |
bb727b5a | 4163 | |
1eb8759b RH |
4164 | case UNORDERED: |
4165 | libfunc = unordtf2_libfunc; | |
4166 | break; | |
4167 | ||
bb727b5a JM |
4168 | default: |
4169 | break; | |
b092b471 | 4170 | } |
77c9c6c2 RK |
4171 | else |
4172 | { | |
4173 | enum machine_mode wider_mode; | |
4174 | ||
34e56753 | 4175 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
4176 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
4177 | { | |
4178 | if ((cmp_optab->handlers[(int) wider_mode].insn_code | |
4179 | != CODE_FOR_nothing) | |
4180 | || (cmp_optab->handlers[(int) wider_mode].libfunc != 0)) | |
4181 | { | |
06e40b26 RS |
4182 | x = protect_from_queue (x, 0); |
4183 | y = protect_from_queue (y, 0); | |
b30f05db BS |
4184 | *px = convert_to_mode (wider_mode, x, 0); |
4185 | *py = convert_to_mode (wider_mode, y, 0); | |
c5c60e15 | 4186 | prepare_float_lib_cmp (px, py, pcomparison, pmode, punsignedp); |
77c9c6c2 RK |
4187 | return; |
4188 | } | |
4189 | } | |
4190 | abort (); | |
4191 | } | |
4192 | ||
0a300065 RK |
4193 | if (libfunc == 0) |
4194 | abort (); | |
4195 | ||
24491a09 KH |
4196 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST_MAKE_BLOCK, |
4197 | word_mode, 2, x, mode, y, mode); | |
b30f05db BS |
4198 | *px = result; |
4199 | *py = const0_rtx; | |
4200 | *pmode = word_mode; | |
1eb8759b RH |
4201 | if (comparison == UNORDERED) |
4202 | *pcomparison = NE; | |
c5c60e15 | 4203 | #ifdef FLOAT_LIB_COMPARE_RETURNS_BOOL |
1eb8759b | 4204 | else if (FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) |
c5c60e15 BS |
4205 | *pcomparison = NE; |
4206 | #endif | |
b30f05db | 4207 | *punsignedp = 0; |
77c9c6c2 RK |
4208 | } |
4209 | \f | |
4210 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4211 | ||
4212 | void | |
0c20a65f | 4213 | emit_indirect_jump (rtx loc) |
77c9c6c2 | 4214 | { |
7e1a450d | 4215 | if (! ((*insn_data[(int) CODE_FOR_indirect_jump].operand[0].predicate) |
f2de2775 JW |
4216 | (loc, Pmode))) |
4217 | loc = copy_to_mode_reg (Pmode, loc); | |
77c9c6c2 RK |
4218 | |
4219 | emit_jump_insn (gen_indirect_jump (loc)); | |
9649fb4d | 4220 | emit_barrier (); |
77c9c6c2 RK |
4221 | } |
4222 | \f | |
49c4584c DE |
4223 | #ifdef HAVE_conditional_move |
4224 | ||
4225 | /* Emit a conditional move instruction if the machine supports one for that | |
4226 | condition and machine mode. | |
4227 | ||
4228 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4229 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4230 | both be constants. | |
4231 | ||
4232 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4233 | should be stored there. MODE is the mode to use should they be constants. | |
4234 | If it is VOIDmode, they cannot both be constants. | |
4235 | ||
4236 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4237 | is not supported. */ | |
4238 | ||
4239 | rtx | |
0c20a65f AJ |
4240 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4241 | enum machine_mode cmode, rtx op2, rtx op3, | |
4242 | enum machine_mode mode, int unsignedp) | |
49c4584c DE |
4243 | { |
4244 | rtx tem, subtarget, comparison, insn; | |
4245 | enum insn_code icode; | |
e5c56fd9 | 4246 | enum rtx_code reversed; |
49c4584c DE |
4247 | |
4248 | /* If one operand is constant, make it the second one. Only do this | |
4249 | if the other operand is not constant as well. */ | |
4250 | ||
e5c56fd9 | 4251 | if (swap_commutative_operands_p (op0, op1)) |
49c4584c DE |
4252 | { |
4253 | tem = op0; | |
4254 | op0 = op1; | |
4255 | op1 = tem; | |
4256 | code = swap_condition (code); | |
4257 | } | |
4258 | ||
c5c76735 JL |
4259 | /* get_condition will prefer to generate LT and GT even if the old |
4260 | comparison was against zero, so undo that canonicalization here since | |
4261 | comparisons against zero are cheaper. */ | |
4262 | if (code == LT && GET_CODE (op1) == CONST_INT && INTVAL (op1) == 1) | |
4263 | code = LE, op1 = const0_rtx; | |
4264 | else if (code == GT && GET_CODE (op1) == CONST_INT && INTVAL (op1) == -1) | |
4265 | code = GE, op1 = const0_rtx; | |
4266 | ||
49c4584c DE |
4267 | if (cmode == VOIDmode) |
4268 | cmode = GET_MODE (op0); | |
4269 | ||
e5c56fd9 JH |
4270 | if (swap_commutative_operands_p (op2, op3) |
4271 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4272 | != UNKNOWN)) | |
49c4584c DE |
4273 | { |
4274 | tem = op2; | |
4275 | op2 = op3; | |
4276 | op3 = tem; | |
e5c56fd9 | 4277 | code = reversed; |
49c4584c DE |
4278 | } |
4279 | ||
4280 | if (mode == VOIDmode) | |
4281 | mode = GET_MODE (op2); | |
4282 | ||
4283 | icode = movcc_gen_code[mode]; | |
4284 | ||
4285 | if (icode == CODE_FOR_nothing) | |
4286 | return 0; | |
4287 | ||
4288 | if (flag_force_mem) | |
4289 | { | |
4290 | op2 = force_not_mem (op2); | |
4291 | op3 = force_not_mem (op3); | |
4292 | } | |
4293 | ||
4294 | if (target) | |
4295 | target = protect_from_queue (target, 1); | |
4296 | else | |
4297 | target = gen_reg_rtx (mode); | |
4298 | ||
4299 | subtarget = target; | |
4300 | ||
4301 | emit_queue (); | |
4302 | ||
4303 | op2 = protect_from_queue (op2, 0); | |
4304 | op3 = protect_from_queue (op3, 0); | |
4305 | ||
4306 | /* If the insn doesn't accept these operands, put them in pseudos. */ | |
4307 | ||
a995e389 RH |
4308 | if (! (*insn_data[icode].operand[0].predicate) |
4309 | (subtarget, insn_data[icode].operand[0].mode)) | |
4310 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
49c4584c | 4311 | |
a995e389 RH |
4312 | if (! (*insn_data[icode].operand[2].predicate) |
4313 | (op2, insn_data[icode].operand[2].mode)) | |
4314 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
49c4584c | 4315 | |
a995e389 RH |
4316 | if (! (*insn_data[icode].operand[3].predicate) |
4317 | (op3, insn_data[icode].operand[3].mode)) | |
4318 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
49c4584c DE |
4319 | |
4320 | /* Everything should now be in the suitable form, so emit the compare insn | |
4321 | and then the conditional move. */ | |
4322 | ||
0c20a65f | 4323 | comparison |
a06ef755 | 4324 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
49c4584c DE |
4325 | |
4326 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
144a5f9d JL |
4327 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4328 | return NULL and let the caller figure out how best to deal with this | |
4329 | situation. */ | |
49c4584c | 4330 | if (GET_CODE (comparison) != code) |
144a5f9d | 4331 | return NULL_RTX; |
0c20a65f | 4332 | |
49c4584c DE |
4333 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4334 | ||
4335 | /* If that failed, then give up. */ | |
4336 | if (insn == 0) | |
4337 | return 0; | |
4338 | ||
4339 | emit_insn (insn); | |
4340 | ||
4341 | if (subtarget != target) | |
4342 | convert_move (target, subtarget, 0); | |
4343 | ||
4344 | return target; | |
4345 | } | |
4346 | ||
40f03658 | 4347 | /* Return nonzero if a conditional move of mode MODE is supported. |
49c4584c DE |
4348 | |
4349 | This function is for combine so it can tell whether an insn that looks | |
4350 | like a conditional move is actually supported by the hardware. If we | |
4351 | guess wrong we lose a bit on optimization, but that's it. */ | |
4352 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4353 | comparisons, and vice versa. How do we handle them? */ | |
4354 | ||
4355 | int | |
0c20a65f | 4356 | can_conditionally_move_p (enum machine_mode mode) |
49c4584c DE |
4357 | { |
4358 | if (movcc_gen_code[mode] != CODE_FOR_nothing) | |
4359 | return 1; | |
4360 | ||
4361 | return 0; | |
4362 | } | |
4363 | ||
4364 | #endif /* HAVE_conditional_move */ | |
068f5dea JH |
4365 | |
4366 | /* Emit a conditional addition instruction if the machine supports one for that | |
4367 | condition and machine mode. | |
4368 | ||
4369 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4370 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4371 | both be constants. | |
4372 | ||
4373 | OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3 | |
4374 | should be stored there. MODE is the mode to use should they be constants. | |
4375 | If it is VOIDmode, they cannot both be constants. | |
4376 | ||
4377 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4378 | is not supported. */ | |
4379 | ||
4380 | rtx | |
0c20a65f AJ |
4381 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4382 | enum machine_mode cmode, rtx op2, rtx op3, | |
4383 | enum machine_mode mode, int unsignedp) | |
068f5dea JH |
4384 | { |
4385 | rtx tem, subtarget, comparison, insn; | |
4386 | enum insn_code icode; | |
4387 | enum rtx_code reversed; | |
4388 | ||
4389 | /* If one operand is constant, make it the second one. Only do this | |
4390 | if the other operand is not constant as well. */ | |
4391 | ||
4392 | if (swap_commutative_operands_p (op0, op1)) | |
4393 | { | |
4394 | tem = op0; | |
4395 | op0 = op1; | |
4396 | op1 = tem; | |
4397 | code = swap_condition (code); | |
4398 | } | |
4399 | ||
4400 | /* get_condition will prefer to generate LT and GT even if the old | |
4401 | comparison was against zero, so undo that canonicalization here since | |
4402 | comparisons against zero are cheaper. */ | |
4403 | if (code == LT && GET_CODE (op1) == CONST_INT && INTVAL (op1) == 1) | |
4404 | code = LE, op1 = const0_rtx; | |
4405 | else if (code == GT && GET_CODE (op1) == CONST_INT && INTVAL (op1) == -1) | |
4406 | code = GE, op1 = const0_rtx; | |
4407 | ||
4408 | if (cmode == VOIDmode) | |
4409 | cmode = GET_MODE (op0); | |
4410 | ||
4411 | if (swap_commutative_operands_p (op2, op3) | |
4412 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4413 | != UNKNOWN)) | |
4414 | { | |
4415 | tem = op2; | |
4416 | op2 = op3; | |
4417 | op3 = tem; | |
4418 | code = reversed; | |
4419 | } | |
4420 | ||
4421 | if (mode == VOIDmode) | |
4422 | mode = GET_MODE (op2); | |
4423 | ||
4424 | icode = addcc_optab->handlers[(int) mode].insn_code; | |
4425 | ||
4426 | if (icode == CODE_FOR_nothing) | |
4427 | return 0; | |
4428 | ||
4429 | if (flag_force_mem) | |
4430 | { | |
4431 | op2 = force_not_mem (op2); | |
4432 | op3 = force_not_mem (op3); | |
4433 | } | |
4434 | ||
4435 | if (target) | |
4436 | target = protect_from_queue (target, 1); | |
4437 | else | |
4438 | target = gen_reg_rtx (mode); | |
4439 | ||
4440 | subtarget = target; | |
4441 | ||
4442 | emit_queue (); | |
4443 | ||
4444 | op2 = protect_from_queue (op2, 0); | |
4445 | op3 = protect_from_queue (op3, 0); | |
4446 | ||
4447 | /* If the insn doesn't accept these operands, put them in pseudos. */ | |
4448 | ||
4449 | if (! (*insn_data[icode].operand[0].predicate) | |
4450 | (subtarget, insn_data[icode].operand[0].mode)) | |
4451 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
4452 | ||
4453 | if (! (*insn_data[icode].operand[2].predicate) | |
4454 | (op2, insn_data[icode].operand[2].mode)) | |
4455 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
4456 | ||
4457 | if (! (*insn_data[icode].operand[3].predicate) | |
4458 | (op3, insn_data[icode].operand[3].mode)) | |
4459 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
4460 | ||
4461 | /* Everything should now be in the suitable form, so emit the compare insn | |
4462 | and then the conditional move. */ | |
4463 | ||
0c20a65f | 4464 | comparison |
068f5dea JH |
4465 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
4466 | ||
4467 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
4468 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just | |
4469 | return NULL and let the caller figure out how best to deal with this | |
4470 | situation. */ | |
4471 | if (GET_CODE (comparison) != code) | |
4472 | return NULL_RTX; | |
0c20a65f | 4473 | |
068f5dea JH |
4474 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4475 | ||
4476 | /* If that failed, then give up. */ | |
4477 | if (insn == 0) | |
4478 | return 0; | |
4479 | ||
4480 | emit_insn (insn); | |
4481 | ||
4482 | if (subtarget != target) | |
4483 | convert_move (target, subtarget, 0); | |
4484 | ||
4485 | return target; | |
4486 | } | |
49c4584c | 4487 | \f |
0913e4b4 AO |
4488 | /* These functions attempt to generate an insn body, rather than |
4489 | emitting the insn, but if the gen function already emits them, we | |
4490 | make no attempt to turn them back into naked patterns. | |
77c9c6c2 RK |
4491 | |
4492 | They do not protect from queued increments, | |
4493 | because they may be used 1) in protect_from_queue itself | |
4494 | and 2) in other passes where there is no queue. */ | |
4495 | ||
4496 | /* Generate and return an insn body to add Y to X. */ | |
4497 | ||
4498 | rtx | |
0c20a65f | 4499 | gen_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4500 | { |
0c20a65f | 4501 | int icode = (int) add_optab->handlers[(int) GET_MODE (x)].insn_code; |
77c9c6c2 | 4502 | |
a995e389 RH |
4503 | if (! ((*insn_data[icode].operand[0].predicate) |
4504 | (x, insn_data[icode].operand[0].mode)) | |
4505 | || ! ((*insn_data[icode].operand[1].predicate) | |
4506 | (x, insn_data[icode].operand[1].mode)) | |
4507 | || ! ((*insn_data[icode].operand[2].predicate) | |
4508 | (y, insn_data[icode].operand[2].mode))) | |
77c9c6c2 RK |
4509 | abort (); |
4510 | ||
4511 | return (GEN_FCN (icode) (x, x, y)); | |
4512 | } | |
4513 | ||
e78d8e51 ZW |
4514 | /* Generate and return an insn body to add r1 and c, |
4515 | storing the result in r0. */ | |
4516 | rtx | |
0c20a65f | 4517 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
e78d8e51 ZW |
4518 | { |
4519 | int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
4520 | ||
7e1a450d | 4521 | if (icode == CODE_FOR_nothing |
e78d8e51 ZW |
4522 | || ! ((*insn_data[icode].operand[0].predicate) |
4523 | (r0, insn_data[icode].operand[0].mode)) | |
4524 | || ! ((*insn_data[icode].operand[1].predicate) | |
4525 | (r1, insn_data[icode].operand[1].mode)) | |
4526 | || ! ((*insn_data[icode].operand[2].predicate) | |
4527 | (c, insn_data[icode].operand[2].mode))) | |
4528 | return NULL_RTX; | |
4529 | ||
4530 | return (GEN_FCN (icode) (r0, r1, c)); | |
4531 | } | |
4532 | ||
77c9c6c2 | 4533 | int |
0c20a65f | 4534 | have_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4535 | { |
fb7e77d7 TM |
4536 | int icode; |
4537 | ||
4538 | if (GET_MODE (x) == VOIDmode) | |
4539 | abort (); | |
4540 | ||
0c20a65f | 4541 | icode = (int) add_optab->handlers[(int) GET_MODE (x)].insn_code; |
fb7e77d7 TM |
4542 | |
4543 | if (icode == CODE_FOR_nothing) | |
4544 | return 0; | |
4545 | ||
4546 | if (! ((*insn_data[icode].operand[0].predicate) | |
4547 | (x, insn_data[icode].operand[0].mode)) | |
4548 | || ! ((*insn_data[icode].operand[1].predicate) | |
4549 | (x, insn_data[icode].operand[1].mode)) | |
4550 | || ! ((*insn_data[icode].operand[2].predicate) | |
4551 | (y, insn_data[icode].operand[2].mode))) | |
4552 | return 0; | |
4553 | ||
4554 | return 1; | |
77c9c6c2 RK |
4555 | } |
4556 | ||
4557 | /* Generate and return an insn body to subtract Y from X. */ | |
4558 | ||
4559 | rtx | |
0c20a65f | 4560 | gen_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4561 | { |
0c20a65f | 4562 | int icode = (int) sub_optab->handlers[(int) GET_MODE (x)].insn_code; |
77c9c6c2 | 4563 | |
a995e389 RH |
4564 | if (! ((*insn_data[icode].operand[0].predicate) |
4565 | (x, insn_data[icode].operand[0].mode)) | |
4566 | || ! ((*insn_data[icode].operand[1].predicate) | |
4567 | (x, insn_data[icode].operand[1].mode)) | |
4568 | || ! ((*insn_data[icode].operand[2].predicate) | |
4569 | (y, insn_data[icode].operand[2].mode))) | |
77c9c6c2 RK |
4570 | abort (); |
4571 | ||
4572 | return (GEN_FCN (icode) (x, x, y)); | |
4573 | } | |
4574 | ||
ef89d648 ZW |
4575 | /* Generate and return an insn body to subtract r1 and c, |
4576 | storing the result in r0. */ | |
4577 | rtx | |
0c20a65f | 4578 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ef89d648 ZW |
4579 | { |
4580 | int icode = (int) sub_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
4581 | ||
7e1a450d | 4582 | if (icode == CODE_FOR_nothing |
ef89d648 ZW |
4583 | || ! ((*insn_data[icode].operand[0].predicate) |
4584 | (r0, insn_data[icode].operand[0].mode)) | |
4585 | || ! ((*insn_data[icode].operand[1].predicate) | |
4586 | (r1, insn_data[icode].operand[1].mode)) | |
4587 | || ! ((*insn_data[icode].operand[2].predicate) | |
4588 | (c, insn_data[icode].operand[2].mode))) | |
4589 | return NULL_RTX; | |
4590 | ||
4591 | return (GEN_FCN (icode) (r0, r1, c)); | |
4592 | } | |
4593 | ||
77c9c6c2 | 4594 | int |
0c20a65f | 4595 | have_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4596 | { |
fb7e77d7 TM |
4597 | int icode; |
4598 | ||
4599 | if (GET_MODE (x) == VOIDmode) | |
4600 | abort (); | |
4601 | ||
0c20a65f | 4602 | icode = (int) sub_optab->handlers[(int) GET_MODE (x)].insn_code; |
fb7e77d7 TM |
4603 | |
4604 | if (icode == CODE_FOR_nothing) | |
4605 | return 0; | |
4606 | ||
4607 | if (! ((*insn_data[icode].operand[0].predicate) | |
4608 | (x, insn_data[icode].operand[0].mode)) | |
4609 | || ! ((*insn_data[icode].operand[1].predicate) | |
4610 | (x, insn_data[icode].operand[1].mode)) | |
4611 | || ! ((*insn_data[icode].operand[2].predicate) | |
4612 | (y, insn_data[icode].operand[2].mode))) | |
4613 | return 0; | |
4614 | ||
4615 | return 1; | |
77c9c6c2 RK |
4616 | } |
4617 | ||
e3654226 | 4618 | /* Generate the body of an instruction to copy Y into X. |
2f937369 | 4619 | It may be a list of insns, if one insn isn't enough. */ |
77c9c6c2 RK |
4620 | |
4621 | rtx | |
0c20a65f | 4622 | gen_move_insn (rtx x, rtx y) |
77c9c6c2 | 4623 | { |
e3654226 | 4624 | rtx seq; |
77c9c6c2 | 4625 | |
e3654226 RS |
4626 | start_sequence (); |
4627 | emit_move_insn_1 (x, y); | |
2f937369 | 4628 | seq = get_insns (); |
e3654226 RS |
4629 | end_sequence (); |
4630 | return seq; | |
77c9c6c2 RK |
4631 | } |
4632 | \f | |
34e56753 RS |
4633 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4634 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4635 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
77c9c6c2 | 4636 | |
34e56753 | 4637 | enum insn_code |
0c20a65f AJ |
4638 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4639 | int unsignedp) | |
77c9c6c2 | 4640 | { |
6dd12198 SE |
4641 | #ifdef HAVE_ptr_extend |
4642 | if (unsignedp < 0) | |
4643 | return CODE_FOR_ptr_extend; | |
4644 | else | |
4645 | #endif | |
4646 | return extendtab[(int) to_mode][(int) from_mode][unsignedp != 0]; | |
77c9c6c2 RK |
4647 | } |
4648 | ||
4649 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4650 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4651 | ||
4652 | rtx | |
0c20a65f AJ |
4653 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4654 | enum machine_mode mfrom, int unsignedp) | |
77c9c6c2 | 4655 | { |
678164a5 | 4656 | return (GEN_FCN (extendtab[(int) mto][(int) mfrom][unsignedp != 0]) (x, y)); |
77c9c6c2 | 4657 | } |
77c9c6c2 RK |
4658 | \f |
4659 | /* can_fix_p and can_float_p say whether the target machine | |
4660 | can directly convert a given fixed point type to | |
4661 | a given floating point type, or vice versa. | |
4662 | The returned value is the CODE_FOR_... value to use, | |
5d81dc5b | 4663 | or CODE_FOR_nothing if these modes cannot be directly converted. |
77c9c6c2 | 4664 | |
5d81dc5b | 4665 | *TRUNCP_PTR is set to 1 if it is necessary to output |
77c9c6c2 RK |
4666 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4667 | ||
4668 | static enum insn_code | |
0c20a65f AJ |
4669 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4670 | int unsignedp, int *truncp_ptr) | |
77c9c6c2 RK |
4671 | { |
4672 | *truncp_ptr = 0; | |
678164a5 RK |
4673 | if (fixtrunctab[(int) fltmode][(int) fixmode][unsignedp != 0] |
4674 | != CODE_FOR_nothing) | |
4675 | return fixtrunctab[(int) fltmode][(int) fixmode][unsignedp != 0]; | |
77c9c6c2 RK |
4676 | |
4677 | if (ftrunc_optab->handlers[(int) fltmode].insn_code != CODE_FOR_nothing) | |
4678 | { | |
4679 | *truncp_ptr = 1; | |
678164a5 | 4680 | return fixtab[(int) fltmode][(int) fixmode][unsignedp != 0]; |
77c9c6c2 RK |
4681 | } |
4682 | return CODE_FOR_nothing; | |
4683 | } | |
4684 | ||
4685 | static enum insn_code | |
0c20a65f AJ |
4686 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4687 | int unsignedp) | |
77c9c6c2 | 4688 | { |
678164a5 | 4689 | return floattab[(int) fltmode][(int) fixmode][unsignedp != 0]; |
77c9c6c2 | 4690 | } |
77c9c6c2 RK |
4691 | \f |
4692 | /* Generate code to convert FROM to floating point | |
34e56753 | 4693 | and store in TO. FROM must be fixed point and not VOIDmode. |
77c9c6c2 RK |
4694 | UNSIGNEDP nonzero means regard FROM as unsigned. |
4695 | Normally this is done by correcting the final value | |
4696 | if it is negative. */ | |
4697 | ||
4698 | void | |
0c20a65f | 4699 | expand_float (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4700 | { |
4701 | enum insn_code icode; | |
b3694847 | 4702 | rtx target = to; |
77c9c6c2 RK |
4703 | enum machine_mode fmode, imode; |
4704 | ||
34e56753 RS |
4705 | /* Crash now, because we won't be able to decide which mode to use. */ |
4706 | if (GET_MODE (from) == VOIDmode) | |
4707 | abort (); | |
4708 | ||
77c9c6c2 RK |
4709 | /* Look for an insn to do the conversion. Do it in the specified |
4710 | modes if possible; otherwise convert either input, output or both to | |
4711 | wider mode. If the integer mode is wider than the mode of FROM, | |
4712 | we can do the conversion signed even if the input is unsigned. */ | |
4713 | ||
7bf0a593 AP |
4714 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4715 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4716 | for (imode = GET_MODE (from); imode != VOIDmode; | |
4717 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4718 | { |
4719 | int doing_unsigned = unsignedp; | |
4720 | ||
5ba02ca6 GK |
4721 | if (fmode != GET_MODE (to) |
4722 | && significand_size (fmode) < GET_MODE_BITSIZE (GET_MODE (from))) | |
4723 | continue; | |
4724 | ||
77c9c6c2 RK |
4725 | icode = can_float_p (fmode, imode, unsignedp); |
4726 | if (icode == CODE_FOR_nothing && imode != GET_MODE (from) && unsignedp) | |
4727 | icode = can_float_p (fmode, imode, 0), doing_unsigned = 0; | |
4728 | ||
4729 | if (icode != CODE_FOR_nothing) | |
4730 | { | |
4731 | to = protect_from_queue (to, 1); | |
06e40b26 | 4732 | from = protect_from_queue (from, 0); |
77c9c6c2 RK |
4733 | |
4734 | if (imode != GET_MODE (from)) | |
4735 | from = convert_to_mode (imode, from, unsignedp); | |
77c9c6c2 RK |
4736 | |
4737 | if (fmode != GET_MODE (to)) | |
4738 | target = gen_reg_rtx (fmode); | |
4739 | ||
4740 | emit_unop_insn (icode, target, from, | |
4741 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
4742 | ||
4743 | if (target != to) | |
4744 | convert_move (to, target, 0); | |
4745 | return; | |
4746 | } | |
7e1a450d | 4747 | } |
77c9c6c2 | 4748 | |
77c9c6c2 RK |
4749 | /* Unsigned integer, and no way to convert directly. |
4750 | Convert as signed, then conditionally adjust the result. */ | |
4751 | if (unsignedp) | |
4752 | { | |
4753 | rtx label = gen_label_rtx (); | |
4754 | rtx temp; | |
4755 | REAL_VALUE_TYPE offset; | |
4756 | ||
4757 | emit_queue (); | |
4758 | ||
4759 | to = protect_from_queue (to, 1); | |
4760 | from = protect_from_queue (from, 0); | |
4761 | ||
4762 | if (flag_force_mem) | |
4763 | from = force_not_mem (from); | |
4764 | ||
c95c47f3 PE |
4765 | /* Look for a usable floating mode FMODE wider than the source and at |
4766 | least as wide as the target. Using FMODE will avoid rounding woes | |
4767 | with unsigned values greater than the signed maximum value. */ | |
70864443 | 4768 | |
c95c47f3 PE |
4769 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4770 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4771 | if (GET_MODE_BITSIZE (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) | |
4772 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) | |
4773 | break; | |
a48fb61b | 4774 | |
c95c47f3 PE |
4775 | if (fmode == VOIDmode) |
4776 | { | |
a48fb61b | 4777 | /* There is no such mode. Pretend the target is wide enough. */ |
c95c47f3 | 4778 | fmode = GET_MODE (to); |
a48fb61b | 4779 | |
0f41302f | 4780 | /* Avoid double-rounding when TO is narrower than FROM. */ |
a48fb61b RK |
4781 | if ((significand_size (fmode) + 1) |
4782 | < GET_MODE_BITSIZE (GET_MODE (from))) | |
4783 | { | |
4784 | rtx temp1; | |
4785 | rtx neglabel = gen_label_rtx (); | |
4786 | ||
0c20a65f | 4787 | /* Don't use TARGET if it isn't a register, is a hard register, |
70864443 | 4788 | or is the wrong mode. */ |
44f51d4a | 4789 | if (GET_CODE (target) != REG |
70864443 RK |
4790 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
4791 | || GET_MODE (target) != fmode) | |
44f51d4a RK |
4792 | target = gen_reg_rtx (fmode); |
4793 | ||
a48fb61b RK |
4794 | imode = GET_MODE (from); |
4795 | do_pending_stack_adjust (); | |
4796 | ||
4797 | /* Test whether the sign bit is set. */ | |
1c0290ea | 4798 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
a06ef755 | 4799 | 0, neglabel); |
a48fb61b RK |
4800 | |
4801 | /* The sign bit is not set. Convert as signed. */ | |
4802 | expand_float (target, from, 0); | |
4803 | emit_jump_insn (gen_jump (label)); | |
2ad79487 | 4804 | emit_barrier (); |
a48fb61b RK |
4805 | |
4806 | /* The sign bit is set. | |
4807 | Convert to a usable (positive signed) value by shifting right | |
4808 | one bit, while remembering if a nonzero bit was shifted | |
4809 | out; i.e., compute (from & 1) | (from >> 1). */ | |
4810 | ||
4811 | emit_label (neglabel); | |
4812 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
70864443 | 4813 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
73d9a835 RK |
4814 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, integer_one_node, |
4815 | NULL_RTX, 1); | |
0c20a65f | 4816 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
70864443 | 4817 | OPTAB_LIB_WIDEN); |
a48fb61b RK |
4818 | expand_float (target, temp, 0); |
4819 | ||
4820 | /* Multiply by 2 to undo the shift above. */ | |
a93738eb | 4821 | temp = expand_binop (fmode, add_optab, target, target, |
7e1a450d | 4822 | target, 0, OPTAB_LIB_WIDEN); |
a93738eb RK |
4823 | if (temp != target) |
4824 | emit_move_insn (target, temp); | |
4825 | ||
a48fb61b RK |
4826 | do_pending_stack_adjust (); |
4827 | emit_label (label); | |
4828 | goto done; | |
4829 | } | |
c95c47f3 PE |
4830 | } |
4831 | ||
77c9c6c2 RK |
4832 | /* If we are about to do some arithmetic to correct for an |
4833 | unsigned operand, do it in a pseudo-register. */ | |
4834 | ||
c95c47f3 | 4835 | if (GET_MODE (to) != fmode |
70864443 | 4836 | || GET_CODE (to) != REG || REGNO (to) < FIRST_PSEUDO_REGISTER) |
c95c47f3 | 4837 | target = gen_reg_rtx (fmode); |
77c9c6c2 RK |
4838 | |
4839 | /* Convert as signed integer to floating. */ | |
4840 | expand_float (target, from, 0); | |
4841 | ||
4842 | /* If FROM is negative (and therefore TO is negative), | |
4843 | correct its value by 2**bitwidth. */ | |
4844 | ||
4845 | do_pending_stack_adjust (); | |
c5d5d461 | 4846 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 4847 | 0, label); |
70864443 | 4848 | |
0c20a65f | 4849 | |
efdc7e19 | 4850 | real_2expN (&offset, GET_MODE_BITSIZE (GET_MODE (from))); |
c95c47f3 | 4851 | temp = expand_binop (fmode, add_optab, target, |
30d88916 | 4852 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
77c9c6c2 RK |
4853 | target, 0, OPTAB_LIB_WIDEN); |
4854 | if (temp != target) | |
4855 | emit_move_insn (target, temp); | |
a48fb61b | 4856 | |
77c9c6c2 RK |
4857 | do_pending_stack_adjust (); |
4858 | emit_label (label); | |
70864443 | 4859 | goto done; |
77c9c6c2 | 4860 | } |
77c9c6c2 | 4861 | |
560f3f8a | 4862 | /* No hardware instruction available; call a library routine to convert from |
b092b471 | 4863 | SImode, DImode, or TImode into SFmode, DFmode, XFmode, or TFmode. */ |
77c9c6c2 | 4864 | { |
6bce1b78 | 4865 | rtx libfcn; |
77c9c6c2 | 4866 | rtx insns; |
9a7f678c | 4867 | rtx value; |
77c9c6c2 RK |
4868 | |
4869 | to = protect_from_queue (to, 1); | |
06e40b26 | 4870 | from = protect_from_queue (from, 0); |
77c9c6c2 RK |
4871 | |
4872 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) | |
4873 | from = convert_to_mode (SImode, from, unsignedp); | |
77c9c6c2 RK |
4874 | |
4875 | if (flag_force_mem) | |
4876 | from = force_not_mem (from); | |
4877 | ||
4878 | if (GET_MODE (to) == SFmode) | |
4879 | { | |
4880 | if (GET_MODE (from) == SImode) | |
6bce1b78 | 4881 | libfcn = floatsisf_libfunc; |
77c9c6c2 | 4882 | else if (GET_MODE (from) == DImode) |
6bce1b78 | 4883 | libfcn = floatdisf_libfunc; |
b092b471 JW |
4884 | else if (GET_MODE (from) == TImode) |
4885 | libfcn = floattisf_libfunc; | |
77c9c6c2 RK |
4886 | else |
4887 | abort (); | |
4888 | } | |
4889 | else if (GET_MODE (to) == DFmode) | |
4890 | { | |
4891 | if (GET_MODE (from) == SImode) | |
6bce1b78 | 4892 | libfcn = floatsidf_libfunc; |
77c9c6c2 | 4893 | else if (GET_MODE (from) == DImode) |
6bce1b78 | 4894 | libfcn = floatdidf_libfunc; |
b092b471 JW |
4895 | else if (GET_MODE (from) == TImode) |
4896 | libfcn = floattidf_libfunc; | |
4897 | else | |
4898 | abort (); | |
4899 | } | |
4900 | else if (GET_MODE (to) == XFmode) | |
4901 | { | |
4902 | if (GET_MODE (from) == SImode) | |
4903 | libfcn = floatsixf_libfunc; | |
4904 | else if (GET_MODE (from) == DImode) | |
4905 | libfcn = floatdixf_libfunc; | |
4906 | else if (GET_MODE (from) == TImode) | |
4907 | libfcn = floattixf_libfunc; | |
4908 | else | |
4909 | abort (); | |
4910 | } | |
4911 | else if (GET_MODE (to) == TFmode) | |
4912 | { | |
4913 | if (GET_MODE (from) == SImode) | |
4914 | libfcn = floatsitf_libfunc; | |
4915 | else if (GET_MODE (from) == DImode) | |
4916 | libfcn = floatditf_libfunc; | |
4917 | else if (GET_MODE (from) == TImode) | |
4918 | libfcn = floattitf_libfunc; | |
77c9c6c2 RK |
4919 | else |
4920 | abort (); | |
4921 | } | |
4922 | else | |
4923 | abort (); | |
4924 | ||
4925 | start_sequence (); | |
4926 | ||
ebb1b59a BS |
4927 | value = emit_library_call_value (libfcn, NULL_RTX, LCT_CONST, |
4928 | GET_MODE (to), 1, from, | |
4929 | GET_MODE (from)); | |
77c9c6c2 RK |
4930 | insns = get_insns (); |
4931 | end_sequence (); | |
4932 | ||
9a7f678c | 4933 | emit_libcall_block (insns, target, value, |
9e6a5703 | 4934 | gen_rtx_FLOAT (GET_MODE (to), from)); |
77c9c6c2 RK |
4935 | } |
4936 | ||
a48fb61b RK |
4937 | done: |
4938 | ||
77c9c6c2 RK |
4939 | /* Copy result to requested destination |
4940 | if we have been computing in a temp location. */ | |
4941 | ||
4942 | if (target != to) | |
4943 | { | |
4944 | if (GET_MODE (target) == GET_MODE (to)) | |
4945 | emit_move_insn (to, target); | |
4946 | else | |
4947 | convert_move (to, target, 0); | |
4948 | } | |
4949 | } | |
4950 | \f | |
4951 | /* expand_fix: generate code to convert FROM to fixed point | |
4952 | and store in TO. FROM must be floating point. */ | |
4953 | ||
4954 | static rtx | |
0c20a65f | 4955 | ftruncify (rtx x) |
77c9c6c2 RK |
4956 | { |
4957 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
4958 | return expand_unop (GET_MODE (x), ftrunc_optab, x, temp, 0); | |
4959 | } | |
4960 | ||
4961 | void | |
0c20a65f | 4962 | expand_fix (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4963 | { |
4964 | enum insn_code icode; | |
b3694847 | 4965 | rtx target = to; |
77c9c6c2 RK |
4966 | enum machine_mode fmode, imode; |
4967 | int must_trunc = 0; | |
6bce1b78 | 4968 | rtx libfcn = 0; |
77c9c6c2 RK |
4969 | |
4970 | /* We first try to find a pair of modes, one real and one integer, at | |
4971 | least as wide as FROM and TO, respectively, in which we can open-code | |
4972 | this conversion. If the integer mode is wider than the mode of TO, | |
4973 | we can do the conversion either signed or unsigned. */ | |
4974 | ||
3987b9db JH |
4975 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
4976 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4977 | for (imode = GET_MODE (to); imode != VOIDmode; | |
4978 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4979 | { |
4980 | int doing_unsigned = unsignedp; | |
4981 | ||
4982 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
4983 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
4984 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
4985 | ||
4986 | if (icode != CODE_FOR_nothing) | |
4987 | { | |
4988 | to = protect_from_queue (to, 1); | |
06e40b26 | 4989 | from = protect_from_queue (from, 0); |
77c9c6c2 RK |
4990 | |
4991 | if (fmode != GET_MODE (from)) | |
4992 | from = convert_to_mode (fmode, from, 0); | |
77c9c6c2 RK |
4993 | |
4994 | if (must_trunc) | |
4995 | from = ftruncify (from); | |
4996 | ||
4997 | if (imode != GET_MODE (to)) | |
4998 | target = gen_reg_rtx (imode); | |
4999 | ||
5000 | emit_unop_insn (icode, target, from, | |
5001 | doing_unsigned ? UNSIGNED_FIX : FIX); | |
5002 | if (target != to) | |
5003 | convert_move (to, target, unsignedp); | |
5004 | return; | |
5005 | } | |
5006 | } | |
5007 | ||
77c9c6c2 RK |
5008 | /* For an unsigned conversion, there is one more way to do it. |
5009 | If we have a signed conversion, we generate code that compares | |
5010 | the real value to the largest representable positive number. If if | |
5011 | is smaller, the conversion is done normally. Otherwise, subtract | |
5012 | one plus the highest signed number, convert, and add it back. | |
5013 | ||
5014 | We only need to check all real modes, since we know we didn't find | |
0c20a65f | 5015 | anything with a wider integer mode. |
0d446150 JH |
5016 | |
5017 | This code used to extend FP value into mode wider than the destination. | |
5018 | This is not needed. Consider, for instance conversion from SFmode | |
5019 | into DImode. | |
5020 | ||
5021 | The hot path trought the code is dealing with inputs smaller than 2^63 | |
5022 | and doing just the conversion, so there is no bits to lose. | |
5023 | ||
5024 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
5025 | inclusive. (as for other imput overflow happens and result is undefined) | |
e0bb17a8 | 5026 | So we know that the most important bit set in mantissa corresponds to |
0d446150 JH |
5027 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
5028 | simply clears out that bit. The rest is trivial. */ | |
77c9c6c2 | 5029 | |
b1ec3c92 | 5030 | if (unsignedp && GET_MODE_BITSIZE (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
77c9c6c2 RK |
5031 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5032 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
0d446150 JH |
5033 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, |
5034 | &must_trunc)) | |
77c9c6c2 | 5035 | { |
e9f7ae44 RS |
5036 | int bitsize; |
5037 | REAL_VALUE_TYPE offset; | |
5038 | rtx limit, lab1, lab2, insn; | |
5039 | ||
5040 | bitsize = GET_MODE_BITSIZE (GET_MODE (to)); | |
efdc7e19 | 5041 | real_2expN (&offset, bitsize - 1); |
30d88916 | 5042 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
e9f7ae44 RS |
5043 | lab1 = gen_label_rtx (); |
5044 | lab2 = gen_label_rtx (); | |
77c9c6c2 RK |
5045 | |
5046 | emit_queue (); | |
5047 | to = protect_from_queue (to, 1); | |
5048 | from = protect_from_queue (from, 0); | |
5049 | ||
5050 | if (flag_force_mem) | |
5051 | from = force_not_mem (from); | |
5052 | ||
5053 | if (fmode != GET_MODE (from)) | |
5054 | from = convert_to_mode (fmode, from, 0); | |
5055 | ||
5056 | /* See if we need to do the subtraction. */ | |
5057 | do_pending_stack_adjust (); | |
c5d5d461 | 5058 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 5059 | 0, lab1); |
77c9c6c2 RK |
5060 | |
5061 | /* If not, do the signed "fix" and branch around fixup code. */ | |
5062 | expand_fix (to, from, 0); | |
5063 | emit_jump_insn (gen_jump (lab2)); | |
5064 | emit_barrier (); | |
5065 | ||
5066 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
5067 | then add 2**(N-1). Do the addition using XOR since this | |
5068 | will often generate better code. */ | |
5069 | emit_label (lab1); | |
5070 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
b1ec3c92 | 5071 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
77c9c6c2 RK |
5072 | expand_fix (to, target, 0); |
5073 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2496c7bd LB |
5074 | gen_int_mode |
5075 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
5076 | GET_MODE (to)), | |
77c9c6c2 RK |
5077 | to, 1, OPTAB_LIB_WIDEN); |
5078 | ||
5079 | if (target != to) | |
5080 | emit_move_insn (to, target); | |
5081 | ||
5082 | emit_label (lab2); | |
5083 | ||
02214a5c RK |
5084 | if (mov_optab->handlers[(int) GET_MODE (to)].insn_code |
5085 | != CODE_FOR_nothing) | |
5086 | { | |
5087 | /* Make a place for a REG_NOTE and add it. */ | |
5088 | insn = emit_move_insn (to, to); | |
5fa671cf AM |
5089 | set_unique_reg_note (insn, |
5090 | REG_EQUAL, | |
5091 | gen_rtx_fmt_e (UNSIGNED_FIX, | |
5092 | GET_MODE (to), | |
5093 | copy_rtx (from))); | |
02214a5c | 5094 | } |
c5c76735 | 5095 | |
77c9c6c2 RK |
5096 | return; |
5097 | } | |
77c9c6c2 RK |
5098 | |
5099 | /* We can't do it with an insn, so use a library call. But first ensure | |
5100 | that the mode of TO is at least as wide as SImode, since those are the | |
5101 | only library calls we know about. */ | |
5102 | ||
5103 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
5104 | { | |
5105 | target = gen_reg_rtx (SImode); | |
5106 | ||
5107 | expand_fix (target, from, unsignedp); | |
5108 | } | |
5109 | else if (GET_MODE (from) == SFmode) | |
5110 | { | |
5111 | if (GET_MODE (to) == SImode) | |
6bce1b78 | 5112 | libfcn = unsignedp ? fixunssfsi_libfunc : fixsfsi_libfunc; |
77c9c6c2 | 5113 | else if (GET_MODE (to) == DImode) |
6bce1b78 | 5114 | libfcn = unsignedp ? fixunssfdi_libfunc : fixsfdi_libfunc; |
b092b471 JW |
5115 | else if (GET_MODE (to) == TImode) |
5116 | libfcn = unsignedp ? fixunssfti_libfunc : fixsfti_libfunc; | |
77c9c6c2 RK |
5117 | else |
5118 | abort (); | |
5119 | } | |
5120 | else if (GET_MODE (from) == DFmode) | |
5121 | { | |
5122 | if (GET_MODE (to) == SImode) | |
6bce1b78 | 5123 | libfcn = unsignedp ? fixunsdfsi_libfunc : fixdfsi_libfunc; |
77c9c6c2 | 5124 | else if (GET_MODE (to) == DImode) |
6bce1b78 | 5125 | libfcn = unsignedp ? fixunsdfdi_libfunc : fixdfdi_libfunc; |
b092b471 JW |
5126 | else if (GET_MODE (to) == TImode) |
5127 | libfcn = unsignedp ? fixunsdfti_libfunc : fixdfti_libfunc; | |
5128 | else | |
5129 | abort (); | |
5130 | } | |
5131 | else if (GET_MODE (from) == XFmode) | |
5132 | { | |
5133 | if (GET_MODE (to) == SImode) | |
5134 | libfcn = unsignedp ? fixunsxfsi_libfunc : fixxfsi_libfunc; | |
5135 | else if (GET_MODE (to) == DImode) | |
5136 | libfcn = unsignedp ? fixunsxfdi_libfunc : fixxfdi_libfunc; | |
5137 | else if (GET_MODE (to) == TImode) | |
5138 | libfcn = unsignedp ? fixunsxfti_libfunc : fixxfti_libfunc; | |
5139 | else | |
5140 | abort (); | |
5141 | } | |
5142 | else if (GET_MODE (from) == TFmode) | |
5143 | { | |
5144 | if (GET_MODE (to) == SImode) | |
5145 | libfcn = unsignedp ? fixunstfsi_libfunc : fixtfsi_libfunc; | |
5146 | else if (GET_MODE (to) == DImode) | |
5147 | libfcn = unsignedp ? fixunstfdi_libfunc : fixtfdi_libfunc; | |
5148 | else if (GET_MODE (to) == TImode) | |
5149 | libfcn = unsignedp ? fixunstfti_libfunc : fixtfti_libfunc; | |
77c9c6c2 RK |
5150 | else |
5151 | abort (); | |
5152 | } | |
5153 | else | |
5154 | abort (); | |
5155 | ||
6bce1b78 | 5156 | if (libfcn) |
77c9c6c2 RK |
5157 | { |
5158 | rtx insns; | |
560f3f8a | 5159 | rtx value; |
77c9c6c2 RK |
5160 | |
5161 | to = protect_from_queue (to, 1); | |
5162 | from = protect_from_queue (from, 0); | |
5163 | ||
5164 | if (flag_force_mem) | |
5165 | from = force_not_mem (from); | |
5166 | ||
5167 | start_sequence (); | |
5168 | ||
ebb1b59a BS |
5169 | value = emit_library_call_value (libfcn, NULL_RTX, LCT_CONST, |
5170 | GET_MODE (to), 1, from, | |
5171 | GET_MODE (from)); | |
77c9c6c2 RK |
5172 | insns = get_insns (); |
5173 | end_sequence (); | |
5174 | ||
560f3f8a | 5175 | emit_libcall_block (insns, target, value, |
9e6a5703 JC |
5176 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
5177 | GET_MODE (to), from)); | |
77c9c6c2 | 5178 | } |
0c20a65f | 5179 | |
3e53ea48 RK |
5180 | if (target != to) |
5181 | { | |
5182 | if (GET_MODE (to) == GET_MODE (target)) | |
5183 | emit_move_insn (to, target); | |
5184 | else | |
5185 | convert_move (to, target, 0); | |
5186 | } | |
77c9c6c2 RK |
5187 | } |
5188 | \f | |
ef89d648 ZW |
5189 | /* Report whether we have an instruction to perform the operation |
5190 | specified by CODE on operands of mode MODE. */ | |
5191 | int | |
0c20a65f | 5192 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ef89d648 ZW |
5193 | { |
5194 | return (code_to_optab[(int) code] != 0 | |
5195 | && (code_to_optab[(int) code]->handlers[(int) mode].insn_code | |
5196 | != CODE_FOR_nothing)); | |
5197 | } | |
5198 | ||
5199 | /* Create a blank optab. */ | |
5200 | static optab | |
0c20a65f | 5201 | new_optab (void) |
77c9c6c2 RK |
5202 | { |
5203 | int i; | |
e2500fed | 5204 | optab op = (optab) ggc_alloc (sizeof (struct optab)); |
77c9c6c2 RK |
5205 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
5206 | { | |
5207 | op->handlers[i].insn_code = CODE_FOR_nothing; | |
5208 | op->handlers[i].libfunc = 0; | |
5209 | } | |
377017c4 | 5210 | |
ef89d648 ZW |
5211 | return op; |
5212 | } | |
377017c4 | 5213 | |
ef89d648 ZW |
5214 | /* Same, but fill in its code as CODE, and write it into the |
5215 | code_to_optab table. */ | |
5216 | static inline optab | |
0c20a65f | 5217 | init_optab (enum rtx_code code) |
ef89d648 ZW |
5218 | { |
5219 | optab op = new_optab (); | |
5220 | op->code = code; | |
5221 | code_to_optab[(int) code] = op; | |
5222 | return op; | |
5223 | } | |
5224 | ||
5225 | /* Same, but fill in its code as CODE, and do _not_ write it into | |
5226 | the code_to_optab table. */ | |
5227 | static inline optab | |
0c20a65f | 5228 | init_optabv (enum rtx_code code) |
ef89d648 ZW |
5229 | { |
5230 | optab op = new_optab (); | |
5231 | op->code = code; | |
77c9c6c2 RK |
5232 | return op; |
5233 | } | |
5234 | ||
b092b471 JW |
5235 | /* Initialize the libfunc fields of an entire group of entries in some |
5236 | optab. Each entry is set equal to a string consisting of a leading | |
5237 | pair of underscores followed by a generic operation name followed by | |
5238 | a mode name (downshifted to lower case) followed by a single character | |
5239 | representing the number of operands for the given operation (which is | |
5240 | usually one of the characters '2', '3', or '4'). | |
5241 | ||
5242 | OPTABLE is the table in which libfunc fields are to be initialized. | |
5243 | FIRST_MODE is the first machine mode index in the given optab to | |
5244 | initialize. | |
5245 | LAST_MODE is the last machine mode index in the given optab to | |
5246 | initialize. | |
5247 | OPNAME is the generic (string) name of the operation. | |
5248 | SUFFIX is the character which specifies the number of operands for | |
5249 | the given generic operation. | |
5250 | */ | |
5251 | ||
5252 | static void | |
0c20a65f AJ |
5253 | init_libfuncs (optab optable, int first_mode, int last_mode, |
5254 | const char *opname, int suffix) | |
b092b471 | 5255 | { |
b3694847 SS |
5256 | int mode; |
5257 | unsigned opname_len = strlen (opname); | |
b092b471 | 5258 | |
fe0035ff RS |
5259 | for (mode = first_mode; (int) mode <= (int) last_mode; |
5260 | mode = (enum machine_mode) ((int) mode + 1)) | |
b092b471 | 5261 | { |
7e1a450d | 5262 | const char *mname = GET_MODE_NAME (mode); |
b3694847 SS |
5263 | unsigned mname_len = strlen (mname); |
5264 | char *libfunc_name = alloca (2 + opname_len + mname_len + 1 + 1); | |
5265 | char *p; | |
5266 | const char *q; | |
b092b471 JW |
5267 | |
5268 | p = libfunc_name; | |
5269 | *p++ = '_'; | |
5270 | *p++ = '_'; | |
5271 | for (q = opname; *q; ) | |
5272 | *p++ = *q++; | |
5273 | for (q = mname; *q; q++) | |
92a438d1 | 5274 | *p++ = TOLOWER (*q); |
b092b471 | 5275 | *p++ = suffix; |
520a57c8 | 5276 | *p = '\0'; |
76095e2f | 5277 | |
b092b471 | 5278 | optable->handlers[(int) mode].libfunc |
68d28100 | 5279 | = init_one_libfunc (ggc_alloc_string (libfunc_name, p - libfunc_name)); |
b092b471 JW |
5280 | } |
5281 | } | |
5282 | ||
5283 | /* Initialize the libfunc fields of an entire group of entries in some | |
5284 | optab which correspond to all integer mode operations. The parameters | |
5285 | have the same meaning as similarly named ones for the `init_libfuncs' | |
5286 | routine. (See above). */ | |
5287 | ||
5288 | static void | |
0c20a65f | 5289 | init_integral_libfuncs (optab optable, const char *opname, int suffix) |
b092b471 | 5290 | { |
c0510d84 DD |
5291 | int maxsize = 2*BITS_PER_WORD; |
5292 | if (maxsize < LONG_LONG_TYPE_SIZE) | |
5293 | maxsize = LONG_LONG_TYPE_SIZE; | |
8275b011 | 5294 | init_libfuncs (optable, word_mode, |
c0510d84 | 5295 | mode_for_size (maxsize, MODE_INT, 0), |
8275b011 | 5296 | opname, suffix); |
b092b471 JW |
5297 | } |
5298 | ||
5299 | /* Initialize the libfunc fields of an entire group of entries in some | |
5300 | optab which correspond to all real mode operations. The parameters | |
5301 | have the same meaning as similarly named ones for the `init_libfuncs' | |
5302 | routine. (See above). */ | |
5303 | ||
5304 | static void | |
0c20a65f | 5305 | init_floating_libfuncs (optab optable, const char *opname, int suffix) |
b092b471 | 5306 | { |
8275b011 RH |
5307 | enum machine_mode fmode, dmode, lmode; |
5308 | ||
5309 | fmode = float_type_node ? TYPE_MODE (float_type_node) : VOIDmode; | |
5310 | dmode = double_type_node ? TYPE_MODE (double_type_node) : VOIDmode; | |
5311 | lmode = long_double_type_node ? TYPE_MODE (long_double_type_node) : VOIDmode; | |
5312 | ||
5313 | if (fmode != VOIDmode) | |
5314 | init_libfuncs (optable, fmode, fmode, opname, suffix); | |
5315 | if (dmode != fmode && dmode != VOIDmode) | |
5316 | init_libfuncs (optable, dmode, dmode, opname, suffix); | |
5317 | if (lmode != dmode && lmode != VOIDmode) | |
5318 | init_libfuncs (optable, lmode, lmode, opname, suffix); | |
b092b471 JW |
5319 | } |
5320 | ||
76095e2f | 5321 | rtx |
0c20a65f | 5322 | init_one_libfunc (const char *name) |
76095e2f | 5323 | { |
52859c77 RH |
5324 | rtx symbol; |
5325 | ||
fb49053f RH |
5326 | /* Create a FUNCTION_DECL that can be passed to |
5327 | targetm.encode_section_info. */ | |
ee1315aa | 5328 | /* ??? We don't have any type information except for this is |
9c2f7166 | 5329 | a function. Pretend this is "int foo()". */ |
ee1315aa | 5330 | tree decl = build_decl (FUNCTION_DECL, get_identifier (name), |
9c2f7166 | 5331 | build_function_type (integer_type_node, NULL_TREE)); |
ee1315aa RH |
5332 | DECL_ARTIFICIAL (decl) = 1; |
5333 | DECL_EXTERNAL (decl) = 1; | |
5334 | TREE_PUBLIC (decl) = 1; | |
5335 | ||
52859c77 RH |
5336 | symbol = XEXP (DECL_RTL (decl), 0); |
5337 | ||
5338 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
5339 | are the flags assigned by targetm.encode_section_info. */ | |
5340 | SYMBOL_REF_DECL (symbol) = 0; | |
5341 | ||
5342 | return symbol; | |
76095e2f RH |
5343 | } |
5344 | ||
77c9c6c2 RK |
5345 | /* Call this once to initialize the contents of the optabs |
5346 | appropriately for the current target machine. */ | |
5347 | ||
5348 | void | |
0c20a65f | 5349 | init_optabs (void) |
77c9c6c2 | 5350 | { |
b6a1cbae | 5351 | unsigned int i, j, k; |
77c9c6c2 | 5352 | |
5d81dc5b | 5353 | /* Start by initializing all tables to contain CODE_FOR_nothing. */ |
77c9c6c2 | 5354 | |
b6a1cbae GM |
5355 | for (i = 0; i < ARRAY_SIZE (fixtab); i++) |
5356 | for (j = 0; j < ARRAY_SIZE (fixtab[0]); j++) | |
5357 | for (k = 0; k < ARRAY_SIZE (fixtab[0][0]); k++) | |
5358 | fixtab[i][j][k] = CODE_FOR_nothing; | |
5359 | ||
5360 | for (i = 0; i < ARRAY_SIZE (fixtrunctab); i++) | |
5361 | for (j = 0; j < ARRAY_SIZE (fixtrunctab[0]); j++) | |
5362 | for (k = 0; k < ARRAY_SIZE (fixtrunctab[0][0]); k++) | |
5363 | fixtrunctab[i][j][k] = CODE_FOR_nothing; | |
5364 | ||
5365 | for (i = 0; i < ARRAY_SIZE (floattab); i++) | |
5366 | for (j = 0; j < ARRAY_SIZE (floattab[0]); j++) | |
5367 | for (k = 0; k < ARRAY_SIZE (floattab[0][0]); k++) | |
5368 | floattab[i][j][k] = CODE_FOR_nothing; | |
5369 | ||
5370 | for (i = 0; i < ARRAY_SIZE (extendtab); i++) | |
5371 | for (j = 0; j < ARRAY_SIZE (extendtab[0]); j++) | |
5372 | for (k = 0; k < ARRAY_SIZE (extendtab[0][0]); k++) | |
5373 | extendtab[i][j][k] = CODE_FOR_nothing; | |
5d81dc5b RK |
5374 | |
5375 | for (i = 0; i < NUM_RTX_CODE; i++) | |
5376 | setcc_gen_code[i] = CODE_FOR_nothing; | |
5377 | ||
49c4584c DE |
5378 | #ifdef HAVE_conditional_move |
5379 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
5380 | movcc_gen_code[i] = CODE_FOR_nothing; | |
5381 | #endif | |
5382 | ||
5d81dc5b | 5383 | add_optab = init_optab (PLUS); |
ef89d648 | 5384 | addv_optab = init_optabv (PLUS); |
5d81dc5b | 5385 | sub_optab = init_optab (MINUS); |
ef89d648 | 5386 | subv_optab = init_optabv (MINUS); |
5d81dc5b | 5387 | smul_optab = init_optab (MULT); |
ef89d648 | 5388 | smulv_optab = init_optabv (MULT); |
5035bbfe TG |
5389 | smul_highpart_optab = init_optab (UNKNOWN); |
5390 | umul_highpart_optab = init_optab (UNKNOWN); | |
5d81dc5b RK |
5391 | smul_widen_optab = init_optab (UNKNOWN); |
5392 | umul_widen_optab = init_optab (UNKNOWN); | |
5393 | sdiv_optab = init_optab (DIV); | |
ef89d648 | 5394 | sdivv_optab = init_optabv (DIV); |
5d81dc5b RK |
5395 | sdivmod_optab = init_optab (UNKNOWN); |
5396 | udiv_optab = init_optab (UDIV); | |
5397 | udivmod_optab = init_optab (UNKNOWN); | |
5398 | smod_optab = init_optab (MOD); | |
5399 | umod_optab = init_optab (UMOD); | |
77c9c6c2 RK |
5400 | ftrunc_optab = init_optab (UNKNOWN); |
5401 | and_optab = init_optab (AND); | |
5402 | ior_optab = init_optab (IOR); | |
5403 | xor_optab = init_optab (XOR); | |
5404 | ashl_optab = init_optab (ASHIFT); | |
5405 | ashr_optab = init_optab (ASHIFTRT); | |
77c9c6c2 RK |
5406 | lshr_optab = init_optab (LSHIFTRT); |
5407 | rotl_optab = init_optab (ROTATE); | |
5408 | rotr_optab = init_optab (ROTATERT); | |
5409 | smin_optab = init_optab (SMIN); | |
5410 | smax_optab = init_optab (SMAX); | |
5411 | umin_optab = init_optab (UMIN); | |
5412 | umax_optab = init_optab (UMAX); | |
b5e01d4b RS |
5413 | pow_optab = init_optab (UNKNOWN); |
5414 | atan2_optab = init_optab (UNKNOWN); | |
ef89d648 ZW |
5415 | |
5416 | /* These three have codes assigned exclusively for the sake of | |
5417 | have_insn_for. */ | |
5418 | mov_optab = init_optab (SET); | |
5419 | movstrict_optab = init_optab (STRICT_LOW_PART); | |
5420 | cmp_optab = init_optab (COMPARE); | |
5421 | ||
77c9c6c2 RK |
5422 | ucmp_optab = init_optab (UNKNOWN); |
5423 | tst_optab = init_optab (UNKNOWN); | |
5424 | neg_optab = init_optab (NEG); | |
ef89d648 | 5425 | negv_optab = init_optabv (NEG); |
77c9c6c2 | 5426 | abs_optab = init_optab (ABS); |
ef89d648 | 5427 | absv_optab = init_optabv (ABS); |
068f5dea | 5428 | addcc_optab = init_optab (UNKNOWN); |
77c9c6c2 RK |
5429 | one_cmpl_optab = init_optab (NOT); |
5430 | ffs_optab = init_optab (FFS); | |
2928cd7a RH |
5431 | clz_optab = init_optab (CLZ); |
5432 | ctz_optab = init_optab (CTZ); | |
5433 | popcount_optab = init_optab (POPCOUNT); | |
5434 | parity_optab = init_optab (PARITY); | |
d45cf215 | 5435 | sqrt_optab = init_optab (SQRT); |
4977bab6 ZW |
5436 | floor_optab = init_optab (UNKNOWN); |
5437 | ceil_optab = init_optab (UNKNOWN); | |
5438 | round_optab = init_optab (UNKNOWN); | |
5439 | trunc_optab = init_optab (UNKNOWN); | |
5440 | nearbyint_optab = init_optab (UNKNOWN); | |
28cf078d JVA |
5441 | sin_optab = init_optab (UNKNOWN); |
5442 | cos_optab = init_optab (UNKNOWN); | |
e7b489c8 RS |
5443 | exp_optab = init_optab (UNKNOWN); |
5444 | log_optab = init_optab (UNKNOWN); | |
82d397c7 RS |
5445 | tan_optab = init_optab (UNKNOWN); |
5446 | atan_optab = init_optab (UNKNOWN); | |
19c3fc24 | 5447 | strlen_optab = init_optab (UNKNOWN); |
1c0290ea BS |
5448 | cbranch_optab = init_optab (UNKNOWN); |
5449 | cmov_optab = init_optab (UNKNOWN); | |
5450 | cstore_optab = init_optab (UNKNOWN); | |
371b8fc0 | 5451 | push_optab = init_optab (UNKNOWN); |
77c9c6c2 | 5452 | |
5d81dc5b RK |
5453 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
5454 | { | |
5455 | movstr_optab[i] = CODE_FOR_nothing; | |
45169d12 | 5456 | clrstr_optab[i] = CODE_FOR_nothing; |
5d81dc5b RK |
5457 | |
5458 | #ifdef HAVE_SECONDARY_RELOADS | |
5459 | reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing; | |
77c9c6c2 | 5460 | #endif |
5d81dc5b RK |
5461 | } |
5462 | ||
5463 | /* Fill in the optabs with the insns we support. */ | |
5464 | init_all_optabs (); | |
5465 | ||
5466 | #ifdef FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
5467 | /* This flag says the same insns that convert to a signed fixnum | |
5468 | also convert validly to an unsigned one. */ | |
5469 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
5470 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
5471 | fixtrunctab[i][j][1] = fixtrunctab[i][j][0]; | |
b092b471 | 5472 | #endif |
5d81dc5b | 5473 | |
5d81dc5b | 5474 | /* Initialize the optabs with the names of the library functions. */ |
b092b471 JW |
5475 | init_integral_libfuncs (add_optab, "add", '3'); |
5476 | init_floating_libfuncs (add_optab, "add", '3'); | |
91ce572a CC |
5477 | init_integral_libfuncs (addv_optab, "addv", '3'); |
5478 | init_floating_libfuncs (addv_optab, "add", '3'); | |
b092b471 JW |
5479 | init_integral_libfuncs (sub_optab, "sub", '3'); |
5480 | init_floating_libfuncs (sub_optab, "sub", '3'); | |
91ce572a CC |
5481 | init_integral_libfuncs (subv_optab, "subv", '3'); |
5482 | init_floating_libfuncs (subv_optab, "sub", '3'); | |
b092b471 JW |
5483 | init_integral_libfuncs (smul_optab, "mul", '3'); |
5484 | init_floating_libfuncs (smul_optab, "mul", '3'); | |
91ce572a CC |
5485 | init_integral_libfuncs (smulv_optab, "mulv", '3'); |
5486 | init_floating_libfuncs (smulv_optab, "mul", '3'); | |
5d81dc5b | 5487 | init_integral_libfuncs (sdiv_optab, "div", '3'); |
ef89d648 | 5488 | init_floating_libfuncs (sdiv_optab, "div", '3'); |
91ce572a | 5489 | init_integral_libfuncs (sdivv_optab, "divv", '3'); |
5d81dc5b RK |
5490 | init_integral_libfuncs (udiv_optab, "udiv", '3'); |
5491 | init_integral_libfuncs (sdivmod_optab, "divmod", '4'); | |
5492 | init_integral_libfuncs (udivmod_optab, "udivmod", '4'); | |
5493 | init_integral_libfuncs (smod_optab, "mod", '3'); | |
5494 | init_integral_libfuncs (umod_optab, "umod", '3'); | |
5d81dc5b RK |
5495 | init_floating_libfuncs (ftrunc_optab, "ftrunc", '2'); |
5496 | init_integral_libfuncs (and_optab, "and", '3'); | |
5497 | init_integral_libfuncs (ior_optab, "ior", '3'); | |
5498 | init_integral_libfuncs (xor_optab, "xor", '3'); | |
5499 | init_integral_libfuncs (ashl_optab, "ashl", '3'); | |
5500 | init_integral_libfuncs (ashr_optab, "ashr", '3'); | |
5d81dc5b | 5501 | init_integral_libfuncs (lshr_optab, "lshr", '3'); |
5d81dc5b RK |
5502 | init_integral_libfuncs (smin_optab, "min", '3'); |
5503 | init_floating_libfuncs (smin_optab, "min", '3'); | |
5504 | init_integral_libfuncs (smax_optab, "max", '3'); | |
5505 | init_floating_libfuncs (smax_optab, "max", '3'); | |
5506 | init_integral_libfuncs (umin_optab, "umin", '3'); | |
5507 | init_integral_libfuncs (umax_optab, "umax", '3'); | |
5508 | init_integral_libfuncs (neg_optab, "neg", '2'); | |
5509 | init_floating_libfuncs (neg_optab, "neg", '2'); | |
91ce572a CC |
5510 | init_integral_libfuncs (negv_optab, "negv", '2'); |
5511 | init_floating_libfuncs (negv_optab, "neg", '2'); | |
5d81dc5b RK |
5512 | init_integral_libfuncs (one_cmpl_optab, "one_cmpl", '2'); |
5513 | init_integral_libfuncs (ffs_optab, "ffs", '2'); | |
2928cd7a RH |
5514 | init_integral_libfuncs (clz_optab, "clz", '2'); |
5515 | init_integral_libfuncs (ctz_optab, "ctz", '2'); | |
5516 | init_integral_libfuncs (popcount_optab, "popcount", '2'); | |
5517 | init_integral_libfuncs (parity_optab, "parity", '2'); | |
5d81dc5b RK |
5518 | |
5519 | /* Comparison libcalls for integers MUST come in pairs, signed/unsigned. */ | |
5520 | init_integral_libfuncs (cmp_optab, "cmp", '2'); | |
5521 | init_integral_libfuncs (ucmp_optab, "ucmp", '2'); | |
5522 | init_floating_libfuncs (cmp_optab, "cmp", '2'); | |
77c9c6c2 RK |
5523 | |
5524 | #ifdef MULSI3_LIBCALL | |
5525 | smul_optab->handlers[(int) SImode].libfunc | |
76095e2f | 5526 | = init_one_libfunc (MULSI3_LIBCALL); |
77c9c6c2 RK |
5527 | #endif |
5528 | #ifdef MULDI3_LIBCALL | |
5529 | smul_optab->handlers[(int) DImode].libfunc | |
76095e2f | 5530 | = init_one_libfunc (MULDI3_LIBCALL); |
77c9c6c2 | 5531 | #endif |
77c9c6c2 | 5532 | |
77c9c6c2 RK |
5533 | #ifdef DIVSI3_LIBCALL |
5534 | sdiv_optab->handlers[(int) SImode].libfunc | |
76095e2f | 5535 | = init_one_libfunc (DIVSI3_LIBCALL); |
77c9c6c2 RK |
5536 | #endif |
5537 | #ifdef DIVDI3_LIBCALL | |
5538 | sdiv_optab->handlers[(int) DImode].libfunc | |
76095e2f | 5539 | = init_one_libfunc (DIVDI3_LIBCALL); |
b092b471 | 5540 | #endif |
77c9c6c2 | 5541 | |
77c9c6c2 RK |
5542 | #ifdef UDIVSI3_LIBCALL |
5543 | udiv_optab->handlers[(int) SImode].libfunc | |
76095e2f | 5544 | = init_one_libfunc (UDIVSI3_LIBCALL); |
77c9c6c2 RK |
5545 | #endif |
5546 | #ifdef UDIVDI3_LIBCALL | |
5547 | udiv_optab->handlers[(int) DImode].libfunc | |
76095e2f | 5548 | = init_one_libfunc (UDIVDI3_LIBCALL); |
b092b471 | 5549 | #endif |
77c9c6c2 RK |
5550 | |
5551 | #ifdef MODSI3_LIBCALL | |
5552 | smod_optab->handlers[(int) SImode].libfunc | |
76095e2f | 5553 | = init_one_libfunc (MODSI3_LIBCALL); |
77c9c6c2 RK |
5554 | #endif |
5555 | #ifdef MODDI3_LIBCALL | |
5556 | smod_optab->handlers[(int) DImode].libfunc | |
76095e2f | 5557 | = init_one_libfunc (MODDI3_LIBCALL); |
b092b471 | 5558 | #endif |
77c9c6c2 RK |
5559 | |
5560 | #ifdef UMODSI3_LIBCALL | |
5561 | umod_optab->handlers[(int) SImode].libfunc | |
76095e2f | 5562 | = init_one_libfunc (UMODSI3_LIBCALL); |
77c9c6c2 RK |
5563 | #endif |
5564 | #ifdef UMODDI3_LIBCALL | |
5565 | umod_optab->handlers[(int) DImode].libfunc | |
76095e2f | 5566 | = init_one_libfunc (UMODDI3_LIBCALL); |
b092b471 | 5567 | #endif |
4754348d | 5568 | |
decdfa82 RS |
5569 | /* Use cabs for DC complex abs, since systems generally have cabs. |
5570 | Don't define any libcall for SCmode, so that cabs will be used. */ | |
5571 | abs_optab->handlers[(int) DCmode].libfunc | |
76095e2f | 5572 | = init_one_libfunc ("cabs"); |
77c9c6c2 | 5573 | |
7f7d6d64 | 5574 | /* The ffs function operates on `int'. */ |
c5c76735 | 5575 | ffs_optab->handlers[(int) mode_for_size (INT_TYPE_SIZE, MODE_INT, 0)].libfunc |
76095e2f RH |
5576 | = init_one_libfunc ("ffs"); |
5577 | ||
5578 | extendsfdf2_libfunc = init_one_libfunc ("__extendsfdf2"); | |
5579 | extendsfxf2_libfunc = init_one_libfunc ("__extendsfxf2"); | |
5580 | extendsftf2_libfunc = init_one_libfunc ("__extendsftf2"); | |
5581 | extenddfxf2_libfunc = init_one_libfunc ("__extenddfxf2"); | |
5582 | extenddftf2_libfunc = init_one_libfunc ("__extenddftf2"); | |
5583 | ||
5584 | truncdfsf2_libfunc = init_one_libfunc ("__truncdfsf2"); | |
5585 | truncxfsf2_libfunc = init_one_libfunc ("__truncxfsf2"); | |
5586 | trunctfsf2_libfunc = init_one_libfunc ("__trunctfsf2"); | |
5587 | truncxfdf2_libfunc = init_one_libfunc ("__truncxfdf2"); | |
5588 | trunctfdf2_libfunc = init_one_libfunc ("__trunctfdf2"); | |
5589 | ||
9602f5a0 | 5590 | abort_libfunc = init_one_libfunc ("abort"); |
76095e2f | 5591 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
b215b52e | 5592 | memmove_libfunc = init_one_libfunc ("memmove"); |
76095e2f RH |
5593 | bcopy_libfunc = init_one_libfunc ("bcopy"); |
5594 | memcmp_libfunc = init_one_libfunc ("memcmp"); | |
5595 | bcmp_libfunc = init_one_libfunc ("__gcc_bcmp"); | |
5596 | memset_libfunc = init_one_libfunc ("memset"); | |
5597 | bzero_libfunc = init_one_libfunc ("bzero"); | |
68d28100 | 5598 | setbits_libfunc = init_one_libfunc ("__setbits"); |
76095e2f | 5599 | |
52a11cbf RH |
5600 | unwind_resume_libfunc = init_one_libfunc (USING_SJLJ_EXCEPTIONS |
5601 | ? "_Unwind_SjLj_Resume" | |
5602 | : "_Unwind_Resume"); | |
6e6a07d2 | 5603 | #ifndef DONT_USE_BUILTIN_SETJMP |
76095e2f RH |
5604 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
5605 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
27a36778 | 5606 | #else |
76095e2f RH |
5607 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
5608 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
27a36778 | 5609 | #endif |
52a11cbf RH |
5610 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
5611 | unwind_sjlj_unregister_libfunc | |
5612 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
6adb4e3a | 5613 | |
76095e2f RH |
5614 | eqhf2_libfunc = init_one_libfunc ("__eqhf2"); |
5615 | nehf2_libfunc = init_one_libfunc ("__nehf2"); | |
5616 | gthf2_libfunc = init_one_libfunc ("__gthf2"); | |
5617 | gehf2_libfunc = init_one_libfunc ("__gehf2"); | |
5618 | lthf2_libfunc = init_one_libfunc ("__lthf2"); | |
5619 | lehf2_libfunc = init_one_libfunc ("__lehf2"); | |
1eb8759b | 5620 | unordhf2_libfunc = init_one_libfunc ("__unordhf2"); |
76095e2f RH |
5621 | |
5622 | eqsf2_libfunc = init_one_libfunc ("__eqsf2"); | |
5623 | nesf2_libfunc = init_one_libfunc ("__nesf2"); | |
5624 | gtsf2_libfunc = init_one_libfunc ("__gtsf2"); | |
5625 | gesf2_libfunc = init_one_libfunc ("__gesf2"); | |
5626 | ltsf2_libfunc = init_one_libfunc ("__ltsf2"); | |
5627 | lesf2_libfunc = init_one_libfunc ("__lesf2"); | |
1eb8759b | 5628 | unordsf2_libfunc = init_one_libfunc ("__unordsf2"); |
76095e2f RH |
5629 | |
5630 | eqdf2_libfunc = init_one_libfunc ("__eqdf2"); | |
5631 | nedf2_libfunc = init_one_libfunc ("__nedf2"); | |
5632 | gtdf2_libfunc = init_one_libfunc ("__gtdf2"); | |
5633 | gedf2_libfunc = init_one_libfunc ("__gedf2"); | |
5634 | ltdf2_libfunc = init_one_libfunc ("__ltdf2"); | |
5635 | ledf2_libfunc = init_one_libfunc ("__ledf2"); | |
1eb8759b | 5636 | unorddf2_libfunc = init_one_libfunc ("__unorddf2"); |
76095e2f RH |
5637 | |
5638 | eqxf2_libfunc = init_one_libfunc ("__eqxf2"); | |
5639 | nexf2_libfunc = init_one_libfunc ("__nexf2"); | |
5640 | gtxf2_libfunc = init_one_libfunc ("__gtxf2"); | |
5641 | gexf2_libfunc = init_one_libfunc ("__gexf2"); | |
5642 | ltxf2_libfunc = init_one_libfunc ("__ltxf2"); | |
5643 | lexf2_libfunc = init_one_libfunc ("__lexf2"); | |
1eb8759b | 5644 | unordxf2_libfunc = init_one_libfunc ("__unordxf2"); |
76095e2f RH |
5645 | |
5646 | eqtf2_libfunc = init_one_libfunc ("__eqtf2"); | |
5647 | netf2_libfunc = init_one_libfunc ("__netf2"); | |
5648 | gttf2_libfunc = init_one_libfunc ("__gttf2"); | |
5649 | getf2_libfunc = init_one_libfunc ("__getf2"); | |
5650 | lttf2_libfunc = init_one_libfunc ("__lttf2"); | |
5651 | letf2_libfunc = init_one_libfunc ("__letf2"); | |
1eb8759b | 5652 | unordtf2_libfunc = init_one_libfunc ("__unordtf2"); |
76095e2f RH |
5653 | |
5654 | floatsisf_libfunc = init_one_libfunc ("__floatsisf"); | |
5655 | floatdisf_libfunc = init_one_libfunc ("__floatdisf"); | |
5656 | floattisf_libfunc = init_one_libfunc ("__floattisf"); | |
5657 | ||
5658 | floatsidf_libfunc = init_one_libfunc ("__floatsidf"); | |
5659 | floatdidf_libfunc = init_one_libfunc ("__floatdidf"); | |
5660 | floattidf_libfunc = init_one_libfunc ("__floattidf"); | |
5661 | ||
5662 | floatsixf_libfunc = init_one_libfunc ("__floatsixf"); | |
5663 | floatdixf_libfunc = init_one_libfunc ("__floatdixf"); | |
5664 | floattixf_libfunc = init_one_libfunc ("__floattixf"); | |
5665 | ||
5666 | floatsitf_libfunc = init_one_libfunc ("__floatsitf"); | |
5667 | floatditf_libfunc = init_one_libfunc ("__floatditf"); | |
5668 | floattitf_libfunc = init_one_libfunc ("__floattitf"); | |
5669 | ||
5670 | fixsfsi_libfunc = init_one_libfunc ("__fixsfsi"); | |
5671 | fixsfdi_libfunc = init_one_libfunc ("__fixsfdi"); | |
5672 | fixsfti_libfunc = init_one_libfunc ("__fixsfti"); | |
5673 | ||
5674 | fixdfsi_libfunc = init_one_libfunc ("__fixdfsi"); | |
5675 | fixdfdi_libfunc = init_one_libfunc ("__fixdfdi"); | |
5676 | fixdfti_libfunc = init_one_libfunc ("__fixdfti"); | |
5677 | ||
5678 | fixxfsi_libfunc = init_one_libfunc ("__fixxfsi"); | |
5679 | fixxfdi_libfunc = init_one_libfunc ("__fixxfdi"); | |
5680 | fixxfti_libfunc = init_one_libfunc ("__fixxfti"); | |
5681 | ||
5682 | fixtfsi_libfunc = init_one_libfunc ("__fixtfsi"); | |
5683 | fixtfdi_libfunc = init_one_libfunc ("__fixtfdi"); | |
5684 | fixtfti_libfunc = init_one_libfunc ("__fixtfti"); | |
5685 | ||
5686 | fixunssfsi_libfunc = init_one_libfunc ("__fixunssfsi"); | |
5687 | fixunssfdi_libfunc = init_one_libfunc ("__fixunssfdi"); | |
5688 | fixunssfti_libfunc = init_one_libfunc ("__fixunssfti"); | |
5689 | ||
5690 | fixunsdfsi_libfunc = init_one_libfunc ("__fixunsdfsi"); | |
5691 | fixunsdfdi_libfunc = init_one_libfunc ("__fixunsdfdi"); | |
5692 | fixunsdfti_libfunc = init_one_libfunc ("__fixunsdfti"); | |
5693 | ||
5694 | fixunsxfsi_libfunc = init_one_libfunc ("__fixunsxfsi"); | |
5695 | fixunsxfdi_libfunc = init_one_libfunc ("__fixunsxfdi"); | |
5696 | fixunsxfti_libfunc = init_one_libfunc ("__fixunsxfti"); | |
5697 | ||
5698 | fixunstfsi_libfunc = init_one_libfunc ("__fixunstfsi"); | |
5699 | fixunstfdi_libfunc = init_one_libfunc ("__fixunstfdi"); | |
5700 | fixunstfti_libfunc = init_one_libfunc ("__fixunstfti"); | |
4754348d | 5701 | |
07417085 KR |
5702 | /* For function entry/exit instrumentation. */ |
5703 | profile_function_entry_libfunc | |
76095e2f | 5704 | = init_one_libfunc ("__cyg_profile_func_enter"); |
07417085 | 5705 | profile_function_exit_libfunc |
76095e2f | 5706 | = init_one_libfunc ("__cyg_profile_func_exit"); |
07417085 | 5707 | |
68d28100 RH |
5708 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
5709 | gcov_init_libfunc = init_one_libfunc ("__gcov_init"); | |
5710 | ||
842a431a DM |
5711 | if (HAVE_conditional_trap) |
5712 | trap_rtx = gen_rtx_fmt_ee (EQ, VOIDmode, NULL_RTX, NULL_RTX); | |
e0cd0770 | 5713 | |
159c2aed DE |
5714 | #ifdef INIT_TARGET_OPTABS |
5715 | /* Allow the target to add more libcalls or rename some, etc. */ | |
5716 | INIT_TARGET_OPTABS; | |
5717 | #endif | |
77c9c6c2 | 5718 | } |
7e1966ca | 5719 | \f |
e0cd0770 JC |
5720 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
5721 | CODE. Return 0 on failure. */ | |
5722 | ||
5723 | rtx | |
0c20a65f AJ |
5724 | gen_cond_trap (enum rtx_code code ATTRIBUTE_UNUSED, rtx op1, |
5725 | rtx op2 ATTRIBUTE_UNUSED, rtx tcode ATTRIBUTE_UNUSED) | |
e0cd0770 JC |
5726 | { |
5727 | enum machine_mode mode = GET_MODE (op1); | |
842a431a DM |
5728 | enum insn_code icode; |
5729 | rtx insn; | |
5730 | ||
5731 | if (!HAVE_conditional_trap) | |
5732 | return 0; | |
e0cd0770 JC |
5733 | |
5734 | if (mode == VOIDmode) | |
5735 | return 0; | |
5736 | ||
842a431a DM |
5737 | icode = cmp_optab->handlers[(int) mode].insn_code; |
5738 | if (icode == CODE_FOR_nothing) | |
5739 | return 0; | |
5740 | ||
5741 | start_sequence (); | |
5742 | op1 = prepare_operand (icode, op1, 0, mode, mode, 0); | |
0310c414 | 5743 | op2 = prepare_operand (icode, op2, 1, mode, mode, 0); |
d893ccde RH |
5744 | if (!op1 || !op2) |
5745 | { | |
5746 | end_sequence (); | |
5747 | return 0; | |
5748 | } | |
842a431a DM |
5749 | emit_insn (GEN_FCN (icode) (op1, op2)); |
5750 | ||
5751 | PUT_CODE (trap_rtx, code); | |
5752 | insn = gen_conditional_trap (trap_rtx, tcode); | |
5753 | if (insn) | |
e0cd0770 | 5754 | { |
842a431a DM |
5755 | emit_insn (insn); |
5756 | insn = get_insns (); | |
e0cd0770 | 5757 | } |
842a431a | 5758 | end_sequence (); |
e0cd0770 | 5759 | |
842a431a | 5760 | return insn; |
e0cd0770 | 5761 | } |
e2500fed GK |
5762 | |
5763 | #include "gt-optabs.h" |