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77c9c6c2 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
40e90eac | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
eeef0e45 | 4 | Free Software Foundation, Inc. |
77c9c6c2 | 5 | |
1322177d | 6 | This file is part of GCC. |
77c9c6c2 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
77c9c6c2 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
77c9c6c2 RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
77c9c6c2 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
718f9c0f | 27 | #include "diagnostic-core.h" |
01198c2f | 28 | #include "toplev.h" |
dff01034 KG |
29 | |
30 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
dc297297 | 31 | is properly defined. */ |
dff01034 | 32 | #include "insn-config.h" |
77c9c6c2 RK |
33 | #include "rtl.h" |
34 | #include "tree.h" | |
6baf1cc8 | 35 | #include "tm_p.h" |
77c9c6c2 | 36 | #include "flags.h" |
49ad7cfa | 37 | #include "function.h" |
52a11cbf | 38 | #include "except.h" |
77c9c6c2 | 39 | #include "expr.h" |
e78d8e51 ZW |
40 | #include "optabs.h" |
41 | #include "libfuncs.h" | |
77c9c6c2 | 42 | #include "recog.h" |
2829c155 | 43 | #include "reload.h" |
87ff9c8e | 44 | #include "ggc.h" |
4a69cf79 | 45 | #include "basic-block.h" |
c15c90bb | 46 | #include "target.h" |
77c9c6c2 | 47 | |
4bcbfa03 | 48 | struct target_optabs default_target_optabs; |
3e9c326a | 49 | struct target_libfuncs default_target_libfuncs; |
4bcbfa03 RS |
50 | #if SWITCHABLE_TARGET |
51 | struct target_optabs *this_target_optabs = &default_target_optabs; | |
3e9c326a | 52 | struct target_libfuncs *this_target_libfuncs = &default_target_libfuncs; |
4bcbfa03 | 53 | #endif |
34220a12 | 54 | |
3e9c326a RS |
55 | #define libfunc_hash \ |
56 | (this_target_libfuncs->x_libfunc_hash) | |
19c3fc24 | 57 | |
377017c4 RK |
58 | /* Contains the optab used for each rtx code. */ |
59 | optab code_to_optab[NUM_RTX_CODE + 1]; | |
60 | ||
f90b7a5a PB |
61 | static void prepare_float_lib_cmp (rtx, rtx, enum rtx_code, rtx *, |
62 | enum machine_mode *); | |
9cce5b20 | 63 | static rtx expand_unop_direct (enum machine_mode, optab, rtx, rtx, int); |
842a431a | 64 | |
8a33f100 JH |
65 | /* Debug facility for use in GDB. */ |
66 | void debug_optab_libfuncs (void); | |
67 | ||
79b87c74 MM |
68 | /* Prefixes for the current version of decimal floating point (BID vs. DPD) */ |
69 | #if ENABLE_DECIMAL_BID_FORMAT | |
70 | #define DECIMAL_PREFIX "bid_" | |
71 | #else | |
72 | #define DECIMAL_PREFIX "dpd_" | |
73 | #endif | |
8a33f100 | 74 | \f |
3e9c326a | 75 | /* Used for libfunc_hash. */ |
8a33f100 JH |
76 | |
77 | static hashval_t | |
78 | hash_libfunc (const void *p) | |
79 | { | |
80 | const struct libfunc_entry *const e = (const struct libfunc_entry *) p; | |
81 | ||
82 | return (((int) e->mode1 + (int) e->mode2 * NUM_MACHINE_MODES) | |
a48b501c | 83 | ^ e->optab); |
8a33f100 JH |
84 | } |
85 | ||
3e9c326a | 86 | /* Used for libfunc_hash. */ |
8a33f100 JH |
87 | |
88 | static int | |
89 | eq_libfunc (const void *p, const void *q) | |
90 | { | |
91 | const struct libfunc_entry *const e1 = (const struct libfunc_entry *) p; | |
92 | const struct libfunc_entry *const e2 = (const struct libfunc_entry *) q; | |
93 | ||
94 | return (e1->optab == e2->optab | |
95 | && e1->mode1 == e2->mode1 | |
96 | && e1->mode2 == e2->mode2); | |
97 | } | |
98 | ||
99 | /* Return libfunc corresponding operation defined by OPTAB converting | |
100 | from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL | |
101 | if no libfunc is available. */ | |
102 | rtx | |
103 | convert_optab_libfunc (convert_optab optab, enum machine_mode mode1, | |
104 | enum machine_mode mode2) | |
105 | { | |
106 | struct libfunc_entry e; | |
107 | struct libfunc_entry **slot; | |
108 | ||
33727b5e | 109 | e.optab = (size_t) (optab - &convert_optab_table[0]); |
8a33f100 JH |
110 | e.mode1 = mode1; |
111 | e.mode2 = mode2; | |
112 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
113 | if (!slot) | |
114 | { | |
115 | if (optab->libcall_gen) | |
116 | { | |
117 | optab->libcall_gen (optab, optab->libcall_basename, mode1, mode2); | |
118 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
119 | if (slot) | |
120 | return (*slot)->libfunc; | |
121 | else | |
122 | return NULL; | |
123 | } | |
124 | return NULL; | |
125 | } | |
126 | return (*slot)->libfunc; | |
127 | } | |
128 | ||
129 | /* Return libfunc corresponding operation defined by OPTAB in MODE. | |
130 | Trigger lazy initialization if needed, return NULL if no libfunc is | |
131 | available. */ | |
132 | rtx | |
133 | optab_libfunc (optab optab, enum machine_mode mode) | |
134 | { | |
135 | struct libfunc_entry e; | |
136 | struct libfunc_entry **slot; | |
137 | ||
33727b5e | 138 | e.optab = (size_t) (optab - &optab_table[0]); |
8a33f100 JH |
139 | e.mode1 = mode; |
140 | e.mode2 = VOIDmode; | |
141 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
142 | if (!slot) | |
143 | { | |
144 | if (optab->libcall_gen) | |
145 | { | |
146 | optab->libcall_gen (optab, optab->libcall_basename, | |
147 | optab->libcall_suffix, mode); | |
148 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, | |
149 | &e, NO_INSERT); | |
150 | if (slot) | |
151 | return (*slot)->libfunc; | |
152 | else | |
153 | return NULL; | |
154 | } | |
155 | return NULL; | |
156 | } | |
157 | return (*slot)->libfunc; | |
158 | } | |
79b87c74 | 159 | |
77c9c6c2 | 160 | \f |
2f937369 | 161 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
77c9c6c2 RK |
162 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
163 | operation). | |
164 | ||
165 | If the last insn does not set TARGET, don't do anything, but return 1. | |
166 | ||
167 | If a previous insn sets TARGET and TARGET is one of OP0 or OP1, | |
168 | don't add the REG_EQUAL note but return 0. Our caller can then try | |
169 | again, ensuring that TARGET is not one of the operands. */ | |
170 | ||
171 | static int | |
0c20a65f | 172 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
77c9c6c2 | 173 | { |
2f937369 | 174 | rtx last_insn, insn, set; |
77c9c6c2 RK |
175 | rtx note; |
176 | ||
e3feb571 | 177 | gcc_assert (insns && INSN_P (insns) && NEXT_INSN (insns)); |
2f937369 | 178 | |
ec8e098d PB |
179 | if (GET_RTX_CLASS (code) != RTX_COMM_ARITH |
180 | && GET_RTX_CLASS (code) != RTX_BIN_ARITH | |
181 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE | |
182 | && GET_RTX_CLASS (code) != RTX_COMPARE | |
183 | && GET_RTX_CLASS (code) != RTX_UNARY) | |
2f937369 DM |
184 | return 1; |
185 | ||
186 | if (GET_CODE (target) == ZERO_EXTRACT) | |
187 | return 1; | |
188 | ||
189 | for (last_insn = insns; | |
190 | NEXT_INSN (last_insn) != NULL_RTX; | |
191 | last_insn = NEXT_INSN (last_insn)) | |
192 | ; | |
193 | ||
194 | set = single_set (last_insn); | |
195 | if (set == NULL_RTX) | |
196 | return 1; | |
197 | ||
198 | if (! rtx_equal_p (SET_DEST (set), target) | |
f9d36a92 | 199 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
2f937369 | 200 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
f9d36a92 | 201 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
77c9c6c2 RK |
202 | return 1; |
203 | ||
204 | /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET | |
205 | besides the last insn. */ | |
206 | if (reg_overlap_mentioned_p (target, op0) | |
207 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
2f937369 DM |
208 | { |
209 | insn = PREV_INSN (last_insn); | |
210 | while (insn != NULL_RTX) | |
211 | { | |
212 | if (reg_set_p (target, insn)) | |
213 | return 0; | |
214 | ||
215 | insn = PREV_INSN (insn); | |
216 | } | |
217 | } | |
77c9c6c2 | 218 | |
ec8e098d | 219 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
9e6a5703 | 220 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); |
77c9c6c2 | 221 | else |
9e6a5703 | 222 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
77c9c6c2 | 223 | |
2f937369 | 224 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
77c9c6c2 RK |
225 | |
226 | return 1; | |
227 | } | |
228 | \f | |
835532b8 RK |
229 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
230 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
0c20a65f | 231 | not actually do a sign-extend or zero-extend, but can leave the |
835532b8 RK |
232 | higher-order bits of the result rtx undefined, for example, in the case |
233 | of logical operations, but not right shifts. */ | |
234 | ||
235 | static rtx | |
0c20a65f AJ |
236 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
237 | int unsignedp, int no_extend) | |
835532b8 RK |
238 | { |
239 | rtx result; | |
240 | ||
8041889f RK |
241 | /* If we don't have to extend and this is a constant, return it. */ |
242 | if (no_extend && GET_MODE (op) == VOIDmode) | |
243 | return op; | |
244 | ||
245 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
246 | extend since it will be more efficient to do so unless the signedness of | |
247 | a promoted object differs from our extension. */ | |
835532b8 | 248 | if (! no_extend |
cb8f73be RK |
249 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
250 | && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp)) | |
0661a3de | 251 | return convert_modes (mode, oldmode, op, unsignedp); |
835532b8 RK |
252 | |
253 | /* If MODE is no wider than a single word, we return a paradoxical | |
254 | SUBREG. */ | |
255 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
9e6a5703 | 256 | return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0); |
835532b8 RK |
257 | |
258 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
259 | part to OP. */ | |
260 | ||
261 | result = gen_reg_rtx (mode); | |
c41c1387 | 262 | emit_clobber (result); |
835532b8 RK |
263 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
264 | return result; | |
265 | } | |
266 | \f | |
71d46ca5 MM |
267 | /* Return the optab used for computing the operation given by the tree code, |
268 | CODE and the tree EXP. This function is not always usable (for example, it | |
269 | cannot give complete results for multiplication or division) but probably | |
270 | ought to be relied on more widely throughout the expander. */ | |
26277d41 | 271 | optab |
71d46ca5 MM |
272 | optab_for_tree_code (enum tree_code code, const_tree type, |
273 | enum optab_subtype subtype) | |
26277d41 PB |
274 | { |
275 | bool trapv; | |
276 | switch (code) | |
277 | { | |
278 | case BIT_AND_EXPR: | |
279 | return and_optab; | |
280 | ||
281 | case BIT_IOR_EXPR: | |
282 | return ior_optab; | |
283 | ||
284 | case BIT_NOT_EXPR: | |
285 | return one_cmpl_optab; | |
286 | ||
287 | case BIT_XOR_EXPR: | |
288 | return xor_optab; | |
289 | ||
290 | case TRUNC_MOD_EXPR: | |
291 | case CEIL_MOD_EXPR: | |
292 | case FLOOR_MOD_EXPR: | |
293 | case ROUND_MOD_EXPR: | |
294 | return TYPE_UNSIGNED (type) ? umod_optab : smod_optab; | |
295 | ||
296 | case RDIV_EXPR: | |
297 | case TRUNC_DIV_EXPR: | |
298 | case CEIL_DIV_EXPR: | |
299 | case FLOOR_DIV_EXPR: | |
300 | case ROUND_DIV_EXPR: | |
301 | case EXACT_DIV_EXPR: | |
0f996086 CF |
302 | if (TYPE_SATURATING(type)) |
303 | return TYPE_UNSIGNED(type) ? usdiv_optab : ssdiv_optab; | |
26277d41 PB |
304 | return TYPE_UNSIGNED (type) ? udiv_optab : sdiv_optab; |
305 | ||
306 | case LSHIFT_EXPR: | |
71d46ca5 MM |
307 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
308 | { | |
309 | if (subtype == optab_vector) | |
310 | return TYPE_SATURATING (type) ? NULL : vashl_optab; | |
311 | ||
312 | gcc_assert (subtype == optab_scalar); | |
313 | } | |
0f996086 CF |
314 | if (TYPE_SATURATING(type)) |
315 | return TYPE_UNSIGNED(type) ? usashl_optab : ssashl_optab; | |
26277d41 PB |
316 | return ashl_optab; |
317 | ||
318 | case RSHIFT_EXPR: | |
71d46ca5 MM |
319 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
320 | { | |
321 | if (subtype == optab_vector) | |
322 | return TYPE_UNSIGNED (type) ? vlshr_optab : vashr_optab; | |
323 | ||
324 | gcc_assert (subtype == optab_scalar); | |
325 | } | |
26277d41 PB |
326 | return TYPE_UNSIGNED (type) ? lshr_optab : ashr_optab; |
327 | ||
328 | case LROTATE_EXPR: | |
71d46ca5 MM |
329 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
330 | { | |
331 | if (subtype == optab_vector) | |
332 | return vrotl_optab; | |
333 | ||
334 | gcc_assert (subtype == optab_scalar); | |
335 | } | |
26277d41 PB |
336 | return rotl_optab; |
337 | ||
338 | case RROTATE_EXPR: | |
71d46ca5 MM |
339 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
340 | { | |
341 | if (subtype == optab_vector) | |
342 | return vrotr_optab; | |
343 | ||
344 | gcc_assert (subtype == optab_scalar); | |
345 | } | |
26277d41 PB |
346 | return rotr_optab; |
347 | ||
348 | case MAX_EXPR: | |
349 | return TYPE_UNSIGNED (type) ? umax_optab : smax_optab; | |
350 | ||
351 | case MIN_EXPR: | |
352 | return TYPE_UNSIGNED (type) ? umin_optab : smin_optab; | |
353 | ||
7ccf35ed DN |
354 | case REALIGN_LOAD_EXPR: |
355 | return vec_realign_load_optab; | |
356 | ||
20f06221 DN |
357 | case WIDEN_SUM_EXPR: |
358 | return TYPE_UNSIGNED (type) ? usum_widen_optab : ssum_widen_optab; | |
359 | ||
360 | case DOT_PROD_EXPR: | |
361 | return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; | |
362 | ||
0354c0c7 BS |
363 | case WIDEN_MULT_PLUS_EXPR: |
364 | return (TYPE_UNSIGNED (type) | |
365 | ? (TYPE_SATURATING (type) | |
366 | ? usmadd_widen_optab : umadd_widen_optab) | |
367 | : (TYPE_SATURATING (type) | |
368 | ? ssmadd_widen_optab : smadd_widen_optab)); | |
369 | ||
370 | case WIDEN_MULT_MINUS_EXPR: | |
371 | return (TYPE_UNSIGNED (type) | |
372 | ? (TYPE_SATURATING (type) | |
373 | ? usmsub_widen_optab : umsub_widen_optab) | |
374 | : (TYPE_SATURATING (type) | |
375 | ? ssmsub_widen_optab : smsub_widen_optab)); | |
376 | ||
61d3cdbb DN |
377 | case REDUC_MAX_EXPR: |
378 | return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; | |
379 | ||
380 | case REDUC_MIN_EXPR: | |
381 | return TYPE_UNSIGNED (type) ? reduc_umin_optab : reduc_smin_optab; | |
382 | ||
383 | case REDUC_PLUS_EXPR: | |
a6b46ba2 DN |
384 | return TYPE_UNSIGNED (type) ? reduc_uplus_optab : reduc_splus_optab; |
385 | ||
386 | case VEC_LSHIFT_EXPR: | |
387 | return vec_shl_optab; | |
388 | ||
389 | case VEC_RSHIFT_EXPR: | |
390 | return vec_shr_optab; | |
61d3cdbb | 391 | |
89d67cca | 392 | case VEC_WIDEN_MULT_HI_EXPR: |
b8698a0f | 393 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
394 | vec_widen_umult_hi_optab : vec_widen_smult_hi_optab; |
395 | ||
396 | case VEC_WIDEN_MULT_LO_EXPR: | |
b8698a0f | 397 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
398 | vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; |
399 | ||
400 | case VEC_UNPACK_HI_EXPR: | |
8115817b | 401 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
402 | vec_unpacku_hi_optab : vec_unpacks_hi_optab; |
403 | ||
404 | case VEC_UNPACK_LO_EXPR: | |
b8698a0f | 405 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
406 | vec_unpacku_lo_optab : vec_unpacks_lo_optab; |
407 | ||
d9987fb4 UB |
408 | case VEC_UNPACK_FLOAT_HI_EXPR: |
409 | /* The signedness is determined from input operand. */ | |
410 | return TYPE_UNSIGNED (type) ? | |
411 | vec_unpacku_float_hi_optab : vec_unpacks_float_hi_optab; | |
412 | ||
413 | case VEC_UNPACK_FLOAT_LO_EXPR: | |
414 | /* The signedness is determined from input operand. */ | |
b8698a0f | 415 | return TYPE_UNSIGNED (type) ? |
d9987fb4 UB |
416 | vec_unpacku_float_lo_optab : vec_unpacks_float_lo_optab; |
417 | ||
8115817b UB |
418 | case VEC_PACK_TRUNC_EXPR: |
419 | return vec_pack_trunc_optab; | |
420 | ||
89d67cca DN |
421 | case VEC_PACK_SAT_EXPR: |
422 | return TYPE_UNSIGNED (type) ? vec_pack_usat_optab : vec_pack_ssat_optab; | |
8115817b | 423 | |
d9987fb4 | 424 | case VEC_PACK_FIX_TRUNC_EXPR: |
9f106823 | 425 | /* The signedness is determined from output operand. */ |
d9987fb4 UB |
426 | return TYPE_UNSIGNED (type) ? |
427 | vec_pack_ufix_trunc_optab : vec_pack_sfix_trunc_optab; | |
428 | ||
26277d41 PB |
429 | default: |
430 | break; | |
431 | } | |
432 | ||
eeef0e45 | 433 | trapv = INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_TRAPS (type); |
26277d41 PB |
434 | switch (code) |
435 | { | |
5be014d5 | 436 | case POINTER_PLUS_EXPR: |
26277d41 | 437 | case PLUS_EXPR: |
0f996086 CF |
438 | if (TYPE_SATURATING(type)) |
439 | return TYPE_UNSIGNED(type) ? usadd_optab : ssadd_optab; | |
26277d41 PB |
440 | return trapv ? addv_optab : add_optab; |
441 | ||
442 | case MINUS_EXPR: | |
0f996086 CF |
443 | if (TYPE_SATURATING(type)) |
444 | return TYPE_UNSIGNED(type) ? ussub_optab : sssub_optab; | |
26277d41 PB |
445 | return trapv ? subv_optab : sub_optab; |
446 | ||
447 | case MULT_EXPR: | |
0f996086 CF |
448 | if (TYPE_SATURATING(type)) |
449 | return TYPE_UNSIGNED(type) ? usmul_optab : ssmul_optab; | |
26277d41 PB |
450 | return trapv ? smulv_optab : smul_optab; |
451 | ||
452 | case NEGATE_EXPR: | |
0f996086 CF |
453 | if (TYPE_SATURATING(type)) |
454 | return TYPE_UNSIGNED(type) ? usneg_optab : ssneg_optab; | |
26277d41 PB |
455 | return trapv ? negv_optab : neg_optab; |
456 | ||
457 | case ABS_EXPR: | |
458 | return trapv ? absv_optab : abs_optab; | |
459 | ||
98b44b0e IR |
460 | case VEC_EXTRACT_EVEN_EXPR: |
461 | return vec_extract_even_optab; | |
462 | ||
463 | case VEC_EXTRACT_ODD_EXPR: | |
464 | return vec_extract_odd_optab; | |
465 | ||
466 | case VEC_INTERLEAVE_HIGH_EXPR: | |
467 | return vec_interleave_high_optab; | |
468 | ||
469 | case VEC_INTERLEAVE_LOW_EXPR: | |
470 | return vec_interleave_low_optab; | |
471 | ||
26277d41 PB |
472 | default: |
473 | return NULL; | |
474 | } | |
475 | } | |
273a2526 | 476 | \f |
7ccf35ed | 477 | |
20f06221 DN |
478 | /* Expand vector widening operations. |
479 | ||
480 | There are two different classes of operations handled here: | |
481 | 1) Operations whose result is wider than all the arguments to the operation. | |
482 | Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR | |
483 | In this case OP0 and optionally OP1 would be initialized, | |
484 | but WIDE_OP wouldn't (not relevant for this case). | |
485 | 2) Operations whose result is of the same size as the last argument to the | |
486 | operation, but wider than all the other arguments to the operation. | |
487 | Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR. | |
488 | In the case WIDE_OP, OP0 and optionally OP1 would be initialized. | |
489 | ||
490 | E.g, when called to expand the following operations, this is how | |
491 | the arguments will be initialized: | |
492 | nops OP0 OP1 WIDE_OP | |
b8698a0f | 493 | widening-sum 2 oprnd0 - oprnd1 |
20f06221 DN |
494 | widening-dot-product 3 oprnd0 oprnd1 oprnd2 |
495 | widening-mult 2 oprnd0 oprnd1 - | |
496 | type-promotion (vec-unpack) 1 oprnd0 - - */ | |
497 | ||
498 | rtx | |
8e7aa1f9 MM |
499 | expand_widen_pattern_expr (sepops ops, rtx op0, rtx op1, rtx wide_op, |
500 | rtx target, int unsignedp) | |
b8698a0f | 501 | { |
20f06221 | 502 | tree oprnd0, oprnd1, oprnd2; |
81f40b79 | 503 | enum machine_mode wmode = VOIDmode, tmode0, tmode1 = VOIDmode; |
20f06221 | 504 | optab widen_pattern_optab; |
b8698a0f | 505 | int icode; |
81f40b79 | 506 | enum machine_mode xmode0, xmode1 = VOIDmode, wxmode = VOIDmode; |
20f06221 DN |
507 | rtx temp; |
508 | rtx pat; | |
509 | rtx xop0, xop1, wxop; | |
8e7aa1f9 | 510 | int nops = TREE_CODE_LENGTH (ops->code); |
20f06221 | 511 | |
8e7aa1f9 | 512 | oprnd0 = ops->op0; |
20f06221 DN |
513 | tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); |
514 | widen_pattern_optab = | |
8e7aa1f9 | 515 | optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); |
0354c0c7 BS |
516 | if (ops->code == WIDEN_MULT_PLUS_EXPR |
517 | || ops->code == WIDEN_MULT_MINUS_EXPR) | |
518 | icode = (int) optab_handler (widen_pattern_optab, | |
947131ba | 519 | TYPE_MODE (TREE_TYPE (ops->op2))); |
0354c0c7 | 520 | else |
947131ba | 521 | icode = (int) optab_handler (widen_pattern_optab, tmode0); |
20f06221 DN |
522 | gcc_assert (icode != CODE_FOR_nothing); |
523 | xmode0 = insn_data[icode].operand[1].mode; | |
524 | ||
525 | if (nops >= 2) | |
526 | { | |
8e7aa1f9 | 527 | oprnd1 = ops->op1; |
20f06221 DN |
528 | tmode1 = TYPE_MODE (TREE_TYPE (oprnd1)); |
529 | xmode1 = insn_data[icode].operand[2].mode; | |
530 | } | |
531 | ||
532 | /* The last operand is of a wider mode than the rest of the operands. */ | |
533 | if (nops == 2) | |
534 | { | |
535 | wmode = tmode1; | |
536 | wxmode = xmode1; | |
537 | } | |
538 | else if (nops == 3) | |
539 | { | |
540 | gcc_assert (tmode1 == tmode0); | |
541 | gcc_assert (op1); | |
8e7aa1f9 | 542 | oprnd2 = ops->op2; |
20f06221 DN |
543 | wmode = TYPE_MODE (TREE_TYPE (oprnd2)); |
544 | wxmode = insn_data[icode].operand[3].mode; | |
545 | } | |
546 | ||
547 | if (!wide_op) | |
548 | wmode = wxmode = insn_data[icode].operand[0].mode; | |
549 | ||
550 | if (!target | |
551 | || ! (*insn_data[icode].operand[0].predicate) (target, wmode)) | |
552 | temp = gen_reg_rtx (wmode); | |
553 | else | |
554 | temp = target; | |
555 | ||
556 | xop0 = op0; | |
557 | xop1 = op1; | |
558 | wxop = wide_op; | |
559 | ||
560 | /* In case the insn wants input operands in modes different from | |
561 | those of the actual operands, convert the operands. It would | |
562 | seem that we don't need to convert CONST_INTs, but we do, so | |
563 | that they're properly zero-extended, sign-extended or truncated | |
564 | for their mode. */ | |
565 | ||
566 | if (GET_MODE (op0) != xmode0 && xmode0 != VOIDmode) | |
567 | xop0 = convert_modes (xmode0, | |
568 | GET_MODE (op0) != VOIDmode | |
569 | ? GET_MODE (op0) | |
570 | : tmode0, | |
571 | xop0, unsignedp); | |
572 | ||
573 | if (op1) | |
574 | if (GET_MODE (op1) != xmode1 && xmode1 != VOIDmode) | |
575 | xop1 = convert_modes (xmode1, | |
576 | GET_MODE (op1) != VOIDmode | |
577 | ? GET_MODE (op1) | |
578 | : tmode1, | |
579 | xop1, unsignedp); | |
580 | ||
581 | if (wide_op) | |
582 | if (GET_MODE (wide_op) != wxmode && wxmode != VOIDmode) | |
583 | wxop = convert_modes (wxmode, | |
584 | GET_MODE (wide_op) != VOIDmode | |
585 | ? GET_MODE (wide_op) | |
586 | : wmode, | |
587 | wxop, unsignedp); | |
588 | ||
589 | /* Now, if insn's predicates don't allow our operands, put them into | |
590 | pseudo regs. */ | |
591 | ||
592 | if (! (*insn_data[icode].operand[1].predicate) (xop0, xmode0) | |
593 | && xmode0 != VOIDmode) | |
594 | xop0 = copy_to_mode_reg (xmode0, xop0); | |
595 | ||
596 | if (op1) | |
597 | { | |
598 | if (! (*insn_data[icode].operand[2].predicate) (xop1, xmode1) | |
599 | && xmode1 != VOIDmode) | |
600 | xop1 = copy_to_mode_reg (xmode1, xop1); | |
601 | ||
602 | if (wide_op) | |
603 | { | |
604 | if (! (*insn_data[icode].operand[3].predicate) (wxop, wxmode) | |
605 | && wxmode != VOIDmode) | |
606 | wxop = copy_to_mode_reg (wxmode, wxop); | |
607 | ||
608 | pat = GEN_FCN (icode) (temp, xop0, xop1, wxop); | |
609 | } | |
610 | else | |
611 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
612 | } | |
613 | else | |
614 | { | |
615 | if (wide_op) | |
616 | { | |
617 | if (! (*insn_data[icode].operand[2].predicate) (wxop, wxmode) | |
618 | && wxmode != VOIDmode) | |
619 | wxop = copy_to_mode_reg (wxmode, wxop); | |
620 | ||
621 | pat = GEN_FCN (icode) (temp, xop0, wxop); | |
622 | } | |
623 | else | |
624 | pat = GEN_FCN (icode) (temp, xop0); | |
625 | } | |
626 | ||
627 | emit_insn (pat); | |
628 | return temp; | |
629 | } | |
630 | ||
7ccf35ed DN |
631 | /* Generate code to perform an operation specified by TERNARY_OPTAB |
632 | on operands OP0, OP1 and OP2, with result having machine-mode MODE. | |
633 | ||
634 | UNSIGNEDP is for the case where we have to widen the operands | |
635 | to perform the operation. It says to use zero-extension. | |
636 | ||
637 | If TARGET is nonzero, the value | |
638 | is generated there, if it is convenient to do so. | |
639 | In all cases an rtx is returned for the locus of the value; | |
640 | this may or may not be TARGET. */ | |
641 | ||
642 | rtx | |
c414ac1d EC |
643 | expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, |
644 | rtx op1, rtx op2, rtx target, int unsignedp) | |
7ccf35ed | 645 | { |
947131ba | 646 | int icode = (int) optab_handler (ternary_optab, mode); |
7ccf35ed DN |
647 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
648 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
649 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
650 | rtx temp; | |
651 | rtx pat; | |
652 | rtx xop0 = op0, xop1 = op1, xop2 = op2; | |
653 | ||
947131ba | 654 | gcc_assert (optab_handler (ternary_optab, mode) != CODE_FOR_nothing); |
7ccf35ed | 655 | |
e3feb571 | 656 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) |
7ccf35ed DN |
657 | temp = gen_reg_rtx (mode); |
658 | else | |
659 | temp = target; | |
660 | ||
661 | /* In case the insn wants input operands in modes different from | |
662 | those of the actual operands, convert the operands. It would | |
663 | seem that we don't need to convert CONST_INTs, but we do, so | |
664 | that they're properly zero-extended, sign-extended or truncated | |
665 | for their mode. */ | |
666 | ||
667 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) | |
668 | xop0 = convert_modes (mode0, | |
669 | GET_MODE (op0) != VOIDmode | |
c414ac1d | 670 | ? GET_MODE (op0) |
7ccf35ed DN |
671 | : mode, |
672 | xop0, unsignedp); | |
673 | ||
674 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
675 | xop1 = convert_modes (mode1, | |
676 | GET_MODE (op1) != VOIDmode | |
677 | ? GET_MODE (op1) | |
678 | : mode, | |
679 | xop1, unsignedp); | |
680 | ||
681 | if (GET_MODE (op2) != mode2 && mode2 != VOIDmode) | |
682 | xop2 = convert_modes (mode2, | |
683 | GET_MODE (op2) != VOIDmode | |
684 | ? GET_MODE (op2) | |
685 | : mode, | |
686 | xop2, unsignedp); | |
687 | ||
688 | /* Now, if insn's predicates don't allow our operands, put them into | |
689 | pseudo regs. */ | |
c414ac1d | 690 | |
e3feb571 | 691 | if (!insn_data[icode].operand[1].predicate (xop0, mode0) |
c414ac1d | 692 | && mode0 != VOIDmode) |
7ccf35ed | 693 | xop0 = copy_to_mode_reg (mode0, xop0); |
c414ac1d | 694 | |
e3feb571 | 695 | if (!insn_data[icode].operand[2].predicate (xop1, mode1) |
7ccf35ed DN |
696 | && mode1 != VOIDmode) |
697 | xop1 = copy_to_mode_reg (mode1, xop1); | |
c414ac1d | 698 | |
e3feb571 | 699 | if (!insn_data[icode].operand[3].predicate (xop2, mode2) |
7ccf35ed DN |
700 | && mode2 != VOIDmode) |
701 | xop2 = copy_to_mode_reg (mode2, xop2); | |
c414ac1d | 702 | |
7ccf35ed | 703 | pat = GEN_FCN (icode) (temp, xop0, xop1, xop2); |
c414ac1d | 704 | |
7ccf35ed | 705 | emit_insn (pat); |
c414ac1d | 706 | return temp; |
7ccf35ed DN |
707 | } |
708 | ||
709 | ||
273a2526 RS |
710 | /* Like expand_binop, but return a constant rtx if the result can be |
711 | calculated at compile time. The arguments and return value are | |
712 | otherwise the same as for expand_binop. */ | |
713 | ||
714 | static rtx | |
715 | simplify_expand_binop (enum machine_mode mode, optab binoptab, | |
716 | rtx op0, rtx op1, rtx target, int unsignedp, | |
717 | enum optab_methods methods) | |
718 | { | |
719 | if (CONSTANT_P (op0) && CONSTANT_P (op1)) | |
68162a97 ILT |
720 | { |
721 | rtx x = simplify_binary_operation (binoptab->code, mode, op0, op1); | |
722 | ||
723 | if (x) | |
724 | return x; | |
725 | } | |
726 | ||
727 | return expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods); | |
273a2526 RS |
728 | } |
729 | ||
730 | /* Like simplify_expand_binop, but always put the result in TARGET. | |
731 | Return true if the expansion succeeded. */ | |
732 | ||
bef5d8b6 | 733 | bool |
273a2526 RS |
734 | force_expand_binop (enum machine_mode mode, optab binoptab, |
735 | rtx op0, rtx op1, rtx target, int unsignedp, | |
736 | enum optab_methods methods) | |
737 | { | |
738 | rtx x = simplify_expand_binop (mode, binoptab, op0, op1, | |
739 | target, unsignedp, methods); | |
740 | if (x == 0) | |
741 | return false; | |
742 | if (x != target) | |
743 | emit_move_insn (target, x); | |
744 | return true; | |
745 | } | |
746 | ||
a6b46ba2 DN |
747 | /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */ |
748 | ||
749 | rtx | |
8e7aa1f9 | 750 | expand_vec_shift_expr (sepops ops, rtx target) |
a6b46ba2 DN |
751 | { |
752 | enum insn_code icode; | |
753 | rtx rtx_op1, rtx_op2; | |
754 | enum machine_mode mode1; | |
755 | enum machine_mode mode2; | |
8e7aa1f9 MM |
756 | enum machine_mode mode = TYPE_MODE (ops->type); |
757 | tree vec_oprnd = ops->op0; | |
758 | tree shift_oprnd = ops->op1; | |
a6b46ba2 DN |
759 | optab shift_optab; |
760 | rtx pat; | |
761 | ||
8e7aa1f9 | 762 | switch (ops->code) |
a6b46ba2 DN |
763 | { |
764 | case VEC_RSHIFT_EXPR: | |
765 | shift_optab = vec_shr_optab; | |
766 | break; | |
767 | case VEC_LSHIFT_EXPR: | |
768 | shift_optab = vec_shl_optab; | |
769 | break; | |
770 | default: | |
771 | gcc_unreachable (); | |
772 | } | |
773 | ||
947131ba | 774 | icode = optab_handler (shift_optab, mode); |
a6b46ba2 DN |
775 | gcc_assert (icode != CODE_FOR_nothing); |
776 | ||
777 | mode1 = insn_data[icode].operand[1].mode; | |
778 | mode2 = insn_data[icode].operand[2].mode; | |
779 | ||
49452c07 | 780 | rtx_op1 = expand_normal (vec_oprnd); |
a6b46ba2 DN |
781 | if (!(*insn_data[icode].operand[1].predicate) (rtx_op1, mode1) |
782 | && mode1 != VOIDmode) | |
783 | rtx_op1 = force_reg (mode1, rtx_op1); | |
784 | ||
49452c07 | 785 | rtx_op2 = expand_normal (shift_oprnd); |
a6b46ba2 DN |
786 | if (!(*insn_data[icode].operand[2].predicate) (rtx_op2, mode2) |
787 | && mode2 != VOIDmode) | |
788 | rtx_op2 = force_reg (mode2, rtx_op2); | |
789 | ||
790 | if (!target | |
791 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
792 | target = gen_reg_rtx (mode); | |
793 | ||
794 | /* Emit instruction */ | |
795 | pat = GEN_FCN (icode) (target, rtx_op1, rtx_op2); | |
796 | gcc_assert (pat); | |
797 | emit_insn (pat); | |
798 | ||
799 | return target; | |
800 | } | |
801 | ||
273a2526 RS |
802 | /* This subroutine of expand_doubleword_shift handles the cases in which |
803 | the effective shift value is >= BITS_PER_WORD. The arguments and return | |
804 | value are the same as for the parent routine, except that SUPERWORD_OP1 | |
805 | is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET. | |
806 | INTO_TARGET may be null if the caller has decided to calculate it. */ | |
807 | ||
808 | static bool | |
809 | expand_superword_shift (optab binoptab, rtx outof_input, rtx superword_op1, | |
810 | rtx outof_target, rtx into_target, | |
811 | int unsignedp, enum optab_methods methods) | |
812 | { | |
813 | if (into_target != 0) | |
814 | if (!force_expand_binop (word_mode, binoptab, outof_input, superword_op1, | |
815 | into_target, unsignedp, methods)) | |
816 | return false; | |
817 | ||
818 | if (outof_target != 0) | |
819 | { | |
820 | /* For a signed right shift, we must fill OUTOF_TARGET with copies | |
821 | of the sign bit, otherwise we must fill it with zeros. */ | |
822 | if (binoptab != ashr_optab) | |
823 | emit_move_insn (outof_target, CONST0_RTX (word_mode)); | |
824 | else | |
825 | if (!force_expand_binop (word_mode, binoptab, | |
826 | outof_input, GEN_INT (BITS_PER_WORD - 1), | |
827 | outof_target, unsignedp, methods)) | |
828 | return false; | |
829 | } | |
830 | return true; | |
831 | } | |
832 | ||
833 | /* This subroutine of expand_doubleword_shift handles the cases in which | |
834 | the effective shift value is < BITS_PER_WORD. The arguments and return | |
835 | value are the same as for the parent routine. */ | |
836 | ||
837 | static bool | |
838 | expand_subword_shift (enum machine_mode op1_mode, optab binoptab, | |
839 | rtx outof_input, rtx into_input, rtx op1, | |
840 | rtx outof_target, rtx into_target, | |
841 | int unsignedp, enum optab_methods methods, | |
842 | unsigned HOST_WIDE_INT shift_mask) | |
843 | { | |
844 | optab reverse_unsigned_shift, unsigned_shift; | |
845 | rtx tmp, carries; | |
846 | ||
847 | reverse_unsigned_shift = (binoptab == ashl_optab ? lshr_optab : ashl_optab); | |
848 | unsigned_shift = (binoptab == ashl_optab ? ashl_optab : lshr_optab); | |
849 | ||
850 | /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT. | |
851 | We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in | |
852 | the opposite direction to BINOPTAB. */ | |
853 | if (CONSTANT_P (op1) || shift_mask >= BITS_PER_WORD) | |
854 | { | |
855 | carries = outof_input; | |
856 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
857 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
858 | 0, true, methods); | |
859 | } | |
860 | else | |
861 | { | |
862 | /* We must avoid shifting by BITS_PER_WORD bits since that is either | |
863 | the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or | |
b01d837f | 864 | has unknown behavior. Do a single shift first, then shift by the |
273a2526 RS |
865 | remainder. It's OK to use ~OP1 as the remainder if shift counts |
866 | are truncated to the mode size. */ | |
867 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
868 | outof_input, const1_rtx, 0, unsignedp, methods); | |
869 | if (shift_mask == BITS_PER_WORD - 1) | |
870 | { | |
871 | tmp = immed_double_const (-1, -1, op1_mode); | |
872 | tmp = simplify_expand_binop (op1_mode, xor_optab, op1, tmp, | |
873 | 0, true, methods); | |
874 | } | |
875 | else | |
876 | { | |
877 | tmp = immed_double_const (BITS_PER_WORD - 1, 0, op1_mode); | |
878 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
879 | 0, true, methods); | |
880 | } | |
881 | } | |
882 | if (tmp == 0 || carries == 0) | |
883 | return false; | |
884 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
885 | carries, tmp, 0, unsignedp, methods); | |
886 | if (carries == 0) | |
887 | return false; | |
888 | ||
889 | /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT | |
890 | so the result can go directly into INTO_TARGET if convenient. */ | |
891 | tmp = expand_binop (word_mode, unsigned_shift, into_input, op1, | |
892 | into_target, unsignedp, methods); | |
893 | if (tmp == 0) | |
894 | return false; | |
895 | ||
896 | /* Now OR in the bits carried over from OUTOF_INPUT. */ | |
897 | if (!force_expand_binop (word_mode, ior_optab, tmp, carries, | |
898 | into_target, unsignedp, methods)) | |
899 | return false; | |
900 | ||
901 | /* Use a standard word_mode shift for the out-of half. */ | |
902 | if (outof_target != 0) | |
903 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
904 | outof_target, unsignedp, methods)) | |
905 | return false; | |
906 | ||
907 | return true; | |
908 | } | |
909 | ||
910 | ||
911 | #ifdef HAVE_conditional_move | |
912 | /* Try implementing expand_doubleword_shift using conditional moves. | |
913 | The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true, | |
914 | otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1 | |
915 | are the shift counts to use in the former and latter case. All other | |
916 | arguments are the same as the parent routine. */ | |
917 | ||
918 | static bool | |
919 | expand_doubleword_shift_condmove (enum machine_mode op1_mode, optab binoptab, | |
920 | enum rtx_code cmp_code, rtx cmp1, rtx cmp2, | |
921 | rtx outof_input, rtx into_input, | |
922 | rtx subword_op1, rtx superword_op1, | |
923 | rtx outof_target, rtx into_target, | |
924 | int unsignedp, enum optab_methods methods, | |
925 | unsigned HOST_WIDE_INT shift_mask) | |
926 | { | |
927 | rtx outof_superword, into_superword; | |
928 | ||
929 | /* Put the superword version of the output into OUTOF_SUPERWORD and | |
930 | INTO_SUPERWORD. */ | |
931 | outof_superword = outof_target != 0 ? gen_reg_rtx (word_mode) : 0; | |
932 | if (outof_target != 0 && subword_op1 == superword_op1) | |
933 | { | |
934 | /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in | |
935 | OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */ | |
936 | into_superword = outof_target; | |
937 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
938 | outof_superword, 0, unsignedp, methods)) | |
939 | return false; | |
940 | } | |
941 | else | |
942 | { | |
943 | into_superword = gen_reg_rtx (word_mode); | |
944 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
945 | outof_superword, into_superword, | |
946 | unsignedp, methods)) | |
947 | return false; | |
948 | } | |
26277d41 | 949 | |
273a2526 RS |
950 | /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */ |
951 | if (!expand_subword_shift (op1_mode, binoptab, | |
952 | outof_input, into_input, subword_op1, | |
953 | outof_target, into_target, | |
954 | unsignedp, methods, shift_mask)) | |
955 | return false; | |
956 | ||
957 | /* Select between them. Do the INTO half first because INTO_SUPERWORD | |
958 | might be the current value of OUTOF_TARGET. */ | |
959 | if (!emit_conditional_move (into_target, cmp_code, cmp1, cmp2, op1_mode, | |
960 | into_target, into_superword, word_mode, false)) | |
961 | return false; | |
962 | ||
963 | if (outof_target != 0) | |
964 | if (!emit_conditional_move (outof_target, cmp_code, cmp1, cmp2, op1_mode, | |
965 | outof_target, outof_superword, | |
966 | word_mode, false)) | |
967 | return false; | |
968 | ||
969 | return true; | |
970 | } | |
971 | #endif | |
972 | ||
973 | /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts. | |
974 | OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first | |
975 | input operand; the shift moves bits in the direction OUTOF_INPUT-> | |
976 | INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words | |
977 | of the target. OP1 is the shift count and OP1_MODE is its mode. | |
978 | If OP1 is constant, it will have been truncated as appropriate | |
979 | and is known to be nonzero. | |
980 | ||
981 | If SHIFT_MASK is zero, the result of word shifts is undefined when the | |
982 | shift count is outside the range [0, BITS_PER_WORD). This routine must | |
983 | avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2). | |
984 | ||
985 | If SHIFT_MASK is nonzero, all word-mode shift counts are effectively | |
986 | masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will | |
987 | fill with zeros or sign bits as appropriate. | |
988 | ||
2a7e31df | 989 | If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize |
273a2526 RS |
990 | a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1. |
991 | Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED. | |
992 | In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2) | |
993 | are undefined. | |
994 | ||
995 | BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function | |
996 | may not use INTO_INPUT after modifying INTO_TARGET, and similarly for | |
997 | OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent | |
998 | function wants to calculate it itself. | |
999 | ||
1000 | Return true if the shift could be successfully synthesized. */ | |
1001 | ||
1002 | static bool | |
1003 | expand_doubleword_shift (enum machine_mode op1_mode, optab binoptab, | |
1004 | rtx outof_input, rtx into_input, rtx op1, | |
1005 | rtx outof_target, rtx into_target, | |
1006 | int unsignedp, enum optab_methods methods, | |
1007 | unsigned HOST_WIDE_INT shift_mask) | |
1008 | { | |
1009 | rtx superword_op1, tmp, cmp1, cmp2; | |
1010 | rtx subword_label, done_label; | |
1011 | enum rtx_code cmp_code; | |
1012 | ||
1013 | /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will | |
1014 | fill the result with sign or zero bits as appropriate. If so, the value | |
1015 | of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call | |
1016 | this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT | |
1017 | and INTO_INPUT), then emit code to set up OUTOF_TARGET. | |
1018 | ||
1019 | This isn't worthwhile for constant shifts since the optimizers will | |
1020 | cope better with in-range shift counts. */ | |
1021 | if (shift_mask >= BITS_PER_WORD | |
1022 | && outof_target != 0 | |
1023 | && !CONSTANT_P (op1)) | |
1024 | { | |
1025 | if (!expand_doubleword_shift (op1_mode, binoptab, | |
1026 | outof_input, into_input, op1, | |
1027 | 0, into_target, | |
1028 | unsignedp, methods, shift_mask)) | |
1029 | return false; | |
1030 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
1031 | outof_target, unsignedp, methods)) | |
1032 | return false; | |
1033 | return true; | |
1034 | } | |
1035 | ||
1036 | /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2) | |
1037 | is true when the effective shift value is less than BITS_PER_WORD. | |
1038 | Set SUPERWORD_OP1 to the shift count that should be used to shift | |
1039 | OUTOF_INPUT into INTO_TARGET when the condition is false. */ | |
1040 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
1041 | if (!CONSTANT_P (op1) && shift_mask == BITS_PER_WORD - 1) | |
1042 | { | |
1043 | /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1 | |
1044 | is a subword shift count. */ | |
1045 | cmp1 = simplify_expand_binop (op1_mode, and_optab, op1, tmp, | |
1046 | 0, true, methods); | |
1047 | cmp2 = CONST0_RTX (op1_mode); | |
1048 | cmp_code = EQ; | |
1049 | superword_op1 = op1; | |
1050 | } | |
1051 | else | |
1052 | { | |
1053 | /* Set CMP1 to OP1 - BITS_PER_WORD. */ | |
1054 | cmp1 = simplify_expand_binop (op1_mode, sub_optab, op1, tmp, | |
1055 | 0, true, methods); | |
1056 | cmp2 = CONST0_RTX (op1_mode); | |
1057 | cmp_code = LT; | |
1058 | superword_op1 = cmp1; | |
1059 | } | |
1060 | if (cmp1 == 0) | |
1061 | return false; | |
1062 | ||
1063 | /* If we can compute the condition at compile time, pick the | |
1064 | appropriate subroutine. */ | |
1065 | tmp = simplify_relational_operation (cmp_code, SImode, op1_mode, cmp1, cmp2); | |
481683e1 | 1066 | if (tmp != 0 && CONST_INT_P (tmp)) |
273a2526 RS |
1067 | { |
1068 | if (tmp == const0_rtx) | |
1069 | return expand_superword_shift (binoptab, outof_input, superword_op1, | |
1070 | outof_target, into_target, | |
1071 | unsignedp, methods); | |
1072 | else | |
1073 | return expand_subword_shift (op1_mode, binoptab, | |
1074 | outof_input, into_input, op1, | |
1075 | outof_target, into_target, | |
1076 | unsignedp, methods, shift_mask); | |
1077 | } | |
1078 | ||
1079 | #ifdef HAVE_conditional_move | |
1080 | /* Try using conditional moves to generate straight-line code. */ | |
1081 | { | |
1082 | rtx start = get_last_insn (); | |
1083 | if (expand_doubleword_shift_condmove (op1_mode, binoptab, | |
1084 | cmp_code, cmp1, cmp2, | |
1085 | outof_input, into_input, | |
1086 | op1, superword_op1, | |
1087 | outof_target, into_target, | |
1088 | unsignedp, methods, shift_mask)) | |
1089 | return true; | |
1090 | delete_insns_since (start); | |
1091 | } | |
1092 | #endif | |
1093 | ||
1094 | /* As a last resort, use branches to select the correct alternative. */ | |
1095 | subword_label = gen_label_rtx (); | |
1096 | done_label = gen_label_rtx (); | |
1097 | ||
2763a67e | 1098 | NO_DEFER_POP; |
273a2526 | 1099 | do_compare_rtx_and_jump (cmp1, cmp2, cmp_code, false, op1_mode, |
40e90eac | 1100 | 0, 0, subword_label, -1); |
2763a67e | 1101 | OK_DEFER_POP; |
273a2526 RS |
1102 | |
1103 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
1104 | outof_target, into_target, | |
1105 | unsignedp, methods)) | |
1106 | return false; | |
1107 | ||
1108 | emit_jump_insn (gen_jump (done_label)); | |
1109 | emit_barrier (); | |
1110 | emit_label (subword_label); | |
1111 | ||
1112 | if (!expand_subword_shift (op1_mode, binoptab, | |
1113 | outof_input, into_input, op1, | |
1114 | outof_target, into_target, | |
1115 | unsignedp, methods, shift_mask)) | |
1116 | return false; | |
1117 | ||
1118 | emit_label (done_label); | |
1119 | return true; | |
1120 | } | |
c64f913e | 1121 | \f |
f927760b RS |
1122 | /* Subroutine of expand_binop. Perform a double word multiplication of |
1123 | operands OP0 and OP1 both of mode MODE, which is exactly twice as wide | |
1124 | as the target's word_mode. This function return NULL_RTX if anything | |
1125 | goes wrong, in which case it may have already emitted instructions | |
1126 | which need to be deleted. | |
1127 | ||
1128 | If we want to multiply two two-word values and have normal and widening | |
1129 | multiplies of single-word values, we can do this with three smaller | |
d70dcf29 | 1130 | multiplications. |
f927760b RS |
1131 | |
1132 | The multiplication proceeds as follows: | |
1133 | _______________________ | |
1134 | [__op0_high_|__op0_low__] | |
1135 | _______________________ | |
1136 | * [__op1_high_|__op1_low__] | |
1137 | _______________________________________________ | |
1138 | _______________________ | |
1139 | (1) [__op0_low__*__op1_low__] | |
1140 | _______________________ | |
1141 | (2a) [__op0_low__*__op1_high_] | |
1142 | _______________________ | |
1143 | (2b) [__op0_high_*__op1_low__] | |
1144 | _______________________ | |
1145 | (3) [__op0_high_*__op1_high_] | |
1146 | ||
1147 | ||
1148 | This gives a 4-word result. Since we are only interested in the | |
1149 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1150 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1151 | calculated using non-widening multiplication. | |
1152 | ||
1153 | (1), however, needs to be calculated with an unsigned widening | |
1154 | multiplication. If this operation is not directly supported we | |
1155 | try using a signed widening multiplication and adjust the result. | |
1156 | This adjustment works as follows: | |
1157 | ||
1158 | If both operands are positive then no adjustment is needed. | |
1159 | ||
1160 | If the operands have different signs, for example op0_low < 0 and | |
1161 | op1_low >= 0, the instruction treats the most significant bit of | |
1162 | op0_low as a sign bit instead of a bit with significance | |
1163 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1164 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1165 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1166 | the result. | |
1167 | ||
1168 | Similarly, if both operands are negative, we need to add | |
1169 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1170 | ||
1171 | We use a trick to adjust quickly. We logically shift op0_low right | |
1172 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1173 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1174 | logical shift exists, we do an arithmetic right shift and subtract | |
1175 | the 0 or -1. */ | |
1176 | ||
1177 | static rtx | |
1178 | expand_doubleword_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
1179 | bool umulp, enum optab_methods methods) | |
1180 | { | |
1181 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1182 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1183 | rtx wordm1 = umulp ? NULL_RTX : GEN_INT (BITS_PER_WORD - 1); | |
1184 | rtx product, adjust, product_high, temp; | |
1185 | ||
1186 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1187 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1188 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1189 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1190 | ||
1191 | /* If we're using an unsigned multiply to directly compute the product | |
1192 | of the low-order words of the operands and perform any required | |
1193 | adjustments of the operands, we begin by trying two more multiplications | |
1194 | and then computing the appropriate sum. | |
1195 | ||
1196 | We have checked above that the required addition is provided. | |
1197 | Full-word addition will normally always succeed, especially if | |
1198 | it is provided at all, so we don't worry about its failure. The | |
1199 | multiplication may well fail, however, so we do handle that. */ | |
1200 | ||
1201 | if (!umulp) | |
1202 | { | |
1203 | /* ??? This could be done with emit_store_flag where available. */ | |
1204 | temp = expand_binop (word_mode, lshr_optab, op0_low, wordm1, | |
1205 | NULL_RTX, 1, methods); | |
1206 | if (temp) | |
1207 | op0_high = expand_binop (word_mode, add_optab, op0_high, temp, | |
69f39b11 | 1208 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1209 | else |
1210 | { | |
1211 | temp = expand_binop (word_mode, ashr_optab, op0_low, wordm1, | |
1212 | NULL_RTX, 0, methods); | |
1213 | if (!temp) | |
1214 | return NULL_RTX; | |
1215 | op0_high = expand_binop (word_mode, sub_optab, op0_high, temp, | |
69f39b11 | 1216 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1217 | } |
1218 | ||
1219 | if (!op0_high) | |
1220 | return NULL_RTX; | |
1221 | } | |
1222 | ||
1223 | adjust = expand_binop (word_mode, smul_optab, op0_high, op1_low, | |
1224 | NULL_RTX, 0, OPTAB_DIRECT); | |
1225 | if (!adjust) | |
1226 | return NULL_RTX; | |
1227 | ||
1228 | /* OP0_HIGH should now be dead. */ | |
1229 | ||
1230 | if (!umulp) | |
1231 | { | |
1232 | /* ??? This could be done with emit_store_flag where available. */ | |
1233 | temp = expand_binop (word_mode, lshr_optab, op1_low, wordm1, | |
1234 | NULL_RTX, 1, methods); | |
1235 | if (temp) | |
1236 | op1_high = expand_binop (word_mode, add_optab, op1_high, temp, | |
69f39b11 | 1237 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1238 | else |
1239 | { | |
1240 | temp = expand_binop (word_mode, ashr_optab, op1_low, wordm1, | |
1241 | NULL_RTX, 0, methods); | |
1242 | if (!temp) | |
1243 | return NULL_RTX; | |
1244 | op1_high = expand_binop (word_mode, sub_optab, op1_high, temp, | |
69f39b11 | 1245 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1246 | } |
1247 | ||
1248 | if (!op1_high) | |
1249 | return NULL_RTX; | |
1250 | } | |
1251 | ||
1252 | temp = expand_binop (word_mode, smul_optab, op1_high, op0_low, | |
1253 | NULL_RTX, 0, OPTAB_DIRECT); | |
1254 | if (!temp) | |
1255 | return NULL_RTX; | |
1256 | ||
1257 | /* OP1_HIGH should now be dead. */ | |
1258 | ||
1259 | adjust = expand_binop (word_mode, add_optab, adjust, temp, | |
c701e857 | 1260 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1261 | |
1262 | if (target && !REG_P (target)) | |
1263 | target = NULL_RTX; | |
1264 | ||
1265 | if (umulp) | |
1266 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1267 | target, 1, OPTAB_DIRECT); | |
1268 | else | |
1269 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, | |
1270 | target, 1, OPTAB_DIRECT); | |
1271 | ||
1272 | if (!product) | |
1273 | return NULL_RTX; | |
1274 | ||
1275 | product_high = operand_subword (product, high, 1, mode); | |
1276 | adjust = expand_binop (word_mode, add_optab, product_high, adjust, | |
c701e857 | 1277 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1278 | emit_move_insn (product_high, adjust); |
1279 | return product; | |
1280 | } | |
1281 | \f | |
ef89d648 ZW |
1282 | /* Wrapper around expand_binop which takes an rtx code to specify |
1283 | the operation to perform, not an optab pointer. All other | |
1284 | arguments are the same. */ | |
1285 | rtx | |
0c20a65f AJ |
1286 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
1287 | rtx op1, rtx target, int unsignedp, | |
1288 | enum optab_methods methods) | |
ef89d648 | 1289 | { |
7e1a450d | 1290 | optab binop = code_to_optab[(int) code]; |
e3feb571 | 1291 | gcc_assert (binop); |
ef89d648 ZW |
1292 | |
1293 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
1294 | } | |
1295 | ||
665d18c6 PB |
1296 | /* Return whether OP0 and OP1 should be swapped when expanding a commutative |
1297 | binop. Order them according to commutative_operand_precedence and, if | |
1298 | possible, try to put TARGET or a pseudo first. */ | |
1299 | static bool | |
1300 | swap_commutative_operands_with_target (rtx target, rtx op0, rtx op1) | |
1301 | { | |
1302 | int op0_prec = commutative_operand_precedence (op0); | |
1303 | int op1_prec = commutative_operand_precedence (op1); | |
1304 | ||
1305 | if (op0_prec < op1_prec) | |
1306 | return true; | |
1307 | ||
1308 | if (op0_prec > op1_prec) | |
1309 | return false; | |
1310 | ||
1311 | /* With equal precedence, both orders are ok, but it is better if the | |
1312 | first operand is TARGET, or if both TARGET and OP0 are pseudos. */ | |
1313 | if (target == 0 || REG_P (target)) | |
1314 | return (REG_P (op1) && !REG_P (op0)) || target == op1; | |
1315 | else | |
1316 | return rtx_equal_p (op1, target); | |
1317 | } | |
1318 | ||
62442ab9 RS |
1319 | /* Return true if BINOPTAB implements a shift operation. */ |
1320 | ||
1321 | static bool | |
1322 | shift_optab_p (optab binoptab) | |
1323 | { | |
1324 | switch (binoptab->code) | |
1325 | { | |
1326 | case ASHIFT: | |
0f996086 CF |
1327 | case SS_ASHIFT: |
1328 | case US_ASHIFT: | |
62442ab9 RS |
1329 | case ASHIFTRT: |
1330 | case LSHIFTRT: | |
1331 | case ROTATE: | |
1332 | case ROTATERT: | |
1333 | return true; | |
1334 | ||
1335 | default: | |
1336 | return false; | |
1337 | } | |
1338 | } | |
1339 | ||
15dc95cb | 1340 | /* Return true if BINOPTAB implements a commutative binary operation. */ |
62442ab9 RS |
1341 | |
1342 | static bool | |
1343 | commutative_optab_p (optab binoptab) | |
1344 | { | |
1345 | return (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH | |
1346 | || binoptab == smul_widen_optab | |
1347 | || binoptab == umul_widen_optab | |
1348 | || binoptab == smul_highpart_optab | |
1349 | || binoptab == umul_highpart_optab); | |
1350 | } | |
1351 | ||
1352 | /* X is to be used in mode MODE as an operand to BINOPTAB. If we're | |
1353 | optimizing, and if the operand is a constant that costs more than | |
1354 | 1 instruction, force the constant into a register and return that | |
1355 | register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */ | |
1356 | ||
1357 | static rtx | |
1358 | avoid_expensive_constant (enum machine_mode mode, optab binoptab, | |
1359 | rtx x, bool unsignedp) | |
1360 | { | |
c99102b8 | 1361 | bool speed = optimize_insn_for_speed_p (); |
fdb2c684 | 1362 | |
47de45c6 RS |
1363 | if (mode != VOIDmode |
1364 | && optimize | |
62442ab9 | 1365 | && CONSTANT_P (x) |
c99102b8 | 1366 | && rtx_cost (x, binoptab->code, speed) > rtx_cost (x, SET, speed)) |
62442ab9 | 1367 | { |
481683e1 | 1368 | if (CONST_INT_P (x)) |
c722c7da RS |
1369 | { |
1370 | HOST_WIDE_INT intval = trunc_int_for_mode (INTVAL (x), mode); | |
1371 | if (intval != INTVAL (x)) | |
1372 | x = GEN_INT (intval); | |
1373 | } | |
1374 | else | |
62442ab9 RS |
1375 | x = convert_modes (mode, VOIDmode, x, unsignedp); |
1376 | x = force_reg (mode, x); | |
1377 | } | |
1378 | return x; | |
1379 | } | |
665d18c6 | 1380 | |
0aa222d1 SL |
1381 | /* Helper function for expand_binop: handle the case where there |
1382 | is an insn that directly implements the indicated operation. | |
1383 | Returns null if this is not possible. */ | |
1384 | static rtx | |
1385 | expand_binop_directly (enum machine_mode mode, optab binoptab, | |
1386 | rtx op0, rtx op1, | |
1387 | rtx target, int unsignedp, enum optab_methods methods, | |
62442ab9 | 1388 | rtx last) |
0aa222d1 | 1389 | { |
947131ba | 1390 | int icode = (int) optab_handler (binoptab, mode); |
0aa222d1 SL |
1391 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
1392 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
1393 | enum machine_mode tmp_mode; | |
62442ab9 | 1394 | bool commutative_p; |
0aa222d1 SL |
1395 | rtx pat; |
1396 | rtx xop0 = op0, xop1 = op1; | |
1397 | rtx temp; | |
62442ab9 | 1398 | rtx swap; |
b8698a0f | 1399 | |
0aa222d1 SL |
1400 | if (target) |
1401 | temp = target; | |
1402 | else | |
1403 | temp = gen_reg_rtx (mode); | |
62442ab9 | 1404 | |
0aa222d1 SL |
1405 | /* If it is a commutative operator and the modes would match |
1406 | if we would swap the operands, we can save the conversions. */ | |
62442ab9 RS |
1407 | commutative_p = commutative_optab_p (binoptab); |
1408 | if (commutative_p | |
1409 | && GET_MODE (xop0) != mode0 && GET_MODE (xop1) != mode1 | |
1410 | && GET_MODE (xop0) == mode1 && GET_MODE (xop1) == mode1) | |
0aa222d1 | 1411 | { |
62442ab9 RS |
1412 | swap = xop0; |
1413 | xop0 = xop1; | |
1414 | xop1 = swap; | |
0aa222d1 | 1415 | } |
b8698a0f | 1416 | |
62442ab9 RS |
1417 | /* If we are optimizing, force expensive constants into a register. */ |
1418 | xop0 = avoid_expensive_constant (mode0, binoptab, xop0, unsignedp); | |
1419 | if (!shift_optab_p (binoptab)) | |
1420 | xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp); | |
1421 | ||
0aa222d1 SL |
1422 | /* In case the insn wants input operands in modes different from |
1423 | those of the actual operands, convert the operands. It would | |
1424 | seem that we don't need to convert CONST_INTs, but we do, so | |
1425 | that they're properly zero-extended, sign-extended or truncated | |
1426 | for their mode. */ | |
b8698a0f | 1427 | |
62442ab9 | 1428 | if (GET_MODE (xop0) != mode0 && mode0 != VOIDmode) |
0aa222d1 | 1429 | xop0 = convert_modes (mode0, |
62442ab9 RS |
1430 | GET_MODE (xop0) != VOIDmode |
1431 | ? GET_MODE (xop0) | |
0aa222d1 SL |
1432 | : mode, |
1433 | xop0, unsignedp); | |
b8698a0f | 1434 | |
62442ab9 | 1435 | if (GET_MODE (xop1) != mode1 && mode1 != VOIDmode) |
0aa222d1 | 1436 | xop1 = convert_modes (mode1, |
62442ab9 RS |
1437 | GET_MODE (xop1) != VOIDmode |
1438 | ? GET_MODE (xop1) | |
0aa222d1 SL |
1439 | : mode, |
1440 | xop1, unsignedp); | |
b8698a0f | 1441 | |
62442ab9 RS |
1442 | /* If operation is commutative, |
1443 | try to make the first operand a register. | |
1444 | Even better, try to make it the same as the target. | |
1445 | Also try to make the last operand a constant. */ | |
1446 | if (commutative_p | |
1447 | && swap_commutative_operands_with_target (target, xop0, xop1)) | |
1448 | { | |
1449 | swap = xop1; | |
1450 | xop1 = xop0; | |
1451 | xop0 = swap; | |
1452 | } | |
1453 | ||
0aa222d1 SL |
1454 | /* Now, if insn's predicates don't allow our operands, put them into |
1455 | pseudo regs. */ | |
b8698a0f | 1456 | |
0aa222d1 SL |
1457 | if (!insn_data[icode].operand[1].predicate (xop0, mode0) |
1458 | && mode0 != VOIDmode) | |
1459 | xop0 = copy_to_mode_reg (mode0, xop0); | |
b8698a0f | 1460 | |
0aa222d1 SL |
1461 | if (!insn_data[icode].operand[2].predicate (xop1, mode1) |
1462 | && mode1 != VOIDmode) | |
1463 | xop1 = copy_to_mode_reg (mode1, xop1); | |
b8698a0f L |
1464 | |
1465 | if (binoptab == vec_pack_trunc_optab | |
0aa222d1 SL |
1466 | || binoptab == vec_pack_usat_optab |
1467 | || binoptab == vec_pack_ssat_optab | |
1468 | || binoptab == vec_pack_ufix_trunc_optab | |
1469 | || binoptab == vec_pack_sfix_trunc_optab) | |
1470 | { | |
1471 | /* The mode of the result is different then the mode of the | |
1472 | arguments. */ | |
1473 | tmp_mode = insn_data[icode].operand[0].mode; | |
1474 | if (GET_MODE_NUNITS (tmp_mode) != 2 * GET_MODE_NUNITS (mode)) | |
1475 | return 0; | |
1476 | } | |
1477 | else | |
1478 | tmp_mode = mode; | |
1479 | ||
1480 | if (!insn_data[icode].operand[0].predicate (temp, tmp_mode)) | |
1481 | temp = gen_reg_rtx (tmp_mode); | |
b8698a0f | 1482 | |
0aa222d1 SL |
1483 | pat = GEN_FCN (icode) (temp, xop0, xop1); |
1484 | if (pat) | |
1485 | { | |
1486 | /* If PAT is composed of more than one insn, try to add an appropriate | |
1487 | REG_EQUAL note to it. If we can't because TEMP conflicts with an | |
1488 | operand, call expand_binop again, this time without a target. */ | |
1489 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX | |
1490 | && ! add_equal_note (pat, temp, binoptab->code, xop0, xop1)) | |
1491 | { | |
1492 | delete_insns_since (last); | |
1493 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, | |
1494 | unsignedp, methods); | |
1495 | } | |
b8698a0f | 1496 | |
0aa222d1 SL |
1497 | emit_insn (pat); |
1498 | return temp; | |
1499 | } | |
1500 | ||
1501 | delete_insns_since (last); | |
1502 | return NULL_RTX; | |
1503 | } | |
1504 | ||
77c9c6c2 RK |
1505 | /* Generate code to perform an operation specified by BINOPTAB |
1506 | on operands OP0 and OP1, with result having machine-mode MODE. | |
1507 | ||
1508 | UNSIGNEDP is for the case where we have to widen the operands | |
1509 | to perform the operation. It says to use zero-extension. | |
1510 | ||
1511 | If TARGET is nonzero, the value | |
1512 | is generated there, if it is convenient to do so. | |
1513 | In all cases an rtx is returned for the locus of the value; | |
1514 | this may or may not be TARGET. */ | |
1515 | ||
1516 | rtx | |
0c20a65f AJ |
1517 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
1518 | rtx target, int unsignedp, enum optab_methods methods) | |
77c9c6c2 | 1519 | { |
70864443 RK |
1520 | enum optab_methods next_methods |
1521 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
1522 | ? OPTAB_WIDEN : methods); | |
d858f359 | 1523 | enum mode_class mclass; |
77c9c6c2 | 1524 | enum machine_mode wider_mode; |
8a33f100 | 1525 | rtx libfunc; |
b3694847 | 1526 | rtx temp; |
abd418d3 | 1527 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
1528 | rtx last; |
1529 | ||
d858f359 | 1530 | mclass = GET_MODE_CLASS (mode); |
77c9c6c2 | 1531 | |
8aecce0a RK |
1532 | /* If subtracting an integer constant, convert this into an addition of |
1533 | the negated constant. */ | |
1534 | ||
481683e1 | 1535 | if (binoptab == sub_optab && CONST_INT_P (op1)) |
8aecce0a RK |
1536 | { |
1537 | op1 = negate_rtx (mode, op1); | |
1538 | binoptab = add_optab; | |
1539 | } | |
1540 | ||
77c9c6c2 RK |
1541 | /* Record where to delete back to if we backtrack. */ |
1542 | last = get_last_insn (); | |
1543 | ||
77c9c6c2 RK |
1544 | /* If we can do it with a three-operand insn, do so. */ |
1545 | ||
1546 | if (methods != OPTAB_MUST_WIDEN | |
947131ba | 1547 | && optab_handler (binoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 1548 | { |
0aa222d1 | 1549 | temp = expand_binop_directly (mode, binoptab, op0, op1, target, |
62442ab9 | 1550 | unsignedp, methods, last); |
0aa222d1 SL |
1551 | if (temp) |
1552 | return temp; | |
77c9c6c2 RK |
1553 | } |
1554 | ||
0aa222d1 SL |
1555 | /* If we were trying to rotate, and that didn't work, try rotating |
1556 | the other direction before falling back to shifts and bitwise-or. */ | |
1557 | if (((binoptab == rotl_optab | |
947131ba | 1558 | && optab_handler (rotr_optab, mode) != CODE_FOR_nothing) |
0aa222d1 | 1559 | || (binoptab == rotr_optab |
947131ba | 1560 | && optab_handler (rotl_optab, mode) != CODE_FOR_nothing)) |
d858f359 | 1561 | && mclass == MODE_INT) |
0f8594ee | 1562 | { |
0aa222d1 SL |
1563 | optab otheroptab = (binoptab == rotl_optab ? rotr_optab : rotl_optab); |
1564 | rtx newop1; | |
9ee34274 | 1565 | unsigned int bits = GET_MODE_BITSIZE (mode); |
0aa222d1 | 1566 | |
481683e1 | 1567 | if (CONST_INT_P (op1)) |
db826dae | 1568 | newop1 = GEN_INT (bits - INTVAL (op1)); |
0aa222d1 | 1569 | else if (targetm.shift_truncation_mask (mode) == bits - 1) |
db826dae | 1570 | newop1 = negate_rtx (GET_MODE (op1), op1); |
0aa222d1 | 1571 | else |
db826dae | 1572 | newop1 = expand_binop (GET_MODE (op1), sub_optab, |
0aa222d1 SL |
1573 | GEN_INT (bits), op1, |
1574 | NULL_RTX, unsignedp, OPTAB_DIRECT); | |
b8698a0f | 1575 | |
0aa222d1 | 1576 | temp = expand_binop_directly (mode, otheroptab, op0, newop1, |
62442ab9 | 1577 | target, unsignedp, methods, last); |
0aa222d1 SL |
1578 | if (temp) |
1579 | return temp; | |
0f8594ee MM |
1580 | } |
1581 | ||
5a5064dc RK |
1582 | /* If this is a multiply, see if we can do a widening operation that |
1583 | takes operands of this mode and makes a wider mode. */ | |
1584 | ||
86556d87 BE |
1585 | if (binoptab == smul_optab |
1586 | && GET_MODE_WIDER_MODE (mode) != VOIDmode | |
947131ba RS |
1587 | && (optab_handler ((unsignedp ? umul_widen_optab : smul_widen_optab), |
1588 | GET_MODE_WIDER_MODE (mode)) | |
5a5064dc RK |
1589 | != CODE_FOR_nothing)) |
1590 | { | |
1591 | temp = expand_binop (GET_MODE_WIDER_MODE (mode), | |
1592 | unsignedp ? umul_widen_optab : smul_widen_optab, | |
73d9a835 | 1593 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
5a5064dc | 1594 | |
70864443 RK |
1595 | if (temp != 0) |
1596 | { | |
28f52a4d R |
1597 | if (GET_MODE_CLASS (mode) == MODE_INT |
1598 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
1599 | GET_MODE_BITSIZE (GET_MODE (temp)))) | |
70864443 RK |
1600 | return gen_lowpart (mode, temp); |
1601 | else | |
1602 | return convert_to_mode (mode, temp, unsignedp); | |
1603 | } | |
5a5064dc RK |
1604 | } |
1605 | ||
9a856ec7 | 1606 | /* Look for a wider mode of the same class for which we think we |
5a5064dc RK |
1607 | can open-code the operation. Check for a widening multiply at the |
1608 | wider mode as well. */ | |
9a856ec7 | 1609 | |
d858f359 | 1610 | if (CLASS_HAS_WIDER_MODES_P (mclass) |
6f43c157 | 1611 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
86556d87 BE |
1612 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
1613 | wider_mode != VOIDmode; | |
9a856ec7 RK |
1614 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1615 | { | |
947131ba | 1616 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing |
5a5064dc RK |
1617 | || (binoptab == smul_optab |
1618 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
947131ba RS |
1619 | && (optab_handler ((unsignedp ? umul_widen_optab |
1620 | : smul_widen_optab), | |
1621 | GET_MODE_WIDER_MODE (wider_mode)) | |
5a5064dc | 1622 | != CODE_FOR_nothing))) |
9a856ec7 RK |
1623 | { |
1624 | rtx xop0 = op0, xop1 = op1; | |
1625 | int no_extend = 0; | |
1626 | ||
1627 | /* For certain integer operations, we need not actually extend | |
1628 | the narrow operands, as long as we will truncate | |
6d2f8887 | 1629 | the results to the same narrowness. */ |
9a856ec7 RK |
1630 | |
1631 | if ((binoptab == ior_optab || binoptab == and_optab | |
1632 | || binoptab == xor_optab | |
1633 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 1634 | || binoptab == smul_optab || binoptab == ashl_optab) |
d858f359 | 1635 | && mclass == MODE_INT) |
62442ab9 RS |
1636 | { |
1637 | no_extend = 1; | |
1638 | xop0 = avoid_expensive_constant (mode, binoptab, | |
1639 | xop0, unsignedp); | |
1640 | if (binoptab != ashl_optab) | |
1641 | xop1 = avoid_expensive_constant (mode, binoptab, | |
1642 | xop1, unsignedp); | |
1643 | } | |
9a856ec7 | 1644 | |
0661a3de | 1645 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
943cc242 RK |
1646 | |
1647 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 1648 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 1649 | no_extend && binoptab != ashl_optab); |
943cc242 | 1650 | |
b1ec3c92 | 1651 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
9a856ec7 RK |
1652 | unsignedp, OPTAB_DIRECT); |
1653 | if (temp) | |
1654 | { | |
d858f359 | 1655 | if (mclass != MODE_INT |
28f52a4d R |
1656 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
1657 | GET_MODE_BITSIZE (wider_mode))) | |
9a856ec7 RK |
1658 | { |
1659 | if (target == 0) | |
1660 | target = gen_reg_rtx (mode); | |
1661 | convert_move (target, temp, 0); | |
1662 | return target; | |
1663 | } | |
1664 | else | |
1665 | return gen_lowpart (mode, temp); | |
1666 | } | |
1667 | else | |
1668 | delete_insns_since (last); | |
1669 | } | |
1670 | } | |
1671 | ||
62442ab9 RS |
1672 | /* If operation is commutative, |
1673 | try to make the first operand a register. | |
1674 | Even better, try to make it the same as the target. | |
1675 | Also try to make the last operand a constant. */ | |
1676 | if (commutative_optab_p (binoptab) | |
1677 | && swap_commutative_operands_with_target (target, op0, op1)) | |
1678 | { | |
1679 | temp = op1; | |
1680 | op1 = op0; | |
1681 | op0 = temp; | |
1682 | } | |
1683 | ||
77c9c6c2 RK |
1684 | /* These can be done a word at a time. */ |
1685 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
d858f359 | 1686 | && mclass == MODE_INT |
77c9c6c2 | 1687 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
947131ba | 1688 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 1689 | { |
bb93b973 | 1690 | int i; |
77c9c6c2 | 1691 | rtx insns; |
77c9c6c2 RK |
1692 | |
1693 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
1694 | won't be accurate, so use a new target. */ | |
1695 | if (target == 0 || target == op0 || target == op1) | |
1696 | target = gen_reg_rtx (mode); | |
1697 | ||
1698 | start_sequence (); | |
1699 | ||
1700 | /* Do the actual arithmetic. */ | |
1701 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
1702 | { | |
1703 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 1704 | rtx x = expand_binop (word_mode, binoptab, |
77c9c6c2 RK |
1705 | operand_subword_force (op0, i, mode), |
1706 | operand_subword_force (op1, i, mode), | |
70864443 RK |
1707 | target_piece, unsignedp, next_methods); |
1708 | ||
1709 | if (x == 0) | |
1710 | break; | |
1711 | ||
77c9c6c2 RK |
1712 | if (target_piece != x) |
1713 | emit_move_insn (target_piece, x); | |
1714 | } | |
1715 | ||
1716 | insns = get_insns (); | |
1717 | end_sequence (); | |
1718 | ||
70864443 RK |
1719 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
1720 | { | |
d70dcf29 | 1721 | emit_insn (insns); |
70864443 RK |
1722 | return target; |
1723 | } | |
77c9c6c2 RK |
1724 | } |
1725 | ||
8c597270 | 1726 | /* Synthesize double word shifts from single word shifts. */ |
e5df894b RK |
1727 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
1728 | || binoptab == ashr_optab) | |
d858f359 | 1729 | && mclass == MODE_INT |
481683e1 | 1730 | && (CONST_INT_P (op1) || optimize_insn_for_speed_p ()) |
8c597270 | 1731 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
947131ba RS |
1732 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing |
1733 | && optab_handler (ashl_optab, word_mode) != CODE_FOR_nothing | |
1734 | && optab_handler (lshr_optab, word_mode) != CODE_FOR_nothing) | |
8c597270 | 1735 | { |
273a2526 RS |
1736 | unsigned HOST_WIDE_INT shift_mask, double_shift_mask; |
1737 | enum machine_mode op1_mode; | |
8c597270 | 1738 | |
273a2526 RS |
1739 | double_shift_mask = targetm.shift_truncation_mask (mode); |
1740 | shift_mask = targetm.shift_truncation_mask (word_mode); | |
1741 | op1_mode = GET_MODE (op1) != VOIDmode ? GET_MODE (op1) : word_mode; | |
8c597270 | 1742 | |
273a2526 | 1743 | /* Apply the truncation to constant shifts. */ |
481683e1 | 1744 | if (double_shift_mask > 0 && CONST_INT_P (op1)) |
273a2526 | 1745 | op1 = GEN_INT (INTVAL (op1) & double_shift_mask); |
8c597270 | 1746 | |
273a2526 RS |
1747 | if (op1 == CONST0_RTX (op1_mode)) |
1748 | return op0; | |
8c597270 | 1749 | |
273a2526 RS |
1750 | /* Make sure that this is a combination that expand_doubleword_shift |
1751 | can handle. See the comments there for details. */ | |
1752 | if (double_shift_mask == 0 | |
1753 | || (shift_mask == BITS_PER_WORD - 1 | |
1754 | && double_shift_mask == BITS_PER_WORD * 2 - 1)) | |
8c597270 | 1755 | { |
d70dcf29 | 1756 | rtx insns; |
273a2526 RS |
1757 | rtx into_target, outof_target; |
1758 | rtx into_input, outof_input; | |
1759 | int left_shift, outof_word; | |
8c597270 | 1760 | |
273a2526 RS |
1761 | /* If TARGET is the same as one of the operands, the REG_EQUAL note |
1762 | won't be accurate, so use a new target. */ | |
1763 | if (target == 0 || target == op0 || target == op1) | |
1764 | target = gen_reg_rtx (mode); | |
8c597270 | 1765 | |
273a2526 | 1766 | start_sequence (); |
8c597270 | 1767 | |
273a2526 RS |
1768 | /* OUTOF_* is the word we are shifting bits away from, and |
1769 | INTO_* is the word that we are shifting bits towards, thus | |
1770 | they differ depending on the direction of the shift and | |
1771 | WORDS_BIG_ENDIAN. */ | |
70864443 | 1772 | |
273a2526 RS |
1773 | left_shift = binoptab == ashl_optab; |
1774 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
70864443 | 1775 | |
273a2526 RS |
1776 | outof_target = operand_subword (target, outof_word, 1, mode); |
1777 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
cf2f7113 | 1778 | |
273a2526 RS |
1779 | outof_input = operand_subword_force (op0, outof_word, mode); |
1780 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
0c20a65f | 1781 | |
273a2526 RS |
1782 | if (expand_doubleword_shift (op1_mode, binoptab, |
1783 | outof_input, into_input, op1, | |
1784 | outof_target, into_target, | |
f8bdb931 | 1785 | unsignedp, next_methods, shift_mask)) |
273a2526 RS |
1786 | { |
1787 | insns = get_insns (); | |
1788 | end_sequence (); | |
8c597270 | 1789 | |
d70dcf29 | 1790 | emit_insn (insns); |
273a2526 RS |
1791 | return target; |
1792 | } | |
1793 | end_sequence (); | |
70864443 | 1794 | } |
8c597270 JW |
1795 | } |
1796 | ||
1797 | /* Synthesize double word rotates from single word shifts. */ | |
1798 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
d858f359 | 1799 | && mclass == MODE_INT |
481683e1 | 1800 | && CONST_INT_P (op1) |
8c597270 | 1801 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
947131ba RS |
1802 | && optab_handler (ashl_optab, word_mode) != CODE_FOR_nothing |
1803 | && optab_handler (lshr_optab, word_mode) != CODE_FOR_nothing) | |
8c597270 | 1804 | { |
ebd8b60d | 1805 | rtx insns; |
8c597270 JW |
1806 | rtx into_target, outof_target; |
1807 | rtx into_input, outof_input; | |
70864443 | 1808 | rtx inter; |
8c597270 JW |
1809 | int shift_count, left_shift, outof_word; |
1810 | ||
1811 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
0c0ab0f1 OH |
1812 | won't be accurate, so use a new target. Do this also if target is not |
1813 | a REG, first because having a register instead may open optimization | |
1ae58c30 | 1814 | opportunities, and second because if target and op0 happen to be MEMs |
0c0ab0f1 OH |
1815 | designating the same location, we would risk clobbering it too early |
1816 | in the code sequence we generate below. */ | |
1817 | if (target == 0 || target == op0 || target == op1 || ! REG_P (target)) | |
8c597270 JW |
1818 | target = gen_reg_rtx (mode); |
1819 | ||
1820 | start_sequence (); | |
1821 | ||
1822 | shift_count = INTVAL (op1); | |
1823 | ||
1824 | /* OUTOF_* is the word we are shifting bits away from, and | |
1825 | INTO_* is the word that we are shifting bits towards, thus | |
1826 | they differ depending on the direction of the shift and | |
1827 | WORDS_BIG_ENDIAN. */ | |
1828 | ||
1829 | left_shift = (binoptab == rotl_optab); | |
1830 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1831 | ||
1832 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1833 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1834 | ||
1835 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1836 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1837 | ||
1838 | if (shift_count == BITS_PER_WORD) | |
1839 | { | |
1840 | /* This is just a word swap. */ | |
1841 | emit_move_insn (outof_target, into_input); | |
1842 | emit_move_insn (into_target, outof_input); | |
70864443 | 1843 | inter = const0_rtx; |
8c597270 JW |
1844 | } |
1845 | else | |
1846 | { | |
1847 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1848 | rtx first_shift_count, second_shift_count; | |
1849 | optab reverse_unsigned_shift, unsigned_shift; | |
1850 | ||
1851 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1852 | ? lshr_optab : ashl_optab); | |
1853 | ||
1854 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1855 | ? ashl_optab : lshr_optab); | |
1856 | ||
1857 | if (shift_count > BITS_PER_WORD) | |
1858 | { | |
1859 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
7e1a450d | 1860 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
8c597270 JW |
1861 | } |
1862 | else | |
1863 | { | |
1864 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1865 | second_shift_count = GEN_INT (shift_count); | |
1866 | } | |
1867 | ||
1868 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1869 | outof_input, first_shift_count, | |
70864443 | 1870 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1871 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1872 | into_input, second_shift_count, | |
5be5c8d4 | 1873 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1874 | |
1875 | if (into_temp1 != 0 && into_temp2 != 0) | |
1876 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1877 | into_target, unsignedp, next_methods); | |
1878 | else | |
1879 | inter = 0; | |
1880 | ||
cb5b00cf | 1881 | if (inter != 0 && inter != into_target) |
70864443 | 1882 | emit_move_insn (into_target, inter); |
8c597270 JW |
1883 | |
1884 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1885 | into_input, first_shift_count, | |
70864443 | 1886 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1887 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1888 | outof_input, second_shift_count, | |
5be5c8d4 | 1889 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1890 | |
1891 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1892 | inter = expand_binop (word_mode, ior_optab, | |
1893 | outof_temp1, outof_temp2, | |
1894 | outof_target, unsignedp, next_methods); | |
1895 | ||
cb5b00cf | 1896 | if (inter != 0 && inter != outof_target) |
70864443 | 1897 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1898 | } |
1899 | ||
1900 | insns = get_insns (); | |
1901 | end_sequence (); | |
1902 | ||
70864443 RK |
1903 | if (inter != 0) |
1904 | { | |
ebd8b60d | 1905 | emit_insn (insns); |
70864443 RK |
1906 | return target; |
1907 | } | |
8c597270 JW |
1908 | } |
1909 | ||
77c9c6c2 RK |
1910 | /* These can be done a word at a time by propagating carries. */ |
1911 | if ((binoptab == add_optab || binoptab == sub_optab) | |
d858f359 | 1912 | && mclass == MODE_INT |
77c9c6c2 | 1913 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD |
947131ba | 1914 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 1915 | { |
e2500fed | 1916 | unsigned int i; |
77c9c6c2 | 1917 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
a4b5414c | 1918 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
07444f1d | 1919 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
64de6c0a | 1920 | rtx xop0, xop1, xtarget; |
77c9c6c2 RK |
1921 | |
1922 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1923 | value is one of those, use it. Otherwise, use 1 since it is the | |
1924 | one easiest to get. */ | |
1925 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1926 | int normalizep = STORE_FLAG_VALUE; | |
1927 | #else | |
1928 | int normalizep = 1; | |
1929 | #endif | |
1930 | ||
1931 | /* Prepare the operands. */ | |
cee85023 RS |
1932 | xop0 = force_reg (mode, op0); |
1933 | xop1 = force_reg (mode, op1); | |
77c9c6c2 | 1934 | |
64de6c0a DE |
1935 | xtarget = gen_reg_rtx (mode); |
1936 | ||
f8cfc6aa | 1937 | if (target == 0 || !REG_P (target)) |
64de6c0a | 1938 | target = xtarget; |
77c9c6c2 | 1939 | |
af2cc4dd | 1940 | /* Indicate for flow that the entire target reg is being set. */ |
f8cfc6aa | 1941 | if (REG_P (target)) |
c41c1387 | 1942 | emit_clobber (xtarget); |
af2cc4dd | 1943 | |
77c9c6c2 RK |
1944 | /* Do the actual arithmetic. */ |
1945 | for (i = 0; i < nwords; i++) | |
1946 | { | |
1947 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
64de6c0a | 1948 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
cee85023 RS |
1949 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
1950 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
77c9c6c2 RK |
1951 | rtx x; |
1952 | ||
1953 | /* Main add/subtract of the input operands. */ | |
34e56753 | 1954 | x = expand_binop (word_mode, binoptab, |
77c9c6c2 | 1955 | op0_piece, op1_piece, |
70864443 | 1956 | target_piece, unsignedp, next_methods); |
77c9c6c2 RK |
1957 | if (x == 0) |
1958 | break; | |
1959 | ||
1960 | if (i + 1 < nwords) | |
1961 | { | |
1962 | /* Store carry from main add/subtract. */ | |
34e56753 | 1963 | carry_out = gen_reg_rtx (word_mode); |
23357404 TG |
1964 | carry_out = emit_store_flag_force (carry_out, |
1965 | (binoptab == add_optab | |
b30f05db | 1966 | ? LT : GT), |
23357404 TG |
1967 | x, op0_piece, |
1968 | word_mode, 1, normalizep); | |
77c9c6c2 RK |
1969 | } |
1970 | ||
1971 | if (i > 0) | |
1972 | { | |
859cb4d8 | 1973 | rtx newx; |
0c20a65f | 1974 | |
77c9c6c2 | 1975 | /* Add/subtract previous carry to main result. */ |
859cb4d8 GK |
1976 | newx = expand_binop (word_mode, |
1977 | normalizep == 1 ? binoptab : otheroptab, | |
1978 | x, carry_in, | |
1979 | NULL_RTX, 1, next_methods); | |
77c9c6c2 RK |
1980 | |
1981 | if (i + 1 < nwords) | |
1982 | { | |
77c9c6c2 | 1983 | /* Get out carry from adding/subtracting carry in. */ |
859cb4d8 | 1984 | rtx carry_tmp = gen_reg_rtx (word_mode); |
23357404 | 1985 | carry_tmp = emit_store_flag_force (carry_tmp, |
859cb4d8 GK |
1986 | (binoptab == add_optab |
1987 | ? LT : GT), | |
1988 | newx, x, | |
23357404 | 1989 | word_mode, 1, normalizep); |
70864443 | 1990 | |
77c9c6c2 | 1991 | /* Logical-ior the two poss. carry together. */ |
34e56753 | 1992 | carry_out = expand_binop (word_mode, ior_optab, |
77c9c6c2 | 1993 | carry_out, carry_tmp, |
70864443 RK |
1994 | carry_out, 0, next_methods); |
1995 | if (carry_out == 0) | |
77c9c6c2 RK |
1996 | break; |
1997 | } | |
859cb4d8 | 1998 | emit_move_insn (target_piece, newx); |
77c9c6c2 | 1999 | } |
06cd9d72 DD |
2000 | else |
2001 | { | |
2002 | if (x != target_piece) | |
2003 | emit_move_insn (target_piece, x); | |
2004 | } | |
77c9c6c2 RK |
2005 | |
2006 | carry_in = carry_out; | |
0c20a65f | 2007 | } |
77c9c6c2 | 2008 | |
e2500fed | 2009 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
77c9c6c2 | 2010 | { |
947131ba | 2011 | if (optab_handler (mov_optab, mode) != CODE_FOR_nothing |
d0ccc658 | 2012 | || ! rtx_equal_p (target, xtarget)) |
02214a5c | 2013 | { |
64de6c0a | 2014 | rtx temp = emit_move_insn (target, xtarget); |
70864443 | 2015 | |
5fa671cf | 2016 | set_unique_reg_note (temp, |
0c20a65f | 2017 | REG_EQUAL, |
5fa671cf AM |
2018 | gen_rtx_fmt_ee (binoptab->code, mode, |
2019 | copy_rtx (xop0), | |
2020 | copy_rtx (xop1))); | |
02214a5c | 2021 | } |
2cd622c3 AO |
2022 | else |
2023 | target = xtarget; | |
c5c76735 | 2024 | |
77c9c6c2 RK |
2025 | return target; |
2026 | } | |
c5c76735 | 2027 | |
77c9c6c2 RK |
2028 | else |
2029 | delete_insns_since (last); | |
2030 | } | |
2031 | ||
f927760b RS |
2032 | /* Attempt to synthesize double word multiplies using a sequence of word |
2033 | mode multiplications. We first attempt to generate a sequence using a | |
2034 | more efficient unsigned widening multiply, and if that fails we then | |
2035 | try using a signed widening multiply. */ | |
77c9c6c2 RK |
2036 | |
2037 | if (binoptab == smul_optab | |
d858f359 | 2038 | && mclass == MODE_INT |
77c9c6c2 | 2039 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
947131ba RS |
2040 | && optab_handler (smul_optab, word_mode) != CODE_FOR_nothing |
2041 | && optab_handler (add_optab, word_mode) != CODE_FOR_nothing) | |
77c9c6c2 | 2042 | { |
f927760b | 2043 | rtx product = NULL_RTX; |
77c9c6c2 | 2044 | |
947131ba | 2045 | if (optab_handler (umul_widen_optab, mode) != CODE_FOR_nothing) |
f927760b RS |
2046 | { |
2047 | product = expand_doubleword_mult (mode, op0, op1, target, | |
2048 | true, methods); | |
2049 | if (!product) | |
77c9c6c2 | 2050 | delete_insns_since (last); |
77c9c6c2 RK |
2051 | } |
2052 | ||
f927760b | 2053 | if (product == NULL_RTX |
947131ba | 2054 | && optab_handler (smul_widen_optab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 2055 | { |
f927760b RS |
2056 | product = expand_doubleword_mult (mode, op0, op1, target, |
2057 | false, methods); | |
2058 | if (!product) | |
2059 | delete_insns_since (last); | |
77c9c6c2 RK |
2060 | } |
2061 | ||
f927760b | 2062 | if (product != NULL_RTX) |
77c9c6c2 | 2063 | { |
947131ba | 2064 | if (optab_handler (mov_optab, mode) != CODE_FOR_nothing) |
70864443 | 2065 | { |
f927760b RS |
2066 | temp = emit_move_insn (target ? target : product, product); |
2067 | set_unique_reg_note (temp, | |
2068 | REG_EQUAL, | |
2069 | gen_rtx_fmt_ee (MULT, mode, | |
2070 | copy_rtx (op0), | |
2071 | copy_rtx (op1))); | |
77c9c6c2 | 2072 | } |
f927760b | 2073 | return product; |
77c9c6c2 | 2074 | } |
77c9c6c2 RK |
2075 | } |
2076 | ||
2077 | /* It can't be open-coded in this mode. | |
2078 | Use a library call if one is available and caller says that's ok. */ | |
2079 | ||
8a33f100 JH |
2080 | libfunc = optab_libfunc (binoptab, mode); |
2081 | if (libfunc | |
77c9c6c2 RK |
2082 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) |
2083 | { | |
2084 | rtx insns; | |
0bbb7f4d RS |
2085 | rtx op1x = op1; |
2086 | enum machine_mode op1_mode = mode; | |
9a7f678c | 2087 | rtx value; |
77c9c6c2 RK |
2088 | |
2089 | start_sequence (); | |
2090 | ||
62442ab9 | 2091 | if (shift_optab_p (binoptab)) |
0bbb7f4d | 2092 | { |
c7ff6e7a | 2093 | op1_mode = targetm.libgcc_shift_count_mode (); |
0bbb7f4d RS |
2094 | /* Specify unsigned here, |
2095 | since negative shift counts are meaningless. */ | |
c7ff6e7a | 2096 | op1x = convert_to_mode (op1_mode, op1, 1); |
0bbb7f4d RS |
2097 | } |
2098 | ||
82f0e2cc RK |
2099 | if (GET_MODE (op0) != VOIDmode |
2100 | && GET_MODE (op0) != mode) | |
5035bbfe TG |
2101 | op0 = convert_to_mode (mode, op0, unsignedp); |
2102 | ||
77c9c6c2 RK |
2103 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
2104 | if the libcall is cse'd or moved. */ | |
8a33f100 | 2105 | value = emit_library_call_value (libfunc, |
ebb1b59a | 2106 | NULL_RTX, LCT_CONST, mode, 2, |
9a7f678c | 2107 | op0, mode, op1x, op1_mode); |
77c9c6c2 RK |
2108 | |
2109 | insns = get_insns (); | |
2110 | end_sequence (); | |
2111 | ||
2112 | target = gen_reg_rtx (mode); | |
9a7f678c | 2113 | emit_libcall_block (insns, target, value, |
9e6a5703 | 2114 | gen_rtx_fmt_ee (binoptab->code, mode, op0, op1)); |
77c9c6c2 RK |
2115 | |
2116 | return target; | |
2117 | } | |
2118 | ||
2119 | delete_insns_since (last); | |
2120 | ||
2121 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2122 | ||
2123 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
2124 | || methods == OPTAB_MUST_WIDEN)) | |
abd418d3 RS |
2125 | { |
2126 | /* Caller says, don't even try. */ | |
2127 | delete_insns_since (entry_last); | |
2128 | return 0; | |
2129 | } | |
77c9c6c2 RK |
2130 | |
2131 | /* Compute the value of METHODS to pass to recursive calls. | |
2132 | Don't allow widening to be tried recursively. */ | |
2133 | ||
2134 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
2135 | ||
34e56753 RS |
2136 | /* Look for a wider mode of the same class for which it appears we can do |
2137 | the operation. */ | |
77c9c6c2 | 2138 | |
d858f359 | 2139 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 2140 | { |
86556d87 BE |
2141 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2142 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
2143 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2144 | { | |
947131ba | 2145 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing |
77c9c6c2 | 2146 | || (methods == OPTAB_LIB |
8a33f100 | 2147 | && optab_libfunc (binoptab, wider_mode))) |
77c9c6c2 RK |
2148 | { |
2149 | rtx xop0 = op0, xop1 = op1; | |
2150 | int no_extend = 0; | |
2151 | ||
34e56753 | 2152 | /* For certain integer operations, we need not actually extend |
77c9c6c2 | 2153 | the narrow operands, as long as we will truncate |
835532b8 | 2154 | the results to the same narrowness. */ |
77c9c6c2 | 2155 | |
34e56753 RS |
2156 | if ((binoptab == ior_optab || binoptab == and_optab |
2157 | || binoptab == xor_optab | |
2158 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 2159 | || binoptab == smul_optab || binoptab == ashl_optab) |
d858f359 | 2160 | && mclass == MODE_INT) |
77c9c6c2 RK |
2161 | no_extend = 1; |
2162 | ||
0661a3de RS |
2163 | xop0 = widen_operand (xop0, wider_mode, mode, |
2164 | unsignedp, no_extend); | |
943cc242 RK |
2165 | |
2166 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 2167 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 2168 | no_extend && binoptab != ashl_optab); |
77c9c6c2 | 2169 | |
b1ec3c92 | 2170 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
77c9c6c2 RK |
2171 | unsignedp, methods); |
2172 | if (temp) | |
2173 | { | |
d858f359 | 2174 | if (mclass != MODE_INT |
28f52a4d R |
2175 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
2176 | GET_MODE_BITSIZE (wider_mode))) | |
77c9c6c2 RK |
2177 | { |
2178 | if (target == 0) | |
2179 | target = gen_reg_rtx (mode); | |
2180 | convert_move (target, temp, 0); | |
2181 | return target; | |
2182 | } | |
2183 | else | |
2184 | return gen_lowpart (mode, temp); | |
2185 | } | |
2186 | else | |
2187 | delete_insns_since (last); | |
2188 | } | |
2189 | } | |
2190 | } | |
2191 | ||
abd418d3 | 2192 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2193 | return 0; |
2194 | } | |
2195 | \f | |
2196 | /* Expand a binary operator which has both signed and unsigned forms. | |
2197 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2198 | signed operations. | |
2199 | ||
2200 | If we widen unsigned operands, we may use a signed wider operation instead | |
2201 | of an unsigned wider operation, since the result would be the same. */ | |
2202 | ||
2203 | rtx | |
0c20a65f AJ |
2204 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2205 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2206 | enum optab_methods methods) | |
77c9c6c2 | 2207 | { |
b3694847 | 2208 | rtx temp; |
77c9c6c2 | 2209 | optab direct_optab = unsignedp ? uoptab : soptab; |
7e5487a2 | 2210 | struct optab_d wide_soptab; |
77c9c6c2 RK |
2211 | |
2212 | /* Do it without widening, if possible. */ | |
2213 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2214 | unsignedp, OPTAB_DIRECT); | |
2215 | if (temp || methods == OPTAB_DIRECT) | |
2216 | return temp; | |
2217 | ||
2218 | /* Try widening to a signed int. Make a fake signed optab that | |
2219 | hides any signed insn for direct use. */ | |
2220 | wide_soptab = *soptab; | |
947131ba | 2221 | set_optab_handler (&wide_soptab, mode, CODE_FOR_nothing); |
ae2bd7d2 AH |
2222 | /* We don't want to generate new hash table entries from this fake |
2223 | optab. */ | |
2224 | wide_soptab.libcall_gen = NULL; | |
77c9c6c2 RK |
2225 | |
2226 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2227 | unsignedp, OPTAB_WIDEN); | |
2228 | ||
2229 | /* For unsigned operands, try widening to an unsigned int. */ | |
2230 | if (temp == 0 && unsignedp) | |
2231 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
2232 | unsignedp, OPTAB_WIDEN); | |
2233 | if (temp || methods == OPTAB_WIDEN) | |
2234 | return temp; | |
2235 | ||
f90b7a5a | 2236 | /* Use the right width libcall if that exists. */ |
77c9c6c2 RK |
2237 | temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); |
2238 | if (temp || methods == OPTAB_LIB) | |
2239 | return temp; | |
2240 | ||
f90b7a5a | 2241 | /* Must widen and use a libcall, use either signed or unsigned. */ |
77c9c6c2 RK |
2242 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, |
2243 | unsignedp, methods); | |
2244 | if (temp != 0) | |
2245 | return temp; | |
2246 | if (unsignedp) | |
2247 | return expand_binop (mode, uoptab, op0, op1, target, | |
2248 | unsignedp, methods); | |
2249 | return 0; | |
2250 | } | |
2251 | \f | |
6c7cf1f0 UB |
2252 | /* Generate code to perform an operation specified by UNOPPTAB |
2253 | on operand OP0, with two results to TARG0 and TARG1. | |
2254 | We assume that the order of the operands for the instruction | |
2255 | is TARG0, TARG1, OP0. | |
2256 | ||
2257 | Either TARG0 or TARG1 may be zero, but what that means is that | |
2258 | the result is not actually wanted. We will generate it into | |
2259 | a dummy pseudo-reg and discard it. They may not both be zero. | |
2260 | ||
2261 | Returns 1 if this operation can be performed; 0 if not. */ | |
2262 | ||
2263 | int | |
a072d43b | 2264 | expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1, |
6c7cf1f0 UB |
2265 | int unsignedp) |
2266 | { | |
2267 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
d858f359 | 2268 | enum mode_class mclass; |
6c7cf1f0 UB |
2269 | enum machine_mode wider_mode; |
2270 | rtx entry_last = get_last_insn (); | |
2271 | rtx last; | |
2272 | ||
d858f359 | 2273 | mclass = GET_MODE_CLASS (mode); |
6c7cf1f0 | 2274 | |
ad76cef8 | 2275 | if (!targ0) |
6c7cf1f0 | 2276 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2277 | if (!targ1) |
6c7cf1f0 UB |
2278 | targ1 = gen_reg_rtx (mode); |
2279 | ||
2280 | /* Record where to go back to if we fail. */ | |
2281 | last = get_last_insn (); | |
2282 | ||
947131ba | 2283 | if (optab_handler (unoptab, mode) != CODE_FOR_nothing) |
6c7cf1f0 | 2284 | { |
947131ba | 2285 | int icode = (int) optab_handler (unoptab, mode); |
6c7cf1f0 UB |
2286 | enum machine_mode mode0 = insn_data[icode].operand[2].mode; |
2287 | rtx pat; | |
2288 | rtx xop0 = op0; | |
2289 | ||
2290 | if (GET_MODE (xop0) != VOIDmode | |
2291 | && GET_MODE (xop0) != mode0) | |
2292 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2293 | ||
2294 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
e3feb571 | 2295 | if (!insn_data[icode].operand[2].predicate (xop0, mode0)) |
6c7cf1f0 UB |
2296 | xop0 = copy_to_mode_reg (mode0, xop0); |
2297 | ||
2298 | /* We could handle this, but we should always be called with a pseudo | |
2299 | for our targets and all insns should take them as outputs. */ | |
e3feb571 NS |
2300 | gcc_assert (insn_data[icode].operand[0].predicate (targ0, mode)); |
2301 | gcc_assert (insn_data[icode].operand[1].predicate (targ1, mode)); | |
6c7cf1f0 UB |
2302 | |
2303 | pat = GEN_FCN (icode) (targ0, targ1, xop0); | |
2304 | if (pat) | |
2305 | { | |
2306 | emit_insn (pat); | |
2307 | return 1; | |
2308 | } | |
2309 | else | |
2310 | delete_insns_since (last); | |
2311 | } | |
2312 | ||
2313 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2314 | ||
d858f359 | 2315 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
6c7cf1f0 | 2316 | { |
86556d87 BE |
2317 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2318 | wider_mode != VOIDmode; | |
6c7cf1f0 UB |
2319 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2320 | { | |
947131ba | 2321 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
6c7cf1f0 UB |
2322 | { |
2323 | rtx t0 = gen_reg_rtx (wider_mode); | |
2324 | rtx t1 = gen_reg_rtx (wider_mode); | |
2325 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); | |
2326 | ||
a072d43b | 2327 | if (expand_twoval_unop (unoptab, cop0, t0, t1, unsignedp)) |
6c7cf1f0 UB |
2328 | { |
2329 | convert_move (targ0, t0, unsignedp); | |
2330 | convert_move (targ1, t1, unsignedp); | |
2331 | return 1; | |
2332 | } | |
2333 | else | |
2334 | delete_insns_since (last); | |
2335 | } | |
2336 | } | |
2337 | } | |
2338 | ||
2339 | delete_insns_since (entry_last); | |
2340 | return 0; | |
2341 | } | |
2342 | \f | |
77c9c6c2 RK |
2343 | /* Generate code to perform an operation specified by BINOPTAB |
2344 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2345 | We assume that the order of the operands for the instruction | |
2346 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2347 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2348 | ||
2349 | Either TARG0 or TARG1 may be zero, but what that means is that | |
38e01259 | 2350 | the result is not actually wanted. We will generate it into |
77c9c6c2 RK |
2351 | a dummy pseudo-reg and discard it. They may not both be zero. |
2352 | ||
2353 | Returns 1 if this operation can be performed; 0 if not. */ | |
2354 | ||
2355 | int | |
0c20a65f AJ |
2356 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2357 | int unsignedp) | |
77c9c6c2 RK |
2358 | { |
2359 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
d858f359 | 2360 | enum mode_class mclass; |
77c9c6c2 | 2361 | enum machine_mode wider_mode; |
abd418d3 | 2362 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
2363 | rtx last; |
2364 | ||
d858f359 | 2365 | mclass = GET_MODE_CLASS (mode); |
77c9c6c2 | 2366 | |
ad76cef8 | 2367 | if (!targ0) |
77c9c6c2 | 2368 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2369 | if (!targ1) |
77c9c6c2 RK |
2370 | targ1 = gen_reg_rtx (mode); |
2371 | ||
2372 | /* Record where to go back to if we fail. */ | |
2373 | last = get_last_insn (); | |
2374 | ||
947131ba | 2375 | if (optab_handler (binoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 2376 | { |
947131ba | 2377 | int icode = (int) optab_handler (binoptab, mode); |
a995e389 RH |
2378 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2379 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
2380 | rtx pat; |
2381 | rtx xop0 = op0, xop1 = op1; | |
2382 | ||
62442ab9 RS |
2383 | /* If we are optimizing, force expensive constants into a register. */ |
2384 | xop0 = avoid_expensive_constant (mode0, binoptab, xop0, unsignedp); | |
2385 | xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp); | |
2386 | ||
874f6a6d EB |
2387 | /* In case the insn wants input operands in modes different from |
2388 | those of the actual operands, convert the operands. It would | |
2389 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
2390 | that they're properly zero-extended, sign-extended or truncated |
2391 | for their mode. */ | |
77c9c6c2 | 2392 | |
874f6a6d EB |
2393 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
2394 | xop0 = convert_modes (mode0, | |
2395 | GET_MODE (op0) != VOIDmode | |
2396 | ? GET_MODE (op0) | |
2397 | : mode, | |
2398 | xop0, unsignedp); | |
2399 | ||
2400 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
2401 | xop1 = convert_modes (mode1, | |
2402 | GET_MODE (op1) != VOIDmode | |
2403 | ? GET_MODE (op1) | |
2404 | : mode, | |
2405 | xop1, unsignedp); | |
77c9c6c2 RK |
2406 | |
2407 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
e3feb571 | 2408 | if (!insn_data[icode].operand[1].predicate (xop0, mode0)) |
77c9c6c2 RK |
2409 | xop0 = copy_to_mode_reg (mode0, xop0); |
2410 | ||
e3feb571 | 2411 | if (!insn_data[icode].operand[2].predicate (xop1, mode1)) |
77c9c6c2 RK |
2412 | xop1 = copy_to_mode_reg (mode1, xop1); |
2413 | ||
2414 | /* We could handle this, but we should always be called with a pseudo | |
2415 | for our targets and all insns should take them as outputs. */ | |
e3feb571 NS |
2416 | gcc_assert (insn_data[icode].operand[0].predicate (targ0, mode)); |
2417 | gcc_assert (insn_data[icode].operand[3].predicate (targ1, mode)); | |
0c20a65f | 2418 | |
77c9c6c2 RK |
2419 | pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1); |
2420 | if (pat) | |
2421 | { | |
2422 | emit_insn (pat); | |
2423 | return 1; | |
2424 | } | |
2425 | else | |
2426 | delete_insns_since (last); | |
2427 | } | |
2428 | ||
2429 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2430 | ||
d858f359 | 2431 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 2432 | { |
86556d87 BE |
2433 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2434 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
2435 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2436 | { | |
947131ba | 2437 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing) |
77c9c6c2 | 2438 | { |
b3694847 SS |
2439 | rtx t0 = gen_reg_rtx (wider_mode); |
2440 | rtx t1 = gen_reg_rtx (wider_mode); | |
76791f3d JH |
2441 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2442 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
77c9c6c2 | 2443 | |
76791f3d | 2444 | if (expand_twoval_binop (binoptab, cop0, cop1, |
77c9c6c2 RK |
2445 | t0, t1, unsignedp)) |
2446 | { | |
2447 | convert_move (targ0, t0, unsignedp); | |
2448 | convert_move (targ1, t1, unsignedp); | |
2449 | return 1; | |
2450 | } | |
2451 | else | |
2452 | delete_insns_since (last); | |
2453 | } | |
2454 | } | |
2455 | } | |
2456 | ||
abd418d3 | 2457 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2458 | return 0; |
2459 | } | |
b3f8d95d MM |
2460 | |
2461 | /* Expand the two-valued library call indicated by BINOPTAB, but | |
2462 | preserve only one of the values. If TARG0 is non-NULL, the first | |
2463 | value is placed into TARG0; otherwise the second value is placed | |
2464 | into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The | |
2465 | value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1). | |
2466 | This routine assumes that the value returned by the library call is | |
2467 | as if the return value was of an integral mode twice as wide as the | |
2468 | mode of OP0. Returns 1 if the call was successful. */ | |
2469 | ||
2470 | bool | |
5906d013 | 2471 | expand_twoval_binop_libfunc (optab binoptab, rtx op0, rtx op1, |
b3f8d95d MM |
2472 | rtx targ0, rtx targ1, enum rtx_code code) |
2473 | { | |
2474 | enum machine_mode mode; | |
2475 | enum machine_mode libval_mode; | |
2476 | rtx libval; | |
2477 | rtx insns; | |
8a33f100 | 2478 | rtx libfunc; |
5906d013 | 2479 | |
b3f8d95d | 2480 | /* Exactly one of TARG0 or TARG1 should be non-NULL. */ |
e3feb571 | 2481 | gcc_assert (!targ0 != !targ1); |
b3f8d95d MM |
2482 | |
2483 | mode = GET_MODE (op0); | |
8a33f100 JH |
2484 | libfunc = optab_libfunc (binoptab, mode); |
2485 | if (!libfunc) | |
b3f8d95d MM |
2486 | return false; |
2487 | ||
2488 | /* The value returned by the library function will have twice as | |
2489 | many bits as the nominal MODE. */ | |
5906d013 | 2490 | libval_mode = smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode), |
b3f8d95d MM |
2491 | MODE_INT); |
2492 | start_sequence (); | |
8a33f100 | 2493 | libval = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
b3f8d95d | 2494 | libval_mode, 2, |
5906d013 | 2495 | op0, mode, |
b3f8d95d MM |
2496 | op1, mode); |
2497 | /* Get the part of VAL containing the value that we want. */ | |
2498 | libval = simplify_gen_subreg (mode, libval, libval_mode, | |
2499 | targ0 ? 0 : GET_MODE_SIZE (mode)); | |
2500 | insns = get_insns (); | |
2501 | end_sequence (); | |
2502 | /* Move the into the desired location. */ | |
5906d013 | 2503 | emit_libcall_block (insns, targ0 ? targ0 : targ1, libval, |
b3f8d95d | 2504 | gen_rtx_fmt_ee (code, mode, op0, op1)); |
5906d013 | 2505 | |
b3f8d95d MM |
2506 | return true; |
2507 | } | |
2508 | ||
77c9c6c2 | 2509 | \f |
ef89d648 ZW |
2510 | /* Wrapper around expand_unop which takes an rtx code to specify |
2511 | the operation to perform, not an optab pointer. All other | |
2512 | arguments are the same. */ | |
2513 | rtx | |
0c20a65f AJ |
2514 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2515 | rtx target, int unsignedp) | |
ef89d648 | 2516 | { |
7e1a450d | 2517 | optab unop = code_to_optab[(int) code]; |
e3feb571 | 2518 | gcc_assert (unop); |
ef89d648 ZW |
2519 | |
2520 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2521 | } | |
2522 | ||
2928cd7a RH |
2523 | /* Try calculating |
2524 | (clz:narrow x) | |
2525 | as | |
2526 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */ | |
2527 | static rtx | |
0c20a65f | 2528 | widen_clz (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a | 2529 | { |
d858f359 KG |
2530 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2531 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
2928cd7a RH |
2532 | { |
2533 | enum machine_mode wider_mode; | |
86556d87 BE |
2534 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2535 | wider_mode != VOIDmode; | |
2928cd7a RH |
2536 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2537 | { | |
947131ba | 2538 | if (optab_handler (clz_optab, wider_mode) != CODE_FOR_nothing) |
2928cd7a RH |
2539 | { |
2540 | rtx xop0, temp, last; | |
2541 | ||
2542 | last = get_last_insn (); | |
2543 | ||
2544 | if (target == 0) | |
2545 | target = gen_reg_rtx (mode); | |
2546 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2547 | temp = expand_unop (wider_mode, clz_optab, xop0, NULL_RTX, true); | |
2548 | if (temp != 0) | |
2549 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2550 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2551 | - GET_MODE_BITSIZE (mode)), | |
2552 | target, true, OPTAB_DIRECT); | |
2553 | if (temp == 0) | |
2554 | delete_insns_since (last); | |
2555 | ||
2556 | return temp; | |
2557 | } | |
2558 | } | |
2559 | } | |
2560 | return 0; | |
2561 | } | |
2562 | ||
9cce5b20 ZW |
2563 | /* Try calculating clz of a double-word quantity as two clz's of word-sized |
2564 | quantities, choosing which based on whether the high word is nonzero. */ | |
2565 | static rtx | |
2566 | expand_doubleword_clz (enum machine_mode mode, rtx op0, rtx target) | |
2567 | { | |
2568 | rtx xop0 = force_reg (mode, op0); | |
2569 | rtx subhi = gen_highpart (word_mode, xop0); | |
2570 | rtx sublo = gen_lowpart (word_mode, xop0); | |
2571 | rtx hi0_label = gen_label_rtx (); | |
2572 | rtx after_label = gen_label_rtx (); | |
2573 | rtx seq, temp, result; | |
2574 | ||
2575 | /* If we were not given a target, use a word_mode register, not a | |
2576 | 'mode' register. The result will fit, and nobody is expecting | |
2577 | anything bigger (the return type of __builtin_clz* is int). */ | |
2578 | if (!target) | |
2579 | target = gen_reg_rtx (word_mode); | |
2580 | ||
2581 | /* In any case, write to a word_mode scratch in both branches of the | |
2582 | conditional, so we can ensure there is a single move insn setting | |
2583 | 'target' to tag a REG_EQUAL note on. */ | |
2584 | result = gen_reg_rtx (word_mode); | |
2585 | ||
2586 | start_sequence (); | |
2587 | ||
2588 | /* If the high word is not equal to zero, | |
2589 | then clz of the full value is clz of the high word. */ | |
2590 | emit_cmp_and_jump_insns (subhi, CONST0_RTX (word_mode), EQ, 0, | |
2591 | word_mode, true, hi0_label); | |
2592 | ||
2593 | temp = expand_unop_direct (word_mode, clz_optab, subhi, result, true); | |
2594 | if (!temp) | |
2595 | goto fail; | |
2596 | ||
2597 | if (temp != result) | |
2598 | convert_move (result, temp, true); | |
2599 | ||
2600 | emit_jump_insn (gen_jump (after_label)); | |
2601 | emit_barrier (); | |
2602 | ||
2603 | /* Else clz of the full value is clz of the low word plus the number | |
2604 | of bits in the high word. */ | |
2605 | emit_label (hi0_label); | |
2606 | ||
2607 | temp = expand_unop_direct (word_mode, clz_optab, sublo, 0, true); | |
2608 | if (!temp) | |
2609 | goto fail; | |
2610 | temp = expand_binop (word_mode, add_optab, temp, | |
2611 | GEN_INT (GET_MODE_BITSIZE (word_mode)), | |
2612 | result, true, OPTAB_DIRECT); | |
2613 | if (!temp) | |
2614 | goto fail; | |
2615 | if (temp != result) | |
2616 | convert_move (result, temp, true); | |
2617 | ||
2618 | emit_label (after_label); | |
2619 | convert_move (target, result, true); | |
2620 | ||
2621 | seq = get_insns (); | |
2622 | end_sequence (); | |
2623 | ||
2624 | add_equal_note (seq, target, CLZ, xop0, 0); | |
2625 | emit_insn (seq); | |
2626 | return target; | |
2627 | ||
2628 | fail: | |
2629 | end_sequence (); | |
2630 | return 0; | |
2631 | } | |
2632 | ||
2e6834d3 RH |
2633 | /* Try calculating |
2634 | (bswap:narrow x) | |
2635 | as | |
2636 | (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */ | |
2637 | static rtx | |
2638 | widen_bswap (enum machine_mode mode, rtx op0, rtx target) | |
2639 | { | |
d858f359 | 2640 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2e6834d3 RH |
2641 | enum machine_mode wider_mode; |
2642 | rtx x, last; | |
2643 | ||
d858f359 | 2644 | if (!CLASS_HAS_WIDER_MODES_P (mclass)) |
2e6834d3 RH |
2645 | return NULL_RTX; |
2646 | ||
2647 | for (wider_mode = GET_MODE_WIDER_MODE (mode); | |
2648 | wider_mode != VOIDmode; | |
2649 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
947131ba | 2650 | if (optab_handler (bswap_optab, wider_mode) != CODE_FOR_nothing) |
2e6834d3 RH |
2651 | goto found; |
2652 | return NULL_RTX; | |
2653 | ||
2654 | found: | |
2655 | last = get_last_insn (); | |
2656 | ||
2657 | x = widen_operand (op0, wider_mode, mode, true, true); | |
2658 | x = expand_unop (wider_mode, bswap_optab, x, NULL_RTX, true); | |
2659 | ||
2660 | if (x != 0) | |
2661 | x = expand_shift (RSHIFT_EXPR, wider_mode, x, | |
2662 | size_int (GET_MODE_BITSIZE (wider_mode) | |
2663 | - GET_MODE_BITSIZE (mode)), | |
2664 | NULL_RTX, true); | |
2665 | ||
2666 | if (x != 0) | |
2667 | { | |
2668 | if (target == 0) | |
2669 | target = gen_reg_rtx (mode); | |
2670 | emit_move_insn (target, gen_lowpart (mode, x)); | |
2671 | } | |
2672 | else | |
2673 | delete_insns_since (last); | |
2674 | ||
2675 | return target; | |
2676 | } | |
2677 | ||
2678 | /* Try calculating bswap as two bswaps of two word-sized operands. */ | |
2679 | ||
2680 | static rtx | |
2681 | expand_doubleword_bswap (enum machine_mode mode, rtx op, rtx target) | |
2682 | { | |
2683 | rtx t0, t1; | |
2684 | ||
2685 | t1 = expand_unop (word_mode, bswap_optab, | |
2686 | operand_subword_force (op, 0, mode), NULL_RTX, true); | |
2687 | t0 = expand_unop (word_mode, bswap_optab, | |
2688 | operand_subword_force (op, 1, mode), NULL_RTX, true); | |
2689 | ||
2690 | if (target == 0) | |
2691 | target = gen_reg_rtx (mode); | |
2692 | if (REG_P (target)) | |
c41c1387 | 2693 | emit_clobber (target); |
2e6834d3 RH |
2694 | emit_move_insn (operand_subword (target, 0, 1, mode), t0); |
2695 | emit_move_insn (operand_subword (target, 1, 1, mode), t1); | |
2696 | ||
2697 | return target; | |
2698 | } | |
2699 | ||
2928cd7a RH |
2700 | /* Try calculating (parity x) as (and (popcount x) 1), where |
2701 | popcount can also be done in a wider mode. */ | |
2702 | static rtx | |
0c20a65f | 2703 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a | 2704 | { |
d858f359 KG |
2705 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2706 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
2928cd7a RH |
2707 | { |
2708 | enum machine_mode wider_mode; | |
2709 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2710 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2711 | { | |
947131ba | 2712 | if (optab_handler (popcount_optab, wider_mode) != CODE_FOR_nothing) |
2928cd7a RH |
2713 | { |
2714 | rtx xop0, temp, last; | |
2715 | ||
2716 | last = get_last_insn (); | |
2717 | ||
2718 | if (target == 0) | |
2719 | target = gen_reg_rtx (mode); | |
2720 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2721 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2722 | true); | |
2723 | if (temp != 0) | |
60c81c89 | 2724 | temp = expand_binop (wider_mode, and_optab, temp, const1_rtx, |
2928cd7a RH |
2725 | target, true, OPTAB_DIRECT); |
2726 | if (temp == 0) | |
2727 | delete_insns_since (last); | |
2728 | ||
2729 | return temp; | |
2730 | } | |
2731 | } | |
2732 | } | |
2733 | return 0; | |
2734 | } | |
2735 | ||
9cce5b20 ZW |
2736 | /* Try calculating ctz(x) as K - clz(x & -x) , |
2737 | where K is GET_MODE_BITSIZE(mode) - 1. | |
2738 | ||
2739 | Both __builtin_ctz and __builtin_clz are undefined at zero, so we | |
2740 | don't have to worry about what the hardware does in that case. (If | |
2741 | the clz instruction produces the usual value at 0, which is K, the | |
2742 | result of this code sequence will be -1; expand_ffs, below, relies | |
2743 | on this. It might be nice to have it be K instead, for consistency | |
2744 | with the (very few) processors that provide a ctz with a defined | |
2745 | value, but that would take one more instruction, and it would be | |
2746 | less convenient for expand_ffs anyway. */ | |
2747 | ||
14670a74 | 2748 | static rtx |
9cce5b20 | 2749 | expand_ctz (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2750 | { |
9cce5b20 | 2751 | rtx seq, temp; |
b8698a0f | 2752 | |
947131ba | 2753 | if (optab_handler (clz_optab, mode) == CODE_FOR_nothing) |
9cce5b20 | 2754 | return 0; |
b8698a0f | 2755 | |
9cce5b20 | 2756 | start_sequence (); |
14670a74 | 2757 | |
9cce5b20 ZW |
2758 | temp = expand_unop_direct (mode, neg_optab, op0, NULL_RTX, true); |
2759 | if (temp) | |
2760 | temp = expand_binop (mode, and_optab, op0, temp, NULL_RTX, | |
2761 | true, OPTAB_DIRECT); | |
2762 | if (temp) | |
2763 | temp = expand_unop_direct (mode, clz_optab, temp, NULL_RTX, true); | |
2764 | if (temp) | |
2765 | temp = expand_binop (mode, sub_optab, GEN_INT (GET_MODE_BITSIZE (mode) - 1), | |
2766 | temp, target, | |
2767 | true, OPTAB_DIRECT); | |
2768 | if (temp == 0) | |
2769 | { | |
2770 | end_sequence (); | |
2771 | return 0; | |
14670a74 | 2772 | } |
9cce5b20 ZW |
2773 | |
2774 | seq = get_insns (); | |
2775 | end_sequence (); | |
2776 | ||
2777 | add_equal_note (seq, temp, CTZ, op0, 0); | |
2778 | emit_insn (seq); | |
2779 | return temp; | |
14670a74 SL |
2780 | } |
2781 | ||
9cce5b20 ZW |
2782 | |
2783 | /* Try calculating ffs(x) using ctz(x) if we have that instruction, or | |
2784 | else with the sequence used by expand_clz. | |
b8698a0f | 2785 | |
9cce5b20 ZW |
2786 | The ffs builtin promises to return zero for a zero value and ctz/clz |
2787 | may have an undefined value in that case. If they do not give us a | |
2788 | convenient value, we have to generate a test and branch. */ | |
14670a74 | 2789 | static rtx |
9cce5b20 | 2790 | expand_ffs (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2791 | { |
a3324f26 ZW |
2792 | HOST_WIDE_INT val = 0; |
2793 | bool defined_at_zero = false; | |
9cce5b20 ZW |
2794 | rtx temp, seq; |
2795 | ||
947131ba | 2796 | if (optab_handler (ctz_optab, mode) != CODE_FOR_nothing) |
14670a74 | 2797 | { |
9cce5b20 | 2798 | start_sequence (); |
14670a74 | 2799 | |
9cce5b20 ZW |
2800 | temp = expand_unop_direct (mode, ctz_optab, op0, 0, true); |
2801 | if (!temp) | |
2802 | goto fail; | |
2803 | ||
2804 | defined_at_zero = (CTZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2); | |
14670a74 | 2805 | } |
947131ba | 2806 | else if (optab_handler (clz_optab, mode) != CODE_FOR_nothing) |
9cce5b20 ZW |
2807 | { |
2808 | start_sequence (); | |
2809 | temp = expand_ctz (mode, op0, 0); | |
2810 | if (!temp) | |
2811 | goto fail; | |
2812 | ||
2813 | if (CLZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2) | |
2814 | { | |
2815 | defined_at_zero = true; | |
2816 | val = (GET_MODE_BITSIZE (mode) - 1) - val; | |
2817 | } | |
2818 | } | |
2819 | else | |
2820 | return 0; | |
2821 | ||
2822 | if (defined_at_zero && val == -1) | |
2823 | /* No correction needed at zero. */; | |
b8698a0f | 2824 | else |
9cce5b20 ZW |
2825 | { |
2826 | /* We don't try to do anything clever with the situation found | |
2827 | on some processors (eg Alpha) where ctz(0:mode) == | |
2828 | bitsize(mode). If someone can think of a way to send N to -1 | |
2829 | and leave alone all values in the range 0..N-1 (where N is a | |
2830 | power of two), cheaper than this test-and-branch, please add it. | |
2831 | ||
2832 | The test-and-branch is done after the operation itself, in case | |
2833 | the operation sets condition codes that can be recycled for this. | |
2834 | (This is true on i386, for instance.) */ | |
2835 | ||
2836 | rtx nonzero_label = gen_label_rtx (); | |
2837 | emit_cmp_and_jump_insns (op0, CONST0_RTX (mode), NE, 0, | |
2838 | mode, true, nonzero_label); | |
2839 | ||
2840 | convert_move (temp, GEN_INT (-1), false); | |
2841 | emit_label (nonzero_label); | |
2842 | } | |
2843 | ||
2844 | /* temp now has a value in the range -1..bitsize-1. ffs is supposed | |
2845 | to produce a value in the range 0..bitsize. */ | |
2846 | temp = expand_binop (mode, add_optab, temp, GEN_INT (1), | |
2847 | target, false, OPTAB_DIRECT); | |
2848 | if (!temp) | |
2849 | goto fail; | |
2850 | ||
2851 | seq = get_insns (); | |
2852 | end_sequence (); | |
2853 | ||
2854 | add_equal_note (seq, temp, FFS, op0, 0); | |
2855 | emit_insn (seq); | |
2856 | return temp; | |
2857 | ||
2858 | fail: | |
2859 | end_sequence (); | |
14670a74 SL |
2860 | return 0; |
2861 | } | |
2862 | ||
c414ac1d | 2863 | /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain |
6b132673 RH |
2864 | conditions, VAL may already be a SUBREG against which we cannot generate |
2865 | a further SUBREG. In this case, we expect forcing the value into a | |
2866 | register will work around the situation. */ | |
2867 | ||
2868 | static rtx | |
2869 | lowpart_subreg_maybe_copy (enum machine_mode omode, rtx val, | |
2870 | enum machine_mode imode) | |
2871 | { | |
2872 | rtx ret; | |
2873 | ret = lowpart_subreg (omode, val, imode); | |
2874 | if (ret == NULL) | |
2875 | { | |
2876 | val = force_reg (imode, val); | |
2877 | ret = lowpart_subreg (omode, val, imode); | |
2878 | gcc_assert (ret != NULL); | |
2879 | } | |
2880 | return ret; | |
2881 | } | |
2882 | ||
8c55a142 RH |
2883 | /* Expand a floating point absolute value or negation operation via a |
2884 | logical operation on the sign bit. */ | |
2885 | ||
2886 | static rtx | |
2887 | expand_absneg_bit (enum rtx_code code, enum machine_mode mode, | |
2888 | rtx op0, rtx target) | |
2889 | { | |
2890 | const struct real_format *fmt; | |
2891 | int bitpos, word, nwords, i; | |
2892 | enum machine_mode imode; | |
54fb1ae0 | 2893 | double_int mask; |
8c55a142 RH |
2894 | rtx temp, insns; |
2895 | ||
2896 | /* The format has to have a simple sign bit. */ | |
2897 | fmt = REAL_MODE_FORMAT (mode); | |
2898 | if (fmt == NULL) | |
2899 | return NULL_RTX; | |
2900 | ||
b87a0206 | 2901 | bitpos = fmt->signbit_rw; |
8c55a142 RH |
2902 | if (bitpos < 0) |
2903 | return NULL_RTX; | |
2904 | ||
2905 | /* Don't create negative zeros if the format doesn't support them. */ | |
2906 | if (code == NEG && !fmt->has_signed_zero) | |
2907 | return NULL_RTX; | |
2908 | ||
2909 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
2910 | { | |
2911 | imode = int_mode_for_mode (mode); | |
2912 | if (imode == BLKmode) | |
2913 | return NULL_RTX; | |
2914 | word = 0; | |
2915 | nwords = 1; | |
2916 | } | |
2917 | else | |
2918 | { | |
2919 | imode = word_mode; | |
2920 | ||
2921 | if (FLOAT_WORDS_BIG_ENDIAN) | |
2922 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
2923 | else | |
2924 | word = bitpos / BITS_PER_WORD; | |
2925 | bitpos = bitpos % BITS_PER_WORD; | |
2926 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
2927 | } | |
2928 | ||
54fb1ae0 | 2929 | mask = double_int_setbit (double_int_zero, bitpos); |
8c55a142 | 2930 | if (code == ABS) |
54fb1ae0 | 2931 | mask = double_int_not (mask); |
8c55a142 RH |
2932 | |
2933 | if (target == 0 || target == op0) | |
2934 | target = gen_reg_rtx (mode); | |
2935 | ||
2936 | if (nwords > 1) | |
2937 | { | |
2938 | start_sequence (); | |
2939 | ||
2940 | for (i = 0; i < nwords; ++i) | |
2941 | { | |
2942 | rtx targ_piece = operand_subword (target, i, 1, mode); | |
2943 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 2944 | |
8c55a142 RH |
2945 | if (i == word) |
2946 | { | |
2947 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
2948 | op0_piece, | |
54fb1ae0 | 2949 | immed_double_int_const (mask, imode), |
8c55a142 RH |
2950 | targ_piece, 1, OPTAB_LIB_WIDEN); |
2951 | if (temp != targ_piece) | |
2952 | emit_move_insn (targ_piece, temp); | |
2953 | } | |
2954 | else | |
2955 | emit_move_insn (targ_piece, op0_piece); | |
2956 | } | |
2957 | ||
2958 | insns = get_insns (); | |
2959 | end_sequence (); | |
2960 | ||
d70dcf29 | 2961 | emit_insn (insns); |
8c55a142 RH |
2962 | } |
2963 | else | |
2964 | { | |
2965 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
2966 | gen_lowpart (imode, op0), | |
54fb1ae0 | 2967 | immed_double_int_const (mask, imode), |
8c55a142 RH |
2968 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); |
2969 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
2970 | ||
2971 | set_unique_reg_note (get_last_insn (), REG_EQUAL, | |
2972 | gen_rtx_fmt_e (code, mode, copy_rtx (op0))); | |
2973 | } | |
2974 | ||
2975 | return target; | |
2976 | } | |
2977 | ||
9cce5b20 ZW |
2978 | /* As expand_unop, but will fail rather than attempt the operation in a |
2979 | different mode or with a libcall. */ | |
2980 | static rtx | |
2981 | expand_unop_direct (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
0c20a65f | 2982 | int unsignedp) |
77c9c6c2 | 2983 | { |
947131ba | 2984 | if (optab_handler (unoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 2985 | { |
947131ba | 2986 | int icode = (int) optab_handler (unoptab, mode); |
a995e389 | 2987 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 | 2988 | rtx xop0 = op0; |
9cce5b20 ZW |
2989 | rtx last = get_last_insn (); |
2990 | rtx pat, temp; | |
77c9c6c2 RK |
2991 | |
2992 | if (target) | |
2993 | temp = target; | |
2994 | else | |
2995 | temp = gen_reg_rtx (mode); | |
2996 | ||
2997 | if (GET_MODE (xop0) != VOIDmode | |
2998 | && GET_MODE (xop0) != mode0) | |
2999 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
3000 | ||
3001 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
3002 | ||
e3feb571 | 3003 | if (!insn_data[icode].operand[1].predicate (xop0, mode0)) |
77c9c6c2 RK |
3004 | xop0 = copy_to_mode_reg (mode0, xop0); |
3005 | ||
e3feb571 | 3006 | if (!insn_data[icode].operand[0].predicate (temp, mode)) |
77c9c6c2 RK |
3007 | temp = gen_reg_rtx (mode); |
3008 | ||
3009 | pat = GEN_FCN (icode) (temp, xop0); | |
3010 | if (pat) | |
3011 | { | |
2f937369 | 3012 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
b1ec3c92 | 3013 | && ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX)) |
77c9c6c2 RK |
3014 | { |
3015 | delete_insns_since (last); | |
b1ec3c92 | 3016 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
77c9c6c2 RK |
3017 | } |
3018 | ||
3019 | emit_insn (pat); | |
0c20a65f | 3020 | |
77c9c6c2 RK |
3021 | return temp; |
3022 | } | |
3023 | else | |
3024 | delete_insns_since (last); | |
3025 | } | |
9cce5b20 ZW |
3026 | return 0; |
3027 | } | |
3028 | ||
3029 | /* Generate code to perform an operation specified by UNOPTAB | |
3030 | on operand OP0, with result having machine-mode MODE. | |
3031 | ||
3032 | UNSIGNEDP is for the case where we have to widen the operands | |
3033 | to perform the operation. It says to use zero-extension. | |
3034 | ||
3035 | If TARGET is nonzero, the value | |
3036 | is generated there, if it is convenient to do so. | |
3037 | In all cases an rtx is returned for the locus of the value; | |
3038 | this may or may not be TARGET. */ | |
3039 | ||
3040 | rtx | |
3041 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
3042 | int unsignedp) | |
3043 | { | |
d858f359 | 3044 | enum mode_class mclass = GET_MODE_CLASS (mode); |
9cce5b20 ZW |
3045 | enum machine_mode wider_mode; |
3046 | rtx temp; | |
8a33f100 | 3047 | rtx libfunc; |
9cce5b20 ZW |
3048 | |
3049 | temp = expand_unop_direct (mode, unoptab, op0, target, unsignedp); | |
3050 | if (temp) | |
3051 | return temp; | |
77c9c6c2 | 3052 | |
9a856ec7 RK |
3053 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
3054 | ||
9cce5b20 | 3055 | /* Widening (or narrowing) clz needs special treatment. */ |
2928cd7a RH |
3056 | if (unoptab == clz_optab) |
3057 | { | |
3058 | temp = widen_clz (mode, op0, target); | |
3059 | if (temp) | |
3060 | return temp; | |
9cce5b20 ZW |
3061 | |
3062 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
947131ba | 3063 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
9cce5b20 ZW |
3064 | { |
3065 | temp = expand_doubleword_clz (mode, op0, target); | |
3066 | if (temp) | |
3067 | return temp; | |
3068 | } | |
3069 | ||
2928cd7a RH |
3070 | goto try_libcall; |
3071 | } | |
3072 | ||
2e6834d3 | 3073 | /* Widening (or narrowing) bswap needs special treatment. */ |
167fa32c | 3074 | if (unoptab == bswap_optab) |
2e6834d3 RH |
3075 | { |
3076 | temp = widen_bswap (mode, op0, target); | |
3077 | if (temp) | |
3078 | return temp; | |
3079 | ||
3080 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
947131ba | 3081 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
2e6834d3 RH |
3082 | { |
3083 | temp = expand_doubleword_bswap (mode, op0, target); | |
3084 | if (temp) | |
3085 | return temp; | |
3086 | } | |
3087 | ||
3088 | goto try_libcall; | |
3089 | } | |
167fa32c | 3090 | |
d858f359 | 3091 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
86556d87 BE |
3092 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3093 | wider_mode != VOIDmode; | |
9a856ec7 RK |
3094 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3095 | { | |
947131ba | 3096 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
9a856ec7 RK |
3097 | { |
3098 | rtx xop0 = op0; | |
9cce5b20 | 3099 | rtx last = get_last_insn (); |
9a856ec7 RK |
3100 | |
3101 | /* For certain operations, we need not actually extend | |
3102 | the narrow operand, as long as we will truncate the | |
835532b8 RK |
3103 | results to the same narrowness. */ |
3104 | ||
0661a3de | 3105 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
3106 | (unoptab == neg_optab |
3107 | || unoptab == one_cmpl_optab) | |
d858f359 | 3108 | && mclass == MODE_INT); |
0c20a65f | 3109 | |
b1ec3c92 CH |
3110 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3111 | unsignedp); | |
9a856ec7 RK |
3112 | |
3113 | if (temp) | |
3114 | { | |
d858f359 | 3115 | if (mclass != MODE_INT |
cd7ec127 R |
3116 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
3117 | GET_MODE_BITSIZE (wider_mode))) | |
9a856ec7 RK |
3118 | { |
3119 | if (target == 0) | |
3120 | target = gen_reg_rtx (mode); | |
3121 | convert_move (target, temp, 0); | |
3122 | return target; | |
3123 | } | |
3124 | else | |
3125 | return gen_lowpart (mode, temp); | |
3126 | } | |
3127 | else | |
3128 | delete_insns_since (last); | |
3129 | } | |
3130 | } | |
3131 | ||
77c9c6c2 RK |
3132 | /* These can be done a word at a time. */ |
3133 | if (unoptab == one_cmpl_optab | |
d858f359 | 3134 | && mclass == MODE_INT |
77c9c6c2 | 3135 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
947131ba | 3136 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 3137 | { |
bb93b973 | 3138 | int i; |
77c9c6c2 RK |
3139 | rtx insns; |
3140 | ||
3141 | if (target == 0 || target == op0) | |
3142 | target = gen_reg_rtx (mode); | |
3143 | ||
3144 | start_sequence (); | |
3145 | ||
3146 | /* Do the actual arithmetic. */ | |
3147 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
3148 | { | |
3149 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 3150 | rtx x = expand_unop (word_mode, unoptab, |
77c9c6c2 RK |
3151 | operand_subword_force (op0, i, mode), |
3152 | target_piece, unsignedp); | |
bb93b973 | 3153 | |
77c9c6c2 RK |
3154 | if (target_piece != x) |
3155 | emit_move_insn (target_piece, x); | |
3156 | } | |
3157 | ||
3158 | insns = get_insns (); | |
3159 | end_sequence (); | |
3160 | ||
d70dcf29 | 3161 | emit_insn (insns); |
77c9c6c2 RK |
3162 | return target; |
3163 | } | |
3164 | ||
8c55a142 | 3165 | if (unoptab->code == NEG) |
4977bab6 | 3166 | { |
8c55a142 | 3167 | /* Try negating floating point values by flipping the sign bit. */ |
74b14698 | 3168 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 3169 | { |
8c55a142 RH |
3170 | temp = expand_absneg_bit (NEG, mode, op0, target); |
3171 | if (temp) | |
3172 | return temp; | |
3173 | } | |
9ee0a442 | 3174 | |
8c55a142 RH |
3175 | /* If there is no negation pattern, and we have no negative zero, |
3176 | try subtracting from zero. */ | |
3177 | if (!HONOR_SIGNED_ZEROS (mode)) | |
3178 | { | |
3179 | temp = expand_binop (mode, (unoptab == negv_optab | |
3180 | ? subv_optab : sub_optab), | |
3181 | CONST0_RTX (mode), op0, target, | |
3182 | unsignedp, OPTAB_DIRECT); | |
3183 | if (temp) | |
3184 | return temp; | |
3185 | } | |
4977bab6 ZW |
3186 | } |
3187 | ||
2928cd7a RH |
3188 | /* Try calculating parity (x) as popcount (x) % 2. */ |
3189 | if (unoptab == parity_optab) | |
3190 | { | |
3191 | temp = expand_parity (mode, op0, target); | |
3192 | if (temp) | |
3193 | return temp; | |
3194 | } | |
3195 | ||
14670a74 SL |
3196 | /* Try implementing ffs (x) in terms of clz (x). */ |
3197 | if (unoptab == ffs_optab) | |
3198 | { | |
3199 | temp = expand_ffs (mode, op0, target); | |
3200 | if (temp) | |
3201 | return temp; | |
3202 | } | |
3203 | ||
3204 | /* Try implementing ctz (x) in terms of clz (x). */ | |
3205 | if (unoptab == ctz_optab) | |
3206 | { | |
3207 | temp = expand_ctz (mode, op0, target); | |
3208 | if (temp) | |
3209 | return temp; | |
3210 | } | |
3211 | ||
2928cd7a | 3212 | try_libcall: |
139e5e08 | 3213 | /* Now try a library call in this mode. */ |
8a33f100 JH |
3214 | libfunc = optab_libfunc (unoptab, mode); |
3215 | if (libfunc) | |
77c9c6c2 RK |
3216 | { |
3217 | rtx insns; | |
9a7f678c | 3218 | rtx value; |
1230d7f8 | 3219 | rtx eq_value; |
2928cd7a RH |
3220 | enum machine_mode outmode = mode; |
3221 | ||
3222 | /* All of these functions return small values. Thus we choose to | |
3223 | have them return something that isn't a double-word. */ | |
3224 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
3225 | || unoptab == popcount_optab || unoptab == parity_optab) | |
cd2ac05b | 3226 | outmode |
390b17c2 RE |
3227 | = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node), |
3228 | optab_libfunc (unoptab, mode))); | |
77c9c6c2 RK |
3229 | |
3230 | start_sequence (); | |
3231 | ||
3232 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3233 | if the libcall is cse'd or moved. */ | |
8a33f100 | 3234 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, outmode, |
2928cd7a | 3235 | 1, op0, mode); |
77c9c6c2 RK |
3236 | insns = get_insns (); |
3237 | end_sequence (); | |
3238 | ||
2928cd7a | 3239 | target = gen_reg_rtx (outmode); |
1230d7f8 RS |
3240 | eq_value = gen_rtx_fmt_e (unoptab->code, mode, op0); |
3241 | if (GET_MODE_SIZE (outmode) < GET_MODE_SIZE (mode)) | |
3242 | eq_value = simplify_gen_unary (TRUNCATE, outmode, eq_value, mode); | |
3243 | else if (GET_MODE_SIZE (outmode) > GET_MODE_SIZE (mode)) | |
3244 | eq_value = simplify_gen_unary (ZERO_EXTEND, outmode, eq_value, mode); | |
3245 | emit_libcall_block (insns, target, value, eq_value); | |
77c9c6c2 RK |
3246 | |
3247 | return target; | |
3248 | } | |
3249 | ||
3250 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3251 | ||
d858f359 | 3252 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 3253 | { |
86556d87 BE |
3254 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3255 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
3256 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3257 | { | |
947131ba | 3258 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing |
8a33f100 | 3259 | || optab_libfunc (unoptab, wider_mode)) |
77c9c6c2 | 3260 | { |
34e56753 | 3261 | rtx xop0 = op0; |
9cce5b20 | 3262 | rtx last = get_last_insn (); |
34e56753 RS |
3263 | |
3264 | /* For certain operations, we need not actually extend | |
3265 | the narrow operand, as long as we will truncate the | |
3266 | results to the same narrowness. */ | |
3267 | ||
0661a3de | 3268 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
3269 | (unoptab == neg_optab |
3270 | || unoptab == one_cmpl_optab) | |
d858f359 | 3271 | && mclass == MODE_INT); |
0c20a65f | 3272 | |
b1ec3c92 CH |
3273 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3274 | unsignedp); | |
34e56753 | 3275 | |
c117dddc KH |
3276 | /* If we are generating clz using wider mode, adjust the |
3277 | result. */ | |
3278 | if (unoptab == clz_optab && temp != 0) | |
3279 | temp = expand_binop (wider_mode, sub_optab, temp, | |
3280 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
3281 | - GET_MODE_BITSIZE (mode)), | |
3282 | target, true, OPTAB_DIRECT); | |
3283 | ||
34e56753 | 3284 | if (temp) |
77c9c6c2 | 3285 | { |
d858f359 | 3286 | if (mclass != MODE_INT) |
34e56753 RS |
3287 | { |
3288 | if (target == 0) | |
3289 | target = gen_reg_rtx (mode); | |
3290 | convert_move (target, temp, 0); | |
3291 | return target; | |
3292 | } | |
3293 | else | |
3294 | return gen_lowpart (mode, temp); | |
77c9c6c2 RK |
3295 | } |
3296 | else | |
34e56753 | 3297 | delete_insns_since (last); |
77c9c6c2 RK |
3298 | } |
3299 | } | |
3300 | } | |
3301 | ||
8c55a142 RH |
3302 | /* One final attempt at implementing negation via subtraction, |
3303 | this time allowing widening of the operand. */ | |
3304 | if (unoptab->code == NEG && !HONOR_SIGNED_ZEROS (mode)) | |
0c20a65f | 3305 | { |
b82b6eea | 3306 | rtx temp; |
91ce572a CC |
3307 | temp = expand_binop (mode, |
3308 | unoptab == negv_optab ? subv_optab : sub_optab, | |
3309 | CONST0_RTX (mode), op0, | |
3310 | target, unsignedp, OPTAB_LIB_WIDEN); | |
b82b6eea | 3311 | if (temp) |
8c55a142 | 3312 | return temp; |
b82b6eea | 3313 | } |
0c20a65f | 3314 | |
77c9c6c2 RK |
3315 | return 0; |
3316 | } | |
3317 | \f | |
decdfa82 RS |
3318 | /* Emit code to compute the absolute value of OP0, with result to |
3319 | TARGET if convenient. (TARGET may be 0.) The return value says | |
3320 | where the result actually is to be found. | |
3321 | ||
3322 | MODE is the mode of the operand; the mode of the result is | |
3323 | different but can be deduced from MODE. | |
3324 | ||
91813b28 | 3325 | */ |
7fd01431 RK |
3326 | |
3327 | rtx | |
0c20a65f AJ |
3328 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
3329 | int result_unsignedp) | |
7fd01431 | 3330 | { |
2ef0a555 | 3331 | rtx temp; |
7fd01431 | 3332 | |
91ce572a CC |
3333 | if (! flag_trapv) |
3334 | result_unsignedp = 1; | |
3335 | ||
7fd01431 | 3336 | /* First try to do it with a special abs instruction. */ |
91ce572a CC |
3337 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
3338 | op0, target, 0); | |
7fd01431 RK |
3339 | if (temp != 0) |
3340 | return temp; | |
3341 | ||
4977bab6 | 3342 | /* For floating point modes, try clearing the sign bit. */ |
3d8bf70f | 3343 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 3344 | { |
8c55a142 RH |
3345 | temp = expand_absneg_bit (ABS, mode, op0, target); |
3346 | if (temp) | |
3347 | return temp; | |
4977bab6 ZW |
3348 | } |
3349 | ||
14a774a9 | 3350 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
947131ba | 3351 | if (optab_handler (smax_optab, mode) != CODE_FOR_nothing |
8c55a142 | 3352 | && !HONOR_SIGNED_ZEROS (mode)) |
14a774a9 RK |
3353 | { |
3354 | rtx last = get_last_insn (); | |
3355 | ||
3356 | temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); | |
3357 | if (temp != 0) | |
3358 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3359 | OPTAB_WIDEN); | |
3360 | ||
3361 | if (temp != 0) | |
3362 | return temp; | |
3363 | ||
3364 | delete_insns_since (last); | |
3365 | } | |
3366 | ||
7fd01431 RK |
3367 | /* If this machine has expensive jumps, we can do integer absolute |
3368 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
e1078cfc | 3369 | where W is the width of MODE. */ |
7fd01431 | 3370 | |
3a4fd356 JH |
3371 | if (GET_MODE_CLASS (mode) == MODE_INT |
3372 | && BRANCH_COST (optimize_insn_for_speed_p (), | |
3373 | false) >= 2) | |
7fd01431 RK |
3374 | { |
3375 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
3376 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3377 | NULL_RTX, 0); | |
3378 | ||
3379 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3380 | OPTAB_LIB_WIDEN); | |
3381 | if (temp != 0) | |
91ce572a CC |
3382 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
3383 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
7fd01431 RK |
3384 | |
3385 | if (temp != 0) | |
3386 | return temp; | |
3387 | } | |
3388 | ||
2ef0a555 RH |
3389 | return NULL_RTX; |
3390 | } | |
3391 | ||
3392 | rtx | |
0c20a65f AJ |
3393 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
3394 | int result_unsignedp, int safe) | |
2ef0a555 RH |
3395 | { |
3396 | rtx temp, op1; | |
3397 | ||
77173bbe KH |
3398 | if (! flag_trapv) |
3399 | result_unsignedp = 1; | |
3400 | ||
2ef0a555 RH |
3401 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
3402 | if (temp != 0) | |
3403 | return temp; | |
3404 | ||
7fd01431 | 3405 | /* If that does not win, use conditional jump and negate. */ |
5c0bf747 RK |
3406 | |
3407 | /* It is safe to use the target if it is the same | |
3408 | as the source if this is also a pseudo register */ | |
f8cfc6aa | 3409 | if (op0 == target && REG_P (op0) |
5c0bf747 RK |
3410 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) |
3411 | safe = 1; | |
3412 | ||
7fd01431 RK |
3413 | op1 = gen_label_rtx (); |
3414 | if (target == 0 || ! safe | |
3415 | || GET_MODE (target) != mode | |
3c0cb5de | 3416 | || (MEM_P (target) && MEM_VOLATILE_P (target)) |
f8cfc6aa | 3417 | || (REG_P (target) |
7fd01431 RK |
3418 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) |
3419 | target = gen_reg_rtx (mode); | |
3420 | ||
3421 | emit_move_insn (target, op0); | |
3422 | NO_DEFER_POP; | |
3423 | ||
3bf78d3b | 3424 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
40e90eac | 3425 | NULL_RTX, NULL_RTX, op1, -1); |
7fd01431 | 3426 | |
91ce572a CC |
3427 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
3428 | target, target, 0); | |
7fd01431 RK |
3429 | if (op0 != target) |
3430 | emit_move_insn (target, op0); | |
3431 | emit_label (op1); | |
3432 | OK_DEFER_POP; | |
3433 | return target; | |
3434 | } | |
046625fa | 3435 | |
65026047 ER |
3436 | /* Emit code to compute the one's complement absolute value of OP0 |
3437 | (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient. | |
3438 | (TARGET may be NULL_RTX.) The return value says where the result | |
3439 | actually is to be found. | |
3440 | ||
3441 | MODE is the mode of the operand; the mode of the result is | |
3442 | different but can be deduced from MODE. */ | |
3443 | ||
3444 | rtx | |
3445 | expand_one_cmpl_abs_nojump (enum machine_mode mode, rtx op0, rtx target) | |
3446 | { | |
3447 | rtx temp; | |
3448 | ||
3449 | /* Not applicable for floating point modes. */ | |
3450 | if (FLOAT_MODE_P (mode)) | |
3451 | return NULL_RTX; | |
3452 | ||
3453 | /* If we have a MAX insn, we can do this as MAX (x, ~x). */ | |
947131ba | 3454 | if (optab_handler (smax_optab, mode) != CODE_FOR_nothing) |
65026047 ER |
3455 | { |
3456 | rtx last = get_last_insn (); | |
3457 | ||
3458 | temp = expand_unop (mode, one_cmpl_optab, op0, NULL_RTX, 0); | |
3459 | if (temp != 0) | |
3460 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3461 | OPTAB_WIDEN); | |
3462 | ||
3463 | if (temp != 0) | |
3464 | return temp; | |
3465 | ||
3466 | delete_insns_since (last); | |
3467 | } | |
3468 | ||
3469 | /* If this machine has expensive jumps, we can do one's complement | |
3470 | absolute value of X as (((signed) x >> (W-1)) ^ x). */ | |
3471 | ||
3472 | if (GET_MODE_CLASS (mode) == MODE_INT | |
3473 | && BRANCH_COST (optimize_insn_for_speed_p (), | |
3474 | false) >= 2) | |
3475 | { | |
3476 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
3477 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3478 | NULL_RTX, 0); | |
3479 | ||
3480 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3481 | OPTAB_LIB_WIDEN); | |
3482 | ||
3483 | if (temp != 0) | |
3484 | return temp; | |
3485 | } | |
3486 | ||
3487 | return NULL_RTX; | |
3488 | } | |
3489 | ||
ae394659 RH |
3490 | /* A subroutine of expand_copysign, perform the copysign operation using the |
3491 | abs and neg primitives advertised to exist on the target. The assumption | |
3492 | is that we have a split register file, and leaving op0 in fp registers, | |
3493 | and not playing with subregs so much, will help the register allocator. */ | |
046625fa | 3494 | |
9abd1955 | 3495 | static rtx |
ae394659 RH |
3496 | expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target, |
3497 | int bitpos, bool op0_is_abs) | |
046625fa | 3498 | { |
046625fa | 3499 | enum machine_mode imode; |
d0c9d431 UB |
3500 | int icode; |
3501 | rtx sign, label; | |
046625fa | 3502 | |
ae394659 RH |
3503 | if (target == op1) |
3504 | target = NULL_RTX; | |
046625fa | 3505 | |
d0c9d431 UB |
3506 | /* Check if the back end provides an insn that handles signbit for the |
3507 | argument's mode. */ | |
947131ba | 3508 | icode = (int) optab_handler (signbit_optab, mode); |
d0c9d431 | 3509 | if (icode != CODE_FOR_nothing) |
ae394659 | 3510 | { |
d0c9d431 UB |
3511 | imode = insn_data[icode].operand[0].mode; |
3512 | sign = gen_reg_rtx (imode); | |
3513 | emit_unop_insn (icode, sign, op1, UNKNOWN); | |
ae394659 RH |
3514 | } |
3515 | else | |
3516 | { | |
54fb1ae0 | 3517 | double_int mask; |
d0c9d431 UB |
3518 | |
3519 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
3520 | { | |
3521 | imode = int_mode_for_mode (mode); | |
3522 | if (imode == BLKmode) | |
3523 | return NULL_RTX; | |
3524 | op1 = gen_lowpart (imode, op1); | |
3525 | } | |
ae394659 | 3526 | else |
d0c9d431 UB |
3527 | { |
3528 | int word; | |
046625fa | 3529 | |
d0c9d431 UB |
3530 | imode = word_mode; |
3531 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3532 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3533 | else | |
3534 | word = bitpos / BITS_PER_WORD; | |
3535 | bitpos = bitpos % BITS_PER_WORD; | |
3536 | op1 = operand_subword_force (op1, word, mode); | |
3537 | } | |
3538 | ||
54fb1ae0 | 3539 | mask = double_int_setbit (double_int_zero, bitpos); |
d0c9d431 | 3540 | |
d0c9d431 | 3541 | sign = expand_binop (imode, and_optab, op1, |
54fb1ae0 | 3542 | immed_double_int_const (mask, imode), |
d0c9d431 | 3543 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
ae394659 | 3544 | } |
046625fa | 3545 | |
d0c9d431 | 3546 | if (!op0_is_abs) |
8c55a142 | 3547 | { |
d0c9d431 UB |
3548 | op0 = expand_unop (mode, abs_optab, op0, target, 0); |
3549 | if (op0 == NULL) | |
3550 | return NULL_RTX; | |
3551 | target = op0; | |
8c55a142 | 3552 | } |
ae394659 RH |
3553 | else |
3554 | { | |
d0c9d431 UB |
3555 | if (target == NULL_RTX) |
3556 | target = copy_to_reg (op0); | |
3557 | else | |
3558 | emit_move_insn (target, op0); | |
ae394659 RH |
3559 | } |
3560 | ||
ae394659 | 3561 | label = gen_label_rtx (); |
d0c9d431 | 3562 | emit_cmp_and_jump_insns (sign, const0_rtx, EQ, NULL_RTX, imode, 1, label); |
ae394659 RH |
3563 | |
3564 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3565 | op0 = simplify_unary_operation (NEG, mode, op0, mode); | |
3566 | else | |
3567 | op0 = expand_unop (mode, neg_optab, op0, target, 0); | |
3568 | if (op0 != target) | |
3569 | emit_move_insn (target, op0); | |
3570 | ||
3571 | emit_label (label); | |
3572 | ||
3573 | return target; | |
3574 | } | |
3575 | ||
3576 | ||
3577 | /* A subroutine of expand_copysign, perform the entire copysign operation | |
3578 | with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS | |
3579 | is true if op0 is known to have its sign bit clear. */ | |
3580 | ||
3581 | static rtx | |
3582 | expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
3583 | int bitpos, bool op0_is_abs) | |
3584 | { | |
3585 | enum machine_mode imode; | |
54fb1ae0 | 3586 | double_int mask; |
ae394659 RH |
3587 | int word, nwords, i; |
3588 | rtx temp, insns; | |
046625fa | 3589 | |
8c55a142 | 3590 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) |
046625fa | 3591 | { |
8c55a142 RH |
3592 | imode = int_mode_for_mode (mode); |
3593 | if (imode == BLKmode) | |
3594 | return NULL_RTX; | |
3595 | word = 0; | |
3596 | nwords = 1; | |
3597 | } | |
3598 | else | |
3599 | { | |
3600 | imode = word_mode; | |
3601 | ||
3602 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3603 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3604 | else | |
3605 | word = bitpos / BITS_PER_WORD; | |
3606 | bitpos = bitpos % BITS_PER_WORD; | |
3607 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
046625fa RH |
3608 | } |
3609 | ||
54fb1ae0 | 3610 | mask = double_int_setbit (double_int_zero, bitpos); |
046625fa | 3611 | |
8c55a142 RH |
3612 | if (target == 0 || target == op0 || target == op1) |
3613 | target = gen_reg_rtx (mode); | |
3614 | ||
3615 | if (nwords > 1) | |
046625fa | 3616 | { |
8c55a142 RH |
3617 | start_sequence (); |
3618 | ||
3619 | for (i = 0; i < nwords; ++i) | |
046625fa | 3620 | { |
8c55a142 RH |
3621 | rtx targ_piece = operand_subword (target, i, 1, mode); |
3622 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 3623 | |
8c55a142 RH |
3624 | if (i == word) |
3625 | { | |
ae394659 | 3626 | if (!op0_is_abs) |
54fb1ae0 AS |
3627 | op0_piece |
3628 | = expand_binop (imode, and_optab, op0_piece, | |
3629 | immed_double_int_const (double_int_not (mask), | |
3630 | imode), | |
3631 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
8c55a142 RH |
3632 | |
3633 | op1 = expand_binop (imode, and_optab, | |
3634 | operand_subword_force (op1, i, mode), | |
54fb1ae0 | 3635 | immed_double_int_const (mask, imode), |
8c55a142 RH |
3636 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3637 | ||
3638 | temp = expand_binop (imode, ior_optab, op0_piece, op1, | |
3639 | targ_piece, 1, OPTAB_LIB_WIDEN); | |
3640 | if (temp != targ_piece) | |
3641 | emit_move_insn (targ_piece, temp); | |
3642 | } | |
3643 | else | |
3644 | emit_move_insn (targ_piece, op0_piece); | |
046625fa | 3645 | } |
8c55a142 RH |
3646 | |
3647 | insns = get_insns (); | |
3648 | end_sequence (); | |
3649 | ||
d70dcf29 | 3650 | emit_insn (insns); |
046625fa RH |
3651 | } |
3652 | else | |
8c55a142 RH |
3653 | { |
3654 | op1 = expand_binop (imode, and_optab, gen_lowpart (imode, op1), | |
54fb1ae0 | 3655 | immed_double_int_const (mask, imode), |
8c55a142 RH |
3656 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3657 | ||
3658 | op0 = gen_lowpart (imode, op0); | |
ae394659 | 3659 | if (!op0_is_abs) |
8c55a142 | 3660 | op0 = expand_binop (imode, and_optab, op0, |
54fb1ae0 AS |
3661 | immed_double_int_const (double_int_not (mask), |
3662 | imode), | |
8c55a142 RH |
3663 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3664 | ||
3665 | temp = expand_binop (imode, ior_optab, op0, op1, | |
3666 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); | |
3667 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
3668 | } | |
046625fa RH |
3669 | |
3670 | return target; | |
3671 | } | |
ae394659 | 3672 | |
c414ac1d | 3673 | /* Expand the C99 copysign operation. OP0 and OP1 must be the same |
ae394659 RH |
3674 | scalar floating point mode. Return NULL if we do not know how to |
3675 | expand the operation inline. */ | |
3676 | ||
3677 | rtx | |
3678 | expand_copysign (rtx op0, rtx op1, rtx target) | |
3679 | { | |
3680 | enum machine_mode mode = GET_MODE (op0); | |
3681 | const struct real_format *fmt; | |
ae394659 RH |
3682 | bool op0_is_abs; |
3683 | rtx temp; | |
3684 | ||
3685 | gcc_assert (SCALAR_FLOAT_MODE_P (mode)); | |
3686 | gcc_assert (GET_MODE (op1) == mode); | |
3687 | ||
3688 | /* First try to do it with a special instruction. */ | |
3689 | temp = expand_binop (mode, copysign_optab, op0, op1, | |
3690 | target, 0, OPTAB_DIRECT); | |
3691 | if (temp) | |
3692 | return temp; | |
3693 | ||
3694 | fmt = REAL_MODE_FORMAT (mode); | |
3695 | if (fmt == NULL || !fmt->has_signed_zero) | |
3696 | return NULL_RTX; | |
3697 | ||
ae394659 RH |
3698 | op0_is_abs = false; |
3699 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3700 | { | |
3701 | if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) | |
3702 | op0 = simplify_unary_operation (ABS, mode, op0, mode); | |
3703 | op0_is_abs = true; | |
3704 | } | |
3705 | ||
c064fde5 RS |
3706 | if (fmt->signbit_ro >= 0 |
3707 | && (GET_CODE (op0) == CONST_DOUBLE | |
947131ba RS |
3708 | || (optab_handler (neg_optab, mode) != CODE_FOR_nothing |
3709 | && optab_handler (abs_optab, mode) != CODE_FOR_nothing))) | |
ae394659 RH |
3710 | { |
3711 | temp = expand_copysign_absneg (mode, op0, op1, target, | |
c064fde5 | 3712 | fmt->signbit_ro, op0_is_abs); |
ae394659 RH |
3713 | if (temp) |
3714 | return temp; | |
3715 | } | |
3716 | ||
c064fde5 RS |
3717 | if (fmt->signbit_rw < 0) |
3718 | return NULL_RTX; | |
3719 | return expand_copysign_bit (mode, op0, op1, target, | |
3720 | fmt->signbit_rw, op0_is_abs); | |
ae394659 | 3721 | } |
7fd01431 | 3722 | \f |
77c9c6c2 RK |
3723 | /* Generate an instruction whose insn-code is INSN_CODE, |
3724 | with two operands: an output TARGET and an input OP0. | |
3725 | TARGET *must* be nonzero, and the output is always stored there. | |
3726 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
b8698a0f | 3727 | the value that is stored into TARGET. |
77c9c6c2 | 3728 | |
18bd082d JH |
3729 | Return false if expansion failed. */ |
3730 | ||
3731 | bool | |
3732 | maybe_emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) | |
77c9c6c2 | 3733 | { |
b3694847 | 3734 | rtx temp; |
a995e389 | 3735 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 | 3736 | rtx pat; |
5e04ef8f | 3737 | rtx last = get_last_insn (); |
77c9c6c2 | 3738 | |
ad76cef8 | 3739 | temp = target; |
77c9c6c2 | 3740 | |
77c9c6c2 RK |
3741 | /* Now, if insn does not accept our operands, put them into pseudos. */ |
3742 | ||
e3feb571 | 3743 | if (!insn_data[icode].operand[1].predicate (op0, mode0)) |
77c9c6c2 RK |
3744 | op0 = copy_to_mode_reg (mode0, op0); |
3745 | ||
1d8eeb63 | 3746 | if (!insn_data[icode].operand[0].predicate (temp, GET_MODE (temp))) |
77c9c6c2 RK |
3747 | temp = gen_reg_rtx (GET_MODE (temp)); |
3748 | ||
3749 | pat = GEN_FCN (icode) (temp, op0); | |
18bd082d | 3750 | if (!pat) |
5e04ef8f JH |
3751 | { |
3752 | delete_insns_since (last); | |
3753 | return false; | |
3754 | } | |
77c9c6c2 | 3755 | |
2f937369 | 3756 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
b1ec3c92 | 3757 | add_equal_note (pat, temp, code, op0, NULL_RTX); |
0c20a65f | 3758 | |
77c9c6c2 RK |
3759 | emit_insn (pat); |
3760 | ||
3761 | if (temp != target) | |
3762 | emit_move_insn (target, temp); | |
18bd082d JH |
3763 | return true; |
3764 | } | |
3765 | /* Generate an instruction whose insn-code is INSN_CODE, | |
3766 | with two operands: an output TARGET and an input OP0. | |
3767 | TARGET *must* be nonzero, and the output is always stored there. | |
3768 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3769 | the value that is stored into TARGET. */ | |
3770 | ||
3771 | void | |
3772 | emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) | |
3773 | { | |
3774 | bool ok = maybe_emit_unop_insn (icode, target, op0, code); | |
3775 | gcc_assert (ok); | |
77c9c6c2 RK |
3776 | } |
3777 | \f | |
326a31e9 R |
3778 | struct no_conflict_data |
3779 | { | |
3780 | rtx target, first, insn; | |
3781 | bool must_stay; | |
3782 | }; | |
3783 | ||
d70dcf29 KZ |
3784 | /* Called via note_stores by emit_libcall_block. Set P->must_stay if |
3785 | the currently examined clobber / store has to stay in the list of | |
3786 | insns that constitute the actual libcall block. */ | |
326a31e9 | 3787 | static void |
7bc980e1 | 3788 | no_conflict_move_test (rtx dest, const_rtx set, void *p0) |
326a31e9 | 3789 | { |
d3bfe4de | 3790 | struct no_conflict_data *p= (struct no_conflict_data *) p0; |
326a31e9 R |
3791 | |
3792 | /* If this inns directly contributes to setting the target, it must stay. */ | |
3793 | if (reg_overlap_mentioned_p (p->target, dest)) | |
3794 | p->must_stay = true; | |
3795 | /* If we haven't committed to keeping any other insns in the list yet, | |
3796 | there is nothing more to check. */ | |
3797 | else if (p->insn == p->first) | |
3798 | return; | |
3799 | /* If this insn sets / clobbers a register that feeds one of the insns | |
3800 | already in the list, this insn has to stay too. */ | |
9617ccfd R |
3801 | else if (reg_overlap_mentioned_p (dest, PATTERN (p->first)) |
3802 | || (CALL_P (p->first) && (find_reg_fusage (p->first, USE, dest))) | |
326a31e9 R |
3803 | || reg_used_between_p (dest, p->first, p->insn) |
3804 | /* Likewise if this insn depends on a register set by a previous | |
ca7a5aec R |
3805 | insn in the list, or if it sets a result (presumably a hard |
3806 | register) that is set or clobbered by a previous insn. | |
3807 | N.B. the modified_*_p (SET_DEST...) tests applied to a MEM | |
3808 | SET_DEST perform the former check on the address, and the latter | |
3809 | check on the MEM. */ | |
326a31e9 R |
3810 | || (GET_CODE (set) == SET |
3811 | && (modified_in_p (SET_SRC (set), p->first) | |
ca7a5aec R |
3812 | || modified_in_p (SET_DEST (set), p->first) |
3813 | || modified_between_p (SET_SRC (set), p->first, p->insn) | |
3814 | || modified_between_p (SET_DEST (set), p->first, p->insn)))) | |
326a31e9 R |
3815 | p->must_stay = true; |
3816 | } | |
3817 | ||
77c9c6c2 RK |
3818 | \f |
3819 | /* Emit code to make a call to a constant function or a library call. | |
3820 | ||
3821 | INSNS is a list containing all insns emitted in the call. | |
3822 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3823 | to TARGET, which is logically equivalent to EQUIV. | |
3824 | ||
3825 | We first emit any insns that set a pseudo on the assumption that these are | |
3826 | loading constants into registers; doing so allows them to be safely cse'ed | |
3827 | between blocks. Then we emit all the other insns in the block, followed by | |
3828 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
856905c2 SB |
3829 | note with an operand of EQUIV. */ |
3830 | ||
77c9c6c2 | 3831 | void |
0c20a65f | 3832 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) |
77c9c6c2 | 3833 | { |
aff2c2d3 | 3834 | rtx final_dest = target; |
0f900dfa | 3835 | rtx next, last, insn; |
77c9c6c2 | 3836 | |
aff2c2d3 BS |
3837 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3838 | into a MEM later. Protect the libcall block from this change. */ | |
3839 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3840 | target = gen_reg_rtx (GET_MODE (target)); | |
0c20a65f | 3841 | |
5154e79a AH |
3842 | /* If we're using non-call exceptions, a libcall corresponding to an |
3843 | operation that may trap may also trap. */ | |
1d65f45c | 3844 | /* ??? See the comment in front of make_reg_eh_region_note. */ |
8f4f502f | 3845 | if (cfun->can_throw_non_call_exceptions && may_trap_p (equiv)) |
5154e79a AH |
3846 | { |
3847 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
4b4bf941 | 3848 | if (CALL_P (insn)) |
5154e79a AH |
3849 | { |
3850 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
1d65f45c RH |
3851 | if (note) |
3852 | { | |
3853 | int lp_nr = INTVAL (XEXP (note, 0)); | |
3854 | if (lp_nr == 0 || lp_nr == INT_MIN) | |
3855 | remove_note (insn, note); | |
3856 | } | |
5154e79a AH |
3857 | } |
3858 | } | |
3859 | else | |
1d65f45c RH |
3860 | { |
3861 | /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION | |
3862 | reg note to indicate that this call cannot throw or execute a nonlocal | |
3863 | goto (unless there is already a REG_EH_REGION note, in which case | |
3864 | we update it). */ | |
3865 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
3866 | if (CALL_P (insn)) | |
3867 | make_reg_eh_region_note_nothrow_nononlocal (insn); | |
3868 | } | |
b472794d | 3869 | |
77c9c6c2 | 3870 | /* First emit all insns that set pseudos. Remove them from the list as |
ccf5f342 | 3871 | we go. Avoid insns that set pseudos which were referenced in previous |
29ebe69a | 3872 | insns. These can be generated by move_by_pieces, for example, |
ccf5f342 RK |
3873 | to update an address. Similarly, avoid insns that reference things |
3874 | set in previous insns. */ | |
77c9c6c2 RK |
3875 | |
3876 | for (insn = insns; insn; insn = next) | |
3877 | { | |
3878 | rtx set = single_set (insn); | |
3879 | ||
3880 | next = NEXT_INSN (insn); | |
3881 | ||
f8cfc6aa | 3882 | if (set != 0 && REG_P (SET_DEST (set)) |
748ebfc7 | 3883 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) |
77c9c6c2 | 3884 | { |
748ebfc7 R |
3885 | struct no_conflict_data data; |
3886 | ||
3887 | data.target = const0_rtx; | |
3888 | data.first = insns; | |
3889 | data.insn = insn; | |
3890 | data.must_stay = 0; | |
3891 | note_stores (PATTERN (insn), no_conflict_move_test, &data); | |
3892 | if (! data.must_stay) | |
3893 | { | |
3894 | if (PREV_INSN (insn)) | |
3895 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3896 | else | |
3897 | insns = next; | |
77c9c6c2 | 3898 | |
748ebfc7 R |
3899 | if (next) |
3900 | PREV_INSN (next) = PREV_INSN (insn); | |
77c9c6c2 | 3901 | |
748ebfc7 R |
3902 | add_insn (insn); |
3903 | } | |
77c9c6c2 | 3904 | } |
695a94b3 RS |
3905 | |
3906 | /* Some ports use a loop to copy large arguments onto the stack. | |
3907 | Don't move anything outside such a loop. */ | |
4b4bf941 | 3908 | if (LABEL_P (insn)) |
695a94b3 | 3909 | break; |
77c9c6c2 RK |
3910 | } |
3911 | ||
77c9c6c2 | 3912 | /* Write the remaining insns followed by the final copy. */ |
77c9c6c2 RK |
3913 | for (insn = insns; insn; insn = next) |
3914 | { | |
3915 | next = NEXT_INSN (insn); | |
3916 | ||
3917 | add_insn (insn); | |
3918 | } | |
3919 | ||
3920 | last = emit_move_insn (target, result); | |
947131ba | 3921 | if (optab_handler (mov_optab, GET_MODE (target)) != CODE_FOR_nothing) |
5fa671cf | 3922 | set_unique_reg_note (last, REG_EQUAL, copy_rtx (equiv)); |
77c9c6c2 | 3923 | |
e85427f9 BS |
3924 | if (final_dest != target) |
3925 | emit_move_insn (final_dest, target); | |
77c9c6c2 RK |
3926 | } |
3927 | \f | |
1c0290ea | 3928 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
1eb8759b RH |
3929 | PURPOSE describes how this comparison will be used. CODE is the rtx |
3930 | comparison code we will be using. | |
3931 | ||
3932 | ??? Actually, CODE is slightly weaker than that. A target is still | |
0c20a65f | 3933 | required to implement all of the normal bcc operations, but not |
1eb8759b | 3934 | required to implement all (or any) of the unordered bcc operations. */ |
0c20a65f | 3935 | |
1c0290ea | 3936 | int |
0c20a65f AJ |
3937 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
3938 | enum can_compare_purpose purpose) | |
b30f05db | 3939 | { |
c3c64f50 PB |
3940 | rtx test; |
3941 | test = gen_rtx_fmt_ee (code, mode, const0_rtx, const0_rtx); | |
b30f05db BS |
3942 | do |
3943 | { | |
c3c64f50 PB |
3944 | int icode; |
3945 | ||
1c0290ea | 3946 | if (purpose == ccp_jump |
947131ba | 3947 | && (icode = optab_handler (cbranch_optab, mode)) != CODE_FOR_nothing |
c3c64f50 PB |
3948 | && insn_data[icode].operand[0].predicate (test, mode)) |
3949 | return 1; | |
3950 | if (purpose == ccp_store_flag | |
947131ba | 3951 | && (icode = optab_handler (cstore_optab, mode)) != CODE_FOR_nothing |
c3c64f50 PB |
3952 | && insn_data[icode].operand[1].predicate (test, mode)) |
3953 | return 1; | |
1c0290ea | 3954 | if (purpose == ccp_cmov |
947131ba | 3955 | && optab_handler (cmov_optab, mode) != CODE_FOR_nothing) |
1c0290ea | 3956 | return 1; |
c3c64f50 | 3957 | |
b30f05db | 3958 | mode = GET_MODE_WIDER_MODE (mode); |
c3c64f50 | 3959 | PUT_MODE (test, mode); |
1c0290ea BS |
3960 | } |
3961 | while (mode != VOIDmode); | |
b30f05db BS |
3962 | |
3963 | return 0; | |
3964 | } | |
3965 | ||
3966 | /* This function is called when we are going to emit a compare instruction that | |
3967 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
3968 | ||
3969 | *PMODE is the mode of the inputs (in case they are const_int). | |
3970 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
f90b7a5a | 3971 | this matters if they need to be widened (as given by METHODS). |
77c9c6c2 | 3972 | |
a06ef755 | 3973 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
77c9c6c2 | 3974 | |
b30f05db BS |
3975 | This function performs all the setup necessary so that the caller only has |
3976 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
3977 | comparison or emitting a library call to perform the comparison if no insn | |
3978 | is available to handle it. | |
3979 | The values which are passed in through pointers can be modified; the caller | |
0e61db61 NS |
3980 | should perform the comparison on the modified values. Constant |
3981 | comparisons must have already been folded. */ | |
77c9c6c2 | 3982 | |
a06ef755 | 3983 | static void |
f90b7a5a PB |
3984 | prepare_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3985 | int unsignedp, enum optab_methods methods, | |
3986 | rtx *ptest, enum machine_mode *pmode) | |
77c9c6c2 | 3987 | { |
b30f05db | 3988 | enum machine_mode mode = *pmode; |
f90b7a5a PB |
3989 | rtx libfunc, test; |
3990 | enum machine_mode cmp_mode; | |
3991 | enum mode_class mclass; | |
3992 | ||
3993 | /* The other methods are not needed. */ | |
3994 | gcc_assert (methods == OPTAB_DIRECT || methods == OPTAB_WIDEN | |
3995 | || methods == OPTAB_LIB_WIDEN); | |
77c9c6c2 | 3996 | |
5e8d1826 PB |
3997 | /* If we are optimizing, force expensive constants into a register. */ |
3998 | if (CONSTANT_P (x) && optimize | |
3999 | && (rtx_cost (x, COMPARE, optimize_insn_for_speed_p ()) | |
4000 | > COSTS_N_INSNS (1))) | |
4001 | x = force_reg (mode, x); | |
4002 | ||
4003 | if (CONSTANT_P (y) && optimize | |
4004 | && (rtx_cost (y, COMPARE, optimize_insn_for_speed_p ()) | |
4005 | > COSTS_N_INSNS (1))) | |
4006 | y = force_reg (mode, y); | |
4007 | ||
362cc3d4 | 4008 | #ifdef HAVE_cc0 |
0e61db61 NS |
4009 | /* Make sure if we have a canonical comparison. The RTL |
4010 | documentation states that canonical comparisons are required only | |
4011 | for targets which have cc0. */ | |
e3feb571 | 4012 | gcc_assert (!CONSTANT_P (x) || CONSTANT_P (y)); |
362cc3d4 MH |
4013 | #endif |
4014 | ||
77c9c6c2 RK |
4015 | /* Don't let both operands fail to indicate the mode. */ |
4016 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
4017 | x = force_reg (mode, x); | |
f90b7a5a PB |
4018 | if (mode == VOIDmode) |
4019 | mode = GET_MODE (x) != VOIDmode ? GET_MODE (x) : GET_MODE (y); | |
77c9c6c2 RK |
4020 | |
4021 | /* Handle all BLKmode compares. */ | |
4022 | ||
4023 | if (mode == BLKmode) | |
4024 | { | |
f90b7a5a | 4025 | enum machine_mode result_mode; |
118355a0 ZW |
4026 | enum insn_code cmp_code; |
4027 | tree length_type; | |
4028 | rtx libfunc; | |
b30f05db | 4029 | rtx result; |
118355a0 | 4030 | rtx opalign |
f4dc10d1 | 4031 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); |
b30f05db | 4032 | |
e3feb571 | 4033 | gcc_assert (size); |
118355a0 | 4034 | |
118355a0 ZW |
4035 | /* Try to use a memory block compare insn - either cmpstr |
4036 | or cmpmem will do. */ | |
4037 | for (cmp_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
4038 | cmp_mode != VOIDmode; | |
4039 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode)) | |
358b8f01 | 4040 | { |
f9621cc4 | 4041 | cmp_code = direct_optab_handler (cmpmem_optab, cmp_mode); |
118355a0 | 4042 | if (cmp_code == CODE_FOR_nothing) |
f9621cc4 | 4043 | cmp_code = direct_optab_handler (cmpstr_optab, cmp_mode); |
40c1d5f8 | 4044 | if (cmp_code == CODE_FOR_nothing) |
f9621cc4 | 4045 | cmp_code = direct_optab_handler (cmpstrn_optab, cmp_mode); |
118355a0 ZW |
4046 | if (cmp_code == CODE_FOR_nothing) |
4047 | continue; | |
4048 | ||
4049 | /* Must make sure the size fits the insn's mode. */ | |
481683e1 | 4050 | if ((CONST_INT_P (size) |
118355a0 ZW |
4051 | && INTVAL (size) >= (1 << GET_MODE_BITSIZE (cmp_mode))) |
4052 | || (GET_MODE_BITSIZE (GET_MODE (size)) | |
4053 | > GET_MODE_BITSIZE (cmp_mode))) | |
4054 | continue; | |
4055 | ||
4056 | result_mode = insn_data[cmp_code].operand[0].mode; | |
358b8f01 | 4057 | result = gen_reg_rtx (result_mode); |
118355a0 ZW |
4058 | size = convert_to_mode (cmp_mode, size, 1); |
4059 | emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign)); | |
4060 | ||
f90b7a5a PB |
4061 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx); |
4062 | *pmode = result_mode; | |
118355a0 | 4063 | return; |
77c9c6c2 | 4064 | } |
118355a0 | 4065 | |
f90b7a5a PB |
4066 | if (methods != OPTAB_LIB && methods != OPTAB_LIB_WIDEN) |
4067 | goto fail; | |
4068 | ||
8f99553f | 4069 | /* Otherwise call a library function, memcmp. */ |
118355a0 ZW |
4070 | libfunc = memcmp_libfunc; |
4071 | length_type = sizetype; | |
118355a0 ZW |
4072 | result_mode = TYPE_MODE (integer_type_node); |
4073 | cmp_mode = TYPE_MODE (length_type); | |
4074 | size = convert_to_mode (TYPE_MODE (length_type), size, | |
8df83eae | 4075 | TYPE_UNSIGNED (length_type)); |
118355a0 | 4076 | |
84b8030f | 4077 | result = emit_library_call_value (libfunc, 0, LCT_PURE, |
118355a0 ZW |
4078 | result_mode, 3, |
4079 | XEXP (x, 0), Pmode, | |
4080 | XEXP (y, 0), Pmode, | |
4081 | size, cmp_mode); | |
f90b7a5a PB |
4082 | |
4083 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx); | |
b30f05db | 4084 | *pmode = result_mode; |
77c9c6c2 RK |
4085 | return; |
4086 | } | |
4087 | ||
27ab3e91 RH |
4088 | /* Don't allow operands to the compare to trap, as that can put the |
4089 | compare and branch in different basic blocks. */ | |
8f4f502f | 4090 | if (cfun->can_throw_non_call_exceptions) |
27ab3e91 RH |
4091 | { |
4092 | if (may_trap_p (x)) | |
4093 | x = force_reg (mode, x); | |
4094 | if (may_trap_p (y)) | |
4095 | y = force_reg (mode, y); | |
4096 | } | |
4097 | ||
4a77c72b PB |
4098 | if (GET_MODE_CLASS (mode) == MODE_CC) |
4099 | { | |
f90b7a5a PB |
4100 | gcc_assert (can_compare_p (comparison, CCmode, ccp_jump)); |
4101 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
4a77c72b PB |
4102 | return; |
4103 | } | |
77c9c6c2 | 4104 | |
f90b7a5a PB |
4105 | mclass = GET_MODE_CLASS (mode); |
4106 | test = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
4107 | cmp_mode = mode; | |
4108 | do | |
4109 | { | |
4110 | enum insn_code icode; | |
947131ba | 4111 | icode = optab_handler (cbranch_optab, cmp_mode); |
f90b7a5a PB |
4112 | if (icode != CODE_FOR_nothing |
4113 | && insn_data[icode].operand[0].predicate (test, VOIDmode)) | |
4114 | { | |
4115 | rtx last = get_last_insn (); | |
4116 | rtx op0 = prepare_operand (icode, x, 1, mode, cmp_mode, unsignedp); | |
4117 | rtx op1 = prepare_operand (icode, y, 2, mode, cmp_mode, unsignedp); | |
4118 | if (op0 && op1 | |
4119 | && insn_data[icode].operand[1].predicate | |
4120 | (op0, insn_data[icode].operand[1].mode) | |
4121 | && insn_data[icode].operand[2].predicate | |
4122 | (op1, insn_data[icode].operand[2].mode)) | |
4123 | { | |
4124 | XEXP (test, 0) = op0; | |
4125 | XEXP (test, 1) = op1; | |
4126 | *ptest = test; | |
4127 | *pmode = cmp_mode; | |
4128 | return; | |
4129 | } | |
4130 | delete_insns_since (last); | |
4131 | } | |
4132 | ||
4133 | if (methods == OPTAB_DIRECT || !CLASS_HAS_WIDER_MODES_P (mclass)) | |
4134 | break; | |
4135 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode); | |
4136 | } | |
4137 | while (cmp_mode != VOIDmode); | |
4138 | ||
4139 | if (methods != OPTAB_LIB_WIDEN) | |
4140 | goto fail; | |
4141 | ||
4142 | if (!SCALAR_FLOAT_MODE_P (mode)) | |
77c9c6c2 | 4143 | { |
9725066d JL |
4144 | rtx result; |
4145 | ||
f90b7a5a PB |
4146 | /* Handle a libcall just for the mode we are using. */ |
4147 | libfunc = optab_libfunc (cmp_optab, mode); | |
4148 | gcc_assert (libfunc); | |
4149 | ||
77c9c6c2 RK |
4150 | /* If we want unsigned, and this mode has a distinct unsigned |
4151 | comparison routine, use that. */ | |
8a33f100 JH |
4152 | if (unsignedp) |
4153 | { | |
ba8a73e9 EB |
4154 | rtx ulibfunc = optab_libfunc (ucmp_optab, mode); |
4155 | if (ulibfunc) | |
4156 | libfunc = ulibfunc; | |
8a33f100 | 4157 | } |
77c9c6c2 | 4158 | |
84b8030f | 4159 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
c7ff6e7a AK |
4160 | targetm.libgcc_cmp_return_mode (), |
4161 | 2, x, mode, y, mode); | |
9725066d | 4162 | |
f34312c2 CD |
4163 | /* There are two kinds of comparison routines. Biased routines |
4164 | return 0/1/2, and unbiased routines return -1/0/1. Other parts | |
4165 | of gcc expect that the comparison operation is equivalent | |
b8698a0f | 4166 | to the modified comparison. For signed comparisons compare the |
f34312c2 CD |
4167 | result against 1 in the biased case, and zero in the unbiased |
4168 | case. For unsigned comparisons always compare against 1 after | |
917f1b7e | 4169 | biasing the unbiased result by adding 1. This gives us a way to |
f34312c2 | 4170 | represent LTU. */ |
f90b7a5a PB |
4171 | x = result; |
4172 | y = const1_rtx; | |
f34312c2 CD |
4173 | |
4174 | if (!TARGET_LIB_INT_CMP_BIASED) | |
b3f8d95d | 4175 | { |
f90b7a5a | 4176 | if (unsignedp) |
b8698a0f | 4177 | x = plus_constant (result, 1); |
f34312c2 | 4178 | else |
f90b7a5a | 4179 | y = const0_rtx; |
b3f8d95d | 4180 | } |
f90b7a5a PB |
4181 | |
4182 | *pmode = word_mode; | |
4183 | prepare_cmp_insn (x, y, comparison, NULL_RTX, unsignedp, methods, | |
4184 | ptest, pmode); | |
77c9c6c2 | 4185 | } |
b8698a0f | 4186 | else |
f90b7a5a | 4187 | prepare_float_lib_cmp (x, y, comparison, ptest, pmode); |
77c9c6c2 | 4188 | |
f90b7a5a PB |
4189 | return; |
4190 | ||
4191 | fail: | |
4192 | *ptest = NULL_RTX; | |
77c9c6c2 RK |
4193 | } |
4194 | ||
b30f05db BS |
4195 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
4196 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
4fe9b91c | 4197 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
b30f05db | 4198 | that it is accepted by the operand predicate. Return the new value. */ |
749a2da1 | 4199 | |
f90b7a5a | 4200 | rtx |
0c20a65f AJ |
4201 | prepare_operand (int icode, rtx x, int opnum, enum machine_mode mode, |
4202 | enum machine_mode wider_mode, int unsignedp) | |
b30f05db | 4203 | { |
b30f05db BS |
4204 | if (mode != wider_mode) |
4205 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
4206 | ||
e3feb571 | 4207 | if (!insn_data[icode].operand[opnum].predicate |
a995e389 | 4208 | (x, insn_data[icode].operand[opnum].mode)) |
d893ccde | 4209 | { |
ef4375b2 | 4210 | if (reload_completed) |
d893ccde RH |
4211 | return NULL_RTX; |
4212 | x = copy_to_mode_reg (insn_data[icode].operand[opnum].mode, x); | |
4213 | } | |
4214 | ||
b30f05db BS |
4215 | return x; |
4216 | } | |
4217 | ||
4218 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
f90b7a5a | 4219 | we can do the branch. */ |
b30f05db BS |
4220 | |
4221 | static void | |
f90b7a5a | 4222 | emit_cmp_and_jump_insn_1 (rtx test, enum machine_mode mode, rtx label) |
b30f05db | 4223 | { |
f90b7a5a PB |
4224 | enum machine_mode optab_mode; |
4225 | enum mode_class mclass; | |
4226 | enum insn_code icode; | |
b30f05db | 4227 | |
f90b7a5a PB |
4228 | mclass = GET_MODE_CLASS (mode); |
4229 | optab_mode = (mclass == MODE_CC) ? CCmode : mode; | |
947131ba | 4230 | icode = optab_handler (cbranch_optab, optab_mode); |
8127d0e0 | 4231 | |
f90b7a5a PB |
4232 | gcc_assert (icode != CODE_FOR_nothing); |
4233 | gcc_assert (insn_data[icode].operand[0].predicate (test, VOIDmode)); | |
4234 | emit_jump_insn (GEN_FCN (icode) (test, XEXP (test, 0), XEXP (test, 1), label)); | |
b30f05db BS |
4235 | } |
4236 | ||
362cc3d4 MH |
4237 | /* Generate code to compare X with Y so that the condition codes are |
4238 | set and to jump to LABEL if the condition is true. If X is a | |
4239 | constant and Y is not a constant, then the comparison is swapped to | |
4240 | ensure that the comparison RTL has the canonical form. | |
4241 | ||
c5d5d461 | 4242 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
f90b7a5a PB |
4243 | need to be widened. UNSIGNEDP is also used to select the proper |
4244 | branch condition code. | |
362cc3d4 | 4245 | |
a06ef755 | 4246 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
362cc3d4 | 4247 | |
c5d5d461 JL |
4248 | MODE is the mode of the inputs (in case they are const_int). |
4249 | ||
f90b7a5a PB |
4250 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). |
4251 | It will be potentially converted into an unsigned variant based on | |
4252 | UNSIGNEDP to select a proper jump instruction. */ | |
362cc3d4 MH |
4253 | |
4254 | void | |
0c20a65f AJ |
4255 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
4256 | enum machine_mode mode, int unsignedp, rtx label) | |
362cc3d4 | 4257 | { |
8c9864f3 | 4258 | rtx op0 = x, op1 = y; |
f90b7a5a | 4259 | rtx test; |
8c9864f3 JH |
4260 | |
4261 | /* Swap operands and condition to ensure canonical RTL. */ | |
45475a3f PB |
4262 | if (swap_commutative_operands_p (x, y) |
4263 | && can_compare_p (swap_condition (comparison), mode, ccp_jump)) | |
362cc3d4 | 4264 | { |
8c9864f3 JH |
4265 | op0 = y, op1 = x; |
4266 | comparison = swap_condition (comparison); | |
362cc3d4 | 4267 | } |
0ca40216 | 4268 | |
45475a3f PB |
4269 | /* If OP0 is still a constant, then both X and Y must be constants |
4270 | or the opposite comparison is not supported. Force X into a register | |
4271 | to create canonical RTL. */ | |
0ca40216 JL |
4272 | if (CONSTANT_P (op0)) |
4273 | op0 = force_reg (mode, op0); | |
0ca40216 | 4274 | |
c5d5d461 JL |
4275 | if (unsignedp) |
4276 | comparison = unsigned_condition (comparison); | |
a06ef755 | 4277 | |
f90b7a5a PB |
4278 | prepare_cmp_insn (op0, op1, comparison, size, unsignedp, OPTAB_LIB_WIDEN, |
4279 | &test, &mode); | |
4280 | emit_cmp_and_jump_insn_1 (test, mode, label); | |
b30f05db BS |
4281 | } |
4282 | ||
77c9c6c2 RK |
4283 | \f |
4284 | /* Emit a library call comparison between floating point X and Y. | |
4285 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
4286 | ||
c5c60e15 | 4287 | static void |
f90b7a5a PB |
4288 | prepare_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison, |
4289 | rtx *ptest, enum machine_mode *pmode) | |
77c9c6c2 | 4290 | { |
c9034561 | 4291 | enum rtx_code swapped = swap_condition (comparison); |
b3f8d95d | 4292 | enum rtx_code reversed = reverse_condition_maybe_unordered (comparison); |
c9034561 | 4293 | enum machine_mode orig_mode = GET_MODE (x); |
7fecf2c7 | 4294 | enum machine_mode mode, cmp_mode; |
6597fd0b | 4295 | rtx true_rtx, false_rtx; |
37bf20ee | 4296 | rtx value, target, insns, equiv; |
0a300065 | 4297 | rtx libfunc = 0; |
b3f8d95d | 4298 | bool reversed_p = false; |
7fecf2c7 | 4299 | cmp_mode = targetm.libgcc_cmp_return_mode (); |
77c9c6c2 | 4300 | |
86556d87 BE |
4301 | for (mode = orig_mode; |
4302 | mode != VOIDmode; | |
4303 | mode = GET_MODE_WIDER_MODE (mode)) | |
77c9c6c2 | 4304 | { |
1bd74ad9 SL |
4305 | if (code_to_optab[comparison] |
4306 | && (libfunc = optab_libfunc (code_to_optab[comparison], mode))) | |
c9034561 | 4307 | break; |
77c9c6c2 | 4308 | |
1bd74ad9 SL |
4309 | if (code_to_optab[swapped] |
4310 | && (libfunc = optab_libfunc (code_to_optab[swapped], mode))) | |
77c9c6c2 | 4311 | { |
c9034561 ZW |
4312 | rtx tmp; |
4313 | tmp = x; x = y; y = tmp; | |
4314 | comparison = swapped; | |
4315 | break; | |
77c9c6c2 | 4316 | } |
77c9c6c2 | 4317 | |
1bd74ad9 | 4318 | if (code_to_optab[reversed] |
6597fd0b | 4319 | && (libfunc = optab_libfunc (code_to_optab[reversed], mode))) |
b3f8d95d MM |
4320 | { |
4321 | comparison = reversed; | |
4322 | reversed_p = true; | |
4323 | break; | |
4324 | } | |
4325 | } | |
5906d013 | 4326 | |
e3feb571 | 4327 | gcc_assert (mode != VOIDmode); |
0a300065 | 4328 | |
c9034561 ZW |
4329 | if (mode != orig_mode) |
4330 | { | |
4331 | x = convert_to_mode (mode, x, 0); | |
4332 | y = convert_to_mode (mode, y, 0); | |
4333 | } | |
4334 | ||
17796a89 RS |
4335 | /* Attach a REG_EQUAL note describing the semantics of the libcall to |
4336 | the RTL. The allows the RTL optimizers to delete the libcall if the | |
4337 | condition can be determined at compile-time. */ | |
6597fd0b PB |
4338 | if (comparison == UNORDERED |
4339 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
4340 | { | |
4341 | true_rtx = const_true_rtx; | |
4342 | false_rtx = const0_rtx; | |
4343 | } | |
4344 | else | |
4345 | { | |
4346 | switch (comparison) | |
4347 | { | |
4348 | case EQ: | |
4349 | true_rtx = const0_rtx; | |
4350 | false_rtx = const_true_rtx; | |
4351 | break; | |
4352 | ||
4353 | case NE: | |
4354 | true_rtx = const_true_rtx; | |
4355 | false_rtx = const0_rtx; | |
4356 | break; | |
4357 | ||
4358 | case GT: | |
4359 | true_rtx = const1_rtx; | |
4360 | false_rtx = const0_rtx; | |
4361 | break; | |
4362 | ||
4363 | case GE: | |
4364 | true_rtx = const0_rtx; | |
4365 | false_rtx = constm1_rtx; | |
4366 | break; | |
4367 | ||
4368 | case LT: | |
4369 | true_rtx = constm1_rtx; | |
4370 | false_rtx = const0_rtx; | |
4371 | break; | |
4372 | ||
4373 | case LE: | |
4374 | true_rtx = const0_rtx; | |
4375 | false_rtx = const1_rtx; | |
4376 | break; | |
4377 | ||
4378 | default: | |
4379 | gcc_unreachable (); | |
4380 | } | |
4381 | } | |
4382 | ||
17796a89 RS |
4383 | if (comparison == UNORDERED) |
4384 | { | |
7fecf2c7 AP |
4385 | rtx temp = simplify_gen_relational (NE, cmp_mode, mode, x, x); |
4386 | equiv = simplify_gen_relational (NE, cmp_mode, mode, y, y); | |
4387 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, | |
17796a89 RS |
4388 | temp, const_true_rtx, equiv); |
4389 | } | |
4390 | else | |
4391 | { | |
7fecf2c7 | 4392 | equiv = simplify_gen_relational (comparison, cmp_mode, mode, x, y); |
17796a89 | 4393 | if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) |
6597fd0b PB |
4394 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, |
4395 | equiv, true_rtx, false_rtx); | |
bd831d5c | 4396 | } |
37bf20ee RS |
4397 | |
4398 | start_sequence (); | |
4399 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, | |
7fecf2c7 | 4400 | cmp_mode, 2, x, mode, y, mode); |
37bf20ee RS |
4401 | insns = get_insns (); |
4402 | end_sequence (); | |
4403 | ||
7fecf2c7 | 4404 | target = gen_reg_rtx (cmp_mode); |
37bf20ee RS |
4405 | emit_libcall_block (insns, target, value, equiv); |
4406 | ||
c9034561 | 4407 | if (comparison == UNORDERED |
6597fd0b PB |
4408 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison) |
4409 | || reversed_p) | |
4410 | *ptest = gen_rtx_fmt_ee (reversed_p ? EQ : NE, VOIDmode, target, false_rtx); | |
4411 | else | |
4412 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, target, const0_rtx); | |
c9034561 | 4413 | |
7fecf2c7 | 4414 | *pmode = cmp_mode; |
77c9c6c2 RK |
4415 | } |
4416 | \f | |
4417 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4418 | ||
4419 | void | |
0c20a65f | 4420 | emit_indirect_jump (rtx loc) |
77c9c6c2 | 4421 | { |
e3feb571 NS |
4422 | if (!insn_data[(int) CODE_FOR_indirect_jump].operand[0].predicate |
4423 | (loc, Pmode)) | |
f2de2775 | 4424 | loc = copy_to_mode_reg (Pmode, loc); |
77c9c6c2 RK |
4425 | |
4426 | emit_jump_insn (gen_indirect_jump (loc)); | |
9649fb4d | 4427 | emit_barrier (); |
77c9c6c2 RK |
4428 | } |
4429 | \f | |
49c4584c DE |
4430 | #ifdef HAVE_conditional_move |
4431 | ||
4432 | /* Emit a conditional move instruction if the machine supports one for that | |
4433 | condition and machine mode. | |
4434 | ||
4435 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4436 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4437 | both be constants. | |
4438 | ||
4439 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4440 | should be stored there. MODE is the mode to use should they be constants. | |
4441 | If it is VOIDmode, they cannot both be constants. | |
4442 | ||
4443 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4444 | is not supported. */ | |
4445 | ||
4446 | rtx | |
0c20a65f AJ |
4447 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4448 | enum machine_mode cmode, rtx op2, rtx op3, | |
4449 | enum machine_mode mode, int unsignedp) | |
49c4584c DE |
4450 | { |
4451 | rtx tem, subtarget, comparison, insn; | |
4452 | enum insn_code icode; | |
e5c56fd9 | 4453 | enum rtx_code reversed; |
49c4584c DE |
4454 | |
4455 | /* If one operand is constant, make it the second one. Only do this | |
4456 | if the other operand is not constant as well. */ | |
4457 | ||
e5c56fd9 | 4458 | if (swap_commutative_operands_p (op0, op1)) |
49c4584c DE |
4459 | { |
4460 | tem = op0; | |
4461 | op0 = op1; | |
4462 | op1 = tem; | |
4463 | code = swap_condition (code); | |
4464 | } | |
4465 | ||
c5c76735 JL |
4466 | /* get_condition will prefer to generate LT and GT even if the old |
4467 | comparison was against zero, so undo that canonicalization here since | |
4468 | comparisons against zero are cheaper. */ | |
87d9741e | 4469 | if (code == LT && op1 == const1_rtx) |
c5c76735 | 4470 | code = LE, op1 = const0_rtx; |
87d9741e | 4471 | else if (code == GT && op1 == constm1_rtx) |
c5c76735 JL |
4472 | code = GE, op1 = const0_rtx; |
4473 | ||
49c4584c DE |
4474 | if (cmode == VOIDmode) |
4475 | cmode = GET_MODE (op0); | |
4476 | ||
e5c56fd9 JH |
4477 | if (swap_commutative_operands_p (op2, op3) |
4478 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4479 | != UNKNOWN)) | |
49c4584c DE |
4480 | { |
4481 | tem = op2; | |
4482 | op2 = op3; | |
4483 | op3 = tem; | |
e5c56fd9 | 4484 | code = reversed; |
49c4584c DE |
4485 | } |
4486 | ||
4487 | if (mode == VOIDmode) | |
4488 | mode = GET_MODE (op2); | |
4489 | ||
f9621cc4 | 4490 | icode = direct_optab_handler (movcc_optab, mode); |
49c4584c DE |
4491 | |
4492 | if (icode == CODE_FOR_nothing) | |
4493 | return 0; | |
4494 | ||
ad76cef8 | 4495 | if (!target) |
49c4584c DE |
4496 | target = gen_reg_rtx (mode); |
4497 | ||
4498 | subtarget = target; | |
4499 | ||
49c4584c DE |
4500 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4501 | ||
e3feb571 | 4502 | if (!insn_data[icode].operand[0].predicate |
a995e389 RH |
4503 | (subtarget, insn_data[icode].operand[0].mode)) |
4504 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
49c4584c | 4505 | |
e3feb571 | 4506 | if (!insn_data[icode].operand[2].predicate |
a995e389 RH |
4507 | (op2, insn_data[icode].operand[2].mode)) |
4508 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
49c4584c | 4509 | |
e3feb571 | 4510 | if (!insn_data[icode].operand[3].predicate |
a995e389 RH |
4511 | (op3, insn_data[icode].operand[3].mode)) |
4512 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
49c4584c | 4513 | |
f90b7a5a | 4514 | /* Everything should now be in the suitable form. */ |
49c4584c | 4515 | |
f90b7a5a PB |
4516 | code = unsignedp ? unsigned_condition (code) : code; |
4517 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
49c4584c | 4518 | |
144a5f9d JL |
4519 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4520 | return NULL and let the caller figure out how best to deal with this | |
4521 | situation. */ | |
f90b7a5a | 4522 | if (!COMPARISON_P (comparison)) |
144a5f9d | 4523 | return NULL_RTX; |
0c20a65f | 4524 | |
f90b7a5a PB |
4525 | do_pending_stack_adjust (); |
4526 | start_sequence (); | |
4527 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), | |
4528 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4529 | &comparison, &cmode); | |
4530 | if (!comparison) | |
4531 | insn = NULL_RTX; | |
4532 | else | |
4533 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); | |
49c4584c DE |
4534 | |
4535 | /* If that failed, then give up. */ | |
4536 | if (insn == 0) | |
f90b7a5a PB |
4537 | { |
4538 | end_sequence (); | |
4539 | return 0; | |
4540 | } | |
49c4584c DE |
4541 | |
4542 | emit_insn (insn); | |
f90b7a5a PB |
4543 | insn = get_insns (); |
4544 | end_sequence (); | |
4545 | emit_insn (insn); | |
49c4584c DE |
4546 | if (subtarget != target) |
4547 | convert_move (target, subtarget, 0); | |
4548 | ||
4549 | return target; | |
4550 | } | |
4551 | ||
40f03658 | 4552 | /* Return nonzero if a conditional move of mode MODE is supported. |
49c4584c DE |
4553 | |
4554 | This function is for combine so it can tell whether an insn that looks | |
4555 | like a conditional move is actually supported by the hardware. If we | |
4556 | guess wrong we lose a bit on optimization, but that's it. */ | |
4557 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4558 | comparisons, and vice versa. How do we handle them? */ | |
4559 | ||
4560 | int | |
0c20a65f | 4561 | can_conditionally_move_p (enum machine_mode mode) |
49c4584c | 4562 | { |
f9621cc4 | 4563 | if (direct_optab_handler (movcc_optab, mode) != CODE_FOR_nothing) |
49c4584c DE |
4564 | return 1; |
4565 | ||
4566 | return 0; | |
4567 | } | |
4568 | ||
4569 | #endif /* HAVE_conditional_move */ | |
068f5dea JH |
4570 | |
4571 | /* Emit a conditional addition instruction if the machine supports one for that | |
4572 | condition and machine mode. | |
4573 | ||
4574 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4575 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4576 | both be constants. | |
4577 | ||
4578 | OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3 | |
4579 | should be stored there. MODE is the mode to use should they be constants. | |
4580 | If it is VOIDmode, they cannot both be constants. | |
4581 | ||
4582 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4583 | is not supported. */ | |
4584 | ||
4585 | rtx | |
0c20a65f AJ |
4586 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4587 | enum machine_mode cmode, rtx op2, rtx op3, | |
4588 | enum machine_mode mode, int unsignedp) | |
068f5dea JH |
4589 | { |
4590 | rtx tem, subtarget, comparison, insn; | |
4591 | enum insn_code icode; | |
4592 | enum rtx_code reversed; | |
4593 | ||
4594 | /* If one operand is constant, make it the second one. Only do this | |
4595 | if the other operand is not constant as well. */ | |
4596 | ||
4597 | if (swap_commutative_operands_p (op0, op1)) | |
4598 | { | |
4599 | tem = op0; | |
4600 | op0 = op1; | |
4601 | op1 = tem; | |
4602 | code = swap_condition (code); | |
4603 | } | |
4604 | ||
4605 | /* get_condition will prefer to generate LT and GT even if the old | |
4606 | comparison was against zero, so undo that canonicalization here since | |
4607 | comparisons against zero are cheaper. */ | |
87d9741e | 4608 | if (code == LT && op1 == const1_rtx) |
068f5dea | 4609 | code = LE, op1 = const0_rtx; |
87d9741e | 4610 | else if (code == GT && op1 == constm1_rtx) |
068f5dea JH |
4611 | code = GE, op1 = const0_rtx; |
4612 | ||
4613 | if (cmode == VOIDmode) | |
4614 | cmode = GET_MODE (op0); | |
4615 | ||
4616 | if (swap_commutative_operands_p (op2, op3) | |
4617 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4618 | != UNKNOWN)) | |
4619 | { | |
4620 | tem = op2; | |
4621 | op2 = op3; | |
4622 | op3 = tem; | |
4623 | code = reversed; | |
4624 | } | |
4625 | ||
4626 | if (mode == VOIDmode) | |
4627 | mode = GET_MODE (op2); | |
4628 | ||
947131ba | 4629 | icode = optab_handler (addcc_optab, mode); |
068f5dea JH |
4630 | |
4631 | if (icode == CODE_FOR_nothing) | |
4632 | return 0; | |
4633 | ||
ad76cef8 | 4634 | if (!target) |
068f5dea JH |
4635 | target = gen_reg_rtx (mode); |
4636 | ||
068f5dea JH |
4637 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4638 | ||
e3feb571 | 4639 | if (!insn_data[icode].operand[0].predicate |
ad76cef8 | 4640 | (target, insn_data[icode].operand[0].mode)) |
068f5dea | 4641 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); |
ad76cef8 PB |
4642 | else |
4643 | subtarget = target; | |
068f5dea | 4644 | |
e3feb571 | 4645 | if (!insn_data[icode].operand[2].predicate |
068f5dea JH |
4646 | (op2, insn_data[icode].operand[2].mode)) |
4647 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
4648 | ||
e3feb571 | 4649 | if (!insn_data[icode].operand[3].predicate |
068f5dea JH |
4650 | (op3, insn_data[icode].operand[3].mode)) |
4651 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
4652 | ||
f90b7a5a | 4653 | /* Everything should now be in the suitable form. */ |
068f5dea | 4654 | |
f90b7a5a PB |
4655 | code = unsignedp ? unsigned_condition (code) : code; |
4656 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
068f5dea | 4657 | |
068f5dea JH |
4658 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4659 | return NULL and let the caller figure out how best to deal with this | |
4660 | situation. */ | |
f90b7a5a | 4661 | if (!COMPARISON_P (comparison)) |
068f5dea | 4662 | return NULL_RTX; |
0c20a65f | 4663 | |
f90b7a5a PB |
4664 | do_pending_stack_adjust (); |
4665 | start_sequence (); | |
4666 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), | |
4667 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4668 | &comparison, &cmode); | |
4669 | if (!comparison) | |
4670 | insn = NULL_RTX; | |
4671 | else | |
4672 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); | |
068f5dea JH |
4673 | |
4674 | /* If that failed, then give up. */ | |
4675 | if (insn == 0) | |
f90b7a5a PB |
4676 | { |
4677 | end_sequence (); | |
4678 | return 0; | |
4679 | } | |
068f5dea JH |
4680 | |
4681 | emit_insn (insn); | |
f90b7a5a PB |
4682 | insn = get_insns (); |
4683 | end_sequence (); | |
4684 | emit_insn (insn); | |
068f5dea JH |
4685 | if (subtarget != target) |
4686 | convert_move (target, subtarget, 0); | |
4687 | ||
4688 | return target; | |
4689 | } | |
49c4584c | 4690 | \f |
0913e4b4 AO |
4691 | /* These functions attempt to generate an insn body, rather than |
4692 | emitting the insn, but if the gen function already emits them, we | |
ad76cef8 | 4693 | make no attempt to turn them back into naked patterns. */ |
77c9c6c2 RK |
4694 | |
4695 | /* Generate and return an insn body to add Y to X. */ | |
4696 | ||
4697 | rtx | |
0c20a65f | 4698 | gen_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4699 | { |
947131ba | 4700 | int icode = (int) optab_handler (add_optab, GET_MODE (x)); |
77c9c6c2 | 4701 | |
e3feb571 NS |
4702 | gcc_assert (insn_data[icode].operand[0].predicate |
4703 | (x, insn_data[icode].operand[0].mode)); | |
4704 | gcc_assert (insn_data[icode].operand[1].predicate | |
4705 | (x, insn_data[icode].operand[1].mode)); | |
4706 | gcc_assert (insn_data[icode].operand[2].predicate | |
4707 | (y, insn_data[icode].operand[2].mode)); | |
77c9c6c2 | 4708 | |
e3feb571 | 4709 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4710 | } |
4711 | ||
e78d8e51 ZW |
4712 | /* Generate and return an insn body to add r1 and c, |
4713 | storing the result in r0. */ | |
8a33f100 | 4714 | |
e78d8e51 | 4715 | rtx |
0c20a65f | 4716 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
e78d8e51 | 4717 | { |
947131ba | 4718 | int icode = (int) optab_handler (add_optab, GET_MODE (r0)); |
e78d8e51 | 4719 | |
7e1a450d | 4720 | if (icode == CODE_FOR_nothing |
e3feb571 NS |
4721 | || !(insn_data[icode].operand[0].predicate |
4722 | (r0, insn_data[icode].operand[0].mode)) | |
4723 | || !(insn_data[icode].operand[1].predicate | |
4724 | (r1, insn_data[icode].operand[1].mode)) | |
4725 | || !(insn_data[icode].operand[2].predicate | |
4726 | (c, insn_data[icode].operand[2].mode))) | |
e78d8e51 ZW |
4727 | return NULL_RTX; |
4728 | ||
e3feb571 | 4729 | return GEN_FCN (icode) (r0, r1, c); |
e78d8e51 ZW |
4730 | } |
4731 | ||
77c9c6c2 | 4732 | int |
0c20a65f | 4733 | have_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4734 | { |
fb7e77d7 TM |
4735 | int icode; |
4736 | ||
e3feb571 | 4737 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4738 | |
947131ba | 4739 | icode = (int) optab_handler (add_optab, GET_MODE (x)); |
fb7e77d7 TM |
4740 | |
4741 | if (icode == CODE_FOR_nothing) | |
4742 | return 0; | |
4743 | ||
e3feb571 NS |
4744 | if (!(insn_data[icode].operand[0].predicate |
4745 | (x, insn_data[icode].operand[0].mode)) | |
4746 | || !(insn_data[icode].operand[1].predicate | |
4747 | (x, insn_data[icode].operand[1].mode)) | |
4748 | || !(insn_data[icode].operand[2].predicate | |
4749 | (y, insn_data[icode].operand[2].mode))) | |
fb7e77d7 TM |
4750 | return 0; |
4751 | ||
4752 | return 1; | |
77c9c6c2 RK |
4753 | } |
4754 | ||
4755 | /* Generate and return an insn body to subtract Y from X. */ | |
4756 | ||
4757 | rtx | |
0c20a65f | 4758 | gen_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4759 | { |
947131ba | 4760 | int icode = (int) optab_handler (sub_optab, GET_MODE (x)); |
77c9c6c2 | 4761 | |
e3feb571 NS |
4762 | gcc_assert (insn_data[icode].operand[0].predicate |
4763 | (x, insn_data[icode].operand[0].mode)); | |
4764 | gcc_assert (insn_data[icode].operand[1].predicate | |
4765 | (x, insn_data[icode].operand[1].mode)); | |
4766 | gcc_assert (insn_data[icode].operand[2].predicate | |
4767 | (y, insn_data[icode].operand[2].mode)); | |
77c9c6c2 | 4768 | |
e3feb571 | 4769 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4770 | } |
4771 | ||
ef89d648 ZW |
4772 | /* Generate and return an insn body to subtract r1 and c, |
4773 | storing the result in r0. */ | |
8a33f100 | 4774 | |
ef89d648 | 4775 | rtx |
0c20a65f | 4776 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ef89d648 | 4777 | { |
947131ba | 4778 | int icode = (int) optab_handler (sub_optab, GET_MODE (r0)); |
ef89d648 | 4779 | |
7e1a450d | 4780 | if (icode == CODE_FOR_nothing |
e3feb571 NS |
4781 | || !(insn_data[icode].operand[0].predicate |
4782 | (r0, insn_data[icode].operand[0].mode)) | |
4783 | || !(insn_data[icode].operand[1].predicate | |
4784 | (r1, insn_data[icode].operand[1].mode)) | |
4785 | || !(insn_data[icode].operand[2].predicate | |
4786 | (c, insn_data[icode].operand[2].mode))) | |
ef89d648 ZW |
4787 | return NULL_RTX; |
4788 | ||
e3feb571 | 4789 | return GEN_FCN (icode) (r0, r1, c); |
ef89d648 ZW |
4790 | } |
4791 | ||
77c9c6c2 | 4792 | int |
0c20a65f | 4793 | have_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4794 | { |
fb7e77d7 TM |
4795 | int icode; |
4796 | ||
e3feb571 | 4797 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4798 | |
947131ba | 4799 | icode = (int) optab_handler (sub_optab, GET_MODE (x)); |
fb7e77d7 TM |
4800 | |
4801 | if (icode == CODE_FOR_nothing) | |
4802 | return 0; | |
4803 | ||
e3feb571 NS |
4804 | if (!(insn_data[icode].operand[0].predicate |
4805 | (x, insn_data[icode].operand[0].mode)) | |
4806 | || !(insn_data[icode].operand[1].predicate | |
4807 | (x, insn_data[icode].operand[1].mode)) | |
4808 | || !(insn_data[icode].operand[2].predicate | |
4809 | (y, insn_data[icode].operand[2].mode))) | |
fb7e77d7 TM |
4810 | return 0; |
4811 | ||
4812 | return 1; | |
77c9c6c2 RK |
4813 | } |
4814 | ||
e3654226 | 4815 | /* Generate the body of an instruction to copy Y into X. |
2f937369 | 4816 | It may be a list of insns, if one insn isn't enough. */ |
77c9c6c2 RK |
4817 | |
4818 | rtx | |
0c20a65f | 4819 | gen_move_insn (rtx x, rtx y) |
77c9c6c2 | 4820 | { |
e3654226 | 4821 | rtx seq; |
77c9c6c2 | 4822 | |
e3654226 RS |
4823 | start_sequence (); |
4824 | emit_move_insn_1 (x, y); | |
2f937369 | 4825 | seq = get_insns (); |
e3654226 RS |
4826 | end_sequence (); |
4827 | return seq; | |
77c9c6c2 RK |
4828 | } |
4829 | \f | |
34e56753 RS |
4830 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4831 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4832 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
77c9c6c2 | 4833 | |
34e56753 | 4834 | enum insn_code |
0c20a65f AJ |
4835 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4836 | int unsignedp) | |
77c9c6c2 | 4837 | { |
85363ca0 | 4838 | convert_optab tab; |
6dd12198 SE |
4839 | #ifdef HAVE_ptr_extend |
4840 | if (unsignedp < 0) | |
4841 | return CODE_FOR_ptr_extend; | |
6dd12198 | 4842 | #endif |
85363ca0 ZW |
4843 | |
4844 | tab = unsignedp ? zext_optab : sext_optab; | |
947131ba | 4845 | return convert_optab_handler (tab, to_mode, from_mode); |
77c9c6c2 RK |
4846 | } |
4847 | ||
4848 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4849 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4850 | ||
4851 | rtx | |
0c20a65f AJ |
4852 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4853 | enum machine_mode mfrom, int unsignedp) | |
77c9c6c2 | 4854 | { |
85363ca0 ZW |
4855 | enum insn_code icode = can_extend_p (mto, mfrom, unsignedp); |
4856 | return GEN_FCN (icode) (x, y); | |
77c9c6c2 | 4857 | } |
77c9c6c2 RK |
4858 | \f |
4859 | /* can_fix_p and can_float_p say whether the target machine | |
4860 | can directly convert a given fixed point type to | |
4861 | a given floating point type, or vice versa. | |
4862 | The returned value is the CODE_FOR_... value to use, | |
5d81dc5b | 4863 | or CODE_FOR_nothing if these modes cannot be directly converted. |
77c9c6c2 | 4864 | |
5d81dc5b | 4865 | *TRUNCP_PTR is set to 1 if it is necessary to output |
77c9c6c2 RK |
4866 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4867 | ||
4868 | static enum insn_code | |
0c20a65f AJ |
4869 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4870 | int unsignedp, int *truncp_ptr) | |
77c9c6c2 | 4871 | { |
85363ca0 ZW |
4872 | convert_optab tab; |
4873 | enum insn_code icode; | |
4874 | ||
4875 | tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab; | |
947131ba | 4876 | icode = convert_optab_handler (tab, fixmode, fltmode); |
85363ca0 ZW |
4877 | if (icode != CODE_FOR_nothing) |
4878 | { | |
4879 | *truncp_ptr = 0; | |
4880 | return icode; | |
4881 | } | |
77c9c6c2 | 4882 | |
0e1d7f32 AH |
4883 | /* FIXME: This requires a port to define both FIX and FTRUNC pattern |
4884 | for this to work. We need to rework the fix* and ftrunc* patterns | |
4885 | and documentation. */ | |
85363ca0 | 4886 | tab = unsignedp ? ufix_optab : sfix_optab; |
947131ba | 4887 | icode = convert_optab_handler (tab, fixmode, fltmode); |
85363ca0 | 4888 | if (icode != CODE_FOR_nothing |
947131ba | 4889 | && optab_handler (ftrunc_optab, fltmode) != CODE_FOR_nothing) |
77c9c6c2 RK |
4890 | { |
4891 | *truncp_ptr = 1; | |
85363ca0 | 4892 | return icode; |
77c9c6c2 | 4893 | } |
85363ca0 ZW |
4894 | |
4895 | *truncp_ptr = 0; | |
77c9c6c2 RK |
4896 | return CODE_FOR_nothing; |
4897 | } | |
4898 | ||
4899 | static enum insn_code | |
0c20a65f AJ |
4900 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4901 | int unsignedp) | |
77c9c6c2 | 4902 | { |
85363ca0 ZW |
4903 | convert_optab tab; |
4904 | ||
4905 | tab = unsignedp ? ufloat_optab : sfloat_optab; | |
947131ba | 4906 | return convert_optab_handler (tab, fltmode, fixmode); |
77c9c6c2 | 4907 | } |
77c9c6c2 RK |
4908 | \f |
4909 | /* Generate code to convert FROM to floating point | |
34e56753 | 4910 | and store in TO. FROM must be fixed point and not VOIDmode. |
77c9c6c2 RK |
4911 | UNSIGNEDP nonzero means regard FROM as unsigned. |
4912 | Normally this is done by correcting the final value | |
4913 | if it is negative. */ | |
4914 | ||
4915 | void | |
0c20a65f | 4916 | expand_float (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4917 | { |
4918 | enum insn_code icode; | |
b3694847 | 4919 | rtx target = to; |
77c9c6c2 | 4920 | enum machine_mode fmode, imode; |
d7735880 | 4921 | bool can_do_signed = false; |
77c9c6c2 | 4922 | |
34e56753 | 4923 | /* Crash now, because we won't be able to decide which mode to use. */ |
e3feb571 | 4924 | gcc_assert (GET_MODE (from) != VOIDmode); |
34e56753 | 4925 | |
77c9c6c2 RK |
4926 | /* Look for an insn to do the conversion. Do it in the specified |
4927 | modes if possible; otherwise convert either input, output or both to | |
4928 | wider mode. If the integer mode is wider than the mode of FROM, | |
4929 | we can do the conversion signed even if the input is unsigned. */ | |
4930 | ||
7bf0a593 AP |
4931 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4932 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4933 | for (imode = GET_MODE (from); imode != VOIDmode; | |
4934 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4935 | { |
4936 | int doing_unsigned = unsignedp; | |
4937 | ||
5ba02ca6 GK |
4938 | if (fmode != GET_MODE (to) |
4939 | && significand_size (fmode) < GET_MODE_BITSIZE (GET_MODE (from))) | |
4940 | continue; | |
4941 | ||
77c9c6c2 | 4942 | icode = can_float_p (fmode, imode, unsignedp); |
d7735880 JM |
4943 | if (icode == CODE_FOR_nothing && unsignedp) |
4944 | { | |
4945 | enum insn_code scode = can_float_p (fmode, imode, 0); | |
4946 | if (scode != CODE_FOR_nothing) | |
4947 | can_do_signed = true; | |
4948 | if (imode != GET_MODE (from)) | |
4949 | icode = scode, doing_unsigned = 0; | |
4950 | } | |
77c9c6c2 RK |
4951 | |
4952 | if (icode != CODE_FOR_nothing) | |
4953 | { | |
77c9c6c2 RK |
4954 | if (imode != GET_MODE (from)) |
4955 | from = convert_to_mode (imode, from, unsignedp); | |
77c9c6c2 RK |
4956 | |
4957 | if (fmode != GET_MODE (to)) | |
4958 | target = gen_reg_rtx (fmode); | |
4959 | ||
4960 | emit_unop_insn (icode, target, from, | |
4961 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
4962 | ||
4963 | if (target != to) | |
4964 | convert_move (to, target, 0); | |
4965 | return; | |
4966 | } | |
7e1a450d | 4967 | } |
77c9c6c2 | 4968 | |
6ef9a246 | 4969 | /* Unsigned integer, and no way to convert directly. Convert as signed, |
cc8d36a1 UB |
4970 | then unconditionally adjust the result. */ |
4971 | if (unsignedp && can_do_signed) | |
77c9c6c2 RK |
4972 | { |
4973 | rtx label = gen_label_rtx (); | |
4974 | rtx temp; | |
4975 | REAL_VALUE_TYPE offset; | |
4976 | ||
c95c47f3 PE |
4977 | /* Look for a usable floating mode FMODE wider than the source and at |
4978 | least as wide as the target. Using FMODE will avoid rounding woes | |
4979 | with unsigned values greater than the signed maximum value. */ | |
70864443 | 4980 | |
c95c47f3 PE |
4981 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4982 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4983 | if (GET_MODE_BITSIZE (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) | |
4984 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) | |
4985 | break; | |
a48fb61b | 4986 | |
c95c47f3 PE |
4987 | if (fmode == VOIDmode) |
4988 | { | |
a48fb61b | 4989 | /* There is no such mode. Pretend the target is wide enough. */ |
c95c47f3 | 4990 | fmode = GET_MODE (to); |
a48fb61b | 4991 | |
0f41302f | 4992 | /* Avoid double-rounding when TO is narrower than FROM. */ |
a48fb61b RK |
4993 | if ((significand_size (fmode) + 1) |
4994 | < GET_MODE_BITSIZE (GET_MODE (from))) | |
4995 | { | |
4996 | rtx temp1; | |
4997 | rtx neglabel = gen_label_rtx (); | |
4998 | ||
0c20a65f | 4999 | /* Don't use TARGET if it isn't a register, is a hard register, |
70864443 | 5000 | or is the wrong mode. */ |
f8cfc6aa | 5001 | if (!REG_P (target) |
70864443 RK |
5002 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
5003 | || GET_MODE (target) != fmode) | |
44f51d4a RK |
5004 | target = gen_reg_rtx (fmode); |
5005 | ||
a48fb61b RK |
5006 | imode = GET_MODE (from); |
5007 | do_pending_stack_adjust (); | |
5008 | ||
5009 | /* Test whether the sign bit is set. */ | |
1c0290ea | 5010 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
a06ef755 | 5011 | 0, neglabel); |
a48fb61b RK |
5012 | |
5013 | /* The sign bit is not set. Convert as signed. */ | |
5014 | expand_float (target, from, 0); | |
5015 | emit_jump_insn (gen_jump (label)); | |
2ad79487 | 5016 | emit_barrier (); |
a48fb61b RK |
5017 | |
5018 | /* The sign bit is set. | |
5019 | Convert to a usable (positive signed) value by shifting right | |
5020 | one bit, while remembering if a nonzero bit was shifted | |
5021 | out; i.e., compute (from & 1) | (from >> 1). */ | |
5022 | ||
5023 | emit_label (neglabel); | |
5024 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
70864443 | 5025 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
73d9a835 RK |
5026 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, integer_one_node, |
5027 | NULL_RTX, 1); | |
0c20a65f | 5028 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
70864443 | 5029 | OPTAB_LIB_WIDEN); |
a48fb61b RK |
5030 | expand_float (target, temp, 0); |
5031 | ||
5032 | /* Multiply by 2 to undo the shift above. */ | |
a93738eb | 5033 | temp = expand_binop (fmode, add_optab, target, target, |
7e1a450d | 5034 | target, 0, OPTAB_LIB_WIDEN); |
a93738eb RK |
5035 | if (temp != target) |
5036 | emit_move_insn (target, temp); | |
5037 | ||
a48fb61b RK |
5038 | do_pending_stack_adjust (); |
5039 | emit_label (label); | |
5040 | goto done; | |
5041 | } | |
c95c47f3 PE |
5042 | } |
5043 | ||
77c9c6c2 RK |
5044 | /* If we are about to do some arithmetic to correct for an |
5045 | unsigned operand, do it in a pseudo-register. */ | |
5046 | ||
c95c47f3 | 5047 | if (GET_MODE (to) != fmode |
f8cfc6aa | 5048 | || !REG_P (to) || REGNO (to) < FIRST_PSEUDO_REGISTER) |
c95c47f3 | 5049 | target = gen_reg_rtx (fmode); |
77c9c6c2 RK |
5050 | |
5051 | /* Convert as signed integer to floating. */ | |
5052 | expand_float (target, from, 0); | |
5053 | ||
5054 | /* If FROM is negative (and therefore TO is negative), | |
5055 | correct its value by 2**bitwidth. */ | |
5056 | ||
5057 | do_pending_stack_adjust (); | |
c5d5d461 | 5058 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 5059 | 0, label); |
70864443 | 5060 | |
0c20a65f | 5061 | |
6ef9a246 | 5062 | real_2expN (&offset, GET_MODE_BITSIZE (GET_MODE (from)), fmode); |
c95c47f3 | 5063 | temp = expand_binop (fmode, add_optab, target, |
30d88916 | 5064 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
77c9c6c2 RK |
5065 | target, 0, OPTAB_LIB_WIDEN); |
5066 | if (temp != target) | |
5067 | emit_move_insn (target, temp); | |
a48fb61b | 5068 | |
77c9c6c2 RK |
5069 | do_pending_stack_adjust (); |
5070 | emit_label (label); | |
70864443 | 5071 | goto done; |
77c9c6c2 | 5072 | } |
77c9c6c2 | 5073 | |
85363ca0 | 5074 | /* No hardware instruction available; call a library routine. */ |
77c9c6c2 | 5075 | { |
85363ca0 | 5076 | rtx libfunc; |
77c9c6c2 | 5077 | rtx insns; |
9a7f678c | 5078 | rtx value; |
85363ca0 | 5079 | convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab; |
77c9c6c2 | 5080 | |
77c9c6c2 RK |
5081 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) |
5082 | from = convert_to_mode (SImode, from, unsignedp); | |
77c9c6c2 | 5083 | |
8a33f100 | 5084 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 5085 | gcc_assert (libfunc); |
77c9c6c2 RK |
5086 | |
5087 | start_sequence (); | |
5088 | ||
85363ca0 | 5089 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
5090 | GET_MODE (to), 1, from, |
5091 | GET_MODE (from)); | |
77c9c6c2 RK |
5092 | insns = get_insns (); |
5093 | end_sequence (); | |
5094 | ||
9a7f678c | 5095 | emit_libcall_block (insns, target, value, |
d1163987 BW |
5096 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FLOAT : FLOAT, |
5097 | GET_MODE (to), from)); | |
77c9c6c2 RK |
5098 | } |
5099 | ||
a48fb61b RK |
5100 | done: |
5101 | ||
77c9c6c2 RK |
5102 | /* Copy result to requested destination |
5103 | if we have been computing in a temp location. */ | |
5104 | ||
5105 | if (target != to) | |
5106 | { | |
5107 | if (GET_MODE (target) == GET_MODE (to)) | |
5108 | emit_move_insn (to, target); | |
5109 | else | |
5110 | convert_move (to, target, 0); | |
5111 | } | |
5112 | } | |
5113 | \f | |
0e1d7f32 AH |
5114 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5115 | must be floating point. */ | |
77c9c6c2 RK |
5116 | |
5117 | void | |
0c20a65f | 5118 | expand_fix (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
5119 | { |
5120 | enum insn_code icode; | |
b3694847 | 5121 | rtx target = to; |
77c9c6c2 RK |
5122 | enum machine_mode fmode, imode; |
5123 | int must_trunc = 0; | |
77c9c6c2 RK |
5124 | |
5125 | /* We first try to find a pair of modes, one real and one integer, at | |
5126 | least as wide as FROM and TO, respectively, in which we can open-code | |
5127 | this conversion. If the integer mode is wider than the mode of TO, | |
5128 | we can do the conversion either signed or unsigned. */ | |
5129 | ||
3987b9db JH |
5130 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5131 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5132 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5133 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
5134 | { |
5135 | int doing_unsigned = unsignedp; | |
5136 | ||
5137 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
5138 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
5139 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
5140 | ||
5141 | if (icode != CODE_FOR_nothing) | |
5142 | { | |
5e04ef8f | 5143 | rtx last = get_last_insn (); |
77c9c6c2 RK |
5144 | if (fmode != GET_MODE (from)) |
5145 | from = convert_to_mode (fmode, from, 0); | |
77c9c6c2 RK |
5146 | |
5147 | if (must_trunc) | |
0e1d7f32 AH |
5148 | { |
5149 | rtx temp = gen_reg_rtx (GET_MODE (from)); | |
5150 | from = expand_unop (GET_MODE (from), ftrunc_optab, from, | |
5151 | temp, 0); | |
5152 | } | |
77c9c6c2 RK |
5153 | |
5154 | if (imode != GET_MODE (to)) | |
5155 | target = gen_reg_rtx (imode); | |
5156 | ||
5e04ef8f JH |
5157 | if (maybe_emit_unop_insn (icode, target, from, |
5158 | doing_unsigned ? UNSIGNED_FIX : FIX)) | |
5159 | { | |
5160 | if (target != to) | |
5161 | convert_move (to, target, unsignedp); | |
5162 | return; | |
5163 | } | |
5164 | delete_insns_since (last); | |
77c9c6c2 RK |
5165 | } |
5166 | } | |
5167 | ||
77c9c6c2 RK |
5168 | /* For an unsigned conversion, there is one more way to do it. |
5169 | If we have a signed conversion, we generate code that compares | |
5170 | the real value to the largest representable positive number. If if | |
5171 | is smaller, the conversion is done normally. Otherwise, subtract | |
5172 | one plus the highest signed number, convert, and add it back. | |
5173 | ||
5174 | We only need to check all real modes, since we know we didn't find | |
0c20a65f | 5175 | anything with a wider integer mode. |
0d446150 JH |
5176 | |
5177 | This code used to extend FP value into mode wider than the destination. | |
6ef9a246 JJ |
5178 | This is needed for decimal float modes which cannot accurately |
5179 | represent one plus the highest signed number of the same size, but | |
5180 | not for binary modes. Consider, for instance conversion from SFmode | |
0d446150 JH |
5181 | into DImode. |
5182 | ||
6fc0bb99 | 5183 | The hot path through the code is dealing with inputs smaller than 2^63 |
0d446150 JH |
5184 | and doing just the conversion, so there is no bits to lose. |
5185 | ||
5186 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
6ef9a246 | 5187 | inclusive. (as for other input overflow happens and result is undefined) |
e0bb17a8 | 5188 | So we know that the most important bit set in mantissa corresponds to |
0d446150 JH |
5189 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
5190 | simply clears out that bit. The rest is trivial. */ | |
77c9c6c2 | 5191 | |
b1ec3c92 | 5192 | if (unsignedp && GET_MODE_BITSIZE (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
77c9c6c2 RK |
5193 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5194 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
6ef9a246 JJ |
5195 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, &must_trunc) |
5196 | && (!DECIMAL_FLOAT_MODE_P (fmode) | |
5197 | || GET_MODE_BITSIZE (fmode) > GET_MODE_BITSIZE (GET_MODE (to)))) | |
77c9c6c2 | 5198 | { |
e9f7ae44 RS |
5199 | int bitsize; |
5200 | REAL_VALUE_TYPE offset; | |
5201 | rtx limit, lab1, lab2, insn; | |
5202 | ||
5203 | bitsize = GET_MODE_BITSIZE (GET_MODE (to)); | |
6ef9a246 | 5204 | real_2expN (&offset, bitsize - 1, fmode); |
30d88916 | 5205 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
e9f7ae44 RS |
5206 | lab1 = gen_label_rtx (); |
5207 | lab2 = gen_label_rtx (); | |
77c9c6c2 | 5208 | |
77c9c6c2 RK |
5209 | if (fmode != GET_MODE (from)) |
5210 | from = convert_to_mode (fmode, from, 0); | |
5211 | ||
5212 | /* See if we need to do the subtraction. */ | |
5213 | do_pending_stack_adjust (); | |
c5d5d461 | 5214 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 5215 | 0, lab1); |
77c9c6c2 RK |
5216 | |
5217 | /* If not, do the signed "fix" and branch around fixup code. */ | |
5218 | expand_fix (to, from, 0); | |
5219 | emit_jump_insn (gen_jump (lab2)); | |
5220 | emit_barrier (); | |
5221 | ||
5222 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
5223 | then add 2**(N-1). Do the addition using XOR since this | |
5224 | will often generate better code. */ | |
5225 | emit_label (lab1); | |
5226 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
b1ec3c92 | 5227 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
77c9c6c2 RK |
5228 | expand_fix (to, target, 0); |
5229 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2496c7bd LB |
5230 | gen_int_mode |
5231 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
5232 | GET_MODE (to)), | |
77c9c6c2 RK |
5233 | to, 1, OPTAB_LIB_WIDEN); |
5234 | ||
5235 | if (target != to) | |
5236 | emit_move_insn (to, target); | |
5237 | ||
5238 | emit_label (lab2); | |
5239 | ||
947131ba | 5240 | if (optab_handler (mov_optab, GET_MODE (to)) != CODE_FOR_nothing) |
02214a5c RK |
5241 | { |
5242 | /* Make a place for a REG_NOTE and add it. */ | |
5243 | insn = emit_move_insn (to, to); | |
5fa671cf AM |
5244 | set_unique_reg_note (insn, |
5245 | REG_EQUAL, | |
5246 | gen_rtx_fmt_e (UNSIGNED_FIX, | |
5247 | GET_MODE (to), | |
5248 | copy_rtx (from))); | |
02214a5c | 5249 | } |
c5c76735 | 5250 | |
77c9c6c2 RK |
5251 | return; |
5252 | } | |
77c9c6c2 RK |
5253 | |
5254 | /* We can't do it with an insn, so use a library call. But first ensure | |
5255 | that the mode of TO is at least as wide as SImode, since those are the | |
5256 | only library calls we know about. */ | |
5257 | ||
5258 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
5259 | { | |
5260 | target = gen_reg_rtx (SImode); | |
5261 | ||
5262 | expand_fix (target, from, unsignedp); | |
5263 | } | |
77c9c6c2 | 5264 | else |
77c9c6c2 RK |
5265 | { |
5266 | rtx insns; | |
560f3f8a | 5267 | rtx value; |
85363ca0 | 5268 | rtx libfunc; |
5906d013 | 5269 | |
85363ca0 | 5270 | convert_optab tab = unsignedp ? ufix_optab : sfix_optab; |
8a33f100 | 5271 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 5272 | gcc_assert (libfunc); |
77c9c6c2 | 5273 | |
77c9c6c2 RK |
5274 | start_sequence (); |
5275 | ||
85363ca0 | 5276 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
5277 | GET_MODE (to), 1, from, |
5278 | GET_MODE (from)); | |
77c9c6c2 RK |
5279 | insns = get_insns (); |
5280 | end_sequence (); | |
5281 | ||
560f3f8a | 5282 | emit_libcall_block (insns, target, value, |
9e6a5703 JC |
5283 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
5284 | GET_MODE (to), from)); | |
77c9c6c2 | 5285 | } |
0c20a65f | 5286 | |
3e53ea48 RK |
5287 | if (target != to) |
5288 | { | |
5289 | if (GET_MODE (to) == GET_MODE (target)) | |
5290 | emit_move_insn (to, target); | |
5291 | else | |
5292 | convert_move (to, target, 0); | |
5293 | } | |
77c9c6c2 | 5294 | } |
bb7f0423 | 5295 | |
0f996086 CF |
5296 | /* Generate code to convert FROM or TO a fixed-point. |
5297 | If UINTP is true, either TO or FROM is an unsigned integer. | |
5298 | If SATP is true, we need to saturate the result. */ | |
5299 | ||
5300 | void | |
5301 | expand_fixed_convert (rtx to, rtx from, int uintp, int satp) | |
5302 | { | |
5303 | enum machine_mode to_mode = GET_MODE (to); | |
5304 | enum machine_mode from_mode = GET_MODE (from); | |
5305 | convert_optab tab; | |
5306 | enum rtx_code this_code; | |
5307 | enum insn_code code; | |
5308 | rtx insns, value; | |
5309 | rtx libfunc; | |
5310 | ||
5311 | if (to_mode == from_mode) | |
5312 | { | |
5313 | emit_move_insn (to, from); | |
5314 | return; | |
5315 | } | |
5316 | ||
5317 | if (uintp) | |
5318 | { | |
5319 | tab = satp ? satfractuns_optab : fractuns_optab; | |
5320 | this_code = satp ? UNSIGNED_SAT_FRACT : UNSIGNED_FRACT_CONVERT; | |
5321 | } | |
5322 | else | |
5323 | { | |
5324 | tab = satp ? satfract_optab : fract_optab; | |
5325 | this_code = satp ? SAT_FRACT : FRACT_CONVERT; | |
5326 | } | |
947131ba | 5327 | code = convert_optab_handler (tab, to_mode, from_mode); |
0f996086 CF |
5328 | if (code != CODE_FOR_nothing) |
5329 | { | |
5330 | emit_unop_insn (code, to, from, this_code); | |
5331 | return; | |
5332 | } | |
5333 | ||
5334 | libfunc = convert_optab_libfunc (tab, to_mode, from_mode); | |
5335 | gcc_assert (libfunc); | |
5336 | ||
5337 | start_sequence (); | |
5338 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, to_mode, | |
5339 | 1, from, from_mode); | |
5340 | insns = get_insns (); | |
5341 | end_sequence (); | |
5342 | ||
5343 | emit_libcall_block (insns, to, value, | |
5344 | gen_rtx_fmt_e (tab->code, to_mode, from)); | |
5345 | } | |
5346 | ||
bb7f0423 RG |
5347 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5348 | must be floating point, TO must be signed. Use the conversion optab | |
5349 | TAB to do the conversion. */ | |
5350 | ||
5351 | bool | |
5352 | expand_sfix_optab (rtx to, rtx from, convert_optab tab) | |
5353 | { | |
5354 | enum insn_code icode; | |
5355 | rtx target = to; | |
5356 | enum machine_mode fmode, imode; | |
5357 | ||
5358 | /* We first try to find a pair of modes, one real and one integer, at | |
5359 | least as wide as FROM and TO, respectively, in which we can open-code | |
5360 | this conversion. If the integer mode is wider than the mode of TO, | |
5361 | we can do the conversion either signed or unsigned. */ | |
5362 | ||
5363 | for (fmode = GET_MODE (from); fmode != VOIDmode; | |
5364 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5365 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5366 | imode = GET_MODE_WIDER_MODE (imode)) | |
5367 | { | |
947131ba | 5368 | icode = convert_optab_handler (tab, imode, fmode); |
bb7f0423 RG |
5369 | if (icode != CODE_FOR_nothing) |
5370 | { | |
5e04ef8f | 5371 | rtx last = get_last_insn (); |
bb7f0423 RG |
5372 | if (fmode != GET_MODE (from)) |
5373 | from = convert_to_mode (fmode, from, 0); | |
5374 | ||
5375 | if (imode != GET_MODE (to)) | |
5376 | target = gen_reg_rtx (imode); | |
5377 | ||
18bd082d | 5378 | if (!maybe_emit_unop_insn (icode, target, from, UNKNOWN)) |
5e04ef8f JH |
5379 | { |
5380 | delete_insns_since (last); | |
5381 | continue; | |
5382 | } | |
bb7f0423 RG |
5383 | if (target != to) |
5384 | convert_move (to, target, 0); | |
5385 | return true; | |
5386 | } | |
5387 | } | |
5388 | ||
5389 | return false; | |
5390 | } | |
77c9c6c2 | 5391 | \f |
ef89d648 ZW |
5392 | /* Report whether we have an instruction to perform the operation |
5393 | specified by CODE on operands of mode MODE. */ | |
5394 | int | |
0c20a65f | 5395 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ef89d648 ZW |
5396 | { |
5397 | return (code_to_optab[(int) code] != 0 | |
947131ba | 5398 | && (optab_handler (code_to_optab[(int) code], mode) |
ef89d648 ZW |
5399 | != CODE_FOR_nothing)); |
5400 | } | |
5401 | ||
c0742514 JJ |
5402 | /* Set all insn_code fields to CODE_FOR_nothing. */ |
5403 | ||
33727b5e | 5404 | static void |
c0742514 | 5405 | init_insn_codes (void) |
85363ca0 | 5406 | { |
596455ce RS |
5407 | memset (optab_table, 0, sizeof (optab_table)); |
5408 | memset (convert_optab_table, 0, sizeof (convert_optab_table)); | |
f9621cc4 | 5409 | memset (direct_optab_table, 0, sizeof (direct_optab_table)); |
85363ca0 ZW |
5410 | } |
5411 | ||
c0742514 | 5412 | /* Initialize OP's code to CODE, and write it into the code_to_optab table. */ |
33727b5e JJ |
5413 | static inline void |
5414 | init_optab (optab op, enum rtx_code code) | |
ef89d648 | 5415 | { |
ef89d648 ZW |
5416 | op->code = code; |
5417 | code_to_optab[(int) code] = op; | |
ef89d648 ZW |
5418 | } |
5419 | ||
5420 | /* Same, but fill in its code as CODE, and do _not_ write it into | |
5421 | the code_to_optab table. */ | |
33727b5e JJ |
5422 | static inline void |
5423 | init_optabv (optab op, enum rtx_code code) | |
ef89d648 | 5424 | { |
ef89d648 | 5425 | op->code = code; |
77c9c6c2 RK |
5426 | } |
5427 | ||
85363ca0 | 5428 | /* Conversion optabs never go in the code_to_optab table. */ |
33727b5e JJ |
5429 | static void |
5430 | init_convert_optab (convert_optab op, enum rtx_code code) | |
85363ca0 | 5431 | { |
85363ca0 | 5432 | op->code = code; |
85363ca0 ZW |
5433 | } |
5434 | ||
b092b471 JW |
5435 | /* Initialize the libfunc fields of an entire group of entries in some |
5436 | optab. Each entry is set equal to a string consisting of a leading | |
5437 | pair of underscores followed by a generic operation name followed by | |
7ef0daad | 5438 | a mode name (downshifted to lowercase) followed by a single character |
b092b471 JW |
5439 | representing the number of operands for the given operation (which is |
5440 | usually one of the characters '2', '3', or '4'). | |
5441 | ||
5442 | OPTABLE is the table in which libfunc fields are to be initialized. | |
b092b471 JW |
5443 | OPNAME is the generic (string) name of the operation. |
5444 | SUFFIX is the character which specifies the number of operands for | |
5445 | the given generic operation. | |
8a33f100 | 5446 | MODE is the mode to generate for. |
b092b471 JW |
5447 | */ |
5448 | ||
5449 | static void | |
8a33f100 | 5450 | gen_libfunc (optab optable, const char *opname, int suffix, enum machine_mode mode) |
b092b471 | 5451 | { |
b3694847 | 5452 | unsigned opname_len = strlen (opname); |
8a33f100 JH |
5453 | const char *mname = GET_MODE_NAME (mode); |
5454 | unsigned mname_len = strlen (mname); | |
d3bfe4de | 5455 | char *libfunc_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
8a33f100 JH |
5456 | char *p; |
5457 | const char *q; | |
b092b471 | 5458 | |
8a33f100 JH |
5459 | p = libfunc_name; |
5460 | *p++ = '_'; | |
5461 | *p++ = '_'; | |
5462 | for (q = opname; *q; ) | |
5463 | *p++ = *q++; | |
5464 | for (q = mname; *q; q++) | |
5465 | *p++ = TOLOWER (*q); | |
5466 | *p++ = suffix; | |
5467 | *p = '\0'; | |
5468 | ||
5469 | set_optab_libfunc (optable, mode, | |
5470 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
b092b471 JW |
5471 | } |
5472 | ||
8a33f100 | 5473 | /* Like gen_libfunc, but verify that integer operation is involved. */ |
b092b471 JW |
5474 | |
5475 | static void | |
8a33f100 JH |
5476 | gen_int_libfunc (optab optable, const char *opname, char suffix, |
5477 | enum machine_mode mode) | |
b092b471 | 5478 | { |
8a33f100 JH |
5479 | int maxsize = 2 * BITS_PER_WORD; |
5480 | ||
5481 | if (GET_MODE_CLASS (mode) != MODE_INT) | |
5482 | return; | |
c0510d84 DD |
5483 | if (maxsize < LONG_LONG_TYPE_SIZE) |
5484 | maxsize = LONG_LONG_TYPE_SIZE; | |
8a33f100 JH |
5485 | if (GET_MODE_CLASS (mode) != MODE_INT |
5486 | || mode < word_mode || GET_MODE_BITSIZE (mode) > maxsize) | |
5487 | return; | |
5488 | gen_libfunc (optable, opname, suffix, mode); | |
b092b471 JW |
5489 | } |
5490 | ||
8a33f100 | 5491 | /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */ |
b092b471 JW |
5492 | |
5493 | static void | |
8a33f100 JH |
5494 | gen_fp_libfunc (optab optable, const char *opname, char suffix, |
5495 | enum machine_mode mode) | |
b092b471 | 5496 | { |
8a33f100 | 5497 | char *dec_opname; |
79b87c74 | 5498 | |
8a33f100 JH |
5499 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
5500 | gen_libfunc (optable, opname, suffix, mode); | |
5501 | if (DECIMAL_FLOAT_MODE_P (mode)) | |
5502 | { | |
d3bfe4de | 5503 | dec_opname = XALLOCAVEC (char, sizeof (DECIMAL_PREFIX) + strlen (opname)); |
8a33f100 JH |
5504 | /* For BID support, change the name to have either a bid_ or dpd_ prefix |
5505 | depending on the low level floating format used. */ | |
5506 | memcpy (dec_opname, DECIMAL_PREFIX, sizeof (DECIMAL_PREFIX) - 1); | |
5507 | strcpy (dec_opname + sizeof (DECIMAL_PREFIX) - 1, opname); | |
5508 | gen_libfunc (optable, dec_opname, suffix, mode); | |
5509 | } | |
5510 | } | |
79b87c74 | 5511 | |
0f996086 CF |
5512 | /* Like gen_libfunc, but verify that fixed-point operation is involved. */ |
5513 | ||
5514 | static void | |
5515 | gen_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5516 | enum machine_mode mode) | |
5517 | { | |
5518 | if (!ALL_FIXED_POINT_MODE_P (mode)) | |
5519 | return; | |
5520 | gen_libfunc (optable, opname, suffix, mode); | |
5521 | } | |
5522 | ||
5523 | /* Like gen_libfunc, but verify that signed fixed-point operation is | |
5524 | involved. */ | |
5525 | ||
5526 | static void | |
5527 | gen_signed_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5528 | enum machine_mode mode) | |
5529 | { | |
5530 | if (!SIGNED_FIXED_POINT_MODE_P (mode)) | |
5531 | return; | |
5532 | gen_libfunc (optable, opname, suffix, mode); | |
5533 | } | |
5534 | ||
5535 | /* Like gen_libfunc, but verify that unsigned fixed-point operation is | |
5536 | involved. */ | |
5537 | ||
5538 | static void | |
5539 | gen_unsigned_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5540 | enum machine_mode mode) | |
5541 | { | |
5542 | if (!UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5543 | return; | |
5544 | gen_libfunc (optable, opname, suffix, mode); | |
5545 | } | |
5546 | ||
8a33f100 JH |
5547 | /* Like gen_libfunc, but verify that FP or INT operation is involved. */ |
5548 | ||
5549 | static void | |
5550 | gen_int_fp_libfunc (optab optable, const char *name, char suffix, | |
5551 | enum machine_mode mode) | |
5552 | { | |
5553 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5554 | gen_fp_libfunc (optable, name, suffix, mode); | |
5555 | if (INTEGRAL_MODE_P (mode)) | |
5556 | gen_int_libfunc (optable, name, suffix, mode); | |
5557 | } | |
5558 | ||
5559 | /* Like gen_libfunc, but verify that FP or INT operation is involved | |
5560 | and add 'v' suffix for integer operation. */ | |
5561 | ||
5562 | static void | |
5563 | gen_intv_fp_libfunc (optab optable, const char *name, char suffix, | |
5564 | enum machine_mode mode) | |
5565 | { | |
5566 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5567 | gen_fp_libfunc (optable, name, suffix, mode); | |
5568 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
5569 | { | |
5570 | int len = strlen (name); | |
d3bfe4de | 5571 | char *v_name = XALLOCAVEC (char, len + 2); |
8a33f100 JH |
5572 | strcpy (v_name, name); |
5573 | v_name[len] = 'v'; | |
5574 | v_name[len + 1] = 0; | |
5575 | gen_int_libfunc (optable, v_name, suffix, mode); | |
5576 | } | |
b092b471 JW |
5577 | } |
5578 | ||
0f996086 CF |
5579 | /* Like gen_libfunc, but verify that FP or INT or FIXED operation is |
5580 | involved. */ | |
5581 | ||
5582 | static void | |
5583 | gen_int_fp_fixed_libfunc (optab optable, const char *name, char suffix, | |
5584 | enum machine_mode mode) | |
5585 | { | |
5586 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5587 | gen_fp_libfunc (optable, name, suffix, mode); | |
5588 | if (INTEGRAL_MODE_P (mode)) | |
5589 | gen_int_libfunc (optable, name, suffix, mode); | |
5590 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5591 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5592 | } | |
5593 | ||
5594 | /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is | |
5595 | involved. */ | |
5596 | ||
5597 | static void | |
5598 | gen_int_fp_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5599 | enum machine_mode mode) | |
5600 | { | |
5601 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5602 | gen_fp_libfunc (optable, name, suffix, mode); | |
5603 | if (INTEGRAL_MODE_P (mode)) | |
5604 | gen_int_libfunc (optable, name, suffix, mode); | |
5605 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5606 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5607 | } | |
5608 | ||
5609 | /* Like gen_libfunc, but verify that INT or FIXED operation is | |
5610 | involved. */ | |
5611 | ||
5612 | static void | |
5613 | gen_int_fixed_libfunc (optab optable, const char *name, char suffix, | |
5614 | enum machine_mode mode) | |
5615 | { | |
5616 | if (INTEGRAL_MODE_P (mode)) | |
5617 | gen_int_libfunc (optable, name, suffix, mode); | |
5618 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5619 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5620 | } | |
5621 | ||
5622 | /* Like gen_libfunc, but verify that INT or signed FIXED operation is | |
5623 | involved. */ | |
5624 | ||
5625 | static void | |
5626 | gen_int_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5627 | enum machine_mode mode) | |
5628 | { | |
5629 | if (INTEGRAL_MODE_P (mode)) | |
5630 | gen_int_libfunc (optable, name, suffix, mode); | |
5631 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5632 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5633 | } | |
5634 | ||
5635 | /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is | |
5636 | involved. */ | |
5637 | ||
5638 | static void | |
5639 | gen_int_unsigned_fixed_libfunc (optab optable, const char *name, char suffix, | |
5640 | enum machine_mode mode) | |
5641 | { | |
5642 | if (INTEGRAL_MODE_P (mode)) | |
5643 | gen_int_libfunc (optable, name, suffix, mode); | |
5644 | if (UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5645 | gen_unsigned_fixed_libfunc (optable, name, suffix, mode); | |
5646 | } | |
5647 | ||
85363ca0 ZW |
5648 | /* Initialize the libfunc fields of an entire group of entries of an |
5649 | inter-mode-class conversion optab. The string formation rules are | |
5650 | similar to the ones for init_libfuncs, above, but instead of having | |
5651 | a mode name and an operand count these functions have two mode names | |
5652 | and no operand count. */ | |
8a33f100 | 5653 | |
85363ca0 | 5654 | static void |
8a33f100 JH |
5655 | gen_interclass_conv_libfunc (convert_optab tab, |
5656 | const char *opname, | |
5657 | enum machine_mode tmode, | |
5658 | enum machine_mode fmode) | |
85363ca0 | 5659 | { |
85363ca0 | 5660 | size_t opname_len = strlen (opname); |
8a33f100 | 5661 | size_t mname_len = 0; |
85363ca0 | 5662 | |
85363ca0 ZW |
5663 | const char *fname, *tname; |
5664 | const char *q; | |
5665 | char *libfunc_name, *suffix; | |
79b87c74 | 5666 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5667 | char *p; |
5668 | ||
79b87c74 MM |
5669 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5670 | depends on which underlying decimal floating point format is used. */ | |
5671 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5672 | ||
8a33f100 | 5673 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5674 | |
d3bfe4de | 5675 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5676 | nondec_name[0] = '_'; |
5677 | nondec_name[1] = '_'; | |
5678 | memcpy (&nondec_name[2], opname, opname_len); | |
5679 | nondec_suffix = nondec_name + opname_len + 2; | |
5680 | ||
d3bfe4de | 5681 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5682 | dec_name[0] = '_'; |
5683 | dec_name[1] = '_'; | |
5684 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5685 | memcpy (&dec_name[2+dec_len], opname, opname_len); | |
5686 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5687 | |
8a33f100 JH |
5688 | fname = GET_MODE_NAME (fmode); |
5689 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5690 | |
8a33f100 JH |
5691 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5692 | { | |
5693 | libfunc_name = dec_name; | |
5694 | suffix = dec_suffix; | |
5695 | } | |
5696 | else | |
5697 | { | |
5698 | libfunc_name = nondec_name; | |
5699 | suffix = nondec_suffix; | |
5700 | } | |
79b87c74 | 5701 | |
8a33f100 JH |
5702 | p = suffix; |
5703 | for (q = fname; *q; p++, q++) | |
5704 | *p = TOLOWER (*q); | |
5705 | for (q = tname; *q; p++, q++) | |
5706 | *p = TOLOWER (*q); | |
85363ca0 | 5707 | |
8a33f100 | 5708 | *p = '\0'; |
85363ca0 | 5709 | |
8a33f100 JH |
5710 | set_conv_libfunc (tab, tmode, fmode, |
5711 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5712 | } |
5713 | ||
8a33f100 JH |
5714 | /* Same as gen_interclass_conv_libfunc but verify that we are producing |
5715 | int->fp conversion. */ | |
5716 | ||
85363ca0 | 5717 | static void |
8a33f100 JH |
5718 | gen_int_to_fp_conv_libfunc (convert_optab tab, |
5719 | const char *opname, | |
5720 | enum machine_mode tmode, | |
5721 | enum machine_mode fmode) | |
5722 | { | |
5723 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5724 | return; | |
5725 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5726 | return; | |
5727 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5728 | } | |
5729 | ||
5730 | /* ufloat_optab is special by using floatun for FP and floatuns decimal fp | |
5731 | naming scheme. */ | |
5732 | ||
5733 | static void | |
5734 | gen_ufloat_conv_libfunc (convert_optab tab, | |
5735 | const char *opname ATTRIBUTE_UNUSED, | |
5736 | enum machine_mode tmode, | |
5737 | enum machine_mode fmode) | |
5738 | { | |
5739 | if (DECIMAL_FLOAT_MODE_P (tmode)) | |
5740 | gen_int_to_fp_conv_libfunc (tab, "floatuns", tmode, fmode); | |
5741 | else | |
5742 | gen_int_to_fp_conv_libfunc (tab, "floatun", tmode, fmode); | |
5743 | } | |
5744 | ||
5745 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5746 | fp->int conversion. */ | |
5747 | ||
5748 | static void | |
5749 | gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab, | |
5750 | const char *opname, | |
5751 | enum machine_mode tmode, | |
5752 | enum machine_mode fmode) | |
5753 | { | |
5754 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5755 | return; | |
5756 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT) | |
5757 | return; | |
5758 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5759 | } | |
5760 | ||
5761 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5762 | fp->int conversion with no decimal floating point involved. */ | |
5763 | ||
5764 | static void | |
5765 | gen_fp_to_int_conv_libfunc (convert_optab tab, | |
5766 | const char *opname, | |
5767 | enum machine_mode tmode, | |
5768 | enum machine_mode fmode) | |
5769 | { | |
5770 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5771 | return; | |
5772 | if (GET_MODE_CLASS (tmode) != MODE_INT) | |
5773 | return; | |
5774 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5775 | } | |
5776 | ||
fa10beec | 5777 | /* Initialize the libfunc fields of an of an intra-mode-class conversion optab. |
8a33f100 JH |
5778 | The string formation rules are |
5779 | similar to the ones for init_libfunc, above. */ | |
5780 | ||
5781 | static void | |
5782 | gen_intraclass_conv_libfunc (convert_optab tab, const char *opname, | |
5783 | enum machine_mode tmode, enum machine_mode fmode) | |
85363ca0 | 5784 | { |
85363ca0 | 5785 | size_t opname_len = strlen (opname); |
8a33f100 | 5786 | size_t mname_len = 0; |
85363ca0 | 5787 | |
8a33f100 | 5788 | const char *fname, *tname; |
85363ca0 | 5789 | const char *q; |
79b87c74 | 5790 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5791 | char *libfunc_name, *suffix; |
5792 | char *p; | |
5793 | ||
79b87c74 MM |
5794 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5795 | depends on which underlying decimal floating point format is used. */ | |
5796 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5797 | ||
8a33f100 | 5798 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5799 | |
d3bfe4de | 5800 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5801 | nondec_name[0] = '_'; |
5802 | nondec_name[1] = '_'; | |
5803 | memcpy (&nondec_name[2], opname, opname_len); | |
5804 | nondec_suffix = nondec_name + opname_len + 2; | |
5805 | ||
d3bfe4de | 5806 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5807 | dec_name[0] = '_'; |
5808 | dec_name[1] = '_'; | |
5809 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5810 | memcpy (&dec_name[2 + dec_len], opname, opname_len); | |
5811 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5812 | |
8a33f100 JH |
5813 | fname = GET_MODE_NAME (fmode); |
5814 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5815 | |
8a33f100 JH |
5816 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5817 | { | |
5818 | libfunc_name = dec_name; | |
5819 | suffix = dec_suffix; | |
5820 | } | |
5821 | else | |
5822 | { | |
5823 | libfunc_name = nondec_name; | |
5824 | suffix = nondec_suffix; | |
5825 | } | |
79b87c74 | 5826 | |
8a33f100 JH |
5827 | p = suffix; |
5828 | for (q = fname; *q; p++, q++) | |
5829 | *p = TOLOWER (*q); | |
5830 | for (q = tname; *q; p++, q++) | |
5831 | *p = TOLOWER (*q); | |
85363ca0 | 5832 | |
8a33f100 JH |
5833 | *p++ = '2'; |
5834 | *p = '\0'; | |
85363ca0 | 5835 | |
8a33f100 JH |
5836 | set_conv_libfunc (tab, tmode, fmode, |
5837 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5838 | } |
5839 | ||
8a33f100 JH |
5840 | /* Pick proper libcall for trunc_optab. We need to chose if we do |
5841 | truncation or extension and interclass or intraclass. */ | |
5842 | ||
5843 | static void | |
5844 | gen_trunc_conv_libfunc (convert_optab tab, | |
5845 | const char *opname, | |
5846 | enum machine_mode tmode, | |
5847 | enum machine_mode fmode) | |
5848 | { | |
5849 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5850 | return; | |
5851 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5852 | return; | |
5853 | if (tmode == fmode) | |
5854 | return; | |
5855 | ||
5856 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5857 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5858 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
b8698a0f | 5859 | |
8a33f100 JH |
5860 | if (GET_MODE_PRECISION (fmode) <= GET_MODE_PRECISION (tmode)) |
5861 | return; | |
5862 | ||
5863 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5864 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5865 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5866 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5867 | } | |
5868 | ||
5869 | /* Pick proper libcall for extend_optab. We need to chose if we do | |
5870 | truncation or extension and interclass or intraclass. */ | |
5871 | ||
5872 | static void | |
5873 | gen_extend_conv_libfunc (convert_optab tab, | |
5874 | const char *opname ATTRIBUTE_UNUSED, | |
5875 | enum machine_mode tmode, | |
5876 | enum machine_mode fmode) | |
5877 | { | |
5878 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5879 | return; | |
5880 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5881 | return; | |
5882 | if (tmode == fmode) | |
5883 | return; | |
5884 | ||
5885 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5886 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5887 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
b8698a0f | 5888 | |
8a33f100 JH |
5889 | if (GET_MODE_PRECISION (fmode) > GET_MODE_PRECISION (tmode)) |
5890 | return; | |
5891 | ||
5892 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5893 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5894 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5895 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5896 | } | |
85363ca0 | 5897 | |
0f996086 CF |
5898 | /* Pick proper libcall for fract_optab. We need to chose if we do |
5899 | interclass or intraclass. */ | |
5900 | ||
5901 | static void | |
5902 | gen_fract_conv_libfunc (convert_optab tab, | |
5903 | const char *opname, | |
5904 | enum machine_mode tmode, | |
5905 | enum machine_mode fmode) | |
5906 | { | |
5907 | if (tmode == fmode) | |
5908 | return; | |
5909 | if (!(ALL_FIXED_POINT_MODE_P (tmode) || ALL_FIXED_POINT_MODE_P (fmode))) | |
5910 | return; | |
5911 | ||
5912 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5913 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5914 | else | |
5915 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5916 | } | |
5917 | ||
5918 | /* Pick proper libcall for fractuns_optab. */ | |
5919 | ||
5920 | static void | |
5921 | gen_fractuns_conv_libfunc (convert_optab tab, | |
5922 | const char *opname, | |
5923 | enum machine_mode tmode, | |
5924 | enum machine_mode fmode) | |
5925 | { | |
5926 | if (tmode == fmode) | |
5927 | return; | |
5928 | /* One mode must be a fixed-point mode, and the other must be an integer | |
5929 | mode. */ | |
5930 | if (!((ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT) | |
5931 | || (ALL_FIXED_POINT_MODE_P (fmode) | |
5932 | && GET_MODE_CLASS (tmode) == MODE_INT))) | |
5933 | return; | |
5934 | ||
5935 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5936 | } | |
5937 | ||
5938 | /* Pick proper libcall for satfract_optab. We need to chose if we do | |
5939 | interclass or intraclass. */ | |
5940 | ||
5941 | static void | |
5942 | gen_satfract_conv_libfunc (convert_optab tab, | |
5943 | const char *opname, | |
5944 | enum machine_mode tmode, | |
5945 | enum machine_mode fmode) | |
5946 | { | |
5947 | if (tmode == fmode) | |
5948 | return; | |
5949 | /* TMODE must be a fixed-point mode. */ | |
5950 | if (!ALL_FIXED_POINT_MODE_P (tmode)) | |
5951 | return; | |
5952 | ||
5953 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5954 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5955 | else | |
5956 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5957 | } | |
5958 | ||
5959 | /* Pick proper libcall for satfractuns_optab. */ | |
5960 | ||
5961 | static void | |
5962 | gen_satfractuns_conv_libfunc (convert_optab tab, | |
5963 | const char *opname, | |
5964 | enum machine_mode tmode, | |
5965 | enum machine_mode fmode) | |
5966 | { | |
5967 | if (tmode == fmode) | |
5968 | return; | |
5969 | /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */ | |
5970 | if (!(ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT)) | |
5971 | return; | |
5972 | ||
5973 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5974 | } | |
5975 | ||
61698f54 RS |
5976 | /* A table of previously-created libfuncs, hashed by name. */ |
5977 | static GTY ((param_is (union tree_node))) htab_t libfunc_decls; | |
52859c77 | 5978 | |
61698f54 | 5979 | /* Hashtable callbacks for libfunc_decls. */ |
ee1315aa | 5980 | |
61698f54 RS |
5981 | static hashval_t |
5982 | libfunc_decl_hash (const void *entry) | |
5983 | { | |
6456e26e | 5984 | return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree) entry)); |
61698f54 | 5985 | } |
52859c77 | 5986 | |
61698f54 RS |
5987 | static int |
5988 | libfunc_decl_eq (const void *entry1, const void *entry2) | |
5989 | { | |
572e5ae3 | 5990 | return DECL_NAME ((const_tree) entry1) == (const_tree) entry2; |
61698f54 | 5991 | } |
52859c77 | 5992 | |
f9417da1 RG |
5993 | /* Build a decl for a libfunc named NAME. */ |
5994 | ||
5995 | tree | |
5996 | build_libfunc_function (const char *name) | |
5997 | { | |
5998 | tree decl = build_decl (UNKNOWN_LOCATION, FUNCTION_DECL, | |
5999 | get_identifier (name), | |
6000 | build_function_type (integer_type_node, NULL_TREE)); | |
6001 | /* ??? We don't have any type information except for this is | |
6002 | a function. Pretend this is "int foo()". */ | |
6003 | DECL_ARTIFICIAL (decl) = 1; | |
6004 | DECL_EXTERNAL (decl) = 1; | |
6005 | TREE_PUBLIC (decl) = 1; | |
6006 | gcc_assert (DECL_ASSEMBLER_NAME (decl)); | |
6007 | ||
6008 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
6009 | are the flags assigned by targetm.encode_section_info. */ | |
6010 | SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl), 0), NULL); | |
6011 | ||
6012 | return decl; | |
6013 | } | |
6014 | ||
61698f54 RS |
6015 | rtx |
6016 | init_one_libfunc (const char *name) | |
6017 | { | |
6018 | tree id, decl; | |
6019 | void **slot; | |
6020 | hashval_t hash; | |
6021 | ||
6022 | if (libfunc_decls == NULL) | |
6023 | libfunc_decls = htab_create_ggc (37, libfunc_decl_hash, | |
6024 | libfunc_decl_eq, NULL); | |
6025 | ||
6026 | /* See if we have already created a libfunc decl for this function. */ | |
6027 | id = get_identifier (name); | |
eef4a603 | 6028 | hash = IDENTIFIER_HASH_VALUE (id); |
61698f54 RS |
6029 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, INSERT); |
6030 | decl = (tree) *slot; | |
6031 | if (decl == NULL) | |
6032 | { | |
6033 | /* Create a new decl, so that it can be passed to | |
6034 | targetm.encode_section_info. */ | |
f9417da1 | 6035 | decl = build_libfunc_function (name); |
61698f54 RS |
6036 | *slot = decl; |
6037 | } | |
6038 | return XEXP (DECL_RTL (decl), 0); | |
76095e2f RH |
6039 | } |
6040 | ||
6b2b8871 JJ |
6041 | /* Adjust the assembler name of libfunc NAME to ASMSPEC. */ |
6042 | ||
6043 | rtx | |
6044 | set_user_assembler_libfunc (const char *name, const char *asmspec) | |
6045 | { | |
6046 | tree id, decl; | |
6047 | void **slot; | |
6048 | hashval_t hash; | |
6049 | ||
6050 | id = get_identifier (name); | |
eef4a603 | 6051 | hash = IDENTIFIER_HASH_VALUE (id); |
6b2b8871 JJ |
6052 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, NO_INSERT); |
6053 | gcc_assert (slot); | |
6054 | decl = (tree) *slot; | |
6055 | set_user_assembler_name (decl, asmspec); | |
6056 | return XEXP (DECL_RTL (decl), 0); | |
6057 | } | |
6058 | ||
c15c90bb ZW |
6059 | /* Call this to reset the function entry for one optab (OPTABLE) in mode |
6060 | MODE to NAME, which should be either 0 or a string constant. */ | |
6061 | void | |
6062 | set_optab_libfunc (optab optable, enum machine_mode mode, const char *name) | |
6063 | { | |
8a33f100 JH |
6064 | rtx val; |
6065 | struct libfunc_entry e; | |
6066 | struct libfunc_entry **slot; | |
33727b5e | 6067 | e.optab = (size_t) (optable - &optab_table[0]); |
8a33f100 JH |
6068 | e.mode1 = mode; |
6069 | e.mode2 = VOIDmode; | |
6070 | ||
c15c90bb | 6071 | if (name) |
8a33f100 | 6072 | val = init_one_libfunc (name); |
c15c90bb | 6073 | else |
8a33f100 JH |
6074 | val = 0; |
6075 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6076 | if (*slot == NULL) | |
a9429e29 | 6077 | *slot = ggc_alloc_libfunc_entry (); |
33727b5e | 6078 | (*slot)->optab = (size_t) (optable - &optab_table[0]); |
8a33f100 JH |
6079 | (*slot)->mode1 = mode; |
6080 | (*slot)->mode2 = VOIDmode; | |
6081 | (*slot)->libfunc = val; | |
c15c90bb ZW |
6082 | } |
6083 | ||
85363ca0 ZW |
6084 | /* Call this to reset the function entry for one conversion optab |
6085 | (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be | |
6086 | either 0 or a string constant. */ | |
6087 | void | |
6088 | set_conv_libfunc (convert_optab optable, enum machine_mode tmode, | |
6089 | enum machine_mode fmode, const char *name) | |
6090 | { | |
8a33f100 JH |
6091 | rtx val; |
6092 | struct libfunc_entry e; | |
6093 | struct libfunc_entry **slot; | |
33727b5e | 6094 | e.optab = (size_t) (optable - &convert_optab_table[0]); |
8a33f100 JH |
6095 | e.mode1 = tmode; |
6096 | e.mode2 = fmode; | |
6097 | ||
85363ca0 | 6098 | if (name) |
8a33f100 | 6099 | val = init_one_libfunc (name); |
85363ca0 | 6100 | else |
8a33f100 JH |
6101 | val = 0; |
6102 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6103 | if (*slot == NULL) | |
a9429e29 | 6104 | *slot = ggc_alloc_libfunc_entry (); |
33727b5e | 6105 | (*slot)->optab = (size_t) (optable - &convert_optab_table[0]); |
8a33f100 JH |
6106 | (*slot)->mode1 = tmode; |
6107 | (*slot)->mode2 = fmode; | |
6108 | (*slot)->libfunc = val; | |
85363ca0 ZW |
6109 | } |
6110 | ||
b5deb7b6 | 6111 | /* Call this to initialize the contents of the optabs |
77c9c6c2 RK |
6112 | appropriately for the current target machine. */ |
6113 | ||
6114 | void | |
0c20a65f | 6115 | init_optabs (void) |
77c9c6c2 | 6116 | { |
3e9c326a RS |
6117 | if (libfunc_hash) |
6118 | { | |
6119 | htab_empty (libfunc_hash); | |
6120 | /* We statically initialize the insn_codes with the equivalent of | |
6121 | CODE_FOR_nothing. Repeat the process if reinitialising. */ | |
6122 | init_insn_codes (); | |
6123 | } | |
6124 | else | |
6125 | libfunc_hash = htab_create_ggc (10, hash_libfunc, eq_libfunc, NULL); | |
c0742514 | 6126 | |
33727b5e JJ |
6127 | init_optab (add_optab, PLUS); |
6128 | init_optabv (addv_optab, PLUS); | |
6129 | init_optab (sub_optab, MINUS); | |
6130 | init_optabv (subv_optab, MINUS); | |
6131 | init_optab (ssadd_optab, SS_PLUS); | |
6132 | init_optab (usadd_optab, US_PLUS); | |
6133 | init_optab (sssub_optab, SS_MINUS); | |
6134 | init_optab (ussub_optab, US_MINUS); | |
6135 | init_optab (smul_optab, MULT); | |
6136 | init_optab (ssmul_optab, SS_MULT); | |
6137 | init_optab (usmul_optab, US_MULT); | |
6138 | init_optabv (smulv_optab, MULT); | |
6139 | init_optab (smul_highpart_optab, UNKNOWN); | |
6140 | init_optab (umul_highpart_optab, UNKNOWN); | |
6141 | init_optab (smul_widen_optab, UNKNOWN); | |
6142 | init_optab (umul_widen_optab, UNKNOWN); | |
6143 | init_optab (usmul_widen_optab, UNKNOWN); | |
6144 | init_optab (smadd_widen_optab, UNKNOWN); | |
6145 | init_optab (umadd_widen_optab, UNKNOWN); | |
6146 | init_optab (ssmadd_widen_optab, UNKNOWN); | |
6147 | init_optab (usmadd_widen_optab, UNKNOWN); | |
6148 | init_optab (smsub_widen_optab, UNKNOWN); | |
6149 | init_optab (umsub_widen_optab, UNKNOWN); | |
6150 | init_optab (ssmsub_widen_optab, UNKNOWN); | |
6151 | init_optab (usmsub_widen_optab, UNKNOWN); | |
6152 | init_optab (sdiv_optab, DIV); | |
6153 | init_optab (ssdiv_optab, SS_DIV); | |
6154 | init_optab (usdiv_optab, US_DIV); | |
6155 | init_optabv (sdivv_optab, DIV); | |
6156 | init_optab (sdivmod_optab, UNKNOWN); | |
6157 | init_optab (udiv_optab, UDIV); | |
6158 | init_optab (udivmod_optab, UNKNOWN); | |
6159 | init_optab (smod_optab, MOD); | |
6160 | init_optab (umod_optab, UMOD); | |
6161 | init_optab (fmod_optab, UNKNOWN); | |
6162 | init_optab (remainder_optab, UNKNOWN); | |
6163 | init_optab (ftrunc_optab, UNKNOWN); | |
6164 | init_optab (and_optab, AND); | |
6165 | init_optab (ior_optab, IOR); | |
6166 | init_optab (xor_optab, XOR); | |
6167 | init_optab (ashl_optab, ASHIFT); | |
6168 | init_optab (ssashl_optab, SS_ASHIFT); | |
6169 | init_optab (usashl_optab, US_ASHIFT); | |
6170 | init_optab (ashr_optab, ASHIFTRT); | |
6171 | init_optab (lshr_optab, LSHIFTRT); | |
6172 | init_optab (rotl_optab, ROTATE); | |
6173 | init_optab (rotr_optab, ROTATERT); | |
6174 | init_optab (smin_optab, SMIN); | |
6175 | init_optab (smax_optab, SMAX); | |
6176 | init_optab (umin_optab, UMIN); | |
6177 | init_optab (umax_optab, UMAX); | |
6178 | init_optab (pow_optab, UNKNOWN); | |
6179 | init_optab (atan2_optab, UNKNOWN); | |
ef89d648 ZW |
6180 | |
6181 | /* These three have codes assigned exclusively for the sake of | |
6182 | have_insn_for. */ | |
33727b5e JJ |
6183 | init_optab (mov_optab, SET); |
6184 | init_optab (movstrict_optab, STRICT_LOW_PART); | |
f90b7a5a PB |
6185 | init_optab (cbranch_optab, COMPARE); |
6186 | ||
6187 | init_optab (cmov_optab, UNKNOWN); | |
6188 | init_optab (cstore_optab, UNKNOWN); | |
6189 | init_optab (ctrap_optab, UNKNOWN); | |
33727b5e JJ |
6190 | |
6191 | init_optab (storent_optab, UNKNOWN); | |
6192 | ||
f90b7a5a | 6193 | init_optab (cmp_optab, UNKNOWN); |
33727b5e | 6194 | init_optab (ucmp_optab, UNKNOWN); |
33727b5e JJ |
6195 | |
6196 | init_optab (eq_optab, EQ); | |
6197 | init_optab (ne_optab, NE); | |
6198 | init_optab (gt_optab, GT); | |
6199 | init_optab (ge_optab, GE); | |
6200 | init_optab (lt_optab, LT); | |
6201 | init_optab (le_optab, LE); | |
6202 | init_optab (unord_optab, UNORDERED); | |
6203 | ||
6204 | init_optab (neg_optab, NEG); | |
6205 | init_optab (ssneg_optab, SS_NEG); | |
6206 | init_optab (usneg_optab, US_NEG); | |
6207 | init_optabv (negv_optab, NEG); | |
6208 | init_optab (abs_optab, ABS); | |
6209 | init_optabv (absv_optab, ABS); | |
6210 | init_optab (addcc_optab, UNKNOWN); | |
6211 | init_optab (one_cmpl_optab, NOT); | |
6212 | init_optab (bswap_optab, BSWAP); | |
6213 | init_optab (ffs_optab, FFS); | |
6214 | init_optab (clz_optab, CLZ); | |
6215 | init_optab (ctz_optab, CTZ); | |
6216 | init_optab (popcount_optab, POPCOUNT); | |
6217 | init_optab (parity_optab, PARITY); | |
6218 | init_optab (sqrt_optab, SQRT); | |
6219 | init_optab (floor_optab, UNKNOWN); | |
6220 | init_optab (ceil_optab, UNKNOWN); | |
6221 | init_optab (round_optab, UNKNOWN); | |
6222 | init_optab (btrunc_optab, UNKNOWN); | |
6223 | init_optab (nearbyint_optab, UNKNOWN); | |
6224 | init_optab (rint_optab, UNKNOWN); | |
6225 | init_optab (sincos_optab, UNKNOWN); | |
6226 | init_optab (sin_optab, UNKNOWN); | |
6227 | init_optab (asin_optab, UNKNOWN); | |
6228 | init_optab (cos_optab, UNKNOWN); | |
6229 | init_optab (acos_optab, UNKNOWN); | |
6230 | init_optab (exp_optab, UNKNOWN); | |
6231 | init_optab (exp10_optab, UNKNOWN); | |
6232 | init_optab (exp2_optab, UNKNOWN); | |
6233 | init_optab (expm1_optab, UNKNOWN); | |
6234 | init_optab (ldexp_optab, UNKNOWN); | |
6235 | init_optab (scalb_optab, UNKNOWN); | |
dc6707b8 | 6236 | init_optab (significand_optab, UNKNOWN); |
33727b5e JJ |
6237 | init_optab (logb_optab, UNKNOWN); |
6238 | init_optab (ilogb_optab, UNKNOWN); | |
6239 | init_optab (log_optab, UNKNOWN); | |
6240 | init_optab (log10_optab, UNKNOWN); | |
6241 | init_optab (log2_optab, UNKNOWN); | |
6242 | init_optab (log1p_optab, UNKNOWN); | |
6243 | init_optab (tan_optab, UNKNOWN); | |
6244 | init_optab (atan_optab, UNKNOWN); | |
6245 | init_optab (copysign_optab, UNKNOWN); | |
6246 | init_optab (signbit_optab, UNKNOWN); | |
6247 | ||
6248 | init_optab (isinf_optab, UNKNOWN); | |
6249 | ||
6250 | init_optab (strlen_optab, UNKNOWN); | |
33727b5e JJ |
6251 | init_optab (push_optab, UNKNOWN); |
6252 | ||
6253 | init_optab (reduc_smax_optab, UNKNOWN); | |
6254 | init_optab (reduc_umax_optab, UNKNOWN); | |
6255 | init_optab (reduc_smin_optab, UNKNOWN); | |
6256 | init_optab (reduc_umin_optab, UNKNOWN); | |
6257 | init_optab (reduc_splus_optab, UNKNOWN); | |
6258 | init_optab (reduc_uplus_optab, UNKNOWN); | |
6259 | ||
6260 | init_optab (ssum_widen_optab, UNKNOWN); | |
6261 | init_optab (usum_widen_optab, UNKNOWN); | |
b8698a0f | 6262 | init_optab (sdot_prod_optab, UNKNOWN); |
33727b5e JJ |
6263 | init_optab (udot_prod_optab, UNKNOWN); |
6264 | ||
6265 | init_optab (vec_extract_optab, UNKNOWN); | |
6266 | init_optab (vec_extract_even_optab, UNKNOWN); | |
6267 | init_optab (vec_extract_odd_optab, UNKNOWN); | |
6268 | init_optab (vec_interleave_high_optab, UNKNOWN); | |
6269 | init_optab (vec_interleave_low_optab, UNKNOWN); | |
6270 | init_optab (vec_set_optab, UNKNOWN); | |
6271 | init_optab (vec_init_optab, UNKNOWN); | |
6272 | init_optab (vec_shl_optab, UNKNOWN); | |
6273 | init_optab (vec_shr_optab, UNKNOWN); | |
6274 | init_optab (vec_realign_load_optab, UNKNOWN); | |
6275 | init_optab (movmisalign_optab, UNKNOWN); | |
6276 | init_optab (vec_widen_umult_hi_optab, UNKNOWN); | |
6277 | init_optab (vec_widen_umult_lo_optab, UNKNOWN); | |
6278 | init_optab (vec_widen_smult_hi_optab, UNKNOWN); | |
6279 | init_optab (vec_widen_smult_lo_optab, UNKNOWN); | |
6280 | init_optab (vec_unpacks_hi_optab, UNKNOWN); | |
6281 | init_optab (vec_unpacks_lo_optab, UNKNOWN); | |
6282 | init_optab (vec_unpacku_hi_optab, UNKNOWN); | |
6283 | init_optab (vec_unpacku_lo_optab, UNKNOWN); | |
6284 | init_optab (vec_unpacks_float_hi_optab, UNKNOWN); | |
6285 | init_optab (vec_unpacks_float_lo_optab, UNKNOWN); | |
6286 | init_optab (vec_unpacku_float_hi_optab, UNKNOWN); | |
6287 | init_optab (vec_unpacku_float_lo_optab, UNKNOWN); | |
6288 | init_optab (vec_pack_trunc_optab, UNKNOWN); | |
6289 | init_optab (vec_pack_usat_optab, UNKNOWN); | |
6290 | init_optab (vec_pack_ssat_optab, UNKNOWN); | |
6291 | init_optab (vec_pack_ufix_trunc_optab, UNKNOWN); | |
6292 | init_optab (vec_pack_sfix_trunc_optab, UNKNOWN); | |
6293 | ||
6294 | init_optab (powi_optab, UNKNOWN); | |
17684d46 | 6295 | |
85363ca0 | 6296 | /* Conversions. */ |
33727b5e JJ |
6297 | init_convert_optab (sext_optab, SIGN_EXTEND); |
6298 | init_convert_optab (zext_optab, ZERO_EXTEND); | |
6299 | init_convert_optab (trunc_optab, TRUNCATE); | |
6300 | init_convert_optab (sfix_optab, FIX); | |
6301 | init_convert_optab (ufix_optab, UNSIGNED_FIX); | |
6302 | init_convert_optab (sfixtrunc_optab, UNKNOWN); | |
6303 | init_convert_optab (ufixtrunc_optab, UNKNOWN); | |
6304 | init_convert_optab (sfloat_optab, FLOAT); | |
6305 | init_convert_optab (ufloat_optab, UNSIGNED_FLOAT); | |
6306 | init_convert_optab (lrint_optab, UNKNOWN); | |
6307 | init_convert_optab (lround_optab, UNKNOWN); | |
6308 | init_convert_optab (lfloor_optab, UNKNOWN); | |
6309 | init_convert_optab (lceil_optab, UNKNOWN); | |
6310 | ||
6311 | init_convert_optab (fract_optab, FRACT_CONVERT); | |
6312 | init_convert_optab (fractuns_optab, UNSIGNED_FRACT_CONVERT); | |
6313 | init_convert_optab (satfract_optab, SAT_FRACT); | |
6314 | init_convert_optab (satfractuns_optab, UNSIGNED_SAT_FRACT); | |
0f996086 | 6315 | |
5d81dc5b RK |
6316 | /* Fill in the optabs with the insns we support. */ |
6317 | init_all_optabs (); | |
6318 | ||
5d81dc5b | 6319 | /* Initialize the optabs with the names of the library functions. */ |
8a33f100 JH |
6320 | add_optab->libcall_basename = "add"; |
6321 | add_optab->libcall_suffix = '3'; | |
0f996086 | 6322 | add_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6323 | addv_optab->libcall_basename = "add"; |
6324 | addv_optab->libcall_suffix = '3'; | |
6325 | addv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6326 | ssadd_optab->libcall_basename = "ssadd"; |
6327 | ssadd_optab->libcall_suffix = '3'; | |
6328 | ssadd_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6329 | usadd_optab->libcall_basename = "usadd"; | |
6330 | usadd_optab->libcall_suffix = '3'; | |
6331 | usadd_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6332 | sub_optab->libcall_basename = "sub"; |
6333 | sub_optab->libcall_suffix = '3'; | |
0f996086 | 6334 | sub_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6335 | subv_optab->libcall_basename = "sub"; |
6336 | subv_optab->libcall_suffix = '3'; | |
6337 | subv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6338 | sssub_optab->libcall_basename = "sssub"; |
6339 | sssub_optab->libcall_suffix = '3'; | |
6340 | sssub_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6341 | ussub_optab->libcall_basename = "ussub"; | |
6342 | ussub_optab->libcall_suffix = '3'; | |
6343 | ussub_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6344 | smul_optab->libcall_basename = "mul"; |
6345 | smul_optab->libcall_suffix = '3'; | |
0f996086 | 6346 | smul_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6347 | smulv_optab->libcall_basename = "mul"; |
6348 | smulv_optab->libcall_suffix = '3'; | |
6349 | smulv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6350 | ssmul_optab->libcall_basename = "ssmul"; |
6351 | ssmul_optab->libcall_suffix = '3'; | |
6352 | ssmul_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6353 | usmul_optab->libcall_basename = "usmul"; | |
6354 | usmul_optab->libcall_suffix = '3'; | |
6355 | usmul_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6356 | sdiv_optab->libcall_basename = "div"; |
6357 | sdiv_optab->libcall_suffix = '3'; | |
0f996086 | 6358 | sdiv_optab->libcall_gen = gen_int_fp_signed_fixed_libfunc; |
8a33f100 JH |
6359 | sdivv_optab->libcall_basename = "divv"; |
6360 | sdivv_optab->libcall_suffix = '3'; | |
6361 | sdivv_optab->libcall_gen = gen_int_libfunc; | |
0f996086 CF |
6362 | ssdiv_optab->libcall_basename = "ssdiv"; |
6363 | ssdiv_optab->libcall_suffix = '3'; | |
6364 | ssdiv_optab->libcall_gen = gen_signed_fixed_libfunc; | |
8a33f100 JH |
6365 | udiv_optab->libcall_basename = "udiv"; |
6366 | udiv_optab->libcall_suffix = '3'; | |
0f996086 CF |
6367 | udiv_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
6368 | usdiv_optab->libcall_basename = "usdiv"; | |
6369 | usdiv_optab->libcall_suffix = '3'; | |
6370 | usdiv_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6371 | sdivmod_optab->libcall_basename = "divmod"; |
6372 | sdivmod_optab->libcall_suffix = '4'; | |
6373 | sdivmod_optab->libcall_gen = gen_int_libfunc; | |
6374 | udivmod_optab->libcall_basename = "udivmod"; | |
6375 | udivmod_optab->libcall_suffix = '4'; | |
6376 | udivmod_optab->libcall_gen = gen_int_libfunc; | |
6377 | smod_optab->libcall_basename = "mod"; | |
6378 | smod_optab->libcall_suffix = '3'; | |
6379 | smod_optab->libcall_gen = gen_int_libfunc; | |
6380 | umod_optab->libcall_basename = "umod"; | |
6381 | umod_optab->libcall_suffix = '3'; | |
6382 | umod_optab->libcall_gen = gen_int_libfunc; | |
6383 | ftrunc_optab->libcall_basename = "ftrunc"; | |
6384 | ftrunc_optab->libcall_suffix = '2'; | |
6385 | ftrunc_optab->libcall_gen = gen_fp_libfunc; | |
6386 | and_optab->libcall_basename = "and"; | |
6387 | and_optab->libcall_suffix = '3'; | |
6388 | and_optab->libcall_gen = gen_int_libfunc; | |
6389 | ior_optab->libcall_basename = "ior"; | |
6390 | ior_optab->libcall_suffix = '3'; | |
6391 | ior_optab->libcall_gen = gen_int_libfunc; | |
6392 | xor_optab->libcall_basename = "xor"; | |
6393 | xor_optab->libcall_suffix = '3'; | |
6394 | xor_optab->libcall_gen = gen_int_libfunc; | |
6395 | ashl_optab->libcall_basename = "ashl"; | |
6396 | ashl_optab->libcall_suffix = '3'; | |
0f996086 CF |
6397 | ashl_optab->libcall_gen = gen_int_fixed_libfunc; |
6398 | ssashl_optab->libcall_basename = "ssashl"; | |
6399 | ssashl_optab->libcall_suffix = '3'; | |
6400 | ssashl_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6401 | usashl_optab->libcall_basename = "usashl"; | |
6402 | usashl_optab->libcall_suffix = '3'; | |
6403 | usashl_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6404 | ashr_optab->libcall_basename = "ashr"; |
6405 | ashr_optab->libcall_suffix = '3'; | |
0f996086 | 6406 | ashr_optab->libcall_gen = gen_int_signed_fixed_libfunc; |
8a33f100 JH |
6407 | lshr_optab->libcall_basename = "lshr"; |
6408 | lshr_optab->libcall_suffix = '3'; | |
0f996086 | 6409 | lshr_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
8a33f100 JH |
6410 | smin_optab->libcall_basename = "min"; |
6411 | smin_optab->libcall_suffix = '3'; | |
6412 | smin_optab->libcall_gen = gen_int_fp_libfunc; | |
6413 | smax_optab->libcall_basename = "max"; | |
6414 | smax_optab->libcall_suffix = '3'; | |
6415 | smax_optab->libcall_gen = gen_int_fp_libfunc; | |
6416 | umin_optab->libcall_basename = "umin"; | |
6417 | umin_optab->libcall_suffix = '3'; | |
6418 | umin_optab->libcall_gen = gen_int_libfunc; | |
6419 | umax_optab->libcall_basename = "umax"; | |
6420 | umax_optab->libcall_suffix = '3'; | |
6421 | umax_optab->libcall_gen = gen_int_libfunc; | |
6422 | neg_optab->libcall_basename = "neg"; | |
6423 | neg_optab->libcall_suffix = '2'; | |
0f996086 CF |
6424 | neg_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
6425 | ssneg_optab->libcall_basename = "ssneg"; | |
6426 | ssneg_optab->libcall_suffix = '2'; | |
6427 | ssneg_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6428 | usneg_optab->libcall_basename = "usneg"; | |
6429 | usneg_optab->libcall_suffix = '2'; | |
6430 | usneg_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6431 | negv_optab->libcall_basename = "neg"; |
6432 | negv_optab->libcall_suffix = '2'; | |
6433 | negv_optab->libcall_gen = gen_intv_fp_libfunc; | |
6434 | one_cmpl_optab->libcall_basename = "one_cmpl"; | |
6435 | one_cmpl_optab->libcall_suffix = '2'; | |
6436 | one_cmpl_optab->libcall_gen = gen_int_libfunc; | |
6437 | ffs_optab->libcall_basename = "ffs"; | |
6438 | ffs_optab->libcall_suffix = '2'; | |
6439 | ffs_optab->libcall_gen = gen_int_libfunc; | |
6440 | clz_optab->libcall_basename = "clz"; | |
6441 | clz_optab->libcall_suffix = '2'; | |
6442 | clz_optab->libcall_gen = gen_int_libfunc; | |
6443 | ctz_optab->libcall_basename = "ctz"; | |
6444 | ctz_optab->libcall_suffix = '2'; | |
6445 | ctz_optab->libcall_gen = gen_int_libfunc; | |
6446 | popcount_optab->libcall_basename = "popcount"; | |
6447 | popcount_optab->libcall_suffix = '2'; | |
6448 | popcount_optab->libcall_gen = gen_int_libfunc; | |
6449 | parity_optab->libcall_basename = "parity"; | |
6450 | parity_optab->libcall_suffix = '2'; | |
6451 | parity_optab->libcall_gen = gen_int_libfunc; | |
d55ab31d MM |
6452 | |
6453 | /* Comparison libcalls for integers MUST come in pairs, | |
6454 | signed/unsigned. */ | |
8a33f100 JH |
6455 | cmp_optab->libcall_basename = "cmp"; |
6456 | cmp_optab->libcall_suffix = '2'; | |
0f996086 | 6457 | cmp_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6458 | ucmp_optab->libcall_basename = "ucmp"; |
6459 | ucmp_optab->libcall_suffix = '2'; | |
6460 | ucmp_optab->libcall_gen = gen_int_libfunc; | |
d55ab31d MM |
6461 | |
6462 | /* EQ etc are floating point only. */ | |
8a33f100 JH |
6463 | eq_optab->libcall_basename = "eq"; |
6464 | eq_optab->libcall_suffix = '2'; | |
6465 | eq_optab->libcall_gen = gen_fp_libfunc; | |
6466 | ne_optab->libcall_basename = "ne"; | |
6467 | ne_optab->libcall_suffix = '2'; | |
6468 | ne_optab->libcall_gen = gen_fp_libfunc; | |
6469 | gt_optab->libcall_basename = "gt"; | |
6470 | gt_optab->libcall_suffix = '2'; | |
6471 | gt_optab->libcall_gen = gen_fp_libfunc; | |
6472 | ge_optab->libcall_basename = "ge"; | |
6473 | ge_optab->libcall_suffix = '2'; | |
6474 | ge_optab->libcall_gen = gen_fp_libfunc; | |
6475 | lt_optab->libcall_basename = "lt"; | |
6476 | lt_optab->libcall_suffix = '2'; | |
6477 | lt_optab->libcall_gen = gen_fp_libfunc; | |
6478 | le_optab->libcall_basename = "le"; | |
6479 | le_optab->libcall_suffix = '2'; | |
6480 | le_optab->libcall_gen = gen_fp_libfunc; | |
6481 | unord_optab->libcall_basename = "unord"; | |
6482 | unord_optab->libcall_suffix = '2'; | |
6483 | unord_optab->libcall_gen = gen_fp_libfunc; | |
6484 | ||
6485 | powi_optab->libcall_basename = "powi"; | |
6486 | powi_optab->libcall_suffix = '2'; | |
6487 | powi_optab->libcall_gen = gen_fp_libfunc; | |
17684d46 | 6488 | |
d55ab31d | 6489 | /* Conversions. */ |
8a33f100 JH |
6490 | sfloat_optab->libcall_basename = "float"; |
6491 | sfloat_optab->libcall_gen = gen_int_to_fp_conv_libfunc; | |
6492 | ufloat_optab->libcall_gen = gen_ufloat_conv_libfunc; | |
6493 | sfix_optab->libcall_basename = "fix"; | |
6494 | sfix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6495 | ufix_optab->libcall_basename = "fixuns"; | |
6496 | ufix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6497 | lrint_optab->libcall_basename = "lrint"; | |
6498 | lrint_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6499 | lround_optab->libcall_basename = "lround"; | |
6500 | lround_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6501 | lfloor_optab->libcall_basename = "lfloor"; | |
6502 | lfloor_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6503 | lceil_optab->libcall_basename = "lceil"; | |
6504 | lceil_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6505 | ||
6506 | /* trunc_optab is also used for FLOAT_EXTEND. */ | |
6507 | sext_optab->libcall_basename = "extend"; | |
6508 | sext_optab->libcall_gen = gen_extend_conv_libfunc; | |
6509 | trunc_optab->libcall_basename = "trunc"; | |
6510 | trunc_optab->libcall_gen = gen_trunc_conv_libfunc; | |
6511 | ||
0f996086 CF |
6512 | /* Conversions for fixed-point modes and other modes. */ |
6513 | fract_optab->libcall_basename = "fract"; | |
6514 | fract_optab->libcall_gen = gen_fract_conv_libfunc; | |
6515 | satfract_optab->libcall_basename = "satfract"; | |
6516 | satfract_optab->libcall_gen = gen_satfract_conv_libfunc; | |
6517 | fractuns_optab->libcall_basename = "fractuns"; | |
6518 | fractuns_optab->libcall_gen = gen_fractuns_conv_libfunc; | |
6519 | satfractuns_optab->libcall_basename = "satfractuns"; | |
6520 | satfractuns_optab->libcall_gen = gen_satfractuns_conv_libfunc; | |
6521 | ||
8a33f100 JH |
6522 | /* The ffs function operates on `int'. Fall back on it if we do not |
6523 | have a libgcc2 function for that width. */ | |
6524 | if (INT_TYPE_SIZE < BITS_PER_WORD) | |
0f900dfa JJ |
6525 | set_optab_libfunc (ffs_optab, mode_for_size (INT_TYPE_SIZE, MODE_INT, 0), |
6526 | "ffs"); | |
76095e2f | 6527 | |
167fa32c EC |
6528 | /* Explicitly initialize the bswap libfuncs since we need them to be |
6529 | valid for things other than word_mode. */ | |
6530 | set_optab_libfunc (bswap_optab, SImode, "__bswapsi2"); | |
6531 | set_optab_libfunc (bswap_optab, DImode, "__bswapdi2"); | |
6532 | ||
85363ca0 ZW |
6533 | /* Use cabs for double complex abs, since systems generally have cabs. |
6534 | Don't define any libcall for float complex, so that cabs will be used. */ | |
6535 | if (complex_double_type_node) | |
8a33f100 | 6536 | set_optab_libfunc (abs_optab, TYPE_MODE (complex_double_type_node), "cabs"); |
76095e2f | 6537 | |
9602f5a0 | 6538 | abort_libfunc = init_one_libfunc ("abort"); |
76095e2f | 6539 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
b215b52e | 6540 | memmove_libfunc = init_one_libfunc ("memmove"); |
76095e2f | 6541 | memcmp_libfunc = init_one_libfunc ("memcmp"); |
76095e2f | 6542 | memset_libfunc = init_one_libfunc ("memset"); |
68d28100 | 6543 | setbits_libfunc = init_one_libfunc ("__setbits"); |
76095e2f | 6544 | |
6e6a07d2 | 6545 | #ifndef DONT_USE_BUILTIN_SETJMP |
76095e2f RH |
6546 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
6547 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
27a36778 | 6548 | #else |
76095e2f RH |
6549 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
6550 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
27a36778 | 6551 | #endif |
52a11cbf RH |
6552 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
6553 | unwind_sjlj_unregister_libfunc | |
6554 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
6adb4e3a | 6555 | |
07417085 KR |
6556 | /* For function entry/exit instrumentation. */ |
6557 | profile_function_entry_libfunc | |
76095e2f | 6558 | = init_one_libfunc ("__cyg_profile_func_enter"); |
07417085 | 6559 | profile_function_exit_libfunc |
76095e2f | 6560 | = init_one_libfunc ("__cyg_profile_func_exit"); |
07417085 | 6561 | |
68d28100 | 6562 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
68d28100 | 6563 | |
159c2aed | 6564 | /* Allow the target to add more libcalls or rename some, etc. */ |
c15c90bb | 6565 | targetm.init_libfuncs (); |
77c9c6c2 | 6566 | } |
b3f8d95d | 6567 | |
b3f8d95d MM |
6568 | /* Print information about the current contents of the optabs on |
6569 | STDERR. */ | |
6570 | ||
24e47c76 | 6571 | DEBUG_FUNCTION void |
b3f8d95d MM |
6572 | debug_optab_libfuncs (void) |
6573 | { | |
6574 | int i; | |
6575 | int j; | |
6576 | int k; | |
6577 | ||
6578 | /* Dump the arithmetic optabs. */ | |
5906d013 | 6579 | for (i = 0; i != (int) OTI_MAX; i++) |
b3f8d95d MM |
6580 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6581 | { | |
6582 | optab o; | |
8a33f100 | 6583 | rtx l; |
b3f8d95d | 6584 | |
33727b5e | 6585 | o = &optab_table[i]; |
bbbbb16a | 6586 | l = optab_libfunc (o, (enum machine_mode) j); |
8a33f100 | 6587 | if (l) |
b3f8d95d | 6588 | { |
8a33f100 | 6589 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6590 | fprintf (stderr, "%s\t%s:\t%s\n", |
b3f8d95d MM |
6591 | GET_RTX_NAME (o->code), |
6592 | GET_MODE_NAME (j), | |
8a33f100 | 6593 | XSTR (l, 0)); |
b3f8d95d MM |
6594 | } |
6595 | } | |
6596 | ||
6597 | /* Dump the conversion optabs. */ | |
c414ac1d | 6598 | for (i = 0; i < (int) COI_MAX; ++i) |
b3f8d95d MM |
6599 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6600 | for (k = 0; k < NUM_MACHINE_MODES; ++k) | |
6601 | { | |
6602 | convert_optab o; | |
8a33f100 | 6603 | rtx l; |
b3f8d95d | 6604 | |
33727b5e | 6605 | o = &convert_optab_table[i]; |
bbbbb16a ILT |
6606 | l = convert_optab_libfunc (o, (enum machine_mode) j, |
6607 | (enum machine_mode) k); | |
8a33f100 | 6608 | if (l) |
b3f8d95d | 6609 | { |
8a33f100 | 6610 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6611 | fprintf (stderr, "%s\t%s\t%s:\t%s\n", |
b3f8d95d MM |
6612 | GET_RTX_NAME (o->code), |
6613 | GET_MODE_NAME (j), | |
6614 | GET_MODE_NAME (k), | |
8a33f100 | 6615 | XSTR (l, 0)); |
b3f8d95d MM |
6616 | } |
6617 | } | |
6618 | } | |
6619 | ||
7e1966ca | 6620 | \f |
e0cd0770 JC |
6621 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
6622 | CODE. Return 0 on failure. */ | |
6623 | ||
6624 | rtx | |
f90b7a5a | 6625 | gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode) |
e0cd0770 JC |
6626 | { |
6627 | enum machine_mode mode = GET_MODE (op1); | |
842a431a DM |
6628 | enum insn_code icode; |
6629 | rtx insn; | |
f90b7a5a | 6630 | rtx trap_rtx; |
e0cd0770 JC |
6631 | |
6632 | if (mode == VOIDmode) | |
6633 | return 0; | |
6634 | ||
947131ba | 6635 | icode = optab_handler (ctrap_optab, mode); |
842a431a DM |
6636 | if (icode == CODE_FOR_nothing) |
6637 | return 0; | |
6638 | ||
f90b7a5a PB |
6639 | /* Some targets only accept a zero trap code. */ |
6640 | if (insn_data[icode].operand[3].predicate | |
6641 | && !insn_data[icode].operand[3].predicate (tcode, VOIDmode)) | |
6642 | return 0; | |
6643 | ||
6644 | do_pending_stack_adjust (); | |
842a431a | 6645 | start_sequence (); |
f90b7a5a PB |
6646 | prepare_cmp_insn (op1, op2, code, NULL_RTX, false, OPTAB_DIRECT, |
6647 | &trap_rtx, &mode); | |
6648 | if (!trap_rtx) | |
6649 | insn = NULL_RTX; | |
6650 | else | |
6651 | insn = GEN_FCN (icode) (trap_rtx, XEXP (trap_rtx, 0), XEXP (trap_rtx, 1), | |
6652 | tcode); | |
6653 | ||
6654 | /* If that failed, then give up. */ | |
6655 | if (insn == 0) | |
d893ccde RH |
6656 | { |
6657 | end_sequence (); | |
6658 | return 0; | |
6659 | } | |
842a431a | 6660 | |
f90b7a5a PB |
6661 | emit_insn (insn); |
6662 | insn = get_insns (); | |
842a431a | 6663 | end_sequence (); |
842a431a | 6664 | return insn; |
e0cd0770 | 6665 | } |
e2500fed | 6666 | |
7ce67fbe DP |
6667 | /* Return rtx code for TCODE. Use UNSIGNEDP to select signed |
6668 | or unsigned operation code. */ | |
6669 | ||
6670 | static enum rtx_code | |
6671 | get_rtx_code (enum tree_code tcode, bool unsignedp) | |
6672 | { | |
6673 | enum rtx_code code; | |
6674 | switch (tcode) | |
6675 | { | |
6676 | case EQ_EXPR: | |
6677 | code = EQ; | |
6678 | break; | |
6679 | case NE_EXPR: | |
6680 | code = NE; | |
6681 | break; | |
6682 | case LT_EXPR: | |
6683 | code = unsignedp ? LTU : LT; | |
6684 | break; | |
6685 | case LE_EXPR: | |
6686 | code = unsignedp ? LEU : LE; | |
6687 | break; | |
6688 | case GT_EXPR: | |
6689 | code = unsignedp ? GTU : GT; | |
6690 | break; | |
6691 | case GE_EXPR: | |
6692 | code = unsignedp ? GEU : GE; | |
6693 | break; | |
c414ac1d | 6694 | |
7ce67fbe DP |
6695 | case UNORDERED_EXPR: |
6696 | code = UNORDERED; | |
6697 | break; | |
6698 | case ORDERED_EXPR: | |
6699 | code = ORDERED; | |
6700 | break; | |
6701 | case UNLT_EXPR: | |
6702 | code = UNLT; | |
6703 | break; | |
6704 | case UNLE_EXPR: | |
6705 | code = UNLE; | |
6706 | break; | |
6707 | case UNGT_EXPR: | |
6708 | code = UNGT; | |
6709 | break; | |
6710 | case UNGE_EXPR: | |
6711 | code = UNGE; | |
6712 | break; | |
6713 | case UNEQ_EXPR: | |
6714 | code = UNEQ; | |
6715 | break; | |
6716 | case LTGT_EXPR: | |
6717 | code = LTGT; | |
6718 | break; | |
6719 | ||
6720 | default: | |
e3feb571 | 6721 | gcc_unreachable (); |
7ce67fbe DP |
6722 | } |
6723 | return code; | |
6724 | } | |
6725 | ||
6726 | /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or | |
6727 | unsigned operators. Do not generate compare instruction. */ | |
6728 | ||
6729 | static rtx | |
6730 | vector_compare_rtx (tree cond, bool unsignedp, enum insn_code icode) | |
6731 | { | |
6732 | enum rtx_code rcode; | |
6733 | tree t_op0, t_op1; | |
6734 | rtx rtx_op0, rtx_op1; | |
6735 | ||
e3feb571 NS |
6736 | /* This is unlikely. While generating VEC_COND_EXPR, auto vectorizer |
6737 | ensures that condition is a relational operation. */ | |
6738 | gcc_assert (COMPARISON_CLASS_P (cond)); | |
7ce67fbe | 6739 | |
c414ac1d | 6740 | rcode = get_rtx_code (TREE_CODE (cond), unsignedp); |
e3feb571 NS |
6741 | t_op0 = TREE_OPERAND (cond, 0); |
6742 | t_op1 = TREE_OPERAND (cond, 1); | |
c414ac1d | 6743 | |
7ce67fbe | 6744 | /* Expand operands. */ |
49452c07 UB |
6745 | rtx_op0 = expand_expr (t_op0, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op0)), |
6746 | EXPAND_STACK_PARM); | |
6747 | rtx_op1 = expand_expr (t_op1, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op1)), | |
6748 | EXPAND_STACK_PARM); | |
7ce67fbe | 6749 | |
e3feb571 | 6750 | if (!insn_data[icode].operand[4].predicate (rtx_op0, GET_MODE (rtx_op0)) |
7ce67fbe DP |
6751 | && GET_MODE (rtx_op0) != VOIDmode) |
6752 | rtx_op0 = force_reg (GET_MODE (rtx_op0), rtx_op0); | |
c414ac1d | 6753 | |
e3feb571 | 6754 | if (!insn_data[icode].operand[5].predicate (rtx_op1, GET_MODE (rtx_op1)) |
7ce67fbe DP |
6755 | && GET_MODE (rtx_op1) != VOIDmode) |
6756 | rtx_op1 = force_reg (GET_MODE (rtx_op1), rtx_op1); | |
6757 | ||
6758 | return gen_rtx_fmt_ee (rcode, VOIDmode, rtx_op0, rtx_op1); | |
6759 | } | |
6760 | ||
8e7aa1f9 | 6761 | /* Return insn code for TYPE, the type of a VEC_COND_EXPR. */ |
c414ac1d EC |
6762 | |
6763 | static inline enum insn_code | |
8e7aa1f9 | 6764 | get_vcond_icode (tree type, enum machine_mode mode) |
7ce67fbe DP |
6765 | { |
6766 | enum insn_code icode = CODE_FOR_nothing; | |
6767 | ||
8e7aa1f9 | 6768 | if (TYPE_UNSIGNED (type)) |
f9621cc4 | 6769 | icode = direct_optab_handler (vcondu_optab, mode); |
7ce67fbe | 6770 | else |
f9621cc4 | 6771 | icode = direct_optab_handler (vcond_optab, mode); |
7ce67fbe DP |
6772 | return icode; |
6773 | } | |
6774 | ||
6775 | /* Return TRUE iff, appropriate vector insns are available | |
8e7aa1f9 | 6776 | for vector cond expr with type TYPE in VMODE mode. */ |
7ce67fbe DP |
6777 | |
6778 | bool | |
8e7aa1f9 | 6779 | expand_vec_cond_expr_p (tree type, enum machine_mode vmode) |
7ce67fbe | 6780 | { |
8e7aa1f9 | 6781 | if (get_vcond_icode (type, vmode) == CODE_FOR_nothing) |
7ce67fbe DP |
6782 | return false; |
6783 | return true; | |
6784 | } | |
6785 | ||
8e7aa1f9 MM |
6786 | /* Generate insns for a VEC_COND_EXPR, given its TYPE and its |
6787 | three operands. */ | |
7ce67fbe DP |
6788 | |
6789 | rtx | |
8e7aa1f9 MM |
6790 | expand_vec_cond_expr (tree vec_cond_type, tree op0, tree op1, tree op2, |
6791 | rtx target) | |
7ce67fbe DP |
6792 | { |
6793 | enum insn_code icode; | |
6794 | rtx comparison, rtx_op1, rtx_op2, cc_op0, cc_op1; | |
8e7aa1f9 MM |
6795 | enum machine_mode mode = TYPE_MODE (vec_cond_type); |
6796 | bool unsignedp = TYPE_UNSIGNED (vec_cond_type); | |
7ce67fbe | 6797 | |
8e7aa1f9 | 6798 | icode = get_vcond_icode (vec_cond_type, mode); |
7ce67fbe DP |
6799 | if (icode == CODE_FOR_nothing) |
6800 | return 0; | |
6801 | ||
3bc751bd | 6802 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) |
7ce67fbe DP |
6803 | target = gen_reg_rtx (mode); |
6804 | ||
6dbd43ba | 6805 | /* Get comparison rtx. First expand both cond expr operands. */ |
8e7aa1f9 | 6806 | comparison = vector_compare_rtx (op0, |
7ce67fbe DP |
6807 | unsignedp, icode); |
6808 | cc_op0 = XEXP (comparison, 0); | |
6809 | cc_op1 = XEXP (comparison, 1); | |
6810 | /* Expand both operands and force them in reg, if required. */ | |
8e7aa1f9 | 6811 | rtx_op1 = expand_normal (op1); |
e3feb571 | 6812 | if (!insn_data[icode].operand[1].predicate (rtx_op1, mode) |
7ce67fbe DP |
6813 | && mode != VOIDmode) |
6814 | rtx_op1 = force_reg (mode, rtx_op1); | |
6815 | ||
8e7aa1f9 | 6816 | rtx_op2 = expand_normal (op2); |
e3feb571 | 6817 | if (!insn_data[icode].operand[2].predicate (rtx_op2, mode) |
7ce67fbe DP |
6818 | && mode != VOIDmode) |
6819 | rtx_op2 = force_reg (mode, rtx_op2); | |
6820 | ||
6821 | /* Emit instruction! */ | |
c414ac1d | 6822 | emit_insn (GEN_FCN (icode) (target, rtx_op1, rtx_op2, |
7ce67fbe DP |
6823 | comparison, cc_op0, cc_op1)); |
6824 | ||
6825 | return target; | |
6826 | } | |
48ae6c13 RH |
6827 | |
6828 | \f | |
6829 | /* This is an internal subroutine of the other compare_and_swap expanders. | |
6830 | MEM, OLD_VAL and NEW_VAL are as you'd expect for a compare-and-swap | |
6831 | operation. TARGET is an optional place to store the value result of | |
6832 | the operation. ICODE is the particular instruction to expand. Return | |
6833 | the result of the operation. */ | |
6834 | ||
6835 | static rtx | |
6836 | expand_val_compare_and_swap_1 (rtx mem, rtx old_val, rtx new_val, | |
6837 | rtx target, enum insn_code icode) | |
6838 | { | |
6839 | enum machine_mode mode = GET_MODE (mem); | |
6840 | rtx insn; | |
6841 | ||
6842 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
6843 | target = gen_reg_rtx (mode); | |
6844 | ||
6845 | if (GET_MODE (old_val) != VOIDmode && GET_MODE (old_val) != mode) | |
6846 | old_val = convert_modes (mode, GET_MODE (old_val), old_val, 1); | |
6847 | if (!insn_data[icode].operand[2].predicate (old_val, mode)) | |
6848 | old_val = force_reg (mode, old_val); | |
6849 | ||
6850 | if (GET_MODE (new_val) != VOIDmode && GET_MODE (new_val) != mode) | |
6851 | new_val = convert_modes (mode, GET_MODE (new_val), new_val, 1); | |
6852 | if (!insn_data[icode].operand[3].predicate (new_val, mode)) | |
6853 | new_val = force_reg (mode, new_val); | |
6854 | ||
6855 | insn = GEN_FCN (icode) (target, mem, old_val, new_val); | |
6856 | if (insn == NULL_RTX) | |
6857 | return NULL_RTX; | |
6858 | emit_insn (insn); | |
6859 | ||
6860 | return target; | |
6861 | } | |
6862 | ||
6863 | /* Expand a compare-and-swap operation and return its value. */ | |
6864 | ||
6865 | rtx | |
6866 | expand_val_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6867 | { | |
6868 | enum machine_mode mode = GET_MODE (mem); | |
f9621cc4 RS |
6869 | enum insn_code icode |
6870 | = direct_optab_handler (sync_compare_and_swap_optab, mode); | |
48ae6c13 RH |
6871 | |
6872 | if (icode == CODE_FOR_nothing) | |
6873 | return NULL_RTX; | |
6874 | ||
6875 | return expand_val_compare_and_swap_1 (mem, old_val, new_val, target, icode); | |
6876 | } | |
6877 | ||
4a77c72b PB |
6878 | /* Helper function to find the MODE_CC set in a sync_compare_and_swap |
6879 | pattern. */ | |
6880 | ||
6881 | static void | |
6882 | find_cc_set (rtx x, const_rtx pat, void *data) | |
6883 | { | |
6884 | if (REG_P (x) && GET_MODE_CLASS (GET_MODE (x)) == MODE_CC | |
6885 | && GET_CODE (pat) == SET) | |
6886 | { | |
6887 | rtx *p_cc_reg = (rtx *) data; | |
6888 | gcc_assert (!*p_cc_reg); | |
6889 | *p_cc_reg = x; | |
6890 | } | |
6891 | } | |
6892 | ||
48ae6c13 RH |
6893 | /* Expand a compare-and-swap operation and store true into the result if |
6894 | the operation was successful and false otherwise. Return the result. | |
6895 | Unlike other routines, TARGET is not optional. */ | |
6896 | ||
6897 | rtx | |
6898 | expand_bool_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6899 | { | |
6900 | enum machine_mode mode = GET_MODE (mem); | |
6901 | enum insn_code icode; | |
4a77c72b | 6902 | rtx subtarget, seq, cc_reg; |
48ae6c13 RH |
6903 | |
6904 | /* If the target supports a compare-and-swap pattern that simultaneously | |
6905 | sets some flag for success, then use it. Otherwise use the regular | |
6906 | compare-and-swap and follow that immediately with a compare insn. */ | |
f9621cc4 | 6907 | icode = direct_optab_handler (sync_compare_and_swap_optab, mode); |
4a77c72b PB |
6908 | if (icode == CODE_FOR_nothing) |
6909 | return NULL_RTX; | |
f12b785d | 6910 | |
e5f5fa2d | 6911 | do_pending_stack_adjust (); |
4a77c72b PB |
6912 | do |
6913 | { | |
6914 | start_sequence (); | |
48ae6c13 | 6915 | subtarget = expand_val_compare_and_swap_1 (mem, old_val, new_val, |
4a77c72b PB |
6916 | NULL_RTX, icode); |
6917 | cc_reg = NULL_RTX; | |
48ae6c13 | 6918 | if (subtarget == NULL_RTX) |
48ae6c13 | 6919 | { |
4a77c72b PB |
6920 | end_sequence (); |
6921 | return NULL_RTX; | |
48ae6c13 | 6922 | } |
48ae6c13 | 6923 | |
4a77c72b PB |
6924 | if (have_insn_for (COMPARE, CCmode)) |
6925 | note_stores (PATTERN (get_last_insn ()), find_cc_set, &cc_reg); | |
6926 | seq = get_insns (); | |
6927 | end_sequence (); | |
48ae6c13 | 6928 | |
4a77c72b PB |
6929 | /* We might be comparing against an old value. Try again. :-( */ |
6930 | if (!cc_reg && MEM_P (old_val)) | |
6931 | { | |
6932 | seq = NULL_RTX; | |
6933 | old_val = force_reg (mode, old_val); | |
6934 | } | |
6935 | } | |
6936 | while (!seq); | |
48ae6c13 | 6937 | |
4a77c72b PB |
6938 | emit_insn (seq); |
6939 | if (cc_reg) | |
f90b7a5a | 6940 | return emit_store_flag_force (target, EQ, cc_reg, const0_rtx, VOIDmode, 0, 1); |
4a77c72b | 6941 | else |
f90b7a5a | 6942 | return emit_store_flag_force (target, EQ, subtarget, old_val, VOIDmode, 1, 1); |
48ae6c13 RH |
6943 | } |
6944 | ||
6945 | /* This is a helper function for the other atomic operations. This function | |
6946 | emits a loop that contains SEQ that iterates until a compare-and-swap | |
6947 | operation at the end succeeds. MEM is the memory to be modified. SEQ is | |
6948 | a set of instructions that takes a value from OLD_REG as an input and | |
6949 | produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be | |
6950 | set to the current contents of MEM. After SEQ, a compare-and-swap will | |
6951 | attempt to update MEM with NEW_REG. The function returns true when the | |
6952 | loop was generated successfully. */ | |
6953 | ||
6954 | static bool | |
6955 | expand_compare_and_swap_loop (rtx mem, rtx old_reg, rtx new_reg, rtx seq) | |
6956 | { | |
6957 | enum machine_mode mode = GET_MODE (mem); | |
6958 | enum insn_code icode; | |
4a77c72b | 6959 | rtx label, cmp_reg, subtarget, cc_reg; |
48ae6c13 RH |
6960 | |
6961 | /* The loop we want to generate looks like | |
6962 | ||
81ba4f39 | 6963 | cmp_reg = mem; |
48ae6c13 | 6964 | label: |
81ba4f39 | 6965 | old_reg = cmp_reg; |
48ae6c13 | 6966 | seq; |
81ba4f39 RH |
6967 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) |
6968 | if (cmp_reg != old_reg) | |
48ae6c13 RH |
6969 | goto label; |
6970 | ||
6971 | Note that we only do the plain load from memory once. Subsequent | |
6972 | iterations use the value loaded by the compare-and-swap pattern. */ | |
6973 | ||
6974 | label = gen_label_rtx (); | |
81ba4f39 | 6975 | cmp_reg = gen_reg_rtx (mode); |
48ae6c13 | 6976 | |
81ba4f39 | 6977 | emit_move_insn (cmp_reg, mem); |
48ae6c13 | 6978 | emit_label (label); |
81ba4f39 | 6979 | emit_move_insn (old_reg, cmp_reg); |
48ae6c13 RH |
6980 | if (seq) |
6981 | emit_insn (seq); | |
6982 | ||
6983 | /* If the target supports a compare-and-swap pattern that simultaneously | |
6984 | sets some flag for success, then use it. Otherwise use the regular | |
6985 | compare-and-swap and follow that immediately with a compare insn. */ | |
f9621cc4 | 6986 | icode = direct_optab_handler (sync_compare_and_swap_optab, mode); |
4a77c72b PB |
6987 | if (icode == CODE_FOR_nothing) |
6988 | return false; | |
48ae6c13 | 6989 | |
4a77c72b PB |
6990 | subtarget = expand_val_compare_and_swap_1 (mem, old_reg, new_reg, |
6991 | cmp_reg, icode); | |
6992 | if (subtarget == NULL_RTX) | |
6993 | return false; | |
48ae6c13 | 6994 | |
4a77c72b PB |
6995 | cc_reg = NULL_RTX; |
6996 | if (have_insn_for (COMPARE, CCmode)) | |
6997 | note_stores (PATTERN (get_last_insn ()), find_cc_set, &cc_reg); | |
6998 | if (cc_reg) | |
6999 | { | |
7000 | cmp_reg = cc_reg; | |
7001 | old_reg = const0_rtx; | |
7002 | } | |
7003 | else | |
7004 | { | |
81ba4f39 RH |
7005 | if (subtarget != cmp_reg) |
7006 | emit_move_insn (cmp_reg, subtarget); | |
48ae6c13 RH |
7007 | } |
7008 | ||
7009 | /* ??? Mark this jump predicted not taken? */ | |
4a77c72b PB |
7010 | emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, const0_rtx, GET_MODE (cmp_reg), 1, |
7011 | label); | |
48ae6c13 RH |
7012 | return true; |
7013 | } | |
7014 | ||
7015 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
c414ac1d | 7016 | case, we do not care about any resulting value. Returns NULL if we |
48ae6c13 RH |
7017 | cannot generate the operation. */ |
7018 | ||
7019 | rtx | |
7020 | expand_sync_operation (rtx mem, rtx val, enum rtx_code code) | |
7021 | { | |
7022 | enum machine_mode mode = GET_MODE (mem); | |
7023 | enum insn_code icode; | |
7024 | rtx insn; | |
7025 | ||
7026 | /* Look to see if the target supports the operation directly. */ | |
7027 | switch (code) | |
7028 | { | |
7029 | case PLUS: | |
f9621cc4 | 7030 | icode = direct_optab_handler (sync_add_optab, mode); |
48ae6c13 RH |
7031 | break; |
7032 | case IOR: | |
f9621cc4 | 7033 | icode = direct_optab_handler (sync_ior_optab, mode); |
48ae6c13 RH |
7034 | break; |
7035 | case XOR: | |
f9621cc4 | 7036 | icode = direct_optab_handler (sync_xor_optab, mode); |
48ae6c13 RH |
7037 | break; |
7038 | case AND: | |
f9621cc4 | 7039 | icode = direct_optab_handler (sync_and_optab, mode); |
48ae6c13 | 7040 | break; |
f12b785d | 7041 | case NOT: |
f9621cc4 | 7042 | icode = direct_optab_handler (sync_nand_optab, mode); |
f12b785d | 7043 | break; |
48ae6c13 RH |
7044 | |
7045 | case MINUS: | |
f9621cc4 | 7046 | icode = direct_optab_handler (sync_sub_optab, mode); |
3b010fe3 | 7047 | if (icode == CODE_FOR_nothing || CONST_INT_P (val)) |
48ae6c13 | 7048 | { |
f9621cc4 | 7049 | icode = direct_optab_handler (sync_add_optab, mode); |
48ae6c13 RH |
7050 | if (icode != CODE_FOR_nothing) |
7051 | { | |
7052 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
7053 | code = PLUS; | |
7054 | } | |
7055 | } | |
7056 | break; | |
7057 | ||
48ae6c13 RH |
7058 | default: |
7059 | gcc_unreachable (); | |
7060 | } | |
7061 | ||
7062 | /* Generate the direct operation, if present. */ | |
7063 | if (icode != CODE_FOR_nothing) | |
7064 | { | |
7065 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7066 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7067 | if (!insn_data[icode].operand[1].predicate (val, mode)) | |
7068 | val = force_reg (mode, val); | |
c414ac1d | 7069 | |
48ae6c13 RH |
7070 | insn = GEN_FCN (icode) (mem, val); |
7071 | if (insn) | |
7072 | { | |
7073 | emit_insn (insn); | |
7074 | return const0_rtx; | |
7075 | } | |
7076 | } | |
7077 | ||
7078 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
7079 | operation with normal arithmetic instructions. */ | |
f9621cc4 RS |
7080 | if (direct_optab_handler (sync_compare_and_swap_optab, mode) |
7081 | != CODE_FOR_nothing) | |
48ae6c13 RH |
7082 | { |
7083 | rtx t0 = gen_reg_rtx (mode), t1; | |
7084 | ||
7085 | start_sequence (); | |
7086 | ||
f12b785d | 7087 | t1 = t0; |
48ae6c13 RH |
7088 | if (code == NOT) |
7089 | { | |
23462d4d UB |
7090 | t1 = expand_simple_binop (mode, AND, t1, val, NULL_RTX, |
7091 | true, OPTAB_LIB_WIDEN); | |
7092 | t1 = expand_simple_unop (mode, code, t1, NULL_RTX, true); | |
48ae6c13 | 7093 | } |
23462d4d UB |
7094 | else |
7095 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, | |
7096 | true, OPTAB_LIB_WIDEN); | |
48ae6c13 RH |
7097 | insn = get_insns (); |
7098 | end_sequence (); | |
7099 | ||
7100 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
7101 | return const0_rtx; | |
7102 | } | |
7103 | ||
7104 | return NULL_RTX; | |
7105 | } | |
7106 | ||
7107 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
7108 | case, we do care about the resulting value: if AFTER is true then | |
c414ac1d | 7109 | return the value MEM holds after the operation, if AFTER is false |
48ae6c13 RH |
7110 | then return the value MEM holds before the operation. TARGET is an |
7111 | optional place for the result value to be stored. */ | |
7112 | ||
7113 | rtx | |
7114 | expand_sync_fetch_operation (rtx mem, rtx val, enum rtx_code code, | |
7115 | bool after, rtx target) | |
7116 | { | |
7117 | enum machine_mode mode = GET_MODE (mem); | |
7118 | enum insn_code old_code, new_code, icode; | |
7119 | bool compensate; | |
7120 | rtx insn; | |
7121 | ||
7122 | /* Look to see if the target supports the operation directly. */ | |
7123 | switch (code) | |
7124 | { | |
7125 | case PLUS: | |
f9621cc4 RS |
7126 | old_code = direct_optab_handler (sync_old_add_optab, mode); |
7127 | new_code = direct_optab_handler (sync_new_add_optab, mode); | |
48ae6c13 RH |
7128 | break; |
7129 | case IOR: | |
f9621cc4 RS |
7130 | old_code = direct_optab_handler (sync_old_ior_optab, mode); |
7131 | new_code = direct_optab_handler (sync_new_ior_optab, mode); | |
48ae6c13 RH |
7132 | break; |
7133 | case XOR: | |
f9621cc4 RS |
7134 | old_code = direct_optab_handler (sync_old_xor_optab, mode); |
7135 | new_code = direct_optab_handler (sync_new_xor_optab, mode); | |
48ae6c13 RH |
7136 | break; |
7137 | case AND: | |
f9621cc4 RS |
7138 | old_code = direct_optab_handler (sync_old_and_optab, mode); |
7139 | new_code = direct_optab_handler (sync_new_and_optab, mode); | |
48ae6c13 | 7140 | break; |
f12b785d | 7141 | case NOT: |
f9621cc4 RS |
7142 | old_code = direct_optab_handler (sync_old_nand_optab, mode); |
7143 | new_code = direct_optab_handler (sync_new_nand_optab, mode); | |
f12b785d | 7144 | break; |
48ae6c13 RH |
7145 | |
7146 | case MINUS: | |
f9621cc4 RS |
7147 | old_code = direct_optab_handler (sync_old_sub_optab, mode); |
7148 | new_code = direct_optab_handler (sync_new_sub_optab, mode); | |
3b010fe3 DD |
7149 | if ((old_code == CODE_FOR_nothing && new_code == CODE_FOR_nothing) |
7150 | || CONST_INT_P (val)) | |
48ae6c13 | 7151 | { |
f9621cc4 RS |
7152 | old_code = direct_optab_handler (sync_old_add_optab, mode); |
7153 | new_code = direct_optab_handler (sync_new_add_optab, mode); | |
48ae6c13 RH |
7154 | if (old_code != CODE_FOR_nothing || new_code != CODE_FOR_nothing) |
7155 | { | |
7156 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
7157 | code = PLUS; | |
7158 | } | |
7159 | } | |
7160 | break; | |
7161 | ||
48ae6c13 RH |
7162 | default: |
7163 | gcc_unreachable (); | |
7164 | } | |
7165 | ||
7166 | /* If the target does supports the proper new/old operation, great. But | |
7167 | if we only support the opposite old/new operation, check to see if we | |
7168 | can compensate. In the case in which the old value is supported, then | |
7169 | we can always perform the operation again with normal arithmetic. In | |
7170 | the case in which the new value is supported, then we can only handle | |
7171 | this in the case the operation is reversible. */ | |
7172 | compensate = false; | |
7173 | if (after) | |
7174 | { | |
7175 | icode = new_code; | |
7176 | if (icode == CODE_FOR_nothing) | |
7177 | { | |
7178 | icode = old_code; | |
7179 | if (icode != CODE_FOR_nothing) | |
7180 | compensate = true; | |
7181 | } | |
7182 | } | |
7183 | else | |
7184 | { | |
7185 | icode = old_code; | |
7186 | if (icode == CODE_FOR_nothing | |
7187 | && (code == PLUS || code == MINUS || code == XOR)) | |
7188 | { | |
7189 | icode = new_code; | |
7190 | if (icode != CODE_FOR_nothing) | |
7191 | compensate = true; | |
7192 | } | |
7193 | } | |
7194 | ||
7195 | /* If we found something supported, great. */ | |
7196 | if (icode != CODE_FOR_nothing) | |
7197 | { | |
7198 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
7199 | target = gen_reg_rtx (mode); | |
7200 | ||
7201 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7202 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7203 | if (!insn_data[icode].operand[2].predicate (val, mode)) | |
7204 | val = force_reg (mode, val); | |
c414ac1d | 7205 | |
48ae6c13 RH |
7206 | insn = GEN_FCN (icode) (target, mem, val); |
7207 | if (insn) | |
7208 | { | |
7209 | emit_insn (insn); | |
7210 | ||
7211 | /* If we need to compensate for using an operation with the | |
7212 | wrong return value, do so now. */ | |
7213 | if (compensate) | |
7214 | { | |
7215 | if (!after) | |
7216 | { | |
7217 | if (code == PLUS) | |
7218 | code = MINUS; | |
7219 | else if (code == MINUS) | |
7220 | code = PLUS; | |
7221 | } | |
f12b785d RH |
7222 | |
7223 | if (code == NOT) | |
23462d4d UB |
7224 | { |
7225 | target = expand_simple_binop (mode, AND, target, val, | |
7226 | NULL_RTX, true, | |
7227 | OPTAB_LIB_WIDEN); | |
7228 | target = expand_simple_unop (mode, code, target, | |
7229 | NULL_RTX, true); | |
7230 | } | |
7231 | else | |
7232 | target = expand_simple_binop (mode, code, target, val, | |
7233 | NULL_RTX, true, | |
7234 | OPTAB_LIB_WIDEN); | |
48ae6c13 RH |
7235 | } |
7236 | ||
7237 | return target; | |
7238 | } | |
7239 | } | |
7240 | ||
7241 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
7242 | operation with normal arithmetic instructions. */ | |
f9621cc4 RS |
7243 | if (direct_optab_handler (sync_compare_and_swap_optab, mode) |
7244 | != CODE_FOR_nothing) | |
48ae6c13 RH |
7245 | { |
7246 | rtx t0 = gen_reg_rtx (mode), t1; | |
7247 | ||
7248 | if (!target || !register_operand (target, mode)) | |
7249 | target = gen_reg_rtx (mode); | |
7250 | ||
7251 | start_sequence (); | |
7252 | ||
f12b785d RH |
7253 | if (!after) |
7254 | emit_move_insn (target, t0); | |
7255 | t1 = t0; | |
48ae6c13 RH |
7256 | if (code == NOT) |
7257 | { | |
23462d4d UB |
7258 | t1 = expand_simple_binop (mode, AND, t1, val, NULL_RTX, |
7259 | true, OPTAB_LIB_WIDEN); | |
7260 | t1 = expand_simple_unop (mode, code, t1, NULL_RTX, true); | |
48ae6c13 | 7261 | } |
23462d4d UB |
7262 | else |
7263 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, | |
7264 | true, OPTAB_LIB_WIDEN); | |
48ae6c13 RH |
7265 | if (after) |
7266 | emit_move_insn (target, t1); | |
7267 | ||
7268 | insn = get_insns (); | |
7269 | end_sequence (); | |
7270 | ||
7271 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
7272 | return target; | |
7273 | } | |
7274 | ||
7275 | return NULL_RTX; | |
7276 | } | |
7277 | ||
7278 | /* This function expands a test-and-set operation. Ideally we atomically | |
7279 | store VAL in MEM and return the previous value in MEM. Some targets | |
7280 | may not support this operation and only support VAL with the constant 1; | |
c414ac1d | 7281 | in this case while the return value will be 0/1, but the exact value |
48ae6c13 RH |
7282 | stored in MEM is target defined. TARGET is an option place to stick |
7283 | the return value. */ | |
7284 | ||
7285 | rtx | |
7286 | expand_sync_lock_test_and_set (rtx mem, rtx val, rtx target) | |
7287 | { | |
7288 | enum machine_mode mode = GET_MODE (mem); | |
7289 | enum insn_code icode; | |
7290 | rtx insn; | |
7291 | ||
7292 | /* If the target supports the test-and-set directly, great. */ | |
f9621cc4 | 7293 | icode = direct_optab_handler (sync_lock_test_and_set_optab, mode); |
48ae6c13 RH |
7294 | if (icode != CODE_FOR_nothing) |
7295 | { | |
7296 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
7297 | target = gen_reg_rtx (mode); | |
7298 | ||
7299 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7300 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7301 | if (!insn_data[icode].operand[2].predicate (val, mode)) | |
7302 | val = force_reg (mode, val); | |
7303 | ||
7304 | insn = GEN_FCN (icode) (target, mem, val); | |
7305 | if (insn) | |
7306 | { | |
7307 | emit_insn (insn); | |
7308 | return target; | |
7309 | } | |
7310 | } | |
7311 | ||
7312 | /* Otherwise, use a compare-and-swap loop for the exchange. */ | |
f9621cc4 RS |
7313 | if (direct_optab_handler (sync_compare_and_swap_optab, mode) |
7314 | != CODE_FOR_nothing) | |
48ae6c13 RH |
7315 | { |
7316 | if (!target || !register_operand (target, mode)) | |
7317 | target = gen_reg_rtx (mode); | |
7318 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7319 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7320 | if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX)) | |
7321 | return target; | |
7322 | } | |
7323 | ||
7324 | return NULL_RTX; | |
7325 | } | |
7326 | ||
e2500fed | 7327 | #include "gt-optabs.h" |