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55a2c322 | 1 | /* Local Register Allocator (LRA) intercommunication header file. |
23a5b65a | 2 | Copyright (C) 2010-2014 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "lra.h" | |
22 | #include "bitmap.h" | |
23 | #include "recog.h" | |
24 | #include "insn-attr.h" | |
25 | #include "insn-codes.h" | |
7b3b6ae4 LC |
26 | #include "insn-config.h" |
27 | #include "regs.h" | |
55a2c322 | 28 | |
a202e609 | 29 | #define lra_assert(c) gcc_checking_assert (c) |
55a2c322 VM |
30 | |
31 | /* The parameter used to prevent infinite reloading for an insn. Each | |
32 | insn operands might require a reload and, if it is a memory, its | |
33 | base and index registers might require a reload too. */ | |
34 | #define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3) | |
35 | ||
55a2c322 VM |
36 | typedef struct lra_live_range *lra_live_range_t; |
37 | ||
38 | /* The structure describes program points where a given pseudo lives. | |
39 | The live ranges can be used to find conflicts with other pseudos. | |
40 | If the live ranges of two pseudos are intersected, the pseudos are | |
41 | in conflict. */ | |
42 | struct lra_live_range | |
43 | { | |
44 | /* Pseudo regno whose live range is described by given | |
45 | structure. */ | |
46 | int regno; | |
47 | /* Program point range. */ | |
48 | int start, finish; | |
49 | /* Next structure describing program points where the pseudo | |
50 | lives. */ | |
51 | lra_live_range_t next; | |
52 | /* Pointer to structures with the same start. */ | |
53 | lra_live_range_t start_next; | |
54 | }; | |
55 | ||
56 | typedef struct lra_copy *lra_copy_t; | |
57 | ||
58 | /* Copy between pseudos which affects assigning hard registers. */ | |
59 | struct lra_copy | |
60 | { | |
61 | /* True if regno1 is the destination of the copy. */ | |
62 | bool regno1_dest_p; | |
63 | /* Execution frequency of the copy. */ | |
64 | int freq; | |
65 | /* Pseudos connected by the copy. REGNO1 < REGNO2. */ | |
66 | int regno1, regno2; | |
67 | /* Next copy with correspondingly REGNO1 and REGNO2. */ | |
68 | lra_copy_t regno1_next, regno2_next; | |
69 | }; | |
70 | ||
71 | /* Common info about a register (pseudo or hard register). */ | |
72 | struct lra_reg | |
73 | { | |
74 | /* Bitmap of UIDs of insns (including debug insns) referring the | |
75 | reg. */ | |
76 | bitmap_head insn_bitmap; | |
77 | /* The following fields are defined only for pseudos. */ | |
78 | /* Hard registers with which the pseudo conflicts. */ | |
79 | HARD_REG_SET conflict_hard_regs; | |
10e1bdb2 TV |
80 | /* Call used registers with which the pseudo conflicts, taking into account |
81 | the registers used by functions called from calls which cross the | |
82 | pseudo. */ | |
83 | HARD_REG_SET actual_call_used_reg_set; | |
55a2c322 VM |
84 | /* We assign hard registers to reload pseudos which can occur in few |
85 | places. So two hard register preferences are enough for them. | |
86 | The following fields define the preferred hard registers. If | |
87 | there are no such hard registers the first field value is | |
88 | negative. If there is only one preferred hard register, the 2nd | |
89 | field is negative. */ | |
90 | int preferred_hard_regno1, preferred_hard_regno2; | |
91 | /* Profits to use the corresponding preferred hard registers. If | |
92 | the both hard registers defined, the first hard register has not | |
93 | less profit than the second one. */ | |
94 | int preferred_hard_regno_profit1, preferred_hard_regno_profit2; | |
95 | #ifdef STACK_REGS | |
96 | /* True if the pseudo should not be assigned to a stack register. */ | |
97 | bool no_stack_p; | |
98 | #endif | |
99 | #ifdef ENABLE_CHECKING | |
100 | /* True if the pseudo crosses a call. It is setup in lra-lives.c | |
101 | and used to check that the pseudo crossing a call did not get a | |
102 | call used hard register. */ | |
103 | bool call_p; | |
104 | #endif | |
105 | /* Number of references and execution frequencies of the register in | |
106 | *non-debug* insns. */ | |
107 | int nrefs, freq; | |
108 | int last_reload; | |
109 | /* Regno used to undo the inheritance. It can be non-zero only | |
110 | between couple of inheritance and undo inheritance passes. */ | |
111 | int restore_regno; | |
112 | /* Value holding by register. If the pseudos have the same value | |
113 | they do not conflict. */ | |
114 | int val; | |
d70a81dd SC |
115 | /* Offset from relative eliminate register to pesudo reg. */ |
116 | int offset; | |
55a2c322 VM |
117 | /* These members are set up in lra-lives.c and updated in |
118 | lra-coalesce.c. */ | |
119 | /* The biggest size mode in which each pseudo reg is referred in | |
120 | whole function (possibly via subreg). */ | |
121 | enum machine_mode biggest_mode; | |
122 | /* Live ranges of the pseudo. */ | |
123 | lra_live_range_t live_ranges; | |
124 | /* This member is set up in lra-lives.c for subsequent | |
125 | assignments. */ | |
126 | lra_copy_t copies; | |
127 | }; | |
128 | ||
129 | /* References to the common info about each register. */ | |
130 | extern struct lra_reg *lra_reg_info; | |
131 | ||
132 | /* Static info about each insn operand (common for all insns with the | |
133 | same ICODE). Warning: if the structure definition is changed, the | |
134 | initializer for debug_operand_data in lra.c should be changed | |
135 | too. */ | |
136 | struct lra_operand_data | |
137 | { | |
138 | /* The machine description constraint string of the operand. */ | |
139 | const char *constraint; | |
140 | /* It is taken only from machine description (which is different | |
141 | from recog_data.operand_mode) and can be of VOIDmode. */ | |
142 | ENUM_BITFIELD(machine_mode) mode : 16; | |
143 | /* The type of the operand (in/out/inout). */ | |
144 | ENUM_BITFIELD (op_type) type : 8; | |
145 | /* Through if accessed through STRICT_LOW. */ | |
146 | unsigned int strict_low : 1; | |
147 | /* True if the operand is an operator. */ | |
148 | unsigned int is_operator : 1; | |
149 | /* True if there is an early clobber alternative for this operand. | |
150 | This field is set up every time when corresponding | |
151 | operand_alternative in lra_static_insn_data is set up. */ | |
152 | unsigned int early_clobber : 1; | |
153 | /* True if the operand is an address. */ | |
154 | unsigned int is_address : 1; | |
155 | }; | |
156 | ||
157 | /* Info about register occurrence in an insn. */ | |
158 | struct lra_insn_reg | |
159 | { | |
160 | /* The biggest mode through which the insn refers to the register | |
161 | occurrence (remember the register can be accessed through a | |
162 | subreg in the insn). */ | |
163 | ENUM_BITFIELD(machine_mode) biggest_mode : 16; | |
164 | /* The type of the corresponding operand which is the register. */ | |
165 | ENUM_BITFIELD (op_type) type : 8; | |
166 | /* True if the reg is accessed through a subreg and the subreg is | |
167 | just a part of the register. */ | |
168 | unsigned int subreg_p : 1; | |
169 | /* True if there is an early clobber alternative for this | |
170 | operand. */ | |
171 | unsigned int early_clobber : 1; | |
172 | /* The corresponding regno of the register. */ | |
173 | int regno; | |
174 | /* Next reg info of the same insn. */ | |
175 | struct lra_insn_reg *next; | |
176 | }; | |
177 | ||
178 | /* Static part (common info for insns with the same ICODE) of LRA | |
179 | internal insn info. It exists in at most one exemplar for each | |
180 | non-negative ICODE. There is only one exception. Each asm insn has | |
181 | own structure. Warning: if the structure definition is changed, | |
182 | the initializer for debug_insn_static_data in lra.c should be | |
183 | changed too. */ | |
184 | struct lra_static_insn_data | |
185 | { | |
186 | /* Static info about each insn operand. */ | |
187 | struct lra_operand_data *operand; | |
188 | /* Each duplication refers to the number of the corresponding | |
189 | operand which is duplicated. */ | |
190 | int *dup_num; | |
191 | /* The number of an operand marked as commutative, -1 otherwise. */ | |
192 | int commutative; | |
193 | /* Number of operands, duplications, and alternatives of the | |
194 | insn. */ | |
195 | char n_operands; | |
196 | char n_dups; | |
197 | char n_alternatives; | |
198 | /* Insns in machine description (or clobbers in asm) may contain | |
199 | explicit hard regs which are not operands. The following list | |
200 | describes such hard registers. */ | |
201 | struct lra_insn_reg *hard_regs; | |
202 | /* Array [n_alternatives][n_operand] of static constraint info for | |
203 | given operand in given alternative. This info can be changed if | |
204 | the target reg info is changed. */ | |
0c331756 | 205 | const struct operand_alternative *operand_alternative; |
55a2c322 VM |
206 | }; |
207 | ||
208 | /* LRA internal info about an insn (LRA internal insn | |
209 | representation). */ | |
210 | struct lra_insn_recog_data | |
211 | { | |
212 | /* The insn code. */ | |
213 | int icode; | |
8d49e7ef VM |
214 | /* The alternative should be used for the insn, -1 if invalid, or we |
215 | should try to use any alternative, or the insn is a debug | |
216 | insn. */ | |
217 | int used_insn_alternative; | |
218 | /* SP offset before the insn relative to one at the func start. */ | |
219 | HOST_WIDE_INT sp_offset; | |
55a2c322 VM |
220 | /* The insn itself. */ |
221 | rtx insn; | |
222 | /* Common data for insns with the same ICODE. Asm insns (their | |
223 | ICODE is negative) do not share such structures. */ | |
224 | struct lra_static_insn_data *insn_static_data; | |
225 | /* Two arrays of size correspondingly equal to the operand and the | |
226 | duplication numbers: */ | |
227 | rtx **operand_loc; /* The operand locations, NULL if no operands. */ | |
228 | rtx **dup_loc; /* The dup locations, NULL if no dups. */ | |
229 | /* Number of hard registers implicitly used in given call insn. The | |
230 | value can be NULL or points to array of the hard register numbers | |
231 | ending with a negative value. */ | |
232 | int *arg_hard_regs; | |
55a2c322 | 233 | /* Alternative enabled for the insn. NULL for debug insns. */ |
4cc8d9d2 | 234 | alternative_mask enabled_alternatives; |
55a2c322 VM |
235 | /* The following member value is always NULL for a debug insn. */ |
236 | struct lra_insn_reg *regs; | |
237 | }; | |
238 | ||
239 | typedef struct lra_insn_recog_data *lra_insn_recog_data_t; | |
240 | ||
c5cd5a7e VM |
241 | /* Whether the clobber is used temporary in LRA. */ |
242 | #define LRA_TEMP_CLOBBER_P(x) \ | |
243 | (RTL_FLAG_CHECK1 ("TEMP_CLOBBER_P", (x), CLOBBER)->unchanging) | |
244 | ||
821b7577 VM |
245 | /* Cost factor for each additional reload and maximal cost reject for |
246 | insn reloads. One might ask about such strange numbers. Their | |
247 | values occurred historically from former reload pass. */ | |
248 | #define LRA_LOSER_COST_FACTOR 6 | |
249 | #define LRA_MAX_REJECT 600 | |
250 | ||
8e3a4869 VM |
251 | /* Maximum allowed number of constraint pass iterations after the last |
252 | spill pass. It is for preventing LRA cycling in a bug case. */ | |
253 | #define LRA_MAX_CONSTRAINT_ITERATION_NUMBER 30 | |
254 | ||
255 | /* The maximal number of inheritance/split passes in LRA. It should | |
256 | be more 1 in order to perform caller saves transformations and much | |
257 | less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many | |
258 | as permitted constraint passes in some complicated cases. The | |
259 | first inheritance/split pass has a biggest impact on generated code | |
260 | quality. Each subsequent affects generated code in less degree. | |
261 | For example, the 3rd pass does not change generated SPEC2000 code | |
262 | at all on x86-64. */ | |
263 | #define LRA_MAX_INHERITANCE_PASSES 2 | |
264 | ||
265 | #if LRA_MAX_INHERITANCE_PASSES <= 0 \ | |
266 | || LRA_MAX_INHERITANCE_PASSES >= LRA_MAX_CONSTRAINT_ITERATION_NUMBER - 8 | |
267 | #error wrong LRA_MAX_INHERITANCE_PASSES value | |
268 | #endif | |
269 | ||
55a2c322 VM |
270 | /* lra.c: */ |
271 | ||
272 | extern FILE *lra_dump_file; | |
273 | ||
274 | extern bool lra_reg_spill_p; | |
275 | ||
276 | extern HARD_REG_SET lra_no_alloc_regs; | |
277 | ||
278 | extern int lra_insn_recog_data_len; | |
279 | extern lra_insn_recog_data_t *lra_insn_recog_data; | |
280 | ||
281 | extern int lra_curr_reload_num; | |
282 | ||
283 | extern void lra_push_insn (rtx); | |
284 | extern void lra_push_insn_by_uid (unsigned int); | |
285 | extern void lra_push_insn_and_update_insn_regno_info (rtx); | |
286 | extern rtx lra_pop_insn (void); | |
287 | extern unsigned int lra_insn_stack_length (void); | |
288 | ||
289 | extern rtx lra_create_new_reg_with_unique_value (enum machine_mode, rtx, | |
290 | enum reg_class, const char *); | |
291 | extern void lra_set_regno_unique_value (int); | |
292 | extern void lra_invalidate_insn_data (rtx); | |
293 | extern void lra_set_insn_deleted (rtx); | |
294 | extern void lra_delete_dead_insn (rtx); | |
295 | extern void lra_emit_add (rtx, rtx, rtx); | |
296 | extern void lra_emit_move (rtx, rtx); | |
297 | extern void lra_update_dups (lra_insn_recog_data_t, signed char *); | |
298 | ||
299 | extern void lra_process_new_insns (rtx, rtx, rtx, const char *); | |
300 | ||
301 | extern lra_insn_recog_data_t lra_set_insn_recog_data (rtx); | |
302 | extern lra_insn_recog_data_t lra_update_insn_recog_data (rtx); | |
303 | extern void lra_set_used_insn_alternative (rtx, int); | |
304 | extern void lra_set_used_insn_alternative_by_uid (int, int); | |
305 | ||
306 | extern void lra_invalidate_insn_regno_info (rtx); | |
307 | extern void lra_update_insn_regno_info (rtx); | |
308 | extern struct lra_insn_reg *lra_get_insn_regs (int); | |
309 | ||
310 | extern void lra_free_copies (void); | |
311 | extern void lra_create_copy (int, int, int); | |
312 | extern lra_copy_t lra_get_copy (int); | |
313 | extern bool lra_former_scratch_p (int); | |
314 | extern bool lra_former_scratch_operand_p (rtx, int); | |
315 | ||
f681cf95 | 316 | extern int lra_new_regno_start; |
55a2c322 VM |
317 | extern int lra_constraint_new_regno_start; |
318 | extern bitmap_head lra_inheritance_pseudos; | |
319 | extern bitmap_head lra_split_regs; | |
2b778c9d | 320 | extern bitmap_head lra_subreg_reload_pseudos; |
55a2c322 VM |
321 | extern bitmap_head lra_optional_reload_pseudos; |
322 | extern int lra_constraint_new_insn_uid_start; | |
323 | ||
324 | /* lra-constraints.c: */ | |
325 | ||
4c2b2d79 | 326 | extern void lra_init_equiv (void); |
55a2c322 VM |
327 | extern int lra_constraint_offset (int, enum machine_mode); |
328 | ||
329 | extern int lra_constraint_iter; | |
330 | extern int lra_constraint_iter_after_spill; | |
331 | extern bool lra_risky_transformations_p; | |
332 | extern int lra_inheritance_iter; | |
333 | extern int lra_undo_inheritance_iter; | |
334 | extern bool lra_constraints (bool); | |
335 | extern void lra_constraints_init (void); | |
336 | extern void lra_constraints_finish (void); | |
337 | extern void lra_inheritance (void); | |
338 | extern bool lra_undo_inheritance (void); | |
339 | ||
340 | /* lra-lives.c: */ | |
341 | ||
342 | extern int lra_live_max_point; | |
343 | extern int *lra_point_freq; | |
344 | ||
345 | extern int lra_hard_reg_usage[FIRST_PSEUDO_REGISTER]; | |
346 | ||
347 | extern int lra_live_range_iter; | |
348 | extern void lra_create_live_ranges (bool); | |
349 | extern lra_live_range_t lra_copy_live_range_list (lra_live_range_t); | |
350 | extern lra_live_range_t lra_merge_live_ranges (lra_live_range_t, | |
351 | lra_live_range_t); | |
352 | extern bool lra_intersected_live_ranges_p (lra_live_range_t, | |
353 | lra_live_range_t); | |
354 | extern void lra_print_live_range_list (FILE *, lra_live_range_t); | |
7b3b6ae4 LC |
355 | extern void debug (lra_live_range &ref); |
356 | extern void debug (lra_live_range *ptr); | |
55a2c322 VM |
357 | extern void lra_debug_live_range_list (lra_live_range_t); |
358 | extern void lra_debug_pseudo_live_ranges (int); | |
359 | extern void lra_debug_live_ranges (void); | |
360 | extern void lra_clear_live_ranges (void); | |
361 | extern void lra_live_ranges_init (void); | |
362 | extern void lra_live_ranges_finish (void); | |
363 | extern void lra_setup_reload_pseudo_preferenced_hard_reg (int, int, int); | |
364 | ||
365 | /* lra-assigns.c: */ | |
366 | ||
367 | extern void lra_setup_reg_renumber (int, int, bool); | |
368 | extern bool lra_assign (void); | |
369 | ||
370 | ||
371 | /* lra-coalesce.c: */ | |
372 | ||
373 | extern int lra_coalesce_iter; | |
374 | extern bool lra_coalesce (void); | |
375 | ||
376 | /* lra-spills.c: */ | |
377 | ||
378 | extern bool lra_need_for_spills_p (void); | |
379 | extern void lra_spill (void); | |
c5cd5a7e | 380 | extern void lra_final_code_change (void); |
55a2c322 VM |
381 | |
382 | ||
383 | /* lra-elimination.c: */ | |
384 | ||
385 | extern void lra_debug_elim_table (void); | |
386 | extern int lra_get_elimination_hard_regno (int); | |
8d49e7ef VM |
387 | extern rtx lra_eliminate_regs_1 (rtx, rtx, enum machine_mode, bool, bool, bool); |
388 | extern void lra_eliminate (bool, bool); | |
55a2c322 VM |
389 | |
390 | extern void lra_eliminate_reg_if_possible (rtx *); | |
391 | ||
392 | \f | |
393 | ||
a2d0d374 VM |
394 | /* Return the hard register which given pseudo REGNO assigned to. |
395 | Negative value means that the register got memory or we don't know | |
396 | allocation yet. */ | |
397 | static inline int | |
398 | lra_get_regno_hard_regno (int regno) | |
399 | { | |
400 | resize_reg_info (); | |
401 | return reg_renumber[regno]; | |
402 | } | |
403 | ||
404 | /* Change class of pseudo REGNO to NEW_CLASS. Print info about it | |
405 | using TITLE. Output a new line if NL_P. */ | |
406 | static void inline | |
407 | lra_change_class (int regno, enum reg_class new_class, | |
408 | const char *title, bool nl_p) | |
409 | { | |
410 | lra_assert (regno >= FIRST_PSEUDO_REGISTER); | |
411 | if (lra_dump_file != NULL) | |
412 | fprintf (lra_dump_file, "%s class %s for r%d", | |
413 | title, reg_class_names[new_class], regno); | |
414 | setup_reg_classes (regno, new_class, NO_REGS, new_class); | |
415 | if (lra_dump_file != NULL && nl_p) | |
416 | fprintf (lra_dump_file, "\n"); | |
417 | } | |
418 | ||
55a2c322 VM |
419 | /* Update insn operands which are duplication of NOP operand. The |
420 | insn is represented by its LRA internal representation ID. */ | |
421 | static inline void | |
422 | lra_update_dup (lra_insn_recog_data_t id, int nop) | |
423 | { | |
424 | int i; | |
425 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
426 | ||
427 | for (i = 0; i < static_id->n_dups; i++) | |
428 | if (static_id->dup_num[i] == nop) | |
429 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
430 | } | |
431 | ||
432 | /* Process operator duplications in insn with ID. We do it after the | |
433 | operands processing. Generally speaking, we could do this probably | |
434 | simultaneously with operands processing because a common practice | |
435 | is to enumerate the operators after their operands. */ | |
436 | static inline void | |
437 | lra_update_operator_dups (lra_insn_recog_data_t id) | |
438 | { | |
439 | int i; | |
440 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
441 | ||
442 | for (i = 0; i < static_id->n_dups; i++) | |
443 | { | |
444 | int ndup = static_id->dup_num[i]; | |
f4eafc30 | 445 | |
55a2c322 VM |
446 | if (static_id->operand[ndup].is_operator) |
447 | *id->dup_loc[i] = *id->operand_loc[ndup]; | |
448 | } | |
449 | } | |
450 | ||
451 | /* Return info about INSN. Set up the info if it is not done yet. */ | |
452 | static inline lra_insn_recog_data_t | |
453 | lra_get_insn_recog_data (rtx insn) | |
454 | { | |
455 | lra_insn_recog_data_t data; | |
456 | unsigned int uid = INSN_UID (insn); | |
457 | ||
458 | if (lra_insn_recog_data_len > (int) uid | |
459 | && (data = lra_insn_recog_data[uid]) != NULL) | |
460 | { | |
461 | /* Check that we did not change insn without updating the insn | |
462 | info. */ | |
463 | lra_assert (data->insn == insn | |
464 | && (INSN_CODE (insn) < 0 | |
465 | || data->icode == INSN_CODE (insn))); | |
466 | return data; | |
467 | } | |
468 | return lra_set_insn_recog_data (insn); | |
469 | } | |
470 | ||
d70a81dd SC |
471 | /* Update offset from pseudos with VAL by INCR. */ |
472 | static inline void | |
473 | lra_update_reg_val_offset (int val, int incr) | |
474 | { | |
475 | int i; | |
476 | ||
477 | for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
478 | { | |
479 | if (lra_reg_info[i].val == val) | |
480 | lra_reg_info[i].offset += incr; | |
481 | } | |
482 | } | |
483 | ||
484 | /* Return true if register content is equal to VAL with OFFSET. */ | |
485 | static inline bool | |
486 | lra_reg_val_equal_p (int regno, int val, int offset) | |
487 | { | |
488 | if (lra_reg_info[regno].val == val | |
489 | && lra_reg_info[regno].offset == offset) | |
490 | return true; | |
491 | ||
492 | return false; | |
493 | } | |
494 | ||
495 | /* Assign value of register FROM to TO. */ | |
496 | static inline void | |
497 | lra_assign_reg_val (int from, int to) | |
498 | { | |
499 | lra_reg_info[to].val = lra_reg_info[from].val; | |
500 | lra_reg_info[to].offset = lra_reg_info[from].offset; | |
501 | } |