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55a2c322 | 1 | /* Local Register Allocator (LRA) intercommunication header file. |
99dee823 | 2 | Copyright (C) 2010-2021 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
f1717f8d KC |
21 | #ifndef GCC_LRA_INT_H |
22 | #define GCC_LRA_INT_H | |
23 | ||
a202e609 | 24 | #define lra_assert(c) gcc_checking_assert (c) |
55a2c322 VM |
25 | |
26 | /* The parameter used to prevent infinite reloading for an insn. Each | |
27 | insn operands might require a reload and, if it is a memory, its | |
28 | base and index registers might require a reload too. */ | |
29 | #define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3) | |
30 | ||
55a2c322 VM |
31 | typedef struct lra_live_range *lra_live_range_t; |
32 | ||
33 | /* The structure describes program points where a given pseudo lives. | |
34 | The live ranges can be used to find conflicts with other pseudos. | |
35 | If the live ranges of two pseudos are intersected, the pseudos are | |
36 | in conflict. */ | |
37 | struct lra_live_range | |
38 | { | |
39 | /* Pseudo regno whose live range is described by given | |
40 | structure. */ | |
41 | int regno; | |
42 | /* Program point range. */ | |
43 | int start, finish; | |
44 | /* Next structure describing program points where the pseudo | |
45 | lives. */ | |
46 | lra_live_range_t next; | |
47 | /* Pointer to structures with the same start. */ | |
48 | lra_live_range_t start_next; | |
49 | }; | |
50 | ||
51 | typedef struct lra_copy *lra_copy_t; | |
52 | ||
53 | /* Copy between pseudos which affects assigning hard registers. */ | |
54 | struct lra_copy | |
55 | { | |
56 | /* True if regno1 is the destination of the copy. */ | |
57 | bool regno1_dest_p; | |
58 | /* Execution frequency of the copy. */ | |
59 | int freq; | |
60 | /* Pseudos connected by the copy. REGNO1 < REGNO2. */ | |
61 | int regno1, regno2; | |
62 | /* Next copy with correspondingly REGNO1 and REGNO2. */ | |
63 | lra_copy_t regno1_next, regno2_next; | |
64 | }; | |
65 | ||
66 | /* Common info about a register (pseudo or hard register). */ | |
6c1dae73 | 67 | class lra_reg |
55a2c322 | 68 | { |
6c1dae73 | 69 | public: |
55a2c322 VM |
70 | /* Bitmap of UIDs of insns (including debug insns) referring the |
71 | reg. */ | |
72 | bitmap_head insn_bitmap; | |
73 | /* The following fields are defined only for pseudos. */ | |
74 | /* Hard registers with which the pseudo conflicts. */ | |
75 | HARD_REG_SET conflict_hard_regs; | |
76 | /* We assign hard registers to reload pseudos which can occur in few | |
77 | places. So two hard register preferences are enough for them. | |
78 | The following fields define the preferred hard registers. If | |
79 | there are no such hard registers the first field value is | |
80 | negative. If there is only one preferred hard register, the 2nd | |
81 | field is negative. */ | |
82 | int preferred_hard_regno1, preferred_hard_regno2; | |
83 | /* Profits to use the corresponding preferred hard registers. If | |
84 | the both hard registers defined, the first hard register has not | |
85 | less profit than the second one. */ | |
86 | int preferred_hard_regno_profit1, preferred_hard_regno_profit2; | |
87 | #ifdef STACK_REGS | |
88 | /* True if the pseudo should not be assigned to a stack register. */ | |
89 | bool no_stack_p; | |
90 | #endif | |
55a2c322 VM |
91 | /* Number of references and execution frequencies of the register in |
92 | *non-debug* insns. */ | |
93 | int nrefs, freq; | |
94 | int last_reload; | |
8a8330b7 VM |
95 | /* rtx used to undo the inheritance. It can be non-null only |
96 | between subsequent inheritance and undo inheritance passes. */ | |
97 | rtx restore_rtx; | |
55a2c322 VM |
98 | /* Value holding by register. If the pseudos have the same value |
99 | they do not conflict. */ | |
100 | int val; | |
d70a81dd | 101 | /* Offset from relative eliminate register to pesudo reg. */ |
73ca989c | 102 | poly_int64 offset; |
55a2c322 VM |
103 | /* These members are set up in lra-lives.c and updated in |
104 | lra-coalesce.c. */ | |
105 | /* The biggest size mode in which each pseudo reg is referred in | |
106 | whole function (possibly via subreg). */ | |
ef4bddc2 | 107 | machine_mode biggest_mode; |
55a2c322 VM |
108 | /* Live ranges of the pseudo. */ |
109 | lra_live_range_t live_ranges; | |
110 | /* This member is set up in lra-lives.c for subsequent | |
111 | assignments. */ | |
112 | lra_copy_t copies; | |
113 | }; | |
114 | ||
115 | /* References to the common info about each register. */ | |
99b1c316 | 116 | extern class lra_reg *lra_reg_info; |
55a2c322 | 117 | |
54178a01 TV |
118 | extern HARD_REG_SET hard_regs_spilled_into; |
119 | ||
55a2c322 VM |
120 | /* Static info about each insn operand (common for all insns with the |
121 | same ICODE). Warning: if the structure definition is changed, the | |
122 | initializer for debug_operand_data in lra.c should be changed | |
123 | too. */ | |
124 | struct lra_operand_data | |
125 | { | |
126 | /* The machine description constraint string of the operand. */ | |
127 | const char *constraint; | |
584898ee VM |
128 | /* Alternatives for which early_clobber can be true. */ |
129 | alternative_mask early_clobber_alts; | |
55a2c322 VM |
130 | /* It is taken only from machine description (which is different |
131 | from recog_data.operand_mode) and can be of VOIDmode. */ | |
132 | ENUM_BITFIELD(machine_mode) mode : 16; | |
133 | /* The type of the operand (in/out/inout). */ | |
134 | ENUM_BITFIELD (op_type) type : 8; | |
135 | /* Through if accessed through STRICT_LOW. */ | |
136 | unsigned int strict_low : 1; | |
137 | /* True if the operand is an operator. */ | |
138 | unsigned int is_operator : 1; | |
55a2c322 VM |
139 | /* True if the operand is an address. */ |
140 | unsigned int is_address : 1; | |
141 | }; | |
142 | ||
143 | /* Info about register occurrence in an insn. */ | |
144 | struct lra_insn_reg | |
145 | { | |
584898ee VM |
146 | /* Alternatives for which early_clobber can be true. */ |
147 | alternative_mask early_clobber_alts; | |
55a2c322 VM |
148 | /* The biggest mode through which the insn refers to the register |
149 | occurrence (remember the register can be accessed through a | |
150 | subreg in the insn). */ | |
151 | ENUM_BITFIELD(machine_mode) biggest_mode : 16; | |
152 | /* The type of the corresponding operand which is the register. */ | |
153 | ENUM_BITFIELD (op_type) type : 8; | |
154 | /* True if the reg is accessed through a subreg and the subreg is | |
155 | just a part of the register. */ | |
156 | unsigned int subreg_p : 1; | |
55a2c322 VM |
157 | /* The corresponding regno of the register. */ |
158 | int regno; | |
159 | /* Next reg info of the same insn. */ | |
160 | struct lra_insn_reg *next; | |
161 | }; | |
162 | ||
163 | /* Static part (common info for insns with the same ICODE) of LRA | |
164 | internal insn info. It exists in at most one exemplar for each | |
165 | non-negative ICODE. There is only one exception. Each asm insn has | |
166 | own structure. Warning: if the structure definition is changed, | |
167 | the initializer for debug_insn_static_data in lra.c should be | |
168 | changed too. */ | |
169 | struct lra_static_insn_data | |
170 | { | |
171 | /* Static info about each insn operand. */ | |
172 | struct lra_operand_data *operand; | |
173 | /* Each duplication refers to the number of the corresponding | |
174 | operand which is duplicated. */ | |
175 | int *dup_num; | |
176 | /* The number of an operand marked as commutative, -1 otherwise. */ | |
177 | int commutative; | |
178 | /* Number of operands, duplications, and alternatives of the | |
179 | insn. */ | |
180 | char n_operands; | |
181 | char n_dups; | |
182 | char n_alternatives; | |
183 | /* Insns in machine description (or clobbers in asm) may contain | |
184 | explicit hard regs which are not operands. The following list | |
185 | describes such hard registers. */ | |
186 | struct lra_insn_reg *hard_regs; | |
187 | /* Array [n_alternatives][n_operand] of static constraint info for | |
188 | given operand in given alternative. This info can be changed if | |
189 | the target reg info is changed. */ | |
0c331756 | 190 | const struct operand_alternative *operand_alternative; |
55a2c322 VM |
191 | }; |
192 | ||
7874b7c5 VM |
193 | /* Negative insn alternative numbers used for special cases. */ |
194 | #define LRA_UNKNOWN_ALT -1 | |
195 | #define LRA_NON_CLOBBERED_ALT -2 | |
196 | ||
55a2c322 VM |
197 | /* LRA internal info about an insn (LRA internal insn |
198 | representation). */ | |
6c1dae73 | 199 | class lra_insn_recog_data |
55a2c322 | 200 | { |
6c1dae73 | 201 | public: |
55a2c322 VM |
202 | /* The insn code. */ |
203 | int icode; | |
7874b7c5 VM |
204 | /* The alternative should be used for the insn, LRA_UNKNOWN_ALT if |
205 | unknown, or we should assume any alternative, or the insn is a | |
206 | debug insn. LRA_NON_CLOBBERED_ALT means ignoring any earlier | |
207 | clobbers for the insn. */ | |
8d49e7ef VM |
208 | int used_insn_alternative; |
209 | /* SP offset before the insn relative to one at the func start. */ | |
73ca989c | 210 | poly_int64 sp_offset; |
55a2c322 | 211 | /* The insn itself. */ |
cfa434f6 | 212 | rtx_insn *insn; |
55a2c322 VM |
213 | /* Common data for insns with the same ICODE. Asm insns (their |
214 | ICODE is negative) do not share such structures. */ | |
215 | struct lra_static_insn_data *insn_static_data; | |
216 | /* Two arrays of size correspondingly equal to the operand and the | |
217 | duplication numbers: */ | |
218 | rtx **operand_loc; /* The operand locations, NULL if no operands. */ | |
219 | rtx **dup_loc; /* The dup locations, NULL if no dups. */ | |
9d86e84e VM |
220 | /* Number of hard registers implicitly used/clobbered in given call |
221 | insn. The value can be NULL or points to array of the hard | |
222 | register numbers ending with a negative value. To differ | |
223 | clobbered and used hard regs, clobbered hard regs are incremented | |
224 | by FIRST_PSEUDO_REGISTER. */ | |
55a2c322 | 225 | int *arg_hard_regs; |
9840b2fa RS |
226 | /* Cached value of get_preferred_alternatives. */ |
227 | alternative_mask preferred_alternatives; | |
55a2c322 VM |
228 | /* The following member value is always NULL for a debug insn. */ |
229 | struct lra_insn_reg *regs; | |
230 | }; | |
231 | ||
99b1c316 | 232 | typedef class lra_insn_recog_data *lra_insn_recog_data_t; |
55a2c322 | 233 | |
c5cd5a7e VM |
234 | /* Whether the clobber is used temporary in LRA. */ |
235 | #define LRA_TEMP_CLOBBER_P(x) \ | |
236 | (RTL_FLAG_CHECK1 ("TEMP_CLOBBER_P", (x), CLOBBER)->unchanging) | |
237 | ||
821b7577 VM |
238 | /* Cost factor for each additional reload and maximal cost reject for |
239 | insn reloads. One might ask about such strange numbers. Their | |
240 | values occurred historically from former reload pass. */ | |
241 | #define LRA_LOSER_COST_FACTOR 6 | |
242 | #define LRA_MAX_REJECT 600 | |
243 | ||
f54437d5 VM |
244 | /* Maximum allowed number of assignment pass iterations after the |
245 | latest spill pass when any former reload pseudo was spilled. It is | |
246 | for preventing LRA cycling in a bug case. */ | |
247 | #define LRA_MAX_ASSIGNMENT_ITERATION_NUMBER 30 | |
8e3a4869 VM |
248 | |
249 | /* The maximal number of inheritance/split passes in LRA. It should | |
250 | be more 1 in order to perform caller saves transformations and much | |
251 | less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many | |
252 | as permitted constraint passes in some complicated cases. The | |
253 | first inheritance/split pass has a biggest impact on generated code | |
254 | quality. Each subsequent affects generated code in less degree. | |
255 | For example, the 3rd pass does not change generated SPEC2000 code | |
256 | at all on x86-64. */ | |
257 | #define LRA_MAX_INHERITANCE_PASSES 2 | |
258 | ||
259 | #if LRA_MAX_INHERITANCE_PASSES <= 0 \ | |
f54437d5 | 260 | || LRA_MAX_INHERITANCE_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8 |
8e3a4869 VM |
261 | #error wrong LRA_MAX_INHERITANCE_PASSES value |
262 | #endif | |
263 | ||
94446928 VM |
264 | /* Analogous macro to the above one but for rematerialization. */ |
265 | #define LRA_MAX_REMATERIALIZATION_PASSES 2 | |
266 | ||
267 | #if LRA_MAX_REMATERIALIZATION_PASSES <= 0 \ | |
268 | || LRA_MAX_REMATERIALIZATION_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8 | |
269 | #error wrong LRA_MAX_REMATERIALIZATION_PASSES value | |
270 | #endif | |
271 | ||
55a2c322 VM |
272 | /* lra.c: */ |
273 | ||
274 | extern FILE *lra_dump_file; | |
275 | ||
15a47f43 | 276 | extern bool lra_hard_reg_split_p; |
11067dee | 277 | extern bool lra_asm_error_p; |
55a2c322 VM |
278 | extern bool lra_reg_spill_p; |
279 | ||
280 | extern HARD_REG_SET lra_no_alloc_regs; | |
281 | ||
282 | extern int lra_insn_recog_data_len; | |
283 | extern lra_insn_recog_data_t *lra_insn_recog_data; | |
284 | ||
285 | extern int lra_curr_reload_num; | |
286 | ||
8160cd3e | 287 | extern void lra_dump_bitmap_with_title (const char *, bitmap, int); |
8a8330b7 | 288 | extern hashval_t lra_rtx_hash (rtx x); |
cfa434f6 | 289 | extern void lra_push_insn (rtx_insn *); |
55a2c322 | 290 | extern void lra_push_insn_by_uid (unsigned int); |
cfa434f6 DM |
291 | extern void lra_push_insn_and_update_insn_regno_info (rtx_insn *); |
292 | extern rtx_insn *lra_pop_insn (void); | |
55a2c322 VM |
293 | extern unsigned int lra_insn_stack_length (void); |
294 | ||
ef4bddc2 | 295 | extern rtx lra_create_new_reg_with_unique_value (machine_mode, rtx, |
55a2c322 VM |
296 | enum reg_class, const char *); |
297 | extern void lra_set_regno_unique_value (int); | |
cfa434f6 DM |
298 | extern void lra_invalidate_insn_data (rtx_insn *); |
299 | extern void lra_set_insn_deleted (rtx_insn *); | |
300 | extern void lra_delete_dead_insn (rtx_insn *); | |
55a2c322 VM |
301 | extern void lra_emit_add (rtx, rtx, rtx); |
302 | extern void lra_emit_move (rtx, rtx); | |
303 | extern void lra_update_dups (lra_insn_recog_data_t, signed char *); | |
304 | ||
cfa434f6 DM |
305 | extern void lra_process_new_insns (rtx_insn *, rtx_insn *, rtx_insn *, |
306 | const char *); | |
55a2c322 | 307 | |
33006d53 | 308 | extern bool lra_substitute_pseudo (rtx *, int, rtx, bool, bool); |
ef87312e | 309 | extern bool lra_substitute_pseudo_within_insn (rtx_insn *, int, rtx, bool); |
8160cd3e | 310 | |
cfa434f6 DM |
311 | extern lra_insn_recog_data_t lra_set_insn_recog_data (rtx_insn *); |
312 | extern lra_insn_recog_data_t lra_update_insn_recog_data (rtx_insn *); | |
313 | extern void lra_set_used_insn_alternative (rtx_insn *, int); | |
55a2c322 VM |
314 | extern void lra_set_used_insn_alternative_by_uid (int, int); |
315 | ||
cfa434f6 DM |
316 | extern void lra_invalidate_insn_regno_info (rtx_insn *); |
317 | extern void lra_update_insn_regno_info (rtx_insn *); | |
55a2c322 VM |
318 | extern struct lra_insn_reg *lra_get_insn_regs (int); |
319 | ||
320 | extern void lra_free_copies (void); | |
321 | extern void lra_create_copy (int, int, int); | |
322 | extern lra_copy_t lra_get_copy (int); | |
55a2c322 | 323 | |
f681cf95 | 324 | extern int lra_new_regno_start; |
55a2c322 | 325 | extern int lra_constraint_new_regno_start; |
8fd827b8 | 326 | extern int lra_bad_spill_regno_start; |
68ba1039 | 327 | extern rtx lra_pmode_pseudo; |
55a2c322 VM |
328 | extern bitmap_head lra_inheritance_pseudos; |
329 | extern bitmap_head lra_split_regs; | |
2b778c9d | 330 | extern bitmap_head lra_subreg_reload_pseudos; |
55a2c322 | 331 | extern bitmap_head lra_optional_reload_pseudos; |
55a2c322 VM |
332 | |
333 | /* lra-constraints.c: */ | |
334 | ||
4c2b2d79 | 335 | extern void lra_init_equiv (void); |
ef4bddc2 | 336 | extern int lra_constraint_offset (int, machine_mode); |
55a2c322 VM |
337 | |
338 | extern int lra_constraint_iter; | |
7436a1c6 | 339 | extern bool check_and_force_assignment_correctness_p; |
55a2c322 VM |
340 | extern int lra_inheritance_iter; |
341 | extern int lra_undo_inheritance_iter; | |
d9cf932c | 342 | extern bool lra_constrain_insn (rtx_insn *); |
55a2c322 VM |
343 | extern bool lra_constraints (bool); |
344 | extern void lra_constraints_init (void); | |
345 | extern void lra_constraints_finish (void); | |
6027ea4c | 346 | extern bool spill_hard_reg_in_range (int, enum reg_class, rtx_insn *, rtx_insn *); |
55a2c322 VM |
347 | extern void lra_inheritance (void); |
348 | extern bool lra_undo_inheritance (void); | |
349 | ||
350 | /* lra-lives.c: */ | |
351 | ||
352 | extern int lra_live_max_point; | |
353 | extern int *lra_point_freq; | |
354 | ||
355 | extern int lra_hard_reg_usage[FIRST_PSEUDO_REGISTER]; | |
356 | ||
357 | extern int lra_live_range_iter; | |
4ab74a01 | 358 | extern void lra_create_live_ranges (bool, bool); |
55a2c322 VM |
359 | extern lra_live_range_t lra_copy_live_range_list (lra_live_range_t); |
360 | extern lra_live_range_t lra_merge_live_ranges (lra_live_range_t, | |
361 | lra_live_range_t); | |
362 | extern bool lra_intersected_live_ranges_p (lra_live_range_t, | |
363 | lra_live_range_t); | |
364 | extern void lra_print_live_range_list (FILE *, lra_live_range_t); | |
7b3b6ae4 LC |
365 | extern void debug (lra_live_range &ref); |
366 | extern void debug (lra_live_range *ptr); | |
55a2c322 VM |
367 | extern void lra_debug_live_range_list (lra_live_range_t); |
368 | extern void lra_debug_pseudo_live_ranges (int); | |
369 | extern void lra_debug_live_ranges (void); | |
370 | extern void lra_clear_live_ranges (void); | |
371 | extern void lra_live_ranges_init (void); | |
372 | extern void lra_live_ranges_finish (void); | |
373 | extern void lra_setup_reload_pseudo_preferenced_hard_reg (int, int, int); | |
374 | ||
375 | /* lra-assigns.c: */ | |
376 | ||
f54437d5 VM |
377 | extern int lra_assignment_iter; |
378 | extern int lra_assignment_iter_after_spill; | |
55a2c322 | 379 | extern void lra_setup_reg_renumber (int, int, bool); |
6027ea4c VM |
380 | extern bool lra_assign (bool &); |
381 | extern bool lra_split_hard_reg_for (void); | |
55a2c322 VM |
382 | |
383 | /* lra-coalesce.c: */ | |
384 | ||
385 | extern int lra_coalesce_iter; | |
386 | extern bool lra_coalesce (void); | |
387 | ||
388 | /* lra-spills.c: */ | |
389 | ||
23e0f4c3 | 390 | extern bool lra_need_for_scratch_reg_p (void); |
55a2c322 VM |
391 | extern bool lra_need_for_spills_p (void); |
392 | extern void lra_spill (void); | |
c5cd5a7e | 393 | extern void lra_final_code_change (void); |
55a2c322 | 394 | |
d9cf932c VM |
395 | /* lra-remat.c: */ |
396 | ||
94446928 | 397 | extern int lra_rematerialization_iter; |
d9cf932c | 398 | extern bool lra_remat (void); |
55a2c322 VM |
399 | |
400 | /* lra-elimination.c: */ | |
401 | ||
402 | extern void lra_debug_elim_table (void); | |
403 | extern int lra_get_elimination_hard_regno (int); | |
d9cf932c | 404 | extern rtx lra_eliminate_regs_1 (rtx_insn *, rtx, machine_mode, |
73ca989c RS |
405 | bool, bool, poly_int64, bool); |
406 | extern void eliminate_regs_in_insn (rtx_insn *insn, bool, bool, poly_int64); | |
8d49e7ef | 407 | extern void lra_eliminate (bool, bool); |
55a2c322 VM |
408 | |
409 | extern void lra_eliminate_reg_if_possible (rtx *); | |
410 | ||
411 | \f | |
412 | ||
a2d0d374 VM |
413 | /* Return the hard register which given pseudo REGNO assigned to. |
414 | Negative value means that the register got memory or we don't know | |
415 | allocation yet. */ | |
416 | static inline int | |
417 | lra_get_regno_hard_regno (int regno) | |
418 | { | |
419 | resize_reg_info (); | |
420 | return reg_renumber[regno]; | |
421 | } | |
422 | ||
423 | /* Change class of pseudo REGNO to NEW_CLASS. Print info about it | |
424 | using TITLE. Output a new line if NL_P. */ | |
425 | static void inline | |
426 | lra_change_class (int regno, enum reg_class new_class, | |
427 | const char *title, bool nl_p) | |
428 | { | |
429 | lra_assert (regno >= FIRST_PSEUDO_REGISTER); | |
430 | if (lra_dump_file != NULL) | |
431 | fprintf (lra_dump_file, "%s class %s for r%d", | |
432 | title, reg_class_names[new_class], regno); | |
433 | setup_reg_classes (regno, new_class, NO_REGS, new_class); | |
434 | if (lra_dump_file != NULL && nl_p) | |
435 | fprintf (lra_dump_file, "\n"); | |
436 | } | |
437 | ||
55a2c322 VM |
438 | /* Update insn operands which are duplication of NOP operand. The |
439 | insn is represented by its LRA internal representation ID. */ | |
440 | static inline void | |
441 | lra_update_dup (lra_insn_recog_data_t id, int nop) | |
442 | { | |
443 | int i; | |
444 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
445 | ||
446 | for (i = 0; i < static_id->n_dups; i++) | |
447 | if (static_id->dup_num[i] == nop) | |
448 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
449 | } | |
450 | ||
451 | /* Process operator duplications in insn with ID. We do it after the | |
452 | operands processing. Generally speaking, we could do this probably | |
453 | simultaneously with operands processing because a common practice | |
454 | is to enumerate the operators after their operands. */ | |
455 | static inline void | |
456 | lra_update_operator_dups (lra_insn_recog_data_t id) | |
457 | { | |
458 | int i; | |
459 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
460 | ||
461 | for (i = 0; i < static_id->n_dups; i++) | |
462 | { | |
463 | int ndup = static_id->dup_num[i]; | |
f4eafc30 | 464 | |
55a2c322 VM |
465 | if (static_id->operand[ndup].is_operator) |
466 | *id->dup_loc[i] = *id->operand_loc[ndup]; | |
467 | } | |
468 | } | |
469 | ||
470 | /* Return info about INSN. Set up the info if it is not done yet. */ | |
471 | static inline lra_insn_recog_data_t | |
cfa434f6 | 472 | lra_get_insn_recog_data (rtx_insn *insn) |
55a2c322 VM |
473 | { |
474 | lra_insn_recog_data_t data; | |
475 | unsigned int uid = INSN_UID (insn); | |
476 | ||
477 | if (lra_insn_recog_data_len > (int) uid | |
478 | && (data = lra_insn_recog_data[uid]) != NULL) | |
479 | { | |
480 | /* Check that we did not change insn without updating the insn | |
481 | info. */ | |
482 | lra_assert (data->insn == insn | |
483 | && (INSN_CODE (insn) < 0 | |
484 | || data->icode == INSN_CODE (insn))); | |
485 | return data; | |
486 | } | |
487 | return lra_set_insn_recog_data (insn); | |
488 | } | |
489 | ||
d70a81dd SC |
490 | /* Update offset from pseudos with VAL by INCR. */ |
491 | static inline void | |
73ca989c | 492 | lra_update_reg_val_offset (int val, poly_int64 incr) |
d70a81dd SC |
493 | { |
494 | int i; | |
495 | ||
496 | for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
497 | { | |
498 | if (lra_reg_info[i].val == val) | |
499 | lra_reg_info[i].offset += incr; | |
500 | } | |
501 | } | |
502 | ||
503 | /* Return true if register content is equal to VAL with OFFSET. */ | |
504 | static inline bool | |
73ca989c | 505 | lra_reg_val_equal_p (int regno, int val, poly_int64 offset) |
d70a81dd SC |
506 | { |
507 | if (lra_reg_info[regno].val == val | |
73ca989c | 508 | && known_eq (lra_reg_info[regno].offset, offset)) |
d70a81dd SC |
509 | return true; |
510 | ||
511 | return false; | |
512 | } | |
513 | ||
514 | /* Assign value of register FROM to TO. */ | |
515 | static inline void | |
516 | lra_assign_reg_val (int from, int to) | |
517 | { | |
518 | lra_reg_info[to].val = lra_reg_info[from].val; | |
519 | lra_reg_info[to].offset = lra_reg_info[from].offset; | |
520 | } | |
f1717f8d KC |
521 | |
522 | #endif /* GCC_LRA_INT_H */ |