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55a2c322 | 1 | /* Code for RTL transformations to satisfy insn constraints. |
aeee4812 | 2 | Copyright (C) 2010-2023 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
f4eafc30 | 89 | ... => |
55a2c322 VM |
90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
c7131fb2 | 112 | #include "backend.h" |
57688950 | 113 | #include "hooks.h" |
957060b5 | 114 | #include "target.h" |
55a2c322 | 115 | #include "rtl.h" |
957060b5 AM |
116 | #include "tree.h" |
117 | #include "predict.h" | |
c7131fb2 | 118 | #include "df.h" |
4d0cdd0c | 119 | #include "memmodel.h" |
55a2c322 | 120 | #include "tm_p.h" |
957060b5 AM |
121 | #include "expmed.h" |
122 | #include "optabs.h" | |
55a2c322 | 123 | #include "regs.h" |
957060b5 | 124 | #include "ira.h" |
55a2c322 VM |
125 | #include "recog.h" |
126 | #include "output.h" | |
127 | #include "addresses.h" | |
55a2c322 | 128 | #include "expr.h" |
60393bbc | 129 | #include "cfgrtl.h" |
55a2c322 | 130 | #include "rtl-error.h" |
c7131fb2 | 131 | #include "lra.h" |
55a2c322 | 132 | #include "lra-int.h" |
013a8899 | 133 | #include "print-rtl.h" |
6ee2cc70 | 134 | #include "function-abi.h" |
6b3034ea | 135 | #include "rtl-iter.h" |
55a2c322 VM |
136 | |
137 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
138 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
139 | reload insns. */ | |
140 | static int bb_reload_num; | |
141 | ||
2c62cbaa VM |
142 | /* The current insn being processed and corresponding its single set |
143 | (NULL otherwise), its data (basic block, the insn data, the insn | |
144 | static data, and the mode of each operand). */ | |
cfa434f6 | 145 | static rtx_insn *curr_insn; |
2c62cbaa | 146 | static rtx curr_insn_set; |
55a2c322 VM |
147 | static basic_block curr_bb; |
148 | static lra_insn_recog_data_t curr_id; | |
149 | static struct lra_static_insn_data *curr_static_id; | |
ef4bddc2 | 150 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
895ff86f VM |
151 | /* Mode of the register substituted by its equivalence with VOIDmode |
152 | (e.g. constant) and whose subreg is given operand of the current | |
153 | insn. VOIDmode in all other cases. */ | |
154 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
55a2c322 VM |
155 | |
156 | \f | |
157 | ||
158 | /* Start numbers for new registers and insns at the current constraints | |
159 | pass start. */ | |
160 | static int new_regno_start; | |
161 | static int new_insn_uid_start; | |
162 | ||
277f65de RS |
163 | /* If LOC is nonnull, strip any outer subreg from it. */ |
164 | static inline rtx * | |
165 | strip_subreg (rtx *loc) | |
166 | { | |
167 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
168 | } | |
169 | ||
55a2c322 VM |
170 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
171 | register, use a hard register from its allocno class. */ | |
172 | static int | |
173 | get_try_hard_regno (int regno) | |
174 | { | |
175 | int hard_regno; | |
176 | enum reg_class rclass; | |
177 | ||
178 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
179 | hard_regno = lra_get_regno_hard_regno (regno); | |
180 | if (hard_regno >= 0) | |
181 | return hard_regno; | |
182 | rclass = lra_get_allocno_class (regno); | |
183 | if (rclass == NO_REGS) | |
184 | return -1; | |
185 | return ira_class_hard_regs[rclass][0]; | |
186 | } | |
187 | ||
265a749f VM |
188 | /* Return the hard regno of X after removing its subreg. If X is not a |
189 | register or a subreg of a register, return -1. If X is a pseudo, use its | |
190 | assignment. If X is a hard regno, return the final hard regno which will be | |
191 | after elimination. */ | |
55a2c322 | 192 | static int |
265a749f | 193 | get_hard_regno (rtx x) |
55a2c322 VM |
194 | { |
195 | rtx reg; | |
1686923c | 196 | int hard_regno; |
55a2c322 VM |
197 | |
198 | reg = x; | |
9d0a9bb4 | 199 | if (SUBREG_P (x)) |
55a2c322 VM |
200 | reg = SUBREG_REG (x); |
201 | if (! REG_P (reg)) | |
202 | return -1; | |
9d0a9bb4 | 203 | if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) |
55a2c322 VM |
204 | hard_regno = lra_get_regno_hard_regno (hard_regno); |
205 | if (hard_regno < 0) | |
206 | return -1; | |
265a749f | 207 | if (HARD_REGISTER_NUM_P (REGNO (reg))) |
1686923c | 208 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
9d0a9bb4 | 209 | if (SUBREG_P (x)) |
1686923c BE |
210 | hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), |
211 | SUBREG_BYTE (x), GET_MODE (x)); | |
212 | return hard_regno; | |
55a2c322 VM |
213 | } |
214 | ||
215 | /* If REGNO is a hard register or has been allocated a hard register, | |
216 | return the class of that register. If REGNO is a reload pseudo | |
217 | created by the current constraints pass, return its allocno class. | |
218 | Return NO_REGS otherwise. */ | |
219 | static enum reg_class | |
220 | get_reg_class (int regno) | |
221 | { | |
222 | int hard_regno; | |
223 | ||
1686923c | 224 | if (! HARD_REGISTER_NUM_P (hard_regno = regno)) |
55a2c322 VM |
225 | hard_regno = lra_get_regno_hard_regno (regno); |
226 | if (hard_regno >= 0) | |
227 | { | |
1686923c | 228 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
55a2c322 VM |
229 | return REGNO_REG_CLASS (hard_regno); |
230 | } | |
231 | if (regno >= new_regno_start) | |
232 | return lra_get_allocno_class (regno); | |
233 | return NO_REGS; | |
234 | } | |
235 | ||
236 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
237 | CL. Use elimination first if REG is a hard register. If REG is a | |
238 | reload pseudo created by this constraints pass, assume that it will | |
239 | be allocated a hard register from its allocno class, but allow that | |
6001db79 RS |
240 | class to be narrowed to CL if it is currently a superset of CL and |
241 | if either: | |
242 | ||
243 | - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or | |
244 | - the instruction we're processing is not a reload move. | |
55a2c322 VM |
245 | |
246 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
247 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
248 | static bool | |
6001db79 RS |
249 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class, |
250 | bool allow_all_reload_class_changes_p = false) | |
55a2c322 VM |
251 | { |
252 | enum reg_class rclass, common_class; | |
ef4bddc2 | 253 | machine_mode reg_mode; |
7f9f83ef | 254 | rtx src; |
55a2c322 VM |
255 | int class_size, hard_regno, nregs, i, j; |
256 | int regno = REGNO (reg); | |
f4eafc30 | 257 | |
55a2c322 VM |
258 | if (new_class != NULL) |
259 | *new_class = NO_REGS; | |
260 | if (regno < FIRST_PSEUDO_REGISTER) | |
261 | { | |
262 | rtx final_reg = reg; | |
263 | rtx *final_loc = &final_reg; | |
f4eafc30 | 264 | |
55a2c322 VM |
265 | lra_eliminate_reg_if_possible (final_loc); |
266 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
267 | } | |
268 | reg_mode = GET_MODE (reg); | |
269 | rclass = get_reg_class (regno); | |
7f9f83ef | 270 | src = curr_insn_set != NULL ? SET_SRC (curr_insn_set) : NULL; |
55a2c322 VM |
271 | if (regno < new_regno_start |
272 | /* Do not allow the constraints for reload instructions to | |
273 | influence the classes of new pseudos. These reloads are | |
274 | typically moves that have many alternatives, and restricting | |
275 | reload pseudos for one alternative may lead to situations | |
276 | where other reload pseudos are no longer allocatable. */ | |
6001db79 RS |
277 | || (!allow_all_reload_class_changes_p |
278 | && INSN_UID (curr_insn) >= new_insn_uid_start | |
7f9f83ef VM |
279 | && src != NULL |
280 | && ((REG_P (src) || MEM_P (src)) | |
281 | || (GET_CODE (src) == SUBREG | |
282 | && (REG_P (SUBREG_REG (src)) || MEM_P (SUBREG_REG (src))))))) | |
55a2c322 VM |
283 | /* When we don't know what class will be used finally for reload |
284 | pseudos, we use ALL_REGS. */ | |
285 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
286 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
287 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
288 | lra_no_alloc_regs))); | |
289 | else | |
290 | { | |
291 | common_class = ira_reg_class_subset[rclass][cl]; | |
292 | if (new_class != NULL) | |
293 | *new_class = common_class; | |
294 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
295 | lra_no_alloc_regs)) | |
296 | return false; | |
297 | /* Check that there are enough allocatable regs. */ | |
298 | class_size = ira_class_hard_regs_num[common_class]; | |
299 | for (i = 0; i < class_size; i++) | |
300 | { | |
301 | hard_regno = ira_class_hard_regs[common_class][i]; | |
ad474626 | 302 | nregs = hard_regno_nregs (hard_regno, reg_mode); |
55a2c322 VM |
303 | if (nregs == 1) |
304 | return true; | |
305 | for (j = 0; j < nregs; j++) | |
f421c426 VM |
306 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
307 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
308 | hard_regno + j)) | |
55a2c322 VM |
309 | break; |
310 | if (j >= nregs) | |
311 | return true; | |
312 | } | |
313 | return false; | |
314 | } | |
315 | } | |
316 | ||
317 | /* Return true if REGNO satisfies a memory constraint. */ | |
318 | static bool | |
319 | in_mem_p (int regno) | |
320 | { | |
321 | return get_reg_class (regno) == NO_REGS; | |
322 | } | |
323 | ||
a953491e RS |
324 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
325 | space AS, and check that each pseudo has the proper kind of hard | |
326 | reg. */ | |
327 | static int | |
ef4bddc2 | 328 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
a953491e RS |
329 | rtx addr, addr_space_t as) |
330 | { | |
331 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
332 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
333 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
334 | return 0; | |
335 | ||
336 | win: | |
337 | return 1; | |
338 | #else | |
339 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
340 | #endif | |
341 | } | |
342 | ||
343 | namespace { | |
344 | /* Temporarily eliminates registers in an address (for the lifetime of | |
345 | the object). */ | |
346 | class address_eliminator { | |
347 | public: | |
348 | address_eliminator (struct address_info *ad); | |
349 | ~address_eliminator (); | |
350 | ||
351 | private: | |
352 | struct address_info *m_ad; | |
353 | rtx *m_base_loc; | |
354 | rtx m_base_reg; | |
355 | rtx *m_index_loc; | |
356 | rtx m_index_reg; | |
357 | }; | |
358 | } | |
359 | ||
360 | address_eliminator::address_eliminator (struct address_info *ad) | |
361 | : m_ad (ad), | |
362 | m_base_loc (strip_subreg (ad->base_term)), | |
363 | m_base_reg (NULL_RTX), | |
364 | m_index_loc (strip_subreg (ad->index_term)), | |
365 | m_index_reg (NULL_RTX) | |
366 | { | |
367 | if (m_base_loc != NULL) | |
368 | { | |
369 | m_base_reg = *m_base_loc; | |
9cb95c07 VM |
370 | /* If we have non-legitimate address which is decomposed not in |
371 | the way we expected, don't do elimination here. In such case | |
372 | the address will be reloaded and elimination will be done in | |
373 | reload insn finally. */ | |
374 | if (REG_P (m_base_reg)) | |
375 | lra_eliminate_reg_if_possible (m_base_loc); | |
a953491e RS |
376 | if (m_ad->base_term2 != NULL) |
377 | *m_ad->base_term2 = *m_ad->base_term; | |
378 | } | |
379 | if (m_index_loc != NULL) | |
380 | { | |
381 | m_index_reg = *m_index_loc; | |
9cb95c07 VM |
382 | if (REG_P (m_index_reg)) |
383 | lra_eliminate_reg_if_possible (m_index_loc); | |
a953491e RS |
384 | } |
385 | } | |
386 | ||
387 | address_eliminator::~address_eliminator () | |
388 | { | |
389 | if (m_base_loc && *m_base_loc != m_base_reg) | |
390 | { | |
391 | *m_base_loc = m_base_reg; | |
392 | if (m_ad->base_term2 != NULL) | |
393 | *m_ad->base_term2 = *m_ad->base_term; | |
394 | } | |
395 | if (m_index_loc && *m_index_loc != m_index_reg) | |
396 | *m_index_loc = m_index_reg; | |
397 | } | |
398 | ||
1aeffdce RS |
399 | /* Return true if the eliminated form of AD is a legitimate target address. |
400 | If OP is a MEM, AD is the address within OP, otherwise OP should be | |
401 | ignored. CONSTRAINT is one constraint that the operand may need | |
402 | to meet. */ | |
a953491e | 403 | static bool |
1aeffdce RS |
404 | valid_address_p (rtx op, struct address_info *ad, |
405 | enum constraint_num constraint) | |
a953491e RS |
406 | { |
407 | address_eliminator eliminator (ad); | |
1aeffdce RS |
408 | |
409 | /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more | |
db8b3e14 | 410 | forgiving than "m". |
411 | Need to extract memory from op for special memory constraint, | |
412 | i.e. bcst_mem_operand in i386 backend. */ | |
413 | if (MEM_P (extract_mem_from_operand (op)) | |
02f2dc44 | 414 | && insn_extra_relaxed_memory_constraint (constraint) |
1aeffdce RS |
415 | && constraint_satisfied_p (op, constraint)) |
416 | return true; | |
417 | ||
a953491e RS |
418 | return valid_address_p (ad->mode, *ad->outer, ad->as); |
419 | } | |
420 | ||
4de7b010 | 421 | /* For special_memory_operand, it could be false for MEM_P (op), |
422 | i.e. bcst_mem_operand in i386 backend. | |
423 | Extract and return real memory operand or op. */ | |
424 | rtx | |
425 | extract_mem_from_operand (rtx op) | |
426 | { | |
427 | for (rtx x = op;; x = XEXP (x, 0)) | |
428 | { | |
429 | if (MEM_P (x)) | |
430 | return x; | |
431 | if (GET_RTX_LENGTH (GET_CODE (x)) != 1 | |
432 | || GET_RTX_FORMAT (GET_CODE (x))[0] != 'e') | |
433 | break; | |
434 | } | |
435 | return op; | |
436 | } | |
437 | ||
a953491e | 438 | /* Return true if the eliminated form of memory reference OP satisfies |
9eb1ca69 | 439 | extra (special) memory constraint CONSTRAINT. */ |
a953491e | 440 | static bool |
777e635f | 441 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
442 | { |
443 | struct address_info ad; | |
4de7b010 | 444 | rtx mem = extract_mem_from_operand (op); |
445 | if (!MEM_P (mem)) | |
446 | return false; | |
a953491e | 447 | |
4de7b010 | 448 | decompose_mem_address (&ad, mem); |
a953491e | 449 | address_eliminator eliminator (&ad); |
777e635f | 450 | return constraint_satisfied_p (op, constraint); |
a953491e RS |
451 | } |
452 | ||
453 | /* Return true if the eliminated form of address AD satisfies extra | |
454 | address constraint CONSTRAINT. */ | |
455 | static bool | |
456 | satisfies_address_constraint_p (struct address_info *ad, | |
777e635f | 457 | enum constraint_num constraint) |
a953491e RS |
458 | { |
459 | address_eliminator eliminator (ad); | |
777e635f | 460 | return constraint_satisfied_p (*ad->outer, constraint); |
a953491e RS |
461 | } |
462 | ||
463 | /* Return true if the eliminated form of address OP satisfies extra | |
464 | address constraint CONSTRAINT. */ | |
465 | static bool | |
777e635f | 466 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
467 | { |
468 | struct address_info ad; | |
469 | ||
470 | decompose_lea_address (&ad, &op); | |
471 | return satisfies_address_constraint_p (&ad, constraint); | |
472 | } | |
a953491e | 473 | |
4c2b2d79 VM |
474 | /* Initiate equivalences for LRA. As we keep original equivalences |
475 | before any elimination, we need to make copies otherwise any change | |
476 | in insns might change the equivalences. */ | |
477 | void | |
478 | lra_init_equiv (void) | |
479 | { | |
480 | ira_expand_reg_equiv (); | |
481 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
482 | { | |
483 | rtx res; | |
484 | ||
485 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
486 | ira_reg_equiv[i].memory = copy_rtx (res); | |
487 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
488 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
489 | } | |
490 | } | |
491 | ||
492 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
493 | ||
494 | /* Update equivalence for REGNO. We need to this as the equivalence | |
495 | might contain other pseudos which are changed by their | |
496 | equivalences. */ | |
497 | static void | |
498 | update_equiv (int regno) | |
499 | { | |
500 | rtx x; | |
501 | ||
502 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
503 | ira_reg_equiv[regno].memory | |
504 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
505 | NULL_RTX); | |
506 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
507 | ira_reg_equiv[regno].invariant | |
508 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
509 | NULL_RTX); | |
510 | } | |
511 | ||
55a2c322 VM |
512 | /* If we have decided to substitute X with another value, return that |
513 | value, otherwise return X. */ | |
514 | static rtx | |
8d49e7ef | 515 | get_equiv (rtx x) |
55a2c322 VM |
516 | { |
517 | int regno; | |
518 | rtx res; | |
519 | ||
520 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
521 | || ! ira_reg_equiv[regno].defined_p | |
522 | || ! ira_reg_equiv[regno].profitable_p | |
523 | || lra_get_regno_hard_regno (regno) >= 0) | |
524 | return x; | |
525 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
d6220b11 KK |
526 | { |
527 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
528 | return x; | |
529 | return res; | |
530 | } | |
55a2c322 VM |
531 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
532 | return res; | |
533 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
534 | return res; | |
535 | gcc_unreachable (); | |
536 | } | |
537 | ||
8d49e7ef VM |
538 | /* If we have decided to substitute X with the equivalent value, |
539 | return that value after elimination for INSN, otherwise return | |
540 | X. */ | |
541 | static rtx | |
cfa434f6 | 542 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
8d49e7ef VM |
543 | { |
544 | rtx res = get_equiv (x); | |
545 | ||
546 | if (x == res || CONSTANT_P (res)) | |
547 | return res; | |
d9cf932c | 548 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
a6af1bf9 | 549 | false, false, 0, true); |
8d49e7ef VM |
550 | } |
551 | ||
55a2c322 VM |
552 | /* Set up curr_operand_mode. */ |
553 | static void | |
554 | init_curr_operand_mode (void) | |
555 | { | |
556 | int nop = curr_static_id->n_operands; | |
557 | for (int i = 0; i < nop; i++) | |
558 | { | |
ef4bddc2 | 559 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
55a2c322 VM |
560 | if (mode == VOIDmode) |
561 | { | |
562 | /* The .md mode for address operands is the mode of the | |
563 | addressed value rather than the mode of the address itself. */ | |
564 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
565 | mode = Pmode; | |
566 | else | |
567 | mode = curr_static_id->operand[i].mode; | |
568 | } | |
569 | curr_operand_mode[i] = mode; | |
570 | } | |
571 | } | |
572 | ||
573 | \f | |
574 | ||
575 | /* The page contains code to reuse input reloads. */ | |
576 | ||
577 | /* Structure describes input reload of the current insns. */ | |
578 | struct input_reload | |
579 | { | |
3f156a6c VM |
580 | /* True for input reload of matched operands. */ |
581 | bool match_p; | |
55a2c322 VM |
582 | /* Reloaded value. */ |
583 | rtx input; | |
584 | /* Reload pseudo used. */ | |
585 | rtx reg; | |
586 | }; | |
587 | ||
588 | /* The number of elements in the following array. */ | |
589 | static int curr_insn_input_reloads_num; | |
590 | /* Array containing info about input reloads. It is used to find the | |
591 | same input reload and reuse the reload pseudo in this case. */ | |
592 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
593 | ||
594 | /* Initiate data concerning reuse of input reloads for the current | |
595 | insn. */ | |
596 | static void | |
597 | init_curr_insn_input_reloads (void) | |
598 | { | |
599 | curr_insn_input_reloads_num = 0; | |
600 | } | |
601 | ||
6b3034ea AC |
602 | /* The canonical form of an rtx inside a MEM is not necessarily the same as the |
603 | canonical form of the rtx outside the MEM. Fix this up in the case that | |
604 | we're reloading an address (and therefore pulling it outside a MEM). */ | |
605 | static rtx | |
606 | canonicalize_reload_addr (rtx addr) | |
607 | { | |
608 | subrtx_var_iterator::array_type array; | |
609 | FOR_EACH_SUBRTX_VAR (iter, array, addr, NONCONST) | |
610 | { | |
611 | rtx x = *iter; | |
612 | if (GET_CODE (x) == MULT && CONST_INT_P (XEXP (x, 1))) | |
613 | { | |
614 | const HOST_WIDE_INT ci = INTVAL (XEXP (x, 1)); | |
615 | const int pwr2 = exact_log2 (ci); | |
616 | if (pwr2 > 0) | |
617 | { | |
618 | /* Rewrite this to use a shift instead, which is canonical when | |
619 | outside of a MEM. */ | |
620 | PUT_CODE (x, ASHIFT); | |
621 | XEXP (x, 1) = GEN_INT (pwr2); | |
622 | } | |
623 | } | |
624 | } | |
625 | ||
626 | return addr; | |
627 | } | |
628 | ||
85419ac5 VM |
629 | /* Create a new pseudo using MODE, RCLASS, EXCLUDE_START_HARD_REGS, ORIGINAL or |
630 | reuse an existing reload pseudo. Don't reuse an existing reload pseudo if | |
631 | IN_SUBREG_P is true and the reused pseudo should be wrapped up in a SUBREG. | |
632 | The result pseudo is returned through RESULT_REG. Return TRUE if we created | |
633 | a new pseudo, FALSE if we reused an existing reload pseudo. Use TITLE to | |
634 | describe new registers for debug purposes. */ | |
55a2c322 | 635 | static bool |
ef4bddc2 | 636 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
85419ac5 VM |
637 | enum reg_class rclass, HARD_REG_SET *exclude_start_hard_regs, |
638 | bool in_subreg_p, const char *title, rtx *result_reg) | |
55a2c322 VM |
639 | { |
640 | int i, regno; | |
641 | enum reg_class new_class; | |
3f156a6c | 642 | bool unique_p = false; |
55a2c322 VM |
643 | |
644 | if (type == OP_OUT) | |
645 | { | |
6001db79 RS |
646 | /* Output reload registers tend to start out with a conservative |
647 | choice of register class. Usually this is ALL_REGS, although | |
648 | a target might narrow it (for performance reasons) through | |
649 | targetm.preferred_reload_class. It's therefore quite common | |
650 | for a reload instruction to require a more restrictive class | |
651 | than the class that was originally assigned to the reload register. | |
652 | ||
653 | In these situations, it's more efficient to refine the choice | |
654 | of register class rather than create a second reload register. | |
655 | This also helps to avoid cycling for registers that are only | |
656 | used by reload instructions. */ | |
657 | if (REG_P (original) | |
658 | && (int) REGNO (original) >= new_regno_start | |
659 | && INSN_UID (curr_insn) >= new_insn_uid_start | |
660 | && in_class_p (original, rclass, &new_class, true)) | |
661 | { | |
662 | unsigned int regno = REGNO (original); | |
663 | if (lra_dump_file != NULL) | |
664 | { | |
665 | fprintf (lra_dump_file, " Reuse r%d for output ", regno); | |
666 | dump_value_slim (lra_dump_file, original, 1); | |
667 | } | |
668 | if (new_class != lra_get_allocno_class (regno)) | |
669 | lra_change_class (regno, new_class, ", change to", false); | |
670 | if (lra_dump_file != NULL) | |
671 | fprintf (lra_dump_file, "\n"); | |
672 | *result_reg = original; | |
673 | return false; | |
674 | } | |
55a2c322 | 675 | *result_reg |
85419ac5 VM |
676 | = lra_create_new_reg_with_unique_value (mode, original, rclass, |
677 | exclude_start_hard_regs, title); | |
55a2c322 VM |
678 | return true; |
679 | } | |
73cca0cc VM |
680 | /* Prevent reuse value of expression with side effects, |
681 | e.g. volatile memory. */ | |
682 | if (! side_effects_p (original)) | |
683 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
3f156a6c VM |
684 | { |
685 | if (! curr_insn_input_reloads[i].match_p | |
686 | && rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
687 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
688 | { | |
689 | rtx reg = curr_insn_input_reloads[i].reg; | |
690 | regno = REGNO (reg); | |
691 | /* If input is equal to original and both are VOIDmode, | |
692 | GET_MODE (reg) might be still different from mode. | |
693 | Ensure we don't return *result_reg with wrong mode. */ | |
694 | if (GET_MODE (reg) != mode) | |
695 | { | |
696 | if (in_subreg_p) | |
697 | continue; | |
cf098191 RS |
698 | if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)), |
699 | GET_MODE_SIZE (mode))) | |
3f156a6c VM |
700 | continue; |
701 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
702 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
703 | continue; | |
704 | } | |
705 | *result_reg = reg; | |
706 | if (lra_dump_file != NULL) | |
707 | { | |
708 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
709 | dump_value_slim (lra_dump_file, original, 1); | |
710 | } | |
711 | if (new_class != lra_get_allocno_class (regno)) | |
712 | lra_change_class (regno, new_class, ", change to", false); | |
713 | if (lra_dump_file != NULL) | |
714 | fprintf (lra_dump_file, "\n"); | |
715 | return false; | |
716 | } | |
717 | /* If we have an input reload with a different mode, make sure it | |
718 | will get a different hard reg. */ | |
719 | else if (REG_P (original) | |
720 | && REG_P (curr_insn_input_reloads[i].input) | |
721 | && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) | |
722 | && (GET_MODE (original) | |
723 | != GET_MODE (curr_insn_input_reloads[i].input))) | |
724 | unique_p = true; | |
725 | } | |
726 | *result_reg = (unique_p | |
727 | ? lra_create_new_reg_with_unique_value | |
85419ac5 VM |
728 | : lra_create_new_reg) (mode, original, rclass, |
729 | exclude_start_hard_regs, title); | |
55a2c322 VM |
730 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); |
731 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
3f156a6c | 732 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; |
55a2c322 VM |
733 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; |
734 | return true; | |
735 | } | |
736 | ||
737 | \f | |
55a2c322 VM |
738 | /* The page contains major code to choose the current insn alternative |
739 | and generate reloads for it. */ | |
740 | ||
741 | /* Return the offset from REGNO of the least significant register | |
742 | in (reg:MODE REGNO). | |
743 | ||
744 | This function is used to tell whether two registers satisfy | |
745 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
746 | ||
747 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
748 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
749 | int | |
ef4bddc2 | 750 | lra_constraint_offset (int regno, machine_mode mode) |
55a2c322 VM |
751 | { |
752 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
b0567726 RS |
753 | |
754 | scalar_int_mode int_mode; | |
755 | if (WORDS_BIG_ENDIAN | |
756 | && is_a <scalar_int_mode> (mode, &int_mode) | |
757 | && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD) | |
ad474626 | 758 | return hard_regno_nregs (regno, mode) - 1; |
55a2c322 VM |
759 | return 0; |
760 | } | |
761 | ||
762 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
763 | if they are the same hard reg, and has special hacks for | |
764 | auto-increment and auto-decrement. This is specifically intended for | |
765 | process_alt_operands to use in determining whether two operands | |
766 | match. X is the operand whose number is the lower of the two. | |
767 | ||
768 | It is supposed that X is the output operand and Y is the input | |
769 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
770 | register in subreg Y as we know it now. Otherwise, it is a | |
771 | negative value. */ | |
772 | static bool | |
773 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
774 | { | |
775 | int i; | |
776 | RTX_CODE code = GET_CODE (x); | |
777 | const char *fmt; | |
778 | ||
779 | if (x == y) | |
780 | return true; | |
781 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
782 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
783 | { | |
784 | int j; | |
f4eafc30 | 785 | |
265a749f | 786 | i = get_hard_regno (x); |
55a2c322 VM |
787 | if (i < 0) |
788 | goto slow; | |
789 | ||
790 | if ((j = y_hard_regno) < 0) | |
791 | goto slow; | |
792 | ||
793 | i += lra_constraint_offset (i, GET_MODE (x)); | |
794 | j += lra_constraint_offset (j, GET_MODE (y)); | |
795 | ||
796 | return i == j; | |
797 | } | |
798 | ||
799 | /* If two operands must match, because they are really a single | |
800 | operand of an assembler insn, then two post-increments are invalid | |
801 | because the assembler insn would increment only once. On the | |
802 | other hand, a post-increment matches ordinary indexing if the | |
803 | post-increment is the output operand. */ | |
804 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
805 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
806 | ||
807 | /* Two pre-increments are invalid because the assembler insn would | |
808 | increment only once. On the other hand, a pre-increment matches | |
809 | ordinary indexing if the pre-increment is the input operand. */ | |
810 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
811 | || GET_CODE (y) == PRE_MODIFY) | |
812 | return operands_match_p (x, XEXP (y, 0), -1); | |
f4eafc30 | 813 | |
55a2c322 VM |
814 | slow: |
815 | ||
9fccb335 RS |
816 | if (code == REG && REG_P (y)) |
817 | return REGNO (x) == REGNO (y); | |
818 | ||
55a2c322 VM |
819 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
820 | && x == SUBREG_REG (y)) | |
821 | return true; | |
822 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
823 | && SUBREG_REG (x) == y) | |
824 | return true; | |
825 | ||
826 | /* Now we have disposed of all the cases in which different rtx | |
827 | codes can match. */ | |
828 | if (code != GET_CODE (y)) | |
829 | return false; | |
830 | ||
831 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
832 | if (GET_MODE (x) != GET_MODE (y)) | |
833 | return false; | |
834 | ||
835 | switch (code) | |
836 | { | |
837 | CASE_CONST_UNIQUE: | |
838 | return false; | |
839 | ||
a87d3f96 RS |
840 | case CONST_VECTOR: |
841 | if (!same_vector_encodings_p (x, y)) | |
842 | return false; | |
843 | break; | |
844 | ||
55a2c322 | 845 | case LABEL_REF: |
04a121a7 | 846 | return label_ref_label (x) == label_ref_label (y); |
55a2c322 VM |
847 | case SYMBOL_REF: |
848 | return XSTR (x, 0) == XSTR (y, 0); | |
849 | ||
850 | default: | |
851 | break; | |
852 | } | |
853 | ||
854 | /* Compare the elements. If any pair of corresponding elements fail | |
855 | to match, return false for the whole things. */ | |
856 | ||
857 | fmt = GET_RTX_FORMAT (code); | |
858 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
859 | { | |
860 | int val, j; | |
861 | switch (fmt[i]) | |
862 | { | |
863 | case 'w': | |
864 | if (XWINT (x, i) != XWINT (y, i)) | |
865 | return false; | |
866 | break; | |
867 | ||
868 | case 'i': | |
869 | if (XINT (x, i) != XINT (y, i)) | |
870 | return false; | |
871 | break; | |
872 | ||
91914e56 RS |
873 | case 'p': |
874 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
875 | return false; | |
876 | break; | |
877 | ||
55a2c322 VM |
878 | case 'e': |
879 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
880 | if (val == 0) | |
881 | return false; | |
882 | break; | |
883 | ||
884 | case '0': | |
885 | break; | |
886 | ||
887 | case 'E': | |
888 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
889 | return false; | |
890 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
891 | { | |
892 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
893 | if (val == 0) | |
894 | return false; | |
895 | } | |
896 | break; | |
897 | ||
898 | /* It is believed that rtx's at this level will never | |
899 | contain anything but integers and other rtx's, except for | |
900 | within LABEL_REFs and SYMBOL_REFs. */ | |
901 | default: | |
902 | gcc_unreachable (); | |
903 | } | |
904 | } | |
905 | return true; | |
906 | } | |
907 | ||
908 | /* True if X is a constant that can be forced into the constant pool. | |
909 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
910 | #define CONST_POOL_OK_P(MODE, X) \ | |
911 | ((MODE) != VOIDmode \ | |
912 | && CONSTANT_P (X) \ | |
913 | && GET_CODE (X) != HIGH \ | |
cf098191 | 914 | && GET_MODE_SIZE (MODE).is_constant () \ |
55a2c322 VM |
915 | && !targetm.cannot_force_const_mem (MODE, X)) |
916 | ||
917 | /* True if C is a non-empty register class that has too few registers | |
918 | to be safely used as a reload target class. */ | |
a9711f36 VM |
919 | #define SMALL_REGISTER_CLASS_P(C) \ |
920 | (ira_class_hard_regs_num [(C)] == 1 \ | |
921 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
922 | && targetm.class_likely_spilled_p (C))) | |
55a2c322 VM |
923 | |
924 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
925 | static void | |
926 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
927 | { | |
928 | enum reg_class rclass; | |
929 | ||
930 | /* Do not make more accurate class from reloads generated. They are | |
931 | mostly moves with a lot of constraints. Making more accurate | |
932 | class may results in very narrow class and impossibility of find | |
933 | registers for several reloads of one insn. */ | |
934 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
935 | return; | |
936 | if (GET_CODE (reg) == SUBREG) | |
937 | reg = SUBREG_REG (reg); | |
938 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
939 | return; | |
940 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
a2d0d374 | 941 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
55a2c322 VM |
942 | } |
943 | ||
4be9717c VM |
944 | /* Searches X for any reference to a reg with the same value as REGNO, |
945 | returning the rtx of the reference found if any. Otherwise, | |
946 | returns NULL_RTX. */ | |
947 | static rtx | |
948 | regno_val_use_in (unsigned int regno, rtx x) | |
949 | { | |
950 | const char *fmt; | |
951 | int i, j; | |
952 | rtx tem; | |
953 | ||
954 | if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) | |
955 | return x; | |
956 | ||
957 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
958 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
959 | { | |
960 | if (fmt[i] == 'e') | |
961 | { | |
962 | if ((tem = regno_val_use_in (regno, XEXP (x, i)))) | |
963 | return tem; | |
964 | } | |
965 | else if (fmt[i] == 'E') | |
966 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
967 | if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) | |
968 | return tem; | |
969 | } | |
970 | ||
971 | return NULL_RTX; | |
972 | } | |
973 | ||
d8321b33 VM |
974 | /* Return true if all current insn non-output operands except INS (it |
975 | has a negaitve end marker) do not use pseudos with the same value | |
976 | as REGNO. */ | |
977 | static bool | |
978 | check_conflict_input_operands (int regno, signed char *ins) | |
979 | { | |
980 | int in; | |
981 | int n_operands = curr_static_id->n_operands; | |
982 | ||
983 | for (int nop = 0; nop < n_operands; nop++) | |
984 | if (! curr_static_id->operand[nop].is_operator | |
985 | && curr_static_id->operand[nop].type != OP_OUT) | |
986 | { | |
987 | for (int i = 0; (in = ins[i]) >= 0; i++) | |
988 | if (in == nop) | |
989 | break; | |
990 | if (in < 0 | |
991 | && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) | |
992 | return false; | |
993 | } | |
994 | return true; | |
995 | } | |
996 | ||
85419ac5 VM |
997 | /* Generate reloads for matching OUT and INS (array of input operand numbers |
998 | with end marker -1) with reg class GOAL_CLASS and EXCLUDE_START_HARD_REGS, | |
999 | considering output operands OUTS (similar array to INS) needing to be in | |
1000 | different registers. Add input and output reloads correspondingly to the | |
1001 | lists *BEFORE and *AFTER. OUT might be negative. In this case we generate | |
aefae0f1 TP |
1002 | input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag |
1003 | that the output operand is early clobbered for chosen alternative. */ | |
55a2c322 | 1004 | static void |
aefae0f1 | 1005 | match_reload (signed char out, signed char *ins, signed char *outs, |
85419ac5 VM |
1006 | enum reg_class goal_class, HARD_REG_SET *exclude_start_hard_regs, |
1007 | rtx_insn **before, rtx_insn **after, bool early_clobber_p) | |
55a2c322 | 1008 | { |
aefae0f1 | 1009 | bool out_conflict; |
55a2c322 | 1010 | int i, in; |
e67d1102 | 1011 | rtx new_in_reg, new_out_reg, reg; |
ef4bddc2 | 1012 | machine_mode inmode, outmode; |
55a2c322 | 1013 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
511dcace | 1014 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
55a2c322 | 1015 | |
55a2c322 | 1016 | inmode = curr_operand_mode[ins[0]]; |
511dcace | 1017 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
55a2c322 VM |
1018 | push_to_sequence (*before); |
1019 | if (inmode != outmode) | |
1020 | { | |
00224b1a RS |
1021 | /* process_alt_operands has already checked that the mode sizes |
1022 | are ordered. */ | |
bd4288c0 | 1023 | if (partial_subreg_p (outmode, inmode)) |
55a2c322 VM |
1024 | { |
1025 | reg = new_in_reg | |
85419ac5 VM |
1026 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, goal_class, |
1027 | exclude_start_hard_regs, | |
1028 | ""); | |
98a05c03 | 1029 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); |
2c62cbaa | 1030 | LRA_SUBREG_P (new_out_reg) = 1; |
350c0fe7 | 1031 | /* If the input reg is dying here, we can use the same hard |
f681cf95 VM |
1032 | register for REG and IN_RTX. We do it only for original |
1033 | pseudos as reload pseudos can die although original | |
1034 | pseudos still live where reload pseudos dies. */ | |
1035 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
d8321b33 VM |
1036 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) |
1037 | && (!early_clobber_p | |
1038 | || check_conflict_input_operands(REGNO (in_rtx), ins))) | |
d70a81dd | 1039 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
55a2c322 VM |
1040 | } |
1041 | else | |
1042 | { | |
1043 | reg = new_out_reg | |
1044 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
85419ac5 VM |
1045 | goal_class, |
1046 | exclude_start_hard_regs, | |
1047 | ""); | |
98a05c03 | 1048 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); |
55a2c322 VM |
1049 | /* NEW_IN_REG is non-paradoxical subreg. We don't want |
1050 | NEW_OUT_REG living above. We add clobber clause for | |
c5cd5a7e VM |
1051 | this. This is just a temporary clobber. We can remove |
1052 | it at the end of LRA work. */ | |
e67d1102 | 1053 | rtx_insn *clobber = emit_clobber (new_out_reg); |
c5cd5a7e | 1054 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
2c62cbaa | 1055 | LRA_SUBREG_P (new_in_reg) = 1; |
350c0fe7 VM |
1056 | if (GET_CODE (in_rtx) == SUBREG) |
1057 | { | |
1058 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
1059 | ||
1060 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
1061 | and NEW_IN_REG are similar, we can use the same hard | |
1062 | register for REG and SUBREG_REG. */ | |
f681cf95 VM |
1063 | if (REG_P (subreg_reg) |
1064 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
1065 | && GET_MODE (subreg_reg) == outmode | |
91914e56 | 1066 | && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg)) |
d8321b33 VM |
1067 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) |
1068 | && (! early_clobber_p | |
1069 | || check_conflict_input_operands (REGNO (subreg_reg), | |
1070 | ins))) | |
d70a81dd | 1071 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
350c0fe7 | 1072 | } |
55a2c322 VM |
1073 | } |
1074 | } | |
1075 | else | |
1076 | { | |
1077 | /* Pseudos have values -- see comments for lra_reg_info. | |
1078 | Different pseudos with the same value do not conflict even if | |
1079 | they live in the same place. When we create a pseudo we | |
1080 | assign value of original pseudo (if any) from which we | |
1081 | created the new pseudo. If we create the pseudo from the | |
3363daad VM |
1082 | input pseudo, the new pseudo will have no conflict with the |
1083 | input pseudo which is wrong when the input pseudo lives after | |
1084 | the insn and as the new pseudo value is changed by the insn | |
1085 | output. Therefore we create the new pseudo from the output | |
1086 | except the case when we have single matched dying input | |
1087 | pseudo. | |
f4eafc30 | 1088 | |
55a2c322 VM |
1089 | We cannot reuse the current output register because we might |
1090 | have a situation like "a <- a op b", where the constraints | |
1091 | force the second input operand ("b") to match the output | |
1092 | operand ("a"). "b" must then be copied into a new register | |
599e1cf8 VM |
1093 | so that it doesn't clobber the current value of "a". |
1094 | ||
67914693 | 1095 | We cannot use the same value if the output pseudo is |
599e1cf8 VM |
1096 | early clobbered or the input pseudo is mentioned in the |
1097 | output, e.g. as an address part in memory, because | |
1098 | output reload will actually extend the pseudo liveness. | |
1099 | We don't care about eliminable hard regs here as we are | |
1100 | interesting only in pseudos. */ | |
f4eafc30 | 1101 | |
aefae0f1 TP |
1102 | /* Matching input's register value is the same as one of the other |
1103 | output operand. Output operands in a parallel insn must be in | |
1104 | different registers. */ | |
1105 | out_conflict = false; | |
1106 | if (REG_P (in_rtx)) | |
1107 | { | |
1108 | for (i = 0; outs[i] >= 0; i++) | |
1109 | { | |
1110 | rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; | |
8c59f411 | 1111 | if (outs[i] != out && REG_P (other_out_rtx) |
aefae0f1 TP |
1112 | && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) |
1113 | != NULL_RTX)) | |
1114 | { | |
1115 | out_conflict = true; | |
1116 | break; | |
1117 | } | |
1118 | } | |
1119 | } | |
1120 | ||
55a2c322 | 1121 | new_in_reg = new_out_reg |
599e1cf8 | 1122 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
3363daad VM |
1123 | && (int) REGNO (in_rtx) < lra_new_regno_start |
1124 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
d8321b33 VM |
1125 | && (! early_clobber_p |
1126 | || check_conflict_input_operands (REGNO (in_rtx), ins)) | |
4be9717c VM |
1127 | && (out < 0 |
1128 | || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) | |
aefae0f1 | 1129 | && !out_conflict |
85419ac5 VM |
1130 | ? lra_create_new_reg (inmode, in_rtx, goal_class, |
1131 | exclude_start_hard_regs, "") | |
1132 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, goal_class, | |
1133 | exclude_start_hard_regs, | |
1134 | "")); | |
55a2c322 | 1135 | } |
511dcace VM |
1136 | /* In operand can be got from transformations before processing insn |
1137 | constraints. One example of such transformations is subreg | |
1138 | reloading (see function simplify_operand_subreg). The new | |
1139 | pseudos created by the transformations might have inaccurate | |
55a2c322 VM |
1140 | class (ALL_REGS) and we should make their classes more |
1141 | accurate. */ | |
1142 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
55a2c322 VM |
1143 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
1144 | *before = get_insns (); | |
1145 | end_sequence (); | |
3f156a6c VM |
1146 | /* Add the new pseudo to consider values of subsequent input reload |
1147 | pseudos. */ | |
1148 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
1149 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; | |
1150 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; | |
1151 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; | |
55a2c322 | 1152 | for (i = 0; (in = ins[i]) >= 0; i++) |
60257913 VM |
1153 | if (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode |
1154 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])) | |
55a2c322 | 1155 | *curr_id->operand_loc[in] = new_in_reg; |
60257913 VM |
1156 | else |
1157 | { | |
1158 | lra_assert | |
1159 | (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
1160 | *curr_id->operand_loc[in] = new_out_reg; | |
1161 | } | |
55a2c322 | 1162 | lra_update_dups (curr_id, ins); |
511dcace VM |
1163 | if (out < 0) |
1164 | return; | |
1165 | /* See a comment for the input operand above. */ | |
1166 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
55a2c322 VM |
1167 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
1168 | { | |
bb37ad8c | 1169 | reg = SUBREG_P (out_rtx) ? SUBREG_REG (out_rtx) : out_rtx; |
55a2c322 | 1170 | start_sequence (); |
bb37ad8c VM |
1171 | /* If we had strict_low_part, use it also in reload to keep other |
1172 | parts unchanged but do it only for regs as strict_low_part | |
1173 | has no sense for memory and probably there is no insn pattern | |
1174 | to match the reload insn in memory case. */ | |
1175 | if (out >= 0 && curr_static_id->operand[out].strict_low && REG_P (reg)) | |
5261cf8c | 1176 | out_rtx = gen_rtx_STRICT_LOW_PART (VOIDmode, out_rtx); |
55a2c322 VM |
1177 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); |
1178 | emit_insn (*after); | |
1179 | *after = get_insns (); | |
1180 | end_sequence (); | |
1181 | } | |
1182 | *curr_id->operand_loc[out] = new_out_reg; | |
1183 | lra_update_dup (curr_id, out); | |
1184 | } | |
1185 | ||
1186 | /* Return register class which is union of all reg classes in insn | |
1187 | constraint alternative string starting with P. */ | |
1188 | static enum reg_class | |
1189 | reg_class_from_constraints (const char *p) | |
1190 | { | |
1191 | int c, len; | |
1192 | enum reg_class op_class = NO_REGS; | |
1193 | ||
1194 | do | |
1195 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1196 | { | |
1197 | case '#': | |
1198 | case ',': | |
1199 | return op_class; | |
1200 | ||
55a2c322 | 1201 | case 'g': |
55a2c322 VM |
1202 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1203 | break; | |
f4eafc30 | 1204 | |
55a2c322 | 1205 | default: |
777e635f RS |
1206 | enum constraint_num cn = lookup_constraint (p); |
1207 | enum reg_class cl = reg_class_for_constraint (cn); | |
1208 | if (cl == NO_REGS) | |
55a2c322 | 1209 | { |
777e635f | 1210 | if (insn_extra_address_constraint (cn)) |
55a2c322 VM |
1211 | op_class |
1212 | = (reg_class_subunion | |
1213 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1214 | ADDRESS, SCRATCH)]); | |
55a2c322 VM |
1215 | break; |
1216 | } | |
f4eafc30 | 1217 | |
777e635f RS |
1218 | op_class = reg_class_subunion[op_class][cl]; |
1219 | break; | |
55a2c322 VM |
1220 | } |
1221 | while ((p += len), c); | |
1222 | return op_class; | |
1223 | } | |
1224 | ||
1225 | /* If OP is a register, return the class of the register as per | |
1226 | get_reg_class, otherwise return NO_REGS. */ | |
1227 | static inline enum reg_class | |
1228 | get_op_class (rtx op) | |
1229 | { | |
1230 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1231 | } | |
1232 | ||
1233 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1234 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1235 | SUBREG for VAL to make them equal. */ | |
cfa434f6 | 1236 | static rtx_insn * |
55a2c322 VM |
1237 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1238 | { | |
1239 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
2c62cbaa | 1240 | { |
cb1cca12 VM |
1241 | /* Usually size of mem_pseudo is greater than val size but in |
1242 | rare cases it can be less as it can be defined by target | |
1243 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
1ccd4874 VM |
1244 | if (! MEM_P (val)) |
1245 | { | |
54b84aa9 EB |
1246 | val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), |
1247 | GET_CODE (val) == SUBREG | |
1248 | ? SUBREG_REG (val) : val); | |
1ccd4874 VM |
1249 | LRA_SUBREG_P (val) = 1; |
1250 | } | |
1251 | else | |
1252 | { | |
1253 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1254 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1255 | } | |
2c62cbaa | 1256 | } |
1476d1bd MM |
1257 | return to_p ? gen_move_insn (mem_pseudo, val) |
1258 | : gen_move_insn (val, mem_pseudo); | |
55a2c322 VM |
1259 | } |
1260 | ||
1261 | /* Process a special case insn (register move), return true if we | |
2c62cbaa | 1262 | don't need to process it anymore. INSN should be a single set |
f15643d4 RS |
1263 | insn. Set up that RTL was changed through CHANGE_P and that hook |
1264 | TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
2c62cbaa | 1265 | SEC_MEM_P. */ |
55a2c322 | 1266 | static bool |
2c62cbaa | 1267 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
55a2c322 VM |
1268 | { |
1269 | int sregno, dregno; | |
ef0006eb | 1270 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
cfa434f6 | 1271 | rtx_insn *before; |
55a2c322 | 1272 | enum reg_class dclass, sclass, secondary_class; |
55a2c322 VM |
1273 | secondary_reload_info sri; |
1274 | ||
2c62cbaa VM |
1275 | lra_assert (curr_insn_set != NULL_RTX); |
1276 | dreg = dest = SET_DEST (curr_insn_set); | |
1277 | sreg = src = SET_SRC (curr_insn_set); | |
55a2c322 VM |
1278 | if (GET_CODE (dest) == SUBREG) |
1279 | dreg = SUBREG_REG (dest); | |
1280 | if (GET_CODE (src) == SUBREG) | |
1281 | sreg = SUBREG_REG (src); | |
1ccd4874 | 1282 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
55a2c322 VM |
1283 | return false; |
1284 | sclass = dclass = NO_REGS; | |
55a2c322 VM |
1285 | if (REG_P (dreg)) |
1286 | dclass = get_reg_class (REGNO (dreg)); | |
767c0982 | 1287 | gcc_assert (dclass < LIM_REG_CLASSES && dclass >= NO_REGS); |
55a2c322 VM |
1288 | if (dclass == ALL_REGS) |
1289 | /* ALL_REGS is used for new pseudos created by transformations | |
1290 | like reload of SUBREG_REG (see function | |
1291 | simplify_operand_subreg). We don't know their class yet. We | |
1292 | should figure out the class from processing the insn | |
1293 | constraints not in this fast path function. Even if ALL_REGS | |
1294 | were a right class for the pseudo, secondary_... hooks usually | |
1295 | are not define for ALL_REGS. */ | |
1296 | return false; | |
55a2c322 VM |
1297 | if (REG_P (sreg)) |
1298 | sclass = get_reg_class (REGNO (sreg)); | |
767c0982 | 1299 | gcc_assert (sclass < LIM_REG_CLASSES && sclass >= NO_REGS); |
55a2c322 VM |
1300 | if (sclass == ALL_REGS) |
1301 | /* See comments above. */ | |
1302 | return false; | |
1ccd4874 VM |
1303 | if (sclass == NO_REGS && dclass == NO_REGS) |
1304 | return false; | |
f15643d4 | 1305 | if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass) |
1ccd4874 | 1306 | && ((sclass != NO_REGS && dclass != NO_REGS) |
94e23f53 RS |
1307 | || (GET_MODE (src) |
1308 | != targetm.secondary_memory_needed_mode (GET_MODE (src))))) | |
55a2c322 VM |
1309 | { |
1310 | *sec_mem_p = true; | |
1311 | return false; | |
1312 | } | |
1ccd4874 VM |
1313 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1314 | return false; | |
55a2c322 VM |
1315 | sri.prev_sri = NULL; |
1316 | sri.icode = CODE_FOR_nothing; | |
1317 | sri.extra_cost = 0; | |
1318 | secondary_class = NO_REGS; | |
1319 | /* Set up hard register for a reload pseudo for hook | |
1320 | secondary_reload because some targets just ignore unassigned | |
1321 | pseudos in the hook. */ | |
1322 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1323 | { | |
1324 | dregno = REGNO (dreg); | |
1325 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1326 | } | |
1327 | else | |
1328 | dregno = -1; | |
1329 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1330 | { | |
1331 | sregno = REGNO (sreg); | |
1332 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1333 | } | |
1334 | else | |
1335 | sregno = -1; | |
1336 | if (sclass != NO_REGS) | |
1337 | secondary_class | |
1338 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1339 | (reg_class_t) sclass, | |
1340 | GET_MODE (src), &sri); | |
1341 | if (sclass == NO_REGS | |
1342 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1343 | && dclass != NO_REGS)) | |
1344 | { | |
55a2c322 VM |
1345 | enum reg_class old_sclass = secondary_class; |
1346 | secondary_reload_info old_sri = sri; | |
55a2c322 VM |
1347 | |
1348 | sri.prev_sri = NULL; | |
1349 | sri.icode = CODE_FOR_nothing; | |
1350 | sri.extra_cost = 0; | |
1351 | secondary_class | |
ef0006eb | 1352 | = (enum reg_class) targetm.secondary_reload (true, src, |
55a2c322 | 1353 | (reg_class_t) dclass, |
ef0006eb | 1354 | GET_MODE (src), &sri); |
55a2c322 VM |
1355 | /* Check the target hook consistency. */ |
1356 | lra_assert | |
1357 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1358 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1359 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1360 | } | |
1361 | if (sregno >= 0) | |
1362 | reg_renumber [sregno] = -1; | |
1363 | if (dregno >= 0) | |
1364 | reg_renumber [dregno] = -1; | |
1365 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1366 | return false; | |
1367 | *change_p = true; | |
1368 | new_reg = NULL_RTX; | |
1369 | if (secondary_class != NO_REGS) | |
ef0006eb | 1370 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
85419ac5 | 1371 | secondary_class, NULL, |
55a2c322 VM |
1372 | "secondary"); |
1373 | start_sequence (); | |
55a2c322 | 1374 | if (sri.icode == CODE_FOR_nothing) |
ef0006eb | 1375 | lra_emit_move (new_reg, src); |
55a2c322 VM |
1376 | else |
1377 | { | |
1378 | enum reg_class scratch_class; | |
1379 | ||
1380 | scratch_class = (reg_class_from_constraints | |
1381 | (insn_data[sri.icode].operand[2].constraint)); | |
1382 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1383 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
85419ac5 | 1384 | scratch_class, NULL, "scratch")); |
55a2c322 | 1385 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, |
ef0006eb | 1386 | src, scratch_reg)); |
55a2c322 VM |
1387 | } |
1388 | before = get_insns (); | |
1389 | end_sequence (); | |
cfa434f6 | 1390 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
55a2c322 | 1391 | if (new_reg != NULL_RTX) |
ef0006eb | 1392 | SET_SRC (curr_insn_set) = new_reg; |
55a2c322 VM |
1393 | else |
1394 | { | |
1395 | if (lra_dump_file != NULL) | |
1396 | { | |
1397 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
cfbeaedf | 1398 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
1399 | } |
1400 | lra_set_insn_deleted (curr_insn); | |
1401 | return true; | |
1402 | } | |
1403 | return false; | |
1404 | } | |
1405 | ||
1406 | /* The following data describe the result of process_alt_operands. | |
1407 | The data are used in curr_insn_transform to generate reloads. */ | |
1408 | ||
1409 | /* The chosen reg classes which should be used for the corresponding | |
1410 | operands. */ | |
1411 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
85419ac5 VM |
1412 | /* Hard registers which cannot be a start hard register for the corresponding |
1413 | operands. */ | |
1414 | static HARD_REG_SET goal_alt_exclude_start_hard_regs[MAX_RECOG_OPERANDS]; | |
55a2c322 VM |
1415 | /* True if the operand should be the same as another operand and that |
1416 | other operand does not need a reload. */ | |
1417 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1418 | /* True if the operand does not need a reload. */ | |
1419 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1420 | /* True if the operand can be offsetable memory. */ | |
1421 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1422 | /* The number of an operand to which given operand can be matched to. */ | |
1423 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1424 | /* The number of elements in the following array. */ | |
1425 | static int goal_alt_dont_inherit_ops_num; | |
1426 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1427 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1428 | /* True if the insn commutative operands should be swapped. */ | |
1429 | static bool goal_alt_swapped; | |
1430 | /* The chosen insn alternative. */ | |
1431 | static int goal_alt_number; | |
1432 | ||
987b67f1 VM |
1433 | /* True if the corresponding operand is the result of an equivalence |
1434 | substitution. */ | |
1435 | static bool equiv_substition_p[MAX_RECOG_OPERANDS]; | |
1436 | ||
55a2c322 VM |
1437 | /* The following five variables are used to choose the best insn |
1438 | alternative. They reflect final characteristics of the best | |
1439 | alternative. */ | |
1440 | ||
1441 | /* Number of necessary reloads and overall cost reflecting the | |
1442 | previous value and other unpleasantness of the best alternative. */ | |
1443 | static int best_losers, best_overall; | |
55a2c322 VM |
1444 | /* Overall number hard registers used for reloads. For example, on |
1445 | some targets we need 2 general registers to reload DFmode and only | |
1446 | one floating point register. */ | |
1447 | static int best_reload_nregs; | |
1448 | /* Overall number reflecting distances of previous reloading the same | |
1449 | value. The distances are counted from the current BB start. It is | |
1450 | used to improve inheritance chances. */ | |
1451 | static int best_reload_sum; | |
1452 | ||
1453 | /* True if the current insn should have no correspondingly input or | |
1454 | output reloads. */ | |
1455 | static bool no_input_reloads_p, no_output_reloads_p; | |
1456 | ||
1457 | /* True if we swapped the commutative operands in the current | |
1458 | insn. */ | |
1459 | static int curr_swapped; | |
1460 | ||
d9cf932c VM |
1461 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1462 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1463 | is nonnull if *LOC is an automodified value; handle that case by | |
1464 | adding the required output reloads to list AFTER. Return true if | |
1465 | the RTL was changed. | |
1466 | ||
1467 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1468 | register. Return false if the address register is correct. */ | |
55a2c322 | 1469 | static bool |
d9cf932c | 1470 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
cfa434f6 | 1471 | enum reg_class cl) |
55a2c322 VM |
1472 | { |
1473 | int regno; | |
1474 | enum reg_class rclass, new_class; | |
277f65de | 1475 | rtx reg; |
55a2c322 | 1476 | rtx new_reg; |
ef4bddc2 | 1477 | machine_mode mode; |
95921002 | 1478 | bool subreg_p, before_p = false; |
55a2c322 | 1479 | |
95921002 VM |
1480 | subreg_p = GET_CODE (*loc) == SUBREG; |
1481 | if (subreg_p) | |
ada2eb68 JW |
1482 | { |
1483 | reg = SUBREG_REG (*loc); | |
1484 | mode = GET_MODE (reg); | |
1485 | ||
1486 | /* For mode with size bigger than ptr_mode, there unlikely to be "mov" | |
1487 | between two registers with different classes, but there normally will | |
1488 | be "mov" which transfers element of vector register into the general | |
1489 | register, and this normally will be a subreg which should be reloaded | |
1490 | as a whole. This is particularly likely to be triggered when | |
1491 | -fno-split-wide-types specified. */ | |
3c11e1af JW |
1492 | if (!REG_P (reg) |
1493 | || in_class_p (reg, cl, &new_class) | |
cf098191 | 1494 | || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))) |
ada2eb68 JW |
1495 | loc = &SUBREG_REG (*loc); |
1496 | } | |
1497 | ||
277f65de | 1498 | reg = *loc; |
55a2c322 VM |
1499 | mode = GET_MODE (reg); |
1500 | if (! REG_P (reg)) | |
1501 | { | |
d9cf932c VM |
1502 | if (check_only_p) |
1503 | return true; | |
55a2c322 VM |
1504 | /* Always reload memory in an address even if the target supports |
1505 | such addresses. */ | |
85419ac5 VM |
1506 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, NULL, |
1507 | "address"); | |
55a2c322 VM |
1508 | before_p = true; |
1509 | } | |
1510 | else | |
1511 | { | |
1512 | regno = REGNO (reg); | |
1513 | rclass = get_reg_class (regno); | |
d9cf932c VM |
1514 | if (! check_only_p |
1515 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
55a2c322 VM |
1516 | { |
1517 | if (lra_dump_file != NULL) | |
1518 | { | |
1519 | fprintf (lra_dump_file, | |
1520 | "Changing pseudo %d in address of insn %u on equiv ", | |
1521 | REGNO (reg), INSN_UID (curr_insn)); | |
cfbeaedf | 1522 | dump_value_slim (lra_dump_file, *loc, 1); |
55a2c322 VM |
1523 | fprintf (lra_dump_file, "\n"); |
1524 | } | |
1525 | *loc = copy_rtx (*loc); | |
1526 | } | |
1527 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1528 | { | |
d9cf932c VM |
1529 | if (check_only_p) |
1530 | return true; | |
55a2c322 VM |
1531 | reg = *loc; |
1532 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
85419ac5 VM |
1533 | mode, reg, cl, NULL, |
1534 | subreg_p, "address", &new_reg)) | |
55a2c322 VM |
1535 | before_p = true; |
1536 | } | |
1537 | else if (new_class != NO_REGS && rclass != new_class) | |
1538 | { | |
d9cf932c VM |
1539 | if (check_only_p) |
1540 | return true; | |
a2d0d374 | 1541 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
1542 | return false; |
1543 | } | |
1544 | else | |
1545 | return false; | |
1546 | } | |
1547 | if (before_p) | |
1548 | { | |
1549 | push_to_sequence (*before); | |
1550 | lra_emit_move (new_reg, reg); | |
1551 | *before = get_insns (); | |
1552 | end_sequence (); | |
1553 | } | |
1554 | *loc = new_reg; | |
1555 | if (after != NULL) | |
1556 | { | |
1557 | start_sequence (); | |
9a9fe2b4 | 1558 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
55a2c322 VM |
1559 | emit_insn (*after); |
1560 | *after = get_insns (); | |
1561 | end_sequence (); | |
1562 | } | |
1563 | return true; | |
1564 | } | |
1565 | ||
4f0bee4c WM |
1566 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1567 | the insn to be inserted before curr insn. AFTER returns the | |
1568 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1569 | are the original reg and new reg for reload. */ | |
1570 | static void | |
cfa434f6 DM |
1571 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1572 | rtx newreg) | |
4f0bee4c WM |
1573 | { |
1574 | if (before) | |
1575 | { | |
1576 | push_to_sequence (*before); | |
1577 | lra_emit_move (newreg, origreg); | |
1578 | *before = get_insns (); | |
1579 | end_sequence (); | |
1580 | } | |
1581 | if (after) | |
1582 | { | |
1583 | start_sequence (); | |
1584 | lra_emit_move (origreg, newreg); | |
1585 | emit_insn (*after); | |
1586 | *after = get_insns (); | |
1587 | end_sequence (); | |
1588 | } | |
1589 | } | |
1590 | ||
ef4bddc2 | 1591 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
ab5d2233 | 1592 | static bool process_address (int, bool, rtx_insn **, rtx_insn **); |
ba38538f | 1593 | |
55a2c322 VM |
1594 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1595 | REG_MODE, add new reloads for further processing. Return true if | |
895ff86f | 1596 | any change was done. */ |
55a2c322 | 1597 | static bool |
ef4bddc2 | 1598 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
55a2c322 | 1599 | { |
497498c8 | 1600 | int hard_regno, inner_hard_regno; |
cfa434f6 | 1601 | rtx_insn *before, *after; |
895ff86f | 1602 | machine_mode mode, innermode; |
55a2c322 VM |
1603 | rtx reg, new_reg; |
1604 | rtx operand = *curr_id->operand_loc[nop]; | |
4f0bee4c WM |
1605 | enum reg_class regclass; |
1606 | enum op_type type; | |
55a2c322 | 1607 | |
cfa434f6 | 1608 | before = after = NULL; |
55a2c322 VM |
1609 | |
1610 | if (GET_CODE (operand) != SUBREG) | |
1611 | return false; | |
f4eafc30 | 1612 | |
55a2c322 VM |
1613 | mode = GET_MODE (operand); |
1614 | reg = SUBREG_REG (operand); | |
895ff86f | 1615 | innermode = GET_MODE (reg); |
4f0bee4c | 1616 | type = curr_static_id->operand[nop].type; |
2e186411 | 1617 | if (MEM_P (reg)) |
ba38538f | 1618 | { |
ab5d2233 EB |
1619 | const bool addr_was_valid |
1620 | = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); | |
ba38538f | 1621 | alter_subreg (curr_id->operand_loc[nop], false); |
ab5d2233 | 1622 | rtx subst = *curr_id->operand_loc[nop]; |
ba38538f | 1623 | lra_assert (MEM_P (subst)); |
8eaff6ef VM |
1624 | const bool addr_is_valid = valid_address_p (GET_MODE (subst), |
1625 | XEXP (subst, 0), | |
1626 | MEM_ADDR_SPACE (subst)); | |
ab5d2233 | 1627 | if (!addr_was_valid |
8eaff6ef | 1628 | || addr_is_valid |
2e186411 AM |
1629 | || ((get_constraint_type (lookup_constraint |
1630 | (curr_static_id->operand[nop].constraint)) | |
1631 | != CT_SPECIAL_MEMORY) | |
1632 | /* We still can reload address and if the address is | |
1633 | valid, we can remove subreg without reloading its | |
1634 | inner memory. */ | |
1635 | && valid_address_p (GET_MODE (subst), | |
1636 | regno_reg_rtx | |
1637 | [ira_class_hard_regs | |
1638 | [base_reg_class (GET_MODE (subst), | |
1639 | MEM_ADDR_SPACE (subst), | |
1640 | ADDRESS, SCRATCH)][0]], | |
1641 | MEM_ADDR_SPACE (subst)))) | |
1642 | { | |
ab5d2233 | 1643 | /* If we change the address for a paradoxical subreg of memory, the |
849fccf8 EB |
1644 | new address might violate the necessary alignment or the access |
1645 | might be slow; take this into consideration. We need not worry | |
ab5d2233 | 1646 | about accesses beyond allocated memory for paradoxical memory |
2e186411 AM |
1647 | subregs as we don't substitute such equiv memory (see processing |
1648 | equivalences in function lra_constraints) and because for spilled | |
1649 | pseudos we allocate stack memory enough for the biggest | |
198075e1 MF |
1650 | corresponding paradoxical subreg. |
1651 | ||
1652 | However, do not blindly simplify a (subreg (mem ...)) for | |
1653 | WORD_REGISTER_OPERATIONS targets as this may lead to loading junk | |
1654 | data into a register when the inner is narrower than outer or | |
1655 | missing important data from memory when the inner is wider than | |
1656 | outer. This rule only applies to modes that are no wider than | |
8eaff6ef VM |
1657 | a word. |
1658 | ||
1659 | If valid memory becomes invalid after subreg elimination | |
f8dc3fb2 VM |
1660 | and address might be different we still have to reload |
1661 | memory. | |
8eaff6ef | 1662 | */ |
f8dc3fb2 VM |
1663 | if ((! addr_was_valid |
1664 | || addr_is_valid | |
1665 | || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))) | |
8eaff6ef VM |
1666 | && !(maybe_ne (GET_MODE_PRECISION (mode), |
1667 | GET_MODE_PRECISION (innermode)) | |
1668 | && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) | |
1669 | && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) | |
1670 | && WORD_REGISTER_OPERATIONS) | |
198075e1 | 1671 | && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) |
e0bd6c9f | 1672 | && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) |
198075e1 | 1673 | || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) |
e0bd6c9f RS |
1674 | && targetm.slow_unaligned_access (innermode, |
1675 | MEM_ALIGN (reg))))) | |
2e186411 AM |
1676 | return true; |
1677 | ||
ab5d2233 EB |
1678 | *curr_id->operand_loc[nop] = operand; |
1679 | ||
1680 | /* But if the address was not valid, we cannot reload the MEM without | |
1681 | reloading the address first. */ | |
1682 | if (!addr_was_valid) | |
1683 | process_address (nop, false, &before, &after); | |
1684 | ||
2e186411 AM |
1685 | /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ |
1686 | enum reg_class rclass | |
1687 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
ab5d2233 | 1688 | if (get_reload_reg (curr_static_id->operand[nop].type, innermode, |
85419ac5 VM |
1689 | reg, rclass, NULL, |
1690 | TRUE, "slow/invalid mem", &new_reg)) | |
2e186411 AM |
1691 | { |
1692 | bool insert_before, insert_after; | |
1693 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1694 | ||
1695 | insert_before = (type != OP_OUT | |
bd4288c0 | 1696 | || partial_subreg_p (mode, innermode)); |
2e186411 AM |
1697 | insert_after = type != OP_IN; |
1698 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1699 | insert_after ? &after : NULL, | |
1700 | reg, new_reg); | |
1701 | } | |
2e186411 AM |
1702 | SUBREG_REG (operand) = new_reg; |
1703 | ||
1704 | /* Convert to MODE. */ | |
1705 | reg = operand; | |
ab5d2233 EB |
1706 | rclass |
1707 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
2e186411 | 1708 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, |
85419ac5 VM |
1709 | rclass, NULL, |
1710 | TRUE, "slow/invalid mem", &new_reg)) | |
2e186411 AM |
1711 | { |
1712 | bool insert_before, insert_after; | |
1713 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1714 | ||
1715 | insert_before = type != OP_OUT; | |
1716 | insert_after = type != OP_IN; | |
1717 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1718 | insert_after ? &after : NULL, | |
1719 | reg, new_reg); | |
1720 | } | |
1721 | *curr_id->operand_loc[nop] = new_reg; | |
1722 | lra_process_new_insns (curr_insn, before, after, | |
8eaff6ef | 1723 | "Inserting slow/invalid mem reload"); |
2e186411 AM |
1724 | return true; |
1725 | } | |
95831c01 | 1726 | |
ba38538f VM |
1727 | /* If the address was valid and became invalid, prefer to reload |
1728 | the memory. Typical case is when the index scale should | |
1729 | correspond the memory. */ | |
2e186411 | 1730 | *curr_id->operand_loc[nop] = operand; |
77850e96 MF |
1731 | /* Do not return false here as the MEM_P (reg) will be processed |
1732 | later in this function. */ | |
ba38538f VM |
1733 | } |
1734 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
55a2c322 VM |
1735 | { |
1736 | alter_subreg (curr_id->operand_loc[nop], false); | |
1737 | return true; | |
1738 | } | |
895ff86f VM |
1739 | else if (CONSTANT_P (reg)) |
1740 | { | |
1741 | /* Try to simplify subreg of constant. It is usually result of | |
1742 | equivalence substitution. */ | |
1743 | if (innermode == VOIDmode | |
1744 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1745 | innermode = curr_static_id->operand[nop].mode; | |
1746 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1747 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1748 | { | |
1749 | *curr_id->operand_loc[nop] = new_reg; | |
1750 | return true; | |
1751 | } | |
1752 | } | |
55a2c322 VM |
1753 | /* Put constant into memory when we have mixed modes. It generates |
1754 | a better code in most cases as it does not need a secondary | |
1755 | reload memory. It also prevents LRA looping when LRA is using | |
1756 | secondary reload memory again and again. */ | |
1757 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1758 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1759 | { | |
1760 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1761 | alter_subreg (curr_id->operand_loc[nop], false); | |
1762 | return true; | |
1763 | } | |
1764 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1765 | if there may be a problem accessing OPERAND in the outer | |
1766 | mode. */ | |
1767 | if ((REG_P (reg) | |
1768 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1769 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1770 | /* Don't reload paradoxical subregs because we could be looping | |
1771 | having repeatedly final regno out of hard regs range. */ | |
ad474626 RS |
1772 | && (hard_regno_nregs (hard_regno, innermode) |
1773 | >= hard_regno_nregs (hard_regno, mode)) | |
895ff86f | 1774 | && simplify_subreg_regno (hard_regno, innermode, |
2c62cbaa VM |
1775 | SUBREG_BYTE (operand), mode) < 0 |
1776 | /* Don't reload subreg for matching reload. It is actually | |
1777 | valid subreg in LRA. */ | |
1778 | && ! LRA_SUBREG_P (operand)) | |
55a2c322 VM |
1779 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1780 | { | |
6e23f296 VM |
1781 | enum reg_class rclass; |
1782 | ||
7613fa50 VM |
1783 | if (REG_P (reg)) |
1784 | /* There is a big probability that we will get the same class | |
6e23f296 VM |
1785 | for the new pseudo and we will get the same insn which |
1786 | means infinite looping. So spill the new pseudo. */ | |
1787 | rclass = NO_REGS; | |
1788 | else | |
1789 | /* The class will be defined later in curr_insn_transform. */ | |
1790 | rclass | |
1791 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
55a2c322 | 1792 | |
25bb0bb5 | 1793 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
85419ac5 VM |
1794 | rclass, NULL, |
1795 | TRUE, "subreg reg", &new_reg)) | |
55a2c322 | 1796 | { |
4f0bee4c | 1797 | bool insert_before, insert_after; |
2b778c9d | 1798 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
4f0bee4c WM |
1799 | |
1800 | insert_before = (type != OP_OUT | |
9eaf97d6 | 1801 | || read_modify_subreg_p (operand)); |
4f0bee4c WM |
1802 | insert_after = (type != OP_IN); |
1803 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1804 | insert_after ? &after : NULL, | |
1805 | reg, new_reg); | |
55a2c322 VM |
1806 | } |
1807 | SUBREG_REG (operand) = new_reg; | |
1808 | lra_process_new_insns (curr_insn, before, after, | |
1809 | "Inserting subreg reload"); | |
1810 | return true; | |
1811 | } | |
4f0bee4c WM |
1812 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1813 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1814 | instead of the outermode, so the size of the hardreg may not be enough | |
1815 | to contain the outermode operand, in that case we may need to insert | |
1816 | reload for the reg. For the following two types of paradoxical subreg, | |
1817 | we need to insert reload: | |
1818 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1819 | other hardreg to contain the outermode operand | |
1820 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1821 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1822 | ||
1823 | Here is a paradoxical subreg example showing how the reload is generated: | |
1824 | ||
1825 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1826 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1827 | ||
1828 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1829 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1830 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1831 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1832 | After reload is inserted: | |
1833 | ||
1834 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1835 | (reg:DI 107 [ __comp ])) -1 | |
1836 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1837 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1838 | ||
1839 | Two reload hard registers will be allocated to reg180 to save TImode data | |
8fd96632 RS |
1840 | in LRA_assign. |
1841 | ||
1842 | For LRA pseudos this should normally be handled by the biggest_mode | |
1843 | mechanism. However, it's possible for new uses of an LRA pseudo | |
1844 | to be introduced after we've allocated it, such as when undoing | |
1845 | inheritance, and the allocated register might not then be appropriate | |
1846 | for the new uses. */ | |
4f0bee4c WM |
1847 | else if (REG_P (reg) |
1848 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
497498c8 RS |
1849 | && paradoxical_subreg_p (operand) |
1850 | && (inner_hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1851 | && ((hard_regno | |
1852 | = simplify_subreg_regno (inner_hard_regno, innermode, | |
1853 | SUBREG_BYTE (operand), mode)) < 0 | |
1854 | || ((hard_regno_nregs (inner_hard_regno, innermode) | |
1855 | < hard_regno_nregs (hard_regno, mode)) | |
1856 | && (regclass = lra_get_allocno_class (REGNO (reg))) | |
1857 | && (type != OP_IN | |
1858 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
1859 | mode, hard_regno) | |
1860 | || overlaps_hard_reg_set_p (lra_no_alloc_regs, | |
1861 | mode, hard_regno))))) | |
4f0bee4c WM |
1862 | { |
1863 | /* The class will be defined later in curr_insn_transform. */ | |
1864 | enum reg_class rclass | |
1865 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1866 | ||
1867 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
85419ac5 VM |
1868 | rclass, NULL, |
1869 | TRUE, "paradoxical subreg", &new_reg)) | |
4f0bee4c WM |
1870 | { |
1871 | rtx subreg; | |
1872 | bool insert_before, insert_after; | |
1873 | ||
1874 | PUT_MODE (new_reg, mode); | |
ea09f50d | 1875 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
4f0bee4c WM |
1876 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1877 | ||
1878 | insert_before = (type != OP_OUT); | |
1879 | insert_after = (type != OP_IN); | |
1880 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1881 | insert_after ? &after : NULL, | |
1882 | reg, subreg); | |
1883 | } | |
1884 | SUBREG_REG (operand) = new_reg; | |
1885 | lra_process_new_insns (curr_insn, before, after, | |
1886 | "Inserting paradoxical subreg reload"); | |
1887 | return true; | |
1888 | } | |
55a2c322 VM |
1889 | return false; |
1890 | } | |
1891 | ||
1892 | /* Return TRUE if X refers for a hard register from SET. */ | |
1893 | static bool | |
1894 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1895 | { | |
1896 | int i, j, x_hard_regno; | |
ef4bddc2 | 1897 | machine_mode mode; |
55a2c322 VM |
1898 | const char *fmt; |
1899 | enum rtx_code code; | |
1900 | ||
1901 | if (x == NULL_RTX) | |
1902 | return false; | |
1903 | code = GET_CODE (x); | |
1904 | mode = GET_MODE (x); | |
145d4e1a | 1905 | |
55a2c322 VM |
1906 | if (code == SUBREG) |
1907 | { | |
145d4e1a AV |
1908 | /* For all SUBREGs we want to check whether the full multi-register |
1909 | overlaps the set. For normal SUBREGs this means 'get_hard_regno' of | |
1910 | the inner register, for paradoxical SUBREGs this means the | |
1911 | 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is | |
1912 | fine. Use the wider mode for all cases. */ | |
1913 | rtx subreg = SUBREG_REG (x); | |
bd5a2c67 | 1914 | mode = wider_subreg_mode (x); |
145d4e1a AV |
1915 | if (mode == GET_MODE (subreg)) |
1916 | { | |
1917 | x = subreg; | |
1918 | code = GET_CODE (x); | |
1919 | } | |
55a2c322 | 1920 | } |
f4eafc30 | 1921 | |
145d4e1a | 1922 | if (REG_P (x) || SUBREG_P (x)) |
55a2c322 | 1923 | { |
265a749f | 1924 | x_hard_regno = get_hard_regno (x); |
55a2c322 VM |
1925 | return (x_hard_regno >= 0 |
1926 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1927 | } | |
55a2c322 VM |
1928 | fmt = GET_RTX_FORMAT (code); |
1929 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1930 | { | |
1931 | if (fmt[i] == 'e') | |
1932 | { | |
1933 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1934 | return true; | |
1935 | } | |
1936 | else if (fmt[i] == 'E') | |
1937 | { | |
1938 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1939 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1940 | return true; | |
1941 | } | |
1942 | } | |
1943 | return false; | |
1944 | } | |
1945 | ||
1946 | /* Return true if OP is a spilled pseudo. */ | |
1947 | static inline bool | |
1948 | spilled_pseudo_p (rtx op) | |
1949 | { | |
1950 | return (REG_P (op) | |
1951 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1952 | } | |
1953 | ||
1954 | /* Return true if X is a general constant. */ | |
1955 | static inline bool | |
1956 | general_constant_p (rtx x) | |
1957 | { | |
1958 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1959 | } | |
1960 | ||
2c62cbaa VM |
1961 | static bool |
1962 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1963 | { | |
1964 | if (cl == NO_REGS) | |
1965 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1966 | return in_class_p (reg, cl, NULL); | |
1967 | } | |
1968 | ||
3c954213 VM |
1969 | /* Return true if SET of RCLASS contains no hard regs which can be |
1970 | used in MODE. */ | |
1971 | static bool | |
1972 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1973 | HARD_REG_SET &set, | |
b8506a8a | 1974 | machine_mode mode) |
3c954213 VM |
1975 | { |
1976 | HARD_REG_SET temp; | |
1977 | ||
c07ad89a | 1978 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
d15e5131 | 1979 | temp = set & ~lra_no_alloc_regs; |
3c954213 VM |
1980 | return (hard_reg_set_subset_p |
1981 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1982 | } | |
1983 | ||
9b195552 VM |
1984 | |
1985 | /* Used to check validity info about small class input operands. It | |
1986 | should be incremented at start of processing an insn | |
1987 | alternative. */ | |
1988 | static unsigned int curr_small_class_check = 0; | |
1989 | ||
a25f3e8e RS |
1990 | /* Update number of used inputs of class OP_CLASS for operand NOP |
1991 | of alternative NALT. Return true if we have more such class operands | |
1992 | than the number of available regs. */ | |
9b195552 | 1993 | static bool |
a25f3e8e RS |
1994 | update_and_check_small_class_inputs (int nop, int nalt, |
1995 | enum reg_class op_class) | |
9b195552 VM |
1996 | { |
1997 | static unsigned int small_class_check[LIM_REG_CLASSES]; | |
1998 | static int small_class_input_nums[LIM_REG_CLASSES]; | |
1999 | ||
2000 | if (SMALL_REGISTER_CLASS_P (op_class) | |
2001 | /* We are interesting in classes became small because of fixing | |
2002 | some hard regs, e.g. by an user through GCC options. */ | |
2003 | && hard_reg_set_intersect_p (reg_class_contents[op_class], | |
2004 | ira_no_alloc_regs) | |
2005 | && (curr_static_id->operand[nop].type != OP_OUT | |
a25f3e8e | 2006 | || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt))) |
9b195552 VM |
2007 | { |
2008 | if (small_class_check[op_class] == curr_small_class_check) | |
2009 | small_class_input_nums[op_class]++; | |
2010 | else | |
2011 | { | |
2012 | small_class_check[op_class] = curr_small_class_check; | |
2013 | small_class_input_nums[op_class] = 1; | |
2014 | } | |
2015 | if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) | |
2016 | return true; | |
2017 | } | |
2018 | return false; | |
2019 | } | |
2020 | ||
55a2c322 VM |
2021 | /* Major function to choose the current insn alternative and what |
2022 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
2023 | negative we should consider only this alternative. Return false if | |
67914693 | 2024 | we cannot choose the alternative or find how to reload the |
55a2c322 VM |
2025 | operands. */ |
2026 | static bool | |
2027 | process_alt_operands (int only_alternative) | |
2028 | { | |
2029 | bool ok_p = false; | |
36ff9dfb | 2030 | int nop, overall, nalt; |
55a2c322 VM |
2031 | int n_alternatives = curr_static_id->n_alternatives; |
2032 | int n_operands = curr_static_id->n_operands; | |
2033 | /* LOSERS counts the operands that don't fit this alternative and | |
2034 | would require loading. */ | |
2035 | int losers; | |
feca7b89 | 2036 | int addr_losers; |
55a2c322 VM |
2037 | /* REJECT is a count of how undesirable this alternative says it is |
2038 | if any reloading is required. If the alternative matches exactly | |
2039 | then REJECT is ignored, but otherwise it gets this much counted | |
2040 | against it in addition to the reloading needed. */ | |
2041 | int reject; | |
feca7b89 VM |
2042 | /* This is defined by '!' or '?' alternative constraint and added to |
2043 | reject. But in some cases it can be ignored. */ | |
2044 | int static_reject; | |
d1457701 | 2045 | int op_reject; |
55a2c322 VM |
2046 | /* The number of elements in the following array. */ |
2047 | int early_clobbered_regs_num; | |
2048 | /* Numbers of operands which are early clobber registers. */ | |
2049 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
2050 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
2051 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
85419ac5 | 2052 | HARD_REG_SET curr_alt_exclude_start_hard_regs[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
2053 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; |
2054 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
2055 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
2056 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
2057 | /* The number of elements in the following array. */ | |
2058 | int curr_alt_dont_inherit_ops_num; | |
2059 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
2060 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
2061 | rtx op; | |
2062 | /* The register when the operand is a subreg of register, otherwise the | |
2063 | operand itself. */ | |
2064 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
2065 | /* The register if the operand is a register or subreg of register, | |
2066 | otherwise NULL. */ | |
2067 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
2068 | int hard_regno[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 2069 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
2070 | int reload_nregs, reload_sum; |
2071 | bool costly_p; | |
2072 | enum reg_class cl; | |
2073 | ||
2074 | /* Calculate some data common for all alternatives to speed up the | |
2075 | function. */ | |
2076 | for (nop = 0; nop < n_operands; nop++) | |
2077 | { | |
7214306b VM |
2078 | rtx reg; |
2079 | ||
55a2c322 VM |
2080 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
2081 | /* The real hard regno of the operand after the allocation. */ | |
265a749f | 2082 | hard_regno[nop] = get_hard_regno (op); |
f4eafc30 | 2083 | |
7214306b VM |
2084 | operand_reg[nop] = reg = op; |
2085 | biggest_mode[nop] = GET_MODE (op); | |
2086 | if (GET_CODE (op) == SUBREG) | |
55a2c322 | 2087 | { |
bd5a2c67 | 2088 | biggest_mode[nop] = wider_subreg_mode (op); |
7214306b | 2089 | operand_reg[nop] = reg = SUBREG_REG (op); |
55a2c322 | 2090 | } |
7214306b | 2091 | if (! REG_P (reg)) |
55a2c322 | 2092 | operand_reg[nop] = NULL_RTX; |
7214306b VM |
2093 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
2094 | || ((int) REGNO (reg) | |
2095 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
2096 | no_subreg_reg_operand[nop] = reg; | |
2097 | else | |
2098 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
2099 | /* Just use natural mode for elimination result. It should | |
2100 | be enough for extra constraints hooks. */ | |
2101 | = regno_reg_rtx[hard_regno[nop]]; | |
55a2c322 VM |
2102 | } |
2103 | ||
2104 | /* The constraints are made of several alternatives. Each operand's | |
2105 | constraint looks like foo,bar,... with commas separating the | |
2106 | alternatives. The first alternatives for all operands go | |
2107 | together, the second alternatives go together, etc. | |
2108 | ||
2109 | First loop over alternatives. */ | |
9840b2fa | 2110 | alternative_mask preferred = curr_id->preferred_alternatives; |
4cc8d9d2 | 2111 | if (only_alternative >= 0) |
9840b2fa | 2112 | preferred &= ALTERNATIVE_BIT (only_alternative); |
4cc8d9d2 | 2113 | |
55a2c322 VM |
2114 | for (nalt = 0; nalt < n_alternatives; nalt++) |
2115 | { | |
2116 | /* Loop over operands for one constraint alternative. */ | |
9840b2fa | 2117 | if (!TEST_BIT (preferred, nalt)) |
55a2c322 VM |
2118 | continue; |
2119 | ||
dbe7895c | 2120 | bool matching_early_clobber[MAX_RECOG_OPERANDS]; |
9b195552 | 2121 | curr_small_class_check++; |
feca7b89 VM |
2122 | overall = losers = addr_losers = 0; |
2123 | static_reject = reject = reload_nregs = reload_sum = 0; | |
55a2c322 | 2124 | for (nop = 0; nop < n_operands; nop++) |
cb1cca12 VM |
2125 | { |
2126 | int inc = (curr_static_id | |
2127 | ->operand_alternative[nalt * n_operands + nop].reject); | |
2128 | if (lra_dump_file != NULL && inc != 0) | |
2129 | fprintf (lra_dump_file, | |
2130 | " Staticly defined alt reject+=%d\n", inc); | |
feca7b89 | 2131 | static_reject += inc; |
dbe7895c | 2132 | matching_early_clobber[nop] = 0; |
cb1cca12 | 2133 | } |
feca7b89 | 2134 | reject += static_reject; |
55a2c322 VM |
2135 | early_clobbered_regs_num = 0; |
2136 | ||
2137 | for (nop = 0; nop < n_operands; nop++) | |
2138 | { | |
2139 | const char *p; | |
2140 | char *end; | |
2141 | int len, c, m, i, opalt_num, this_alternative_matches; | |
2142 | bool win, did_match, offmemok, early_clobber_p; | |
2143 | /* false => this operand can be reloaded somehow for this | |
2144 | alternative. */ | |
2145 | bool badop; | |
2146 | /* true => this operand can be reloaded if the alternative | |
2147 | allows regs. */ | |
2148 | bool winreg; | |
2149 | /* True if a constant forced into memory would be OK for | |
2150 | this operand. */ | |
2151 | bool constmemok; | |
2152 | enum reg_class this_alternative, this_costly_alternative; | |
2153 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
85419ac5 | 2154 | HARD_REG_SET this_alternative_exclude_start_hard_regs; |
55a2c322 VM |
2155 | bool this_alternative_match_win, this_alternative_win; |
2156 | bool this_alternative_offmemok; | |
80f466c4 | 2157 | bool scratch_p; |
ef4bddc2 | 2158 | machine_mode mode; |
777e635f | 2159 | enum constraint_num cn; |
55a2c322 VM |
2160 | |
2161 | opalt_num = nalt * n_operands + nop; | |
2162 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
2163 | { | |
2164 | /* Fast track for no constraints at all. */ | |
2165 | curr_alt[nop] = NO_REGS; | |
2166 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
2167 | curr_alt_win[nop] = true; | |
2168 | curr_alt_match_win[nop] = false; | |
2169 | curr_alt_offmemok[nop] = false; | |
2170 | curr_alt_matches[nop] = -1; | |
2171 | continue; | |
2172 | } | |
f4eafc30 | 2173 | |
55a2c322 VM |
2174 | op = no_subreg_reg_operand[nop]; |
2175 | mode = curr_operand_mode[nop]; | |
2176 | ||
2177 | win = did_match = winreg = offmemok = constmemok = false; | |
2178 | badop = true; | |
f4eafc30 | 2179 | |
55a2c322 VM |
2180 | early_clobber_p = false; |
2181 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
f4eafc30 | 2182 | |
55a2c322 VM |
2183 | this_costly_alternative = this_alternative = NO_REGS; |
2184 | /* We update set of possible hard regs besides its class | |
2185 | because reg class might be inaccurate. For example, | |
2186 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
2187 | is translated in HI_REGS because classes are merged by | |
2188 | pairs and there is no accurate intermediate class. */ | |
2189 | CLEAR_HARD_REG_SET (this_alternative_set); | |
2190 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
85419ac5 | 2191 | CLEAR_HARD_REG_SET (this_alternative_exclude_start_hard_regs); |
55a2c322 VM |
2192 | this_alternative_win = false; |
2193 | this_alternative_match_win = false; | |
2194 | this_alternative_offmemok = false; | |
2195 | this_alternative_matches = -1; | |
f4eafc30 | 2196 | |
55a2c322 VM |
2197 | /* An empty constraint should be excluded by the fast |
2198 | track. */ | |
2199 | lra_assert (*p != 0 && *p != ','); | |
f4eafc30 | 2200 | |
d1457701 | 2201 | op_reject = 0; |
55a2c322 VM |
2202 | /* Scan this alternative's specs for this operand; set WIN |
2203 | if the operand fits any letter in this alternative. | |
2204 | Otherwise, clear BADOP if this operand could fit some | |
2205 | letter after reloads, or set WINREG if this operand could | |
2206 | fit after reloads provided the constraint allows some | |
2207 | registers. */ | |
2208 | costly_p = false; | |
2209 | do | |
2210 | { | |
2211 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
2212 | { | |
2213 | case '\0': | |
2214 | len = 0; | |
2215 | break; | |
2216 | case ',': | |
2217 | c = '\0'; | |
2218 | break; | |
f4eafc30 | 2219 | |
55a2c322 VM |
2220 | case '&': |
2221 | early_clobber_p = true; | |
2222 | break; | |
f4eafc30 | 2223 | |
d1457701 VM |
2224 | case '$': |
2225 | op_reject += LRA_MAX_REJECT; | |
2226 | break; | |
2227 | case '^': | |
2228 | op_reject += LRA_LOSER_COST_FACTOR; | |
2229 | break; | |
2230 | ||
55a2c322 VM |
2231 | case '#': |
2232 | /* Ignore rest of this alternative. */ | |
2233 | c = '\0'; | |
2234 | break; | |
f4eafc30 | 2235 | |
55a2c322 VM |
2236 | case '0': case '1': case '2': case '3': case '4': |
2237 | case '5': case '6': case '7': case '8': case '9': | |
2238 | { | |
2239 | int m_hregno; | |
2240 | bool match_p; | |
f4eafc30 | 2241 | |
55a2c322 VM |
2242 | m = strtoul (p, &end, 10); |
2243 | p = end; | |
2244 | len = 0; | |
2245 | lra_assert (nop > m); | |
f4eafc30 | 2246 | |
00224b1a RS |
2247 | /* Reject matches if we don't know which operand is |
2248 | bigger. This situation would arguably be a bug in | |
2249 | an .md pattern, but could also occur in a user asm. */ | |
2250 | if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]), | |
2251 | GET_MODE_SIZE (biggest_mode[nop]))) | |
2252 | break; | |
2253 | ||
a426543a VM |
2254 | /* Don't match wrong asm insn operands for proper |
2255 | diagnostic later. */ | |
2256 | if (INSN_CODE (curr_insn) < 0 | |
2257 | && (curr_operand_mode[m] == BLKmode | |
2258 | || curr_operand_mode[nop] == BLKmode) | |
2259 | && curr_operand_mode[m] != curr_operand_mode[nop]) | |
2260 | break; | |
2261 | ||
265a749f | 2262 | m_hregno = get_hard_regno (*curr_id->operand_loc[m]); |
55a2c322 VM |
2263 | /* We are supposed to match a previous operand. |
2264 | If we do, we win if that one did. If we do | |
2265 | not, count both of the operands as losers. | |
2266 | (This is too conservative, since most of the | |
2267 | time only a single reload insn will be needed | |
2268 | to make the two operands win. As a result, | |
2269 | this alternative may be rejected when it is | |
2270 | actually desirable.) */ | |
2271 | match_p = false; | |
2272 | if (operands_match_p (*curr_id->operand_loc[nop], | |
2273 | *curr_id->operand_loc[m], m_hregno)) | |
2274 | { | |
2275 | /* We should reject matching of an early | |
2276 | clobber operand if the matching operand is | |
2277 | not dying in the insn. */ | |
a25f3e8e RS |
2278 | if (!TEST_BIT (curr_static_id->operand[m] |
2279 | .early_clobber_alts, nalt) | |
55a2c322 VM |
2280 | || operand_reg[nop] == NULL_RTX |
2281 | || (find_regno_note (curr_insn, REG_DEAD, | |
1c86bd80 VM |
2282 | REGNO (op)) |
2283 | || REGNO (op) == REGNO (operand_reg[m]))) | |
55a2c322 VM |
2284 | match_p = true; |
2285 | } | |
2286 | if (match_p) | |
2287 | { | |
2288 | /* If we are matching a non-offsettable | |
2289 | address where an offsettable address was | |
2290 | expected, then we must reject this | |
2291 | combination, because we can't reload | |
2292 | it. */ | |
2293 | if (curr_alt_offmemok[m] | |
2294 | && MEM_P (*curr_id->operand_loc[m]) | |
2295 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
2296 | continue; | |
55a2c322 VM |
2297 | } |
2298 | else | |
2299 | { | |
9f41de41 VM |
2300 | /* If the operands do not match and one |
2301 | operand is INOUT, we can not match them. | |
2302 | Try other possibilities, e.g. other | |
2303 | alternatives or commutative operand | |
2304 | exchange. */ | |
2305 | if (curr_static_id->operand[nop].type == OP_INOUT | |
2306 | || curr_static_id->operand[m].type == OP_INOUT) | |
2307 | break; | |
2f0b80c7 | 2308 | /* Operands don't match. If the operands are |
613caed2 VM |
2309 | different user defined explicit hard |
2310 | registers, then we cannot make them match | |
2311 | when one is early clobber operand. */ | |
2f0b80c7 PB |
2312 | if ((REG_P (*curr_id->operand_loc[nop]) |
2313 | || SUBREG_P (*curr_id->operand_loc[nop])) | |
2314 | && (REG_P (*curr_id->operand_loc[m]) | |
2315 | || SUBREG_P (*curr_id->operand_loc[m]))) | |
2316 | { | |
2317 | rtx nop_reg = *curr_id->operand_loc[nop]; | |
2318 | if (SUBREG_P (nop_reg)) | |
2319 | nop_reg = SUBREG_REG (nop_reg); | |
2320 | rtx m_reg = *curr_id->operand_loc[m]; | |
2321 | if (SUBREG_P (m_reg)) | |
2322 | m_reg = SUBREG_REG (m_reg); | |
2323 | ||
2324 | if (REG_P (nop_reg) | |
2325 | && HARD_REGISTER_P (nop_reg) | |
2326 | && REG_USERVAR_P (nop_reg) | |
2327 | && REG_P (m_reg) | |
2328 | && HARD_REGISTER_P (m_reg) | |
2329 | && REG_USERVAR_P (m_reg)) | |
613caed2 VM |
2330 | { |
2331 | int i; | |
2332 | ||
2333 | for (i = 0; i < early_clobbered_regs_num; i++) | |
2334 | if (m == early_clobbered_nops[i]) | |
2335 | break; | |
2336 | if (i < early_clobbered_regs_num | |
2337 | || early_clobber_p) | |
2338 | break; | |
2339 | } | |
2f0b80c7 | 2340 | } |
2f0b80c7 PB |
2341 | /* Both operands must allow a reload register, |
2342 | otherwise we cannot make them match. */ | |
55a2c322 VM |
2343 | if (curr_alt[m] == NO_REGS) |
2344 | break; | |
2345 | /* Retroactively mark the operand we had to | |
2346 | match as a loser, if it wasn't already and | |
2347 | it wasn't matched to a register constraint | |
2348 | (e.g it might be matched by memory). */ | |
2349 | if (curr_alt_win[m] | |
2350 | && (operand_reg[m] == NULL_RTX | |
2351 | || hard_regno[m] < 0)) | |
2352 | { | |
2353 | losers++; | |
2354 | reload_nregs | |
2355 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
2356 | [GET_MODE (*curr_id->operand_loc[m])]); | |
2357 | } | |
f4eafc30 | 2358 | |
f4581282 VM |
2359 | /* Prefer matching earlyclobber alternative as |
2360 | it results in less hard regs required for | |
2361 | the insn than a non-matching earlyclobber | |
2362 | alternative. */ | |
a25f3e8e RS |
2363 | if (TEST_BIT (curr_static_id->operand[m] |
2364 | .early_clobber_alts, nalt)) | |
f4581282 VM |
2365 | { |
2366 | if (lra_dump_file != NULL) | |
2367 | fprintf | |
2368 | (lra_dump_file, | |
2369 | " %d Matching earlyclobber alt:" | |
2370 | " reject--\n", | |
2371 | nop); | |
dbe7895c AS |
2372 | if (!matching_early_clobber[m]) |
2373 | { | |
2374 | reject--; | |
2375 | matching_early_clobber[m] = 1; | |
2376 | } | |
f4581282 VM |
2377 | } |
2378 | /* Otherwise we prefer no matching | |
2379 | alternatives because it gives more freedom | |
2380 | in RA. */ | |
2381 | else if (operand_reg[nop] == NULL_RTX | |
2382 | || (find_regno_note (curr_insn, REG_DEAD, | |
2383 | REGNO (operand_reg[nop])) | |
2384 | == NULL_RTX)) | |
cb1cca12 VM |
2385 | { |
2386 | if (lra_dump_file != NULL) | |
2387 | fprintf | |
2388 | (lra_dump_file, | |
2389 | " %d Matching alt: reject+=2\n", | |
2390 | nop); | |
2391 | reject += 2; | |
2392 | } | |
55a2c322 VM |
2393 | } |
2394 | /* If we have to reload this operand and some | |
2395 | previous operand also had to match the same | |
2396 | thing as this operand, we don't know how to do | |
2397 | that. */ | |
2398 | if (!match_p || !curr_alt_win[m]) | |
2399 | { | |
2400 | for (i = 0; i < nop; i++) | |
2401 | if (curr_alt_matches[i] == m) | |
2402 | break; | |
2403 | if (i < nop) | |
2404 | break; | |
2405 | } | |
2406 | else | |
2407 | did_match = true; | |
f4eafc30 | 2408 | |
28ed1460 | 2409 | this_alternative_matches = m; |
55a2c322 VM |
2410 | /* This can be fixed with reloads if the operand |
2411 | we are supposed to match can be fixed with | |
2412 | reloads. */ | |
2413 | badop = false; | |
2414 | this_alternative = curr_alt[m]; | |
6576d245 | 2415 | this_alternative_set = curr_alt_set[m]; |
85419ac5 VM |
2416 | this_alternative_exclude_start_hard_regs |
2417 | = curr_alt_exclude_start_hard_regs[m]; | |
821b7577 | 2418 | winreg = this_alternative != NO_REGS; |
55a2c322 VM |
2419 | break; |
2420 | } | |
f4eafc30 | 2421 | |
55a2c322 VM |
2422 | case 'g': |
2423 | if (MEM_P (op) | |
2424 | || general_constant_p (op) | |
2425 | || spilled_pseudo_p (op)) | |
2426 | win = true; | |
777e635f | 2427 | cl = GENERAL_REGS; |
55a2c322 | 2428 | goto reg; |
f4eafc30 | 2429 | |
55a2c322 | 2430 | default: |
777e635f RS |
2431 | cn = lookup_constraint (p); |
2432 | switch (get_constraint_type (cn)) | |
55a2c322 | 2433 | { |
777e635f RS |
2434 | case CT_REGISTER: |
2435 | cl = reg_class_for_constraint (cn); | |
2436 | if (cl != NO_REGS) | |
2437 | goto reg; | |
2438 | break; | |
f4eafc30 | 2439 | |
d9c35eee RS |
2440 | case CT_CONST_INT: |
2441 | if (CONST_INT_P (op) | |
2442 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2443 | win = true; | |
2444 | break; | |
2445 | ||
777e635f | 2446 | case CT_MEMORY: |
0d37e2d3 | 2447 | case CT_RELAXED_MEMORY: |
2e0aa43f | 2448 | if (MEM_P (op) |
2449 | && satisfies_memory_constraint_p (op, cn)) | |
777e635f RS |
2450 | win = true; |
2451 | else if (spilled_pseudo_p (op)) | |
2452 | win = true; | |
2453 | ||
2454 | /* If we didn't already win, we can reload constants | |
2455 | via force_const_mem or put the pseudo value into | |
2456 | memory, or make other memory by reloading the | |
2457 | address like for 'o'. */ | |
2458 | if (CONST_POOL_OK_P (mode, op) | |
987b67f1 VM |
2459 | || MEM_P (op) || REG_P (op) |
2460 | /* We can restore the equiv insn by a | |
2461 | reload. */ | |
2462 | || equiv_substition_p[nop]) | |
777e635f RS |
2463 | badop = false; |
2464 | constmemok = true; | |
2465 | offmemok = true; | |
2466 | break; | |
2467 | ||
2468 | case CT_ADDRESS: | |
998fd141 AO |
2469 | /* An asm operand with an address constraint |
2470 | that doesn't satisfy address_operand has | |
2471 | is_address cleared, so that we don't try to | |
2472 | make a non-address fit. */ | |
2473 | if (!curr_static_id->operand[nop].is_address) | |
2474 | break; | |
777e635f RS |
2475 | /* If we didn't already win, we can reload the address |
2476 | into a base register. */ | |
2477 | if (satisfies_address_constraint_p (op, cn)) | |
2478 | win = true; | |
2479 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2480 | ADDRESS, SCRATCH); | |
2481 | badop = false; | |
2482 | goto reg; | |
2483 | ||
2484 | case CT_FIXED_FORM: | |
2485 | if (constraint_satisfied_p (op, cn)) | |
55a2c322 | 2486 | win = true; |
55a2c322 | 2487 | break; |
9eb1ca69 VM |
2488 | |
2489 | case CT_SPECIAL_MEMORY: | |
4de7b010 | 2490 | if (satisfies_memory_constraint_p (op, cn)) |
9eb1ca69 VM |
2491 | win = true; |
2492 | else if (spilled_pseudo_p (op)) | |
2493 | win = true; | |
2494 | break; | |
55a2c322 | 2495 | } |
777e635f | 2496 | break; |
f4eafc30 | 2497 | |
777e635f | 2498 | reg: |
a5b821e4 JJ |
2499 | if (mode == BLKmode) |
2500 | break; | |
55a2c322 | 2501 | this_alternative = reg_class_subunion[this_alternative][cl]; |
274a4d29 VM |
2502 | if (hard_reg_set_subset_p (this_alternative_set, |
2503 | reg_class_contents[cl])) | |
2504 | this_alternative_exclude_start_hard_regs | |
2505 | = ira_exclude_class_mode_regs[cl][mode]; | |
2506 | else if (!hard_reg_set_subset_p (reg_class_contents[cl], | |
2507 | this_alternative_set)) | |
2508 | this_alternative_exclude_start_hard_regs | |
2509 | |= ira_exclude_class_mode_regs[cl][mode]; | |
44942965 | 2510 | this_alternative_set |= reg_class_contents[cl]; |
55a2c322 VM |
2511 | if (costly_p) |
2512 | { | |
2513 | this_costly_alternative | |
2514 | = reg_class_subunion[this_costly_alternative][cl]; | |
44942965 | 2515 | this_costly_alternative_set |= reg_class_contents[cl]; |
55a2c322 | 2516 | } |
55a2c322 VM |
2517 | winreg = true; |
2518 | if (REG_P (op)) | |
2519 | { | |
2520 | if (hard_regno[nop] >= 0 | |
2521 | && in_hard_reg_set_p (this_alternative_set, | |
85419ac5 VM |
2522 | mode, hard_regno[nop]) |
2523 | && !TEST_HARD_REG_BIT | |
2524 | (this_alternative_exclude_start_hard_regs, | |
2525 | hard_regno[nop])) | |
55a2c322 VM |
2526 | win = true; |
2527 | else if (hard_regno[nop] < 0 | |
2528 | && in_class_p (op, this_alternative, NULL)) | |
2529 | win = true; | |
2530 | } | |
2531 | break; | |
2532 | } | |
2533 | if (c != ' ' && c != '\t') | |
2534 | costly_p = c == '*'; | |
2535 | } | |
2536 | while ((p += len), c); | |
f4eafc30 | 2537 | |
80f466c4 | 2538 | scratch_p = (operand_reg[nop] != NULL_RTX |
44fbc9c6 | 2539 | && ira_former_scratch_p (REGNO (operand_reg[nop]))); |
55a2c322 VM |
2540 | /* Record which operands fit this alternative. */ |
2541 | if (win) | |
2542 | { | |
2543 | this_alternative_win = true; | |
2544 | if (operand_reg[nop] != NULL_RTX) | |
2545 | { | |
2546 | if (hard_regno[nop] >= 0) | |
2547 | { | |
2548 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2549 | mode, hard_regno[nop])) | |
cb1cca12 VM |
2550 | { |
2551 | if (lra_dump_file != NULL) | |
2552 | fprintf (lra_dump_file, | |
2553 | " %d Costly set: reject++\n", | |
2554 | nop); | |
2555 | reject++; | |
2556 | } | |
55a2c322 VM |
2557 | } |
2558 | else | |
2559 | { | |
80f466c4 VM |
2560 | /* Prefer won reg to spilled pseudo under other |
2561 | equal conditions for possibe inheritance. */ | |
2562 | if (! scratch_p) | |
2563 | { | |
2564 | if (lra_dump_file != NULL) | |
2565 | fprintf | |
2566 | (lra_dump_file, | |
2567 | " %d Non pseudo reload: reject++\n", | |
2568 | nop); | |
2569 | reject++; | |
2570 | } | |
55a2c322 VM |
2571 | if (in_class_p (operand_reg[nop], |
2572 | this_costly_alternative, NULL)) | |
cb1cca12 VM |
2573 | { |
2574 | if (lra_dump_file != NULL) | |
2575 | fprintf | |
2576 | (lra_dump_file, | |
2577 | " %d Non pseudo costly reload:" | |
2578 | " reject++\n", | |
2579 | nop); | |
2580 | reject++; | |
2581 | } | |
55a2c322 | 2582 | } |
9c582551 | 2583 | /* We simulate the behavior of old reload here. |
55a2c322 VM |
2584 | Although scratches need hard registers and it |
2585 | might result in spilling other pseudos, no reload | |
2586 | insns are generated for the scratches. So it | |
2587 | might cost something but probably less than old | |
2588 | reload pass believes. */ | |
80f466c4 | 2589 | if (scratch_p) |
cb1cca12 VM |
2590 | { |
2591 | if (lra_dump_file != NULL) | |
2592 | fprintf (lra_dump_file, | |
80f466c4 | 2593 | " %d Scratch win: reject+=2\n", |
cb1cca12 | 2594 | nop); |
80f466c4 | 2595 | reject += 2; |
cb1cca12 | 2596 | } |
55a2c322 VM |
2597 | } |
2598 | } | |
2599 | else if (did_match) | |
2600 | this_alternative_match_win = true; | |
2601 | else | |
2602 | { | |
2603 | int const_to_mem = 0; | |
2604 | bool no_regs_p; | |
2605 | ||
d1457701 | 2606 | reject += op_reject; |
8d49e7ef VM |
2607 | /* Never do output reload of stack pointer. It makes |
2608 | impossible to do elimination when SP is changed in | |
2609 | RTL. */ | |
2610 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2611 | && curr_static_id->operand[nop].type != OP_IN) | |
2612 | goto fail; | |
2613 | ||
e86c0101 SB |
2614 | /* If this alternative asks for a specific reg class, see if there |
2615 | is at least one allocatable register in that class. */ | |
55a2c322 VM |
2616 | no_regs_p |
2617 | = (this_alternative == NO_REGS | |
2618 | || (hard_reg_set_subset_p | |
2619 | (reg_class_contents[this_alternative], | |
2620 | lra_no_alloc_regs))); | |
e86c0101 SB |
2621 | |
2622 | /* For asms, verify that the class for this alternative is possible | |
2623 | for the mode that is specified. */ | |
ecee672b | 2624 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
e86c0101 SB |
2625 | { |
2626 | int i; | |
2627 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
f939c3e6 | 2628 | if (targetm.hard_regno_mode_ok (i, mode) |
8f21260c VM |
2629 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2630 | mode, i)) | |
e86c0101 SB |
2631 | break; |
2632 | if (i == FIRST_PSEUDO_REGISTER) | |
2633 | winreg = false; | |
2634 | } | |
2635 | ||
55a2c322 VM |
2636 | /* If this operand accepts a register, and if the |
2637 | register class has at least one allocatable register, | |
2638 | then this operand can be reloaded. */ | |
2639 | if (winreg && !no_regs_p) | |
2640 | badop = false; | |
f4eafc30 | 2641 | |
55a2c322 | 2642 | if (badop) |
8f21260c VM |
2643 | { |
2644 | if (lra_dump_file != NULL) | |
2645 | fprintf (lra_dump_file, | |
2646 | " alt=%d: Bad operand -- refuse\n", | |
2647 | nalt); | |
2648 | goto fail; | |
2649 | } | |
55a2c322 | 2650 | |
d13835b6 VM |
2651 | if (this_alternative != NO_REGS) |
2652 | { | |
d15e5131 RS |
2653 | HARD_REG_SET available_regs |
2654 | = (reg_class_contents[this_alternative] | |
2655 | & ~((ira_prohibited_class_mode_regs | |
2656 | [this_alternative][mode]) | |
2657 | | lra_no_alloc_regs)); | |
d13835b6 VM |
2658 | if (hard_reg_set_empty_p (available_regs)) |
2659 | { | |
2660 | /* There are no hard regs holding a value of given | |
2661 | mode. */ | |
2662 | if (offmemok) | |
2663 | { | |
2664 | this_alternative = NO_REGS; | |
2665 | if (lra_dump_file != NULL) | |
2666 | fprintf (lra_dump_file, | |
2667 | " %d Using memory because of" | |
2668 | " a bad mode: reject+=2\n", | |
2669 | nop); | |
2670 | reject += 2; | |
2671 | } | |
2672 | else | |
2673 | { | |
2674 | if (lra_dump_file != NULL) | |
2675 | fprintf (lra_dump_file, | |
2676 | " alt=%d: Wrong mode -- refuse\n", | |
2677 | nalt); | |
2678 | goto fail; | |
2679 | } | |
2680 | } | |
2681 | } | |
2682 | ||
2ae577fd VM |
2683 | /* If not assigned pseudo has a class which a subset of |
2684 | required reg class, it is a less costly alternative | |
2685 | as the pseudo still can get a hard reg of necessary | |
2686 | class. */ | |
2687 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2688 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2689 | && ira_class_subset_p[this_alternative][cl]) | |
2690 | { | |
2691 | if (lra_dump_file != NULL) | |
2692 | fprintf | |
2693 | (lra_dump_file, | |
2694 | " %d Super set class reg: reject-=3\n", nop); | |
2695 | reject -= 3; | |
2696 | } | |
2697 | ||
55a2c322 VM |
2698 | this_alternative_offmemok = offmemok; |
2699 | if (this_costly_alternative != NO_REGS) | |
cb1cca12 VM |
2700 | { |
2701 | if (lra_dump_file != NULL) | |
2702 | fprintf (lra_dump_file, | |
2703 | " %d Costly loser: reject++\n", nop); | |
2704 | reject++; | |
2705 | } | |
55a2c322 VM |
2706 | /* If the operand is dying, has a matching constraint, |
2707 | and satisfies constraints of the matched operand | |
f4581282 | 2708 | which failed to satisfy the own constraints, most probably |
a9711f36 VM |
2709 | the reload for this operand will be gone. */ |
2710 | if (this_alternative_matches >= 0 | |
2711 | && !curr_alt_win[this_alternative_matches] | |
2712 | && REG_P (op) | |
2713 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2714 | && (hard_regno[nop] >= 0 | |
2715 | ? in_hard_reg_set_p (this_alternative_set, | |
2716 | mode, hard_regno[nop]) | |
2717 | : in_class_p (op, this_alternative, NULL))) | |
2718 | { | |
2719 | if (lra_dump_file != NULL) | |
2720 | fprintf | |
2721 | (lra_dump_file, | |
2722 | " %d Dying matched operand reload: reject++\n", | |
2723 | nop); | |
2724 | reject++; | |
2725 | } | |
2726 | else | |
027ece11 | 2727 | { |
5306401f VM |
2728 | /* Strict_low_part requires to reload the register |
2729 | not the sub-register. In this case we should | |
2730 | check that a final reload hard reg can hold the | |
2731 | value mode. */ | |
027ece11 VM |
2732 | if (curr_static_id->operand[nop].strict_low |
2733 | && REG_P (op) | |
2734 | && hard_regno[nop] < 0 | |
2735 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2736 | && ira_class_hard_regs_num[this_alternative] > 0 | |
f939c3e6 RS |
2737 | && (!targetm.hard_regno_mode_ok |
2738 | (ira_class_hard_regs[this_alternative][0], | |
2739 | GET_MODE (*curr_id->operand_loc[nop])))) | |
8f21260c VM |
2740 | { |
2741 | if (lra_dump_file != NULL) | |
2742 | fprintf | |
2743 | (lra_dump_file, | |
2744 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2745 | nalt); | |
2746 | goto fail; | |
2747 | } | |
027ece11 VM |
2748 | losers++; |
2749 | } | |
55a2c322 VM |
2750 | if (operand_reg[nop] != NULL_RTX |
2751 | /* Output operands and matched input operands are | |
2752 | not inherited. The following conditions do not | |
2753 | exactly describe the previous statement but they | |
2754 | are pretty close. */ | |
2755 | && curr_static_id->operand[nop].type != OP_OUT | |
2756 | && (this_alternative_matches < 0 | |
2757 | || curr_static_id->operand[nop].type != OP_IN)) | |
2758 | { | |
2759 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2760 | (operand_reg[nop])] | |
2761 | .last_reload); | |
2762 | ||
6334f3e9 VM |
2763 | /* The value of reload_sum has sense only if we |
2764 | process insns in their order. It happens only on | |
2765 | the first constraints sub-pass when we do most of | |
2766 | reload work. */ | |
2767 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
55a2c322 VM |
2768 | reload_sum += last_reload - bb_reload_num; |
2769 | } | |
2770 | /* If this is a constant that is reloaded into the | |
2771 | desired class by copying it to memory first, count | |
2772 | that as another reload. This is consistent with | |
2773 | other code and is required to avoid choosing another | |
2774 | alternative when the constant is moved into memory. | |
2775 | Note that the test here is precisely the same as in | |
2776 | the code below that calls force_const_mem. */ | |
2777 | if (CONST_POOL_OK_P (mode, op) | |
2778 | && ((targetm.preferred_reload_class | |
2779 | (op, this_alternative) == NO_REGS) | |
2780 | || no_input_reloads_p)) | |
2781 | { | |
2782 | const_to_mem = 1; | |
2783 | if (! no_regs_p) | |
2784 | losers++; | |
2785 | } | |
f4eafc30 | 2786 | |
55a2c322 VM |
2787 | /* Alternative loses if it requires a type of reload not |
2788 | permitted for this insn. We can always reload | |
2789 | objects with a REG_UNUSED note. */ | |
2790 | if ((curr_static_id->operand[nop].type != OP_IN | |
2791 | && no_output_reloads_p | |
2792 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2793 | || (curr_static_id->operand[nop].type != OP_OUT | |
8f21260c VM |
2794 | && no_input_reloads_p && ! const_to_mem) |
2795 | || (this_alternative_matches >= 0 | |
9102dadd VM |
2796 | && (no_input_reloads_p |
2797 | || (no_output_reloads_p | |
2798 | && (curr_static_id->operand | |
2799 | [this_alternative_matches].type != OP_IN) | |
2800 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2801 | no_subreg_reg_operand | |
2802 | [this_alternative_matches]))))) | |
8f21260c VM |
2803 | { |
2804 | if (lra_dump_file != NULL) | |
2805 | fprintf | |
2806 | (lra_dump_file, | |
5f564fd0 | 2807 | " alt=%d: No input/output reload -- refuse\n", |
8f21260c VM |
2808 | nalt); |
2809 | goto fail; | |
2810 | } | |
f4eafc30 | 2811 | |
67914693 | 2812 | /* Alternative loses if it required class pseudo cannot |
f66af4aa | 2813 | hold value of required mode. Such insns can be |
7b6e0c54 | 2814 | described by insn definitions with mode iterators. */ |
f66af4aa VM |
2815 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2816 | && ! hard_reg_set_empty_p (this_alternative_set) | |
7b6e0c54 VM |
2817 | /* It is common practice for constraints to use a |
2818 | class which does not have actually enough regs to | |
2819 | hold the value (e.g. x86 AREG for mode requiring | |
2820 | more one general reg). Therefore we have 2 | |
155ed511 SL |
2821 | conditions to check that the reload pseudo cannot |
2822 | hold the mode value. */ | |
f939c3e6 RS |
2823 | && (!targetm.hard_regno_mode_ok |
2824 | (ira_class_hard_regs[this_alternative][0], | |
2825 | GET_MODE (*curr_id->operand_loc[nop]))) | |
7b6e0c54 VM |
2826 | /* The above condition is not enough as the first |
2827 | reg in ira_class_hard_regs can be not aligned for | |
2828 | multi-words mode values. */ | |
3c954213 VM |
2829 | && (prohibited_class_reg_set_mode_p |
2830 | (this_alternative, this_alternative_set, | |
2831 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2832 | { | |
2833 | if (lra_dump_file != NULL) | |
2834 | fprintf (lra_dump_file, | |
2835 | " alt=%d: reload pseudo for op %d " | |
0d7bac69 | 2836 | "cannot hold the mode value -- refuse\n", |
3c954213 VM |
2837 | nalt, nop); |
2838 | goto fail; | |
f66af4aa VM |
2839 | } |
2840 | ||
821b7577 VM |
2841 | /* Check strong discouragement of reload of non-constant |
2842 | into class THIS_ALTERNATIVE. */ | |
2843 | if (! CONSTANT_P (op) && ! no_regs_p | |
2844 | && (targetm.preferred_reload_class | |
2845 | (op, this_alternative) == NO_REGS | |
2846 | || (curr_static_id->operand[nop].type == OP_OUT | |
2847 | && (targetm.preferred_output_reload_class | |
2848 | (op, this_alternative) == NO_REGS)))) | |
cb1cca12 | 2849 | { |
a8a728aa VM |
2850 | if (offmemok && REG_P (op)) |
2851 | { | |
2852 | if (lra_dump_file != NULL) | |
2853 | fprintf | |
2854 | (lra_dump_file, | |
2855 | " %d Spill pseudo into memory: reject+=3\n", | |
2856 | nop); | |
2857 | reject += 3; | |
2858 | } | |
2859 | else | |
2860 | { | |
2861 | if (lra_dump_file != NULL) | |
2862 | fprintf | |
2863 | (lra_dump_file, | |
2864 | " %d Non-prefered reload: reject+=%d\n", | |
2865 | nop, LRA_MAX_REJECT); | |
2866 | reject += LRA_MAX_REJECT; | |
2867 | } | |
cb1cca12 | 2868 | } |
f4eafc30 | 2869 | |
ed52a84e VM |
2870 | if (! (MEM_P (op) && offmemok) |
2871 | && ! (const_to_mem && constmemok)) | |
55a2c322 VM |
2872 | { |
2873 | /* We prefer to reload pseudos over reloading other | |
2874 | things, since such reloads may be able to be | |
2875 | eliminated later. So bump REJECT in other cases. | |
2876 | Don't do this in the case where we are forcing a | |
2877 | constant into memory and it will then win since | |
2878 | we don't want to have a different alternative | |
2879 | match then. */ | |
2880 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
cb1cca12 VM |
2881 | { |
2882 | if (lra_dump_file != NULL) | |
2883 | fprintf | |
2884 | (lra_dump_file, | |
2885 | " %d Non-pseudo reload: reject+=2\n", | |
2886 | nop); | |
2887 | reject += 2; | |
2888 | } | |
f4eafc30 | 2889 | |
55a2c322 VM |
2890 | if (! no_regs_p) |
2891 | reload_nregs | |
2892 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
36ff9dfb VM |
2893 | |
2894 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
cb1cca12 VM |
2895 | { |
2896 | if (lra_dump_file != NULL) | |
2897 | fprintf | |
2898 | (lra_dump_file, | |
2899 | " %d Small class reload: reject+=%d\n", | |
2900 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2901 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2902 | } | |
55a2c322 VM |
2903 | } |
2904 | ||
1bdc4b11 VM |
2905 | /* We are trying to spill pseudo into memory. It is |
2906 | usually more costly than moving to a hard register | |
2907 | although it might takes the same number of | |
5f225ef4 VM |
2908 | reloads. |
2909 | ||
2910 | Non-pseudo spill may happen also. Suppose a target allows both | |
2911 | register and memory in the operand constraint alternatives, | |
2912 | then it's typical that an eliminable register has a substition | |
2913 | of "base + offset" which can either be reloaded by a simple | |
2914 | "new_reg <= base + offset" which will match the register | |
2915 | constraint, or a similar reg addition followed by further spill | |
2916 | to and reload from memory which will match the memory | |
2917 | constraint, but this memory spill will be much more costly | |
2918 | usually. | |
2919 | ||
2920 | Code below increases the reject for both pseudo and non-pseudo | |
2921 | spill. */ | |
10406801 JW |
2922 | if (no_regs_p |
2923 | && !(MEM_P (op) && offmemok) | |
2924 | && !(REG_P (op) && hard_regno[nop] < 0)) | |
cb1cca12 VM |
2925 | { |
2926 | if (lra_dump_file != NULL) | |
2927 | fprintf | |
2928 | (lra_dump_file, | |
5f225ef4 VM |
2929 | " %d Spill %spseudo into memory: reject+=3\n", |
2930 | nop, REG_P (op) ? "" : "Non-"); | |
cb1cca12 | 2931 | reject += 3; |
7891065a VM |
2932 | if (VECTOR_MODE_P (mode)) |
2933 | { | |
2934 | /* Spilling vectors into memory is usually more | |
2935 | costly as they contain big values. */ | |
2936 | if (lra_dump_file != NULL) | |
2937 | fprintf | |
2938 | (lra_dump_file, | |
2939 | " %d Spill vector pseudo: reject+=2\n", | |
2940 | nop); | |
2941 | reject += 2; | |
2942 | } | |
cb1cca12 | 2943 | } |
1bdc4b11 | 2944 | |
4796d8f6 VM |
2945 | /* When we use an operand requiring memory in given |
2946 | alternative, the insn should write *and* read the | |
2947 | value to/from memory it is costly in comparison with | |
2948 | an insn alternative which does not use memory | |
2949 | (e.g. register or immediate operand). We exclude | |
2950 | memory operand for such case as we can satisfy the | |
2951 | memory constraints by reloading address. */ | |
2952 | if (no_regs_p && offmemok && !MEM_P (op)) | |
9b195552 VM |
2953 | { |
2954 | if (lra_dump_file != NULL) | |
2955 | fprintf | |
2956 | (lra_dump_file, | |
2957 | " Using memory insn operand %d: reject+=3\n", | |
2958 | nop); | |
2959 | reject += 3; | |
2960 | } | |
2961 | ||
7100b561 UB |
2962 | /* If reload requires moving value through secondary |
2963 | memory, it will need one more insn at least. */ | |
2964 | if (this_alternative != NO_REGS | |
2965 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2966 | && ((curr_static_id->operand[nop].type != OP_OUT | |
f15643d4 RS |
2967 | && targetm.secondary_memory_needed (GET_MODE (op), cl, |
2968 | this_alternative)) | |
7100b561 | 2969 | || (curr_static_id->operand[nop].type != OP_IN |
f15643d4 RS |
2970 | && (targetm.secondary_memory_needed |
2971 | (GET_MODE (op), this_alternative, cl))))) | |
7100b561 | 2972 | losers++; |
f15643d4 | 2973 | |
feca7b89 VM |
2974 | if (MEM_P (op) && offmemok) |
2975 | addr_losers++; | |
82396b8c | 2976 | else |
8b8e41e5 | 2977 | { |
82396b8c VM |
2978 | /* Input reloads can be inherited more often than |
2979 | output reloads can be removed, so penalize output | |
2980 | reloads. */ | |
2981 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
2982 | { | |
2983 | if (lra_dump_file != NULL) | |
2984 | fprintf | |
2985 | (lra_dump_file, | |
2986 | " %d Non input pseudo reload: reject++\n", | |
2987 | nop); | |
2988 | reject++; | |
2989 | } | |
2990 | ||
2991 | if (curr_static_id->operand[nop].type == OP_INOUT) | |
2992 | { | |
2993 | if (lra_dump_file != NULL) | |
2994 | fprintf | |
2995 | (lra_dump_file, | |
2996 | " %d Input/Output reload: reject+=%d\n", | |
2997 | nop, LRA_LOSER_COST_FACTOR); | |
2998 | reject += LRA_LOSER_COST_FACTOR; | |
2999 | } | |
8b8e41e5 | 3000 | } |
55a2c322 | 3001 | } |
f4eafc30 | 3002 | |
80f466c4 | 3003 | if (early_clobber_p && ! scratch_p) |
cb1cca12 VM |
3004 | { |
3005 | if (lra_dump_file != NULL) | |
3006 | fprintf (lra_dump_file, | |
3007 | " %d Early clobber: reject++\n", nop); | |
3008 | reject++; | |
3009 | } | |
55a2c322 VM |
3010 | /* ??? We check early clobbers after processing all operands |
3011 | (see loop below) and there we update the costs more. | |
3012 | Should we update the cost (may be approximately) here | |
3013 | because of early clobber register reloads or it is a rare | |
3014 | or non-important thing to be worth to do it. */ | |
feca7b89 VM |
3015 | overall = (losers * LRA_LOSER_COST_FACTOR + reject |
3016 | - (addr_losers == losers ? static_reject : 0)); | |
55a2c322 | 3017 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
deca73f5 VM |
3018 | { |
3019 | if (lra_dump_file != NULL) | |
3020 | fprintf (lra_dump_file, | |
cb1cca12 | 3021 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
deca73f5 VM |
3022 | nalt, overall, losers); |
3023 | goto fail; | |
3024 | } | |
55a2c322 | 3025 | |
a25f3e8e RS |
3026 | if (update_and_check_small_class_inputs (nop, nalt, |
3027 | this_alternative)) | |
9b195552 VM |
3028 | { |
3029 | if (lra_dump_file != NULL) | |
3030 | fprintf (lra_dump_file, | |
3031 | " alt=%d, not enough small class regs -- refuse\n", | |
3032 | nalt); | |
3033 | goto fail; | |
3034 | } | |
55a2c322 | 3035 | curr_alt[nop] = this_alternative; |
6576d245 | 3036 | curr_alt_set[nop] = this_alternative_set; |
85419ac5 VM |
3037 | curr_alt_exclude_start_hard_regs[nop] |
3038 | = this_alternative_exclude_start_hard_regs; | |
55a2c322 VM |
3039 | curr_alt_win[nop] = this_alternative_win; |
3040 | curr_alt_match_win[nop] = this_alternative_match_win; | |
3041 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
3042 | curr_alt_matches[nop] = this_alternative_matches; | |
f4eafc30 | 3043 | |
55a2c322 VM |
3044 | if (this_alternative_matches >= 0 |
3045 | && !did_match && !this_alternative_win) | |
3046 | curr_alt_win[this_alternative_matches] = false; | |
f4eafc30 | 3047 | |
55a2c322 VM |
3048 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
3049 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
3050 | } | |
feca7b89 | 3051 | |
2c62cbaa VM |
3052 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
3053 | /* Prevent processing non-move insns. */ | |
3054 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
3055 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
3056 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
3057 | && REG_P (no_subreg_reg_operand[0]) | |
3058 | && REG_P (no_subreg_reg_operand[1]) | |
3059 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
3060 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
3061 | || (! curr_alt_win[0] && curr_alt_win[1] | |
3062 | && REG_P (no_subreg_reg_operand[1]) | |
feca7b89 VM |
3063 | /* Check that we reload memory not the memory |
3064 | address. */ | |
9125b9fc VM |
3065 | && ! (curr_alt_offmemok[0] |
3066 | && MEM_P (no_subreg_reg_operand[0])) | |
2c62cbaa VM |
3067 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) |
3068 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
3069 | && REG_P (no_subreg_reg_operand[0]) | |
feca7b89 VM |
3070 | /* Check that we reload memory not the memory |
3071 | address. */ | |
9125b9fc VM |
3072 | && ! (curr_alt_offmemok[1] |
3073 | && MEM_P (no_subreg_reg_operand[1])) | |
2c62cbaa VM |
3074 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) |
3075 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
3076 | no_subreg_reg_operand[1]) | |
3077 | || (targetm.preferred_reload_class | |
3078 | (no_subreg_reg_operand[1], | |
3079 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
3080 | /* If it is a result of recent elimination in move | |
3081 | insn we can transform it into an add still by | |
3082 | using this alternative. */ | |
b4c96972 RS |
3083 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS |
3084 | /* Likewise if the source has been replaced with an | |
3085 | equivalent value. This only happens once -- the reload | |
3086 | will use the equivalent value instead of the register it | |
3087 | replaces -- so there should be no danger of cycling. */ | |
3088 | && !equiv_substition_p[1]))) | |
cb1cca12 VM |
3089 | { |
3090 | /* We have a move insn and a new reload insn will be similar | |
9125b9fc VM |
3091 | to the current insn. We should avoid such situation as |
3092 | it results in LRA cycling. */ | |
3093 | if (lra_dump_file != NULL) | |
3094 | fprintf (lra_dump_file, | |
3095 | " Cycle danger: overall += LRA_MAX_REJECT\n"); | |
cb1cca12 VM |
3096 | overall += LRA_MAX_REJECT; |
3097 | } | |
55a2c322 VM |
3098 | ok_p = true; |
3099 | curr_alt_dont_inherit_ops_num = 0; | |
3100 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
3101 | { | |
2194f7a2 | 3102 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
55a2c322 VM |
3103 | HARD_REG_SET temp_set; |
3104 | ||
3105 | i = early_clobbered_nops[nop]; | |
3106 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
3107 | || hard_regno[i] < 0) | |
3108 | continue; | |
1c86bd80 | 3109 | lra_assert (operand_reg[i] != NULL_RTX); |
55a2c322 VM |
3110 | clobbered_hard_regno = hard_regno[i]; |
3111 | CLEAR_HARD_REG_SET (temp_set); | |
a6457974 VM |
3112 | add_to_hard_reg_set (&temp_set, GET_MODE (*curr_id->operand_loc[i]), |
3113 | clobbered_hard_regno); | |
2194f7a2 | 3114 | first_conflict_j = last_conflict_j = -1; |
55a2c322 VM |
3115 | for (j = 0; j < n_operands; j++) |
3116 | if (j == i | |
3117 | /* We don't want process insides of match_operator and | |
3118 | match_parallel because otherwise we would process | |
3119 | their operands once again generating a wrong | |
3120 | code. */ | |
3121 | || curr_static_id->operand[j].is_operator) | |
3122 | continue; | |
3123 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
3124 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
3125 | continue; | |
1c86bd80 VM |
3126 | /* If we don't reload j-th operand, check conflicts. */ |
3127 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
3128 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
2194f7a2 VM |
3129 | { |
3130 | if (first_conflict_j < 0) | |
3131 | first_conflict_j = j; | |
3132 | last_conflict_j = j; | |
2f0b80c7 PB |
3133 | /* Both the earlyclobber operand and conflicting operand |
3134 | cannot both be user defined hard registers. */ | |
3135 | if (HARD_REGISTER_P (operand_reg[i]) | |
3136 | && REG_USERVAR_P (operand_reg[i]) | |
3137 | && operand_reg[j] != NULL_RTX | |
3138 | && HARD_REGISTER_P (operand_reg[j]) | |
3139 | && REG_USERVAR_P (operand_reg[j])) | |
eb69a49c JJ |
3140 | { |
3141 | /* For asm, let curr_insn_transform diagnose it. */ | |
3142 | if (INSN_CODE (curr_insn) < 0) | |
3143 | return false; | |
3144 | fatal_insn ("unable to generate reloads for " | |
3145 | "impossible constraints:", curr_insn); | |
3146 | } | |
2194f7a2 VM |
3147 | } |
3148 | if (last_conflict_j < 0) | |
55a2c322 | 3149 | continue; |
2f0b80c7 PB |
3150 | |
3151 | /* If an earlyclobber operand conflicts with another non-matching | |
3152 | operand (ie, they have been assigned the same hard register), | |
3153 | then it is better to reload the other operand, as there may | |
3154 | exist yet another operand with a matching constraint associated | |
3155 | with the earlyclobber operand. However, if one of the operands | |
3156 | is an explicit use of a hard register, then we must reload the | |
3157 | other non-hard register operand. */ | |
3158 | if (HARD_REGISTER_P (operand_reg[i]) | |
3159 | || (first_conflict_j == last_conflict_j | |
3160 | && operand_reg[last_conflict_j] != NULL_RTX | |
3161 | && !curr_alt_match_win[last_conflict_j] | |
3162 | && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) | |
1c86bd80 | 3163 | { |
2194f7a2 VM |
3164 | curr_alt_win[last_conflict_j] = false; |
3165 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
3166 | = last_conflict_j; | |
1c86bd80 | 3167 | losers++; |
cb1cca12 VM |
3168 | if (lra_dump_file != NULL) |
3169 | fprintf | |
3170 | (lra_dump_file, | |
3171 | " %d Conflict early clobber reload: reject--\n", | |
3172 | i); | |
1c86bd80 | 3173 | } |
55a2c322 VM |
3174 | else |
3175 | { | |
1c86bd80 VM |
3176 | /* We need to reload early clobbered register and the |
3177 | matched registers. */ | |
3178 | for (j = 0; j < n_operands; j++) | |
3179 | if (curr_alt_matches[j] == i) | |
3180 | { | |
3181 | curr_alt_match_win[j] = false; | |
3182 | losers++; | |
3183 | overall += LRA_LOSER_COST_FACTOR; | |
3184 | } | |
3185 | if (! curr_alt_match_win[i]) | |
3186 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
3187 | else | |
3188 | { | |
3189 | /* Remember pseudos used for match reloads are never | |
3190 | inherited. */ | |
3191 | lra_assert (curr_alt_matches[i] >= 0); | |
3192 | curr_alt_win[curr_alt_matches[i]] = false; | |
3193 | } | |
3194 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
3195 | losers++; | |
cb1cca12 VM |
3196 | if (lra_dump_file != NULL) |
3197 | fprintf | |
3198 | (lra_dump_file, | |
aa326bfb | 3199 | " %d Matched conflict early clobber reloads: " |
cb1cca12 VM |
3200 | "reject--\n", |
3201 | i); | |
dbe7895c AS |
3202 | } |
3203 | /* Early clobber was already reflected in REJECT. */ | |
3204 | if (!matching_early_clobber[i]) | |
3205 | { | |
3206 | lra_assert (reject > 0); | |
deca73f5 | 3207 | reject--; |
dbe7895c | 3208 | matching_early_clobber[i] = 1; |
55a2c322 | 3209 | } |
dbe7895c | 3210 | overall += LRA_LOSER_COST_FACTOR - 1; |
55a2c322 | 3211 | } |
deca73f5 | 3212 | if (lra_dump_file != NULL) |
36ff9dfb VM |
3213 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
3214 | nalt, overall, losers, reload_nregs); | |
deca73f5 | 3215 | |
55a2c322 VM |
3216 | /* If this alternative can be made to work by reloading, and it |
3217 | needs less reloading than the others checked so far, record | |
3218 | it as the chosen goal for reloading. */ | |
3219 | if ((best_losers != 0 && losers == 0) | |
3220 | || (((best_losers == 0 && losers == 0) | |
3221 | || (best_losers != 0 && losers != 0)) | |
3222 | && (best_overall > overall | |
3223 | || (best_overall == overall | |
3224 | /* If the cost of the reloads is the same, | |
3225 | prefer alternative which requires minimal | |
36ff9dfb VM |
3226 | number of reload regs. */ |
3227 | && (reload_nregs < best_reload_nregs | |
3228 | || (reload_nregs == best_reload_nregs | |
f15feaf9 VM |
3229 | && (best_reload_sum < reload_sum |
3230 | || (best_reload_sum == reload_sum | |
3231 | && nalt < goal_alt_number)))))))) | |
55a2c322 VM |
3232 | { |
3233 | for (nop = 0; nop < n_operands; nop++) | |
3234 | { | |
3235 | goal_alt_win[nop] = curr_alt_win[nop]; | |
3236 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
3237 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
3238 | goal_alt[nop] = curr_alt[nop]; | |
85419ac5 VM |
3239 | goal_alt_exclude_start_hard_regs[nop] |
3240 | = curr_alt_exclude_start_hard_regs[nop]; | |
55a2c322 VM |
3241 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; |
3242 | } | |
3243 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
3244 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
3245 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
3246 | goal_alt_swapped = curr_swapped; | |
3247 | best_overall = overall; | |
3248 | best_losers = losers; | |
55a2c322 VM |
3249 | best_reload_nregs = reload_nregs; |
3250 | best_reload_sum = reload_sum; | |
3251 | goal_alt_number = nalt; | |
3252 | } | |
3253 | if (losers == 0) | |
3254 | /* Everything is satisfied. Do not process alternatives | |
f4eafc30 | 3255 | anymore. */ |
55a2c322 VM |
3256 | break; |
3257 | fail: | |
3258 | ; | |
3259 | } | |
3260 | return ok_p; | |
3261 | } | |
3262 | ||
c31d2d11 RS |
3263 | /* Make reload base reg from address AD. */ |
3264 | static rtx | |
3265 | base_to_reg (struct address_info *ad) | |
3266 | { | |
3267 | enum reg_class cl; | |
3268 | int code = -1; | |
3269 | rtx new_inner = NULL_RTX; | |
3270 | rtx new_reg = NULL_RTX; | |
fee3e72c DM |
3271 | rtx_insn *insn; |
3272 | rtx_insn *last_insn = get_last_insn(); | |
c31d2d11 | 3273 | |
0a001dcb | 3274 | lra_assert (ad->disp == ad->disp_term); |
c31d2d11 RS |
3275 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3276 | get_index_code (ad)); | |
85419ac5 VM |
3277 | new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, cl, NULL, |
3278 | "base"); | |
c31d2d11 RS |
3279 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, |
3280 | ad->disp_term == NULL | |
0a001dcb | 3281 | ? const0_rtx |
c31d2d11 RS |
3282 | : *ad->disp_term); |
3283 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
3284 | return NULL_RTX; | |
0a001dcb | 3285 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); |
c31d2d11 RS |
3286 | code = recog_memoized (insn); |
3287 | if (code < 0) | |
3288 | { | |
3289 | delete_insns_since (last_insn); | |
3290 | return NULL_RTX; | |
3291 | } | |
3292 | ||
3293 | return new_inner; | |
3294 | } | |
3295 | ||
9005477f | 3296 | /* Make reload base reg + DISP from address AD. Return the new pseudo. */ |
55a2c322 | 3297 | static rtx |
9005477f | 3298 | base_plus_disp_to_reg (struct address_info *ad, rtx disp) |
55a2c322 VM |
3299 | { |
3300 | enum reg_class cl; | |
3301 | rtx new_reg; | |
3302 | ||
9005477f | 3303 | lra_assert (ad->base == ad->base_term); |
277f65de RS |
3304 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3305 | get_index_code (ad)); | |
85419ac5 VM |
3306 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, cl, NULL, |
3307 | "base + disp"); | |
9005477f | 3308 | lra_emit_add (new_reg, *ad->base_term, disp); |
55a2c322 VM |
3309 | return new_reg; |
3310 | } | |
3311 | ||
6e071b1e VM |
3312 | /* Make reload of index part of address AD. Return the new |
3313 | pseudo. */ | |
3314 | static rtx | |
3315 | index_part_to_reg (struct address_info *ad) | |
3316 | { | |
3317 | rtx new_reg; | |
3318 | ||
3319 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
85419ac5 | 3320 | INDEX_REG_CLASS, NULL, "index term"); |
6e071b1e VM |
3321 | expand_mult (GET_MODE (*ad->index), *ad->index_term, |
3322 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
3323 | return new_reg; | |
3324 | } | |
3325 | ||
277f65de RS |
3326 | /* Return true if we can add a displacement to address AD, even if that |
3327 | makes the address invalid. The fix-up code requires any new address | |
3328 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
02ea4bf4 | 3329 | static bool |
277f65de | 3330 | can_add_disp_p (struct address_info *ad) |
02ea4bf4 | 3331 | { |
277f65de RS |
3332 | return (!ad->autoinc_p |
3333 | && ad->segment == NULL | |
3334 | && ad->base == ad->base_term | |
3335 | && ad->disp == ad->disp_term); | |
02ea4bf4 RS |
3336 | } |
3337 | ||
277f65de RS |
3338 | /* Make equiv substitution in address AD. Return true if a substitution |
3339 | was made. */ | |
55a2c322 | 3340 | static bool |
277f65de | 3341 | equiv_address_substitution (struct address_info *ad) |
55a2c322 | 3342 | { |
277f65de | 3343 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
73ca989c RS |
3344 | poly_int64 disp; |
3345 | HOST_WIDE_INT scale; | |
55a2c322 VM |
3346 | bool change_p; |
3347 | ||
277f65de RS |
3348 | base_term = strip_subreg (ad->base_term); |
3349 | if (base_term == NULL) | |
55a2c322 VM |
3350 | base_reg = new_base_reg = NULL_RTX; |
3351 | else | |
3352 | { | |
277f65de | 3353 | base_reg = *base_term; |
8d49e7ef | 3354 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
55a2c322 | 3355 | } |
277f65de RS |
3356 | index_term = strip_subreg (ad->index_term); |
3357 | if (index_term == NULL) | |
55a2c322 VM |
3358 | index_reg = new_index_reg = NULL_RTX; |
3359 | else | |
3360 | { | |
277f65de | 3361 | index_reg = *index_term; |
8d49e7ef | 3362 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
55a2c322 VM |
3363 | } |
3364 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
3365 | return false; | |
3366 | disp = 0; | |
3367 | change_p = false; | |
3368 | if (lra_dump_file != NULL) | |
3369 | { | |
3370 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
3371 | INSN_UID (curr_insn)); | |
cfbeaedf | 3372 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3373 | } |
3374 | if (base_reg != new_base_reg) | |
3375 | { | |
73ca989c | 3376 | poly_int64 offset; |
55a2c322 VM |
3377 | if (REG_P (new_base_reg)) |
3378 | { | |
277f65de | 3379 | *base_term = new_base_reg; |
55a2c322 VM |
3380 | change_p = true; |
3381 | } | |
3382 | else if (GET_CODE (new_base_reg) == PLUS | |
3383 | && REG_P (XEXP (new_base_reg, 0)) | |
73ca989c | 3384 | && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset) |
277f65de | 3385 | && can_add_disp_p (ad)) |
55a2c322 | 3386 | { |
73ca989c | 3387 | disp += offset; |
277f65de | 3388 | *base_term = XEXP (new_base_reg, 0); |
55a2c322 VM |
3389 | change_p = true; |
3390 | } | |
277f65de RS |
3391 | if (ad->base_term2 != NULL) |
3392 | *ad->base_term2 = *ad->base_term; | |
55a2c322 | 3393 | } |
55a2c322 VM |
3394 | if (index_reg != new_index_reg) |
3395 | { | |
73ca989c | 3396 | poly_int64 offset; |
55a2c322 VM |
3397 | if (REG_P (new_index_reg)) |
3398 | { | |
277f65de | 3399 | *index_term = new_index_reg; |
55a2c322 VM |
3400 | change_p = true; |
3401 | } | |
3402 | else if (GET_CODE (new_index_reg) == PLUS | |
3403 | && REG_P (XEXP (new_index_reg, 0)) | |
73ca989c | 3404 | && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset) |
277f65de | 3405 | && can_add_disp_p (ad) |
02ea4bf4 | 3406 | && (scale = get_index_scale (ad))) |
55a2c322 | 3407 | { |
73ca989c | 3408 | disp += offset * scale; |
277f65de | 3409 | *index_term = XEXP (new_index_reg, 0); |
55a2c322 VM |
3410 | change_p = true; |
3411 | } | |
3412 | } | |
73ca989c | 3413 | if (maybe_ne (disp, 0)) |
55a2c322 | 3414 | { |
277f65de RS |
3415 | if (ad->disp != NULL) |
3416 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
55a2c322 VM |
3417 | else |
3418 | { | |
277f65de RS |
3419 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
3420 | update_address (ad); | |
55a2c322 VM |
3421 | } |
3422 | change_p = true; | |
3423 | } | |
3424 | if (lra_dump_file != NULL) | |
3425 | { | |
3426 | if (! change_p) | |
3427 | fprintf (lra_dump_file, " -- no change\n"); | |
3428 | else | |
3429 | { | |
3430 | fprintf (lra_dump_file, " on equiv "); | |
cfbeaedf | 3431 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3432 | fprintf (lra_dump_file, "\n"); |
3433 | } | |
3434 | } | |
3435 | return change_p; | |
3436 | } | |
3437 | ||
04b4828c VM |
3438 | /* Skip all modifiers and whitespaces in constraint STR and return the |
3439 | result. */ | |
3440 | static const char * | |
8bf983c7 | 3441 | skip_constraint_modifiers (const char *str) |
04b4828c VM |
3442 | { |
3443 | for (;;str++) | |
3444 | switch (*str) | |
3445 | { | |
8bf983c7 | 3446 | case '+': case '&' : case '=': case '*': case ' ': case '\t': |
04b4828c VM |
3447 | case '$': case '^' : case '%': case '?': case '!': |
3448 | break; | |
3449 | default: return str; | |
3450 | } | |
3451 | } | |
3452 | ||
d9cf932c VM |
3453 | /* Major function to make reloads for an address in operand NOP or |
3454 | check its correctness (If CHECK_ONLY_P is true). The supported | |
3455 | cases are: | |
bd3d34d4 | 3456 | |
5a107a0f VM |
3457 | 1) an address that existed before LRA started, at which point it |
3458 | must have been valid. These addresses are subject to elimination | |
3459 | and may have become invalid due to the elimination offset being out | |
3460 | of range. | |
bd3d34d4 | 3461 | |
5a107a0f VM |
3462 | 2) an address created by forcing a constant to memory |
3463 | (force_const_to_mem). The initial form of these addresses might | |
3464 | not be valid, and it is this function's job to make them valid. | |
bd3d34d4 RS |
3465 | |
3466 | 3) a frame address formed from a register and a (possibly zero) | |
5a107a0f VM |
3467 | constant offset. As above, these addresses might not be valid and |
3468 | this function must make them so. | |
bd3d34d4 RS |
3469 | |
3470 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
55a2c322 | 3471 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
cc8849a1 VM |
3472 | address. Return true for any RTL change. |
3473 | ||
3474 | The function is a helper function which does not produce all | |
d9cf932c VM |
3475 | transformations (when CHECK_ONLY_P is false) which can be |
3476 | necessary. It does just basic steps. To do all necessary | |
3477 | transformations use function process_address. */ | |
55a2c322 | 3478 | static bool |
d9cf932c VM |
3479 | process_address_1 (int nop, bool check_only_p, |
3480 | rtx_insn **before, rtx_insn **after) | |
55a2c322 | 3481 | { |
277f65de RS |
3482 | struct address_info ad; |
3483 | rtx new_reg; | |
bc2fc1f3 | 3484 | HOST_WIDE_INT scale; |
55a2c322 | 3485 | rtx op = *curr_id->operand_loc[nop]; |
db8b3e14 | 3486 | rtx mem = extract_mem_from_operand (op); |
04b4828c VM |
3487 | const char *constraint; |
3488 | enum constraint_num cn; | |
d9cf932c | 3489 | bool change_p = false; |
55a2c322 | 3490 | |
db8b3e14 | 3491 | if (MEM_P (mem) |
3492 | && GET_MODE (mem) == BLKmode | |
3493 | && GET_CODE (XEXP (mem, 0)) == SCRATCH) | |
823bb054 SB |
3494 | return false; |
3495 | ||
04b4828c | 3496 | constraint |
8bf983c7 | 3497 | = skip_constraint_modifiers (curr_static_id->operand[nop].constraint); |
fb5d9e83 VM |
3498 | if (IN_RANGE (constraint[0], '0', '9')) |
3499 | { | |
3500 | char *end; | |
3501 | unsigned long dup = strtoul (constraint, &end, 10); | |
3502 | constraint | |
8bf983c7 | 3503 | = skip_constraint_modifiers (curr_static_id->operand[dup].constraint); |
fb5d9e83 | 3504 | } |
d81019db VM |
3505 | cn = lookup_constraint (*constraint == '\0' ? "X" : constraint); |
3506 | /* If we have several alternatives or/and several constraints in an | |
3507 | alternative and we can not say at this stage what constraint will be used, | |
3508 | use unknown constraint. The exception is an address constraint. If | |
3509 | operand has one address constraint, probably all others constraints are | |
3510 | address ones. */ | |
8bf983c7 VM |
3511 | if (constraint[0] != '\0' && get_constraint_type (cn) != CT_ADDRESS |
3512 | && *skip_constraint_modifiers (constraint | |
3513 | + CONSTRAINT_LEN (constraint[0], | |
3514 | constraint)) != '\0') | |
a4670f58 | 3515 | cn = CONSTRAINT__UNKNOWN; |
998fd141 AO |
3516 | if (insn_extra_address_constraint (cn) |
3517 | /* When we find an asm operand with an address constraint that | |
3518 | doesn't satisfy address_operand to begin with, we clear | |
3519 | is_address, so that we don't try to make a non-address fit. | |
3520 | If the asm statement got this far, it's because other | |
3521 | constraints are available, and we'll use them, disregarding | |
3522 | the unsatisfiable address ones. */ | |
3523 | && curr_static_id->operand[nop].is_address) | |
277f65de | 3524 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
164f0634 | 3525 | /* Do not attempt to decompose arbitrary addresses generated by combine |
db8b3e14 | 3526 | for asm operands with loose constraints, e.g 'X'. |
3527 | Need to extract memory from op for special memory constraint, | |
3528 | i.e. bcst_mem_operand in i386 backend. */ | |
3529 | else if (MEM_P (mem) | |
a81a0bfa | 3530 | && !(INSN_CODE (curr_insn) < 0 |
d38bbb85 VM |
3531 | && get_constraint_type (cn) == CT_FIXED_FORM |
3532 | && constraint_satisfied_p (op, cn))) | |
db8b3e14 | 3533 | decompose_mem_address (&ad, mem); |
55a2c322 VM |
3534 | else if (GET_CODE (op) == SUBREG |
3535 | && MEM_P (SUBREG_REG (op))) | |
277f65de | 3536 | decompose_mem_address (&ad, SUBREG_REG (op)); |
55a2c322 VM |
3537 | else |
3538 | return false; | |
70712859 KK |
3539 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
3540 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
3541 | when INDEX_REG_CLASS is a single register class. */ | |
3542 | if (ad.base_term != NULL | |
3543 | && ad.index_term != NULL | |
3544 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
3545 | && REG_P (*ad.base_term) | |
3546 | && REG_P (*ad.index_term) | |
3547 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
3548 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
3549 | { | |
3550 | std::swap (ad.base, ad.index); | |
3551 | std::swap (ad.base_term, ad.index_term); | |
3552 | } | |
d9cf932c VM |
3553 | if (! check_only_p) |
3554 | change_p = equiv_address_substitution (&ad); | |
277f65de | 3555 | if (ad.base_term != NULL |
55a2c322 | 3556 | && (process_addr_reg |
d9cf932c | 3557 | (ad.base_term, check_only_p, before, |
277f65de RS |
3558 | (ad.autoinc_p |
3559 | && !(REG_P (*ad.base_term) | |
3560 | && find_regno_note (curr_insn, REG_DEAD, | |
3561 | REGNO (*ad.base_term)) != NULL_RTX) | |
55a2c322 | 3562 | ? after : NULL), |
277f65de RS |
3563 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
3564 | get_index_code (&ad))))) | |
55a2c322 VM |
3565 | { |
3566 | change_p = true; | |
277f65de RS |
3567 | if (ad.base_term2 != NULL) |
3568 | *ad.base_term2 = *ad.base_term; | |
55a2c322 | 3569 | } |
277f65de | 3570 | if (ad.index_term != NULL |
d9cf932c VM |
3571 | && process_addr_reg (ad.index_term, check_only_p, |
3572 | before, NULL, INDEX_REG_CLASS)) | |
55a2c322 VM |
3573 | change_p = true; |
3574 | ||
777e635f RS |
3575 | /* Target hooks sometimes don't treat extra-constraint addresses as |
3576 | legitimate address_operands, so handle them specially. */ | |
8677664e | 3577 | if (insn_extra_address_constraint (cn) |
777e635f | 3578 | && satisfies_address_constraint_p (&ad, cn)) |
2c62cbaa | 3579 | return change_p; |
2c62cbaa | 3580 | |
d9cf932c VM |
3581 | if (check_only_p) |
3582 | return change_p; | |
3583 | ||
277f65de | 3584 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
bd3d34d4 RS |
3585 | |
3586 | 1) the original address was valid, but either elimination or | |
5a107a0f VM |
3587 | equiv_address_substitution was applied and that made |
3588 | the address invalid. | |
bd3d34d4 RS |
3589 | |
3590 | 2) the address is an invalid symbolic address created by | |
5a107a0f | 3591 | force_const_to_mem. |
bd3d34d4 RS |
3592 | |
3593 | 3) the address is a frame address with an invalid offset. | |
3594 | ||
c31d2d11 RS |
3595 | 4) the address is a frame address with an invalid base. |
3596 | ||
2c62cbaa VM |
3597 | All these cases involve a non-autoinc address, so there is no |
3598 | point revalidating other types. */ | |
1aeffdce | 3599 | if (ad.autoinc_p || valid_address_p (op, &ad, cn)) |
55a2c322 VM |
3600 | return change_p; |
3601 | ||
bd3d34d4 RS |
3602 | /* Any index existed before LRA started, so we can assume that the |
3603 | presence and shape of the index is valid. */ | |
55a2c322 | 3604 | push_to_sequence (*before); |
2c62cbaa | 3605 | lra_assert (ad.disp == ad.disp_term); |
277f65de | 3606 | if (ad.base == NULL) |
55a2c322 | 3607 | { |
277f65de | 3608 | if (ad.index == NULL) |
55a2c322 | 3609 | { |
95831c01 VM |
3610 | rtx_insn *insn; |
3611 | rtx_insn *last = get_last_insn (); | |
55a2c322 | 3612 | int code = -1; |
277f65de RS |
3613 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
3614 | SCRATCH, SCRATCH); | |
2c62cbaa | 3615 | rtx addr = *ad.inner; |
277f65de | 3616 | |
85419ac5 | 3617 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "addr"); |
d0b2266a TS |
3618 | if (HAVE_lo_sum) |
3619 | { | |
d0b2266a TS |
3620 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
3621 | insn = emit_insn (gen_rtx_SET | |
3622 | (new_reg, | |
3623 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
3624 | code = recog_memoized (insn); | |
3625 | if (code >= 0) | |
3626 | { | |
3627 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
1aeffdce | 3628 | if (!valid_address_p (op, &ad, cn)) |
d0b2266a | 3629 | { |
f1b3e385 IS |
3630 | /* Try to put lo_sum into register. */ |
3631 | insn = emit_insn (gen_rtx_SET | |
3632 | (new_reg, | |
3633 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3634 | code = recog_memoized (insn); | |
3635 | if (code >= 0) | |
3636 | { | |
3637 | *ad.inner = new_reg; | |
3638 | if (!valid_address_p (op, &ad, cn)) | |
3639 | { | |
3640 | *ad.inner = addr; | |
3641 | code = -1; | |
3642 | } | |
3643 | } | |
3644 | ||
d0b2266a TS |
3645 | } |
3646 | } | |
3647 | if (code < 0) | |
3648 | delete_insns_since (last); | |
3649 | } | |
3650 | ||
55a2c322 VM |
3651 | if (code < 0) |
3652 | { | |
2c62cbaa VM |
3653 | /* addr => new_base, case (2) above. */ |
3654 | lra_emit_move (new_reg, addr); | |
95831c01 VM |
3655 | |
3656 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3657 | insn != NULL_RTX; | |
3658 | insn = NEXT_INSN (insn)) | |
3659 | if (recog_memoized (insn) < 0) | |
3660 | break; | |
3661 | if (insn != NULL_RTX) | |
3662 | { | |
3663 | /* Do nothing if we cannot generate right insns. | |
9c582551 | 3664 | This is analogous to reload pass behavior. */ |
95831c01 VM |
3665 | delete_insns_since (last); |
3666 | end_sequence (); | |
3667 | return false; | |
3668 | } | |
2c62cbaa | 3669 | *ad.inner = new_reg; |
55a2c322 VM |
3670 | } |
3671 | } | |
3672 | else | |
3673 | { | |
bd3d34d4 RS |
3674 | /* index * scale + disp => new base + index * scale, |
3675 | case (1) above. */ | |
277f65de RS |
3676 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3677 | GET_CODE (*ad.index)); | |
55a2c322 VM |
3678 | |
3679 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
85419ac5 | 3680 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "disp"); |
277f65de RS |
3681 | lra_emit_move (new_reg, *ad.disp); |
3682 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3683 | new_reg, *ad.index); | |
55a2c322 VM |
3684 | } |
3685 | } | |
277f65de | 3686 | else if (ad.index == NULL) |
55a2c322 | 3687 | { |
5a107a0f VM |
3688 | int regno; |
3689 | enum reg_class cl; | |
cfa434f6 DM |
3690 | rtx set; |
3691 | rtx_insn *insns, *last_insn; | |
c31d2d11 RS |
3692 | /* Try to reload base into register only if the base is invalid |
3693 | for the address but with valid offset, case (4) above. */ | |
3694 | start_sequence (); | |
3695 | new_reg = base_to_reg (&ad); | |
3696 | ||
bd3d34d4 | 3697 | /* base + disp => new base, cases (1) and (3) above. */ |
55a2c322 VM |
3698 | /* Another option would be to reload the displacement into an |
3699 | index register. However, postreload has code to optimize | |
3700 | address reloads that have the same base and different | |
3701 | displacements, so reloading into an index register would | |
3702 | not necessarily be a win. */ | |
c31d2d11 | 3703 | if (new_reg == NULL_RTX) |
9005477f RS |
3704 | { |
3705 | /* See if the target can split the displacement into a | |
3706 | legitimate new displacement from a local anchor. */ | |
3707 | gcc_assert (ad.disp == ad.disp_term); | |
3708 | poly_int64 orig_offset; | |
3709 | rtx offset1, offset2; | |
3710 | if (poly_int_rtx_p (*ad.disp, &orig_offset) | |
3711 | && targetm.legitimize_address_displacement (&offset1, &offset2, | |
3712 | orig_offset, | |
3713 | ad.mode)) | |
3714 | { | |
3715 | new_reg = base_plus_disp_to_reg (&ad, offset1); | |
3716 | new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2); | |
3717 | } | |
3718 | else | |
3719 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
3720 | } | |
5a107a0f VM |
3721 | insns = get_insns (); |
3722 | last_insn = get_last_insn (); | |
3723 | /* If we generated at least two insns, try last insn source as | |
3724 | an address. If we succeed, we generate one less insn. */ | |
9005477f RS |
3725 | if (REG_P (new_reg) |
3726 | && last_insn != insns | |
3727 | && (set = single_set (last_insn)) != NULL_RTX | |
5a107a0f VM |
3728 | && GET_CODE (SET_SRC (set)) == PLUS |
3729 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3730 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3731 | { | |
3732 | *ad.inner = SET_SRC (set); | |
1aeffdce | 3733 | if (valid_address_p (op, &ad, cn)) |
5a107a0f VM |
3734 | { |
3735 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3736 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3737 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3738 | get_index_code (&ad)); | |
3739 | regno = REGNO (*ad.base_term); | |
3740 | if (regno >= FIRST_PSEUDO_REGISTER | |
3741 | && cl != lra_get_allocno_class (regno)) | |
a2d0d374 | 3742 | lra_change_class (regno, cl, " Change to", true); |
5a107a0f VM |
3743 | new_reg = SET_SRC (set); |
3744 | delete_insns_since (PREV_INSN (last_insn)); | |
3745 | } | |
3746 | } | |
3747 | end_sequence (); | |
3748 | emit_insn (insns); | |
277f65de | 3749 | *ad.inner = new_reg; |
55a2c322 | 3750 | } |
6e071b1e | 3751 | else if (ad.disp_term != NULL) |
55a2c322 | 3752 | { |
bd3d34d4 RS |
3753 | /* base + scale * index + disp => new base + scale * index, |
3754 | case (1) above. */ | |
9005477f RS |
3755 | gcc_assert (ad.disp == ad.disp_term); |
3756 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
277f65de RS |
3757 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), |
3758 | new_reg, *ad.index); | |
55a2c322 | 3759 | } |
bc2fc1f3 | 3760 | else if ((scale = get_index_scale (&ad)) == 1) |
5a770e01 VM |
3761 | { |
3762 | /* The last transformation to one reg will be made in | |
3763 | curr_insn_transform function. */ | |
3764 | end_sequence (); | |
3765 | return false; | |
3766 | } | |
bc2fc1f3 | 3767 | else if (scale != 0) |
6e071b1e VM |
3768 | { |
3769 | /* base + scale * index => base + new_reg, | |
3770 | case (1) above. | |
3771 | Index part of address may become invalid. For example, we | |
3772 | changed pseudo on the equivalent memory and a subreg of the | |
3773 | pseudo onto the memory of different mode for which the scale is | |
3774 | prohibitted. */ | |
3775 | new_reg = index_part_to_reg (&ad); | |
3776 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3777 | *ad.base_term, new_reg); | |
3778 | } | |
bc2fc1f3 VM |
3779 | else |
3780 | { | |
3781 | enum reg_class cl = base_reg_class (ad.mode, ad.as, | |
3782 | SCRATCH, SCRATCH); | |
3783 | rtx addr = *ad.inner; | |
3784 | ||
85419ac5 | 3785 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "addr"); |
bc2fc1f3 VM |
3786 | /* addr => new_base. */ |
3787 | lra_emit_move (new_reg, addr); | |
3788 | *ad.inner = new_reg; | |
3789 | } | |
55a2c322 VM |
3790 | *before = get_insns (); |
3791 | end_sequence (); | |
3792 | return true; | |
3793 | } | |
3794 | ||
d9cf932c VM |
3795 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3796 | Use process_address_1 as a helper function. Return true for any | |
3797 | RTL changes. | |
3798 | ||
3799 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3800 | false if the address correct. */ | |
cc8849a1 | 3801 | static bool |
d9cf932c VM |
3802 | process_address (int nop, bool check_only_p, |
3803 | rtx_insn **before, rtx_insn **after) | |
cc8849a1 VM |
3804 | { |
3805 | bool res = false; | |
3806 | ||
d9cf932c VM |
3807 | while (process_address_1 (nop, check_only_p, before, after)) |
3808 | { | |
3809 | if (check_only_p) | |
3810 | return true; | |
3811 | res = true; | |
3812 | } | |
cc8849a1 VM |
3813 | return res; |
3814 | } | |
3815 | ||
55a2c322 VM |
3816 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3817 | auto-increment or auto-decrement RTX whose operand is a register or | |
3818 | memory location; so reloading involves incrementing that location. | |
3819 | IN is either identical to VALUE, or some cheaper place to reload | |
3820 | value being incremented/decremented from. | |
3821 | ||
3822 | INC_AMOUNT is the number to increment or decrement by (always | |
3823 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3824 | ||
3825 | Return pseudo containing the result. */ | |
3826 | static rtx | |
31ae0e43 | 3827 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) |
55a2c322 VM |
3828 | { |
3829 | /* REG or MEM to be copied and incremented. */ | |
3830 | rtx incloc = XEXP (value, 0); | |
3831 | /* Nonzero if increment after copying. */ | |
3832 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3833 | || GET_CODE (value) == POST_MODIFY); | |
cfa434f6 | 3834 | rtx_insn *last; |
55a2c322 | 3835 | rtx inc; |
647d790d | 3836 | rtx_insn *add_insn; |
55a2c322 VM |
3837 | int code; |
3838 | rtx real_in = in == value ? incloc : in; | |
3839 | rtx result; | |
3840 | bool plus_p = true; | |
3841 | ||
3842 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3843 | { | |
3844 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3845 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3846 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3847 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3848 | inc = XEXP (XEXP (value, 1), 1); | |
3849 | } | |
3850 | else | |
3851 | { | |
3852 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3853 | inc_amount = -inc_amount; | |
3854 | ||
31ae0e43 | 3855 | inc = gen_int_mode (inc_amount, GET_MODE (value)); |
55a2c322 VM |
3856 | } |
3857 | ||
3858 | if (! post && REG_P (incloc)) | |
3859 | result = incloc; | |
3860 | else | |
85419ac5 | 3861 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, NULL, |
55a2c322 VM |
3862 | "INC/DEC result"); |
3863 | ||
3864 | if (real_in != result) | |
3865 | { | |
3866 | /* First copy the location to the result register. */ | |
3867 | lra_assert (REG_P (result)); | |
3868 | emit_insn (gen_move_insn (result, real_in)); | |
3869 | } | |
3870 | ||
3871 | /* We suppose that there are insns to add/sub with the constant | |
3872 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3873 | old reload worked with this assumption. If the assumption | |
3874 | becomes wrong, we should use approach in function | |
3875 | base_plus_disp_to_reg. */ | |
3876 | if (in == value) | |
3877 | { | |
3878 | /* See if we can directly increment INCLOC. */ | |
3879 | last = get_last_insn (); | |
3880 | add_insn = emit_insn (plus_p | |
3881 | ? gen_add2_insn (incloc, inc) | |
3882 | : gen_sub2_insn (incloc, inc)); | |
3883 | ||
3884 | code = recog_memoized (add_insn); | |
3885 | if (code >= 0) | |
3886 | { | |
3887 | if (! post && result != incloc) | |
3888 | emit_insn (gen_move_insn (result, incloc)); | |
3889 | return result; | |
3890 | } | |
3891 | delete_insns_since (last); | |
3892 | } | |
3893 | ||
3894 | /* If couldn't do the increment directly, must increment in RESULT. | |
3895 | The way we do this depends on whether this is pre- or | |
3896 | post-increment. For pre-increment, copy INCLOC to the reload | |
3897 | register, increment it there, then save back. */ | |
3898 | if (! post) | |
3899 | { | |
3900 | if (real_in != result) | |
3901 | emit_insn (gen_move_insn (result, real_in)); | |
3902 | if (plus_p) | |
3903 | emit_insn (gen_add2_insn (result, inc)); | |
3904 | else | |
3905 | emit_insn (gen_sub2_insn (result, inc)); | |
3906 | if (result != incloc) | |
3907 | emit_insn (gen_move_insn (incloc, result)); | |
3908 | } | |
3909 | else | |
3910 | { | |
3911 | /* Post-increment. | |
3912 | ||
3913 | Because this might be a jump insn or a compare, and because | |
3914 | RESULT may not be available after the insn in an input | |
3915 | reload, we must do the incrementing before the insn being | |
3916 | reloaded for. | |
3917 | ||
3918 | We have already copied IN to RESULT. Increment the copy in | |
3919 | RESULT, save that back, then decrement RESULT so it has | |
3920 | the original value. */ | |
3921 | if (plus_p) | |
3922 | emit_insn (gen_add2_insn (result, inc)); | |
3923 | else | |
3924 | emit_insn (gen_sub2_insn (result, inc)); | |
3925 | emit_insn (gen_move_insn (incloc, result)); | |
3926 | /* Restore non-modified value for the result. We prefer this | |
3927 | way because it does not require an additional hard | |
3928 | register. */ | |
3929 | if (plus_p) | |
3930 | { | |
73ca989c RS |
3931 | poly_int64 offset; |
3932 | if (poly_int_rtx_p (inc, &offset)) | |
69db2d57 | 3933 | emit_insn (gen_add2_insn (result, |
73ca989c | 3934 | gen_int_mode (-offset, |
69db2d57 | 3935 | GET_MODE (result)))); |
55a2c322 VM |
3936 | else |
3937 | emit_insn (gen_sub2_insn (result, inc)); | |
3938 | } | |
3939 | else | |
3940 | emit_insn (gen_add2_insn (result, inc)); | |
3941 | } | |
3942 | return result; | |
3943 | } | |
3944 | ||
2c62cbaa VM |
3945 | /* Return true if the current move insn does not need processing as we |
3946 | already know that it satisfies its constraints. */ | |
3947 | static bool | |
3948 | simple_move_p (void) | |
3949 | { | |
3950 | rtx dest, src; | |
3951 | enum reg_class dclass, sclass; | |
3952 | ||
3953 | lra_assert (curr_insn_set != NULL_RTX); | |
3954 | dest = SET_DEST (curr_insn_set); | |
3955 | src = SET_SRC (curr_insn_set); | |
2008be40 SB |
3956 | |
3957 | /* If the instruction has multiple sets we need to process it even if it | |
3958 | is single_set. This can happen if one or more of the SETs are dead. | |
3959 | See PR73650. */ | |
3960 | if (multiple_sets (curr_insn)) | |
3961 | return false; | |
3962 | ||
2c62cbaa VM |
3963 | return ((dclass = get_op_class (dest)) != NO_REGS |
3964 | && (sclass = get_op_class (src)) != NO_REGS | |
3965 | /* The backend guarantees that register moves of cost 2 | |
3966 | never need reloads. */ | |
03b9b5ce | 3967 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
2c62cbaa VM |
3968 | } |
3969 | ||
55a2c322 VM |
3970 | /* Swap operands NOP and NOP + 1. */ |
3971 | static inline void | |
3972 | swap_operands (int nop) | |
3973 | { | |
fab27f52 MM |
3974 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3975 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3976 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
987b67f1 | 3977 | std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); |
55a2c322 VM |
3978 | /* Swap the duplicates too. */ |
3979 | lra_update_dup (curr_id, nop); | |
3980 | lra_update_dup (curr_id, nop + 1); | |
3981 | } | |
3982 | ||
3983 | /* Main entry point of the constraint code: search the body of the | |
3984 | current insn to choose the best alternative. It is mimicking insn | |
3985 | alternative cost calculation model of former reload pass. That is | |
3986 | because machine descriptions were written to use this model. This | |
3987 | model can be changed in future. Make commutative operand exchange | |
3988 | if it is chosen. | |
3989 | ||
d9cf932c VM |
3990 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3991 | constraints. Return true if any change happened during function | |
3992 | call. | |
3993 | ||
3994 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3995 | check that the insn satisfies all constraints. If the insn does | |
3996 | not satisfy any constraint, return true. */ | |
55a2c322 | 3997 | static bool |
d9cf932c | 3998 | curr_insn_transform (bool check_only_p) |
55a2c322 VM |
3999 | { |
4000 | int i, j, k; | |
4001 | int n_operands; | |
4002 | int n_alternatives; | |
aefae0f1 | 4003 | int n_outputs; |
55a2c322 VM |
4004 | int commutative; |
4005 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
511dcace | 4006 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
aefae0f1 | 4007 | signed char outputs[MAX_RECOG_OPERANDS + 1]; |
cfa434f6 | 4008 | rtx_insn *before, *after; |
55a2c322 VM |
4009 | bool alt_p = false; |
4010 | /* Flag that the insn has been changed through a transformation. */ | |
4011 | bool change_p; | |
4012 | bool sec_mem_p; | |
55a2c322 | 4013 | bool use_sec_mem_p; |
55a2c322 VM |
4014 | int max_regno_before; |
4015 | int reused_alternative_num; | |
4016 | ||
2c62cbaa VM |
4017 | curr_insn_set = single_set (curr_insn); |
4018 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
7874b7c5 VM |
4019 | { |
4020 | /* We assume that the corresponding insn alternative has no | |
4021 | earlier clobbers. If it is not the case, don't define move | |
4022 | cost equal to 2 for the corresponding register classes. */ | |
4023 | lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); | |
4024 | return false; | |
4025 | } | |
2c62cbaa | 4026 | |
55a2c322 VM |
4027 | no_input_reloads_p = no_output_reloads_p = false; |
4028 | goal_alt_number = -1; | |
2c62cbaa | 4029 | change_p = sec_mem_p = false; |
55a2c322 | 4030 | |
bd1cd0d0 SB |
4031 | /* CALL_INSNs are not allowed to have any output reloads. */ |
4032 | if (CALL_P (curr_insn)) | |
55a2c322 | 4033 | no_output_reloads_p = true; |
55a2c322 VM |
4034 | |
4035 | n_operands = curr_static_id->n_operands; | |
4036 | n_alternatives = curr_static_id->n_alternatives; | |
4037 | ||
4038 | /* Just return "no reloads" if insn has no operands with | |
4039 | constraints. */ | |
4040 | if (n_operands == 0 || n_alternatives == 0) | |
4041 | return false; | |
4042 | ||
4043 | max_regno_before = max_reg_num (); | |
4044 | ||
4045 | for (i = 0; i < n_operands; i++) | |
4046 | { | |
4047 | goal_alt_matched[i][0] = -1; | |
4048 | goal_alt_matches[i] = -1; | |
4049 | } | |
4050 | ||
4051 | commutative = curr_static_id->commutative; | |
4052 | ||
4053 | /* Now see what we need for pseudos that didn't get hard regs or got | |
4054 | the wrong kind of hard reg. For this, we must consider all the | |
4055 | operands together against the register constraints. */ | |
4056 | ||
821b7577 | 4057 | best_losers = best_overall = INT_MAX; |
36ff9dfb | 4058 | best_reload_sum = 0; |
55a2c322 VM |
4059 | |
4060 | curr_swapped = false; | |
4061 | goal_alt_swapped = false; | |
4062 | ||
d9cf932c VM |
4063 | if (! check_only_p) |
4064 | /* Make equivalence substitution and memory subreg elimination | |
4065 | before address processing because an address legitimacy can | |
4066 | depend on memory mode. */ | |
4067 | for (i = 0; i < n_operands; i++) | |
4068 | { | |
0b87be09 | 4069 | rtx op, subst, old; |
d9cf932c | 4070 | bool op_change_p = false; |
0b87be09 VM |
4071 | |
4072 | if (curr_static_id->operand[i].is_operator) | |
4073 | continue; | |
d9cf932c | 4074 | |
0b87be09 | 4075 | old = op = *curr_id->operand_loc[i]; |
d9cf932c VM |
4076 | if (GET_CODE (old) == SUBREG) |
4077 | old = SUBREG_REG (old); | |
4078 | subst = get_equiv_with_elimination (old, curr_insn); | |
895ff86f | 4079 | original_subreg_reg_mode[i] = VOIDmode; |
987b67f1 | 4080 | equiv_substition_p[i] = false; |
d9cf932c VM |
4081 | if (subst != old) |
4082 | { | |
987b67f1 | 4083 | equiv_substition_p[i] = true; |
d9cf932c VM |
4084 | subst = copy_rtx (subst); |
4085 | lra_assert (REG_P (old)); | |
895ff86f | 4086 | if (GET_CODE (op) != SUBREG) |
d9cf932c | 4087 | *curr_id->operand_loc[i] = subst; |
895ff86f VM |
4088 | else |
4089 | { | |
4090 | SUBREG_REG (op) = subst; | |
4091 | if (GET_MODE (subst) == VOIDmode) | |
4092 | original_subreg_reg_mode[i] = GET_MODE (old); | |
4093 | } | |
d9cf932c VM |
4094 | if (lra_dump_file != NULL) |
4095 | { | |
4096 | fprintf (lra_dump_file, | |
4097 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
4098 | REGNO (old), i, INSN_UID (curr_insn)); | |
4099 | dump_value_slim (lra_dump_file, subst, 1); | |
895ff86f | 4100 | fprintf (lra_dump_file, "\n"); |
d9cf932c VM |
4101 | } |
4102 | op_change_p = change_p = true; | |
4103 | } | |
4104 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
4105 | { | |
4106 | change_p = true; | |
4107 | lra_update_dup (curr_id, i); | |
4108 | } | |
4109 | } | |
55a2c322 VM |
4110 | |
4111 | /* Reload address registers and displacements. We do it before | |
4112 | finding an alternative because of memory constraints. */ | |
cfa434f6 | 4113 | before = after = NULL; |
55a2c322 VM |
4114 | for (i = 0; i < n_operands; i++) |
4115 | if (! curr_static_id->operand[i].is_operator | |
d9cf932c | 4116 | && process_address (i, check_only_p, &before, &after)) |
55a2c322 | 4117 | { |
d9cf932c VM |
4118 | if (check_only_p) |
4119 | return true; | |
55a2c322 VM |
4120 | change_p = true; |
4121 | lra_update_dup (curr_id, i); | |
4122 | } | |
cc8849a1 | 4123 | |
55a2c322 VM |
4124 | if (change_p) |
4125 | /* If we've changed the instruction then any alternative that | |
4126 | we chose previously may no longer be valid. */ | |
7874b7c5 | 4127 | lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); |
55a2c322 | 4128 | |
d9cf932c | 4129 | if (! check_only_p && curr_insn_set != NULL_RTX |
2c62cbaa VM |
4130 | && check_and_process_move (&change_p, &sec_mem_p)) |
4131 | return change_p; | |
4132 | ||
55a2c322 VM |
4133 | try_swapped: |
4134 | ||
7874b7c5 | 4135 | reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; |
55a2c322 VM |
4136 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
4137 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
4138 | reused_alternative_num, INSN_UID (curr_insn)); | |
4139 | ||
4140 | if (process_alt_operands (reused_alternative_num)) | |
4141 | alt_p = true; | |
4142 | ||
d9cf932c VM |
4143 | if (check_only_p) |
4144 | return ! alt_p || best_losers != 0; | |
4145 | ||
55a2c322 VM |
4146 | /* If insn is commutative (it's safe to exchange a certain pair of |
4147 | operands) then we need to try each alternative twice, the second | |
4148 | time matching those two operands as if we had exchanged them. To | |
4149 | do this, really exchange them in operands. | |
4150 | ||
4151 | If we have just tried the alternatives the second time, return | |
4152 | operands to normal and drop through. */ | |
4153 | ||
4154 | if (reused_alternative_num < 0 && commutative >= 0) | |
4155 | { | |
4156 | curr_swapped = !curr_swapped; | |
4157 | if (curr_swapped) | |
4158 | { | |
4159 | swap_operands (commutative); | |
4160 | goto try_swapped; | |
4161 | } | |
4162 | else | |
4163 | swap_operands (commutative); | |
4164 | } | |
4165 | ||
55a2c322 VM |
4166 | if (! alt_p && ! sec_mem_p) |
4167 | { | |
4168 | /* No alternative works with reloads?? */ | |
4169 | if (INSN_CODE (curr_insn) >= 0) | |
4170 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
4171 | error_for_asm (curr_insn, | |
4172 | "inconsistent operand constraints in an %<asm%>"); | |
11067dee | 4173 | lra_asm_error_p = true; |
2f2709e6 VM |
4174 | if (! JUMP_P (curr_insn)) |
4175 | { | |
4176 | /* Avoid further trouble with this insn. Don't generate use | |
4177 | pattern here as we could use the insn SP offset. */ | |
4178 | lra_set_insn_deleted (curr_insn); | |
4179 | } | |
4180 | else | |
4181 | { | |
4182 | lra_invalidate_insn_data (curr_insn); | |
4183 | ira_nullify_asm_goto (curr_insn); | |
4184 | lra_update_insn_regno_info (curr_insn); | |
4185 | } | |
55a2c322 VM |
4186 | return true; |
4187 | } | |
4188 | ||
4189 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
4190 | them. Update the operand numbers of any reloads already | |
4191 | pushed. */ | |
4192 | ||
4193 | if (goal_alt_swapped) | |
4194 | { | |
4195 | if (lra_dump_file != NULL) | |
4196 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
4197 | INSN_UID (curr_insn)); | |
4198 | ||
4199 | /* Swap the duplicates too. */ | |
4200 | swap_operands (commutative); | |
4201 | change_p = true; | |
4202 | } | |
4203 | ||
f15643d4 | 4204 | /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined |
55a2c322 VM |
4205 | too conservatively. So we use the secondary memory only if there |
4206 | is no any alternative without reloads. */ | |
4207 | use_sec_mem_p = false; | |
4208 | if (! alt_p) | |
4209 | use_sec_mem_p = true; | |
4210 | else if (sec_mem_p) | |
4211 | { | |
4212 | for (i = 0; i < n_operands; i++) | |
4213 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
4214 | break; | |
4215 | use_sec_mem_p = i < n_operands; | |
4216 | } | |
4217 | ||
4218 | if (use_sec_mem_p) | |
4219 | { | |
e03dd765 | 4220 | int in = -1, out = -1; |
89d56d79 | 4221 | rtx new_reg, src, dest, rld; |
ef4bddc2 | 4222 | machine_mode sec_mode, rld_mode; |
55a2c322 | 4223 | |
e03dd765 VM |
4224 | lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); |
4225 | dest = SET_DEST (curr_insn_set); | |
4226 | src = SET_SRC (curr_insn_set); | |
4227 | for (i = 0; i < n_operands; i++) | |
4228 | if (*curr_id->operand_loc[i] == dest) | |
4229 | out = i; | |
4230 | else if (*curr_id->operand_loc[i] == src) | |
4231 | in = i; | |
4232 | for (i = 0; i < curr_static_id->n_dups; i++) | |
4233 | if (out < 0 && *curr_id->dup_loc[i] == dest) | |
4234 | out = curr_static_id->dup_num[i]; | |
4235 | else if (in < 0 && *curr_id->dup_loc[i] == src) | |
4236 | in = curr_static_id->dup_num[i]; | |
4237 | lra_assert (out >= 0 && in >= 0 | |
4238 | && curr_static_id->operand[out].type == OP_OUT | |
4239 | && curr_static_id->operand[in].type == OP_IN); | |
bd4288c0 | 4240 | rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest; |
66aa7879 | 4241 | rld_mode = GET_MODE (rld); |
94e23f53 | 4242 | sec_mode = targetm.secondary_memory_needed_mode (rld_mode); |
85419ac5 VM |
4243 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, NO_REGS, NULL, |
4244 | "secondary"); | |
55a2c322 | 4245 | /* If the mode is changed, it should be wider. */ |
bd4288c0 | 4246 | lra_assert (!partial_subreg_p (sec_mode, rld_mode)); |
89d56d79 VM |
4247 | if (sec_mode != rld_mode) |
4248 | { | |
4249 | /* If the target says specifically to use another mode for | |
67914693 | 4250 | secondary memory moves we cannot reuse the original |
89d56d79 | 4251 | insn. */ |
1ccd4874 | 4252 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4253 | lra_process_new_insns (curr_insn, NULL, after, |
1ccd4874 VM |
4254 | "Inserting the sec. move"); |
4255 | /* We may have non null BEFORE here (e.g. after address | |
4256 | processing. */ | |
4257 | push_to_sequence (before); | |
4258 | before = emit_spill_move (true, new_reg, src); | |
4259 | emit_insn (before); | |
4260 | before = get_insns (); | |
4261 | end_sequence (); | |
cfa434f6 | 4262 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
1ccd4874 VM |
4263 | lra_set_insn_deleted (curr_insn); |
4264 | } | |
89d56d79 | 4265 | else if (dest == rld) |
1ccd4874 | 4266 | { |
e03dd765 VM |
4267 | *curr_id->operand_loc[out] = new_reg; |
4268 | lra_update_dup (curr_id, out); | |
66aa7879 | 4269 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4270 | lra_process_new_insns (curr_insn, NULL, after, |
66aa7879 VM |
4271 | "Inserting the sec. move"); |
4272 | } | |
4273 | else | |
4274 | { | |
e03dd765 VM |
4275 | *curr_id->operand_loc[in] = new_reg; |
4276 | lra_update_dup (curr_id, in); | |
1ccd4874 VM |
4277 | /* See comments above. */ |
4278 | push_to_sequence (before); | |
66aa7879 | 4279 | before = emit_spill_move (true, new_reg, src); |
1ccd4874 VM |
4280 | emit_insn (before); |
4281 | before = get_insns (); | |
4282 | end_sequence (); | |
cfa434f6 | 4283 | lra_process_new_insns (curr_insn, before, NULL, |
66aa7879 VM |
4284 | "Inserting the sec. move"); |
4285 | } | |
4286 | lra_update_insn_regno_info (curr_insn); | |
55a2c322 VM |
4287 | return true; |
4288 | } | |
55a2c322 VM |
4289 | |
4290 | lra_assert (goal_alt_number >= 0); | |
4291 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
4292 | ||
4293 | if (lra_dump_file != NULL) | |
4294 | { | |
4295 | const char *p; | |
4296 | ||
4297 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
4298 | goal_alt_number, INSN_UID (curr_insn)); | |
4299 | for (i = 0; i < n_operands; i++) | |
4300 | { | |
4301 | p = (curr_static_id->operand_alternative | |
4302 | [goal_alt_number * n_operands + i].constraint); | |
4303 | if (*p == '\0') | |
4304 | continue; | |
4305 | fprintf (lra_dump_file, " (%d) ", i); | |
4306 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
4307 | fputc (*p, lra_dump_file); | |
4308 | } | |
36ff9dfb VM |
4309 | if (INSN_CODE (curr_insn) >= 0 |
4310 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
4311 | fprintf (lra_dump_file, " {%s}", p); | |
73ca989c RS |
4312 | if (maybe_ne (curr_id->sp_offset, 0)) |
4313 | { | |
4314 | fprintf (lra_dump_file, " (sp_off="); | |
4315 | print_dec (curr_id->sp_offset, lra_dump_file); | |
4316 | fprintf (lra_dump_file, ")"); | |
4317 | } | |
4318 | fprintf (lra_dump_file, "\n"); | |
55a2c322 VM |
4319 | } |
4320 | ||
4321 | /* Right now, for any pair of operands I and J that are required to | |
4322 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
4323 | goal_alt_matched[J]. */ | |
f4eafc30 | 4324 | |
55a2c322 VM |
4325 | for (i = 0; i < n_operands; i++) |
4326 | if ((j = goal_alt_matches[i]) >= 0) | |
4327 | { | |
4328 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
4329 | ; | |
4330 | /* We allow matching one output operand and several input | |
4331 | operands. */ | |
4332 | lra_assert (k == 0 | |
4333 | || (curr_static_id->operand[j].type == OP_OUT | |
4334 | && curr_static_id->operand[i].type == OP_IN | |
4335 | && (curr_static_id->operand | |
4336 | [goal_alt_matched[j][0]].type == OP_IN))); | |
4337 | goal_alt_matched[j][k] = i; | |
4338 | goal_alt_matched[j][k + 1] = -1; | |
4339 | } | |
f4eafc30 | 4340 | |
55a2c322 VM |
4341 | for (i = 0; i < n_operands; i++) |
4342 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
f4eafc30 | 4343 | |
55a2c322 VM |
4344 | /* Any constants that aren't allowed and can't be reloaded into |
4345 | registers are here changed into memory references. */ | |
4346 | for (i = 0; i < n_operands; i++) | |
4347 | if (goal_alt_win[i]) | |
4348 | { | |
4349 | int regno; | |
4350 | enum reg_class new_class; | |
4351 | rtx reg = *curr_id->operand_loc[i]; | |
4352 | ||
4353 | if (GET_CODE (reg) == SUBREG) | |
4354 | reg = SUBREG_REG (reg); | |
f4eafc30 | 4355 | |
55a2c322 VM |
4356 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
4357 | { | |
4358 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
4359 | ||
4360 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
4361 | { | |
4362 | lra_assert (ok_p); | |
a2d0d374 | 4363 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
4364 | } |
4365 | } | |
4366 | } | |
4367 | else | |
4368 | { | |
4369 | const char *constraint; | |
4370 | char c; | |
4371 | rtx op = *curr_id->operand_loc[i]; | |
4372 | rtx subreg = NULL_RTX; | |
ef4bddc2 | 4373 | machine_mode mode = curr_operand_mode[i]; |
f4eafc30 | 4374 | |
55a2c322 VM |
4375 | if (GET_CODE (op) == SUBREG) |
4376 | { | |
4377 | subreg = op; | |
4378 | op = SUBREG_REG (op); | |
4379 | mode = GET_MODE (op); | |
4380 | } | |
f4eafc30 | 4381 | |
55a2c322 VM |
4382 | if (CONST_POOL_OK_P (mode, op) |
4383 | && ((targetm.preferred_reload_class | |
4384 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
4385 | || no_input_reloads_p)) | |
4386 | { | |
4387 | rtx tem = force_const_mem (mode, op); | |
f4eafc30 | 4388 | |
55a2c322 VM |
4389 | change_p = true; |
4390 | if (subreg != NULL_RTX) | |
4391 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
f4eafc30 | 4392 | |
55a2c322 VM |
4393 | *curr_id->operand_loc[i] = tem; |
4394 | lra_update_dup (curr_id, i); | |
d9cf932c | 4395 | process_address (i, false, &before, &after); |
f4eafc30 | 4396 | |
55a2c322 VM |
4397 | /* If the alternative accepts constant pool refs directly |
4398 | there will be no reload needed at all. */ | |
4399 | if (subreg != NULL_RTX) | |
4400 | continue; | |
4401 | /* Skip alternatives before the one requested. */ | |
4402 | constraint = (curr_static_id->operand_alternative | |
4403 | [goal_alt_number * n_operands + i].constraint); | |
4404 | for (; | |
4405 | (c = *constraint) && c != ',' && c != '#'; | |
4406 | constraint += CONSTRAINT_LEN (c, constraint)) | |
4407 | { | |
777e635f | 4408 | enum constraint_num cn = lookup_constraint (constraint); |
9eb1ca69 | 4409 | if ((insn_extra_memory_constraint (cn) |
02f2dc44 VM |
4410 | || insn_extra_special_memory_constraint (cn) |
4411 | || insn_extra_relaxed_memory_constraint (cn)) | |
777e635f | 4412 | && satisfies_memory_constraint_p (tem, cn)) |
55a2c322 | 4413 | break; |
55a2c322 VM |
4414 | } |
4415 | if (c == '\0' || c == ',' || c == '#') | |
4416 | continue; | |
f4eafc30 | 4417 | |
55a2c322 VM |
4418 | goal_alt_win[i] = true; |
4419 | } | |
4420 | } | |
f4eafc30 | 4421 | |
aefae0f1 | 4422 | n_outputs = 0; |
8c59f411 VM |
4423 | for (i = 0; i < n_operands; i++) |
4424 | if (curr_static_id->operand[i].type == OP_OUT) | |
4425 | outputs[n_outputs++] = i; | |
4426 | outputs[n_outputs] = -1; | |
55a2c322 VM |
4427 | for (i = 0; i < n_operands; i++) |
4428 | { | |
2b778c9d VM |
4429 | int regno; |
4430 | bool optional_p = false; | |
55a2c322 VM |
4431 | rtx old, new_reg; |
4432 | rtx op = *curr_id->operand_loc[i]; | |
4433 | ||
4434 | if (goal_alt_win[i]) | |
4435 | { | |
4436 | if (goal_alt[i] == NO_REGS | |
4437 | && REG_P (op) | |
4438 | /* When we assign NO_REGS it means that we will not | |
4439 | assign a hard register to the scratch pseudo by | |
4440 | assigment pass and the scratch pseudo will be | |
4441 | spilled. Spilled scratch pseudos are transformed | |
4442 | back to scratches at the LRA end. */ | |
44fbc9c6 VM |
4443 | && ira_former_scratch_operand_p (curr_insn, i) |
4444 | && ira_former_scratch_p (REGNO (op))) | |
deca73f5 VM |
4445 | { |
4446 | int regno = REGNO (op); | |
a2d0d374 | 4447 | lra_change_class (regno, NO_REGS, " Change to", true); |
deca73f5 VM |
4448 | if (lra_get_regno_hard_regno (regno) >= 0) |
4449 | /* We don't have to mark all insn affected by the | |
4450 | spilled pseudo as there is only one such insn, the | |
4451 | current one. */ | |
4452 | reg_renumber[regno] = -1; | |
6c051d60 VM |
4453 | lra_assert (bitmap_single_bit_set_p |
4454 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
deca73f5 | 4455 | } |
2b778c9d VM |
4456 | /* We can do an optional reload. If the pseudo got a hard |
4457 | reg, we might improve the code through inheritance. If | |
4458 | it does not get a hard register we coalesce memory/memory | |
4459 | moves later. Ignore move insns to avoid cycling. */ | |
b0681c9e | 4460 | if (! lra_simple_p |
2b778c9d VM |
4461 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
4462 | && goal_alt[i] != NO_REGS && REG_P (op) | |
4463 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
a2d0d374 | 4464 | && regno < new_regno_start |
44fbc9c6 | 4465 | && ! ira_former_scratch_p (regno) |
2b778c9d | 4466 | && reg_renumber[regno] < 0 |
3c954213 VM |
4467 | /* Check that the optional reload pseudo will be able to |
4468 | hold given mode value. */ | |
4469 | && ! (prohibited_class_reg_set_mode_p | |
4470 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4471 | PSEUDO_REGNO_MODE (regno))) | |
2b778c9d | 4472 | && (curr_insn_set == NULL_RTX |
b0681c9e VM |
4473 | || !((REG_P (SET_SRC (curr_insn_set)) |
4474 | || MEM_P (SET_SRC (curr_insn_set)) | |
4475 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
4476 | && (REG_P (SET_DEST (curr_insn_set)) | |
4477 | || MEM_P (SET_DEST (curr_insn_set)) | |
4478 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
2b778c9d | 4479 | optional_p = true; |
c07a0a22 VM |
4480 | else if (goal_alt_matched[i][0] != -1 |
4481 | && curr_static_id->operand[i].type == OP_OUT | |
4482 | && (curr_static_id->operand_alternative | |
33163a62 VM |
4483 | [goal_alt_number * n_operands + i].earlyclobber) |
4484 | && REG_P (op)) | |
c07a0a22 | 4485 | { |
33163a62 VM |
4486 | for (j = 0; goal_alt_matched[i][j] != -1; j++) |
4487 | { | |
4488 | rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; | |
4489 | ||
4490 | if (REG_P (op2) && REGNO (op) != REGNO (op2)) | |
4491 | break; | |
4492 | } | |
4493 | if (goal_alt_matched[i][j] != -1) | |
4494 | { | |
4495 | /* Generate reloads for different output and matched | |
4496 | input registers. This is the easiest way to avoid | |
4497 | creation of non-existing register conflicts in | |
e53b6e56 | 4498 | lra-lives.cc. */ |
85419ac5 VM |
4499 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], |
4500 | &goal_alt_exclude_start_hard_regs[i], &before, | |
33163a62 | 4501 | &after, TRUE); |
33163a62 | 4502 | } |
c07a0a22 VM |
4503 | continue; |
4504 | } | |
2b778c9d VM |
4505 | else |
4506 | continue; | |
55a2c322 | 4507 | } |
f4eafc30 | 4508 | |
55a2c322 VM |
4509 | /* Operands that match previous ones have already been handled. */ |
4510 | if (goal_alt_matches[i] >= 0) | |
4511 | continue; | |
4512 | ||
4513 | /* We should not have an operand with a non-offsettable address | |
4514 | appearing where an offsettable address will do. It also may | |
4515 | be a case when the address should be special in other words | |
4516 | not a general one (e.g. it needs no index reg). */ | |
4517 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
4518 | { | |
4519 | enum reg_class rclass; | |
4520 | rtx *loc = &XEXP (op, 0); | |
4521 | enum rtx_code code = GET_CODE (*loc); | |
4522 | ||
4523 | push_to_sequence (before); | |
4524 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
4525 | MEM, SCRATCH); | |
4526 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
4527 | new_reg = emit_inc (rclass, *loc, *loc, | |
4528 | /* This value does not matter for MODIFY. */ | |
4529 | GET_MODE_SIZE (GET_MODE (op))); | |
85419ac5 VM |
4530 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, |
4531 | NULL, FALSE, | |
55a2c322 | 4532 | "offsetable address", &new_reg)) |
634c3ff0 VM |
4533 | { |
4534 | rtx addr = *loc; | |
4535 | enum rtx_code code = GET_CODE (addr); | |
6b3034ea AC |
4536 | bool align_p = false; |
4537 | ||
634c3ff0 | 4538 | if (code == AND && CONST_INT_P (XEXP (addr, 1))) |
6b3034ea AC |
4539 | { |
4540 | /* (and ... (const_int -X)) is used to align to X bytes. */ | |
4541 | align_p = true; | |
4542 | addr = XEXP (*loc, 0); | |
4543 | } | |
4544 | else | |
4545 | addr = canonicalize_reload_addr (addr); | |
4546 | ||
634c3ff0 | 4547 | lra_emit_move (new_reg, addr); |
6b3034ea | 4548 | if (align_p) |
634c3ff0 VM |
4549 | emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))); |
4550 | } | |
55a2c322 VM |
4551 | before = get_insns (); |
4552 | end_sequence (); | |
4553 | *loc = new_reg; | |
4554 | lra_update_dup (curr_id, i); | |
4555 | } | |
4556 | else if (goal_alt_matched[i][0] == -1) | |
4557 | { | |
ef4bddc2 | 4558 | machine_mode mode; |
55a2c322 | 4559 | rtx reg, *loc; |
91914e56 | 4560 | int hard_regno; |
55a2c322 VM |
4561 | enum op_type type = curr_static_id->operand[i].type; |
4562 | ||
4563 | loc = curr_id->operand_loc[i]; | |
4564 | mode = curr_operand_mode[i]; | |
4565 | if (GET_CODE (*loc) == SUBREG) | |
4566 | { | |
4567 | reg = SUBREG_REG (*loc); | |
91914e56 | 4568 | poly_int64 byte = SUBREG_BYTE (*loc); |
55a2c322 | 4569 | if (REG_P (reg) |
8e02e8a0 MF |
4570 | /* Strict_low_part requires reloading the register and not |
4571 | just the subreg. Likewise for a strict subreg no wider | |
4572 | than a word for WORD_REGISTER_OPERATIONS targets. */ | |
55a2c322 | 4573 | && (curr_static_id->operand[i].strict_low |
03a95621 | 4574 | || (!paradoxical_subreg_p (mode, GET_MODE (reg)) |
55a2c322 VM |
4575 | && (hard_regno |
4576 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
4577 | && (simplify_subreg_regno | |
4578 | (hard_regno, | |
4579 | GET_MODE (reg), byte, mode) < 0) | |
4580 | && (goal_alt[i] == NO_REGS | |
4581 | || (simplify_subreg_regno | |
4582 | (ira_class_hard_regs[goal_alt[i]][0], | |
8e02e8a0 | 4583 | GET_MODE (reg), byte, mode) >= 0))) |
e5f83886 | 4584 | || (partial_subreg_p (mode, GET_MODE (reg)) |
cf098191 RS |
4585 | && known_le (GET_MODE_SIZE (GET_MODE (reg)), |
4586 | UNITS_PER_WORD) | |
70596a0f VM |
4587 | && WORD_REGISTER_OPERATIONS)) |
4588 | /* Avoid the situation when there are no available hard regs | |
4589 | for the pseudo mode but there are ones for the subreg | |
4590 | mode: */ | |
4591 | && !(goal_alt[i] != NO_REGS | |
4592 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
4593 | && (prohibited_class_reg_set_mode_p | |
4594 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4595 | GET_MODE (reg))) | |
4596 | && !(prohibited_class_reg_set_mode_p | |
4597 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4598 | mode)))) | |
55a2c322 | 4599 | { |
62cdb862 MF |
4600 | /* An OP_INOUT is required when reloading a subreg of a |
4601 | mode wider than a word to ensure that data beyond the | |
4602 | word being reloaded is preserved. Also automatically | |
4603 | ensure that strict_low_part reloads are made into | |
4604 | OP_INOUT which should already be true from the backend | |
4605 | constraints. */ | |
4606 | if (type == OP_OUT | |
4607 | && (curr_static_id->operand[i].strict_low | |
9eaf97d6 | 4608 | || read_modify_subreg_p (*loc))) |
8b8e23de | 4609 | type = OP_INOUT; |
55a2c322 VM |
4610 | loc = &SUBREG_REG (*loc); |
4611 | mode = GET_MODE (*loc); | |
4612 | } | |
4613 | } | |
4614 | old = *loc; | |
95921002 | 4615 | if (get_reload_reg (type, mode, old, goal_alt[i], |
85419ac5 | 4616 | &goal_alt_exclude_start_hard_regs[i], |
95921002 | 4617 | loc != curr_id->operand_loc[i], "", &new_reg) |
55a2c322 VM |
4618 | && type != OP_OUT) |
4619 | { | |
4620 | push_to_sequence (before); | |
4621 | lra_emit_move (new_reg, old); | |
4622 | before = get_insns (); | |
4623 | end_sequence (); | |
4624 | } | |
4625 | *loc = new_reg; | |
4626 | if (type != OP_IN | |
4627 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
4628 | { | |
4629 | start_sequence (); | |
4630 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
4631 | emit_insn (after); | |
4632 | after = get_insns (); | |
4633 | end_sequence (); | |
4634 | *loc = new_reg; | |
4635 | } | |
4636 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
4637 | if (goal_alt_dont_inherit_ops[j] == i) | |
4638 | { | |
4639 | lra_set_regno_unique_value (REGNO (new_reg)); | |
4640 | break; | |
4641 | } | |
4642 | lra_update_dup (curr_id, i); | |
4643 | } | |
4644 | else if (curr_static_id->operand[i].type == OP_IN | |
4645 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
57d69a63 VM |
4646 | == OP_OUT |
4647 | || (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4648 | == OP_INOUT | |
4649 | && (operands_match_p | |
4650 | (*curr_id->operand_loc[i], | |
4651 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4652 | -1))))) | |
55a2c322 | 4653 | { |
511dcace VM |
4654 | /* generate reloads for input and matched outputs. */ |
4655 | match_inputs[0] = i; | |
4656 | match_inputs[1] = -1; | |
aefae0f1 | 4657 | match_reload (goal_alt_matched[i][0], match_inputs, outputs, |
85419ac5 VM |
4658 | goal_alt[i], &goal_alt_exclude_start_hard_regs[i], |
4659 | &before, &after, | |
599e1cf8 VM |
4660 | curr_static_id->operand_alternative |
4661 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
4662 | .earlyclobber); | |
55a2c322 | 4663 | } |
57d69a63 VM |
4664 | else if ((curr_static_id->operand[i].type == OP_OUT |
4665 | || (curr_static_id->operand[i].type == OP_INOUT | |
4666 | && (operands_match_p | |
4667 | (*curr_id->operand_loc[i], | |
4668 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4669 | -1)))) | |
55a2c322 | 4670 | && (curr_static_id->operand[goal_alt_matched[i][0]].type |
57d69a63 | 4671 | == OP_IN)) |
511dcace | 4672 | /* Generate reloads for output and matched inputs. */ |
85419ac5 VM |
4673 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], |
4674 | &goal_alt_exclude_start_hard_regs[i], &before, &after, | |
4675 | curr_static_id->operand_alternative | |
4676 | [goal_alt_number * n_operands + i].earlyclobber); | |
511dcace VM |
4677 | else if (curr_static_id->operand[i].type == OP_IN |
4678 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4679 | == OP_IN)) | |
4680 | { | |
4681 | /* Generate reloads for matched inputs. */ | |
4682 | match_inputs[0] = i; | |
4683 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
4684 | match_inputs[j + 1] = k; | |
4685 | match_inputs[j + 1] = -1; | |
85419ac5 VM |
4686 | match_reload (-1, match_inputs, outputs, goal_alt[i], |
4687 | &goal_alt_exclude_start_hard_regs[i], | |
4688 | &before, &after, false); | |
511dcace | 4689 | } |
55a2c322 VM |
4690 | else |
4691 | /* We must generate code in any case when function | |
4692 | process_alt_operands decides that it is possible. */ | |
4693 | gcc_unreachable (); | |
aefae0f1 | 4694 | |
2b778c9d VM |
4695 | if (optional_p) |
4696 | { | |
8a8330b7 VM |
4697 | rtx reg = op; |
4698 | ||
4699 | lra_assert (REG_P (reg)); | |
4700 | regno = REGNO (reg); | |
2b778c9d VM |
4701 | op = *curr_id->operand_loc[i]; /* Substitution. */ |
4702 | if (GET_CODE (op) == SUBREG) | |
4703 | op = SUBREG_REG (op); | |
4704 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
4705 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
8a8330b7 | 4706 | lra_reg_info[REGNO (op)].restore_rtx = reg; |
2b778c9d VM |
4707 | if (lra_dump_file != NULL) |
4708 | fprintf (lra_dump_file, | |
4709 | " Making reload reg %d for reg %d optional\n", | |
4710 | REGNO (op), regno); | |
4711 | } | |
55a2c322 VM |
4712 | } |
4713 | if (before != NULL_RTX || after != NULL_RTX | |
4714 | || max_regno_before != max_reg_num ()) | |
4715 | change_p = true; | |
4716 | if (change_p) | |
4717 | { | |
4718 | lra_update_operator_dups (curr_id); | |
4719 | /* Something changes -- process the insn. */ | |
4720 | lra_update_insn_regno_info (curr_insn); | |
4721 | } | |
4722 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
4723 | return change_p; | |
4724 | } | |
4725 | ||
d9cf932c VM |
4726 | /* Return true if INSN satisfies all constraints. In other words, no |
4727 | reload insns are needed. */ | |
4728 | bool | |
4729 | lra_constrain_insn (rtx_insn *insn) | |
4730 | { | |
4731 | int saved_new_regno_start = new_regno_start; | |
4732 | int saved_new_insn_uid_start = new_insn_uid_start; | |
4733 | bool change_p; | |
4734 | ||
4735 | curr_insn = insn; | |
4736 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4737 | curr_static_id = curr_id->insn_static_data; | |
4738 | new_insn_uid_start = get_max_uid (); | |
4739 | new_regno_start = max_reg_num (); | |
4740 | change_p = curr_insn_transform (true); | |
4741 | new_regno_start = saved_new_regno_start; | |
4742 | new_insn_uid_start = saved_new_insn_uid_start; | |
4743 | return ! change_p; | |
4744 | } | |
4745 | ||
55a2c322 VM |
4746 | /* Return true if X is in LIST. */ |
4747 | static bool | |
4748 | in_list_p (rtx x, rtx list) | |
4749 | { | |
4750 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
4751 | if (XEXP (list, 0) == x) | |
4752 | return true; | |
4753 | return false; | |
4754 | } | |
4755 | ||
4756 | /* Return true if X contains an allocatable hard register (if | |
4757 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
4758 | static bool | |
4759 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4760 | { | |
4761 | int i, j; | |
4762 | const char *fmt; | |
4763 | enum rtx_code code; | |
4764 | ||
4765 | code = GET_CODE (x); | |
4766 | if (REG_P (x)) | |
4767 | { | |
4768 | int regno = REGNO (x); | |
4769 | HARD_REG_SET alloc_regs; | |
4770 | ||
4771 | if (hard_reg_p) | |
4772 | { | |
4773 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4774 | regno = lra_get_regno_hard_regno (regno); | |
4775 | if (regno < 0) | |
4776 | return false; | |
50b3f54d | 4777 | alloc_regs = ~lra_no_alloc_regs; |
55a2c322 VM |
4778 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); |
4779 | } | |
4780 | else | |
4781 | { | |
4782 | if (regno < FIRST_PSEUDO_REGISTER) | |
4783 | return false; | |
4784 | if (! spilled_p) | |
4785 | return true; | |
4786 | return lra_get_regno_hard_regno (regno) < 0; | |
4787 | } | |
4788 | } | |
4789 | fmt = GET_RTX_FORMAT (code); | |
4790 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4791 | { | |
4792 | if (fmt[i] == 'e') | |
4793 | { | |
4794 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4795 | return true; | |
4796 | } | |
4797 | else if (fmt[i] == 'E') | |
4798 | { | |
4799 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4800 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4801 | return true; | |
4802 | } | |
4803 | } | |
4804 | return false; | |
4805 | } | |
4806 | ||
28430b2e VM |
4807 | /* Process all regs in location *LOC and change them on equivalent |
4808 | substitution. Return true if any change was done. */ | |
55a2c322 | 4809 | static bool |
28430b2e | 4810 | loc_equivalence_change_p (rtx *loc) |
55a2c322 VM |
4811 | { |
4812 | rtx subst, reg, x = *loc; | |
4813 | bool result = false; | |
4814 | enum rtx_code code = GET_CODE (x); | |
4815 | const char *fmt; | |
4816 | int i, j; | |
4817 | ||
4818 | if (code == SUBREG) | |
4819 | { | |
4820 | reg = SUBREG_REG (x); | |
8d49e7ef | 4821 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
55a2c322 VM |
4822 | && GET_MODE (subst) == VOIDmode) |
4823 | { | |
4824 | /* We cannot reload debug location. Simplify subreg here | |
4825 | while we know the inner mode. */ | |
4826 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4827 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4828 | return true; | |
4829 | } | |
4830 | } | |
8d49e7ef | 4831 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
55a2c322 VM |
4832 | { |
4833 | *loc = subst; | |
4834 | return true; | |
4835 | } | |
4836 | ||
4837 | /* Scan all the operand sub-expressions. */ | |
4838 | fmt = GET_RTX_FORMAT (code); | |
4839 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4840 | { | |
4841 | if (fmt[i] == 'e') | |
28430b2e | 4842 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
55a2c322 VM |
4843 | else if (fmt[i] == 'E') |
4844 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4845 | result | |
28430b2e | 4846 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
55a2c322 VM |
4847 | } |
4848 | return result; | |
4849 | } | |
4850 | ||
d0608e59 | 4851 | /* Similar to loc_equivalence_change_p, but for use as |
4c2b2d79 VM |
4852 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4853 | elimination is done. If it null we don't do the elimination. */ | |
d0608e59 | 4854 | static rtx |
4c2b2d79 | 4855 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
d0608e59 JJ |
4856 | { |
4857 | if (!REG_P (loc)) | |
4858 | return NULL_RTX; | |
4859 | ||
4c2b2d79 | 4860 | rtx subst = (data == NULL |
cfa434f6 | 4861 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
d0608e59 JJ |
4862 | if (subst != loc) |
4863 | return subst; | |
4864 | ||
4865 | return NULL_RTX; | |
4866 | } | |
4867 | ||
55a2c322 VM |
4868 | /* Maximum number of generated reload insns per an insn. It is for |
4869 | preventing this pass cycling in a bug case. */ | |
4870 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4871 | ||
4872 | /* The current iteration number of this LRA pass. */ | |
4873 | int lra_constraint_iter; | |
4874 | ||
7436a1c6 VM |
4875 | /* True if we should during assignment sub-pass check assignment |
4876 | correctness for all pseudos and spill some of them to correct | |
4877 | conflicts. It can be necessary when we substitute equiv which | |
4878 | needs checking register allocation correctness because the | |
4879 | equivalent value contains allocatable hard registers, or when we | |
4880 | restore multi-register pseudo, or when we change the insn code and | |
4881 | its operand became INOUT operand when it was IN one before. */ | |
4882 | bool check_and_force_assignment_correctness_p; | |
55a2c322 VM |
4883 | |
4884 | /* Return true if REGNO is referenced in more than one block. */ | |
4885 | static bool | |
4886 | multi_block_pseudo_p (int regno) | |
4887 | { | |
4888 | basic_block bb = NULL; | |
4889 | unsigned int uid; | |
4890 | bitmap_iterator bi; | |
f4eafc30 | 4891 | |
55a2c322 VM |
4892 | if (regno < FIRST_PSEUDO_REGISTER) |
4893 | return false; | |
f4eafc30 | 4894 | |
4839de55 PP |
4895 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4896 | if (bb == NULL) | |
4897 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4898 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4899 | return true; | |
4900 | return false; | |
55a2c322 VM |
4901 | } |
4902 | ||
1966c91b VM |
4903 | /* Return true if LIST contains a deleted insn. */ |
4904 | static bool | |
0cc97fc5 | 4905 | contains_deleted_insn_p (rtx_insn_list *list) |
1966c91b | 4906 | { |
0cc97fc5 DM |
4907 | for (; list != NULL_RTX; list = list->next ()) |
4908 | if (NOTE_P (list->insn ()) | |
4909 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
1966c91b VM |
4910 | return true; |
4911 | return false; | |
4912 | } | |
4913 | ||
55a2c322 VM |
4914 | /* Return true if X contains a pseudo dying in INSN. */ |
4915 | static bool | |
605780f6 | 4916 | dead_pseudo_p (rtx x, rtx_insn *insn) |
55a2c322 VM |
4917 | { |
4918 | int i, j; | |
4919 | const char *fmt; | |
4920 | enum rtx_code code; | |
4921 | ||
4922 | if (REG_P (x)) | |
4923 | return (insn != NULL_RTX | |
4924 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4925 | code = GET_CODE (x); | |
4926 | fmt = GET_RTX_FORMAT (code); | |
4927 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4928 | { | |
4929 | if (fmt[i] == 'e') | |
4930 | { | |
4931 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4932 | return true; | |
4933 | } | |
4934 | else if (fmt[i] == 'E') | |
4935 | { | |
4936 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4937 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4938 | return true; | |
4939 | } | |
4940 | } | |
4941 | return false; | |
4942 | } | |
4943 | ||
4944 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4945 | side. */ | |
4946 | static bool | |
e8a54173 | 4947 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
55a2c322 VM |
4948 | { |
4949 | rtx set = single_set (insn); | |
4950 | ||
4951 | gcc_assert (set != NULL); | |
4952 | return dead_pseudo_p (SET_SRC (set), insn); | |
4953 | } | |
4954 | ||
4955 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4956 | insn right hand side. */ | |
4957 | static bool | |
4958 | init_insn_rhs_dead_pseudo_p (int regno) | |
4959 | { | |
0cc97fc5 | 4960 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
55a2c322 VM |
4961 | |
4962 | if (insns == NULL) | |
4963 | return false; | |
0cc97fc5 DM |
4964 | for (; insns != NULL_RTX; insns = insns->next ()) |
4965 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
55a2c322 VM |
4966 | return true; |
4967 | return false; | |
4968 | } | |
4969 | ||
01e54ef8 VM |
4970 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4971 | reverse only if we have one init insn with given REGNO as a | |
4972 | source. */ | |
4973 | static bool | |
4974 | reverse_equiv_p (int regno) | |
4975 | { | |
0cc97fc5 DM |
4976 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4977 | rtx set; | |
01e54ef8 | 4978 | |
0cc97fc5 | 4979 | if (insns == NULL) |
01e54ef8 | 4980 | return false; |
0cc97fc5 DM |
4981 | if (! INSN_P (insns->insn ()) |
4982 | || insns->next () != NULL) | |
01e54ef8 | 4983 | return false; |
0cc97fc5 | 4984 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
01e54ef8 VM |
4985 | return false; |
4986 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4987 | } | |
4988 | ||
4989 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4990 | call this function only for non-reverse equivalence. */ | |
4991 | static bool | |
4992 | contains_reloaded_insn_p (int regno) | |
4993 | { | |
4994 | rtx set; | |
0cc97fc5 | 4995 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
01e54ef8 | 4996 | |
0cc97fc5 DM |
4997 | for (; list != NULL; list = list->next ()) |
4998 | if ((set = single_set (list->insn ())) == NULL_RTX | |
01e54ef8 VM |
4999 | || ! REG_P (SET_DEST (set)) |
5000 | || (int) REGNO (SET_DEST (set)) != regno) | |
5001 | return true; | |
5002 | return false; | |
5003 | } | |
5004 | ||
57688950 VM |
5005 | /* Try combine secondary memory reload insn FROM for insn TO into TO insn. |
5006 | FROM should be a load insn (usually a secondary memory reload insn). Return | |
5007 | TRUE in case of success. */ | |
5008 | static bool | |
5009 | combine_reload_insn (rtx_insn *from, rtx_insn *to) | |
5010 | { | |
5011 | bool ok_p; | |
5012 | rtx_insn *saved_insn; | |
5013 | rtx set, from_reg, to_reg, op; | |
5014 | enum reg_class to_class, from_class; | |
5015 | int n, nop; | |
5016 | signed char changed_nops[MAX_RECOG_OPERANDS + 1]; | |
57688950 VM |
5017 | |
5018 | /* Check conditions for second memory reload and original insn: */ | |
5019 | if ((targetm.secondary_memory_needed | |
5020 | == hook_bool_mode_reg_class_t_reg_class_t_false) | |
44a13125 PB |
5021 | || NEXT_INSN (from) != to |
5022 | || !NONDEBUG_INSN_P (to) | |
5023 | || CALL_P (to)) | |
5024 | return false; | |
5025 | ||
5026 | lra_insn_recog_data_t id = lra_get_insn_recog_data (to); | |
5027 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
5028 | ||
5029 | if (id->used_insn_alternative == LRA_UNKNOWN_ALT | |
57688950 VM |
5030 | || (set = single_set (from)) == NULL_RTX) |
5031 | return false; | |
5032 | from_reg = SET_DEST (set); | |
5033 | to_reg = SET_SRC (set); | |
5034 | /* Ignore optional reloads: */ | |
5035 | if (! REG_P (from_reg) || ! REG_P (to_reg) | |
5036 | || bitmap_bit_p (&lra_optional_reload_pseudos, REGNO (from_reg))) | |
5037 | return false; | |
5038 | to_class = lra_get_allocno_class (REGNO (to_reg)); | |
5039 | from_class = lra_get_allocno_class (REGNO (from_reg)); | |
5040 | /* Check that reload insn is a load: */ | |
5041 | if (to_class != NO_REGS || from_class == NO_REGS) | |
5042 | return false; | |
5043 | for (n = nop = 0; nop < static_id->n_operands; nop++) | |
5044 | { | |
5045 | if (static_id->operand[nop].type != OP_IN) | |
5046 | continue; | |
5047 | op = *id->operand_loc[nop]; | |
5048 | if (!REG_P (op) || REGNO (op) != REGNO (from_reg)) | |
5049 | continue; | |
5050 | *id->operand_loc[nop] = to_reg; | |
5051 | changed_nops[n++] = nop; | |
5052 | } | |
5053 | changed_nops[n] = -1; | |
5054 | lra_update_dups (id, changed_nops); | |
5055 | lra_update_insn_regno_info (to); | |
5056 | ok_p = recog_memoized (to) >= 0; | |
5057 | if (ok_p) | |
5058 | { | |
5059 | /* Check that combined insn does not need any reloads: */ | |
5060 | saved_insn = curr_insn; | |
5061 | curr_insn = to; | |
5062 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5063 | curr_static_id = curr_id->insn_static_data; | |
5064 | ok_p = !curr_insn_transform (true); | |
5065 | curr_insn = saved_insn; | |
5066 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5067 | curr_static_id = curr_id->insn_static_data; | |
5068 | } | |
5069 | if (ok_p) | |
5070 | { | |
5071 | id->used_insn_alternative = -1; | |
5072 | lra_push_insn_and_update_insn_regno_info (to); | |
5073 | if (lra_dump_file != NULL) | |
5074 | { | |
5075 | fprintf (lra_dump_file, " Use combined insn:\n"); | |
5076 | dump_insn_slim (lra_dump_file, to); | |
5077 | } | |
5078 | return true; | |
5079 | } | |
5080 | if (lra_dump_file != NULL) | |
5081 | { | |
5082 | fprintf (lra_dump_file, " Failed combined insn:\n"); | |
5083 | dump_insn_slim (lra_dump_file, to); | |
5084 | } | |
5085 | for (int i = 0; i < n; i++) | |
5086 | { | |
5087 | nop = changed_nops[i]; | |
5088 | *id->operand_loc[nop] = from_reg; | |
5089 | } | |
5090 | lra_update_dups (id, changed_nops); | |
5091 | lra_update_insn_regno_info (to); | |
5092 | if (lra_dump_file != NULL) | |
5093 | { | |
5094 | fprintf (lra_dump_file, " Restoring insn after failed combining:\n"); | |
5095 | dump_insn_slim (lra_dump_file, to); | |
5096 | } | |
5097 | return false; | |
5098 | } | |
5099 | ||
55a2c322 VM |
5100 | /* Entry function of LRA constraint pass. Return true if the |
5101 | constraint pass did change the code. */ | |
5102 | bool | |
5103 | lra_constraints (bool first_p) | |
5104 | { | |
5105 | bool changed_p; | |
5106 | int i, hard_regno, new_insns_num; | |
6cd1dd26 VM |
5107 | unsigned int min_len, new_min_len, uid; |
5108 | rtx set, x, reg, dest_reg; | |
57688950 | 5109 | rtx_insn *original_insn; |
55a2c322 | 5110 | basic_block last_bb; |
6cd1dd26 | 5111 | bitmap_iterator bi; |
55a2c322 VM |
5112 | |
5113 | lra_constraint_iter++; | |
5114 | if (lra_dump_file != NULL) | |
5115 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
5116 | lra_constraint_iter); | |
55a2c322 | 5117 | changed_p = false; |
bcb21886 KY |
5118 | if (pic_offset_table_rtx |
5119 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
7436a1c6 VM |
5120 | check_and_force_assignment_correctness_p = true; |
5121 | else if (first_p) | |
15961e4a VM |
5122 | /* On the first iteration we should check IRA assignment |
5123 | correctness. In rare cases, the assignments can be wrong as | |
7e4d17a8 VM |
5124 | early clobbers operands are ignored in IRA or usages of |
5125 | paradoxical sub-registers are not taken into account by | |
5126 | IRA. */ | |
7436a1c6 | 5127 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
5128 | new_insn_uid_start = get_max_uid (); |
5129 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
8d49e7ef VM |
5130 | /* Mark used hard regs for target stack size calulations. */ |
5131 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
5132 | if (lra_reg_info[i].nrefs != 0 | |
5133 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
5134 | { | |
5135 | int j, nregs; | |
5136 | ||
ad474626 | 5137 | nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode); |
8d49e7ef VM |
5138 | for (j = 0; j < nregs; j++) |
5139 | df_set_regs_ever_live (hard_regno + j, true); | |
5140 | } | |
5141 | /* Do elimination before the equivalence processing as we can spill | |
5142 | some pseudos during elimination. */ | |
5143 | lra_eliminate (false, first_p); | |
d648b5ff | 5144 | auto_bitmap equiv_insn_bitmap (®_obstack); |
55a2c322 VM |
5145 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
5146 | if (lra_reg_info[i].nrefs != 0) | |
5147 | { | |
5148 | ira_reg_equiv[i].profitable_p = true; | |
6cd1dd26 | 5149 | reg = regno_reg_rtx[i]; |
8d49e7ef | 5150 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
55a2c322 VM |
5151 | { |
5152 | bool pseudo_p = contains_reg_p (x, false, false); | |
55a2c322 | 5153 | |
67914693 | 5154 | /* After RTL transformation, we cannot guarantee that |
1966c91b VM |
5155 | pseudo in the substitution was not reloaded which might |
5156 | make equivalence invalid. For example, in reverse | |
5157 | equiv of p0 | |
5158 | ||
5159 | p0 <- ... | |
5160 | ... | |
5161 | equiv_mem <- p0 | |
5162 | ||
5163 | the memory address register was reloaded before the 2nd | |
5164 | insn. */ | |
5165 | if ((! first_p && pseudo_p) | |
5166 | /* We don't use DF for compilation speed sake. So it | |
5167 | is problematic to update live info when we use an | |
5168 | equivalence containing pseudos in more than one | |
5169 | BB. */ | |
5170 | || (pseudo_p && multi_block_pseudo_p (i)) | |
5171 | /* If an init insn was deleted for some reason, cancel | |
5172 | the equiv. We could update the equiv insns after | |
5173 | transformations including an equiv insn deletion | |
5174 | but it is not worthy as such cases are extremely | |
5175 | rare. */ | |
5176 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
55a2c322 VM |
5177 | /* If it is not a reverse equivalence, we check that a |
5178 | pseudo in rhs of the init insn is not dying in the | |
5179 | insn. Otherwise, the live info at the beginning of | |
5180 | the corresponding BB might be wrong after we | |
5181 | removed the insn. When the equiv can be a | |
5182 | constant, the right hand side of the init insn can | |
5183 | be a pseudo. */ | |
01e54ef8 VM |
5184 | || (! reverse_equiv_p (i) |
5185 | && (init_insn_rhs_dead_pseudo_p (i) | |
5186 | /* If we reloaded the pseudo in an equivalence | |
67914693 | 5187 | init insn, we cannot remove the equiv init |
01e54ef8 VM |
5188 | insns and the init insns might write into |
5189 | const memory in this case. */ | |
5190 | || contains_reloaded_insn_p (i))) | |
b28ece32 VM |
5191 | /* Prevent access beyond equivalent memory for |
5192 | paradoxical subregs. */ | |
5193 | || (MEM_P (x) | |
cf098191 RS |
5194 | && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode), |
5195 | GET_MODE_SIZE (GET_MODE (x)))) | |
bcb21886 KY |
5196 | || (pic_offset_table_rtx |
5197 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
5198 | && (targetm.preferred_reload_class | |
5199 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
b81a2f0d | 5200 | || contains_symbol_ref_p (x)))) |
a33e3dcb VM |
5201 | ira_reg_equiv[i].defined_p |
5202 | = ira_reg_equiv[i].caller_save_p = false; | |
55a2c322 VM |
5203 | if (contains_reg_p (x, false, true)) |
5204 | ira_reg_equiv[i].profitable_p = false; | |
8d49e7ef | 5205 | if (get_equiv (reg) != reg) |
d648b5ff | 5206 | bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
55a2c322 VM |
5207 | } |
5208 | } | |
4c2b2d79 VM |
5209 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
5210 | update_equiv (i); | |
6cd1dd26 VM |
5211 | /* We should add all insns containing pseudos which should be |
5212 | substituted by their equivalences. */ | |
d648b5ff | 5213 | EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi) |
6cd1dd26 | 5214 | lra_push_insn_by_uid (uid); |
55a2c322 VM |
5215 | min_len = lra_insn_stack_length (); |
5216 | new_insns_num = 0; | |
5217 | last_bb = NULL; | |
5218 | changed_p = false; | |
57688950 | 5219 | original_insn = NULL; |
55a2c322 VM |
5220 | while ((new_min_len = lra_insn_stack_length ()) != 0) |
5221 | { | |
5222 | curr_insn = lra_pop_insn (); | |
5223 | --new_min_len; | |
f4eafc30 | 5224 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
55a2c322 VM |
5225 | if (curr_bb != last_bb) |
5226 | { | |
5227 | last_bb = curr_bb; | |
5228 | bb_reload_num = lra_curr_reload_num; | |
5229 | } | |
5230 | if (min_len > new_min_len) | |
5231 | { | |
5232 | min_len = new_min_len; | |
5233 | new_insns_num = 0; | |
57688950 | 5234 | original_insn = curr_insn; |
55a2c322 | 5235 | } |
57688950 VM |
5236 | else if (combine_reload_insn (curr_insn, original_insn)) |
5237 | { | |
5238 | continue; | |
5239 | } | |
55a2c322 VM |
5240 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) |
5241 | internal_error | |
a9c697b8 | 5242 | ("maximum number of generated reload insns per insn achieved (%d)", |
55a2c322 VM |
5243 | MAX_RELOAD_INSNS_NUMBER); |
5244 | new_insns_num++; | |
5245 | if (DEBUG_INSN_P (curr_insn)) | |
5246 | { | |
5247 | /* We need to check equivalence in debug insn and change | |
5248 | pseudo to the equivalent value if necessary. */ | |
5249 | curr_id = lra_get_insn_recog_data (curr_insn); | |
d648b5ff | 5250 | if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))) |
4d64ce5c | 5251 | { |
d0608e59 JJ |
5252 | rtx old = *curr_id->operand_loc[0]; |
5253 | *curr_id->operand_loc[0] | |
5254 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
4c2b2d79 | 5255 | loc_equivalence_callback, curr_insn); |
d0608e59 JJ |
5256 | if (old != *curr_id->operand_loc[0]) |
5257 | { | |
5258 | lra_update_insn_regno_info (curr_insn); | |
5259 | changed_p = true; | |
5260 | } | |
4d64ce5c | 5261 | } |
55a2c322 VM |
5262 | } |
5263 | else if (INSN_P (curr_insn)) | |
5264 | { | |
5265 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
5266 | { | |
5267 | dest_reg = SET_DEST (set); | |
5268 | /* The equivalence pseudo could be set up as SUBREG in a | |
5269 | case when it is a call restore insn in a mode | |
5270 | different from the pseudo mode. */ | |
5271 | if (GET_CODE (dest_reg) == SUBREG) | |
5272 | dest_reg = SUBREG_REG (dest_reg); | |
5273 | if ((REG_P (dest_reg) | |
8d49e7ef | 5274 | && (x = get_equiv (dest_reg)) != dest_reg |
55a2c322 | 5275 | /* Remove insns which set up a pseudo whose value |
67914693 | 5276 | cannot be changed. Such insns might be not in |
55a2c322 VM |
5277 | init_insns because we don't update equiv data |
5278 | during insn transformations. | |
5a107a0f | 5279 | |
55a2c322 VM |
5280 | As an example, let suppose that a pseudo got |
5281 | hard register and on the 1st pass was not | |
5282 | changed to equivalent constant. We generate an | |
5283 | additional insn setting up the pseudo because of | |
5284 | secondary memory movement. Then the pseudo is | |
5285 | spilled and we use the equiv constant. In this | |
5286 | case we should remove the additional insn and | |
f6937e32 | 5287 | this insn is not init_insns list. */ |
55a2c322 | 5288 | && (! MEM_P (x) || MEM_READONLY_P (x) |
f6937e32 VM |
5289 | /* Check that this is actually an insn setting |
5290 | up the equivalence. */ | |
55a2c322 VM |
5291 | || in_list_p (curr_insn, |
5292 | ira_reg_equiv | |
5293 | [REGNO (dest_reg)].init_insns))) | |
8d49e7ef | 5294 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
55a2c322 VM |
5295 | && in_list_p (curr_insn, |
5296 | ira_reg_equiv | |
5297 | [REGNO (SET_SRC (set))].init_insns))) | |
5298 | { | |
5299 | /* This is equiv init insn of pseudo which did not get a | |
5300 | hard register -- remove the insn. */ | |
5301 | if (lra_dump_file != NULL) | |
5302 | { | |
5303 | fprintf (lra_dump_file, | |
5304 | " Removing equiv init insn %i (freq=%d)\n", | |
5305 | INSN_UID (curr_insn), | |
fef37404 | 5306 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
cfbeaedf | 5307 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5308 | } |
5309 | if (contains_reg_p (x, true, false)) | |
7436a1c6 | 5310 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
5311 | lra_set_insn_deleted (curr_insn); |
5312 | continue; | |
5313 | } | |
5314 | } | |
5315 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5316 | curr_static_id = curr_id->insn_static_data; | |
5317 | init_curr_insn_input_reloads (); | |
5318 | init_curr_operand_mode (); | |
d9cf932c | 5319 | if (curr_insn_transform (false)) |
55a2c322 | 5320 | changed_p = true; |
28430b2e VM |
5321 | /* Check non-transformed insns too for equiv change as USE |
5322 | or CLOBBER don't need reloads but can contain pseudos | |
5323 | being changed on their equivalences. */ | |
d648b5ff | 5324 | else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)) |
28430b2e VM |
5325 | && loc_equivalence_change_p (&PATTERN (curr_insn))) |
5326 | { | |
5327 | lra_update_insn_regno_info (curr_insn); | |
5328 | changed_p = true; | |
5329 | } | |
55a2c322 VM |
5330 | } |
5331 | } | |
d648b5ff | 5332 | |
55a2c322 VM |
5333 | /* If we used a new hard regno, changed_p should be true because the |
5334 | hard reg is assigned to a new pseudo. */ | |
b2b29377 | 5335 | if (flag_checking && !changed_p) |
55a2c322 VM |
5336 | { |
5337 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
5338 | if (lra_reg_info[i].nrefs != 0 | |
5339 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
5340 | { | |
ad474626 RS |
5341 | int j, nregs = hard_regno_nregs (hard_regno, |
5342 | PSEUDO_REGNO_MODE (i)); | |
f4eafc30 | 5343 | |
55a2c322 VM |
5344 | for (j = 0; j < nregs; j++) |
5345 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
5346 | } | |
5347 | } | |
55a2c322 VM |
5348 | return changed_p; |
5349 | } | |
5350 | ||
8a8330b7 VM |
5351 | static void initiate_invariants (void); |
5352 | static void finish_invariants (void); | |
5353 | ||
55a2c322 VM |
5354 | /* Initiate the LRA constraint pass. It is done once per |
5355 | function. */ | |
5356 | void | |
5357 | lra_constraints_init (void) | |
5358 | { | |
8a8330b7 | 5359 | initiate_invariants (); |
55a2c322 VM |
5360 | } |
5361 | ||
5362 | /* Finalize the LRA constraint pass. It is done once per | |
5363 | function. */ | |
5364 | void | |
5365 | lra_constraints_finish (void) | |
5366 | { | |
8a8330b7 VM |
5367 | finish_invariants (); |
5368 | } | |
5369 | ||
5370 | \f | |
5371 | ||
5372 | /* Structure describes invariants for ineheritance. */ | |
eb0f8780 | 5373 | struct lra_invariant |
8a8330b7 VM |
5374 | { |
5375 | /* The order number of the invariant. */ | |
5376 | int num; | |
5377 | /* The invariant RTX. */ | |
5378 | rtx invariant_rtx; | |
5379 | /* The origin insn of the invariant. */ | |
5380 | rtx_insn *insn; | |
5381 | }; | |
5382 | ||
eb0f8780 | 5383 | typedef lra_invariant invariant_t; |
8a8330b7 VM |
5384 | typedef invariant_t *invariant_ptr_t; |
5385 | typedef const invariant_t *const_invariant_ptr_t; | |
5386 | ||
5387 | /* Pointer to the inheritance invariants. */ | |
5388 | static vec<invariant_ptr_t> invariants; | |
5389 | ||
5390 | /* Allocation pool for the invariants. */ | |
eb0f8780 | 5391 | static object_allocator<lra_invariant> *invariants_pool; |
8a8330b7 VM |
5392 | |
5393 | /* Hash table for the invariants. */ | |
5394 | static htab_t invariant_table; | |
5395 | ||
5396 | /* Hash function for INVARIANT. */ | |
5397 | static hashval_t | |
5398 | invariant_hash (const void *invariant) | |
5399 | { | |
5400 | rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; | |
5401 | return lra_rtx_hash (inv); | |
5402 | } | |
5403 | ||
5404 | /* Equal function for invariants INVARIANT1 and INVARIANT2. */ | |
5405 | static int | |
5406 | invariant_eq_p (const void *invariant1, const void *invariant2) | |
5407 | { | |
5408 | rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; | |
5409 | rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; | |
5410 | ||
5411 | return rtx_equal_p (inv1, inv2); | |
5412 | } | |
5413 | ||
5414 | /* Insert INVARIANT_RTX into the table if it is not there yet. Return | |
5415 | invariant which is in the table. */ | |
5416 | static invariant_ptr_t | |
5417 | insert_invariant (rtx invariant_rtx) | |
5418 | { | |
5419 | void **entry_ptr; | |
5420 | invariant_t invariant; | |
5421 | invariant_ptr_t invariant_ptr; | |
5422 | ||
5423 | invariant.invariant_rtx = invariant_rtx; | |
5424 | entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); | |
5425 | if (*entry_ptr == NULL) | |
5426 | { | |
5427 | invariant_ptr = invariants_pool->allocate (); | |
5428 | invariant_ptr->invariant_rtx = invariant_rtx; | |
5429 | invariant_ptr->insn = NULL; | |
5430 | invariants.safe_push (invariant_ptr); | |
5431 | *entry_ptr = (void *) invariant_ptr; | |
5432 | } | |
5433 | return (invariant_ptr_t) *entry_ptr; | |
5434 | } | |
5435 | ||
5436 | /* Initiate the invariant table. */ | |
5437 | static void | |
5438 | initiate_invariants (void) | |
5439 | { | |
5440 | invariants.create (100); | |
eb0f8780 ML |
5441 | invariants_pool |
5442 | = new object_allocator<lra_invariant> ("Inheritance invariants"); | |
8a8330b7 VM |
5443 | invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); |
5444 | } | |
5445 | ||
5446 | /* Finish the invariant table. */ | |
5447 | static void | |
5448 | finish_invariants (void) | |
5449 | { | |
5450 | htab_delete (invariant_table); | |
5451 | delete invariants_pool; | |
5452 | invariants.release (); | |
5453 | } | |
5454 | ||
5455 | /* Make the invariant table empty. */ | |
5456 | static void | |
5457 | clear_invariants (void) | |
5458 | { | |
5459 | htab_empty (invariant_table); | |
5460 | invariants_pool->release (); | |
5461 | invariants.truncate (0); | |
55a2c322 VM |
5462 | } |
5463 | ||
5464 | \f | |
5465 | ||
5466 | /* This page contains code to do inheritance/split | |
5467 | transformations. */ | |
5468 | ||
5469 | /* Number of reloads passed so far in current EBB. */ | |
5470 | static int reloads_num; | |
5471 | ||
5472 | /* Number of calls passed so far in current EBB. */ | |
5473 | static int calls_num; | |
5474 | ||
a1e6ee38 RS |
5475 | /* Index ID is the CALLS_NUM associated the last call we saw with |
5476 | ABI identifier ID. */ | |
5477 | static int last_call_for_abi[NUM_ABI_IDS]; | |
5478 | ||
5479 | /* Which registers have been fully or partially clobbered by a call | |
5480 | since they were last used. */ | |
5481 | static HARD_REG_SET full_and_partial_call_clobbers; | |
5482 | ||
55a2c322 VM |
5483 | /* Current reload pseudo check for validity of elements in |
5484 | USAGE_INSNS. */ | |
5485 | static int curr_usage_insns_check; | |
5486 | ||
5487 | /* Info about last usage of registers in EBB to do inheritance/split | |
5488 | transformation. Inheritance transformation is done from a spilled | |
5489 | pseudo and split transformations from a hard register or a pseudo | |
5490 | assigned to a hard register. */ | |
5491 | struct usage_insns | |
5492 | { | |
5493 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
5494 | value INSNS is valid. The insns is chain of optional debug insns | |
1ccd4874 VM |
5495 | and a finishing non-debug insn using the corresponding reg. The |
5496 | value is also used to mark the registers which are set up in the | |
5497 | current insn. The negated insn uid is used for this. */ | |
55a2c322 VM |
5498 | int check; |
5499 | /* Value of global reloads_num at the last insn in INSNS. */ | |
5500 | int reloads_num; | |
5501 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
5502 | int calls_num; | |
5503 | /* It can be true only for splitting. And it means that the restore | |
5504 | insn should be put after insn given by the following member. */ | |
5505 | bool after_p; | |
5506 | /* Next insns in the current EBB which use the original reg and the | |
5507 | original reg value is not changed between the current insn and | |
5508 | the next insns. In order words, e.g. for inheritance, if we need | |
5509 | to use the original reg value again in the next insns we can try | |
5510 | to use the value in a hard register from a reload insn of the | |
5511 | current insn. */ | |
5512 | rtx insns; | |
5513 | }; | |
5514 | ||
5515 | /* Map: regno -> corresponding pseudo usage insns. */ | |
5516 | static struct usage_insns *usage_insns; | |
5517 | ||
5518 | static void | |
1476d1bd | 5519 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
55a2c322 VM |
5520 | { |
5521 | usage_insns[regno].check = curr_usage_insns_check; | |
5522 | usage_insns[regno].insns = insn; | |
5523 | usage_insns[regno].reloads_num = reloads_num; | |
5524 | usage_insns[regno].calls_num = calls_num; | |
5525 | usage_insns[regno].after_p = after_p; | |
a1e6ee38 RS |
5526 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) |
5527 | remove_from_hard_reg_set (&full_and_partial_call_clobbers, | |
5528 | PSEUDO_REGNO_MODE (regno), | |
5529 | reg_renumber[regno]); | |
55a2c322 VM |
5530 | } |
5531 | ||
5532 | /* The function is used to form list REGNO usages which consists of | |
5533 | optional debug insns finished by a non-debug insn using REGNO. | |
5534 | RELOADS_NUM is current number of reload insns processed so far. */ | |
5535 | static void | |
767dc529 | 5536 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
55a2c322 VM |
5537 | { |
5538 | rtx next_usage_insns; | |
f4eafc30 | 5539 | |
55a2c322 VM |
5540 | if (usage_insns[regno].check == curr_usage_insns_check |
5541 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
5542 | && DEBUG_INSN_P (insn)) | |
5543 | { | |
5544 | /* Check that we did not add the debug insn yet. */ | |
5545 | if (next_usage_insns != insn | |
5546 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
5547 | || XEXP (next_usage_insns, 0) != insn)) | |
5548 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
5549 | next_usage_insns); | |
5550 | } | |
5551 | else if (NONDEBUG_INSN_P (insn)) | |
5552 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
5553 | else | |
5554 | usage_insns[regno].check = 0; | |
5555 | } | |
f4eafc30 | 5556 | |
bc3591eb | 5557 | /* Return first non-debug insn in list USAGE_INSNS. */ |
e8a54173 | 5558 | static rtx_insn * |
bc3591eb VM |
5559 | skip_usage_debug_insns (rtx usage_insns) |
5560 | { | |
5561 | rtx insn; | |
5562 | ||
5563 | /* Skip debug insns. */ | |
5564 | for (insn = usage_insns; | |
5565 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
5566 | insn = XEXP (insn, 1)) | |
5567 | ; | |
e8a54173 | 5568 | return safe_as_a <rtx_insn *> (insn); |
bc3591eb VM |
5569 | } |
5570 | ||
5571 | /* Return true if we need secondary memory moves for insn in | |
5572 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
5573 | into the insn. */ | |
5574 | static bool | |
fbebbadd JR |
5575 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
5576 | rtx usage_insns ATTRIBUTE_UNUSED) | |
bc3591eb | 5577 | { |
e8a54173 DM |
5578 | rtx_insn *insn; |
5579 | rtx set, dest; | |
bc3591eb VM |
5580 | enum reg_class cl; |
5581 | ||
5582 | if (inher_cl == ALL_REGS | |
5583 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
5584 | return false; | |
5585 | lra_assert (INSN_P (insn)); | |
5586 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
5587 | return false; | |
5588 | dest = SET_DEST (set); | |
5589 | if (! REG_P (dest)) | |
5590 | return false; | |
5591 | lra_assert (inher_cl != NO_REGS); | |
5592 | cl = get_reg_class (REGNO (dest)); | |
5593 | return (cl != NO_REGS && cl != ALL_REGS | |
f15643d4 | 5594 | && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl)); |
bc3591eb VM |
5595 | } |
5596 | ||
55a2c322 VM |
5597 | /* Registers involved in inheritance/split in the current EBB |
5598 | (inheritance/split pseudos and original registers). */ | |
5599 | static bitmap_head check_only_regs; | |
5600 | ||
67914693 | 5601 | /* Reload pseudos cannot be involded in invariant inheritance in the |
8a8330b7 VM |
5602 | current EBB. */ |
5603 | static bitmap_head invalid_invariant_regs; | |
5604 | ||
55a2c322 VM |
5605 | /* Do inheritance transformations for insn INSN, which defines (if |
5606 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
5607 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
5608 | form as the "insns" field of usage_insns. Return true if we | |
5609 | succeed in such transformation. | |
5610 | ||
5611 | The transformations look like: | |
5612 | ||
5613 | p <- ... i <- ... | |
5614 | ... p <- i (new insn) | |
5615 | ... => | |
5616 | <- ... p ... <- ... i ... | |
5617 | or | |
5618 | ... i <- p (new insn) | |
5619 | <- ... p ... <- ... i ... | |
5620 | ... => | |
5621 | <- ... p ... <- ... i ... | |
5622 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
f4eafc30 L |
5623 | |
5624 | ||
55a2c322 VM |
5625 | The inheritance pseudo has the smallest class of two classes CL and |
5626 | class of ORIGINAL REGNO. */ | |
5627 | static bool | |
5628 | inherit_reload_reg (bool def_p, int original_regno, | |
cfa434f6 | 5629 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
55a2c322 | 5630 | { |
2ae577fd VM |
5631 | if (optimize_function_for_size_p (cfun)) |
5632 | return false; | |
5633 | ||
55a2c322 VM |
5634 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
5635 | rtx original_reg = regno_reg_rtx[original_regno]; | |
cfa434f6 DM |
5636 | rtx new_reg, usage_insn; |
5637 | rtx_insn *new_insns; | |
55a2c322 VM |
5638 | |
5639 | lra_assert (! usage_insns[original_regno].after_p); | |
5640 | if (lra_dump_file != NULL) | |
5641 | fprintf (lra_dump_file, | |
bc3591eb | 5642 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
55a2c322 VM |
5643 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
5644 | { | |
5645 | if (lra_dump_file != NULL) | |
5646 | { | |
5647 | fprintf (lra_dump_file, | |
bc3591eb | 5648 | " Rejecting inheritance for %d " |
55a2c322 VM |
5649 | "because of disjoint classes %s and %s\n", |
5650 | original_regno, reg_class_names[cl], | |
5651 | reg_class_names[rclass]); | |
5652 | fprintf (lra_dump_file, | |
bc3591eb | 5653 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
55a2c322 VM |
5654 | } |
5655 | return false; | |
5656 | } | |
5657 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
5658 | /* We don't use a subset of two classes because it can be | |
5659 | NO_REGS. This transformation is still profitable in most | |
5660 | cases even if the classes are not intersected as register | |
5661 | move is probably cheaper than a memory load. */ | |
5662 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
5663 | { | |
5664 | if (lra_dump_file != NULL) | |
5665 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
5666 | reg_class_names[cl], reg_class_names[rclass]); | |
f4eafc30 | 5667 | |
55a2c322 VM |
5668 | rclass = cl; |
5669 | } | |
66aa7879 | 5670 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
bc3591eb VM |
5671 | { |
5672 | /* Reject inheritance resulting in secondary memory moves. | |
5673 | Otherwise, there is a danger in LRA cycling. Also such | |
5674 | transformation will be unprofitable. */ | |
5675 | if (lra_dump_file != NULL) | |
5676 | { | |
e8a54173 | 5677 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
bc3591eb VM |
5678 | rtx set = single_set (insn); |
5679 | ||
5680 | lra_assert (set != NULL_RTX); | |
5681 | ||
5682 | rtx dest = SET_DEST (set); | |
5683 | ||
5684 | lra_assert (REG_P (dest)); | |
5685 | fprintf (lra_dump_file, | |
5686 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
5687 | "as secondary mem is needed\n", | |
5688 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
66aa7879 | 5689 | original_regno, reg_class_names[rclass]); |
bc3591eb VM |
5690 | fprintf (lra_dump_file, |
5691 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5692 | } | |
5693 | return false; | |
5694 | } | |
55a2c322 | 5695 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
85419ac5 | 5696 | rclass, NULL, "inheritance"); |
55a2c322 VM |
5697 | start_sequence (); |
5698 | if (def_p) | |
a810ee82 | 5699 | lra_emit_move (original_reg, new_reg); |
55a2c322 | 5700 | else |
a810ee82 | 5701 | lra_emit_move (new_reg, original_reg); |
55a2c322 VM |
5702 | new_insns = get_insns (); |
5703 | end_sequence (); | |
5704 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
5705 | { | |
5706 | if (lra_dump_file != NULL) | |
5707 | { | |
5708 | fprintf (lra_dump_file, | |
bc3591eb | 5709 | " Rejecting inheritance %d->%d " |
55a2c322 VM |
5710 | "as it results in 2 or more insns:\n", |
5711 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5712 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
55a2c322 VM |
5713 | fprintf (lra_dump_file, |
5714 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5715 | } | |
5716 | return false; | |
5717 | } | |
ef87312e | 5718 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
55a2c322 VM |
5719 | lra_update_insn_regno_info (insn); |
5720 | if (! def_p) | |
5721 | /* We now have a new usage insn for original regno. */ | |
5722 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
5723 | if (lra_dump_file != NULL) | |
bc3591eb | 5724 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
55a2c322 | 5725 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
8a8330b7 | 5726 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
55a2c322 VM |
5727 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5728 | bitmap_set_bit (&check_only_regs, original_regno); | |
5729 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5730 | if (def_p) | |
cfa434f6 | 5731 | lra_process_new_insns (insn, NULL, new_insns, |
55a2c322 VM |
5732 | "Add original<-inheritance"); |
5733 | else | |
cfa434f6 | 5734 | lra_process_new_insns (insn, new_insns, NULL, |
55a2c322 VM |
5735 | "Add inheritance<-original"); |
5736 | while (next_usage_insns != NULL_RTX) | |
5737 | { | |
5738 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5739 | { | |
5740 | usage_insn = next_usage_insns; | |
5741 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
5742 | next_usage_insns = NULL; | |
5743 | } | |
5744 | else | |
5745 | { | |
5746 | usage_insn = XEXP (next_usage_insns, 0); | |
5747 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5748 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5749 | } | |
33006d53 JJ |
5750 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, |
5751 | DEBUG_INSN_P (usage_insn)); | |
cfa434f6 | 5752 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5753 | if (lra_dump_file != NULL) |
5754 | { | |
96a95ac1 | 5755 | basic_block bb = BLOCK_FOR_INSN (usage_insn); |
55a2c322 VM |
5756 | fprintf (lra_dump_file, |
5757 | " Inheritance reuse change %d->%d (bb%d):\n", | |
5758 | original_regno, REGNO (new_reg), | |
96a95ac1 | 5759 | bb ? bb->index : -1); |
1476d1bd | 5760 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5761 | } |
5762 | } | |
5763 | if (lra_dump_file != NULL) | |
5764 | fprintf (lra_dump_file, | |
5765 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5766 | return true; | |
5767 | } | |
5768 | ||
5769 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
5770 | was assigned to a hard register. */ | |
5771 | static inline bool | |
5772 | need_for_call_save_p (int regno) | |
5773 | { | |
5774 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
a1e6ee38 RS |
5775 | if (usage_insns[regno].calls_num < calls_num) |
5776 | { | |
5777 | unsigned int abis = 0; | |
5778 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) | |
5779 | if (last_call_for_abi[i] > usage_insns[regno].calls_num) | |
5780 | abis |= 1 << i; | |
5781 | gcc_assert (abis); | |
5782 | if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers, | |
5783 | PSEUDO_REGNO_MODE (regno), | |
5784 | reg_renumber[regno])) | |
5785 | return true; | |
5786 | } | |
5787 | return false; | |
55a2c322 VM |
5788 | } |
5789 | ||
1aa95df7 | 5790 | /* Global registers occurring in the current EBB. */ |
55a2c322 VM |
5791 | static bitmap_head ebb_global_regs; |
5792 | ||
5793 | /* Return true if we need a split for hard register REGNO or pseudo | |
5794 | REGNO which was assigned to a hard register. | |
5795 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
5796 | used for reloads since the EBB end. It is an approximation of the | |
5797 | used hard registers in the split range. The exact value would | |
5798 | require expensive calculations. If we were aggressive with | |
5799 | splitting because of the approximation, the split pseudo will save | |
5800 | the same hard register assignment and will be removed in the undo | |
5801 | pass. We still need the approximation because too aggressive | |
5802 | splitting would result in too inaccurate cost calculation in the | |
5803 | assignment pass because of too many generated moves which will be | |
5804 | probably removed in the undo pass. */ | |
5805 | static inline bool | |
5806 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
5807 | { | |
5808 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
5809 | ||
5810 | lra_assert (hard_regno >= 0); | |
5811 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
5812 | /* Don't split eliminable hard registers, otherwise we can | |
5813 | split hard registers like hard frame pointer, which | |
5814 | lives on BB start/end according to DF-infrastructure, | |
5815 | when there is a pseudo assigned to the register and | |
5816 | living in the same BB. */ | |
5817 | && (regno >= FIRST_PSEUDO_REGISTER | |
5818 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
5819 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
e32e4c4a VM |
5820 | /* Don't split call clobbered hard regs living through |
5821 | calls, otherwise we might have a check problem in the | |
5822 | assign sub-pass as in the most cases (exception is a | |
7436a1c6 | 5823 | situation when check_and_force_assignment_correctness_p value is |
e32e4c4a VM |
5824 | true) the assign pass assumes that all pseudos living |
5825 | through calls are assigned to call saved hard regs. */ | |
5826 | && (regno >= FIRST_PSEUDO_REGISTER | |
a1e6ee38 | 5827 | || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno)) |
55a2c322 VM |
5828 | /* We need at least 2 reloads to make pseudo splitting |
5829 | profitable. We should provide hard regno splitting in | |
5830 | any case to solve 1st insn scheduling problem when | |
5831 | moving hard register definition up might result in | |
5832 | impossibility to find hard register for reload pseudo of | |
5833 | small register class. */ | |
5834 | && (usage_insns[regno].reloads_num | |
8e9d68a9 | 5835 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
55a2c322 VM |
5836 | && (regno < FIRST_PSEUDO_REGISTER |
5837 | /* For short living pseudos, spilling + inheritance can | |
5838 | be considered a substitution for splitting. | |
5839 | Therefore we do not splitting for local pseudos. It | |
5840 | decreases also aggressiveness of splitting. The | |
5841 | minimal number of references is chosen taking into | |
5842 | account that for 2 references splitting has no sense | |
5843 | as we can just spill the pseudo. */ | |
5844 | || (regno >= FIRST_PSEUDO_REGISTER | |
5845 | && lra_reg_info[regno].nrefs > 3 | |
5846 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
5847 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
5848 | } | |
5849 | ||
5850 | /* Return class for the split pseudo created from original pseudo with | |
5851 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
5852 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
5853 | results in no secondary memory movements. */ | |
5854 | static enum reg_class | |
5855 | choose_split_class (enum reg_class allocno_class, | |
5856 | int hard_regno ATTRIBUTE_UNUSED, | |
ef4bddc2 | 5857 | machine_mode mode ATTRIBUTE_UNUSED) |
55a2c322 | 5858 | { |
55a2c322 VM |
5859 | int i; |
5860 | enum reg_class cl, best_cl = NO_REGS; | |
ef4dbe49 JR |
5861 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
5862 | = REGNO_REG_CLASS (hard_regno); | |
f4eafc30 | 5863 | |
f15643d4 | 5864 | if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class) |
55a2c322 VM |
5865 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) |
5866 | return allocno_class; | |
5867 | for (i = 0; | |
5868 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
5869 | i++) | |
f15643d4 RS |
5870 | if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class) |
5871 | && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl) | |
55a2c322 VM |
5872 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) |
5873 | && (best_cl == NO_REGS | |
5874 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
5875 | best_cl = cl; | |
5876 | return best_cl; | |
55a2c322 VM |
5877 | } |
5878 | ||
10827a92 VM |
5879 | /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. It only |
5880 | makes sense to call this function if NEW_REGNO is always equal to | |
5881 | ORIGINAL_REGNO. Set up defined_p flag when caller_save_p flag is set up and | |
5882 | CALL_SAVE_P is true. */ | |
8ffa3150 RS |
5883 | |
5884 | static void | |
10827a92 VM |
5885 | lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno, |
5886 | bool call_save_p) | |
8ffa3150 | 5887 | { |
10827a92 VM |
5888 | if (!ira_reg_equiv[original_regno].defined_p |
5889 | && !(call_save_p && ira_reg_equiv[original_regno].caller_save_p)) | |
8ffa3150 RS |
5890 | return; |
5891 | ||
5892 | ira_expand_reg_equiv (); | |
5893 | ira_reg_equiv[new_regno].defined_p = true; | |
5894 | if (ira_reg_equiv[original_regno].memory) | |
5895 | ira_reg_equiv[new_regno].memory | |
5896 | = copy_rtx (ira_reg_equiv[original_regno].memory); | |
5897 | if (ira_reg_equiv[original_regno].constant) | |
5898 | ira_reg_equiv[new_regno].constant | |
5899 | = copy_rtx (ira_reg_equiv[original_regno].constant); | |
5900 | if (ira_reg_equiv[original_regno].invariant) | |
5901 | ira_reg_equiv[new_regno].invariant | |
5902 | = copy_rtx (ira_reg_equiv[original_regno].invariant); | |
5903 | } | |
5904 | ||
55a2c322 VM |
5905 | /* Do split transformations for insn INSN, which defines or uses |
5906 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
5907 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
6027ea4c | 5908 | "insns" field of usage_insns. If TO is not NULL, we don't use |
037586dd VM |
5909 | usage_insns, we put restore insns after TO insn. It is a case when |
5910 | we call it from lra_split_hard_reg_for, outside the inheritance | |
5911 | pass. | |
55a2c322 VM |
5912 | |
5913 | The transformations look like: | |
5914 | ||
5915 | p <- ... p <- ... | |
5916 | ... s <- p (new insn -- save) | |
5917 | ... => | |
5918 | ... p <- s (new insn -- restore) | |
5919 | <- ... p ... <- ... p ... | |
5920 | or | |
5921 | <- ... p ... <- ... p ... | |
5922 | ... s <- p (new insn -- save) | |
5923 | ... => | |
5924 | ... p <- s (new insn -- restore) | |
5925 | <- ... p ... <- ... p ... | |
5926 | ||
5927 | where p is an original pseudo got a hard register or a hard | |
5928 | register and s is a new split pseudo. The save is put before INSN | |
5929 | if BEFORE_P is true. Return true if we succeed in such | |
5930 | transformation. */ | |
5931 | static bool | |
cfa434f6 | 5932 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
6027ea4c | 5933 | rtx next_usage_insns, rtx_insn *to) |
55a2c322 VM |
5934 | { |
5935 | enum reg_class rclass; | |
5936 | rtx original_reg; | |
77bce07c | 5937 | int hard_regno, nregs; |
cfa434f6 DM |
5938 | rtx new_reg, usage_insn; |
5939 | rtx_insn *restore, *save; | |
55a2c322 VM |
5940 | bool after_p; |
5941 | bool call_save_p; | |
3cbf012a | 5942 | machine_mode mode; |
55a2c322 VM |
5943 | |
5944 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
5945 | { | |
5946 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
5947 | hard_regno = original_regno; | |
5948 | call_save_p = false; | |
77bce07c | 5949 | nregs = 1; |
3cbf012a BS |
5950 | mode = lra_reg_info[hard_regno].biggest_mode; |
5951 | machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); | |
4bbd51af | 5952 | /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as |
f99f64f6 VM |
5953 | part of a multi-word register. In that case, just use the reg_rtx |
5954 | mode. Do the same also if the biggest mode was larger than a register | |
5955 | or we can not compare the modes. Otherwise, limit the size to that of | |
9046e0d4 | 5956 | the biggest access in the function or to the natural mode at least. */ |
f99f64f6 VM |
5957 | if (mode == VOIDmode |
5958 | || !ordered_p (GET_MODE_PRECISION (mode), | |
5959 | GET_MODE_PRECISION (reg_rtx_mode)) | |
9046e0d4 VM |
5960 | || paradoxical_subreg_p (mode, reg_rtx_mode) |
5961 | || maybe_gt (GET_MODE_PRECISION (reg_rtx_mode), GET_MODE_PRECISION (mode))) | |
3cbf012a BS |
5962 | { |
5963 | original_reg = regno_reg_rtx[hard_regno]; | |
5964 | mode = reg_rtx_mode; | |
5965 | } | |
5966 | else | |
5967 | original_reg = gen_rtx_REG (mode, hard_regno); | |
55a2c322 VM |
5968 | } |
5969 | else | |
5970 | { | |
3cbf012a | 5971 | mode = PSEUDO_REGNO_MODE (original_regno); |
55a2c322 | 5972 | hard_regno = reg_renumber[original_regno]; |
ad474626 | 5973 | nregs = hard_regno_nregs (hard_regno, mode); |
55a2c322 VM |
5974 | rclass = lra_get_allocno_class (original_regno); |
5975 | original_reg = regno_reg_rtx[original_regno]; | |
5976 | call_save_p = need_for_call_save_p (original_regno); | |
5977 | } | |
55a2c322 VM |
5978 | lra_assert (hard_regno >= 0); |
5979 | if (lra_dump_file != NULL) | |
5980 | fprintf (lra_dump_file, | |
5981 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
3cbf012a | 5982 | |
55a2c322 VM |
5983 | if (call_save_p) |
5984 | { | |
cb1cca12 | 5985 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
ad474626 | 5986 | hard_regno_nregs (hard_regno, mode), |
cb1cca12 | 5987 | mode); |
85419ac5 | 5988 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, NULL, "save"); |
55a2c322 VM |
5989 | } |
5990 | else | |
5991 | { | |
3cbf012a | 5992 | rclass = choose_split_class (rclass, hard_regno, mode); |
55a2c322 VM |
5993 | if (rclass == NO_REGS) |
5994 | { | |
5995 | if (lra_dump_file != NULL) | |
5996 | { | |
5997 | fprintf (lra_dump_file, | |
5998 | " Rejecting split of %d(%s): " | |
5999 | "no good reg class for %d(%s)\n", | |
6000 | original_regno, | |
6001 | reg_class_names[lra_get_allocno_class (original_regno)], | |
6002 | hard_regno, | |
6003 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
6004 | fprintf | |
6005 | (lra_dump_file, | |
6006 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
6007 | } | |
6008 | return false; | |
6009 | } | |
1b51df94 MF |
6010 | /* Split_if_necessary can split hard registers used as part of a |
6011 | multi-register mode but splits each register individually. The | |
6012 | mode used for each independent register may not be supported | |
6013 | so reject the split. Splitting the wider mode should theoretically | |
6014 | be possible but is not implemented. */ | |
f939c3e6 | 6015 | if (!targetm.hard_regno_mode_ok (hard_regno, mode)) |
1b51df94 MF |
6016 | { |
6017 | if (lra_dump_file != NULL) | |
6018 | { | |
6019 | fprintf (lra_dump_file, | |
6020 | " Rejecting split of %d(%s): unsuitable mode %s\n", | |
6021 | original_regno, | |
6022 | reg_class_names[lra_get_allocno_class (original_regno)], | |
6023 | GET_MODE_NAME (mode)); | |
6024 | fprintf | |
6025 | (lra_dump_file, | |
6026 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
6027 | } | |
6028 | return false; | |
6029 | } | |
85419ac5 | 6030 | new_reg = lra_create_new_reg (mode, original_reg, rclass, NULL, "split"); |
55a2c322 VM |
6031 | reg_renumber[REGNO (new_reg)] = hard_regno; |
6032 | } | |
8ffa3150 | 6033 | int new_regno = REGNO (new_reg); |
55a2c322 | 6034 | save = emit_spill_move (true, new_reg, original_reg); |
c61fe0cc | 6035 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
55a2c322 | 6036 | { |
55a2c322 VM |
6037 | if (lra_dump_file != NULL) |
6038 | { | |
6039 | fprintf | |
6040 | (lra_dump_file, | |
c61fe0cc | 6041 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
8ffa3150 | 6042 | original_regno, new_regno); |
dc01c3d1 | 6043 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
55a2c322 VM |
6044 | fprintf (lra_dump_file, |
6045 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
6046 | } | |
6047 | return false; | |
6048 | } | |
6049 | restore = emit_spill_move (false, new_reg, original_reg); | |
c61fe0cc | 6050 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
55a2c322 | 6051 | { |
55a2c322 VM |
6052 | if (lra_dump_file != NULL) |
6053 | { | |
6054 | fprintf (lra_dump_file, | |
6055 | " Rejecting split %d->%d " | |
c61fe0cc | 6056 | "resulting in > 2 restore insns:\n", |
8ffa3150 | 6057 | original_regno, new_regno); |
dc01c3d1 | 6058 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
55a2c322 VM |
6059 | fprintf (lra_dump_file, |
6060 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
6061 | } | |
6062 | return false; | |
6063 | } | |
8ffa3150 RS |
6064 | /* Transfer equivalence information to the spill register, so that |
6065 | if we fail to allocate the spill register, we have the option of | |
6066 | rematerializing the original value instead of spilling to the stack. */ | |
6067 | if (!HARD_REGISTER_NUM_P (original_regno) | |
6068 | && mode == PSEUDO_REGNO_MODE (original_regno)) | |
10827a92 | 6069 | lra_copy_reg_equiv (new_regno, original_regno, call_save_p); |
8ffa3150 | 6070 | lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; |
8ffa3150 | 6071 | bitmap_set_bit (&lra_split_regs, new_regno); |
6027ea4c | 6072 | if (to != NULL) |
55a2c322 | 6073 | { |
037586dd | 6074 | lra_assert (next_usage_insns == NULL); |
6027ea4c VM |
6075 | usage_insn = to; |
6076 | after_p = TRUE; | |
6077 | } | |
6078 | else | |
6079 | { | |
037586dd VM |
6080 | /* We need check_only_regs only inside the inheritance pass. */ |
6081 | bitmap_set_bit (&check_only_regs, new_regno); | |
6082 | bitmap_set_bit (&check_only_regs, original_regno); | |
6027ea4c VM |
6083 | after_p = usage_insns[original_regno].after_p; |
6084 | for (;;) | |
b3231b65 | 6085 | { |
6027ea4c VM |
6086 | if (GET_CODE (next_usage_insns) != INSN_LIST) |
6087 | { | |
6088 | usage_insn = next_usage_insns; | |
6089 | break; | |
6090 | } | |
6091 | usage_insn = XEXP (next_usage_insns, 0); | |
6092 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
6093 | next_usage_insns = XEXP (next_usage_insns, 1); | |
6094 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, | |
6095 | true); | |
6096 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); | |
6097 | if (lra_dump_file != NULL) | |
6098 | { | |
6099 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
6100 | original_regno, new_regno); | |
6101 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); | |
6102 | } | |
55a2c322 VM |
6103 | } |
6104 | } | |
6105 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
6106 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
cfa434f6 DM |
6107 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
6108 | after_p ? NULL : restore, | |
6109 | after_p ? restore : NULL, | |
55a2c322 VM |
6110 | call_save_p |
6111 | ? "Add reg<-save" : "Add reg<-split"); | |
cfa434f6 DM |
6112 | lra_process_new_insns (insn, before_p ? save : NULL, |
6113 | before_p ? NULL : save, | |
55a2c322 VM |
6114 | call_save_p |
6115 | ? "Add save<-reg" : "Add split<-reg"); | |
d8e5fff6 | 6116 | if (nregs > 1 || original_regno < FIRST_PSEUDO_REGISTER) |
77bce07c VM |
6117 | /* If we are trying to split multi-register. We should check |
6118 | conflicts on the next assignment sub-pass. IRA can allocate on | |
6119 | sub-register levels, LRA do this on pseudos level right now and | |
6120 | this discrepancy may create allocation conflicts after | |
d8e5fff6 VM |
6121 | splitting. |
6122 | ||
6123 | If we are trying to split hard register we should also check conflicts | |
6124 | as such splitting can create artificial conflict of the hard register | |
6125 | with another pseudo because of simplified conflict calculation in | |
6126 | LRA. */ | |
7436a1c6 | 6127 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
6128 | if (lra_dump_file != NULL) |
6129 | fprintf (lra_dump_file, | |
6130 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
6131 | return true; | |
6132 | } | |
6133 | ||
6027ea4c VM |
6134 | /* Split a hard reg for reload pseudo REGNO having RCLASS and living |
6135 | in the range [FROM, TO]. Return true if did a split. Otherwise, | |
6136 | return false. */ | |
6137 | bool | |
6138 | spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to) | |
6139 | { | |
6140 | int i, hard_regno; | |
6141 | int rclass_size; | |
6142 | rtx_insn *insn; | |
7293e3f5 VM |
6143 | unsigned int uid; |
6144 | bitmap_iterator bi; | |
6145 | HARD_REG_SET ignore; | |
6027ea4c VM |
6146 | |
6147 | lra_assert (from != NULL && to != NULL); | |
db69f666 | 6148 | ignore = lra_no_alloc_regs; |
7293e3f5 VM |
6149 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
6150 | { | |
6151 | lra_insn_recog_data_t id = lra_insn_recog_data[uid]; | |
6152 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
6153 | struct lra_insn_reg *reg; | |
6154 | ||
6155 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
65e87462 | 6156 | if (reg->regno < FIRST_PSEUDO_REGISTER) |
7293e3f5 VM |
6157 | SET_HARD_REG_BIT (ignore, reg->regno); |
6158 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
6159 | SET_HARD_REG_BIT (ignore, reg->regno); | |
6160 | } | |
6027ea4c VM |
6161 | rclass_size = ira_class_hard_regs_num[rclass]; |
6162 | for (i = 0; i < rclass_size; i++) | |
6163 | { | |
6164 | hard_regno = ira_class_hard_regs[rclass][i]; | |
7293e3f5 VM |
6165 | if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) |
6166 | || TEST_HARD_REG_BIT (ignore, hard_regno)) | |
6027ea4c VM |
6167 | continue; |
6168 | for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) | |
dc843a85 | 6169 | { |
3664a0f1 | 6170 | struct lra_static_insn_data *static_id; |
dc843a85 IL |
6171 | struct lra_insn_reg *reg; |
6172 | ||
3664a0f1 IL |
6173 | if (!INSN_P (insn)) |
6174 | continue; | |
6175 | if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, | |
6176 | INSN_UID (insn))) | |
dc843a85 | 6177 | break; |
3664a0f1 | 6178 | static_id = lra_get_insn_recog_data (insn)->insn_static_data; |
dc843a85 IL |
6179 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) |
6180 | if (reg->regno == hard_regno) | |
6181 | break; | |
6182 | if (reg != NULL) | |
6183 | break; | |
6184 | } | |
6027ea4c VM |
6185 | if (insn != NEXT_INSN (to)) |
6186 | continue; | |
6187 | if (split_reg (TRUE, hard_regno, from, NULL, to)) | |
6188 | return true; | |
6189 | } | |
6190 | return false; | |
6191 | } | |
6192 | ||
55a2c322 VM |
6193 | /* Recognize that we need a split transformation for insn INSN, which |
6194 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
6195 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
6196 | hard registers which might be used for reloads since the EBB end. | |
6197 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
6198 | uid before starting INSN processing. Return true if we succeed in | |
6199 | such transformation. */ | |
6200 | static bool | |
ef4bddc2 | 6201 | split_if_necessary (int regno, machine_mode mode, |
55a2c322 | 6202 | HARD_REG_SET potential_reload_hard_regs, |
cfa434f6 | 6203 | bool before_p, rtx_insn *insn, int max_uid) |
55a2c322 VM |
6204 | { |
6205 | bool res = false; | |
6206 | int i, nregs = 1; | |
6207 | rtx next_usage_insns; | |
6208 | ||
6209 | if (regno < FIRST_PSEUDO_REGISTER) | |
ad474626 | 6210 | nregs = hard_regno_nregs (regno, mode); |
55a2c322 VM |
6211 | for (i = 0; i < nregs; i++) |
6212 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
6213 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
6214 | /* To avoid processing the register twice or more. */ | |
6215 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
6216 | && INSN_UID (next_usage_insns) < max_uid) | |
6217 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
6218 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
6219 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
6027ea4c | 6220 | && split_reg (before_p, regno + i, insn, next_usage_insns, NULL)) |
55a2c322 VM |
6221 | res = true; |
6222 | return res; | |
6223 | } | |
6224 | ||
8a8330b7 VM |
6225 | /* Return TRUE if rtx X is considered as an invariant for |
6226 | inheritance. */ | |
6227 | static bool | |
6228 | invariant_p (const_rtx x) | |
6229 | { | |
6230 | machine_mode mode; | |
6231 | const char *fmt; | |
6232 | enum rtx_code code; | |
6233 | int i, j; | |
6234 | ||
850b8aa3 SB |
6235 | if (side_effects_p (x)) |
6236 | return false; | |
6237 | ||
8a8330b7 VM |
6238 | code = GET_CODE (x); |
6239 | mode = GET_MODE (x); | |
6240 | if (code == SUBREG) | |
6241 | { | |
6242 | x = SUBREG_REG (x); | |
6243 | code = GET_CODE (x); | |
bd5a2c67 | 6244 | mode = wider_subreg_mode (mode, GET_MODE (x)); |
8a8330b7 VM |
6245 | } |
6246 | ||
6247 | if (MEM_P (x)) | |
6248 | return false; | |
6249 | ||
6250 | if (REG_P (x)) | |
6251 | { | |
6252 | int i, nregs, regno = REGNO (x); | |
6253 | ||
6254 | if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM | |
6255 | || TEST_HARD_REG_BIT (eliminable_regset, regno) | |
6256 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
6257 | return false; | |
ad474626 | 6258 | nregs = hard_regno_nregs (regno, mode); |
8a8330b7 VM |
6259 | for (i = 0; i < nregs; i++) |
6260 | if (! fixed_regs[regno + i] | |
6261 | /* A hard register may be clobbered in the current insn | |
6262 | but we can ignore this case because if the hard | |
6263 | register is used it should be set somewhere after the | |
6264 | clobber. */ | |
6265 | || bitmap_bit_p (&invalid_invariant_regs, regno + i)) | |
6266 | return false; | |
6267 | } | |
6268 | fmt = GET_RTX_FORMAT (code); | |
6269 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6270 | { | |
6271 | if (fmt[i] == 'e') | |
6272 | { | |
6273 | if (! invariant_p (XEXP (x, i))) | |
6274 | return false; | |
6275 | } | |
6276 | else if (fmt[i] == 'E') | |
6277 | { | |
6278 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6279 | if (! invariant_p (XVECEXP (x, i, j))) | |
6280 | return false; | |
6281 | } | |
6282 | } | |
6283 | return true; | |
6284 | } | |
6285 | ||
6286 | /* We have 'dest_reg <- invariant'. Let us try to make an invariant | |
6287 | inheritance transformation (using dest_reg instead invariant in a | |
6288 | subsequent insn). */ | |
6289 | static bool | |
6290 | process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) | |
6291 | { | |
6292 | invariant_ptr_t invariant_ptr; | |
6293 | rtx_insn *insn, *new_insns; | |
6294 | rtx insn_set, insn_reg, new_reg; | |
6295 | int insn_regno; | |
6296 | bool succ_p = false; | |
6297 | int dst_regno = REGNO (dst_reg); | |
b8506a8a | 6298 | machine_mode dst_mode = GET_MODE (dst_reg); |
8a8330b7 VM |
6299 | enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; |
6300 | ||
6301 | invariant_ptr = insert_invariant (invariant_rtx); | |
6302 | if ((insn = invariant_ptr->insn) != NULL_RTX) | |
6303 | { | |
6304 | /* We have a subsequent insn using the invariant. */ | |
6305 | insn_set = single_set (insn); | |
6306 | lra_assert (insn_set != NULL); | |
6307 | insn_reg = SET_DEST (insn_set); | |
6308 | lra_assert (REG_P (insn_reg)); | |
6309 | insn_regno = REGNO (insn_reg); | |
6310 | insn_reg_cl = lra_get_allocno_class (insn_regno); | |
6311 | ||
6312 | if (dst_mode == GET_MODE (insn_reg) | |
6313 | /* We should consider only result move reg insns which are | |
6314 | cheap. */ | |
6315 | && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 | |
6316 | && targetm.register_move_cost (dst_mode, cl, cl) == 2) | |
6317 | { | |
6318 | if (lra_dump_file != NULL) | |
6319 | fprintf (lra_dump_file, | |
6320 | " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); | |
85419ac5 VM |
6321 | new_reg = lra_create_new_reg (dst_mode, dst_reg, cl, NULL, |
6322 | "invariant inheritance"); | |
8a8330b7 VM |
6323 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); |
6324 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
b10d44ef | 6325 | lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); |
8a8330b7 VM |
6326 | start_sequence (); |
6327 | lra_emit_move (new_reg, dst_reg); | |
6328 | new_insns = get_insns (); | |
6329 | end_sequence (); | |
6330 | lra_process_new_insns (curr_insn, NULL, new_insns, | |
6331 | "Add invariant inheritance<-original"); | |
6332 | start_sequence (); | |
6333 | lra_emit_move (SET_DEST (insn_set), new_reg); | |
6334 | new_insns = get_insns (); | |
6335 | end_sequence (); | |
6336 | lra_process_new_insns (insn, NULL, new_insns, | |
6337 | "Changing reload<-inheritance"); | |
6338 | lra_set_insn_deleted (insn); | |
6339 | succ_p = true; | |
6340 | if (lra_dump_file != NULL) | |
6341 | { | |
6342 | fprintf (lra_dump_file, | |
6343 | " Invariant inheritance reuse change %d (bb%d):\n", | |
6344 | REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); | |
6345 | dump_insn_slim (lra_dump_file, insn); | |
6346 | fprintf (lra_dump_file, | |
6347 | " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); | |
6348 | } | |
6349 | } | |
6350 | } | |
6351 | invariant_ptr->insn = curr_insn; | |
6352 | return succ_p; | |
6353 | } | |
6354 | ||
55a2c322 VM |
6355 | /* Check only registers living at the current program point in the |
6356 | current EBB. */ | |
6357 | static bitmap_head live_regs; | |
6358 | ||
6359 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
6360 | inheritance/split transformation. The function removes dead moves | |
6361 | too. */ | |
6362 | static void | |
cfa434f6 | 6363 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
6364 | { |
6365 | unsigned int j; | |
8e9d68a9 | 6366 | int i, regno; |
55a2c322 | 6367 | bool live_p; |
cfa434f6 DM |
6368 | rtx_insn *prev_insn; |
6369 | rtx set; | |
55a2c322 VM |
6370 | bool remove_p; |
6371 | basic_block last_bb, prev_bb, curr_bb; | |
6372 | bitmap_iterator bi; | |
6373 | struct lra_insn_reg *reg; | |
6374 | edge e; | |
6375 | edge_iterator ei; | |
6376 | ||
f4eafc30 | 6377 | last_bb = BLOCK_FOR_INSN (tail); |
55a2c322 VM |
6378 | prev_bb = NULL; |
6379 | for (curr_insn = tail; | |
6380 | curr_insn != PREV_INSN (head); | |
6381 | curr_insn = prev_insn) | |
6382 | { | |
6383 | prev_insn = PREV_INSN (curr_insn); | |
911598e3 VM |
6384 | /* We need to process empty blocks too. They contain |
6385 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
6386 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
6387 | continue; | |
55a2c322 VM |
6388 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
6389 | if (curr_bb != prev_bb) | |
6390 | { | |
6391 | if (prev_bb != NULL) | |
6392 | { | |
6393 | /* Update df_get_live_in (prev_bb): */ | |
6394 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6395 | if (bitmap_bit_p (&live_regs, j)) | |
6396 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
6397 | else | |
6398 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
6399 | } | |
6400 | if (curr_bb != last_bb) | |
6401 | { | |
6402 | /* Update df_get_live_out (curr_bb): */ | |
6403 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6404 | { | |
6405 | live_p = bitmap_bit_p (&live_regs, j); | |
6406 | if (! live_p) | |
6407 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
6408 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
6409 | { | |
6410 | live_p = true; | |
6411 | break; | |
6412 | } | |
6413 | if (live_p) | |
6414 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
6415 | else | |
6416 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
6417 | } | |
6418 | } | |
6419 | prev_bb = curr_bb; | |
6420 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
6421 | } | |
44b94bdb | 6422 | if (! NONDEBUG_INSN_P (curr_insn)) |
55a2c322 VM |
6423 | continue; |
6424 | curr_id = lra_get_insn_recog_data (curr_insn); | |
8e9d68a9 | 6425 | curr_static_id = curr_id->insn_static_data; |
55a2c322 | 6426 | remove_p = false; |
53250f44 BS |
6427 | if ((set = single_set (curr_insn)) != NULL_RTX |
6428 | && REG_P (SET_DEST (set)) | |
55a2c322 | 6429 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER |
53250f44 | 6430 | && SET_DEST (set) != pic_offset_table_rtx |
55a2c322 VM |
6431 | && bitmap_bit_p (&check_only_regs, regno) |
6432 | && ! bitmap_bit_p (&live_regs, regno)) | |
6433 | remove_p = true; | |
6434 | /* See which defined values die here. */ | |
6435 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6436 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6437 | bitmap_clear_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6438 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6439 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6440 | bitmap_clear_bit (&live_regs, reg->regno); | |
9d86e84e VM |
6441 | if (curr_id->arg_hard_regs != NULL) |
6442 | /* Make clobbered argument hard registers die. */ | |
6443 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6444 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6445 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
55a2c322 VM |
6446 | /* Mark each used value as live. */ |
6447 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
d89ae27c | 6448 | if (reg->type != OP_OUT |
55a2c322 VM |
6449 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
6450 | bitmap_set_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6451 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6452 | if (reg->type != OP_OUT | |
6453 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
6454 | bitmap_set_bit (&live_regs, reg->regno); | |
6455 | if (curr_id->arg_hard_regs != NULL) | |
9d86e84e | 6456 | /* Make used argument hard registers live. */ |
8e9d68a9 | 6457 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
9d86e84e VM |
6458 | if (regno < FIRST_PSEUDO_REGISTER |
6459 | && bitmap_bit_p (&check_only_regs, regno)) | |
8e9d68a9 | 6460 | bitmap_set_bit (&live_regs, regno); |
55a2c322 VM |
6461 | /* It is quite important to remove dead move insns because it |
6462 | means removing dead store. We don't need to process them for | |
6463 | constraints. */ | |
6464 | if (remove_p) | |
6465 | { | |
6466 | if (lra_dump_file != NULL) | |
6467 | { | |
6468 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
cfbeaedf | 6469 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6470 | } |
6471 | lra_set_insn_deleted (curr_insn); | |
6472 | } | |
6473 | } | |
6474 | } | |
6475 | ||
6476 | /* The structure describes info to do an inheritance for the current | |
6477 | insn. We need to collect such info first before doing the | |
6478 | transformations because the transformations change the insn | |
6479 | internal representation. */ | |
6480 | struct to_inherit | |
6481 | { | |
6482 | /* Original regno. */ | |
6483 | int regno; | |
6484 | /* Subsequent insns which can inherit original reg value. */ | |
6485 | rtx insns; | |
6486 | }; | |
6487 | ||
6488 | /* Array containing all info for doing inheritance from the current | |
6489 | insn. */ | |
6490 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
6491 | ||
6492 | /* Number elements in the previous array. */ | |
6493 | static int to_inherit_num; | |
6494 | ||
6495 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
6496 | structure to_inherit. */ | |
6497 | static void | |
6498 | add_to_inherit (int regno, rtx insns) | |
6499 | { | |
6500 | int i; | |
6501 | ||
6502 | for (i = 0; i < to_inherit_num; i++) | |
6503 | if (to_inherit[i].regno == regno) | |
6504 | return; | |
6505 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
6506 | to_inherit[to_inherit_num].regno = regno; | |
6507 | to_inherit[to_inherit_num++].insns = insns; | |
6508 | } | |
6509 | ||
6510 | /* Return the last non-debug insn in basic block BB, or the block begin | |
6511 | note if none. */ | |
cfa434f6 | 6512 | static rtx_insn * |
55a2c322 VM |
6513 | get_last_insertion_point (basic_block bb) |
6514 | { | |
cfa434f6 | 6515 | rtx_insn *insn; |
55a2c322 VM |
6516 | |
6517 | FOR_BB_INSNS_REVERSE (bb, insn) | |
6518 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
6519 | return insn; | |
6520 | gcc_unreachable (); | |
6521 | } | |
6522 | ||
6523 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
6524 | TO) or by registers set up in a jump insn in BB FROM. */ | |
6525 | static void | |
6526 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
6527 | { | |
cfa434f6 | 6528 | rtx_insn *last; |
55a2c322 VM |
6529 | struct lra_insn_reg *reg; |
6530 | edge e; | |
6531 | edge_iterator ei; | |
6532 | ||
6533 | lra_assert (to != NULL); | |
6534 | bitmap_clear (res); | |
6535 | FOR_EACH_EDGE (e, ei, from->succs) | |
6536 | if (e->dest != to) | |
6537 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
6538 | last = get_last_insertion_point (from); | |
6539 | if (! JUMP_P (last)) | |
6540 | return; | |
6541 | curr_id = lra_get_insn_recog_data (last); | |
6542 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6543 | if (reg->type != OP_IN) | |
6544 | bitmap_set_bit (res, reg->regno); | |
6545 | } | |
f4eafc30 | 6546 | |
55a2c322 VM |
6547 | /* Used as a temporary results of some bitmap calculations. */ |
6548 | static bitmap_head temp_bitmap; | |
6549 | ||
8e9d68a9 VM |
6550 | /* We split for reloads of small class of hard regs. The following |
6551 | defines how many hard regs the class should have to be qualified as | |
6552 | small. The code is mostly oriented to x86/x86-64 architecture | |
6553 | where some insns need to use only specific register or pair of | |
6554 | registers and these register can live in RTL explicitly, e.g. for | |
6555 | parameter passing. */ | |
6556 | static const int max_small_class_regs_num = 2; | |
6557 | ||
55a2c322 VM |
6558 | /* Do inheritance/split transformations in EBB starting with HEAD and |
6559 | finishing on TAIL. We process EBB insns in the reverse order. | |
6560 | Return true if we did any inheritance/split transformation in the | |
6561 | EBB. | |
6562 | ||
6563 | We should avoid excessive splitting which results in worse code | |
6564 | because of inaccurate cost calculations for spilling new split | |
6565 | pseudos in such case. To achieve this we do splitting only if | |
6566 | register pressure is high in given basic block and there are reload | |
6567 | pseudos requiring hard registers. We could do more register | |
6568 | pressure calculations at any given program point to avoid necessary | |
6569 | splitting even more but it is to expensive and the current approach | |
6570 | works well enough. */ | |
6571 | static bool | |
cfa434f6 | 6572 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
6573 | { |
6574 | int i, src_regno, dst_regno, nregs; | |
df2980be | 6575 | bool change_p, succ_p, update_reloads_num_p; |
cfa434f6 | 6576 | rtx_insn *prev_insn, *last_insn; |
8a8330b7 | 6577 | rtx next_usage_insns, curr_set; |
55a2c322 VM |
6578 | enum reg_class cl; |
6579 | struct lra_insn_reg *reg; | |
6580 | basic_block last_processed_bb, curr_bb = NULL; | |
6581 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
6582 | bitmap to_process; | |
6583 | unsigned int j; | |
6584 | bitmap_iterator bi; | |
6585 | bool head_p, after_p; | |
6586 | ||
6587 | change_p = false; | |
6588 | curr_usage_insns_check++; | |
8a8330b7 | 6589 | clear_invariants (); |
55a2c322 | 6590 | reloads_num = calls_num = 0; |
a1e6ee38 RS |
6591 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) |
6592 | last_call_for_abi[i] = 0; | |
6593 | CLEAR_HARD_REG_SET (full_and_partial_call_clobbers); | |
55a2c322 | 6594 | bitmap_clear (&check_only_regs); |
8a8330b7 | 6595 | bitmap_clear (&invalid_invariant_regs); |
55a2c322 VM |
6596 | last_processed_bb = NULL; |
6597 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
44942965 | 6598 | live_hard_regs = eliminable_regset | lra_no_alloc_regs; |
55a2c322 VM |
6599 | /* We don't process new insns generated in the loop. */ |
6600 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
6601 | { | |
6602 | prev_insn = PREV_INSN (curr_insn); | |
6603 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
6604 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
6605 | if (last_processed_bb != curr_bb) | |
6606 | { | |
6607 | /* We are at the end of BB. Add qualified living | |
6608 | pseudos for potential splitting. */ | |
6609 | to_process = df_get_live_out (curr_bb); | |
6610 | if (last_processed_bb != NULL) | |
f4eafc30 | 6611 | { |
55a2c322 VM |
6612 | /* We are somewhere in the middle of EBB. */ |
6613 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
6614 | &temp_bitmap); | |
6615 | to_process = &temp_bitmap; | |
6616 | } | |
6617 | last_processed_bb = curr_bb; | |
6618 | last_insn = get_last_insertion_point (curr_bb); | |
6619 | after_p = (! JUMP_P (last_insn) | |
6620 | && (! CALL_P (last_insn) | |
6621 | || (find_reg_note (last_insn, | |
6622 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
6623 | && ! SIBLING_CALL_P (last_insn)))); | |
55a2c322 VM |
6624 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
6625 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6626 | { | |
6627 | if ((int) j >= lra_constraint_new_regno_start) | |
6628 | break; | |
6629 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6630 | { | |
6631 | if (j < FIRST_PSEUDO_REGISTER) | |
6632 | SET_HARD_REG_BIT (live_hard_regs, j); | |
6633 | else | |
6634 | add_to_hard_reg_set (&live_hard_regs, | |
6635 | PSEUDO_REGNO_MODE (j), | |
6636 | reg_renumber[j]); | |
6637 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
6638 | } | |
6639 | } | |
6640 | } | |
6641 | src_regno = dst_regno = -1; | |
8a8330b7 VM |
6642 | curr_set = single_set (curr_insn); |
6643 | if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) | |
6644 | dst_regno = REGNO (SET_DEST (curr_set)); | |
6645 | if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) | |
6646 | src_regno = REGNO (SET_SRC (curr_set)); | |
df2980be | 6647 | update_reloads_num_p = true; |
55a2c322 VM |
6648 | if (src_regno < lra_constraint_new_regno_start |
6649 | && src_regno >= FIRST_PSEUDO_REGISTER | |
6650 | && reg_renumber[src_regno] < 0 | |
6651 | && dst_regno >= lra_constraint_new_regno_start | |
6652 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
6653 | { | |
6654 | /* 'reload_pseudo <- original_pseudo'. */ | |
8e9d68a9 VM |
6655 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6656 | reloads_num++; | |
df2980be | 6657 | update_reloads_num_p = false; |
55a2c322 VM |
6658 | succ_p = false; |
6659 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6660 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
6661 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
6662 | curr_insn, next_usage_insns); | |
6663 | if (succ_p) | |
6664 | change_p = true; | |
6665 | else | |
6666 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6667 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6668 | potential_reload_hard_regs |= reg_class_contents[cl]; |
55a2c322 | 6669 | } |
8a8330b7 VM |
6670 | else if (src_regno < 0 |
6671 | && dst_regno >= lra_constraint_new_regno_start | |
6672 | && invariant_p (SET_SRC (curr_set)) | |
6673 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS | |
f7abdf36 VM |
6674 | && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) |
6675 | && ! bitmap_bit_p (&invalid_invariant_regs, | |
6676 | ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) | |
8a8330b7 VM |
6677 | { |
6678 | /* 'reload_pseudo <- invariant'. */ | |
6679 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) | |
6680 | reloads_num++; | |
6681 | update_reloads_num_p = false; | |
6682 | if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) | |
6683 | change_p = true; | |
6684 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6685 | potential_reload_hard_regs |= reg_class_contents[cl]; |
8a8330b7 | 6686 | } |
55a2c322 VM |
6687 | else if (src_regno >= lra_constraint_new_regno_start |
6688 | && dst_regno < lra_constraint_new_regno_start | |
6689 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
6690 | && reg_renumber[dst_regno] < 0 | |
6691 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
6692 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6693 | && (next_usage_insns | |
6694 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6695 | { | |
8e9d68a9 VM |
6696 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6697 | reloads_num++; | |
df2980be | 6698 | update_reloads_num_p = false; |
55a2c322 VM |
6699 | /* 'original_pseudo <- reload_pseudo'. */ |
6700 | if (! JUMP_P (curr_insn) | |
6701 | && inherit_reload_reg (true, dst_regno, cl, | |
6702 | curr_insn, next_usage_insns)) | |
6703 | change_p = true; | |
6704 | /* Invalidate. */ | |
6705 | usage_insns[dst_regno].check = 0; | |
6706 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6707 | potential_reload_hard_regs |= reg_class_contents[cl]; |
55a2c322 VM |
6708 | } |
6709 | else if (INSN_P (curr_insn)) | |
6710 | { | |
2f259720 | 6711 | int iter; |
55a2c322 VM |
6712 | int max_uid = get_max_uid (); |
6713 | ||
6714 | curr_id = lra_get_insn_recog_data (curr_insn); | |
2f259720 | 6715 | curr_static_id = curr_id->insn_static_data; |
55a2c322 VM |
6716 | to_inherit_num = 0; |
6717 | /* Process insn definitions. */ | |
2f259720 VM |
6718 | for (iter = 0; iter < 2; iter++) |
6719 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6720 | reg != NULL; | |
6721 | reg = reg->next) | |
6722 | if (reg->type != OP_IN | |
6723 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
6724 | { | |
6725 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
6726 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
6727 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6728 | && (next_usage_insns | |
6729 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6730 | { | |
6731 | struct lra_insn_reg *r; | |
6732 | ||
6733 | for (r = curr_id->regs; r != NULL; r = r->next) | |
6734 | if (r->type != OP_OUT && r->regno == dst_regno) | |
6735 | break; | |
6736 | /* Don't do inheritance if the pseudo is also | |
6737 | used in the insn. */ | |
6738 | if (r == NULL) | |
67914693 | 6739 | /* We cannot do inheritance right now |
2f259720 VM |
6740 | because the current insn reg info (chain |
6741 | regs) can change after that. */ | |
6742 | add_to_inherit (dst_regno, next_usage_insns); | |
6743 | } | |
67914693 | 6744 | /* We cannot process one reg twice here because of |
2f259720 VM |
6745 | usage_insns invalidation. */ |
6746 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
6747 | || reg_renumber[dst_regno] >= 0) | |
e32e4c4a | 6748 | && ! reg->subreg_p && reg->type != OP_IN) |
2f259720 VM |
6749 | { |
6750 | HARD_REG_SET s; | |
6751 | ||
6752 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
6753 | potential_reload_hard_regs, | |
6754 | false, curr_insn, max_uid)) | |
6755 | change_p = true; | |
6756 | CLEAR_HARD_REG_SET (s); | |
6757 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
6758 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
6759 | else | |
6760 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
6761 | reg_renumber[dst_regno]); | |
d15e5131 RS |
6762 | live_hard_regs &= ~s; |
6763 | potential_reload_hard_regs &= ~s; | |
2f259720 VM |
6764 | } |
6765 | /* We should invalidate potential inheritance or | |
6766 | splitting for the current insn usages to the next | |
6767 | usage insns (see code below) as the output pseudo | |
6768 | prevents this. */ | |
6769 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
6770 | && reg_renumber[dst_regno] < 0) | |
6771 | || (reg->type == OP_OUT && ! reg->subreg_p | |
6772 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
6773 | || reg_renumber[dst_regno] >= 0))) | |
6774 | { | |
6775 | /* Invalidate and mark definitions. */ | |
6776 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6777 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
6778 | else | |
6779 | { | |
ad474626 RS |
6780 | nregs = hard_regno_nregs (dst_regno, |
6781 | reg->biggest_mode); | |
2f259720 VM |
6782 | for (i = 0; i < nregs; i++) |
6783 | usage_insns[dst_regno + i].check | |
6784 | = -(int) INSN_UID (curr_insn); | |
6785 | } | |
6786 | } | |
6787 | } | |
9d86e84e VM |
6788 | /* Process clobbered call regs. */ |
6789 | if (curr_id->arg_hard_regs != NULL) | |
6790 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6791 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6792 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
6793 | = -(int) INSN_UID (curr_insn); | |
55a2c322 VM |
6794 | if (! JUMP_P (curr_insn)) |
6795 | for (i = 0; i < to_inherit_num; i++) | |
6796 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
6797 | ALL_REGS, curr_insn, | |
6798 | to_inherit[i].insns)) | |
6799 | change_p = true; | |
6800 | if (CALL_P (curr_insn)) | |
6801 | { | |
cfa434f6 DM |
6802 | rtx cheap, pat, dest; |
6803 | rtx_insn *restore; | |
55a2c322 VM |
6804 | int regno, hard_regno; |
6805 | ||
6806 | calls_num++; | |
a1e6ee38 RS |
6807 | function_abi callee_abi = insn_callee_abi (curr_insn); |
6808 | last_call_for_abi[callee_abi.id ()] = calls_num; | |
6809 | full_and_partial_call_clobbers | |
6810 | |= callee_abi.full_and_partial_reg_clobbers (); | |
55a2c322 VM |
6811 | if ((cheap = find_reg_note (curr_insn, |
6812 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
6813 | && ((cheap = XEXP (cheap, 0)), true) | |
6814 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
6815 | && (hard_regno = reg_renumber[regno]) >= 0 | |
851dac7c | 6816 | && usage_insns[regno].check == curr_usage_insns_check |
55a2c322 VM |
6817 | /* If there are pending saves/restores, the |
6818 | optimization is not worth. */ | |
6819 | && usage_insns[regno].calls_num == calls_num - 1 | |
a1e6ee38 | 6820 | && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno)) |
55a2c322 VM |
6821 | { |
6822 | /* Restore the pseudo from the call result as | |
6823 | REG_RETURNED note says that the pseudo value is | |
6824 | in the call result and the pseudo is an argument | |
6825 | of the call. */ | |
6826 | pat = PATTERN (curr_insn); | |
6827 | if (GET_CODE (pat) == PARALLEL) | |
6828 | pat = XVECEXP (pat, 0, 0); | |
6829 | dest = SET_DEST (pat); | |
54bddf1d IE |
6830 | /* For multiple return values dest is PARALLEL. |
6831 | Currently we handle only single return value case. */ | |
6832 | if (REG_P (dest)) | |
6833 | { | |
6834 | start_sequence (); | |
6835 | emit_move_insn (cheap, copy_rtx (dest)); | |
6836 | restore = get_insns (); | |
6837 | end_sequence (); | |
6838 | lra_process_new_insns (curr_insn, NULL, restore, | |
6839 | "Inserting call parameter restore"); | |
6840 | /* We don't need to save/restore of the pseudo from | |
6841 | this call. */ | |
6842 | usage_insns[regno].calls_num = calls_num; | |
a1e6ee38 RS |
6843 | remove_from_hard_reg_set |
6844 | (&full_and_partial_call_clobbers, | |
6845 | GET_MODE (cheap), hard_regno); | |
54bddf1d IE |
6846 | bitmap_set_bit (&check_only_regs, regno); |
6847 | } | |
55a2c322 VM |
6848 | } |
6849 | } | |
6850 | to_inherit_num = 0; | |
6851 | /* Process insn usages. */ | |
2f259720 VM |
6852 | for (iter = 0; iter < 2; iter++) |
6853 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6854 | reg != NULL; | |
6855 | reg = reg->next) | |
6856 | if ((reg->type != OP_OUT | |
6857 | || (reg->type == OP_OUT && reg->subreg_p)) | |
6858 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
6859 | { | |
6860 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
6861 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
6862 | { | |
6863 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6864 | && (next_usage_insns | |
6865 | = usage_insns[src_regno].insns) != NULL_RTX | |
6866 | && NONDEBUG_INSN_P (curr_insn)) | |
6867 | add_to_inherit (src_regno, next_usage_insns); | |
6868 | else if (usage_insns[src_regno].check | |
6869 | != -(int) INSN_UID (curr_insn)) | |
6870 | /* Add usages but only if the reg is not set up | |
6871 | in the same insn. */ | |
6872 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6873 | } | |
6874 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
6875 | || reg_renumber[src_regno] >= 0) | |
6876 | { | |
6877 | bool before_p; | |
e67d1102 | 6878 | rtx_insn *use_insn = curr_insn; |
2f259720 VM |
6879 | |
6880 | before_p = (JUMP_P (curr_insn) | |
6881 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
6882 | if (NONDEBUG_INSN_P (curr_insn) | |
8e9d68a9 | 6883 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
2f259720 VM |
6884 | && split_if_necessary (src_regno, reg->biggest_mode, |
6885 | potential_reload_hard_regs, | |
6886 | before_p, curr_insn, max_uid)) | |
6887 | { | |
6888 | if (reg->subreg_p) | |
7436a1c6 | 6889 | check_and_force_assignment_correctness_p = true; |
2f259720 | 6890 | change_p = true; |
8e9d68a9 | 6891 | /* Invalidate. */ |
2f259720 VM |
6892 | usage_insns[src_regno].check = 0; |
6893 | if (before_p) | |
6894 | use_insn = PREV_INSN (curr_insn); | |
6895 | } | |
6896 | if (NONDEBUG_INSN_P (curr_insn)) | |
6897 | { | |
6898 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6899 | add_to_hard_reg_set (&live_hard_regs, | |
6900 | reg->biggest_mode, src_regno); | |
6901 | else | |
6902 | add_to_hard_reg_set (&live_hard_regs, | |
6903 | PSEUDO_REGNO_MODE (src_regno), | |
6904 | reg_renumber[src_regno]); | |
6905 | } | |
16ba97b9 VM |
6906 | if (src_regno >= FIRST_PSEUDO_REGISTER) |
6907 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
6908 | else | |
6909 | { | |
6910 | for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++) | |
6911 | add_next_usage_insn (src_regno + i, use_insn, reloads_num); | |
6912 | } | |
2f259720 VM |
6913 | } |
6914 | } | |
9d86e84e | 6915 | /* Process used call regs. */ |
df2980be VM |
6916 | if (curr_id->arg_hard_regs != NULL) |
6917 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6918 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6919 | { | |
6920 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
6921 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6922 | } | |
55a2c322 VM |
6923 | for (i = 0; i < to_inherit_num; i++) |
6924 | { | |
6925 | src_regno = to_inherit[i].regno; | |
6926 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
6927 | curr_insn, to_inherit[i].insns)) | |
6928 | change_p = true; | |
6929 | else | |
6930 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6931 | } | |
6932 | } | |
df2980be | 6933 | if (update_reloads_num_p |
8a8330b7 | 6934 | && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) |
df2980be VM |
6935 | { |
6936 | int regno = -1; | |
8a8330b7 VM |
6937 | if ((REG_P (SET_DEST (curr_set)) |
6938 | && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6939 | && reg_renumber[regno] < 0 |
6940 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
8a8330b7 VM |
6941 | || (REG_P (SET_SRC (curr_set)) |
6942 | && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6943 | && reg_renumber[regno] < 0 |
6944 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
6945 | { | |
8e9d68a9 VM |
6946 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6947 | reloads_num++; | |
df2980be | 6948 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
44942965 | 6949 | potential_reload_hard_regs |= reg_class_contents[cl]; |
df2980be VM |
6950 | } |
6951 | } | |
8a8330b7 VM |
6952 | if (NONDEBUG_INSN_P (curr_insn)) |
6953 | { | |
6954 | int regno; | |
6955 | ||
6956 | /* Invalidate invariants with changed regs. */ | |
6957 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6958 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6959 | if (reg->type != OP_IN) | |
f7abdf36 VM |
6960 | { |
6961 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6962 | bitmap_set_bit (&invalid_invariant_regs, | |
6963 | ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); | |
6964 | } | |
8a8330b7 VM |
6965 | curr_static_id = curr_id->insn_static_data; |
6966 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) | |
6967 | if (reg->type != OP_IN) | |
6968 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6969 | if (curr_id->arg_hard_regs != NULL) | |
6970 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
f7abdf36 | 6971 | if (regno >= FIRST_PSEUDO_REGISTER) |
8a8330b7 | 6972 | bitmap_set_bit (&invalid_invariant_regs, |
f7abdf36 | 6973 | regno - FIRST_PSEUDO_REGISTER); |
8a8330b7 | 6974 | } |
55a2c322 VM |
6975 | /* We reached the start of the current basic block. */ |
6976 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
6977 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
6978 | { | |
6979 | /* We reached the beginning of the current block -- do | |
6980 | rest of spliting in the current BB. */ | |
6981 | to_process = df_get_live_in (curr_bb); | |
6982 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
f4eafc30 | 6983 | { |
55a2c322 VM |
6984 | /* We are somewhere in the middle of EBB. */ |
6985 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
6986 | curr_bb, &temp_bitmap); | |
6987 | to_process = &temp_bitmap; | |
6988 | } | |
6989 | head_p = true; | |
6990 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6991 | { | |
6992 | if ((int) j >= lra_constraint_new_regno_start) | |
6993 | break; | |
6994 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6995 | && usage_insns[j].check == curr_usage_insns_check | |
6996 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
6997 | { | |
6998 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
6999 | { | |
7000 | if (lra_dump_file != NULL && head_p) | |
7001 | { | |
7002 | fprintf (lra_dump_file, | |
7003 | " ----------------------------------\n"); | |
7004 | head_p = false; | |
7005 | } | |
7006 | if (split_reg (false, j, bb_note (curr_bb), | |
6027ea4c | 7007 | next_usage_insns, NULL)) |
55a2c322 VM |
7008 | change_p = true; |
7009 | } | |
7010 | usage_insns[j].check = 0; | |
7011 | } | |
7012 | } | |
7013 | } | |
7014 | } | |
7015 | return change_p; | |
7016 | } | |
7017 | ||
7018 | /* This value affects EBB forming. If probability of edge from EBB to | |
7019 | a BB is not greater than the following value, we don't add the BB | |
f4eafc30 | 7020 | to EBB. */ |
fb8a0e40 | 7021 | #define EBB_PROBABILITY_CUTOFF \ |
028d4092 | 7022 | ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100) |
55a2c322 VM |
7023 | |
7024 | /* Current number of inheritance/split iteration. */ | |
7025 | int lra_inheritance_iter; | |
7026 | ||
7027 | /* Entry function for inheritance/split pass. */ | |
7028 | void | |
7029 | lra_inheritance (void) | |
7030 | { | |
7031 | int i; | |
7032 | basic_block bb, start_bb; | |
7033 | edge e; | |
7034 | ||
55a2c322 | 7035 | lra_inheritance_iter++; |
8e3a4869 | 7036 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b VM |
7037 | return; |
7038 | timevar_push (TV_LRA_INHERITANCE); | |
55a2c322 VM |
7039 | if (lra_dump_file != NULL) |
7040 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
7041 | lra_inheritance_iter); | |
7042 | curr_usage_insns_check = 0; | |
7043 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
7044 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
7045 | usage_insns[i].check = 0; | |
7046 | bitmap_initialize (&check_only_regs, ®_obstack); | |
8a8330b7 | 7047 | bitmap_initialize (&invalid_invariant_regs, ®_obstack); |
55a2c322 VM |
7048 | bitmap_initialize (&live_regs, ®_obstack); |
7049 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
7050 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
11cd3bed | 7051 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
7052 | { |
7053 | start_bb = bb; | |
7054 | if (lra_dump_file != NULL) | |
7055 | fprintf (lra_dump_file, "EBB"); | |
7056 | /* Form a EBB starting with BB. */ | |
7057 | bitmap_clear (&ebb_global_regs); | |
7058 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
7059 | for (;;) | |
7060 | { | |
7061 | if (lra_dump_file != NULL) | |
7062 | fprintf (lra_dump_file, " %d", bb->index); | |
fefa31b5 DM |
7063 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
7064 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
55a2c322 VM |
7065 | break; |
7066 | e = find_fallthru_edge (bb->succs); | |
7067 | if (! e) | |
7068 | break; | |
357067f2 JH |
7069 | if (e->probability.initialized_p () |
7070 | && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF) | |
55a2c322 VM |
7071 | break; |
7072 | bb = bb->next_bb; | |
7073 | } | |
7074 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
7075 | if (lra_dump_file != NULL) | |
7076 | fprintf (lra_dump_file, "\n"); | |
7077 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
7078 | /* Remember that the EBB head and tail can change in | |
7079 | inherit_in_ebb. */ | |
7080 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
7081 | } | |
1c252ef3 RB |
7082 | bitmap_release (&ebb_global_regs); |
7083 | bitmap_release (&temp_bitmap); | |
7084 | bitmap_release (&live_regs); | |
7085 | bitmap_release (&invalid_invariant_regs); | |
7086 | bitmap_release (&check_only_regs); | |
55a2c322 VM |
7087 | free (usage_insns); |
7088 | ||
7089 | timevar_pop (TV_LRA_INHERITANCE); | |
7090 | } | |
7091 | ||
7092 | \f | |
7093 | ||
7094 | /* This page contains code to undo failed inheritance/split | |
7095 | transformations. */ | |
7096 | ||
7097 | /* Current number of iteration undoing inheritance/split. */ | |
7098 | int lra_undo_inheritance_iter; | |
7099 | ||
7100 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
7101 | inheritance/split which are REMOVED_PSEUDOS. */ | |
7102 | static void | |
7103 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
7104 | { | |
7105 | unsigned int regno; | |
7106 | bitmap_iterator bi; | |
7107 | ||
7108 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
8a8330b7 VM |
7109 | if (bitmap_clear_bit (live, regno) |
7110 | && REG_P (lra_reg_info[regno].restore_rtx)) | |
7111 | bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); | |
55a2c322 VM |
7112 | } |
7113 | ||
7114 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
7115 | number. */ | |
7116 | static int | |
7117 | get_regno (rtx reg) | |
7118 | { | |
7119 | if (GET_CODE (reg) == SUBREG) | |
7120 | reg = SUBREG_REG (reg); | |
7121 | if (REG_P (reg)) | |
7122 | return REGNO (reg); | |
7123 | return -1; | |
7124 | } | |
7125 | ||
cefe08a4 VM |
7126 | /* Delete a move INSN with destination reg DREGNO and a previous |
7127 | clobber insn with the same regno. The inheritance/split code can | |
7128 | generate moves with preceding clobber and when we delete such moves | |
7129 | we should delete the clobber insn too to keep the correct life | |
7130 | info. */ | |
7131 | static void | |
7132 | delete_move_and_clobber (rtx_insn *insn, int dregno) | |
7133 | { | |
7134 | rtx_insn *prev_insn = PREV_INSN (insn); | |
7135 | ||
7136 | lra_set_insn_deleted (insn); | |
79b57d18 | 7137 | lra_assert (dregno >= 0); |
cefe08a4 VM |
7138 | if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) |
7139 | && GET_CODE (PATTERN (prev_insn)) == CLOBBER | |
7140 | && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) | |
7141 | lra_set_insn_deleted (prev_insn); | |
7142 | } | |
7143 | ||
55a2c322 VM |
7144 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and |
7145 | return true if we did any change. The undo transformations for | |
7146 | inheritance looks like | |
7147 | i <- i2 | |
7148 | p <- i => p <- i2 | |
7149 | or removing | |
7150 | p <- i, i <- p, and i <- i3 | |
7151 | where p is original pseudo from which inheritance pseudo i was | |
7152 | created, i and i3 are removed inheritance pseudos, i2 is another | |
7153 | not removed inheritance pseudo. All split pseudos or other | |
7154 | occurrences of removed inheritance pseudos are changed on the | |
7155 | corresponding original pseudos. | |
7156 | ||
7157 | The function also schedules insns changed and created during | |
7158 | inheritance/split pass for processing by the subsequent constraint | |
7159 | pass. */ | |
7160 | static bool | |
7161 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
7162 | { | |
7163 | basic_block bb; | |
8a8330b7 VM |
7164 | int regno, sregno, prev_sregno, dregno; |
7165 | rtx restore_rtx; | |
cfa434f6 DM |
7166 | rtx set, prev_set; |
7167 | rtx_insn *prev_insn; | |
55a2c322 VM |
7168 | bool change_p, done_p; |
7169 | ||
7170 | change_p = ! bitmap_empty_p (remove_pseudos); | |
67914693 | 7171 | /* We cannot finish the function right away if CHANGE_P is true |
55a2c322 VM |
7172 | because we need to marks insns affected by previous |
7173 | inheritance/split pass for processing by the subsequent | |
7174 | constraint pass. */ | |
11cd3bed | 7175 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
7176 | { |
7177 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
7178 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
7179 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
7180 | { | |
7181 | if (! INSN_P (curr_insn)) | |
7182 | continue; | |
7183 | done_p = false; | |
7184 | sregno = dregno = -1; | |
7185 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
7186 | && (set = single_set (curr_insn)) != NULL_RTX) | |
7187 | { | |
7188 | dregno = get_regno (SET_DEST (set)); | |
7189 | sregno = get_regno (SET_SRC (set)); | |
7190 | } | |
f4eafc30 | 7191 | |
55a2c322 VM |
7192 | if (sregno >= 0 && dregno >= 0) |
7193 | { | |
8a8330b7 VM |
7194 | if (bitmap_bit_p (remove_pseudos, dregno) |
7195 | && ! REG_P (lra_reg_info[dregno].restore_rtx)) | |
7196 | { | |
7197 | /* invariant inheritance pseudo <- original pseudo */ | |
7198 | if (lra_dump_file != NULL) | |
7199 | { | |
7200 | fprintf (lra_dump_file, " Removing invariant inheritance:\n"); | |
7201 | dump_insn_slim (lra_dump_file, curr_insn); | |
7202 | fprintf (lra_dump_file, "\n"); | |
7203 | } | |
7204 | delete_move_and_clobber (curr_insn, dregno); | |
7205 | done_p = true; | |
7206 | } | |
7207 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
7208 | && ! REG_P (lra_reg_info[sregno].restore_rtx)) | |
7209 | { | |
7210 | /* reload pseudo <- invariant inheritance pseudo */ | |
7211 | start_sequence (); | |
67914693 | 7212 | /* We cannot just change the source. It might be |
8a8330b7 | 7213 | an insn different from the move. */ |
b10d44ef | 7214 | emit_insn (lra_reg_info[sregno].restore_rtx); |
8a8330b7 VM |
7215 | rtx_insn *new_insns = get_insns (); |
7216 | end_sequence (); | |
b10d44ef VM |
7217 | lra_assert (single_set (new_insns) != NULL |
7218 | && SET_DEST (set) == SET_DEST (single_set (new_insns))); | |
8a8330b7 VM |
7219 | lra_process_new_insns (curr_insn, NULL, new_insns, |
7220 | "Changing reload<-invariant inheritance"); | |
7221 | delete_move_and_clobber (curr_insn, dregno); | |
7222 | done_p = true; | |
7223 | } | |
7224 | else if ((bitmap_bit_p (remove_pseudos, sregno) | |
7225 | && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno | |
7226 | || (bitmap_bit_p (remove_pseudos, dregno) | |
7227 | && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
7228 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
7229 | == get_regno (lra_reg_info[dregno].restore_rtx))))) | |
55a2c322 | 7230 | || (bitmap_bit_p (remove_pseudos, dregno) |
8a8330b7 | 7231 | && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) |
55a2c322 VM |
7232 | /* One of the following cases: |
7233 | original <- removed inheritance pseudo | |
7234 | removed inherit pseudo <- another removed inherit pseudo | |
7235 | removed inherit pseudo <- original pseudo | |
7236 | Or | |
7237 | removed_split_pseudo <- original_reg | |
7238 | original_reg <- removed_split_pseudo */ | |
7239 | { | |
7240 | if (lra_dump_file != NULL) | |
7241 | { | |
7242 | fprintf (lra_dump_file, " Removing %s:\n", | |
7243 | bitmap_bit_p (&lra_split_regs, sregno) | |
7244 | || bitmap_bit_p (&lra_split_regs, dregno) | |
7245 | ? "split" : "inheritance"); | |
cfbeaedf | 7246 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 | 7247 | } |
cefe08a4 | 7248 | delete_move_and_clobber (curr_insn, dregno); |
55a2c322 VM |
7249 | done_p = true; |
7250 | } | |
7251 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
7252 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
7253 | { | |
7254 | /* Search the following pattern: | |
7255 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
7256 | original_pseudo <- inherit_or_split_pseudo1 | |
7257 | where the 2nd insn is the current insn and | |
7258 | inherit_or_split_pseudo2 is not removed. If it is found, | |
7259 | change the current insn onto: | |
7260 | original_pseudo <- inherit_or_split_pseudo2. */ | |
7261 | for (prev_insn = PREV_INSN (curr_insn); | |
7262 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
7263 | prev_insn = PREV_INSN (prev_insn)) | |
7264 | ; | |
7265 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
7266 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
7267 | /* There should be no subregs in insn we are | |
7268 | searching because only the original reg might | |
7269 | be in subreg when we changed the mode of | |
7270 | load/store for splitting. */ | |
7271 | && REG_P (SET_DEST (prev_set)) | |
7272 | && REG_P (SET_SRC (prev_set)) | |
7273 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
7274 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
7275 | >= FIRST_PSEUDO_REGISTER) | |
8a8330b7 VM |
7276 | && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX |
7277 | || | |
7278 | /* As we consider chain of inheritance or | |
7279 | splitting described in above comment we should | |
7280 | check that sregno and prev_sregno were | |
7281 | inheritance/split pseudos created from the | |
7282 | same original regno. */ | |
7283 | (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
7284 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
7285 | == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) | |
55a2c322 VM |
7286 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) |
7287 | { | |
7288 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
7289 | == GET_MODE (regno_reg_rtx[sregno])); | |
ef61d1ab AK |
7290 | /* Although we have a single set, the insn can |
7291 | contain more one sregno register occurrence | |
7292 | as a source. Change all occurrences. */ | |
7293 | lra_substitute_pseudo_within_insn (curr_insn, sregno, | |
7294 | SET_SRC (prev_set), | |
7295 | false); | |
12b308fa VM |
7296 | /* As we are finishing with processing the insn |
7297 | here, check the destination too as it might | |
7298 | inheritance pseudo for another pseudo. */ | |
7299 | if (bitmap_bit_p (remove_pseudos, dregno) | |
7300 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
8a8330b7 VM |
7301 | && (restore_rtx |
7302 | = lra_reg_info[dregno].restore_rtx) != NULL_RTX) | |
12b308fa VM |
7303 | { |
7304 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
8a8330b7 | 7305 | SUBREG_REG (SET_DEST (set)) = restore_rtx; |
12b308fa | 7306 | else |
8a8330b7 | 7307 | SET_DEST (set) = restore_rtx; |
12b308fa | 7308 | } |
55a2c322 VM |
7309 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
7310 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 7311 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
7312 | done_p = true; |
7313 | if (lra_dump_file != NULL) | |
7314 | { | |
7315 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
cfbeaedf | 7316 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
7317 | } |
7318 | } | |
7319 | } | |
7320 | } | |
7321 | if (! done_p) | |
7322 | { | |
7323 | struct lra_insn_reg *reg; | |
7324 | bool restored_regs_p = false; | |
7325 | bool kept_regs_p = false; | |
7326 | ||
7327 | curr_id = lra_get_insn_recog_data (curr_insn); | |
7328 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
7329 | { | |
7330 | regno = reg->regno; | |
8a8330b7 VM |
7331 | restore_rtx = lra_reg_info[regno].restore_rtx; |
7332 | if (restore_rtx != NULL_RTX) | |
55a2c322 VM |
7333 | { |
7334 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
7335 | { | |
ef87312e | 7336 | lra_substitute_pseudo_within_insn |
8a8330b7 | 7337 | (curr_insn, regno, restore_rtx, false); |
55a2c322 VM |
7338 | restored_regs_p = true; |
7339 | } | |
7340 | else | |
7341 | kept_regs_p = true; | |
7342 | } | |
7343 | } | |
7344 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
7345 | { | |
7346 | /* The instruction has changed since the previous | |
7347 | constraints pass. */ | |
7348 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
7349 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 7350 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
7351 | } |
7352 | else if (restored_regs_p) | |
7353 | /* The instruction has been restored to the form that | |
7354 | it had during the previous constraints pass. */ | |
7355 | lra_update_insn_regno_info (curr_insn); | |
7356 | if (restored_regs_p && lra_dump_file != NULL) | |
7357 | { | |
7358 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
cfbeaedf | 7359 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
7360 | } |
7361 | } | |
7362 | } | |
7363 | } | |
7364 | return change_p; | |
7365 | } | |
7366 | ||
2b778c9d VM |
7367 | /* If optional reload pseudos failed to get a hard register or was not |
7368 | inherited, it is better to remove optional reloads. We do this | |
7369 | transformation after undoing inheritance to figure out necessity to | |
7370 | remove optional reloads easier. Return true if we do any | |
7371 | change. */ | |
7372 | static bool | |
7373 | undo_optional_reloads (void) | |
7374 | { | |
b0681c9e | 7375 | bool change_p, keep_p; |
2b778c9d VM |
7376 | unsigned int regno, uid; |
7377 | bitmap_iterator bi, bi2; | |
cfa434f6 DM |
7378 | rtx_insn *insn; |
7379 | rtx set, src, dest; | |
d648b5ff | 7380 | auto_bitmap removed_optional_reload_pseudos (®_obstack); |
2b778c9d | 7381 | |
d648b5ff | 7382 | bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos); |
2b778c9d | 7383 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) |
aa940f7c VM |
7384 | { |
7385 | keep_p = false; | |
080cbf9e | 7386 | /* Keep optional reloads from previous subpasses. */ |
8a8330b7 | 7387 | if (lra_reg_info[regno].restore_rtx == NULL_RTX |
080cbf9e VM |
7388 | /* If the original pseudo changed its allocation, just |
7389 | removing the optional pseudo is dangerous as the original | |
7390 | pseudo will have longer live range. */ | |
8a8330b7 | 7391 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) |
aa940f7c VM |
7392 | keep_p = true; |
7393 | else if (reg_renumber[regno] >= 0) | |
7394 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
b0681c9e | 7395 | { |
aa940f7c VM |
7396 | insn = lra_insn_recog_data[uid]->insn; |
7397 | if ((set = single_set (insn)) == NULL_RTX) | |
7398 | continue; | |
7399 | src = SET_SRC (set); | |
7400 | dest = SET_DEST (set); | |
12f8dc0b AO |
7401 | if ((! REG_P (src) && ! SUBREG_P (src)) |
7402 | || (! REG_P (dest) && ! SUBREG_P (dest))) | |
aa940f7c | 7403 | continue; |
12f8dc0b | 7404 | if (get_regno (dest) == (int) regno |
aa940f7c | 7405 | /* Ignore insn for optional reloads itself. */ |
12f8dc0b AO |
7406 | && (get_regno (lra_reg_info[regno].restore_rtx) |
7407 | != get_regno (src)) | |
aa940f7c | 7408 | /* Check only inheritance on last inheritance pass. */ |
12f8dc0b | 7409 | && get_regno (src) >= new_regno_start |
aa940f7c | 7410 | /* Check that the optional reload was inherited. */ |
12f8dc0b | 7411 | && bitmap_bit_p (&lra_inheritance_pseudos, get_regno (src))) |
aa940f7c VM |
7412 | { |
7413 | keep_p = true; | |
7414 | break; | |
7415 | } | |
b0681c9e | 7416 | } |
aa940f7c VM |
7417 | if (keep_p) |
7418 | { | |
d648b5ff | 7419 | bitmap_clear_bit (removed_optional_reload_pseudos, regno); |
aa940f7c VM |
7420 | if (lra_dump_file != NULL) |
7421 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
7422 | } | |
7423 | } | |
d648b5ff TS |
7424 | change_p = ! bitmap_empty_p (removed_optional_reload_pseudos); |
7425 | auto_bitmap insn_bitmap (®_obstack); | |
7426 | EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi) | |
2b778c9d VM |
7427 | { |
7428 | if (lra_dump_file != NULL) | |
7429 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
d648b5ff TS |
7430 | bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap); |
7431 | EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2) | |
2b778c9d | 7432 | { |
12f8dc0b AO |
7433 | /* We may have already removed a clobber. */ |
7434 | if (!lra_insn_recog_data[uid]) | |
7435 | continue; | |
2b778c9d VM |
7436 | insn = lra_insn_recog_data[uid]->insn; |
7437 | if ((set = single_set (insn)) != NULL_RTX) | |
7438 | { | |
7439 | src = SET_SRC (set); | |
7440 | dest = SET_DEST (set); | |
12f8dc0b AO |
7441 | if ((REG_P (src) || SUBREG_P (src)) |
7442 | && (REG_P (dest) || SUBREG_P (dest)) | |
7443 | && ((get_regno (src) == (int) regno | |
7444 | && (get_regno (lra_reg_info[regno].restore_rtx) | |
7445 | == get_regno (dest))) | |
7446 | || (get_regno (dest) == (int) regno | |
7447 | && (get_regno (lra_reg_info[regno].restore_rtx) | |
7448 | == get_regno (src))))) | |
2b778c9d VM |
7449 | { |
7450 | if (lra_dump_file != NULL) | |
7451 | { | |
7452 | fprintf (lra_dump_file, " Deleting move %u\n", | |
7453 | INSN_UID (insn)); | |
7454 | dump_insn_slim (lra_dump_file, insn); | |
7455 | } | |
12f8dc0b | 7456 | delete_move_and_clobber (insn, get_regno (dest)); |
2b778c9d VM |
7457 | continue; |
7458 | } | |
7459 | /* We should not worry about generation memory-memory | |
7460 | moves here as if the corresponding inheritance did | |
7461 | not work (inheritance pseudo did not get a hard reg), | |
7462 | we remove the inheritance pseudo and the optional | |
7463 | reload. */ | |
7464 | } | |
12f8dc0b AO |
7465 | if (GET_CODE (PATTERN (insn)) == CLOBBER |
7466 | && REG_P (SET_DEST (insn)) | |
7467 | && get_regno (SET_DEST (insn)) == (int) regno) | |
7468 | /* Refuse to remap clobbers to preexisting pseudos. */ | |
7469 | gcc_unreachable (); | |
ef87312e | 7470 | lra_substitute_pseudo_within_insn |
8a8330b7 | 7471 | (insn, regno, lra_reg_info[regno].restore_rtx, false); |
2b778c9d VM |
7472 | lra_update_insn_regno_info (insn); |
7473 | if (lra_dump_file != NULL) | |
7474 | { | |
7475 | fprintf (lra_dump_file, | |
7476 | " Restoring original insn:\n"); | |
7477 | dump_insn_slim (lra_dump_file, insn); | |
7478 | } | |
7479 | } | |
7480 | } | |
7481 | /* Clear restore_regnos. */ | |
7482 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
8a8330b7 | 7483 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d VM |
7484 | return change_p; |
7485 | } | |
7486 | ||
55a2c322 VM |
7487 | /* Entry function for undoing inheritance/split transformation. Return true |
7488 | if we did any RTL change in this pass. */ | |
7489 | bool | |
7490 | lra_undo_inheritance (void) | |
7491 | { | |
7492 | unsigned int regno; | |
8a8330b7 | 7493 | int hard_regno; |
55a2c322 | 7494 | int n_all_inherit, n_inherit, n_all_split, n_split; |
8a8330b7 | 7495 | rtx restore_rtx; |
55a2c322 VM |
7496 | bitmap_iterator bi; |
7497 | bool change_p; | |
7498 | ||
7499 | lra_undo_inheritance_iter++; | |
8e3a4869 | 7500 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b | 7501 | return false; |
55a2c322 VM |
7502 | if (lra_dump_file != NULL) |
7503 | fprintf (lra_dump_file, | |
7504 | "\n********** Undoing inheritance #%d: **********\n\n", | |
7505 | lra_undo_inheritance_iter); | |
d648b5ff | 7506 | auto_bitmap remove_pseudos (®_obstack); |
55a2c322 VM |
7507 | n_inherit = n_all_inherit = 0; |
7508 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7509 | if (lra_reg_info[regno].restore_rtx != NULL_RTX) |
55a2c322 VM |
7510 | { |
7511 | n_all_inherit++; | |
b0681c9e VM |
7512 | if (reg_renumber[regno] < 0 |
7513 | /* If the original pseudo changed its allocation, just | |
7514 | removing inheritance is dangerous as for changing | |
7515 | allocation we used shorter live-ranges. */ | |
8a8330b7 VM |
7516 | && (! REG_P (lra_reg_info[regno].restore_rtx) |
7517 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) | |
d648b5ff | 7518 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7519 | else |
7520 | n_inherit++; | |
7521 | } | |
7522 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
7523 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
7524 | n_inherit, n_all_inherit, | |
7525 | (double) n_inherit / n_all_inherit * 100); | |
7526 | n_split = n_all_split = 0; | |
7527 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
8a8330b7 | 7528 | if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) |
55a2c322 | 7529 | { |
8a8330b7 VM |
7530 | int restore_regno = REGNO (restore_rtx); |
7531 | ||
55a2c322 VM |
7532 | n_all_split++; |
7533 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
7534 | ? reg_renumber[restore_regno] : restore_regno); | |
7535 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
d648b5ff | 7536 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7537 | else |
7538 | { | |
7539 | n_split++; | |
7540 | if (lra_dump_file != NULL) | |
7541 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
7542 | regno, restore_regno); | |
7543 | } | |
7544 | } | |
7545 | if (lra_dump_file != NULL && n_all_split != 0) | |
7546 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
7547 | n_split, n_all_split, | |
7548 | (double) n_split / n_all_split * 100); | |
d648b5ff | 7549 | change_p = remove_inheritance_pseudos (remove_pseudos); |
55a2c322 VM |
7550 | /* Clear restore_regnos. */ |
7551 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7552 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
55a2c322 | 7553 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) |
8a8330b7 | 7554 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d | 7555 | change_p = undo_optional_reloads () || change_p; |
55a2c322 VM |
7556 | return change_p; |
7557 | } |