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c8465d70 | 1 | /* Perform various loop optimizations, including strength reduction. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
8beccec8 | 3 | 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
b4ad7b23 | 4 | |
1322177d | 5 | This file is part of GCC. |
b4ad7b23 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
b4ad7b23 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
b4ad7b23 RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
b4ad7b23 | 21 | |
b4ad7b23 RS |
22 | /* This is the loop optimization pass of the compiler. |
23 | It finds invariant computations within loops and moves them | |
e6fcb60d | 24 | to the beginning of the loop. Then it identifies basic and |
4ca0d6d4 CL |
25 | general induction variables. |
26 | ||
27 | Basic induction variables (BIVs) are a pseudo registers which are set within | |
28 | a loop only by incrementing or decrementing its value. General induction | |
29 | variables (GIVs) are pseudo registers with a value which is a linear function | |
30 | of a basic induction variable. BIVs are recognized by `basic_induction_var'; | |
31 | GIVs by `general_induction_var'. | |
32 | ||
33 | Once induction variables are identified, strength reduction is applied to the | |
34 | general induction variables, and induction variable elimination is applied to | |
b4ad7b23 RS |
35 | the basic induction variables. |
36 | ||
37 | It also finds cases where | |
38 | a register is set within the loop by zero-extending a narrower value | |
39 | and changes these to zero the entire register once before the loop | |
40 | and merely copy the low part within the loop. | |
41 | ||
42 | Most of the complexity is in heuristics to decide when it is worth | |
43 | while to do these things. */ | |
44 | ||
45 | #include "config.h" | |
670ee920 | 46 | #include "system.h" |
4977bab6 ZW |
47 | #include "coretypes.h" |
48 | #include "tm.h" | |
b4ad7b23 | 49 | #include "rtl.h" |
6baf1cc8 | 50 | #include "tm_p.h" |
49ad7cfa | 51 | #include "function.h" |
b4ad7b23 | 52 | #include "expr.h" |
efc9bd41 | 53 | #include "hard-reg-set.h" |
c29f60c0 | 54 | #include "basic-block.h" |
b4ad7b23 | 55 | #include "insn-config.h" |
b4ad7b23 | 56 | #include "regs.h" |
b4ad7b23 RS |
57 | #include "recog.h" |
58 | #include "flags.h" | |
59 | #include "real.h" | |
b4ad7b23 | 60 | #include "loop.h" |
eab5c70a | 61 | #include "cselib.h" |
6adb4e3a | 62 | #include "except.h" |
2e107e9e | 63 | #include "toplev.h" |
aa18f20e | 64 | #include "predict.h" |
0dd0e980 | 65 | #include "insn-flags.h" |
11303d15 | 66 | #include "optabs.h" |
3d436d2a | 67 | #include "cfgloop.h" |
0dd0e980 JH |
68 | |
69 | /* Not really meaningful values, but at least something. */ | |
70 | #ifndef SIMULTANEOUS_PREFETCHES | |
71 | #define SIMULTANEOUS_PREFETCHES 3 | |
72 | #endif | |
73 | #ifndef PREFETCH_BLOCK | |
74 | #define PREFETCH_BLOCK 32 | |
75 | #endif | |
76 | #ifndef HAVE_prefetch | |
77 | #define HAVE_prefetch 0 | |
a415f7bc | 78 | #define CODE_FOR_prefetch 0 |
0dd0e980 JH |
79 | #define gen_prefetch(a,b,c) (abort(), NULL_RTX) |
80 | #endif | |
81 | ||
e0bb17a8 | 82 | /* Give up the prefetch optimizations once we exceed a given threshold. |
0dd0e980 JH |
83 | It is unlikely that we would be able to optimize something in a loop |
84 | with so many detected prefetches. */ | |
85 | #define MAX_PREFETCHES 100 | |
86 | /* The number of prefetch blocks that are beneficial to fetch at once before | |
87 | a loop with a known (and low) iteration count. */ | |
88 | #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6 | |
89 | /* For very tiny loops it is not worthwhile to prefetch even before the loop, | |
90 | since it is likely that the data are already in the cache. */ | |
91 | #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2 | |
0dd0e980 JH |
92 | |
93 | /* Parameterize some prefetch heuristics so they can be turned on and off | |
3d042e77 | 94 | easily for performance testing on new architectures. These can be |
0dd0e980 JH |
95 | defined in target-dependent files. */ |
96 | ||
97 | /* Prefetch is worthwhile only when loads/stores are dense. */ | |
98 | #ifndef PREFETCH_ONLY_DENSE_MEM | |
99 | #define PREFETCH_ONLY_DENSE_MEM 1 | |
100 | #endif | |
101 | ||
102 | /* Define what we mean by "dense" loads and stores; This value divided by 256 | |
103 | is the minimum percentage of memory references that worth prefetching. */ | |
104 | #ifndef PREFETCH_DENSE_MEM | |
105 | #define PREFETCH_DENSE_MEM 220 | |
106 | #endif | |
107 | ||
108 | /* Do not prefetch for a loop whose iteration count is known to be low. */ | |
109 | #ifndef PREFETCH_NO_LOW_LOOPCNT | |
110 | #define PREFETCH_NO_LOW_LOOPCNT 1 | |
111 | #endif | |
112 | ||
113 | /* Define what we mean by a "low" iteration count. */ | |
114 | #ifndef PREFETCH_LOW_LOOPCNT | |
115 | #define PREFETCH_LOW_LOOPCNT 32 | |
116 | #endif | |
117 | ||
118 | /* Do not prefetch for a loop that contains a function call; such a loop is | |
119 | probably not an internal loop. */ | |
120 | #ifndef PREFETCH_NO_CALL | |
121 | #define PREFETCH_NO_CALL 1 | |
122 | #endif | |
123 | ||
124 | /* Do not prefetch accesses with an extreme stride. */ | |
125 | #ifndef PREFETCH_NO_EXTREME_STRIDE | |
126 | #define PREFETCH_NO_EXTREME_STRIDE 1 | |
127 | #endif | |
128 | ||
129 | /* Define what we mean by an "extreme" stride. */ | |
130 | #ifndef PREFETCH_EXTREME_STRIDE | |
131 | #define PREFETCH_EXTREME_STRIDE 4096 | |
132 | #endif | |
133 | ||
79a497cd JJ |
134 | /* Define a limit to how far apart indices can be and still be merged |
135 | into a single prefetch. */ | |
136 | #ifndef PREFETCH_EXTREME_DIFFERENCE | |
137 | #define PREFETCH_EXTREME_DIFFERENCE 4096 | |
138 | #endif | |
139 | ||
140 | /* Issue prefetch instructions before the loop to fetch data to be used | |
141 | in the first few loop iterations. */ | |
142 | #ifndef PREFETCH_BEFORE_LOOP | |
143 | #define PREFETCH_BEFORE_LOOP 1 | |
144 | #endif | |
145 | ||
0dd0e980 JH |
146 | /* Do not handle reversed order prefetches (negative stride). */ |
147 | #ifndef PREFETCH_NO_REVERSE_ORDER | |
148 | #define PREFETCH_NO_REVERSE_ORDER 1 | |
149 | #endif | |
150 | ||
79a497cd JJ |
151 | /* Prefetch even if the GIV is in conditional code. */ |
152 | #ifndef PREFETCH_CONDITIONAL | |
62e6ca55 | 153 | #define PREFETCH_CONDITIONAL 1 |
0dd0e980 JH |
154 | #endif |
155 | ||
b8056b46 MH |
156 | #define LOOP_REG_LIFETIME(LOOP, REGNO) \ |
157 | ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO))) | |
158 | ||
159 | #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \ | |
160 | ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \ | |
161 | || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start))) | |
162 | ||
d5e0243a DE |
163 | #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \ |
164 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
44a5565d | 165 | ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1) |
d5e0243a | 166 | |
8529a489 | 167 | |
b4ad7b23 | 168 | /* Vector mapping INSN_UIDs to luids. |
d45cf215 | 169 | The luids are like uids but increase monotonically always. |
b4ad7b23 RS |
170 | We use them to see whether a jump comes from outside a given loop. */ |
171 | ||
172 | int *uid_luid; | |
173 | ||
174 | /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop | |
175 | number the insn is contained in. */ | |
176 | ||
a2be868f | 177 | struct loop **uid_loop; |
b4ad7b23 RS |
178 | |
179 | /* 1 + largest uid of any insn. */ | |
180 | ||
181 | int max_uid_for_loop; | |
182 | ||
b4ad7b23 RS |
183 | /* Number of loops detected in current function. Used as index to the |
184 | next few tables. */ | |
185 | ||
186 | static int max_loop_num; | |
187 | ||
b4ad7b23 RS |
188 | /* Bound on pseudo register number before loop optimization. |
189 | A pseudo has valid regscan info if its number is < max_reg_before_loop. */ | |
770ae6cc | 190 | unsigned int max_reg_before_loop; |
b4ad7b23 | 191 | |
0a326ec9 BS |
192 | /* The value to pass to the next call of reg_scan_update. */ |
193 | static int loop_max_reg; | |
b4ad7b23 RS |
194 | \f |
195 | /* During the analysis of a loop, a chain of `struct movable's | |
196 | is made to record all the movable insns found. | |
197 | Then the entire chain can be scanned to decide which to move. */ | |
198 | ||
199 | struct movable | |
200 | { | |
201 | rtx insn; /* A movable insn */ | |
0f41302f MS |
202 | rtx set_src; /* The expression this reg is set from. */ |
203 | rtx set_dest; /* The destination of this SET. */ | |
b4ad7b23 | 204 | rtx dependencies; /* When INSN is libcall, this is an EXPR_LIST |
0f41302f | 205 | of any registers used within the LIBCALL. */ |
e6fcb60d | 206 | int consec; /* Number of consecutive following insns |
b4ad7b23 | 207 | that must be moved with this one. */ |
770ae6cc | 208 | unsigned int regno; /* The register it sets */ |
b4ad7b23 RS |
209 | short lifetime; /* lifetime of that register; |
210 | may be adjusted when matching movables | |
211 | that load the same value are found. */ | |
212 | short savings; /* Number of insns we can move for this reg, | |
213 | including other movables that force this | |
214 | or match this one. */ | |
0c20a65f | 215 | ENUM_BITFIELD(machine_mode) savemode : 8; /* Nonzero means it is a mode for |
8f7ee471 DJ |
216 | a low part that we should avoid changing when |
217 | clearing the rest of the reg. */ | |
b4ad7b23 RS |
218 | unsigned int cond : 1; /* 1 if only conditionally movable */ |
219 | unsigned int force : 1; /* 1 means MUST move this insn */ | |
220 | unsigned int global : 1; /* 1 means reg is live outside this loop */ | |
221 | /* If PARTIAL is 1, GLOBAL means something different: | |
222 | that the reg is live outside the range from where it is set | |
223 | to the following label. */ | |
224 | unsigned int done : 1; /* 1 inhibits further processing of this */ | |
e6fcb60d | 225 | |
b4ad7b23 RS |
226 | unsigned int partial : 1; /* 1 means this reg is used for zero-extending. |
227 | In particular, moving it does not make it | |
228 | invariant. */ | |
229 | unsigned int move_insn : 1; /* 1 means that we call emit_move_insn to | |
230 | load SRC, rather than copying INSN. */ | |
1a61c29f JW |
231 | unsigned int move_insn_first:1;/* Same as above, if this is necessary for the |
232 | first insn of a consecutive sets group. */ | |
0f41302f | 233 | unsigned int is_equiv : 1; /* 1 means a REG_EQUIV is present on INSN. */ |
8f7ee471 DJ |
234 | unsigned int insert_temp : 1; /* 1 means we copy to a new pseudo and replace |
235 | the original insn with a copy from that | |
3dc575ff | 236 | pseudo, rather than deleting it. */ |
b4ad7b23 RS |
237 | struct movable *match; /* First entry for same value */ |
238 | struct movable *forces; /* An insn that must be moved if this is */ | |
239 | struct movable *next; | |
240 | }; | |
241 | ||
45f97e2e | 242 | |
b4ad7b23 RS |
243 | FILE *loop_dump_stream; |
244 | ||
245 | /* Forward declarations. */ | |
246 | ||
0c20a65f AJ |
247 | static void invalidate_loops_containing_label (rtx); |
248 | static void find_and_verify_loops (rtx, struct loops *); | |
249 | static void mark_loop_jump (rtx, struct loop *); | |
250 | static void prescan_loop (struct loop *); | |
251 | static int reg_in_basic_block_p (rtx, rtx); | |
252 | static int consec_sets_invariant_p (const struct loop *, rtx, int, rtx); | |
253 | static int labels_in_range_p (rtx, int); | |
254 | static void count_one_set (struct loop_regs *, rtx, rtx, rtx *); | |
255 | static void note_addr_stored (rtx, rtx, void *); | |
256 | static void note_set_pseudo_multiple_uses (rtx, rtx, void *); | |
257 | static int loop_reg_used_before_p (const struct loop *, rtx, rtx); | |
258 | static void scan_loop (struct loop*, int); | |
e9a25f70 | 259 | #if 0 |
0c20a65f | 260 | static void replace_call_address (rtx, rtx, rtx); |
e9a25f70 | 261 | #endif |
0c20a65f AJ |
262 | static rtx skip_consec_insns (rtx, int); |
263 | static int libcall_benefit (rtx); | |
264 | static void ignore_some_movables (struct loop_movables *); | |
265 | static void force_movables (struct loop_movables *); | |
266 | static void combine_movables (struct loop_movables *, struct loop_regs *); | |
267 | static int num_unmoved_movables (const struct loop *); | |
268 | static int regs_match_p (rtx, rtx, struct loop_movables *); | |
269 | static int rtx_equal_for_loop_p (rtx, rtx, struct loop_movables *, | |
270 | struct loop_regs *); | |
271 | static void add_label_notes (rtx, rtx); | |
272 | static void move_movables (struct loop *loop, struct loop_movables *, int, | |
273 | int); | |
274 | static void loop_movables_add (struct loop_movables *, struct movable *); | |
275 | static void loop_movables_free (struct loop_movables *); | |
276 | static int count_nonfixed_reads (const struct loop *, rtx); | |
277 | static void loop_bivs_find (struct loop *); | |
278 | static void loop_bivs_init_find (struct loop *); | |
279 | static void loop_bivs_check (struct loop *); | |
280 | static void loop_givs_find (struct loop *); | |
281 | static void loop_givs_check (struct loop *); | |
282 | static int loop_biv_eliminable_p (struct loop *, struct iv_class *, int, int); | |
283 | static int loop_giv_reduce_benefit (struct loop *, struct iv_class *, | |
284 | struct induction *, rtx); | |
285 | static void loop_givs_dead_check (struct loop *, struct iv_class *); | |
286 | static void loop_givs_reduce (struct loop *, struct iv_class *); | |
287 | static void loop_givs_rescan (struct loop *, struct iv_class *, rtx *); | |
288 | static void loop_ivs_free (struct loop *); | |
289 | static void strength_reduce (struct loop *, int); | |
290 | static void find_single_use_in_loop (struct loop_regs *, rtx, rtx); | |
291 | static int valid_initial_value_p (rtx, rtx, int, rtx); | |
292 | static void find_mem_givs (const struct loop *, rtx, rtx, int, int); | |
293 | static void record_biv (struct loop *, struct induction *, rtx, rtx, rtx, | |
294 | rtx, rtx *, int, int); | |
295 | static void check_final_value (const struct loop *, struct induction *); | |
296 | static void loop_ivs_dump (const struct loop *, FILE *, int); | |
297 | static void loop_iv_class_dump (const struct iv_class *, FILE *, int); | |
298 | static void loop_biv_dump (const struct induction *, FILE *, int); | |
299 | static void loop_giv_dump (const struct induction *, FILE *, int); | |
300 | static void record_giv (const struct loop *, struct induction *, rtx, rtx, | |
301 | rtx, rtx, rtx, rtx, int, enum g_types, int, int, | |
302 | rtx *); | |
303 | static void update_giv_derive (const struct loop *, rtx); | |
03988cac | 304 | static void check_ext_dependent_givs (const struct loop *, struct iv_class *); |
0c20a65f AJ |
305 | static int basic_induction_var (const struct loop *, rtx, enum machine_mode, |
306 | rtx, rtx, rtx *, rtx *, rtx **); | |
307 | static rtx simplify_giv_expr (const struct loop *, rtx, rtx *, int *); | |
308 | static int general_induction_var (const struct loop *loop, rtx, rtx *, rtx *, | |
309 | rtx *, rtx *, int, int *, enum machine_mode); | |
310 | static int consec_sets_giv (const struct loop *, int, rtx, rtx, rtx, rtx *, | |
311 | rtx *, rtx *, rtx *); | |
312 | static int check_dbra_loop (struct loop *, int); | |
313 | static rtx express_from_1 (rtx, rtx, rtx); | |
314 | static rtx combine_givs_p (struct induction *, struct induction *); | |
315 | static int cmp_combine_givs_stats (const void *, const void *); | |
316 | static void combine_givs (struct loop_regs *, struct iv_class *); | |
317 | static int product_cheap_p (rtx, rtx); | |
318 | static int maybe_eliminate_biv (const struct loop *, struct iv_class *, int, | |
319 | int, int); | |
320 | static int maybe_eliminate_biv_1 (const struct loop *, rtx, rtx, | |
321 | struct iv_class *, int, basic_block, rtx); | |
322 | static int last_use_this_basic_block (rtx, rtx); | |
323 | static void record_initial (rtx, rtx, void *); | |
324 | static void update_reg_last_use (rtx, rtx); | |
325 | static rtx next_insn_in_loop (const struct loop *, rtx); | |
326 | static void loop_regs_scan (const struct loop *, int); | |
327 | static int count_insns_in_loop (const struct loop *); | |
328 | static int find_mem_in_note_1 (rtx *, void *); | |
329 | static rtx find_mem_in_note (rtx); | |
330 | static void load_mems (const struct loop *); | |
331 | static int insert_loop_mem (rtx *, void *); | |
332 | static int replace_loop_mem (rtx *, void *); | |
333 | static void replace_loop_mems (rtx, rtx, rtx, int); | |
334 | static int replace_loop_reg (rtx *, void *); | |
335 | static void replace_loop_regs (rtx insn, rtx, rtx); | |
336 | static void note_reg_stored (rtx, rtx, void *); | |
337 | static void try_copy_prop (const struct loop *, rtx, unsigned int); | |
338 | static void try_swap_copy_prop (const struct loop *, rtx, unsigned int); | |
339 | static rtx check_insn_for_givs (struct loop *, rtx, int, int); | |
340 | static rtx check_insn_for_bivs (struct loop *, rtx, int, int); | |
341 | static rtx gen_add_mult (rtx, rtx, rtx, rtx); | |
342 | static void loop_regs_update (const struct loop *, rtx); | |
343 | static int iv_add_mult_cost (rtx, rtx, rtx, rtx); | |
344 | ||
345 | static rtx loop_insn_emit_after (const struct loop *, basic_block, rtx, rtx); | |
346 | static rtx loop_call_insn_emit_before (const struct loop *, basic_block, | |
347 | rtx, rtx); | |
348 | static rtx loop_call_insn_hoist (const struct loop *, rtx); | |
349 | static rtx loop_insn_sink_or_swim (const struct loop *, rtx); | |
350 | ||
351 | static void loop_dump_aux (const struct loop *, FILE *, int); | |
352 | static void loop_delete_insns (rtx, rtx); | |
353 | static HOST_WIDE_INT remove_constant_addition (rtx *); | |
354 | static rtx gen_load_of_final_value (rtx, rtx); | |
355 | void debug_ivs (const struct loop *); | |
356 | void debug_iv_class (const struct iv_class *); | |
357 | void debug_biv (const struct induction *); | |
358 | void debug_giv (const struct induction *); | |
359 | void debug_loop (const struct loop *); | |
360 | void debug_loops (const struct loops *); | |
6057c0e6 | 361 | |
afa1738b MH |
362 | typedef struct loop_replace_args |
363 | { | |
364 | rtx match; | |
365 | rtx replacement; | |
366 | rtx insn; | |
367 | } loop_replace_args; | |
368 | ||
41a972a9 | 369 | /* Nonzero iff INSN is between START and END, inclusive. */ |
6b8c9327 AJ |
370 | #define INSN_IN_RANGE_P(INSN, START, END) \ |
371 | (INSN_UID (INSN) < max_uid_for_loop \ | |
41a972a9 MM |
372 | && INSN_LUID (INSN) >= INSN_LUID (START) \ |
373 | && INSN_LUID (INSN) <= INSN_LUID (END)) | |
8c660648 | 374 | |
2a1777af | 375 | /* Indirect_jump_in_function is computed once per function. */ |
5527bf14 | 376 | static int indirect_jump_in_function; |
0c20a65f | 377 | static int indirect_jump_in_function_p (rtx); |
2a1777af | 378 | |
0c20a65f | 379 | static int compute_luids (rtx, rtx, int); |
a6207a2b | 380 | |
0c20a65f AJ |
381 | static int biv_elimination_giv_has_0_offset (struct induction *, |
382 | struct induction *, rtx); | |
b4ad7b23 | 383 | \f |
b4ad7b23 RS |
384 | /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to |
385 | copy the value of the strength reduced giv to its original register. */ | |
45f97e2e RH |
386 | static int copy_cost; |
387 | ||
388 | /* Cost of using a register, to normalize the benefits of a giv. */ | |
389 | static int reg_address_cost; | |
390 | ||
b4ad7b23 | 391 | void |
0c20a65f | 392 | init_loop (void) |
b4ad7b23 | 393 | { |
38a448ca | 394 | rtx reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
b4ad7b23 | 395 | |
01329426 | 396 | reg_address_cost = address_cost (reg, SImode); |
45f97e2e | 397 | |
f1c1dfc3 | 398 | copy_cost = COSTS_N_INSNS (1); |
b4ad7b23 RS |
399 | } |
400 | \f | |
3ec2b590 R |
401 | /* Compute the mapping from uids to luids. |
402 | LUIDs are numbers assigned to insns, like uids, | |
403 | except that luids increase monotonically through the code. | |
404 | Start at insn START and stop just before END. Assign LUIDs | |
405 | starting with PREV_LUID + 1. Return the last assigned LUID + 1. */ | |
406 | static int | |
0c20a65f | 407 | compute_luids (rtx start, rtx end, int prev_luid) |
3ec2b590 R |
408 | { |
409 | int i; | |
410 | rtx insn; | |
411 | ||
412 | for (insn = start, i = prev_luid; insn != end; insn = NEXT_INSN (insn)) | |
413 | { | |
414 | if (INSN_UID (insn) >= max_uid_for_loop) | |
415 | continue; | |
416 | /* Don't assign luids to line-number NOTEs, so that the distance in | |
417 | luids between two insns is not affected by -g. */ | |
418 | if (GET_CODE (insn) != NOTE | |
419 | || NOTE_LINE_NUMBER (insn) <= 0) | |
420 | uid_luid[INSN_UID (insn)] = ++i; | |
421 | else | |
422 | /* Give a line number note the same luid as preceding insn. */ | |
423 | uid_luid[INSN_UID (insn)] = i; | |
424 | } | |
425 | return i + 1; | |
426 | } | |
427 | \f | |
b4ad7b23 RS |
428 | /* Entry point of this file. Perform loop optimization |
429 | on the current function. F is the first insn of the function | |
430 | and DUMPFILE is a stream for output of a trace of actions taken | |
431 | (or 0 if none should be output). */ | |
432 | ||
433 | void | |
0c20a65f | 434 | loop_optimize (rtx f, FILE *dumpfile, int flags) |
b4ad7b23 | 435 | { |
b3694847 SS |
436 | rtx insn; |
437 | int i; | |
a2be868f MH |
438 | struct loops loops_data; |
439 | struct loops *loops = &loops_data; | |
4cda35d4 | 440 | struct loop_info *loops_info; |
b4ad7b23 RS |
441 | |
442 | loop_dump_stream = dumpfile; | |
443 | ||
444 | init_recog_no_volatile (); | |
b4ad7b23 RS |
445 | |
446 | max_reg_before_loop = max_reg_num (); | |
0a326ec9 | 447 | loop_max_reg = max_reg_before_loop; |
b4ad7b23 | 448 | |
b4ad7b23 RS |
449 | regs_may_share = 0; |
450 | ||
0f41302f | 451 | /* Count the number of loops. */ |
b4ad7b23 RS |
452 | |
453 | max_loop_num = 0; | |
454 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
455 | { | |
456 | if (GET_CODE (insn) == NOTE | |
457 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
458 | max_loop_num++; | |
459 | } | |
460 | ||
461 | /* Don't waste time if no loops. */ | |
462 | if (max_loop_num == 0) | |
463 | return; | |
464 | ||
a2be868f MH |
465 | loops->num = max_loop_num; |
466 | ||
b4ad7b23 RS |
467 | /* Get size to use for tables indexed by uids. |
468 | Leave some space for labels allocated by find_and_verify_loops. */ | |
1c01e9df | 469 | max_uid_for_loop = get_max_uid () + 1 + max_loop_num * 32; |
b4ad7b23 | 470 | |
703ad42b KG |
471 | uid_luid = xcalloc (max_uid_for_loop, sizeof (int)); |
472 | uid_loop = xcalloc (max_uid_for_loop, sizeof (struct loop *)); | |
8c660648 | 473 | |
4cda35d4 | 474 | /* Allocate storage for array of loops. */ |
703ad42b | 475 | loops->array = xcalloc (loops->num, sizeof (struct loop)); |
4cda35d4 | 476 | |
b4ad7b23 RS |
477 | /* Find and process each loop. |
478 | First, find them, and record them in order of their beginnings. */ | |
a2be868f | 479 | find_and_verify_loops (f, loops); |
b4ad7b23 | 480 | |
4cda35d4 MH |
481 | /* Allocate and initialize auxiliary loop information. */ |
482 | loops_info = xcalloc (loops->num, sizeof (struct loop_info)); | |
3d436d2a | 483 | for (i = 0; i < (int) loops->num; i++) |
52b38064 | 484 | loops->array[i].aux = loops_info + i; |
4cda35d4 | 485 | |
b4ad7b23 RS |
486 | /* Now find all register lifetimes. This must be done after |
487 | find_and_verify_loops, because it might reorder the insns in the | |
488 | function. */ | |
0a326ec9 | 489 | reg_scan (f, max_reg_before_loop, 1); |
b4ad7b23 | 490 | |
7506f491 DE |
491 | /* This must occur after reg_scan so that registers created by gcse |
492 | will have entries in the register tables. | |
493 | ||
494 | We could have added a call to reg_scan after gcse_main in toplev.c, | |
495 | but moving this call to init_alias_analysis is more efficient. */ | |
496 | init_alias_analysis (); | |
497 | ||
e318cec0 R |
498 | /* See if we went too far. Note that get_max_uid already returns |
499 | one more that the maximum uid of all insn. */ | |
1c01e9df TW |
500 | if (get_max_uid () > max_uid_for_loop) |
501 | abort (); | |
f5963e61 | 502 | /* Now reset it to the actual size we need. See above. */ |
e318cec0 | 503 | max_uid_for_loop = get_max_uid (); |
1c01e9df | 504 | |
a2be868f MH |
505 | /* find_and_verify_loops has already called compute_luids, but it |
506 | might have rearranged code afterwards, so we need to recompute | |
507 | the luids now. */ | |
4977bab6 | 508 | compute_luids (f, NULL_RTX, 0); |
b4ad7b23 RS |
509 | |
510 | /* Don't leave gaps in uid_luid for insns that have been | |
511 | deleted. It is possible that the first or last insn | |
512 | using some register has been deleted by cross-jumping. | |
513 | Make sure that uid_luid for that former insn's uid | |
514 | points to the general area where that insn used to be. */ | |
515 | for (i = 0; i < max_uid_for_loop; i++) | |
516 | { | |
517 | uid_luid[0] = uid_luid[i]; | |
518 | if (uid_luid[0] != 0) | |
519 | break; | |
520 | } | |
521 | for (i = 0; i < max_uid_for_loop; i++) | |
522 | if (uid_luid[i] == 0) | |
523 | uid_luid[i] = uid_luid[i - 1]; | |
524 | ||
2a1777af JL |
525 | /* Determine if the function has indirect jump. On some systems |
526 | this prevents low overhead loop instructions from being used. */ | |
8c660648 | 527 | indirect_jump_in_function = indirect_jump_in_function_p (f); |
8c660648 | 528 | |
78458962 MH |
529 | /* Now scan the loops, last ones first, since this means inner ones are done |
530 | before outer ones. */ | |
531 | for (i = max_loop_num - 1; i >= 0; i--) | |
532 | { | |
533 | struct loop *loop = &loops->array[i]; | |
534 | ||
a2be868f | 535 | if (! loop->invalid && loop->end) |
1bf14ad7 | 536 | scan_loop (loop, flags); |
a2be868f | 537 | } |
07e857c2 | 538 | |
45f97e2e | 539 | end_alias_analysis (); |
67289ea6 MM |
540 | |
541 | /* Clean up. */ | |
67289ea6 | 542 | free (uid_luid); |
a2be868f | 543 | free (uid_loop); |
4cda35d4 MH |
544 | free (loops_info); |
545 | free (loops->array); | |
b4ad7b23 RS |
546 | } |
547 | \f | |
41a972a9 MM |
548 | /* Returns the next insn, in execution order, after INSN. START and |
549 | END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop, | |
0534b804 | 550 | respectively. LOOP->TOP, if non-NULL, is the top of the loop in the |
41a972a9 MM |
551 | insn-stream; it is used with loops that are entered near the |
552 | bottom. */ | |
553 | ||
554 | static rtx | |
0c20a65f | 555 | next_insn_in_loop (const struct loop *loop, rtx insn) |
41a972a9 MM |
556 | { |
557 | insn = NEXT_INSN (insn); | |
558 | ||
a2be868f | 559 | if (insn == loop->end) |
41a972a9 | 560 | { |
a2be868f | 561 | if (loop->top) |
41a972a9 | 562 | /* Go to the top of the loop, and continue there. */ |
a2be868f | 563 | insn = loop->top; |
41a972a9 MM |
564 | else |
565 | /* We're done. */ | |
566 | insn = NULL_RTX; | |
567 | } | |
568 | ||
a2be868f | 569 | if (insn == loop->scan_start) |
41a972a9 MM |
570 | /* We're done. */ |
571 | insn = NULL_RTX; | |
572 | ||
573 | return insn; | |
574 | } | |
575 | ||
a2be868f | 576 | /* Optimize one loop described by LOOP. */ |
b4ad7b23 RS |
577 | |
578 | /* ??? Could also move memory writes out of loops if the destination address | |
579 | is invariant, the source is invariant, the memory write is not volatile, | |
580 | and if we can prove that no read inside the loop can read this address | |
581 | before the write occurs. If there is a read of this address after the | |
582 | write, then we can also mark the memory read as invariant. */ | |
583 | ||
584 | static void | |
0c20a65f | 585 | scan_loop (struct loop *loop, int flags) |
b4ad7b23 | 586 | { |
1ecd860b MH |
587 | struct loop_info *loop_info = LOOP_INFO (loop); |
588 | struct loop_regs *regs = LOOP_REGS (loop); | |
b3694847 | 589 | int i; |
a2be868f MH |
590 | rtx loop_start = loop->start; |
591 | rtx loop_end = loop->end; | |
41a972a9 | 592 | rtx p; |
b4ad7b23 RS |
593 | /* 1 if we are scanning insns that could be executed zero times. */ |
594 | int maybe_never = 0; | |
595 | /* 1 if we are scanning insns that might never be executed | |
596 | due to a subroutine call which might exit before they are reached. */ | |
597 | int call_passed = 0; | |
b4ad7b23 RS |
598 | /* Number of insns in the loop. */ |
599 | int insn_count; | |
b4ad7b23 | 600 | int tem; |
0a326ec9 | 601 | rtx temp, update_start, update_end; |
b4ad7b23 RS |
602 | /* The SET from an insn, if it is the only SET in the insn. */ |
603 | rtx set, set1; | |
604 | /* Chain describing insns movable in current loop. */ | |
6ec92010 | 605 | struct loop_movables *movables = LOOP_MOVABLES (loop); |
b4ad7b23 RS |
606 | /* Ratio of extra register life span we can justify |
607 | for saving an instruction. More if loop doesn't call subroutines | |
608 | since in that case saving an insn makes more difference | |
609 | and more registers are available. */ | |
610 | int threshold; | |
5ea7a4ae JW |
611 | /* Nonzero if we are scanning instructions in a sub-loop. */ |
612 | int loop_depth = 0; | |
ed6cc1f5 | 613 | int in_libcall; |
a2be868f | 614 | |
afa1738b MH |
615 | loop->top = 0; |
616 | ||
02055ad6 MH |
617 | movables->head = 0; |
618 | movables->last = 0; | |
02055ad6 | 619 | |
b4ad7b23 RS |
620 | /* Determine whether this loop starts with a jump down to a test at |
621 | the end. This will occur for a small number of loops with a test | |
622 | that is too complex to duplicate in front of the loop. | |
623 | ||
624 | We search for the first insn or label in the loop, skipping NOTEs. | |
625 | However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG | |
626 | (because we might have a loop executed only once that contains a | |
627 | loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END | |
628 | (in case we have a degenerate loop). | |
629 | ||
630 | Note that if we mistakenly think that a loop is entered at the top | |
631 | when, in fact, it is entered at the exit test, the only effect will be | |
632 | slightly poorer optimization. Making the opposite error can generate | |
e6fcb60d | 633 | incorrect code. Since very few loops now start with a jump to the |
b4ad7b23 RS |
634 | exit test, the code here to detect that case is very conservative. */ |
635 | ||
636 | for (p = NEXT_INSN (loop_start); | |
a2be868f | 637 | p != loop_end |
2c3c49de | 638 | && GET_CODE (p) != CODE_LABEL && ! INSN_P (p) |
b4ad7b23 RS |
639 | && (GET_CODE (p) != NOTE |
640 | || (NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_BEG | |
641 | && NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_END)); | |
642 | p = NEXT_INSN (p)) | |
643 | ; | |
644 | ||
a2be868f | 645 | loop->scan_start = p; |
b4ad7b23 | 646 | |
96a45535 MH |
647 | /* If loop end is the end of the current function, then emit a |
648 | NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy | |
649 | note insn. This is the position we use when sinking insns out of | |
650 | the loop. */ | |
651 | if (NEXT_INSN (loop->end) != 0) | |
652 | loop->sink = NEXT_INSN (loop->end); | |
653 | else | |
654 | loop->sink = emit_note_after (NOTE_INSN_DELETED, loop->end); | |
655 | ||
b4ad7b23 | 656 | /* Set up variables describing this loop. */ |
a2be868f | 657 | prescan_loop (loop); |
3c748bb6 | 658 | threshold = (loop_info->has_call ? 1 : 2) * (1 + n_non_fixed_regs); |
b4ad7b23 RS |
659 | |
660 | /* If loop has a jump before the first label, | |
661 | the true entry is the target of that jump. | |
662 | Start scan from there. | |
a2be868f | 663 | But record in LOOP->TOP the place where the end-test jumps |
b4ad7b23 | 664 | back to so we can scan that after the end of the loop. */ |
4977bab6 | 665 | if (GET_CODE (p) == JUMP_INSN |
b4ad7b23 | 666 | /* Loop entry must be unconditional jump (and not a RETURN) */ |
4977bab6 ZW |
667 | && any_uncondjump_p (p) |
668 | && JUMP_LABEL (p) != 0 | |
669 | /* Check to see whether the jump actually | |
670 | jumps out of the loop (meaning it's no loop). | |
671 | This case can happen for things like | |
672 | do {..} while (0). If this label was generated previously | |
673 | by loop, we can't tell anything about it and have to reject | |
674 | the loop. */ | |
675 | && INSN_IN_RANGE_P (JUMP_LABEL (p), loop_start, loop_end)) | |
676 | { | |
677 | loop->top = next_label (loop->scan_start); | |
678 | loop->scan_start = JUMP_LABEL (p); | |
b4ad7b23 RS |
679 | } |
680 | ||
a2be868f | 681 | /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid |
b4ad7b23 | 682 | as required by loop_reg_used_before_p. So skip such loops. (This |
e6fcb60d | 683 | test may never be true, but it's best to play it safe.) |
b4ad7b23 RS |
684 | |
685 | Also, skip loops where we do not start scanning at a label. This | |
686 | test also rejects loops starting with a JUMP_INSN that failed the | |
687 | test above. */ | |
688 | ||
a2be868f MH |
689 | if (INSN_UID (loop->scan_start) >= max_uid_for_loop |
690 | || GET_CODE (loop->scan_start) != CODE_LABEL) | |
b4ad7b23 RS |
691 | { |
692 | if (loop_dump_stream) | |
693 | fprintf (loop_dump_stream, "\nLoop from %d to %d is phony.\n\n", | |
a2be868f | 694 | INSN_UID (loop_start), INSN_UID (loop_end)); |
b4ad7b23 RS |
695 | return; |
696 | } | |
697 | ||
1d7ae250 MH |
698 | /* Allocate extra space for REGs that might be created by load_mems. |
699 | We allocate a little extra slop as well, in the hopes that we | |
700 | won't have to reallocate the regs array. */ | |
28680540 MM |
701 | loop_regs_scan (loop, loop_info->mems_idx + 16); |
702 | insn_count = count_insns_in_loop (loop); | |
b4ad7b23 RS |
703 | |
704 | if (loop_dump_stream) | |
705 | { | |
706 | fprintf (loop_dump_stream, "\nLoop from %d to %d: %d real insns.\n", | |
a2be868f MH |
707 | INSN_UID (loop_start), INSN_UID (loop_end), insn_count); |
708 | if (loop->cont) | |
b4ad7b23 | 709 | fprintf (loop_dump_stream, "Continue at insn %d.\n", |
a2be868f | 710 | INSN_UID (loop->cont)); |
b4ad7b23 RS |
711 | } |
712 | ||
713 | /* Scan through the loop finding insns that are safe to move. | |
f1d4ac80 | 714 | Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that |
b4ad7b23 RS |
715 | this reg will be considered invariant for subsequent insns. |
716 | We consider whether subsequent insns use the reg | |
717 | in deciding whether it is worth actually moving. | |
718 | ||
719 | MAYBE_NEVER is nonzero if we have passed a conditional jump insn | |
720 | and therefore it is possible that the insns we are scanning | |
721 | would never be executed. At such times, we must make sure | |
722 | that it is safe to execute the insn once instead of zero times. | |
723 | When MAYBE_NEVER is 0, all insns will be executed at least once | |
724 | so that is not a problem. */ | |
725 | ||
ed6cc1f5 | 726 | for (in_libcall = 0, p = next_insn_in_loop (loop, loop->scan_start); |
41a972a9 | 727 | p != NULL_RTX; |
a2be868f | 728 | p = next_insn_in_loop (loop, p)) |
b4ad7b23 | 729 | { |
ed6cc1f5 R |
730 | if (in_libcall && INSN_P (p) && find_reg_note (p, REG_RETVAL, NULL_RTX)) |
731 | in_libcall--; | |
732 | if (GET_CODE (p) == INSN) | |
b4ad7b23 | 733 | { |
ed6cc1f5 | 734 | temp = find_reg_note (p, REG_LIBCALL, NULL_RTX); |
b4ad7b23 | 735 | if (temp) |
ed6cc1f5 R |
736 | in_libcall++; |
737 | if (! in_libcall | |
738 | && (set = single_set (p)) | |
739 | && GET_CODE (SET_DEST (set)) == REG | |
740 | #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
741 | && SET_DEST (set) != pic_offset_table_rtx | |
742 | #endif | |
743 | && ! regs->array[REGNO (SET_DEST (set))].may_not_optimize) | |
b4ad7b23 | 744 | { |
ed6cc1f5 R |
745 | int tem1 = 0; |
746 | int tem2 = 0; | |
747 | int move_insn = 0; | |
8f7ee471 | 748 | int insert_temp = 0; |
ed6cc1f5 R |
749 | rtx src = SET_SRC (set); |
750 | rtx dependencies = 0; | |
751 | ||
752 | /* Figure out what to use as a source of this insn. If a | |
753 | REG_EQUIV note is given or if a REG_EQUAL note with a | |
754 | constant operand is specified, use it as the source and | |
755 | mark that we should move this insn by calling | |
756 | emit_move_insn rather that duplicating the insn. | |
757 | ||
758 | Otherwise, only use the REG_EQUAL contents if a REG_RETVAL | |
759 | note is present. */ | |
760 | temp = find_reg_note (p, REG_EQUIV, NULL_RTX); | |
761 | if (temp) | |
b4ad7b23 | 762 | src = XEXP (temp, 0), move_insn = 1; |
ed6cc1f5 | 763 | else |
b4ad7b23 | 764 | { |
ed6cc1f5 R |
765 | temp = find_reg_note (p, REG_EQUAL, NULL_RTX); |
766 | if (temp && CONSTANT_P (XEXP (temp, 0))) | |
767 | src = XEXP (temp, 0), move_insn = 1; | |
768 | if (temp && find_reg_note (p, REG_RETVAL, NULL_RTX)) | |
769 | { | |
770 | src = XEXP (temp, 0); | |
771 | /* A libcall block can use regs that don't appear in | |
772 | the equivalent expression. To move the libcall, | |
773 | we must move those regs too. */ | |
774 | dependencies = libcall_other_reg (p, src); | |
775 | } | |
b4ad7b23 RS |
776 | } |
777 | ||
3d042e77 | 778 | /* For parallels, add any possible uses to the dependencies, as |
ed6cc1f5 R |
779 | we can't move the insn without resolving them first. */ |
780 | if (GET_CODE (PATTERN (p)) == PARALLEL) | |
b4ad7b23 | 781 | { |
ed6cc1f5 | 782 | for (i = 0; i < XVECLEN (PATTERN (p), 0); i++) |
b4ad7b23 | 783 | { |
ed6cc1f5 R |
784 | rtx x = XVECEXP (PATTERN (p), 0, i); |
785 | if (GET_CODE (x) == USE) | |
786 | dependencies | |
787 | = gen_rtx_EXPR_LIST (VOIDmode, XEXP (x, 0), | |
788 | dependencies); | |
b4ad7b23 | 789 | } |
b4ad7b23 | 790 | } |
ed6cc1f5 | 791 | |
8f7ee471 DJ |
792 | if (/* The register is used in basic blocks other |
793 | than the one where it is set (meaning that | |
794 | something after this point in the loop might | |
795 | depend on its value before the set). */ | |
796 | ! reg_in_basic_block_p (p, SET_DEST (set)) | |
797 | /* And the set is not guaranteed to be executed once | |
798 | the loop starts, or the value before the set is | |
799 | needed before the set occurs... | |
800 | ||
801 | ??? Note we have quadratic behavior here, mitigated | |
802 | by the fact that the previous test will often fail for | |
803 | large loops. Rather than re-scanning the entire loop | |
804 | each time for register usage, we should build tables | |
805 | of the register usage and use them here instead. */ | |
806 | && (maybe_never | |
807 | || loop_reg_used_before_p (loop, set, p))) | |
808 | /* It is unsafe to move the set. However, it may be OK to | |
0c20a65f | 809 | move the source into a new pseudo, and substitute a |
8f7ee471 DJ |
810 | reg-to-reg copy for the original insn. |
811 | ||
812 | This code used to consider it OK to move a set of a variable | |
813 | which was not created by the user and not used in an exit | |
814 | test. | |
815 | That behavior is incorrect and was removed. */ | |
816 | insert_temp = 1; | |
817 | ||
9feff114 JDA |
818 | /* Don't try to optimize a MODE_CC set with a constant |
819 | source. It probably will be combined with a conditional | |
820 | jump. */ | |
821 | if (GET_MODE_CLASS (GET_MODE (SET_DEST (set))) == MODE_CC | |
822 | && CONSTANT_P (src)) | |
823 | ; | |
ed6cc1f5 R |
824 | /* Don't try to optimize a register that was made |
825 | by loop-optimization for an inner loop. | |
826 | We don't know its life-span, so we can't compute | |
827 | the benefit. */ | |
9feff114 | 828 | else if (REGNO (SET_DEST (set)) >= max_reg_before_loop) |
ed6cc1f5 | 829 | ; |
773eae39 EB |
830 | /* Don't move the source and add a reg-to-reg copy: |
831 | - with -Os (this certainly increases size), | |
832 | - if the mode doesn't support copy operations (obviously), | |
833 | - if the source is already a reg (the motion will gain nothing), | |
834 | - if the source is a legitimate constant (likewise). */ | |
0c20a65f | 835 | else if (insert_temp |
773eae39 EB |
836 | && (optimize_size |
837 | || ! can_copy_p (GET_MODE (SET_SRC (set))) | |
838 | || GET_CODE (SET_SRC (set)) == REG | |
8f7ee471 DJ |
839 | || (CONSTANT_P (SET_SRC (set)) |
840 | && LEGITIMATE_CONSTANT_P (SET_SRC (set))))) | |
ed6cc1f5 R |
841 | ; |
842 | else if ((tem = loop_invariant_p (loop, src)) | |
843 | && (dependencies == 0 | |
844 | || (tem2 | |
845 | = loop_invariant_p (loop, dependencies)) != 0) | |
846 | && (regs->array[REGNO (SET_DEST (set))].set_in_loop == 1 | |
847 | || (tem1 | |
848 | = consec_sets_invariant_p | |
849 | (loop, SET_DEST (set), | |
850 | regs->array[REGNO (SET_DEST (set))].set_in_loop, | |
851 | p))) | |
852 | /* If the insn can cause a trap (such as divide by zero), | |
853 | can't move it unless it's guaranteed to be executed | |
854 | once loop is entered. Even a function call might | |
855 | prevent the trap insn from being reached | |
856 | (since it might exit!) */ | |
857 | && ! ((maybe_never || call_passed) | |
858 | && may_trap_p (src))) | |
b4ad7b23 | 859 | { |
b3694847 | 860 | struct movable *m; |
ed6cc1f5 R |
861 | int regno = REGNO (SET_DEST (set)); |
862 | ||
863 | /* A potential lossage is where we have a case where two insns | |
864 | can be combined as long as they are both in the loop, but | |
865 | we move one of them outside the loop. For large loops, | |
866 | this can lose. The most common case of this is the address | |
867 | of a function being called. | |
868 | ||
869 | Therefore, if this register is marked as being used | |
870 | exactly once if we are in a loop with calls | |
871 | (a "large loop"), see if we can replace the usage of | |
872 | this register with the source of this SET. If we can, | |
873 | delete this insn. | |
874 | ||
875 | Don't do this if P has a REG_RETVAL note or if we have | |
876 | SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */ | |
877 | ||
878 | if (loop_info->has_call | |
879 | && regs->array[regno].single_usage != 0 | |
880 | && regs->array[regno].single_usage != const0_rtx | |
881 | && REGNO_FIRST_UID (regno) == INSN_UID (p) | |
882 | && (REGNO_LAST_UID (regno) | |
883 | == INSN_UID (regs->array[regno].single_usage)) | |
884 | && regs->array[regno].set_in_loop == 1 | |
885 | && GET_CODE (SET_SRC (set)) != ASM_OPERANDS | |
886 | && ! side_effects_p (SET_SRC (set)) | |
887 | && ! find_reg_note (p, REG_RETVAL, NULL_RTX) | |
888 | && (! SMALL_REGISTER_CLASSES | |
889 | || (! (GET_CODE (SET_SRC (set)) == REG | |
890 | && (REGNO (SET_SRC (set)) | |
891 | < FIRST_PSEUDO_REGISTER)))) | |
892 | /* This test is not redundant; SET_SRC (set) might be | |
893 | a call-clobbered register and the life of REGNO | |
894 | might span a call. */ | |
895 | && ! modified_between_p (SET_SRC (set), p, | |
896 | regs->array[regno].single_usage) | |
897 | && no_labels_between_p (p, | |
898 | regs->array[regno].single_usage) | |
899 | && validate_replace_rtx (SET_DEST (set), SET_SRC (set), | |
900 | regs->array[regno].single_usage)) | |
901 | { | |
902 | /* Replace any usage in a REG_EQUAL note. Must copy | |
903 | the new source, so that we don't get rtx sharing | |
904 | between the SET_SOURCE and REG_NOTES of insn p. */ | |
905 | REG_NOTES (regs->array[regno].single_usage) | |
906 | = (replace_rtx | |
907 | (REG_NOTES (regs->array[regno].single_usage), | |
908 | SET_DEST (set), copy_rtx (SET_SRC (set)))); | |
909 | ||
910 | delete_insn (p); | |
911 | for (i = 0; i < LOOP_REGNO_NREGS (regno, SET_DEST (set)); | |
912 | i++) | |
913 | regs->array[regno+i].set_in_loop = 0; | |
914 | continue; | |
915 | } | |
916 | ||
703ad42b | 917 | m = xmalloc (sizeof (struct movable)); |
b4ad7b23 RS |
918 | m->next = 0; |
919 | m->insn = p; | |
ed6cc1f5 R |
920 | m->set_src = src; |
921 | m->dependencies = dependencies; | |
b4ad7b23 | 922 | m->set_dest = SET_DEST (set); |
b4ad7b23 | 923 | m->force = 0; |
ed6cc1f5 R |
924 | m->consec |
925 | = regs->array[REGNO (SET_DEST (set))].set_in_loop - 1; | |
b4ad7b23 RS |
926 | m->done = 0; |
927 | m->forces = 0; | |
ed6cc1f5 R |
928 | m->partial = 0; |
929 | m->move_insn = move_insn; | |
8cf619da | 930 | m->move_insn_first = 0; |
8f7ee471 | 931 | m->insert_temp = insert_temp; |
ed6cc1f5 R |
932 | m->is_equiv = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0); |
933 | m->savemode = VOIDmode; | |
b4ad7b23 | 934 | m->regno = regno; |
ed6cc1f5 R |
935 | /* Set M->cond if either loop_invariant_p |
936 | or consec_sets_invariant_p returned 2 | |
937 | (only conditionally invariant). */ | |
938 | m->cond = ((tem | tem1 | tem2) > 1); | |
939 | m->global = LOOP_REG_GLOBAL_P (loop, regno); | |
b4ad7b23 | 940 | m->match = 0; |
b8056b46 | 941 | m->lifetime = LOOP_REG_LIFETIME (loop, regno); |
ed6cc1f5 R |
942 | m->savings = regs->array[regno].n_times_set; |
943 | if (find_reg_note (p, REG_RETVAL, NULL_RTX)) | |
944 | m->savings += libcall_benefit (p); | |
44a5565d | 945 | for (i = 0; i < LOOP_REGNO_NREGS (regno, SET_DEST (set)); i++) |
ed6cc1f5 | 946 | regs->array[regno+i].set_in_loop = move_insn ? -2 : -1; |
b4ad7b23 | 947 | /* Add M to the end of the chain MOVABLES. */ |
6ec92010 | 948 | loop_movables_add (movables, m); |
ed6cc1f5 R |
949 | |
950 | if (m->consec > 0) | |
951 | { | |
952 | /* It is possible for the first instruction to have a | |
953 | REG_EQUAL note but a non-invariant SET_SRC, so we must | |
954 | remember the status of the first instruction in case | |
955 | the last instruction doesn't have a REG_EQUAL note. */ | |
956 | m->move_insn_first = m->move_insn; | |
957 | ||
958 | /* Skip this insn, not checking REG_LIBCALL notes. */ | |
959 | p = next_nonnote_insn (p); | |
960 | /* Skip the consecutive insns, if there are any. */ | |
961 | p = skip_consec_insns (p, m->consec); | |
962 | /* Back up to the last insn of the consecutive group. */ | |
963 | p = prev_nonnote_insn (p); | |
964 | ||
965 | /* We must now reset m->move_insn, m->is_equiv, and | |
966 | possibly m->set_src to correspond to the effects of | |
967 | all the insns. */ | |
968 | temp = find_reg_note (p, REG_EQUIV, NULL_RTX); | |
969 | if (temp) | |
970 | m->set_src = XEXP (temp, 0), m->move_insn = 1; | |
971 | else | |
972 | { | |
973 | temp = find_reg_note (p, REG_EQUAL, NULL_RTX); | |
974 | if (temp && CONSTANT_P (XEXP (temp, 0))) | |
975 | m->set_src = XEXP (temp, 0), m->move_insn = 1; | |
976 | else | |
977 | m->move_insn = 0; | |
978 | ||
979 | } | |
980 | m->is_equiv | |
981 | = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0); | |
982 | } | |
983 | } | |
984 | /* If this register is always set within a STRICT_LOW_PART | |
985 | or set to zero, then its high bytes are constant. | |
986 | So clear them outside the loop and within the loop | |
987 | just load the low bytes. | |
988 | We must check that the machine has an instruction to do so. | |
989 | Also, if the value loaded into the register | |
990 | depends on the same register, this cannot be done. */ | |
991 | else if (SET_SRC (set) == const0_rtx | |
992 | && GET_CODE (NEXT_INSN (p)) == INSN | |
993 | && (set1 = single_set (NEXT_INSN (p))) | |
994 | && GET_CODE (set1) == SET | |
995 | && (GET_CODE (SET_DEST (set1)) == STRICT_LOW_PART) | |
996 | && (GET_CODE (XEXP (SET_DEST (set1), 0)) == SUBREG) | |
997 | && (SUBREG_REG (XEXP (SET_DEST (set1), 0)) | |
998 | == SET_DEST (set)) | |
999 | && !reg_mentioned_p (SET_DEST (set), SET_SRC (set1))) | |
1000 | { | |
1001 | int regno = REGNO (SET_DEST (set)); | |
1002 | if (regs->array[regno].set_in_loop == 2) | |
1003 | { | |
1004 | struct movable *m; | |
703ad42b | 1005 | m = xmalloc (sizeof (struct movable)); |
ed6cc1f5 R |
1006 | m->next = 0; |
1007 | m->insn = p; | |
1008 | m->set_dest = SET_DEST (set); | |
1009 | m->dependencies = 0; | |
1010 | m->force = 0; | |
1011 | m->consec = 0; | |
1012 | m->done = 0; | |
1013 | m->forces = 0; | |
1014 | m->move_insn = 0; | |
1015 | m->move_insn_first = 0; | |
8f7ee471 | 1016 | m->insert_temp = insert_temp; |
ed6cc1f5 R |
1017 | m->partial = 1; |
1018 | /* If the insn may not be executed on some cycles, | |
1019 | we can't clear the whole reg; clear just high part. | |
1020 | Not even if the reg is used only within this loop. | |
1021 | Consider this: | |
1022 | while (1) | |
1023 | while (s != t) { | |
1024 | if (foo ()) x = *s; | |
1025 | use (x); | |
1026 | } | |
1027 | Clearing x before the inner loop could clobber a value | |
1028 | being saved from the last time around the outer loop. | |
1029 | However, if the reg is not used outside this loop | |
1030 | and all uses of the register are in the same | |
1031 | basic block as the store, there is no problem. | |
1032 | ||
1033 | If this insn was made by loop, we don't know its | |
1034 | INSN_LUID and hence must make a conservative | |
1035 | assumption. */ | |
1036 | m->global = (INSN_UID (p) >= max_uid_for_loop | |
1037 | || LOOP_REG_GLOBAL_P (loop, regno) | |
1038 | || (labels_in_range_p | |
1039 | (p, REGNO_FIRST_LUID (regno)))); | |
1040 | if (maybe_never && m->global) | |
1041 | m->savemode = GET_MODE (SET_SRC (set1)); | |
1042 | else | |
1043 | m->savemode = VOIDmode; | |
1044 | m->regno = regno; | |
1045 | m->cond = 0; | |
1046 | m->match = 0; | |
1047 | m->lifetime = LOOP_REG_LIFETIME (loop, regno); | |
1048 | m->savings = 1; | |
1049 | for (i = 0; | |
44a5565d | 1050 | i < LOOP_REGNO_NREGS (regno, SET_DEST (set)); |
ed6cc1f5 R |
1051 | i++) |
1052 | regs->array[regno+i].set_in_loop = -1; | |
1053 | /* Add M to the end of the chain MOVABLES. */ | |
1054 | loop_movables_add (movables, m); | |
1055 | } | |
b4ad7b23 RS |
1056 | } |
1057 | } | |
1058 | } | |
1059 | /* Past a call insn, we get to insns which might not be executed | |
1060 | because the call might exit. This matters for insns that trap. | |
e76d9acb | 1061 | Constant and pure call insns always return, so they don't count. */ |
24a28584 | 1062 | else if (GET_CODE (p) == CALL_INSN && ! CONST_OR_PURE_CALL_P (p)) |
b4ad7b23 RS |
1063 | call_passed = 1; |
1064 | /* Past a label or a jump, we get to insns for which we | |
1065 | can't count on whether or how many times they will be | |
1066 | executed during each iteration. Therefore, we can | |
1067 | only move out sets of trivial variables | |
1068 | (those not used after the loop). */ | |
8516af93 | 1069 | /* Similar code appears twice in strength_reduce. */ |
b4ad7b23 RS |
1070 | else if ((GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) |
1071 | /* If we enter the loop in the middle, and scan around to the | |
1072 | beginning, don't set maybe_never for that. This must be an | |
1073 | unconditional jump, otherwise the code at the top of the | |
1074 | loop might never be executed. Unconditional jumps are | |
fb530c07 | 1075 | followed by a barrier then the loop_end. */ |
e11e816e | 1076 | && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop->top |
a2be868f | 1077 | && NEXT_INSN (NEXT_INSN (p)) == loop_end |
7f1c097d | 1078 | && any_uncondjump_p (p))) |
b4ad7b23 | 1079 | maybe_never = 1; |
5ea7a4ae JW |
1080 | else if (GET_CODE (p) == NOTE) |
1081 | { | |
1082 | /* At the virtual top of a converted loop, insns are again known to | |
1083 | be executed: logically, the loop begins here even though the exit | |
1084 | code has been duplicated. */ | |
1085 | if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP && loop_depth == 0) | |
1086 | maybe_never = call_passed = 0; | |
1087 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) | |
1088 | loop_depth++; | |
1089 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END) | |
1090 | loop_depth--; | |
1091 | } | |
b4ad7b23 RS |
1092 | } |
1093 | ||
1094 | /* If one movable subsumes another, ignore that other. */ | |
1095 | ||
1096 | ignore_some_movables (movables); | |
1097 | ||
1098 | /* For each movable insn, see if the reg that it loads | |
1099 | leads when it dies right into another conditionally movable insn. | |
1100 | If so, record that the second insn "forces" the first one, | |
1101 | since the second can be moved only if the first is. */ | |
1102 | ||
1103 | force_movables (movables); | |
1104 | ||
1105 | /* See if there are multiple movable insns that load the same value. | |
1106 | If there are, make all but the first point at the first one | |
1107 | through the `match' field, and add the priorities of them | |
1108 | all together as the priority of the first. */ | |
1109 | ||
1ecd860b | 1110 | combine_movables (movables, regs); |
e6fcb60d | 1111 | |
b4ad7b23 | 1112 | /* Now consider each movable insn to decide whether it is worth moving. |
f1d4ac80 | 1113 | Store 0 in regs->array[I].set_in_loop for each reg I that is moved. |
b4ad7b23 | 1114 | |
fe352c29 | 1115 | For machines with few registers this increases code size, so do not |
0c20a65f | 1116 | move moveables when optimizing for code size on such machines. |
fe352c29 | 1117 | (The 18 below is the value for i386.) */ |
9dd07f87 | 1118 | |
0c20a65f | 1119 | if (!optimize_size |
fe352c29 | 1120 | || (reg_class_size[GENERAL_REGS] > 18 && !loop_info->has_call)) |
44c5edc0 JJ |
1121 | { |
1122 | move_movables (loop, movables, threshold, insn_count); | |
1123 | ||
1124 | /* Recalculate regs->array if move_movables has created new | |
1125 | registers. */ | |
1126 | if (max_reg_num () > regs->num) | |
1127 | { | |
1128 | loop_regs_scan (loop, 0); | |
1129 | for (update_start = loop_start; | |
1130 | PREV_INSN (update_start) | |
1131 | && GET_CODE (PREV_INSN (update_start)) != CODE_LABEL; | |
1132 | update_start = PREV_INSN (update_start)) | |
1133 | ; | |
1134 | update_end = NEXT_INSN (loop_end); | |
1135 | ||
1136 | reg_scan_update (update_start, update_end, loop_max_reg); | |
1137 | loop_max_reg = max_reg_num (); | |
1138 | } | |
1139 | } | |
b4ad7b23 RS |
1140 | |
1141 | /* Now candidates that still are negative are those not moved. | |
f1d4ac80 | 1142 | Change regs->array[I].set_in_loop to indicate that those are not actually |
1ecd860b | 1143 | invariant. */ |
f1d4ac80 MH |
1144 | for (i = 0; i < regs->num; i++) |
1145 | if (regs->array[i].set_in_loop < 0) | |
1146 | regs->array[i].set_in_loop = regs->array[i].n_times_set; | |
b4ad7b23 | 1147 | |
3ec2b590 | 1148 | /* Now that we've moved some things out of the loop, we might be able to |
d6b44532 | 1149 | hoist even more memory references. */ |
1d7ae250 MH |
1150 | load_mems (loop); |
1151 | ||
1152 | /* Recalculate regs->array if load_mems has created new registers. */ | |
1153 | if (max_reg_num () > regs->num) | |
28680540 | 1154 | loop_regs_scan (loop, 0); |
4b259e3f | 1155 | |
0a326ec9 | 1156 | for (update_start = loop_start; |
0534b804 MH |
1157 | PREV_INSN (update_start) |
1158 | && GET_CODE (PREV_INSN (update_start)) != CODE_LABEL; | |
0a326ec9 BS |
1159 | update_start = PREV_INSN (update_start)) |
1160 | ; | |
a2be868f | 1161 | update_end = NEXT_INSN (loop_end); |
0a326ec9 BS |
1162 | |
1163 | reg_scan_update (update_start, update_end, loop_max_reg); | |
1164 | loop_max_reg = max_reg_num (); | |
1165 | ||
b4ad7b23 | 1166 | if (flag_strength_reduce) |
45f97e2e | 1167 | { |
bb45bd5a JJ |
1168 | if (update_end && GET_CODE (update_end) == CODE_LABEL) |
1169 | /* Ensure our label doesn't go away. */ | |
1170 | LABEL_NUSES (update_end)++; | |
1171 | ||
28680540 | 1172 | strength_reduce (loop, flags); |
0a326ec9 BS |
1173 | |
1174 | reg_scan_update (update_start, update_end, loop_max_reg); | |
1175 | loop_max_reg = max_reg_num (); | |
bb45bd5a JJ |
1176 | |
1177 | if (update_end && GET_CODE (update_end) == CODE_LABEL | |
1178 | && --LABEL_NUSES (update_end) == 0) | |
53c17031 | 1179 | delete_related_insns (update_end); |
45f97e2e | 1180 | } |
8deb8e2c | 1181 | |
6ec92010 MH |
1182 | |
1183 | /* The movable information is required for strength reduction. */ | |
1184 | loop_movables_free (movables); | |
1185 | ||
f1d4ac80 MH |
1186 | free (regs->array); |
1187 | regs->array = 0; | |
1188 | regs->num = 0; | |
b4ad7b23 RS |
1189 | } |
1190 | \f | |
1191 | /* Add elements to *OUTPUT to record all the pseudo-regs | |
1192 | mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */ | |
1193 | ||
1194 | void | |
0c20a65f | 1195 | record_excess_regs (rtx in_this, rtx not_in_this, rtx *output) |
b4ad7b23 RS |
1196 | { |
1197 | enum rtx_code code; | |
6f7d635c | 1198 | const char *fmt; |
b4ad7b23 RS |
1199 | int i; |
1200 | ||
1201 | code = GET_CODE (in_this); | |
1202 | ||
1203 | switch (code) | |
1204 | { | |
1205 | case PC: | |
1206 | case CC0: | |
1207 | case CONST_INT: | |
1208 | case CONST_DOUBLE: | |
1209 | case CONST: | |
1210 | case SYMBOL_REF: | |
1211 | case LABEL_REF: | |
1212 | return; | |
1213 | ||
1214 | case REG: | |
1215 | if (REGNO (in_this) >= FIRST_PSEUDO_REGISTER | |
1216 | && ! reg_mentioned_p (in_this, not_in_this)) | |
38a448ca | 1217 | *output = gen_rtx_EXPR_LIST (VOIDmode, in_this, *output); |
b4ad7b23 | 1218 | return; |
e6fcb60d | 1219 | |
e9a25f70 JL |
1220 | default: |
1221 | break; | |
b4ad7b23 RS |
1222 | } |
1223 | ||
1224 | fmt = GET_RTX_FORMAT (code); | |
1225 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1226 | { | |
1227 | int j; | |
1228 | ||
1229 | switch (fmt[i]) | |
1230 | { | |
1231 | case 'E': | |
1232 | for (j = 0; j < XVECLEN (in_this, i); j++) | |
1233 | record_excess_regs (XVECEXP (in_this, i, j), not_in_this, output); | |
1234 | break; | |
1235 | ||
1236 | case 'e': | |
1237 | record_excess_regs (XEXP (in_this, i), not_in_this, output); | |
1238 | break; | |
1239 | } | |
1240 | } | |
1241 | } | |
1242 | \f | |
1243 | /* Check what regs are referred to in the libcall block ending with INSN, | |
1244 | aside from those mentioned in the equivalent value. | |
1245 | If there are none, return 0. | |
1246 | If there are one or more, return an EXPR_LIST containing all of them. */ | |
1247 | ||
89d3d442 | 1248 | rtx |
0c20a65f | 1249 | libcall_other_reg (rtx insn, rtx equiv) |
b4ad7b23 | 1250 | { |
5fd8383e | 1251 | rtx note = find_reg_note (insn, REG_RETVAL, NULL_RTX); |
b4ad7b23 RS |
1252 | rtx p = XEXP (note, 0); |
1253 | rtx output = 0; | |
1254 | ||
1255 | /* First, find all the regs used in the libcall block | |
1256 | that are not mentioned as inputs to the result. */ | |
1257 | ||
1258 | while (p != insn) | |
1259 | { | |
1260 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN | |
1261 | || GET_CODE (p) == CALL_INSN) | |
1262 | record_excess_regs (PATTERN (p), equiv, &output); | |
1263 | p = NEXT_INSN (p); | |
1264 | } | |
1265 | ||
1266 | return output; | |
1267 | } | |
1268 | \f | |
1269 | /* Return 1 if all uses of REG | |
1270 | are between INSN and the end of the basic block. */ | |
1271 | ||
e6fcb60d | 1272 | static int |
0c20a65f | 1273 | reg_in_basic_block_p (rtx insn, rtx reg) |
b4ad7b23 RS |
1274 | { |
1275 | int regno = REGNO (reg); | |
1276 | rtx p; | |
1277 | ||
b1f21e0a | 1278 | if (REGNO_FIRST_UID (regno) != INSN_UID (insn)) |
b4ad7b23 RS |
1279 | return 0; |
1280 | ||
1281 | /* Search this basic block for the already recorded last use of the reg. */ | |
1282 | for (p = insn; p; p = NEXT_INSN (p)) | |
1283 | { | |
1284 | switch (GET_CODE (p)) | |
1285 | { | |
1286 | case NOTE: | |
1287 | break; | |
1288 | ||
1289 | case INSN: | |
1290 | case CALL_INSN: | |
1291 | /* Ordinary insn: if this is the last use, we win. */ | |
b1f21e0a | 1292 | if (REGNO_LAST_UID (regno) == INSN_UID (p)) |
b4ad7b23 RS |
1293 | return 1; |
1294 | break; | |
1295 | ||
1296 | case JUMP_INSN: | |
1297 | /* Jump insn: if this is the last use, we win. */ | |
b1f21e0a | 1298 | if (REGNO_LAST_UID (regno) == INSN_UID (p)) |
b4ad7b23 RS |
1299 | return 1; |
1300 | /* Otherwise, it's the end of the basic block, so we lose. */ | |
1301 | return 0; | |
1302 | ||
1303 | case CODE_LABEL: | |
1304 | case BARRIER: | |
1305 | /* It's the end of the basic block, so we lose. */ | |
1306 | return 0; | |
e6fcb60d | 1307 | |
e9a25f70 JL |
1308 | default: |
1309 | break; | |
b4ad7b23 RS |
1310 | } |
1311 | } | |
1312 | ||
035a6890 R |
1313 | /* The "last use" that was recorded can't be found after the first |
1314 | use. This can happen when the last use was deleted while | |
1315 | processing an inner loop, this inner loop was then completely | |
1316 | unrolled, and the outer loop is always exited after the inner loop, | |
1317 | so that everything after the first use becomes a single basic block. */ | |
1318 | return 1; | |
b4ad7b23 RS |
1319 | } |
1320 | \f | |
1321 | /* Compute the benefit of eliminating the insns in the block whose | |
1322 | last insn is LAST. This may be a group of insns used to compute a | |
1323 | value directly or can contain a library call. */ | |
1324 | ||
1325 | static int | |
0c20a65f | 1326 | libcall_benefit (rtx last) |
b4ad7b23 RS |
1327 | { |
1328 | rtx insn; | |
1329 | int benefit = 0; | |
1330 | ||
5fd8383e | 1331 | for (insn = XEXP (find_reg_note (last, REG_RETVAL, NULL_RTX), 0); |
b4ad7b23 RS |
1332 | insn != last; insn = NEXT_INSN (insn)) |
1333 | { | |
1334 | if (GET_CODE (insn) == CALL_INSN) | |
1335 | benefit += 10; /* Assume at least this many insns in a library | |
0f41302f | 1336 | routine. */ |
b4ad7b23 RS |
1337 | else if (GET_CODE (insn) == INSN |
1338 | && GET_CODE (PATTERN (insn)) != USE | |
1339 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
1340 | benefit++; | |
1341 | } | |
1342 | ||
1343 | return benefit; | |
1344 | } | |
1345 | \f | |
1346 | /* Skip COUNT insns from INSN, counting library calls as 1 insn. */ | |
1347 | ||
1348 | static rtx | |
0c20a65f | 1349 | skip_consec_insns (rtx insn, int count) |
b4ad7b23 RS |
1350 | { |
1351 | for (; count > 0; count--) | |
1352 | { | |
1353 | rtx temp; | |
1354 | ||
1355 | /* If first insn of libcall sequence, skip to end. */ | |
e6fcb60d | 1356 | /* Do this at start of loop, since INSN is guaranteed to |
b4ad7b23 RS |
1357 | be an insn here. */ |
1358 | if (GET_CODE (insn) != NOTE | |
5fd8383e | 1359 | && (temp = find_reg_note (insn, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
1360 | insn = XEXP (temp, 0); |
1361 | ||
e6fcb60d KH |
1362 | do |
1363 | insn = NEXT_INSN (insn); | |
b4ad7b23 RS |
1364 | while (GET_CODE (insn) == NOTE); |
1365 | } | |
1366 | ||
1367 | return insn; | |
1368 | } | |
1369 | ||
1370 | /* Ignore any movable whose insn falls within a libcall | |
1371 | which is part of another movable. | |
1372 | We make use of the fact that the movable for the libcall value | |
1373 | was made later and so appears later on the chain. */ | |
1374 | ||
1375 | static void | |
0c20a65f | 1376 | ignore_some_movables (struct loop_movables *movables) |
b4ad7b23 | 1377 | { |
b3694847 | 1378 | struct movable *m, *m1; |
b4ad7b23 | 1379 | |
02055ad6 | 1380 | for (m = movables->head; m; m = m->next) |
b4ad7b23 RS |
1381 | { |
1382 | /* Is this a movable for the value of a libcall? */ | |
5fd8383e | 1383 | rtx note = find_reg_note (m->insn, REG_RETVAL, NULL_RTX); |
b4ad7b23 RS |
1384 | if (note) |
1385 | { | |
1386 | rtx insn; | |
1387 | /* Check for earlier movables inside that range, | |
1388 | and mark them invalid. We cannot use LUIDs here because | |
1389 | insns created by loop.c for prior loops don't have LUIDs. | |
1390 | Rather than reject all such insns from movables, we just | |
1391 | explicitly check each insn in the libcall (since invariant | |
1392 | libcalls aren't that common). */ | |
1393 | for (insn = XEXP (note, 0); insn != m->insn; insn = NEXT_INSN (insn)) | |
02055ad6 | 1394 | for (m1 = movables->head; m1 != m; m1 = m1->next) |
b4ad7b23 RS |
1395 | if (m1->insn == insn) |
1396 | m1->done = 1; | |
1397 | } | |
1398 | } | |
e6fcb60d | 1399 | } |
b4ad7b23 RS |
1400 | |
1401 | /* For each movable insn, see if the reg that it loads | |
1402 | leads when it dies right into another conditionally movable insn. | |
1403 | If so, record that the second insn "forces" the first one, | |
1404 | since the second can be moved only if the first is. */ | |
1405 | ||
1406 | static void | |
0c20a65f | 1407 | force_movables (struct loop_movables *movables) |
b4ad7b23 | 1408 | { |
b3694847 SS |
1409 | struct movable *m, *m1; |
1410 | ||
02055ad6 | 1411 | for (m1 = movables->head; m1; m1 = m1->next) |
b4ad7b23 RS |
1412 | /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */ |
1413 | if (!m1->partial && !m1->done) | |
1414 | { | |
1415 | int regno = m1->regno; | |
1416 | for (m = m1->next; m; m = m->next) | |
1417 | /* ??? Could this be a bug? What if CSE caused the | |
1418 | register of M1 to be used after this insn? | |
1419 | Since CSE does not update regno_last_uid, | |
1420 | this insn M->insn might not be where it dies. | |
1421 | But very likely this doesn't matter; what matters is | |
1422 | that M's reg is computed from M1's reg. */ | |
b1f21e0a | 1423 | if (INSN_UID (m->insn) == REGNO_LAST_UID (regno) |
b4ad7b23 RS |
1424 | && !m->done) |
1425 | break; | |
1426 | if (m != 0 && m->set_src == m1->set_dest | |
1427 | /* If m->consec, m->set_src isn't valid. */ | |
1428 | && m->consec == 0) | |
1429 | m = 0; | |
1430 | ||
1431 | /* Increase the priority of the moving the first insn | |
1432 | since it permits the second to be moved as well. */ | |
1433 | if (m != 0) | |
1434 | { | |
1435 | m->forces = m1; | |
1436 | m1->lifetime += m->lifetime; | |
3875b31d | 1437 | m1->savings += m->savings; |
b4ad7b23 RS |
1438 | } |
1439 | } | |
1440 | } | |
1441 | \f | |
1442 | /* Find invariant expressions that are equal and can be combined into | |
1443 | one register. */ | |
1444 | ||
1445 | static void | |
0c20a65f | 1446 | combine_movables (struct loop_movables *movables, struct loop_regs *regs) |
b4ad7b23 | 1447 | { |
b3694847 | 1448 | struct movable *m; |
703ad42b | 1449 | char *matched_regs = xmalloc (regs->num); |
b4ad7b23 RS |
1450 | enum machine_mode mode; |
1451 | ||
1452 | /* Regs that are set more than once are not allowed to match | |
1453 | or be matched. I'm no longer sure why not. */ | |
02a566dc DJ |
1454 | /* Only pseudo registers are allowed to match or be matched, |
1455 | since move_movables does not validate the change. */ | |
b4ad7b23 RS |
1456 | /* Perhaps testing m->consec_sets would be more appropriate here? */ |
1457 | ||
02055ad6 | 1458 | for (m = movables->head; m; m = m->next) |
f1d4ac80 | 1459 | if (m->match == 0 && regs->array[m->regno].n_times_set == 1 |
02a566dc | 1460 | && m->regno >= FIRST_PSEUDO_REGISTER |
8f7ee471 | 1461 | && !m->insert_temp |
e6fcb60d | 1462 | && !m->partial) |
b4ad7b23 | 1463 | { |
b3694847 | 1464 | struct movable *m1; |
b4ad7b23 | 1465 | int regno = m->regno; |
b4ad7b23 | 1466 | |
961192e1 | 1467 | memset (matched_regs, 0, regs->num); |
b4ad7b23 RS |
1468 | matched_regs[regno] = 1; |
1469 | ||
88016fb7 DE |
1470 | /* We want later insns to match the first one. Don't make the first |
1471 | one match any later ones. So start this loop at m->next. */ | |
1472 | for (m1 = m->next; m1; m1 = m1->next) | |
02a566dc | 1473 | if (m != m1 && m1->match == 0 |
8f7ee471 | 1474 | && !m1->insert_temp |
f1d4ac80 | 1475 | && regs->array[m1->regno].n_times_set == 1 |
02a566dc | 1476 | && m1->regno >= FIRST_PSEUDO_REGISTER |
b4ad7b23 RS |
1477 | /* A reg used outside the loop mustn't be eliminated. */ |
1478 | && !m1->global | |
1479 | /* A reg used for zero-extending mustn't be eliminated. */ | |
1480 | && !m1->partial | |
1481 | && (matched_regs[m1->regno] | |
1482 | || | |
1483 | ( | |
1484 | /* Can combine regs with different modes loaded from the | |
1485 | same constant only if the modes are the same or | |
1486 | if both are integer modes with M wider or the same | |
1487 | width as M1. The check for integer is redundant, but | |
1488 | safe, since the only case of differing destination | |
1489 | modes with equal sources is when both sources are | |
1490 | VOIDmode, i.e., CONST_INT. */ | |
1491 | (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest) | |
1492 | || (GET_MODE_CLASS (GET_MODE (m->set_dest)) == MODE_INT | |
1493 | && GET_MODE_CLASS (GET_MODE (m1->set_dest)) == MODE_INT | |
1494 | && (GET_MODE_BITSIZE (GET_MODE (m->set_dest)) | |
1495 | >= GET_MODE_BITSIZE (GET_MODE (m1->set_dest))))) | |
1496 | /* See if the source of M1 says it matches M. */ | |
1497 | && ((GET_CODE (m1->set_src) == REG | |
1498 | && matched_regs[REGNO (m1->set_src)]) | |
1499 | || rtx_equal_for_loop_p (m->set_src, m1->set_src, | |
1ecd860b | 1500 | movables, regs)))) |
b4ad7b23 RS |
1501 | && ((m->dependencies == m1->dependencies) |
1502 | || rtx_equal_p (m->dependencies, m1->dependencies))) | |
1503 | { | |
1504 | m->lifetime += m1->lifetime; | |
1505 | m->savings += m1->savings; | |
1506 | m1->done = 1; | |
1507 | m1->match = m; | |
1508 | matched_regs[m1->regno] = 1; | |
1509 | } | |
1510 | } | |
1511 | ||
1512 | /* Now combine the regs used for zero-extension. | |
1513 | This can be done for those not marked `global' | |
1514 | provided their lives don't overlap. */ | |
1515 | ||
1516 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
1517 | mode = GET_MODE_WIDER_MODE (mode)) | |
1518 | { | |
b3694847 | 1519 | struct movable *m0 = 0; |
b4ad7b23 RS |
1520 | |
1521 | /* Combine all the registers for extension from mode MODE. | |
1522 | Don't combine any that are used outside this loop. */ | |
02055ad6 | 1523 | for (m = movables->head; m; m = m->next) |
b4ad7b23 RS |
1524 | if (m->partial && ! m->global |
1525 | && mode == GET_MODE (SET_SRC (PATTERN (NEXT_INSN (m->insn))))) | |
1526 | { | |
b3694847 SS |
1527 | struct movable *m1; |
1528 | ||
8529a489 MH |
1529 | int first = REGNO_FIRST_LUID (m->regno); |
1530 | int last = REGNO_LAST_LUID (m->regno); | |
b4ad7b23 RS |
1531 | |
1532 | if (m0 == 0) | |
1533 | { | |
1534 | /* First one: don't check for overlap, just record it. */ | |
1535 | m0 = m; | |
e6fcb60d | 1536 | continue; |
b4ad7b23 RS |
1537 | } |
1538 | ||
1539 | /* Make sure they extend to the same mode. | |
1540 | (Almost always true.) */ | |
1541 | if (GET_MODE (m->set_dest) != GET_MODE (m0->set_dest)) | |
e6fcb60d | 1542 | continue; |
b4ad7b23 RS |
1543 | |
1544 | /* We already have one: check for overlap with those | |
1545 | already combined together. */ | |
02055ad6 | 1546 | for (m1 = movables->head; m1 != m; m1 = m1->next) |
b4ad7b23 | 1547 | if (m1 == m0 || (m1->partial && m1->match == m0)) |
8529a489 MH |
1548 | if (! (REGNO_FIRST_LUID (m1->regno) > last |
1549 | || REGNO_LAST_LUID (m1->regno) < first)) | |
b4ad7b23 RS |
1550 | goto overlap; |
1551 | ||
1552 | /* No overlap: we can combine this with the others. */ | |
1553 | m0->lifetime += m->lifetime; | |
1554 | m0->savings += m->savings; | |
1555 | m->done = 1; | |
1556 | m->match = m0; | |
1557 | ||
e6fcb60d KH |
1558 | overlap: |
1559 | ; | |
b4ad7b23 RS |
1560 | } |
1561 | } | |
4da896b2 MM |
1562 | |
1563 | /* Clean up. */ | |
1564 | free (matched_regs); | |
b4ad7b23 | 1565 | } |
28680540 MM |
1566 | |
1567 | /* Returns the number of movable instructions in LOOP that were not | |
1568 | moved outside the loop. */ | |
1569 | ||
1570 | static int | |
0c20a65f | 1571 | num_unmoved_movables (const struct loop *loop) |
28680540 MM |
1572 | { |
1573 | int num = 0; | |
1574 | struct movable *m; | |
1575 | ||
1576 | for (m = LOOP_MOVABLES (loop)->head; m; m = m->next) | |
1577 | if (!m->done) | |
1578 | ++num; | |
1579 | ||
1580 | return num; | |
1581 | } | |
1582 | ||
b4ad7b23 RS |
1583 | \f |
1584 | /* Return 1 if regs X and Y will become the same if moved. */ | |
1585 | ||
1586 | static int | |
0c20a65f | 1587 | regs_match_p (rtx x, rtx y, struct loop_movables *movables) |
b4ad7b23 | 1588 | { |
770ae6cc RK |
1589 | unsigned int xn = REGNO (x); |
1590 | unsigned int yn = REGNO (y); | |
b4ad7b23 RS |
1591 | struct movable *mx, *my; |
1592 | ||
02055ad6 | 1593 | for (mx = movables->head; mx; mx = mx->next) |
b4ad7b23 RS |
1594 | if (mx->regno == xn) |
1595 | break; | |
1596 | ||
02055ad6 | 1597 | for (my = movables->head; my; my = my->next) |
b4ad7b23 RS |
1598 | if (my->regno == yn) |
1599 | break; | |
1600 | ||
1601 | return (mx && my | |
1602 | && ((mx->match == my->match && mx->match != 0) | |
1603 | || mx->match == my | |
1604 | || mx == my->match)); | |
1605 | } | |
1606 | ||
1607 | /* Return 1 if X and Y are identical-looking rtx's. | |
1608 | This is the Lisp function EQUAL for rtx arguments. | |
1609 | ||
1610 | If two registers are matching movables or a movable register and an | |
1611 | equivalent constant, consider them equal. */ | |
1612 | ||
1613 | static int | |
0c20a65f AJ |
1614 | rtx_equal_for_loop_p (rtx x, rtx y, struct loop_movables *movables, |
1615 | struct loop_regs *regs) | |
b4ad7b23 | 1616 | { |
b3694847 SS |
1617 | int i; |
1618 | int j; | |
1619 | struct movable *m; | |
1620 | enum rtx_code code; | |
1621 | const char *fmt; | |
b4ad7b23 RS |
1622 | |
1623 | if (x == y) | |
1624 | return 1; | |
1625 | if (x == 0 || y == 0) | |
1626 | return 0; | |
1627 | ||
1628 | code = GET_CODE (x); | |
1629 | ||
1630 | /* If we have a register and a constant, they may sometimes be | |
1631 | equal. */ | |
f1d4ac80 | 1632 | if (GET_CODE (x) == REG && regs->array[REGNO (x)].set_in_loop == -2 |
b4ad7b23 | 1633 | && CONSTANT_P (y)) |
b1a0c816 | 1634 | { |
02055ad6 | 1635 | for (m = movables->head; m; m = m->next) |
b1a0c816 JL |
1636 | if (m->move_insn && m->regno == REGNO (x) |
1637 | && rtx_equal_p (m->set_src, y)) | |
1638 | return 1; | |
1639 | } | |
f1d4ac80 | 1640 | else if (GET_CODE (y) == REG && regs->array[REGNO (y)].set_in_loop == -2 |
b4ad7b23 | 1641 | && CONSTANT_P (x)) |
b1a0c816 | 1642 | { |
02055ad6 | 1643 | for (m = movables->head; m; m = m->next) |
b1a0c816 JL |
1644 | if (m->move_insn && m->regno == REGNO (y) |
1645 | && rtx_equal_p (m->set_src, x)) | |
1646 | return 1; | |
1647 | } | |
b4ad7b23 RS |
1648 | |
1649 | /* Otherwise, rtx's of different codes cannot be equal. */ | |
1650 | if (code != GET_CODE (y)) | |
1651 | return 0; | |
1652 | ||
1653 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. | |
1654 | (REG:SI x) and (REG:HI x) are NOT equivalent. */ | |
1655 | ||
1656 | if (GET_MODE (x) != GET_MODE (y)) | |
1657 | return 0; | |
1658 | ||
1659 | /* These three types of rtx's can be compared nonrecursively. */ | |
1660 | if (code == REG) | |
1661 | return (REGNO (x) == REGNO (y) || regs_match_p (x, y, movables)); | |
1662 | ||
1663 | if (code == LABEL_REF) | |
1664 | return XEXP (x, 0) == XEXP (y, 0); | |
1665 | if (code == SYMBOL_REF) | |
1666 | return XSTR (x, 0) == XSTR (y, 0); | |
1667 | ||
1668 | /* Compare the elements. If any pair of corresponding elements | |
1669 | fail to match, return 0 for the whole things. */ | |
1670 | ||
1671 | fmt = GET_RTX_FORMAT (code); | |
1672 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1673 | { | |
1674 | switch (fmt[i]) | |
1675 | { | |
5fd8383e RK |
1676 | case 'w': |
1677 | if (XWINT (x, i) != XWINT (y, i)) | |
1678 | return 0; | |
1679 | break; | |
1680 | ||
b4ad7b23 RS |
1681 | case 'i': |
1682 | if (XINT (x, i) != XINT (y, i)) | |
1683 | return 0; | |
1684 | break; | |
1685 | ||
1686 | case 'E': | |
1687 | /* Two vectors must have the same length. */ | |
1688 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
1689 | return 0; | |
1690 | ||
1691 | /* And the corresponding elements must match. */ | |
1692 | for (j = 0; j < XVECLEN (x, i); j++) | |
1ecd860b MH |
1693 | if (rtx_equal_for_loop_p (XVECEXP (x, i, j), XVECEXP (y, i, j), |
1694 | movables, regs) == 0) | |
b4ad7b23 RS |
1695 | return 0; |
1696 | break; | |
1697 | ||
1698 | case 'e': | |
ed5bb68d MH |
1699 | if (rtx_equal_for_loop_p (XEXP (x, i), XEXP (y, i), movables, regs) |
1700 | == 0) | |
b4ad7b23 RS |
1701 | return 0; |
1702 | break; | |
1703 | ||
1704 | case 's': | |
1705 | if (strcmp (XSTR (x, i), XSTR (y, i))) | |
1706 | return 0; | |
1707 | break; | |
1708 | ||
1709 | case 'u': | |
1710 | /* These are just backpointers, so they don't matter. */ | |
1711 | break; | |
1712 | ||
1713 | case '0': | |
1714 | break; | |
1715 | ||
1716 | /* It is believed that rtx's at this level will never | |
1717 | contain anything but integers and other rtx's, | |
1718 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
1719 | default: | |
1720 | abort (); | |
1721 | } | |
1722 | } | |
1723 | return 1; | |
1724 | } | |
1725 | \f | |
c160c628 | 1726 | /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all |
5b1ef594 | 1727 | insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL |
dc297297 | 1728 | references is incremented once for each added note. */ |
c160c628 RK |
1729 | |
1730 | static void | |
0c20a65f | 1731 | add_label_notes (rtx x, rtx insns) |
c160c628 RK |
1732 | { |
1733 | enum rtx_code code = GET_CODE (x); | |
7dcd3836 | 1734 | int i, j; |
6f7d635c | 1735 | const char *fmt; |
c160c628 RK |
1736 | rtx insn; |
1737 | ||
82d00367 | 1738 | if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x)) |
c160c628 | 1739 | { |
6b3603c2 | 1740 | /* This code used to ignore labels that referred to dispatch tables to |
e0bb17a8 | 1741 | avoid flow generating (slightly) worse code. |
6b3603c2 JL |
1742 | |
1743 | We no longer ignore such label references (see LABEL_REF handling in | |
1744 | mark_jump_label for additional information). */ | |
1745 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
1746 | if (reg_mentioned_p (XEXP (x, 0), insn)) | |
5b1ef594 | 1747 | { |
6b8c9327 | 1748 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, XEXP (x, 0), |
5b1ef594 JDA |
1749 | REG_NOTES (insn)); |
1750 | if (LABEL_P (XEXP (x, 0))) | |
1751 | LABEL_NUSES (XEXP (x, 0))++; | |
1752 | } | |
c160c628 RK |
1753 | } |
1754 | ||
1755 | fmt = GET_RTX_FORMAT (code); | |
1756 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7dcd3836 RK |
1757 | { |
1758 | if (fmt[i] == 'e') | |
1759 | add_label_notes (XEXP (x, i), insns); | |
1760 | else if (fmt[i] == 'E') | |
1761 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1762 | add_label_notes (XVECEXP (x, i, j), insns); | |
1763 | } | |
c160c628 RK |
1764 | } |
1765 | \f | |
b4ad7b23 RS |
1766 | /* Scan MOVABLES, and move the insns that deserve to be moved. |
1767 | If two matching movables are combined, replace one reg with the | |
1768 | other throughout. */ | |
1769 | ||
1770 | static void | |
0c20a65f AJ |
1771 | move_movables (struct loop *loop, struct loop_movables *movables, |
1772 | int threshold, int insn_count) | |
b4ad7b23 | 1773 | { |
1ecd860b | 1774 | struct loop_regs *regs = LOOP_REGS (loop); |
ed5bb68d | 1775 | int nregs = regs->num; |
b4ad7b23 | 1776 | rtx new_start = 0; |
b3694847 SS |
1777 | struct movable *m; |
1778 | rtx p; | |
0534b804 MH |
1779 | rtx loop_start = loop->start; |
1780 | rtx loop_end = loop->end; | |
b4ad7b23 RS |
1781 | /* Map of pseudo-register replacements to handle combining |
1782 | when we move several insns that load the same value | |
1783 | into different pseudo-registers. */ | |
703ad42b KG |
1784 | rtx *reg_map = xcalloc (nregs, sizeof (rtx)); |
1785 | char *already_moved = xcalloc (nregs, sizeof (char)); | |
b4ad7b23 | 1786 | |
02055ad6 | 1787 | for (m = movables->head; m; m = m->next) |
b4ad7b23 RS |
1788 | { |
1789 | /* Describe this movable insn. */ | |
1790 | ||
1791 | if (loop_dump_stream) | |
1792 | { | |
1793 | fprintf (loop_dump_stream, "Insn %d: regno %d (life %d), ", | |
1794 | INSN_UID (m->insn), m->regno, m->lifetime); | |
1795 | if (m->consec > 0) | |
1796 | fprintf (loop_dump_stream, "consec %d, ", m->consec); | |
1797 | if (m->cond) | |
1798 | fprintf (loop_dump_stream, "cond "); | |
1799 | if (m->force) | |
1800 | fprintf (loop_dump_stream, "force "); | |
1801 | if (m->global) | |
1802 | fprintf (loop_dump_stream, "global "); | |
1803 | if (m->done) | |
1804 | fprintf (loop_dump_stream, "done "); | |
1805 | if (m->move_insn) | |
1806 | fprintf (loop_dump_stream, "move-insn "); | |
1807 | if (m->match) | |
1808 | fprintf (loop_dump_stream, "matches %d ", | |
1809 | INSN_UID (m->match->insn)); | |
1810 | if (m->forces) | |
1811 | fprintf (loop_dump_stream, "forces %d ", | |
1812 | INSN_UID (m->forces->insn)); | |
1813 | } | |
1814 | ||
b4ad7b23 RS |
1815 | /* Ignore the insn if it's already done (it matched something else). |
1816 | Otherwise, see if it is now safe to move. */ | |
1817 | ||
1818 | if (!m->done | |
1819 | && (! m->cond | |
0534b804 | 1820 | || (1 == loop_invariant_p (loop, m->set_src) |
b4ad7b23 | 1821 | && (m->dependencies == 0 |
0534b804 | 1822 | || 1 == loop_invariant_p (loop, m->dependencies)) |
b4ad7b23 | 1823 | && (m->consec == 0 |
0534b804 | 1824 | || 1 == consec_sets_invariant_p (loop, m->set_dest, |
b4ad7b23 RS |
1825 | m->consec + 1, |
1826 | m->insn)))) | |
1827 | && (! m->forces || m->forces->done)) | |
1828 | { | |
b3694847 SS |
1829 | int regno; |
1830 | rtx p; | |
b4ad7b23 RS |
1831 | int savings = m->savings; |
1832 | ||
1833 | /* We have an insn that is safe to move. | |
1834 | Compute its desirability. */ | |
1835 | ||
1836 | p = m->insn; | |
1837 | regno = m->regno; | |
1838 | ||
1839 | if (loop_dump_stream) | |
1840 | fprintf (loop_dump_stream, "savings %d ", savings); | |
1841 | ||
f1d4ac80 | 1842 | if (regs->array[regno].moved_once && loop_dump_stream) |
877ca132 | 1843 | fprintf (loop_dump_stream, "halved since already moved "); |
b4ad7b23 RS |
1844 | |
1845 | /* An insn MUST be moved if we already moved something else | |
1846 | which is safe only if this one is moved too: that is, | |
1847 | if already_moved[REGNO] is nonzero. */ | |
1848 | ||
1849 | /* An insn is desirable to move if the new lifetime of the | |
1850 | register is no more than THRESHOLD times the old lifetime. | |
1851 | If it's not desirable, it means the loop is so big | |
1852 | that moving won't speed things up much, | |
1853 | and it is liable to make register usage worse. */ | |
1854 | ||
1855 | /* It is also desirable to move if it can be moved at no | |
1856 | extra cost because something else was already moved. */ | |
1857 | ||
1858 | if (already_moved[regno] | |
e5eb27e5 | 1859 | || flag_move_all_movables |
877ca132 | 1860 | || (threshold * savings * m->lifetime) >= |
f1d4ac80 | 1861 | (regs->array[regno].moved_once ? insn_count * 2 : insn_count) |
b4ad7b23 | 1862 | || (m->forces && m->forces->done |
f1d4ac80 | 1863 | && regs->array[m->forces->regno].n_times_set == 1)) |
b4ad7b23 RS |
1864 | { |
1865 | int count; | |
b3694847 | 1866 | struct movable *m1; |
6a651371 | 1867 | rtx first = NULL_RTX; |
8f7ee471 DJ |
1868 | rtx newreg = NULL_RTX; |
1869 | ||
1870 | if (m->insert_temp) | |
1871 | newreg = gen_reg_rtx (GET_MODE (m->set_dest)); | |
b4ad7b23 RS |
1872 | |
1873 | /* Now move the insns that set the reg. */ | |
1874 | ||
1875 | if (m->partial && m->match) | |
1876 | { | |
1877 | rtx newpat, i1; | |
1878 | rtx r1, r2; | |
1879 | /* Find the end of this chain of matching regs. | |
1880 | Thus, we load each reg in the chain from that one reg. | |
1881 | And that reg is loaded with 0 directly, | |
1882 | since it has ->match == 0. */ | |
1883 | for (m1 = m; m1->match; m1 = m1->match); | |
1884 | newpat = gen_move_insn (SET_DEST (PATTERN (m->insn)), | |
1885 | SET_DEST (PATTERN (m1->insn))); | |
804a718a | 1886 | i1 = loop_insn_hoist (loop, newpat); |
b4ad7b23 RS |
1887 | |
1888 | /* Mark the moved, invariant reg as being allowed to | |
1889 | share a hard reg with the other matching invariant. */ | |
1890 | REG_NOTES (i1) = REG_NOTES (m->insn); | |
1891 | r1 = SET_DEST (PATTERN (m->insn)); | |
1892 | r2 = SET_DEST (PATTERN (m1->insn)); | |
38a448ca RH |
1893 | regs_may_share |
1894 | = gen_rtx_EXPR_LIST (VOIDmode, r1, | |
1895 | gen_rtx_EXPR_LIST (VOIDmode, r2, | |
1896 | regs_may_share)); | |
49ce134f | 1897 | delete_insn (m->insn); |
b4ad7b23 RS |
1898 | |
1899 | if (new_start == 0) | |
1900 | new_start = i1; | |
1901 | ||
1902 | if (loop_dump_stream) | |
1903 | fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1)); | |
1904 | } | |
1905 | /* If we are to re-generate the item being moved with a | |
1906 | new move insn, first delete what we have and then emit | |
1907 | the move insn before the loop. */ | |
1908 | else if (m->move_insn) | |
1909 | { | |
804a718a | 1910 | rtx i1, temp, seq; |
b4ad7b23 RS |
1911 | |
1912 | for (count = m->consec; count >= 0; count--) | |
1913 | { | |
1914 | /* If this is the first insn of a library call sequence, | |
ed6cc1f5 | 1915 | something is very wrong. */ |
b4ad7b23 | 1916 | if (GET_CODE (p) != NOTE |
5fd8383e | 1917 | && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
ed6cc1f5 | 1918 | abort (); |
b4ad7b23 RS |
1919 | |
1920 | /* If this is the last insn of a libcall sequence, then | |
1921 | delete every insn in the sequence except the last. | |
1922 | The last insn is handled in the normal manner. */ | |
1923 | if (GET_CODE (p) != NOTE | |
5fd8383e | 1924 | && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX))) |
b4ad7b23 RS |
1925 | { |
1926 | temp = XEXP (temp, 0); | |
1927 | while (temp != p) | |
49ce134f | 1928 | temp = delete_insn (temp); |
b4ad7b23 RS |
1929 | } |
1930 | ||
9655bf95 | 1931 | temp = p; |
49ce134f | 1932 | p = delete_insn (p); |
9655bf95 DM |
1933 | |
1934 | /* simplify_giv_expr expects that it can walk the insns | |
1935 | at m->insn forwards and see this old sequence we are | |
1936 | tossing here. delete_insn does preserve the next | |
1937 | pointers, but when we skip over a NOTE we must fix | |
1938 | it up. Otherwise that code walks into the non-deleted | |
1939 | insn stream. */ | |
dd202606 | 1940 | while (p && GET_CODE (p) == NOTE) |
9655bf95 | 1941 | p = NEXT_INSN (temp) = NEXT_INSN (p); |
8f7ee471 DJ |
1942 | |
1943 | if (m->insert_temp) | |
1944 | { | |
1945 | /* Replace the original insn with a move from | |
3dc575ff | 1946 | our newly created temp. */ |
8f7ee471 | 1947 | start_sequence (); |
0c20a65f | 1948 | emit_move_insn (m->set_dest, newreg); |
8f7ee471 DJ |
1949 | seq = get_insns (); |
1950 | end_sequence (); | |
1951 | emit_insn_before (seq, p); | |
1952 | } | |
b4ad7b23 RS |
1953 | } |
1954 | ||
1955 | start_sequence (); | |
0c20a65f | 1956 | emit_move_insn (m->insert_temp ? newreg : m->set_dest, |
8f7ee471 | 1957 | m->set_src); |
2f937369 | 1958 | seq = get_insns (); |
b4ad7b23 RS |
1959 | end_sequence (); |
1960 | ||
2f937369 | 1961 | add_label_notes (m->set_src, seq); |
c160c628 | 1962 | |
804a718a | 1963 | i1 = loop_insn_hoist (loop, seq); |
5fd8383e | 1964 | if (! find_reg_note (i1, REG_EQUAL, NULL_RTX)) |
3d238248 JJ |
1965 | set_unique_reg_note (i1, |
1966 | m->is_equiv ? REG_EQUIV : REG_EQUAL, | |
1967 | m->set_src); | |
b4ad7b23 RS |
1968 | |
1969 | if (loop_dump_stream) | |
1970 | fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1)); | |
1971 | ||
1972 | /* The more regs we move, the less we like moving them. */ | |
1973 | threshold -= 3; | |
1974 | } | |
1975 | else | |
1976 | { | |
1977 | for (count = m->consec; count >= 0; count--) | |
1978 | { | |
1979 | rtx i1, temp; | |
1980 | ||
0f41302f | 1981 | /* If first insn of libcall sequence, skip to end. */ |
e6fcb60d | 1982 | /* Do this at start of loop, since p is guaranteed to |
b4ad7b23 RS |
1983 | be an insn here. */ |
1984 | if (GET_CODE (p) != NOTE | |
5fd8383e | 1985 | && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
1986 | p = XEXP (temp, 0); |
1987 | ||
1988 | /* If last insn of libcall sequence, move all | |
1989 | insns except the last before the loop. The last | |
1990 | insn is handled in the normal manner. */ | |
1991 | if (GET_CODE (p) != NOTE | |
5fd8383e | 1992 | && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX))) |
b4ad7b23 RS |
1993 | { |
1994 | rtx fn_address = 0; | |
1995 | rtx fn_reg = 0; | |
1996 | rtx fn_address_insn = 0; | |
1997 | ||
1998 | first = 0; | |
1999 | for (temp = XEXP (temp, 0); temp != p; | |
2000 | temp = NEXT_INSN (temp)) | |
2001 | { | |
2002 | rtx body; | |
2003 | rtx n; | |
2004 | rtx next; | |
2005 | ||
2006 | if (GET_CODE (temp) == NOTE) | |
2007 | continue; | |
2008 | ||
2009 | body = PATTERN (temp); | |
2010 | ||
2011 | /* Find the next insn after TEMP, | |
2012 | not counting USE or NOTE insns. */ | |
2013 | for (next = NEXT_INSN (temp); next != p; | |
2014 | next = NEXT_INSN (next)) | |
2015 | if (! (GET_CODE (next) == INSN | |
2016 | && GET_CODE (PATTERN (next)) == USE) | |
2017 | && GET_CODE (next) != NOTE) | |
2018 | break; | |
e6fcb60d | 2019 | |
b4ad7b23 RS |
2020 | /* If that is the call, this may be the insn |
2021 | that loads the function address. | |
2022 | ||
2023 | Extract the function address from the insn | |
2024 | that loads it into a register. | |
2025 | If this insn was cse'd, we get incorrect code. | |
2026 | ||
2027 | So emit a new move insn that copies the | |
2028 | function address into the register that the | |
2029 | call insn will use. flow.c will delete any | |
2030 | redundant stores that we have created. */ | |
2031 | if (GET_CODE (next) == CALL_INSN | |
2032 | && GET_CODE (body) == SET | |
2033 | && GET_CODE (SET_DEST (body)) == REG | |
5fd8383e RK |
2034 | && (n = find_reg_note (temp, REG_EQUAL, |
2035 | NULL_RTX))) | |
b4ad7b23 RS |
2036 | { |
2037 | fn_reg = SET_SRC (body); | |
2038 | if (GET_CODE (fn_reg) != REG) | |
2039 | fn_reg = SET_DEST (body); | |
2040 | fn_address = XEXP (n, 0); | |
2041 | fn_address_insn = temp; | |
2042 | } | |
2043 | /* We have the call insn. | |
2044 | If it uses the register we suspect it might, | |
2045 | load it with the correct address directly. */ | |
2046 | if (GET_CODE (temp) == CALL_INSN | |
2047 | && fn_address != 0 | |
d9f8a199 | 2048 | && reg_referenced_p (fn_reg, body)) |
86e21212 MH |
2049 | loop_insn_emit_after (loop, 0, fn_address_insn, |
2050 | gen_move_insn | |
2051 | (fn_reg, fn_address)); | |
b4ad7b23 RS |
2052 | |
2053 | if (GET_CODE (temp) == CALL_INSN) | |
f97d29ce | 2054 | { |
86e21212 | 2055 | i1 = loop_call_insn_hoist (loop, body); |
f97d29ce JW |
2056 | /* Because the USAGE information potentially |
2057 | contains objects other than hard registers | |
2058 | we need to copy it. */ | |
8c4f5c09 | 2059 | if (CALL_INSN_FUNCTION_USAGE (temp)) |
db3cf6fb MS |
2060 | CALL_INSN_FUNCTION_USAGE (i1) |
2061 | = copy_rtx (CALL_INSN_FUNCTION_USAGE (temp)); | |
f97d29ce | 2062 | } |
b4ad7b23 | 2063 | else |
804a718a | 2064 | i1 = loop_insn_hoist (loop, body); |
b4ad7b23 RS |
2065 | if (first == 0) |
2066 | first = i1; | |
2067 | if (temp == fn_address_insn) | |
2068 | fn_address_insn = i1; | |
2069 | REG_NOTES (i1) = REG_NOTES (temp); | |
49ce134f JH |
2070 | REG_NOTES (temp) = NULL; |
2071 | delete_insn (temp); | |
b4ad7b23 | 2072 | } |
18985c91 R |
2073 | if (new_start == 0) |
2074 | new_start = first; | |
b4ad7b23 RS |
2075 | } |
2076 | if (m->savemode != VOIDmode) | |
2077 | { | |
2078 | /* P sets REG to zero; but we should clear only | |
2079 | the bits that are not covered by the mode | |
2080 | m->savemode. */ | |
2081 | rtx reg = m->set_dest; | |
2082 | rtx sequence; | |
2083 | rtx tem; | |
e6fcb60d | 2084 | |
b4ad7b23 | 2085 | start_sequence (); |
ef89d648 ZW |
2086 | tem = expand_simple_binop |
2087 | (GET_MODE (reg), AND, reg, | |
5fd8383e RK |
2088 | GEN_INT ((((HOST_WIDE_INT) 1 |
2089 | << GET_MODE_BITSIZE (m->savemode))) | |
b4ad7b23 RS |
2090 | - 1), |
2091 | reg, 1, OPTAB_LIB_WIDEN); | |
2092 | if (tem == 0) | |
2093 | abort (); | |
2094 | if (tem != reg) | |
2095 | emit_move_insn (reg, tem); | |
2f937369 | 2096 | sequence = get_insns (); |
b4ad7b23 | 2097 | end_sequence (); |
804a718a | 2098 | i1 = loop_insn_hoist (loop, sequence); |
b4ad7b23 RS |
2099 | } |
2100 | else if (GET_CODE (p) == CALL_INSN) | |
f97d29ce | 2101 | { |
86e21212 | 2102 | i1 = loop_call_insn_hoist (loop, PATTERN (p)); |
f97d29ce JW |
2103 | /* Because the USAGE information potentially |
2104 | contains objects other than hard registers | |
2105 | we need to copy it. */ | |
8c4f5c09 | 2106 | if (CALL_INSN_FUNCTION_USAGE (p)) |
db3cf6fb MS |
2107 | CALL_INSN_FUNCTION_USAGE (i1) |
2108 | = copy_rtx (CALL_INSN_FUNCTION_USAGE (p)); | |
f97d29ce | 2109 | } |
1a61c29f JW |
2110 | else if (count == m->consec && m->move_insn_first) |
2111 | { | |
804a718a | 2112 | rtx seq; |
1a61c29f JW |
2113 | /* The SET_SRC might not be invariant, so we must |
2114 | use the REG_EQUAL note. */ | |
2115 | start_sequence (); | |
2116 | emit_move_insn (m->set_dest, m->set_src); | |
2f937369 | 2117 | seq = get_insns (); |
1a61c29f JW |
2118 | end_sequence (); |
2119 | ||
2f937369 | 2120 | add_label_notes (m->set_src, seq); |
1a61c29f | 2121 | |
804a718a | 2122 | i1 = loop_insn_hoist (loop, seq); |
1a61c29f | 2123 | if (! find_reg_note (i1, REG_EQUAL, NULL_RTX)) |
3d238248 JJ |
2124 | set_unique_reg_note (i1, m->is_equiv ? REG_EQUIV |
2125 | : REG_EQUAL, m->set_src); | |
1a61c29f | 2126 | } |
8f7ee471 DJ |
2127 | else if (m->insert_temp) |
2128 | { | |
703ad42b KG |
2129 | rtx *reg_map2 = xcalloc (REGNO (newreg), |
2130 | sizeof(rtx)); | |
8f7ee471 DJ |
2131 | reg_map2 [m->regno] = newreg; |
2132 | ||
2133 | i1 = loop_insn_hoist (loop, copy_rtx (PATTERN (p))); | |
2134 | replace_regs (i1, reg_map2, REGNO (newreg), 1); | |
2135 | free (reg_map2); | |
0c20a65f | 2136 | } |
b4ad7b23 | 2137 | else |
804a718a | 2138 | i1 = loop_insn_hoist (loop, PATTERN (p)); |
b4ad7b23 | 2139 | |
1a61c29f JW |
2140 | if (REG_NOTES (i1) == 0) |
2141 | { | |
2142 | REG_NOTES (i1) = REG_NOTES (p); | |
49ce134f | 2143 | REG_NOTES (p) = NULL; |
b4ad7b23 | 2144 | |
1a61c29f JW |
2145 | /* If there is a REG_EQUAL note present whose value |
2146 | is not loop invariant, then delete it, since it | |
2147 | may cause problems with later optimization passes. | |
2148 | It is possible for cse to create such notes | |
2149 | like this as a result of record_jump_cond. */ | |
e6fcb60d | 2150 | |
1a61c29f | 2151 | if ((temp = find_reg_note (i1, REG_EQUAL, NULL_RTX)) |
0534b804 | 2152 | && ! loop_invariant_p (loop, XEXP (temp, 0))) |
1a61c29f JW |
2153 | remove_note (i1, temp); |
2154 | } | |
e6726b1f | 2155 | |
b4ad7b23 RS |
2156 | if (new_start == 0) |
2157 | new_start = i1; | |
2158 | ||
2159 | if (loop_dump_stream) | |
2160 | fprintf (loop_dump_stream, " moved to %d", | |
2161 | INSN_UID (i1)); | |
2162 | ||
b4ad7b23 RS |
2163 | /* If library call, now fix the REG_NOTES that contain |
2164 | insn pointers, namely REG_LIBCALL on FIRST | |
2165 | and REG_RETVAL on I1. */ | |
51723711 | 2166 | if ((temp = find_reg_note (i1, REG_RETVAL, NULL_RTX))) |
b4ad7b23 RS |
2167 | { |
2168 | XEXP (temp, 0) = first; | |
5fd8383e | 2169 | temp = find_reg_note (first, REG_LIBCALL, NULL_RTX); |
b4ad7b23 RS |
2170 | XEXP (temp, 0) = i1; |
2171 | } | |
2172 | ||
9655bf95 | 2173 | temp = p; |
49ce134f | 2174 | delete_insn (p); |
9655bf95 DM |
2175 | p = NEXT_INSN (p); |
2176 | ||
2177 | /* simplify_giv_expr expects that it can walk the insns | |
2178 | at m->insn forwards and see this old sequence we are | |
2179 | tossing here. delete_insn does preserve the next | |
2180 | pointers, but when we skip over a NOTE we must fix | |
2181 | it up. Otherwise that code walks into the non-deleted | |
2182 | insn stream. */ | |
2183 | while (p && GET_CODE (p) == NOTE) | |
2184 | p = NEXT_INSN (temp) = NEXT_INSN (p); | |
8f7ee471 DJ |
2185 | |
2186 | if (m->insert_temp) | |
2187 | { | |
2188 | rtx seq; | |
2189 | /* Replace the original insn with a move from | |
3dc575ff | 2190 | our newly created temp. */ |
8f7ee471 | 2191 | start_sequence (); |
0c20a65f | 2192 | emit_move_insn (m->set_dest, newreg); |
8f7ee471 DJ |
2193 | seq = get_insns (); |
2194 | end_sequence (); | |
2195 | emit_insn_before (seq, p); | |
2196 | } | |
b4ad7b23 RS |
2197 | } |
2198 | ||
2199 | /* The more regs we move, the less we like moving them. */ | |
2200 | threshold -= 3; | |
2201 | } | |
2202 | ||
8f7ee471 | 2203 | m->done = 1; |
b4ad7b23 | 2204 | |
8f7ee471 | 2205 | if (!m->insert_temp) |
d5e0243a | 2206 | { |
8f7ee471 DJ |
2207 | /* Any other movable that loads the same register |
2208 | MUST be moved. */ | |
2209 | already_moved[regno] = 1; | |
b4ad7b23 | 2210 | |
8f7ee471 DJ |
2211 | /* This reg has been moved out of one loop. */ |
2212 | regs->array[regno].moved_once = 1; | |
b4ad7b23 | 2213 | |
8f7ee471 DJ |
2214 | /* The reg set here is now invariant. */ |
2215 | if (! m->partial) | |
2216 | { | |
2217 | int i; | |
2218 | for (i = 0; i < LOOP_REGNO_NREGS (regno, m->set_dest); i++) | |
2219 | regs->array[regno+i].set_in_loop = 0; | |
2220 | } | |
2221 | ||
2222 | /* Change the length-of-life info for the register | |
2223 | to say it lives at least the full length of this loop. | |
2224 | This will help guide optimizations in outer loops. */ | |
2225 | ||
2226 | if (REGNO_FIRST_LUID (regno) > INSN_LUID (loop_start)) | |
2227 | /* This is the old insn before all the moved insns. | |
2228 | We can't use the moved insn because it is out of range | |
2229 | in uid_luid. Only the old insns have luids. */ | |
2230 | REGNO_FIRST_UID (regno) = INSN_UID (loop_start); | |
2231 | if (REGNO_LAST_LUID (regno) < INSN_LUID (loop_end)) | |
2232 | REGNO_LAST_UID (regno) = INSN_UID (loop_end); | |
2233 | } | |
b4ad7b23 RS |
2234 | |
2235 | /* Combine with this moved insn any other matching movables. */ | |
2236 | ||
2237 | if (! m->partial) | |
02055ad6 | 2238 | for (m1 = movables->head; m1; m1 = m1->next) |
b4ad7b23 RS |
2239 | if (m1->match == m) |
2240 | { | |
2241 | rtx temp; | |
2242 | ||
2243 | /* Schedule the reg loaded by M1 | |
2244 | for replacement so that shares the reg of M. | |
2245 | If the modes differ (only possible in restricted | |
51f0646f JL |
2246 | circumstances, make a SUBREG. |
2247 | ||
2248 | Note this assumes that the target dependent files | |
2249 | treat REG and SUBREG equally, including within | |
2250 | GO_IF_LEGITIMATE_ADDRESS and in all the | |
2251 | predicates since we never verify that replacing the | |
2252 | original register with a SUBREG results in a | |
2253 | recognizable insn. */ | |
b4ad7b23 RS |
2254 | if (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest)) |
2255 | reg_map[m1->regno] = m->set_dest; | |
2256 | else | |
2257 | reg_map[m1->regno] | |
2258 | = gen_lowpart_common (GET_MODE (m1->set_dest), | |
2259 | m->set_dest); | |
e6fcb60d | 2260 | |
b4ad7b23 RS |
2261 | /* Get rid of the matching insn |
2262 | and prevent further processing of it. */ | |
2263 | m1->done = 1; | |
2264 | ||
938d968e | 2265 | /* If library call, delete all insns. */ |
51723711 KG |
2266 | if ((temp = find_reg_note (m1->insn, REG_RETVAL, |
2267 | NULL_RTX))) | |
49ce134f JH |
2268 | delete_insn_chain (XEXP (temp, 0), m1->insn); |
2269 | else | |
2270 | delete_insn (m1->insn); | |
b4ad7b23 RS |
2271 | |
2272 | /* Any other movable that loads the same register | |
2273 | MUST be moved. */ | |
2274 | already_moved[m1->regno] = 1; | |
2275 | ||
2276 | /* The reg merged here is now invariant, | |
2277 | if the reg it matches is invariant. */ | |
2278 | if (! m->partial) | |
d5e0243a DE |
2279 | { |
2280 | int i; | |
2281 | for (i = 0; | |
44a5565d | 2282 | i < LOOP_REGNO_NREGS (regno, m1->set_dest); |
d5e0243a DE |
2283 | i++) |
2284 | regs->array[m1->regno+i].set_in_loop = 0; | |
2285 | } | |
b4ad7b23 RS |
2286 | } |
2287 | } | |
2288 | else if (loop_dump_stream) | |
2289 | fprintf (loop_dump_stream, "not desirable"); | |
2290 | } | |
2291 | else if (loop_dump_stream && !m->match) | |
2292 | fprintf (loop_dump_stream, "not safe"); | |
2293 | ||
2294 | if (loop_dump_stream) | |
2295 | fprintf (loop_dump_stream, "\n"); | |
2296 | } | |
2297 | ||
2298 | if (new_start == 0) | |
2299 | new_start = loop_start; | |
2300 | ||
2301 | /* Go through all the instructions in the loop, making | |
2302 | all the register substitutions scheduled in REG_MAP. */ | |
0534b804 | 2303 | for (p = new_start; p != loop_end; p = NEXT_INSN (p)) |
b4ad7b23 RS |
2304 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN |
2305 | || GET_CODE (p) == CALL_INSN) | |
2306 | { | |
2307 | replace_regs (PATTERN (p), reg_map, nregs, 0); | |
2308 | replace_regs (REG_NOTES (p), reg_map, nregs, 0); | |
da0c128e | 2309 | INSN_CODE (p) = -1; |
b4ad7b23 | 2310 | } |
4da896b2 MM |
2311 | |
2312 | /* Clean up. */ | |
2313 | free (reg_map); | |
2314 | free (already_moved); | |
b4ad7b23 | 2315 | } |
6ec92010 MH |
2316 | |
2317 | ||
2318 | static void | |
0c20a65f | 2319 | loop_movables_add (struct loop_movables *movables, struct movable *m) |
6ec92010 MH |
2320 | { |
2321 | if (movables->head == 0) | |
2322 | movables->head = m; | |
2323 | else | |
2324 | movables->last->next = m; | |
2325 | movables->last = m; | |
2326 | } | |
2327 | ||
2328 | ||
2329 | static void | |
0c20a65f | 2330 | loop_movables_free (struct loop_movables *movables) |
6ec92010 MH |
2331 | { |
2332 | struct movable *m; | |
2333 | struct movable *m_next; | |
2334 | ||
2335 | for (m = movables->head; m; m = m_next) | |
2336 | { | |
2337 | m_next = m->next; | |
2338 | free (m); | |
2339 | } | |
6b8c9327 | 2340 | } |
b4ad7b23 RS |
2341 | \f |
2342 | #if 0 | |
2343 | /* Scan X and replace the address of any MEM in it with ADDR. | |
2344 | REG is the address that MEM should have before the replacement. */ | |
2345 | ||
2346 | static void | |
0c20a65f | 2347 | replace_call_address (rtx x, rtx reg, rtx addr) |
b4ad7b23 | 2348 | { |
b3694847 SS |
2349 | enum rtx_code code; |
2350 | int i; | |
2351 | const char *fmt; | |
b4ad7b23 RS |
2352 | |
2353 | if (x == 0) | |
2354 | return; | |
2355 | code = GET_CODE (x); | |
2356 | switch (code) | |
2357 | { | |
2358 | case PC: | |
2359 | case CC0: | |
2360 | case CONST_INT: | |
2361 | case CONST_DOUBLE: | |
2362 | case CONST: | |
2363 | case SYMBOL_REF: | |
2364 | case LABEL_REF: | |
2365 | case REG: | |
2366 | return; | |
2367 | ||
2368 | case SET: | |
2369 | /* Short cut for very common case. */ | |
2370 | replace_call_address (XEXP (x, 1), reg, addr); | |
2371 | return; | |
2372 | ||
2373 | case CALL: | |
2374 | /* Short cut for very common case. */ | |
2375 | replace_call_address (XEXP (x, 0), reg, addr); | |
2376 | return; | |
2377 | ||
2378 | case MEM: | |
2379 | /* If this MEM uses a reg other than the one we expected, | |
2380 | something is wrong. */ | |
2381 | if (XEXP (x, 0) != reg) | |
2382 | abort (); | |
2383 | XEXP (x, 0) = addr; | |
2384 | return; | |
e6fcb60d | 2385 | |
e9a25f70 JL |
2386 | default: |
2387 | break; | |
b4ad7b23 RS |
2388 | } |
2389 | ||
2390 | fmt = GET_RTX_FORMAT (code); | |
2391 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2392 | { | |
2393 | if (fmt[i] == 'e') | |
2394 | replace_call_address (XEXP (x, i), reg, addr); | |
d4757e6a | 2395 | else if (fmt[i] == 'E') |
b4ad7b23 | 2396 | { |
b3694847 | 2397 | int j; |
b4ad7b23 RS |
2398 | for (j = 0; j < XVECLEN (x, i); j++) |
2399 | replace_call_address (XVECEXP (x, i, j), reg, addr); | |
2400 | } | |
2401 | } | |
2402 | } | |
2403 | #endif | |
2404 | \f | |
2405 | /* Return the number of memory refs to addresses that vary | |
2406 | in the rtx X. */ | |
2407 | ||
2408 | static int | |
0c20a65f | 2409 | count_nonfixed_reads (const struct loop *loop, rtx x) |
b4ad7b23 | 2410 | { |
b3694847 SS |
2411 | enum rtx_code code; |
2412 | int i; | |
2413 | const char *fmt; | |
b4ad7b23 RS |
2414 | int value; |
2415 | ||
2416 | if (x == 0) | |
2417 | return 0; | |
2418 | ||
2419 | code = GET_CODE (x); | |
2420 | switch (code) | |
2421 | { | |
2422 | case PC: | |
2423 | case CC0: | |
2424 | case CONST_INT: | |
2425 | case CONST_DOUBLE: | |
2426 | case CONST: | |
2427 | case SYMBOL_REF: | |
2428 | case LABEL_REF: | |
2429 | case REG: | |
2430 | return 0; | |
2431 | ||
2432 | case MEM: | |
0534b804 MH |
2433 | return ((loop_invariant_p (loop, XEXP (x, 0)) != 1) |
2434 | + count_nonfixed_reads (loop, XEXP (x, 0))); | |
e6fcb60d | 2435 | |
e9a25f70 JL |
2436 | default: |
2437 | break; | |
b4ad7b23 RS |
2438 | } |
2439 | ||
2440 | value = 0; | |
2441 | fmt = GET_RTX_FORMAT (code); | |
2442 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2443 | { | |
2444 | if (fmt[i] == 'e') | |
0534b804 MH |
2445 | value += count_nonfixed_reads (loop, XEXP (x, i)); |
2446 | if (fmt[i] == 'E') | |
b4ad7b23 | 2447 | { |
b3694847 | 2448 | int j; |
b4ad7b23 | 2449 | for (j = 0; j < XVECLEN (x, i); j++) |
0534b804 | 2450 | value += count_nonfixed_reads (loop, XVECEXP (x, i, j)); |
b4ad7b23 RS |
2451 | } |
2452 | } | |
2453 | return value; | |
2454 | } | |
b4ad7b23 | 2455 | \f |
3c748bb6 | 2456 | /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed', |
576d0b54 | 2457 | `has_call', `has_nonconst_call', `has_volatile', `has_tablejump', |
afa1738b MH |
2458 | `unknown_address_altered', `unknown_constant_address_altered', and |
2459 | `num_mem_sets' in LOOP. Also, fill in the array `mems' and the | |
2460 | list `store_mems' in LOOP. */ | |
b4ad7b23 RS |
2461 | |
2462 | static void | |
0c20a65f | 2463 | prescan_loop (struct loop *loop) |
b4ad7b23 | 2464 | { |
b3694847 | 2465 | int level = 1; |
41a972a9 | 2466 | rtx insn; |
52b38064 | 2467 | struct loop_info *loop_info = LOOP_INFO (loop); |
a2be868f MH |
2468 | rtx start = loop->start; |
2469 | rtx end = loop->end; | |
41a972a9 MM |
2470 | /* The label after END. Jumping here is just like falling off the |
2471 | end of the loop. We use next_nonnote_insn instead of next_label | |
2472 | as a hedge against the (pathological) case where some actual insn | |
2473 | might end up between the two. */ | |
2474 | rtx exit_target = next_nonnote_insn (end); | |
3c748bb6 | 2475 | |
3c748bb6 | 2476 | loop_info->has_indirect_jump = indirect_jump_in_function; |
e304a8e6 | 2477 | loop_info->pre_header_has_call = 0; |
3c748bb6 | 2478 | loop_info->has_call = 0; |
576d0b54 | 2479 | loop_info->has_nonconst_call = 0; |
62e6ca55 | 2480 | loop_info->has_prefetch = 0; |
3c748bb6 MH |
2481 | loop_info->has_volatile = 0; |
2482 | loop_info->has_tablejump = 0; | |
3c748bb6 | 2483 | loop_info->has_multiple_exit_targets = 0; |
a2be868f | 2484 | loop->level = 1; |
b4ad7b23 | 2485 | |
afa1738b MH |
2486 | loop_info->unknown_address_altered = 0; |
2487 | loop_info->unknown_constant_address_altered = 0; | |
2488 | loop_info->store_mems = NULL_RTX; | |
2489 | loop_info->first_loop_store_insn = NULL_RTX; | |
2490 | loop_info->mems_idx = 0; | |
2491 | loop_info->num_mem_sets = 0; | |
3eae4643 | 2492 | /* If loop opts run twice, this was set on 1st pass for 2nd. */ |
dad482e6 | 2493 | loop_info->preconditioned = NOTE_PRECONDITIONED (end); |
e304a8e6 | 2494 | |
6b8c9327 | 2495 | for (insn = start; insn && GET_CODE (insn) != CODE_LABEL; |
e304a8e6 MH |
2496 | insn = PREV_INSN (insn)) |
2497 | { | |
2498 | if (GET_CODE (insn) == CALL_INSN) | |
2499 | { | |
2500 | loop_info->pre_header_has_call = 1; | |
2501 | break; | |
2502 | } | |
2503 | } | |
2504 | ||
b4ad7b23 RS |
2505 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); |
2506 | insn = NEXT_INSN (insn)) | |
2507 | { | |
b7fe373b | 2508 | switch (GET_CODE (insn)) |
b4ad7b23 | 2509 | { |
b7fe373b | 2510 | case NOTE: |
b4ad7b23 RS |
2511 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) |
2512 | { | |
2513 | ++level; | |
2514 | /* Count number of loops contained in this one. */ | |
a2be868f | 2515 | loop->level++; |
b4ad7b23 RS |
2516 | } |
2517 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
b7fe373b RH |
2518 | --level; |
2519 | break; | |
2520 | ||
2521 | case CALL_INSN: | |
24a28584 | 2522 | if (! CONST_OR_PURE_CALL_P (insn)) |
576d0b54 MH |
2523 | { |
2524 | loop_info->unknown_address_altered = 1; | |
2525 | loop_info->has_nonconst_call = 1; | |
2526 | } | |
a6a063b8 AM |
2527 | else if (pure_call_p (insn)) |
2528 | loop_info->has_nonconst_call = 1; | |
3c748bb6 | 2529 | loop_info->has_call = 1; |
b7fe373b RH |
2530 | if (can_throw_internal (insn)) |
2531 | loop_info->has_multiple_exit_targets = 1; | |
ee960939 OH |
2532 | |
2533 | /* Calls initializing constant objects have CLOBBER of MEM /u in the | |
2534 | attached FUNCTION_USAGE expression list, not accounted for by the | |
2535 | code above. We should note these to avoid missing dependencies in | |
2536 | later references. */ | |
2537 | { | |
2538 | rtx fusage_entry; | |
0c20a65f AJ |
2539 | |
2540 | for (fusage_entry = CALL_INSN_FUNCTION_USAGE (insn); | |
ee960939 OH |
2541 | fusage_entry; fusage_entry = XEXP (fusage_entry, 1)) |
2542 | { | |
2543 | rtx fusage = XEXP (fusage_entry, 0); | |
2544 | ||
2545 | if (GET_CODE (fusage) == CLOBBER | |
2546 | && GET_CODE (XEXP (fusage, 0)) == MEM | |
2547 | && RTX_UNCHANGING_P (XEXP (fusage, 0))) | |
2548 | { | |
2549 | note_stores (fusage, note_addr_stored, loop_info); | |
2550 | if (! loop_info->first_loop_store_insn | |
2551 | && loop_info->store_mems) | |
2552 | loop_info->first_loop_store_insn = insn; | |
2553 | } | |
2554 | } | |
2555 | } | |
b7fe373b RH |
2556 | break; |
2557 | ||
2558 | case JUMP_INSN: | |
2559 | if (! loop_info->has_multiple_exit_targets) | |
2560 | { | |
2561 | rtx set = pc_set (insn); | |
2562 | ||
2563 | if (set) | |
2564 | { | |
7d104885 | 2565 | rtx src = SET_SRC (set); |
b7fe373b RH |
2566 | rtx label1, label2; |
2567 | ||
7d104885 | 2568 | if (GET_CODE (src) == IF_THEN_ELSE) |
b7fe373b | 2569 | { |
7d104885 GS |
2570 | label1 = XEXP (src, 1); |
2571 | label2 = XEXP (src, 2); | |
b7fe373b RH |
2572 | } |
2573 | else | |
2574 | { | |
7d104885 | 2575 | label1 = src; |
b7fe373b RH |
2576 | label2 = NULL_RTX; |
2577 | } | |
2578 | ||
2579 | do | |
2580 | { | |
2581 | if (label1 && label1 != pc_rtx) | |
2582 | { | |
2583 | if (GET_CODE (label1) != LABEL_REF) | |
2584 | { | |
2585 | /* Something tricky. */ | |
2586 | loop_info->has_multiple_exit_targets = 1; | |
2587 | break; | |
2588 | } | |
2589 | else if (XEXP (label1, 0) != exit_target | |
2590 | && LABEL_OUTSIDE_LOOP_P (label1)) | |
2591 | { | |
2592 | /* A jump outside the current loop. */ | |
2593 | loop_info->has_multiple_exit_targets = 1; | |
2594 | break; | |
2595 | } | |
2596 | } | |
2597 | ||
2598 | label1 = label2; | |
2599 | label2 = NULL_RTX; | |
2600 | } | |
2601 | while (label1); | |
2602 | } | |
2603 | else | |
2604 | { | |
2605 | /* A return, or something tricky. */ | |
2606 | loop_info->has_multiple_exit_targets = 1; | |
2607 | } | |
2608 | } | |
2609 | /* FALLTHRU */ | |
41a972a9 | 2610 | |
b7fe373b | 2611 | case INSN: |
41a972a9 | 2612 | if (volatile_refs_p (PATTERN (insn))) |
3c748bb6 | 2613 | loop_info->has_volatile = 1; |
8c368ee2 DE |
2614 | |
2615 | if (GET_CODE (insn) == JUMP_INSN | |
2616 | && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2617 | || GET_CODE (PATTERN (insn)) == ADDR_VEC)) | |
3c748bb6 | 2618 | loop_info->has_tablejump = 1; |
e6fcb60d | 2619 | |
afa1738b MH |
2620 | note_stores (PATTERN (insn), note_addr_stored, loop_info); |
2621 | if (! loop_info->first_loop_store_insn && loop_info->store_mems) | |
2622 | loop_info->first_loop_store_insn = insn; | |
41a972a9 | 2623 | |
b7fe373b RH |
2624 | if (flag_non_call_exceptions && can_throw_internal (insn)) |
2625 | loop_info->has_multiple_exit_targets = 1; | |
2626 | break; | |
552bc76f | 2627 | |
b7fe373b RH |
2628 | default: |
2629 | break; | |
b4ad7b23 RS |
2630 | } |
2631 | } | |
41a972a9 MM |
2632 | |
2633 | /* Now, rescan the loop, setting up the LOOP_MEMS array. */ | |
20bd7bfa | 2634 | if (/* An exception thrown by a called function might land us |
41a972a9 | 2635 | anywhere. */ |
576d0b54 | 2636 | ! loop_info->has_nonconst_call |
41a972a9 MM |
2637 | /* We don't want loads for MEMs moved to a location before the |
2638 | one at which their stack memory becomes allocated. (Note | |
2639 | that this is not a problem for malloc, etc., since those | |
2640 | require actual function calls. */ | |
a2be868f | 2641 | && ! current_function_calls_alloca |
41a972a9 MM |
2642 | /* There are ways to leave the loop other than falling off the |
2643 | end. */ | |
a2be868f | 2644 | && ! loop_info->has_multiple_exit_targets) |
41a972a9 MM |
2645 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); |
2646 | insn = NEXT_INSN (insn)) | |
afa1738b | 2647 | for_each_rtx (&insn, insert_loop_mem, loop_info); |
20bd7bfa JW |
2648 | |
2649 | /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so | |
2650 | that loop_invariant_p and load_mems can use true_dependence | |
2651 | to determine what is really clobbered. */ | |
afa1738b | 2652 | if (loop_info->unknown_address_altered) |
20bd7bfa JW |
2653 | { |
2654 | rtx mem = gen_rtx_MEM (BLKmode, const0_rtx); | |
2655 | ||
fd5d5b07 | 2656 | loop_info->store_mems |
afa1738b | 2657 | = gen_rtx_EXPR_LIST (VOIDmode, mem, loop_info->store_mems); |
20bd7bfa | 2658 | } |
afa1738b | 2659 | if (loop_info->unknown_constant_address_altered) |
20bd7bfa JW |
2660 | { |
2661 | rtx mem = gen_rtx_MEM (BLKmode, const0_rtx); | |
2662 | ||
2663 | RTX_UNCHANGING_P (mem) = 1; | |
fd5d5b07 | 2664 | loop_info->store_mems |
afa1738b | 2665 | = gen_rtx_EXPR_LIST (VOIDmode, mem, loop_info->store_mems); |
20bd7bfa | 2666 | } |
b4ad7b23 RS |
2667 | } |
2668 | \f | |
6a58eee9 RH |
2669 | /* Invalidate all loops containing LABEL. */ |
2670 | ||
2671 | static void | |
0c20a65f | 2672 | invalidate_loops_containing_label (rtx label) |
6a58eee9 RH |
2673 | { |
2674 | struct loop *loop; | |
2675 | for (loop = uid_loop[INSN_UID (label)]; loop; loop = loop->outer) | |
2676 | loop->invalid = 1; | |
2677 | } | |
2678 | ||
b4ad7b23 RS |
2679 | /* Scan the function looking for loops. Record the start and end of each loop. |
2680 | Also mark as invalid loops any loops that contain a setjmp or are branched | |
2681 | to from outside the loop. */ | |
2682 | ||
2683 | static void | |
0c20a65f | 2684 | find_and_verify_loops (rtx f, struct loops *loops) |
b4ad7b23 | 2685 | { |
a2be868f MH |
2686 | rtx insn; |
2687 | rtx label; | |
2688 | int num_loops; | |
2689 | struct loop *current_loop; | |
2690 | struct loop *next_loop; | |
2691 | struct loop *loop; | |
2692 | ||
2693 | num_loops = loops->num; | |
b4ad7b23 | 2694 | |
3ec2b590 R |
2695 | compute_luids (f, NULL_RTX, 0); |
2696 | ||
b4ad7b23 RS |
2697 | /* If there are jumps to undefined labels, |
2698 | treat them as jumps out of any/all loops. | |
2699 | This also avoids writing past end of tables when there are no loops. */ | |
a2be868f | 2700 | uid_loop[0] = NULL; |
b4ad7b23 RS |
2701 | |
2702 | /* Find boundaries of loops, mark which loops are contained within | |
2703 | loops, and invalidate loops that have setjmp. */ | |
2704 | ||
a2be868f MH |
2705 | num_loops = 0; |
2706 | current_loop = NULL; | |
b4ad7b23 RS |
2707 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
2708 | { | |
2709 | if (GET_CODE (insn) == NOTE) | |
2710 | switch (NOTE_LINE_NUMBER (insn)) | |
2711 | { | |
2712 | case NOTE_INSN_LOOP_BEG: | |
a2be868f MH |
2713 | next_loop = loops->array + num_loops; |
2714 | next_loop->num = num_loops; | |
2715 | num_loops++; | |
2716 | next_loop->start = insn; | |
2717 | next_loop->outer = current_loop; | |
b4ad7b23 RS |
2718 | current_loop = next_loop; |
2719 | break; | |
2720 | ||
3ec2b590 | 2721 | case NOTE_INSN_LOOP_CONT: |
a2be868f | 2722 | current_loop->cont = insn; |
3ec2b590 | 2723 | break; |
e375c819 MH |
2724 | |
2725 | case NOTE_INSN_LOOP_VTOP: | |
2726 | current_loop->vtop = insn; | |
2727 | break; | |
2728 | ||
b4ad7b23 | 2729 | case NOTE_INSN_LOOP_END: |
a2be868f | 2730 | if (! current_loop) |
b4ad7b23 RS |
2731 | abort (); |
2732 | ||
a2be868f | 2733 | current_loop->end = insn; |
a2be868f | 2734 | current_loop = current_loop->outer; |
b4ad7b23 RS |
2735 | break; |
2736 | ||
e9a25f70 JL |
2737 | default: |
2738 | break; | |
b4ad7b23 RS |
2739 | } |
2740 | ||
19652adf | 2741 | if (GET_CODE (insn) == CALL_INSN |
570a98eb JH |
2742 | && find_reg_note (insn, REG_SETJMP, NULL)) |
2743 | { | |
2744 | /* In this case, we must invalidate our current loop and any | |
2745 | enclosing loop. */ | |
2746 | for (loop = current_loop; loop; loop = loop->outer) | |
2747 | { | |
2748 | loop->invalid = 1; | |
2749 | if (loop_dump_stream) | |
2750 | fprintf (loop_dump_stream, | |
2751 | "\nLoop at %d ignored due to setjmp.\n", | |
2752 | INSN_UID (loop->start)); | |
2753 | } | |
2754 | } | |
2755 | ||
b4ad7b23 RS |
2756 | /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the |
2757 | enclosing loop, but this doesn't matter. */ | |
a2be868f | 2758 | uid_loop[INSN_UID (insn)] = current_loop; |
b4ad7b23 RS |
2759 | } |
2760 | ||
034dabc9 JW |
2761 | /* Any loop containing a label used in an initializer must be invalidated, |
2762 | because it can be jumped into from anywhere. */ | |
034dabc9 | 2763 | for (label = forced_labels; label; label = XEXP (label, 1)) |
6a58eee9 | 2764 | invalidate_loops_containing_label (XEXP (label, 0)); |
034dabc9 | 2765 | |
6adb4e3a MS |
2766 | /* Any loop containing a label used for an exception handler must be |
2767 | invalidated, because it can be jumped into from anywhere. */ | |
6a58eee9 | 2768 | for_each_eh_label (invalidate_loops_containing_label); |
6adb4e3a | 2769 | |
034dabc9 JW |
2770 | /* Now scan all insn's in the function. If any JUMP_INSN branches into a |
2771 | loop that it is not contained within, that loop is marked invalid. | |
2772 | If any INSN or CALL_INSN uses a label's address, then the loop containing | |
2773 | that label is marked invalid, because it could be jumped into from | |
2774 | anywhere. | |
b4ad7b23 RS |
2775 | |
2776 | Also look for blocks of code ending in an unconditional branch that | |
e6fcb60d | 2777 | exits the loop. If such a block is surrounded by a conditional |
b4ad7b23 RS |
2778 | branch around the block, move the block elsewhere (see below) and |
2779 | invert the jump to point to the code block. This may eliminate a | |
2780 | label in our loop and will simplify processing by both us and a | |
2781 | possible second cse pass. */ | |
2782 | ||
2783 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2784 | if (INSN_P (insn)) |
b4ad7b23 | 2785 | { |
a2be868f | 2786 | struct loop *this_loop = uid_loop[INSN_UID (insn)]; |
b4ad7b23 | 2787 | |
034dabc9 JW |
2788 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) |
2789 | { | |
2790 | rtx note = find_reg_note (insn, REG_LABEL, NULL_RTX); | |
2791 | if (note) | |
6a58eee9 | 2792 | invalidate_loops_containing_label (XEXP (note, 0)); |
034dabc9 JW |
2793 | } |
2794 | ||
2795 | if (GET_CODE (insn) != JUMP_INSN) | |
2796 | continue; | |
2797 | ||
a2be868f | 2798 | mark_loop_jump (PATTERN (insn), this_loop); |
b4ad7b23 RS |
2799 | |
2800 | /* See if this is an unconditional branch outside the loop. */ | |
a2be868f | 2801 | if (this_loop |
b4ad7b23 | 2802 | && (GET_CODE (PATTERN (insn)) == RETURN |
7f1c097d JH |
2803 | || (any_uncondjump_p (insn) |
2804 | && onlyjump_p (insn) | |
a2be868f MH |
2805 | && (uid_loop[INSN_UID (JUMP_LABEL (insn))] |
2806 | != this_loop))) | |
1c01e9df | 2807 | && get_max_uid () < max_uid_for_loop) |
b4ad7b23 RS |
2808 | { |
2809 | rtx p; | |
2810 | rtx our_next = next_real_insn (insn); | |
3b10cf4b | 2811 | rtx last_insn_to_move = NEXT_INSN (insn); |
a2be868f MH |
2812 | struct loop *dest_loop; |
2813 | struct loop *outer_loop = NULL; | |
b4ad7b23 RS |
2814 | |
2815 | /* Go backwards until we reach the start of the loop, a label, | |
2816 | or a JUMP_INSN. */ | |
2817 | for (p = PREV_INSN (insn); | |
2818 | GET_CODE (p) != CODE_LABEL | |
2819 | && ! (GET_CODE (p) == NOTE | |
2820 | && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) | |
2821 | && GET_CODE (p) != JUMP_INSN; | |
2822 | p = PREV_INSN (p)) | |
2823 | ; | |
2824 | ||
edf711a4 RK |
2825 | /* Check for the case where we have a jump to an inner nested |
2826 | loop, and do not perform the optimization in that case. */ | |
2827 | ||
fdccb6df | 2828 | if (JUMP_LABEL (insn)) |
edf711a4 | 2829 | { |
a2be868f MH |
2830 | dest_loop = uid_loop[INSN_UID (JUMP_LABEL (insn))]; |
2831 | if (dest_loop) | |
fdccb6df | 2832 | { |
a2be868f MH |
2833 | for (outer_loop = dest_loop; outer_loop; |
2834 | outer_loop = outer_loop->outer) | |
2835 | if (outer_loop == this_loop) | |
fdccb6df RK |
2836 | break; |
2837 | } | |
edf711a4 | 2838 | } |
edf711a4 | 2839 | |
89724a5a RK |
2840 | /* Make sure that the target of P is within the current loop. */ |
2841 | ||
9a8e74f0 | 2842 | if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) |
a2be868f MH |
2843 | && uid_loop[INSN_UID (JUMP_LABEL (p))] != this_loop) |
2844 | outer_loop = this_loop; | |
89724a5a | 2845 | |
b4ad7b23 RS |
2846 | /* If we stopped on a JUMP_INSN to the next insn after INSN, |
2847 | we have a block of code to try to move. | |
2848 | ||
2849 | We look backward and then forward from the target of INSN | |
2850 | to find a BARRIER at the same loop depth as the target. | |
2851 | If we find such a BARRIER, we make a new label for the start | |
2852 | of the block, invert the jump in P and point it to that label, | |
2853 | and move the block of code to the spot we found. */ | |
2854 | ||
a2be868f | 2855 | if (! outer_loop |
edf711a4 | 2856 | && GET_CODE (p) == JUMP_INSN |
c6096c5e RS |
2857 | && JUMP_LABEL (p) != 0 |
2858 | /* Just ignore jumps to labels that were never emitted. | |
2859 | These always indicate compilation errors. */ | |
2860 | && INSN_UID (JUMP_LABEL (p)) != 0 | |
7f1c097d | 2861 | && any_condjump_p (p) && onlyjump_p (p) |
3b10cf4b MM |
2862 | && next_real_insn (JUMP_LABEL (p)) == our_next |
2863 | /* If it's not safe to move the sequence, then we | |
2864 | mustn't try. */ | |
e6fcb60d | 2865 | && insns_safe_to_move_p (p, NEXT_INSN (insn), |
3b10cf4b | 2866 | &last_insn_to_move)) |
b4ad7b23 RS |
2867 | { |
2868 | rtx target | |
2869 | = JUMP_LABEL (insn) ? JUMP_LABEL (insn) : get_last_insn (); | |
a2be868f | 2870 | struct loop *target_loop = uid_loop[INSN_UID (target)]; |
17bec8ee | 2871 | rtx loc, loc2; |
c4f81e4a JH |
2872 | rtx tmp; |
2873 | ||
2874 | /* Search for possible garbage past the conditional jumps | |
b0fd92a3 | 2875 | and look for the last barrier. */ |
c4f81e4a JH |
2876 | for (tmp = last_insn_to_move; |
2877 | tmp && GET_CODE (tmp) != CODE_LABEL; tmp = NEXT_INSN (tmp)) | |
2878 | if (GET_CODE (tmp) == BARRIER) | |
2879 | last_insn_to_move = tmp; | |
b4ad7b23 RS |
2880 | |
2881 | for (loc = target; loc; loc = PREV_INSN (loc)) | |
2882 | if (GET_CODE (loc) == BARRIER | |
17bec8ee BS |
2883 | /* Don't move things inside a tablejump. */ |
2884 | && ((loc2 = next_nonnote_insn (loc)) == 0 | |
2885 | || GET_CODE (loc2) != CODE_LABEL | |
2886 | || (loc2 = next_nonnote_insn (loc2)) == 0 | |
2887 | || GET_CODE (loc2) != JUMP_INSN | |
2888 | || (GET_CODE (PATTERN (loc2)) != ADDR_VEC | |
2889 | && GET_CODE (PATTERN (loc2)) != ADDR_DIFF_VEC)) | |
a2be868f | 2890 | && uid_loop[INSN_UID (loc)] == target_loop) |
b4ad7b23 RS |
2891 | break; |
2892 | ||
2893 | if (loc == 0) | |
2894 | for (loc = target; loc; loc = NEXT_INSN (loc)) | |
2895 | if (GET_CODE (loc) == BARRIER | |
17bec8ee BS |
2896 | /* Don't move things inside a tablejump. */ |
2897 | && ((loc2 = next_nonnote_insn (loc)) == 0 | |
2898 | || GET_CODE (loc2) != CODE_LABEL | |
2899 | || (loc2 = next_nonnote_insn (loc2)) == 0 | |
2900 | || GET_CODE (loc2) != JUMP_INSN | |
2901 | || (GET_CODE (PATTERN (loc2)) != ADDR_VEC | |
2902 | && GET_CODE (PATTERN (loc2)) != ADDR_DIFF_VEC)) | |
a2be868f | 2903 | && uid_loop[INSN_UID (loc)] == target_loop) |
b4ad7b23 RS |
2904 | break; |
2905 | ||
2906 | if (loc) | |
2907 | { | |
2908 | rtx cond_label = JUMP_LABEL (p); | |
2909 | rtx new_label = get_label_after (p); | |
2910 | ||
2911 | /* Ensure our label doesn't go away. */ | |
2912 | LABEL_NUSES (cond_label)++; | |
2913 | ||
a2be868f | 2914 | /* Verify that uid_loop is large enough and that |
0f41302f | 2915 | we can invert P. */ |
9ba11d5a RH |
2916 | if (invert_jump (p, new_label, 1)) |
2917 | { | |
2918 | rtx q, r; | |
2919 | ||
2920 | /* If no suitable BARRIER was found, create a suitable | |
2921 | one before TARGET. Since TARGET is a fall through | |
09da1532 | 2922 | path, we'll need to insert a jump around our block |
4fe9b91c | 2923 | and add a BARRIER before TARGET. |
9ba11d5a RH |
2924 | |
2925 | This creates an extra unconditional jump outside | |
2926 | the loop. However, the benefits of removing rarely | |
2927 | executed instructions from inside the loop usually | |
2928 | outweighs the cost of the extra unconditional jump | |
2929 | outside the loop. */ | |
2930 | if (loc == 0) | |
2931 | { | |
2932 | rtx temp; | |
2933 | ||
2934 | temp = gen_jump (JUMP_LABEL (insn)); | |
2935 | temp = emit_jump_insn_before (temp, target); | |
2936 | JUMP_LABEL (temp) = JUMP_LABEL (insn); | |
2937 | LABEL_NUSES (JUMP_LABEL (insn))++; | |
2938 | loc = emit_barrier_before (target); | |
2939 | } | |
2940 | ||
2941 | /* Include the BARRIER after INSN and copy the | |
2942 | block after LOC. */ | |
2b7d71b2 JJ |
2943 | if (squeeze_notes (&new_label, &last_insn_to_move)) |
2944 | abort (); | |
9ba11d5a RH |
2945 | reorder_insns (new_label, last_insn_to_move, loc); |
2946 | ||
2947 | /* All those insns are now in TARGET_LOOP. */ | |
e6fcb60d | 2948 | for (q = new_label; |
9ba11d5a RH |
2949 | q != NEXT_INSN (last_insn_to_move); |
2950 | q = NEXT_INSN (q)) | |
2951 | uid_loop[INSN_UID (q)] = target_loop; | |
2952 | ||
2953 | /* The label jumped to by INSN is no longer a loop | |
2954 | exit. Unless INSN does not have a label (e.g., | |
2955 | it is a RETURN insn), search loop->exit_labels | |
2956 | to find its label_ref, and remove it. Also turn | |
2957 | off LABEL_OUTSIDE_LOOP_P bit. */ | |
2958 | if (JUMP_LABEL (insn)) | |
2959 | { | |
fd5d5b07 KH |
2960 | for (q = 0, r = this_loop->exit_labels; |
2961 | r; | |
2962 | q = r, r = LABEL_NEXTREF (r)) | |
9ba11d5a RH |
2963 | if (XEXP (r, 0) == JUMP_LABEL (insn)) |
2964 | { | |
2965 | LABEL_OUTSIDE_LOOP_P (r) = 0; | |
2966 | if (q) | |
2967 | LABEL_NEXTREF (q) = LABEL_NEXTREF (r); | |
2968 | else | |
2969 | this_loop->exit_labels = LABEL_NEXTREF (r); | |
2970 | break; | |
2971 | } | |
2972 | ||
2973 | for (loop = this_loop; loop && loop != target_loop; | |
2974 | loop = loop->outer) | |
2975 | loop->exit_count--; | |
2976 | ||
2977 | /* If we didn't find it, then something is | |
2978 | wrong. */ | |
2979 | if (! r) | |
2980 | abort (); | |
2981 | } | |
2982 | ||
2983 | /* P is now a jump outside the loop, so it must be put | |
2984 | in loop->exit_labels, and marked as such. | |
2985 | The easiest way to do this is to just call | |
2986 | mark_loop_jump again for P. */ | |
2987 | mark_loop_jump (PATTERN (p), this_loop); | |
2988 | ||
2989 | /* If INSN now jumps to the insn after it, | |
2990 | delete INSN. */ | |
2991 | if (JUMP_LABEL (insn) != 0 | |
2992 | && (next_real_insn (JUMP_LABEL (insn)) | |
2993 | == next_real_insn (insn))) | |
53c17031 | 2994 | delete_related_insns (insn); |
9ba11d5a | 2995 | } |
b4ad7b23 RS |
2996 | |
2997 | /* Continue the loop after where the conditional | |
2998 | branch used to jump, since the only branch insn | |
2999 | in the block (if it still remains) is an inter-loop | |
3000 | branch and hence needs no processing. */ | |
3001 | insn = NEXT_INSN (cond_label); | |
3002 | ||
3003 | if (--LABEL_NUSES (cond_label) == 0) | |
53c17031 | 3004 | delete_related_insns (cond_label); |
3ad0cfaf RK |
3005 | |
3006 | /* This loop will be continued with NEXT_INSN (insn). */ | |
3007 | insn = PREV_INSN (insn); | |
b4ad7b23 RS |
3008 | } |
3009 | } | |
3010 | } | |
3011 | } | |
3012 | } | |
3013 | ||
3014 | /* If any label in X jumps to a loop different from LOOP_NUM and any of the | |
3015 | loops it is contained in, mark the target loop invalid. | |
3016 | ||
3017 | For speed, we assume that X is part of a pattern of a JUMP_INSN. */ | |
3018 | ||
3019 | static void | |
0c20a65f | 3020 | mark_loop_jump (rtx x, struct loop *loop) |
b4ad7b23 | 3021 | { |
a2be868f MH |
3022 | struct loop *dest_loop; |
3023 | struct loop *outer_loop; | |
b4ad7b23 RS |
3024 | int i; |
3025 | ||
3026 | switch (GET_CODE (x)) | |
3027 | { | |
3028 | case PC: | |
3029 | case USE: | |
3030 | case CLOBBER: | |
3031 | case REG: | |
3032 | case MEM: | |
3033 | case CONST_INT: | |
3034 | case CONST_DOUBLE: | |
3035 | case RETURN: | |
3036 | return; | |
3037 | ||
3038 | case CONST: | |
3039 | /* There could be a label reference in here. */ | |
a2be868f | 3040 | mark_loop_jump (XEXP (x, 0), loop); |
b4ad7b23 RS |
3041 | return; |
3042 | ||
3043 | case PLUS: | |
3044 | case MINUS: | |
3045 | case MULT: | |
a2be868f MH |
3046 | mark_loop_jump (XEXP (x, 0), loop); |
3047 | mark_loop_jump (XEXP (x, 1), loop); | |
b4ad7b23 RS |
3048 | return; |
3049 | ||
c4ae2725 JL |
3050 | case LO_SUM: |
3051 | /* This may refer to a LABEL_REF or SYMBOL_REF. */ | |
a2be868f | 3052 | mark_loop_jump (XEXP (x, 1), loop); |
c4ae2725 JL |
3053 | return; |
3054 | ||
b4ad7b23 RS |
3055 | case SIGN_EXTEND: |
3056 | case ZERO_EXTEND: | |
a2be868f | 3057 | mark_loop_jump (XEXP (x, 0), loop); |
b4ad7b23 RS |
3058 | return; |
3059 | ||
3060 | case LABEL_REF: | |
a2be868f | 3061 | dest_loop = uid_loop[INSN_UID (XEXP (x, 0))]; |
b4ad7b23 RS |
3062 | |
3063 | /* Link together all labels that branch outside the loop. This | |
3064 | is used by final_[bg]iv_value and the loop unrolling code. Also | |
3065 | mark this LABEL_REF so we know that this branch should predict | |
3066 | false. */ | |
3067 | ||
edf711a4 RK |
3068 | /* A check to make sure the label is not in an inner nested loop, |
3069 | since this does not count as a loop exit. */ | |
a2be868f | 3070 | if (dest_loop) |
edf711a4 | 3071 | { |
a2be868f MH |
3072 | for (outer_loop = dest_loop; outer_loop; |
3073 | outer_loop = outer_loop->outer) | |
3074 | if (outer_loop == loop) | |
edf711a4 RK |
3075 | break; |
3076 | } | |
3077 | else | |
a2be868f | 3078 | outer_loop = NULL; |
edf711a4 | 3079 | |
a2be868f | 3080 | if (loop && ! outer_loop) |
b4ad7b23 RS |
3081 | { |
3082 | LABEL_OUTSIDE_LOOP_P (x) = 1; | |
a2be868f MH |
3083 | LABEL_NEXTREF (x) = loop->exit_labels; |
3084 | loop->exit_labels = x; | |
353127c2 | 3085 | |
a2be868f MH |
3086 | for (outer_loop = loop; |
3087 | outer_loop && outer_loop != dest_loop; | |
3088 | outer_loop = outer_loop->outer) | |
3089 | outer_loop->exit_count++; | |
b4ad7b23 RS |
3090 | } |
3091 | ||
3092 | /* If this is inside a loop, but not in the current loop or one enclosed | |
3093 | by it, it invalidates at least one loop. */ | |
3094 | ||
a2be868f | 3095 | if (! dest_loop) |
b4ad7b23 RS |
3096 | return; |
3097 | ||
3098 | /* We must invalidate every nested loop containing the target of this | |
3099 | label, except those that also contain the jump insn. */ | |
3100 | ||
a2be868f | 3101 | for (; dest_loop; dest_loop = dest_loop->outer) |
b4ad7b23 RS |
3102 | { |
3103 | /* Stop when we reach a loop that also contains the jump insn. */ | |
a2be868f | 3104 | for (outer_loop = loop; outer_loop; outer_loop = outer_loop->outer) |
b4ad7b23 RS |
3105 | if (dest_loop == outer_loop) |
3106 | return; | |
3107 | ||
3108 | /* If we get here, we know we need to invalidate a loop. */ | |
a2be868f | 3109 | if (loop_dump_stream && ! dest_loop->invalid) |
b4ad7b23 RS |
3110 | fprintf (loop_dump_stream, |
3111 | "\nLoop at %d ignored due to multiple entry points.\n", | |
a2be868f | 3112 | INSN_UID (dest_loop->start)); |
e6fcb60d | 3113 | |
a2be868f | 3114 | dest_loop->invalid = 1; |
b4ad7b23 RS |
3115 | } |
3116 | return; | |
3117 | ||
3118 | case SET: | |
3119 | /* If this is not setting pc, ignore. */ | |
3120 | if (SET_DEST (x) == pc_rtx) | |
a2be868f | 3121 | mark_loop_jump (SET_SRC (x), loop); |
b4ad7b23 RS |
3122 | return; |
3123 | ||
3124 | case IF_THEN_ELSE: | |
a2be868f MH |
3125 | mark_loop_jump (XEXP (x, 1), loop); |
3126 | mark_loop_jump (XEXP (x, 2), loop); | |
b4ad7b23 RS |
3127 | return; |
3128 | ||
3129 | case PARALLEL: | |
3130 | case ADDR_VEC: | |
3131 | for (i = 0; i < XVECLEN (x, 0); i++) | |
a2be868f | 3132 | mark_loop_jump (XVECEXP (x, 0, i), loop); |
b4ad7b23 RS |
3133 | return; |
3134 | ||
3135 | case ADDR_DIFF_VEC: | |
3136 | for (i = 0; i < XVECLEN (x, 1); i++) | |
a2be868f | 3137 | mark_loop_jump (XVECEXP (x, 1, i), loop); |
b4ad7b23 RS |
3138 | return; |
3139 | ||
3140 | default: | |
c4ae2725 JL |
3141 | /* Strictly speaking this is not a jump into the loop, only a possible |
3142 | jump out of the loop. However, we have no way to link the destination | |
3143 | of this jump onto the list of exit labels. To be safe we mark this | |
3144 | loop and any containing loops as invalid. */ | |
a2be868f | 3145 | if (loop) |
353127c2 | 3146 | { |
a2be868f | 3147 | for (outer_loop = loop; outer_loop; outer_loop = outer_loop->outer) |
c4ae2725 | 3148 | { |
a2be868f | 3149 | if (loop_dump_stream && ! outer_loop->invalid) |
c4ae2725 JL |
3150 | fprintf (loop_dump_stream, |
3151 | "\nLoop at %d ignored due to unknown exit jump.\n", | |
a2be868f MH |
3152 | INSN_UID (outer_loop->start)); |
3153 | outer_loop->invalid = 1; | |
c4ae2725 | 3154 | } |
353127c2 | 3155 | } |
b6ccc3fb | 3156 | return; |
b4ad7b23 RS |
3157 | } |
3158 | } | |
3159 | \f | |
3160 | /* Return nonzero if there is a label in the range from | |
3161 | insn INSN to and including the insn whose luid is END | |
3162 | INSN must have an assigned luid (i.e., it must not have | |
3163 | been previously created by loop.c). */ | |
3164 | ||
3165 | static int | |
0c20a65f | 3166 | labels_in_range_p (rtx insn, int end) |
b4ad7b23 RS |
3167 | { |
3168 | while (insn && INSN_LUID (insn) <= end) | |
3169 | { | |
3170 | if (GET_CODE (insn) == CODE_LABEL) | |
3171 | return 1; | |
3172 | insn = NEXT_INSN (insn); | |
3173 | } | |
3174 | ||
3175 | return 0; | |
3176 | } | |
3177 | ||
3178 | /* Record that a memory reference X is being set. */ | |
3179 | ||
3180 | static void | |
0c20a65f AJ |
3181 | note_addr_stored (rtx x, rtx y ATTRIBUTE_UNUSED, |
3182 | void *data ATTRIBUTE_UNUSED) | |
b4ad7b23 | 3183 | { |
afa1738b MH |
3184 | struct loop_info *loop_info = data; |
3185 | ||
b4ad7b23 RS |
3186 | if (x == 0 || GET_CODE (x) != MEM) |
3187 | return; | |
3188 | ||
3189 | /* Count number of memory writes. | |
3190 | This affects heuristics in strength_reduce. */ | |
afa1738b | 3191 | loop_info->num_mem_sets++; |
fd5d5b07 | 3192 | |
ca800983 | 3193 | /* BLKmode MEM means all memory is clobbered. */ |
afa1738b | 3194 | if (GET_MODE (x) == BLKmode) |
14a774a9 RK |
3195 | { |
3196 | if (RTX_UNCHANGING_P (x)) | |
afa1738b | 3197 | loop_info->unknown_constant_address_altered = 1; |
14a774a9 | 3198 | else |
afa1738b | 3199 | loop_info->unknown_address_altered = 1; |
fd5d5b07 | 3200 | |
14a774a9 RK |
3201 | return; |
3202 | } | |
fd5d5b07 KH |
3203 | |
3204 | loop_info->store_mems = gen_rtx_EXPR_LIST (VOIDmode, x, | |
afa1738b | 3205 | loop_info->store_mems); |
b4ad7b23 | 3206 | } |
59487769 JL |
3207 | |
3208 | /* X is a value modified by an INSN that references a biv inside a loop | |
3209 | exit test (ie, X is somehow related to the value of the biv). If X | |
3210 | is a pseudo that is used more than once, then the biv is (effectively) | |
635a2a90 | 3211 | used more than once. DATA is a pointer to a loop_regs structure. */ |
59487769 JL |
3212 | |
3213 | static void | |
0c20a65f | 3214 | note_set_pseudo_multiple_uses (rtx x, rtx y ATTRIBUTE_UNUSED, void *data) |
59487769 | 3215 | { |
1ecd860b MH |
3216 | struct loop_regs *regs = (struct loop_regs *) data; |
3217 | ||
59487769 JL |
3218 | if (x == 0) |
3219 | return; | |
3220 | ||
3221 | while (GET_CODE (x) == STRICT_LOW_PART | |
3222 | || GET_CODE (x) == SIGN_EXTRACT | |
3223 | || GET_CODE (x) == ZERO_EXTRACT | |
3224 | || GET_CODE (x) == SUBREG) | |
3225 | x = XEXP (x, 0); | |
3226 | ||
3227 | if (GET_CODE (x) != REG || REGNO (x) < FIRST_PSEUDO_REGISTER) | |
3228 | return; | |
3229 | ||
3230 | /* If we do not have usage information, or if we know the register | |
3231 | is used more than once, note that fact for check_dbra_loop. */ | |
3232 | if (REGNO (x) >= max_reg_before_loop | |
f1d4ac80 MH |
3233 | || ! regs->array[REGNO (x)].single_usage |
3234 | || regs->array[REGNO (x)].single_usage == const0_rtx) | |
635a2a90 | 3235 | regs->multiple_uses = 1; |
59487769 | 3236 | } |
b4ad7b23 RS |
3237 | \f |
3238 | /* Return nonzero if the rtx X is invariant over the current loop. | |
3239 | ||
3240 | The value is 2 if we refer to something only conditionally invariant. | |
3241 | ||
20bd7bfa | 3242 | A memory ref is invariant if it is not volatile and does not conflict |
afa1738b | 3243 | with anything stored in `loop_info->store_mems'. */ |
b4ad7b23 RS |
3244 | |
3245 | int | |
0c20a65f | 3246 | loop_invariant_p (const struct loop *loop, rtx x) |
b4ad7b23 | 3247 | { |
afa1738b | 3248 | struct loop_info *loop_info = LOOP_INFO (loop); |
1ecd860b | 3249 | struct loop_regs *regs = LOOP_REGS (loop); |
b3694847 SS |
3250 | int i; |
3251 | enum rtx_code code; | |
3252 | const char *fmt; | |
b4ad7b23 | 3253 | int conditional = 0; |
5026a502 | 3254 | rtx mem_list_entry; |
b4ad7b23 RS |
3255 | |
3256 | if (x == 0) | |
3257 | return 1; | |
3258 | code = GET_CODE (x); | |
3259 | switch (code) | |
3260 | { | |
3261 | case CONST_INT: | |
3262 | case CONST_DOUBLE: | |
3263 | case SYMBOL_REF: | |
3264 | case CONST: | |
3265 | return 1; | |
3266 | ||
3267 | case LABEL_REF: | |
3268 | /* A LABEL_REF is normally invariant, however, if we are unrolling | |
3269 | loops, and this label is inside the loop, then it isn't invariant. | |
3270 | This is because each unrolled copy of the loop body will have | |
3271 | a copy of this label. If this was invariant, then an insn loading | |
3272 | the address of this label into a register might get moved outside | |
3273 | the loop, and then each loop body would end up using the same label. | |
3274 | ||
3275 | We don't know the loop bounds here though, so just fail for all | |
3276 | labels. */ | |
b17d5d7c | 3277 | if (flag_old_unroll_loops) |
b4ad7b23 RS |
3278 | return 0; |
3279 | else | |
3280 | return 1; | |
3281 | ||
3282 | case PC: | |
3283 | case CC0: | |
3284 | case UNSPEC_VOLATILE: | |
3285 | return 0; | |
3286 | ||
3287 | case REG: | |
3288 | /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid | |
3289 | since the reg might be set by initialization within the loop. */ | |
1f027d54 RK |
3290 | |
3291 | if ((x == frame_pointer_rtx || x == hard_frame_pointer_rtx | |
71cef493 | 3292 | || x == arg_pointer_rtx || x == pic_offset_table_rtx) |
1f027d54 | 3293 | && ! current_function_has_nonlocal_goto) |
b4ad7b23 | 3294 | return 1; |
1f027d54 | 3295 | |
0534b804 | 3296 | if (LOOP_INFO (loop)->has_call |
b4ad7b23 RS |
3297 | && REGNO (x) < FIRST_PSEUDO_REGISTER && call_used_regs[REGNO (x)]) |
3298 | return 0; | |
1f027d54 | 3299 | |
2aff9508 DJ |
3300 | /* Out-of-range regs can occur when we are called from unrolling. |
3301 | These have always been created by the unroller and are set in | |
32dd366d | 3302 | the loop, hence are never invariant. */ |
2aff9508 | 3303 | |
fc555370 | 3304 | if (REGNO (x) >= (unsigned) regs->num) |
2aff9508 DJ |
3305 | return 0; |
3306 | ||
f1d4ac80 | 3307 | if (regs->array[REGNO (x)].set_in_loop < 0) |
b4ad7b23 | 3308 | return 2; |
1f027d54 | 3309 | |
f1d4ac80 | 3310 | return regs->array[REGNO (x)].set_in_loop == 0; |
b4ad7b23 RS |
3311 | |
3312 | case MEM: | |
d5e3f151 JW |
3313 | /* Volatile memory references must be rejected. Do this before |
3314 | checking for read-only items, so that volatile read-only items | |
3315 | will be rejected also. */ | |
3316 | if (MEM_VOLATILE_P (x)) | |
3317 | return 0; | |
3318 | ||
b4ad7b23 | 3319 | /* See if there is any dependence between a store and this load. */ |
afa1738b | 3320 | mem_list_entry = loop_info->store_mems; |
5026a502 JL |
3321 | while (mem_list_entry) |
3322 | { | |
3323 | if (true_dependence (XEXP (mem_list_entry, 0), VOIDmode, | |
3324 | x, rtx_varies_p)) | |
3325 | return 0; | |
14a774a9 | 3326 | |
5026a502 JL |
3327 | mem_list_entry = XEXP (mem_list_entry, 1); |
3328 | } | |
b4ad7b23 RS |
3329 | |
3330 | /* It's not invalidated by a store in memory | |
3331 | but we must still verify the address is invariant. */ | |
3332 | break; | |
3333 | ||
3334 | case ASM_OPERANDS: | |
3335 | /* Don't mess with insns declared volatile. */ | |
3336 | if (MEM_VOLATILE_P (x)) | |
3337 | return 0; | |
e9a25f70 | 3338 | break; |
e6fcb60d | 3339 | |
e9a25f70 JL |
3340 | default: |
3341 | break; | |
b4ad7b23 RS |
3342 | } |
3343 | ||
3344 | fmt = GET_RTX_FORMAT (code); | |
3345 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3346 | { | |
3347 | if (fmt[i] == 'e') | |
3348 | { | |
0534b804 | 3349 | int tem = loop_invariant_p (loop, XEXP (x, i)); |
b4ad7b23 RS |
3350 | if (tem == 0) |
3351 | return 0; | |
3352 | if (tem == 2) | |
3353 | conditional = 1; | |
3354 | } | |
3355 | else if (fmt[i] == 'E') | |
3356 | { | |
b3694847 | 3357 | int j; |
b4ad7b23 RS |
3358 | for (j = 0; j < XVECLEN (x, i); j++) |
3359 | { | |
0534b804 | 3360 | int tem = loop_invariant_p (loop, XVECEXP (x, i, j)); |
b4ad7b23 RS |
3361 | if (tem == 0) |
3362 | return 0; | |
3363 | if (tem == 2) | |
3364 | conditional = 1; | |
3365 | } | |
3366 | ||
3367 | } | |
3368 | } | |
3369 | ||
3370 | return 1 + conditional; | |
3371 | } | |
b4ad7b23 RS |
3372 | \f |
3373 | /* Return nonzero if all the insns in the loop that set REG | |
3374 | are INSN and the immediately following insns, | |
3375 | and if each of those insns sets REG in an invariant way | |
3376 | (not counting uses of REG in them). | |
3377 | ||
3378 | The value is 2 if some of these insns are only conditionally invariant. | |
3379 | ||
3380 | We assume that INSN itself is the first set of REG | |
3381 | and that its source is invariant. */ | |
3382 | ||
3383 | static int | |
0c20a65f AJ |
3384 | consec_sets_invariant_p (const struct loop *loop, rtx reg, int n_sets, |
3385 | rtx insn) | |
b4ad7b23 | 3386 | { |
1ecd860b | 3387 | struct loop_regs *regs = LOOP_REGS (loop); |
770ae6cc RK |
3388 | rtx p = insn; |
3389 | unsigned int regno = REGNO (reg); | |
b4ad7b23 RS |
3390 | rtx temp; |
3391 | /* Number of sets we have to insist on finding after INSN. */ | |
3392 | int count = n_sets - 1; | |
f1d4ac80 | 3393 | int old = regs->array[regno].set_in_loop; |
b4ad7b23 RS |
3394 | int value = 0; |
3395 | int this; | |
3396 | ||
3397 | /* If N_SETS hit the limit, we can't rely on its value. */ | |
3398 | if (n_sets == 127) | |
3399 | return 0; | |
3400 | ||
f1d4ac80 | 3401 | regs->array[regno].set_in_loop = 0; |
b4ad7b23 RS |
3402 | |
3403 | while (count > 0) | |
3404 | { | |
b3694847 | 3405 | enum rtx_code code; |
b4ad7b23 RS |
3406 | rtx set; |
3407 | ||
3408 | p = NEXT_INSN (p); | |
3409 | code = GET_CODE (p); | |
3410 | ||
38e01259 | 3411 | /* If library call, skip to end of it. */ |
5fd8383e | 3412 | if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
3413 | p = XEXP (temp, 0); |
3414 | ||
3415 | this = 0; | |
3416 | if (code == INSN | |
3417 | && (set = single_set (p)) | |
3418 | && GET_CODE (SET_DEST (set)) == REG | |
3419 | && REGNO (SET_DEST (set)) == regno) | |
3420 | { | |
0534b804 | 3421 | this = loop_invariant_p (loop, SET_SRC (set)); |
b4ad7b23 RS |
3422 | if (this != 0) |
3423 | value |= this; | |
51723711 | 3424 | else if ((temp = find_reg_note (p, REG_EQUAL, NULL_RTX))) |
b4ad7b23 | 3425 | { |
83d90aac JW |
3426 | /* If this is a libcall, then any invariant REG_EQUAL note is OK. |
3427 | If this is an ordinary insn, then only CONSTANT_P REG_EQUAL | |
3428 | notes are OK. */ | |
3429 | this = (CONSTANT_P (XEXP (temp, 0)) | |
3430 | || (find_reg_note (p, REG_RETVAL, NULL_RTX) | |
0534b804 | 3431 | && loop_invariant_p (loop, XEXP (temp, 0)))); |
b4ad7b23 RS |
3432 | if (this != 0) |
3433 | value |= this; | |
3434 | } | |
3435 | } | |
3436 | if (this != 0) | |
3437 | count--; | |
3438 | else if (code != NOTE) | |
3439 | { | |
f1d4ac80 | 3440 | regs->array[regno].set_in_loop = old; |
b4ad7b23 RS |
3441 | return 0; |
3442 | } | |
3443 | } | |
3444 | ||
f1d4ac80 | 3445 | regs->array[regno].set_in_loop = old; |
0534b804 | 3446 | /* If loop_invariant_p ever returned 2, we return 2. */ |
b4ad7b23 RS |
3447 | return 1 + (value & 2); |
3448 | } | |
3449 | ||
3450 | #if 0 | |
3451 | /* I don't think this condition is sufficient to allow INSN | |
3452 | to be moved, so we no longer test it. */ | |
3453 | ||
3454 | /* Return 1 if all insns in the basic block of INSN and following INSN | |
3455 | that set REG are invariant according to TABLE. */ | |
3456 | ||
3457 | static int | |
0c20a65f | 3458 | all_sets_invariant_p (rtx reg, rtx insn, short *table) |
b4ad7b23 | 3459 | { |
b3694847 SS |
3460 | rtx p = insn; |
3461 | int regno = REGNO (reg); | |
b4ad7b23 RS |
3462 | |
3463 | while (1) | |
3464 | { | |
b3694847 | 3465 | enum rtx_code code; |
b4ad7b23 RS |
3466 | p = NEXT_INSN (p); |
3467 | code = GET_CODE (p); | |
3468 | if (code == CODE_LABEL || code == JUMP_INSN) | |
3469 | return 1; | |
3470 | if (code == INSN && GET_CODE (PATTERN (p)) == SET | |
3471 | && GET_CODE (SET_DEST (PATTERN (p))) == REG | |
3472 | && REGNO (SET_DEST (PATTERN (p))) == regno) | |
3473 | { | |
0534b804 | 3474 | if (! loop_invariant_p (loop, SET_SRC (PATTERN (p)), table)) |
b4ad7b23 RS |
3475 | return 0; |
3476 | } | |
3477 | } | |
3478 | } | |
3479 | #endif /* 0 */ | |
3480 | \f | |
3481 | /* Look at all uses (not sets) of registers in X. For each, if it is | |
3482 | the single use, set USAGE[REGNO] to INSN; if there was a previous use in | |
3483 | a different insn, set USAGE[REGNO] to const0_rtx. */ | |
3484 | ||
3485 | static void | |
0c20a65f | 3486 | find_single_use_in_loop (struct loop_regs *regs, rtx insn, rtx x) |
b4ad7b23 RS |
3487 | { |
3488 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 3489 | const char *fmt = GET_RTX_FORMAT (code); |
b4ad7b23 RS |
3490 | int i, j; |
3491 | ||
3492 | if (code == REG) | |
f1d4ac80 MH |
3493 | regs->array[REGNO (x)].single_usage |
3494 | = (regs->array[REGNO (x)].single_usage != 0 | |
3495 | && regs->array[REGNO (x)].single_usage != insn) | |
b4ad7b23 RS |
3496 | ? const0_rtx : insn; |
3497 | ||
3498 | else if (code == SET) | |
3499 | { | |
3500 | /* Don't count SET_DEST if it is a REG; otherwise count things | |
3501 | in SET_DEST because if a register is partially modified, it won't | |
e6fcb60d | 3502 | show up as a potential movable so we don't care how USAGE is set |
b4ad7b23 RS |
3503 | for it. */ |
3504 | if (GET_CODE (SET_DEST (x)) != REG) | |
f1d4ac80 MH |
3505 | find_single_use_in_loop (regs, insn, SET_DEST (x)); |
3506 | find_single_use_in_loop (regs, insn, SET_SRC (x)); | |
b4ad7b23 RS |
3507 | } |
3508 | else | |
3509 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3510 | { | |
3511 | if (fmt[i] == 'e' && XEXP (x, i) != 0) | |
f1d4ac80 | 3512 | find_single_use_in_loop (regs, insn, XEXP (x, i)); |
b4ad7b23 RS |
3513 | else if (fmt[i] == 'E') |
3514 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f1d4ac80 | 3515 | find_single_use_in_loop (regs, insn, XVECEXP (x, i, j)); |
b4ad7b23 RS |
3516 | } |
3517 | } | |
3518 | \f | |
a4c3ddd8 | 3519 | /* Count and record any set in X which is contained in INSN. Update |
f1d4ac80 MH |
3520 | REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set |
3521 | in X. */ | |
a4c3ddd8 BS |
3522 | |
3523 | static void | |
0c20a65f | 3524 | count_one_set (struct loop_regs *regs, rtx insn, rtx x, rtx *last_set) |
a4c3ddd8 BS |
3525 | { |
3526 | if (GET_CODE (x) == CLOBBER && GET_CODE (XEXP (x, 0)) == REG) | |
3527 | /* Don't move a reg that has an explicit clobber. | |
3528 | It's not worth the pain to try to do it correctly. */ | |
f1d4ac80 | 3529 | regs->array[REGNO (XEXP (x, 0))].may_not_optimize = 1; |
a4c3ddd8 BS |
3530 | |
3531 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
3532 | { | |
3533 | rtx dest = SET_DEST (x); | |
3534 | while (GET_CODE (dest) == SUBREG | |
3535 | || GET_CODE (dest) == ZERO_EXTRACT | |
3536 | || GET_CODE (dest) == SIGN_EXTRACT | |
3537 | || GET_CODE (dest) == STRICT_LOW_PART) | |
3538 | dest = XEXP (dest, 0); | |
3539 | if (GET_CODE (dest) == REG) | |
3540 | { | |
d5e0243a | 3541 | int i; |
b3694847 | 3542 | int regno = REGNO (dest); |
44a5565d | 3543 | for (i = 0; i < LOOP_REGNO_NREGS (regno, dest); i++) |
d5e0243a DE |
3544 | { |
3545 | /* If this is the first setting of this reg | |
3546 | in current basic block, and it was set before, | |
3547 | it must be set in two basic blocks, so it cannot | |
3548 | be moved out of the loop. */ | |
3549 | if (regs->array[regno].set_in_loop > 0 | |
51a7f205 | 3550 | && last_set[regno] == 0) |
d5e0243a DE |
3551 | regs->array[regno+i].may_not_optimize = 1; |
3552 | /* If this is not first setting in current basic block, | |
3553 | see if reg was used in between previous one and this. | |
3554 | If so, neither one can be moved. */ | |
3555 | if (last_set[regno] != 0 | |
3556 | && reg_used_between_p (dest, last_set[regno], insn)) | |
3557 | regs->array[regno+i].may_not_optimize = 1; | |
3558 | if (regs->array[regno+i].set_in_loop < 127) | |
3559 | ++regs->array[regno+i].set_in_loop; | |
3560 | last_set[regno+i] = insn; | |
3561 | } | |
a4c3ddd8 BS |
3562 | } |
3563 | } | |
3564 | } | |
b4ad7b23 | 3565 | \f |
0534b804 MH |
3566 | /* Given a loop that is bounded by LOOP->START and LOOP->END and that |
3567 | is entered at LOOP->SCAN_START, return 1 if the register set in SET | |
3568 | contained in insn INSN is used by any insn that precedes INSN in | |
3569 | cyclic order starting from the loop entry point. | |
b4ad7b23 RS |
3570 | |
3571 | We don't want to use INSN_LUID here because if we restrict INSN to those | |
3572 | that have a valid INSN_LUID, it means we cannot move an invariant out | |
3573 | from an inner loop past two loops. */ | |
3574 | ||
3575 | static int | |
0c20a65f | 3576 | loop_reg_used_before_p (const struct loop *loop, rtx set, rtx insn) |
b4ad7b23 RS |
3577 | { |
3578 | rtx reg = SET_DEST (set); | |
3579 | rtx p; | |
3580 | ||
3581 | /* Scan forward checking for register usage. If we hit INSN, we | |
a2be868f MH |
3582 | are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */ |
3583 | for (p = loop->scan_start; p != insn; p = NEXT_INSN (p)) | |
b4ad7b23 | 3584 | { |
2c3c49de | 3585 | if (INSN_P (p) && reg_overlap_mentioned_p (reg, PATTERN (p))) |
b4ad7b23 RS |
3586 | return 1; |
3587 | ||
a2be868f MH |
3588 | if (p == loop->end) |
3589 | p = loop->start; | |
b4ad7b23 RS |
3590 | } |
3591 | ||
3592 | return 0; | |
3593 | } | |
3594 | \f | |
0dd0e980 JH |
3595 | |
3596 | /* Information we collect about arrays that we might want to prefetch. */ | |
3597 | struct prefetch_info | |
3598 | { | |
3599 | struct iv_class *class; /* Class this prefetch is based on. */ | |
3600 | struct induction *giv; /* GIV this prefetch is based on. */ | |
3601 | rtx base_address; /* Start prefetching from this address plus | |
3602 | index. */ | |
3603 | HOST_WIDE_INT index; | |
3604 | HOST_WIDE_INT stride; /* Prefetch stride in bytes in each | |
3605 | iteration. */ | |
3dc60fc7 | 3606 | unsigned int bytes_accessed; /* Sum of sizes of all accesses to this |
0dd0e980 JH |
3607 | prefetch area in one iteration. */ |
3608 | unsigned int total_bytes; /* Total bytes loop will access in this block. | |
3609 | This is set only for loops with known | |
3610 | iteration counts and is 0xffffffff | |
3611 | otherwise. */ | |
62e6ca55 JJ |
3612 | int prefetch_in_loop; /* Number of prefetch insns in loop. */ |
3613 | int prefetch_before_loop; /* Number of prefetch insns before loop. */ | |
0dd0e980 | 3614 | unsigned int write : 1; /* 1 for read/write prefetches. */ |
0dd0e980 JH |
3615 | }; |
3616 | ||
3617 | /* Data used by check_store function. */ | |
3618 | struct check_store_data | |
3619 | { | |
3620 | rtx mem_address; | |
3621 | int mem_write; | |
3622 | }; | |
3623 | ||
0c20a65f AJ |
3624 | static void check_store (rtx, rtx, void *); |
3625 | static void emit_prefetch_instructions (struct loop *); | |
3626 | static int rtx_equal_for_prefetch_p (rtx, rtx); | |
0dd0e980 JH |
3627 | |
3628 | /* Set mem_write when mem_address is found. Used as callback to | |
3629 | note_stores. */ | |
3630 | static void | |
0c20a65f | 3631 | check_store (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data) |
0dd0e980 | 3632 | { |
505ddab6 | 3633 | struct check_store_data *d = (struct check_store_data *) data; |
0dd0e980 JH |
3634 | |
3635 | if ((GET_CODE (x) == MEM) && rtx_equal_p (d->mem_address, XEXP (x, 0))) | |
3636 | d->mem_write = 1; | |
3637 | } | |
3638 | \f | |
3639 | /* Like rtx_equal_p, but attempts to swap commutative operands. This is | |
3640 | important to get some addresses combined. Later more sophisticated | |
3d042e77 | 3641 | transformations can be added when necessary. |
0dd0e980 JH |
3642 | |
3643 | ??? Same trick with swapping operand is done at several other places. | |
3644 | It can be nice to develop some common way to handle this. */ | |
3645 | ||
3646 | static int | |
0c20a65f | 3647 | rtx_equal_for_prefetch_p (rtx x, rtx y) |
0dd0e980 JH |
3648 | { |
3649 | int i; | |
3650 | int j; | |
3651 | enum rtx_code code = GET_CODE (x); | |
3652 | const char *fmt; | |
3653 | ||
3654 | if (x == y) | |
3655 | return 1; | |
3656 | if (code != GET_CODE (y)) | |
3657 | return 0; | |
3658 | ||
3659 | code = GET_CODE (x); | |
3660 | ||
3661 | if (GET_RTX_CLASS (code) == 'c') | |
3662 | { | |
3663 | return ((rtx_equal_for_prefetch_p (XEXP (x, 0), XEXP (y, 0)) | |
3664 | && rtx_equal_for_prefetch_p (XEXP (x, 1), XEXP (y, 1))) | |
3665 | || (rtx_equal_for_prefetch_p (XEXP (x, 0), XEXP (y, 1)) | |
3666 | && rtx_equal_for_prefetch_p (XEXP (x, 1), XEXP (y, 0)))); | |
3667 | } | |
3668 | /* Compare the elements. If any pair of corresponding elements fails to | |
3669 | match, return 0 for the whole thing. */ | |
3670 | ||
3671 | fmt = GET_RTX_FORMAT (code); | |
3672 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3673 | { | |
3674 | switch (fmt[i]) | |
3675 | { | |
3676 | case 'w': | |
3677 | if (XWINT (x, i) != XWINT (y, i)) | |
3678 | return 0; | |
3679 | break; | |
3680 | ||
3681 | case 'i': | |
3682 | if (XINT (x, i) != XINT (y, i)) | |
3683 | return 0; | |
3684 | break; | |
3685 | ||
3686 | case 'E': | |
3687 | /* Two vectors must have the same length. */ | |
3688 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
3689 | return 0; | |
3690 | ||
3691 | /* And the corresponding elements must match. */ | |
3692 | for (j = 0; j < XVECLEN (x, i); j++) | |
3693 | if (rtx_equal_for_prefetch_p (XVECEXP (x, i, j), | |
3694 | XVECEXP (y, i, j)) == 0) | |
3695 | return 0; | |
3696 | break; | |
3697 | ||
3698 | case 'e': | |
3699 | if (rtx_equal_for_prefetch_p (XEXP (x, i), XEXP (y, i)) == 0) | |
3700 | return 0; | |
3701 | break; | |
3702 | ||
3703 | case 's': | |
3704 | if (strcmp (XSTR (x, i), XSTR (y, i))) | |
3705 | return 0; | |
3706 | break; | |
3707 | ||
3708 | case 'u': | |
3709 | /* These are just backpointers, so they don't matter. */ | |
3710 | break; | |
3711 | ||
3712 | case '0': | |
3713 | break; | |
3714 | ||
3715 | /* It is believed that rtx's at this level will never | |
3716 | contain anything but integers and other rtx's, | |
3717 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
3718 | default: | |
3719 | abort (); | |
3720 | } | |
3721 | } | |
3722 | return 1; | |
3723 | } | |
3724 | \f | |
3725 | /* Remove constant addition value from the expression X (when present) | |
3726 | and return it. */ | |
62ab1caf | 3727 | |
0dd0e980 | 3728 | static HOST_WIDE_INT |
0c20a65f | 3729 | remove_constant_addition (rtx *x) |
0dd0e980 JH |
3730 | { |
3731 | HOST_WIDE_INT addval = 0; | |
62ab1caf | 3732 | rtx exp = *x; |
0dd0e980 | 3733 | |
a2cd028f | 3734 | /* Avoid clobbering a shared CONST expression. */ |
0dd0e980 | 3735 | if (GET_CODE (exp) == CONST) |
a2cd028f JJ |
3736 | { |
3737 | if (GET_CODE (XEXP (exp, 0)) == PLUS | |
3738 | && GET_CODE (XEXP (XEXP (exp, 0), 0)) == SYMBOL_REF | |
3739 | && GET_CODE (XEXP (XEXP (exp, 0), 1)) == CONST_INT) | |
3740 | { | |
3741 | *x = XEXP (XEXP (exp, 0), 0); | |
3742 | return INTVAL (XEXP (XEXP (exp, 0), 1)); | |
3743 | } | |
3744 | return 0; | |
3745 | } | |
3746 | ||
0dd0e980 JH |
3747 | if (GET_CODE (exp) == CONST_INT) |
3748 | { | |
3749 | addval = INTVAL (exp); | |
3750 | *x = const0_rtx; | |
3751 | } | |
62ab1caf | 3752 | |
0dd0e980 JH |
3753 | /* For plus expression recurse on ourself. */ |
3754 | else if (GET_CODE (exp) == PLUS) | |
3755 | { | |
3756 | addval += remove_constant_addition (&XEXP (exp, 0)); | |
3757 | addval += remove_constant_addition (&XEXP (exp, 1)); | |
62ab1caf RK |
3758 | |
3759 | /* In case our parameter was constant, remove extra zero from the | |
3760 | expression. */ | |
0dd0e980 | 3761 | if (XEXP (exp, 0) == const0_rtx) |
e11e816e | 3762 | *x = XEXP (exp, 1); |
0dd0e980 | 3763 | else if (XEXP (exp, 1) == const0_rtx) |
e11e816e | 3764 | *x = XEXP (exp, 0); |
0dd0e980 | 3765 | } |
62ab1caf | 3766 | |
0dd0e980 JH |
3767 | return addval; |
3768 | } | |
3769 | ||
3770 | /* Attempt to identify accesses to arrays that are most likely to cause cache | |
3771 | misses, and emit prefetch instructions a few prefetch blocks forward. | |
3772 | ||
3773 | To detect the arrays we use the GIV information that was collected by the | |
3774 | strength reduction pass. | |
3775 | ||
3776 | The prefetch instructions are generated after the GIV information is done | |
3777 | and before the strength reduction process. The new GIVs are injected into | |
3778 | the strength reduction tables, so the prefetch addresses are optimized as | |
3779 | well. | |
3780 | ||
3781 | GIVs are split into base address, stride, and constant addition values. | |
3782 | GIVs with the same address, stride and close addition values are combined | |
3783 | into a single prefetch. Also writes to GIVs are detected, so that prefetch | |
3784 | for write instructions can be used for the block we write to, on machines | |
3785 | that support write prefetches. | |
3786 | ||
3787 | Several heuristics are used to determine when to prefetch. They are | |
3a79cccb | 3788 | controlled by defined symbols that can be overridden for each target. */ |
62ab1caf | 3789 | |
0dd0e980 | 3790 | static void |
0c20a65f | 3791 | emit_prefetch_instructions (struct loop *loop) |
0dd0e980 JH |
3792 | { |
3793 | int num_prefetches = 0; | |
3794 | int num_real_prefetches = 0; | |
3795 | int num_real_write_prefetches = 0; | |
62e6ca55 JJ |
3796 | int num_prefetches_before = 0; |
3797 | int num_write_prefetches_before = 0; | |
3798 | int ahead = 0; | |
0dd0e980 JH |
3799 | int i; |
3800 | struct iv_class *bl; | |
3801 | struct induction *iv; | |
3802 | struct prefetch_info info[MAX_PREFETCHES]; | |
3803 | struct loop_ivs *ivs = LOOP_IVS (loop); | |
3804 | ||
3805 | if (!HAVE_prefetch) | |
3806 | return; | |
3807 | ||
3808 | /* Consider only loops w/o calls. When a call is done, the loop is probably | |
3809 | slow enough to read the memory. */ | |
3810 | if (PREFETCH_NO_CALL && LOOP_INFO (loop)->has_call) | |
3811 | { | |
3812 | if (loop_dump_stream) | |
79a497cd | 3813 | fprintf (loop_dump_stream, "Prefetch: ignoring loop: has call.\n"); |
62ab1caf | 3814 | |
0dd0e980 JH |
3815 | return; |
3816 | } | |
3817 | ||
79a497cd | 3818 | /* Don't prefetch in loops known to have few iterations. */ |
0dd0e980 JH |
3819 | if (PREFETCH_NO_LOW_LOOPCNT |
3820 | && LOOP_INFO (loop)->n_iterations | |
3821 | && LOOP_INFO (loop)->n_iterations <= PREFETCH_LOW_LOOPCNT) | |
3822 | { | |
3823 | if (loop_dump_stream) | |
3824 | fprintf (loop_dump_stream, | |
79a497cd | 3825 | "Prefetch: ignoring loop: not enough iterations.\n"); |
0dd0e980 JH |
3826 | return; |
3827 | } | |
3828 | ||
3829 | /* Search all induction variables and pick those interesting for the prefetch | |
3830 | machinery. */ | |
3831 | for (bl = ivs->list; bl; bl = bl->next) | |
3832 | { | |
3833 | struct induction *biv = bl->biv, *biv1; | |
3834 | int basestride = 0; | |
3835 | ||
3836 | biv1 = biv; | |
62ab1caf | 3837 | |
0dd0e980 JH |
3838 | /* Expect all BIVs to be executed in each iteration. This makes our |
3839 | analysis more conservative. */ | |
3840 | while (biv1) | |
3841 | { | |
3842 | /* Discard non-constant additions that we can't handle well yet, and | |
3843 | BIVs that are executed multiple times; such BIVs ought to be | |
3844 | handled in the nested loop. We accept not_every_iteration BIVs, | |
3845 | since these only result in larger strides and make our | |
79a497cd | 3846 | heuristics more conservative. */ |
0dd0e980 JH |
3847 | if (GET_CODE (biv->add_val) != CONST_INT) |
3848 | { | |
3849 | if (loop_dump_stream) | |
3850 | { | |
62ab1caf | 3851 | fprintf (loop_dump_stream, |
79a497cd | 3852 | "Prefetch: ignoring biv %d: non-constant addition at insn %d:", |
0dd0e980 JH |
3853 | REGNO (biv->src_reg), INSN_UID (biv->insn)); |
3854 | print_rtl (loop_dump_stream, biv->add_val); | |
3855 | fprintf (loop_dump_stream, "\n"); | |
3856 | } | |
3857 | break; | |
3858 | } | |
62ab1caf | 3859 | |
0dd0e980 JH |
3860 | if (biv->maybe_multiple) |
3861 | { | |
3862 | if (loop_dump_stream) | |
3863 | { | |
62ab1caf | 3864 | fprintf (loop_dump_stream, |
79a497cd | 3865 | "Prefetch: ignoring biv %d: maybe_multiple at insn %i:", |
0dd0e980 JH |
3866 | REGNO (biv->src_reg), INSN_UID (biv->insn)); |
3867 | print_rtl (loop_dump_stream, biv->add_val); | |
3868 | fprintf (loop_dump_stream, "\n"); | |
3869 | } | |
3870 | break; | |
3871 | } | |
62ab1caf | 3872 | |
0dd0e980 JH |
3873 | basestride += INTVAL (biv1->add_val); |
3874 | biv1 = biv1->next_iv; | |
3875 | } | |
62ab1caf | 3876 | |
0dd0e980 JH |
3877 | if (biv1 || !basestride) |
3878 | continue; | |
62ab1caf | 3879 | |
0dd0e980 JH |
3880 | for (iv = bl->giv; iv; iv = iv->next_iv) |
3881 | { | |
3882 | rtx address; | |
3883 | rtx temp; | |
3884 | HOST_WIDE_INT index = 0; | |
3885 | int add = 1; | |
79a497cd JJ |
3886 | HOST_WIDE_INT stride = 0; |
3887 | int stride_sign = 1; | |
0dd0e980 | 3888 | struct check_store_data d; |
79a497cd | 3889 | const char *ignore_reason = NULL; |
0dd0e980 JH |
3890 | int size = GET_MODE_SIZE (GET_MODE (iv)); |
3891 | ||
79a497cd JJ |
3892 | /* See whether an induction variable is interesting to us and if |
3893 | not, report the reason. */ | |
3894 | if (iv->giv_type != DEST_ADDR) | |
3895 | ignore_reason = "giv is not a destination address"; | |
3896 | ||
3897 | /* We are interested only in constant stride memory references | |
3898 | in order to be able to compute density easily. */ | |
3899 | else if (GET_CODE (iv->mult_val) != CONST_INT) | |
3900 | ignore_reason = "stride is not constant"; | |
3901 | ||
3902 | else | |
3903 | { | |
3904 | stride = INTVAL (iv->mult_val) * basestride; | |
3905 | if (stride < 0) | |
62e6ca55 | 3906 | { |
79a497cd JJ |
3907 | stride = -stride; |
3908 | stride_sign = -1; | |
62e6ca55 | 3909 | } |
79a497cd JJ |
3910 | |
3911 | /* On some targets, reversed order prefetches are not | |
62e6ca55 | 3912 | worthwhile. */ |
79a497cd JJ |
3913 | if (PREFETCH_NO_REVERSE_ORDER && stride_sign < 0) |
3914 | ignore_reason = "reversed order stride"; | |
3915 | ||
3916 | /* Prefetch of accesses with an extreme stride might not be | |
62e6ca55 | 3917 | worthwhile, either. */ |
79a497cd JJ |
3918 | else if (PREFETCH_NO_EXTREME_STRIDE |
3919 | && stride > PREFETCH_EXTREME_STRIDE) | |
3920 | ignore_reason = "extreme stride"; | |
3921 | ||
62ab1caf | 3922 | /* Ignore GIVs with varying add values; we can't predict the |
62e6ca55 | 3923 | value for the next iteration. */ |
79a497cd JJ |
3924 | else if (!loop_invariant_p (loop, iv->add_val)) |
3925 | ignore_reason = "giv has varying add value"; | |
3926 | ||
62ab1caf | 3927 | /* Ignore GIVs in the nested loops; they ought to have been |
62e6ca55 | 3928 | handled already. */ |
79a497cd JJ |
3929 | else if (iv->maybe_multiple) |
3930 | ignore_reason = "giv is in nested loop"; | |
3931 | } | |
3932 | ||
3933 | if (ignore_reason != NULL) | |
0dd0e980 JH |
3934 | { |
3935 | if (loop_dump_stream) | |
79a497cd JJ |
3936 | fprintf (loop_dump_stream, |
3937 | "Prefetch: ignoring giv at %d: %s.\n", | |
3938 | INSN_UID (iv->insn), ignore_reason); | |
0dd0e980 JH |
3939 | continue; |
3940 | } | |
3941 | ||
3942 | /* Determine the pointer to the basic array we are examining. It is | |
3943 | the sum of the BIV's initial value and the GIV's add_val. */ | |
0dd0e980 JH |
3944 | address = copy_rtx (iv->add_val); |
3945 | temp = copy_rtx (bl->initial_value); | |
3946 | ||
3947 | address = simplify_gen_binary (PLUS, Pmode, temp, address); | |
3948 | index = remove_constant_addition (&address); | |
3949 | ||
0dd0e980 JH |
3950 | d.mem_write = 0; |
3951 | d.mem_address = *iv->location; | |
62ab1caf | 3952 | |
0dd0e980 JH |
3953 | /* When the GIV is not always executed, we might be better off by |
3954 | not dirtying the cache pages. */ | |
79a497cd | 3955 | if (PREFETCH_CONDITIONAL || iv->always_executed) |
0dd0e980 | 3956 | note_stores (PATTERN (iv->insn), check_store, &d); |
62e6ca55 JJ |
3957 | else |
3958 | { | |
3959 | if (loop_dump_stream) | |
3960 | fprintf (loop_dump_stream, "Prefetch: Ignoring giv at %d: %s\n", | |
3961 | INSN_UID (iv->insn), "in conditional code."); | |
3962 | continue; | |
3963 | } | |
0dd0e980 JH |
3964 | |
3965 | /* Attempt to find another prefetch to the same array and see if we | |
3966 | can merge this one. */ | |
3967 | for (i = 0; i < num_prefetches; i++) | |
3968 | if (rtx_equal_for_prefetch_p (address, info[i].base_address) | |
3969 | && stride == info[i].stride) | |
3970 | { | |
3971 | /* In case both access same array (same location | |
3972 | just with small difference in constant indexes), merge | |
3973 | the prefetches. Just do the later and the earlier will | |
3974 | get prefetched from previous iteration. | |
79a497cd | 3975 | The artificial threshold should not be too small, |
0dd0e980 JH |
3976 | but also not bigger than small portion of memory usually |
3977 | traversed by single loop. */ | |
79a497cd JJ |
3978 | if (index >= info[i].index |
3979 | && index - info[i].index < PREFETCH_EXTREME_DIFFERENCE) | |
0dd0e980 JH |
3980 | { |
3981 | info[i].write |= d.mem_write; | |
79a497cd | 3982 | info[i].bytes_accessed += size; |
0dd0e980 JH |
3983 | info[i].index = index; |
3984 | info[i].giv = iv; | |
3985 | info[i].class = bl; | |
3986 | info[num_prefetches].base_address = address; | |
3987 | add = 0; | |
3988 | break; | |
3989 | } | |
62ab1caf | 3990 | |
79a497cd JJ |
3991 | if (index < info[i].index |
3992 | && info[i].index - index < PREFETCH_EXTREME_DIFFERENCE) | |
0dd0e980 JH |
3993 | { |
3994 | info[i].write |= d.mem_write; | |
79a497cd | 3995 | info[i].bytes_accessed += size; |
0dd0e980 JH |
3996 | add = 0; |
3997 | break; | |
3998 | } | |
3999 | } | |
62ab1caf | 4000 | |
0dd0e980 JH |
4001 | /* Merging failed. */ |
4002 | if (add) | |
4003 | { | |
4004 | info[num_prefetches].giv = iv; | |
4005 | info[num_prefetches].class = bl; | |
4006 | info[num_prefetches].index = index; | |
4007 | info[num_prefetches].stride = stride; | |
4008 | info[num_prefetches].base_address = address; | |
4009 | info[num_prefetches].write = d.mem_write; | |
79a497cd | 4010 | info[num_prefetches].bytes_accessed = size; |
0dd0e980 JH |
4011 | num_prefetches++; |
4012 | if (num_prefetches >= MAX_PREFETCHES) | |
4013 | { | |
4014 | if (loop_dump_stream) | |
62ab1caf RK |
4015 | fprintf (loop_dump_stream, |
4016 | "Maximal number of prefetches exceeded.\n"); | |
0dd0e980 JH |
4017 | return; |
4018 | } | |
4019 | } | |
4020 | } | |
4021 | } | |
62ab1caf | 4022 | |
0dd0e980 JH |
4023 | for (i = 0; i < num_prefetches; i++) |
4024 | { | |
79a497cd JJ |
4025 | int density; |
4026 | ||
4027 | /* Attempt to calculate the total number of bytes fetched by all | |
4028 | iterations of the loop. Avoid overflow. */ | |
0dd0e980 | 4029 | if (LOOP_INFO (loop)->n_iterations |
62e6ca55 | 4030 | && ((unsigned HOST_WIDE_INT) (0xffffffff / info[i].stride) |
62ab1caf | 4031 | >= LOOP_INFO (loop)->n_iterations)) |
0dd0e980 JH |
4032 | info[i].total_bytes = info[i].stride * LOOP_INFO (loop)->n_iterations; |
4033 | else | |
4034 | info[i].total_bytes = 0xffffffff; | |
4035 | ||
79a497cd JJ |
4036 | density = info[i].bytes_accessed * 100 / info[i].stride; |
4037 | ||
4038 | /* Prefetch might be worthwhile only when the loads/stores are dense. */ | |
4039 | if (PREFETCH_ONLY_DENSE_MEM) | |
4040 | if (density * 256 > PREFETCH_DENSE_MEM * 100 | |
4041 | && (info[i].total_bytes / PREFETCH_BLOCK | |
62e6ca55 | 4042 | >= PREFETCH_BLOCKS_BEFORE_LOOP_MIN)) |
79a497cd JJ |
4043 | { |
4044 | info[i].prefetch_before_loop = 1; | |
4045 | info[i].prefetch_in_loop | |
4046 | = (info[i].total_bytes / PREFETCH_BLOCK | |
62e6ca55 | 4047 | > PREFETCH_BLOCKS_BEFORE_LOOP_MAX); |
79a497cd | 4048 | } |
62e6ca55 | 4049 | else |
79a497cd JJ |
4050 | { |
4051 | info[i].prefetch_in_loop = 0, info[i].prefetch_before_loop = 0; | |
4052 | if (loop_dump_stream) | |
4053 | fprintf (loop_dump_stream, | |
4054 | "Prefetch: ignoring giv at %d: %d%% density is too low.\n", | |
4055 | INSN_UID (info[i].giv->insn), density); | |
4056 | } | |
0dd0e980 | 4057 | else |
79a497cd | 4058 | info[i].prefetch_in_loop = 1, info[i].prefetch_before_loop = 1; |
0dd0e980 | 4059 | |
62e6ca55 JJ |
4060 | /* Find how many prefetch instructions we'll use within the loop. */ |
4061 | if (info[i].prefetch_in_loop != 0) | |
0dd0e980 | 4062 | { |
62e6ca55 | 4063 | info[i].prefetch_in_loop = ((info[i].stride + PREFETCH_BLOCK - 1) |
0dd0e980 | 4064 | / PREFETCH_BLOCK); |
62e6ca55 | 4065 | num_real_prefetches += info[i].prefetch_in_loop; |
0dd0e980 | 4066 | if (info[i].write) |
62e6ca55 | 4067 | num_real_write_prefetches += info[i].prefetch_in_loop; |
0dd0e980 JH |
4068 | } |
4069 | } | |
62ab1caf | 4070 | |
62e6ca55 JJ |
4071 | /* Determine how many iterations ahead to prefetch within the loop, based |
4072 | on how many prefetches we currently expect to do within the loop. */ | |
4073 | if (num_real_prefetches != 0) | |
4074 | { | |
4075 | if ((ahead = SIMULTANEOUS_PREFETCHES / num_real_prefetches) == 0) | |
4076 | { | |
4077 | if (loop_dump_stream) | |
4078 | fprintf (loop_dump_stream, | |
4079 | "Prefetch: ignoring prefetches within loop: ahead is zero; %d < %d\n", | |
4080 | SIMULTANEOUS_PREFETCHES, num_real_prefetches); | |
4081 | num_real_prefetches = 0, num_real_write_prefetches = 0; | |
4082 | } | |
4083 | } | |
4084 | /* We'll also use AHEAD to determine how many prefetch instructions to | |
4085 | emit before a loop, so don't leave it zero. */ | |
4086 | if (ahead == 0) | |
4087 | ahead = PREFETCH_BLOCKS_BEFORE_LOOP_MAX; | |
4088 | ||
4089 | for (i = 0; i < num_prefetches; i++) | |
0dd0e980 | 4090 | { |
62e6ca55 JJ |
4091 | /* Update if we've decided not to prefetch anything within the loop. */ |
4092 | if (num_real_prefetches == 0) | |
4093 | info[i].prefetch_in_loop = 0; | |
4094 | ||
4095 | /* Find how many prefetch instructions we'll use before the loop. */ | |
4096 | if (info[i].prefetch_before_loop != 0) | |
4097 | { | |
4098 | int n = info[i].total_bytes / PREFETCH_BLOCK; | |
4099 | if (n > ahead) | |
4100 | n = ahead; | |
4101 | info[i].prefetch_before_loop = n; | |
4102 | num_prefetches_before += n; | |
4103 | if (info[i].write) | |
4104 | num_write_prefetches_before += n; | |
4105 | } | |
4106 | ||
4107 | if (loop_dump_stream) | |
0dd0e980 | 4108 | { |
79a497cd JJ |
4109 | if (info[i].prefetch_in_loop == 0 |
4110 | && info[i].prefetch_before_loop == 0) | |
4111 | continue; | |
4112 | fprintf (loop_dump_stream, "Prefetch insn: %d", | |
0dd0e980 | 4113 | INSN_UID (info[i].giv->insn)); |
62ab1caf | 4114 | fprintf (loop_dump_stream, |
62e6ca55 JJ |
4115 | "; in loop: %d; before: %d; %s\n", |
4116 | info[i].prefetch_in_loop, | |
4117 | info[i].prefetch_before_loop, | |
79a497cd JJ |
4118 | info[i].write ? "read/write" : "read only"); |
4119 | fprintf (loop_dump_stream, | |
4120 | " density: %d%%; bytes_accessed: %u; total_bytes: %u\n", | |
4121 | (int) (info[i].bytes_accessed * 100 / info[i].stride), | |
4122 | info[i].bytes_accessed, info[i].total_bytes); | |
90ff44cf KG |
4123 | fprintf (loop_dump_stream, " index: " HOST_WIDE_INT_PRINT_DEC |
4124 | "; stride: " HOST_WIDE_INT_PRINT_DEC "; address: ", | |
4125 | info[i].index, info[i].stride); | |
79a497cd JJ |
4126 | print_rtl (loop_dump_stream, info[i].base_address); |
4127 | fprintf (loop_dump_stream, "\n"); | |
0dd0e980 | 4128 | } |
0dd0e980 JH |
4129 | } |
4130 | ||
62e6ca55 | 4131 | if (num_real_prefetches + num_prefetches_before > 0) |
79a497cd | 4132 | { |
62e6ca55 JJ |
4133 | /* Record that this loop uses prefetch instructions. */ |
4134 | LOOP_INFO (loop)->has_prefetch = 1; | |
4135 | ||
79a497cd | 4136 | if (loop_dump_stream) |
62e6ca55 JJ |
4137 | { |
4138 | fprintf (loop_dump_stream, "Real prefetches needed within loop: %d (write: %d)\n", | |
4139 | num_real_prefetches, num_real_write_prefetches); | |
4140 | fprintf (loop_dump_stream, "Real prefetches needed before loop: %d (write: %d)\n", | |
4141 | num_prefetches_before, num_write_prefetches_before); | |
4142 | } | |
79a497cd | 4143 | } |
62ab1caf | 4144 | |
0dd0e980 JH |
4145 | for (i = 0; i < num_prefetches; i++) |
4146 | { | |
62e6ca55 | 4147 | int y; |
62ab1caf | 4148 | |
62e6ca55 JJ |
4149 | for (y = 0; y < info[i].prefetch_in_loop; y++) |
4150 | { | |
4151 | rtx loc = copy_rtx (*info[i].giv->location); | |
4152 | rtx insn; | |
4153 | int bytes_ahead = PREFETCH_BLOCK * (ahead + y); | |
4154 | rtx before_insn = info[i].giv->insn; | |
4155 | rtx prev_insn = PREV_INSN (info[i].giv->insn); | |
ba4f7968 | 4156 | rtx seq; |
62e6ca55 JJ |
4157 | |
4158 | /* We can save some effort by offsetting the address on | |
4159 | architectures with offsettable memory references. */ | |
4160 | if (offsettable_address_p (0, VOIDmode, loc)) | |
4161 | loc = plus_constant (loc, bytes_ahead); | |
4162 | else | |
0dd0e980 | 4163 | { |
62e6ca55 JJ |
4164 | rtx reg = gen_reg_rtx (Pmode); |
4165 | loop_iv_add_mult_emit_before (loop, loc, const1_rtx, | |
0c20a65f AJ |
4166 | GEN_INT (bytes_ahead), reg, |
4167 | 0, before_insn); | |
62e6ca55 JJ |
4168 | loc = reg; |
4169 | } | |
0dd0e980 | 4170 | |
ba4f7968 | 4171 | start_sequence (); |
62e6ca55 JJ |
4172 | /* Make sure the address operand is valid for prefetch. */ |
4173 | if (! (*insn_data[(int)CODE_FOR_prefetch].operand[0].predicate) | |
4174 | (loc, insn_data[(int)CODE_FOR_prefetch].operand[0].mode)) | |
4175 | loc = force_reg (Pmode, loc); | |
ba4f7968 JH |
4176 | emit_insn (gen_prefetch (loc, GEN_INT (info[i].write), |
4177 | GEN_INT (3))); | |
2f937369 | 4178 | seq = get_insns (); |
ba4f7968 JH |
4179 | end_sequence (); |
4180 | emit_insn_before (seq, before_insn); | |
62e6ca55 JJ |
4181 | |
4182 | /* Check all insns emitted and record the new GIV | |
4183 | information. */ | |
4184 | insn = NEXT_INSN (prev_insn); | |
4185 | while (insn != before_insn) | |
4186 | { | |
4187 | insn = check_insn_for_givs (loop, insn, | |
4188 | info[i].giv->always_executed, | |
4189 | info[i].giv->maybe_multiple); | |
4190 | insn = NEXT_INSN (insn); | |
0dd0e980 JH |
4191 | } |
4192 | } | |
62ab1caf | 4193 | |
62e6ca55 | 4194 | if (PREFETCH_BEFORE_LOOP) |
0dd0e980 | 4195 | { |
62e6ca55 JJ |
4196 | /* Emit insns before the loop to fetch the first cache lines or, |
4197 | if we're not prefetching within the loop, everything we expect | |
4198 | to need. */ | |
4199 | for (y = 0; y < info[i].prefetch_before_loop; y++) | |
0dd0e980 JH |
4200 | { |
4201 | rtx reg = gen_reg_rtx (Pmode); | |
4202 | rtx loop_start = loop->start; | |
62e6ca55 | 4203 | rtx init_val = info[i].class->initial_value; |
0dd0e980 JH |
4204 | rtx add_val = simplify_gen_binary (PLUS, Pmode, |
4205 | info[i].giv->add_val, | |
4206 | GEN_INT (y * PREFETCH_BLOCK)); | |
62ab1caf | 4207 | |
62e6ca55 JJ |
4208 | /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a |
4209 | non-constant INIT_VAL to have the same mode as REG, which | |
4210 | in this case we know to be Pmode. */ | |
4211 | if (GET_MODE (init_val) != Pmode && !CONSTANT_P (init_val)) | |
b0c42aed JH |
4212 | { |
4213 | rtx seq; | |
4214 | ||
4215 | start_sequence (); | |
4216 | init_val = convert_to_mode (Pmode, init_val, 0); | |
4217 | seq = get_insns (); | |
4218 | end_sequence (); | |
4219 | loop_insn_emit_before (loop, 0, loop_start, seq); | |
4220 | } | |
62e6ca55 | 4221 | loop_iv_add_mult_emit_before (loop, init_val, |
0dd0e980 | 4222 | info[i].giv->mult_val, |
62e6ca55 | 4223 | add_val, reg, 0, loop_start); |
0dd0e980 | 4224 | emit_insn_before (gen_prefetch (reg, GEN_INT (info[i].write), |
62ab1caf RK |
4225 | GEN_INT (3)), |
4226 | loop_start); | |
0dd0e980 JH |
4227 | } |
4228 | } | |
4229 | } | |
62ab1caf | 4230 | |
0dd0e980 JH |
4231 | return; |
4232 | } | |
4233 | \f | |
b4ad7b23 RS |
4234 | /* Communication with routines called via `note_stores'. */ |
4235 | ||
4236 | static rtx note_insn; | |
4237 | ||
cc2902df | 4238 | /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */ |
b4ad7b23 RS |
4239 | |
4240 | static rtx addr_placeholder; | |
4241 | ||
4242 | /* ??? Unfinished optimizations, and possible future optimizations, | |
4243 | for the strength reduction code. */ | |
4244 | ||
b4ad7b23 | 4245 | /* ??? The interaction of biv elimination, and recognition of 'constant' |
0f41302f | 4246 | bivs, may cause problems. */ |
b4ad7b23 RS |
4247 | |
4248 | /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause | |
4249 | performance problems. | |
4250 | ||
4251 | Perhaps don't eliminate things that can be combined with an addressing | |
4252 | mode. Find all givs that have the same biv, mult_val, and add_val; | |
4253 | then for each giv, check to see if its only use dies in a following | |
4254 | memory address. If so, generate a new memory address and check to see | |
4255 | if it is valid. If it is valid, then store the modified memory address, | |
4256 | otherwise, mark the giv as not done so that it will get its own iv. */ | |
4257 | ||
4258 | /* ??? Could try to optimize branches when it is known that a biv is always | |
4259 | positive. */ | |
4260 | ||
4261 | /* ??? When replace a biv in a compare insn, we should replace with closest | |
4262 | giv so that an optimized branch can still be recognized by the combiner, | |
4263 | e.g. the VAX acb insn. */ | |
4264 | ||
4265 | /* ??? Many of the checks involving uid_luid could be simplified if regscan | |
4266 | was rerun in loop_optimize whenever a register was added or moved. | |
4267 | Also, some of the optimizations could be a little less conservative. */ | |
4268 | \f | |
5e787f07 JH |
4269 | /* Scan the loop body and call FNCALL for each insn. In the addition to the |
4270 | LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the | |
4271 | callback. | |
e6fcb60d | 4272 | |
048c8616 EB |
4273 | NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at |
4274 | least once for every loop iteration except for the last one. | |
5e787f07 JH |
4275 | |
4276 | MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every | |
4277 | loop iteration. | |
4278 | */ | |
4279 | void | |
0c20a65f | 4280 | for_each_insn_in_loop (struct loop *loop, loop_insn_callback fncall) |
b4ad7b23 | 4281 | { |
b4ad7b23 | 4282 | int not_every_iteration = 0; |
7dcd3836 | 4283 | int maybe_multiple = 0; |
ae188a87 | 4284 | int past_loop_latch = 0; |
5ea7a4ae | 4285 | int loop_depth = 0; |
5e787f07 | 4286 | rtx p; |
b4ad7b23 | 4287 | |
a2be868f | 4288 | /* If loop_scan_start points to the loop exit test, we have to be wary of |
5353610b | 4289 | subversive use of gotos inside expression statements. */ |
5e787f07 JH |
4290 | if (prev_nonnote_insn (loop->scan_start) != prev_nonnote_insn (loop->start)) |
4291 | maybe_multiple = back_branch_in_range_p (loop, loop->scan_start); | |
b4ad7b23 | 4292 | |
4b7e68e7 | 4293 | /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */ |
5e787f07 | 4294 | for (p = next_insn_in_loop (loop, loop->scan_start); |
41a972a9 | 4295 | p != NULL_RTX; |
a2be868f | 4296 | p = next_insn_in_loop (loop, p)) |
b4ad7b23 | 4297 | { |
c35971c8 | 4298 | p = fncall (loop, p, not_every_iteration, maybe_multiple); |
b4ad7b23 | 4299 | |
7dcd3836 | 4300 | /* Past CODE_LABEL, we get to insns that may be executed multiple |
5e787f07 JH |
4301 | times. The only way we can be sure that they can't is if every |
4302 | jump insn between here and the end of the loop either | |
4303 | returns, exits the loop, is a jump to a location that is still | |
4304 | behind the label, or is a jump to the loop start. */ | |
7dcd3836 RK |
4305 | |
4306 | if (GET_CODE (p) == CODE_LABEL) | |
4307 | { | |
4308 | rtx insn = p; | |
4309 | ||
4310 | maybe_multiple = 0; | |
4311 | ||
4312 | while (1) | |
4313 | { | |
4314 | insn = NEXT_INSN (insn); | |
5e787f07 | 4315 | if (insn == loop->scan_start) |
7dcd3836 | 4316 | break; |
5e787f07 | 4317 | if (insn == loop->end) |
7dcd3836 | 4318 | { |
5e787f07 JH |
4319 | if (loop->top != 0) |
4320 | insn = loop->top; | |
7dcd3836 RK |
4321 | else |
4322 | break; | |
5e787f07 | 4323 | if (insn == loop->scan_start) |
7dcd3836 RK |
4324 | break; |
4325 | } | |
4326 | ||
4327 | if (GET_CODE (insn) == JUMP_INSN | |
4328 | && GET_CODE (PATTERN (insn)) != RETURN | |
7f1c097d | 4329 | && (!any_condjump_p (insn) |
7dcd3836 | 4330 | || (JUMP_LABEL (insn) != 0 |
5e787f07 JH |
4331 | && JUMP_LABEL (insn) != loop->scan_start |
4332 | && !loop_insn_first_p (p, JUMP_LABEL (insn))))) | |
8516af93 JW |
4333 | { |
4334 | maybe_multiple = 1; | |
4335 | break; | |
4336 | } | |
7dcd3836 RK |
4337 | } |
4338 | } | |
4339 | ||
8516af93 | 4340 | /* Past a jump, we get to insns for which we can't count |
5e787f07 | 4341 | on whether they will be executed during each iteration. */ |
8516af93 | 4342 | /* This code appears twice in strength_reduce. There is also similar |
5e787f07 | 4343 | code in scan_loop. */ |
8516af93 | 4344 | if (GET_CODE (p) == JUMP_INSN |
5e787f07 JH |
4345 | /* If we enter the loop in the middle, and scan around to the |
4346 | beginning, don't set not_every_iteration for that. | |
4347 | This can be any kind of jump, since we want to know if insns | |
4348 | will be executed if the loop is executed. */ | |
4349 | && !(JUMP_LABEL (p) == loop->top | |
048c8616 EB |
4350 | && ((NEXT_INSN (NEXT_INSN (p)) == loop->end |
4351 | && any_uncondjump_p (p)) | |
4352 | || (NEXT_INSN (p) == loop->end && any_condjump_p (p))))) | |
8516af93 JW |
4353 | { |
4354 | rtx label = 0; | |
4355 | ||
4356 | /* If this is a jump outside the loop, then it also doesn't | |
4357 | matter. Check to see if the target of this branch is on the | |
a2be868f | 4358 | loop->exits_labels list. */ |
5e787f07 | 4359 | |
0534b804 | 4360 | for (label = loop->exit_labels; label; label = LABEL_NEXTREF (label)) |
8516af93 JW |
4361 | if (XEXP (label, 0) == JUMP_LABEL (p)) |
4362 | break; | |
4363 | ||
5e787f07 | 4364 | if (!label) |
8516af93 JW |
4365 | not_every_iteration = 1; |
4366 | } | |
b4ad7b23 | 4367 | |
5ea7a4ae JW |
4368 | else if (GET_CODE (p) == NOTE) |
4369 | { | |
4370 | /* At the virtual top of a converted loop, insns are again known to | |
4371 | be executed each iteration: logically, the loop begins here | |
5f3db57e JL |
4372 | even though the exit code has been duplicated. |
4373 | ||
4374 | Insns are also again known to be executed each iteration at | |
4375 | the LOOP_CONT note. */ | |
4376 | if ((NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP | |
4377 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_CONT) | |
4378 | && loop_depth == 0) | |
5ea7a4ae JW |
4379 | not_every_iteration = 0; |
4380 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) | |
4381 | loop_depth++; | |
4382 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END) | |
4383 | loop_depth--; | |
4384 | } | |
b4ad7b23 | 4385 | |
ae188a87 | 4386 | /* Note if we pass a loop latch. If we do, then we can not clear |
5e787f07 JH |
4387 | NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in |
4388 | a loop since a jump before the last CODE_LABEL may have started | |
4389 | a new loop iteration. | |
4390 | ||
4391 | Note that LOOP_TOP is only set for rotated loops and we need | |
4392 | this check for all loops, so compare against the CODE_LABEL | |
4393 | which immediately follows LOOP_START. */ | |
4394 | if (GET_CODE (p) == JUMP_INSN | |
4395 | && JUMP_LABEL (p) == NEXT_INSN (loop->start)) | |
ae188a87 JL |
4396 | past_loop_latch = 1; |
4397 | ||
b4ad7b23 | 4398 | /* Unlike in the code motion pass where MAYBE_NEVER indicates that |
5e787f07 JH |
4399 | an insn may never be executed, NOT_EVERY_ITERATION indicates whether |
4400 | or not an insn is known to be executed each iteration of the | |
4401 | loop, whether or not any iterations are known to occur. | |
b4ad7b23 | 4402 | |
5e787f07 JH |
4403 | Therefore, if we have just passed a label and have no more labels |
4404 | between here and the test insn of the loop, and we have not passed | |
4405 | a jump to the top of the loop, then we know these insns will be | |
4406 | executed each iteration. */ | |
b4ad7b23 | 4407 | |
5e787f07 JH |
4408 | if (not_every_iteration |
4409 | && !past_loop_latch | |
ae188a87 | 4410 | && GET_CODE (p) == CODE_LABEL |
5e787f07 JH |
4411 | && no_labels_between_p (p, loop->end) |
4412 | && loop_insn_first_p (p, loop->cont)) | |
b4ad7b23 RS |
4413 | not_every_iteration = 0; |
4414 | } | |
5e787f07 JH |
4415 | } |
4416 | \f | |
5e787f07 | 4417 | static void |
0c20a65f | 4418 | loop_bivs_find (struct loop *loop) |
5e787f07 | 4419 | { |
1ecd860b | 4420 | struct loop_regs *regs = LOOP_REGS (loop); |
ed5bb68d | 4421 | struct loop_ivs *ivs = LOOP_IVS (loop); |
14be28e5 | 4422 | /* Temporary list pointers for traversing ivs->list. */ |
5e787f07 | 4423 | struct iv_class *bl, **backbl; |
5e787f07 | 4424 | |
14be28e5 | 4425 | ivs->list = 0; |
5e787f07 | 4426 | |
5e787f07 | 4427 | for_each_insn_in_loop (loop, check_insn_for_bivs); |
6b8c9327 | 4428 | |
14be28e5 | 4429 | /* Scan ivs->list to remove all regs that proved not to be bivs. |
1ecd860b | 4430 | Make a sanity check against regs->n_times_set. */ |
14be28e5 | 4431 | for (backbl = &ivs->list, bl = *backbl; bl; bl = bl->next) |
b4ad7b23 | 4432 | { |
ed5bb68d | 4433 | if (REG_IV_TYPE (ivs, bl->regno) != BASIC_INDUCT |
b4ad7b23 RS |
4434 | /* Above happens if register modified by subreg, etc. */ |
4435 | /* Make sure it is not recognized as a basic induction var: */ | |
f1d4ac80 | 4436 | || regs->array[bl->regno].n_times_set != bl->biv_count |
b4ad7b23 RS |
4437 | /* If never incremented, it is invariant that we decided not to |
4438 | move. So leave it alone. */ | |
4439 | || ! bl->incremented) | |
4440 | { | |
4441 | if (loop_dump_stream) | |
c804f3f8 | 4442 | fprintf (loop_dump_stream, "Biv %d: discarded, %s\n", |
b4ad7b23 | 4443 | bl->regno, |
ed5bb68d | 4444 | (REG_IV_TYPE (ivs, bl->regno) != BASIC_INDUCT |
b4ad7b23 RS |
4445 | ? "not induction variable" |
4446 | : (! bl->incremented ? "never incremented" | |
4447 | : "count error"))); | |
e6fcb60d | 4448 | |
ed5bb68d | 4449 | REG_IV_TYPE (ivs, bl->regno) = NOT_BASIC_INDUCT; |
b4ad7b23 RS |
4450 | *backbl = bl->next; |
4451 | } | |
4452 | else | |
4453 | { | |
4454 | backbl = &bl->next; | |
4455 | ||
4456 | if (loop_dump_stream) | |
c804f3f8 | 4457 | fprintf (loop_dump_stream, "Biv %d: verified\n", bl->regno); |
b4ad7b23 RS |
4458 | } |
4459 | } | |
6ec73c7c | 4460 | } |
b4ad7b23 | 4461 | |
b4ad7b23 | 4462 | |
4912a07c | 4463 | /* Determine how BIVS are initialized by looking through pre-header |
6ec73c7c MH |
4464 | extended basic block. */ |
4465 | static void | |
0c20a65f | 4466 | loop_bivs_init_find (struct loop *loop) |
6ec73c7c | 4467 | { |
6ec73c7c | 4468 | struct loop_ivs *ivs = LOOP_IVS (loop); |
14be28e5 | 4469 | /* Temporary list pointers for traversing ivs->list. */ |
6ec73c7c | 4470 | struct iv_class *bl; |
e304a8e6 MH |
4471 | int call_seen; |
4472 | rtx p; | |
b4ad7b23 RS |
4473 | |
4474 | /* Find initial value for each biv by searching backwards from loop_start, | |
4475 | halting at first label. Also record any test condition. */ | |
4476 | ||
4477 | call_seen = 0; | |
e304a8e6 | 4478 | for (p = loop->start; p && GET_CODE (p) != CODE_LABEL; p = PREV_INSN (p)) |
b4ad7b23 | 4479 | { |
e304a8e6 MH |
4480 | rtx test; |
4481 | ||
b4ad7b23 RS |
4482 | note_insn = p; |
4483 | ||
4484 | if (GET_CODE (p) == CALL_INSN) | |
4485 | call_seen = 1; | |
4486 | ||
ce7de04c | 4487 | if (INSN_P (p)) |
ed5bb68d | 4488 | note_stores (PATTERN (p), record_initial, ivs); |
b4ad7b23 RS |
4489 | |
4490 | /* Record any test of a biv that branches around the loop if no store | |
4491 | between it and the start of loop. We only care about tests with | |
4492 | constants and registers and only certain of those. */ | |
4493 | if (GET_CODE (p) == JUMP_INSN | |
4494 | && JUMP_LABEL (p) != 0 | |
e304a8e6 | 4495 | && next_real_insn (JUMP_LABEL (p)) == next_real_insn (loop->end) |
0534b804 | 4496 | && (test = get_condition_for_loop (loop, p)) != 0 |
b4ad7b23 RS |
4497 | && GET_CODE (XEXP (test, 0)) == REG |
4498 | && REGNO (XEXP (test, 0)) < max_reg_before_loop | |
8b634749 | 4499 | && (bl = REG_IV_CLASS (ivs, REGNO (XEXP (test, 0)))) != 0 |
e304a8e6 | 4500 | && valid_initial_value_p (XEXP (test, 1), p, call_seen, loop->start) |
b4ad7b23 RS |
4501 | && bl->init_insn == 0) |
4502 | { | |
4503 | /* If an NE test, we have an initial value! */ | |
4504 | if (GET_CODE (test) == NE) | |
4505 | { | |
4506 | bl->init_insn = p; | |
38a448ca RH |
4507 | bl->init_set = gen_rtx_SET (VOIDmode, |
4508 | XEXP (test, 0), XEXP (test, 1)); | |
b4ad7b23 RS |
4509 | } |
4510 | else | |
4511 | bl->initial_test = test; | |
4512 | } | |
4513 | } | |
6ec73c7c MH |
4514 | } |
4515 | ||
4516 | ||
4517 | /* Look at the each biv and see if we can say anything better about its | |
4518 | initial value from any initializing insns set up above. (This is done | |
4519 | in two passes to avoid missing SETs in a PARALLEL.) */ | |
4520 | static void | |
0c20a65f | 4521 | loop_bivs_check (struct loop *loop) |
6ec73c7c MH |
4522 | { |
4523 | struct loop_ivs *ivs = LOOP_IVS (loop); | |
14be28e5 | 4524 | /* Temporary list pointers for traversing ivs->list. */ |
6ec73c7c MH |
4525 | struct iv_class *bl; |
4526 | struct iv_class **backbl; | |
b4ad7b23 | 4527 | |
14be28e5 | 4528 | for (backbl = &ivs->list; (bl = *backbl); backbl = &bl->next) |
b4ad7b23 RS |
4529 | { |
4530 | rtx src; | |
956d6950 | 4531 | rtx note; |
b4ad7b23 RS |
4532 | |
4533 | if (! bl->init_insn) | |
4534 | continue; | |
4535 | ||
956d6950 JL |
4536 | /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value |
4537 | is a constant, use the value of that. */ | |
4538 | if (((note = find_reg_note (bl->init_insn, REG_EQUAL, 0)) != NULL | |
4539 | && CONSTANT_P (XEXP (note, 0))) | |
4540 | || ((note = find_reg_note (bl->init_insn, REG_EQUIV, 0)) != NULL | |
4541 | && CONSTANT_P (XEXP (note, 0)))) | |
4542 | src = XEXP (note, 0); | |
4543 | else | |
4544 | src = SET_SRC (bl->init_set); | |
b4ad7b23 RS |
4545 | |
4546 | if (loop_dump_stream) | |
4547 | fprintf (loop_dump_stream, | |
c804f3f8 | 4548 | "Biv %d: initialized at insn %d: initial value ", |
b4ad7b23 RS |
4549 | bl->regno, INSN_UID (bl->init_insn)); |
4550 | ||
43a674af JW |
4551 | if ((GET_MODE (src) == GET_MODE (regno_reg_rtx[bl->regno]) |
4552 | || GET_MODE (src) == VOIDmode) | |
6b8c9327 AJ |
4553 | && valid_initial_value_p (src, bl->init_insn, |
4554 | LOOP_INFO (loop)->pre_header_has_call, | |
e304a8e6 | 4555 | loop->start)) |
b4ad7b23 RS |
4556 | { |
4557 | bl->initial_value = src; | |
4558 | ||
4559 | if (loop_dump_stream) | |
4560 | { | |
c804f3f8 MH |
4561 | print_simple_rtl (loop_dump_stream, src); |
4562 | fputc ('\n', loop_dump_stream); | |
b4ad7b23 RS |
4563 | } |
4564 | } | |
b4f75276 | 4565 | /* If we can't make it a giv, |
6ec73c7c | 4566 | let biv keep initial value of "itself". */ |
b4f75276 BS |
4567 | else if (loop_dump_stream) |
4568 | fprintf (loop_dump_stream, "is complex\n"); | |
3ec2b590 | 4569 | } |
6ec73c7c | 4570 | } |
3ec2b590 | 4571 | |
b4ad7b23 | 4572 | |
6ec73c7c MH |
4573 | /* Search the loop for general induction variables. */ |
4574 | ||
4575 | static void | |
0c20a65f | 4576 | loop_givs_find (struct loop* loop) |
6ec73c7c | 4577 | { |
5e787f07 | 4578 | for_each_insn_in_loop (loop, check_insn_for_givs); |
6ec73c7c | 4579 | } |
b4ad7b23 | 4580 | |
b4ad7b23 | 4581 | |
6ec73c7c MH |
4582 | /* For each giv for which we still don't know whether or not it is |
4583 | replaceable, check to see if it is replaceable because its final value | |
6d2f8887 | 4584 | can be calculated. */ |
b4ad7b23 | 4585 | |
6ec73c7c | 4586 | static void |
0c20a65f | 4587 | loop_givs_check (struct loop *loop) |
6ec73c7c MH |
4588 | { |
4589 | struct loop_ivs *ivs = LOOP_IVS (loop); | |
4590 | struct iv_class *bl; | |
b4ad7b23 | 4591 | |
14be28e5 | 4592 | for (bl = ivs->list; bl; bl = bl->next) |
b4ad7b23 RS |
4593 | { |
4594 | struct induction *v; | |
4595 | ||
4596 | for (v = bl->giv; v; v = v->next_iv) | |
4597 | if (! v->replaceable && ! v->not_replaceable) | |
0534b804 | 4598 | check_final_value (loop, v); |
b4ad7b23 | 4599 | } |
6ec73c7c MH |
4600 | } |
4601 | ||
4602 | ||
cc2902df | 4603 | /* Return nonzero if it is possible to eliminate the biv BL provided |
e304a8e6 MH |
4604 | all givs are reduced. This is possible if either the reg is not |
4605 | used outside the loop, or we can compute what its final value will | |
4606 | be. */ | |
4607 | ||
4608 | static int | |
0c20a65f AJ |
4609 | loop_biv_eliminable_p (struct loop *loop, struct iv_class *bl, |
4610 | int threshold, int insn_count) | |
6ec73c7c | 4611 | { |
e304a8e6 MH |
4612 | /* For architectures with a decrement_and_branch_until_zero insn, |
4613 | don't do this if we put a REG_NONNEG note on the endtest for this | |
4614 | biv. */ | |
4615 | ||
4616 | #ifdef HAVE_decrement_and_branch_until_zero | |
4617 | if (bl->nonneg) | |
4618 | { | |
4619 | if (loop_dump_stream) | |
4620 | fprintf (loop_dump_stream, | |
4621 | "Cannot eliminate nonneg biv %d.\n", bl->regno); | |
4622 | return 0; | |
4623 | } | |
4624 | #endif | |
4625 | ||
4626 | /* Check that biv is used outside loop or if it has a final value. | |
4627 | Compare against bl->init_insn rather than loop->start. We aren't | |
4628 | concerned with any uses of the biv between init_insn and | |
4629 | loop->start since these won't be affected by the value of the biv | |
4630 | elsewhere in the function, so long as init_insn doesn't use the | |
4631 | biv itself. */ | |
6b8c9327 | 4632 | |
6ec73c7c MH |
4633 | if ((REGNO_LAST_LUID (bl->regno) < INSN_LUID (loop->end) |
4634 | && bl->init_insn | |
4635 | && INSN_UID (bl->init_insn) < max_uid_for_loop | |
4636 | && REGNO_FIRST_LUID (bl->regno) >= INSN_LUID (bl->init_insn) | |
6ec73c7c | 4637 | && ! reg_mentioned_p (bl->biv->dest_reg, SET_SRC (bl->init_set))) |
e304a8e6 | 4638 | || (bl->final_value = final_biv_value (loop, bl))) |
6ec73c7c | 4639 | return maybe_eliminate_biv (loop, bl, 0, threshold, insn_count); |
6b8c9327 | 4640 | |
e304a8e6 MH |
4641 | if (loop_dump_stream) |
4642 | { | |
4643 | fprintf (loop_dump_stream, | |
4644 | "Cannot eliminate biv %d.\n", | |
4645 | bl->regno); | |
4646 | fprintf (loop_dump_stream, | |
4647 | "First use: insn %d, last use: insn %d.\n", | |
4648 | REGNO_FIRST_UID (bl->regno), | |
4649 | REGNO_LAST_UID (bl->regno)); | |
4650 | } | |
4651 | return 0; | |
4652 | } | |
4653 | ||
4654 | ||
4655 | /* Reduce each giv of BL that we have decided to reduce. */ | |
4656 | ||
4657 | static void | |
0c20a65f | 4658 | loop_givs_reduce (struct loop *loop, struct iv_class *bl) |
e304a8e6 MH |
4659 | { |
4660 | struct induction *v; | |
4661 | ||
4662 | for (v = bl->giv; v; v = v->next_iv) | |
4663 | { | |
4664 | struct induction *tv; | |
4665 | if (! v->ignore && v->same == 0) | |
4666 | { | |
4667 | int auto_inc_opt = 0; | |
6b8c9327 | 4668 | |
e304a8e6 MH |
4669 | /* If the code for derived givs immediately below has already |
4670 | allocated a new_reg, we must keep it. */ | |
4671 | if (! v->new_reg) | |
4672 | v->new_reg = gen_reg_rtx (v->mode); | |
6b8c9327 | 4673 | |
e304a8e6 MH |
4674 | #ifdef AUTO_INC_DEC |
4675 | /* If the target has auto-increment addressing modes, and | |
4676 | this is an address giv, then try to put the increment | |
4677 | immediately after its use, so that flow can create an | |
4678 | auto-increment addressing mode. */ | |
4679 | if (v->giv_type == DEST_ADDR && bl->biv_count == 1 | |
4680 | && bl->biv->always_executed && ! bl->biv->maybe_multiple | |
4681 | /* We don't handle reversed biv's because bl->biv->insn | |
4682 | does not have a valid INSN_LUID. */ | |
4683 | && ! bl->reversed | |
4684 | && v->always_executed && ! v->maybe_multiple | |
4685 | && INSN_UID (v->insn) < max_uid_for_loop) | |
4686 | { | |
4687 | /* If other giv's have been combined with this one, then | |
4688 | this will work only if all uses of the other giv's occur | |
4689 | before this giv's insn. This is difficult to check. | |
6b8c9327 | 4690 | |
e304a8e6 MH |
4691 | We simplify this by looking for the common case where |
4692 | there is one DEST_REG giv, and this giv's insn is the | |
4693 | last use of the dest_reg of that DEST_REG giv. If the | |
4694 | increment occurs after the address giv, then we can | |
4695 | perform the optimization. (Otherwise, the increment | |
4696 | would have to go before other_giv, and we would not be | |
4697 | able to combine it with the address giv to get an | |
4698 | auto-inc address.) */ | |
4699 | if (v->combined_with) | |
4700 | { | |
4701 | struct induction *other_giv = 0; | |
6b8c9327 | 4702 | |
e304a8e6 MH |
4703 | for (tv = bl->giv; tv; tv = tv->next_iv) |
4704 | if (tv->same == v) | |
4705 | { | |
4706 | if (other_giv) | |
4707 | break; | |
4708 | else | |
4709 | other_giv = tv; | |
4710 | } | |
4711 | if (! tv && other_giv | |
4712 | && REGNO (other_giv->dest_reg) < max_reg_before_loop | |
4713 | && (REGNO_LAST_UID (REGNO (other_giv->dest_reg)) | |
4714 | == INSN_UID (v->insn)) | |
4715 | && INSN_LUID (v->insn) < INSN_LUID (bl->biv->insn)) | |
4716 | auto_inc_opt = 1; | |
4717 | } | |
4718 | /* Check for case where increment is before the address | |
4719 | giv. Do this test in "loop order". */ | |
4720 | else if ((INSN_LUID (v->insn) > INSN_LUID (bl->biv->insn) | |
4721 | && (INSN_LUID (v->insn) < INSN_LUID (loop->scan_start) | |
4722 | || (INSN_LUID (bl->biv->insn) | |
4723 | > INSN_LUID (loop->scan_start)))) | |
4724 | || (INSN_LUID (v->insn) < INSN_LUID (loop->scan_start) | |
4725 | && (INSN_LUID (loop->scan_start) | |
4726 | < INSN_LUID (bl->biv->insn)))) | |
4727 | auto_inc_opt = -1; | |
4728 | else | |
4729 | auto_inc_opt = 1; | |
6b8c9327 | 4730 | |
e304a8e6 MH |
4731 | #ifdef HAVE_cc0 |
4732 | { | |
4733 | rtx prev; | |
6b8c9327 | 4734 | |
e304a8e6 MH |
4735 | /* We can't put an insn immediately after one setting |
4736 | cc0, or immediately before one using cc0. */ | |
4737 | if ((auto_inc_opt == 1 && sets_cc0_p (PATTERN (v->insn))) | |
4738 | || (auto_inc_opt == -1 | |
4739 | && (prev = prev_nonnote_insn (v->insn)) != 0 | |
4740 | && INSN_P (prev) | |
4741 | && sets_cc0_p (PATTERN (prev)))) | |
4742 | auto_inc_opt = 0; | |
4743 | } | |
4744 | #endif | |
6b8c9327 | 4745 | |
e304a8e6 MH |
4746 | if (auto_inc_opt) |
4747 | v->auto_inc_opt = 1; | |
4748 | } | |
4749 | #endif | |
6b8c9327 | 4750 | |
e304a8e6 MH |
4751 | /* For each place where the biv is incremented, add an insn |
4752 | to increment the new, reduced reg for the giv. */ | |
4753 | for (tv = bl->biv; tv; tv = tv->next_iv) | |
4754 | { | |
4755 | rtx insert_before; | |
6b8c9327 | 4756 | |
c7d325c8 GN |
4757 | /* Skip if location is the same as a previous one. */ |
4758 | if (tv->same) | |
4759 | continue; | |
e304a8e6 | 4760 | if (! auto_inc_opt) |
2567406a | 4761 | insert_before = NEXT_INSN (tv->insn); |
e304a8e6 MH |
4762 | else if (auto_inc_opt == 1) |
4763 | insert_before = NEXT_INSN (v->insn); | |
4764 | else | |
4765 | insert_before = v->insn; | |
6b8c9327 | 4766 | |
e304a8e6 | 4767 | if (tv->mult_val == const1_rtx) |
96a45535 | 4768 | loop_iv_add_mult_emit_before (loop, tv->add_val, v->mult_val, |
6b8c9327 | 4769 | v->new_reg, v->new_reg, |
96a45535 | 4770 | 0, insert_before); |
e304a8e6 MH |
4771 | else /* tv->mult_val == const0_rtx */ |
4772 | /* A multiply is acceptable here | |
4773 | since this is presumed to be seldom executed. */ | |
96a45535 | 4774 | loop_iv_add_mult_emit_before (loop, tv->add_val, v->mult_val, |
6b8c9327 | 4775 | v->add_val, v->new_reg, |
96a45535 | 4776 | 0, insert_before); |
e304a8e6 | 4777 | } |
6b8c9327 | 4778 | |
e304a8e6 | 4779 | /* Add code at loop start to initialize giv's reduced reg. */ |
6b8c9327 | 4780 | |
96a45535 MH |
4781 | loop_iv_add_mult_hoist (loop, |
4782 | extend_value_for_giv (v, bl->initial_value), | |
4783 | v->mult_val, v->add_val, v->new_reg); | |
e304a8e6 MH |
4784 | } |
4785 | } | |
4786 | } | |
4787 | ||
4788 | ||
4789 | /* Check for givs whose first use is their definition and whose | |
4790 | last use is the definition of another giv. If so, it is likely | |
4791 | dead and should not be used to derive another giv nor to | |
4792 | eliminate a biv. */ | |
4793 | ||
4794 | static void | |
0c20a65f | 4795 | loop_givs_dead_check (struct loop *loop ATTRIBUTE_UNUSED, struct iv_class *bl) |
e304a8e6 MH |
4796 | { |
4797 | struct induction *v; | |
4798 | ||
4799 | for (v = bl->giv; v; v = v->next_iv) | |
4800 | { | |
4801 | if (v->ignore | |
4802 | || (v->same && v->same->ignore)) | |
4803 | continue; | |
6b8c9327 | 4804 | |
e304a8e6 MH |
4805 | if (v->giv_type == DEST_REG |
4806 | && REGNO_FIRST_UID (REGNO (v->dest_reg)) == INSN_UID (v->insn)) | |
4807 | { | |
4808 | struct induction *v1; | |
6b8c9327 | 4809 | |
e304a8e6 MH |
4810 | for (v1 = bl->giv; v1; v1 = v1->next_iv) |
4811 | if (REGNO_LAST_UID (REGNO (v->dest_reg)) == INSN_UID (v1->insn)) | |
4812 | v->maybe_dead = 1; | |
4813 | } | |
4814 | } | |
4815 | } | |
4816 | ||
4817 | ||
4818 | static void | |
0c20a65f | 4819 | loop_givs_rescan (struct loop *loop, struct iv_class *bl, rtx *reg_map) |
e304a8e6 MH |
4820 | { |
4821 | struct induction *v; | |
4822 | ||
4823 | for (v = bl->giv; v; v = v->next_iv) | |
4824 | { | |
4825 | if (v->same && v->same->ignore) | |
4826 | v->ignore = 1; | |
6b8c9327 | 4827 | |
e304a8e6 MH |
4828 | if (v->ignore) |
4829 | continue; | |
6b8c9327 | 4830 | |
e304a8e6 MH |
4831 | /* Update expression if this was combined, in case other giv was |
4832 | replaced. */ | |
4833 | if (v->same) | |
4834 | v->new_reg = replace_rtx (v->new_reg, | |
4835 | v->same->dest_reg, v->same->new_reg); | |
6b8c9327 | 4836 | |
e304a8e6 MH |
4837 | /* See if this register is known to be a pointer to something. If |
4838 | so, see if we can find the alignment. First see if there is a | |
4839 | destination register that is a pointer. If so, this shares the | |
4840 | alignment too. Next see if we can deduce anything from the | |
4841 | computational information. If not, and this is a DEST_ADDR | |
4842 | giv, at least we know that it's a pointer, though we don't know | |
4843 | the alignment. */ | |
4844 | if (GET_CODE (v->new_reg) == REG | |
4845 | && v->giv_type == DEST_REG | |
4846 | && REG_POINTER (v->dest_reg)) | |
4847 | mark_reg_pointer (v->new_reg, | |
4848 | REGNO_POINTER_ALIGN (REGNO (v->dest_reg))); | |
4849 | else if (GET_CODE (v->new_reg) == REG | |
4850 | && REG_POINTER (v->src_reg)) | |
4851 | { | |
4852 | unsigned int align = REGNO_POINTER_ALIGN (REGNO (v->src_reg)); | |
6b8c9327 | 4853 | |
e304a8e6 MH |
4854 | if (align == 0 |
4855 | || GET_CODE (v->add_val) != CONST_INT | |
4856 | || INTVAL (v->add_val) % (align / BITS_PER_UNIT) != 0) | |
4857 | align = 0; | |
6b8c9327 | 4858 | |
e304a8e6 MH |
4859 | mark_reg_pointer (v->new_reg, align); |
4860 | } | |
4861 | else if (GET_CODE (v->new_reg) == REG | |
4862 | && GET_CODE (v->add_val) == REG | |
4863 | && REG_POINTER (v->add_val)) | |
4864 | { | |
4865 | unsigned int align = REGNO_POINTER_ALIGN (REGNO (v->add_val)); | |
6b8c9327 | 4866 | |
e304a8e6 MH |
4867 | if (align == 0 || GET_CODE (v->mult_val) != CONST_INT |
4868 | || INTVAL (v->mult_val) % (align / BITS_PER_UNIT) != 0) | |
4869 | align = 0; | |
6b8c9327 | 4870 | |
e304a8e6 MH |
4871 | mark_reg_pointer (v->new_reg, align); |
4872 | } | |
4873 | else if (GET_CODE (v->new_reg) == REG && v->giv_type == DEST_ADDR) | |
4874 | mark_reg_pointer (v->new_reg, 0); | |
6b8c9327 | 4875 | |
e304a8e6 MH |
4876 | if (v->giv_type == DEST_ADDR) |
4877 | /* Store reduced reg as the address in the memref where we found | |
4878 | this giv. */ | |
4879 | validate_change (v->insn, v->location, v->new_reg, 0); | |
4880 | else if (v->replaceable) | |
4881 | { | |
4882 | reg_map[REGNO (v->dest_reg)] = v->new_reg; | |
4883 | } | |
4884 | else | |
4885 | { | |
f1a73cfe | 4886 | rtx original_insn = v->insn; |
544823b6 | 4887 | rtx note; |
f1a73cfe | 4888 | |
e304a8e6 MH |
4889 | /* Not replaceable; emit an insn to set the original giv reg from |
4890 | the reduced giv, same as above. */ | |
f1a73cfe EB |
4891 | v->insn = loop_insn_emit_after (loop, 0, original_insn, |
4892 | gen_move_insn (v->dest_reg, | |
4893 | v->new_reg)); | |
4894 | ||
0c20a65f AJ |
4895 | /* The original insn may have a REG_EQUAL note. This note is |
4896 | now incorrect and may result in invalid substitutions later. | |
4897 | The original insn is dead, but may be part of a libcall | |
4898 | sequence, which doesn't seem worth the bother of handling. */ | |
4899 | note = find_reg_note (original_insn, REG_EQUAL, NULL_RTX); | |
4900 | if (note) | |
4901 | remove_note (original_insn, note); | |
e304a8e6 | 4902 | } |
6b8c9327 | 4903 | |
e304a8e6 MH |
4904 | /* When a loop is reversed, givs which depend on the reversed |
4905 | biv, and which are live outside the loop, must be set to their | |
4906 | correct final value. This insn is only needed if the giv is | |
4907 | not replaceable. The correct final value is the same as the | |
4908 | value that the giv starts the reversed loop with. */ | |
4909 | if (bl->reversed && ! v->replaceable) | |
6b8c9327 | 4910 | loop_iv_add_mult_sink (loop, |
96a45535 MH |
4911 | extend_value_for_giv (v, bl->initial_value), |
4912 | v->mult_val, v->add_val, v->dest_reg); | |
e304a8e6 | 4913 | else if (v->final_value) |
6b8c9327 | 4914 | loop_insn_sink_or_swim (loop, |
74411039 JH |
4915 | gen_load_of_final_value (v->dest_reg, |
4916 | v->final_value)); | |
6b8c9327 | 4917 | |
e304a8e6 MH |
4918 | if (loop_dump_stream) |
4919 | { | |
4920 | fprintf (loop_dump_stream, "giv at %d reduced to ", | |
4921 | INSN_UID (v->insn)); | |
c804f3f8 | 4922 | print_simple_rtl (loop_dump_stream, v->new_reg); |
e304a8e6 MH |
4923 | fprintf (loop_dump_stream, "\n"); |
4924 | } | |
4925 | } | |
4926 | } | |
4927 | ||
4928 | ||
4929 | static int | |
0c20a65f AJ |
4930 | loop_giv_reduce_benefit (struct loop *loop ATTRIBUTE_UNUSED, |
4931 | struct iv_class *bl, struct induction *v, | |
4932 | rtx test_reg) | |
e304a8e6 MH |
4933 | { |
4934 | int add_cost; | |
4935 | int benefit; | |
4936 | ||
4937 | benefit = v->benefit; | |
4938 | PUT_MODE (test_reg, v->mode); | |
4939 | add_cost = iv_add_mult_cost (bl->biv->add_val, v->mult_val, | |
4940 | test_reg, test_reg); | |
6b8c9327 | 4941 | |
e304a8e6 MH |
4942 | /* Reduce benefit if not replaceable, since we will insert a |
4943 | move-insn to replace the insn that calculates this giv. Don't do | |
4944 | this unless the giv is a user variable, since it will often be | |
4945 | marked non-replaceable because of the duplication of the exit | |
4946 | code outside the loop. In such a case, the copies we insert are | |
4947 | dead and will be deleted. So they don't have a cost. Similar | |
4948 | situations exist. */ | |
4949 | /* ??? The new final_[bg]iv_value code does a much better job of | |
4950 | finding replaceable giv's, and hence this code may no longer be | |
4951 | necessary. */ | |
4952 | if (! v->replaceable && ! bl->eliminable | |
4953 | && REG_USERVAR_P (v->dest_reg)) | |
4954 | benefit -= copy_cost; | |
6b8c9327 | 4955 | |
e304a8e6 MH |
4956 | /* Decrease the benefit to count the add-insns that we will insert |
4957 | to increment the reduced reg for the giv. ??? This can | |
4958 | overestimate the run-time cost of the additional insns, e.g. if | |
4959 | there are multiple basic blocks that increment the biv, but only | |
4960 | one of these blocks is executed during each iteration. There is | |
4961 | no good way to detect cases like this with the current structure | |
4962 | of the loop optimizer. This code is more accurate for | |
4963 | determining code size than run-time benefits. */ | |
4964 | benefit -= add_cost * bl->biv_count; | |
4965 | ||
4966 | /* Decide whether to strength-reduce this giv or to leave the code | |
4967 | unchanged (recompute it from the biv each time it is used). This | |
4968 | decision can be made independently for each giv. */ | |
4969 | ||
4970 | #ifdef AUTO_INC_DEC | |
4971 | /* Attempt to guess whether autoincrement will handle some of the | |
4972 | new add insns; if so, increase BENEFIT (undo the subtraction of | |
4973 | add_cost that was done above). */ | |
4974 | if (v->giv_type == DEST_ADDR | |
4975 | /* Increasing the benefit is risky, since this is only a guess. | |
4976 | Avoid increasing register pressure in cases where there would | |
4977 | be no other benefit from reducing this giv. */ | |
4978 | && benefit > 0 | |
4979 | && GET_CODE (v->mult_val) == CONST_INT) | |
4980 | { | |
616fde53 MH |
4981 | int size = GET_MODE_SIZE (GET_MODE (v->mem)); |
4982 | ||
e304a8e6 | 4983 | if (HAVE_POST_INCREMENT |
616fde53 | 4984 | && INTVAL (v->mult_val) == size) |
e304a8e6 MH |
4985 | benefit += add_cost * bl->biv_count; |
4986 | else if (HAVE_PRE_INCREMENT | |
616fde53 | 4987 | && INTVAL (v->mult_val) == size) |
e304a8e6 MH |
4988 | benefit += add_cost * bl->biv_count; |
4989 | else if (HAVE_POST_DECREMENT | |
616fde53 | 4990 | && -INTVAL (v->mult_val) == size) |
e304a8e6 MH |
4991 | benefit += add_cost * bl->biv_count; |
4992 | else if (HAVE_PRE_DECREMENT | |
616fde53 | 4993 | && -INTVAL (v->mult_val) == size) |
e304a8e6 MH |
4994 | benefit += add_cost * bl->biv_count; |
4995 | } | |
4996 | #endif | |
4997 | ||
4998 | return benefit; | |
6ec73c7c MH |
4999 | } |
5000 | ||
5001 | ||
b2735d9a MH |
5002 | /* Free IV structures for LOOP. */ |
5003 | ||
5004 | static void | |
0c20a65f | 5005 | loop_ivs_free (struct loop *loop) |
b2735d9a MH |
5006 | { |
5007 | struct loop_ivs *ivs = LOOP_IVS (loop); | |
5008 | struct iv_class *iv = ivs->list; | |
6b8c9327 | 5009 | |
b2735d9a MH |
5010 | free (ivs->regs); |
5011 | ||
5012 | while (iv) | |
5013 | { | |
5014 | struct iv_class *next = iv->next; | |
5015 | struct induction *induction; | |
5016 | struct induction *next_induction; | |
6b8c9327 | 5017 | |
b2735d9a MH |
5018 | for (induction = iv->biv; induction; induction = next_induction) |
5019 | { | |
5020 | next_induction = induction->next_iv; | |
5021 | free (induction); | |
5022 | } | |
5023 | for (induction = iv->giv; induction; induction = next_induction) | |
5024 | { | |
5025 | next_induction = induction->next_iv; | |
5026 | free (induction); | |
5027 | } | |
6b8c9327 | 5028 | |
b2735d9a MH |
5029 | free (iv); |
5030 | iv = next; | |
5031 | } | |
5032 | } | |
5033 | ||
5034 | ||
6ec73c7c MH |
5035 | /* Perform strength reduction and induction variable elimination. |
5036 | ||
5037 | Pseudo registers created during this function will be beyond the | |
f1d4ac80 MH |
5038 | last valid index in several tables including |
5039 | REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a | |
5040 | problem here, because the added registers cannot be givs outside of | |
5041 | their loop, and hence will never be reconsidered. But scan_loop | |
5042 | must check regnos to make sure they are in bounds. */ | |
6ec73c7c MH |
5043 | |
5044 | static void | |
0c20a65f | 5045 | strength_reduce (struct loop *loop, int flags) |
6ec73c7c MH |
5046 | { |
5047 | struct loop_info *loop_info = LOOP_INFO (loop); | |
5048 | struct loop_regs *regs = LOOP_REGS (loop); | |
5049 | struct loop_ivs *ivs = LOOP_IVS (loop); | |
5050 | rtx p; | |
14be28e5 | 5051 | /* Temporary list pointer for traversing ivs->list. */ |
e304a8e6 | 5052 | struct iv_class *bl; |
6ec73c7c MH |
5053 | /* Ratio of extra register life span we can justify |
5054 | for saving an instruction. More if loop doesn't call subroutines | |
5055 | since in that case saving an insn makes more difference | |
5056 | and more registers are available. */ | |
5057 | /* ??? could set this to last value of threshold in move_movables */ | |
5058 | int threshold = (loop_info->has_call ? 1 : 2) * (3 + n_non_fixed_regs); | |
5059 | /* Map of pseudo-register replacements. */ | |
5060 | rtx *reg_map = NULL; | |
5061 | int reg_map_size; | |
6ec73c7c | 5062 | int unrolled_insn_copies = 0; |
6ec73c7c | 5063 | rtx test_reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
28680540 | 5064 | int insn_count = count_insns_in_loop (loop); |
6ec73c7c MH |
5065 | |
5066 | addr_placeholder = gen_reg_rtx (Pmode); | |
5067 | ||
14be28e5 | 5068 | ivs->n_regs = max_reg_before_loop; |
703ad42b | 5069 | ivs->regs = xcalloc (ivs->n_regs, sizeof (struct iv)); |
6ec73c7c MH |
5070 | |
5071 | /* Find all BIVs in loop. */ | |
5072 | loop_bivs_find (loop); | |
5073 | ||
5074 | /* Exit if there are no bivs. */ | |
14be28e5 | 5075 | if (! ivs->list) |
6ec73c7c MH |
5076 | { |
5077 | /* Can still unroll the loop anyways, but indicate that there is no | |
5078 | strength reduction info available. */ | |
5079 | if (flags & LOOP_UNROLL) | |
96a45535 | 5080 | unroll_loop (loop, insn_count, 0); |
6ec73c7c | 5081 | |
b2735d9a MH |
5082 | loop_ivs_free (loop); |
5083 | return; | |
6ec73c7c MH |
5084 | } |
5085 | ||
4912a07c | 5086 | /* Determine how BIVS are initialized by looking through pre-header |
6ec73c7c MH |
5087 | extended basic block. */ |
5088 | loop_bivs_init_find (loop); | |
5089 | ||
5090 | /* Look at the each biv and see if we can say anything better about its | |
5091 | initial value from any initializing insns set up above. */ | |
5092 | loop_bivs_check (loop); | |
5093 | ||
5094 | /* Search the loop for general induction variables. */ | |
5095 | loop_givs_find (loop); | |
5096 | ||
5097 | /* Try to calculate and save the number of loop iterations. This is | |
5098 | set to zero if the actual number can not be calculated. This must | |
5099 | be called after all giv's have been identified, since otherwise it may | |
5100 | fail if the iteration variable is a giv. */ | |
5101 | loop_iterations (loop); | |
5102 | ||
0dd0e980 JH |
5103 | #ifdef HAVE_prefetch |
5104 | if (flags & LOOP_PREFETCH) | |
5105 | emit_prefetch_instructions (loop); | |
5106 | #endif | |
5107 | ||
6ec73c7c MH |
5108 | /* Now for each giv for which we still don't know whether or not it is |
5109 | replaceable, check to see if it is replaceable because its final value | |
5110 | can be calculated. This must be done after loop_iterations is called, | |
5111 | so that final_giv_value will work correctly. */ | |
5112 | loop_givs_check (loop); | |
b4ad7b23 RS |
5113 | |
5114 | /* Try to prove that the loop counter variable (if any) is always | |
5115 | nonnegative; if so, record that fact with a REG_NONNEG note | |
5116 | so that "decrement and branch until zero" insn can be used. */ | |
a2be868f | 5117 | check_dbra_loop (loop, insn_count); |
b4ad7b23 | 5118 | |
97ec0ad8 R |
5119 | /* Create reg_map to hold substitutions for replaceable giv regs. |
5120 | Some givs might have been made from biv increments, so look at | |
ed5bb68d | 5121 | ivs->reg_iv_type for a suitable size. */ |
14be28e5 | 5122 | reg_map_size = ivs->n_regs; |
703ad42b | 5123 | reg_map = xcalloc (reg_map_size, sizeof (rtx)); |
b4ad7b23 RS |
5124 | |
5125 | /* Examine each iv class for feasibility of strength reduction/induction | |
5126 | variable elimination. */ | |
5127 | ||
14be28e5 | 5128 | for (bl = ivs->list; bl; bl = bl->next) |
b4ad7b23 RS |
5129 | { |
5130 | struct induction *v; | |
5131 | int benefit; | |
6b8c9327 | 5132 | |
b4ad7b23 | 5133 | /* Test whether it will be possible to eliminate this biv |
6ec73c7c | 5134 | provided all givs are reduced. */ |
e304a8e6 | 5135 | bl->eliminable = loop_biv_eliminable_p (loop, bl, threshold, insn_count); |
b4ad7b23 | 5136 | |
97ebd24c JW |
5137 | /* This will be true at the end, if all givs which depend on this |
5138 | biv have been strength reduced. | |
5139 | We can't (currently) eliminate the biv unless this is so. */ | |
5140 | bl->all_reduced = 1; | |
5141 | ||
6ec73c7c | 5142 | /* Check each extension dependent giv in this class to see if its |
e8cb4873 | 5143 | root biv is safe from wrapping in the interior mode. */ |
03988cac | 5144 | check_ext_dependent_givs (loop, bl); |
e8cb4873 | 5145 | |
b4ad7b23 | 5146 | /* Combine all giv's for this iv_class. */ |
1ecd860b | 5147 | combine_givs (regs, bl); |
b4ad7b23 | 5148 | |
b4ad7b23 RS |
5149 | for (v = bl->giv; v; v = v->next_iv) |
5150 | { | |
5151 | struct induction *tv; | |
5152 | ||
5153 | if (v->ignore || v->same) | |
5154 | continue; | |
5155 | ||
e304a8e6 | 5156 | benefit = loop_giv_reduce_benefit (loop, bl, v, test_reg); |
b4ad7b23 RS |
5157 | |
5158 | /* If an insn is not to be strength reduced, then set its ignore | |
e304a8e6 | 5159 | flag, and clear bl->all_reduced. */ |
b4ad7b23 | 5160 | |
e6f6eb29 JW |
5161 | /* A giv that depends on a reversed biv must be reduced if it is |
5162 | used after the loop exit, otherwise, it would have the wrong | |
5163 | value after the loop exit. To make it simple, just reduce all | |
5164 | of such giv's whether or not we know they are used after the loop | |
5165 | exit. */ | |
5166 | ||
6ec73c7c MH |
5167 | if (! flag_reduce_all_givs |
5168 | && v->lifetime * threshold * benefit < insn_count | |
5169 | && ! bl->reversed) | |
b4ad7b23 RS |
5170 | { |
5171 | if (loop_dump_stream) | |
5172 | fprintf (loop_dump_stream, | |
5173 | "giv of insn %d not worth while, %d vs %d.\n", | |
5174 | INSN_UID (v->insn), | |
5175 | v->lifetime * threshold * benefit, insn_count); | |
5176 | v->ignore = 1; | |
e304a8e6 | 5177 | bl->all_reduced = 0; |
b4ad7b23 RS |
5178 | } |
5179 | else | |
5180 | { | |
5181 | /* Check that we can increment the reduced giv without a | |
5182 | multiply insn. If not, reject it. */ | |
5183 | ||
5184 | for (tv = bl->biv; tv; tv = tv->next_iv) | |
5185 | if (tv->mult_val == const1_rtx | |
5186 | && ! product_cheap_p (tv->add_val, v->mult_val)) | |
5187 | { | |
5188 | if (loop_dump_stream) | |
5189 | fprintf (loop_dump_stream, | |
5190 | "giv of insn %d: would need a multiply.\n", | |
5191 | INSN_UID (v->insn)); | |
5192 | v->ignore = 1; | |
e304a8e6 | 5193 | bl->all_reduced = 0; |
b4ad7b23 RS |
5194 | break; |
5195 | } | |
5196 | } | |
5197 | } | |
5198 | ||
8c354a41 R |
5199 | /* Check for givs whose first use is their definition and whose |
5200 | last use is the definition of another giv. If so, it is likely | |
5201 | dead and should not be used to derive another giv nor to | |
5202 | eliminate a biv. */ | |
e304a8e6 | 5203 | loop_givs_dead_check (loop, bl); |
8c354a41 | 5204 | |
b4ad7b23 | 5205 | /* Reduce each giv that we decided to reduce. */ |
e304a8e6 | 5206 | loop_givs_reduce (loop, bl); |
b4ad7b23 RS |
5207 | |
5208 | /* Rescan all givs. If a giv is the same as a giv not reduced, mark it | |
5209 | as not reduced. | |
e6fcb60d | 5210 | |
b4ad7b23 RS |
5211 | For each giv register that can be reduced now: if replaceable, |
5212 | substitute reduced reg wherever the old giv occurs; | |
8c354a41 | 5213 | else add new move insn "giv_reg = reduced_reg". */ |
96a45535 | 5214 | loop_givs_rescan (loop, bl, reg_map); |
b4ad7b23 RS |
5215 | |
5216 | /* All the givs based on the biv bl have been reduced if they | |
5217 | merit it. */ | |
5218 | ||
5219 | /* For each giv not marked as maybe dead that has been combined with a | |
5220 | second giv, clear any "maybe dead" mark on that second giv. | |
5221 | v->new_reg will either be or refer to the register of the giv it | |
5222 | combined with. | |
5223 | ||
e304a8e6 MH |
5224 | Doing this clearing avoids problems in biv elimination where |
5225 | a giv's new_reg is a complex value that can't be put in the | |
5226 | insn but the giv combined with (with a reg as new_reg) is | |
5227 | marked maybe_dead. Since the register will be used in either | |
5228 | case, we'd prefer it be used from the simpler giv. */ | |
b4ad7b23 RS |
5229 | |
5230 | for (v = bl->giv; v; v = v->next_iv) | |
5231 | if (! v->maybe_dead && v->same) | |
5232 | v->same->maybe_dead = 0; | |
5233 | ||
5234 | /* Try to eliminate the biv, if it is a candidate. | |
e304a8e6 | 5235 | This won't work if ! bl->all_reduced, |
b4ad7b23 RS |
5236 | since the givs we planned to use might not have been reduced. |
5237 | ||
e304a8e6 MH |
5238 | We have to be careful that we didn't initially think we could |
5239 | eliminate this biv because of a giv that we now think may be | |
5240 | dead and shouldn't be used as a biv replacement. | |
b4ad7b23 RS |
5241 | |
5242 | Also, there is the possibility that we may have a giv that looks | |
5243 | like it can be used to eliminate a biv, but the resulting insn | |
e6fcb60d | 5244 | isn't valid. This can happen, for example, on the 88k, where a |
b4ad7b23 | 5245 | JUMP_INSN can compare a register only with zero. Attempts to |
c5b7917e | 5246 | replace it with a compare with a constant will fail. |
b4ad7b23 RS |
5247 | |
5248 | Note that in cases where this call fails, we may have replaced some | |
5249 | of the occurrences of the biv with a giv, but no harm was done in | |
5250 | doing so in the rare cases where it can occur. */ | |
5251 | ||
e304a8e6 | 5252 | if (bl->all_reduced == 1 && bl->eliminable |
0534b804 | 5253 | && maybe_eliminate_biv (loop, bl, 1, threshold, insn_count)) |
b4ad7b23 RS |
5254 | { |
5255 | /* ?? If we created a new test to bypass the loop entirely, | |
5256 | or otherwise drop straight in, based on this test, then | |
5257 | we might want to rewrite it also. This way some later | |
5258 | pass has more hope of removing the initialization of this | |
0f41302f | 5259 | biv entirely. */ |
b4ad7b23 RS |
5260 | |
5261 | /* If final_value != 0, then the biv may be used after loop end | |
5262 | and we must emit an insn to set it just in case. | |
5263 | ||
5264 | Reversed bivs already have an insn after the loop setting their | |
5265 | value, so we don't need another one. We can't calculate the | |
0f41302f | 5266 | proper final value for such a biv here anyways. */ |
e304a8e6 | 5267 | if (bl->final_value && ! bl->reversed) |
74411039 JH |
5268 | loop_insn_sink_or_swim (loop, |
5269 | gen_load_of_final_value (bl->biv->dest_reg, | |
5270 | bl->final_value)); | |
b4ad7b23 | 5271 | |
b4ad7b23 RS |
5272 | if (loop_dump_stream) |
5273 | fprintf (loop_dump_stream, "Reg %d: biv eliminated\n", | |
5274 | bl->regno); | |
5275 | } | |
5c7f5a5f RH |
5276 | /* See above note wrt final_value. But since we couldn't eliminate |
5277 | the biv, we must set the value after the loop instead of before. */ | |
5278 | else if (bl->final_value && ! bl->reversed) | |
74411039 JH |
5279 | loop_insn_sink (loop, gen_load_of_final_value (bl->biv->dest_reg, |
5280 | bl->final_value)); | |
b4ad7b23 RS |
5281 | } |
5282 | ||
5283 | /* Go through all the instructions in the loop, making all the | |
5284 | register substitutions scheduled in REG_MAP. */ | |
5285 | ||
e304a8e6 | 5286 | for (p = loop->start; p != loop->end; p = NEXT_INSN (p)) |
b4ad7b23 | 5287 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN |
e6fcb60d | 5288 | || GET_CODE (p) == CALL_INSN) |
b4ad7b23 | 5289 | { |
97ec0ad8 R |
5290 | replace_regs (PATTERN (p), reg_map, reg_map_size, 0); |
5291 | replace_regs (REG_NOTES (p), reg_map, reg_map_size, 0); | |
da0c128e | 5292 | INSN_CODE (p) = -1; |
b4ad7b23 RS |
5293 | } |
5294 | ||
73049ebc MT |
5295 | if (loop_info->n_iterations > 0) |
5296 | { | |
5297 | /* When we completely unroll a loop we will likely not need the increment | |
5298 | of the loop BIV and we will not need the conditional branch at the | |
5299 | end of the loop. */ | |
5300 | unrolled_insn_copies = insn_count - 2; | |
5301 | ||
5302 | #ifdef HAVE_cc0 | |
5303 | /* When we completely unroll a loop on a HAVE_cc0 machine we will not | |
5304 | need the comparison before the conditional branch at the end of the | |
5305 | loop. */ | |
80b8e8de | 5306 | unrolled_insn_copies -= 1; |
73049ebc MT |
5307 | #endif |
5308 | ||
5309 | /* We'll need one copy for each loop iteration. */ | |
5310 | unrolled_insn_copies *= loop_info->n_iterations; | |
5311 | ||
5312 | /* A little slop to account for the ability to remove initialization | |
5313 | code, better CSE, and other secondary benefits of completely | |
5314 | unrolling some loops. */ | |
5315 | unrolled_insn_copies -= 1; | |
5316 | ||
5317 | /* Clamp the value. */ | |
5318 | if (unrolled_insn_copies < 0) | |
5319 | unrolled_insn_copies = 0; | |
5320 | } | |
e6fcb60d | 5321 | |
b4ad7b23 RS |
5322 | /* Unroll loops from within strength reduction so that we can use the |
5323 | induction variable information that strength_reduce has already | |
73049ebc MT |
5324 | collected. Always unroll loops that would be as small or smaller |
5325 | unrolled than when rolled. */ | |
1bf14ad7 | 5326 | if ((flags & LOOP_UNROLL) |
5e1afb11 | 5327 | || ((flags & LOOP_AUTO_UNROLL) |
6584b4aa | 5328 | && loop_info->n_iterations > 0 |
73049ebc | 5329 | && unrolled_insn_copies <= insn_count)) |
96a45535 | 5330 | unroll_loop (loop, insn_count, 1); |
b4ad7b23 | 5331 | |
5527bf14 RH |
5332 | #ifdef HAVE_doloop_end |
5333 | if (HAVE_doloop_end && (flags & LOOP_BCT) && flag_branch_on_count_reg) | |
5334 | doloop_optimize (loop); | |
5335 | #endif /* HAVE_doloop_end */ | |
8c660648 | 5336 | |
aa18f20e JH |
5337 | /* In case number of iterations is known, drop branch prediction note |
5338 | in the branch. Do that only in second loop pass, as loop unrolling | |
5339 | may change the number of iterations performed. */ | |
26b738be | 5340 | if (flags & LOOP_BCT) |
aa18f20e | 5341 | { |
26b738be RH |
5342 | unsigned HOST_WIDE_INT n |
5343 | = loop_info->n_iterations / loop_info->unroll_number; | |
5344 | if (n > 1) | |
7df98878 | 5345 | predict_insn (prev_nonnote_insn (loop->end), PRED_LOOP_ITERATIONS, |
26b738be | 5346 | REG_BR_PROB_BASE - REG_BR_PROB_BASE / n); |
aa18f20e JH |
5347 | } |
5348 | ||
b4ad7b23 RS |
5349 | if (loop_dump_stream) |
5350 | fprintf (loop_dump_stream, "\n"); | |
69ba6af3 | 5351 | |
b2735d9a | 5352 | loop_ivs_free (loop); |
4da896b2 MM |
5353 | if (reg_map) |
5354 | free (reg_map); | |
b4ad7b23 RS |
5355 | } |
5356 | \f | |
5e787f07 | 5357 | /*Record all basic induction variables calculated in the insn. */ |
82ee5e63 | 5358 | static rtx |
0c20a65f AJ |
5359 | check_insn_for_bivs (struct loop *loop, rtx p, int not_every_iteration, |
5360 | int maybe_multiple) | |
5e787f07 | 5361 | { |
ed5bb68d | 5362 | struct loop_ivs *ivs = LOOP_IVS (loop); |
5e787f07 JH |
5363 | rtx set; |
5364 | rtx dest_reg; | |
5365 | rtx inc_val; | |
5366 | rtx mult_val; | |
5367 | rtx *location; | |
5368 | ||
5369 | if (GET_CODE (p) == INSN | |
5370 | && (set = single_set (p)) | |
5371 | && GET_CODE (SET_DEST (set)) == REG) | |
5372 | { | |
5373 | dest_reg = SET_DEST (set); | |
5374 | if (REGNO (dest_reg) < max_reg_before_loop | |
5375 | && REGNO (dest_reg) >= FIRST_PSEUDO_REGISTER | |
ed5bb68d | 5376 | && REG_IV_TYPE (ivs, REGNO (dest_reg)) != NOT_BASIC_INDUCT) |
5e787f07 | 5377 | { |
5e787f07 JH |
5378 | if (basic_induction_var (loop, SET_SRC (set), |
5379 | GET_MODE (SET_SRC (set)), | |
5380 | dest_reg, p, &inc_val, &mult_val, | |
98d1cd45 | 5381 | &location)) |
5e787f07 JH |
5382 | { |
5383 | /* It is a possible basic induction variable. | |
5384 | Create and initialize an induction structure for it. */ | |
5385 | ||
703ad42b | 5386 | struct induction *v = xmalloc (sizeof (struct induction)); |
5e787f07 | 5387 | |
ed5bb68d | 5388 | record_biv (loop, v, p, dest_reg, inc_val, mult_val, location, |
98d1cd45 | 5389 | not_every_iteration, maybe_multiple); |
ed5bb68d | 5390 | REG_IV_TYPE (ivs, REGNO (dest_reg)) = BASIC_INDUCT; |
5e787f07 | 5391 | } |
86fee241 | 5392 | else if (REGNO (dest_reg) < ivs->n_regs) |
ed5bb68d | 5393 | REG_IV_TYPE (ivs, REGNO (dest_reg)) = NOT_BASIC_INDUCT; |
5e787f07 JH |
5394 | } |
5395 | } | |
82ee5e63 | 5396 | return p; |
5e787f07 JH |
5397 | } |
5398 | \f | |
e6fcb60d | 5399 | /* Record all givs calculated in the insn. |
5e787f07 JH |
5400 | A register is a giv if: it is only set once, it is a function of a |
5401 | biv and a constant (or invariant), and it is not a biv. */ | |
82ee5e63 | 5402 | static rtx |
0c20a65f AJ |
5403 | check_insn_for_givs (struct loop *loop, rtx p, int not_every_iteration, |
5404 | int maybe_multiple) | |
5e787f07 | 5405 | { |
1ecd860b | 5406 | struct loop_regs *regs = LOOP_REGS (loop); |
ed5bb68d | 5407 | |
5e787f07 JH |
5408 | rtx set; |
5409 | /* Look for a general induction variable in a register. */ | |
5410 | if (GET_CODE (p) == INSN | |
5411 | && (set = single_set (p)) | |
5412 | && GET_CODE (SET_DEST (set)) == REG | |
f1d4ac80 | 5413 | && ! regs->array[REGNO (SET_DEST (set))].may_not_optimize) |
5e787f07 JH |
5414 | { |
5415 | rtx src_reg; | |
5416 | rtx dest_reg; | |
5417 | rtx add_val; | |
5418 | rtx mult_val; | |
e8cb4873 | 5419 | rtx ext_val; |
5e787f07 JH |
5420 | int benefit; |
5421 | rtx regnote = 0; | |
5422 | rtx last_consec_insn; | |
5423 | ||
5424 | dest_reg = SET_DEST (set); | |
5425 | if (REGNO (dest_reg) < FIRST_PSEUDO_REGISTER) | |
82ee5e63 | 5426 | return p; |
5e787f07 JH |
5427 | |
5428 | if (/* SET_SRC is a giv. */ | |
5429 | (general_induction_var (loop, SET_SRC (set), &src_reg, &add_val, | |
e8cb4873 | 5430 | &mult_val, &ext_val, 0, &benefit, VOIDmode) |
5e787f07 JH |
5431 | /* Equivalent expression is a giv. */ |
5432 | || ((regnote = find_reg_note (p, REG_EQUAL, NULL_RTX)) | |
5433 | && general_induction_var (loop, XEXP (regnote, 0), &src_reg, | |
e8cb4873 | 5434 | &add_val, &mult_val, &ext_val, 0, |
01329426 | 5435 | &benefit, VOIDmode))) |
5e787f07 JH |
5436 | /* Don't try to handle any regs made by loop optimization. |
5437 | We have nothing on them in regno_first_uid, etc. */ | |
5438 | && REGNO (dest_reg) < max_reg_before_loop | |
5439 | /* Don't recognize a BASIC_INDUCT_VAR here. */ | |
5440 | && dest_reg != src_reg | |
5441 | /* This must be the only place where the register is set. */ | |
f1d4ac80 | 5442 | && (regs->array[REGNO (dest_reg)].n_times_set == 1 |
5e787f07 JH |
5443 | /* or all sets must be consecutive and make a giv. */ |
5444 | || (benefit = consec_sets_giv (loop, benefit, p, | |
5445 | src_reg, dest_reg, | |
e8cb4873 | 5446 | &add_val, &mult_val, &ext_val, |
5e787f07 JH |
5447 | &last_consec_insn)))) |
5448 | { | |
703ad42b | 5449 | struct induction *v = xmalloc (sizeof (struct induction)); |
5e787f07 JH |
5450 | |
5451 | /* If this is a library call, increase benefit. */ | |
5452 | if (find_reg_note (p, REG_RETVAL, NULL_RTX)) | |
5453 | benefit += libcall_benefit (p); | |
5454 | ||
5455 | /* Skip the consecutive insns, if there are any. */ | |
f1d4ac80 | 5456 | if (regs->array[REGNO (dest_reg)].n_times_set != 1) |
5e787f07 JH |
5457 | p = last_consec_insn; |
5458 | ||
5459 | record_giv (loop, v, p, src_reg, dest_reg, mult_val, add_val, | |
e8cb4873 | 5460 | ext_val, benefit, DEST_REG, not_every_iteration, |
505ddab6 | 5461 | maybe_multiple, (rtx*) 0); |
5e787f07 JH |
5462 | |
5463 | } | |
5464 | } | |
5465 | ||
5e787f07 | 5466 | /* Look for givs which are memory addresses. */ |
5e787f07 JH |
5467 | if (GET_CODE (p) == INSN) |
5468 | find_mem_givs (loop, PATTERN (p), p, not_every_iteration, | |
5469 | maybe_multiple); | |
5e787f07 JH |
5470 | |
5471 | /* Update the status of whether giv can derive other givs. This can | |
5472 | change when we pass a label or an insn that updates a biv. */ | |
5473 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN | |
e6fcb60d | 5474 | || GET_CODE (p) == CODE_LABEL) |
5e787f07 | 5475 | update_giv_derive (loop, p); |
82ee5e63 | 5476 | return p; |
5e787f07 JH |
5477 | } |
5478 | \f | |
b4ad7b23 RS |
5479 | /* Return 1 if X is a valid source for an initial value (or as value being |
5480 | compared against in an initial test). | |
5481 | ||
5482 | X must be either a register or constant and must not be clobbered between | |
5483 | the current insn and the start of the loop. | |
5484 | ||
5485 | INSN is the insn containing X. */ | |
5486 | ||
5487 | static int | |
0c20a65f | 5488 | valid_initial_value_p (rtx x, rtx insn, int call_seen, rtx loop_start) |
b4ad7b23 RS |
5489 | { |
5490 | if (CONSTANT_P (x)) | |
5491 | return 1; | |
5492 | ||
d45cf215 | 5493 | /* Only consider pseudos we know about initialized in insns whose luids |
b4ad7b23 RS |
5494 | we know. */ |
5495 | if (GET_CODE (x) != REG | |
5496 | || REGNO (x) >= max_reg_before_loop) | |
5497 | return 0; | |
5498 | ||
5499 | /* Don't use call-clobbered registers across a call which clobbers it. On | |
5500 | some machines, don't use any hard registers at all. */ | |
5501 | if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
e9a25f70 JL |
5502 | && (SMALL_REGISTER_CLASSES |
5503 | || (call_used_regs[REGNO (x)] && call_seen))) | |
b4ad7b23 RS |
5504 | return 0; |
5505 | ||
5506 | /* Don't use registers that have been clobbered before the start of the | |
5507 | loop. */ | |
5508 | if (reg_set_between_p (x, insn, loop_start)) | |
5509 | return 0; | |
5510 | ||
5511 | return 1; | |
5512 | } | |
5513 | \f | |
5514 | /* Scan X for memory refs and check each memory address | |
5515 | as a possible giv. INSN is the insn whose pattern X comes from. | |
5516 | NOT_EVERY_ITERATION is 1 if the insn might not be executed during | |
c5c76735 | 5517 | every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed |
3d042e77 | 5518 | more than once in each loop iteration. */ |
b4ad7b23 RS |
5519 | |
5520 | static void | |
0c20a65f AJ |
5521 | find_mem_givs (const struct loop *loop, rtx x, rtx insn, |
5522 | int not_every_iteration, int maybe_multiple) | |
b4ad7b23 | 5523 | { |
b3694847 SS |
5524 | int i, j; |
5525 | enum rtx_code code; | |
5526 | const char *fmt; | |
b4ad7b23 RS |
5527 | |
5528 | if (x == 0) | |
5529 | return; | |
5530 | ||
5531 | code = GET_CODE (x); | |
5532 | switch (code) | |
5533 | { | |
5534 | case REG: | |
5535 | case CONST_INT: | |
5536 | case CONST: | |
5537 | case CONST_DOUBLE: | |
5538 | case SYMBOL_REF: | |
5539 | case LABEL_REF: | |
5540 | case PC: | |
5541 | case CC0: | |
5542 | case ADDR_VEC: | |
5543 | case ADDR_DIFF_VEC: | |
5544 | case USE: | |
5545 | case CLOBBER: | |
5546 | return; | |
5547 | ||
5548 | case MEM: | |
5549 | { | |
5550 | rtx src_reg; | |
5551 | rtx add_val; | |
5552 | rtx mult_val; | |
e8cb4873 | 5553 | rtx ext_val; |
b4ad7b23 RS |
5554 | int benefit; |
5555 | ||
45f97e2e | 5556 | /* This code used to disable creating GIVs with mult_val == 1 and |
e6fcb60d | 5557 | add_val == 0. However, this leads to lost optimizations when |
45f97e2e | 5558 | it comes time to combine a set of related DEST_ADDR GIVs, since |
6d2f8887 | 5559 | this one would not be seen. */ |
b4ad7b23 | 5560 | |
0534b804 | 5561 | if (general_induction_var (loop, XEXP (x, 0), &src_reg, &add_val, |
e8cb4873 RH |
5562 | &mult_val, &ext_val, 1, &benefit, |
5563 | GET_MODE (x))) | |
b4ad7b23 RS |
5564 | { |
5565 | /* Found one; record it. */ | |
703ad42b | 5566 | struct induction *v = xmalloc (sizeof (struct induction)); |
b4ad7b23 | 5567 | |
0534b804 | 5568 | record_giv (loop, v, insn, src_reg, addr_placeholder, mult_val, |
e8cb4873 RH |
5569 | add_val, ext_val, benefit, DEST_ADDR, |
5570 | not_every_iteration, maybe_multiple, &XEXP (x, 0)); | |
b4ad7b23 | 5571 | |
099f0f3f | 5572 | v->mem = x; |
b4ad7b23 | 5573 | } |
b4ad7b23 | 5574 | } |
e9a25f70 JL |
5575 | return; |
5576 | ||
5577 | default: | |
5578 | break; | |
b4ad7b23 RS |
5579 | } |
5580 | ||
5581 | /* Recursively scan the subexpressions for other mem refs. */ | |
5582 | ||
5583 | fmt = GET_RTX_FORMAT (code); | |
5584 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5585 | if (fmt[i] == 'e') | |
0534b804 MH |
5586 | find_mem_givs (loop, XEXP (x, i), insn, not_every_iteration, |
5587 | maybe_multiple); | |
b4ad7b23 RS |
5588 | else if (fmt[i] == 'E') |
5589 | for (j = 0; j < XVECLEN (x, i); j++) | |
0534b804 MH |
5590 | find_mem_givs (loop, XVECEXP (x, i, j), insn, not_every_iteration, |
5591 | maybe_multiple); | |
b4ad7b23 RS |
5592 | } |
5593 | \f | |
5594 | /* Fill in the data about one biv update. | |
5595 | V is the `struct induction' in which we record the biv. (It is | |
5596 | allocated by the caller, with alloca.) | |
5597 | INSN is the insn that sets it. | |
5598 | DEST_REG is the biv's reg. | |
5599 | ||
5600 | MULT_VAL is const1_rtx if the biv is being incremented here, in which case | |
5601 | INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is | |
7dcd3836 RK |
5602 | being set to INC_VAL. |
5603 | ||
5604 | NOT_EVERY_ITERATION is nonzero if this biv update is not know to be | |
5605 | executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update | |
5606 | can be executed more than once per iteration. If MAYBE_MULTIPLE | |
5607 | and NOT_EVERY_ITERATION are both zero, we know that the biv update is | |
5608 | executed exactly once per iteration. */ | |
b4ad7b23 RS |
5609 | |
5610 | static void | |
0c20a65f AJ |
5611 | record_biv (struct loop *loop, struct induction *v, rtx insn, rtx dest_reg, |
5612 | rtx inc_val, rtx mult_val, rtx *location, | |
5613 | int not_every_iteration, int maybe_multiple) | |
b4ad7b23 | 5614 | { |
ed5bb68d | 5615 | struct loop_ivs *ivs = LOOP_IVS (loop); |
b4ad7b23 RS |
5616 | struct iv_class *bl; |
5617 | ||
5618 | v->insn = insn; | |
5619 | v->src_reg = dest_reg; | |
5620 | v->dest_reg = dest_reg; | |
5621 | v->mult_val = mult_val; | |
5622 | v->add_val = inc_val; | |
affd4f33 | 5623 | v->ext_dependent = NULL_RTX; |
3ec2b590 | 5624 | v->location = location; |
b4ad7b23 RS |
5625 | v->mode = GET_MODE (dest_reg); |
5626 | v->always_computable = ! not_every_iteration; | |
8516af93 | 5627 | v->always_executed = ! not_every_iteration; |
7dcd3836 | 5628 | v->maybe_multiple = maybe_multiple; |
c7d325c8 | 5629 | v->same = 0; |
b4ad7b23 RS |
5630 | |
5631 | /* Add this to the reg's iv_class, creating a class | |
5632 | if this is the first incrementation of the reg. */ | |
5633 | ||
8b634749 | 5634 | bl = REG_IV_CLASS (ivs, REGNO (dest_reg)); |
b4ad7b23 RS |
5635 | if (bl == 0) |
5636 | { | |
5637 | /* Create and initialize new iv_class. */ | |
5638 | ||
703ad42b | 5639 | bl = xmalloc (sizeof (struct iv_class)); |
b4ad7b23 RS |
5640 | |
5641 | bl->regno = REGNO (dest_reg); | |
5642 | bl->biv = 0; | |
5643 | bl->giv = 0; | |
5644 | bl->biv_count = 0; | |
5645 | bl->giv_count = 0; | |
5646 | ||
5647 | /* Set initial value to the reg itself. */ | |
5648 | bl->initial_value = dest_reg; | |
e304a8e6 | 5649 | bl->final_value = 0; |
c5b7917e | 5650 | /* We haven't seen the initializing insn yet */ |
b4ad7b23 RS |
5651 | bl->init_insn = 0; |
5652 | bl->init_set = 0; | |
5653 | bl->initial_test = 0; | |
5654 | bl->incremented = 0; | |
5655 | bl->eliminable = 0; | |
5656 | bl->nonneg = 0; | |
5657 | bl->reversed = 0; | |
b5d27be7 | 5658 | bl->total_benefit = 0; |
b4ad7b23 | 5659 | |
14be28e5 MH |
5660 | /* Add this class to ivs->list. */ |
5661 | bl->next = ivs->list; | |
5662 | ivs->list = bl; | |
b4ad7b23 RS |
5663 | |
5664 | /* Put it in the array of biv register classes. */ | |
8b634749 | 5665 | REG_IV_CLASS (ivs, REGNO (dest_reg)) = bl; |
b4ad7b23 | 5666 | } |
c7d325c8 GN |
5667 | else |
5668 | { | |
5669 | /* Check if location is the same as a previous one. */ | |
5670 | struct induction *induction; | |
5671 | for (induction = bl->biv; induction; induction = induction->next_iv) | |
5672 | if (location == induction->location) | |
5673 | { | |
5674 | v->same = induction; | |
5675 | break; | |
5676 | } | |
5677 | } | |
b4ad7b23 RS |
5678 | |
5679 | /* Update IV_CLASS entry for this biv. */ | |
5680 | v->next_iv = bl->biv; | |
5681 | bl->biv = v; | |
5682 | bl->biv_count++; | |
5683 | if (mult_val == const1_rtx) | |
5684 | bl->incremented = 1; | |
5685 | ||
5686 | if (loop_dump_stream) | |
c804f3f8 | 5687 | loop_biv_dump (v, loop_dump_stream, 0); |
b4ad7b23 RS |
5688 | } |
5689 | \f | |
5690 | /* Fill in the data about one giv. | |
5691 | V is the `struct induction' in which we record the giv. (It is | |
5692 | allocated by the caller, with alloca.) | |
5693 | INSN is the insn that sets it. | |
5694 | BENEFIT estimates the savings from deleting this insn. | |
5695 | TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed | |
5696 | into a register or is used as a memory address. | |
5697 | ||
5698 | SRC_REG is the biv reg which the giv is computed from. | |
5699 | DEST_REG is the giv's reg (if the giv is stored in a reg). | |
5700 | MULT_VAL and ADD_VAL are the coefficients used to compute the giv. | |
5701 | LOCATION points to the place where this giv's value appears in INSN. */ | |
5702 | ||
5703 | static void | |
0c20a65f AJ |
5704 | record_giv (const struct loop *loop, struct induction *v, rtx insn, |
5705 | rtx src_reg, rtx dest_reg, rtx mult_val, rtx add_val, | |
5706 | rtx ext_val, int benefit, enum g_types type, | |
5707 | int not_every_iteration, int maybe_multiple, rtx *location) | |
b4ad7b23 | 5708 | { |
ed5bb68d | 5709 | struct loop_ivs *ivs = LOOP_IVS (loop); |
b4ad7b23 RS |
5710 | struct induction *b; |
5711 | struct iv_class *bl; | |
5712 | rtx set = single_set (insn); | |
ce7de04c JH |
5713 | rtx temp; |
5714 | ||
3d042e77 | 5715 | /* Attempt to prove constantness of the values. Don't let simplify_rtx |
9b3bd424 | 5716 | undo the MULT canonicalization that we performed earlier. */ |
ce7de04c | 5717 | temp = simplify_rtx (add_val); |
9b3bd424 RH |
5718 | if (temp |
5719 | && ! (GET_CODE (add_val) == MULT | |
5720 | && GET_CODE (temp) == ASHIFT)) | |
ce7de04c | 5721 | add_val = temp; |
b4ad7b23 RS |
5722 | |
5723 | v->insn = insn; | |
5724 | v->src_reg = src_reg; | |
5725 | v->giv_type = type; | |
5726 | v->dest_reg = dest_reg; | |
5727 | v->mult_val = mult_val; | |
5728 | v->add_val = add_val; | |
affd4f33 | 5729 | v->ext_dependent = ext_val; |
b4ad7b23 RS |
5730 | v->benefit = benefit; |
5731 | v->location = location; | |
5732 | v->cant_derive = 0; | |
5733 | v->combined_with = 0; | |
c5c76735 | 5734 | v->maybe_multiple = maybe_multiple; |
b4ad7b23 RS |
5735 | v->maybe_dead = 0; |
5736 | v->derive_adjustment = 0; | |
5737 | v->same = 0; | |
5738 | v->ignore = 0; | |
5739 | v->new_reg = 0; | |
5740 | v->final_value = 0; | |
f415f7be | 5741 | v->same_insn = 0; |
8516af93 | 5742 | v->auto_inc_opt = 0; |
9ae8ffe7 JL |
5743 | v->unrolled = 0; |
5744 | v->shared = 0; | |
b4ad7b23 RS |
5745 | |
5746 | /* The v->always_computable field is used in update_giv_derive, to | |
5747 | determine whether a giv can be used to derive another giv. For a | |
5748 | DEST_REG giv, INSN computes a new value for the giv, so its value | |
5749 | isn't computable if INSN insn't executed every iteration. | |
5750 | However, for a DEST_ADDR giv, INSN merely uses the value of the giv; | |
5751 | it does not compute a new value. Hence the value is always computable | |
d45cf215 | 5752 | regardless of whether INSN is executed each iteration. */ |
b4ad7b23 RS |
5753 | |
5754 | if (type == DEST_ADDR) | |
5755 | v->always_computable = 1; | |
5756 | else | |
5757 | v->always_computable = ! not_every_iteration; | |
5758 | ||
8516af93 JW |
5759 | v->always_executed = ! not_every_iteration; |
5760 | ||
b4ad7b23 RS |
5761 | if (type == DEST_ADDR) |
5762 | { | |
5763 | v->mode = GET_MODE (*location); | |
5764 | v->lifetime = 1; | |
b4ad7b23 RS |
5765 | } |
5766 | else /* type == DEST_REG */ | |
5767 | { | |
5768 | v->mode = GET_MODE (SET_DEST (set)); | |
5769 | ||
b8056b46 | 5770 | v->lifetime = LOOP_REG_LIFETIME (loop, REGNO (dest_reg)); |
b4ad7b23 | 5771 | |
b4ad7b23 RS |
5772 | /* If the lifetime is zero, it means that this register is |
5773 | really a dead store. So mark this as a giv that can be | |
0f41302f | 5774 | ignored. This will not prevent the biv from being eliminated. */ |
b4ad7b23 RS |
5775 | if (v->lifetime == 0) |
5776 | v->ignore = 1; | |
5777 | ||
ed5bb68d MH |
5778 | REG_IV_TYPE (ivs, REGNO (dest_reg)) = GENERAL_INDUCT; |
5779 | REG_IV_INFO (ivs, REGNO (dest_reg)) = v; | |
b4ad7b23 RS |
5780 | } |
5781 | ||
5782 | /* Add the giv to the class of givs computed from one biv. */ | |
5783 | ||
8b634749 | 5784 | bl = REG_IV_CLASS (ivs, REGNO (src_reg)); |
b4ad7b23 RS |
5785 | if (bl) |
5786 | { | |
5787 | v->next_iv = bl->giv; | |
5788 | bl->giv = v; | |
5789 | /* Don't count DEST_ADDR. This is supposed to count the number of | |
5790 | insns that calculate givs. */ | |
5791 | if (type == DEST_REG) | |
5792 | bl->giv_count++; | |
5793 | bl->total_benefit += benefit; | |
5794 | } | |
5795 | else | |
5796 | /* Fatal error, biv missing for this giv? */ | |
5797 | abort (); | |
5798 | ||
5799 | if (type == DEST_ADDR) | |
3bdcef4d AJ |
5800 | { |
5801 | v->replaceable = 1; | |
5802 | v->not_replaceable = 0; | |
5803 | } | |
b4ad7b23 RS |
5804 | else |
5805 | { | |
5806 | /* The giv can be replaced outright by the reduced register only if all | |
5807 | of the following conditions are true: | |
6b8c9327 | 5808 | - the insn that sets the giv is always executed on any iteration |
b4ad7b23 RS |
5809 | on which the giv is used at all |
5810 | (there are two ways to deduce this: | |
5811 | either the insn is executed on every iteration, | |
5812 | or all uses follow that insn in the same basic block), | |
6b8c9327 | 5813 | - the giv is not used outside the loop |
b4ad7b23 RS |
5814 | - no assignments to the biv occur during the giv's lifetime. */ |
5815 | ||
b1f21e0a | 5816 | if (REGNO_FIRST_UID (REGNO (dest_reg)) == INSN_UID (insn) |
b4ad7b23 | 5817 | /* Previous line always fails if INSN was moved by loop opt. */ |
8529a489 | 5818 | && REGNO_LAST_LUID (REGNO (dest_reg)) |
0534b804 | 5819 | < INSN_LUID (loop->end) |
b4ad7b23 RS |
5820 | && (! not_every_iteration |
5821 | || last_use_this_basic_block (dest_reg, insn))) | |
e6fcb60d | 5822 | { |
b4ad7b23 RS |
5823 | /* Now check that there are no assignments to the biv within the |
5824 | giv's lifetime. This requires two separate checks. */ | |
5825 | ||
5826 | /* Check each biv update, and fail if any are between the first | |
5827 | and last use of the giv. | |
e6fcb60d | 5828 | |
b4ad7b23 RS |
5829 | If this loop contains an inner loop that was unrolled, then |
5830 | the insn modifying the biv may have been emitted by the loop | |
5831 | unrolling code, and hence does not have a valid luid. Just | |
5832 | mark the biv as not replaceable in this case. It is not very | |
5833 | useful as a biv, because it is used in two different loops. | |
5834 | It is very unlikely that we would be able to optimize the giv | |
5835 | using this biv anyways. */ | |
5836 | ||
5837 | v->replaceable = 1; | |
3bdcef4d | 5838 | v->not_replaceable = 0; |
b4ad7b23 RS |
5839 | for (b = bl->biv; b; b = b->next_iv) |
5840 | { | |
5841 | if (INSN_UID (b->insn) >= max_uid_for_loop | |
8529a489 MH |
5842 | || ((INSN_LUID (b->insn) |
5843 | >= REGNO_FIRST_LUID (REGNO (dest_reg))) | |
5844 | && (INSN_LUID (b->insn) | |
5845 | <= REGNO_LAST_LUID (REGNO (dest_reg))))) | |
b4ad7b23 RS |
5846 | { |
5847 | v->replaceable = 0; | |
5848 | v->not_replaceable = 1; | |
5849 | break; | |
e6fcb60d | 5850 | } |
b4ad7b23 RS |
5851 | } |
5852 | ||
5031afa7 JW |
5853 | /* If there are any backwards branches that go from after the |
5854 | biv update to before it, then this giv is not replaceable. */ | |
b4ad7b23 | 5855 | if (v->replaceable) |
5031afa7 | 5856 | for (b = bl->biv; b; b = b->next_iv) |
0534b804 | 5857 | if (back_branch_in_range_p (loop, b->insn)) |
5031afa7 JW |
5858 | { |
5859 | v->replaceable = 0; | |
5860 | v->not_replaceable = 1; | |
5861 | break; | |
5862 | } | |
b4ad7b23 RS |
5863 | } |
5864 | else | |
5865 | { | |
5866 | /* May still be replaceable, we don't have enough info here to | |
5867 | decide. */ | |
5868 | v->replaceable = 0; | |
5869 | v->not_replaceable = 0; | |
5870 | } | |
5871 | } | |
5872 | ||
45f97e2e RH |
5873 | /* Record whether the add_val contains a const_int, for later use by |
5874 | combine_givs. */ | |
5875 | { | |
5876 | rtx tem = add_val; | |
5877 | ||
5878 | v->no_const_addval = 1; | |
5879 | if (tem == const0_rtx) | |
5880 | ; | |
ce7de04c | 5881 | else if (CONSTANT_P (add_val)) |
45f97e2e | 5882 | v->no_const_addval = 0; |
ce7de04c | 5883 | if (GET_CODE (tem) == PLUS) |
45f97e2e | 5884 | { |
ce7de04c | 5885 | while (1) |
45f97e2e RH |
5886 | { |
5887 | if (GET_CODE (XEXP (tem, 0)) == PLUS) | |
5888 | tem = XEXP (tem, 0); | |
5889 | else if (GET_CODE (XEXP (tem, 1)) == PLUS) | |
5890 | tem = XEXP (tem, 1); | |
5891 | else | |
5892 | break; | |
5893 | } | |
ce7de04c JH |
5894 | if (CONSTANT_P (XEXP (tem, 1))) |
5895 | v->no_const_addval = 0; | |
45f97e2e RH |
5896 | } |
5897 | } | |
5898 | ||
b4ad7b23 | 5899 | if (loop_dump_stream) |
c804f3f8 | 5900 | loop_giv_dump (v, loop_dump_stream, 0); |
b4ad7b23 RS |
5901 | } |
5902 | ||
b4ad7b23 RS |
5903 | /* All this does is determine whether a giv can be made replaceable because |
5904 | its final value can be calculated. This code can not be part of record_giv | |
5905 | above, because final_giv_value requires that the number of loop iterations | |
5906 | be known, and that can not be accurately calculated until after all givs | |
5907 | have been identified. */ | |
5908 | ||
5909 | static void | |
0c20a65f | 5910 | check_final_value (const struct loop *loop, struct induction *v) |
b4ad7b23 | 5911 | { |
b4ad7b23 | 5912 | rtx final_value = 0; |
b4ad7b23 | 5913 | |
b4ad7b23 RS |
5914 | /* DEST_ADDR givs will never reach here, because they are always marked |
5915 | replaceable above in record_giv. */ | |
5916 | ||
5917 | /* The giv can be replaced outright by the reduced register only if all | |
5918 | of the following conditions are true: | |
5919 | - the insn that sets the giv is always executed on any iteration | |
5920 | on which the giv is used at all | |
5921 | (there are two ways to deduce this: | |
5922 | either the insn is executed on every iteration, | |
5923 | or all uses follow that insn in the same basic block), | |
5924 | - its final value can be calculated (this condition is different | |
5925 | than the one above in record_giv) | |
70dd0f7f | 5926 | - it's not used before the it's set |
b4ad7b23 RS |
5927 | - no assignments to the biv occur during the giv's lifetime. */ |
5928 | ||
5929 | #if 0 | |
5930 | /* This is only called now when replaceable is known to be false. */ | |
5931 | /* Clear replaceable, so that it won't confuse final_giv_value. */ | |
5932 | v->replaceable = 0; | |
5933 | #endif | |
5934 | ||
0534b804 | 5935 | if ((final_value = final_giv_value (loop, v)) |
045d7161 EB |
5936 | && (v->always_executed |
5937 | || last_use_this_basic_block (v->dest_reg, v->insn))) | |
b4ad7b23 | 5938 | { |
70dd0f7f | 5939 | int biv_increment_seen = 0, before_giv_insn = 0; |
b4ad7b23 RS |
5940 | rtx p = v->insn; |
5941 | rtx last_giv_use; | |
5942 | ||
5943 | v->replaceable = 1; | |
3bdcef4d | 5944 | v->not_replaceable = 0; |
b4ad7b23 RS |
5945 | |
5946 | /* When trying to determine whether or not a biv increment occurs | |
5947 | during the lifetime of the giv, we can ignore uses of the variable | |
5948 | outside the loop because final_value is true. Hence we can not | |
5949 | use regno_last_uid and regno_first_uid as above in record_giv. */ | |
5950 | ||
5951 | /* Search the loop to determine whether any assignments to the | |
5952 | biv occur during the giv's lifetime. Start with the insn | |
5953 | that sets the giv, and search around the loop until we come | |
5954 | back to that insn again. | |
5955 | ||
5956 | Also fail if there is a jump within the giv's lifetime that jumps | |
5957 | to somewhere outside the lifetime but still within the loop. This | |
5958 | catches spaghetti code where the execution order is not linear, and | |
5959 | hence the above test fails. Here we assume that the giv lifetime | |
5960 | does not extend from one iteration of the loop to the next, so as | |
5961 | to make the test easier. Since the lifetime isn't known yet, | |
5962 | this requires two loops. See also record_giv above. */ | |
5963 | ||
5964 | last_giv_use = v->insn; | |
5965 | ||
5966 | while (1) | |
5967 | { | |
5968 | p = NEXT_INSN (p); | |
0534b804 | 5969 | if (p == loop->end) |
70dd0f7f FS |
5970 | { |
5971 | before_giv_insn = 1; | |
5972 | p = NEXT_INSN (loop->start); | |
5973 | } | |
b4ad7b23 RS |
5974 | if (p == v->insn) |
5975 | break; | |
5976 | ||
5977 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN | |
5978 | || GET_CODE (p) == CALL_INSN) | |
5979 | { | |
8a09bb27 JW |
5980 | /* It is possible for the BIV increment to use the GIV if we |
5981 | have a cycle. Thus we must be sure to check each insn for | |
5982 | both BIV and GIV uses, and we must check for BIV uses | |
5983 | first. */ | |
5984 | ||
5985 | if (! biv_increment_seen | |
5986 | && reg_set_p (v->src_reg, PATTERN (p))) | |
5987 | biv_increment_seen = 1; | |
fd5d5b07 | 5988 | |
8a09bb27 | 5989 | if (reg_mentioned_p (v->dest_reg, PATTERN (p))) |
b4ad7b23 | 5990 | { |
70dd0f7f | 5991 | if (biv_increment_seen || before_giv_insn) |
b4ad7b23 RS |
5992 | { |
5993 | v->replaceable = 0; | |
5994 | v->not_replaceable = 1; | |
5995 | break; | |
5996 | } | |
8a09bb27 | 5997 | last_giv_use = p; |
b4ad7b23 | 5998 | } |
b4ad7b23 RS |
5999 | } |
6000 | } | |
e6fcb60d | 6001 | |
b4ad7b23 RS |
6002 | /* Now that the lifetime of the giv is known, check for branches |
6003 | from within the lifetime to outside the lifetime if it is still | |
6004 | replaceable. */ | |
6005 | ||
6006 | if (v->replaceable) | |
6007 | { | |
6008 | p = v->insn; | |
6009 | while (1) | |
6010 | { | |
6011 | p = NEXT_INSN (p); | |
0534b804 MH |
6012 | if (p == loop->end) |
6013 | p = NEXT_INSN (loop->start); | |
b4ad7b23 RS |
6014 | if (p == last_giv_use) |
6015 | break; | |
6016 | ||
6017 | if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) | |
6018 | && LABEL_NAME (JUMP_LABEL (p)) | |
1cb1fe66 | 6019 | && ((loop_insn_first_p (JUMP_LABEL (p), v->insn) |
0534b804 | 6020 | && loop_insn_first_p (loop->start, JUMP_LABEL (p))) |
1cb1fe66 | 6021 | || (loop_insn_first_p (last_giv_use, JUMP_LABEL (p)) |
0534b804 | 6022 | && loop_insn_first_p (JUMP_LABEL (p), loop->end)))) |
b4ad7b23 RS |
6023 | { |
6024 | v->replaceable = 0; | |
6025 | v->not_replaceable = 1; | |
6026 | ||
6027 | if (loop_dump_stream) | |
6028 | fprintf (loop_dump_stream, | |
6029 | "Found branch outside giv lifetime.\n"); | |
6030 | ||
6031 | break; | |
6032 | } | |
6033 | } | |
6034 | } | |
6035 | ||
6036 | /* If it is replaceable, then save the final value. */ | |
6037 | if (v->replaceable) | |
6038 | v->final_value = final_value; | |
6039 | } | |
6040 | ||
6041 | if (loop_dump_stream && v->replaceable) | |
6042 | fprintf (loop_dump_stream, "Insn %d: giv reg %d final_value replaceable\n", | |
6043 | INSN_UID (v->insn), REGNO (v->dest_reg)); | |
6044 | } | |
6045 | \f | |
6046 | /* Update the status of whether a giv can derive other givs. | |
6047 | ||
6048 | We need to do something special if there is or may be an update to the biv | |
6049 | between the time the giv is defined and the time it is used to derive | |
6050 | another giv. | |
6051 | ||
6052 | In addition, a giv that is only conditionally set is not allowed to | |
6053 | derive another giv once a label has been passed. | |
6054 | ||
6055 | The cases we look at are when a label or an update to a biv is passed. */ | |
6056 | ||
6057 | static void | |
0c20a65f | 6058 | update_giv_derive (const struct loop *loop, rtx p) |
b4ad7b23 | 6059 | { |
ed5bb68d | 6060 | struct loop_ivs *ivs = LOOP_IVS (loop); |
b4ad7b23 RS |
6061 | struct iv_class *bl; |
6062 | struct induction *biv, *giv; | |
6063 | rtx tem; | |
6064 | int dummy; | |
6065 | ||
6066 | /* Search all IV classes, then all bivs, and finally all givs. | |
6067 | ||
7dcd3836 | 6068 | There are three cases we are concerned with. First we have the situation |
b4ad7b23 RS |
6069 | of a giv that is only updated conditionally. In that case, it may not |
6070 | derive any givs after a label is passed. | |
6071 | ||
6072 | The second case is when a biv update occurs, or may occur, after the | |
6073 | definition of a giv. For certain biv updates (see below) that are | |
6074 | known to occur between the giv definition and use, we can adjust the | |
6075 | giv definition. For others, or when the biv update is conditional, | |
6076 | we must prevent the giv from deriving any other givs. There are two | |
6077 | sub-cases within this case. | |
6078 | ||
6079 | If this is a label, we are concerned with any biv update that is done | |
6080 | conditionally, since it may be done after the giv is defined followed by | |
6081 | a branch here (actually, we need to pass both a jump and a label, but | |
6082 | this extra tracking doesn't seem worth it). | |
6083 | ||
7dcd3836 RK |
6084 | If this is a jump, we are concerned about any biv update that may be |
6085 | executed multiple times. We are actually only concerned about | |
6086 | backward jumps, but it is probably not worth performing the test | |
6087 | on the jump again here. | |
6088 | ||
6089 | If this is a biv update, we must adjust the giv status to show that a | |
b4ad7b23 RS |
6090 | subsequent biv update was performed. If this adjustment cannot be done, |
6091 | the giv cannot derive further givs. */ | |
6092 | ||
14be28e5 | 6093 | for (bl = ivs->list; bl; bl = bl->next) |
b4ad7b23 | 6094 | for (biv = bl->biv; biv; biv = biv->next_iv) |
7dcd3836 RK |
6095 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN |
6096 | || biv->insn == p) | |
b4ad7b23 RS |
6097 | { |
6098 | for (giv = bl->giv; giv; giv = giv->next_iv) | |
6099 | { | |
6100 | /* If cant_derive is already true, there is no point in | |
6101 | checking all of these conditions again. */ | |
6102 | if (giv->cant_derive) | |
6103 | continue; | |
6104 | ||
6105 | /* If this giv is conditionally set and we have passed a label, | |
6106 | it cannot derive anything. */ | |
6107 | if (GET_CODE (p) == CODE_LABEL && ! giv->always_computable) | |
6108 | giv->cant_derive = 1; | |
6109 | ||
6110 | /* Skip givs that have mult_val == 0, since | |
6111 | they are really invariants. Also skip those that are | |
6112 | replaceable, since we know their lifetime doesn't contain | |
6113 | any biv update. */ | |
6114 | else if (giv->mult_val == const0_rtx || giv->replaceable) | |
6115 | continue; | |
6116 | ||
6117 | /* The only way we can allow this giv to derive another | |
6118 | is if this is a biv increment and we can form the product | |
6119 | of biv->add_val and giv->mult_val. In this case, we will | |
6120 | be able to compute a compensation. */ | |
6121 | else if (biv->insn == p) | |
6122 | { | |
e8cb4873 | 6123 | rtx ext_val_dummy; |
c160c628 | 6124 | |
e8cb4873 | 6125 | tem = 0; |
c160c628 | 6126 | if (biv->mult_val == const1_rtx) |
0534b804 MH |
6127 | tem = simplify_giv_expr (loop, |
6128 | gen_rtx_MULT (giv->mode, | |
38a448ca RH |
6129 | biv->add_val, |
6130 | giv->mult_val), | |
e8cb4873 | 6131 | &ext_val_dummy, &dummy); |
c160c628 RK |
6132 | |
6133 | if (tem && giv->derive_adjustment) | |
c5c76735 | 6134 | tem = simplify_giv_expr |
0534b804 MH |
6135 | (loop, |
6136 | gen_rtx_PLUS (giv->mode, tem, giv->derive_adjustment), | |
e8cb4873 | 6137 | &ext_val_dummy, &dummy); |
c5c76735 | 6138 | |
c160c628 | 6139 | if (tem) |
b4ad7b23 RS |
6140 | giv->derive_adjustment = tem; |
6141 | else | |
6142 | giv->cant_derive = 1; | |
6143 | } | |
7dcd3836 RK |
6144 | else if ((GET_CODE (p) == CODE_LABEL && ! biv->always_computable) |
6145 | || (GET_CODE (p) == JUMP_INSN && biv->maybe_multiple)) | |
b4ad7b23 RS |
6146 | giv->cant_derive = 1; |
6147 | } | |
6148 | } | |
6149 | } | |
6150 | \f | |
6151 | /* Check whether an insn is an increment legitimate for a basic induction var. | |
7056f7e8 RS |
6152 | X is the source of insn P, or a part of it. |
6153 | MODE is the mode in which X should be interpreted. | |
6154 | ||
b4ad7b23 RS |
6155 | DEST_REG is the putative biv, also the destination of the insn. |
6156 | We accept patterns of these forms: | |
09d7f5a5 | 6157 | REG = REG + INVARIANT (includes REG = REG - CONSTANT) |
b4ad7b23 | 6158 | REG = INVARIANT + REG |
b4ad7b23 RS |
6159 | |
6160 | If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX, | |
3ec2b590 R |
6161 | store the additive term into *INC_VAL, and store the place where |
6162 | we found the additive term into *LOCATION. | |
b4ad7b23 RS |
6163 | |
6164 | If X is an assignment of an invariant into DEST_REG, we set | |
6165 | *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL. | |
6166 | ||
09d7f5a5 RK |
6167 | We also want to detect a BIV when it corresponds to a variable |
6168 | whose mode was promoted via PROMOTED_MODE. In that case, an increment | |
6169 | of the variable may be a PLUS that adds a SUBREG of that variable to | |
6170 | an invariant and then sign- or zero-extends the result of the PLUS | |
6171 | into the variable. | |
6172 | ||
6173 | Most GIVs in such cases will be in the promoted mode, since that is the | |
6174 | probably the natural computation mode (and almost certainly the mode | |
6175 | used for addresses) on the machine. So we view the pseudo-reg containing | |
6176 | the variable as the BIV, as if it were simply incremented. | |
6177 | ||
6178 | Note that treating the entire pseudo as a BIV will result in making | |
6179 | simple increments to any GIVs based on it. However, if the variable | |
6180 | overflows in its declared mode but not its promoted mode, the result will | |
e6fcb60d | 6181 | be incorrect. This is acceptable if the variable is signed, since |
09d7f5a5 RK |
6182 | overflows in such cases are undefined, but not if it is unsigned, since |
6183 | those overflows are defined. So we only check for SIGN_EXTEND and | |
6184 | not ZERO_EXTEND. | |
6185 | ||
6186 | If we cannot find a biv, we return 0. */ | |
b4ad7b23 RS |
6187 | |
6188 | static int | |
0c20a65f AJ |
6189 | basic_induction_var (const struct loop *loop, rtx x, enum machine_mode mode, |
6190 | rtx dest_reg, rtx p, rtx *inc_val, rtx *mult_val, | |
6191 | rtx **location) | |
b4ad7b23 | 6192 | { |
b3694847 | 6193 | enum rtx_code code; |
3ec2b590 | 6194 | rtx *argp, arg; |
16f6812f | 6195 | rtx insn, set = 0, last, inc; |
b4ad7b23 RS |
6196 | |
6197 | code = GET_CODE (x); | |
69ba6af3 | 6198 | *location = NULL; |
b4ad7b23 RS |
6199 | switch (code) |
6200 | { | |
6201 | case PLUS: | |
45f97e2e | 6202 | if (rtx_equal_p (XEXP (x, 0), dest_reg) |
09d7f5a5 RK |
6203 | || (GET_CODE (XEXP (x, 0)) == SUBREG |
6204 | && SUBREG_PROMOTED_VAR_P (XEXP (x, 0)) | |
6205 | && SUBREG_REG (XEXP (x, 0)) == dest_reg)) | |
3ec2b590 R |
6206 | { |
6207 | argp = &XEXP (x, 1); | |
6208 | } | |
45f97e2e | 6209 | else if (rtx_equal_p (XEXP (x, 1), dest_reg) |
09d7f5a5 | 6210 | || (GET_CODE (XEXP (x, 1)) == SUBREG |
b81fd0f4 RS |
6211 | && SUBREG_PROMOTED_VAR_P (XEXP (x, 1)) |
6212 | && SUBREG_REG (XEXP (x, 1)) == dest_reg)) | |
3ec2b590 R |
6213 | { |
6214 | argp = &XEXP (x, 0); | |
6215 | } | |
b4ad7b23 | 6216 | else |
e6fcb60d | 6217 | return 0; |
b4ad7b23 | 6218 | |
3ec2b590 | 6219 | arg = *argp; |
0534b804 | 6220 | if (loop_invariant_p (loop, arg) != 1) |
b4ad7b23 RS |
6221 | return 0; |
6222 | ||
16f6812f JJ |
6223 | /* convert_modes can emit new instructions, e.g. when arg is a loop |
6224 | invariant MEM and dest_reg has a different mode. | |
6225 | These instructions would be emitted after the end of the function | |
d91edf86 | 6226 | and then *inc_val would be an uninitialized pseudo. |
16f6812f JJ |
6227 | Detect this and bail in this case. |
6228 | Other alternatives to solve this can be introducing a convert_modes | |
6229 | variant which is allowed to fail but not allowed to emit new | |
6230 | instructions, emit these instructions before loop start and let | |
6231 | it be garbage collected if *inc_val is never used or saving the | |
6232 | *inc_val initialization sequence generated here and when *inc_val | |
6233 | is going to be actually used, emit it at some suitable place. */ | |
6234 | last = get_last_insn (); | |
6235 | inc = convert_modes (GET_MODE (dest_reg), GET_MODE (x), arg, 0); | |
6236 | if (get_last_insn () != last) | |
6237 | { | |
6238 | delete_insns_since (last); | |
6239 | return 0; | |
6240 | } | |
6241 | ||
6242 | *inc_val = inc; | |
b4ad7b23 | 6243 | *mult_val = const1_rtx; |
3ec2b590 | 6244 | *location = argp; |
b4ad7b23 RS |
6245 | return 1; |
6246 | ||
09d7f5a5 | 6247 | case SUBREG: |
b76b08ef RK |
6248 | /* If what's inside the SUBREG is a BIV, then the SUBREG. This will |
6249 | handle addition of promoted variables. | |
6250 | ??? The comment at the start of this function is wrong: promoted | |
6251 | variable increments don't look like it says they do. */ | |
6252 | return basic_induction_var (loop, SUBREG_REG (x), | |
6253 | GET_MODE (SUBREG_REG (x)), | |
6254 | dest_reg, p, inc_val, mult_val, location); | |
b4ad7b23 | 6255 | |
09d7f5a5 | 6256 | case REG: |
45f97e2e | 6257 | /* If this register is assigned in a previous insn, look at its |
09d7f5a5 RK |
6258 | source, but don't go outside the loop or past a label. */ |
6259 | ||
af198097 R |
6260 | /* If this sets a register to itself, we would repeat any previous |
6261 | biv increment if we applied this strategy blindly. */ | |
6262 | if (rtx_equal_p (dest_reg, x)) | |
6263 | return 0; | |
6264 | ||
45f97e2e RH |
6265 | insn = p; |
6266 | while (1) | |
6267 | { | |
7dbe6ae9 | 6268 | rtx dest; |
e6fcb60d KH |
6269 | do |
6270 | { | |
6271 | insn = PREV_INSN (insn); | |
6272 | } | |
6273 | while (insn && GET_CODE (insn) == NOTE | |
6274 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG); | |
09d7f5a5 | 6275 | |
e6fcb60d | 6276 | if (!insn) |
45f97e2e RH |
6277 | break; |
6278 | set = single_set (insn); | |
6279 | if (set == 0) | |
6280 | break; | |
7dbe6ae9 BS |
6281 | dest = SET_DEST (set); |
6282 | if (dest == x | |
6283 | || (GET_CODE (dest) == SUBREG | |
6284 | && (GET_MODE_SIZE (GET_MODE (dest)) <= UNITS_PER_WORD) | |
6285 | && (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT) | |
6286 | && SUBREG_REG (dest) == x)) | |
6287 | return basic_induction_var (loop, SET_SRC (set), | |
6288 | (GET_MODE (SET_SRC (set)) == VOIDmode | |
6289 | ? GET_MODE (x) | |
6290 | : GET_MODE (SET_SRC (set))), | |
6291 | dest_reg, insn, | |
6292 | inc_val, mult_val, location); | |
6293 | ||
6294 | while (GET_CODE (dest) == SIGN_EXTRACT | |
6295 | || GET_CODE (dest) == ZERO_EXTRACT | |
6296 | || GET_CODE (dest) == SUBREG | |
6297 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6298 | dest = XEXP (dest, 0); | |
6299 | if (dest == x) | |
6300 | break; | |
45f97e2e | 6301 | } |
fd5d5b07 | 6302 | /* Fall through. */ |
b4ad7b23 RS |
6303 | |
6304 | /* Can accept constant setting of biv only when inside inner most loop. | |
6b8c9327 | 6305 | Otherwise, a biv of an inner loop may be incorrectly recognized |
b4ad7b23 RS |
6306 | as a biv of the outer loop, |
6307 | causing code to be moved INTO the inner loop. */ | |
6308 | case MEM: | |
0534b804 | 6309 | if (loop_invariant_p (loop, x) != 1) |
b4ad7b23 RS |
6310 | return 0; |
6311 | case CONST_INT: | |
6312 | case SYMBOL_REF: | |
6313 | case CONST: | |
829002bb BM |
6314 | /* convert_modes aborts if we try to convert to or from CCmode, so just |
6315 | exclude that case. It is very unlikely that a condition code value | |
4061c1a3 JJ |
6316 | would be a useful iterator anyways. convert_modes aborts if we try to |
6317 | convert a float mode to non-float or vice versa too. */ | |
0534b804 | 6318 | if (loop->level == 1 |
4061c1a3 JJ |
6319 | && GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (dest_reg)) |
6320 | && GET_MODE_CLASS (mode) != MODE_CC) | |
fd5d5b07 | 6321 | { |
7056f7e8 | 6322 | /* Possible bug here? Perhaps we don't know the mode of X. */ |
16f6812f JJ |
6323 | last = get_last_insn (); |
6324 | inc = convert_modes (GET_MODE (dest_reg), mode, x, 0); | |
6325 | if (get_last_insn () != last) | |
6326 | { | |
6327 | delete_insns_since (last); | |
6328 | return 0; | |
6329 | } | |
6330 | ||
6331 | *inc_val = inc; | |
e6fcb60d KH |
6332 | *mult_val = const0_rtx; |
6333 | return 1; | |
6334 | } | |
b4ad7b23 | 6335 | else |
e6fcb60d | 6336 | return 0; |
b4ad7b23 | 6337 | |
09d7f5a5 | 6338 | case SIGN_EXTEND: |
4fa26a60 RS |
6339 | /* Ignore this BIV if signed arithmetic overflow is defined. */ |
6340 | if (flag_wrapv) | |
6341 | return 0; | |
0534b804 | 6342 | return basic_induction_var (loop, XEXP (x, 0), GET_MODE (XEXP (x, 0)), |
98d1cd45 | 6343 | dest_reg, p, inc_val, mult_val, location); |
45f97e2e | 6344 | |
09d7f5a5 RK |
6345 | case ASHIFTRT: |
6346 | /* Similar, since this can be a sign extension. */ | |
6347 | for (insn = PREV_INSN (p); | |
6348 | (insn && GET_CODE (insn) == NOTE | |
6349 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG); | |
6350 | insn = PREV_INSN (insn)) | |
6351 | ; | |
6352 | ||
6353 | if (insn) | |
6354 | set = single_set (insn); | |
6355 | ||
af198097 R |
6356 | if (! rtx_equal_p (dest_reg, XEXP (x, 0)) |
6357 | && set && SET_DEST (set) == XEXP (x, 0) | |
09d7f5a5 RK |
6358 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
6359 | && INTVAL (XEXP (x, 1)) >= 0 | |
6360 | && GET_CODE (SET_SRC (set)) == ASHIFT | |
98d1cd45 R |
6361 | && XEXP (x, 1) == XEXP (SET_SRC (set), 1)) |
6362 | return basic_induction_var (loop, XEXP (SET_SRC (set), 0), | |
6363 | GET_MODE (XEXP (x, 0)), | |
6364 | dest_reg, insn, inc_val, mult_val, | |
6365 | location); | |
09d7f5a5 RK |
6366 | return 0; |
6367 | ||
b4ad7b23 RS |
6368 | default: |
6369 | return 0; | |
6370 | } | |
6371 | } | |
6372 | \f | |
6373 | /* A general induction variable (giv) is any quantity that is a linear | |
6374 | function of a basic induction variable, | |
6375 | i.e. giv = biv * mult_val + add_val. | |
6376 | The coefficients can be any loop invariant quantity. | |
6377 | A giv need not be computed directly from the biv; | |
6378 | it can be computed by way of other givs. */ | |
6379 | ||
6380 | /* Determine whether X computes a giv. | |
6381 | If it does, return a nonzero value | |
6382 | which is the benefit from eliminating the computation of X; | |
6383 | set *SRC_REG to the register of the biv that it is computed from; | |
6384 | set *ADD_VAL and *MULT_VAL to the coefficients, | |
6385 | such that the value of X is biv * mult + add; */ | |
6386 | ||
6387 | static int | |
0c20a65f AJ |
6388 | general_induction_var (const struct loop *loop, rtx x, rtx *src_reg, |
6389 | rtx *add_val, rtx *mult_val, rtx *ext_val, | |
6390 | int is_addr, int *pbenefit, | |
6391 | enum machine_mode addr_mode) | |
b4ad7b23 | 6392 | { |
ed5bb68d | 6393 | struct loop_ivs *ivs = LOOP_IVS (loop); |
b4ad7b23 | 6394 | rtx orig_x = x; |
b4ad7b23 RS |
6395 | |
6396 | /* If this is an invariant, forget it, it isn't a giv. */ | |
0534b804 | 6397 | if (loop_invariant_p (loop, x) == 1) |
b4ad7b23 RS |
6398 | return 0; |
6399 | ||
45f97e2e | 6400 | *pbenefit = 0; |
e8cb4873 RH |
6401 | *ext_val = NULL_RTX; |
6402 | x = simplify_giv_expr (loop, x, ext_val, pbenefit); | |
b4ad7b23 | 6403 | if (x == 0) |
1f8f4a0b | 6404 | return 0; |
b4ad7b23 RS |
6405 | |
6406 | switch (GET_CODE (x)) | |
6407 | { | |
6408 | case USE: | |
6409 | case CONST_INT: | |
6410 | /* Since this is now an invariant and wasn't before, it must be a giv | |
6411 | with MULT_VAL == 0. It doesn't matter which BIV we associate this | |
6412 | with. */ | |
14be28e5 | 6413 | *src_reg = ivs->list->biv->dest_reg; |
b4ad7b23 RS |
6414 | *mult_val = const0_rtx; |
6415 | *add_val = x; | |
6416 | break; | |
6417 | ||
6418 | case REG: | |
6419 | /* This is equivalent to a BIV. */ | |
6420 | *src_reg = x; | |
6421 | *mult_val = const1_rtx; | |
6422 | *add_val = const0_rtx; | |
6423 | break; | |
6424 | ||
6425 | case PLUS: | |
6426 | /* Either (plus (biv) (invar)) or | |
6427 | (plus (mult (biv) (invar_1)) (invar_2)). */ | |
6428 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
6429 | { | |
6430 | *src_reg = XEXP (XEXP (x, 0), 0); | |
6431 | *mult_val = XEXP (XEXP (x, 0), 1); | |
6432 | } | |
6433 | else | |
6434 | { | |
6435 | *src_reg = XEXP (x, 0); | |
6436 | *mult_val = const1_rtx; | |
6437 | } | |
6438 | *add_val = XEXP (x, 1); | |
6439 | break; | |
6440 | ||
6441 | case MULT: | |
6442 | /* ADD_VAL is zero. */ | |
6443 | *src_reg = XEXP (x, 0); | |
6444 | *mult_val = XEXP (x, 1); | |
6445 | *add_val = const0_rtx; | |
6446 | break; | |
6447 | ||
6448 | default: | |
6449 | abort (); | |
6450 | } | |
6451 | ||
6452 | /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be | |
6453 | unless they are CONST_INT). */ | |
6454 | if (GET_CODE (*add_val) == USE) | |
6455 | *add_val = XEXP (*add_val, 0); | |
6456 | if (GET_CODE (*mult_val) == USE) | |
6457 | *mult_val = XEXP (*mult_val, 0); | |
6458 | ||
45f97e2e | 6459 | if (is_addr) |
01329426 | 6460 | *pbenefit += address_cost (orig_x, addr_mode) - reg_address_cost; |
45f97e2e RH |
6461 | else |
6462 | *pbenefit += rtx_cost (orig_x, SET); | |
b4ad7b23 | 6463 | |
45f97e2e | 6464 | /* Always return true if this is a giv so it will be detected as such, |
e6fcb60d KH |
6465 | even if the benefit is zero or negative. This allows elimination |
6466 | of bivs that might otherwise not be eliminated. */ | |
6467 | return 1; | |
b4ad7b23 RS |
6468 | } |
6469 | \f | |
6470 | /* Given an expression, X, try to form it as a linear function of a biv. | |
6471 | We will canonicalize it to be of the form | |
6b8c9327 | 6472 | (plus (mult (BIV) (invar_1)) |
b4ad7b23 | 6473 | (invar_2)) |
c5b7917e | 6474 | with possible degeneracies. |
b4ad7b23 RS |
6475 | |
6476 | The invariant expressions must each be of a form that can be used as a | |
6477 | machine operand. We surround then with a USE rtx (a hack, but localized | |
6478 | and certainly unambiguous!) if not a CONST_INT for simplicity in this | |
6479 | routine; it is the caller's responsibility to strip them. | |
6480 | ||
6481 | If no such canonicalization is possible (i.e., two biv's are used or an | |
6482 | expression that is neither invariant nor a biv or giv), this routine | |
6483 | returns 0. | |
6484 | ||
cc2902df | 6485 | For a nonzero return, the result will have a code of CONST_INT, USE, |
e6fcb60d | 6486 | REG (for a BIV), PLUS, or MULT. No other codes will occur. |
b4ad7b23 RS |
6487 | |
6488 | *BENEFIT will be incremented by the benefit of any sub-giv encountered. */ | |
6489 | ||
0c20a65f AJ |
6490 | static rtx sge_plus (enum machine_mode, rtx, rtx); |
6491 | static rtx sge_plus_constant (rtx, rtx); | |
45f97e2e | 6492 | |
b4ad7b23 | 6493 | static rtx |
0c20a65f | 6494 | simplify_giv_expr (const struct loop *loop, rtx x, rtx *ext_val, int *benefit) |
b4ad7b23 | 6495 | { |
ed5bb68d | 6496 | struct loop_ivs *ivs = LOOP_IVS (loop); |
1ecd860b | 6497 | struct loop_regs *regs = LOOP_REGS (loop); |
b4ad7b23 RS |
6498 | enum machine_mode mode = GET_MODE (x); |
6499 | rtx arg0, arg1; | |
6500 | rtx tem; | |
6501 | ||
6502 | /* If this is not an integer mode, or if we cannot do arithmetic in this | |
6503 | mode, this can't be a giv. */ | |
6504 | if (mode != VOIDmode | |
6505 | && (GET_MODE_CLASS (mode) != MODE_INT | |
5fd8383e | 6506 | || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)) |
45f97e2e | 6507 | return NULL_RTX; |
b4ad7b23 RS |
6508 | |
6509 | switch (GET_CODE (x)) | |
6510 | { | |
6511 | case PLUS: | |
e8cb4873 RH |
6512 | arg0 = simplify_giv_expr (loop, XEXP (x, 0), ext_val, benefit); |
6513 | arg1 = simplify_giv_expr (loop, XEXP (x, 1), ext_val, benefit); | |
b4ad7b23 | 6514 | if (arg0 == 0 || arg1 == 0) |
45f97e2e | 6515 | return NULL_RTX; |
b4ad7b23 RS |
6516 | |
6517 | /* Put constant last, CONST_INT last if both constant. */ | |
6518 | if ((GET_CODE (arg0) == USE | |
6519 | || GET_CODE (arg0) == CONST_INT) | |
45f97e2e RH |
6520 | && ! ((GET_CODE (arg0) == USE |
6521 | && GET_CODE (arg1) == USE) | |
6522 | || GET_CODE (arg1) == CONST_INT)) | |
b4ad7b23 RS |
6523 | tem = arg0, arg0 = arg1, arg1 = tem; |
6524 | ||
6525 | /* Handle addition of zero, then addition of an invariant. */ | |
6526 | if (arg1 == const0_rtx) | |
6527 | return arg0; | |
6528 | else if (GET_CODE (arg1) == CONST_INT || GET_CODE (arg1) == USE) | |
6529 | switch (GET_CODE (arg0)) | |
6530 | { | |
6531 | case CONST_INT: | |
6532 | case USE: | |
45f97e2e | 6533 | /* Adding two invariants must result in an invariant, so enclose |
6b8c9327 | 6534 | addition operation inside a USE and return it. */ |
b4ad7b23 RS |
6535 | if (GET_CODE (arg0) == USE) |
6536 | arg0 = XEXP (arg0, 0); | |
da0af5a5 JL |
6537 | if (GET_CODE (arg1) == USE) |
6538 | arg1 = XEXP (arg1, 0); | |
6539 | ||
45f97e2e RH |
6540 | if (GET_CODE (arg0) == CONST_INT) |
6541 | tem = arg0, arg0 = arg1, arg1 = tem; | |
6542 | if (GET_CODE (arg1) == CONST_INT) | |
6543 | tem = sge_plus_constant (arg0, arg1); | |
da0af5a5 | 6544 | else |
45f97e2e | 6545 | tem = sge_plus (mode, arg0, arg1); |
b4ad7b23 | 6546 | |
45f97e2e RH |
6547 | if (GET_CODE (tem) != CONST_INT) |
6548 | tem = gen_rtx_USE (mode, tem); | |
b4ad7b23 RS |
6549 | return tem; |
6550 | ||
6551 | case REG: | |
6552 | case MULT: | |
6553 | /* biv + invar or mult + invar. Return sum. */ | |
38a448ca | 6554 | return gen_rtx_PLUS (mode, arg0, arg1); |
b4ad7b23 RS |
6555 | |
6556 | case PLUS: | |
6557 | /* (a + invar_1) + invar_2. Associate. */ | |
c5c76735 | 6558 | return |
0534b804 MH |
6559 | simplify_giv_expr (loop, |
6560 | gen_rtx_PLUS (mode, | |
c5c76735 JL |
6561 | XEXP (arg0, 0), |
6562 | gen_rtx_PLUS (mode, | |
6563 | XEXP (arg0, 1), | |
6564 | arg1)), | |
e8cb4873 | 6565 | ext_val, benefit); |
b4ad7b23 RS |
6566 | |
6567 | default: | |
6568 | abort (); | |
6569 | } | |
6570 | ||
6571 | /* Each argument must be either REG, PLUS, or MULT. Convert REG to | |
6572 | MULT to reduce cases. */ | |
6573 | if (GET_CODE (arg0) == REG) | |
38a448ca | 6574 | arg0 = gen_rtx_MULT (mode, arg0, const1_rtx); |
b4ad7b23 | 6575 | if (GET_CODE (arg1) == REG) |
38a448ca | 6576 | arg1 = gen_rtx_MULT (mode, arg1, const1_rtx); |
b4ad7b23 RS |
6577 | |
6578 | /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT. | |
6579 | Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT. | |
6580 | Recurse to associate the second PLUS. */ | |
6581 | if (GET_CODE (arg1) == MULT) | |
6582 | tem = arg0, arg0 = arg1, arg1 = tem; | |
6583 | ||
6584 | if (GET_CODE (arg1) == PLUS) | |
505ddab6 KH |
6585 | return |
6586 | simplify_giv_expr (loop, | |
6587 | gen_rtx_PLUS (mode, | |
6588 | gen_rtx_PLUS (mode, arg0, | |
6589 | XEXP (arg1, 0)), | |
6590 | XEXP (arg1, 1)), | |
6591 | ext_val, benefit); | |
b4ad7b23 RS |
6592 | |
6593 | /* Now must have MULT + MULT. Distribute if same biv, else not giv. */ | |
6594 | if (GET_CODE (arg0) != MULT || GET_CODE (arg1) != MULT) | |
45f97e2e | 6595 | return NULL_RTX; |
b4ad7b23 | 6596 | |
45f97e2e RH |
6597 | if (!rtx_equal_p (arg0, arg1)) |
6598 | return NULL_RTX; | |
b4ad7b23 | 6599 | |
0534b804 MH |
6600 | return simplify_giv_expr (loop, |
6601 | gen_rtx_MULT (mode, | |
38a448ca RH |
6602 | XEXP (arg0, 0), |
6603 | gen_rtx_PLUS (mode, | |
6604 | XEXP (arg0, 1), | |
6605 | XEXP (arg1, 1))), | |
e8cb4873 | 6606 | ext_val, benefit); |
b4ad7b23 RS |
6607 | |
6608 | case MINUS: | |
0f41302f | 6609 | /* Handle "a - b" as "a + b * (-1)". */ |
0534b804 MH |
6610 | return simplify_giv_expr (loop, |
6611 | gen_rtx_PLUS (mode, | |
38a448ca | 6612 | XEXP (x, 0), |
c5c76735 JL |
6613 | gen_rtx_MULT (mode, |
6614 | XEXP (x, 1), | |
38a448ca | 6615 | constm1_rtx)), |
e8cb4873 | 6616 | ext_val, benefit); |
b4ad7b23 RS |
6617 | |
6618 | case MULT: | |
e8cb4873 RH |
6619 | arg0 = simplify_giv_expr (loop, XEXP (x, 0), ext_val, benefit); |
6620 | arg1 = simplify_giv_expr (loop, XEXP (x, 1), ext_val, benefit); | |
b4ad7b23 | 6621 | if (arg0 == 0 || arg1 == 0) |
45f97e2e | 6622 | return NULL_RTX; |
b4ad7b23 RS |
6623 | |
6624 | /* Put constant last, CONST_INT last if both constant. */ | |
6625 | if ((GET_CODE (arg0) == USE || GET_CODE (arg0) == CONST_INT) | |
6626 | && GET_CODE (arg1) != CONST_INT) | |
6627 | tem = arg0, arg0 = arg1, arg1 = tem; | |
6628 | ||
6629 | /* If second argument is not now constant, not giv. */ | |
6630 | if (GET_CODE (arg1) != USE && GET_CODE (arg1) != CONST_INT) | |
45f97e2e | 6631 | return NULL_RTX; |
b4ad7b23 RS |
6632 | |
6633 | /* Handle multiply by 0 or 1. */ | |
6634 | if (arg1 == const0_rtx) | |
6635 | return const0_rtx; | |
6636 | ||
6637 | else if (arg1 == const1_rtx) | |
6638 | return arg0; | |
6639 | ||
6640 | switch (GET_CODE (arg0)) | |
6641 | { | |
6642 | case REG: | |
6643 | /* biv * invar. Done. */ | |
38a448ca | 6644 | return gen_rtx_MULT (mode, arg0, arg1); |
b4ad7b23 RS |
6645 | |
6646 | case CONST_INT: | |
6647 | /* Product of two constants. */ | |
5fd8383e | 6648 | return GEN_INT (INTVAL (arg0) * INTVAL (arg1)); |
b4ad7b23 RS |
6649 | |
6650 | case USE: | |
29aef5ca | 6651 | /* invar * invar is a giv, but attempt to simplify it somehow. */ |
45f97e2e RH |
6652 | if (GET_CODE (arg1) != CONST_INT) |
6653 | return NULL_RTX; | |
6654 | ||
6655 | arg0 = XEXP (arg0, 0); | |
29aef5ca | 6656 | if (GET_CODE (arg0) == MULT) |
45f97e2e | 6657 | { |
29aef5ca JH |
6658 | /* (invar_0 * invar_1) * invar_2. Associate. */ |
6659 | return simplify_giv_expr (loop, | |
6660 | gen_rtx_MULT (mode, | |
6661 | XEXP (arg0, 0), | |
6662 | gen_rtx_MULT (mode, | |
6663 | XEXP (arg0, | |
6664 | 1), | |
6665 | arg1)), | |
e8cb4873 | 6666 | ext_val, benefit); |
45f97e2e | 6667 | } |
2067c116 | 6668 | /* Propagate the MULT expressions to the innermost nodes. */ |
29aef5ca JH |
6669 | else if (GET_CODE (arg0) == PLUS) |
6670 | { | |
6671 | /* (invar_0 + invar_1) * invar_2. Distribute. */ | |
6672 | return simplify_giv_expr (loop, | |
6673 | gen_rtx_PLUS (mode, | |
6674 | gen_rtx_MULT (mode, | |
6675 | XEXP (arg0, | |
6676 | 0), | |
6677 | arg1), | |
6678 | gen_rtx_MULT (mode, | |
6679 | XEXP (arg0, | |
6680 | 1), | |
6681 | arg1)), | |
e8cb4873 | 6682 | ext_val, benefit); |
29aef5ca JH |
6683 | } |
6684 | return gen_rtx_USE (mode, gen_rtx_MULT (mode, arg0, arg1)); | |
b4ad7b23 RS |
6685 | |
6686 | case MULT: | |
6687 | /* (a * invar_1) * invar_2. Associate. */ | |
0534b804 MH |
6688 | return simplify_giv_expr (loop, |
6689 | gen_rtx_MULT (mode, | |
c5c76735 | 6690 | XEXP (arg0, 0), |
38a448ca RH |
6691 | gen_rtx_MULT (mode, |
6692 | XEXP (arg0, 1), | |
6693 | arg1)), | |
e8cb4873 | 6694 | ext_val, benefit); |
b4ad7b23 RS |
6695 | |
6696 | case PLUS: | |
6697 | /* (a + invar_1) * invar_2. Distribute. */ | |
0534b804 MH |
6698 | return simplify_giv_expr (loop, |
6699 | gen_rtx_PLUS (mode, | |
38a448ca RH |
6700 | gen_rtx_MULT (mode, |
6701 | XEXP (arg0, 0), | |
6702 | arg1), | |
6703 | gen_rtx_MULT (mode, | |
6704 | XEXP (arg0, 1), | |
6705 | arg1)), | |
e8cb4873 | 6706 | ext_val, benefit); |
b4ad7b23 RS |
6707 | |
6708 | default: | |
6709 | abort (); | |
6710 | } | |
6711 | ||
6712 | case ASHIFT: | |
b4ad7b23 RS |
6713 | /* Shift by constant is multiply by power of two. */ |
6714 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6715 | return 0; | |
6716 | ||
c5c76735 | 6717 | return |
0534b804 MH |
6718 | simplify_giv_expr (loop, |
6719 | gen_rtx_MULT (mode, | |
c5c76735 JL |
6720 | XEXP (x, 0), |
6721 | GEN_INT ((HOST_WIDE_INT) 1 | |
6722 | << INTVAL (XEXP (x, 1)))), | |
e8cb4873 | 6723 | ext_val, benefit); |
b4ad7b23 RS |
6724 | |
6725 | case NEG: | |
6726 | /* "-a" is "a * (-1)" */ | |
0534b804 MH |
6727 | return simplify_giv_expr (loop, |
6728 | gen_rtx_MULT (mode, XEXP (x, 0), constm1_rtx), | |
e8cb4873 | 6729 | ext_val, benefit); |
b4ad7b23 RS |
6730 | |
6731 | case NOT: | |
6732 | /* "~a" is "-a - 1". Silly, but easy. */ | |
0534b804 MH |
6733 | return simplify_giv_expr (loop, |
6734 | gen_rtx_MINUS (mode, | |
38a448ca RH |
6735 | gen_rtx_NEG (mode, XEXP (x, 0)), |
6736 | const1_rtx), | |
e8cb4873 | 6737 | ext_val, benefit); |
b4ad7b23 RS |
6738 | |
6739 | case USE: | |
6740 | /* Already in proper form for invariant. */ | |
6741 | return x; | |
6742 | ||
e8cb4873 RH |
6743 | case SIGN_EXTEND: |
6744 | case ZERO_EXTEND: | |
6745 | case TRUNCATE: | |
6746 | /* Conditionally recognize extensions of simple IVs. After we've | |
fd5d5b07 | 6747 | computed loop traversal counts and verified the range of the |
e8cb4873 RH |
6748 | source IV, we'll reevaluate this as a GIV. */ |
6749 | if (*ext_val == NULL_RTX) | |
6750 | { | |
6751 | arg0 = simplify_giv_expr (loop, XEXP (x, 0), ext_val, benefit); | |
6752 | if (arg0 && *ext_val == NULL_RTX && GET_CODE (arg0) == REG) | |
6753 | { | |
6754 | *ext_val = gen_rtx_fmt_e (GET_CODE (x), mode, arg0); | |
6755 | return arg0; | |
6756 | } | |
6757 | } | |
6758 | goto do_default; | |
6759 | ||
fd5d5b07 | 6760 | case REG: |
b4ad7b23 RS |
6761 | /* If this is a new register, we can't deal with it. */ |
6762 | if (REGNO (x) >= max_reg_before_loop) | |
6763 | return 0; | |
6764 | ||
6765 | /* Check for biv or giv. */ | |
ed5bb68d | 6766 | switch (REG_IV_TYPE (ivs, REGNO (x))) |
b4ad7b23 RS |
6767 | { |
6768 | case BASIC_INDUCT: | |
6769 | return x; | |
6770 | case GENERAL_INDUCT: | |
6771 | { | |
ed5bb68d | 6772 | struct induction *v = REG_IV_INFO (ivs, REGNO (x)); |
b4ad7b23 RS |
6773 | |
6774 | /* Form expression from giv and add benefit. Ensure this giv | |
6775 | can derive another and subtract any needed adjustment if so. */ | |
630c79be BS |
6776 | |
6777 | /* Increasing the benefit here is risky. The only case in which it | |
6778 | is arguably correct is if this is the only use of V. In other | |
6779 | cases, this will artificially inflate the benefit of the current | |
6780 | giv, and lead to suboptimal code. Thus, it is disabled, since | |
6781 | potentially not reducing an only marginally beneficial giv is | |
6782 | less harmful than reducing many givs that are not really | |
6783 | beneficial. */ | |
6784 | { | |
f1d4ac80 | 6785 | rtx single_use = regs->array[REGNO (x)].single_usage; |
630c79be BS |
6786 | if (single_use && single_use != const0_rtx) |
6787 | *benefit += v->benefit; | |
6788 | } | |
6789 | ||
b4ad7b23 RS |
6790 | if (v->cant_derive) |
6791 | return 0; | |
6792 | ||
c5c76735 JL |
6793 | tem = gen_rtx_PLUS (mode, gen_rtx_MULT (mode, |
6794 | v->src_reg, v->mult_val), | |
6795 | v->add_val); | |
6796 | ||
b4ad7b23 | 6797 | if (v->derive_adjustment) |
38a448ca | 6798 | tem = gen_rtx_MINUS (mode, tem, v->derive_adjustment); |
e8cb4873 RH |
6799 | arg0 = simplify_giv_expr (loop, tem, ext_val, benefit); |
6800 | if (*ext_val) | |
6801 | { | |
affd4f33 | 6802 | if (!v->ext_dependent) |
e8cb4873 RH |
6803 | return arg0; |
6804 | } | |
6805 | else | |
6806 | { | |
affd4f33 | 6807 | *ext_val = v->ext_dependent; |
e8cb4873 RH |
6808 | return arg0; |
6809 | } | |
6810 | return 0; | |
b4ad7b23 | 6811 | } |
e9a25f70 JL |
6812 | |
6813 | default: | |
e8cb4873 | 6814 | do_default: |
45f97e2e RH |
6815 | /* If it isn't an induction variable, and it is invariant, we |
6816 | may be able to simplify things further by looking through | |
6817 | the bits we just moved outside the loop. */ | |
0534b804 | 6818 | if (loop_invariant_p (loop, x) == 1) |
45f97e2e RH |
6819 | { |
6820 | struct movable *m; | |
6ec92010 | 6821 | struct loop_movables *movables = LOOP_MOVABLES (loop); |
45f97e2e | 6822 | |
6ec92010 | 6823 | for (m = movables->head; m; m = m->next) |
45f97e2e RH |
6824 | if (rtx_equal_p (x, m->set_dest)) |
6825 | { | |
6826 | /* Ok, we found a match. Substitute and simplify. */ | |
6827 | ||
e6fcb60d | 6828 | /* If we match another movable, we must use that, as |
45f97e2e RH |
6829 | this one is going away. */ |
6830 | if (m->match) | |
e6fcb60d | 6831 | return simplify_giv_expr (loop, m->match->set_dest, |
e8cb4873 | 6832 | ext_val, benefit); |
45f97e2e | 6833 | |
cc2902df | 6834 | /* If consec is nonzero, this is a member of a group of |
45f97e2e RH |
6835 | instructions that were moved together. We handle this |
6836 | case only to the point of seeking to the last insn and | |
6837 | looking for a REG_EQUAL. Fail if we don't find one. */ | |
6838 | if (m->consec != 0) | |
6839 | { | |
6840 | int i = m->consec; | |
6841 | tem = m->insn; | |
fd5d5b07 KH |
6842 | do |
6843 | { | |
6844 | tem = NEXT_INSN (tem); | |
6845 | } | |
6846 | while (--i > 0); | |
45f97e2e RH |
6847 | |
6848 | tem = find_reg_note (tem, REG_EQUAL, NULL_RTX); | |
6849 | if (tem) | |
6850 | tem = XEXP (tem, 0); | |
6851 | } | |
6852 | else | |
6853 | { | |
e6fcb60d KH |
6854 | tem = single_set (m->insn); |
6855 | if (tem) | |
45f97e2e RH |
6856 | tem = SET_SRC (tem); |
6857 | } | |
6858 | ||
6859 | if (tem) | |
6860 | { | |
6861 | /* What we are most interested in is pointer | |
6862 | arithmetic on invariants -- only take | |
6863 | patterns we may be able to do something with. */ | |
6864 | if (GET_CODE (tem) == PLUS | |
6865 | || GET_CODE (tem) == MULT | |
6866 | || GET_CODE (tem) == ASHIFT | |
6867 | || GET_CODE (tem) == CONST_INT | |
6868 | || GET_CODE (tem) == SYMBOL_REF) | |
6869 | { | |
e8cb4873 RH |
6870 | tem = simplify_giv_expr (loop, tem, ext_val, |
6871 | benefit); | |
45f97e2e RH |
6872 | if (tem) |
6873 | return tem; | |
6874 | } | |
6875 | else if (GET_CODE (tem) == CONST | |
fd5d5b07 KH |
6876 | && GET_CODE (XEXP (tem, 0)) == PLUS |
6877 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == SYMBOL_REF | |
6878 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT) | |
45f97e2e | 6879 | { |
0534b804 | 6880 | tem = simplify_giv_expr (loop, XEXP (tem, 0), |
e8cb4873 | 6881 | ext_val, benefit); |
45f97e2e RH |
6882 | if (tem) |
6883 | return tem; | |
6884 | } | |
6885 | } | |
6886 | break; | |
6887 | } | |
6888 | } | |
e9a25f70 | 6889 | break; |
b4ad7b23 RS |
6890 | } |
6891 | ||
6892 | /* Fall through to general case. */ | |
6893 | default: | |
6894 | /* If invariant, return as USE (unless CONST_INT). | |
6895 | Otherwise, not giv. */ | |
6896 | if (GET_CODE (x) == USE) | |
6897 | x = XEXP (x, 0); | |
6898 | ||
0534b804 | 6899 | if (loop_invariant_p (loop, x) == 1) |
b4ad7b23 RS |
6900 | { |
6901 | if (GET_CODE (x) == CONST_INT) | |
6902 | return x; | |
45f97e2e RH |
6903 | if (GET_CODE (x) == CONST |
6904 | && GET_CODE (XEXP (x, 0)) == PLUS | |
6905 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
6906 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
6907 | x = XEXP (x, 0); | |
6908 | return gen_rtx_USE (mode, x); | |
b4ad7b23 RS |
6909 | } |
6910 | else | |
6911 | return 0; | |
6912 | } | |
6913 | } | |
45f97e2e RH |
6914 | |
6915 | /* This routine folds invariants such that there is only ever one | |
6916 | CONST_INT in the summation. It is only used by simplify_giv_expr. */ | |
6917 | ||
6918 | static rtx | |
0c20a65f | 6919 | sge_plus_constant (rtx x, rtx c) |
45f97e2e RH |
6920 | { |
6921 | if (GET_CODE (x) == CONST_INT) | |
6922 | return GEN_INT (INTVAL (x) + INTVAL (c)); | |
6923 | else if (GET_CODE (x) != PLUS) | |
6924 | return gen_rtx_PLUS (GET_MODE (x), x, c); | |
6925 | else if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6926 | { | |
6927 | return gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
6928 | GEN_INT (INTVAL (XEXP (x, 1)) + INTVAL (c))); | |
6929 | } | |
6930 | else if (GET_CODE (XEXP (x, 0)) == PLUS | |
6931 | || GET_CODE (XEXP (x, 1)) != PLUS) | |
6932 | { | |
6933 | return gen_rtx_PLUS (GET_MODE (x), | |
6934 | sge_plus_constant (XEXP (x, 0), c), XEXP (x, 1)); | |
6935 | } | |
6936 | else | |
6937 | { | |
6938 | return gen_rtx_PLUS (GET_MODE (x), | |
6939 | sge_plus_constant (XEXP (x, 1), c), XEXP (x, 0)); | |
6940 | } | |
6941 | } | |
6942 | ||
6943 | static rtx | |
0c20a65f | 6944 | sge_plus (enum machine_mode mode, rtx x, rtx y) |
45f97e2e RH |
6945 | { |
6946 | while (GET_CODE (y) == PLUS) | |
6947 | { | |
6948 | rtx a = XEXP (y, 0); | |
6949 | if (GET_CODE (a) == CONST_INT) | |
6950 | x = sge_plus_constant (x, a); | |
6951 | else | |
6952 | x = gen_rtx_PLUS (mode, x, a); | |
6953 | y = XEXP (y, 1); | |
6954 | } | |
6955 | if (GET_CODE (y) == CONST_INT) | |
6956 | x = sge_plus_constant (x, y); | |
6957 | else | |
6958 | x = gen_rtx_PLUS (mode, x, y); | |
6959 | return x; | |
6960 | } | |
b4ad7b23 RS |
6961 | \f |
6962 | /* Help detect a giv that is calculated by several consecutive insns; | |
6963 | for example, | |
6964 | giv = biv * M | |
6965 | giv = giv + A | |
6966 | The caller has already identified the first insn P as having a giv as dest; | |
6967 | we check that all other insns that set the same register follow | |
6968 | immediately after P, that they alter nothing else, | |
6969 | and that the result of the last is still a giv. | |
6970 | ||
6971 | The value is 0 if the reg set in P is not really a giv. | |
6972 | Otherwise, the value is the amount gained by eliminating | |
6973 | all the consecutive insns that compute the value. | |
6974 | ||
6975 | FIRST_BENEFIT is the amount gained by eliminating the first insn, P. | |
6976 | SRC_REG is the reg of the biv; DEST_REG is the reg of the giv. | |
6977 | ||
6978 | The coefficients of the ultimate giv value are stored in | |
6979 | *MULT_VAL and *ADD_VAL. */ | |
6980 | ||
6981 | static int | |
0c20a65f AJ |
6982 | consec_sets_giv (const struct loop *loop, int first_benefit, rtx p, |
6983 | rtx src_reg, rtx dest_reg, rtx *add_val, rtx *mult_val, | |
6984 | rtx *ext_val, rtx *last_consec_insn) | |
b4ad7b23 | 6985 | { |
ed5bb68d | 6986 | struct loop_ivs *ivs = LOOP_IVS (loop); |
1ecd860b | 6987 | struct loop_regs *regs = LOOP_REGS (loop); |
b4ad7b23 RS |
6988 | int count; |
6989 | enum rtx_code code; | |
6990 | int benefit; | |
6991 | rtx temp; | |
6992 | rtx set; | |
6993 | ||
6994 | /* Indicate that this is a giv so that we can update the value produced in | |
e6fcb60d | 6995 | each insn of the multi-insn sequence. |
b4ad7b23 RS |
6996 | |
6997 | This induction structure will be used only by the call to | |
6998 | general_induction_var below, so we can allocate it on our stack. | |
6999 | If this is a giv, our caller will replace the induct var entry with | |
7000 | a new induction structure. */ | |
847dde95 BS |
7001 | struct induction *v; |
7002 | ||
7003 | if (REG_IV_TYPE (ivs, REGNO (dest_reg)) != UNKNOWN_INDUCT) | |
7004 | return 0; | |
7005 | ||
703ad42b | 7006 | v = alloca (sizeof (struct induction)); |
b4ad7b23 RS |
7007 | v->src_reg = src_reg; |
7008 | v->mult_val = *mult_val; | |
7009 | v->add_val = *add_val; | |
7010 | v->benefit = first_benefit; | |
7011 | v->cant_derive = 0; | |
7012 | v->derive_adjustment = 0; | |
affd4f33 | 7013 | v->ext_dependent = NULL_RTX; |
b4ad7b23 | 7014 | |
ed5bb68d MH |
7015 | REG_IV_TYPE (ivs, REGNO (dest_reg)) = GENERAL_INDUCT; |
7016 | REG_IV_INFO (ivs, REGNO (dest_reg)) = v; | |
b4ad7b23 | 7017 | |
f1d4ac80 | 7018 | count = regs->array[REGNO (dest_reg)].n_times_set - 1; |
b4ad7b23 RS |
7019 | |
7020 | while (count > 0) | |
7021 | { | |
7022 | p = NEXT_INSN (p); | |
7023 | code = GET_CODE (p); | |
7024 | ||
7025 | /* If libcall, skip to end of call sequence. */ | |
5fd8383e | 7026 | if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
7027 | p = XEXP (temp, 0); |
7028 | ||
7029 | if (code == INSN | |
7030 | && (set = single_set (p)) | |
7031 | && GET_CODE (SET_DEST (set)) == REG | |
7032 | && SET_DEST (set) == dest_reg | |
0534b804 | 7033 | && (general_induction_var (loop, SET_SRC (set), &src_reg, |
e8cb4873 RH |
7034 | add_val, mult_val, ext_val, 0, |
7035 | &benefit, VOIDmode) | |
b4ad7b23 | 7036 | /* Giv created by equivalent expression. */ |
5fd8383e | 7037 | || ((temp = find_reg_note (p, REG_EQUAL, NULL_RTX)) |
0534b804 | 7038 | && general_induction_var (loop, XEXP (temp, 0), &src_reg, |
e8cb4873 RH |
7039 | add_val, mult_val, ext_val, 0, |
7040 | &benefit, VOIDmode))) | |
b4ad7b23 RS |
7041 | && src_reg == v->src_reg) |
7042 | { | |
5fd8383e | 7043 | if (find_reg_note (p, REG_RETVAL, NULL_RTX)) |
b4ad7b23 RS |
7044 | benefit += libcall_benefit (p); |
7045 | ||
7046 | count--; | |
7047 | v->mult_val = *mult_val; | |
7048 | v->add_val = *add_val; | |
630c79be | 7049 | v->benefit += benefit; |
b4ad7b23 RS |
7050 | } |
7051 | else if (code != NOTE) | |
7052 | { | |
7053 | /* Allow insns that set something other than this giv to a | |
7054 | constant. Such insns are needed on machines which cannot | |
7055 | include long constants and should not disqualify a giv. */ | |
7056 | if (code == INSN | |
7057 | && (set = single_set (p)) | |
7058 | && SET_DEST (set) != dest_reg | |
7059 | && CONSTANT_P (SET_SRC (set))) | |
7060 | continue; | |
7061 | ||
ed5bb68d | 7062 | REG_IV_TYPE (ivs, REGNO (dest_reg)) = UNKNOWN_INDUCT; |
b4ad7b23 RS |
7063 | return 0; |
7064 | } | |
7065 | } | |
7066 | ||
847dde95 | 7067 | REG_IV_TYPE (ivs, REGNO (dest_reg)) = UNKNOWN_INDUCT; |
a07516d3 | 7068 | *last_consec_insn = p; |
b4ad7b23 RS |
7069 | return v->benefit; |
7070 | } | |
7071 | \f | |
7072 | /* Return an rtx, if any, that expresses giv G2 as a function of the register | |
7073 | represented by G1. If no such expression can be found, or it is clear that | |
e6fcb60d | 7074 | it cannot possibly be a valid address, 0 is returned. |
b4ad7b23 RS |
7075 | |
7076 | To perform the computation, we note that | |
6b8c9327 | 7077 | G1 = x * v + a and |
45f97e2e | 7078 | G2 = y * v + b |
b4ad7b23 RS |
7079 | where `v' is the biv. |
7080 | ||
45f97e2e RH |
7081 | So G2 = (y/b) * G1 + (b - a*y/x). |
7082 | ||
7083 | Note that MULT = y/x. | |
7084 | ||
7085 | Update: A and B are now allowed to be additive expressions such that | |
7086 | B contains all variables in A. That is, computing B-A will not require | |
7087 | subtracting variables. */ | |
7088 | ||
7089 | static rtx | |
0c20a65f | 7090 | express_from_1 (rtx a, rtx b, rtx mult) |
45f97e2e RH |
7091 | { |
7092 | /* If MULT is zero, then A*MULT is zero, and our expression is B. */ | |
7093 | ||
7094 | if (mult == const0_rtx) | |
7095 | return b; | |
7096 | ||
7097 | /* If MULT is not 1, we cannot handle A with non-constants, since we | |
7098 | would then be required to subtract multiples of the registers in A. | |
7099 | This is theoretically possible, and may even apply to some Fortran | |
7100 | constructs, but it is a lot of work and we do not attempt it here. */ | |
7101 | ||
7102 | if (mult != const1_rtx && GET_CODE (a) != CONST_INT) | |
7103 | return NULL_RTX; | |
7104 | ||
7105 | /* In general these structures are sorted top to bottom (down the PLUS | |
7106 | chain), but not left to right across the PLUS. If B is a higher | |
7107 | order giv than A, we can strip one level and recurse. If A is higher | |
7108 | order, we'll eventually bail out, but won't know that until the end. | |
7109 | If they are the same, we'll strip one level around this loop. */ | |
7110 | ||
7111 | while (GET_CODE (a) == PLUS && GET_CODE (b) == PLUS) | |
7112 | { | |
7113 | rtx ra, rb, oa, ob, tmp; | |
7114 | ||
7115 | ra = XEXP (a, 0), oa = XEXP (a, 1); | |
7116 | if (GET_CODE (ra) == PLUS) | |
e6fcb60d | 7117 | tmp = ra, ra = oa, oa = tmp; |
45f97e2e RH |
7118 | |
7119 | rb = XEXP (b, 0), ob = XEXP (b, 1); | |
7120 | if (GET_CODE (rb) == PLUS) | |
e6fcb60d | 7121 | tmp = rb, rb = ob, ob = tmp; |
45f97e2e RH |
7122 | |
7123 | if (rtx_equal_p (ra, rb)) | |
7124 | /* We matched: remove one reg completely. */ | |
7125 | a = oa, b = ob; | |
7126 | else if (GET_CODE (ob) != PLUS && rtx_equal_p (ra, ob)) | |
7127 | /* An alternate match. */ | |
7128 | a = oa, b = rb; | |
7129 | else if (GET_CODE (oa) != PLUS && rtx_equal_p (oa, rb)) | |
7130 | /* An alternate match. */ | |
7131 | a = ra, b = ob; | |
7132 | else | |
7133 | { | |
fd5d5b07 | 7134 | /* Indicates an extra register in B. Strip one level from B and |
45f97e2e RH |
7135 | recurse, hoping B was the higher order expression. */ |
7136 | ob = express_from_1 (a, ob, mult); | |
7137 | if (ob == NULL_RTX) | |
7138 | return NULL_RTX; | |
7139 | return gen_rtx_PLUS (GET_MODE (b), rb, ob); | |
7140 | } | |
7141 | } | |
7142 | ||
7143 | /* Here we are at the last level of A, go through the cases hoping to | |
7144 | get rid of everything but a constant. */ | |
7145 | ||
7146 | if (GET_CODE (a) == PLUS) | |
7147 | { | |
efe3eb65 | 7148 | rtx ra, oa; |
45f97e2e RH |
7149 | |
7150 | ra = XEXP (a, 0), oa = XEXP (a, 1); | |
7151 | if (rtx_equal_p (oa, b)) | |
7152 | oa = ra; | |
7153 | else if (!rtx_equal_p (ra, b)) | |
7154 | return NULL_RTX; | |
7155 | ||
7156 | if (GET_CODE (oa) != CONST_INT) | |
7157 | return NULL_RTX; | |
7158 | ||
7159 | return GEN_INT (-INTVAL (oa) * INTVAL (mult)); | |
7160 | } | |
7161 | else if (GET_CODE (a) == CONST_INT) | |
7162 | { | |
7163 | return plus_constant (b, -INTVAL (a) * INTVAL (mult)); | |
7164 | } | |
ce7de04c JH |
7165 | else if (CONSTANT_P (a)) |
7166 | { | |
9b3bd424 RH |
7167 | enum machine_mode mode_a = GET_MODE (a); |
7168 | enum machine_mode mode_b = GET_MODE (b); | |
7169 | enum machine_mode mode = mode_b == VOIDmode ? mode_a : mode_b; | |
7170 | return simplify_gen_binary (MINUS, mode, b, a); | |
ce7de04c | 7171 | } |
45f97e2e RH |
7172 | else if (GET_CODE (b) == PLUS) |
7173 | { | |
7174 | if (rtx_equal_p (a, XEXP (b, 0))) | |
7175 | return XEXP (b, 1); | |
7176 | else if (rtx_equal_p (a, XEXP (b, 1))) | |
7177 | return XEXP (b, 0); | |
7178 | else | |
7179 | return NULL_RTX; | |
7180 | } | |
7181 | else if (rtx_equal_p (a, b)) | |
7182 | return const0_rtx; | |
7183 | ||
7184 | return NULL_RTX; | |
7185 | } | |
b4ad7b23 | 7186 | |
4d87f7a7 | 7187 | rtx |
0c20a65f | 7188 | express_from (struct induction *g1, struct induction *g2) |
b4ad7b23 RS |
7189 | { |
7190 | rtx mult, add; | |
7191 | ||
7192 | /* The value that G1 will be multiplied by must be a constant integer. Also, | |
7193 | the only chance we have of getting a valid address is if b*c/a (see above | |
7194 | for notation) is also an integer. */ | |
45f97e2e RH |
7195 | if (GET_CODE (g1->mult_val) == CONST_INT |
7196 | && GET_CODE (g2->mult_val) == CONST_INT) | |
7197 | { | |
7198 | if (g1->mult_val == const0_rtx | |
e6fcb60d KH |
7199 | || INTVAL (g2->mult_val) % INTVAL (g1->mult_val) != 0) |
7200 | return NULL_RTX; | |
45f97e2e RH |
7201 | mult = GEN_INT (INTVAL (g2->mult_val) / INTVAL (g1->mult_val)); |
7202 | } | |
7203 | else if (rtx_equal_p (g1->mult_val, g2->mult_val)) | |
7204 | mult = const1_rtx; | |
7205 | else | |
7206 | { | |
7207 | /* ??? Find out if the one is a multiple of the other? */ | |
7208 | return NULL_RTX; | |
7209 | } | |
b4ad7b23 | 7210 | |
45f97e2e | 7211 | add = express_from_1 (g1->add_val, g2->add_val, mult); |
e0485b85 RH |
7212 | if (add == NULL_RTX) |
7213 | { | |
7214 | /* Failed. If we've got a multiplication factor between G1 and G2, | |
7215 | scale G1's addend and try again. */ | |
7216 | if (INTVAL (mult) > 1) | |
7217 | { | |
7218 | rtx g1_add_val = g1->add_val; | |
7219 | if (GET_CODE (g1_add_val) == MULT | |
7220 | && GET_CODE (XEXP (g1_add_val, 1)) == CONST_INT) | |
7221 | { | |
7222 | HOST_WIDE_INT m; | |
7223 | m = INTVAL (mult) * INTVAL (XEXP (g1_add_val, 1)); | |
7224 | g1_add_val = gen_rtx_MULT (GET_MODE (g1_add_val), | |
7225 | XEXP (g1_add_val, 0), GEN_INT (m)); | |
7226 | } | |
7227 | else | |
7228 | { | |
7229 | g1_add_val = gen_rtx_MULT (GET_MODE (g1_add_val), g1_add_val, | |
7230 | mult); | |
7231 | } | |
7232 | ||
7233 | add = express_from_1 (g1_add_val, g2->add_val, const1_rtx); | |
7234 | } | |
7235 | } | |
45f97e2e RH |
7236 | if (add == NULL_RTX) |
7237 | return NULL_RTX; | |
b4ad7b23 RS |
7238 | |
7239 | /* Form simplified final result. */ | |
7240 | if (mult == const0_rtx) | |
7241 | return add; | |
7242 | else if (mult == const1_rtx) | |
7243 | mult = g1->dest_reg; | |
7244 | else | |
38a448ca | 7245 | mult = gen_rtx_MULT (g2->mode, g1->dest_reg, mult); |
b4ad7b23 RS |
7246 | |
7247 | if (add == const0_rtx) | |
7248 | return mult; | |
7249 | else | |
86219cc7 BS |
7250 | { |
7251 | if (GET_CODE (add) == PLUS | |
7252 | && CONSTANT_P (XEXP (add, 1))) | |
7253 | { | |
7254 | rtx tem = XEXP (add, 1); | |
7255 | mult = gen_rtx_PLUS (g2->mode, mult, XEXP (add, 0)); | |
7256 | add = tem; | |
7257 | } | |
e6fcb60d | 7258 | |
86219cc7 BS |
7259 | return gen_rtx_PLUS (g2->mode, mult, add); |
7260 | } | |
b4ad7b23 | 7261 | } |
b4ad7b23 | 7262 | \f |
da5a44b3 BS |
7263 | /* Return an rtx, if any, that expresses giv G2 as a function of the register |
7264 | represented by G1. This indicates that G2 should be combined with G1 and | |
7265 | that G2 can use (either directly or via an address expression) a register | |
7266 | used to represent G1. */ | |
b4ad7b23 | 7267 | |
45f97e2e | 7268 | static rtx |
0c20a65f | 7269 | combine_givs_p (struct induction *g1, struct induction *g2) |
b4ad7b23 | 7270 | { |
e8cb4873 RH |
7271 | rtx comb, ret; |
7272 | ||
ff7cc307 | 7273 | /* With the introduction of ext dependent givs, we must care for modes. |
e8cb4873 RH |
7274 | G2 must not use a wider mode than G1. */ |
7275 | if (GET_MODE_SIZE (g1->mode) < GET_MODE_SIZE (g2->mode)) | |
7276 | return NULL_RTX; | |
7277 | ||
7278 | ret = comb = express_from (g1, g2); | |
7279 | if (comb == NULL_RTX) | |
7280 | return NULL_RTX; | |
7281 | if (g1->mode != g2->mode) | |
7282 | ret = gen_lowpart (g2->mode, comb); | |
b4ad7b23 | 7283 | |
45f97e2e RH |
7284 | /* If these givs are identical, they can be combined. We use the results |
7285 | of express_from because the addends are not in a canonical form, so | |
7286 | rtx_equal_p is a weaker test. */ | |
3ec2b590 R |
7287 | /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the |
7288 | combination to be the other way round. */ | |
e8cb4873 | 7289 | if (comb == g1->dest_reg |
3ec2b590 | 7290 | && (g1->giv_type == DEST_REG || g2->giv_type == DEST_ADDR)) |
b4ad7b23 | 7291 | { |
e8cb4873 | 7292 | return ret; |
b4ad7b23 RS |
7293 | } |
7294 | ||
b4ad7b23 RS |
7295 | /* If G2 can be expressed as a function of G1 and that function is valid |
7296 | as an address and no more expensive than using a register for G2, | |
7297 | the expression of G2 in terms of G1 can be used. */ | |
e8cb4873 | 7298 | if (ret != NULL_RTX |
45f97e2e | 7299 | && g2->giv_type == DEST_ADDR |
dcefdf67 RH |
7300 | && memory_address_p (GET_MODE (g2->mem), ret)) |
7301 | return ret; | |
b4ad7b23 | 7302 | |
45f97e2e | 7303 | return NULL_RTX; |
b4ad7b23 RS |
7304 | } |
7305 | \f | |
ff7cc307 | 7306 | /* Check each extension dependent giv in this class to see if its |
e8cb4873 RH |
7307 | root biv is safe from wrapping in the interior mode, which would |
7308 | make the giv illegal. */ | |
7309 | ||
7310 | static void | |
03988cac | 7311 | check_ext_dependent_givs (const struct loop *loop, struct iv_class *bl) |
e8cb4873 | 7312 | { |
03988cac | 7313 | struct loop_info *loop_info = LOOP_INFO (loop); |
e8cb4873 RH |
7314 | int ze_ok = 0, se_ok = 0, info_ok = 0; |
7315 | enum machine_mode biv_mode = GET_MODE (bl->biv->src_reg); | |
7316 | HOST_WIDE_INT start_val; | |
616fde53 MH |
7317 | unsigned HOST_WIDE_INT u_end_val = 0; |
7318 | unsigned HOST_WIDE_INT u_start_val = 0; | |
e8cb4873 RH |
7319 | rtx incr = pc_rtx; |
7320 | struct induction *v; | |
7321 | ||
7322 | /* Make sure the iteration data is available. We must have | |
7323 | constants in order to be certain of no overflow. */ | |
e8cb4873 RH |
7324 | if (loop_info->n_iterations > 0 |
7325 | && bl->initial_value | |
7326 | && GET_CODE (bl->initial_value) == CONST_INT | |
7327 | && (incr = biv_total_increment (bl)) | |
7328 | && GET_CODE (incr) == CONST_INT | |
7329 | /* Make sure the host can represent the arithmetic. */ | |
7330 | && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (biv_mode)) | |
7331 | { | |
7332 | unsigned HOST_WIDE_INT abs_incr, total_incr; | |
7333 | HOST_WIDE_INT s_end_val; | |
7334 | int neg_incr; | |
7335 | ||
7336 | info_ok = 1; | |
7337 | start_val = INTVAL (bl->initial_value); | |
7338 | u_start_val = start_val; | |
fd5d5b07 | 7339 | |
e8cb4873 RH |
7340 | neg_incr = 0, abs_incr = INTVAL (incr); |
7341 | if (INTVAL (incr) < 0) | |
7342 | neg_incr = 1, abs_incr = -abs_incr; | |
7343 | total_incr = abs_incr * loop_info->n_iterations; | |
7344 | ||
3d042e77 | 7345 | /* Check for host arithmetic overflow. */ |
e8cb4873 RH |
7346 | if (total_incr / loop_info->n_iterations == abs_incr) |
7347 | { | |
7348 | unsigned HOST_WIDE_INT u_max; | |
7349 | HOST_WIDE_INT s_max; | |
7350 | ||
7351 | u_end_val = start_val + (neg_incr ? -total_incr : total_incr); | |
7352 | s_end_val = u_end_val; | |
7353 | u_max = GET_MODE_MASK (biv_mode); | |
7354 | s_max = u_max >> 1; | |
fd5d5b07 | 7355 | |
e8cb4873 RH |
7356 | /* Check zero extension of biv ok. */ |
7357 | if (start_val >= 0 | |
3d042e77 | 7358 | /* Check for host arithmetic overflow. */ |
e8cb4873 RH |
7359 | && (neg_incr |
7360 | ? u_end_val < u_start_val | |
7361 | : u_end_val > u_start_val) | |
7362 | /* Check for target arithmetic overflow. */ | |
7363 | && (neg_incr | |
7364 | ? 1 /* taken care of with host overflow */ | |
7365 | : u_end_val <= u_max)) | |
7366 | { | |
7367 | ze_ok = 1; | |
7368 | } | |
fd5d5b07 | 7369 | |
e8cb4873 RH |
7370 | /* Check sign extension of biv ok. */ |
7371 | /* ??? While it is true that overflow with signed and pointer | |
7372 | arithmetic is undefined, I fear too many programmers don't | |
7373 | keep this fact in mind -- myself included on occasion. | |
7374 | So leave alone with the signed overflow optimizations. */ | |
7375 | if (start_val >= -s_max - 1 | |
3d042e77 | 7376 | /* Check for host arithmetic overflow. */ |
e8cb4873 RH |
7377 | && (neg_incr |
7378 | ? s_end_val < start_val | |
7379 | : s_end_val > start_val) | |
7380 | /* Check for target arithmetic overflow. */ | |
7381 | && (neg_incr | |
7382 | ? s_end_val >= -s_max - 1 | |
7383 | : s_end_val <= s_max)) | |
7384 | { | |
7385 | se_ok = 1; | |
7386 | } | |
7387 | } | |
7388 | } | |
7389 | ||
03988cac UW |
7390 | /* If we know the BIV is compared at run-time against an |
7391 | invariant value, and the increment is +/- 1, we may also | |
7392 | be able to prove that the BIV cannot overflow. */ | |
7393 | else if (bl->biv->src_reg == loop_info->iteration_var | |
7394 | && loop_info->comparison_value | |
7395 | && loop_invariant_p (loop, loop_info->comparison_value) | |
7396 | && (incr = biv_total_increment (bl)) | |
7397 | && GET_CODE (incr) == CONST_INT) | |
7398 | { | |
7399 | /* If the increment is +1, and the exit test is a <, | |
7400 | the BIV cannot overflow. (For <=, we have the | |
7401 | problematic case that the comparison value might | |
7402 | be the maximum value of the range.) */ | |
7403 | if (INTVAL (incr) == 1) | |
7404 | { | |
7405 | if (loop_info->comparison_code == LT) | |
7406 | se_ok = ze_ok = 1; | |
7407 | else if (loop_info->comparison_code == LTU) | |
7408 | ze_ok = 1; | |
7409 | } | |
7410 | ||
7411 | /* Likewise for increment -1 and exit test >. */ | |
7412 | if (INTVAL (incr) == -1) | |
7413 | { | |
7414 | if (loop_info->comparison_code == GT) | |
7415 | se_ok = ze_ok = 1; | |
7416 | else if (loop_info->comparison_code == GTU) | |
7417 | ze_ok = 1; | |
7418 | } | |
7419 | } | |
7420 | ||
e8cb4873 RH |
7421 | /* Invalidate givs that fail the tests. */ |
7422 | for (v = bl->giv; v; v = v->next_iv) | |
affd4f33 | 7423 | if (v->ext_dependent) |
e8cb4873 | 7424 | { |
affd4f33 | 7425 | enum rtx_code code = GET_CODE (v->ext_dependent); |
e8cb4873 RH |
7426 | int ok = 0; |
7427 | ||
7428 | switch (code) | |
7429 | { | |
7430 | case SIGN_EXTEND: | |
7431 | ok = se_ok; | |
7432 | break; | |
7433 | case ZERO_EXTEND: | |
7434 | ok = ze_ok; | |
7435 | break; | |
7436 | ||
7437 | case TRUNCATE: | |
7438 | /* We don't know whether this value is being used as either | |
7439 | signed or unsigned, so to safely truncate we must satisfy | |
fd5d5b07 | 7440 | both. The initial check here verifies the BIV itself; |
e8cb4873 | 7441 | once that is successful we may check its range wrt the |
03988cac UW |
7442 | derived GIV. This works only if we were able to determine |
7443 | constant start and end values above. */ | |
7444 | if (se_ok && ze_ok && info_ok) | |
e8cb4873 | 7445 | { |
affd4f33 | 7446 | enum machine_mode outer_mode = GET_MODE (v->ext_dependent); |
e8cb4873 RH |
7447 | unsigned HOST_WIDE_INT max = GET_MODE_MASK (outer_mode) >> 1; |
7448 | ||
7449 | /* We know from the above that both endpoints are nonnegative, | |
7450 | and that there is no wrapping. Verify that both endpoints | |
7451 | are within the (signed) range of the outer mode. */ | |
7452 | if (u_start_val <= max && u_end_val <= max) | |
7453 | ok = 1; | |
7454 | } | |
7455 | break; | |
7456 | ||
7457 | default: | |
7458 | abort (); | |
7459 | } | |
7460 | ||
7461 | if (ok) | |
7462 | { | |
7463 | if (loop_dump_stream) | |
7464 | { | |
fd5d5b07 | 7465 | fprintf (loop_dump_stream, |
ff7cc307 | 7466 | "Verified ext dependent giv at %d of reg %d\n", |
fd5d5b07 | 7467 | INSN_UID (v->insn), bl->regno); |
e8cb4873 RH |
7468 | } |
7469 | } | |
7470 | else | |
7471 | { | |
7472 | if (loop_dump_stream) | |
7473 | { | |
7474 | const char *why; | |
7475 | ||
7476 | if (info_ok) | |
7477 | why = "biv iteration values overflowed"; | |
7478 | else | |
7479 | { | |
7480 | if (incr == pc_rtx) | |
7481 | incr = biv_total_increment (bl); | |
7482 | if (incr == const1_rtx) | |
7483 | why = "biv iteration info incomplete; incr by 1"; | |
7484 | else | |
7485 | why = "biv iteration info incomplete"; | |
7486 | } | |
7487 | ||
fd5d5b07 | 7488 | fprintf (loop_dump_stream, |
ff7cc307 | 7489 | "Failed ext dependent giv at %d, %s\n", |
fd5d5b07 | 7490 | INSN_UID (v->insn), why); |
e8cb4873 RH |
7491 | } |
7492 | v->ignore = 1; | |
97ebd24c | 7493 | bl->all_reduced = 0; |
e8cb4873 RH |
7494 | } |
7495 | } | |
7496 | } | |
7497 | ||
7498 | /* Generate a version of VALUE in a mode appropriate for initializing V. */ | |
7499 | ||
7500 | rtx | |
0c20a65f | 7501 | extend_value_for_giv (struct induction *v, rtx value) |
e8cb4873 | 7502 | { |
affd4f33 | 7503 | rtx ext_dep = v->ext_dependent; |
e8cb4873 RH |
7504 | |
7505 | if (! ext_dep) | |
7506 | return value; | |
7507 | ||
affd4f33 | 7508 | /* Recall that check_ext_dependent_givs verified that the known bounds |
e8cb4873 RH |
7509 | of a biv did not overflow or wrap with respect to the extension for |
7510 | the giv. Therefore, constants need no additional adjustment. */ | |
7511 | if (CONSTANT_P (value) && GET_MODE (value) == VOIDmode) | |
7512 | return value; | |
7513 | ||
7514 | /* Otherwise, we must adjust the value to compensate for the | |
7515 | differing modes of the biv and the giv. */ | |
7516 | return gen_rtx_fmt_e (GET_CODE (ext_dep), GET_MODE (ext_dep), value); | |
7517 | } | |
7518 | \f | |
45f97e2e RH |
7519 | struct combine_givs_stats |
7520 | { | |
7521 | int giv_number; | |
7522 | int total_benefit; | |
7523 | }; | |
7524 | ||
7525 | static int | |
0c20a65f | 7526 | cmp_combine_givs_stats (const void *xp, const void *yp) |
45f97e2e | 7527 | { |
f428f252 KG |
7528 | const struct combine_givs_stats * const x = |
7529 | (const struct combine_givs_stats *) xp; | |
7530 | const struct combine_givs_stats * const y = | |
7531 | (const struct combine_givs_stats *) yp; | |
45f97e2e RH |
7532 | int d; |
7533 | d = y->total_benefit - x->total_benefit; | |
7534 | /* Stabilize the sort. */ | |
7535 | if (!d) | |
7536 | d = x->giv_number - y->giv_number; | |
7537 | return d; | |
7538 | } | |
7539 | ||
b4ad7b23 RS |
7540 | /* Check all pairs of givs for iv_class BL and see if any can be combined with |
7541 | any other. If so, point SAME to the giv combined with and set NEW_REG to | |
7542 | be an expression (in terms of the other giv's DEST_REG) equivalent to the | |
7543 | giv. Also, update BENEFIT and related fields for cost/benefit analysis. */ | |
7544 | ||
7545 | static void | |
0c20a65f | 7546 | combine_givs (struct loop_regs *regs, struct iv_class *bl) |
b4ad7b23 | 7547 | { |
ba12c883 RH |
7548 | /* Additional benefit to add for being combined multiple times. */ |
7549 | const int extra_benefit = 3; | |
7550 | ||
29a82058 | 7551 | struct induction *g1, *g2, **giv_array; |
45f97e2e RH |
7552 | int i, j, k, giv_count; |
7553 | struct combine_givs_stats *stats; | |
7554 | rtx *can_combine; | |
b4ad7b23 | 7555 | |
7027f90a JW |
7556 | /* Count givs, because bl->giv_count is incorrect here. */ |
7557 | giv_count = 0; | |
b4ad7b23 | 7558 | for (g1 = bl->giv; g1; g1 = g1->next_iv) |
45f97e2e RH |
7559 | if (!g1->ignore) |
7560 | giv_count++; | |
7027f90a | 7561 | |
703ad42b | 7562 | giv_array = alloca (giv_count * sizeof (struct induction *)); |
7027f90a JW |
7563 | i = 0; |
7564 | for (g1 = bl->giv; g1; g1 = g1->next_iv) | |
45f97e2e RH |
7565 | if (!g1->ignore) |
7566 | giv_array[i++] = g1; | |
7027f90a | 7567 | |
703ad42b KG |
7568 | stats = xcalloc (giv_count, sizeof (*stats)); |
7569 | can_combine = xcalloc (giv_count, giv_count * sizeof (rtx)); | |
7027f90a JW |
7570 | |
7571 | for (i = 0; i < giv_count; i++) | |
7572 | { | |
45f97e2e | 7573 | int this_benefit; |
ba12c883 | 7574 | rtx single_use; |
45f97e2e | 7575 | |
7027f90a | 7576 | g1 = giv_array[i]; |
ba12c883 RH |
7577 | stats[i].giv_number = i; |
7578 | ||
7579 | /* If a DEST_REG GIV is used only once, do not allow it to combine | |
7580 | with anything, for in doing so we will gain nothing that cannot | |
7581 | be had by simply letting the GIV with which we would have combined | |
e6fcb60d | 7582 | to be reduced on its own. The losage shows up in particular with |
ba12c883 RH |
7583 | DEST_ADDR targets on hosts with reg+reg addressing, though it can |
7584 | be seen elsewhere as well. */ | |
7585 | if (g1->giv_type == DEST_REG | |
f1d4ac80 | 7586 | && (single_use = regs->array[REGNO (g1->dest_reg)].single_usage) |
ba12c883 RH |
7587 | && single_use != const0_rtx) |
7588 | continue; | |
45f97e2e RH |
7589 | |
7590 | this_benefit = g1->benefit; | |
7591 | /* Add an additional weight for zero addends. */ | |
7592 | if (g1->no_const_addval) | |
7593 | this_benefit += 1; | |
ba12c883 | 7594 | |
45f97e2e RH |
7595 | for (j = 0; j < giv_count; j++) |
7596 | { | |
7597 | rtx this_combine; | |
7598 | ||
7599 | g2 = giv_array[j]; | |
7600 | if (g1 != g2 | |
7601 | && (this_combine = combine_givs_p (g1, g2)) != NULL_RTX) | |
7602 | { | |
e6fcb60d | 7603 | can_combine[i * giv_count + j] = this_combine; |
ba12c883 | 7604 | this_benefit += g2->benefit + extra_benefit; |
45f97e2e RH |
7605 | } |
7606 | } | |
45f97e2e RH |
7607 | stats[i].total_benefit = this_benefit; |
7608 | } | |
7609 | ||
7610 | /* Iterate, combining until we can't. */ | |
7611 | restart: | |
e6fcb60d | 7612 | qsort (stats, giv_count, sizeof (*stats), cmp_combine_givs_stats); |
45f97e2e RH |
7613 | |
7614 | if (loop_dump_stream) | |
7615 | { | |
7616 | fprintf (loop_dump_stream, "Sorted combine statistics:\n"); | |
7617 | for (k = 0; k < giv_count; k++) | |
7618 | { | |
7619 | g1 = giv_array[stats[k].giv_number]; | |
7620 | if (!g1->combined_with && !g1->same) | |
e6fcb60d | 7621 | fprintf (loop_dump_stream, " {%d, %d}", |
45f97e2e RH |
7622 | INSN_UID (giv_array[stats[k].giv_number]->insn), |
7623 | stats[k].total_benefit); | |
7624 | } | |
7625 | putc ('\n', loop_dump_stream); | |
7626 | } | |
7627 | ||
7628 | for (k = 0; k < giv_count; k++) | |
7629 | { | |
7630 | int g1_add_benefit = 0; | |
7631 | ||
7632 | i = stats[k].giv_number; | |
7633 | g1 = giv_array[i]; | |
7634 | ||
7635 | /* If it has already been combined, skip. */ | |
7636 | if (g1->combined_with || g1->same) | |
7637 | continue; | |
7638 | ||
7639 | for (j = 0; j < giv_count; j++) | |
7640 | { | |
7641 | g2 = giv_array[j]; | |
e6fcb60d | 7642 | if (g1 != g2 && can_combine[i * giv_count + j] |
45f97e2e RH |
7643 | /* If it has already been combined, skip. */ |
7644 | && ! g2->same && ! g2->combined_with) | |
7645 | { | |
7646 | int l; | |
7647 | ||
e6fcb60d | 7648 | g2->new_reg = can_combine[i * giv_count + j]; |
45f97e2e | 7649 | g2->same = g1; |
5bb08c84 JH |
7650 | /* For destination, we now may replace by mem expression instead |
7651 | of register. This changes the costs considerably, so add the | |
7652 | compensation. */ | |
7653 | if (g2->giv_type == DEST_ADDR) | |
7654 | g2->benefit = (g2->benefit + reg_address_cost | |
7655 | - address_cost (g2->new_reg, | |
7656 | GET_MODE (g2->mem))); | |
3ec2b590 | 7657 | g1->combined_with++; |
45f97e2e RH |
7658 | g1->lifetime += g2->lifetime; |
7659 | ||
ba12c883 | 7660 | g1_add_benefit += g2->benefit; |
45f97e2e RH |
7661 | |
7662 | /* ??? The new final_[bg]iv_value code does a much better job | |
7663 | of finding replaceable giv's, and hence this code may no | |
7664 | longer be necessary. */ | |
7665 | if (! g2->replaceable && REG_USERVAR_P (g2->dest_reg)) | |
7666 | g1_add_benefit -= copy_cost; | |
e6fcb60d | 7667 | |
45f97e2e RH |
7668 | /* To help optimize the next set of combinations, remove |
7669 | this giv from the benefits of other potential mates. */ | |
7670 | for (l = 0; l < giv_count; ++l) | |
7671 | { | |
7672 | int m = stats[l].giv_number; | |
e6fcb60d | 7673 | if (can_combine[m * giv_count + j]) |
ba12c883 | 7674 | stats[l].total_benefit -= g2->benefit + extra_benefit; |
45f97e2e RH |
7675 | } |
7676 | ||
7677 | if (loop_dump_stream) | |
7678 | fprintf (loop_dump_stream, | |
630c79be BS |
7679 | "giv at %d combined with giv at %d; new benefit %d + %d, lifetime %d\n", |
7680 | INSN_UID (g2->insn), INSN_UID (g1->insn), | |
7681 | g1->benefit, g1_add_benefit, g1->lifetime); | |
45f97e2e RH |
7682 | } |
7683 | } | |
7684 | ||
7685 | /* To help optimize the next set of combinations, remove | |
7686 | this giv from the benefits of other potential mates. */ | |
7687 | if (g1->combined_with) | |
7688 | { | |
7689 | for (j = 0; j < giv_count; ++j) | |
7690 | { | |
7691 | int m = stats[j].giv_number; | |
e6fcb60d | 7692 | if (can_combine[m * giv_count + i]) |
ba12c883 | 7693 | stats[j].total_benefit -= g1->benefit + extra_benefit; |
45f97e2e RH |
7694 | } |
7695 | ||
7696 | g1->benefit += g1_add_benefit; | |
7697 | ||
7698 | /* We've finished with this giv, and everything it touched. | |
e6fcb60d | 7699 | Restart the combination so that proper weights for the |
45f97e2e RH |
7700 | rest of the givs are properly taken into account. */ |
7701 | /* ??? Ideally we would compact the arrays at this point, so | |
7702 | as to not cover old ground. But sanely compacting | |
7703 | can_combine is tricky. */ | |
7704 | goto restart; | |
7705 | } | |
7027f90a | 7706 | } |
67289ea6 MM |
7707 | |
7708 | /* Clean up. */ | |
7709 | free (stats); | |
7710 | free (can_combine); | |
b4ad7b23 RS |
7711 | } |
7712 | \f | |
0c20a65f AJ |
7713 | /* Generate sequence for REG = B * M + A. B is the initial value of |
7714 | the basic induction variable, M a multiplicative constant, A an | |
7715 | additive constant and REG the destination register. */ | |
b4ad7b23 | 7716 | |
96a45535 | 7717 | static rtx |
0c20a65f | 7718 | gen_add_mult (rtx b, rtx m, rtx a, rtx reg) |
b4ad7b23 RS |
7719 | { |
7720 | rtx seq; | |
7721 | rtx result; | |
7722 | ||
b4ad7b23 | 7723 | start_sequence (); |
96a45535 | 7724 | /* Use unsigned arithmetic. */ |
91ce572a | 7725 | result = expand_mult_add (b, reg, m, a, GET_MODE (reg), 1); |
b4ad7b23 RS |
7726 | if (reg != result) |
7727 | emit_move_insn (reg, result); | |
2f937369 | 7728 | seq = get_insns (); |
b4ad7b23 RS |
7729 | end_sequence (); |
7730 | ||
96a45535 MH |
7731 | return seq; |
7732 | } | |
7733 | ||
7734 | ||
7735 | /* Update registers created in insn sequence SEQ. */ | |
9ae8ffe7 | 7736 | |
96a45535 | 7737 | static void |
0c20a65f | 7738 | loop_regs_update (const struct loop *loop ATTRIBUTE_UNUSED, rtx seq) |
96a45535 | 7739 | { |
2f937369 DM |
7740 | rtx insn; |
7741 | ||
96a45535 | 7742 | /* Update register info for alias analysis. */ |
00116a7b | 7743 | |
10ef35a9 JW |
7744 | insn = seq; |
7745 | while (insn != NULL_RTX) | |
00116a7b | 7746 | { |
10ef35a9 | 7747 | rtx set = single_set (insn); |
2f937369 | 7748 | |
10ef35a9 JW |
7749 | if (set && GET_CODE (SET_DEST (set)) == REG) |
7750 | record_base_value (REGNO (SET_DEST (set)), SET_SRC (set), 0); | |
2f937369 | 7751 | |
10ef35a9 | 7752 | insn = NEXT_INSN (insn); |
00116a7b | 7753 | } |
b4ad7b23 | 7754 | } |
630c79be | 7755 | |
96a45535 | 7756 | |
0c20a65f AJ |
7757 | /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B |
7758 | is the initial value of the basic induction variable, M a | |
7759 | multiplicative constant, A an additive constant and REG the | |
7760 | destination register. */ | |
96a45535 MH |
7761 | |
7762 | void | |
0c20a65f AJ |
7763 | loop_iv_add_mult_emit_before (const struct loop *loop, rtx b, rtx m, rtx a, |
7764 | rtx reg, basic_block before_bb, rtx before_insn) | |
96a45535 MH |
7765 | { |
7766 | rtx seq; | |
7767 | ||
7768 | if (! before_insn) | |
7769 | { | |
7770 | loop_iv_add_mult_hoist (loop, b, m, a, reg); | |
7771 | return; | |
7772 | } | |
7773 | ||
7774 | /* Use copy_rtx to prevent unexpected sharing of these rtx. */ | |
2e279a9b | 7775 | seq = gen_add_mult (copy_rtx (b), copy_rtx (m), copy_rtx (a), reg); |
96a45535 MH |
7776 | |
7777 | /* Increase the lifetime of any invariants moved further in code. */ | |
7778 | update_reg_last_use (a, before_insn); | |
7779 | update_reg_last_use (b, before_insn); | |
7780 | update_reg_last_use (m, before_insn); | |
7781 | ||
96a45535 | 7782 | /* It is possible that the expansion created lots of new registers. |
ac8354b1 JW |
7783 | Iterate over the sequence we just created and record them all. We |
7784 | must do this before inserting the sequence. */ | |
96a45535 | 7785 | loop_regs_update (loop, seq); |
ac8354b1 JW |
7786 | |
7787 | loop_insn_emit_before (loop, before_bb, before_insn, seq); | |
96a45535 MH |
7788 | } |
7789 | ||
7790 | ||
0c20a65f AJ |
7791 | /* Emit insns in loop pre-header to set REG = B * M + A. B is the |
7792 | initial value of the basic induction variable, M a multiplicative | |
7793 | constant, A an additive constant and REG the destination | |
7794 | register. */ | |
96a45535 MH |
7795 | |
7796 | void | |
0c20a65f | 7797 | loop_iv_add_mult_sink (const struct loop *loop, rtx b, rtx m, rtx a, rtx reg) |
96a45535 MH |
7798 | { |
7799 | rtx seq; | |
7800 | ||
7801 | /* Use copy_rtx to prevent unexpected sharing of these rtx. */ | |
2e279a9b | 7802 | seq = gen_add_mult (copy_rtx (b), copy_rtx (m), copy_rtx (a), reg); |
96a45535 MH |
7803 | |
7804 | /* Increase the lifetime of any invariants moved further in code. | |
7805 | ???? Is this really necessary? */ | |
7806 | update_reg_last_use (a, loop->sink); | |
7807 | update_reg_last_use (b, loop->sink); | |
7808 | update_reg_last_use (m, loop->sink); | |
7809 | ||
96a45535 | 7810 | /* It is possible that the expansion created lots of new registers. |
ac8354b1 JW |
7811 | Iterate over the sequence we just created and record them all. We |
7812 | must do this before inserting the sequence. */ | |
96a45535 | 7813 | loop_regs_update (loop, seq); |
ac8354b1 JW |
7814 | |
7815 | loop_insn_sink (loop, seq); | |
96a45535 MH |
7816 | } |
7817 | ||
7818 | ||
0c20a65f AJ |
7819 | /* Emit insns after loop to set REG = B * M + A. B is the initial |
7820 | value of the basic induction variable, M a multiplicative constant, | |
7821 | A an additive constant and REG the destination register. */ | |
96a45535 MH |
7822 | |
7823 | void | |
0c20a65f | 7824 | loop_iv_add_mult_hoist (const struct loop *loop, rtx b, rtx m, rtx a, rtx reg) |
96a45535 MH |
7825 | { |
7826 | rtx seq; | |
7827 | ||
7828 | /* Use copy_rtx to prevent unexpected sharing of these rtx. */ | |
2e279a9b | 7829 | seq = gen_add_mult (copy_rtx (b), copy_rtx (m), copy_rtx (a), reg); |
96a45535 | 7830 | |
96a45535 | 7831 | /* It is possible that the expansion created lots of new registers. |
ac8354b1 JW |
7832 | Iterate over the sequence we just created and record them all. We |
7833 | must do this before inserting the sequence. */ | |
96a45535 | 7834 | loop_regs_update (loop, seq); |
ac8354b1 JW |
7835 | |
7836 | loop_insn_hoist (loop, seq); | |
96a45535 MH |
7837 | } |
7838 | ||
7839 | ||
7840 | ||
7841 | /* Similar to gen_add_mult, but compute cost rather than generating | |
7842 | sequence. */ | |
7843 | ||
630c79be | 7844 | static int |
0c20a65f | 7845 | iv_add_mult_cost (rtx b, rtx m, rtx a, rtx reg) |
630c79be BS |
7846 | { |
7847 | int cost = 0; | |
7848 | rtx last, result; | |
7849 | ||
7850 | start_sequence (); | |
96a45535 | 7851 | result = expand_mult_add (b, reg, m, a, GET_MODE (reg), 1); |
630c79be BS |
7852 | if (reg != result) |
7853 | emit_move_insn (reg, result); | |
7854 | last = get_last_insn (); | |
7855 | while (last) | |
7856 | { | |
7857 | rtx t = single_set (last); | |
7858 | if (t) | |
7859 | cost += rtx_cost (SET_SRC (t), SET); | |
7860 | last = PREV_INSN (last); | |
7861 | } | |
7862 | end_sequence (); | |
7863 | return cost; | |
7864 | } | |
b4ad7b23 RS |
7865 | \f |
7866 | /* Test whether A * B can be computed without | |
2f937369 DM |
7867 | an actual multiply insn. Value is 1 if so. |
7868 | ||
7869 | ??? This function stinks because it generates a ton of wasted RTL | |
7870 | ??? and as a result fragments GC memory to no end. There are other | |
7871 | ??? places in the compiler which are invoked a lot and do the same | |
7872 | ??? thing, generate wasted RTL just to see if something is possible. */ | |
b4ad7b23 RS |
7873 | |
7874 | static int | |
0c20a65f | 7875 | product_cheap_p (rtx a, rtx b) |
b4ad7b23 | 7876 | { |
b4ad7b23 | 7877 | rtx tmp; |
2f937369 | 7878 | int win, n_insns; |
b4ad7b23 | 7879 | |
0f41302f | 7880 | /* If only one is constant, make it B. */ |
b4ad7b23 RS |
7881 | if (GET_CODE (a) == CONST_INT) |
7882 | tmp = a, a = b, b = tmp; | |
7883 | ||
7884 | /* If first constant, both constant, so don't need multiply. */ | |
7885 | if (GET_CODE (a) == CONST_INT) | |
7886 | return 1; | |
7887 | ||
7888 | /* If second not constant, neither is constant, so would need multiply. */ | |
7889 | if (GET_CODE (b) != CONST_INT) | |
7890 | return 0; | |
7891 | ||
7892 | /* One operand is constant, so might not need multiply insn. Generate the | |
7893 | code for the multiply and see if a call or multiply, or long sequence | |
7894 | of insns is generated. */ | |
7895 | ||
b4ad7b23 | 7896 | start_sequence (); |
91ce572a | 7897 | expand_mult (GET_MODE (a), a, b, NULL_RTX, 1); |
2f937369 | 7898 | tmp = get_insns (); |
b4ad7b23 RS |
7899 | end_sequence (); |
7900 | ||
2f937369 DM |
7901 | win = 1; |
7902 | if (INSN_P (tmp)) | |
b4ad7b23 | 7903 | { |
2f937369 DM |
7904 | n_insns = 0; |
7905 | while (tmp != NULL_RTX) | |
7906 | { | |
7907 | rtx next = NEXT_INSN (tmp); | |
7908 | ||
7909 | if (++n_insns > 3 | |
7910 | || GET_CODE (tmp) != INSN | |
7911 | || (GET_CODE (PATTERN (tmp)) == SET | |
7912 | && GET_CODE (SET_SRC (PATTERN (tmp))) == MULT) | |
7913 | || (GET_CODE (PATTERN (tmp)) == PARALLEL | |
7914 | && GET_CODE (XVECEXP (PATTERN (tmp), 0, 0)) == SET | |
7915 | && GET_CODE (SET_SRC (XVECEXP (PATTERN (tmp), 0, 0))) == MULT)) | |
7916 | { | |
7917 | win = 0; | |
7918 | break; | |
7919 | } | |
7920 | ||
7921 | tmp = next; | |
7922 | } | |
b4ad7b23 RS |
7923 | } |
7924 | else if (GET_CODE (tmp) == SET | |
7925 | && GET_CODE (SET_SRC (tmp)) == MULT) | |
7926 | win = 0; | |
7927 | else if (GET_CODE (tmp) == PARALLEL | |
7928 | && GET_CODE (XVECEXP (tmp, 0, 0)) == SET | |
7929 | && GET_CODE (SET_SRC (XVECEXP (tmp, 0, 0))) == MULT) | |
7930 | win = 0; | |
7931 | ||
b4ad7b23 RS |
7932 | return win; |
7933 | } | |
7934 | \f | |
7935 | /* Check to see if loop can be terminated by a "decrement and branch until | |
7936 | zero" instruction. If so, add a REG_NONNEG note to the branch insn if so. | |
7937 | Also try reversing an increment loop to a decrement loop | |
7938 | to see if the optimization can be performed. | |
7939 | Value is nonzero if optimization was performed. */ | |
7940 | ||
7941 | /* This is useful even if the architecture doesn't have such an insn, | |
7942 | because it might change a loops which increments from 0 to n to a loop | |
7943 | which decrements from n to 0. A loop that decrements to zero is usually | |
7944 | faster than one that increments from zero. */ | |
7945 | ||
7946 | /* ??? This could be rewritten to use some of the loop unrolling procedures, | |
7947 | such as approx_final_value, biv_total_increment, loop_iterations, and | |
7948 | final_[bg]iv_value. */ | |
7949 | ||
7950 | static int | |
0c20a65f | 7951 | check_dbra_loop (struct loop *loop, int insn_count) |
b4ad7b23 | 7952 | { |
1ecd860b MH |
7953 | struct loop_info *loop_info = LOOP_INFO (loop); |
7954 | struct loop_regs *regs = LOOP_REGS (loop); | |
ed5bb68d | 7955 | struct loop_ivs *ivs = LOOP_IVS (loop); |
b4ad7b23 RS |
7956 | struct iv_class *bl; |
7957 | rtx reg; | |
7958 | rtx jump_label; | |
7959 | rtx final_value; | |
7960 | rtx start_value; | |
b4ad7b23 RS |
7961 | rtx new_add_val; |
7962 | rtx comparison; | |
7963 | rtx before_comparison; | |
7964 | rtx p; | |
0628fde6 JW |
7965 | rtx jump; |
7966 | rtx first_compare; | |
7967 | int compare_and_branch; | |
a2be868f MH |
7968 | rtx loop_start = loop->start; |
7969 | rtx loop_end = loop->end; | |
b4ad7b23 RS |
7970 | |
7971 | /* If last insn is a conditional branch, and the insn before tests a | |
7972 | register value, try to optimize it. Otherwise, we can't do anything. */ | |
7973 | ||
0628fde6 | 7974 | jump = PREV_INSN (loop_end); |
0534b804 | 7975 | comparison = get_condition_for_loop (loop, jump); |
b4ad7b23 RS |
7976 | if (comparison == 0) |
7977 | return 0; | |
7f1c097d JH |
7978 | if (!onlyjump_p (jump)) |
7979 | return 0; | |
b4ad7b23 | 7980 | |
0628fde6 JW |
7981 | /* Try to compute whether the compare/branch at the loop end is one or |
7982 | two instructions. */ | |
ec6ec6aa | 7983 | get_condition (jump, &first_compare, false); |
0628fde6 JW |
7984 | if (first_compare == jump) |
7985 | compare_and_branch = 1; | |
7986 | else if (first_compare == prev_nonnote_insn (jump)) | |
7987 | compare_and_branch = 2; | |
7988 | else | |
7989 | return 0; | |
7990 | ||
947851b2 CC |
7991 | { |
7992 | /* If more than one condition is present to control the loop, then | |
5d8fcdcb | 7993 | do not proceed, as this function does not know how to rewrite |
7905cfef JL |
7994 | loop tests with more than one condition. |
7995 | ||
7996 | Look backwards from the first insn in the last comparison | |
7997 | sequence and see if we've got another comparison sequence. */ | |
947851b2 CC |
7998 | |
7999 | rtx jump1; | |
7905cfef | 8000 | if ((jump1 = prev_nonnote_insn (first_compare)) != loop->cont) |
c12c6a56 | 8001 | if (GET_CODE (jump1) == JUMP_INSN) |
fd5d5b07 | 8002 | return 0; |
947851b2 CC |
8003 | } |
8004 | ||
b4ad7b23 RS |
8005 | /* Check all of the bivs to see if the compare uses one of them. |
8006 | Skip biv's set more than once because we can't guarantee that | |
8007 | it will be zero on the last iteration. Also skip if the biv is | |
8008 | used between its update and the test insn. */ | |
8009 | ||
14be28e5 | 8010 | for (bl = ivs->list; bl; bl = bl->next) |
b4ad7b23 RS |
8011 | { |
8012 | if (bl->biv_count == 1 | |
6979065c | 8013 | && ! bl->biv->maybe_multiple |
b4ad7b23 RS |
8014 | && bl->biv->dest_reg == XEXP (comparison, 0) |
8015 | && ! reg_used_between_p (regno_reg_rtx[bl->regno], bl->biv->insn, | |
0628fde6 | 8016 | first_compare)) |
b4ad7b23 RS |
8017 | break; |
8018 | } | |
8019 | ||
ce4191ee RS |
8020 | /* Try swapping the comparison to identify a suitable biv. */ |
8021 | if (!bl) | |
8022 | for (bl = ivs->list; bl; bl = bl->next) | |
8023 | if (bl->biv_count == 1 | |
8024 | && ! bl->biv->maybe_multiple | |
8025 | && bl->biv->dest_reg == XEXP (comparison, 1) | |
8026 | && ! reg_used_between_p (regno_reg_rtx[bl->regno], bl->biv->insn, | |
8027 | first_compare)) | |
8028 | { | |
8029 | comparison = gen_rtx_fmt_ee (swap_condition (GET_CODE (comparison)), | |
8030 | VOIDmode, | |
8031 | XEXP (comparison, 1), | |
8032 | XEXP (comparison, 0)); | |
8033 | break; | |
8034 | } | |
8035 | ||
b4ad7b23 RS |
8036 | if (! bl) |
8037 | return 0; | |
8038 | ||
8039 | /* Look for the case where the basic induction variable is always | |
8040 | nonnegative, and equals zero on the last iteration. | |
8041 | In this case, add a reg_note REG_NONNEG, which allows the | |
8042 | m68k DBRA instruction to be used. */ | |
8043 | ||
87d9741e | 8044 | if (((GET_CODE (comparison) == GT && XEXP (comparison, 1) == constm1_rtx) |
b4ad7b23 RS |
8045 | || (GET_CODE (comparison) == NE && XEXP (comparison, 1) == const0_rtx)) |
8046 | && GET_CODE (bl->biv->add_val) == CONST_INT | |
8047 | && INTVAL (bl->biv->add_val) < 0) | |
8048 | { | |
8049 | /* Initial value must be greater than 0, | |
8050 | init_val % -dec_value == 0 to ensure that it equals zero on | |
8051 | the last iteration */ | |
8052 | ||
8053 | if (GET_CODE (bl->initial_value) == CONST_INT | |
8054 | && INTVAL (bl->initial_value) > 0 | |
db3cf6fb MS |
8055 | && (INTVAL (bl->initial_value) |
8056 | % (-INTVAL (bl->biv->add_val))) == 0) | |
b4ad7b23 RS |
8057 | { |
8058 | /* register always nonnegative, add REG_NOTE to branch */ | |
65b98a02 JW |
8059 | if (! find_reg_note (jump, REG_NONNEG, NULL_RTX)) |
8060 | REG_NOTES (jump) | |
8061 | = gen_rtx_EXPR_LIST (REG_NONNEG, bl->biv->dest_reg, | |
8062 | REG_NOTES (jump)); | |
b4ad7b23 RS |
8063 | bl->nonneg = 1; |
8064 | ||
8065 | return 1; | |
8066 | } | |
8067 | ||
8068 | /* If the decrement is 1 and the value was tested as >= 0 before | |
8069 | the loop, then we can safely optimize. */ | |
8070 | for (p = loop_start; p; p = PREV_INSN (p)) | |
8071 | { | |
8072 | if (GET_CODE (p) == CODE_LABEL) | |
8073 | break; | |
8074 | if (GET_CODE (p) != JUMP_INSN) | |
8075 | continue; | |
8076 | ||
0534b804 | 8077 | before_comparison = get_condition_for_loop (loop, p); |
b4ad7b23 RS |
8078 | if (before_comparison |
8079 | && XEXP (before_comparison, 0) == bl->biv->dest_reg | |
edeac5de AK |
8080 | && (GET_CODE (before_comparison) == LT |
8081 | || GET_CODE (before_comparison) == LTU) | |
b4ad7b23 RS |
8082 | && XEXP (before_comparison, 1) == const0_rtx |
8083 | && ! reg_set_between_p (bl->biv->dest_reg, p, loop_start) | |
8084 | && INTVAL (bl->biv->add_val) == -1) | |
8085 | { | |
65b98a02 JW |
8086 | if (! find_reg_note (jump, REG_NONNEG, NULL_RTX)) |
8087 | REG_NOTES (jump) | |
8088 | = gen_rtx_EXPR_LIST (REG_NONNEG, bl->biv->dest_reg, | |
8089 | REG_NOTES (jump)); | |
b4ad7b23 RS |
8090 | bl->nonneg = 1; |
8091 | ||
8092 | return 1; | |
8093 | } | |
8094 | } | |
8095 | } | |
ef178af3 ZW |
8096 | else if (GET_CODE (bl->biv->add_val) == CONST_INT |
8097 | && INTVAL (bl->biv->add_val) > 0) | |
b4ad7b23 RS |
8098 | { |
8099 | /* Try to change inc to dec, so can apply above optimization. */ | |
8100 | /* Can do this if: | |
8101 | all registers modified are induction variables or invariant, | |
8102 | all memory references have non-overlapping addresses | |
8103 | (obviously true if only one write) | |
8104 | allow 2 insns for the compare/jump at the end of the loop. */ | |
45cc060e JW |
8105 | /* Also, we must avoid any instructions which use both the reversed |
8106 | biv and another biv. Such instructions will fail if the loop is | |
8107 | reversed. We meet this condition by requiring that either | |
8108 | no_use_except_counting is true, or else that there is only | |
8109 | one biv. */ | |
b4ad7b23 RS |
8110 | int num_nonfixed_reads = 0; |
8111 | /* 1 if the iteration var is used only to count iterations. */ | |
8112 | int no_use_except_counting = 0; | |
b418c26e JW |
8113 | /* 1 if the loop has no memory store, or it has a single memory store |
8114 | which is reversible. */ | |
8115 | int reversible_mem_store = 1; | |
b4ad7b23 | 8116 | |
2b701ab7 RH |
8117 | if (bl->giv_count == 0 |
8118 | && !loop->exit_count | |
8119 | && !loop_info->has_multiple_exit_targets) | |
b4ad7b23 RS |
8120 | { |
8121 | rtx bivreg = regno_reg_rtx[bl->regno]; | |
c7b30677 | 8122 | struct iv_class *blt; |
b4ad7b23 RS |
8123 | |
8124 | /* If there are no givs for this biv, and the only exit is the | |
38e01259 | 8125 | fall through at the end of the loop, then |
b4ad7b23 RS |
8126 | see if perhaps there are no uses except to count. */ |
8127 | no_use_except_counting = 1; | |
8128 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) | |
2c3c49de | 8129 | if (INSN_P (p)) |
b4ad7b23 RS |
8130 | { |
8131 | rtx set = single_set (p); | |
8132 | ||
8133 | if (set && GET_CODE (SET_DEST (set)) == REG | |
8134 | && REGNO (SET_DEST (set)) == bl->regno) | |
8135 | /* An insn that sets the biv is okay. */ | |
8136 | ; | |
3ec6c6ee NS |
8137 | else if (!reg_mentioned_p (bivreg, PATTERN (p))) |
8138 | /* An insn that doesn't mention the biv is okay. */ | |
8139 | ; | |
8140 | else if (p == prev_nonnote_insn (prev_nonnote_insn (loop_end)) | |
8141 | || p == prev_nonnote_insn (loop_end)) | |
59487769 JL |
8142 | { |
8143 | /* If either of these insns uses the biv and sets a pseudo | |
8144 | that has more than one usage, then the biv has uses | |
8145 | other than counting since it's used to derive a value | |
8146 | that is used more than one time. */ | |
84832317 | 8147 | note_stores (PATTERN (p), note_set_pseudo_multiple_uses, |
1ecd860b MH |
8148 | regs); |
8149 | if (regs->multiple_uses) | |
59487769 JL |
8150 | { |
8151 | no_use_except_counting = 0; | |
8152 | break; | |
8153 | } | |
8154 | } | |
3ec6c6ee | 8155 | else |
b4ad7b23 RS |
8156 | { |
8157 | no_use_except_counting = 0; | |
8158 | break; | |
8159 | } | |
8160 | } | |
c7b30677 | 8161 | |
b7fe373b RH |
8162 | /* A biv has uses besides counting if it is used to set |
8163 | another biv. */ | |
c7b30677 | 8164 | for (blt = ivs->list; blt; blt = blt->next) |
b7fe373b RH |
8165 | if (blt->init_set |
8166 | && reg_mentioned_p (bivreg, SET_SRC (blt->init_set))) | |
c7b30677 FS |
8167 | { |
8168 | no_use_except_counting = 0; | |
8169 | break; | |
8170 | } | |
b4ad7b23 RS |
8171 | } |
8172 | ||
c48ba252 | 8173 | if (no_use_except_counting) |
e6fcb60d KH |
8174 | /* No need to worry about MEMs. */ |
8175 | ; | |
afa1738b | 8176 | else if (loop_info->num_mem_sets <= 1) |
c48ba252 R |
8177 | { |
8178 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) | |
2c3c49de | 8179 | if (INSN_P (p)) |
0534b804 | 8180 | num_nonfixed_reads += count_nonfixed_reads (loop, PATTERN (p)); |
c48ba252 R |
8181 | |
8182 | /* If the loop has a single store, and the destination address is | |
8183 | invariant, then we can't reverse the loop, because this address | |
8184 | might then have the wrong value at loop exit. | |
8185 | This would work if the source was invariant also, however, in that | |
8186 | case, the insn should have been moved out of the loop. */ | |
8187 | ||
afa1738b | 8188 | if (loop_info->num_mem_sets == 1) |
2d4fde68 R |
8189 | { |
8190 | struct induction *v; | |
8191 | ||
28680540 MM |
8192 | /* If we could prove that each of the memory locations |
8193 | written to was different, then we could reverse the | |
8194 | store -- but we don't presently have any way of | |
8195 | knowing that. */ | |
8196 | reversible_mem_store = 0; | |
2d4fde68 R |
8197 | |
8198 | /* If the store depends on a register that is set after the | |
8199 | store, it depends on the initial value, and is thus not | |
8200 | reversible. */ | |
8201 | for (v = bl->giv; reversible_mem_store && v; v = v->next_iv) | |
8202 | { | |
8203 | if (v->giv_type == DEST_REG | |
8204 | && reg_mentioned_p (v->dest_reg, | |
afa1738b | 8205 | PATTERN (loop_info->first_loop_store_insn)) |
fd5d5b07 | 8206 | && loop_insn_first_p (loop_info->first_loop_store_insn, |
afa1738b | 8207 | v->insn)) |
2d4fde68 R |
8208 | reversible_mem_store = 0; |
8209 | } | |
8210 | } | |
c48ba252 R |
8211 | } |
8212 | else | |
8213 | return 0; | |
b418c26e | 8214 | |
b4ad7b23 RS |
8215 | /* This code only acts for innermost loops. Also it simplifies |
8216 | the memory address check by only reversing loops with | |
8217 | zero or one memory access. | |
8218 | Two memory accesses could involve parts of the same array, | |
c48ba252 R |
8219 | and that can't be reversed. |
8220 | If the biv is used only for counting, than we don't need to worry | |
8221 | about all these things. */ | |
8222 | ||
8223 | if ((num_nonfixed_reads <= 1 | |
576d0b54 | 8224 | && ! loop_info->has_nonconst_call |
62e6ca55 | 8225 | && ! loop_info->has_prefetch |
3c748bb6 | 8226 | && ! loop_info->has_volatile |
c48ba252 | 8227 | && reversible_mem_store |
afa1738b | 8228 | && (bl->giv_count + bl->biv_count + loop_info->num_mem_sets |
28680540 | 8229 | + num_unmoved_movables (loop) + compare_and_branch == insn_count) |
14be28e5 | 8230 | && (bl == ivs->list && bl->next == 0)) |
62e6ca55 | 8231 | || (no_use_except_counting && ! loop_info->has_prefetch)) |
b4ad7b23 | 8232 | { |
b4ad7b23 RS |
8233 | rtx tem; |
8234 | ||
8235 | /* Loop can be reversed. */ | |
8236 | if (loop_dump_stream) | |
8237 | fprintf (loop_dump_stream, "Can reverse loop\n"); | |
8238 | ||
8239 | /* Now check other conditions: | |
e9a25f70 | 8240 | |
956d6950 | 8241 | The increment must be a constant, as must the initial value, |
e6fcb60d | 8242 | and the comparison code must be LT. |
b4ad7b23 RS |
8243 | |
8244 | This test can probably be improved since +/- 1 in the constant | |
8245 | can be obtained by changing LT to LE and vice versa; this is | |
8246 | confusing. */ | |
8247 | ||
e9a25f70 | 8248 | if (comparison |
c48ba252 R |
8249 | /* for constants, LE gets turned into LT */ |
8250 | && (GET_CODE (comparison) == LT | |
8251 | || (GET_CODE (comparison) == LE | |
edeac5de AK |
8252 | && no_use_except_counting) |
8253 | || GET_CODE (comparison) == LTU)) | |
b4ad7b23 | 8254 | { |
f428f252 | 8255 | HOST_WIDE_INT add_val, add_adjust, comparison_val = 0; |
c48ba252 R |
8256 | rtx initial_value, comparison_value; |
8257 | int nonneg = 0; | |
8258 | enum rtx_code cmp_code; | |
8259 | int comparison_const_width; | |
8260 | unsigned HOST_WIDE_INT comparison_sign_mask; | |
e9a25f70 JL |
8261 | |
8262 | add_val = INTVAL (bl->biv->add_val); | |
c48ba252 | 8263 | comparison_value = XEXP (comparison, 1); |
2c74fb2b AS |
8264 | if (GET_MODE (comparison_value) == VOIDmode) |
8265 | comparison_const_width | |
8266 | = GET_MODE_BITSIZE (GET_MODE (XEXP (comparison, 0))); | |
8267 | else | |
8268 | comparison_const_width | |
8269 | = GET_MODE_BITSIZE (GET_MODE (comparison_value)); | |
c48ba252 R |
8270 | if (comparison_const_width > HOST_BITS_PER_WIDE_INT) |
8271 | comparison_const_width = HOST_BITS_PER_WIDE_INT; | |
8272 | comparison_sign_mask | |
e6fcb60d | 8273 | = (unsigned HOST_WIDE_INT) 1 << (comparison_const_width - 1); |
c48ba252 | 8274 | |
3aa94dc8 JL |
8275 | /* If the comparison value is not a loop invariant, then we |
8276 | can not reverse this loop. | |
8277 | ||
8278 | ??? If the insns which initialize the comparison value as | |
8279 | a whole compute an invariant result, then we could move | |
8280 | them out of the loop and proceed with loop reversal. */ | |
0534b804 | 8281 | if (! loop_invariant_p (loop, comparison_value)) |
3aa94dc8 JL |
8282 | return 0; |
8283 | ||
c48ba252 R |
8284 | if (GET_CODE (comparison_value) == CONST_INT) |
8285 | comparison_val = INTVAL (comparison_value); | |
e9a25f70 | 8286 | initial_value = bl->initial_value; |
e6fcb60d KH |
8287 | |
8288 | /* Normalize the initial value if it is an integer and | |
a8decb2c JL |
8289 | has no other use except as a counter. This will allow |
8290 | a few more loops to be reversed. */ | |
8291 | if (no_use_except_counting | |
c48ba252 | 8292 | && GET_CODE (comparison_value) == CONST_INT |
a8decb2c | 8293 | && GET_CODE (initial_value) == CONST_INT) |
e9a25f70 JL |
8294 | { |
8295 | comparison_val = comparison_val - INTVAL (bl->initial_value); | |
c48ba252 R |
8296 | /* The code below requires comparison_val to be a multiple |
8297 | of add_val in order to do the loop reversal, so | |
8298 | round up comparison_val to a multiple of add_val. | |
8299 | Since comparison_value is constant, we know that the | |
8300 | current comparison code is LT. */ | |
8301 | comparison_val = comparison_val + add_val - 1; | |
8302 | comparison_val | |
8303 | -= (unsigned HOST_WIDE_INT) comparison_val % add_val; | |
8304 | /* We postpone overflow checks for COMPARISON_VAL here; | |
8305 | even if there is an overflow, we might still be able to | |
8306 | reverse the loop, if converting the loop exit test to | |
8307 | NE is possible. */ | |
8308 | initial_value = const0_rtx; | |
e9a25f70 JL |
8309 | } |
8310 | ||
c48ba252 R |
8311 | /* First check if we can do a vanilla loop reversal. */ |
8312 | if (initial_value == const0_rtx | |
3c748bb6 MH |
8313 | /* If we have a decrement_and_branch_on_count, |
8314 | prefer the NE test, since this will allow that | |
8315 | instruction to be generated. Note that we must | |
8316 | use a vanilla loop reversal if the biv is used to | |
8317 | calculate a giv or has a non-counting use. */ | |
8318 | #if ! defined (HAVE_decrement_and_branch_until_zero) \ | |
8319 | && defined (HAVE_decrement_and_branch_on_count) | |
a2be868f | 8320 | && (! (add_val == 1 && loop->vtop |
c5cbf81e JL |
8321 | && (bl->biv_count == 0 |
8322 | || no_use_except_counting))) | |
c48ba252 R |
8323 | #endif |
8324 | && GET_CODE (comparison_value) == CONST_INT | |
8325 | /* Now do postponed overflow checks on COMPARISON_VAL. */ | |
8326 | && ! (((comparison_val - add_val) ^ INTVAL (comparison_value)) | |
8327 | & comparison_sign_mask)) | |
8328 | { | |
8329 | /* Register will always be nonnegative, with value | |
8330 | 0 on last iteration */ | |
8331 | add_adjust = add_val; | |
8332 | nonneg = 1; | |
8333 | cmp_code = GE; | |
8334 | } | |
a2be868f | 8335 | else if (add_val == 1 && loop->vtop |
c5cbf81e JL |
8336 | && (bl->biv_count == 0 |
8337 | || no_use_except_counting)) | |
c48ba252 R |
8338 | { |
8339 | add_adjust = 0; | |
8340 | cmp_code = NE; | |
8341 | } | |
8342 | else | |
8343 | return 0; | |
8344 | ||
8345 | if (GET_CODE (comparison) == LE) | |
8346 | add_adjust -= add_val; | |
8347 | ||
e9a25f70 JL |
8348 | /* If the initial value is not zero, or if the comparison |
8349 | value is not an exact multiple of the increment, then we | |
8350 | can not reverse this loop. */ | |
c48ba252 R |
8351 | if (initial_value == const0_rtx |
8352 | && GET_CODE (comparison_value) == CONST_INT) | |
8353 | { | |
8354 | if (((unsigned HOST_WIDE_INT) comparison_val % add_val) != 0) | |
8355 | return 0; | |
8356 | } | |
8357 | else | |
8358 | { | |
8359 | if (! no_use_except_counting || add_val != 1) | |
8360 | return 0; | |
8361 | } | |
e9a25f70 | 8362 | |
8ed69d09 R |
8363 | final_value = comparison_value; |
8364 | ||
e9a25f70 JL |
8365 | /* Reset these in case we normalized the initial value |
8366 | and comparison value above. */ | |
8ed69d09 R |
8367 | if (GET_CODE (comparison_value) == CONST_INT |
8368 | && GET_CODE (initial_value) == CONST_INT) | |
8369 | { | |
8370 | comparison_value = GEN_INT (comparison_val); | |
8371 | final_value | |
8372 | = GEN_INT (comparison_val + INTVAL (bl->initial_value)); | |
8373 | } | |
e9a25f70 | 8374 | bl->initial_value = initial_value; |
b4ad7b23 RS |
8375 | |
8376 | /* Save some info needed to produce the new insns. */ | |
8377 | reg = bl->biv->dest_reg; | |
353df065 | 8378 | jump_label = condjump_label (PREV_INSN (loop_end)); |
fd5d5b07 | 8379 | new_add_val = GEN_INT (-INTVAL (bl->biv->add_val)); |
b4ad7b23 | 8380 | |
c48ba252 R |
8381 | /* Set start_value; if this is not a CONST_INT, we need |
8382 | to generate a SUB. | |
8383 | Initialize biv to start_value before loop start. | |
b4ad7b23 RS |
8384 | The old initializing insn will be deleted as a |
8385 | dead store by flow.c. */ | |
c48ba252 R |
8386 | if (initial_value == const0_rtx |
8387 | && GET_CODE (comparison_value) == CONST_INT) | |
8388 | { | |
8389 | start_value = GEN_INT (comparison_val - add_adjust); | |
804a718a | 8390 | loop_insn_hoist (loop, gen_move_insn (reg, start_value)); |
c48ba252 R |
8391 | } |
8392 | else if (GET_CODE (initial_value) == CONST_INT) | |
8393 | { | |
c48ba252 | 8394 | enum machine_mode mode = GET_MODE (reg); |
ef89d648 ZW |
8395 | rtx offset = GEN_INT (-INTVAL (initial_value) - add_adjust); |
8396 | rtx add_insn = gen_add3_insn (reg, comparison_value, offset); | |
8397 | ||
8398 | if (add_insn == 0) | |
c48ba252 | 8399 | return 0; |
ef89d648 | 8400 | |
c48ba252 R |
8401 | start_value |
8402 | = gen_rtx_PLUS (mode, comparison_value, offset); | |
ef89d648 | 8403 | loop_insn_hoist (loop, add_insn); |
c48ba252 R |
8404 | if (GET_CODE (comparison) == LE) |
8405 | final_value = gen_rtx_PLUS (mode, comparison_value, | |
8406 | GEN_INT (add_val)); | |
8407 | } | |
8408 | else if (! add_adjust) | |
8409 | { | |
8410 | enum machine_mode mode = GET_MODE (reg); | |
ef89d648 ZW |
8411 | rtx sub_insn = gen_sub3_insn (reg, comparison_value, |
8412 | initial_value); | |
8413 | ||
8414 | if (sub_insn == 0) | |
c48ba252 R |
8415 | return 0; |
8416 | start_value | |
8417 | = gen_rtx_MINUS (mode, comparison_value, initial_value); | |
ef89d648 | 8418 | loop_insn_hoist (loop, sub_insn); |
c48ba252 R |
8419 | } |
8420 | else | |
8421 | /* We could handle the other cases too, but it'll be | |
8422 | better to have a testcase first. */ | |
8423 | return 0; | |
b4ad7b23 | 8424 | |
225a7e3d JL |
8425 | /* We may not have a single insn which can increment a reg, so |
8426 | create a sequence to hold all the insns from expand_inc. */ | |
8427 | start_sequence (); | |
8428 | expand_inc (reg, new_add_val); | |
2f937369 | 8429 | tem = get_insns (); |
e6fcb60d | 8430 | end_sequence (); |
225a7e3d | 8431 | |
86e21212 | 8432 | p = loop_insn_emit_before (loop, 0, bl->biv->insn, tem); |
49ce134f | 8433 | delete_insn (bl->biv->insn); |
e6fcb60d | 8434 | |
b4ad7b23 RS |
8435 | /* Update biv info to reflect its new status. */ |
8436 | bl->biv->insn = p; | |
8437 | bl->initial_value = start_value; | |
8438 | bl->biv->add_val = new_add_val; | |
8439 | ||
5629b16c | 8440 | /* Update loop info. */ |
eb6a3bc0 MH |
8441 | loop_info->initial_value = reg; |
8442 | loop_info->initial_equiv_value = reg; | |
5629b16c MH |
8443 | loop_info->final_value = const0_rtx; |
8444 | loop_info->final_equiv_value = const0_rtx; | |
8445 | loop_info->comparison_value = const0_rtx; | |
8446 | loop_info->comparison_code = cmp_code; | |
8447 | loop_info->increment = new_add_val; | |
8448 | ||
b4ad7b23 RS |
8449 | /* Inc LABEL_NUSES so that delete_insn will |
8450 | not delete the label. */ | |
fd5d5b07 | 8451 | LABEL_NUSES (XEXP (jump_label, 0))++; |
b4ad7b23 RS |
8452 | |
8453 | /* Emit an insn after the end of the loop to set the biv's | |
8454 | proper exit value if it is used anywhere outside the loop. */ | |
0628fde6 | 8455 | if ((REGNO_LAST_UID (bl->regno) != INSN_UID (first_compare)) |
b4ad7b23 | 8456 | || ! bl->init_insn |
b1f21e0a | 8457 | || REGNO_FIRST_UID (bl->regno) != INSN_UID (bl->init_insn)) |
74411039 | 8458 | loop_insn_sink (loop, gen_load_of_final_value (reg, final_value)); |
b4ad7b23 RS |
8459 | |
8460 | /* Delete compare/branch at end of loop. */ | |
53c17031 | 8461 | delete_related_insns (PREV_INSN (loop_end)); |
0628fde6 | 8462 | if (compare_and_branch == 2) |
53c17031 | 8463 | delete_related_insns (first_compare); |
b4ad7b23 RS |
8464 | |
8465 | /* Add new compare/branch insn at end of loop. */ | |
8466 | start_sequence (); | |
362cc3d4 | 8467 | emit_cmp_and_jump_insns (reg, const0_rtx, cmp_code, NULL_RTX, |
a06ef755 | 8468 | GET_MODE (reg), 0, |
362cc3d4 | 8469 | XEXP (jump_label, 0)); |
2f937369 | 8470 | tem = get_insns (); |
b4ad7b23 RS |
8471 | end_sequence (); |
8472 | emit_jump_insn_before (tem, loop_end); | |
8473 | ||
a7060368 MH |
8474 | for (tem = PREV_INSN (loop_end); |
8475 | tem && GET_CODE (tem) != JUMP_INSN; | |
8476 | tem = PREV_INSN (tem)) | |
8477 | ; | |
8478 | ||
8479 | if (tem) | |
8480 | JUMP_LABEL (tem) = XEXP (jump_label, 0); | |
8481 | ||
c48ba252 | 8482 | if (nonneg) |
b4ad7b23 | 8483 | { |
c48ba252 R |
8484 | if (tem) |
8485 | { | |
c48ba252 R |
8486 | /* Increment of LABEL_NUSES done above. */ |
8487 | /* Register is now always nonnegative, | |
8488 | so add REG_NONNEG note to the branch. */ | |
65b98a02 | 8489 | REG_NOTES (tem) = gen_rtx_EXPR_LIST (REG_NONNEG, reg, |
c48ba252 R |
8490 | REG_NOTES (tem)); |
8491 | } | |
8492 | bl->nonneg = 1; | |
b4ad7b23 RS |
8493 | } |
8494 | ||
22b452e7 BS |
8495 | /* No insn may reference both the reversed and another biv or it |
8496 | will fail (see comment near the top of the loop reversal | |
8497 | code). | |
8498 | Earlier on, we have verified that the biv has no use except | |
8499 | counting, or it is the only biv in this function. | |
8500 | However, the code that computes no_use_except_counting does | |
8501 | not verify reg notes. It's possible to have an insn that | |
8502 | references another biv, and has a REG_EQUAL note with an | |
8503 | expression based on the reversed biv. To avoid this case, | |
8504 | remove all REG_EQUAL notes based on the reversed biv | |
8505 | here. */ | |
8506 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) | |
2c3c49de | 8507 | if (INSN_P (p)) |
22b452e7 BS |
8508 | { |
8509 | rtx *pnote; | |
8510 | rtx set = single_set (p); | |
8511 | /* If this is a set of a GIV based on the reversed biv, any | |
8512 | REG_EQUAL notes should still be correct. */ | |
8513 | if (! set | |
8514 | || GET_CODE (SET_DEST (set)) != REG | |
14be28e5 | 8515 | || (size_t) REGNO (SET_DEST (set)) >= ivs->n_regs |
ed5bb68d MH |
8516 | || REG_IV_TYPE (ivs, REGNO (SET_DEST (set))) != GENERAL_INDUCT |
8517 | || REG_IV_INFO (ivs, REGNO (SET_DEST (set)))->src_reg != bl->biv->src_reg) | |
22b452e7 BS |
8518 | for (pnote = ®_NOTES (p); *pnote;) |
8519 | { | |
8520 | if (REG_NOTE_KIND (*pnote) == REG_EQUAL | |
8521 | && reg_mentioned_p (regno_reg_rtx[bl->regno], | |
8522 | XEXP (*pnote, 0))) | |
8523 | *pnote = XEXP (*pnote, 1); | |
8524 | else | |
8525 | pnote = &XEXP (*pnote, 1); | |
8526 | } | |
8527 | } | |
8528 | ||
b4ad7b23 RS |
8529 | /* Mark that this biv has been reversed. Each giv which depends |
8530 | on this biv, and which is also live past the end of the loop | |
8531 | will have to be fixed up. */ | |
8532 | ||
8533 | bl->reversed = 1; | |
8534 | ||
8535 | if (loop_dump_stream) | |
b50cb11f MH |
8536 | { |
8537 | fprintf (loop_dump_stream, "Reversed loop"); | |
8538 | if (bl->nonneg) | |
8539 | fprintf (loop_dump_stream, " and added reg_nonneg\n"); | |
8540 | else | |
8541 | fprintf (loop_dump_stream, "\n"); | |
8542 | } | |
b4ad7b23 RS |
8543 | |
8544 | return 1; | |
8545 | } | |
8546 | } | |
8547 | } | |
8548 | ||
8549 | return 0; | |
8550 | } | |
8551 | \f | |
8552 | /* Verify whether the biv BL appears to be eliminable, | |
8553 | based on the insns in the loop that refer to it. | |
b4ad7b23 | 8554 | |
cc2902df | 8555 | If ELIMINATE_P is nonzero, actually do the elimination. |
b4ad7b23 RS |
8556 | |
8557 | THRESHOLD and INSN_COUNT are from loop_optimize and are used to | |
8558 | determine whether invariant insns should be placed inside or at the | |
8559 | start of the loop. */ | |
8560 | ||
8561 | static int | |
0c20a65f AJ |
8562 | maybe_eliminate_biv (const struct loop *loop, struct iv_class *bl, |
8563 | int eliminate_p, int threshold, int insn_count) | |
b4ad7b23 | 8564 | { |
ed5bb68d | 8565 | struct loop_ivs *ivs = LOOP_IVS (loop); |
b4ad7b23 | 8566 | rtx reg = bl->biv->dest_reg; |
bd5a664e | 8567 | rtx p; |
b4ad7b23 RS |
8568 | |
8569 | /* Scan all insns in the loop, stopping if we find one that uses the | |
8570 | biv in a way that we cannot eliminate. */ | |
8571 | ||
96a45535 | 8572 | for (p = loop->start; p != loop->end; p = NEXT_INSN (p)) |
b4ad7b23 RS |
8573 | { |
8574 | enum rtx_code code = GET_CODE (p); | |
96a45535 MH |
8575 | basic_block where_bb = 0; |
8576 | rtx where_insn = threshold >= insn_count ? 0 : p; | |
039baf9e | 8577 | rtx note; |
b4ad7b23 | 8578 | |
fdb1833a R |
8579 | /* If this is a libcall that sets a giv, skip ahead to its end. */ |
8580 | if (GET_RTX_CLASS (code) == 'i') | |
8581 | { | |
039baf9e | 8582 | note = find_reg_note (p, REG_LIBCALL, NULL_RTX); |
fdb1833a R |
8583 | |
8584 | if (note) | |
8585 | { | |
8586 | rtx last = XEXP (note, 0); | |
8587 | rtx set = single_set (last); | |
8588 | ||
8589 | if (set && GET_CODE (SET_DEST (set)) == REG) | |
8590 | { | |
770ae6cc | 8591 | unsigned int regno = REGNO (SET_DEST (set)); |
fdb1833a | 8592 | |
86fee241 | 8593 | if (regno < ivs->n_regs |
ed5bb68d MH |
8594 | && REG_IV_TYPE (ivs, regno) == GENERAL_INDUCT |
8595 | && REG_IV_INFO (ivs, regno)->src_reg == bl->biv->src_reg) | |
fdb1833a R |
8596 | p = last; |
8597 | } | |
8598 | } | |
8599 | } | |
039baf9e EB |
8600 | |
8601 | /* Closely examine the insn if the biv is mentioned. */ | |
b4ad7b23 RS |
8602 | if ((code == INSN || code == JUMP_INSN || code == CALL_INSN) |
8603 | && reg_mentioned_p (reg, PATTERN (p)) | |
0534b804 | 8604 | && ! maybe_eliminate_biv_1 (loop, PATTERN (p), p, bl, |
96a45535 | 8605 | eliminate_p, where_bb, where_insn)) |
b4ad7b23 RS |
8606 | { |
8607 | if (loop_dump_stream) | |
8608 | fprintf (loop_dump_stream, | |
8609 | "Cannot eliminate biv %d: biv used in insn %d.\n", | |
8610 | bl->regno, INSN_UID (p)); | |
8611 | break; | |
8612 | } | |
039baf9e EB |
8613 | |
8614 | /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */ | |
8615 | if (eliminate_p | |
8616 | && (note = find_reg_note (p, REG_EQUAL, NULL_RTX)) != NULL_RTX | |
8617 | && reg_mentioned_p (reg, XEXP (note, 0))) | |
8618 | remove_note (p, note); | |
b4ad7b23 RS |
8619 | } |
8620 | ||
96a45535 | 8621 | if (p == loop->end) |
b4ad7b23 RS |
8622 | { |
8623 | if (loop_dump_stream) | |
8624 | fprintf (loop_dump_stream, "biv %d %s eliminated.\n", | |
8625 | bl->regno, eliminate_p ? "was" : "can be"); | |
8626 | return 1; | |
8627 | } | |
8628 | ||
8629 | return 0; | |
8630 | } | |
8631 | \f | |
a6207a2b | 8632 | /* INSN and REFERENCE are instructions in the same insn chain. |
cc2902df | 8633 | Return nonzero if INSN is first. */ |
a6207a2b | 8634 | |
c99f8c2a | 8635 | int |
0c20a65f | 8636 | loop_insn_first_p (rtx insn, rtx reference) |
a6207a2b | 8637 | { |
f38cbf0f R |
8638 | rtx p, q; |
8639 | ||
e6fcb60d | 8640 | for (p = insn, q = reference;;) |
f38cbf0f R |
8641 | { |
8642 | /* Start with test for not first so that INSN == REFERENCE yields not | |
8643 | first. */ | |
8644 | if (q == insn || ! p) | |
e11e816e | 8645 | return 0; |
f38cbf0f | 8646 | if (p == reference || ! q) |
e11e816e | 8647 | return 1; |
f38cbf0f | 8648 | |
7c2772f1 R |
8649 | /* Either of P or Q might be a NOTE. Notes have the same LUID as the |
8650 | previous insn, hence the <= comparison below does not work if | |
8651 | P is a note. */ | |
f38cbf0f | 8652 | if (INSN_UID (p) < max_uid_for_loop |
7c2772f1 R |
8653 | && INSN_UID (q) < max_uid_for_loop |
8654 | && GET_CODE (p) != NOTE) | |
8655 | return INSN_LUID (p) <= INSN_LUID (q); | |
f38cbf0f | 8656 | |
7c2772f1 R |
8657 | if (INSN_UID (p) >= max_uid_for_loop |
8658 | || GET_CODE (p) == NOTE) | |
f38cbf0f R |
8659 | p = NEXT_INSN (p); |
8660 | if (INSN_UID (q) >= max_uid_for_loop) | |
8661 | q = NEXT_INSN (q); | |
8662 | } | |
a6207a2b R |
8663 | } |
8664 | ||
cc2902df | 8665 | /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if |
a6207a2b R |
8666 | the offset that we have to take into account due to auto-increment / |
8667 | div derivation is zero. */ | |
8668 | static int | |
0c20a65f AJ |
8669 | biv_elimination_giv_has_0_offset (struct induction *biv, |
8670 | struct induction *giv, rtx insn) | |
a6207a2b R |
8671 | { |
8672 | /* If the giv V had the auto-inc address optimization applied | |
8673 | to it, and INSN occurs between the giv insn and the biv | |
8674 | insn, then we'd have to adjust the value used here. | |
8675 | This is rare, so we don't bother to make this possible. */ | |
8676 | if (giv->auto_inc_opt | |
8677 | && ((loop_insn_first_p (giv->insn, insn) | |
8678 | && loop_insn_first_p (insn, biv->insn)) | |
8679 | || (loop_insn_first_p (biv->insn, insn) | |
8680 | && loop_insn_first_p (insn, giv->insn)))) | |
8681 | return 0; | |
8682 | ||
a6207a2b R |
8683 | return 1; |
8684 | } | |
8685 | ||
b4ad7b23 RS |
8686 | /* If BL appears in X (part of the pattern of INSN), see if we can |
8687 | eliminate its use. If so, return 1. If not, return 0. | |
8688 | ||
8689 | If BIV does not appear in X, return 1. | |
8690 | ||
cc2902df | 8691 | If ELIMINATE_P is nonzero, actually do the elimination. |
96a45535 MH |
8692 | WHERE_INSN/WHERE_BB indicate where extra insns should be added. |
8693 | Depending on how many items have been moved out of the loop, it | |
cc2902df | 8694 | will either be before INSN (when WHERE_INSN is nonzero) or at the |
96a45535 | 8695 | start of the loop (when WHERE_INSN is zero). */ |
b4ad7b23 RS |
8696 | |
8697 | static int | |
0c20a65f AJ |
8698 | maybe_eliminate_biv_1 (const struct loop *loop, rtx x, rtx insn, |
8699 | struct iv_class *bl, int eliminate_p, | |
8700 | basic_block where_bb, rtx where_insn) | |
b4ad7b23 RS |
8701 | { |
8702 | enum rtx_code code = GET_CODE (x); | |
8703 | rtx reg = bl->biv->dest_reg; | |
8704 | enum machine_mode mode = GET_MODE (reg); | |
8705 | struct induction *v; | |
51723711 KG |
8706 | rtx arg, tem; |
8707 | #ifdef HAVE_cc0 | |
8708 | rtx new; | |
8709 | #endif | |
b4ad7b23 | 8710 | int arg_operand; |
6f7d635c | 8711 | const char *fmt; |
b4ad7b23 RS |
8712 | int i, j; |
8713 | ||
8714 | switch (code) | |
8715 | { | |
8716 | case REG: | |
8717 | /* If we haven't already been able to do something with this BIV, | |
8718 | we can't eliminate it. */ | |
8719 | if (x == reg) | |
8720 | return 0; | |
8721 | return 1; | |
8722 | ||
8723 | case SET: | |
8724 | /* If this sets the BIV, it is not a problem. */ | |
8725 | if (SET_DEST (x) == reg) | |
8726 | return 1; | |
8727 | ||
8728 | /* If this is an insn that defines a giv, it is also ok because | |
8729 | it will go away when the giv is reduced. */ | |
8730 | for (v = bl->giv; v; v = v->next_iv) | |
8731 | if (v->giv_type == DEST_REG && SET_DEST (x) == v->dest_reg) | |
8732 | return 1; | |
8733 | ||
8734 | #ifdef HAVE_cc0 | |
8735 | if (SET_DEST (x) == cc0_rtx && SET_SRC (x) == reg) | |
8736 | { | |
8737 | /* Can replace with any giv that was reduced and | |
8738 | that has (MULT_VAL != 0) and (ADD_VAL == 0). | |
fbdc6da8 RK |
8739 | Require a constant for MULT_VAL, so we know it's nonzero. |
8740 | ??? We disable this optimization to avoid potential | |
8741 | overflows. */ | |
b4ad7b23 RS |
8742 | |
8743 | for (v = bl->giv; v; v = v->next_iv) | |
3508c681 | 8744 | if (GET_CODE (v->mult_val) == CONST_INT && v->mult_val != const0_rtx |
b4ad7b23 | 8745 | && v->add_val == const0_rtx |
453331a3 | 8746 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8747 | && v->mode == mode |
8748 | && 0) | |
b4ad7b23 | 8749 | { |
a6207a2b | 8750 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8751 | continue; |
8752 | ||
b4ad7b23 RS |
8753 | if (! eliminate_p) |
8754 | return 1; | |
8755 | ||
8756 | /* If the giv has the opposite direction of change, | |
8757 | then reverse the comparison. */ | |
8758 | if (INTVAL (v->mult_val) < 0) | |
38a448ca RH |
8759 | new = gen_rtx_COMPARE (GET_MODE (v->new_reg), |
8760 | const0_rtx, v->new_reg); | |
b4ad7b23 RS |
8761 | else |
8762 | new = v->new_reg; | |
8763 | ||
8764 | /* We can probably test that giv's reduced reg. */ | |
8765 | if (validate_change (insn, &SET_SRC (x), new, 0)) | |
8766 | return 1; | |
8767 | } | |
8768 | ||
8769 | /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0); | |
8770 | replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL). | |
fbdc6da8 RK |
8771 | Require a constant for MULT_VAL, so we know it's nonzero. |
8772 | ??? Do this only if ADD_VAL is a pointer to avoid a potential | |
8773 | overflow problem. */ | |
b4ad7b23 RS |
8774 | |
8775 | for (v = bl->giv; v; v = v->next_iv) | |
e6fcb60d KH |
8776 | if (GET_CODE (v->mult_val) == CONST_INT |
8777 | && v->mult_val != const0_rtx | |
453331a3 | 8778 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8779 | && v->mode == mode |
8780 | && (GET_CODE (v->add_val) == SYMBOL_REF | |
8781 | || GET_CODE (v->add_val) == LABEL_REF | |
8782 | || GET_CODE (v->add_val) == CONST | |
8783 | || (GET_CODE (v->add_val) == REG | |
3502dc9c | 8784 | && REG_POINTER (v->add_val)))) |
b4ad7b23 | 8785 | { |
a6207a2b | 8786 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8787 | continue; |
8788 | ||
b4ad7b23 RS |
8789 | if (! eliminate_p) |
8790 | return 1; | |
8791 | ||
8792 | /* If the giv has the opposite direction of change, | |
8793 | then reverse the comparison. */ | |
8794 | if (INTVAL (v->mult_val) < 0) | |
38a448ca RH |
8795 | new = gen_rtx_COMPARE (VOIDmode, copy_rtx (v->add_val), |
8796 | v->new_reg); | |
b4ad7b23 | 8797 | else |
38a448ca RH |
8798 | new = gen_rtx_COMPARE (VOIDmode, v->new_reg, |
8799 | copy_rtx (v->add_val)); | |
b4ad7b23 RS |
8800 | |
8801 | /* Replace biv with the giv's reduced register. */ | |
8802 | update_reg_last_use (v->add_val, insn); | |
8803 | if (validate_change (insn, &SET_SRC (PATTERN (insn)), new, 0)) | |
8804 | return 1; | |
8805 | ||
8806 | /* Insn doesn't support that constant or invariant. Copy it | |
8807 | into a register (it will be a loop invariant.) */ | |
8808 | tem = gen_reg_rtx (GET_MODE (v->new_reg)); | |
8809 | ||
86e21212 MH |
8810 | loop_insn_emit_before (loop, 0, where_insn, |
8811 | gen_move_insn (tem, | |
8812 | copy_rtx (v->add_val))); | |
b4ad7b23 | 8813 | |
2ae3dcac | 8814 | /* Substitute the new register for its invariant value in |
e6fcb60d | 8815 | the compare expression. */ |
2ae3dcac RK |
8816 | XEXP (new, (INTVAL (v->mult_val) < 0) ? 0 : 1) = tem; |
8817 | if (validate_change (insn, &SET_SRC (PATTERN (insn)), new, 0)) | |
b4ad7b23 RS |
8818 | return 1; |
8819 | } | |
8820 | } | |
8821 | #endif | |
8822 | break; | |
8823 | ||
8824 | case COMPARE: | |
8825 | case EQ: case NE: | |
8826 | case GT: case GE: case GTU: case GEU: | |
8827 | case LT: case LE: case LTU: case LEU: | |
8828 | /* See if either argument is the biv. */ | |
8829 | if (XEXP (x, 0) == reg) | |
8830 | arg = XEXP (x, 1), arg_operand = 1; | |
8831 | else if (XEXP (x, 1) == reg) | |
8832 | arg = XEXP (x, 0), arg_operand = 0; | |
8833 | else | |
8834 | break; | |
8835 | ||
8836 | if (CONSTANT_P (arg)) | |
8837 | { | |
8838 | /* First try to replace with any giv that has constant positive | |
8839 | mult_val and constant add_val. We might be able to support | |
8840 | negative mult_val, but it seems complex to do it in general. */ | |
8841 | ||
8842 | for (v = bl->giv; v; v = v->next_iv) | |
e6fcb60d KH |
8843 | if (GET_CODE (v->mult_val) == CONST_INT |
8844 | && INTVAL (v->mult_val) > 0 | |
fbdc6da8 RK |
8845 | && (GET_CODE (v->add_val) == SYMBOL_REF |
8846 | || GET_CODE (v->add_val) == LABEL_REF | |
8847 | || GET_CODE (v->add_val) == CONST | |
8848 | || (GET_CODE (v->add_val) == REG | |
3502dc9c | 8849 | && REG_POINTER (v->add_val))) |
453331a3 | 8850 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
b4ad7b23 RS |
8851 | && v->mode == mode) |
8852 | { | |
a6207a2b | 8853 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8854 | continue; |
8855 | ||
ce60bf25 EB |
8856 | /* Don't eliminate if the linear combination that makes up |
8857 | the giv overflows when it is applied to ARG. */ | |
8858 | if (GET_CODE (arg) == CONST_INT) | |
8859 | { | |
8860 | rtx add_val; | |
8861 | ||
8862 | if (GET_CODE (v->add_val) == CONST_INT) | |
8863 | add_val = v->add_val; | |
8864 | else | |
8865 | add_val = const0_rtx; | |
8866 | ||
8867 | if (const_mult_add_overflow_p (arg, v->mult_val, | |
8868 | add_val, mode, 1)) | |
8869 | continue; | |
8870 | } | |
8871 | ||
b4ad7b23 RS |
8872 | if (! eliminate_p) |
8873 | return 1; | |
8874 | ||
8875 | /* Replace biv with the giv's reduced reg. */ | |
e6fcb60d | 8876 | validate_change (insn, &XEXP (x, 1 - arg_operand), v->new_reg, 1); |
b4ad7b23 RS |
8877 | |
8878 | /* If all constants are actually constant integers and | |
8879 | the derived constant can be directly placed in the COMPARE, | |
8880 | do so. */ | |
8881 | if (GET_CODE (arg) == CONST_INT | |
3508c681 JH |
8882 | && GET_CODE (v->add_val) == CONST_INT) |
8883 | { | |
ce60bf25 EB |
8884 | tem = expand_mult_add (arg, NULL_RTX, v->mult_val, |
8885 | v->add_val, mode, 1); | |
3508c681 JH |
8886 | } |
8887 | else | |
8888 | { | |
8889 | /* Otherwise, load it into a register. */ | |
8890 | tem = gen_reg_rtx (mode); | |
96a45535 MH |
8891 | loop_iv_add_mult_emit_before (loop, arg, |
8892 | v->mult_val, v->add_val, | |
8893 | tem, where_bb, where_insn); | |
3508c681 | 8894 | } |
ce60bf25 EB |
8895 | |
8896 | validate_change (insn, &XEXP (x, arg_operand), tem, 1); | |
8897 | ||
3508c681 | 8898 | if (apply_change_group ()) |
b4ad7b23 | 8899 | return 1; |
b4ad7b23 | 8900 | } |
e6fcb60d | 8901 | |
b4ad7b23 | 8902 | /* Look for giv with positive constant mult_val and nonconst add_val. |
e6fcb60d | 8903 | Insert insns to calculate new compare value. |
fbdc6da8 | 8904 | ??? Turn this off due to possible overflow. */ |
b4ad7b23 RS |
8905 | |
8906 | for (v = bl->giv; v; v = v->next_iv) | |
e6fcb60d KH |
8907 | if (GET_CODE (v->mult_val) == CONST_INT |
8908 | && INTVAL (v->mult_val) > 0 | |
453331a3 | 8909 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8910 | && v->mode == mode |
8911 | && 0) | |
b4ad7b23 RS |
8912 | { |
8913 | rtx tem; | |
8914 | ||
a6207a2b | 8915 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8916 | continue; |
8917 | ||
b4ad7b23 RS |
8918 | if (! eliminate_p) |
8919 | return 1; | |
8920 | ||
8921 | tem = gen_reg_rtx (mode); | |
8922 | ||
8923 | /* Replace biv with giv's reduced register. */ | |
8924 | validate_change (insn, &XEXP (x, 1 - arg_operand), | |
8925 | v->new_reg, 1); | |
8926 | ||
8927 | /* Compute value to compare against. */ | |
6b8c9327 | 8928 | loop_iv_add_mult_emit_before (loop, arg, |
96a45535 MH |
8929 | v->mult_val, v->add_val, |
8930 | tem, where_bb, where_insn); | |
b4ad7b23 RS |
8931 | /* Use it in this insn. */ |
8932 | validate_change (insn, &XEXP (x, arg_operand), tem, 1); | |
8933 | if (apply_change_group ()) | |
8934 | return 1; | |
8935 | } | |
8936 | } | |
8937 | else if (GET_CODE (arg) == REG || GET_CODE (arg) == MEM) | |
8938 | { | |
0534b804 | 8939 | if (loop_invariant_p (loop, arg) == 1) |
b4ad7b23 RS |
8940 | { |
8941 | /* Look for giv with constant positive mult_val and nonconst | |
e6fcb60d | 8942 | add_val. Insert insns to compute new compare value. |
fbdc6da8 | 8943 | ??? Turn this off due to possible overflow. */ |
b4ad7b23 RS |
8944 | |
8945 | for (v = bl->giv; v; v = v->next_iv) | |
3508c681 | 8946 | if (GET_CODE (v->mult_val) == CONST_INT && INTVAL (v->mult_val) > 0 |
453331a3 | 8947 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8948 | && v->mode == mode |
8949 | && 0) | |
b4ad7b23 RS |
8950 | { |
8951 | rtx tem; | |
8952 | ||
a6207a2b | 8953 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8954 | continue; |
8955 | ||
b4ad7b23 RS |
8956 | if (! eliminate_p) |
8957 | return 1; | |
8958 | ||
8959 | tem = gen_reg_rtx (mode); | |
8960 | ||
8961 | /* Replace biv with giv's reduced register. */ | |
8962 | validate_change (insn, &XEXP (x, 1 - arg_operand), | |
8963 | v->new_reg, 1); | |
8964 | ||
8965 | /* Compute value to compare against. */ | |
6b8c9327 | 8966 | loop_iv_add_mult_emit_before (loop, arg, |
96a45535 MH |
8967 | v->mult_val, v->add_val, |
8968 | tem, where_bb, where_insn); | |
b4ad7b23 RS |
8969 | validate_change (insn, &XEXP (x, arg_operand), tem, 1); |
8970 | if (apply_change_group ()) | |
8971 | return 1; | |
8972 | } | |
8973 | } | |
8974 | ||
8975 | /* This code has problems. Basically, you can't know when | |
8976 | seeing if we will eliminate BL, whether a particular giv | |
8977 | of ARG will be reduced. If it isn't going to be reduced, | |
8978 | we can't eliminate BL. We can try forcing it to be reduced, | |
8979 | but that can generate poor code. | |
8980 | ||
8981 | The problem is that the benefit of reducing TV, below should | |
8982 | be increased if BL can actually be eliminated, but this means | |
8983 | we might have to do a topological sort of the order in which | |
8984 | we try to process biv. It doesn't seem worthwhile to do | |
8985 | this sort of thing now. */ | |
8986 | ||
8987 | #if 0 | |
8988 | /* Otherwise the reg compared with had better be a biv. */ | |
8989 | if (GET_CODE (arg) != REG | |
ed5bb68d | 8990 | || REG_IV_TYPE (ivs, REGNO (arg)) != BASIC_INDUCT) |
b4ad7b23 RS |
8991 | return 0; |
8992 | ||
8993 | /* Look for a pair of givs, one for each biv, | |
8994 | with identical coefficients. */ | |
8995 | for (v = bl->giv; v; v = v->next_iv) | |
8996 | { | |
8997 | struct induction *tv; | |
8998 | ||
8999 | if (v->ignore || v->maybe_dead || v->mode != mode) | |
9000 | continue; | |
9001 | ||
6b8c9327 | 9002 | for (tv = REG_IV_CLASS (ivs, REGNO (arg))->giv; tv; |
8b634749 | 9003 | tv = tv->next_iv) |
b4ad7b23 RS |
9004 | if (! tv->ignore && ! tv->maybe_dead |
9005 | && rtx_equal_p (tv->mult_val, v->mult_val) | |
9006 | && rtx_equal_p (tv->add_val, v->add_val) | |
9007 | && tv->mode == mode) | |
9008 | { | |
a6207a2b | 9009 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
9010 | continue; |
9011 | ||
b4ad7b23 RS |
9012 | if (! eliminate_p) |
9013 | return 1; | |
9014 | ||
9015 | /* Replace biv with its giv's reduced reg. */ | |
e6fcb60d | 9016 | XEXP (x, 1 - arg_operand) = v->new_reg; |
b4ad7b23 RS |
9017 | /* Replace other operand with the other giv's |
9018 | reduced reg. */ | |
9019 | XEXP (x, arg_operand) = tv->new_reg; | |
9020 | return 1; | |
9021 | } | |
9022 | } | |
9023 | #endif | |
9024 | } | |
9025 | ||
9026 | /* If we get here, the biv can't be eliminated. */ | |
9027 | return 0; | |
9028 | ||
9029 | case MEM: | |
9030 | /* If this address is a DEST_ADDR giv, it doesn't matter if the | |
9031 | biv is used in it, since it will be replaced. */ | |
9032 | for (v = bl->giv; v; v = v->next_iv) | |
9033 | if (v->giv_type == DEST_ADDR && v->location == &XEXP (x, 0)) | |
9034 | return 1; | |
9035 | break; | |
e9a25f70 JL |
9036 | |
9037 | default: | |
9038 | break; | |
b4ad7b23 RS |
9039 | } |
9040 | ||
9041 | /* See if any subexpression fails elimination. */ | |
9042 | fmt = GET_RTX_FORMAT (code); | |
9043 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9044 | { | |
9045 | switch (fmt[i]) | |
9046 | { | |
9047 | case 'e': | |
e6fcb60d | 9048 | if (! maybe_eliminate_biv_1 (loop, XEXP (x, i), insn, bl, |
96a45535 | 9049 | eliminate_p, where_bb, where_insn)) |
b4ad7b23 RS |
9050 | return 0; |
9051 | break; | |
9052 | ||
9053 | case 'E': | |
9054 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
0534b804 | 9055 | if (! maybe_eliminate_biv_1 (loop, XVECEXP (x, i, j), insn, bl, |
96a45535 | 9056 | eliminate_p, where_bb, where_insn)) |
b4ad7b23 RS |
9057 | return 0; |
9058 | break; | |
9059 | } | |
9060 | } | |
9061 | ||
9062 | return 1; | |
e6fcb60d | 9063 | } |
b4ad7b23 RS |
9064 | \f |
9065 | /* Return nonzero if the last use of REG | |
9066 | is in an insn following INSN in the same basic block. */ | |
9067 | ||
9068 | static int | |
0c20a65f | 9069 | last_use_this_basic_block (rtx reg, rtx insn) |
b4ad7b23 RS |
9070 | { |
9071 | rtx n; | |
9072 | for (n = insn; | |
9073 | n && GET_CODE (n) != CODE_LABEL && GET_CODE (n) != JUMP_INSN; | |
9074 | n = NEXT_INSN (n)) | |
9075 | { | |
b1f21e0a | 9076 | if (REGNO_LAST_UID (REGNO (reg)) == INSN_UID (n)) |
b4ad7b23 RS |
9077 | return 1; |
9078 | } | |
9079 | return 0; | |
9080 | } | |
9081 | \f | |
9082 | /* Called via `note_stores' to record the initial value of a biv. Here we | |
9083 | just record the location of the set and process it later. */ | |
9084 | ||
9085 | static void | |
0c20a65f | 9086 | record_initial (rtx dest, rtx set, void *data ATTRIBUTE_UNUSED) |
b4ad7b23 | 9087 | { |
ed5bb68d | 9088 | struct loop_ivs *ivs = (struct loop_ivs *) data; |
b4ad7b23 RS |
9089 | struct iv_class *bl; |
9090 | ||
9091 | if (GET_CODE (dest) != REG | |
86fee241 | 9092 | || REGNO (dest) >= ivs->n_regs |
ed5bb68d | 9093 | || REG_IV_TYPE (ivs, REGNO (dest)) != BASIC_INDUCT) |
b4ad7b23 RS |
9094 | return; |
9095 | ||
8b634749 | 9096 | bl = REG_IV_CLASS (ivs, REGNO (dest)); |
b4ad7b23 RS |
9097 | |
9098 | /* If this is the first set found, record it. */ | |
9099 | if (bl->init_insn == 0) | |
9100 | { | |
9101 | bl->init_insn = note_insn; | |
9102 | bl->init_set = set; | |
9103 | } | |
9104 | } | |
9105 | \f | |
9106 | /* If any of the registers in X are "old" and currently have a last use earlier | |
9107 | than INSN, update them to have a last use of INSN. Their actual last use | |
9108 | will be the previous insn but it will not have a valid uid_luid so we can't | |
96a45535 | 9109 | use it. X must be a source expression only. */ |
b4ad7b23 RS |
9110 | |
9111 | static void | |
0c20a65f | 9112 | update_reg_last_use (rtx x, rtx insn) |
b4ad7b23 RS |
9113 | { |
9114 | /* Check for the case where INSN does not have a valid luid. In this case, | |
9115 | there is no need to modify the regno_last_uid, as this can only happen | |
9116 | when code is inserted after the loop_end to set a pseudo's final value, | |
6b8c9327 AJ |
9117 | and hence this insn will never be the last use of x. |
9118 | ???? This comment is not correct. See for example loop_givs_reduce. | |
96a45535 | 9119 | This may insert an insn before another new insn. */ |
b4ad7b23 RS |
9120 | if (GET_CODE (x) == REG && REGNO (x) < max_reg_before_loop |
9121 | && INSN_UID (insn) < max_uid_for_loop | |
8529a489 | 9122 | && REGNO_LAST_LUID (REGNO (x)) < INSN_LUID (insn)) |
96a45535 MH |
9123 | { |
9124 | REGNO_LAST_UID (REGNO (x)) = INSN_UID (insn); | |
9125 | } | |
b4ad7b23 RS |
9126 | else |
9127 | { | |
b3694847 SS |
9128 | int i, j; |
9129 | const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
b4ad7b23 RS |
9130 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
9131 | { | |
9132 | if (fmt[i] == 'e') | |
9133 | update_reg_last_use (XEXP (x, i), insn); | |
9134 | else if (fmt[i] == 'E') | |
9135 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9136 | update_reg_last_use (XVECEXP (x, i, j), insn); | |
9137 | } | |
9138 | } | |
9139 | } | |
9140 | \f | |
a49a6a68 JW |
9141 | /* Given an insn INSN and condition COND, return the condition in a |
9142 | canonical form to simplify testing by callers. Specifically: | |
b4ad7b23 RS |
9143 | |
9144 | (1) The code will always be a comparison operation (EQ, NE, GT, etc.). | |
9145 | (2) Both operands will be machine operands; (cc0) will have been replaced. | |
9146 | (3) If an operand is a constant, it will be the second operand. | |
9147 | (4) (LE x const) will be replaced with (LT x <const+1>) and similarly | |
a49a6a68 JW |
9148 | for GE, GEU, and LEU. |
9149 | ||
9150 | If the condition cannot be understood, or is an inequality floating-point | |
9151 | comparison which needs to be reversed, 0 will be returned. | |
9152 | ||
cc2902df | 9153 | If REVERSE is nonzero, then reverse the condition prior to canonizing it. |
a49a6a68 | 9154 | |
cc2902df | 9155 | If EARLIEST is nonzero, it is a pointer to a place where the earliest |
a49a6a68 JW |
9156 | insn used in locating the condition was found. If a replacement test |
9157 | of the condition is desired, it should be placed in front of that | |
10f13594 RH |
9158 | insn and we will be sure that the inputs are still valid. |
9159 | ||
cc2902df | 9160 | If WANT_REG is nonzero, we wish the condition to be relative to that |
10f13594 | 9161 | register, if possible. Therefore, do not canonicalize the condition |
ec6ec6aa ZD |
9162 | further. If ALLOW_CC_MODE is nonzero, allow the condition returned |
9163 | to be a compare to a CC mode register. */ | |
b4ad7b23 RS |
9164 | |
9165 | rtx | |
0c20a65f | 9166 | canonicalize_condition (rtx insn, rtx cond, int reverse, rtx *earliest, |
ec6ec6aa | 9167 | rtx want_reg, int allow_cc_mode) |
b4ad7b23 RS |
9168 | { |
9169 | enum rtx_code code; | |
a49a6a68 | 9170 | rtx prev = insn; |
b4ad7b23 RS |
9171 | rtx set; |
9172 | rtx tem; | |
9173 | rtx op0, op1; | |
9174 | int reverse_code = 0; | |
f283421d | 9175 | enum machine_mode mode; |
b4ad7b23 | 9176 | |
a49a6a68 JW |
9177 | code = GET_CODE (cond); |
9178 | mode = GET_MODE (cond); | |
9179 | op0 = XEXP (cond, 0); | |
9180 | op1 = XEXP (cond, 1); | |
b4ad7b23 | 9181 | |
a49a6a68 | 9182 | if (reverse) |
c9212f33 JH |
9183 | code = reversed_comparison_code (cond, insn); |
9184 | if (code == UNKNOWN) | |
9185 | return 0; | |
b4ad7b23 RS |
9186 | |
9187 | if (earliest) | |
a49a6a68 | 9188 | *earliest = insn; |
b4ad7b23 RS |
9189 | |
9190 | /* If we are comparing a register with zero, see if the register is set | |
9191 | in the previous insn to a COMPARE or a comparison operation. Perform | |
9192 | the same tests as a function of STORE_FLAG_VALUE as find_comparison_args | |
9193 | in cse.c */ | |
9194 | ||
10f13594 | 9195 | while (GET_RTX_CLASS (code) == '<' |
fd5d5b07 | 9196 | && op1 == CONST0_RTX (GET_MODE (op0)) |
10f13594 | 9197 | && op0 != want_reg) |
b4ad7b23 | 9198 | { |
cc2902df | 9199 | /* Set nonzero when we find something of interest. */ |
b4ad7b23 RS |
9200 | rtx x = 0; |
9201 | ||
9202 | #ifdef HAVE_cc0 | |
9203 | /* If comparison with cc0, import actual comparison from compare | |
9204 | insn. */ | |
9205 | if (op0 == cc0_rtx) | |
9206 | { | |
9207 | if ((prev = prev_nonnote_insn (prev)) == 0 | |
9208 | || GET_CODE (prev) != INSN | |
9209 | || (set = single_set (prev)) == 0 | |
9210 | || SET_DEST (set) != cc0_rtx) | |
9211 | return 0; | |
9212 | ||
9213 | op0 = SET_SRC (set); | |
9214 | op1 = CONST0_RTX (GET_MODE (op0)); | |
9215 | if (earliest) | |
9216 | *earliest = prev; | |
9217 | } | |
9218 | #endif | |
9219 | ||
9220 | /* If this is a COMPARE, pick up the two things being compared. */ | |
9221 | if (GET_CODE (op0) == COMPARE) | |
9222 | { | |
9223 | op1 = XEXP (op0, 1); | |
9224 | op0 = XEXP (op0, 0); | |
9225 | continue; | |
9226 | } | |
9227 | else if (GET_CODE (op0) != REG) | |
9228 | break; | |
9229 | ||
9230 | /* Go back to the previous insn. Stop if it is not an INSN. We also | |
9231 | stop if it isn't a single set or if it has a REG_INC note because | |
9232 | we don't want to bother dealing with it. */ | |
9233 | ||
9234 | if ((prev = prev_nonnote_insn (prev)) == 0 | |
9235 | || GET_CODE (prev) != INSN | |
ff81832f | 9236 | || FIND_REG_INC_NOTE (prev, NULL_RTX)) |
c9212f33 JH |
9237 | break; |
9238 | ||
9239 | set = set_of (op0, prev); | |
9240 | ||
9241 | if (set | |
9242 | && (GET_CODE (set) != SET | |
9243 | || !rtx_equal_p (SET_DEST (set), op0))) | |
b4ad7b23 RS |
9244 | break; |
9245 | ||
9246 | /* If this is setting OP0, get what it sets it to if it looks | |
9247 | relevant. */ | |
c9212f33 | 9248 | if (set) |
b4ad7b23 | 9249 | { |
6d90e7c0 | 9250 | enum machine_mode inner_mode = GET_MODE (SET_DEST (set)); |
efdc7e19 RH |
9251 | #ifdef FLOAT_STORE_FLAG_VALUE |
9252 | REAL_VALUE_TYPE fsfv; | |
9253 | #endif | |
b4ad7b23 | 9254 | |
f283421d RH |
9255 | /* ??? We may not combine comparisons done in a CCmode with |
9256 | comparisons not done in a CCmode. This is to aid targets | |
9257 | like Alpha that have an IEEE compliant EQ instruction, and | |
9258 | a non-IEEE compliant BEQ instruction. The use of CCmode is | |
9259 | actually artificial, simply to prevent the combination, but | |
12f289ac JW |
9260 | should not affect other platforms. |
9261 | ||
9262 | However, we must allow VOIDmode comparisons to match either | |
9263 | CCmode or non-CCmode comparison, because some ports have | |
9264 | modeless comparisons inside branch patterns. | |
9265 | ||
9266 | ??? This mode check should perhaps look more like the mode check | |
9267 | in simplify_comparison in combine. */ | |
f283421d | 9268 | |
b4ad7b23 | 9269 | if ((GET_CODE (SET_SRC (set)) == COMPARE |
b565a316 RK |
9270 | || (((code == NE |
9271 | || (code == LT | |
9272 | && GET_MODE_CLASS (inner_mode) == MODE_INT | |
5fd8383e RK |
9273 | && (GET_MODE_BITSIZE (inner_mode) |
9274 | <= HOST_BITS_PER_WIDE_INT) | |
b565a316 | 9275 | && (STORE_FLAG_VALUE |
5fd8383e RK |
9276 | & ((HOST_WIDE_INT) 1 |
9277 | << (GET_MODE_BITSIZE (inner_mode) - 1)))) | |
b565a316 RK |
9278 | #ifdef FLOAT_STORE_FLAG_VALUE |
9279 | || (code == LT | |
9280 | && GET_MODE_CLASS (inner_mode) == MODE_FLOAT | |
efdc7e19 RH |
9281 | && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode), |
9282 | REAL_VALUE_NEGATIVE (fsfv))) | |
b565a316 RK |
9283 | #endif |
9284 | )) | |
f283421d | 9285 | && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<')) |
12f289ac JW |
9286 | && (((GET_MODE_CLASS (mode) == MODE_CC) |
9287 | == (GET_MODE_CLASS (inner_mode) == MODE_CC)) | |
9288 | || mode == VOIDmode || inner_mode == VOIDmode)) | |
b4ad7b23 | 9289 | x = SET_SRC (set); |
b565a316 RK |
9290 | else if (((code == EQ |
9291 | || (code == GE | |
5fd8383e RK |
9292 | && (GET_MODE_BITSIZE (inner_mode) |
9293 | <= HOST_BITS_PER_WIDE_INT) | |
b565a316 RK |
9294 | && GET_MODE_CLASS (inner_mode) == MODE_INT |
9295 | && (STORE_FLAG_VALUE | |
5fd8383e RK |
9296 | & ((HOST_WIDE_INT) 1 |
9297 | << (GET_MODE_BITSIZE (inner_mode) - 1)))) | |
b565a316 RK |
9298 | #ifdef FLOAT_STORE_FLAG_VALUE |
9299 | || (code == GE | |
9300 | && GET_MODE_CLASS (inner_mode) == MODE_FLOAT | |
efdc7e19 RH |
9301 | && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode), |
9302 | REAL_VALUE_NEGATIVE (fsfv))) | |
fb8ca0a4 | 9303 | #endif |
b565a316 | 9304 | )) |
f283421d | 9305 | && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<' |
e6fcb60d | 9306 | && (((GET_MODE_CLASS (mode) == MODE_CC) |
12f289ac JW |
9307 | == (GET_MODE_CLASS (inner_mode) == MODE_CC)) |
9308 | || mode == VOIDmode || inner_mode == VOIDmode)) | |
9309 | ||
b4ad7b23 | 9310 | { |
b4ad7b23 RS |
9311 | reverse_code = 1; |
9312 | x = SET_SRC (set); | |
9313 | } | |
71ef37f6 RK |
9314 | else |
9315 | break; | |
b4ad7b23 RS |
9316 | } |
9317 | ||
9318 | else if (reg_set_p (op0, prev)) | |
9319 | /* If this sets OP0, but not directly, we have to give up. */ | |
9320 | break; | |
9321 | ||
9322 | if (x) | |
9323 | { | |
9324 | if (GET_RTX_CLASS (GET_CODE (x)) == '<') | |
9325 | code = GET_CODE (x); | |
9326 | if (reverse_code) | |
9327 | { | |
c9212f33 | 9328 | code = reversed_comparison_code (x, prev); |
1eb8759b RH |
9329 | if (code == UNKNOWN) |
9330 | return 0; | |
b4ad7b23 RS |
9331 | reverse_code = 0; |
9332 | } | |
9333 | ||
9334 | op0 = XEXP (x, 0), op1 = XEXP (x, 1); | |
9335 | if (earliest) | |
9336 | *earliest = prev; | |
9337 | } | |
9338 | } | |
9339 | ||
9340 | /* If constant is first, put it last. */ | |
9341 | if (CONSTANT_P (op0)) | |
9342 | code = swap_condition (code), tem = op0, op0 = op1, op1 = tem; | |
9343 | ||
9344 | /* If OP0 is the result of a comparison, we weren't able to find what | |
9345 | was really being compared, so fail. */ | |
ec6ec6aa ZD |
9346 | if (!allow_cc_mode |
9347 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) | |
b4ad7b23 RS |
9348 | return 0; |
9349 | ||
d8cfa4ee RK |
9350 | /* Canonicalize any ordered comparison with integers involving equality |
9351 | if we can do computations in the relevant mode and we do not | |
9352 | overflow. */ | |
9353 | ||
ec6ec6aa ZD |
9354 | if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_CC |
9355 | && GET_CODE (op1) == CONST_INT | |
d8cfa4ee RK |
9356 | && GET_MODE (op0) != VOIDmode |
9357 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT) | |
b4ad7b23 | 9358 | { |
5fd8383e RK |
9359 | HOST_WIDE_INT const_val = INTVAL (op1); |
9360 | unsigned HOST_WIDE_INT uconst_val = const_val; | |
d8cfa4ee RK |
9361 | unsigned HOST_WIDE_INT max_val |
9362 | = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0)); | |
b4ad7b23 RS |
9363 | |
9364 | switch (code) | |
d8cfa4ee RK |
9365 | { |
9366 | case LE: | |
e51712db | 9367 | if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) |
e879eb2f | 9368 | code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0)); |
d8cfa4ee | 9369 | break; |
b4ad7b23 | 9370 | |
460f50dc R |
9371 | /* When cross-compiling, const_val might be sign-extended from |
9372 | BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */ | |
d8cfa4ee | 9373 | case GE: |
e51712db | 9374 | if ((HOST_WIDE_INT) (const_val & max_val) |
d8cfa4ee RK |
9375 | != (((HOST_WIDE_INT) 1 |
9376 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
e879eb2f | 9377 | code = GT, op1 = gen_int_mode (const_val - 1, GET_MODE (op0)); |
d8cfa4ee | 9378 | break; |
b4ad7b23 | 9379 | |
d8cfa4ee | 9380 | case LEU: |
460f50dc | 9381 | if (uconst_val < max_val) |
e879eb2f | 9382 | code = LTU, op1 = gen_int_mode (uconst_val + 1, GET_MODE (op0)); |
d8cfa4ee | 9383 | break; |
b4ad7b23 | 9384 | |
d8cfa4ee RK |
9385 | case GEU: |
9386 | if (uconst_val != 0) | |
e879eb2f | 9387 | code = GTU, op1 = gen_int_mode (uconst_val - 1, GET_MODE (op0)); |
d8cfa4ee | 9388 | break; |
e9a25f70 JL |
9389 | |
9390 | default: | |
9391 | break; | |
d8cfa4ee | 9392 | } |
b4ad7b23 RS |
9393 | } |
9394 | ||
b4ad7b23 | 9395 | /* Never return CC0; return zero instead. */ |
8beccec8 | 9396 | if (CC0_P (op0)) |
b4ad7b23 | 9397 | return 0; |
b4ad7b23 | 9398 | |
38a448ca | 9399 | return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
b4ad7b23 RS |
9400 | } |
9401 | ||
a49a6a68 JW |
9402 | /* Given a jump insn JUMP, return the condition that will cause it to branch |
9403 | to its JUMP_LABEL. If the condition cannot be understood, or is an | |
9404 | inequality floating-point comparison which needs to be reversed, 0 will | |
9405 | be returned. | |
9406 | ||
cc2902df | 9407 | If EARLIEST is nonzero, it is a pointer to a place where the earliest |
a49a6a68 JW |
9408 | insn used in locating the condition was found. If a replacement test |
9409 | of the condition is desired, it should be placed in front of that | |
ec6ec6aa ZD |
9410 | insn and we will be sure that the inputs are still valid. |
9411 | ||
9412 | If ALLOW_CC_MODE is nonzero, allow the condition returned to be a | |
9413 | compare CC mode register. */ | |
a49a6a68 JW |
9414 | |
9415 | rtx | |
ec6ec6aa | 9416 | get_condition (rtx jump, rtx *earliest, int allow_cc_mode) |
a49a6a68 JW |
9417 | { |
9418 | rtx cond; | |
9419 | int reverse; | |
7f1c097d | 9420 | rtx set; |
a49a6a68 JW |
9421 | |
9422 | /* If this is not a standard conditional jump, we can't parse it. */ | |
9423 | if (GET_CODE (jump) != JUMP_INSN | |
7f1c097d | 9424 | || ! any_condjump_p (jump)) |
a49a6a68 | 9425 | return 0; |
7f1c097d | 9426 | set = pc_set (jump); |
a49a6a68 | 9427 | |
7f1c097d | 9428 | cond = XEXP (SET_SRC (set), 0); |
a49a6a68 JW |
9429 | |
9430 | /* If this branches to JUMP_LABEL when the condition is false, reverse | |
9431 | the condition. */ | |
9432 | reverse | |
7f1c097d JH |
9433 | = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF |
9434 | && XEXP (XEXP (SET_SRC (set), 2), 0) == JUMP_LABEL (jump); | |
a49a6a68 | 9435 | |
ec6ec6aa ZD |
9436 | return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX, |
9437 | allow_cc_mode); | |
a49a6a68 JW |
9438 | } |
9439 | ||
b4ad7b23 RS |
9440 | /* Similar to above routine, except that we also put an invariant last |
9441 | unless both operands are invariants. */ | |
9442 | ||
9443 | rtx | |
0c20a65f | 9444 | get_condition_for_loop (const struct loop *loop, rtx x) |
b4ad7b23 | 9445 | { |
ec6ec6aa | 9446 | rtx comparison = get_condition (x, (rtx*) 0, false); |
b4ad7b23 RS |
9447 | |
9448 | if (comparison == 0 | |
0534b804 MH |
9449 | || ! loop_invariant_p (loop, XEXP (comparison, 0)) |
9450 | || loop_invariant_p (loop, XEXP (comparison, 1))) | |
b4ad7b23 RS |
9451 | return comparison; |
9452 | ||
38a448ca RH |
9453 | return gen_rtx_fmt_ee (swap_condition (GET_CODE (comparison)), VOIDmode, |
9454 | XEXP (comparison, 1), XEXP (comparison, 0)); | |
b4ad7b23 | 9455 | } |
8c660648 | 9456 | |
2a1777af | 9457 | /* Scan the function and determine whether it has indirect (computed) jumps. |
8c660648 | 9458 | |
2a1777af JL |
9459 | This is taken mostly from flow.c; similar code exists elsewhere |
9460 | in the compiler. It may be useful to put this into rtlanal.c. */ | |
8c660648 | 9461 | static int |
0c20a65f | 9462 | indirect_jump_in_function_p (rtx start) |
8c660648 JL |
9463 | { |
9464 | rtx insn; | |
8c660648 | 9465 | |
2a1777af JL |
9466 | for (insn = start; insn; insn = NEXT_INSN (insn)) |
9467 | if (computed_jump_p (insn)) | |
9468 | return 1; | |
7019d00e L |
9469 | |
9470 | return 0; | |
8c660648 | 9471 | } |
41a972a9 MM |
9472 | |
9473 | /* Add MEM to the LOOP_MEMS array, if appropriate. See the | |
9474 | documentation for LOOP_MEMS for the definition of `appropriate'. | |
9475 | This function is called from prescan_loop via for_each_rtx. */ | |
9476 | ||
9477 | static int | |
0c20a65f | 9478 | insert_loop_mem (rtx *mem, void *data ATTRIBUTE_UNUSED) |
41a972a9 | 9479 | { |
afa1738b | 9480 | struct loop_info *loop_info = data; |
41a972a9 MM |
9481 | int i; |
9482 | rtx m = *mem; | |
9483 | ||
9484 | if (m == NULL_RTX) | |
9485 | return 0; | |
9486 | ||
9487 | switch (GET_CODE (m)) | |
9488 | { | |
9489 | case MEM: | |
9490 | break; | |
9491 | ||
27114460 RH |
9492 | case CLOBBER: |
9493 | /* We're not interested in MEMs that are only clobbered. */ | |
9494 | return -1; | |
9495 | ||
41a972a9 MM |
9496 | case CONST_DOUBLE: |
9497 | /* We're not interested in the MEM associated with a | |
9498 | CONST_DOUBLE, so there's no need to traverse into this. */ | |
9499 | return -1; | |
9500 | ||
4ce580a2 RE |
9501 | case EXPR_LIST: |
9502 | /* We're not interested in any MEMs that only appear in notes. */ | |
9503 | return -1; | |
9504 | ||
41a972a9 MM |
9505 | default: |
9506 | /* This is not a MEM. */ | |
9507 | return 0; | |
9508 | } | |
9509 | ||
9510 | /* See if we've already seen this MEM. */ | |
afa1738b MH |
9511 | for (i = 0; i < loop_info->mems_idx; ++i) |
9512 | if (rtx_equal_p (m, loop_info->mems[i].mem)) | |
41a972a9 | 9513 | { |
afa1738b | 9514 | if (GET_MODE (m) != GET_MODE (loop_info->mems[i].mem)) |
41a972a9 MM |
9515 | /* The modes of the two memory accesses are different. If |
9516 | this happens, something tricky is going on, and we just | |
9517 | don't optimize accesses to this MEM. */ | |
afa1738b | 9518 | loop_info->mems[i].optimize = 0; |
41a972a9 MM |
9519 | |
9520 | return 0; | |
9521 | } | |
9522 | ||
9523 | /* Resize the array, if necessary. */ | |
afa1738b | 9524 | if (loop_info->mems_idx == loop_info->mems_allocated) |
41a972a9 | 9525 | { |
afa1738b MH |
9526 | if (loop_info->mems_allocated != 0) |
9527 | loop_info->mems_allocated *= 2; | |
41a972a9 | 9528 | else |
afa1738b | 9529 | loop_info->mems_allocated = 32; |
41a972a9 | 9530 | |
703ad42b KG |
9531 | loop_info->mems = xrealloc (loop_info->mems, |
9532 | loop_info->mems_allocated * sizeof (loop_mem_info)); | |
41a972a9 MM |
9533 | } |
9534 | ||
9535 | /* Actually insert the MEM. */ | |
afa1738b | 9536 | loop_info->mems[loop_info->mems_idx].mem = m; |
41a972a9 MM |
9537 | /* We can't hoist this MEM out of the loop if it's a BLKmode MEM |
9538 | because we can't put it in a register. We still store it in the | |
9539 | table, though, so that if we see the same address later, but in a | |
9540 | non-BLK mode, we'll not think we can optimize it at that point. */ | |
afa1738b MH |
9541 | loop_info->mems[loop_info->mems_idx].optimize = (GET_MODE (m) != BLKmode); |
9542 | loop_info->mems[loop_info->mems_idx].reg = NULL_RTX; | |
9543 | ++loop_info->mems_idx; | |
8deb8e2c MM |
9544 | |
9545 | return 0; | |
41a972a9 MM |
9546 | } |
9547 | ||
1d7ae250 MH |
9548 | |
9549 | /* Allocate REGS->ARRAY or reallocate it if it is too small. | |
9550 | ||
9551 | Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each | |
9552 | register that is modified by an insn between FROM and TO. If the | |
9553 | value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or | |
9554 | more, stop incrementing it, to avoid overflow. | |
9555 | ||
9556 | Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which | |
9557 | register I is used, if it is only used once. Otherwise, it is set | |
9558 | to 0 (for no uses) or const0_rtx for more than one use. This | |
9559 | parameter may be zero, in which case this processing is not done. | |
9560 | ||
9561 | Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not | |
28680540 | 9562 | optimize register I. */ |
41a972a9 MM |
9563 | |
9564 | static void | |
0c20a65f | 9565 | loop_regs_scan (const struct loop *loop, int extra_size) |
41a972a9 | 9566 | { |
1ecd860b | 9567 | struct loop_regs *regs = LOOP_REGS (loop); |
1d7ae250 MH |
9568 | int old_nregs; |
9569 | /* last_set[n] is nonzero iff reg n has been set in the current | |
9570 | basic block. In that case, it is the insn that last set reg n. */ | |
9571 | rtx *last_set; | |
9572 | rtx insn; | |
1d7ae250 | 9573 | int i; |
41a972a9 | 9574 | |
1d7ae250 MH |
9575 | old_nregs = regs->num; |
9576 | regs->num = max_reg_num (); | |
e6fcb60d | 9577 | |
1d7ae250 MH |
9578 | /* Grow the regs array if not allocated or too small. */ |
9579 | if (regs->num >= regs->size) | |
41a972a9 | 9580 | { |
1d7ae250 | 9581 | regs->size = regs->num + extra_size; |
6b8c9327 | 9582 | |
703ad42b | 9583 | regs->array = xrealloc (regs->array, regs->size * sizeof (*regs->array)); |
1d7ae250 MH |
9584 | |
9585 | /* Zero the new elements. */ | |
9586 | memset (regs->array + old_nregs, 0, | |
9587 | (regs->size - old_nregs) * sizeof (*regs->array)); | |
9588 | } | |
41a972a9 | 9589 | |
1d7ae250 MH |
9590 | /* Clear previously scanned fields but do not clear n_times_set. */ |
9591 | for (i = 0; i < old_nregs; i++) | |
9592 | { | |
9593 | regs->array[i].set_in_loop = 0; | |
9594 | regs->array[i].may_not_optimize = 0; | |
9595 | regs->array[i].single_usage = NULL_RTX; | |
9596 | } | |
9597 | ||
703ad42b | 9598 | last_set = xcalloc (regs->num, sizeof (rtx)); |
f1d4ac80 | 9599 | |
1d7ae250 MH |
9600 | /* Scan the loop, recording register usage. */ |
9601 | for (insn = loop->top ? loop->top : loop->start; insn != loop->end; | |
9602 | insn = NEXT_INSN (insn)) | |
9603 | { | |
9604 | if (INSN_P (insn)) | |
f1d4ac80 | 9605 | { |
1d7ae250 MH |
9606 | /* Record registers that have exactly one use. */ |
9607 | find_single_use_in_loop (regs, insn, PATTERN (insn)); | |
587f56c2 | 9608 | |
1d7ae250 MH |
9609 | /* Include uses in REG_EQUAL notes. */ |
9610 | if (REG_NOTES (insn)) | |
9611 | find_single_use_in_loop (regs, insn, REG_NOTES (insn)); | |
41a972a9 | 9612 | |
1d7ae250 MH |
9613 | if (GET_CODE (PATTERN (insn)) == SET |
9614 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
9615 | count_one_set (regs, insn, PATTERN (insn), last_set); | |
9616 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
9617 | { | |
b3694847 | 9618 | int i; |
1d7ae250 MH |
9619 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
9620 | count_one_set (regs, insn, XVECEXP (PATTERN (insn), 0, i), | |
9621 | last_set); | |
9622 | } | |
8deb8e2c | 9623 | } |
41a972a9 | 9624 | |
1d7ae250 MH |
9625 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN) |
9626 | memset (last_set, 0, regs->num * sizeof (rtx)); | |
2d34c587 UW |
9627 | |
9628 | /* Invalidate all registers used for function argument passing. | |
9629 | We check rtx_varies_p for the same reason as below, to allow | |
9630 | optimizing PIC calculations. */ | |
9631 | if (GET_CODE (insn) == CALL_INSN) | |
9632 | { | |
9633 | rtx link; | |
0c20a65f AJ |
9634 | for (link = CALL_INSN_FUNCTION_USAGE (insn); |
9635 | link; | |
2d34c587 UW |
9636 | link = XEXP (link, 1)) |
9637 | { | |
9638 | rtx op, reg; | |
9639 | ||
9640 | if (GET_CODE (op = XEXP (link, 0)) == USE | |
9641 | && GET_CODE (reg = XEXP (op, 0)) == REG | |
9642 | && rtx_varies_p (reg, 1)) | |
9643 | regs->array[REGNO (reg)].may_not_optimize = 1; | |
9644 | } | |
9645 | } | |
1d7ae250 | 9646 | } |
41a972a9 | 9647 | |
bc532bf7 SC |
9648 | /* Invalidate all hard registers clobbered by calls. With one exception: |
9649 | a call-clobbered PIC register is still function-invariant for our | |
9650 | purposes, since we can hoist any PIC calculations out of the loop. | |
9651 | Thus the call to rtx_varies_p. */ | |
9652 | if (LOOP_INFO (loop)->has_call) | |
9653 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
9654 | if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i) | |
603b4b92 | 9655 | && rtx_varies_p (regno_reg_rtx[i], 1)) |
e11e816e KH |
9656 | { |
9657 | regs->array[i].may_not_optimize = 1; | |
9658 | regs->array[i].set_in_loop = 1; | |
9659 | } | |
e6fcb60d | 9660 | |
dd0208b9 | 9661 | #ifdef AVOID_CCMODE_COPIES |
1d7ae250 MH |
9662 | /* Don't try to move insns which set CC registers if we should not |
9663 | create CCmode register copies. */ | |
9664 | for (i = regs->num - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
9665 | if (GET_MODE_CLASS (GET_MODE (regno_reg_rtx[i])) == MODE_CC) | |
9666 | regs->array[i].may_not_optimize = 1; | |
dd0208b9 | 9667 | #endif |
6b8c9327 | 9668 | |
1d7ae250 MH |
9669 | /* Set regs->array[I].n_times_set for the new registers. */ |
9670 | for (i = old_nregs; i < regs->num; i++) | |
9671 | regs->array[i].n_times_set = regs->array[i].set_in_loop; | |
dd0208b9 | 9672 | |
1d7ae250 | 9673 | free (last_set); |
41a972a9 MM |
9674 | } |
9675 | ||
28680540 MM |
9676 | /* Returns the number of real INSNs in the LOOP. */ |
9677 | ||
9678 | static int | |
0c20a65f | 9679 | count_insns_in_loop (const struct loop *loop) |
28680540 MM |
9680 | { |
9681 | int count = 0; | |
9682 | rtx insn; | |
9683 | ||
9684 | for (insn = loop->top ? loop->top : loop->start; insn != loop->end; | |
9685 | insn = NEXT_INSN (insn)) | |
9686 | if (INSN_P (insn)) | |
9687 | ++count; | |
9688 | ||
9689 | return count; | |
9690 | } | |
1d7ae250 | 9691 | |
a2be868f | 9692 | /* Move MEMs into registers for the duration of the loop. */ |
41a972a9 MM |
9693 | |
9694 | static void | |
0c20a65f | 9695 | load_mems (const struct loop *loop) |
41a972a9 | 9696 | { |
afa1738b | 9697 | struct loop_info *loop_info = LOOP_INFO (loop); |
1ecd860b | 9698 | struct loop_regs *regs = LOOP_REGS (loop); |
41a972a9 MM |
9699 | int maybe_never = 0; |
9700 | int i; | |
1757e774 | 9701 | rtx p, prev_ebb_head; |
41a972a9 | 9702 | rtx label = NULL_RTX; |
48c4d691 | 9703 | rtx end_label; |
328f4006 BS |
9704 | /* Nonzero if the next instruction may never be executed. */ |
9705 | int next_maybe_never = 0; | |
616fde53 | 9706 | unsigned int last_max_reg = max_reg_num (); |
41a972a9 | 9707 | |
afa1738b | 9708 | if (loop_info->mems_idx == 0) |
328f4006 | 9709 | return; |
41a972a9 | 9710 | |
48c4d691 JJ |
9711 | /* We cannot use next_label here because it skips over normal insns. */ |
9712 | end_label = next_nonnote_insn (loop->end); | |
9713 | if (end_label && GET_CODE (end_label) != CODE_LABEL) | |
9714 | end_label = NULL_RTX; | |
eab5c70a | 9715 | |
48c4d691 JJ |
9716 | /* Check to see if it's possible that some instructions in the loop are |
9717 | never executed. Also check if there is a goto out of the loop other | |
9718 | than right after the end of the loop. */ | |
e6fcb60d | 9719 | for (p = next_insn_in_loop (loop, loop->scan_start); |
17e2b3cb | 9720 | p != NULL_RTX; |
a2be868f | 9721 | p = next_insn_in_loop (loop, p)) |
328f4006 BS |
9722 | { |
9723 | if (GET_CODE (p) == CODE_LABEL) | |
9724 | maybe_never = 1; | |
9725 | else if (GET_CODE (p) == JUMP_INSN | |
9726 | /* If we enter the loop in the middle, and scan | |
9727 | around to the beginning, don't set maybe_never | |
9728 | for that. This must be an unconditional jump, | |
9729 | otherwise the code at the top of the loop might | |
9730 | never be executed. Unconditional jumps are | |
9731 | followed a by barrier then loop end. */ | |
e6fcb60d | 9732 | && ! (GET_CODE (p) == JUMP_INSN |
a2be868f MH |
9733 | && JUMP_LABEL (p) == loop->top |
9734 | && NEXT_INSN (NEXT_INSN (p)) == loop->end | |
7f1c097d | 9735 | && any_uncondjump_p (p))) |
41a972a9 | 9736 | { |
48c4d691 JJ |
9737 | /* If this is a jump outside of the loop but not right |
9738 | after the end of the loop, we would have to emit new fixup | |
9739 | sequences for each such label. */ | |
13c502cd MM |
9740 | if (/* If we can't tell where control might go when this |
9741 | JUMP_INSN is executed, we must be conservative. */ | |
9742 | !JUMP_LABEL (p) | |
9743 | || (JUMP_LABEL (p) != end_label | |
9744 | && (INSN_UID (JUMP_LABEL (p)) >= max_uid_for_loop | |
9745 | || INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (loop->start) | |
9746 | || INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (loop->end)))) | |
48c4d691 JJ |
9747 | return; |
9748 | ||
7f1c097d | 9749 | if (!any_condjump_p (p)) |
328f4006 | 9750 | /* Something complicated. */ |
41a972a9 | 9751 | maybe_never = 1; |
328f4006 BS |
9752 | else |
9753 | /* If there are any more instructions in the loop, they | |
9754 | might not be reached. */ | |
e6fcb60d KH |
9755 | next_maybe_never = 1; |
9756 | } | |
328f4006 BS |
9757 | else if (next_maybe_never) |
9758 | maybe_never = 1; | |
9759 | } | |
9760 | ||
48c4d691 JJ |
9761 | /* Find start of the extended basic block that enters the loop. */ |
9762 | for (p = loop->start; | |
9763 | PREV_INSN (p) && GET_CODE (p) != CODE_LABEL; | |
9764 | p = PREV_INSN (p)) | |
9765 | ; | |
1757e774 | 9766 | prev_ebb_head = p; |
48c4d691 JJ |
9767 | |
9768 | cselib_init (); | |
9769 | ||
9770 | /* Build table of mems that get set to constant values before the | |
9771 | loop. */ | |
9772 | for (; p != loop->start; p = NEXT_INSN (p)) | |
9773 | cselib_process_insn (p); | |
9774 | ||
328f4006 | 9775 | /* Actually move the MEMs. */ |
afa1738b | 9776 | for (i = 0; i < loop_info->mems_idx; ++i) |
328f4006 | 9777 | { |
d2335c24 MH |
9778 | regset_head load_copies; |
9779 | regset_head store_copies; | |
328f4006 BS |
9780 | int written = 0; |
9781 | rtx reg; | |
afa1738b | 9782 | rtx mem = loop_info->mems[i].mem; |
328f4006 | 9783 | rtx mem_list_entry; |
41a972a9 | 9784 | |
e6fcb60d | 9785 | if (MEM_VOLATILE_P (mem) |
0534b804 | 9786 | || loop_invariant_p (loop, XEXP (mem, 0)) != 1) |
328f4006 | 9787 | /* There's no telling whether or not MEM is modified. */ |
afa1738b | 9788 | loop_info->mems[i].optimize = 0; |
328f4006 BS |
9789 | |
9790 | /* Go through the MEMs written to in the loop to see if this | |
9791 | one is aliased by one of them. */ | |
afa1738b | 9792 | mem_list_entry = loop_info->store_mems; |
328f4006 | 9793 | while (mem_list_entry) |
41a972a9 | 9794 | { |
328f4006 BS |
9795 | if (rtx_equal_p (mem, XEXP (mem_list_entry, 0))) |
9796 | written = 1; | |
9797 | else if (true_dependence (XEXP (mem_list_entry, 0), VOIDmode, | |
9798 | mem, rtx_varies_p)) | |
41a972a9 | 9799 | { |
328f4006 | 9800 | /* MEM is indeed aliased by this store. */ |
afa1738b | 9801 | loop_info->mems[i].optimize = 0; |
328f4006 | 9802 | break; |
41a972a9 | 9803 | } |
328f4006 BS |
9804 | mem_list_entry = XEXP (mem_list_entry, 1); |
9805 | } | |
f0b60c1c SM |
9806 | |
9807 | if (flag_float_store && written | |
9808 | && GET_MODE_CLASS (GET_MODE (mem)) == MODE_FLOAT) | |
afa1738b | 9809 | loop_info->mems[i].optimize = 0; |
e6fcb60d | 9810 | |
328f4006 | 9811 | /* If this MEM is written to, we must be sure that there |
e6fcb60d | 9812 | are no reads from another MEM that aliases this one. */ |
afa1738b | 9813 | if (loop_info->mems[i].optimize && written) |
328f4006 BS |
9814 | { |
9815 | int j; | |
41a972a9 | 9816 | |
afa1738b | 9817 | for (j = 0; j < loop_info->mems_idx; ++j) |
328f4006 BS |
9818 | { |
9819 | if (j == i) | |
9820 | continue; | |
9821 | else if (true_dependence (mem, | |
9822 | VOIDmode, | |
afa1738b | 9823 | loop_info->mems[j].mem, |
328f4006 | 9824 | rtx_varies_p)) |
41a972a9 | 9825 | { |
afa1738b | 9826 | /* It's not safe to hoist loop_info->mems[i] out of |
328f4006 | 9827 | the loop because writes to it might not be |
afa1738b MH |
9828 | seen by reads from loop_info->mems[j]. */ |
9829 | loop_info->mems[i].optimize = 0; | |
328f4006 | 9830 | break; |
41a972a9 MM |
9831 | } |
9832 | } | |
328f4006 | 9833 | } |
41a972a9 | 9834 | |
328f4006 BS |
9835 | if (maybe_never && may_trap_p (mem)) |
9836 | /* We can't access the MEM outside the loop; it might | |
9837 | cause a trap that wouldn't have happened otherwise. */ | |
afa1738b | 9838 | loop_info->mems[i].optimize = 0; |
e6fcb60d | 9839 | |
afa1738b | 9840 | if (!loop_info->mems[i].optimize) |
328f4006 BS |
9841 | /* We thought we were going to lift this MEM out of the |
9842 | loop, but later discovered that we could not. */ | |
9843 | continue; | |
41a972a9 | 9844 | |
d2335c24 MH |
9845 | INIT_REG_SET (&load_copies); |
9846 | INIT_REG_SET (&store_copies); | |
c29f60c0 | 9847 | |
328f4006 BS |
9848 | /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in |
9849 | order to keep scan_loop from moving stores to this MEM | |
9850 | out of the loop just because this REG is neither a | |
9851 | user-variable nor used in the loop test. */ | |
9852 | reg = gen_reg_rtx (GET_MODE (mem)); | |
9853 | REG_USERVAR_P (reg) = 1; | |
afa1738b | 9854 | loop_info->mems[i].reg = reg; |
328f4006 BS |
9855 | |
9856 | /* Now, replace all references to the MEM with the | |
1757e774 | 9857 | corresponding pseudos. */ |
c29f60c0 | 9858 | maybe_never = 0; |
a2be868f | 9859 | for (p = next_insn_in_loop (loop, loop->scan_start); |
328f4006 | 9860 | p != NULL_RTX; |
a2be868f | 9861 | p = next_insn_in_loop (loop, p)) |
328f4006 | 9862 | { |
2c3c49de | 9863 | if (INSN_P (p)) |
c29f60c0 | 9864 | { |
d2335c24 MH |
9865 | rtx set; |
9866 | ||
9867 | set = single_set (p); | |
9868 | ||
c29f60c0 BS |
9869 | /* See if this copies the mem into a register that isn't |
9870 | modified afterwards. We'll try to do copy propagation | |
9871 | a little further on. */ | |
c29f60c0 BS |
9872 | if (set |
9873 | /* @@@ This test is _way_ too conservative. */ | |
9874 | && ! maybe_never | |
9875 | && GET_CODE (SET_DEST (set)) == REG | |
9876 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER | |
9877 | && REGNO (SET_DEST (set)) < last_max_reg | |
f1d4ac80 | 9878 | && regs->array[REGNO (SET_DEST (set))].n_times_set == 1 |
d2335c24 MH |
9879 | && rtx_equal_p (SET_SRC (set), mem)) |
9880 | SET_REGNO_REG_SET (&load_copies, REGNO (SET_DEST (set))); | |
9881 | ||
fd5d5b07 | 9882 | /* See if this copies the mem from a register that isn't |
d2335c24 MH |
9883 | modified afterwards. We'll try to remove the |
9884 | redundant copy later on by doing a little register | |
9885 | renaming and copy propagation. This will help | |
9886 | to untangle things for the BIV detection code. */ | |
fd5d5b07 KH |
9887 | if (set |
9888 | && ! maybe_never | |
9889 | && GET_CODE (SET_SRC (set)) == REG | |
9890 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER | |
9891 | && REGNO (SET_SRC (set)) < last_max_reg | |
f1d4ac80 | 9892 | && regs->array[REGNO (SET_SRC (set))].n_times_set == 1 |
fd5d5b07 KH |
9893 | && rtx_equal_p (SET_DEST (set), mem)) |
9894 | SET_REGNO_REG_SET (&store_copies, REGNO (SET_SRC (set))); | |
9895 | ||
fcae219a R |
9896 | /* If this is a call which uses / clobbers this memory |
9897 | location, we must not change the interface here. */ | |
9898 | if (GET_CODE (p) == CALL_INSN | |
9899 | && reg_mentioned_p (loop_info->mems[i].mem, | |
9900 | CALL_INSN_FUNCTION_USAGE (p))) | |
9901 | { | |
9902 | cancel_changes (0); | |
9903 | loop_info->mems[i].optimize = 0; | |
9904 | break; | |
9905 | } | |
9906 | else | |
9907 | /* Replace the memory reference with the shadow register. */ | |
9908 | replace_loop_mems (p, loop_info->mems[i].mem, | |
e81eb37f | 9909 | loop_info->mems[i].reg, written); |
c29f60c0 BS |
9910 | } |
9911 | ||
9912 | if (GET_CODE (p) == CODE_LABEL | |
9913 | || GET_CODE (p) == JUMP_INSN) | |
9914 | maybe_never = 1; | |
328f4006 | 9915 | } |
41a972a9 | 9916 | |
fcae219a R |
9917 | if (! loop_info->mems[i].optimize) |
9918 | ; /* We found we couldn't do the replacement, so do nothing. */ | |
9919 | else if (! apply_change_group ()) | |
328f4006 | 9920 | /* We couldn't replace all occurrences of the MEM. */ |
afa1738b | 9921 | loop_info->mems[i].optimize = 0; |
328f4006 BS |
9922 | else |
9923 | { | |
0534b804 | 9924 | /* Load the memory immediately before LOOP->START, which is |
328f4006 | 9925 | the NOTE_LOOP_BEG. */ |
eab5c70a BS |
9926 | cselib_val *e = cselib_lookup (mem, VOIDmode, 0); |
9927 | rtx set; | |
9928 | rtx best = mem; | |
9929 | int j; | |
9930 | struct elt_loc_list *const_equiv = 0; | |
9931 | ||
9932 | if (e) | |
9933 | { | |
9934 | struct elt_loc_list *equiv; | |
9935 | struct elt_loc_list *best_equiv = 0; | |
9936 | for (equiv = e->locs; equiv; equiv = equiv->next) | |
9937 | { | |
9938 | if (CONSTANT_P (equiv->loc)) | |
9939 | const_equiv = equiv; | |
28b6b9b2 | 9940 | else if (GET_CODE (equiv->loc) == REG |
1757e774 | 9941 | /* Extending hard register lifetimes causes crash |
28b6b9b2 JH |
9942 | on SRC targets. Doing so on non-SRC is |
9943 | probably also not good idea, since we most | |
9944 | probably have pseudoregister equivalence as | |
9945 | well. */ | |
9946 | && REGNO (equiv->loc) >= FIRST_PSEUDO_REGISTER) | |
eab5c70a BS |
9947 | best_equiv = equiv; |
9948 | } | |
9949 | /* Use the constant equivalence if that is cheap enough. */ | |
9950 | if (! best_equiv) | |
9951 | best_equiv = const_equiv; | |
9952 | else if (const_equiv | |
9953 | && (rtx_cost (const_equiv->loc, SET) | |
9954 | <= rtx_cost (best_equiv->loc, SET))) | |
9955 | { | |
9956 | best_equiv = const_equiv; | |
9957 | const_equiv = 0; | |
9958 | } | |
9959 | ||
9960 | /* If best_equiv is nonzero, we know that MEM is set to a | |
9961 | constant or register before the loop. We will use this | |
9962 | knowledge to initialize the shadow register with that | |
9963 | constant or reg rather than by loading from MEM. */ | |
9964 | if (best_equiv) | |
9965 | best = copy_rtx (best_equiv->loc); | |
9966 | } | |
1757e774 | 9967 | |
eab5c70a | 9968 | set = gen_move_insn (reg, best); |
804a718a | 9969 | set = loop_insn_hoist (loop, set); |
1757e774 BS |
9970 | if (REG_P (best)) |
9971 | { | |
9972 | for (p = prev_ebb_head; p != loop->start; p = NEXT_INSN (p)) | |
9973 | if (REGNO_LAST_UID (REGNO (best)) == INSN_UID (p)) | |
9974 | { | |
9975 | REGNO_LAST_UID (REGNO (best)) = INSN_UID (set); | |
9976 | break; | |
9977 | } | |
9978 | } | |
9979 | ||
eab5c70a | 9980 | if (const_equiv) |
3d238248 | 9981 | set_unique_reg_note (set, REG_EQUAL, copy_rtx (const_equiv->loc)); |
41a972a9 | 9982 | |
328f4006 BS |
9983 | if (written) |
9984 | { | |
9985 | if (label == NULL_RTX) | |
41a972a9 | 9986 | { |
328f4006 | 9987 | label = gen_label_rtx (); |
a2be868f | 9988 | emit_label_after (label, loop->end); |
41a972a9 MM |
9989 | } |
9990 | ||
328f4006 BS |
9991 | /* Store the memory immediately after END, which is |
9992 | the NOTE_LOOP_END. */ | |
e6fcb60d | 9993 | set = gen_move_insn (copy_rtx (mem), reg); |
86e21212 | 9994 | loop_insn_emit_after (loop, 0, label, set); |
328f4006 BS |
9995 | } |
9996 | ||
9997 | if (loop_dump_stream) | |
9998 | { | |
9999 | fprintf (loop_dump_stream, "Hoisted regno %d %s from ", | |
10000 | REGNO (reg), (written ? "r/w" : "r/o")); | |
10001 | print_rtl (loop_dump_stream, mem); | |
10002 | fputc ('\n', loop_dump_stream); | |
41a972a9 | 10003 | } |
c29f60c0 BS |
10004 | |
10005 | /* Attempt a bit of copy propagation. This helps untangle the | |
10006 | data flow, and enables {basic,general}_induction_var to find | |
10007 | more bivs/givs. */ | |
10008 | EXECUTE_IF_SET_IN_REG_SET | |
d2335c24 | 10009 | (&load_copies, FIRST_PSEUDO_REGISTER, j, |
c29f60c0 | 10010 | { |
d2335c24 | 10011 | try_copy_prop (loop, reg, j); |
c29f60c0 | 10012 | }); |
d2335c24 MH |
10013 | CLEAR_REG_SET (&load_copies); |
10014 | ||
10015 | EXECUTE_IF_SET_IN_REG_SET | |
10016 | (&store_copies, FIRST_PSEUDO_REGISTER, j, | |
10017 | { | |
10018 | try_swap_copy_prop (loop, reg, j); | |
10019 | }); | |
10020 | CLEAR_REG_SET (&store_copies); | |
41a972a9 MM |
10021 | } |
10022 | } | |
10023 | ||
1b24cd79 RS |
10024 | /* Now, we need to replace all references to the previous exit |
10025 | label with the new one. */ | |
48c4d691 | 10026 | if (label != NULL_RTX && end_label != NULL_RTX) |
1b24cd79 RS |
10027 | for (p = loop->start; p != loop->end; p = NEXT_INSN (p)) |
10028 | if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == end_label) | |
10029 | redirect_jump (p, label, false); | |
eab5c70a BS |
10030 | |
10031 | cselib_finish (); | |
41a972a9 MM |
10032 | } |
10033 | ||
8571e492 BS |
10034 | /* For communication between note_reg_stored and its caller. */ |
10035 | struct note_reg_stored_arg | |
10036 | { | |
10037 | int set_seen; | |
10038 | rtx reg; | |
10039 | }; | |
10040 | ||
10041 | /* Called via note_stores, record in SET_SEEN whether X, which is written, | |
10042 | is equal to ARG. */ | |
10043 | static void | |
0c20a65f | 10044 | note_reg_stored (rtx x, rtx setter ATTRIBUTE_UNUSED, void *arg) |
8571e492 | 10045 | { |
e6fcb60d | 10046 | struct note_reg_stored_arg *t = (struct note_reg_stored_arg *) arg; |
8571e492 BS |
10047 | if (t->reg == x) |
10048 | t->set_seen = 1; | |
10049 | } | |
10050 | ||
c29f60c0 BS |
10051 | /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT. |
10052 | There must be exactly one insn that sets this pseudo; it will be | |
10053 | deleted if all replacements succeed and we can prove that the register | |
0534b804 | 10054 | is not used after the loop. */ |
770ae6cc | 10055 | |
c29f60c0 | 10056 | static void |
0c20a65f | 10057 | try_copy_prop (const struct loop *loop, rtx replacement, unsigned int regno) |
c29f60c0 | 10058 | { |
8571e492 BS |
10059 | /* This is the reg that we are copying from. */ |
10060 | rtx reg_rtx = regno_reg_rtx[regno]; | |
c29f60c0 BS |
10061 | rtx init_insn = 0; |
10062 | rtx insn; | |
8571e492 BS |
10063 | /* These help keep track of whether we replaced all uses of the reg. */ |
10064 | int replaced_last = 0; | |
10065 | int store_is_first = 0; | |
10066 | ||
a2be868f | 10067 | for (insn = next_insn_in_loop (loop, loop->scan_start); |
c29f60c0 | 10068 | insn != NULL_RTX; |
a2be868f | 10069 | insn = next_insn_in_loop (loop, insn)) |
c29f60c0 BS |
10070 | { |
10071 | rtx set; | |
d42971c4 | 10072 | |
8571e492 BS |
10073 | /* Only substitute within one extended basic block from the initializing |
10074 | insn. */ | |
10075 | if (GET_CODE (insn) == CODE_LABEL && init_insn) | |
10076 | break; | |
d42971c4 | 10077 | |
2c3c49de | 10078 | if (! INSN_P (insn)) |
c29f60c0 | 10079 | continue; |
8571e492 BS |
10080 | |
10081 | /* Is this the initializing insn? */ | |
c29f60c0 BS |
10082 | set = single_set (insn); |
10083 | if (set | |
10084 | && GET_CODE (SET_DEST (set)) == REG | |
10085 | && REGNO (SET_DEST (set)) == regno) | |
10086 | { | |
10087 | if (init_insn) | |
10088 | abort (); | |
8571e492 | 10089 | |
c29f60c0 | 10090 | init_insn = insn; |
8571e492 BS |
10091 | if (REGNO_FIRST_UID (regno) == INSN_UID (insn)) |
10092 | store_is_first = 1; | |
10093 | } | |
10094 | ||
10095 | /* Only substitute after seeing the initializing insn. */ | |
10096 | if (init_insn && insn != init_insn) | |
e6fcb60d | 10097 | { |
8571e492 | 10098 | struct note_reg_stored_arg arg; |
8571e492 | 10099 | |
afa1738b | 10100 | replace_loop_regs (insn, reg_rtx, replacement); |
8571e492 BS |
10101 | if (REGNO_LAST_UID (regno) == INSN_UID (insn)) |
10102 | replaced_last = 1; | |
10103 | ||
10104 | /* Stop replacing when REPLACEMENT is modified. */ | |
10105 | arg.reg = replacement; | |
10106 | arg.set_seen = 0; | |
10107 | note_stores (PATTERN (insn), note_reg_stored, &arg); | |
10108 | if (arg.set_seen) | |
f1330226 JH |
10109 | { |
10110 | rtx note = find_reg_note (insn, REG_EQUAL, NULL); | |
10111 | ||
10112 | /* It is possible that we've turned previously valid REG_EQUAL to | |
10113 | invalid, as we change the REGNO to REPLACEMENT and unlike REGNO, | |
10114 | REPLACEMENT is modified, we get different meaning. */ | |
10115 | if (note && reg_mentioned_p (replacement, XEXP (note, 0))) | |
10116 | remove_note (insn, note); | |
10117 | break; | |
10118 | } | |
c29f60c0 | 10119 | } |
c29f60c0 BS |
10120 | } |
10121 | if (! init_insn) | |
10122 | abort (); | |
10123 | if (apply_change_group ()) | |
10124 | { | |
8571e492 BS |
10125 | if (loop_dump_stream) |
10126 | fprintf (loop_dump_stream, " Replaced reg %d", regno); | |
10127 | if (store_is_first && replaced_last) | |
c29f60c0 | 10128 | { |
e8c8470b MM |
10129 | rtx first; |
10130 | rtx retval_note; | |
10131 | ||
10132 | /* Assume we're just deleting INIT_INSN. */ | |
10133 | first = init_insn; | |
10134 | /* Look for REG_RETVAL note. If we're deleting the end of | |
10135 | the libcall sequence, the whole sequence can go. */ | |
10136 | retval_note = find_reg_note (init_insn, REG_RETVAL, NULL_RTX); | |
10137 | /* If we found a REG_RETVAL note, find the first instruction | |
10138 | in the sequence. */ | |
10139 | if (retval_note) | |
10140 | first = XEXP (retval_note, 0); | |
10141 | ||
10142 | /* Delete the instructions. */ | |
10143 | loop_delete_insns (first, init_insn); | |
c29f60c0 BS |
10144 | } |
10145 | if (loop_dump_stream) | |
8571e492 | 10146 | fprintf (loop_dump_stream, ".\n"); |
c29f60c0 BS |
10147 | } |
10148 | } | |
10149 | ||
e8c8470b MM |
10150 | /* Replace all the instructions from FIRST up to and including LAST |
10151 | with NOTE_INSN_DELETED notes. */ | |
10152 | ||
10153 | static void | |
0c20a65f | 10154 | loop_delete_insns (rtx first, rtx last) |
e8c8470b MM |
10155 | { |
10156 | while (1) | |
10157 | { | |
e8c8470b MM |
10158 | if (loop_dump_stream) |
10159 | fprintf (loop_dump_stream, ", deleting init_insn (%d)", | |
10160 | INSN_UID (first)); | |
ca6c03ca | 10161 | delete_insn (first); |
e8c8470b MM |
10162 | |
10163 | /* If this was the LAST instructions we're supposed to delete, | |
10164 | we're done. */ | |
10165 | if (first == last) | |
10166 | break; | |
10167 | ||
10168 | first = NEXT_INSN (first); | |
10169 | } | |
10170 | } | |
10171 | ||
d2335c24 MH |
10172 | /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within |
10173 | loop LOOP if the order of the sets of these registers can be | |
10174 | swapped. There must be exactly one insn within the loop that sets | |
10175 | this pseudo followed immediately by a move insn that sets | |
10176 | REPLACEMENT with REGNO. */ | |
10177 | static void | |
0c20a65f AJ |
10178 | try_swap_copy_prop (const struct loop *loop, rtx replacement, |
10179 | unsigned int regno) | |
d2335c24 MH |
10180 | { |
10181 | rtx insn; | |
616fde53 | 10182 | rtx set = NULL_RTX; |
d2335c24 MH |
10183 | unsigned int new_regno; |
10184 | ||
10185 | new_regno = REGNO (replacement); | |
10186 | ||
10187 | for (insn = next_insn_in_loop (loop, loop->scan_start); | |
10188 | insn != NULL_RTX; | |
10189 | insn = next_insn_in_loop (loop, insn)) | |
10190 | { | |
10191 | /* Search for the insn that copies REGNO to NEW_REGNO? */ | |
616fde53 | 10192 | if (INSN_P (insn) |
d2335c24 MH |
10193 | && (set = single_set (insn)) |
10194 | && GET_CODE (SET_DEST (set)) == REG | |
10195 | && REGNO (SET_DEST (set)) == new_regno | |
10196 | && GET_CODE (SET_SRC (set)) == REG | |
10197 | && REGNO (SET_SRC (set)) == regno) | |
10198 | break; | |
10199 | } | |
10200 | ||
0ef52662 | 10201 | if (insn != NULL_RTX) |
d2335c24 MH |
10202 | { |
10203 | rtx prev_insn; | |
10204 | rtx prev_set; | |
fd5d5b07 | 10205 | |
d2335c24 MH |
10206 | /* Some DEF-USE info would come in handy here to make this |
10207 | function more general. For now, just check the previous insn | |
10208 | which is the most likely candidate for setting REGNO. */ | |
fd5d5b07 | 10209 | |
d2335c24 | 10210 | prev_insn = PREV_INSN (insn); |
fd5d5b07 | 10211 | |
616fde53 | 10212 | if (INSN_P (insn) |
d2335c24 MH |
10213 | && (prev_set = single_set (prev_insn)) |
10214 | && GET_CODE (SET_DEST (prev_set)) == REG | |
10215 | && REGNO (SET_DEST (prev_set)) == regno) | |
10216 | { | |
10217 | /* We have: | |
10218 | (set (reg regno) (expr)) | |
10219 | (set (reg new_regno) (reg regno)) | |
fd5d5b07 | 10220 | |
d2335c24 MH |
10221 | so try converting this to: |
10222 | (set (reg new_regno) (expr)) | |
10223 | (set (reg regno) (reg new_regno)) | |
10224 | ||
10225 | The former construct is often generated when a global | |
10226 | variable used for an induction variable is shadowed by a | |
10227 | register (NEW_REGNO). The latter construct improves the | |
10228 | chances of GIV replacement and BIV elimination. */ | |
10229 | ||
10230 | validate_change (prev_insn, &SET_DEST (prev_set), | |
10231 | replacement, 1); | |
10232 | validate_change (insn, &SET_DEST (set), | |
10233 | SET_SRC (set), 1); | |
10234 | validate_change (insn, &SET_SRC (set), | |
10235 | replacement, 1); | |
10236 | ||
10237 | if (apply_change_group ()) | |
10238 | { | |
10239 | if (loop_dump_stream) | |
fd5d5b07 KH |
10240 | fprintf (loop_dump_stream, |
10241 | " Swapped set of reg %d at %d with reg %d at %d.\n", | |
10242 | regno, INSN_UID (insn), | |
d2335c24 MH |
10243 | new_regno, INSN_UID (prev_insn)); |
10244 | ||
10245 | /* Update first use of REGNO. */ | |
10246 | if (REGNO_FIRST_UID (regno) == INSN_UID (prev_insn)) | |
10247 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
10248 | ||
10249 | /* Now perform copy propagation to hopefully | |
10250 | remove all uses of REGNO within the loop. */ | |
10251 | try_copy_prop (loop, replacement, regno); | |
10252 | } | |
10253 | } | |
10254 | } | |
10255 | } | |
10256 | ||
00dcfe80 AM |
10257 | /* Worker function for find_mem_in_note, called via for_each_rtx. */ |
10258 | ||
e81eb37f | 10259 | static int |
0c20a65f | 10260 | find_mem_in_note_1 (rtx *x, void *data) |
e81eb37f AM |
10261 | { |
10262 | if (*x != NULL_RTX && GET_CODE (*x) == MEM) | |
10263 | { | |
10264 | rtx *res = (rtx *) data; | |
10265 | *res = *x; | |
10266 | return 1; | |
10267 | } | |
10268 | return 0; | |
10269 | } | |
10270 | ||
00dcfe80 AM |
10271 | /* Returns the first MEM found in NOTE by depth-first search. */ |
10272 | ||
e81eb37f | 10273 | static rtx |
0c20a65f | 10274 | find_mem_in_note (rtx note) |
e81eb37f AM |
10275 | { |
10276 | if (note && for_each_rtx (¬e, find_mem_in_note_1, ¬e)) | |
10277 | return note; | |
10278 | return NULL_RTX; | |
10279 | } | |
0c20a65f | 10280 | |
41a972a9 | 10281 | /* Replace MEM with its associated pseudo register. This function is |
afa1738b MH |
10282 | called from load_mems via for_each_rtx. DATA is actually a pointer |
10283 | to a structure describing the instruction currently being scanned | |
41a972a9 MM |
10284 | and the MEM we are currently replacing. */ |
10285 | ||
10286 | static int | |
0c20a65f | 10287 | replace_loop_mem (rtx *mem, void *data) |
41a972a9 | 10288 | { |
fd5d5b07 | 10289 | loop_replace_args *args = (loop_replace_args *) data; |
41a972a9 MM |
10290 | rtx m = *mem; |
10291 | ||
10292 | if (m == NULL_RTX) | |
10293 | return 0; | |
10294 | ||
10295 | switch (GET_CODE (m)) | |
10296 | { | |
10297 | case MEM: | |
10298 | break; | |
10299 | ||
10300 | case CONST_DOUBLE: | |
10301 | /* We're not interested in the MEM associated with a | |
10302 | CONST_DOUBLE, so there's no need to traverse into one. */ | |
10303 | return -1; | |
10304 | ||
10305 | default: | |
10306 | /* This is not a MEM. */ | |
10307 | return 0; | |
10308 | } | |
10309 | ||
afa1738b | 10310 | if (!rtx_equal_p (args->match, m)) |
41a972a9 MM |
10311 | /* This is not the MEM we are currently replacing. */ |
10312 | return 0; | |
10313 | ||
41a972a9 | 10314 | /* Actually replace the MEM. */ |
afa1738b | 10315 | validate_change (args->insn, mem, args->replacement, 1); |
41a972a9 MM |
10316 | |
10317 | return 0; | |
10318 | } | |
10319 | ||
afa1738b | 10320 | static void |
0c20a65f | 10321 | replace_loop_mems (rtx insn, rtx mem, rtx reg, int written) |
fd5d5b07 | 10322 | { |
afa1738b MH |
10323 | loop_replace_args args; |
10324 | ||
10325 | args.insn = insn; | |
10326 | args.match = mem; | |
10327 | args.replacement = reg; | |
10328 | ||
10329 | for_each_rtx (&insn, replace_loop_mem, &args); | |
e81eb37f AM |
10330 | |
10331 | /* If we hoist a mem write out of the loop, then REG_EQUAL | |
10332 | notes referring to the mem are no longer valid. */ | |
10333 | if (written) | |
10334 | { | |
10335 | rtx note, sub; | |
10336 | rtx *link; | |
10337 | ||
10338 | for (link = ®_NOTES (insn); (note = *link); link = &XEXP (note, 1)) | |
10339 | { | |
10340 | if (REG_NOTE_KIND (note) == REG_EQUAL | |
10341 | && (sub = find_mem_in_note (note)) | |
10342 | && true_dependence (mem, VOIDmode, sub, rtx_varies_p)) | |
10343 | { | |
10344 | /* Remove the note. */ | |
10345 | validate_change (NULL_RTX, link, XEXP (note, 1), 1); | |
10346 | break; | |
10347 | } | |
10348 | } | |
10349 | } | |
afa1738b MH |
10350 | } |
10351 | ||
c29f60c0 | 10352 | /* Replace one register with another. Called through for_each_rtx; PX points |
fd5d5b07 | 10353 | to the rtx being scanned. DATA is actually a pointer to |
afa1738b | 10354 | a structure of arguments. */ |
c29f60c0 BS |
10355 | |
10356 | static int | |
0c20a65f | 10357 | replace_loop_reg (rtx *px, void *data) |
c29f60c0 BS |
10358 | { |
10359 | rtx x = *px; | |
fd5d5b07 | 10360 | loop_replace_args *args = (loop_replace_args *) data; |
c29f60c0 BS |
10361 | |
10362 | if (x == NULL_RTX) | |
10363 | return 0; | |
10364 | ||
afa1738b MH |
10365 | if (x == args->match) |
10366 | validate_change (args->insn, px, args->replacement, 1); | |
c29f60c0 BS |
10367 | |
10368 | return 0; | |
10369 | } | |
10370 | ||
afa1738b | 10371 | static void |
0c20a65f | 10372 | replace_loop_regs (rtx insn, rtx reg, rtx replacement) |
afa1738b MH |
10373 | { |
10374 | loop_replace_args args; | |
10375 | ||
10376 | args.insn = insn; | |
10377 | args.match = reg; | |
10378 | args.replacement = replacement; | |
10379 | ||
10380 | for_each_rtx (&insn, replace_loop_reg, &args); | |
10381 | } | |
6057c0e6 | 10382 | \f |
96a45535 MH |
10383 | /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB |
10384 | (ignored in the interim). */ | |
10385 | ||
10386 | static rtx | |
0c20a65f AJ |
10387 | loop_insn_emit_after (const struct loop *loop ATTRIBUTE_UNUSED, |
10388 | basic_block where_bb ATTRIBUTE_UNUSED, rtx where_insn, | |
10389 | rtx pattern) | |
96a45535 MH |
10390 | { |
10391 | return emit_insn_after (pattern, where_insn); | |
10392 | } | |
10393 | ||
10394 | ||
cc2902df | 10395 | /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN |
804a718a MH |
10396 | in basic block WHERE_BB (ignored in the interim) within the loop |
10397 | otherwise hoist PATTERN into the loop pre-header. */ | |
10398 | ||
86e21212 | 10399 | rtx |
0c20a65f AJ |
10400 | loop_insn_emit_before (const struct loop *loop, |
10401 | basic_block where_bb ATTRIBUTE_UNUSED, | |
10402 | rtx where_insn, rtx pattern) | |
804a718a MH |
10403 | { |
10404 | if (! where_insn) | |
10405 | return loop_insn_hoist (loop, pattern); | |
10406 | return emit_insn_before (pattern, where_insn); | |
10407 | } | |
10408 | ||
10409 | ||
86e21212 MH |
10410 | /* Emit call insn for PATTERN before WHERE_INSN in basic block |
10411 | WHERE_BB (ignored in the interim) within the loop. */ | |
10412 | ||
10413 | static rtx | |
0c20a65f AJ |
10414 | loop_call_insn_emit_before (const struct loop *loop ATTRIBUTE_UNUSED, |
10415 | basic_block where_bb ATTRIBUTE_UNUSED, | |
10416 | rtx where_insn, rtx pattern) | |
86e21212 MH |
10417 | { |
10418 | return emit_call_insn_before (pattern, where_insn); | |
10419 | } | |
10420 | ||
10421 | ||
804a718a MH |
10422 | /* Hoist insn for PATTERN into the loop pre-header. */ |
10423 | ||
10424 | rtx | |
0c20a65f | 10425 | loop_insn_hoist (const struct loop *loop, rtx pattern) |
804a718a MH |
10426 | { |
10427 | return loop_insn_emit_before (loop, 0, loop->start, pattern); | |
10428 | } | |
96a45535 MH |
10429 | |
10430 | ||
86e21212 MH |
10431 | /* Hoist call insn for PATTERN into the loop pre-header. */ |
10432 | ||
10433 | static rtx | |
0c20a65f | 10434 | loop_call_insn_hoist (const struct loop *loop, rtx pattern) |
86e21212 MH |
10435 | { |
10436 | return loop_call_insn_emit_before (loop, 0, loop->start, pattern); | |
10437 | } | |
10438 | ||
10439 | ||
96a45535 MH |
10440 | /* Sink insn for PATTERN after the loop end. */ |
10441 | ||
10442 | rtx | |
0c20a65f | 10443 | loop_insn_sink (const struct loop *loop, rtx pattern) |
96a45535 MH |
10444 | { |
10445 | return loop_insn_emit_before (loop, 0, loop->sink, pattern); | |
10446 | } | |
10447 | ||
e0bb17a8 | 10448 | /* bl->final_value can be either general_operand or PLUS of general_operand |
3d042e77 | 10449 | and constant. Emit sequence of instructions to load it into REG. */ |
74411039 | 10450 | static rtx |
0c20a65f | 10451 | gen_load_of_final_value (rtx reg, rtx final_value) |
74411039 JH |
10452 | { |
10453 | rtx seq; | |
10454 | start_sequence (); | |
10455 | final_value = force_operand (final_value, reg); | |
10456 | if (final_value != reg) | |
10457 | emit_move_insn (reg, final_value); | |
2f937369 | 10458 | seq = get_insns (); |
74411039 JH |
10459 | end_sequence (); |
10460 | return seq; | |
10461 | } | |
96a45535 MH |
10462 | |
10463 | /* If the loop has multiple exits, emit insn for PATTERN before the | |
10464 | loop to ensure that it will always be executed no matter how the | |
10465 | loop exits. Otherwise, emit the insn for PATTERN after the loop, | |
10466 | since this is slightly more efficient. */ | |
10467 | ||
10468 | static rtx | |
0c20a65f | 10469 | loop_insn_sink_or_swim (const struct loop *loop, rtx pattern) |
96a45535 MH |
10470 | { |
10471 | if (loop->exit_count) | |
10472 | return loop_insn_hoist (loop, pattern); | |
10473 | else | |
10474 | return loop_insn_sink (loop, pattern); | |
10475 | } | |
804a718a | 10476 | \f |
099f0f3f | 10477 | static void |
0c20a65f | 10478 | loop_ivs_dump (const struct loop *loop, FILE *file, int verbose) |
099f0f3f MH |
10479 | { |
10480 | struct iv_class *bl; | |
10481 | int iv_num = 0; | |
10482 | ||
10483 | if (! loop || ! file) | |
10484 | return; | |
10485 | ||
10486 | for (bl = LOOP_IVS (loop)->list; bl; bl = bl->next) | |
10487 | iv_num++; | |
10488 | ||
10489 | fprintf (file, "Loop %d: %d IV classes\n", loop->num, iv_num); | |
10490 | ||
10491 | for (bl = LOOP_IVS (loop)->list; bl; bl = bl->next) | |
10492 | { | |
10493 | loop_iv_class_dump (bl, file, verbose); | |
10494 | fputc ('\n', file); | |
10495 | } | |
10496 | } | |
10497 | ||
10498 | ||
10499 | static void | |
0c20a65f AJ |
10500 | loop_iv_class_dump (const struct iv_class *bl, FILE *file, |
10501 | int verbose ATTRIBUTE_UNUSED) | |
099f0f3f MH |
10502 | { |
10503 | struct induction *v; | |
10504 | rtx incr; | |
10505 | int i; | |
10506 | ||
10507 | if (! bl || ! file) | |
10508 | return; | |
10509 | ||
10510 | fprintf (file, "IV class for reg %d, benefit %d\n", | |
10511 | bl->regno, bl->total_benefit); | |
10512 | ||
10513 | fprintf (file, " Init insn %d", INSN_UID (bl->init_insn)); | |
10514 | if (bl->initial_value) | |
10515 | { | |
10516 | fprintf (file, ", init val: "); | |
10517 | print_simple_rtl (file, bl->initial_value); | |
10518 | } | |
10519 | if (bl->initial_test) | |
10520 | { | |
10521 | fprintf (file, ", init test: "); | |
10522 | print_simple_rtl (file, bl->initial_test); | |
10523 | } | |
10524 | fputc ('\n', file); | |
10525 | ||
10526 | if (bl->final_value) | |
10527 | { | |
10528 | fprintf (file, " Final val: "); | |
10529 | print_simple_rtl (file, bl->final_value); | |
10530 | fputc ('\n', file); | |
10531 | } | |
10532 | ||
10533 | if ((incr = biv_total_increment (bl))) | |
10534 | { | |
10535 | fprintf (file, " Total increment: "); | |
10536 | print_simple_rtl (file, incr); | |
10537 | fputc ('\n', file); | |
10538 | } | |
10539 | ||
10540 | /* List the increments. */ | |
10541 | for (i = 0, v = bl->biv; v; v = v->next_iv, i++) | |
10542 | { | |
10543 | fprintf (file, " Inc%d: insn %d, incr: ", i, INSN_UID (v->insn)); | |
10544 | print_simple_rtl (file, v->add_val); | |
10545 | fputc ('\n', file); | |
10546 | } | |
10547 | ||
10548 | /* List the givs. */ | |
10549 | for (i = 0, v = bl->giv; v; v = v->next_iv, i++) | |
10550 | { | |
6b8c9327 | 10551 | fprintf (file, " Giv%d: insn %d, benefit %d, ", |
099f0f3f MH |
10552 | i, INSN_UID (v->insn), v->benefit); |
10553 | if (v->giv_type == DEST_ADDR) | |
e11e816e | 10554 | print_simple_rtl (file, v->mem); |
099f0f3f | 10555 | else |
e11e816e | 10556 | print_simple_rtl (file, single_set (v->insn)); |
099f0f3f MH |
10557 | fputc ('\n', file); |
10558 | } | |
10559 | } | |
10560 | ||
10561 | ||
c804f3f8 | 10562 | static void |
0c20a65f | 10563 | loop_biv_dump (const struct induction *v, FILE *file, int verbose) |
c804f3f8 MH |
10564 | { |
10565 | if (! v || ! file) | |
10566 | return; | |
10567 | ||
10568 | fprintf (file, | |
10569 | "Biv %d: insn %d", | |
10570 | REGNO (v->dest_reg), INSN_UID (v->insn)); | |
10571 | fprintf (file, " const "); | |
10572 | print_simple_rtl (file, v->add_val); | |
10573 | ||
10574 | if (verbose && v->final_value) | |
10575 | { | |
6b8c9327 | 10576 | fputc ('\n', file); |
c804f3f8 MH |
10577 | fprintf (file, " final "); |
10578 | print_simple_rtl (file, v->final_value); | |
10579 | } | |
10580 | ||
10581 | fputc ('\n', file); | |
10582 | } | |
10583 | ||
10584 | ||
10585 | static void | |
0c20a65f | 10586 | loop_giv_dump (const struct induction *v, FILE *file, int verbose) |
c804f3f8 MH |
10587 | { |
10588 | if (! v || ! file) | |
10589 | return; | |
10590 | ||
10591 | if (v->giv_type == DEST_REG) | |
10592 | fprintf (file, "Giv %d: insn %d", | |
e11e816e | 10593 | REGNO (v->dest_reg), INSN_UID (v->insn)); |
c804f3f8 MH |
10594 | else |
10595 | fprintf (file, "Dest address: insn %d", | |
10596 | INSN_UID (v->insn)); | |
6b8c9327 | 10597 | |
c804f3f8 MH |
10598 | fprintf (file, " src reg %d benefit %d", |
10599 | REGNO (v->src_reg), v->benefit); | |
10600 | fprintf (file, " lifetime %d", | |
10601 | v->lifetime); | |
6b8c9327 | 10602 | |
c804f3f8 MH |
10603 | if (v->replaceable) |
10604 | fprintf (file, " replaceable"); | |
6b8c9327 | 10605 | |
c804f3f8 MH |
10606 | if (v->no_const_addval) |
10607 | fprintf (file, " ncav"); | |
6b8c9327 | 10608 | |
affd4f33 | 10609 | if (v->ext_dependent) |
c804f3f8 | 10610 | { |
affd4f33 | 10611 | switch (GET_CODE (v->ext_dependent)) |
c804f3f8 MH |
10612 | { |
10613 | case SIGN_EXTEND: | |
10614 | fprintf (file, " ext se"); | |
10615 | break; | |
10616 | case ZERO_EXTEND: | |
10617 | fprintf (file, " ext ze"); | |
10618 | break; | |
10619 | case TRUNCATE: | |
10620 | fprintf (file, " ext tr"); | |
505ddab6 | 10621 | break; |
c804f3f8 MH |
10622 | default: |
10623 | abort (); | |
10624 | } | |
10625 | } | |
10626 | ||
6b8c9327 | 10627 | fputc ('\n', file); |
c804f3f8 MH |
10628 | fprintf (file, " mult "); |
10629 | print_simple_rtl (file, v->mult_val); | |
10630 | ||
6b8c9327 | 10631 | fputc ('\n', file); |
c804f3f8 MH |
10632 | fprintf (file, " add "); |
10633 | print_simple_rtl (file, v->add_val); | |
10634 | ||
10635 | if (verbose && v->final_value) | |
10636 | { | |
6b8c9327 | 10637 | fputc ('\n', file); |
c804f3f8 MH |
10638 | fprintf (file, " final "); |
10639 | print_simple_rtl (file, v->final_value); | |
10640 | } | |
10641 | ||
6b8c9327 | 10642 | fputc ('\n', file); |
c804f3f8 MH |
10643 | } |
10644 | ||
10645 | ||
099f0f3f | 10646 | void |
0c20a65f | 10647 | debug_ivs (const struct loop *loop) |
099f0f3f MH |
10648 | { |
10649 | loop_ivs_dump (loop, stderr, 1); | |
10650 | } | |
10651 | ||
10652 | ||
10653 | void | |
0c20a65f | 10654 | debug_iv_class (const struct iv_class *bl) |
099f0f3f MH |
10655 | { |
10656 | loop_iv_class_dump (bl, stderr, 1); | |
10657 | } | |
10658 | ||
10659 | ||
c804f3f8 | 10660 | void |
0c20a65f | 10661 | debug_biv (const struct induction *v) |
c804f3f8 MH |
10662 | { |
10663 | loop_biv_dump (v, stderr, 1); | |
10664 | } | |
10665 | ||
10666 | ||
10667 | void | |
0c20a65f | 10668 | debug_giv (const struct induction *v) |
c804f3f8 MH |
10669 | { |
10670 | loop_giv_dump (v, stderr, 1); | |
10671 | } | |
10672 | ||
10673 | ||
6057c0e6 MH |
10674 | #define LOOP_BLOCK_NUM_1(INSN) \ |
10675 | ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1) | |
10676 | ||
10677 | /* The notes do not have an assigned block, so look at the next insn. */ | |
10678 | #define LOOP_BLOCK_NUM(INSN) \ | |
10679 | ((INSN) ? (GET_CODE (INSN) == NOTE \ | |
10680 | ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \ | |
10681 | : LOOP_BLOCK_NUM_1 (INSN)) \ | |
10682 | : -1) | |
10683 | ||
10684 | #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1) | |
10685 | ||
fd5d5b07 | 10686 | static void |
0c20a65f AJ |
10687 | loop_dump_aux (const struct loop *loop, FILE *file, |
10688 | int verbose ATTRIBUTE_UNUSED) | |
6057c0e6 MH |
10689 | { |
10690 | rtx label; | |
10691 | ||
10692 | if (! loop || ! file) | |
10693 | return; | |
10694 | ||
10695 | /* Print diagnostics to compare our concept of a loop with | |
10696 | what the loop notes say. */ | |
10697 | if (! PREV_INSN (loop->first->head) | |
10698 | || GET_CODE (PREV_INSN (loop->first->head)) != NOTE | |
10699 | || NOTE_LINE_NUMBER (PREV_INSN (loop->first->head)) | |
10700 | != NOTE_INSN_LOOP_BEG) | |
fd5d5b07 | 10701 | fprintf (file, ";; No NOTE_INSN_LOOP_BEG at %d\n", |
6057c0e6 MH |
10702 | INSN_UID (PREV_INSN (loop->first->head))); |
10703 | if (! NEXT_INSN (loop->last->end) | |
10704 | || GET_CODE (NEXT_INSN (loop->last->end)) != NOTE | |
10705 | || NOTE_LINE_NUMBER (NEXT_INSN (loop->last->end)) | |
10706 | != NOTE_INSN_LOOP_END) | |
10707 | fprintf (file, ";; No NOTE_INSN_LOOP_END at %d\n", | |
10708 | INSN_UID (NEXT_INSN (loop->last->end))); | |
10709 | ||
10710 | if (loop->start) | |
10711 | { | |
10712 | fprintf (file, | |
10713 | ";; start %d (%d), cont dom %d (%d), cont %d (%d), vtop %d (%d), end %d (%d)\n", | |
10714 | LOOP_BLOCK_NUM (loop->start), | |
10715 | LOOP_INSN_UID (loop->start), | |
10716 | LOOP_BLOCK_NUM (loop->cont), | |
10717 | LOOP_INSN_UID (loop->cont), | |
10718 | LOOP_BLOCK_NUM (loop->cont), | |
10719 | LOOP_INSN_UID (loop->cont), | |
10720 | LOOP_BLOCK_NUM (loop->vtop), | |
10721 | LOOP_INSN_UID (loop->vtop), | |
10722 | LOOP_BLOCK_NUM (loop->end), | |
10723 | LOOP_INSN_UID (loop->end)); | |
10724 | fprintf (file, ";; top %d (%d), scan start %d (%d)\n", | |
10725 | LOOP_BLOCK_NUM (loop->top), | |
fd5d5b07 | 10726 | LOOP_INSN_UID (loop->top), |
6057c0e6 MH |
10727 | LOOP_BLOCK_NUM (loop->scan_start), |
10728 | LOOP_INSN_UID (loop->scan_start)); | |
10729 | fprintf (file, ";; exit_count %d", loop->exit_count); | |
10730 | if (loop->exit_count) | |
10731 | { | |
10732 | fputs (", labels:", file); | |
10733 | for (label = loop->exit_labels; label; label = LABEL_NEXTREF (label)) | |
10734 | { | |
10735 | fprintf (file, " %d ", | |
10736 | LOOP_INSN_UID (XEXP (label, 0))); | |
10737 | } | |
10738 | } | |
10739 | fputs ("\n", file); | |
fd5d5b07 | 10740 | |
6057c0e6 MH |
10741 | /* This can happen when a marked loop appears as two nested loops, |
10742 | say from while (a || b) {}. The inner loop won't match | |
10743 | the loop markers but the outer one will. */ | |
0b17ab2f | 10744 | if (LOOP_BLOCK_NUM (loop->cont) != loop->latch->index) |
6057c0e6 MH |
10745 | fprintf (file, ";; NOTE_INSN_LOOP_CONT not in loop latch\n"); |
10746 | } | |
10747 | } | |
6057c0e6 MH |
10748 | |
10749 | /* Call this function from the debugger to dump LOOP. */ | |
10750 | ||
10751 | void | |
0c20a65f | 10752 | debug_loop (const struct loop *loop) |
6057c0e6 MH |
10753 | { |
10754 | flow_loop_dump (loop, stderr, loop_dump_aux, 1); | |
10755 | } | |
685efa54 MH |
10756 | |
10757 | /* Call this function from the debugger to dump LOOPS. */ | |
10758 | ||
10759 | void | |
0c20a65f | 10760 | debug_loops (const struct loops *loops) |
685efa54 MH |
10761 | { |
10762 | flow_loops_dump (loops, stderr, loop_dump_aux, 1); | |
10763 | } |