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c8465d70 | 1 | /* Perform various loop optimizations, including strength reduction. |
a544cfd2 | 2 | Copyright (C) 1987, 88, 89, 91-99, 2000 Free Software Foundation, Inc. |
b4ad7b23 RS |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
a35311b0 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
b4ad7b23 RS |
20 | |
21 | ||
22 | /* This is the loop optimization pass of the compiler. | |
23 | It finds invariant computations within loops and moves them | |
24 | to the beginning of the loop. Then it identifies basic and | |
25 | general induction variables. Strength reduction is applied to the general | |
26 | induction variables, and induction variable elimination is applied to | |
27 | the basic induction variables. | |
28 | ||
29 | It also finds cases where | |
30 | a register is set within the loop by zero-extending a narrower value | |
31 | and changes these to zero the entire register once before the loop | |
32 | and merely copy the low part within the loop. | |
33 | ||
34 | Most of the complexity is in heuristics to decide when it is worth | |
35 | while to do these things. */ | |
36 | ||
37 | #include "config.h" | |
670ee920 | 38 | #include "system.h" |
b4ad7b23 | 39 | #include "rtl.h" |
6baf1cc8 | 40 | #include "tm_p.h" |
b4ad7b23 | 41 | #include "obstack.h" |
49ad7cfa | 42 | #include "function.h" |
b4ad7b23 | 43 | #include "expr.h" |
c29f60c0 | 44 | #include "basic-block.h" |
b4ad7b23 RS |
45 | #include "insn-config.h" |
46 | #include "insn-flags.h" | |
47 | #include "regs.h" | |
48 | #include "hard-reg-set.h" | |
49 | #include "recog.h" | |
50 | #include "flags.h" | |
51 | #include "real.h" | |
b4ad7b23 | 52 | #include "loop.h" |
6adb4e3a | 53 | #include "except.h" |
2e107e9e | 54 | #include "toplev.h" |
b4ad7b23 | 55 | |
3c748bb6 MH |
56 | /* Information about the loop being processed used to compute |
57 | the number of loop iterations for loop unrolling and doloop | |
58 | optimization. */ | |
a2be868f | 59 | static struct loop_info loop_info_data; |
3c748bb6 | 60 | |
b4ad7b23 | 61 | /* Vector mapping INSN_UIDs to luids. |
d45cf215 | 62 | The luids are like uids but increase monotonically always. |
b4ad7b23 RS |
63 | We use them to see whether a jump comes from outside a given loop. */ |
64 | ||
65 | int *uid_luid; | |
66 | ||
67 | /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop | |
68 | number the insn is contained in. */ | |
69 | ||
a2be868f | 70 | struct loop **uid_loop; |
b4ad7b23 RS |
71 | |
72 | /* 1 + largest uid of any insn. */ | |
73 | ||
74 | int max_uid_for_loop; | |
75 | ||
76 | /* 1 + luid of last insn. */ | |
77 | ||
78 | static int max_luid; | |
79 | ||
80 | /* Number of loops detected in current function. Used as index to the | |
81 | next few tables. */ | |
82 | ||
83 | static int max_loop_num; | |
84 | ||
b4ad7b23 RS |
85 | /* Indexed by register number, contains the number of times the reg |
86 | is set during the loop being scanned. | |
87 | During code motion, a negative value indicates a reg that has been | |
88 | made a candidate; in particular -2 means that it is an candidate that | |
c5b7917e | 89 | we know is equal to a constant and -1 means that it is an candidate |
b4ad7b23 RS |
90 | not known equal to a constant. |
91 | After code motion, regs moved have 0 (which is accurate now) | |
92 | while the failed candidates have the original number of times set. | |
93 | ||
94 | Therefore, at all times, == 0 indicates an invariant register; | |
95 | < 0 a conditionally invariant one. */ | |
96 | ||
4b259e3f | 97 | static varray_type set_in_loop; |
b4ad7b23 | 98 | |
4b259e3f | 99 | /* Original value of set_in_loop; same except that this value |
b4ad7b23 RS |
100 | is not set negative for a reg whose sets have been made candidates |
101 | and not set to 0 for a reg that is moved. */ | |
102 | ||
4b259e3f | 103 | static varray_type n_times_set; |
b4ad7b23 RS |
104 | |
105 | /* Index by register number, 1 indicates that the register | |
106 | cannot be moved or strength reduced. */ | |
107 | ||
8deb8e2c | 108 | static varray_type may_not_optimize; |
b4ad7b23 | 109 | |
d6b44532 RH |
110 | /* Contains the insn in which a register was used if it was used |
111 | exactly once; contains const0_rtx if it was used more than once. */ | |
112 | ||
113 | static varray_type reg_single_usage; | |
114 | ||
b4ad7b23 RS |
115 | /* Nonzero means reg N has already been moved out of one loop. |
116 | This reduces the desire to move it out of another. */ | |
117 | ||
118 | static char *moved_once; | |
119 | ||
5026a502 | 120 | /* List of MEMs that are stored in this loop. */ |
b4ad7b23 | 121 | |
5026a502 | 122 | static rtx loop_store_mems; |
b4ad7b23 | 123 | |
2d4fde68 R |
124 | /* The insn where the first of these was found. */ |
125 | static rtx first_loop_store_insn; | |
126 | ||
41a972a9 MM |
127 | typedef struct loop_mem_info { |
128 | rtx mem; /* The MEM itself. */ | |
129 | rtx reg; /* Corresponding pseudo, if any. */ | |
130 | int optimize; /* Nonzero if we can optimize access to this MEM. */ | |
131 | } loop_mem_info; | |
132 | ||
133 | /* Array of MEMs that are used (read or written) in this loop, but | |
134 | cannot be aliased by anything in this loop, except perhaps | |
135 | themselves. In other words, if loop_mems[i] is altered during the | |
136 | loop, it is altered by an expression that is rtx_equal_p to it. */ | |
137 | ||
138 | static loop_mem_info *loop_mems; | |
139 | ||
140 | /* The index of the next available slot in LOOP_MEMS. */ | |
141 | ||
142 | static int loop_mems_idx; | |
143 | ||
144 | /* The number of elements allocated in LOOP_MEMs. */ | |
145 | ||
146 | static int loop_mems_allocated; | |
147 | ||
3c748bb6 MH |
148 | /* Nonzero if we don't know what MEMs were changed in the current |
149 | loop. This happens if the loop contains a call (in which case | |
150 | `loop_info->has_call' will also be set) or if we store into more | |
151 | than NUM_STORES MEMs. */ | |
b4ad7b23 RS |
152 | |
153 | static int unknown_address_altered; | |
154 | ||
14a774a9 RK |
155 | /* The above doesn't count any readonly memory locations that are stored. |
156 | This does. */ | |
157 | ||
158 | static int unknown_constant_address_altered; | |
159 | ||
b4ad7b23 RS |
160 | /* Count of movable (i.e. invariant) instructions discovered in the loop. */ |
161 | static int num_movables; | |
162 | ||
163 | /* Count of memory write instructions discovered in the loop. */ | |
164 | static int num_mem_sets; | |
165 | ||
b4ad7b23 RS |
166 | /* Bound on pseudo register number before loop optimization. |
167 | A pseudo has valid regscan info if its number is < max_reg_before_loop. */ | |
168 | int max_reg_before_loop; | |
169 | ||
0a326ec9 BS |
170 | /* The value to pass to the next call of reg_scan_update. */ |
171 | static int loop_max_reg; | |
172 | ||
b4ad7b23 RS |
173 | /* This obstack is used in product_cheap_p to allocate its rtl. It |
174 | may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx. | |
175 | If we used the same obstack that it did, we would be deallocating | |
176 | that array. */ | |
177 | ||
178 | static struct obstack temp_obstack; | |
179 | ||
180 | /* This is where the pointer to the obstack being used for RTL is stored. */ | |
181 | ||
182 | extern struct obstack *rtl_obstack; | |
183 | ||
184 | #define obstack_chunk_alloc xmalloc | |
185 | #define obstack_chunk_free free | |
b4ad7b23 RS |
186 | \f |
187 | /* During the analysis of a loop, a chain of `struct movable's | |
188 | is made to record all the movable insns found. | |
189 | Then the entire chain can be scanned to decide which to move. */ | |
190 | ||
191 | struct movable | |
192 | { | |
193 | rtx insn; /* A movable insn */ | |
0f41302f MS |
194 | rtx set_src; /* The expression this reg is set from. */ |
195 | rtx set_dest; /* The destination of this SET. */ | |
b4ad7b23 | 196 | rtx dependencies; /* When INSN is libcall, this is an EXPR_LIST |
0f41302f | 197 | of any registers used within the LIBCALL. */ |
b4ad7b23 RS |
198 | int consec; /* Number of consecutive following insns |
199 | that must be moved with this one. */ | |
200 | int regno; /* The register it sets */ | |
201 | short lifetime; /* lifetime of that register; | |
202 | may be adjusted when matching movables | |
203 | that load the same value are found. */ | |
204 | short savings; /* Number of insns we can move for this reg, | |
205 | including other movables that force this | |
206 | or match this one. */ | |
207 | unsigned int cond : 1; /* 1 if only conditionally movable */ | |
208 | unsigned int force : 1; /* 1 means MUST move this insn */ | |
209 | unsigned int global : 1; /* 1 means reg is live outside this loop */ | |
210 | /* If PARTIAL is 1, GLOBAL means something different: | |
211 | that the reg is live outside the range from where it is set | |
212 | to the following label. */ | |
213 | unsigned int done : 1; /* 1 inhibits further processing of this */ | |
214 | ||
215 | unsigned int partial : 1; /* 1 means this reg is used for zero-extending. | |
216 | In particular, moving it does not make it | |
217 | invariant. */ | |
218 | unsigned int move_insn : 1; /* 1 means that we call emit_move_insn to | |
219 | load SRC, rather than copying INSN. */ | |
1a61c29f JW |
220 | unsigned int move_insn_first:1;/* Same as above, if this is necessary for the |
221 | first insn of a consecutive sets group. */ | |
0f41302f | 222 | unsigned int is_equiv : 1; /* 1 means a REG_EQUIV is present on INSN. */ |
b4ad7b23 RS |
223 | enum machine_mode savemode; /* Nonzero means it is a mode for a low part |
224 | that we should avoid changing when clearing | |
225 | the rest of the reg. */ | |
226 | struct movable *match; /* First entry for same value */ | |
227 | struct movable *forces; /* An insn that must be moved if this is */ | |
228 | struct movable *next; | |
229 | }; | |
230 | ||
45f97e2e RH |
231 | static struct movable *the_movables; |
232 | ||
b4ad7b23 RS |
233 | FILE *loop_dump_stream; |
234 | ||
235 | /* Forward declarations. */ | |
236 | ||
3fe41456 KG |
237 | static void verify_dominator PARAMS ((struct loop *)); |
238 | static void find_and_verify_loops PARAMS ((rtx, struct loops *)); | |
239 | static void mark_loop_jump PARAMS ((rtx, struct loop *)); | |
240 | static void prescan_loop PARAMS ((struct loop *)); | |
241 | static int reg_in_basic_block_p PARAMS ((rtx, rtx)); | |
242 | static int consec_sets_invariant_p PARAMS ((rtx, int, rtx)); | |
243 | static int labels_in_range_p PARAMS ((rtx, int)); | |
244 | static void count_one_set PARAMS ((rtx, rtx, varray_type, rtx *)); | |
245 | ||
246 | static void count_loop_regs_set PARAMS ((rtx, rtx, varray_type, varray_type, | |
8deb8e2c | 247 | int *, int)); |
3fe41456 KG |
248 | static void note_addr_stored PARAMS ((rtx, rtx, void *)); |
249 | static void note_set_pseudo_multiple_uses PARAMS ((rtx, rtx, void *)); | |
250 | static int loop_reg_used_before_p PARAMS ((const struct loop *, rtx, rtx)); | |
251 | static void scan_loop PARAMS ((struct loop*, int, int)); | |
e9a25f70 | 252 | #if 0 |
3fe41456 | 253 | static void replace_call_address PARAMS ((rtx, rtx, rtx)); |
e9a25f70 | 254 | #endif |
3fe41456 KG |
255 | static rtx skip_consec_insns PARAMS ((rtx, int)); |
256 | static int libcall_benefit PARAMS ((rtx)); | |
257 | static void ignore_some_movables PARAMS ((struct movable *)); | |
258 | static void force_movables PARAMS ((struct movable *)); | |
259 | static void combine_movables PARAMS ((struct movable *, int)); | |
260 | static int regs_match_p PARAMS ((rtx, rtx, struct movable *)); | |
261 | static int rtx_equal_for_loop_p PARAMS ((rtx, rtx, struct movable *)); | |
262 | static void add_label_notes PARAMS ((rtx, rtx)); | |
263 | static void move_movables PARAMS ((struct movable *, int, int, rtx, rtx, int)); | |
264 | static int count_nonfixed_reads PARAMS ((rtx)); | |
265 | static void strength_reduce PARAMS ((struct loop *, int, int, int)); | |
266 | static void find_single_use_in_loop PARAMS ((rtx, rtx, varray_type)); | |
267 | static int valid_initial_value_p PARAMS ((rtx, rtx, int, rtx)); | |
268 | static void find_mem_givs PARAMS ((rtx, rtx, int, int, rtx, rtx)); | |
269 | static void record_biv PARAMS ((struct induction *, rtx, rtx, rtx, rtx, rtx *, int, int, int)); | |
270 | static void check_final_value PARAMS ((struct induction *, rtx, rtx, | |
302670f3 | 271 | unsigned HOST_WIDE_INT)); |
3fe41456 KG |
272 | static void record_giv PARAMS ((struct induction *, rtx, rtx, rtx, rtx, rtx, int, enum g_types, int, int, rtx *, rtx, rtx)); |
273 | static void update_giv_derive PARAMS ((rtx)); | |
274 | static int basic_induction_var PARAMS ((rtx, enum machine_mode, rtx, rtx, int, rtx *, rtx *, rtx **, int *)); | |
275 | static rtx simplify_giv_expr PARAMS ((rtx, int *)); | |
276 | static int general_induction_var PARAMS ((rtx, rtx *, rtx *, rtx *, int, int *)); | |
277 | static int consec_sets_giv PARAMS ((int, rtx, rtx, rtx, rtx *, rtx *, rtx *)); | |
278 | static int check_dbra_loop PARAMS ((struct loop *, int)); | |
279 | static rtx express_from_1 PARAMS ((rtx, rtx, rtx)); | |
280 | static rtx combine_givs_p PARAMS ((struct induction *, struct induction *)); | |
281 | static void combine_givs PARAMS ((struct iv_class *)); | |
3ec2b590 | 282 | struct recombine_givs_stats; |
3fe41456 KG |
283 | static int find_life_end PARAMS ((rtx, struct recombine_givs_stats *, rtx, rtx)); |
284 | static void recombine_givs PARAMS ((struct iv_class *, rtx, rtx, int)); | |
285 | static int product_cheap_p PARAMS ((rtx, rtx)); | |
286 | static int maybe_eliminate_biv PARAMS ((struct iv_class *, rtx, rtx, int, int, int)); | |
287 | static int maybe_eliminate_biv_1 PARAMS ((rtx, rtx, struct iv_class *, int, rtx)); | |
288 | static int last_use_this_basic_block PARAMS ((rtx, rtx)); | |
289 | static void record_initial PARAMS ((rtx, rtx, void *)); | |
290 | static void update_reg_last_use PARAMS ((rtx, rtx)); | |
291 | static rtx next_insn_in_loop PARAMS ((const struct loop *, rtx)); | |
292 | static void load_mems_and_recount_loop_regs_set PARAMS ((const struct loop*, | |
a2be868f | 293 | int *)); |
3fe41456 KG |
294 | static void load_mems PARAMS ((const struct loop *)); |
295 | static int insert_loop_mem PARAMS ((rtx *, void *)); | |
296 | static int replace_loop_mem PARAMS ((rtx *, void *)); | |
297 | static int replace_loop_reg PARAMS ((rtx *, void *)); | |
298 | static void note_reg_stored PARAMS ((rtx, rtx, void *)); | |
299 | static void try_copy_prop PARAMS ((const struct loop *, rtx, int)); | |
300 | static int replace_label PARAMS ((rtx *, void *)); | |
41a972a9 MM |
301 | |
302 | typedef struct rtx_and_int { | |
303 | rtx r; | |
304 | int i; | |
305 | } rtx_and_int; | |
306 | ||
307 | typedef struct rtx_pair { | |
308 | rtx r1; | |
309 | rtx r2; | |
310 | } rtx_pair; | |
311 | ||
312 | /* Nonzero iff INSN is between START and END, inclusive. */ | |
313 | #define INSN_IN_RANGE_P(INSN, START, END) \ | |
314 | (INSN_UID (INSN) < max_uid_for_loop \ | |
315 | && INSN_LUID (INSN) >= INSN_LUID (START) \ | |
316 | && INSN_LUID (INSN) <= INSN_LUID (END)) | |
8c660648 | 317 | |
51723711 | 318 | #ifdef HAVE_decrement_and_branch_on_count |
cac8ce95 | 319 | /* Test whether BCT applicable and safe. */ |
3fe41456 | 320 | static void insert_bct PARAMS ((struct loop *)); |
8c660648 | 321 | |
cac8ce95 | 322 | /* Auxiliary function that inserts the BCT pattern into the loop. */ |
3fe41456 | 323 | static void instrument_loop_bct PARAMS ((rtx, rtx, rtx)); |
51723711 | 324 | #endif /* HAVE_decrement_and_branch_on_count */ |
8c660648 | 325 | |
2a1777af JL |
326 | /* Indirect_jump_in_function is computed once per function. */ |
327 | int indirect_jump_in_function = 0; | |
3fe41456 | 328 | static int indirect_jump_in_function_p PARAMS ((rtx)); |
2a1777af | 329 | |
3fe41456 | 330 | static int compute_luids PARAMS ((rtx, rtx, int)); |
a6207a2b | 331 | |
3fe41456 | 332 | static int biv_elimination_giv_has_0_offset PARAMS ((struct induction *, |
a6207a2b | 333 | struct induction *, rtx)); |
b4ad7b23 RS |
334 | \f |
335 | /* Relative gain of eliminating various kinds of operations. */ | |
45f97e2e | 336 | static int add_cost; |
b4ad7b23 | 337 | #if 0 |
45f97e2e RH |
338 | static int shift_cost; |
339 | static int mult_cost; | |
b4ad7b23 RS |
340 | #endif |
341 | ||
342 | /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to | |
343 | copy the value of the strength reduced giv to its original register. */ | |
45f97e2e RH |
344 | static int copy_cost; |
345 | ||
346 | /* Cost of using a register, to normalize the benefits of a giv. */ | |
347 | static int reg_address_cost; | |
348 | ||
b4ad7b23 RS |
349 | |
350 | void | |
351 | init_loop () | |
352 | { | |
353 | char *free_point = (char *) oballoc (1); | |
38a448ca | 354 | rtx reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
b4ad7b23 | 355 | |
38a448ca | 356 | add_cost = rtx_cost (gen_rtx_PLUS (word_mode, reg, reg), SET); |
b4ad7b23 | 357 | |
45f97e2e RH |
358 | #ifdef ADDRESS_COST |
359 | reg_address_cost = ADDRESS_COST (reg); | |
360 | #else | |
361 | reg_address_cost = rtx_cost (reg, MEM); | |
362 | #endif | |
363 | ||
b4ad7b23 RS |
364 | /* We multiply by 2 to reconcile the difference in scale between |
365 | these two ways of computing costs. Otherwise the cost of a copy | |
366 | will be far less than the cost of an add. */ | |
5fd8383e | 367 | |
b4ad7b23 | 368 | copy_cost = 2 * 2; |
b4ad7b23 RS |
369 | |
370 | /* Free the objects we just allocated. */ | |
371 | obfree (free_point); | |
372 | ||
373 | /* Initialize the obstack used for rtl in product_cheap_p. */ | |
374 | gcc_obstack_init (&temp_obstack); | |
375 | } | |
376 | \f | |
3ec2b590 R |
377 | /* Compute the mapping from uids to luids. |
378 | LUIDs are numbers assigned to insns, like uids, | |
379 | except that luids increase monotonically through the code. | |
380 | Start at insn START and stop just before END. Assign LUIDs | |
381 | starting with PREV_LUID + 1. Return the last assigned LUID + 1. */ | |
382 | static int | |
383 | compute_luids (start, end, prev_luid) | |
384 | rtx start, end; | |
385 | int prev_luid; | |
386 | { | |
387 | int i; | |
388 | rtx insn; | |
389 | ||
390 | for (insn = start, i = prev_luid; insn != end; insn = NEXT_INSN (insn)) | |
391 | { | |
392 | if (INSN_UID (insn) >= max_uid_for_loop) | |
393 | continue; | |
394 | /* Don't assign luids to line-number NOTEs, so that the distance in | |
395 | luids between two insns is not affected by -g. */ | |
396 | if (GET_CODE (insn) != NOTE | |
397 | || NOTE_LINE_NUMBER (insn) <= 0) | |
398 | uid_luid[INSN_UID (insn)] = ++i; | |
399 | else | |
400 | /* Give a line number note the same luid as preceding insn. */ | |
401 | uid_luid[INSN_UID (insn)] = i; | |
402 | } | |
403 | return i + 1; | |
404 | } | |
405 | \f | |
b4ad7b23 RS |
406 | /* Entry point of this file. Perform loop optimization |
407 | on the current function. F is the first insn of the function | |
408 | and DUMPFILE is a stream for output of a trace of actions taken | |
409 | (or 0 if none should be output). */ | |
410 | ||
411 | void | |
5accd822 | 412 | loop_optimize (f, dumpfile, unroll_p, bct_p) |
b4ad7b23 RS |
413 | /* f is the first instruction of a chain of insns for one function */ |
414 | rtx f; | |
415 | FILE *dumpfile; | |
5accd822 | 416 | int unroll_p, bct_p; |
b4ad7b23 RS |
417 | { |
418 | register rtx insn; | |
419 | register int i; | |
a2be868f MH |
420 | struct loops loops_data; |
421 | struct loops *loops = &loops_data; | |
b4ad7b23 RS |
422 | |
423 | loop_dump_stream = dumpfile; | |
424 | ||
425 | init_recog_no_volatile (); | |
b4ad7b23 RS |
426 | |
427 | max_reg_before_loop = max_reg_num (); | |
0a326ec9 | 428 | loop_max_reg = max_reg_before_loop; |
b4ad7b23 | 429 | |
b4ad7b23 RS |
430 | regs_may_share = 0; |
431 | ||
0f41302f | 432 | /* Count the number of loops. */ |
b4ad7b23 RS |
433 | |
434 | max_loop_num = 0; | |
435 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
436 | { | |
437 | if (GET_CODE (insn) == NOTE | |
438 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
439 | max_loop_num++; | |
440 | } | |
441 | ||
442 | /* Don't waste time if no loops. */ | |
443 | if (max_loop_num == 0) | |
444 | return; | |
445 | ||
a2be868f MH |
446 | loops->num = max_loop_num; |
447 | ||
67289ea6 MM |
448 | moved_once = (char *) xcalloc (max_reg_before_loop, sizeof (char)); |
449 | ||
b4ad7b23 RS |
450 | /* Get size to use for tables indexed by uids. |
451 | Leave some space for labels allocated by find_and_verify_loops. */ | |
1c01e9df | 452 | max_uid_for_loop = get_max_uid () + 1 + max_loop_num * 32; |
b4ad7b23 | 453 | |
67289ea6 | 454 | uid_luid = (int *) xcalloc (max_uid_for_loop, sizeof (int)); |
a2be868f MH |
455 | uid_loop = (struct loop **) xcalloc (max_uid_for_loop, |
456 | sizeof (struct loop *)); | |
8c660648 | 457 | |
b4ad7b23 RS |
458 | /* Find and process each loop. |
459 | First, find them, and record them in order of their beginnings. */ | |
a2be868f | 460 | find_and_verify_loops (f, loops); |
b4ad7b23 RS |
461 | |
462 | /* Now find all register lifetimes. This must be done after | |
463 | find_and_verify_loops, because it might reorder the insns in the | |
464 | function. */ | |
0a326ec9 | 465 | reg_scan (f, max_reg_before_loop, 1); |
b4ad7b23 | 466 | |
7506f491 DE |
467 | /* This must occur after reg_scan so that registers created by gcse |
468 | will have entries in the register tables. | |
469 | ||
470 | We could have added a call to reg_scan after gcse_main in toplev.c, | |
471 | but moving this call to init_alias_analysis is more efficient. */ | |
472 | init_alias_analysis (); | |
473 | ||
e318cec0 R |
474 | /* See if we went too far. Note that get_max_uid already returns |
475 | one more that the maximum uid of all insn. */ | |
1c01e9df TW |
476 | if (get_max_uid () > max_uid_for_loop) |
477 | abort (); | |
f5963e61 | 478 | /* Now reset it to the actual size we need. See above. */ |
e318cec0 | 479 | max_uid_for_loop = get_max_uid (); |
1c01e9df | 480 | |
a2be868f MH |
481 | /* find_and_verify_loops has already called compute_luids, but it |
482 | might have rearranged code afterwards, so we need to recompute | |
483 | the luids now. */ | |
3ec2b590 | 484 | max_luid = compute_luids (f, NULL_RTX, 0); |
b4ad7b23 RS |
485 | |
486 | /* Don't leave gaps in uid_luid for insns that have been | |
487 | deleted. It is possible that the first or last insn | |
488 | using some register has been deleted by cross-jumping. | |
489 | Make sure that uid_luid for that former insn's uid | |
490 | points to the general area where that insn used to be. */ | |
491 | for (i = 0; i < max_uid_for_loop; i++) | |
492 | { | |
493 | uid_luid[0] = uid_luid[i]; | |
494 | if (uid_luid[0] != 0) | |
495 | break; | |
496 | } | |
497 | for (i = 0; i < max_uid_for_loop; i++) | |
498 | if (uid_luid[i] == 0) | |
499 | uid_luid[i] = uid_luid[i - 1]; | |
500 | ||
428248f7 MM |
501 | /* If debugging and unrolling loops, we must replicate the tree |
502 | nodes corresponding to the BLOCKs inside the loop, so that the | |
503 | original one to one mapping will remain. We sometimes unroll | |
504 | loops even when unroll_p is false, so we must always do this when | |
505 | debugging. */ | |
506 | if (write_symbols != NO_DEBUG) | |
07e857c2 | 507 | find_loop_tree_blocks (); |
b4ad7b23 | 508 | |
2a1777af JL |
509 | /* Determine if the function has indirect jump. On some systems |
510 | this prevents low overhead loop instructions from being used. */ | |
8c660648 | 511 | indirect_jump_in_function = indirect_jump_in_function_p (f); |
8c660648 | 512 | |
b4ad7b23 RS |
513 | /* Now scan the loops, last ones first, since this means inner ones are done |
514 | before outer ones. */ | |
a2be868f MH |
515 | for (i = max_loop_num - 1; i >= 0; i--) |
516 | { | |
517 | struct loop *loop = &loops->array[i]; | |
518 | ||
519 | if (! loop->invalid && loop->end) | |
520 | scan_loop (loop, unroll_p, bct_p); | |
521 | } | |
07e857c2 | 522 | |
428248f7 MM |
523 | /* Replicate the BLOCKs. */ |
524 | if (write_symbols != NO_DEBUG) | |
07e857c2 | 525 | unroll_block_trees (); |
45f97e2e RH |
526 | |
527 | end_alias_analysis (); | |
67289ea6 MM |
528 | |
529 | /* Clean up. */ | |
530 | free (moved_once); | |
531 | free (uid_luid); | |
a2be868f | 532 | free (uid_loop); |
b4ad7b23 RS |
533 | } |
534 | \f | |
41a972a9 MM |
535 | /* Returns the next insn, in execution order, after INSN. START and |
536 | END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop, | |
537 | respectively. LOOP_TOP, if non-NULL, is the top of the loop in the | |
538 | insn-stream; it is used with loops that are entered near the | |
539 | bottom. */ | |
540 | ||
541 | static rtx | |
a2be868f MH |
542 | next_insn_in_loop (loop, insn) |
543 | const struct loop *loop; | |
41a972a9 | 544 | rtx insn; |
41a972a9 MM |
545 | { |
546 | insn = NEXT_INSN (insn); | |
547 | ||
a2be868f | 548 | if (insn == loop->end) |
41a972a9 | 549 | { |
a2be868f | 550 | if (loop->top) |
41a972a9 | 551 | /* Go to the top of the loop, and continue there. */ |
a2be868f | 552 | insn = loop->top; |
41a972a9 MM |
553 | else |
554 | /* We're done. */ | |
555 | insn = NULL_RTX; | |
556 | } | |
557 | ||
a2be868f | 558 | if (insn == loop->scan_start) |
41a972a9 MM |
559 | /* We're done. */ |
560 | insn = NULL_RTX; | |
561 | ||
562 | return insn; | |
563 | } | |
564 | ||
a2be868f | 565 | /* Optimize one loop described by LOOP. */ |
b4ad7b23 RS |
566 | |
567 | /* ??? Could also move memory writes out of loops if the destination address | |
568 | is invariant, the source is invariant, the memory write is not volatile, | |
569 | and if we can prove that no read inside the loop can read this address | |
570 | before the write occurs. If there is a read of this address after the | |
571 | write, then we can also mark the memory read as invariant. */ | |
572 | ||
573 | static void | |
a2be868f MH |
574 | scan_loop (loop, unroll_p, bct_p) |
575 | struct loop *loop; | |
5accd822 | 576 | int unroll_p, bct_p; |
b4ad7b23 RS |
577 | { |
578 | register int i; | |
a2be868f MH |
579 | rtx loop_start = loop->start; |
580 | rtx loop_end = loop->end; | |
41a972a9 | 581 | rtx p; |
b4ad7b23 RS |
582 | /* 1 if we are scanning insns that could be executed zero times. */ |
583 | int maybe_never = 0; | |
584 | /* 1 if we are scanning insns that might never be executed | |
585 | due to a subroutine call which might exit before they are reached. */ | |
586 | int call_passed = 0; | |
b4ad7b23 RS |
587 | /* Jump insn that enters the loop, or 0 if control drops in. */ |
588 | rtx loop_entry_jump = 0; | |
b4ad7b23 RS |
589 | /* Number of insns in the loop. */ |
590 | int insn_count; | |
591 | int in_libcall = 0; | |
592 | int tem; | |
0a326ec9 | 593 | rtx temp, update_start, update_end; |
b4ad7b23 RS |
594 | /* The SET from an insn, if it is the only SET in the insn. */ |
595 | rtx set, set1; | |
596 | /* Chain describing insns movable in current loop. */ | |
597 | struct movable *movables = 0; | |
598 | /* Last element in `movables' -- so we can add elements at the end. */ | |
599 | struct movable *last_movable = 0; | |
600 | /* Ratio of extra register life span we can justify | |
601 | for saving an instruction. More if loop doesn't call subroutines | |
602 | since in that case saving an insn makes more difference | |
603 | and more registers are available. */ | |
604 | int threshold; | |
5ea7a4ae JW |
605 | /* Nonzero if we are scanning instructions in a sub-loop. */ |
606 | int loop_depth = 0; | |
41a972a9 | 607 | int nregs; |
a2be868f MH |
608 | struct loop_info *loop_info = &loop_info_data; |
609 | ||
610 | loop->info = loop_info; | |
611 | loop->top = 0; | |
b4ad7b23 RS |
612 | |
613 | /* Determine whether this loop starts with a jump down to a test at | |
614 | the end. This will occur for a small number of loops with a test | |
615 | that is too complex to duplicate in front of the loop. | |
616 | ||
617 | We search for the first insn or label in the loop, skipping NOTEs. | |
618 | However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG | |
619 | (because we might have a loop executed only once that contains a | |
620 | loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END | |
621 | (in case we have a degenerate loop). | |
622 | ||
623 | Note that if we mistakenly think that a loop is entered at the top | |
624 | when, in fact, it is entered at the exit test, the only effect will be | |
625 | slightly poorer optimization. Making the opposite error can generate | |
626 | incorrect code. Since very few loops now start with a jump to the | |
627 | exit test, the code here to detect that case is very conservative. */ | |
628 | ||
629 | for (p = NEXT_INSN (loop_start); | |
a2be868f | 630 | p != loop_end |
b4ad7b23 RS |
631 | && GET_CODE (p) != CODE_LABEL && GET_RTX_CLASS (GET_CODE (p)) != 'i' |
632 | && (GET_CODE (p) != NOTE | |
633 | || (NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_BEG | |
634 | && NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_END)); | |
635 | p = NEXT_INSN (p)) | |
636 | ; | |
637 | ||
a2be868f | 638 | loop->scan_start = p; |
b4ad7b23 RS |
639 | |
640 | /* Set up variables describing this loop. */ | |
a2be868f | 641 | prescan_loop (loop); |
3c748bb6 | 642 | threshold = (loop_info->has_call ? 1 : 2) * (1 + n_non_fixed_regs); |
b4ad7b23 RS |
643 | |
644 | /* If loop has a jump before the first label, | |
645 | the true entry is the target of that jump. | |
646 | Start scan from there. | |
a2be868f | 647 | But record in LOOP->TOP the place where the end-test jumps |
b4ad7b23 RS |
648 | back to so we can scan that after the end of the loop. */ |
649 | if (GET_CODE (p) == JUMP_INSN) | |
650 | { | |
651 | loop_entry_jump = p; | |
652 | ||
653 | /* Loop entry must be unconditional jump (and not a RETURN) */ | |
654 | if (simplejump_p (p) | |
655 | && JUMP_LABEL (p) != 0 | |
656 | /* Check to see whether the jump actually | |
657 | jumps out of the loop (meaning it's no loop). | |
658 | This case can happen for things like | |
659 | do {..} while (0). If this label was generated previously | |
660 | by loop, we can't tell anything about it and have to reject | |
661 | the loop. */ | |
a2be868f | 662 | && INSN_IN_RANGE_P (JUMP_LABEL (p), loop_start, loop_end)) |
b4ad7b23 | 663 | { |
a2be868f MH |
664 | loop->top = next_label (loop->scan_start); |
665 | loop->scan_start = JUMP_LABEL (p); | |
b4ad7b23 RS |
666 | } |
667 | } | |
668 | ||
a2be868f | 669 | /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid |
b4ad7b23 RS |
670 | as required by loop_reg_used_before_p. So skip such loops. (This |
671 | test may never be true, but it's best to play it safe.) | |
672 | ||
673 | Also, skip loops where we do not start scanning at a label. This | |
674 | test also rejects loops starting with a JUMP_INSN that failed the | |
675 | test above. */ | |
676 | ||
a2be868f MH |
677 | if (INSN_UID (loop->scan_start) >= max_uid_for_loop |
678 | || GET_CODE (loop->scan_start) != CODE_LABEL) | |
b4ad7b23 RS |
679 | { |
680 | if (loop_dump_stream) | |
681 | fprintf (loop_dump_stream, "\nLoop from %d to %d is phony.\n\n", | |
a2be868f | 682 | INSN_UID (loop_start), INSN_UID (loop_end)); |
b4ad7b23 RS |
683 | return; |
684 | } | |
685 | ||
686 | /* Count number of times each reg is set during this loop. | |
8deb8e2c | 687 | Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out |
d6b44532 | 688 | the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */ |
41a972a9 MM |
689 | |
690 | /* Allocate extra space for REGS that might be created by | |
8deb8e2c MM |
691 | load_mems. We allocate a little extra slop as well, in the hopes |
692 | that even after the moving of movables creates some new registers | |
693 | we won't have to reallocate these arrays. However, we do grow | |
694 | the arrays, if necessary, in load_mems_recount_loop_regs_set. */ | |
695 | nregs = max_reg_num () + loop_mems_idx + 16; | |
4b259e3f | 696 | VARRAY_INT_INIT (set_in_loop, nregs, "set_in_loop"); |
8deb8e2c | 697 | VARRAY_INT_INIT (n_times_set, nregs, "n_times_set"); |
8deb8e2c | 698 | VARRAY_CHAR_INIT (may_not_optimize, nregs, "may_not_optimize"); |
d6b44532 | 699 | VARRAY_RTX_INIT (reg_single_usage, nregs, "reg_single_usage"); |
b4ad7b23 | 700 | |
a2be868f | 701 | count_loop_regs_set (loop->top ? loop->top : loop->start, loop->end, |
b4ad7b23 RS |
702 | may_not_optimize, reg_single_usage, &insn_count, nregs); |
703 | ||
704 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
8deb8e2c MM |
705 | { |
706 | VARRAY_CHAR (may_not_optimize, i) = 1; | |
4b259e3f | 707 | VARRAY_INT (set_in_loop, i) = 1; |
8deb8e2c | 708 | } |
ef9e3c5b JL |
709 | |
710 | #ifdef AVOID_CCMODE_COPIES | |
711 | /* Don't try to move insns which set CC registers if we should not | |
712 | create CCmode register copies. */ | |
3568fdd2 | 713 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) |
ef9e3c5b | 714 | if (GET_MODE_CLASS (GET_MODE (regno_reg_rtx[i])) == MODE_CC) |
8deb8e2c | 715 | VARRAY_CHAR (may_not_optimize, i) = 1; |
ef9e3c5b JL |
716 | #endif |
717 | ||
4b259e3f R |
718 | bcopy ((char *) &set_in_loop->data, |
719 | (char *) &n_times_set->data, nregs * sizeof (int)); | |
b4ad7b23 RS |
720 | |
721 | if (loop_dump_stream) | |
722 | { | |
723 | fprintf (loop_dump_stream, "\nLoop from %d to %d: %d real insns.\n", | |
a2be868f MH |
724 | INSN_UID (loop_start), INSN_UID (loop_end), insn_count); |
725 | if (loop->cont) | |
b4ad7b23 | 726 | fprintf (loop_dump_stream, "Continue at insn %d.\n", |
a2be868f | 727 | INSN_UID (loop->cont)); |
b4ad7b23 RS |
728 | } |
729 | ||
730 | /* Scan through the loop finding insns that are safe to move. | |
4b259e3f | 731 | Set set_in_loop negative for the reg being set, so that |
b4ad7b23 RS |
732 | this reg will be considered invariant for subsequent insns. |
733 | We consider whether subsequent insns use the reg | |
734 | in deciding whether it is worth actually moving. | |
735 | ||
736 | MAYBE_NEVER is nonzero if we have passed a conditional jump insn | |
737 | and therefore it is possible that the insns we are scanning | |
738 | would never be executed. At such times, we must make sure | |
739 | that it is safe to execute the insn once instead of zero times. | |
740 | When MAYBE_NEVER is 0, all insns will be executed at least once | |
741 | so that is not a problem. */ | |
742 | ||
a2be868f | 743 | for (p = next_insn_in_loop (loop, loop->scan_start); |
41a972a9 | 744 | p != NULL_RTX; |
a2be868f | 745 | p = next_insn_in_loop (loop, p)) |
b4ad7b23 | 746 | { |
b4ad7b23 | 747 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i' |
5fd8383e | 748 | && find_reg_note (p, REG_LIBCALL, NULL_RTX)) |
b4ad7b23 RS |
749 | in_libcall = 1; |
750 | else if (GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
5fd8383e | 751 | && find_reg_note (p, REG_RETVAL, NULL_RTX)) |
b4ad7b23 RS |
752 | in_libcall = 0; |
753 | ||
754 | if (GET_CODE (p) == INSN | |
755 | && (set = single_set (p)) | |
756 | && GET_CODE (SET_DEST (set)) == REG | |
8deb8e2c | 757 | && ! VARRAY_CHAR (may_not_optimize, REGNO (SET_DEST (set)))) |
b4ad7b23 RS |
758 | { |
759 | int tem1 = 0; | |
760 | int tem2 = 0; | |
761 | int move_insn = 0; | |
762 | rtx src = SET_SRC (set); | |
763 | rtx dependencies = 0; | |
764 | ||
765 | /* Figure out what to use as a source of this insn. If a REG_EQUIV | |
766 | note is given or if a REG_EQUAL note with a constant operand is | |
767 | specified, use it as the source and mark that we should move | |
768 | this insn by calling emit_move_insn rather that duplicating the | |
769 | insn. | |
770 | ||
771 | Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note | |
772 | is present. */ | |
5fd8383e | 773 | temp = find_reg_note (p, REG_EQUIV, NULL_RTX); |
b4ad7b23 RS |
774 | if (temp) |
775 | src = XEXP (temp, 0), move_insn = 1; | |
776 | else | |
777 | { | |
5fd8383e | 778 | temp = find_reg_note (p, REG_EQUAL, NULL_RTX); |
b4ad7b23 RS |
779 | if (temp && CONSTANT_P (XEXP (temp, 0))) |
780 | src = XEXP (temp, 0), move_insn = 1; | |
5fd8383e | 781 | if (temp && find_reg_note (p, REG_RETVAL, NULL_RTX)) |
b4ad7b23 RS |
782 | { |
783 | src = XEXP (temp, 0); | |
784 | /* A libcall block can use regs that don't appear in | |
785 | the equivalent expression. To move the libcall, | |
786 | we must move those regs too. */ | |
787 | dependencies = libcall_other_reg (p, src); | |
788 | } | |
789 | } | |
790 | ||
791 | /* Don't try to optimize a register that was made | |
792 | by loop-optimization for an inner loop. | |
793 | We don't know its life-span, so we can't compute the benefit. */ | |
794 | if (REGNO (SET_DEST (set)) >= max_reg_before_loop) | |
795 | ; | |
77854601 | 796 | else if (/* The register is used in basic blocks other |
95ca22f4 MM |
797 | than the one where it is set (meaning that |
798 | something after this point in the loop might | |
799 | depend on its value before the set). */ | |
77854601 MH |
800 | ! reg_in_basic_block_p (p, SET_DEST (set)) |
801 | /* And the set is not guaranteed to be executed one | |
802 | the loop starts, or the value before the set is | |
803 | needed before the set occurs... | |
804 | ||
805 | ??? Note we have quadratic behaviour here, mitigated | |
806 | by the fact that the previous test will often fail for | |
807 | large loops. Rather than re-scanning the entire loop | |
808 | each time for register usage, we should build tables | |
809 | of the register usage and use them here instead. */ | |
810 | && (maybe_never | |
a2be868f | 811 | || loop_reg_used_before_p (loop, set, p))) |
e1f7435e JL |
812 | /* It is unsafe to move the set. |
813 | ||
814 | This code used to consider it OK to move a set of a variable | |
815 | which was not created by the user and not used in an exit test. | |
816 | That behavior is incorrect and was removed. */ | |
b4ad7b23 RS |
817 | ; |
818 | else if ((tem = invariant_p (src)) | |
819 | && (dependencies == 0 | |
820 | || (tem2 = invariant_p (dependencies)) != 0) | |
4b259e3f | 821 | && (VARRAY_INT (set_in_loop, |
8deb8e2c | 822 | REGNO (SET_DEST (set))) == 1 |
b4ad7b23 | 823 | || (tem1 |
8deb8e2c MM |
824 | = consec_sets_invariant_p |
825 | (SET_DEST (set), | |
4b259e3f | 826 | VARRAY_INT (set_in_loop, REGNO (SET_DEST (set))), |
8deb8e2c | 827 | p))) |
b4ad7b23 RS |
828 | /* If the insn can cause a trap (such as divide by zero), |
829 | can't move it unless it's guaranteed to be executed | |
830 | once loop is entered. Even a function call might | |
831 | prevent the trap insn from being reached | |
832 | (since it might exit!) */ | |
833 | && ! ((maybe_never || call_passed) | |
834 | && may_trap_p (src))) | |
835 | { | |
836 | register struct movable *m; | |
837 | register int regno = REGNO (SET_DEST (set)); | |
838 | ||
839 | /* A potential lossage is where we have a case where two insns | |
840 | can be combined as long as they are both in the loop, but | |
841 | we move one of them outside the loop. For large loops, | |
842 | this can lose. The most common case of this is the address | |
843 | of a function being called. | |
844 | ||
845 | Therefore, if this register is marked as being used exactly | |
846 | once if we are in a loop with calls (a "large loop"), see if | |
847 | we can replace the usage of this register with the source | |
848 | of this SET. If we can, delete this insn. | |
849 | ||
850 | Don't do this if P has a REG_RETVAL note or if we have | |
851 | SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */ | |
852 | ||
3c748bb6 | 853 | if (loop_info->has_call |
d6b44532 | 854 | && VARRAY_RTX (reg_single_usage, regno) != 0 |
8deb8e2c | 855 | && VARRAY_RTX (reg_single_usage, regno) != const0_rtx |
b1f21e0a MM |
856 | && REGNO_FIRST_UID (regno) == INSN_UID (p) |
857 | && (REGNO_LAST_UID (regno) | |
8deb8e2c | 858 | == INSN_UID (VARRAY_RTX (reg_single_usage, regno))) |
4b259e3f | 859 | && VARRAY_INT (set_in_loop, regno) == 1 |
b4ad7b23 | 860 | && ! side_effects_p (SET_SRC (set)) |
5fd8383e | 861 | && ! find_reg_note (p, REG_RETVAL, NULL_RTX) |
e9a25f70 JL |
862 | && (! SMALL_REGISTER_CLASSES |
863 | || (! (GET_CODE (SET_SRC (set)) == REG | |
864 | && REGNO (SET_SRC (set)) < FIRST_PSEUDO_REGISTER))) | |
b4ad7b23 RS |
865 | /* This test is not redundant; SET_SRC (set) might be |
866 | a call-clobbered register and the life of REGNO | |
867 | might span a call. */ | |
868 | && ! modified_between_p (SET_SRC (set), p, | |
8deb8e2c MM |
869 | VARRAY_RTX |
870 | (reg_single_usage, regno)) | |
871 | && no_labels_between_p (p, VARRAY_RTX (reg_single_usage, regno)) | |
b4ad7b23 | 872 | && validate_replace_rtx (SET_DEST (set), SET_SRC (set), |
8deb8e2c MM |
873 | VARRAY_RTX |
874 | (reg_single_usage, regno))) | |
b4ad7b23 | 875 | { |
5eeedd4d JW |
876 | /* Replace any usage in a REG_EQUAL note. Must copy the |
877 | new source, so that we don't get rtx sharing between the | |
878 | SET_SOURCE and REG_NOTES of insn p. */ | |
8deb8e2c MM |
879 | REG_NOTES (VARRAY_RTX (reg_single_usage, regno)) |
880 | = replace_rtx (REG_NOTES (VARRAY_RTX | |
881 | (reg_single_usage, regno)), | |
5eeedd4d | 882 | SET_DEST (set), copy_rtx (SET_SRC (set))); |
b4ad7b23 RS |
883 | |
884 | PUT_CODE (p, NOTE); | |
885 | NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; | |
886 | NOTE_SOURCE_FILE (p) = 0; | |
4b259e3f | 887 | VARRAY_INT (set_in_loop, regno) = 0; |
b4ad7b23 RS |
888 | continue; |
889 | } | |
890 | ||
891 | m = (struct movable *) alloca (sizeof (struct movable)); | |
892 | m->next = 0; | |
893 | m->insn = p; | |
894 | m->set_src = src; | |
895 | m->dependencies = dependencies; | |
896 | m->set_dest = SET_DEST (set); | |
897 | m->force = 0; | |
4b259e3f | 898 | m->consec = VARRAY_INT (set_in_loop, |
8deb8e2c | 899 | REGNO (SET_DEST (set))) - 1; |
b4ad7b23 RS |
900 | m->done = 0; |
901 | m->forces = 0; | |
902 | m->partial = 0; | |
903 | m->move_insn = move_insn; | |
1a61c29f | 904 | m->move_insn_first = 0; |
5fd8383e | 905 | m->is_equiv = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0); |
b4ad7b23 RS |
906 | m->savemode = VOIDmode; |
907 | m->regno = regno; | |
908 | /* Set M->cond if either invariant_p or consec_sets_invariant_p | |
909 | returned 2 (only conditionally invariant). */ | |
910 | m->cond = ((tem | tem1 | tem2) > 1); | |
a2be868f MH |
911 | m->global = (uid_luid[REGNO_LAST_UID (regno)] |
912 | > INSN_LUID (loop_end) | |
b1f21e0a | 913 | || uid_luid[REGNO_FIRST_UID (regno)] < INSN_LUID (loop_start)); |
b4ad7b23 | 914 | m->match = 0; |
b1f21e0a MM |
915 | m->lifetime = (uid_luid[REGNO_LAST_UID (regno)] |
916 | - uid_luid[REGNO_FIRST_UID (regno)]); | |
4b259e3f | 917 | m->savings = VARRAY_INT (n_times_set, regno); |
5fd8383e | 918 | if (find_reg_note (p, REG_RETVAL, NULL_RTX)) |
b4ad7b23 | 919 | m->savings += libcall_benefit (p); |
4b259e3f | 920 | VARRAY_INT (set_in_loop, regno) = move_insn ? -2 : -1; |
b4ad7b23 RS |
921 | /* Add M to the end of the chain MOVABLES. */ |
922 | if (movables == 0) | |
923 | movables = m; | |
924 | else | |
925 | last_movable->next = m; | |
926 | last_movable = m; | |
927 | ||
928 | if (m->consec > 0) | |
929 | { | |
1a61c29f JW |
930 | /* It is possible for the first instruction to have a |
931 | REG_EQUAL note but a non-invariant SET_SRC, so we must | |
932 | remember the status of the first instruction in case | |
933 | the last instruction doesn't have a REG_EQUAL note. */ | |
934 | m->move_insn_first = m->move_insn; | |
935 | ||
b4ad7b23 | 936 | /* Skip this insn, not checking REG_LIBCALL notes. */ |
202a34fd | 937 | p = next_nonnote_insn (p); |
b4ad7b23 RS |
938 | /* Skip the consecutive insns, if there are any. */ |
939 | p = skip_consec_insns (p, m->consec); | |
940 | /* Back up to the last insn of the consecutive group. */ | |
941 | p = prev_nonnote_insn (p); | |
942 | ||
943 | /* We must now reset m->move_insn, m->is_equiv, and possibly | |
944 | m->set_src to correspond to the effects of all the | |
945 | insns. */ | |
5fd8383e | 946 | temp = find_reg_note (p, REG_EQUIV, NULL_RTX); |
b4ad7b23 RS |
947 | if (temp) |
948 | m->set_src = XEXP (temp, 0), m->move_insn = 1; | |
949 | else | |
950 | { | |
5fd8383e | 951 | temp = find_reg_note (p, REG_EQUAL, NULL_RTX); |
b4ad7b23 RS |
952 | if (temp && CONSTANT_P (XEXP (temp, 0))) |
953 | m->set_src = XEXP (temp, 0), m->move_insn = 1; | |
954 | else | |
955 | m->move_insn = 0; | |
956 | ||
957 | } | |
5fd8383e | 958 | m->is_equiv = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0); |
b4ad7b23 RS |
959 | } |
960 | } | |
961 | /* If this register is always set within a STRICT_LOW_PART | |
962 | or set to zero, then its high bytes are constant. | |
963 | So clear them outside the loop and within the loop | |
964 | just load the low bytes. | |
965 | We must check that the machine has an instruction to do so. | |
966 | Also, if the value loaded into the register | |
967 | depends on the same register, this cannot be done. */ | |
968 | else if (SET_SRC (set) == const0_rtx | |
969 | && GET_CODE (NEXT_INSN (p)) == INSN | |
970 | && (set1 = single_set (NEXT_INSN (p))) | |
971 | && GET_CODE (set1) == SET | |
972 | && (GET_CODE (SET_DEST (set1)) == STRICT_LOW_PART) | |
973 | && (GET_CODE (XEXP (SET_DEST (set1), 0)) == SUBREG) | |
974 | && (SUBREG_REG (XEXP (SET_DEST (set1), 0)) | |
975 | == SET_DEST (set)) | |
976 | && !reg_mentioned_p (SET_DEST (set), SET_SRC (set1))) | |
977 | { | |
978 | register int regno = REGNO (SET_DEST (set)); | |
4b259e3f | 979 | if (VARRAY_INT (set_in_loop, regno) == 2) |
b4ad7b23 RS |
980 | { |
981 | register struct movable *m; | |
982 | m = (struct movable *) alloca (sizeof (struct movable)); | |
983 | m->next = 0; | |
984 | m->insn = p; | |
985 | m->set_dest = SET_DEST (set); | |
986 | m->dependencies = 0; | |
987 | m->force = 0; | |
988 | m->consec = 0; | |
989 | m->done = 0; | |
990 | m->forces = 0; | |
991 | m->move_insn = 0; | |
8cf619da | 992 | m->move_insn_first = 0; |
b4ad7b23 RS |
993 | m->partial = 1; |
994 | /* If the insn may not be executed on some cycles, | |
995 | we can't clear the whole reg; clear just high part. | |
996 | Not even if the reg is used only within this loop. | |
997 | Consider this: | |
998 | while (1) | |
999 | while (s != t) { | |
1000 | if (foo ()) x = *s; | |
1001 | use (x); | |
1002 | } | |
1003 | Clearing x before the inner loop could clobber a value | |
1004 | being saved from the last time around the outer loop. | |
1005 | However, if the reg is not used outside this loop | |
1006 | and all uses of the register are in the same | |
1007 | basic block as the store, there is no problem. | |
1008 | ||
1009 | If this insn was made by loop, we don't know its | |
1010 | INSN_LUID and hence must make a conservative | |
0f41302f | 1011 | assumption. */ |
b4ad7b23 | 1012 | m->global = (INSN_UID (p) >= max_uid_for_loop |
b1f21e0a | 1013 | || (uid_luid[REGNO_LAST_UID (regno)] |
a2be868f | 1014 | > INSN_LUID (loop_end)) |
b1f21e0a | 1015 | || (uid_luid[REGNO_FIRST_UID (regno)] |
b4ad7b23 RS |
1016 | < INSN_LUID (p)) |
1017 | || (labels_in_range_p | |
b1f21e0a | 1018 | (p, uid_luid[REGNO_FIRST_UID (regno)]))); |
b4ad7b23 RS |
1019 | if (maybe_never && m->global) |
1020 | m->savemode = GET_MODE (SET_SRC (set1)); | |
1021 | else | |
1022 | m->savemode = VOIDmode; | |
1023 | m->regno = regno; | |
1024 | m->cond = 0; | |
1025 | m->match = 0; | |
b1f21e0a MM |
1026 | m->lifetime = (uid_luid[REGNO_LAST_UID (regno)] |
1027 | - uid_luid[REGNO_FIRST_UID (regno)]); | |
b4ad7b23 | 1028 | m->savings = 1; |
4b259e3f | 1029 | VARRAY_INT (set_in_loop, regno) = -1; |
b4ad7b23 RS |
1030 | /* Add M to the end of the chain MOVABLES. */ |
1031 | if (movables == 0) | |
1032 | movables = m; | |
1033 | else | |
1034 | last_movable->next = m; | |
1035 | last_movable = m; | |
1036 | } | |
1037 | } | |
1038 | } | |
1039 | /* Past a call insn, we get to insns which might not be executed | |
1040 | because the call might exit. This matters for insns that trap. | |
1041 | Call insns inside a REG_LIBCALL/REG_RETVAL block always return, | |
1042 | so they don't count. */ | |
1043 | else if (GET_CODE (p) == CALL_INSN && ! in_libcall) | |
1044 | call_passed = 1; | |
1045 | /* Past a label or a jump, we get to insns for which we | |
1046 | can't count on whether or how many times they will be | |
1047 | executed during each iteration. Therefore, we can | |
1048 | only move out sets of trivial variables | |
1049 | (those not used after the loop). */ | |
8516af93 | 1050 | /* Similar code appears twice in strength_reduce. */ |
b4ad7b23 RS |
1051 | else if ((GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN) |
1052 | /* If we enter the loop in the middle, and scan around to the | |
1053 | beginning, don't set maybe_never for that. This must be an | |
1054 | unconditional jump, otherwise the code at the top of the | |
1055 | loop might never be executed. Unconditional jumps are | |
1056 | followed a by barrier then loop end. */ | |
a2be868f MH |
1057 | && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop->top |
1058 | && NEXT_INSN (NEXT_INSN (p)) == loop_end | |
b4ad7b23 RS |
1059 | && simplejump_p (p))) |
1060 | maybe_never = 1; | |
5ea7a4ae JW |
1061 | else if (GET_CODE (p) == NOTE) |
1062 | { | |
1063 | /* At the virtual top of a converted loop, insns are again known to | |
1064 | be executed: logically, the loop begins here even though the exit | |
1065 | code has been duplicated. */ | |
1066 | if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP && loop_depth == 0) | |
1067 | maybe_never = call_passed = 0; | |
1068 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) | |
1069 | loop_depth++; | |
1070 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END) | |
1071 | loop_depth--; | |
1072 | } | |
b4ad7b23 RS |
1073 | } |
1074 | ||
1075 | /* If one movable subsumes another, ignore that other. */ | |
1076 | ||
1077 | ignore_some_movables (movables); | |
1078 | ||
1079 | /* For each movable insn, see if the reg that it loads | |
1080 | leads when it dies right into another conditionally movable insn. | |
1081 | If so, record that the second insn "forces" the first one, | |
1082 | since the second can be moved only if the first is. */ | |
1083 | ||
1084 | force_movables (movables); | |
1085 | ||
1086 | /* See if there are multiple movable insns that load the same value. | |
1087 | If there are, make all but the first point at the first one | |
1088 | through the `match' field, and add the priorities of them | |
1089 | all together as the priority of the first. */ | |
1090 | ||
1091 | combine_movables (movables, nregs); | |
1092 | ||
1093 | /* Now consider each movable insn to decide whether it is worth moving. | |
4b259e3f | 1094 | Store 0 in set_in_loop for each reg that is moved. |
b4ad7b23 | 1095 | |
9dd07f87 R |
1096 | Generally this increases code size, so do not move moveables when |
1097 | optimizing for code size. */ | |
1098 | ||
1099 | if (! optimize_size) | |
1100 | move_movables (movables, threshold, | |
a2be868f | 1101 | insn_count, loop_start, loop_end, nregs); |
b4ad7b23 RS |
1102 | |
1103 | /* Now candidates that still are negative are those not moved. | |
4b259e3f | 1104 | Change set_in_loop to indicate that those are not actually invariant. */ |
b4ad7b23 | 1105 | for (i = 0; i < nregs; i++) |
4b259e3f R |
1106 | if (VARRAY_INT (set_in_loop, i) < 0) |
1107 | VARRAY_INT (set_in_loop, i) = VARRAY_INT (n_times_set, i); | |
b4ad7b23 | 1108 | |
3ec2b590 | 1109 | /* Now that we've moved some things out of the loop, we might be able to |
d6b44532 | 1110 | hoist even more memory references. */ |
a2be868f | 1111 | load_mems_and_recount_loop_regs_set (loop, &insn_count); |
4b259e3f | 1112 | |
0a326ec9 BS |
1113 | for (update_start = loop_start; |
1114 | PREV_INSN (update_start) && GET_CODE (PREV_INSN (update_start)) != CODE_LABEL; | |
1115 | update_start = PREV_INSN (update_start)) | |
1116 | ; | |
a2be868f | 1117 | update_end = NEXT_INSN (loop_end); |
0a326ec9 BS |
1118 | |
1119 | reg_scan_update (update_start, update_end, loop_max_reg); | |
1120 | loop_max_reg = max_reg_num (); | |
1121 | ||
b4ad7b23 | 1122 | if (flag_strength_reduce) |
45f97e2e RH |
1123 | { |
1124 | the_movables = movables; | |
a2be868f | 1125 | strength_reduce (loop, insn_count, unroll_p, bct_p); |
0a326ec9 BS |
1126 | |
1127 | reg_scan_update (update_start, update_end, loop_max_reg); | |
1128 | loop_max_reg = max_reg_num (); | |
45f97e2e | 1129 | } |
8deb8e2c | 1130 | |
d6b44532 | 1131 | VARRAY_FREE (reg_single_usage); |
4b259e3f | 1132 | VARRAY_FREE (set_in_loop); |
8deb8e2c | 1133 | VARRAY_FREE (n_times_set); |
8deb8e2c | 1134 | VARRAY_FREE (may_not_optimize); |
b4ad7b23 RS |
1135 | } |
1136 | \f | |
1137 | /* Add elements to *OUTPUT to record all the pseudo-regs | |
1138 | mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */ | |
1139 | ||
1140 | void | |
1141 | record_excess_regs (in_this, not_in_this, output) | |
1142 | rtx in_this, not_in_this; | |
1143 | rtx *output; | |
1144 | { | |
1145 | enum rtx_code code; | |
6f7d635c | 1146 | const char *fmt; |
b4ad7b23 RS |
1147 | int i; |
1148 | ||
1149 | code = GET_CODE (in_this); | |
1150 | ||
1151 | switch (code) | |
1152 | { | |
1153 | case PC: | |
1154 | case CC0: | |
1155 | case CONST_INT: | |
1156 | case CONST_DOUBLE: | |
1157 | case CONST: | |
1158 | case SYMBOL_REF: | |
1159 | case LABEL_REF: | |
1160 | return; | |
1161 | ||
1162 | case REG: | |
1163 | if (REGNO (in_this) >= FIRST_PSEUDO_REGISTER | |
1164 | && ! reg_mentioned_p (in_this, not_in_this)) | |
38a448ca | 1165 | *output = gen_rtx_EXPR_LIST (VOIDmode, in_this, *output); |
b4ad7b23 | 1166 | return; |
e9a25f70 JL |
1167 | |
1168 | default: | |
1169 | break; | |
b4ad7b23 RS |
1170 | } |
1171 | ||
1172 | fmt = GET_RTX_FORMAT (code); | |
1173 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1174 | { | |
1175 | int j; | |
1176 | ||
1177 | switch (fmt[i]) | |
1178 | { | |
1179 | case 'E': | |
1180 | for (j = 0; j < XVECLEN (in_this, i); j++) | |
1181 | record_excess_regs (XVECEXP (in_this, i, j), not_in_this, output); | |
1182 | break; | |
1183 | ||
1184 | case 'e': | |
1185 | record_excess_regs (XEXP (in_this, i), not_in_this, output); | |
1186 | break; | |
1187 | } | |
1188 | } | |
1189 | } | |
1190 | \f | |
1191 | /* Check what regs are referred to in the libcall block ending with INSN, | |
1192 | aside from those mentioned in the equivalent value. | |
1193 | If there are none, return 0. | |
1194 | If there are one or more, return an EXPR_LIST containing all of them. */ | |
1195 | ||
89d3d442 | 1196 | rtx |
b4ad7b23 RS |
1197 | libcall_other_reg (insn, equiv) |
1198 | rtx insn, equiv; | |
1199 | { | |
5fd8383e | 1200 | rtx note = find_reg_note (insn, REG_RETVAL, NULL_RTX); |
b4ad7b23 RS |
1201 | rtx p = XEXP (note, 0); |
1202 | rtx output = 0; | |
1203 | ||
1204 | /* First, find all the regs used in the libcall block | |
1205 | that are not mentioned as inputs to the result. */ | |
1206 | ||
1207 | while (p != insn) | |
1208 | { | |
1209 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN | |
1210 | || GET_CODE (p) == CALL_INSN) | |
1211 | record_excess_regs (PATTERN (p), equiv, &output); | |
1212 | p = NEXT_INSN (p); | |
1213 | } | |
1214 | ||
1215 | return output; | |
1216 | } | |
1217 | \f | |
1218 | /* Return 1 if all uses of REG | |
1219 | are between INSN and the end of the basic block. */ | |
1220 | ||
1221 | static int | |
1222 | reg_in_basic_block_p (insn, reg) | |
1223 | rtx insn, reg; | |
1224 | { | |
1225 | int regno = REGNO (reg); | |
1226 | rtx p; | |
1227 | ||
b1f21e0a | 1228 | if (REGNO_FIRST_UID (regno) != INSN_UID (insn)) |
b4ad7b23 RS |
1229 | return 0; |
1230 | ||
1231 | /* Search this basic block for the already recorded last use of the reg. */ | |
1232 | for (p = insn; p; p = NEXT_INSN (p)) | |
1233 | { | |
1234 | switch (GET_CODE (p)) | |
1235 | { | |
1236 | case NOTE: | |
1237 | break; | |
1238 | ||
1239 | case INSN: | |
1240 | case CALL_INSN: | |
1241 | /* Ordinary insn: if this is the last use, we win. */ | |
b1f21e0a | 1242 | if (REGNO_LAST_UID (regno) == INSN_UID (p)) |
b4ad7b23 RS |
1243 | return 1; |
1244 | break; | |
1245 | ||
1246 | case JUMP_INSN: | |
1247 | /* Jump insn: if this is the last use, we win. */ | |
b1f21e0a | 1248 | if (REGNO_LAST_UID (regno) == INSN_UID (p)) |
b4ad7b23 RS |
1249 | return 1; |
1250 | /* Otherwise, it's the end of the basic block, so we lose. */ | |
1251 | return 0; | |
1252 | ||
1253 | case CODE_LABEL: | |
1254 | case BARRIER: | |
1255 | /* It's the end of the basic block, so we lose. */ | |
1256 | return 0; | |
e9a25f70 JL |
1257 | |
1258 | default: | |
1259 | break; | |
b4ad7b23 RS |
1260 | } |
1261 | } | |
1262 | ||
1263 | /* The "last use" doesn't follow the "first use"?? */ | |
1264 | abort (); | |
1265 | } | |
1266 | \f | |
1267 | /* Compute the benefit of eliminating the insns in the block whose | |
1268 | last insn is LAST. This may be a group of insns used to compute a | |
1269 | value directly or can contain a library call. */ | |
1270 | ||
1271 | static int | |
1272 | libcall_benefit (last) | |
1273 | rtx last; | |
1274 | { | |
1275 | rtx insn; | |
1276 | int benefit = 0; | |
1277 | ||
5fd8383e | 1278 | for (insn = XEXP (find_reg_note (last, REG_RETVAL, NULL_RTX), 0); |
b4ad7b23 RS |
1279 | insn != last; insn = NEXT_INSN (insn)) |
1280 | { | |
1281 | if (GET_CODE (insn) == CALL_INSN) | |
1282 | benefit += 10; /* Assume at least this many insns in a library | |
0f41302f | 1283 | routine. */ |
b4ad7b23 RS |
1284 | else if (GET_CODE (insn) == INSN |
1285 | && GET_CODE (PATTERN (insn)) != USE | |
1286 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
1287 | benefit++; | |
1288 | } | |
1289 | ||
1290 | return benefit; | |
1291 | } | |
1292 | \f | |
1293 | /* Skip COUNT insns from INSN, counting library calls as 1 insn. */ | |
1294 | ||
1295 | static rtx | |
1296 | skip_consec_insns (insn, count) | |
1297 | rtx insn; | |
1298 | int count; | |
1299 | { | |
1300 | for (; count > 0; count--) | |
1301 | { | |
1302 | rtx temp; | |
1303 | ||
1304 | /* If first insn of libcall sequence, skip to end. */ | |
1305 | /* Do this at start of loop, since INSN is guaranteed to | |
1306 | be an insn here. */ | |
1307 | if (GET_CODE (insn) != NOTE | |
5fd8383e | 1308 | && (temp = find_reg_note (insn, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
1309 | insn = XEXP (temp, 0); |
1310 | ||
1311 | do insn = NEXT_INSN (insn); | |
1312 | while (GET_CODE (insn) == NOTE); | |
1313 | } | |
1314 | ||
1315 | return insn; | |
1316 | } | |
1317 | ||
1318 | /* Ignore any movable whose insn falls within a libcall | |
1319 | which is part of another movable. | |
1320 | We make use of the fact that the movable for the libcall value | |
1321 | was made later and so appears later on the chain. */ | |
1322 | ||
1323 | static void | |
1324 | ignore_some_movables (movables) | |
1325 | struct movable *movables; | |
1326 | { | |
1327 | register struct movable *m, *m1; | |
1328 | ||
1329 | for (m = movables; m; m = m->next) | |
1330 | { | |
1331 | /* Is this a movable for the value of a libcall? */ | |
5fd8383e | 1332 | rtx note = find_reg_note (m->insn, REG_RETVAL, NULL_RTX); |
b4ad7b23 RS |
1333 | if (note) |
1334 | { | |
1335 | rtx insn; | |
1336 | /* Check for earlier movables inside that range, | |
1337 | and mark them invalid. We cannot use LUIDs here because | |
1338 | insns created by loop.c for prior loops don't have LUIDs. | |
1339 | Rather than reject all such insns from movables, we just | |
1340 | explicitly check each insn in the libcall (since invariant | |
1341 | libcalls aren't that common). */ | |
1342 | for (insn = XEXP (note, 0); insn != m->insn; insn = NEXT_INSN (insn)) | |
1343 | for (m1 = movables; m1 != m; m1 = m1->next) | |
1344 | if (m1->insn == insn) | |
1345 | m1->done = 1; | |
1346 | } | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | /* For each movable insn, see if the reg that it loads | |
1351 | leads when it dies right into another conditionally movable insn. | |
1352 | If so, record that the second insn "forces" the first one, | |
1353 | since the second can be moved only if the first is. */ | |
1354 | ||
1355 | static void | |
1356 | force_movables (movables) | |
1357 | struct movable *movables; | |
1358 | { | |
1359 | register struct movable *m, *m1; | |
1360 | for (m1 = movables; m1; m1 = m1->next) | |
1361 | /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */ | |
1362 | if (!m1->partial && !m1->done) | |
1363 | { | |
1364 | int regno = m1->regno; | |
1365 | for (m = m1->next; m; m = m->next) | |
1366 | /* ??? Could this be a bug? What if CSE caused the | |
1367 | register of M1 to be used after this insn? | |
1368 | Since CSE does not update regno_last_uid, | |
1369 | this insn M->insn might not be where it dies. | |
1370 | But very likely this doesn't matter; what matters is | |
1371 | that M's reg is computed from M1's reg. */ | |
b1f21e0a | 1372 | if (INSN_UID (m->insn) == REGNO_LAST_UID (regno) |
b4ad7b23 RS |
1373 | && !m->done) |
1374 | break; | |
1375 | if (m != 0 && m->set_src == m1->set_dest | |
1376 | /* If m->consec, m->set_src isn't valid. */ | |
1377 | && m->consec == 0) | |
1378 | m = 0; | |
1379 | ||
1380 | /* Increase the priority of the moving the first insn | |
1381 | since it permits the second to be moved as well. */ | |
1382 | if (m != 0) | |
1383 | { | |
1384 | m->forces = m1; | |
1385 | m1->lifetime += m->lifetime; | |
3875b31d | 1386 | m1->savings += m->savings; |
b4ad7b23 RS |
1387 | } |
1388 | } | |
1389 | } | |
1390 | \f | |
1391 | /* Find invariant expressions that are equal and can be combined into | |
1392 | one register. */ | |
1393 | ||
1394 | static void | |
1395 | combine_movables (movables, nregs) | |
1396 | struct movable *movables; | |
1397 | int nregs; | |
1398 | { | |
1399 | register struct movable *m; | |
4da896b2 | 1400 | char *matched_regs = (char *) xmalloc (nregs); |
b4ad7b23 RS |
1401 | enum machine_mode mode; |
1402 | ||
1403 | /* Regs that are set more than once are not allowed to match | |
1404 | or be matched. I'm no longer sure why not. */ | |
1405 | /* Perhaps testing m->consec_sets would be more appropriate here? */ | |
1406 | ||
1407 | for (m = movables; m; m = m->next) | |
4b259e3f | 1408 | if (m->match == 0 && VARRAY_INT (n_times_set, m->regno) == 1 && !m->partial) |
b4ad7b23 RS |
1409 | { |
1410 | register struct movable *m1; | |
1411 | int regno = m->regno; | |
b4ad7b23 RS |
1412 | |
1413 | bzero (matched_regs, nregs); | |
1414 | matched_regs[regno] = 1; | |
1415 | ||
88016fb7 DE |
1416 | /* We want later insns to match the first one. Don't make the first |
1417 | one match any later ones. So start this loop at m->next. */ | |
1418 | for (m1 = m->next; m1; m1 = m1->next) | |
4b259e3f | 1419 | if (m != m1 && m1->match == 0 && VARRAY_INT (n_times_set, m1->regno) == 1 |
b4ad7b23 RS |
1420 | /* A reg used outside the loop mustn't be eliminated. */ |
1421 | && !m1->global | |
1422 | /* A reg used for zero-extending mustn't be eliminated. */ | |
1423 | && !m1->partial | |
1424 | && (matched_regs[m1->regno] | |
1425 | || | |
1426 | ( | |
1427 | /* Can combine regs with different modes loaded from the | |
1428 | same constant only if the modes are the same or | |
1429 | if both are integer modes with M wider or the same | |
1430 | width as M1. The check for integer is redundant, but | |
1431 | safe, since the only case of differing destination | |
1432 | modes with equal sources is when both sources are | |
1433 | VOIDmode, i.e., CONST_INT. */ | |
1434 | (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest) | |
1435 | || (GET_MODE_CLASS (GET_MODE (m->set_dest)) == MODE_INT | |
1436 | && GET_MODE_CLASS (GET_MODE (m1->set_dest)) == MODE_INT | |
1437 | && (GET_MODE_BITSIZE (GET_MODE (m->set_dest)) | |
1438 | >= GET_MODE_BITSIZE (GET_MODE (m1->set_dest))))) | |
1439 | /* See if the source of M1 says it matches M. */ | |
1440 | && ((GET_CODE (m1->set_src) == REG | |
1441 | && matched_regs[REGNO (m1->set_src)]) | |
1442 | || rtx_equal_for_loop_p (m->set_src, m1->set_src, | |
1443 | movables)))) | |
1444 | && ((m->dependencies == m1->dependencies) | |
1445 | || rtx_equal_p (m->dependencies, m1->dependencies))) | |
1446 | { | |
1447 | m->lifetime += m1->lifetime; | |
1448 | m->savings += m1->savings; | |
1449 | m1->done = 1; | |
1450 | m1->match = m; | |
1451 | matched_regs[m1->regno] = 1; | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | /* Now combine the regs used for zero-extension. | |
1456 | This can be done for those not marked `global' | |
1457 | provided their lives don't overlap. */ | |
1458 | ||
1459 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
1460 | mode = GET_MODE_WIDER_MODE (mode)) | |
1461 | { | |
1462 | register struct movable *m0 = 0; | |
1463 | ||
1464 | /* Combine all the registers for extension from mode MODE. | |
1465 | Don't combine any that are used outside this loop. */ | |
1466 | for (m = movables; m; m = m->next) | |
1467 | if (m->partial && ! m->global | |
1468 | && mode == GET_MODE (SET_SRC (PATTERN (NEXT_INSN (m->insn))))) | |
1469 | { | |
1470 | register struct movable *m1; | |
b1f21e0a MM |
1471 | int first = uid_luid[REGNO_FIRST_UID (m->regno)]; |
1472 | int last = uid_luid[REGNO_LAST_UID (m->regno)]; | |
b4ad7b23 RS |
1473 | |
1474 | if (m0 == 0) | |
1475 | { | |
1476 | /* First one: don't check for overlap, just record it. */ | |
1477 | m0 = m; | |
1478 | continue; | |
1479 | } | |
1480 | ||
1481 | /* Make sure they extend to the same mode. | |
1482 | (Almost always true.) */ | |
1483 | if (GET_MODE (m->set_dest) != GET_MODE (m0->set_dest)) | |
1484 | continue; | |
1485 | ||
1486 | /* We already have one: check for overlap with those | |
1487 | already combined together. */ | |
1488 | for (m1 = movables; m1 != m; m1 = m1->next) | |
1489 | if (m1 == m0 || (m1->partial && m1->match == m0)) | |
b1f21e0a MM |
1490 | if (! (uid_luid[REGNO_FIRST_UID (m1->regno)] > last |
1491 | || uid_luid[REGNO_LAST_UID (m1->regno)] < first)) | |
b4ad7b23 RS |
1492 | goto overlap; |
1493 | ||
1494 | /* No overlap: we can combine this with the others. */ | |
1495 | m0->lifetime += m->lifetime; | |
1496 | m0->savings += m->savings; | |
1497 | m->done = 1; | |
1498 | m->match = m0; | |
1499 | ||
1500 | overlap: ; | |
1501 | } | |
1502 | } | |
4da896b2 MM |
1503 | |
1504 | /* Clean up. */ | |
1505 | free (matched_regs); | |
b4ad7b23 RS |
1506 | } |
1507 | \f | |
1508 | /* Return 1 if regs X and Y will become the same if moved. */ | |
1509 | ||
1510 | static int | |
1511 | regs_match_p (x, y, movables) | |
1512 | rtx x, y; | |
1513 | struct movable *movables; | |
1514 | { | |
1515 | int xn = REGNO (x); | |
1516 | int yn = REGNO (y); | |
1517 | struct movable *mx, *my; | |
1518 | ||
1519 | for (mx = movables; mx; mx = mx->next) | |
1520 | if (mx->regno == xn) | |
1521 | break; | |
1522 | ||
1523 | for (my = movables; my; my = my->next) | |
1524 | if (my->regno == yn) | |
1525 | break; | |
1526 | ||
1527 | return (mx && my | |
1528 | && ((mx->match == my->match && mx->match != 0) | |
1529 | || mx->match == my | |
1530 | || mx == my->match)); | |
1531 | } | |
1532 | ||
1533 | /* Return 1 if X and Y are identical-looking rtx's. | |
1534 | This is the Lisp function EQUAL for rtx arguments. | |
1535 | ||
1536 | If two registers are matching movables or a movable register and an | |
1537 | equivalent constant, consider them equal. */ | |
1538 | ||
1539 | static int | |
1540 | rtx_equal_for_loop_p (x, y, movables) | |
1541 | rtx x, y; | |
1542 | struct movable *movables; | |
1543 | { | |
1544 | register int i; | |
1545 | register int j; | |
1546 | register struct movable *m; | |
1547 | register enum rtx_code code; | |
6f7d635c | 1548 | register const char *fmt; |
b4ad7b23 RS |
1549 | |
1550 | if (x == y) | |
1551 | return 1; | |
1552 | if (x == 0 || y == 0) | |
1553 | return 0; | |
1554 | ||
1555 | code = GET_CODE (x); | |
1556 | ||
1557 | /* If we have a register and a constant, they may sometimes be | |
1558 | equal. */ | |
4b259e3f | 1559 | if (GET_CODE (x) == REG && VARRAY_INT (set_in_loop, REGNO (x)) == -2 |
b4ad7b23 | 1560 | && CONSTANT_P (y)) |
b1a0c816 JL |
1561 | { |
1562 | for (m = movables; m; m = m->next) | |
1563 | if (m->move_insn && m->regno == REGNO (x) | |
1564 | && rtx_equal_p (m->set_src, y)) | |
1565 | return 1; | |
1566 | } | |
4b259e3f | 1567 | else if (GET_CODE (y) == REG && VARRAY_INT (set_in_loop, REGNO (y)) == -2 |
b4ad7b23 | 1568 | && CONSTANT_P (x)) |
b1a0c816 JL |
1569 | { |
1570 | for (m = movables; m; m = m->next) | |
1571 | if (m->move_insn && m->regno == REGNO (y) | |
1572 | && rtx_equal_p (m->set_src, x)) | |
1573 | return 1; | |
1574 | } | |
b4ad7b23 RS |
1575 | |
1576 | /* Otherwise, rtx's of different codes cannot be equal. */ | |
1577 | if (code != GET_CODE (y)) | |
1578 | return 0; | |
1579 | ||
1580 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. | |
1581 | (REG:SI x) and (REG:HI x) are NOT equivalent. */ | |
1582 | ||
1583 | if (GET_MODE (x) != GET_MODE (y)) | |
1584 | return 0; | |
1585 | ||
1586 | /* These three types of rtx's can be compared nonrecursively. */ | |
1587 | if (code == REG) | |
1588 | return (REGNO (x) == REGNO (y) || regs_match_p (x, y, movables)); | |
1589 | ||
1590 | if (code == LABEL_REF) | |
1591 | return XEXP (x, 0) == XEXP (y, 0); | |
1592 | if (code == SYMBOL_REF) | |
1593 | return XSTR (x, 0) == XSTR (y, 0); | |
1594 | ||
1595 | /* Compare the elements. If any pair of corresponding elements | |
1596 | fail to match, return 0 for the whole things. */ | |
1597 | ||
1598 | fmt = GET_RTX_FORMAT (code); | |
1599 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1600 | { | |
1601 | switch (fmt[i]) | |
1602 | { | |
5fd8383e RK |
1603 | case 'w': |
1604 | if (XWINT (x, i) != XWINT (y, i)) | |
1605 | return 0; | |
1606 | break; | |
1607 | ||
b4ad7b23 RS |
1608 | case 'i': |
1609 | if (XINT (x, i) != XINT (y, i)) | |
1610 | return 0; | |
1611 | break; | |
1612 | ||
1613 | case 'E': | |
1614 | /* Two vectors must have the same length. */ | |
1615 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
1616 | return 0; | |
1617 | ||
1618 | /* And the corresponding elements must match. */ | |
1619 | for (j = 0; j < XVECLEN (x, i); j++) | |
1620 | if (rtx_equal_for_loop_p (XVECEXP (x, i, j), XVECEXP (y, i, j), movables) == 0) | |
1621 | return 0; | |
1622 | break; | |
1623 | ||
1624 | case 'e': | |
1625 | if (rtx_equal_for_loop_p (XEXP (x, i), XEXP (y, i), movables) == 0) | |
1626 | return 0; | |
1627 | break; | |
1628 | ||
1629 | case 's': | |
1630 | if (strcmp (XSTR (x, i), XSTR (y, i))) | |
1631 | return 0; | |
1632 | break; | |
1633 | ||
1634 | case 'u': | |
1635 | /* These are just backpointers, so they don't matter. */ | |
1636 | break; | |
1637 | ||
1638 | case '0': | |
1639 | break; | |
1640 | ||
1641 | /* It is believed that rtx's at this level will never | |
1642 | contain anything but integers and other rtx's, | |
1643 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
1644 | default: | |
1645 | abort (); | |
1646 | } | |
1647 | } | |
1648 | return 1; | |
1649 | } | |
1650 | \f | |
c160c628 | 1651 | /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all |
3c748bb6 | 1652 | insns in INSNS which use the reference. */ |
c160c628 RK |
1653 | |
1654 | static void | |
1655 | add_label_notes (x, insns) | |
1656 | rtx x; | |
1657 | rtx insns; | |
1658 | { | |
1659 | enum rtx_code code = GET_CODE (x); | |
7dcd3836 | 1660 | int i, j; |
6f7d635c | 1661 | const char *fmt; |
c160c628 RK |
1662 | rtx insn; |
1663 | ||
82d00367 | 1664 | if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x)) |
c160c628 | 1665 | { |
6b3603c2 JL |
1666 | /* This code used to ignore labels that referred to dispatch tables to |
1667 | avoid flow generating (slighly) worse code. | |
1668 | ||
1669 | We no longer ignore such label references (see LABEL_REF handling in | |
1670 | mark_jump_label for additional information). */ | |
1671 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
1672 | if (reg_mentioned_p (XEXP (x, 0), insn)) | |
1673 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_LABEL, XEXP (x, 0), | |
1674 | REG_NOTES (insn)); | |
c160c628 RK |
1675 | } |
1676 | ||
1677 | fmt = GET_RTX_FORMAT (code); | |
1678 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7dcd3836 RK |
1679 | { |
1680 | if (fmt[i] == 'e') | |
1681 | add_label_notes (XEXP (x, i), insns); | |
1682 | else if (fmt[i] == 'E') | |
1683 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1684 | add_label_notes (XVECEXP (x, i, j), insns); | |
1685 | } | |
c160c628 RK |
1686 | } |
1687 | \f | |
b4ad7b23 RS |
1688 | /* Scan MOVABLES, and move the insns that deserve to be moved. |
1689 | If two matching movables are combined, replace one reg with the | |
1690 | other throughout. */ | |
1691 | ||
1692 | static void | |
1693 | move_movables (movables, threshold, insn_count, loop_start, end, nregs) | |
1694 | struct movable *movables; | |
1695 | int threshold; | |
1696 | int insn_count; | |
1697 | rtx loop_start; | |
1698 | rtx end; | |
1699 | int nregs; | |
1700 | { | |
1701 | rtx new_start = 0; | |
1702 | register struct movable *m; | |
1703 | register rtx p; | |
1704 | /* Map of pseudo-register replacements to handle combining | |
1705 | when we move several insns that load the same value | |
1706 | into different pseudo-registers. */ | |
4da896b2 MM |
1707 | rtx *reg_map = (rtx *) xcalloc (nregs, sizeof (rtx)); |
1708 | char *already_moved = (char *) xcalloc (nregs, sizeof (char)); | |
b4ad7b23 RS |
1709 | |
1710 | num_movables = 0; | |
1711 | ||
1712 | for (m = movables; m; m = m->next) | |
1713 | { | |
1714 | /* Describe this movable insn. */ | |
1715 | ||
1716 | if (loop_dump_stream) | |
1717 | { | |
1718 | fprintf (loop_dump_stream, "Insn %d: regno %d (life %d), ", | |
1719 | INSN_UID (m->insn), m->regno, m->lifetime); | |
1720 | if (m->consec > 0) | |
1721 | fprintf (loop_dump_stream, "consec %d, ", m->consec); | |
1722 | if (m->cond) | |
1723 | fprintf (loop_dump_stream, "cond "); | |
1724 | if (m->force) | |
1725 | fprintf (loop_dump_stream, "force "); | |
1726 | if (m->global) | |
1727 | fprintf (loop_dump_stream, "global "); | |
1728 | if (m->done) | |
1729 | fprintf (loop_dump_stream, "done "); | |
1730 | if (m->move_insn) | |
1731 | fprintf (loop_dump_stream, "move-insn "); | |
1732 | if (m->match) | |
1733 | fprintf (loop_dump_stream, "matches %d ", | |
1734 | INSN_UID (m->match->insn)); | |
1735 | if (m->forces) | |
1736 | fprintf (loop_dump_stream, "forces %d ", | |
1737 | INSN_UID (m->forces->insn)); | |
1738 | } | |
1739 | ||
1740 | /* Count movables. Value used in heuristics in strength_reduce. */ | |
1741 | num_movables++; | |
1742 | ||
1743 | /* Ignore the insn if it's already done (it matched something else). | |
1744 | Otherwise, see if it is now safe to move. */ | |
1745 | ||
1746 | if (!m->done | |
1747 | && (! m->cond | |
1748 | || (1 == invariant_p (m->set_src) | |
1749 | && (m->dependencies == 0 | |
1750 | || 1 == invariant_p (m->dependencies)) | |
1751 | && (m->consec == 0 | |
1752 | || 1 == consec_sets_invariant_p (m->set_dest, | |
1753 | m->consec + 1, | |
1754 | m->insn)))) | |
1755 | && (! m->forces || m->forces->done)) | |
1756 | { | |
1757 | register int regno; | |
1758 | register rtx p; | |
1759 | int savings = m->savings; | |
1760 | ||
1761 | /* We have an insn that is safe to move. | |
1762 | Compute its desirability. */ | |
1763 | ||
1764 | p = m->insn; | |
1765 | regno = m->regno; | |
1766 | ||
1767 | if (loop_dump_stream) | |
1768 | fprintf (loop_dump_stream, "savings %d ", savings); | |
1769 | ||
877ca132 HB |
1770 | if (moved_once[regno] && loop_dump_stream) |
1771 | fprintf (loop_dump_stream, "halved since already moved "); | |
b4ad7b23 RS |
1772 | |
1773 | /* An insn MUST be moved if we already moved something else | |
1774 | which is safe only if this one is moved too: that is, | |
1775 | if already_moved[REGNO] is nonzero. */ | |
1776 | ||
1777 | /* An insn is desirable to move if the new lifetime of the | |
1778 | register is no more than THRESHOLD times the old lifetime. | |
1779 | If it's not desirable, it means the loop is so big | |
1780 | that moving won't speed things up much, | |
1781 | and it is liable to make register usage worse. */ | |
1782 | ||
1783 | /* It is also desirable to move if it can be moved at no | |
1784 | extra cost because something else was already moved. */ | |
1785 | ||
1786 | if (already_moved[regno] | |
e5eb27e5 | 1787 | || flag_move_all_movables |
877ca132 HB |
1788 | || (threshold * savings * m->lifetime) >= |
1789 | (moved_once[regno] ? insn_count * 2 : insn_count) | |
b4ad7b23 | 1790 | || (m->forces && m->forces->done |
4b259e3f | 1791 | && VARRAY_INT (n_times_set, m->forces->regno) == 1)) |
b4ad7b23 RS |
1792 | { |
1793 | int count; | |
1794 | register struct movable *m1; | |
6a651371 | 1795 | rtx first = NULL_RTX; |
b4ad7b23 RS |
1796 | |
1797 | /* Now move the insns that set the reg. */ | |
1798 | ||
1799 | if (m->partial && m->match) | |
1800 | { | |
1801 | rtx newpat, i1; | |
1802 | rtx r1, r2; | |
1803 | /* Find the end of this chain of matching regs. | |
1804 | Thus, we load each reg in the chain from that one reg. | |
1805 | And that reg is loaded with 0 directly, | |
1806 | since it has ->match == 0. */ | |
1807 | for (m1 = m; m1->match; m1 = m1->match); | |
1808 | newpat = gen_move_insn (SET_DEST (PATTERN (m->insn)), | |
1809 | SET_DEST (PATTERN (m1->insn))); | |
1810 | i1 = emit_insn_before (newpat, loop_start); | |
1811 | ||
1812 | /* Mark the moved, invariant reg as being allowed to | |
1813 | share a hard reg with the other matching invariant. */ | |
1814 | REG_NOTES (i1) = REG_NOTES (m->insn); | |
1815 | r1 = SET_DEST (PATTERN (m->insn)); | |
1816 | r2 = SET_DEST (PATTERN (m1->insn)); | |
38a448ca RH |
1817 | regs_may_share |
1818 | = gen_rtx_EXPR_LIST (VOIDmode, r1, | |
1819 | gen_rtx_EXPR_LIST (VOIDmode, r2, | |
1820 | regs_may_share)); | |
b4ad7b23 RS |
1821 | delete_insn (m->insn); |
1822 | ||
1823 | if (new_start == 0) | |
1824 | new_start = i1; | |
1825 | ||
1826 | if (loop_dump_stream) | |
1827 | fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1)); | |
1828 | } | |
1829 | /* If we are to re-generate the item being moved with a | |
1830 | new move insn, first delete what we have and then emit | |
1831 | the move insn before the loop. */ | |
1832 | else if (m->move_insn) | |
1833 | { | |
1834 | rtx i1, temp; | |
1835 | ||
1836 | for (count = m->consec; count >= 0; count--) | |
1837 | { | |
1838 | /* If this is the first insn of a library call sequence, | |
1839 | skip to the end. */ | |
1840 | if (GET_CODE (p) != NOTE | |
5fd8383e | 1841 | && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
1842 | p = XEXP (temp, 0); |
1843 | ||
1844 | /* If this is the last insn of a libcall sequence, then | |
1845 | delete every insn in the sequence except the last. | |
1846 | The last insn is handled in the normal manner. */ | |
1847 | if (GET_CODE (p) != NOTE | |
5fd8383e | 1848 | && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX))) |
b4ad7b23 RS |
1849 | { |
1850 | temp = XEXP (temp, 0); | |
1851 | while (temp != p) | |
1852 | temp = delete_insn (temp); | |
1853 | } | |
1854 | ||
9655bf95 | 1855 | temp = p; |
b4ad7b23 | 1856 | p = delete_insn (p); |
9655bf95 DM |
1857 | |
1858 | /* simplify_giv_expr expects that it can walk the insns | |
1859 | at m->insn forwards and see this old sequence we are | |
1860 | tossing here. delete_insn does preserve the next | |
1861 | pointers, but when we skip over a NOTE we must fix | |
1862 | it up. Otherwise that code walks into the non-deleted | |
1863 | insn stream. */ | |
dd202606 | 1864 | while (p && GET_CODE (p) == NOTE) |
9655bf95 | 1865 | p = NEXT_INSN (temp) = NEXT_INSN (p); |
b4ad7b23 RS |
1866 | } |
1867 | ||
1868 | start_sequence (); | |
1869 | emit_move_insn (m->set_dest, m->set_src); | |
c160c628 | 1870 | temp = get_insns (); |
b4ad7b23 RS |
1871 | end_sequence (); |
1872 | ||
c160c628 RK |
1873 | add_label_notes (m->set_src, temp); |
1874 | ||
1875 | i1 = emit_insns_before (temp, loop_start); | |
5fd8383e | 1876 | if (! find_reg_note (i1, REG_EQUAL, NULL_RTX)) |
b4ad7b23 | 1877 | REG_NOTES (i1) |
38a448ca RH |
1878 | = gen_rtx_EXPR_LIST (m->is_equiv ? REG_EQUIV : REG_EQUAL, |
1879 | m->set_src, REG_NOTES (i1)); | |
b4ad7b23 RS |
1880 | |
1881 | if (loop_dump_stream) | |
1882 | fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1)); | |
1883 | ||
1884 | /* The more regs we move, the less we like moving them. */ | |
1885 | threshold -= 3; | |
1886 | } | |
1887 | else | |
1888 | { | |
1889 | for (count = m->consec; count >= 0; count--) | |
1890 | { | |
1891 | rtx i1, temp; | |
1892 | ||
0f41302f | 1893 | /* If first insn of libcall sequence, skip to end. */ |
b4ad7b23 RS |
1894 | /* Do this at start of loop, since p is guaranteed to |
1895 | be an insn here. */ | |
1896 | if (GET_CODE (p) != NOTE | |
5fd8383e | 1897 | && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
1898 | p = XEXP (temp, 0); |
1899 | ||
1900 | /* If last insn of libcall sequence, move all | |
1901 | insns except the last before the loop. The last | |
1902 | insn is handled in the normal manner. */ | |
1903 | if (GET_CODE (p) != NOTE | |
5fd8383e | 1904 | && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX))) |
b4ad7b23 RS |
1905 | { |
1906 | rtx fn_address = 0; | |
1907 | rtx fn_reg = 0; | |
1908 | rtx fn_address_insn = 0; | |
1909 | ||
1910 | first = 0; | |
1911 | for (temp = XEXP (temp, 0); temp != p; | |
1912 | temp = NEXT_INSN (temp)) | |
1913 | { | |
1914 | rtx body; | |
1915 | rtx n; | |
1916 | rtx next; | |
1917 | ||
1918 | if (GET_CODE (temp) == NOTE) | |
1919 | continue; | |
1920 | ||
1921 | body = PATTERN (temp); | |
1922 | ||
1923 | /* Find the next insn after TEMP, | |
1924 | not counting USE or NOTE insns. */ | |
1925 | for (next = NEXT_INSN (temp); next != p; | |
1926 | next = NEXT_INSN (next)) | |
1927 | if (! (GET_CODE (next) == INSN | |
1928 | && GET_CODE (PATTERN (next)) == USE) | |
1929 | && GET_CODE (next) != NOTE) | |
1930 | break; | |
1931 | ||
1932 | /* If that is the call, this may be the insn | |
1933 | that loads the function address. | |
1934 | ||
1935 | Extract the function address from the insn | |
1936 | that loads it into a register. | |
1937 | If this insn was cse'd, we get incorrect code. | |
1938 | ||
1939 | So emit a new move insn that copies the | |
1940 | function address into the register that the | |
1941 | call insn will use. flow.c will delete any | |
1942 | redundant stores that we have created. */ | |
1943 | if (GET_CODE (next) == CALL_INSN | |
1944 | && GET_CODE (body) == SET | |
1945 | && GET_CODE (SET_DEST (body)) == REG | |
5fd8383e RK |
1946 | && (n = find_reg_note (temp, REG_EQUAL, |
1947 | NULL_RTX))) | |
b4ad7b23 RS |
1948 | { |
1949 | fn_reg = SET_SRC (body); | |
1950 | if (GET_CODE (fn_reg) != REG) | |
1951 | fn_reg = SET_DEST (body); | |
1952 | fn_address = XEXP (n, 0); | |
1953 | fn_address_insn = temp; | |
1954 | } | |
1955 | /* We have the call insn. | |
1956 | If it uses the register we suspect it might, | |
1957 | load it with the correct address directly. */ | |
1958 | if (GET_CODE (temp) == CALL_INSN | |
1959 | && fn_address != 0 | |
d9f8a199 | 1960 | && reg_referenced_p (fn_reg, body)) |
b4ad7b23 RS |
1961 | emit_insn_after (gen_move_insn (fn_reg, |
1962 | fn_address), | |
1963 | fn_address_insn); | |
1964 | ||
1965 | if (GET_CODE (temp) == CALL_INSN) | |
f97d29ce JW |
1966 | { |
1967 | i1 = emit_call_insn_before (body, loop_start); | |
1968 | /* Because the USAGE information potentially | |
1969 | contains objects other than hard registers | |
1970 | we need to copy it. */ | |
8c4f5c09 | 1971 | if (CALL_INSN_FUNCTION_USAGE (temp)) |
db3cf6fb MS |
1972 | CALL_INSN_FUNCTION_USAGE (i1) |
1973 | = copy_rtx (CALL_INSN_FUNCTION_USAGE (temp)); | |
f97d29ce | 1974 | } |
b4ad7b23 RS |
1975 | else |
1976 | i1 = emit_insn_before (body, loop_start); | |
1977 | if (first == 0) | |
1978 | first = i1; | |
1979 | if (temp == fn_address_insn) | |
1980 | fn_address_insn = i1; | |
1981 | REG_NOTES (i1) = REG_NOTES (temp); | |
1982 | delete_insn (temp); | |
1983 | } | |
18985c91 R |
1984 | if (new_start == 0) |
1985 | new_start = first; | |
b4ad7b23 RS |
1986 | } |
1987 | if (m->savemode != VOIDmode) | |
1988 | { | |
1989 | /* P sets REG to zero; but we should clear only | |
1990 | the bits that are not covered by the mode | |
1991 | m->savemode. */ | |
1992 | rtx reg = m->set_dest; | |
1993 | rtx sequence; | |
1994 | rtx tem; | |
1995 | ||
1996 | start_sequence (); | |
1997 | tem = expand_binop | |
1998 | (GET_MODE (reg), and_optab, reg, | |
5fd8383e RK |
1999 | GEN_INT ((((HOST_WIDE_INT) 1 |
2000 | << GET_MODE_BITSIZE (m->savemode))) | |
b4ad7b23 RS |
2001 | - 1), |
2002 | reg, 1, OPTAB_LIB_WIDEN); | |
2003 | if (tem == 0) | |
2004 | abort (); | |
2005 | if (tem != reg) | |
2006 | emit_move_insn (reg, tem); | |
2007 | sequence = gen_sequence (); | |
2008 | end_sequence (); | |
2009 | i1 = emit_insn_before (sequence, loop_start); | |
2010 | } | |
2011 | else if (GET_CODE (p) == CALL_INSN) | |
f97d29ce JW |
2012 | { |
2013 | i1 = emit_call_insn_before (PATTERN (p), loop_start); | |
2014 | /* Because the USAGE information potentially | |
2015 | contains objects other than hard registers | |
2016 | we need to copy it. */ | |
8c4f5c09 | 2017 | if (CALL_INSN_FUNCTION_USAGE (p)) |
db3cf6fb MS |
2018 | CALL_INSN_FUNCTION_USAGE (i1) |
2019 | = copy_rtx (CALL_INSN_FUNCTION_USAGE (p)); | |
f97d29ce | 2020 | } |
1a61c29f JW |
2021 | else if (count == m->consec && m->move_insn_first) |
2022 | { | |
2023 | /* The SET_SRC might not be invariant, so we must | |
2024 | use the REG_EQUAL note. */ | |
2025 | start_sequence (); | |
2026 | emit_move_insn (m->set_dest, m->set_src); | |
2027 | temp = get_insns (); | |
2028 | end_sequence (); | |
2029 | ||
2030 | add_label_notes (m->set_src, temp); | |
2031 | ||
2032 | i1 = emit_insns_before (temp, loop_start); | |
2033 | if (! find_reg_note (i1, REG_EQUAL, NULL_RTX)) | |
2034 | REG_NOTES (i1) | |
2035 | = gen_rtx_EXPR_LIST ((m->is_equiv ? REG_EQUIV | |
2036 | : REG_EQUAL), | |
2037 | m->set_src, REG_NOTES (i1)); | |
2038 | } | |
b4ad7b23 RS |
2039 | else |
2040 | i1 = emit_insn_before (PATTERN (p), loop_start); | |
2041 | ||
1a61c29f JW |
2042 | if (REG_NOTES (i1) == 0) |
2043 | { | |
2044 | REG_NOTES (i1) = REG_NOTES (p); | |
b4ad7b23 | 2045 | |
1a61c29f JW |
2046 | /* If there is a REG_EQUAL note present whose value |
2047 | is not loop invariant, then delete it, since it | |
2048 | may cause problems with later optimization passes. | |
2049 | It is possible for cse to create such notes | |
2050 | like this as a result of record_jump_cond. */ | |
e6726b1f | 2051 | |
1a61c29f JW |
2052 | if ((temp = find_reg_note (i1, REG_EQUAL, NULL_RTX)) |
2053 | && ! invariant_p (XEXP (temp, 0))) | |
2054 | remove_note (i1, temp); | |
2055 | } | |
e6726b1f | 2056 | |
b4ad7b23 RS |
2057 | if (new_start == 0) |
2058 | new_start = i1; | |
2059 | ||
2060 | if (loop_dump_stream) | |
2061 | fprintf (loop_dump_stream, " moved to %d", | |
2062 | INSN_UID (i1)); | |
2063 | ||
b4ad7b23 RS |
2064 | /* If library call, now fix the REG_NOTES that contain |
2065 | insn pointers, namely REG_LIBCALL on FIRST | |
2066 | and REG_RETVAL on I1. */ | |
51723711 | 2067 | if ((temp = find_reg_note (i1, REG_RETVAL, NULL_RTX))) |
b4ad7b23 RS |
2068 | { |
2069 | XEXP (temp, 0) = first; | |
5fd8383e | 2070 | temp = find_reg_note (first, REG_LIBCALL, NULL_RTX); |
b4ad7b23 RS |
2071 | XEXP (temp, 0) = i1; |
2072 | } | |
2073 | ||
9655bf95 | 2074 | temp = p; |
b4ad7b23 | 2075 | delete_insn (p); |
9655bf95 DM |
2076 | p = NEXT_INSN (p); |
2077 | ||
2078 | /* simplify_giv_expr expects that it can walk the insns | |
2079 | at m->insn forwards and see this old sequence we are | |
2080 | tossing here. delete_insn does preserve the next | |
2081 | pointers, but when we skip over a NOTE we must fix | |
2082 | it up. Otherwise that code walks into the non-deleted | |
2083 | insn stream. */ | |
2084 | while (p && GET_CODE (p) == NOTE) | |
2085 | p = NEXT_INSN (temp) = NEXT_INSN (p); | |
b4ad7b23 RS |
2086 | } |
2087 | ||
2088 | /* The more regs we move, the less we like moving them. */ | |
2089 | threshold -= 3; | |
2090 | } | |
2091 | ||
2092 | /* Any other movable that loads the same register | |
2093 | MUST be moved. */ | |
2094 | already_moved[regno] = 1; | |
2095 | ||
2096 | /* This reg has been moved out of one loop. */ | |
2097 | moved_once[regno] = 1; | |
2098 | ||
2099 | /* The reg set here is now invariant. */ | |
2100 | if (! m->partial) | |
4b259e3f | 2101 | VARRAY_INT (set_in_loop, regno) = 0; |
b4ad7b23 RS |
2102 | |
2103 | m->done = 1; | |
2104 | ||
2105 | /* Change the length-of-life info for the register | |
2106 | to say it lives at least the full length of this loop. | |
2107 | This will help guide optimizations in outer loops. */ | |
2108 | ||
b1f21e0a | 2109 | if (uid_luid[REGNO_FIRST_UID (regno)] > INSN_LUID (loop_start)) |
b4ad7b23 RS |
2110 | /* This is the old insn before all the moved insns. |
2111 | We can't use the moved insn because it is out of range | |
2112 | in uid_luid. Only the old insns have luids. */ | |
b1f21e0a MM |
2113 | REGNO_FIRST_UID (regno) = INSN_UID (loop_start); |
2114 | if (uid_luid[REGNO_LAST_UID (regno)] < INSN_LUID (end)) | |
2115 | REGNO_LAST_UID (regno) = INSN_UID (end); | |
b4ad7b23 RS |
2116 | |
2117 | /* Combine with this moved insn any other matching movables. */ | |
2118 | ||
2119 | if (! m->partial) | |
2120 | for (m1 = movables; m1; m1 = m1->next) | |
2121 | if (m1->match == m) | |
2122 | { | |
2123 | rtx temp; | |
2124 | ||
2125 | /* Schedule the reg loaded by M1 | |
2126 | for replacement so that shares the reg of M. | |
2127 | If the modes differ (only possible in restricted | |
51f0646f JL |
2128 | circumstances, make a SUBREG. |
2129 | ||
2130 | Note this assumes that the target dependent files | |
2131 | treat REG and SUBREG equally, including within | |
2132 | GO_IF_LEGITIMATE_ADDRESS and in all the | |
2133 | predicates since we never verify that replacing the | |
2134 | original register with a SUBREG results in a | |
2135 | recognizable insn. */ | |
b4ad7b23 RS |
2136 | if (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest)) |
2137 | reg_map[m1->regno] = m->set_dest; | |
2138 | else | |
2139 | reg_map[m1->regno] | |
2140 | = gen_lowpart_common (GET_MODE (m1->set_dest), | |
2141 | m->set_dest); | |
2142 | ||
2143 | /* Get rid of the matching insn | |
2144 | and prevent further processing of it. */ | |
2145 | m1->done = 1; | |
2146 | ||
2147 | /* if library call, delete all insn except last, which | |
2148 | is deleted below */ | |
51723711 KG |
2149 | if ((temp = find_reg_note (m1->insn, REG_RETVAL, |
2150 | NULL_RTX))) | |
b4ad7b23 RS |
2151 | { |
2152 | for (temp = XEXP (temp, 0); temp != m1->insn; | |
2153 | temp = NEXT_INSN (temp)) | |
2154 | delete_insn (temp); | |
2155 | } | |
2156 | delete_insn (m1->insn); | |
2157 | ||
2158 | /* Any other movable that loads the same register | |
2159 | MUST be moved. */ | |
2160 | already_moved[m1->regno] = 1; | |
2161 | ||
2162 | /* The reg merged here is now invariant, | |
2163 | if the reg it matches is invariant. */ | |
2164 | if (! m->partial) | |
4b259e3f | 2165 | VARRAY_INT (set_in_loop, m1->regno) = 0; |
b4ad7b23 RS |
2166 | } |
2167 | } | |
2168 | else if (loop_dump_stream) | |
2169 | fprintf (loop_dump_stream, "not desirable"); | |
2170 | } | |
2171 | else if (loop_dump_stream && !m->match) | |
2172 | fprintf (loop_dump_stream, "not safe"); | |
2173 | ||
2174 | if (loop_dump_stream) | |
2175 | fprintf (loop_dump_stream, "\n"); | |
2176 | } | |
2177 | ||
2178 | if (new_start == 0) | |
2179 | new_start = loop_start; | |
2180 | ||
2181 | /* Go through all the instructions in the loop, making | |
2182 | all the register substitutions scheduled in REG_MAP. */ | |
2183 | for (p = new_start; p != end; p = NEXT_INSN (p)) | |
2184 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN | |
2185 | || GET_CODE (p) == CALL_INSN) | |
2186 | { | |
2187 | replace_regs (PATTERN (p), reg_map, nregs, 0); | |
2188 | replace_regs (REG_NOTES (p), reg_map, nregs, 0); | |
da0c128e | 2189 | INSN_CODE (p) = -1; |
b4ad7b23 | 2190 | } |
4da896b2 MM |
2191 | |
2192 | /* Clean up. */ | |
2193 | free (reg_map); | |
2194 | free (already_moved); | |
b4ad7b23 RS |
2195 | } |
2196 | \f | |
2197 | #if 0 | |
2198 | /* Scan X and replace the address of any MEM in it with ADDR. | |
2199 | REG is the address that MEM should have before the replacement. */ | |
2200 | ||
2201 | static void | |
2202 | replace_call_address (x, reg, addr) | |
2203 | rtx x, reg, addr; | |
2204 | { | |
2205 | register enum rtx_code code; | |
2206 | register int i; | |
6f7d635c | 2207 | register const char *fmt; |
b4ad7b23 RS |
2208 | |
2209 | if (x == 0) | |
2210 | return; | |
2211 | code = GET_CODE (x); | |
2212 | switch (code) | |
2213 | { | |
2214 | case PC: | |
2215 | case CC0: | |
2216 | case CONST_INT: | |
2217 | case CONST_DOUBLE: | |
2218 | case CONST: | |
2219 | case SYMBOL_REF: | |
2220 | case LABEL_REF: | |
2221 | case REG: | |
2222 | return; | |
2223 | ||
2224 | case SET: | |
2225 | /* Short cut for very common case. */ | |
2226 | replace_call_address (XEXP (x, 1), reg, addr); | |
2227 | return; | |
2228 | ||
2229 | case CALL: | |
2230 | /* Short cut for very common case. */ | |
2231 | replace_call_address (XEXP (x, 0), reg, addr); | |
2232 | return; | |
2233 | ||
2234 | case MEM: | |
2235 | /* If this MEM uses a reg other than the one we expected, | |
2236 | something is wrong. */ | |
2237 | if (XEXP (x, 0) != reg) | |
2238 | abort (); | |
2239 | XEXP (x, 0) = addr; | |
2240 | return; | |
e9a25f70 JL |
2241 | |
2242 | default: | |
2243 | break; | |
b4ad7b23 RS |
2244 | } |
2245 | ||
2246 | fmt = GET_RTX_FORMAT (code); | |
2247 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2248 | { | |
2249 | if (fmt[i] == 'e') | |
2250 | replace_call_address (XEXP (x, i), reg, addr); | |
d4757e6a | 2251 | else if (fmt[i] == 'E') |
b4ad7b23 RS |
2252 | { |
2253 | register int j; | |
2254 | for (j = 0; j < XVECLEN (x, i); j++) | |
2255 | replace_call_address (XVECEXP (x, i, j), reg, addr); | |
2256 | } | |
2257 | } | |
2258 | } | |
2259 | #endif | |
2260 | \f | |
2261 | /* Return the number of memory refs to addresses that vary | |
2262 | in the rtx X. */ | |
2263 | ||
2264 | static int | |
2265 | count_nonfixed_reads (x) | |
2266 | rtx x; | |
2267 | { | |
2268 | register enum rtx_code code; | |
2269 | register int i; | |
6f7d635c | 2270 | register const char *fmt; |
b4ad7b23 RS |
2271 | int value; |
2272 | ||
2273 | if (x == 0) | |
2274 | return 0; | |
2275 | ||
2276 | code = GET_CODE (x); | |
2277 | switch (code) | |
2278 | { | |
2279 | case PC: | |
2280 | case CC0: | |
2281 | case CONST_INT: | |
2282 | case CONST_DOUBLE: | |
2283 | case CONST: | |
2284 | case SYMBOL_REF: | |
2285 | case LABEL_REF: | |
2286 | case REG: | |
2287 | return 0; | |
2288 | ||
2289 | case MEM: | |
2290 | return ((invariant_p (XEXP (x, 0)) != 1) | |
2291 | + count_nonfixed_reads (XEXP (x, 0))); | |
e9a25f70 JL |
2292 | |
2293 | default: | |
2294 | break; | |
b4ad7b23 RS |
2295 | } |
2296 | ||
2297 | value = 0; | |
2298 | fmt = GET_RTX_FORMAT (code); | |
2299 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2300 | { | |
2301 | if (fmt[i] == 'e') | |
2302 | value += count_nonfixed_reads (XEXP (x, i)); | |
d4757e6a | 2303 | else if (fmt[i] == 'E') |
b4ad7b23 RS |
2304 | { |
2305 | register int j; | |
2306 | for (j = 0; j < XVECLEN (x, i); j++) | |
2307 | value += count_nonfixed_reads (XVECEXP (x, i, j)); | |
2308 | } | |
2309 | } | |
2310 | return value; | |
2311 | } | |
2312 | ||
2313 | \f | |
2314 | #if 0 | |
2315 | /* P is an instruction that sets a register to the result of a ZERO_EXTEND. | |
2316 | Replace it with an instruction to load just the low bytes | |
2317 | if the machine supports such an instruction, | |
2318 | and insert above LOOP_START an instruction to clear the register. */ | |
2319 | ||
2320 | static void | |
2321 | constant_high_bytes (p, loop_start) | |
2322 | rtx p, loop_start; | |
2323 | { | |
2324 | register rtx new; | |
2325 | register int insn_code_number; | |
2326 | ||
2327 | /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...))) | |
2328 | to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */ | |
2329 | ||
c5c76735 JL |
2330 | new |
2331 | = gen_rtx_SET | |
2332 | (VOIDmode, | |
2333 | gen_rtx_STRICT_LOW_PART | |
2334 | (VOIDmode, | |
2335 | gen_rtx_SUBREG (GET_MODE (XEXP (SET_SRC (PATTERN (p)), 0)), | |
2336 | SET_DEST (PATTERN (p)), 0)), | |
2337 | XEXP (SET_SRC (PATTERN (p)), 0)); | |
2338 | ||
b4ad7b23 RS |
2339 | insn_code_number = recog (new, p); |
2340 | ||
2341 | if (insn_code_number) | |
2342 | { | |
2343 | register int i; | |
2344 | ||
2345 | /* Clear destination register before the loop. */ | |
c5c76735 JL |
2346 | emit_insn_before (gen_rtx_SET (VOIDmode, |
2347 | SET_DEST (PATTERN (p)), const0_rtx), | |
b4ad7b23 RS |
2348 | loop_start); |
2349 | ||
2350 | /* Inside the loop, just load the low part. */ | |
2351 | PATTERN (p) = new; | |
2352 | } | |
2353 | } | |
2354 | #endif | |
2355 | \f | |
3c748bb6 MH |
2356 | /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed', |
2357 | `has_call', `has_volatile', and `has_tablejump' within LOOP_INFO. | |
14a774a9 RK |
2358 | Set the global variables `unknown_address_altered', |
2359 | `unknown_constant_address_altered', and `num_mem_sets'. Also, fill | |
2360 | in the array `loop_mems' and the list `loop_store_mems'. */ | |
b4ad7b23 RS |
2361 | |
2362 | static void | |
a2be868f MH |
2363 | prescan_loop (loop) |
2364 | struct loop *loop; | |
b4ad7b23 RS |
2365 | { |
2366 | register int level = 1; | |
41a972a9 | 2367 | rtx insn; |
a2be868f MH |
2368 | struct loop_info *loop_info = loop->info; |
2369 | rtx start = loop->start; | |
2370 | rtx end = loop->end; | |
41a972a9 MM |
2371 | /* The label after END. Jumping here is just like falling off the |
2372 | end of the loop. We use next_nonnote_insn instead of next_label | |
2373 | as a hedge against the (pathological) case where some actual insn | |
2374 | might end up between the two. */ | |
2375 | rtx exit_target = next_nonnote_insn (end); | |
3c748bb6 | 2376 | |
3c748bb6 MH |
2377 | loop_info->has_indirect_jump = indirect_jump_in_function; |
2378 | loop_info->has_call = 0; | |
2379 | loop_info->has_volatile = 0; | |
2380 | loop_info->has_tablejump = 0; | |
3c748bb6 | 2381 | loop_info->has_multiple_exit_targets = 0; |
a2be868f MH |
2382 | loop->cont = 0; |
2383 | loop->vtop = 0; | |
2384 | loop->level = 1; | |
b4ad7b23 RS |
2385 | |
2386 | unknown_address_altered = 0; | |
14a774a9 | 2387 | unknown_constant_address_altered = 0; |
5026a502 | 2388 | loop_store_mems = NULL_RTX; |
2d4fde68 | 2389 | first_loop_store_insn = NULL_RTX; |
41a972a9 | 2390 | loop_mems_idx = 0; |
b4ad7b23 | 2391 | num_mem_sets = 0; |
b4ad7b23 RS |
2392 | |
2393 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
2394 | insn = NEXT_INSN (insn)) | |
2395 | { | |
2396 | if (GET_CODE (insn) == NOTE) | |
2397 | { | |
2398 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
2399 | { | |
2400 | ++level; | |
2401 | /* Count number of loops contained in this one. */ | |
a2be868f | 2402 | loop->level++; |
b4ad7b23 RS |
2403 | } |
2404 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
2405 | { | |
2406 | --level; | |
2407 | if (level == 0) | |
2408 | { | |
2409 | end = insn; | |
2410 | break; | |
2411 | } | |
2412 | } | |
2413 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_CONT) | |
2414 | { | |
2415 | if (level == 1) | |
a2be868f | 2416 | loop->cont = insn; |
3c748bb6 MH |
2417 | } |
2418 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_VTOP) | |
2419 | { | |
2420 | /* If there is a NOTE_INSN_LOOP_VTOP, then this is a for | |
2421 | or while style loop, with a loop exit test at the | |
2422 | start. Thus, we can assume that the loop condition | |
2423 | was true when the loop was entered. */ | |
2424 | if (level == 1) | |
a2be868f | 2425 | loop->vtop = insn; |
b4ad7b23 RS |
2426 | } |
2427 | } | |
2428 | else if (GET_CODE (insn) == CALL_INSN) | |
2429 | { | |
9ae8ffe7 JL |
2430 | if (! CONST_CALL_P (insn)) |
2431 | unknown_address_altered = 1; | |
3c748bb6 | 2432 | loop_info->has_call = 1; |
b4ad7b23 | 2433 | } |
41a972a9 | 2434 | else if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) |
b4ad7b23 | 2435 | { |
41a972a9 MM |
2436 | rtx label1 = NULL_RTX; |
2437 | rtx label2 = NULL_RTX; | |
2438 | ||
2439 | if (volatile_refs_p (PATTERN (insn))) | |
3c748bb6 | 2440 | loop_info->has_volatile = 1; |
8c368ee2 DE |
2441 | |
2442 | if (GET_CODE (insn) == JUMP_INSN | |
2443 | && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2444 | || GET_CODE (PATTERN (insn)) == ADDR_VEC)) | |
3c748bb6 | 2445 | loop_info->has_tablejump = 1; |
41a972a9 | 2446 | |
84832317 | 2447 | note_stores (PATTERN (insn), note_addr_stored, NULL); |
2d4fde68 R |
2448 | if (! first_loop_store_insn && loop_store_mems) |
2449 | first_loop_store_insn = insn; | |
41a972a9 | 2450 | |
3c748bb6 | 2451 | if (! loop_info->has_multiple_exit_targets |
41a972a9 MM |
2452 | && GET_CODE (insn) == JUMP_INSN |
2453 | && GET_CODE (PATTERN (insn)) == SET | |
2454 | && SET_DEST (PATTERN (insn)) == pc_rtx) | |
552bc76f | 2455 | { |
41a972a9 MM |
2456 | if (GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE) |
2457 | { | |
2458 | label1 = XEXP (SET_SRC (PATTERN (insn)), 1); | |
2459 | label2 = XEXP (SET_SRC (PATTERN (insn)), 2); | |
2460 | } | |
2461 | else | |
2462 | { | |
2463 | label1 = SET_SRC (PATTERN (insn)); | |
2464 | } | |
2465 | ||
2466 | do { | |
2467 | if (label1 && label1 != pc_rtx) | |
2468 | { | |
2469 | if (GET_CODE (label1) != LABEL_REF) | |
2470 | { | |
2471 | /* Something tricky. */ | |
3c748bb6 | 2472 | loop_info->has_multiple_exit_targets = 1; |
41a972a9 MM |
2473 | break; |
2474 | } | |
2475 | else if (XEXP (label1, 0) != exit_target | |
2476 | && LABEL_OUTSIDE_LOOP_P (label1)) | |
2477 | { | |
2478 | /* A jump outside the current loop. */ | |
3c748bb6 | 2479 | loop_info->has_multiple_exit_targets = 1; |
41a972a9 MM |
2480 | break; |
2481 | } | |
2482 | } | |
552bc76f | 2483 | |
41a972a9 MM |
2484 | label1 = label2; |
2485 | label2 = NULL_RTX; | |
2486 | } while (label1); | |
552bc76f | 2487 | } |
b4ad7b23 | 2488 | } |
41a972a9 | 2489 | else if (GET_CODE (insn) == RETURN) |
3c748bb6 | 2490 | loop_info->has_multiple_exit_targets = 1; |
b4ad7b23 | 2491 | } |
41a972a9 MM |
2492 | |
2493 | /* Now, rescan the loop, setting up the LOOP_MEMS array. */ | |
2494 | if (/* We can't tell what MEMs are aliased by what. */ | |
a2be868f | 2495 | ! unknown_address_altered |
41a972a9 MM |
2496 | /* An exception thrown by a called function might land us |
2497 | anywhere. */ | |
a2be868f | 2498 | && ! loop_info->has_call |
41a972a9 MM |
2499 | /* We don't want loads for MEMs moved to a location before the |
2500 | one at which their stack memory becomes allocated. (Note | |
2501 | that this is not a problem for malloc, etc., since those | |
2502 | require actual function calls. */ | |
a2be868f | 2503 | && ! current_function_calls_alloca |
41a972a9 MM |
2504 | /* There are ways to leave the loop other than falling off the |
2505 | end. */ | |
a2be868f | 2506 | && ! loop_info->has_multiple_exit_targets) |
41a972a9 MM |
2507 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); |
2508 | insn = NEXT_INSN (insn)) | |
2509 | for_each_rtx (&insn, insert_loop_mem, 0); | |
b4ad7b23 RS |
2510 | } |
2511 | \f | |
a2be868f | 2512 | /* LOOP->CONT_DOMINATOR is now the last label between the loop start |
3ec2b590 R |
2513 | and the continue note that is a the destination of a (cond)jump after |
2514 | the continue note. If there is any (cond)jump between the loop start | |
a2be868f MH |
2515 | and what we have so far as LOOP->CONT_DOMINATOR that has a |
2516 | target between LOOP->DOMINATOR and the continue note, move | |
2517 | LOOP->CONT_DOMINATOR forward to that label; if a jump's | |
2518 | destination cannot be determined, clear LOOP->CONT_DOMINATOR. */ | |
3ec2b590 R |
2519 | |
2520 | static void | |
a2be868f MH |
2521 | verify_dominator (loop) |
2522 | struct loop *loop; | |
3ec2b590 R |
2523 | { |
2524 | rtx insn; | |
2525 | ||
a2be868f | 2526 | if (! loop->cont_dominator) |
3ec2b590 R |
2527 | /* This can happen for an empty loop, e.g. in |
2528 | gcc.c-torture/compile/920410-2.c */ | |
2529 | return; | |
a2be868f | 2530 | if (loop->cont_dominator == const0_rtx) |
3ec2b590 | 2531 | { |
a2be868f | 2532 | loop->cont_dominator = 0; |
3ec2b590 R |
2533 | return; |
2534 | } | |
a2be868f | 2535 | for (insn = loop->start; insn != loop->cont_dominator; |
3ec2b590 R |
2536 | insn = NEXT_INSN (insn)) |
2537 | { | |
2538 | if (GET_CODE (insn) == JUMP_INSN | |
2539 | && GET_CODE (PATTERN (insn)) != RETURN) | |
2540 | { | |
2541 | rtx label = JUMP_LABEL (insn); | |
8d22ad72 JL |
2542 | int label_luid; |
2543 | ||
2544 | /* If it is not a jump we can easily understand or for | |
2545 | which we do not have jump target information in the JUMP_LABEL | |
2546 | field (consider ADDR_VEC and ADDR_DIFF_VEC insns), then clear | |
a2be868f | 2547 | LOOP->CONT_DOMINATOR. */ |
8d22ad72 JL |
2548 | if ((! condjump_p (insn) |
2549 | && ! condjump_in_parallel_p (insn)) | |
2550 | || label == NULL_RTX) | |
3ec2b590 | 2551 | { |
a2be868f | 2552 | loop->cont_dominator = NULL_RTX; |
3ec2b590 R |
2553 | return; |
2554 | } | |
8d22ad72 JL |
2555 | |
2556 | label_luid = INSN_LUID (label); | |
a2be868f | 2557 | if (label_luid < INSN_LUID (loop->cont) |
3ec2b590 | 2558 | && (label_luid |
a2be868f MH |
2559 | > INSN_LUID (loop->cont))) |
2560 | loop->cont_dominator = label; | |
3ec2b590 R |
2561 | } |
2562 | } | |
2563 | } | |
2564 | ||
b4ad7b23 RS |
2565 | /* Scan the function looking for loops. Record the start and end of each loop. |
2566 | Also mark as invalid loops any loops that contain a setjmp or are branched | |
2567 | to from outside the loop. */ | |
2568 | ||
2569 | static void | |
a2be868f | 2570 | find_and_verify_loops (f, loops) |
b4ad7b23 | 2571 | rtx f; |
a2be868f | 2572 | struct loops *loops; |
b4ad7b23 | 2573 | { |
a2be868f MH |
2574 | rtx insn; |
2575 | rtx label; | |
2576 | int num_loops; | |
2577 | struct loop *current_loop; | |
2578 | struct loop *next_loop; | |
2579 | struct loop *loop; | |
2580 | ||
2581 | num_loops = loops->num; | |
b4ad7b23 | 2582 | |
3ec2b590 R |
2583 | compute_luids (f, NULL_RTX, 0); |
2584 | ||
b4ad7b23 RS |
2585 | /* If there are jumps to undefined labels, |
2586 | treat them as jumps out of any/all loops. | |
2587 | This also avoids writing past end of tables when there are no loops. */ | |
a2be868f | 2588 | uid_loop[0] = NULL; |
b4ad7b23 | 2589 | |
a2be868f MH |
2590 | loops->array = (struct loop *) |
2591 | xmalloc (num_loops * sizeof (struct loop)); | |
2592 | bzero ((char *)loops->array, num_loops * sizeof (struct loop)); | |
2593 | ||
b4ad7b23 RS |
2594 | /* Find boundaries of loops, mark which loops are contained within |
2595 | loops, and invalidate loops that have setjmp. */ | |
2596 | ||
a2be868f MH |
2597 | num_loops = 0; |
2598 | current_loop = NULL; | |
b4ad7b23 RS |
2599 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
2600 | { | |
2601 | if (GET_CODE (insn) == NOTE) | |
2602 | switch (NOTE_LINE_NUMBER (insn)) | |
2603 | { | |
2604 | case NOTE_INSN_LOOP_BEG: | |
a2be868f MH |
2605 | next_loop = loops->array + num_loops; |
2606 | next_loop->num = num_loops; | |
2607 | num_loops++; | |
2608 | next_loop->start = insn; | |
2609 | next_loop->outer = current_loop; | |
b4ad7b23 RS |
2610 | current_loop = next_loop; |
2611 | break; | |
2612 | ||
2613 | case NOTE_INSN_SETJMP: | |
2614 | /* In this case, we must invalidate our current loop and any | |
2615 | enclosing loop. */ | |
a2be868f | 2616 | for (loop = current_loop; loop; loop = loop->outer) |
b4ad7b23 | 2617 | { |
a2be868f | 2618 | loop->invalid = 1; |
b4ad7b23 RS |
2619 | if (loop_dump_stream) |
2620 | fprintf (loop_dump_stream, | |
2621 | "\nLoop at %d ignored due to setjmp.\n", | |
a2be868f | 2622 | INSN_UID (loop->start)); |
b4ad7b23 RS |
2623 | } |
2624 | break; | |
2625 | ||
3ec2b590 | 2626 | case NOTE_INSN_LOOP_CONT: |
a2be868f | 2627 | current_loop->cont = insn; |
3ec2b590 | 2628 | break; |
b4ad7b23 | 2629 | case NOTE_INSN_LOOP_END: |
a2be868f | 2630 | if (! current_loop) |
b4ad7b23 RS |
2631 | abort (); |
2632 | ||
a2be868f | 2633 | current_loop->end = insn; |
3ec2b590 | 2634 | verify_dominator (current_loop); |
a2be868f | 2635 | current_loop = current_loop->outer; |
b4ad7b23 RS |
2636 | break; |
2637 | ||
e9a25f70 JL |
2638 | default: |
2639 | break; | |
b4ad7b23 | 2640 | } |
3ec2b590 | 2641 | /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT |
a2be868f | 2642 | and NOTE_INSN_LOOP_END notes, update loop->dominator. */ |
3ec2b590 R |
2643 | else if (GET_CODE (insn) == JUMP_INSN |
2644 | && GET_CODE (PATTERN (insn)) != RETURN | |
a2be868f | 2645 | && current_loop) |
3ec2b590 | 2646 | { |
3ec2b590 R |
2647 | rtx label = JUMP_LABEL (insn); |
2648 | ||
2649 | if (! condjump_p (insn) && ! condjump_in_parallel_p (insn)) | |
2650 | label = NULL_RTX; | |
2651 | ||
a2be868f | 2652 | loop = current_loop; |
3ec2b590 R |
2653 | do |
2654 | { | |
2655 | /* First see if we care about this loop. */ | |
a2be868f | 2656 | if (loop->cont && loop->cont_dominator != const0_rtx) |
3ec2b590 R |
2657 | { |
2658 | /* If the jump destination is not known, invalidate | |
a2be868f | 2659 | loop->const_dominator. */ |
3ec2b590 | 2660 | if (! label) |
a2be868f | 2661 | loop->cont_dominator = const0_rtx; |
3ec2b590 R |
2662 | else |
2663 | /* Check if the destination is between loop start and | |
2664 | cont. */ | |
2665 | if ((INSN_LUID (label) | |
a2be868f | 2666 | < INSN_LUID (loop->cont)) |
3ec2b590 | 2667 | && (INSN_LUID (label) |
a2be868f | 2668 | > INSN_LUID (loop->start)) |
3ec2b590 R |
2669 | /* And if there is no later destination already |
2670 | recorded. */ | |
a2be868f | 2671 | && (! loop->cont_dominator |
3ec2b590 | 2672 | || (INSN_LUID (label) |
a2be868f MH |
2673 | > INSN_LUID (loop->cont_dominator)))) |
2674 | loop->cont_dominator = label; | |
3ec2b590 | 2675 | } |
a2be868f | 2676 | loop = loop->outer; |
3ec2b590 | 2677 | } |
a2be868f | 2678 | while (loop); |
3ec2b590 | 2679 | } |
b4ad7b23 RS |
2680 | |
2681 | /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the | |
2682 | enclosing loop, but this doesn't matter. */ | |
a2be868f | 2683 | uid_loop[INSN_UID (insn)] = current_loop; |
b4ad7b23 RS |
2684 | } |
2685 | ||
034dabc9 JW |
2686 | /* Any loop containing a label used in an initializer must be invalidated, |
2687 | because it can be jumped into from anywhere. */ | |
2688 | ||
2689 | for (label = forced_labels; label; label = XEXP (label, 1)) | |
2690 | { | |
a2be868f MH |
2691 | for (loop = uid_loop[INSN_UID (XEXP (label, 0))]; |
2692 | loop; loop = loop->outer) | |
2693 | loop->invalid = 1; | |
034dabc9 JW |
2694 | } |
2695 | ||
6adb4e3a MS |
2696 | /* Any loop containing a label used for an exception handler must be |
2697 | invalidated, because it can be jumped into from anywhere. */ | |
2698 | ||
2699 | for (label = exception_handler_labels; label; label = XEXP (label, 1)) | |
2700 | { | |
a2be868f MH |
2701 | for (loop = uid_loop[INSN_UID (XEXP (label, 0))]; |
2702 | loop; loop = loop->outer) | |
2703 | loop->invalid = 1; | |
6adb4e3a MS |
2704 | } |
2705 | ||
034dabc9 JW |
2706 | /* Now scan all insn's in the function. If any JUMP_INSN branches into a |
2707 | loop that it is not contained within, that loop is marked invalid. | |
2708 | If any INSN or CALL_INSN uses a label's address, then the loop containing | |
2709 | that label is marked invalid, because it could be jumped into from | |
2710 | anywhere. | |
b4ad7b23 RS |
2711 | |
2712 | Also look for blocks of code ending in an unconditional branch that | |
2713 | exits the loop. If such a block is surrounded by a conditional | |
2714 | branch around the block, move the block elsewhere (see below) and | |
2715 | invert the jump to point to the code block. This may eliminate a | |
2716 | label in our loop and will simplify processing by both us and a | |
2717 | possible second cse pass. */ | |
2718 | ||
2719 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
034dabc9 | 2720 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') |
b4ad7b23 | 2721 | { |
a2be868f | 2722 | struct loop *this_loop = uid_loop[INSN_UID (insn)]; |
b4ad7b23 | 2723 | |
034dabc9 JW |
2724 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) |
2725 | { | |
2726 | rtx note = find_reg_note (insn, REG_LABEL, NULL_RTX); | |
2727 | if (note) | |
2728 | { | |
a2be868f MH |
2729 | for (loop = uid_loop[INSN_UID (XEXP (note, 0))]; |
2730 | loop; loop = loop->outer) | |
2731 | loop->invalid = 1; | |
034dabc9 JW |
2732 | } |
2733 | } | |
2734 | ||
2735 | if (GET_CODE (insn) != JUMP_INSN) | |
2736 | continue; | |
2737 | ||
a2be868f | 2738 | mark_loop_jump (PATTERN (insn), this_loop); |
b4ad7b23 RS |
2739 | |
2740 | /* See if this is an unconditional branch outside the loop. */ | |
a2be868f | 2741 | if (this_loop |
b4ad7b23 RS |
2742 | && (GET_CODE (PATTERN (insn)) == RETURN |
2743 | || (simplejump_p (insn) | |
a2be868f MH |
2744 | && (uid_loop[INSN_UID (JUMP_LABEL (insn))] |
2745 | != this_loop))) | |
1c01e9df | 2746 | && get_max_uid () < max_uid_for_loop) |
b4ad7b23 RS |
2747 | { |
2748 | rtx p; | |
2749 | rtx our_next = next_real_insn (insn); | |
3b10cf4b | 2750 | rtx last_insn_to_move = NEXT_INSN (insn); |
a2be868f MH |
2751 | struct loop *dest_loop; |
2752 | struct loop *outer_loop = NULL; | |
b4ad7b23 RS |
2753 | |
2754 | /* Go backwards until we reach the start of the loop, a label, | |
2755 | or a JUMP_INSN. */ | |
2756 | for (p = PREV_INSN (insn); | |
2757 | GET_CODE (p) != CODE_LABEL | |
2758 | && ! (GET_CODE (p) == NOTE | |
2759 | && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) | |
2760 | && GET_CODE (p) != JUMP_INSN; | |
2761 | p = PREV_INSN (p)) | |
2762 | ; | |
2763 | ||
edf711a4 RK |
2764 | /* Check for the case where we have a jump to an inner nested |
2765 | loop, and do not perform the optimization in that case. */ | |
2766 | ||
fdccb6df | 2767 | if (JUMP_LABEL (insn)) |
edf711a4 | 2768 | { |
a2be868f MH |
2769 | dest_loop = uid_loop[INSN_UID (JUMP_LABEL (insn))]; |
2770 | if (dest_loop) | |
fdccb6df | 2771 | { |
a2be868f MH |
2772 | for (outer_loop = dest_loop; outer_loop; |
2773 | outer_loop = outer_loop->outer) | |
2774 | if (outer_loop == this_loop) | |
fdccb6df RK |
2775 | break; |
2776 | } | |
edf711a4 | 2777 | } |
edf711a4 | 2778 | |
89724a5a RK |
2779 | /* Make sure that the target of P is within the current loop. */ |
2780 | ||
9a8e74f0 | 2781 | if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) |
a2be868f MH |
2782 | && uid_loop[INSN_UID (JUMP_LABEL (p))] != this_loop) |
2783 | outer_loop = this_loop; | |
89724a5a | 2784 | |
b4ad7b23 RS |
2785 | /* If we stopped on a JUMP_INSN to the next insn after INSN, |
2786 | we have a block of code to try to move. | |
2787 | ||
2788 | We look backward and then forward from the target of INSN | |
2789 | to find a BARRIER at the same loop depth as the target. | |
2790 | If we find such a BARRIER, we make a new label for the start | |
2791 | of the block, invert the jump in P and point it to that label, | |
2792 | and move the block of code to the spot we found. */ | |
2793 | ||
a2be868f | 2794 | if (! outer_loop |
edf711a4 | 2795 | && GET_CODE (p) == JUMP_INSN |
c6096c5e RS |
2796 | && JUMP_LABEL (p) != 0 |
2797 | /* Just ignore jumps to labels that were never emitted. | |
2798 | These always indicate compilation errors. */ | |
2799 | && INSN_UID (JUMP_LABEL (p)) != 0 | |
2800 | && condjump_p (p) | |
2801 | && ! simplejump_p (p) | |
3b10cf4b MM |
2802 | && next_real_insn (JUMP_LABEL (p)) == our_next |
2803 | /* If it's not safe to move the sequence, then we | |
2804 | mustn't try. */ | |
2805 | && insns_safe_to_move_p (p, NEXT_INSN (insn), | |
2806 | &last_insn_to_move)) | |
b4ad7b23 RS |
2807 | { |
2808 | rtx target | |
2809 | = JUMP_LABEL (insn) ? JUMP_LABEL (insn) : get_last_insn (); | |
a2be868f | 2810 | struct loop *target_loop = uid_loop[INSN_UID (target)]; |
17bec8ee | 2811 | rtx loc, loc2; |
b4ad7b23 RS |
2812 | |
2813 | for (loc = target; loc; loc = PREV_INSN (loc)) | |
2814 | if (GET_CODE (loc) == BARRIER | |
17bec8ee BS |
2815 | /* Don't move things inside a tablejump. */ |
2816 | && ((loc2 = next_nonnote_insn (loc)) == 0 | |
2817 | || GET_CODE (loc2) != CODE_LABEL | |
2818 | || (loc2 = next_nonnote_insn (loc2)) == 0 | |
2819 | || GET_CODE (loc2) != JUMP_INSN | |
2820 | || (GET_CODE (PATTERN (loc2)) != ADDR_VEC | |
2821 | && GET_CODE (PATTERN (loc2)) != ADDR_DIFF_VEC)) | |
a2be868f | 2822 | && uid_loop[INSN_UID (loc)] == target_loop) |
b4ad7b23 RS |
2823 | break; |
2824 | ||
2825 | if (loc == 0) | |
2826 | for (loc = target; loc; loc = NEXT_INSN (loc)) | |
2827 | if (GET_CODE (loc) == BARRIER | |
17bec8ee BS |
2828 | /* Don't move things inside a tablejump. */ |
2829 | && ((loc2 = next_nonnote_insn (loc)) == 0 | |
2830 | || GET_CODE (loc2) != CODE_LABEL | |
2831 | || (loc2 = next_nonnote_insn (loc2)) == 0 | |
2832 | || GET_CODE (loc2) != JUMP_INSN | |
2833 | || (GET_CODE (PATTERN (loc2)) != ADDR_VEC | |
2834 | && GET_CODE (PATTERN (loc2)) != ADDR_DIFF_VEC)) | |
a2be868f | 2835 | && uid_loop[INSN_UID (loc)] == target_loop) |
b4ad7b23 RS |
2836 | break; |
2837 | ||
2838 | if (loc) | |
2839 | { | |
2840 | rtx cond_label = JUMP_LABEL (p); | |
2841 | rtx new_label = get_label_after (p); | |
2842 | ||
2843 | /* Ensure our label doesn't go away. */ | |
2844 | LABEL_NUSES (cond_label)++; | |
2845 | ||
a2be868f | 2846 | /* Verify that uid_loop is large enough and that |
0f41302f | 2847 | we can invert P. */ |
1c01e9df | 2848 | if (invert_jump (p, new_label)) |
b4ad7b23 RS |
2849 | { |
2850 | rtx q, r; | |
2851 | ||
72ec635f JL |
2852 | /* If no suitable BARRIER was found, create a suitable |
2853 | one before TARGET. Since TARGET is a fall through | |
2854 | path, we'll need to insert an jump around our block | |
2855 | and a add a BARRIER before TARGET. | |
2856 | ||
2857 | This creates an extra unconditional jump outside | |
2858 | the loop. However, the benefits of removing rarely | |
2859 | executed instructions from inside the loop usually | |
2860 | outweighs the cost of the extra unconditional jump | |
2861 | outside the loop. */ | |
2862 | if (loc == 0) | |
2863 | { | |
2864 | rtx temp; | |
2865 | ||
2866 | temp = gen_jump (JUMP_LABEL (insn)); | |
2867 | temp = emit_jump_insn_before (temp, target); | |
2868 | JUMP_LABEL (temp) = JUMP_LABEL (insn); | |
2869 | LABEL_NUSES (JUMP_LABEL (insn))++; | |
2870 | loc = emit_barrier_before (target); | |
2871 | } | |
2872 | ||
b4ad7b23 RS |
2873 | /* Include the BARRIER after INSN and copy the |
2874 | block after LOC. */ | |
3b10cf4b MM |
2875 | new_label = squeeze_notes (new_label, |
2876 | last_insn_to_move); | |
2877 | reorder_insns (new_label, last_insn_to_move, loc); | |
b4ad7b23 | 2878 | |
a2be868f | 2879 | /* All those insns are now in TARGET_LOOP. */ |
3b10cf4b MM |
2880 | for (q = new_label; |
2881 | q != NEXT_INSN (last_insn_to_move); | |
b4ad7b23 | 2882 | q = NEXT_INSN (q)) |
a2be868f | 2883 | uid_loop[INSN_UID (q)] = target_loop; |
b4ad7b23 RS |
2884 | |
2885 | /* The label jumped to by INSN is no longer a loop exit. | |
2886 | Unless INSN does not have a label (e.g., it is a | |
a2be868f | 2887 | RETURN insn), search loop->exit_labels to find |
b4ad7b23 RS |
2888 | its label_ref, and remove it. Also turn off |
2889 | LABEL_OUTSIDE_LOOP_P bit. */ | |
2890 | if (JUMP_LABEL (insn)) | |
2891 | { | |
2892 | for (q = 0, | |
a2be868f | 2893 | r = this_loop->exit_labels; |
b4ad7b23 RS |
2894 | r; q = r, r = LABEL_NEXTREF (r)) |
2895 | if (XEXP (r, 0) == JUMP_LABEL (insn)) | |
2896 | { | |
2897 | LABEL_OUTSIDE_LOOP_P (r) = 0; | |
2898 | if (q) | |
2899 | LABEL_NEXTREF (q) = LABEL_NEXTREF (r); | |
2900 | else | |
a2be868f | 2901 | this_loop->exit_labels = LABEL_NEXTREF (r); |
b4ad7b23 RS |
2902 | break; |
2903 | } | |
2904 | ||
a2be868f MH |
2905 | for (loop = this_loop; loop && loop != target_loop; |
2906 | loop = loop->outer) | |
2907 | loop->exit_count--; | |
353127c2 | 2908 | |
a2be868f MH |
2909 | /* If we didn't find it, then something is |
2910 | wrong. */ | |
b4ad7b23 RS |
2911 | if (! r) |
2912 | abort (); | |
2913 | } | |
2914 | ||
2915 | /* P is now a jump outside the loop, so it must be put | |
a2be868f | 2916 | in loop->exit_labels, and marked as such. |
b4ad7b23 RS |
2917 | The easiest way to do this is to just call |
2918 | mark_loop_jump again for P. */ | |
a2be868f | 2919 | mark_loop_jump (PATTERN (p), this_loop); |
b4ad7b23 RS |
2920 | |
2921 | /* If INSN now jumps to the insn after it, | |
2922 | delete INSN. */ | |
2923 | if (JUMP_LABEL (insn) != 0 | |
2924 | && (next_real_insn (JUMP_LABEL (insn)) | |
2925 | == next_real_insn (insn))) | |
2926 | delete_insn (insn); | |
2927 | } | |
2928 | ||
2929 | /* Continue the loop after where the conditional | |
2930 | branch used to jump, since the only branch insn | |
2931 | in the block (if it still remains) is an inter-loop | |
2932 | branch and hence needs no processing. */ | |
2933 | insn = NEXT_INSN (cond_label); | |
2934 | ||
2935 | if (--LABEL_NUSES (cond_label) == 0) | |
2936 | delete_insn (cond_label); | |
3ad0cfaf RK |
2937 | |
2938 | /* This loop will be continued with NEXT_INSN (insn). */ | |
2939 | insn = PREV_INSN (insn); | |
b4ad7b23 RS |
2940 | } |
2941 | } | |
2942 | } | |
2943 | } | |
2944 | } | |
2945 | ||
2946 | /* If any label in X jumps to a loop different from LOOP_NUM and any of the | |
2947 | loops it is contained in, mark the target loop invalid. | |
2948 | ||
2949 | For speed, we assume that X is part of a pattern of a JUMP_INSN. */ | |
2950 | ||
2951 | static void | |
a2be868f | 2952 | mark_loop_jump (x, loop) |
b4ad7b23 | 2953 | rtx x; |
a2be868f | 2954 | struct loop *loop; |
b4ad7b23 | 2955 | { |
a2be868f MH |
2956 | struct loop *dest_loop; |
2957 | struct loop *outer_loop; | |
b4ad7b23 RS |
2958 | int i; |
2959 | ||
2960 | switch (GET_CODE (x)) | |
2961 | { | |
2962 | case PC: | |
2963 | case USE: | |
2964 | case CLOBBER: | |
2965 | case REG: | |
2966 | case MEM: | |
2967 | case CONST_INT: | |
2968 | case CONST_DOUBLE: | |
2969 | case RETURN: | |
2970 | return; | |
2971 | ||
2972 | case CONST: | |
2973 | /* There could be a label reference in here. */ | |
a2be868f | 2974 | mark_loop_jump (XEXP (x, 0), loop); |
b4ad7b23 RS |
2975 | return; |
2976 | ||
2977 | case PLUS: | |
2978 | case MINUS: | |
2979 | case MULT: | |
a2be868f MH |
2980 | mark_loop_jump (XEXP (x, 0), loop); |
2981 | mark_loop_jump (XEXP (x, 1), loop); | |
b4ad7b23 RS |
2982 | return; |
2983 | ||
c4ae2725 JL |
2984 | case LO_SUM: |
2985 | /* This may refer to a LABEL_REF or SYMBOL_REF. */ | |
a2be868f | 2986 | mark_loop_jump (XEXP (x, 1), loop); |
c4ae2725 JL |
2987 | return; |
2988 | ||
b4ad7b23 RS |
2989 | case SIGN_EXTEND: |
2990 | case ZERO_EXTEND: | |
a2be868f | 2991 | mark_loop_jump (XEXP (x, 0), loop); |
b4ad7b23 RS |
2992 | return; |
2993 | ||
2994 | case LABEL_REF: | |
a2be868f | 2995 | dest_loop = uid_loop[INSN_UID (XEXP (x, 0))]; |
b4ad7b23 RS |
2996 | |
2997 | /* Link together all labels that branch outside the loop. This | |
2998 | is used by final_[bg]iv_value and the loop unrolling code. Also | |
2999 | mark this LABEL_REF so we know that this branch should predict | |
3000 | false. */ | |
3001 | ||
edf711a4 RK |
3002 | /* A check to make sure the label is not in an inner nested loop, |
3003 | since this does not count as a loop exit. */ | |
a2be868f | 3004 | if (dest_loop) |
edf711a4 | 3005 | { |
a2be868f MH |
3006 | for (outer_loop = dest_loop; outer_loop; |
3007 | outer_loop = outer_loop->outer) | |
3008 | if (outer_loop == loop) | |
edf711a4 RK |
3009 | break; |
3010 | } | |
3011 | else | |
a2be868f | 3012 | outer_loop = NULL; |
edf711a4 | 3013 | |
a2be868f | 3014 | if (loop && ! outer_loop) |
b4ad7b23 RS |
3015 | { |
3016 | LABEL_OUTSIDE_LOOP_P (x) = 1; | |
a2be868f MH |
3017 | LABEL_NEXTREF (x) = loop->exit_labels; |
3018 | loop->exit_labels = x; | |
353127c2 | 3019 | |
a2be868f MH |
3020 | for (outer_loop = loop; |
3021 | outer_loop && outer_loop != dest_loop; | |
3022 | outer_loop = outer_loop->outer) | |
3023 | outer_loop->exit_count++; | |
b4ad7b23 RS |
3024 | } |
3025 | ||
3026 | /* If this is inside a loop, but not in the current loop or one enclosed | |
3027 | by it, it invalidates at least one loop. */ | |
3028 | ||
a2be868f | 3029 | if (! dest_loop) |
b4ad7b23 RS |
3030 | return; |
3031 | ||
3032 | /* We must invalidate every nested loop containing the target of this | |
3033 | label, except those that also contain the jump insn. */ | |
3034 | ||
a2be868f | 3035 | for (; dest_loop; dest_loop = dest_loop->outer) |
b4ad7b23 RS |
3036 | { |
3037 | /* Stop when we reach a loop that also contains the jump insn. */ | |
a2be868f | 3038 | for (outer_loop = loop; outer_loop; outer_loop = outer_loop->outer) |
b4ad7b23 RS |
3039 | if (dest_loop == outer_loop) |
3040 | return; | |
3041 | ||
3042 | /* If we get here, we know we need to invalidate a loop. */ | |
a2be868f | 3043 | if (loop_dump_stream && ! dest_loop->invalid) |
b4ad7b23 RS |
3044 | fprintf (loop_dump_stream, |
3045 | "\nLoop at %d ignored due to multiple entry points.\n", | |
a2be868f | 3046 | INSN_UID (dest_loop->start)); |
b4ad7b23 | 3047 | |
a2be868f | 3048 | dest_loop->invalid = 1; |
b4ad7b23 RS |
3049 | } |
3050 | return; | |
3051 | ||
3052 | case SET: | |
3053 | /* If this is not setting pc, ignore. */ | |
3054 | if (SET_DEST (x) == pc_rtx) | |
a2be868f | 3055 | mark_loop_jump (SET_SRC (x), loop); |
b4ad7b23 RS |
3056 | return; |
3057 | ||
3058 | case IF_THEN_ELSE: | |
a2be868f MH |
3059 | mark_loop_jump (XEXP (x, 1), loop); |
3060 | mark_loop_jump (XEXP (x, 2), loop); | |
b4ad7b23 RS |
3061 | return; |
3062 | ||
3063 | case PARALLEL: | |
3064 | case ADDR_VEC: | |
3065 | for (i = 0; i < XVECLEN (x, 0); i++) | |
a2be868f | 3066 | mark_loop_jump (XVECEXP (x, 0, i), loop); |
b4ad7b23 RS |
3067 | return; |
3068 | ||
3069 | case ADDR_DIFF_VEC: | |
3070 | for (i = 0; i < XVECLEN (x, 1); i++) | |
a2be868f | 3071 | mark_loop_jump (XVECEXP (x, 1, i), loop); |
b4ad7b23 RS |
3072 | return; |
3073 | ||
3074 | default: | |
c4ae2725 JL |
3075 | /* Strictly speaking this is not a jump into the loop, only a possible |
3076 | jump out of the loop. However, we have no way to link the destination | |
3077 | of this jump onto the list of exit labels. To be safe we mark this | |
3078 | loop and any containing loops as invalid. */ | |
a2be868f | 3079 | if (loop) |
353127c2 | 3080 | { |
a2be868f | 3081 | for (outer_loop = loop; outer_loop; outer_loop = outer_loop->outer) |
c4ae2725 | 3082 | { |
a2be868f | 3083 | if (loop_dump_stream && ! outer_loop->invalid) |
c4ae2725 JL |
3084 | fprintf (loop_dump_stream, |
3085 | "\nLoop at %d ignored due to unknown exit jump.\n", | |
a2be868f MH |
3086 | INSN_UID (outer_loop->start)); |
3087 | outer_loop->invalid = 1; | |
c4ae2725 | 3088 | } |
353127c2 | 3089 | } |
b6ccc3fb | 3090 | return; |
b4ad7b23 RS |
3091 | } |
3092 | } | |
3093 | \f | |
3094 | /* Return nonzero if there is a label in the range from | |
3095 | insn INSN to and including the insn whose luid is END | |
3096 | INSN must have an assigned luid (i.e., it must not have | |
3097 | been previously created by loop.c). */ | |
3098 | ||
3099 | static int | |
3100 | labels_in_range_p (insn, end) | |
3101 | rtx insn; | |
3102 | int end; | |
3103 | { | |
3104 | while (insn && INSN_LUID (insn) <= end) | |
3105 | { | |
3106 | if (GET_CODE (insn) == CODE_LABEL) | |
3107 | return 1; | |
3108 | insn = NEXT_INSN (insn); | |
3109 | } | |
3110 | ||
3111 | return 0; | |
3112 | } | |
3113 | ||
3114 | /* Record that a memory reference X is being set. */ | |
3115 | ||
3116 | static void | |
84832317 | 3117 | note_addr_stored (x, y, data) |
b4ad7b23 | 3118 | rtx x; |
693e265f | 3119 | rtx y ATTRIBUTE_UNUSED; |
84832317 | 3120 | void *data ATTRIBUTE_UNUSED; |
b4ad7b23 | 3121 | { |
b4ad7b23 RS |
3122 | if (x == 0 || GET_CODE (x) != MEM) |
3123 | return; | |
3124 | ||
3125 | /* Count number of memory writes. | |
3126 | This affects heuristics in strength_reduce. */ | |
3127 | num_mem_sets++; | |
3128 | ||
ca800983 | 3129 | /* BLKmode MEM means all memory is clobbered. */ |
14a774a9 RK |
3130 | if (GET_MODE (x) == BLKmode) |
3131 | { | |
3132 | if (RTX_UNCHANGING_P (x)) | |
3133 | unknown_constant_address_altered = 1; | |
3134 | else | |
3135 | unknown_address_altered = 1; | |
ca800983 | 3136 | |
14a774a9 RK |
3137 | return; |
3138 | } | |
b4ad7b23 | 3139 | |
5026a502 | 3140 | loop_store_mems = gen_rtx_EXPR_LIST (VOIDmode, x, loop_store_mems); |
b4ad7b23 | 3141 | } |
59487769 JL |
3142 | |
3143 | /* X is a value modified by an INSN that references a biv inside a loop | |
3144 | exit test (ie, X is somehow related to the value of the biv). If X | |
3145 | is a pseudo that is used more than once, then the biv is (effectively) | |
84832317 MM |
3146 | used more than once. DATA is really an `int *', and is set if the |
3147 | biv is used more than once. */ | |
59487769 JL |
3148 | |
3149 | static void | |
84832317 | 3150 | note_set_pseudo_multiple_uses (x, y, data) |
59487769 JL |
3151 | rtx x; |
3152 | rtx y ATTRIBUTE_UNUSED; | |
84832317 | 3153 | void *data; |
59487769 JL |
3154 | { |
3155 | if (x == 0) | |
3156 | return; | |
3157 | ||
3158 | while (GET_CODE (x) == STRICT_LOW_PART | |
3159 | || GET_CODE (x) == SIGN_EXTRACT | |
3160 | || GET_CODE (x) == ZERO_EXTRACT | |
3161 | || GET_CODE (x) == SUBREG) | |
3162 | x = XEXP (x, 0); | |
3163 | ||
3164 | if (GET_CODE (x) != REG || REGNO (x) < FIRST_PSEUDO_REGISTER) | |
3165 | return; | |
3166 | ||
3167 | /* If we do not have usage information, or if we know the register | |
3168 | is used more than once, note that fact for check_dbra_loop. */ | |
3169 | if (REGNO (x) >= max_reg_before_loop | |
3170 | || ! VARRAY_RTX (reg_single_usage, REGNO (x)) | |
3171 | || VARRAY_RTX (reg_single_usage, REGNO (x)) == const0_rtx) | |
84832317 | 3172 | *((int *) data) = 1; |
59487769 | 3173 | } |
b4ad7b23 RS |
3174 | \f |
3175 | /* Return nonzero if the rtx X is invariant over the current loop. | |
3176 | ||
3177 | The value is 2 if we refer to something only conditionally invariant. | |
3178 | ||
3179 | If `unknown_address_altered' is nonzero, no memory ref is invariant. | |
3180 | Otherwise, a memory ref is invariant if it does not conflict with | |
3181 | anything stored in `loop_store_mems'. */ | |
3182 | ||
3183 | int | |
3184 | invariant_p (x) | |
3185 | register rtx x; | |
3186 | { | |
3187 | register int i; | |
3188 | register enum rtx_code code; | |
6f7d635c | 3189 | register const char *fmt; |
b4ad7b23 | 3190 | int conditional = 0; |
5026a502 | 3191 | rtx mem_list_entry; |
b4ad7b23 RS |
3192 | |
3193 | if (x == 0) | |
3194 | return 1; | |
3195 | code = GET_CODE (x); | |
3196 | switch (code) | |
3197 | { | |
3198 | case CONST_INT: | |
3199 | case CONST_DOUBLE: | |
3200 | case SYMBOL_REF: | |
3201 | case CONST: | |
3202 | return 1; | |
3203 | ||
3204 | case LABEL_REF: | |
3205 | /* A LABEL_REF is normally invariant, however, if we are unrolling | |
3206 | loops, and this label is inside the loop, then it isn't invariant. | |
3207 | This is because each unrolled copy of the loop body will have | |
3208 | a copy of this label. If this was invariant, then an insn loading | |
3209 | the address of this label into a register might get moved outside | |
3210 | the loop, and then each loop body would end up using the same label. | |
3211 | ||
3212 | We don't know the loop bounds here though, so just fail for all | |
3213 | labels. */ | |
81797aba | 3214 | if (flag_unroll_loops) |
b4ad7b23 RS |
3215 | return 0; |
3216 | else | |
3217 | return 1; | |
3218 | ||
3219 | case PC: | |
3220 | case CC0: | |
3221 | case UNSPEC_VOLATILE: | |
3222 | return 0; | |
3223 | ||
3224 | case REG: | |
3225 | /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid | |
3226 | since the reg might be set by initialization within the loop. */ | |
1f027d54 RK |
3227 | |
3228 | if ((x == frame_pointer_rtx || x == hard_frame_pointer_rtx | |
3229 | || x == arg_pointer_rtx) | |
3230 | && ! current_function_has_nonlocal_goto) | |
b4ad7b23 | 3231 | return 1; |
1f027d54 | 3232 | |
a2be868f | 3233 | if (loop_info_data.has_call |
b4ad7b23 RS |
3234 | && REGNO (x) < FIRST_PSEUDO_REGISTER && call_used_regs[REGNO (x)]) |
3235 | return 0; | |
1f027d54 | 3236 | |
4b259e3f | 3237 | if (VARRAY_INT (set_in_loop, REGNO (x)) < 0) |
b4ad7b23 | 3238 | return 2; |
1f027d54 | 3239 | |
4b259e3f | 3240 | return VARRAY_INT (set_in_loop, REGNO (x)) == 0; |
b4ad7b23 RS |
3241 | |
3242 | case MEM: | |
d5e3f151 JW |
3243 | /* Volatile memory references must be rejected. Do this before |
3244 | checking for read-only items, so that volatile read-only items | |
3245 | will be rejected also. */ | |
3246 | if (MEM_VOLATILE_P (x)) | |
3247 | return 0; | |
3248 | ||
14a774a9 RK |
3249 | /* If we had a subroutine call, any location in memory could |
3250 | have been clobbered. We used to test here for volatile and | |
3251 | readonly, but true_dependence knows how to do that better | |
3252 | than we do. */ | |
3253 | if (RTX_UNCHANGING_P (x) | |
3254 | ? unknown_constant_address_altered : unknown_address_altered) | |
b4ad7b23 RS |
3255 | return 0; |
3256 | ||
3257 | /* See if there is any dependence between a store and this load. */ | |
5026a502 JL |
3258 | mem_list_entry = loop_store_mems; |
3259 | while (mem_list_entry) | |
3260 | { | |
3261 | if (true_dependence (XEXP (mem_list_entry, 0), VOIDmode, | |
3262 | x, rtx_varies_p)) | |
3263 | return 0; | |
14a774a9 | 3264 | |
5026a502 JL |
3265 | mem_list_entry = XEXP (mem_list_entry, 1); |
3266 | } | |
b4ad7b23 RS |
3267 | |
3268 | /* It's not invalidated by a store in memory | |
3269 | but we must still verify the address is invariant. */ | |
3270 | break; | |
3271 | ||
3272 | case ASM_OPERANDS: | |
3273 | /* Don't mess with insns declared volatile. */ | |
3274 | if (MEM_VOLATILE_P (x)) | |
3275 | return 0; | |
e9a25f70 JL |
3276 | break; |
3277 | ||
3278 | default: | |
3279 | break; | |
b4ad7b23 RS |
3280 | } |
3281 | ||
3282 | fmt = GET_RTX_FORMAT (code); | |
3283 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3284 | { | |
3285 | if (fmt[i] == 'e') | |
3286 | { | |
3287 | int tem = invariant_p (XEXP (x, i)); | |
3288 | if (tem == 0) | |
3289 | return 0; | |
3290 | if (tem == 2) | |
3291 | conditional = 1; | |
3292 | } | |
3293 | else if (fmt[i] == 'E') | |
3294 | { | |
3295 | register int j; | |
3296 | for (j = 0; j < XVECLEN (x, i); j++) | |
3297 | { | |
3298 | int tem = invariant_p (XVECEXP (x, i, j)); | |
3299 | if (tem == 0) | |
3300 | return 0; | |
3301 | if (tem == 2) | |
3302 | conditional = 1; | |
3303 | } | |
3304 | ||
3305 | } | |
3306 | } | |
3307 | ||
3308 | return 1 + conditional; | |
3309 | } | |
3310 | ||
b4ad7b23 RS |
3311 | \f |
3312 | /* Return nonzero if all the insns in the loop that set REG | |
3313 | are INSN and the immediately following insns, | |
3314 | and if each of those insns sets REG in an invariant way | |
3315 | (not counting uses of REG in them). | |
3316 | ||
3317 | The value is 2 if some of these insns are only conditionally invariant. | |
3318 | ||
3319 | We assume that INSN itself is the first set of REG | |
3320 | and that its source is invariant. */ | |
3321 | ||
3322 | static int | |
3323 | consec_sets_invariant_p (reg, n_sets, insn) | |
3324 | int n_sets; | |
3325 | rtx reg, insn; | |
3326 | { | |
3327 | register rtx p = insn; | |
3328 | register int regno = REGNO (reg); | |
3329 | rtx temp; | |
3330 | /* Number of sets we have to insist on finding after INSN. */ | |
3331 | int count = n_sets - 1; | |
4b259e3f | 3332 | int old = VARRAY_INT (set_in_loop, regno); |
b4ad7b23 RS |
3333 | int value = 0; |
3334 | int this; | |
3335 | ||
3336 | /* If N_SETS hit the limit, we can't rely on its value. */ | |
3337 | if (n_sets == 127) | |
3338 | return 0; | |
3339 | ||
4b259e3f | 3340 | VARRAY_INT (set_in_loop, regno) = 0; |
b4ad7b23 RS |
3341 | |
3342 | while (count > 0) | |
3343 | { | |
3344 | register enum rtx_code code; | |
3345 | rtx set; | |
3346 | ||
3347 | p = NEXT_INSN (p); | |
3348 | code = GET_CODE (p); | |
3349 | ||
38e01259 | 3350 | /* If library call, skip to end of it. */ |
5fd8383e | 3351 | if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
3352 | p = XEXP (temp, 0); |
3353 | ||
3354 | this = 0; | |
3355 | if (code == INSN | |
3356 | && (set = single_set (p)) | |
3357 | && GET_CODE (SET_DEST (set)) == REG | |
3358 | && REGNO (SET_DEST (set)) == regno) | |
3359 | { | |
3360 | this = invariant_p (SET_SRC (set)); | |
3361 | if (this != 0) | |
3362 | value |= this; | |
51723711 | 3363 | else if ((temp = find_reg_note (p, REG_EQUAL, NULL_RTX))) |
b4ad7b23 | 3364 | { |
83d90aac JW |
3365 | /* If this is a libcall, then any invariant REG_EQUAL note is OK. |
3366 | If this is an ordinary insn, then only CONSTANT_P REG_EQUAL | |
3367 | notes are OK. */ | |
3368 | this = (CONSTANT_P (XEXP (temp, 0)) | |
3369 | || (find_reg_note (p, REG_RETVAL, NULL_RTX) | |
3370 | && invariant_p (XEXP (temp, 0)))); | |
b4ad7b23 RS |
3371 | if (this != 0) |
3372 | value |= this; | |
3373 | } | |
3374 | } | |
3375 | if (this != 0) | |
3376 | count--; | |
3377 | else if (code != NOTE) | |
3378 | { | |
4b259e3f | 3379 | VARRAY_INT (set_in_loop, regno) = old; |
b4ad7b23 RS |
3380 | return 0; |
3381 | } | |
3382 | } | |
3383 | ||
4b259e3f | 3384 | VARRAY_INT (set_in_loop, regno) = old; |
b4ad7b23 RS |
3385 | /* If invariant_p ever returned 2, we return 2. */ |
3386 | return 1 + (value & 2); | |
3387 | } | |
3388 | ||
3389 | #if 0 | |
3390 | /* I don't think this condition is sufficient to allow INSN | |
3391 | to be moved, so we no longer test it. */ | |
3392 | ||
3393 | /* Return 1 if all insns in the basic block of INSN and following INSN | |
3394 | that set REG are invariant according to TABLE. */ | |
3395 | ||
3396 | static int | |
3397 | all_sets_invariant_p (reg, insn, table) | |
3398 | rtx reg, insn; | |
3399 | short *table; | |
3400 | { | |
3401 | register rtx p = insn; | |
3402 | register int regno = REGNO (reg); | |
3403 | ||
3404 | while (1) | |
3405 | { | |
3406 | register enum rtx_code code; | |
3407 | p = NEXT_INSN (p); | |
3408 | code = GET_CODE (p); | |
3409 | if (code == CODE_LABEL || code == JUMP_INSN) | |
3410 | return 1; | |
3411 | if (code == INSN && GET_CODE (PATTERN (p)) == SET | |
3412 | && GET_CODE (SET_DEST (PATTERN (p))) == REG | |
3413 | && REGNO (SET_DEST (PATTERN (p))) == regno) | |
3414 | { | |
3415 | if (!invariant_p (SET_SRC (PATTERN (p)), table)) | |
3416 | return 0; | |
3417 | } | |
3418 | } | |
3419 | } | |
3420 | #endif /* 0 */ | |
3421 | \f | |
3422 | /* Look at all uses (not sets) of registers in X. For each, if it is | |
3423 | the single use, set USAGE[REGNO] to INSN; if there was a previous use in | |
3424 | a different insn, set USAGE[REGNO] to const0_rtx. */ | |
3425 | ||
3426 | static void | |
3427 | find_single_use_in_loop (insn, x, usage) | |
3428 | rtx insn; | |
3429 | rtx x; | |
8deb8e2c | 3430 | varray_type usage; |
b4ad7b23 RS |
3431 | { |
3432 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 3433 | const char *fmt = GET_RTX_FORMAT (code); |
b4ad7b23 RS |
3434 | int i, j; |
3435 | ||
3436 | if (code == REG) | |
8deb8e2c MM |
3437 | VARRAY_RTX (usage, REGNO (x)) |
3438 | = (VARRAY_RTX (usage, REGNO (x)) != 0 | |
3439 | && VARRAY_RTX (usage, REGNO (x)) != insn) | |
b4ad7b23 RS |
3440 | ? const0_rtx : insn; |
3441 | ||
3442 | else if (code == SET) | |
3443 | { | |
3444 | /* Don't count SET_DEST if it is a REG; otherwise count things | |
3445 | in SET_DEST because if a register is partially modified, it won't | |
3446 | show up as a potential movable so we don't care how USAGE is set | |
3447 | for it. */ | |
3448 | if (GET_CODE (SET_DEST (x)) != REG) | |
3449 | find_single_use_in_loop (insn, SET_DEST (x), usage); | |
3450 | find_single_use_in_loop (insn, SET_SRC (x), usage); | |
3451 | } | |
3452 | else | |
3453 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3454 | { | |
3455 | if (fmt[i] == 'e' && XEXP (x, i) != 0) | |
3456 | find_single_use_in_loop (insn, XEXP (x, i), usage); | |
3457 | else if (fmt[i] == 'E') | |
3458 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3459 | find_single_use_in_loop (insn, XVECEXP (x, i, j), usage); | |
3460 | } | |
3461 | } | |
3462 | \f | |
a4c3ddd8 BS |
3463 | /* Count and record any set in X which is contained in INSN. Update |
3464 | MAY_NOT_MOVE and LAST_SET for any register set in X. */ | |
3465 | ||
3466 | static void | |
3467 | count_one_set (insn, x, may_not_move, last_set) | |
3468 | rtx insn, x; | |
3469 | varray_type may_not_move; | |
3470 | rtx *last_set; | |
3471 | { | |
3472 | if (GET_CODE (x) == CLOBBER && GET_CODE (XEXP (x, 0)) == REG) | |
3473 | /* Don't move a reg that has an explicit clobber. | |
3474 | It's not worth the pain to try to do it correctly. */ | |
3475 | VARRAY_CHAR (may_not_move, REGNO (XEXP (x, 0))) = 1; | |
3476 | ||
3477 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
3478 | { | |
3479 | rtx dest = SET_DEST (x); | |
3480 | while (GET_CODE (dest) == SUBREG | |
3481 | || GET_CODE (dest) == ZERO_EXTRACT | |
3482 | || GET_CODE (dest) == SIGN_EXTRACT | |
3483 | || GET_CODE (dest) == STRICT_LOW_PART) | |
3484 | dest = XEXP (dest, 0); | |
3485 | if (GET_CODE (dest) == REG) | |
3486 | { | |
3487 | register int regno = REGNO (dest); | |
3488 | /* If this is the first setting of this reg | |
3489 | in current basic block, and it was set before, | |
3490 | it must be set in two basic blocks, so it cannot | |
3491 | be moved out of the loop. */ | |
4b259e3f | 3492 | if (VARRAY_INT (set_in_loop, regno) > 0 |
a4c3ddd8 BS |
3493 | && last_set[regno] == 0) |
3494 | VARRAY_CHAR (may_not_move, regno) = 1; | |
3495 | /* If this is not first setting in current basic block, | |
3496 | see if reg was used in between previous one and this. | |
3497 | If so, neither one can be moved. */ | |
3498 | if (last_set[regno] != 0 | |
3499 | && reg_used_between_p (dest, last_set[regno], insn)) | |
3500 | VARRAY_CHAR (may_not_move, regno) = 1; | |
4b259e3f R |
3501 | if (VARRAY_INT (set_in_loop, regno) < 127) |
3502 | ++VARRAY_INT (set_in_loop, regno); | |
a4c3ddd8 BS |
3503 | last_set[regno] = insn; |
3504 | } | |
3505 | } | |
3506 | } | |
3507 | ||
4b259e3f | 3508 | /* Increment SET_IN_LOOP at the index of each register |
b4ad7b23 | 3509 | that is modified by an insn between FROM and TO. |
4b259e3f | 3510 | If the value of an element of SET_IN_LOOP becomes 127 or more, |
b4ad7b23 RS |
3511 | stop incrementing it, to avoid overflow. |
3512 | ||
3513 | Store in SINGLE_USAGE[I] the single insn in which register I is | |
3514 | used, if it is only used once. Otherwise, it is set to 0 (for no | |
3515 | uses) or const0_rtx for more than one use. This parameter may be zero, | |
3516 | in which case this processing is not done. | |
3517 | ||
3518 | Store in *COUNT_PTR the number of actual instruction | |
3519 | in the loop. We use this to decide what is worth moving out. */ | |
3520 | ||
3521 | /* last_set[n] is nonzero iff reg n has been set in the current basic block. | |
3522 | In that case, it is the insn that last set reg n. */ | |
3523 | ||
3524 | static void | |
3525 | count_loop_regs_set (from, to, may_not_move, single_usage, count_ptr, nregs) | |
3526 | register rtx from, to; | |
8deb8e2c MM |
3527 | varray_type may_not_move; |
3528 | varray_type single_usage; | |
b4ad7b23 RS |
3529 | int *count_ptr; |
3530 | int nregs; | |
3531 | { | |
4da896b2 | 3532 | register rtx *last_set = (rtx *) xcalloc (nregs, sizeof (rtx)); |
b4ad7b23 RS |
3533 | register rtx insn; |
3534 | register int count = 0; | |
b4ad7b23 | 3535 | |
b4ad7b23 RS |
3536 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) |
3537 | { | |
3538 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
3539 | { | |
3540 | ++count; | |
3541 | ||
d6b44532 RH |
3542 | /* Record registers that have exactly one use. */ |
3543 | find_single_use_in_loop (insn, PATTERN (insn), single_usage); | |
b4ad7b23 | 3544 | |
d6b44532 RH |
3545 | /* Include uses in REG_EQUAL notes. */ |
3546 | if (REG_NOTES (insn)) | |
3547 | find_single_use_in_loop (insn, REG_NOTES (insn), single_usage); | |
b4ad7b23 | 3548 | |
b4ad7b23 RS |
3549 | if (GET_CODE (PATTERN (insn)) == SET |
3550 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
a4c3ddd8 | 3551 | count_one_set (insn, PATTERN (insn), may_not_move, last_set); |
b4ad7b23 RS |
3552 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
3553 | { | |
3554 | register int i; | |
3555 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
a4c3ddd8 BS |
3556 | count_one_set (insn, XVECEXP (PATTERN (insn), 0, i), |
3557 | may_not_move, last_set); | |
b4ad7b23 RS |
3558 | } |
3559 | } | |
4c9a05bc | 3560 | |
b4ad7b23 | 3561 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN) |
4c9a05bc | 3562 | bzero ((char *) last_set, nregs * sizeof (rtx)); |
b4ad7b23 RS |
3563 | } |
3564 | *count_ptr = count; | |
4da896b2 MM |
3565 | |
3566 | /* Clean up. */ | |
3567 | free (last_set); | |
b4ad7b23 RS |
3568 | } |
3569 | \f | |
3570 | /* Given a loop that is bounded by LOOP_START and LOOP_END | |
a2be868f | 3571 | and that is entered at LOOP_SCAN_START, |
b4ad7b23 RS |
3572 | return 1 if the register set in SET contained in insn INSN is used by |
3573 | any insn that precedes INSN in cyclic order starting | |
3574 | from the loop entry point. | |
3575 | ||
3576 | We don't want to use INSN_LUID here because if we restrict INSN to those | |
3577 | that have a valid INSN_LUID, it means we cannot move an invariant out | |
3578 | from an inner loop past two loops. */ | |
3579 | ||
3580 | static int | |
a2be868f MH |
3581 | loop_reg_used_before_p (loop, set, insn) |
3582 | const struct loop *loop; | |
3583 | rtx set, insn; | |
b4ad7b23 RS |
3584 | { |
3585 | rtx reg = SET_DEST (set); | |
3586 | rtx p; | |
3587 | ||
3588 | /* Scan forward checking for register usage. If we hit INSN, we | |
a2be868f MH |
3589 | are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */ |
3590 | for (p = loop->scan_start; p != insn; p = NEXT_INSN (p)) | |
b4ad7b23 RS |
3591 | { |
3592 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
3593 | && reg_overlap_mentioned_p (reg, PATTERN (p))) | |
3594 | return 1; | |
3595 | ||
a2be868f MH |
3596 | if (p == loop->end) |
3597 | p = loop->start; | |
b4ad7b23 RS |
3598 | } |
3599 | ||
3600 | return 0; | |
3601 | } | |
3602 | \f | |
3603 | /* A "basic induction variable" or biv is a pseudo reg that is set | |
3604 | (within this loop) only by incrementing or decrementing it. */ | |
3605 | /* A "general induction variable" or giv is a pseudo reg whose | |
3606 | value is a linear function of a biv. */ | |
3607 | ||
3608 | /* Bivs are recognized by `basic_induction_var'; | |
45f97e2e | 3609 | Givs by `general_induction_var'. */ |
b4ad7b23 RS |
3610 | |
3611 | /* Indexed by register number, indicates whether or not register is an | |
3612 | induction variable, and if so what type. */ | |
3613 | ||
3ec2b590 | 3614 | varray_type reg_iv_type; |
b4ad7b23 RS |
3615 | |
3616 | /* Indexed by register number, contains pointer to `struct induction' | |
3617 | if register is an induction variable. This holds general info for | |
3618 | all induction variables. */ | |
3619 | ||
3ec2b590 | 3620 | varray_type reg_iv_info; |
b4ad7b23 RS |
3621 | |
3622 | /* Indexed by register number, contains pointer to `struct iv_class' | |
3623 | if register is a basic induction variable. This holds info describing | |
3624 | the class (a related group) of induction variables that the biv belongs | |
3625 | to. */ | |
3626 | ||
3627 | struct iv_class **reg_biv_class; | |
3628 | ||
3629 | /* The head of a list which links together (via the next field) | |
3630 | every iv class for the current loop. */ | |
3631 | ||
3632 | struct iv_class *loop_iv_list; | |
3633 | ||
3ec2b590 R |
3634 | /* Givs made from biv increments are always splittable for loop unrolling. |
3635 | Since there is no regscan info for them, we have to keep track of them | |
3636 | separately. */ | |
3637 | int first_increment_giv, last_increment_giv; | |
3638 | ||
b4ad7b23 RS |
3639 | /* Communication with routines called via `note_stores'. */ |
3640 | ||
3641 | static rtx note_insn; | |
3642 | ||
3643 | /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */ | |
3644 | ||
3645 | static rtx addr_placeholder; | |
3646 | ||
3647 | /* ??? Unfinished optimizations, and possible future optimizations, | |
3648 | for the strength reduction code. */ | |
3649 | ||
b4ad7b23 | 3650 | /* ??? The interaction of biv elimination, and recognition of 'constant' |
0f41302f | 3651 | bivs, may cause problems. */ |
b4ad7b23 RS |
3652 | |
3653 | /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause | |
3654 | performance problems. | |
3655 | ||
3656 | Perhaps don't eliminate things that can be combined with an addressing | |
3657 | mode. Find all givs that have the same biv, mult_val, and add_val; | |
3658 | then for each giv, check to see if its only use dies in a following | |
3659 | memory address. If so, generate a new memory address and check to see | |
3660 | if it is valid. If it is valid, then store the modified memory address, | |
3661 | otherwise, mark the giv as not done so that it will get its own iv. */ | |
3662 | ||
3663 | /* ??? Could try to optimize branches when it is known that a biv is always | |
3664 | positive. */ | |
3665 | ||
3666 | /* ??? When replace a biv in a compare insn, we should replace with closest | |
3667 | giv so that an optimized branch can still be recognized by the combiner, | |
3668 | e.g. the VAX acb insn. */ | |
3669 | ||
3670 | /* ??? Many of the checks involving uid_luid could be simplified if regscan | |
3671 | was rerun in loop_optimize whenever a register was added or moved. | |
3672 | Also, some of the optimizations could be a little less conservative. */ | |
3673 | \f | |
41a972a9 | 3674 | /* Perform strength reduction and induction variable elimination. |
b4ad7b23 | 3675 | |
41a972a9 | 3676 | Pseudo registers created during this function will be beyond the last |
b4ad7b23 RS |
3677 | valid index in several tables including n_times_set and regno_last_uid. |
3678 | This does not cause a problem here, because the added registers cannot be | |
3679 | givs outside of their loop, and hence will never be reconsidered. | |
41a972a9 MM |
3680 | But scan_loop must check regnos to make sure they are in bounds. |
3681 | ||
a2be868f | 3682 | LOOP_SCAN_START is the first instruction in the loop, as the loop would |
41a972a9 MM |
3683 | actually be executed. END is the NOTE_INSN_LOOP_END. LOOP_TOP is |
3684 | the first instruction in the loop, as it is layed out in the | |
6dd49eb4 R |
3685 | instruction stream. LOOP_START is the NOTE_INSN_LOOP_BEG. |
3686 | LOOP_CONT is the NOTE_INSN_LOOP_CONT. */ | |
b4ad7b23 RS |
3687 | |
3688 | static void | |
a2be868f MH |
3689 | strength_reduce (loop, insn_count, unroll_p, bct_p) |
3690 | struct loop *loop; | |
b4ad7b23 | 3691 | int insn_count; |
d46965b9 | 3692 | int unroll_p, bct_p ATTRIBUTE_UNUSED; |
b4ad7b23 RS |
3693 | { |
3694 | rtx p; | |
3695 | rtx set; | |
3696 | rtx inc_val; | |
3697 | rtx mult_val; | |
3698 | rtx dest_reg; | |
3ec2b590 | 3699 | rtx *location; |
b4ad7b23 RS |
3700 | /* This is 1 if current insn is not executed at least once for every loop |
3701 | iteration. */ | |
3702 | int not_every_iteration = 0; | |
7dcd3836 RK |
3703 | /* This is 1 if current insn may be executed more than once for every |
3704 | loop iteration. */ | |
3705 | int maybe_multiple = 0; | |
ae188a87 JL |
3706 | /* This is 1 if we have past a branch back to the top of the loop |
3707 | (aka a loop latch). */ | |
3708 | int past_loop_latch = 0; | |
b4ad7b23 RS |
3709 | /* Temporary list pointers for traversing loop_iv_list. */ |
3710 | struct iv_class *bl, **backbl; | |
a2be868f | 3711 | struct loop_info *loop_info = loop->info; |
b4ad7b23 RS |
3712 | /* Ratio of extra register life span we can justify |
3713 | for saving an instruction. More if loop doesn't call subroutines | |
3714 | since in that case saving an insn makes more difference | |
3715 | and more registers are available. */ | |
3716 | /* ??? could set this to last value of threshold in move_movables */ | |
3c748bb6 | 3717 | int threshold = (loop_info->has_call ? 1 : 2) * (3 + n_non_fixed_regs); |
b4ad7b23 | 3718 | /* Map of pseudo-register replacements. */ |
4da896b2 | 3719 | rtx *reg_map = NULL; |
97ec0ad8 | 3720 | int reg_map_size; |
b4ad7b23 RS |
3721 | int call_seen; |
3722 | rtx test; | |
3723 | rtx end_insert_before; | |
5ea7a4ae | 3724 | int loop_depth = 0; |
3ec2b590 | 3725 | int n_extra_increment; |
f428f252 | 3726 | int unrolled_insn_copies = 0; |
a2be868f MH |
3727 | rtx loop_start = loop->start; |
3728 | rtx loop_end = loop->end; | |
3729 | rtx loop_scan_start = loop->scan_start; | |
3730 | rtx loop_top = loop->top; | |
3731 | rtx loop_cont = loop->cont; | |
b4ad7b23 | 3732 | |
a2be868f | 3733 | /* If loop_scan_start points to the loop exit test, we have to be wary of |
5353610b | 3734 | subversive use of gotos inside expression statements. */ |
a2be868f MH |
3735 | if (prev_nonnote_insn (loop_scan_start) != prev_nonnote_insn (loop_start)) |
3736 | maybe_multiple = back_branch_in_range_p (loop_scan_start, loop_start, loop_end); | |
5353610b | 3737 | |
3ec2b590 R |
3738 | VARRAY_INT_INIT (reg_iv_type, max_reg_before_loop, "reg_iv_type"); |
3739 | VARRAY_GENERIC_PTR_INIT (reg_iv_info, max_reg_before_loop, "reg_iv_info"); | |
b4ad7b23 | 3740 | reg_biv_class = (struct iv_class **) |
4da896b2 | 3741 | xcalloc (max_reg_before_loop, sizeof (struct iv_class *)); |
b4ad7b23 RS |
3742 | |
3743 | loop_iv_list = 0; | |
3744 | addr_placeholder = gen_reg_rtx (Pmode); | |
3745 | ||
3746 | /* Save insn immediately after the loop_end. Insns inserted after loop_end | |
3747 | must be put before this insn, so that they will appear in the right | |
b2586fe0 | 3748 | order (i.e. loop order). |
b4ad7b23 | 3749 | |
b2586fe0 JL |
3750 | If loop_end is the end of the current function, then emit a |
3751 | NOTE_INSN_DELETED after loop_end and set end_insert_before to the | |
3752 | dummy note insn. */ | |
3753 | if (NEXT_INSN (loop_end) != 0) | |
3754 | end_insert_before = NEXT_INSN (loop_end); | |
3755 | else | |
3756 | end_insert_before = emit_note_after (NOTE_INSN_DELETED, loop_end); | |
b4ad7b23 RS |
3757 | |
3758 | /* Scan through loop to find all possible bivs. */ | |
3759 | ||
a2be868f | 3760 | for (p = next_insn_in_loop (loop, loop_scan_start); |
41a972a9 | 3761 | p != NULL_RTX; |
a2be868f | 3762 | p = next_insn_in_loop (loop, p)) |
b4ad7b23 | 3763 | { |
b4ad7b23 RS |
3764 | if (GET_CODE (p) == INSN |
3765 | && (set = single_set (p)) | |
3766 | && GET_CODE (SET_DEST (set)) == REG) | |
3767 | { | |
3768 | dest_reg = SET_DEST (set); | |
3769 | if (REGNO (dest_reg) < max_reg_before_loop | |
3770 | && REGNO (dest_reg) >= FIRST_PSEUDO_REGISTER | |
3ec2b590 | 3771 | && REG_IV_TYPE (REGNO (dest_reg)) != NOT_BASIC_INDUCT) |
b4ad7b23 | 3772 | { |
60fb6df9 RH |
3773 | int multi_insn_incr = 0; |
3774 | ||
7056f7e8 | 3775 | if (basic_induction_var (SET_SRC (set), GET_MODE (SET_SRC (set)), |
a2be868f MH |
3776 | dest_reg, p, loop->level, |
3777 | &inc_val, &mult_val, | |
60fb6df9 | 3778 | &location, &multi_insn_incr)) |
b4ad7b23 RS |
3779 | { |
3780 | /* It is a possible basic induction variable. | |
3781 | Create and initialize an induction structure for it. */ | |
3782 | ||
3783 | struct induction *v | |
3784 | = (struct induction *) alloca (sizeof (struct induction)); | |
3785 | ||
3ec2b590 | 3786 | record_biv (v, p, dest_reg, inc_val, mult_val, location, |
60fb6df9 RH |
3787 | not_every_iteration, maybe_multiple, |
3788 | multi_insn_incr); | |
3ec2b590 | 3789 | REG_IV_TYPE (REGNO (dest_reg)) = BASIC_INDUCT; |
b4ad7b23 RS |
3790 | } |
3791 | else if (REGNO (dest_reg) < max_reg_before_loop) | |
3ec2b590 | 3792 | REG_IV_TYPE (REGNO (dest_reg)) = NOT_BASIC_INDUCT; |
b4ad7b23 RS |
3793 | } |
3794 | } | |
3795 | ||
7dcd3836 RK |
3796 | /* Past CODE_LABEL, we get to insns that may be executed multiple |
3797 | times. The only way we can be sure that they can't is if every | |
38e01259 | 3798 | jump insn between here and the end of the loop either |
5353610b R |
3799 | returns, exits the loop, is a jump to a location that is still |
3800 | behind the label, or is a jump to the loop start. */ | |
7dcd3836 RK |
3801 | |
3802 | if (GET_CODE (p) == CODE_LABEL) | |
3803 | { | |
3804 | rtx insn = p; | |
3805 | ||
3806 | maybe_multiple = 0; | |
3807 | ||
3808 | while (1) | |
3809 | { | |
3810 | insn = NEXT_INSN (insn); | |
a2be868f | 3811 | if (insn == loop_scan_start) |
7dcd3836 | 3812 | break; |
a2be868f | 3813 | if (insn == loop_end) |
7dcd3836 RK |
3814 | { |
3815 | if (loop_top != 0) | |
f67ff5de | 3816 | insn = loop_top; |
7dcd3836 RK |
3817 | else |
3818 | break; | |
a2be868f | 3819 | if (insn == loop_scan_start) |
7dcd3836 RK |
3820 | break; |
3821 | } | |
3822 | ||
3823 | if (GET_CODE (insn) == JUMP_INSN | |
3824 | && GET_CODE (PATTERN (insn)) != RETURN | |
3825 | && (! condjump_p (insn) | |
3826 | || (JUMP_LABEL (insn) != 0 | |
a2be868f | 3827 | && JUMP_LABEL (insn) != loop_scan_start |
1cb1fe66 | 3828 | && ! loop_insn_first_p (p, JUMP_LABEL (insn))))) |
8516af93 JW |
3829 | { |
3830 | maybe_multiple = 1; | |
3831 | break; | |
3832 | } | |
7dcd3836 RK |
3833 | } |
3834 | } | |
3835 | ||
8516af93 JW |
3836 | /* Past a jump, we get to insns for which we can't count |
3837 | on whether they will be executed during each iteration. */ | |
3838 | /* This code appears twice in strength_reduce. There is also similar | |
3839 | code in scan_loop. */ | |
3840 | if (GET_CODE (p) == JUMP_INSN | |
b4ad7b23 RS |
3841 | /* If we enter the loop in the middle, and scan around to the |
3842 | beginning, don't set not_every_iteration for that. | |
3843 | This can be any kind of jump, since we want to know if insns | |
3844 | will be executed if the loop is executed. */ | |
8516af93 | 3845 | && ! (JUMP_LABEL (p) == loop_top |
b4ad7b23 RS |
3846 | && ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p)) |
3847 | || (NEXT_INSN (p) == loop_end && condjump_p (p))))) | |
8516af93 JW |
3848 | { |
3849 | rtx label = 0; | |
3850 | ||
3851 | /* If this is a jump outside the loop, then it also doesn't | |
3852 | matter. Check to see if the target of this branch is on the | |
a2be868f | 3853 | loop->exits_labels list. */ |
8516af93 | 3854 | |
a2be868f | 3855 | for (label = uid_loop[INSN_UID (loop_start)]->exit_labels; |
8516af93 JW |
3856 | label; |
3857 | label = LABEL_NEXTREF (label)) | |
3858 | if (XEXP (label, 0) == JUMP_LABEL (p)) | |
3859 | break; | |
3860 | ||
3861 | if (! label) | |
3862 | not_every_iteration = 1; | |
3863 | } | |
b4ad7b23 | 3864 | |
5ea7a4ae JW |
3865 | else if (GET_CODE (p) == NOTE) |
3866 | { | |
3867 | /* At the virtual top of a converted loop, insns are again known to | |
3868 | be executed each iteration: logically, the loop begins here | |
5f3db57e JL |
3869 | even though the exit code has been duplicated. |
3870 | ||
3871 | Insns are also again known to be executed each iteration at | |
3872 | the LOOP_CONT note. */ | |
3873 | if ((NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP | |
3874 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_CONT) | |
3875 | && loop_depth == 0) | |
5ea7a4ae JW |
3876 | not_every_iteration = 0; |
3877 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) | |
3878 | loop_depth++; | |
3879 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END) | |
3880 | loop_depth--; | |
3881 | } | |
b4ad7b23 | 3882 | |
ae188a87 JL |
3883 | /* Note if we pass a loop latch. If we do, then we can not clear |
3884 | NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in | |
3885 | a loop since a jump before the last CODE_LABEL may have started | |
3886 | a new loop iteration. | |
3887 | ||
3888 | Note that LOOP_TOP is only set for rotated loops and we need | |
3889 | this check for all loops, so compare against the CODE_LABEL | |
3890 | which immediately follows LOOP_START. */ | |
a2be868f MH |
3891 | if (GET_CODE (p) == JUMP_INSN |
3892 | && JUMP_LABEL (p) == NEXT_INSN (loop_start)) | |
ae188a87 JL |
3893 | past_loop_latch = 1; |
3894 | ||
b4ad7b23 RS |
3895 | /* Unlike in the code motion pass where MAYBE_NEVER indicates that |
3896 | an insn may never be executed, NOT_EVERY_ITERATION indicates whether | |
3897 | or not an insn is known to be executed each iteration of the | |
3898 | loop, whether or not any iterations are known to occur. | |
3899 | ||
3900 | Therefore, if we have just passed a label and have no more labels | |
ae188a87 JL |
3901 | between here and the test insn of the loop, and we have not passed |
3902 | a jump to the top of the loop, then we know these insns will be | |
3903 | executed each iteration. */ | |
b4ad7b23 | 3904 | |
ae188a87 JL |
3905 | if (not_every_iteration |
3906 | && ! past_loop_latch | |
3907 | && GET_CODE (p) == CODE_LABEL | |
6dd49eb4 | 3908 | && no_labels_between_p (p, loop_end) |
1cb1fe66 | 3909 | && loop_insn_first_p (p, loop_cont)) |
b4ad7b23 RS |
3910 | not_every_iteration = 0; |
3911 | } | |
3912 | ||
3913 | /* Scan loop_iv_list to remove all regs that proved not to be bivs. | |
3914 | Make a sanity check against n_times_set. */ | |
3915 | for (backbl = &loop_iv_list, bl = *backbl; bl; bl = bl->next) | |
3916 | { | |
60fb6df9 RH |
3917 | int fail = 0; |
3918 | ||
3ec2b590 | 3919 | if (REG_IV_TYPE (bl->regno) != BASIC_INDUCT |
b4ad7b23 RS |
3920 | /* Above happens if register modified by subreg, etc. */ |
3921 | /* Make sure it is not recognized as a basic induction var: */ | |
8deb8e2c | 3922 | || VARRAY_INT (n_times_set, bl->regno) != bl->biv_count |
b4ad7b23 RS |
3923 | /* If never incremented, it is invariant that we decided not to |
3924 | move. So leave it alone. */ | |
3925 | || ! bl->incremented) | |
60fb6df9 RH |
3926 | fail = 1; |
3927 | else if (bl->biv_count > 1) | |
3928 | { | |
3929 | /* ??? If we have multiple increments for this BIV, and any of | |
3930 | them take multiple insns to perform the increment, drop the | |
3931 | BIV, since the bit below that converts the extra increments | |
3932 | into GIVs can't handle the multiple insn increment. */ | |
3933 | ||
3934 | struct induction *v; | |
3935 | for (v = bl->biv; v ; v = v->next_iv) | |
3936 | if (v->multi_insn_incr) | |
3937 | fail = 1; | |
3938 | } | |
3939 | ||
3940 | if (fail) | |
b4ad7b23 RS |
3941 | { |
3942 | if (loop_dump_stream) | |
3943 | fprintf (loop_dump_stream, "Reg %d: biv discarded, %s\n", | |
3944 | bl->regno, | |
3ec2b590 | 3945 | (REG_IV_TYPE (bl->regno) != BASIC_INDUCT |
b4ad7b23 RS |
3946 | ? "not induction variable" |
3947 | : (! bl->incremented ? "never incremented" | |
3948 | : "count error"))); | |
3949 | ||
3ec2b590 | 3950 | REG_IV_TYPE (bl->regno) = NOT_BASIC_INDUCT; |
b4ad7b23 RS |
3951 | *backbl = bl->next; |
3952 | } | |
3953 | else | |
3954 | { | |
3955 | backbl = &bl->next; | |
3956 | ||
3957 | if (loop_dump_stream) | |
3958 | fprintf (loop_dump_stream, "Reg %d: biv verified\n", bl->regno); | |
3959 | } | |
3960 | } | |
3961 | ||
3962 | /* Exit if there are no bivs. */ | |
3963 | if (! loop_iv_list) | |
3964 | { | |
3965 | /* Can still unroll the loop anyways, but indicate that there is no | |
3966 | strength reduction info available. */ | |
81797aba | 3967 | if (unroll_p) |
a2be868f | 3968 | unroll_loop (loop, insn_count, end_insert_before, 0); |
b4ad7b23 | 3969 | |
69ba6af3 | 3970 | goto egress; |
b4ad7b23 RS |
3971 | } |
3972 | ||
3973 | /* Find initial value for each biv by searching backwards from loop_start, | |
3974 | halting at first label. Also record any test condition. */ | |
3975 | ||
3976 | call_seen = 0; | |
3977 | for (p = loop_start; p && GET_CODE (p) != CODE_LABEL; p = PREV_INSN (p)) | |
3978 | { | |
3979 | note_insn = p; | |
3980 | ||
3981 | if (GET_CODE (p) == CALL_INSN) | |
3982 | call_seen = 1; | |
3983 | ||
3984 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN | |
3985 | || GET_CODE (p) == CALL_INSN) | |
84832317 | 3986 | note_stores (PATTERN (p), record_initial, NULL); |
b4ad7b23 RS |
3987 | |
3988 | /* Record any test of a biv that branches around the loop if no store | |
3989 | between it and the start of loop. We only care about tests with | |
3990 | constants and registers and only certain of those. */ | |
3991 | if (GET_CODE (p) == JUMP_INSN | |
3992 | && JUMP_LABEL (p) != 0 | |
3993 | && next_real_insn (JUMP_LABEL (p)) == next_real_insn (loop_end) | |
3994 | && (test = get_condition_for_loop (p)) != 0 | |
3995 | && GET_CODE (XEXP (test, 0)) == REG | |
3996 | && REGNO (XEXP (test, 0)) < max_reg_before_loop | |
3997 | && (bl = reg_biv_class[REGNO (XEXP (test, 0))]) != 0 | |
3998 | && valid_initial_value_p (XEXP (test, 1), p, call_seen, loop_start) | |
3999 | && bl->init_insn == 0) | |
4000 | { | |
4001 | /* If an NE test, we have an initial value! */ | |
4002 | if (GET_CODE (test) == NE) | |
4003 | { | |
4004 | bl->init_insn = p; | |
38a448ca RH |
4005 | bl->init_set = gen_rtx_SET (VOIDmode, |
4006 | XEXP (test, 0), XEXP (test, 1)); | |
b4ad7b23 RS |
4007 | } |
4008 | else | |
4009 | bl->initial_test = test; | |
4010 | } | |
4011 | } | |
4012 | ||
4013 | /* Look at the each biv and see if we can say anything better about its | |
4014 | initial value from any initializing insns set up above. (This is done | |
4015 | in two passes to avoid missing SETs in a PARALLEL.) */ | |
53dc05e4 | 4016 | for (backbl = &loop_iv_list; (bl = *backbl); backbl = &bl->next) |
b4ad7b23 RS |
4017 | { |
4018 | rtx src; | |
956d6950 | 4019 | rtx note; |
b4ad7b23 RS |
4020 | |
4021 | if (! bl->init_insn) | |
4022 | continue; | |
4023 | ||
956d6950 JL |
4024 | /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value |
4025 | is a constant, use the value of that. */ | |
4026 | if (((note = find_reg_note (bl->init_insn, REG_EQUAL, 0)) != NULL | |
4027 | && CONSTANT_P (XEXP (note, 0))) | |
4028 | || ((note = find_reg_note (bl->init_insn, REG_EQUIV, 0)) != NULL | |
4029 | && CONSTANT_P (XEXP (note, 0)))) | |
4030 | src = XEXP (note, 0); | |
4031 | else | |
4032 | src = SET_SRC (bl->init_set); | |
b4ad7b23 RS |
4033 | |
4034 | if (loop_dump_stream) | |
4035 | fprintf (loop_dump_stream, | |
4036 | "Biv %d initialized at insn %d: initial value ", | |
4037 | bl->regno, INSN_UID (bl->init_insn)); | |
4038 | ||
43a674af JW |
4039 | if ((GET_MODE (src) == GET_MODE (regno_reg_rtx[bl->regno]) |
4040 | || GET_MODE (src) == VOIDmode) | |
63d59526 | 4041 | && valid_initial_value_p (src, bl->init_insn, call_seen, loop_start)) |
b4ad7b23 RS |
4042 | { |
4043 | bl->initial_value = src; | |
4044 | ||
4045 | if (loop_dump_stream) | |
4046 | { | |
4047 | if (GET_CODE (src) == CONST_INT) | |
9ba7a303 JC |
4048 | { |
4049 | fprintf (loop_dump_stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (src)); | |
4050 | fputc ('\n', loop_dump_stream); | |
4051 | } | |
b4ad7b23 RS |
4052 | else |
4053 | { | |
4054 | print_rtl (loop_dump_stream, src); | |
4055 | fprintf (loop_dump_stream, "\n"); | |
4056 | } | |
4057 | } | |
4058 | } | |
4059 | else | |
4060 | { | |
3ec2b590 | 4061 | struct iv_class *bl2 = 0; |
6a651371 | 4062 | rtx increment = NULL_RTX; |
3ec2b590 R |
4063 | |
4064 | /* Biv initial value is not a simple move. If it is the sum of | |
4065 | another biv and a constant, check if both bivs are incremented | |
4066 | in lockstep. Then we are actually looking at a giv. | |
4067 | For simplicity, we only handle the case where there is but a | |
4068 | single increment, and the register is not used elsewhere. */ | |
4069 | if (bl->biv_count == 1 | |
4070 | && bl->regno < max_reg_before_loop | |
4071 | && uid_luid[REGNO_LAST_UID (bl->regno)] < INSN_LUID (loop_end) | |
4072 | && GET_CODE (src) == PLUS | |
4073 | && GET_CODE (XEXP (src, 0)) == REG | |
4074 | && CONSTANT_P (XEXP (src, 1)) | |
4075 | && ((increment = biv_total_increment (bl, loop_start, loop_end)) | |
4076 | != NULL_RTX)) | |
4077 | { | |
4078 | int regno = REGNO (XEXP (src, 0)); | |
b4ad7b23 | 4079 | |
3ec2b590 R |
4080 | for (bl2 = loop_iv_list; bl2; bl2 = bl2->next) |
4081 | if (bl2->regno == regno) | |
4082 | break; | |
4083 | } | |
4084 | ||
4085 | /* Now, can we transform this biv into a giv? */ | |
4086 | if (bl2 | |
4087 | && bl2->biv_count == 1 | |
4088 | && rtx_equal_p (increment, | |
4089 | biv_total_increment (bl2, loop_start, loop_end)) | |
4090 | /* init_insn is only set to insns that are before loop_start | |
4091 | without any intervening labels. */ | |
4092 | && ! reg_set_between_p (bl2->biv->src_reg, | |
4093 | PREV_INSN (bl->init_insn), loop_start) | |
4094 | /* The register from BL2 must be set before the register from | |
4095 | BL is set, or we must be able to move the latter set after | |
4096 | the former set. Currently there can't be any labels | |
51f53e01 | 4097 | in-between when biv_total_increment returns nonzero both times |
3ec2b590 R |
4098 | but we test it here in case some day some real cfg analysis |
4099 | gets used to set always_computable. */ | |
328de7da AS |
4100 | && (loop_insn_first_p (bl2->biv->insn, bl->biv->insn) |
4101 | ? no_labels_between_p (bl2->biv->insn, bl->biv->insn) | |
4102 | : (! reg_used_between_p (bl->biv->src_reg, bl->biv->insn, | |
4103 | bl2->biv->insn) | |
4104 | && no_jumps_between_p (bl->biv->insn, bl2->biv->insn))) | |
3ec2b590 R |
4105 | && validate_change (bl->biv->insn, |
4106 | &SET_SRC (single_set (bl->biv->insn)), | |
4107 | copy_rtx (src), 0)) | |
4108 | { | |
a2be868f | 4109 | rtx dominator = uid_loop[INSN_UID (loop_start)]->cont_dominator; |
3ec2b590 R |
4110 | rtx giv = bl->biv->src_reg; |
4111 | rtx giv_insn = bl->biv->insn; | |
4112 | rtx after_giv = NEXT_INSN (giv_insn); | |
4113 | ||
4114 | if (loop_dump_stream) | |
4115 | fprintf (loop_dump_stream, "is giv of biv %d\n", bl2->regno); | |
4116 | /* Let this giv be discovered by the generic code. */ | |
4117 | REG_IV_TYPE (bl->regno) = UNKNOWN_INDUCT; | |
dd1bd863 | 4118 | reg_biv_class[bl->regno] = (struct iv_class *) NULL_PTR; |
3ec2b590 R |
4119 | /* We can get better optimization if we can move the giv setting |
4120 | before the first giv use. */ | |
4121 | if (dominator | |
a2be868f | 4122 | && ! loop_insn_first_p (dominator, loop_scan_start) |
3ec2b590 R |
4123 | && ! reg_set_between_p (bl2->biv->src_reg, loop_start, |
4124 | dominator) | |
4125 | && ! reg_used_between_p (giv, loop_start, dominator) | |
4126 | && ! reg_used_between_p (giv, giv_insn, loop_end)) | |
4127 | { | |
4128 | rtx p; | |
22b4cc65 | 4129 | rtx next; |
3ec2b590 | 4130 | |
22b4cc65 | 4131 | for (next = NEXT_INSN (dominator); ; next = NEXT_INSN (next)) |
3ec2b590 | 4132 | { |
3ec2b590 R |
4133 | if ((GET_RTX_CLASS (GET_CODE (next)) == 'i' |
4134 | && (reg_mentioned_p (giv, PATTERN (next)) | |
4135 | || reg_set_p (bl2->biv->src_reg, next))) | |
4136 | || GET_CODE (next) == JUMP_INSN) | |
4137 | break; | |
4138 | #ifdef HAVE_cc0 | |
4139 | if (GET_RTX_CLASS (GET_CODE (next)) != 'i' | |
4140 | || ! sets_cc0_p (PATTERN (next))) | |
4141 | #endif | |
4142 | dominator = next; | |
4143 | } | |
4144 | if (loop_dump_stream) | |
4145 | fprintf (loop_dump_stream, "move after insn %d\n", | |
4146 | INSN_UID (dominator)); | |
4147 | /* Avoid problems with luids by actually moving the insn | |
4148 | and adjusting all luids in the range. */ | |
4149 | reorder_insns (giv_insn, giv_insn, dominator); | |
4150 | for (p = dominator; INSN_UID (p) >= max_uid_for_loop; ) | |
4151 | p = PREV_INSN (p); | |
4152 | compute_luids (giv_insn, after_giv, INSN_LUID (p)); | |
4153 | /* If the only purpose of the init insn is to initialize | |
4154 | this giv, delete it. */ | |
4155 | if (single_set (bl->init_insn) | |
4156 | && ! reg_used_between_p (giv, bl->init_insn, loop_start)) | |
4157 | delete_insn (bl->init_insn); | |
4158 | } | |
1cb1fe66 | 4159 | else if (! loop_insn_first_p (bl2->biv->insn, bl->biv->insn)) |
3ec2b590 R |
4160 | { |
4161 | rtx p = PREV_INSN (giv_insn); | |
4162 | while (INSN_UID (p) >= max_uid_for_loop) | |
4163 | p = PREV_INSN (p); | |
4164 | reorder_insns (giv_insn, giv_insn, bl2->biv->insn); | |
4165 | compute_luids (after_giv, NEXT_INSN (giv_insn), | |
4166 | INSN_LUID (p)); | |
4167 | } | |
4168 | /* Remove this biv from the chain. */ | |
4169 | if (bl->next) | |
e76d2376 R |
4170 | { |
4171 | /* We move the following giv from *bl->next into *bl. | |
4172 | We have to update reg_biv_class for that moved biv | |
4173 | to point to its new address. */ | |
4174 | *bl = *bl->next; | |
4175 | reg_biv_class[bl->regno] = bl; | |
4176 | } | |
3ec2b590 R |
4177 | else |
4178 | { | |
4179 | *backbl = 0; | |
4180 | break; | |
4181 | } | |
4182 | } | |
4183 | ||
4184 | /* If we can't make it a giv, | |
4185 | let biv keep initial value of "itself". */ | |
4186 | else if (loop_dump_stream) | |
b4ad7b23 RS |
4187 | fprintf (loop_dump_stream, "is complex\n"); |
4188 | } | |
4189 | } | |
4190 | ||
3ec2b590 R |
4191 | /* If a biv is unconditionally incremented several times in a row, convert |
4192 | all but the last increment into a giv. */ | |
4193 | ||
4194 | /* Get an upper bound for the number of registers | |
4195 | we might have after all bivs have been processed. */ | |
4196 | first_increment_giv = max_reg_num (); | |
4197 | for (n_extra_increment = 0, bl = loop_iv_list; bl; bl = bl->next) | |
4198 | n_extra_increment += bl->biv_count - 1; | |
6449b397 NC |
4199 | |
4200 | /* If the loop contains volatile memory references do not allow any | |
a2be868f MH |
4201 | replacements to take place, since this could loose the volatile |
4202 | markers. */ | |
3c748bb6 | 4203 | if (n_extra_increment && ! loop_info->has_volatile) |
3ec2b590 R |
4204 | { |
4205 | int nregs = first_increment_giv + n_extra_increment; | |
4206 | ||
4207 | /* Reallocate reg_iv_type and reg_iv_info. */ | |
4208 | VARRAY_GROW (reg_iv_type, nregs); | |
4209 | VARRAY_GROW (reg_iv_info, nregs); | |
4210 | ||
4211 | for (bl = loop_iv_list; bl; bl = bl->next) | |
4212 | { | |
4213 | struct induction **vp, *v, *next; | |
b72bdd84 R |
4214 | int biv_dead_after_loop = 0; |
4215 | ||
a2be868f MH |
4216 | /* The biv increments lists are in reverse order. Fix this |
4217 | first. */ | |
3ec2b590 R |
4218 | for (v = bl->biv, bl->biv = 0; v; v = next) |
4219 | { | |
4220 | next = v->next_iv; | |
4221 | v->next_iv = bl->biv; | |
4222 | bl->biv = v; | |
4223 | } | |
b72bdd84 R |
4224 | |
4225 | /* We must guard against the case that an early exit between v->insn | |
4226 | and next->insn leaves the biv live after the loop, since that | |
4227 | would mean that we'd be missing an increment for the final | |
4228 | value. The following test to set biv_dead_after_loop is like | |
4229 | the first part of the test to set bl->eliminable. | |
4230 | We don't check here if we can calculate the final value, since | |
4231 | this can't succeed if we already know that there is a jump | |
4232 | between v->insn and next->insn, yet next->always_executed is | |
4233 | set and next->maybe_multiple is cleared. Such a combination | |
cc291433 | 4234 | implies that the jump destination is outside the loop. |
b72bdd84 R |
4235 | If we want to make this check more sophisticated, we should |
4236 | check each branch between v->insn and next->insn individually | |
cc291433 | 4237 | to see if the biv is dead at its destination. */ |
b72bdd84 R |
4238 | |
4239 | if (uid_luid[REGNO_LAST_UID (bl->regno)] < INSN_LUID (loop_end) | |
4240 | && bl->init_insn | |
4241 | && INSN_UID (bl->init_insn) < max_uid_for_loop | |
4242 | && (uid_luid[REGNO_FIRST_UID (bl->regno)] | |
4243 | >= INSN_LUID (bl->init_insn)) | |
4244 | #ifdef HAVE_decrement_and_branch_until_zero | |
4245 | && ! bl->nonneg | |
4246 | #endif | |
4247 | && ! reg_mentioned_p (bl->biv->dest_reg, SET_SRC (bl->init_set))) | |
4248 | biv_dead_after_loop = 1; | |
4249 | ||
3ec2b590 R |
4250 | for (vp = &bl->biv, next = *vp; v = next, next = v->next_iv;) |
4251 | { | |
4252 | HOST_WIDE_INT offset; | |
a47f48d8 | 4253 | rtx set, add_val, old_reg, dest_reg, last_use_insn, note; |
3ec2b590 | 4254 | int old_regno, new_regno; |
b72bdd84 | 4255 | |
3ec2b590 R |
4256 | if (! v->always_executed |
4257 | || v->maybe_multiple | |
4258 | || GET_CODE (v->add_val) != CONST_INT | |
4259 | || ! next->always_executed | |
4260 | || next->maybe_multiple | |
b72bdd84 | 4261 | || ! CONSTANT_P (next->add_val) |
2485126f R |
4262 | || v->mult_val != const1_rtx |
4263 | || next->mult_val != const1_rtx | |
b72bdd84 R |
4264 | || ! (biv_dead_after_loop |
4265 | || no_jumps_between_p (v->insn, next->insn))) | |
3ec2b590 R |
4266 | { |
4267 | vp = &v->next_iv; | |
4268 | continue; | |
4269 | } | |
4270 | offset = INTVAL (v->add_val); | |
4271 | set = single_set (v->insn); | |
4272 | add_val = plus_constant (next->add_val, offset); | |
4273 | old_reg = v->dest_reg; | |
4274 | dest_reg = gen_reg_rtx (v->mode); | |
4275 | ||
f56246be R |
4276 | /* Unlike reg_iv_type / reg_iv_info, the other three arrays |
4277 | have been allocated with some slop space, so we may not | |
4278 | actually need to reallocate them. If we do, the following | |
4279 | if statement will be executed just once in this loop. */ | |
3ec2b590 R |
4280 | if ((unsigned) max_reg_num () > n_times_set->num_elements) |
4281 | { | |
f56246be | 4282 | /* Grow all the remaining arrays. */ |
3ec2b590 R |
4283 | VARRAY_GROW (set_in_loop, nregs); |
4284 | VARRAY_GROW (n_times_set, nregs); | |
4285 | VARRAY_GROW (may_not_optimize, nregs); | |
a366a40a | 4286 | VARRAY_GROW (reg_single_usage, nregs); |
3ec2b590 R |
4287 | } |
4288 | ||
8e9fb571 | 4289 | if (! validate_change (next->insn, next->location, add_val, 0)) |
3ec2b590 R |
4290 | { |
4291 | vp = &v->next_iv; | |
4292 | continue; | |
4293 | } | |
8e9fb571 R |
4294 | |
4295 | /* Here we can try to eliminate the increment by combining | |
4296 | it into the uses. */ | |
4297 | ||
4298 | /* Set last_use_insn so that we can check against it. */ | |
4299 | ||
4300 | for (last_use_insn = v->insn, p = NEXT_INSN (v->insn); | |
4301 | p != next->insn; | |
a2be868f | 4302 | p = next_insn_in_loop (loop, p)) |
8e9fb571 | 4303 | { |
8e9fb571 R |
4304 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
4305 | continue; | |
4306 | if (reg_mentioned_p (old_reg, PATTERN (p))) | |
4307 | { | |
4308 | last_use_insn = p; | |
4309 | } | |
4310 | } | |
4311 | ||
4312 | /* If we can't get the LUIDs for the insns, we can't | |
4313 | calculate the lifetime. This is likely from unrolling | |
4314 | of an inner loop, so there is little point in making this | |
4315 | a DEST_REG giv anyways. */ | |
4316 | if (INSN_UID (v->insn) >= max_uid_for_loop | |
4317 | || INSN_UID (last_use_insn) >= max_uid_for_loop | |
4318 | || ! validate_change (v->insn, &SET_DEST (set), dest_reg, 0)) | |
4319 | { | |
4320 | /* Change the increment at NEXT back to what it was. */ | |
4321 | if (! validate_change (next->insn, next->location, | |
4322 | next->add_val, 0)) | |
4323 | abort (); | |
4324 | vp = &v->next_iv; | |
4325 | continue; | |
4326 | } | |
3ec2b590 R |
4327 | next->add_val = add_val; |
4328 | v->dest_reg = dest_reg; | |
4329 | v->giv_type = DEST_REG; | |
4330 | v->location = &SET_SRC (set); | |
4331 | v->cant_derive = 0; | |
4332 | v->combined_with = 0; | |
4333 | v->maybe_dead = 0; | |
4334 | v->derive_adjustment = 0; | |
4335 | v->same = 0; | |
4336 | v->ignore = 0; | |
4337 | v->new_reg = 0; | |
4338 | v->final_value = 0; | |
4339 | v->same_insn = 0; | |
4340 | v->auto_inc_opt = 0; | |
4341 | v->unrolled = 0; | |
4342 | v->shared = 0; | |
4d87f7a7 | 4343 | v->derived_from = 0; |
3ec2b590 R |
4344 | v->always_computable = 1; |
4345 | v->always_executed = 1; | |
4346 | v->replaceable = 1; | |
4347 | v->no_const_addval = 0; | |
4348 | ||
4349 | old_regno = REGNO (old_reg); | |
4350 | new_regno = REGNO (dest_reg); | |
4351 | VARRAY_INT (set_in_loop, old_regno)--; | |
4352 | VARRAY_INT (set_in_loop, new_regno) = 1; | |
4353 | VARRAY_INT (n_times_set, old_regno)--; | |
4354 | VARRAY_INT (n_times_set, new_regno) = 1; | |
4355 | VARRAY_CHAR (may_not_optimize, new_regno) = 0; | |
4356 | ||
4357 | REG_IV_TYPE (new_regno) = GENERAL_INDUCT; | |
4358 | REG_IV_INFO (new_regno) = v; | |
a47f48d8 R |
4359 | |
4360 | /* If next_insn has a REG_EQUAL note that mentiones OLD_REG, | |
4361 | it must be replaced. */ | |
4362 | note = find_reg_note (next->insn, REG_EQUAL, NULL_RTX); | |
4363 | if (note && reg_mentioned_p (old_reg, XEXP (note, 0))) | |
4364 | XEXP (note, 0) = copy_rtx (SET_SRC (single_set (next->insn))); | |
4365 | ||
3ec2b590 R |
4366 | /* Remove the increment from the list of biv increments, |
4367 | and record it as a giv. */ | |
4368 | *vp = next; | |
4369 | bl->biv_count--; | |
4370 | v->next_iv = bl->giv; | |
4371 | bl->giv = v; | |
4372 | bl->giv_count++; | |
4373 | v->benefit = rtx_cost (SET_SRC (set), SET); | |
4374 | bl->total_benefit += v->benefit; | |
4375 | ||
4376 | /* Now replace the biv with DEST_REG in all insns between | |
4377 | the replaced increment and the next increment, and | |
4378 | remember the last insn that needed a replacement. */ | |
4379 | for (last_use_insn = v->insn, p = NEXT_INSN (v->insn); | |
4380 | p != next->insn; | |
a2be868f | 4381 | p = next_insn_in_loop (loop, p)) |
3ec2b590 R |
4382 | { |
4383 | rtx note; | |
4384 | ||
4385 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
4386 | continue; | |
4387 | if (reg_mentioned_p (old_reg, PATTERN (p))) | |
4388 | { | |
4389 | last_use_insn = p; | |
4390 | if (! validate_replace_rtx (old_reg, dest_reg, p)) | |
4391 | abort (); | |
4392 | } | |
4393 | for (note = REG_NOTES (p); note; note = XEXP (note, 1)) | |
4394 | { | |
4395 | if (GET_CODE (note) == EXPR_LIST) | |
4396 | XEXP (note, 0) | |
4397 | = replace_rtx (XEXP (note, 0), old_reg, dest_reg); | |
4398 | } | |
4399 | } | |
4400 | ||
4401 | v->last_use = last_use_insn; | |
e1bb2458 | 4402 | v->lifetime = INSN_LUID (last_use_insn) - INSN_LUID (v->insn); |
3ec2b590 R |
4403 | /* If the lifetime is zero, it means that this register is really |
4404 | a dead store. So mark this as a giv that can be ignored. | |
4405 | This will not prevent the biv from being eliminated. */ | |
4406 | if (v->lifetime == 0) | |
4407 | v->ignore = 1; | |
1ccf8937 R |
4408 | |
4409 | if (loop_dump_stream) | |
4410 | fprintf (loop_dump_stream, | |
60fb6df9 | 4411 | "Increment %d of biv %d converted to giv %d.\n", |
1ccf8937 | 4412 | INSN_UID (v->insn), old_regno, new_regno); |
3ec2b590 R |
4413 | } |
4414 | } | |
4415 | } | |
4416 | last_increment_giv = max_reg_num () - 1; | |
4417 | ||
b4ad7b23 RS |
4418 | /* Search the loop for general induction variables. */ |
4419 | ||
4420 | /* A register is a giv if: it is only set once, it is a function of a | |
4421 | biv and a constant (or invariant), and it is not a biv. */ | |
4422 | ||
4423 | not_every_iteration = 0; | |
5ea7a4ae | 4424 | loop_depth = 0; |
c5c76735 | 4425 | maybe_multiple = 0; |
a2be868f | 4426 | p = loop_scan_start; |
b4ad7b23 RS |
4427 | while (1) |
4428 | { | |
4429 | p = NEXT_INSN (p); | |
4430 | /* At end of a straight-in loop, we are done. | |
4431 | At end of a loop entered at the bottom, scan the top. */ | |
a2be868f | 4432 | if (p == loop_scan_start) |
b4ad7b23 | 4433 | break; |
a2be868f | 4434 | if (p == loop_end) |
b4ad7b23 RS |
4435 | { |
4436 | if (loop_top != 0) | |
f67ff5de | 4437 | p = loop_top; |
b4ad7b23 RS |
4438 | else |
4439 | break; | |
a2be868f | 4440 | if (p == loop_scan_start) |
b4ad7b23 RS |
4441 | break; |
4442 | } | |
4443 | ||
4444 | /* Look for a general induction variable in a register. */ | |
4445 | if (GET_CODE (p) == INSN | |
4446 | && (set = single_set (p)) | |
4447 | && GET_CODE (SET_DEST (set)) == REG | |
8deb8e2c | 4448 | && ! VARRAY_CHAR (may_not_optimize, REGNO (SET_DEST (set)))) |
b4ad7b23 RS |
4449 | { |
4450 | rtx src_reg; | |
4451 | rtx add_val; | |
4452 | rtx mult_val; | |
4453 | int benefit; | |
4454 | rtx regnote = 0; | |
a07516d3 | 4455 | rtx last_consec_insn; |
b4ad7b23 RS |
4456 | |
4457 | dest_reg = SET_DEST (set); | |
4458 | if (REGNO (dest_reg) < FIRST_PSEUDO_REGISTER) | |
4459 | continue; | |
4460 | ||
4461 | if (/* SET_SRC is a giv. */ | |
45f97e2e RH |
4462 | (general_induction_var (SET_SRC (set), &src_reg, &add_val, |
4463 | &mult_val, 0, &benefit) | |
0f41302f | 4464 | /* Equivalent expression is a giv. */ |
5fd8383e | 4465 | || ((regnote = find_reg_note (p, REG_EQUAL, NULL_RTX)) |
45f97e2e RH |
4466 | && general_induction_var (XEXP (regnote, 0), &src_reg, |
4467 | &add_val, &mult_val, 0, | |
4468 | &benefit))) | |
b4ad7b23 RS |
4469 | /* Don't try to handle any regs made by loop optimization. |
4470 | We have nothing on them in regno_first_uid, etc. */ | |
4471 | && REGNO (dest_reg) < max_reg_before_loop | |
4472 | /* Don't recognize a BASIC_INDUCT_VAR here. */ | |
4473 | && dest_reg != src_reg | |
4474 | /* This must be the only place where the register is set. */ | |
8deb8e2c | 4475 | && (VARRAY_INT (n_times_set, REGNO (dest_reg)) == 1 |
0f41302f | 4476 | /* or all sets must be consecutive and make a giv. */ |
b4ad7b23 RS |
4477 | || (benefit = consec_sets_giv (benefit, p, |
4478 | src_reg, dest_reg, | |
a07516d3 R |
4479 | &add_val, &mult_val, |
4480 | &last_consec_insn)))) | |
b4ad7b23 | 4481 | { |
b4ad7b23 RS |
4482 | struct induction *v |
4483 | = (struct induction *) alloca (sizeof (struct induction)); | |
b4ad7b23 RS |
4484 | |
4485 | /* If this is a library call, increase benefit. */ | |
5fd8383e | 4486 | if (find_reg_note (p, REG_RETVAL, NULL_RTX)) |
b4ad7b23 RS |
4487 | benefit += libcall_benefit (p); |
4488 | ||
4489 | /* Skip the consecutive insns, if there are any. */ | |
a07516d3 R |
4490 | if (VARRAY_INT (n_times_set, REGNO (dest_reg)) != 1) |
4491 | p = last_consec_insn; | |
b4ad7b23 RS |
4492 | |
4493 | record_giv (v, p, src_reg, dest_reg, mult_val, add_val, benefit, | |
c5c76735 JL |
4494 | DEST_REG, not_every_iteration, maybe_multiple, |
4495 | NULL_PTR, loop_start, loop_end); | |
b4ad7b23 RS |
4496 | |
4497 | } | |
4498 | } | |
4499 | ||
4500 | #ifndef DONT_REDUCE_ADDR | |
4501 | /* Look for givs which are memory addresses. */ | |
4502 | /* This resulted in worse code on a VAX 8600. I wonder if it | |
4503 | still does. */ | |
4504 | if (GET_CODE (p) == INSN) | |
c5c76735 JL |
4505 | find_mem_givs (PATTERN (p), p, not_every_iteration, maybe_multiple, |
4506 | loop_start, loop_end); | |
b4ad7b23 RS |
4507 | #endif |
4508 | ||
4509 | /* Update the status of whether giv can derive other givs. This can | |
4510 | change when we pass a label or an insn that updates a biv. */ | |
7dcd3836 RK |
4511 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN |
4512 | || GET_CODE (p) == CODE_LABEL) | |
b4ad7b23 RS |
4513 | update_giv_derive (p); |
4514 | ||
c5c76735 JL |
4515 | /* Past CODE_LABEL, we get to insns that may be executed multiple |
4516 | times. The only way we can be sure that they can't is if every | |
4517 | every jump insn between here and the end of the loop either | |
4518 | returns, exits the loop, is a forward jump, or is a jump | |
4519 | to the loop start. */ | |
4520 | ||
4521 | if (GET_CODE (p) == CODE_LABEL) | |
4522 | { | |
4523 | rtx insn = p; | |
4524 | ||
4525 | maybe_multiple = 0; | |
4526 | ||
4527 | while (1) | |
4528 | { | |
4529 | insn = NEXT_INSN (insn); | |
a2be868f | 4530 | if (insn == loop_scan_start) |
c5c76735 | 4531 | break; |
a2be868f | 4532 | if (insn == loop_end) |
c5c76735 JL |
4533 | { |
4534 | if (loop_top != 0) | |
4535 | insn = loop_top; | |
4536 | else | |
4537 | break; | |
a2be868f | 4538 | if (insn == loop_scan_start) |
c5c76735 JL |
4539 | break; |
4540 | } | |
4541 | ||
4542 | if (GET_CODE (insn) == JUMP_INSN | |
4543 | && GET_CODE (PATTERN (insn)) != RETURN | |
4544 | && (! condjump_p (insn) | |
4545 | || (JUMP_LABEL (insn) != 0 | |
a2be868f | 4546 | && JUMP_LABEL (insn) != loop_scan_start |
c5c76735 JL |
4547 | && (INSN_UID (JUMP_LABEL (insn)) >= max_uid_for_loop |
4548 | || INSN_UID (insn) >= max_uid_for_loop | |
4549 | || (INSN_LUID (JUMP_LABEL (insn)) | |
4550 | < INSN_LUID (insn)))))) | |
4551 | { | |
4552 | maybe_multiple = 1; | |
4553 | break; | |
4554 | } | |
4555 | } | |
4556 | } | |
4557 | ||
8516af93 JW |
4558 | /* Past a jump, we get to insns for which we can't count |
4559 | on whether they will be executed during each iteration. */ | |
4560 | /* This code appears twice in strength_reduce. There is also similar | |
4561 | code in scan_loop. */ | |
4562 | if (GET_CODE (p) == JUMP_INSN | |
4563 | /* If we enter the loop in the middle, and scan around to the | |
4564 | beginning, don't set not_every_iteration for that. | |
b4ad7b23 RS |
4565 | This can be any kind of jump, since we want to know if insns |
4566 | will be executed if the loop is executed. */ | |
8516af93 | 4567 | && ! (JUMP_LABEL (p) == loop_top |
b4ad7b23 RS |
4568 | && ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p)) |
4569 | || (NEXT_INSN (p) == loop_end && condjump_p (p))))) | |
8516af93 JW |
4570 | { |
4571 | rtx label = 0; | |
4572 | ||
4573 | /* If this is a jump outside the loop, then it also doesn't | |
4574 | matter. Check to see if the target of this branch is on the | |
a2be868f | 4575 | loop->exits_labels list. */ |
8516af93 | 4576 | |
a2be868f | 4577 | for (label = uid_loop[INSN_UID (loop_start)]->exit_labels; |
8516af93 JW |
4578 | label; |
4579 | label = LABEL_NEXTREF (label)) | |
4580 | if (XEXP (label, 0) == JUMP_LABEL (p)) | |
4581 | break; | |
4582 | ||
4583 | if (! label) | |
4584 | not_every_iteration = 1; | |
4585 | } | |
b4ad7b23 | 4586 | |
5ea7a4ae JW |
4587 | else if (GET_CODE (p) == NOTE) |
4588 | { | |
4589 | /* At the virtual top of a converted loop, insns are again known to | |
4590 | be executed each iteration: logically, the loop begins here | |
5f3db57e JL |
4591 | even though the exit code has been duplicated. |
4592 | ||
4593 | Insns are also again known to be executed each iteration at | |
4594 | the LOOP_CONT note. */ | |
4595 | if ((NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP | |
4596 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_CONT) | |
4597 | && loop_depth == 0) | |
5ea7a4ae JW |
4598 | not_every_iteration = 0; |
4599 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) | |
4600 | loop_depth++; | |
4601 | else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END) | |
4602 | loop_depth--; | |
4603 | } | |
b4ad7b23 RS |
4604 | |
4605 | /* Unlike in the code motion pass where MAYBE_NEVER indicates that | |
4606 | an insn may never be executed, NOT_EVERY_ITERATION indicates whether | |
4607 | or not an insn is known to be executed each iteration of the | |
4608 | loop, whether or not any iterations are known to occur. | |
4609 | ||
4610 | Therefore, if we have just passed a label and have no more labels | |
4611 | between here and the test insn of the loop, we know these insns | |
4612 | will be executed each iteration. */ | |
4613 | ||
4614 | if (not_every_iteration && GET_CODE (p) == CODE_LABEL | |
6dd49eb4 | 4615 | && no_labels_between_p (p, loop_end) |
1cb1fe66 | 4616 | && loop_insn_first_p (p, loop_cont)) |
b4ad7b23 RS |
4617 | not_every_iteration = 0; |
4618 | } | |
4619 | ||
4620 | /* Try to calculate and save the number of loop iterations. This is | |
4621 | set to zero if the actual number can not be calculated. This must | |
4622 | be called after all giv's have been identified, since otherwise it may | |
4623 | fail if the iteration variable is a giv. */ | |
4624 | ||
a2be868f | 4625 | loop_iterations (loop); |
b4ad7b23 RS |
4626 | |
4627 | /* Now for each giv for which we still don't know whether or not it is | |
4628 | replaceable, check to see if it is replaceable because its final value | |
4629 | can be calculated. This must be done after loop_iterations is called, | |
4630 | so that final_giv_value will work correctly. */ | |
4631 | ||
4632 | for (bl = loop_iv_list; bl; bl = bl->next) | |
4633 | { | |
4634 | struct induction *v; | |
4635 | ||
4636 | for (v = bl->giv; v; v = v->next_iv) | |
4637 | if (! v->replaceable && ! v->not_replaceable) | |
302670f3 | 4638 | check_final_value (v, loop_start, loop_end, loop_info->n_iterations); |
b4ad7b23 RS |
4639 | } |
4640 | ||
4641 | /* Try to prove that the loop counter variable (if any) is always | |
4642 | nonnegative; if so, record that fact with a REG_NONNEG note | |
4643 | so that "decrement and branch until zero" insn can be used. */ | |
a2be868f | 4644 | check_dbra_loop (loop, insn_count); |
b4ad7b23 | 4645 | |
97ec0ad8 R |
4646 | /* Create reg_map to hold substitutions for replaceable giv regs. |
4647 | Some givs might have been made from biv increments, so look at | |
4648 | reg_iv_type for a suitable size. */ | |
4649 | reg_map_size = reg_iv_type->num_elements; | |
4da896b2 | 4650 | reg_map = (rtx *) xcalloc (reg_map_size, sizeof (rtx)); |
b4ad7b23 RS |
4651 | |
4652 | /* Examine each iv class for feasibility of strength reduction/induction | |
4653 | variable elimination. */ | |
4654 | ||
4655 | for (bl = loop_iv_list; bl; bl = bl->next) | |
4656 | { | |
4657 | struct induction *v; | |
4658 | int benefit; | |
4659 | int all_reduced; | |
4660 | rtx final_value = 0; | |
3c748bb6 | 4661 | unsigned int nregs; |
b4ad7b23 RS |
4662 | |
4663 | /* Test whether it will be possible to eliminate this biv | |
4664 | provided all givs are reduced. This is possible if either | |
4665 | the reg is not used outside the loop, or we can compute | |
4666 | what its final value will be. | |
4667 | ||
4668 | For architectures with a decrement_and_branch_until_zero insn, | |
4669 | don't do this if we put a REG_NONNEG note on the endtest for | |
4670 | this biv. */ | |
4671 | ||
4672 | /* Compare against bl->init_insn rather than loop_start. | |
4673 | We aren't concerned with any uses of the biv between | |
4674 | init_insn and loop_start since these won't be affected | |
4675 | by the value of the biv elsewhere in the function, so | |
4676 | long as init_insn doesn't use the biv itself. | |
4677 | March 14, 1989 -- self@bayes.arc.nasa.gov */ | |
4678 | ||
b1f21e0a | 4679 | if ((uid_luid[REGNO_LAST_UID (bl->regno)] < INSN_LUID (loop_end) |
b4ad7b23 RS |
4680 | && bl->init_insn |
4681 | && INSN_UID (bl->init_insn) < max_uid_for_loop | |
b1f21e0a | 4682 | && uid_luid[REGNO_FIRST_UID (bl->regno)] >= INSN_LUID (bl->init_insn) |
b4ad7b23 RS |
4683 | #ifdef HAVE_decrement_and_branch_until_zero |
4684 | && ! bl->nonneg | |
4685 | #endif | |
4686 | && ! reg_mentioned_p (bl->biv->dest_reg, SET_SRC (bl->init_set))) | |
302670f3 MH |
4687 | || ((final_value = final_biv_value (bl, loop_start, loop_end, |
4688 | loop_info->n_iterations)) | |
b4ad7b23 RS |
4689 | #ifdef HAVE_decrement_and_branch_until_zero |
4690 | && ! bl->nonneg | |
4691 | #endif | |
4692 | )) | |
a2be868f | 4693 | bl->eliminable = maybe_eliminate_biv (bl, loop_start, loop_end, 0, |
b4ad7b23 RS |
4694 | threshold, insn_count); |
4695 | else | |
4696 | { | |
4697 | if (loop_dump_stream) | |
4698 | { | |
4699 | fprintf (loop_dump_stream, | |
4700 | "Cannot eliminate biv %d.\n", | |
4701 | bl->regno); | |
4702 | fprintf (loop_dump_stream, | |
4703 | "First use: insn %d, last use: insn %d.\n", | |
b1f21e0a MM |
4704 | REGNO_FIRST_UID (bl->regno), |
4705 | REGNO_LAST_UID (bl->regno)); | |
b4ad7b23 RS |
4706 | } |
4707 | } | |
4708 | ||
4709 | /* Combine all giv's for this iv_class. */ | |
4710 | combine_givs (bl); | |
4711 | ||
4712 | /* This will be true at the end, if all givs which depend on this | |
4713 | biv have been strength reduced. | |
4714 | We can't (currently) eliminate the biv unless this is so. */ | |
4715 | all_reduced = 1; | |
4716 | ||
4717 | /* Check each giv in this class to see if we will benefit by reducing | |
4718 | it. Skip giv's combined with others. */ | |
4719 | for (v = bl->giv; v; v = v->next_iv) | |
4720 | { | |
4721 | struct induction *tv; | |
4722 | ||
4723 | if (v->ignore || v->same) | |
4724 | continue; | |
4725 | ||
4726 | benefit = v->benefit; | |
4727 | ||
4728 | /* Reduce benefit if not replaceable, since we will insert | |
4729 | a move-insn to replace the insn that calculates this giv. | |
4730 | Don't do this unless the giv is a user variable, since it | |
4731 | will often be marked non-replaceable because of the duplication | |
4732 | of the exit code outside the loop. In such a case, the copies | |
4733 | we insert are dead and will be deleted. So they don't have | |
4734 | a cost. Similar situations exist. */ | |
4735 | /* ??? The new final_[bg]iv_value code does a much better job | |
4736 | of finding replaceable giv's, and hence this code may no longer | |
4737 | be necessary. */ | |
4738 | if (! v->replaceable && ! bl->eliminable | |
4739 | && REG_USERVAR_P (v->dest_reg)) | |
4740 | benefit -= copy_cost; | |
4741 | ||
4742 | /* Decrease the benefit to count the add-insns that we will | |
4743 | insert to increment the reduced reg for the giv. */ | |
4744 | benefit -= add_cost * bl->biv_count; | |
4745 | ||
4746 | /* Decide whether to strength-reduce this giv or to leave the code | |
4747 | unchanged (recompute it from the biv each time it is used). | |
4748 | This decision can be made independently for each giv. */ | |
4749 | ||
ab162578 JL |
4750 | #ifdef AUTO_INC_DEC |
4751 | /* Attempt to guess whether autoincrement will handle some of the | |
4752 | new add insns; if so, increase BENEFIT (undo the subtraction of | |
4753 | add_cost that was done above). */ | |
4754 | if (v->giv_type == DEST_ADDR | |
4755 | && GET_CODE (v->mult_val) == CONST_INT) | |
4756 | { | |
940da324 JL |
4757 | if (HAVE_POST_INCREMENT |
4758 | && INTVAL (v->mult_val) == GET_MODE_SIZE (v->mem_mode)) | |
ab162578 | 4759 | benefit += add_cost * bl->biv_count; |
940da324 JL |
4760 | else if (HAVE_PRE_INCREMENT |
4761 | && INTVAL (v->mult_val) == GET_MODE_SIZE (v->mem_mode)) | |
4762 | benefit += add_cost * bl->biv_count; | |
4763 | else if (HAVE_POST_DECREMENT | |
4764 | && -INTVAL (v->mult_val) == GET_MODE_SIZE (v->mem_mode)) | |
4765 | benefit += add_cost * bl->biv_count; | |
4766 | else if (HAVE_PRE_DECREMENT | |
4767 | && -INTVAL (v->mult_val) == GET_MODE_SIZE (v->mem_mode)) | |
ab162578 | 4768 | benefit += add_cost * bl->biv_count; |
ab162578 JL |
4769 | } |
4770 | #endif | |
b4ad7b23 RS |
4771 | |
4772 | /* If an insn is not to be strength reduced, then set its ignore | |
4773 | flag, and clear all_reduced. */ | |
4774 | ||
e6f6eb29 JW |
4775 | /* A giv that depends on a reversed biv must be reduced if it is |
4776 | used after the loop exit, otherwise, it would have the wrong | |
4777 | value after the loop exit. To make it simple, just reduce all | |
4778 | of such giv's whether or not we know they are used after the loop | |
4779 | exit. */ | |
4780 | ||
e5eb27e5 JL |
4781 | if ( ! flag_reduce_all_givs && v->lifetime * threshold * benefit < insn_count |
4782 | && ! bl->reversed ) | |
b4ad7b23 RS |
4783 | { |
4784 | if (loop_dump_stream) | |
4785 | fprintf (loop_dump_stream, | |
4786 | "giv of insn %d not worth while, %d vs %d.\n", | |
4787 | INSN_UID (v->insn), | |
4788 | v->lifetime * threshold * benefit, insn_count); | |
4789 | v->ignore = 1; | |
4790 | all_reduced = 0; | |
4791 | } | |
4792 | else | |
4793 | { | |
4794 | /* Check that we can increment the reduced giv without a | |
4795 | multiply insn. If not, reject it. */ | |
4796 | ||
4797 | for (tv = bl->biv; tv; tv = tv->next_iv) | |
4798 | if (tv->mult_val == const1_rtx | |
4799 | && ! product_cheap_p (tv->add_val, v->mult_val)) | |
4800 | { | |
4801 | if (loop_dump_stream) | |
4802 | fprintf (loop_dump_stream, | |
4803 | "giv of insn %d: would need a multiply.\n", | |
4804 | INSN_UID (v->insn)); | |
4805 | v->ignore = 1; | |
4806 | all_reduced = 0; | |
4807 | break; | |
4808 | } | |
4809 | } | |
4810 | } | |
4811 | ||
8c354a41 R |
4812 | /* Check for givs whose first use is their definition and whose |
4813 | last use is the definition of another giv. If so, it is likely | |
4814 | dead and should not be used to derive another giv nor to | |
4815 | eliminate a biv. */ | |
4816 | for (v = bl->giv; v; v = v->next_iv) | |
4817 | { | |
4818 | if (v->ignore | |
4819 | || (v->same && v->same->ignore)) | |
4820 | continue; | |
4821 | ||
4822 | if (v->last_use) | |
4823 | { | |
4824 | struct induction *v1; | |
4825 | ||
4826 | for (v1 = bl->giv; v1; v1 = v1->next_iv) | |
4827 | if (v->last_use == v1->insn) | |
4828 | v->maybe_dead = 1; | |
4829 | } | |
4830 | else if (v->giv_type == DEST_REG | |
4831 | && REGNO_FIRST_UID (REGNO (v->dest_reg)) == INSN_UID (v->insn)) | |
4832 | { | |
4833 | struct induction *v1; | |
4834 | ||
4835 | for (v1 = bl->giv; v1; v1 = v1->next_iv) | |
4836 | if (REGNO_LAST_UID (REGNO (v->dest_reg)) == INSN_UID (v1->insn)) | |
4837 | v->maybe_dead = 1; | |
4838 | } | |
4839 | } | |
4840 | ||
3ec2b590 | 4841 | /* Now that we know which givs will be reduced, try to rearrange the |
f56246be R |
4842 | combinations to reduce register pressure. |
4843 | recombine_givs calls find_life_end, which needs reg_iv_type and | |
4844 | reg_iv_info to be valid for all pseudos. We do the necessary | |
4845 | reallocation here since it allows to check if there are still | |
4846 | more bivs to process. */ | |
4847 | nregs = max_reg_num (); | |
4848 | if (nregs > reg_iv_type->num_elements) | |
4849 | { | |
4850 | /* If there are still more bivs to process, allocate some slack | |
4851 | space so that we're not constantly reallocating these arrays. */ | |
4852 | if (bl->next) | |
4853 | nregs += nregs / 4; | |
4854 | /* Reallocate reg_iv_type and reg_iv_info. */ | |
4855 | VARRAY_GROW (reg_iv_type, nregs); | |
4856 | VARRAY_GROW (reg_iv_info, nregs); | |
4857 | } | |
53dc05e4 | 4858 | recombine_givs (bl, loop_start, loop_end, unroll_p); |
3ec2b590 | 4859 | |
b4ad7b23 RS |
4860 | /* Reduce each giv that we decided to reduce. */ |
4861 | ||
4862 | for (v = bl->giv; v; v = v->next_iv) | |
4863 | { | |
4864 | struct induction *tv; | |
4865 | if (! v->ignore && v->same == 0) | |
4866 | { | |
8516af93 JW |
4867 | int auto_inc_opt = 0; |
4868 | ||
743f9f5d R |
4869 | /* If the code for derived givs immediately below has already |
4870 | allocated a new_reg, we must keep it. */ | |
4871 | if (! v->new_reg) | |
4872 | v->new_reg = gen_reg_rtx (v->mode); | |
b4ad7b23 | 4873 | |
4d87f7a7 | 4874 | if (v->derived_from) |
3ec2b590 | 4875 | { |
743f9f5d R |
4876 | struct induction *d = v->derived_from; |
4877 | ||
4878 | /* In case d->dest_reg is not replaceable, we have | |
4879 | to replace it in v->insn now. */ | |
4880 | if (! d->new_reg) | |
4881 | d->new_reg = gen_reg_rtx (d->mode); | |
4882 | PATTERN (v->insn) | |
4883 | = replace_rtx (PATTERN (v->insn), d->dest_reg, d->new_reg); | |
3ec2b590 R |
4884 | PATTERN (v->insn) |
4885 | = replace_rtx (PATTERN (v->insn), v->dest_reg, v->new_reg); | |
1b786838 R |
4886 | /* For each place where the biv is incremented, add an |
4887 | insn to set the new, reduced reg for the giv. | |
4888 | We used to do this only for biv_count != 1, but | |
4889 | this fails when there is a giv after a single biv | |
4890 | increment, e.g. when the last giv was expressed as | |
4891 | pre-decrement. */ | |
4892 | for (tv = bl->biv; tv; tv = tv->next_iv) | |
3ec2b590 | 4893 | { |
1b786838 R |
4894 | /* We always emit reduced giv increments before the |
4895 | biv increment when bl->biv_count != 1. So by | |
4896 | emitting the add insns for derived givs after the | |
4897 | biv increment, they pick up the updated value of | |
4898 | the reduced giv. | |
4899 | If the reduced giv is processed with | |
4900 | auto_inc_opt == 1, then it is incremented earlier | |
4901 | than the biv, hence we'll still pick up the right | |
4902 | value. | |
4903 | If it's processed with auto_inc_opt == -1, | |
4904 | that implies that the biv increment is before the | |
4905 | first reduced giv's use. The derived giv's lifetime | |
4906 | is after the reduced giv's lifetime, hence in this | |
4907 | case, the biv increment doesn't matter. */ | |
4908 | emit_insn_after (copy_rtx (PATTERN (v->insn)), tv->insn); | |
3ec2b590 R |
4909 | } |
4910 | continue; | |
4911 | } | |
4912 | ||
8516af93 JW |
4913 | #ifdef AUTO_INC_DEC |
4914 | /* If the target has auto-increment addressing modes, and | |
4915 | this is an address giv, then try to put the increment | |
4916 | immediately after its use, so that flow can create an | |
4917 | auto-increment addressing mode. */ | |
4918 | if (v->giv_type == DEST_ADDR && bl->biv_count == 1 | |
085daa5a JW |
4919 | && bl->biv->always_executed && ! bl->biv->maybe_multiple |
4920 | /* We don't handle reversed biv's because bl->biv->insn | |
4921 | does not have a valid INSN_LUID. */ | |
4922 | && ! bl->reversed | |
f5963e61 JL |
4923 | && v->always_executed && ! v->maybe_multiple |
4924 | && INSN_UID (v->insn) < max_uid_for_loop) | |
8516af93 JW |
4925 | { |
4926 | /* If other giv's have been combined with this one, then | |
4927 | this will work only if all uses of the other giv's occur | |
4928 | before this giv's insn. This is difficult to check. | |
4929 | ||
4930 | We simplify this by looking for the common case where | |
4931 | there is one DEST_REG giv, and this giv's insn is the | |
4932 | last use of the dest_reg of that DEST_REG giv. If the | |
38e01259 | 4933 | increment occurs after the address giv, then we can |
8516af93 JW |
4934 | perform the optimization. (Otherwise, the increment |
4935 | would have to go before other_giv, and we would not be | |
4936 | able to combine it with the address giv to get an | |
4937 | auto-inc address.) */ | |
4938 | if (v->combined_with) | |
4939 | { | |
4940 | struct induction *other_giv = 0; | |
4941 | ||
4942 | for (tv = bl->giv; tv; tv = tv->next_iv) | |
4943 | if (tv->same == v) | |
4944 | { | |
4945 | if (other_giv) | |
4946 | break; | |
4947 | else | |
4948 | other_giv = tv; | |
4949 | } | |
4950 | if (! tv && other_giv | |
43243872 | 4951 | && REGNO (other_giv->dest_reg) < max_reg_before_loop |
b1f21e0a | 4952 | && (REGNO_LAST_UID (REGNO (other_giv->dest_reg)) |
8516af93 JW |
4953 | == INSN_UID (v->insn)) |
4954 | && INSN_LUID (v->insn) < INSN_LUID (bl->biv->insn)) | |
4955 | auto_inc_opt = 1; | |
4956 | } | |
38e01259 | 4957 | /* Check for case where increment is before the address |
72b0c616 RK |
4958 | giv. Do this test in "loop order". */ |
4959 | else if ((INSN_LUID (v->insn) > INSN_LUID (bl->biv->insn) | |
a2be868f | 4960 | && (INSN_LUID (v->insn) < INSN_LUID (loop_scan_start) |
72b0c616 | 4961 | || (INSN_LUID (bl->biv->insn) |
a2be868f MH |
4962 | > INSN_LUID (loop_scan_start)))) |
4963 | || (INSN_LUID (v->insn) < INSN_LUID (loop_scan_start) | |
4964 | && (INSN_LUID (loop_scan_start) | |
72b0c616 | 4965 | < INSN_LUID (bl->biv->insn)))) |
8516af93 JW |
4966 | auto_inc_opt = -1; |
4967 | else | |
4968 | auto_inc_opt = 1; | |
4969 | ||
bb91b814 | 4970 | #ifdef HAVE_cc0 |
a7a4457e DE |
4971 | { |
4972 | rtx prev; | |
4973 | ||
4974 | /* We can't put an insn immediately after one setting | |
4975 | cc0, or immediately before one using cc0. */ | |
4976 | if ((auto_inc_opt == 1 && sets_cc0_p (PATTERN (v->insn))) | |
4977 | || (auto_inc_opt == -1 | |
4978 | && (prev = prev_nonnote_insn (v->insn)) != 0 | |
4979 | && GET_RTX_CLASS (GET_CODE (prev)) == 'i' | |
4980 | && sets_cc0_p (PATTERN (prev)))) | |
4981 | auto_inc_opt = 0; | |
4982 | } | |
bb91b814 JW |
4983 | #endif |
4984 | ||
8516af93 JW |
4985 | if (auto_inc_opt) |
4986 | v->auto_inc_opt = 1; | |
4987 | } | |
4988 | #endif | |
4989 | ||
4990 | /* For each place where the biv is incremented, add an insn | |
4991 | to increment the new, reduced reg for the giv. */ | |
b4ad7b23 RS |
4992 | for (tv = bl->biv; tv; tv = tv->next_iv) |
4993 | { | |
8516af93 JW |
4994 | rtx insert_before; |
4995 | ||
4996 | if (! auto_inc_opt) | |
4997 | insert_before = tv->insn; | |
4998 | else if (auto_inc_opt == 1) | |
4999 | insert_before = NEXT_INSN (v->insn); | |
5000 | else | |
5001 | insert_before = v->insn; | |
5002 | ||
b4ad7b23 RS |
5003 | if (tv->mult_val == const1_rtx) |
5004 | emit_iv_add_mult (tv->add_val, v->mult_val, | |
8516af93 | 5005 | v->new_reg, v->new_reg, insert_before); |
b4ad7b23 RS |
5006 | else /* tv->mult_val == const0_rtx */ |
5007 | /* A multiply is acceptable here | |
5008 | since this is presumed to be seldom executed. */ | |
5009 | emit_iv_add_mult (tv->add_val, v->mult_val, | |
8516af93 | 5010 | v->add_val, v->new_reg, insert_before); |
b4ad7b23 RS |
5011 | } |
5012 | ||
5013 | /* Add code at loop start to initialize giv's reduced reg. */ | |
5014 | ||
5015 | emit_iv_add_mult (bl->initial_value, v->mult_val, | |
5016 | v->add_val, v->new_reg, loop_start); | |
5017 | } | |
5018 | } | |
5019 | ||
5020 | /* Rescan all givs. If a giv is the same as a giv not reduced, mark it | |
5021 | as not reduced. | |
5022 | ||
5023 | For each giv register that can be reduced now: if replaceable, | |
5024 | substitute reduced reg wherever the old giv occurs; | |
8c354a41 | 5025 | else add new move insn "giv_reg = reduced_reg". */ |
b4ad7b23 | 5026 | |
b4ad7b23 RS |
5027 | for (v = bl->giv; v; v = v->next_iv) |
5028 | { | |
5029 | if (v->same && v->same->ignore) | |
5030 | v->ignore = 1; | |
5031 | ||
5032 | if (v->ignore) | |
5033 | continue; | |
5034 | ||
b4ad7b23 RS |
5035 | /* Update expression if this was combined, in case other giv was |
5036 | replaced. */ | |
5037 | if (v->same) | |
5038 | v->new_reg = replace_rtx (v->new_reg, | |
5039 | v->same->dest_reg, v->same->new_reg); | |
5040 | ||
5041 | if (v->giv_type == DEST_ADDR) | |
5042 | /* Store reduced reg as the address in the memref where we found | |
5043 | this giv. */ | |
9abdca9c | 5044 | validate_change (v->insn, v->location, v->new_reg, 0); |
b4ad7b23 RS |
5045 | else if (v->replaceable) |
5046 | { | |
5047 | reg_map[REGNO (v->dest_reg)] = v->new_reg; | |
5048 | ||
5049 | #if 0 | |
5050 | /* I can no longer duplicate the original problem. Perhaps | |
5051 | this is unnecessary now? */ | |
5052 | ||
5053 | /* Replaceable; it isn't strictly necessary to delete the old | |
5054 | insn and emit a new one, because v->dest_reg is now dead. | |
5055 | ||
5056 | However, especially when unrolling loops, the special | |
5057 | handling for (set REG0 REG1) in the second cse pass may | |
5058 | make v->dest_reg live again. To avoid this problem, emit | |
5059 | an insn to set the original giv reg from the reduced giv. | |
5060 | We can not delete the original insn, since it may be part | |
5061 | of a LIBCALL, and the code in flow that eliminates dead | |
5062 | libcalls will fail if it is deleted. */ | |
5063 | emit_insn_after (gen_move_insn (v->dest_reg, v->new_reg), | |
5064 | v->insn); | |
5065 | #endif | |
5066 | } | |
5067 | else | |
5068 | { | |
5069 | /* Not replaceable; emit an insn to set the original giv reg from | |
5070 | the reduced giv, same as above. */ | |
5071 | emit_insn_after (gen_move_insn (v->dest_reg, v->new_reg), | |
5072 | v->insn); | |
5073 | } | |
5074 | ||
5075 | /* When a loop is reversed, givs which depend on the reversed | |
5076 | biv, and which are live outside the loop, must be set to their | |
5077 | correct final value. This insn is only needed if the giv is | |
5078 | not replaceable. The correct final value is the same as the | |
5079 | value that the giv starts the reversed loop with. */ | |
5080 | if (bl->reversed && ! v->replaceable) | |
5081 | emit_iv_add_mult (bl->initial_value, v->mult_val, | |
5082 | v->add_val, v->dest_reg, end_insert_before); | |
5083 | else if (v->final_value) | |
5084 | { | |
5085 | rtx insert_before; | |
5086 | ||
5087 | /* If the loop has multiple exits, emit the insn before the | |
5088 | loop to ensure that it will always be executed no matter | |
5089 | how the loop exits. Otherwise, emit the insn after the loop, | |
5090 | since this is slightly more efficient. */ | |
a2be868f | 5091 | if (uid_loop[INSN_UID (loop_start)]->exit_count) |
b4ad7b23 RS |
5092 | insert_before = loop_start; |
5093 | else | |
5094 | insert_before = end_insert_before; | |
5095 | emit_insn_before (gen_move_insn (v->dest_reg, v->final_value), | |
5096 | insert_before); | |
5097 | ||
5098 | #if 0 | |
5099 | /* If the insn to set the final value of the giv was emitted | |
5100 | before the loop, then we must delete the insn inside the loop | |
5101 | that sets it. If this is a LIBCALL, then we must delete | |
5102 | every insn in the libcall. Note, however, that | |
5103 | final_giv_value will only succeed when there are multiple | |
5104 | exits if the giv is dead at each exit, hence it does not | |
5105 | matter that the original insn remains because it is dead | |
5106 | anyways. */ | |
5107 | /* Delete the insn inside the loop that sets the giv since | |
5108 | the giv is now set before (or after) the loop. */ | |
5109 | delete_insn (v->insn); | |
5110 | #endif | |
5111 | } | |
5112 | ||
5113 | if (loop_dump_stream) | |
5114 | { | |
5115 | fprintf (loop_dump_stream, "giv at %d reduced to ", | |
5116 | INSN_UID (v->insn)); | |
5117 | print_rtl (loop_dump_stream, v->new_reg); | |
5118 | fprintf (loop_dump_stream, "\n"); | |
5119 | } | |
5120 | } | |
5121 | ||
5122 | /* All the givs based on the biv bl have been reduced if they | |
5123 | merit it. */ | |
5124 | ||
5125 | /* For each giv not marked as maybe dead that has been combined with a | |
5126 | second giv, clear any "maybe dead" mark on that second giv. | |
5127 | v->new_reg will either be or refer to the register of the giv it | |
5128 | combined with. | |
5129 | ||
5130 | Doing this clearing avoids problems in biv elimination where a | |
5131 | giv's new_reg is a complex value that can't be put in the insn but | |
5132 | the giv combined with (with a reg as new_reg) is marked maybe_dead. | |
5133 | Since the register will be used in either case, we'd prefer it be | |
5134 | used from the simpler giv. */ | |
5135 | ||
5136 | for (v = bl->giv; v; v = v->next_iv) | |
5137 | if (! v->maybe_dead && v->same) | |
5138 | v->same->maybe_dead = 0; | |
5139 | ||
5140 | /* Try to eliminate the biv, if it is a candidate. | |
5141 | This won't work if ! all_reduced, | |
5142 | since the givs we planned to use might not have been reduced. | |
5143 | ||
d45cf215 | 5144 | We have to be careful that we didn't initially think we could eliminate |
b4ad7b23 RS |
5145 | this biv because of a giv that we now think may be dead and shouldn't |
5146 | be used as a biv replacement. | |
5147 | ||
5148 | Also, there is the possibility that we may have a giv that looks | |
5149 | like it can be used to eliminate a biv, but the resulting insn | |
5150 | isn't valid. This can happen, for example, on the 88k, where a | |
5151 | JUMP_INSN can compare a register only with zero. Attempts to | |
c5b7917e | 5152 | replace it with a compare with a constant will fail. |
b4ad7b23 RS |
5153 | |
5154 | Note that in cases where this call fails, we may have replaced some | |
5155 | of the occurrences of the biv with a giv, but no harm was done in | |
5156 | doing so in the rare cases where it can occur. */ | |
5157 | ||
5158 | if (all_reduced == 1 && bl->eliminable | |
a2be868f | 5159 | && maybe_eliminate_biv (bl, loop_start, loop_end, 1, |
b4ad7b23 RS |
5160 | threshold, insn_count)) |
5161 | ||
5162 | { | |
5163 | /* ?? If we created a new test to bypass the loop entirely, | |
5164 | or otherwise drop straight in, based on this test, then | |
5165 | we might want to rewrite it also. This way some later | |
5166 | pass has more hope of removing the initialization of this | |
0f41302f | 5167 | biv entirely. */ |
b4ad7b23 RS |
5168 | |
5169 | /* If final_value != 0, then the biv may be used after loop end | |
5170 | and we must emit an insn to set it just in case. | |
5171 | ||
5172 | Reversed bivs already have an insn after the loop setting their | |
5173 | value, so we don't need another one. We can't calculate the | |
0f41302f | 5174 | proper final value for such a biv here anyways. */ |
b4ad7b23 RS |
5175 | if (final_value != 0 && ! bl->reversed) |
5176 | { | |
5177 | rtx insert_before; | |
5178 | ||
5179 | /* If the loop has multiple exits, emit the insn before the | |
5180 | loop to ensure that it will always be executed no matter | |
5181 | how the loop exits. Otherwise, emit the insn after the | |
5182 | loop, since this is slightly more efficient. */ | |
a2be868f | 5183 | if (uid_loop[INSN_UID (loop_start)]->exit_count) |
b4ad7b23 RS |
5184 | insert_before = loop_start; |
5185 | else | |
5186 | insert_before = end_insert_before; | |
5187 | ||
5188 | emit_insn_before (gen_move_insn (bl->biv->dest_reg, final_value), | |
5189 | end_insert_before); | |
5190 | } | |
5191 | ||
5192 | #if 0 | |
5193 | /* Delete all of the instructions inside the loop which set | |
5194 | the biv, as they are all dead. If is safe to delete them, | |
5195 | because an insn setting a biv will never be part of a libcall. */ | |
5196 | /* However, deleting them will invalidate the regno_last_uid info, | |
5197 | so keeping them around is more convenient. Final_biv_value | |
5198 | will only succeed when there are multiple exits if the biv | |
5199 | is dead at each exit, hence it does not matter that the original | |
5200 | insn remains, because it is dead anyways. */ | |
5201 | for (v = bl->biv; v; v = v->next_iv) | |
5202 | delete_insn (v->insn); | |
5203 | #endif | |
5204 | ||
5205 | if (loop_dump_stream) | |
5206 | fprintf (loop_dump_stream, "Reg %d: biv eliminated\n", | |
5207 | bl->regno); | |
5208 | } | |
5209 | } | |
5210 | ||
5211 | /* Go through all the instructions in the loop, making all the | |
5212 | register substitutions scheduled in REG_MAP. */ | |
5213 | ||
a2be868f | 5214 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) |
b4ad7b23 RS |
5215 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN |
5216 | || GET_CODE (p) == CALL_INSN) | |
5217 | { | |
97ec0ad8 R |
5218 | replace_regs (PATTERN (p), reg_map, reg_map_size, 0); |
5219 | replace_regs (REG_NOTES (p), reg_map, reg_map_size, 0); | |
da0c128e | 5220 | INSN_CODE (p) = -1; |
b4ad7b23 RS |
5221 | } |
5222 | ||
73049ebc MT |
5223 | if (loop_info->n_iterations > 0) |
5224 | { | |
5225 | /* When we completely unroll a loop we will likely not need the increment | |
5226 | of the loop BIV and we will not need the conditional branch at the | |
5227 | end of the loop. */ | |
5228 | unrolled_insn_copies = insn_count - 2; | |
5229 | ||
5230 | #ifdef HAVE_cc0 | |
5231 | /* When we completely unroll a loop on a HAVE_cc0 machine we will not | |
5232 | need the comparison before the conditional branch at the end of the | |
5233 | loop. */ | |
80b8e8de | 5234 | unrolled_insn_copies -= 1; |
73049ebc MT |
5235 | #endif |
5236 | ||
5237 | /* We'll need one copy for each loop iteration. */ | |
5238 | unrolled_insn_copies *= loop_info->n_iterations; | |
5239 | ||
5240 | /* A little slop to account for the ability to remove initialization | |
5241 | code, better CSE, and other secondary benefits of completely | |
5242 | unrolling some loops. */ | |
5243 | unrolled_insn_copies -= 1; | |
5244 | ||
5245 | /* Clamp the value. */ | |
5246 | if (unrolled_insn_copies < 0) | |
5247 | unrolled_insn_copies = 0; | |
5248 | } | |
5249 | ||
b4ad7b23 RS |
5250 | /* Unroll loops from within strength reduction so that we can use the |
5251 | induction variable information that strength_reduce has already | |
73049ebc MT |
5252 | collected. Always unroll loops that would be as small or smaller |
5253 | unrolled than when rolled. */ | |
5254 | if (unroll_p | |
5255 | || (loop_info->n_iterations > 0 | |
5256 | && unrolled_insn_copies <= insn_count)) | |
a2be868f | 5257 | unroll_loop (loop, insn_count, end_insert_before, 1); |
b4ad7b23 | 5258 | |
8c660648 | 5259 | #ifdef HAVE_decrement_and_branch_on_count |
cac8ce95 DE |
5260 | /* Instrument the loop with BCT insn. */ |
5261 | if (HAVE_decrement_and_branch_on_count && bct_p | |
5262 | && flag_branch_on_count_reg) | |
a2be868f | 5263 | insert_bct (loop); |
cac8ce95 | 5264 | #endif /* HAVE_decrement_and_branch_on_count */ |
8c660648 | 5265 | |
b4ad7b23 RS |
5266 | if (loop_dump_stream) |
5267 | fprintf (loop_dump_stream, "\n"); | |
69ba6af3 RH |
5268 | |
5269 | egress: | |
3ec2b590 R |
5270 | VARRAY_FREE (reg_iv_type); |
5271 | VARRAY_FREE (reg_iv_info); | |
4da896b2 MM |
5272 | free (reg_biv_class); |
5273 | if (reg_map) | |
5274 | free (reg_map); | |
b4ad7b23 RS |
5275 | } |
5276 | \f | |
5277 | /* Return 1 if X is a valid source for an initial value (or as value being | |
5278 | compared against in an initial test). | |
5279 | ||
5280 | X must be either a register or constant and must not be clobbered between | |
5281 | the current insn and the start of the loop. | |
5282 | ||
5283 | INSN is the insn containing X. */ | |
5284 | ||
5285 | static int | |
5286 | valid_initial_value_p (x, insn, call_seen, loop_start) | |
5287 | rtx x; | |
5288 | rtx insn; | |
5289 | int call_seen; | |
5290 | rtx loop_start; | |
5291 | { | |
5292 | if (CONSTANT_P (x)) | |
5293 | return 1; | |
5294 | ||
d45cf215 | 5295 | /* Only consider pseudos we know about initialized in insns whose luids |
b4ad7b23 RS |
5296 | we know. */ |
5297 | if (GET_CODE (x) != REG | |
5298 | || REGNO (x) >= max_reg_before_loop) | |
5299 | return 0; | |
5300 | ||
5301 | /* Don't use call-clobbered registers across a call which clobbers it. On | |
5302 | some machines, don't use any hard registers at all. */ | |
5303 | if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
e9a25f70 JL |
5304 | && (SMALL_REGISTER_CLASSES |
5305 | || (call_used_regs[REGNO (x)] && call_seen))) | |
b4ad7b23 RS |
5306 | return 0; |
5307 | ||
5308 | /* Don't use registers that have been clobbered before the start of the | |
5309 | loop. */ | |
5310 | if (reg_set_between_p (x, insn, loop_start)) | |
5311 | return 0; | |
5312 | ||
5313 | return 1; | |
5314 | } | |
5315 | \f | |
5316 | /* Scan X for memory refs and check each memory address | |
5317 | as a possible giv. INSN is the insn whose pattern X comes from. | |
5318 | NOT_EVERY_ITERATION is 1 if the insn might not be executed during | |
c5c76735 JL |
5319 | every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed |
5320 | more thanonce in each loop iteration. */ | |
b4ad7b23 RS |
5321 | |
5322 | static void | |
c5c76735 JL |
5323 | find_mem_givs (x, insn, not_every_iteration, maybe_multiple, loop_start, |
5324 | loop_end) | |
b4ad7b23 RS |
5325 | rtx x; |
5326 | rtx insn; | |
c5c76735 | 5327 | int not_every_iteration, maybe_multiple; |
b4ad7b23 RS |
5328 | rtx loop_start, loop_end; |
5329 | { | |
5330 | register int i, j; | |
5331 | register enum rtx_code code; | |
6f7d635c | 5332 | register const char *fmt; |
b4ad7b23 RS |
5333 | |
5334 | if (x == 0) | |
5335 | return; | |
5336 | ||
5337 | code = GET_CODE (x); | |
5338 | switch (code) | |
5339 | { | |
5340 | case REG: | |
5341 | case CONST_INT: | |
5342 | case CONST: | |
5343 | case CONST_DOUBLE: | |
5344 | case SYMBOL_REF: | |
5345 | case LABEL_REF: | |
5346 | case PC: | |
5347 | case CC0: | |
5348 | case ADDR_VEC: | |
5349 | case ADDR_DIFF_VEC: | |
5350 | case USE: | |
5351 | case CLOBBER: | |
5352 | return; | |
5353 | ||
5354 | case MEM: | |
5355 | { | |
5356 | rtx src_reg; | |
5357 | rtx add_val; | |
5358 | rtx mult_val; | |
5359 | int benefit; | |
5360 | ||
45f97e2e RH |
5361 | /* This code used to disable creating GIVs with mult_val == 1 and |
5362 | add_val == 0. However, this leads to lost optimizations when | |
5363 | it comes time to combine a set of related DEST_ADDR GIVs, since | |
5364 | this one would not be seen. */ | |
b4ad7b23 | 5365 | |
45f97e2e RH |
5366 | if (general_induction_var (XEXP (x, 0), &src_reg, &add_val, |
5367 | &mult_val, 1, &benefit)) | |
b4ad7b23 RS |
5368 | { |
5369 | /* Found one; record it. */ | |
5370 | struct induction *v | |
5371 | = (struct induction *) oballoc (sizeof (struct induction)); | |
5372 | ||
5373 | record_giv (v, insn, src_reg, addr_placeholder, mult_val, | |
5374 | add_val, benefit, DEST_ADDR, not_every_iteration, | |
c5c76735 | 5375 | maybe_multiple, &XEXP (x, 0), loop_start, loop_end); |
b4ad7b23 RS |
5376 | |
5377 | v->mem_mode = GET_MODE (x); | |
5378 | } | |
b4ad7b23 | 5379 | } |
e9a25f70 JL |
5380 | return; |
5381 | ||
5382 | default: | |
5383 | break; | |
b4ad7b23 RS |
5384 | } |
5385 | ||
5386 | /* Recursively scan the subexpressions for other mem refs. */ | |
5387 | ||
5388 | fmt = GET_RTX_FORMAT (code); | |
5389 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5390 | if (fmt[i] == 'e') | |
c5c76735 JL |
5391 | find_mem_givs (XEXP (x, i), insn, not_every_iteration, maybe_multiple, |
5392 | loop_start, loop_end); | |
b4ad7b23 RS |
5393 | else if (fmt[i] == 'E') |
5394 | for (j = 0; j < XVECLEN (x, i); j++) | |
5395 | find_mem_givs (XVECEXP (x, i, j), insn, not_every_iteration, | |
c5c76735 | 5396 | maybe_multiple, loop_start, loop_end); |
b4ad7b23 RS |
5397 | } |
5398 | \f | |
5399 | /* Fill in the data about one biv update. | |
5400 | V is the `struct induction' in which we record the biv. (It is | |
5401 | allocated by the caller, with alloca.) | |
5402 | INSN is the insn that sets it. | |
5403 | DEST_REG is the biv's reg. | |
5404 | ||
5405 | MULT_VAL is const1_rtx if the biv is being incremented here, in which case | |
5406 | INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is | |
7dcd3836 RK |
5407 | being set to INC_VAL. |
5408 | ||
5409 | NOT_EVERY_ITERATION is nonzero if this biv update is not know to be | |
5410 | executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update | |
5411 | can be executed more than once per iteration. If MAYBE_MULTIPLE | |
5412 | and NOT_EVERY_ITERATION are both zero, we know that the biv update is | |
5413 | executed exactly once per iteration. */ | |
b4ad7b23 RS |
5414 | |
5415 | static void | |
3ec2b590 | 5416 | record_biv (v, insn, dest_reg, inc_val, mult_val, location, |
60fb6df9 | 5417 | not_every_iteration, maybe_multiple, multi_insn_incr) |
b4ad7b23 RS |
5418 | struct induction *v; |
5419 | rtx insn; | |
5420 | rtx dest_reg; | |
5421 | rtx inc_val; | |
5422 | rtx mult_val; | |
3ec2b590 | 5423 | rtx *location; |
b4ad7b23 | 5424 | int not_every_iteration; |
7dcd3836 | 5425 | int maybe_multiple; |
009fef52 | 5426 | int multi_insn_incr; |
b4ad7b23 RS |
5427 | { |
5428 | struct iv_class *bl; | |
5429 | ||
5430 | v->insn = insn; | |
5431 | v->src_reg = dest_reg; | |
5432 | v->dest_reg = dest_reg; | |
5433 | v->mult_val = mult_val; | |
5434 | v->add_val = inc_val; | |
3ec2b590 | 5435 | v->location = location; |
b4ad7b23 RS |
5436 | v->mode = GET_MODE (dest_reg); |
5437 | v->always_computable = ! not_every_iteration; | |
8516af93 | 5438 | v->always_executed = ! not_every_iteration; |
7dcd3836 | 5439 | v->maybe_multiple = maybe_multiple; |
60fb6df9 | 5440 | v->multi_insn_incr = multi_insn_incr; |
b4ad7b23 RS |
5441 | |
5442 | /* Add this to the reg's iv_class, creating a class | |
5443 | if this is the first incrementation of the reg. */ | |
5444 | ||
5445 | bl = reg_biv_class[REGNO (dest_reg)]; | |
5446 | if (bl == 0) | |
5447 | { | |
5448 | /* Create and initialize new iv_class. */ | |
5449 | ||
5450 | bl = (struct iv_class *) oballoc (sizeof (struct iv_class)); | |
5451 | ||
5452 | bl->regno = REGNO (dest_reg); | |
5453 | bl->biv = 0; | |
5454 | bl->giv = 0; | |
5455 | bl->biv_count = 0; | |
5456 | bl->giv_count = 0; | |
5457 | ||
5458 | /* Set initial value to the reg itself. */ | |
5459 | bl->initial_value = dest_reg; | |
c5b7917e | 5460 | /* We haven't seen the initializing insn yet */ |
b4ad7b23 RS |
5461 | bl->init_insn = 0; |
5462 | bl->init_set = 0; | |
5463 | bl->initial_test = 0; | |
5464 | bl->incremented = 0; | |
5465 | bl->eliminable = 0; | |
5466 | bl->nonneg = 0; | |
5467 | bl->reversed = 0; | |
b5d27be7 | 5468 | bl->total_benefit = 0; |
b4ad7b23 RS |
5469 | |
5470 | /* Add this class to loop_iv_list. */ | |
5471 | bl->next = loop_iv_list; | |
5472 | loop_iv_list = bl; | |
5473 | ||
5474 | /* Put it in the array of biv register classes. */ | |
5475 | reg_biv_class[REGNO (dest_reg)] = bl; | |
5476 | } | |
5477 | ||
5478 | /* Update IV_CLASS entry for this biv. */ | |
5479 | v->next_iv = bl->biv; | |
5480 | bl->biv = v; | |
5481 | bl->biv_count++; | |
5482 | if (mult_val == const1_rtx) | |
5483 | bl->incremented = 1; | |
5484 | ||
5485 | if (loop_dump_stream) | |
5486 | { | |
5487 | fprintf (loop_dump_stream, | |
5488 | "Insn %d: possible biv, reg %d,", | |
5489 | INSN_UID (insn), REGNO (dest_reg)); | |
5490 | if (GET_CODE (inc_val) == CONST_INT) | |
9ba7a303 JC |
5491 | { |
5492 | fprintf (loop_dump_stream, " const ="); | |
5493 | fprintf (loop_dump_stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (inc_val)); | |
5494 | fputc ('\n', loop_dump_stream); | |
5495 | } | |
b4ad7b23 RS |
5496 | else |
5497 | { | |
5498 | fprintf (loop_dump_stream, " const = "); | |
5499 | print_rtl (loop_dump_stream, inc_val); | |
5500 | fprintf (loop_dump_stream, "\n"); | |
5501 | } | |
5502 | } | |
5503 | } | |
5504 | \f | |
5505 | /* Fill in the data about one giv. | |
5506 | V is the `struct induction' in which we record the giv. (It is | |
5507 | allocated by the caller, with alloca.) | |
5508 | INSN is the insn that sets it. | |
5509 | BENEFIT estimates the savings from deleting this insn. | |
5510 | TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed | |
5511 | into a register or is used as a memory address. | |
5512 | ||
5513 | SRC_REG is the biv reg which the giv is computed from. | |
5514 | DEST_REG is the giv's reg (if the giv is stored in a reg). | |
5515 | MULT_VAL and ADD_VAL are the coefficients used to compute the giv. | |
5516 | LOCATION points to the place where this giv's value appears in INSN. */ | |
5517 | ||
5518 | static void | |
5519 | record_giv (v, insn, src_reg, dest_reg, mult_val, add_val, benefit, | |
c5c76735 JL |
5520 | type, not_every_iteration, maybe_multiple, location, loop_start, |
5521 | loop_end) | |
b4ad7b23 RS |
5522 | struct induction *v; |
5523 | rtx insn; | |
5524 | rtx src_reg; | |
5525 | rtx dest_reg; | |
5526 | rtx mult_val, add_val; | |
5527 | int benefit; | |
5528 | enum g_types type; | |
c5c76735 | 5529 | int not_every_iteration, maybe_multiple; |
b4ad7b23 RS |
5530 | rtx *location; |
5531 | rtx loop_start, loop_end; | |
5532 | { | |
5533 | struct induction *b; | |
5534 | struct iv_class *bl; | |
5535 | rtx set = single_set (insn); | |
b4ad7b23 RS |
5536 | |
5537 | v->insn = insn; | |
5538 | v->src_reg = src_reg; | |
5539 | v->giv_type = type; | |
5540 | v->dest_reg = dest_reg; | |
5541 | v->mult_val = mult_val; | |
5542 | v->add_val = add_val; | |
5543 | v->benefit = benefit; | |
5544 | v->location = location; | |
5545 | v->cant_derive = 0; | |
5546 | v->combined_with = 0; | |
c5c76735 | 5547 | v->maybe_multiple = maybe_multiple; |
60fb6df9 | 5548 | v->multi_insn_incr = 0; |
b4ad7b23 RS |
5549 | v->maybe_dead = 0; |
5550 | v->derive_adjustment = 0; | |
5551 | v->same = 0; | |
5552 | v->ignore = 0; | |
5553 | v->new_reg = 0; | |
5554 | v->final_value = 0; | |
f415f7be | 5555 | v->same_insn = 0; |
8516af93 | 5556 | v->auto_inc_opt = 0; |
9ae8ffe7 JL |
5557 | v->unrolled = 0; |
5558 | v->shared = 0; | |
4d87f7a7 | 5559 | v->derived_from = 0; |
3ec2b590 | 5560 | v->last_use = 0; |
b4ad7b23 RS |
5561 | |
5562 | /* The v->always_computable field is used in update_giv_derive, to | |
5563 | determine whether a giv can be used to derive another giv. For a | |
5564 | DEST_REG giv, INSN computes a new value for the giv, so its value | |
5565 | isn't computable if INSN insn't executed every iteration. | |
5566 | However, for a DEST_ADDR giv, INSN merely uses the value of the giv; | |
5567 | it does not compute a new value. Hence the value is always computable | |
d45cf215 | 5568 | regardless of whether INSN is executed each iteration. */ |
b4ad7b23 RS |
5569 | |
5570 | if (type == DEST_ADDR) | |
5571 | v->always_computable = 1; | |
5572 | else | |
5573 | v->always_computable = ! not_every_iteration; | |
5574 | ||
8516af93 JW |
5575 | v->always_executed = ! not_every_iteration; |
5576 | ||
b4ad7b23 RS |
5577 | if (type == DEST_ADDR) |
5578 | { | |
5579 | v->mode = GET_MODE (*location); | |
5580 | v->lifetime = 1; | |
b4ad7b23 RS |
5581 | } |
5582 | else /* type == DEST_REG */ | |
5583 | { | |
5584 | v->mode = GET_MODE (SET_DEST (set)); | |
5585 | ||
b1f21e0a MM |
5586 | v->lifetime = (uid_luid[REGNO_LAST_UID (REGNO (dest_reg))] |
5587 | - uid_luid[REGNO_FIRST_UID (REGNO (dest_reg))]); | |
b4ad7b23 | 5588 | |
b4ad7b23 RS |
5589 | /* If the lifetime is zero, it means that this register is |
5590 | really a dead store. So mark this as a giv that can be | |
0f41302f | 5591 | ignored. This will not prevent the biv from being eliminated. */ |
b4ad7b23 RS |
5592 | if (v->lifetime == 0) |
5593 | v->ignore = 1; | |
5594 | ||
3ec2b590 R |
5595 | REG_IV_TYPE (REGNO (dest_reg)) = GENERAL_INDUCT; |
5596 | REG_IV_INFO (REGNO (dest_reg)) = v; | |
b4ad7b23 RS |
5597 | } |
5598 | ||
5599 | /* Add the giv to the class of givs computed from one biv. */ | |
5600 | ||
5601 | bl = reg_biv_class[REGNO (src_reg)]; | |
5602 | if (bl) | |
5603 | { | |
5604 | v->next_iv = bl->giv; | |
5605 | bl->giv = v; | |
5606 | /* Don't count DEST_ADDR. This is supposed to count the number of | |
5607 | insns that calculate givs. */ | |
5608 | if (type == DEST_REG) | |
5609 | bl->giv_count++; | |
5610 | bl->total_benefit += benefit; | |
5611 | } | |
5612 | else | |
5613 | /* Fatal error, biv missing for this giv? */ | |
5614 | abort (); | |
5615 | ||
5616 | if (type == DEST_ADDR) | |
5617 | v->replaceable = 1; | |
5618 | else | |
5619 | { | |
5620 | /* The giv can be replaced outright by the reduced register only if all | |
5621 | of the following conditions are true: | |
5622 | - the insn that sets the giv is always executed on any iteration | |
5623 | on which the giv is used at all | |
5624 | (there are two ways to deduce this: | |
5625 | either the insn is executed on every iteration, | |
5626 | or all uses follow that insn in the same basic block), | |
5627 | - the giv is not used outside the loop | |
5628 | - no assignments to the biv occur during the giv's lifetime. */ | |
5629 | ||
b1f21e0a | 5630 | if (REGNO_FIRST_UID (REGNO (dest_reg)) == INSN_UID (insn) |
b4ad7b23 | 5631 | /* Previous line always fails if INSN was moved by loop opt. */ |
b1f21e0a | 5632 | && uid_luid[REGNO_LAST_UID (REGNO (dest_reg))] < INSN_LUID (loop_end) |
b4ad7b23 RS |
5633 | && (! not_every_iteration |
5634 | || last_use_this_basic_block (dest_reg, insn))) | |
5635 | { | |
5636 | /* Now check that there are no assignments to the biv within the | |
5637 | giv's lifetime. This requires two separate checks. */ | |
5638 | ||
5639 | /* Check each biv update, and fail if any are between the first | |
5640 | and last use of the giv. | |
5641 | ||
5642 | If this loop contains an inner loop that was unrolled, then | |
5643 | the insn modifying the biv may have been emitted by the loop | |
5644 | unrolling code, and hence does not have a valid luid. Just | |
5645 | mark the biv as not replaceable in this case. It is not very | |
5646 | useful as a biv, because it is used in two different loops. | |
5647 | It is very unlikely that we would be able to optimize the giv | |
5648 | using this biv anyways. */ | |
5649 | ||
5650 | v->replaceable = 1; | |
5651 | for (b = bl->biv; b; b = b->next_iv) | |
5652 | { | |
5653 | if (INSN_UID (b->insn) >= max_uid_for_loop | |
5654 | || ((uid_luid[INSN_UID (b->insn)] | |
b1f21e0a | 5655 | >= uid_luid[REGNO_FIRST_UID (REGNO (dest_reg))]) |
b4ad7b23 | 5656 | && (uid_luid[INSN_UID (b->insn)] |
b1f21e0a | 5657 | <= uid_luid[REGNO_LAST_UID (REGNO (dest_reg))]))) |
b4ad7b23 RS |
5658 | { |
5659 | v->replaceable = 0; | |
5660 | v->not_replaceable = 1; | |
5661 | break; | |
5662 | } | |
5663 | } | |
5664 | ||
5031afa7 JW |
5665 | /* If there are any backwards branches that go from after the |
5666 | biv update to before it, then this giv is not replaceable. */ | |
b4ad7b23 | 5667 | if (v->replaceable) |
5031afa7 JW |
5668 | for (b = bl->biv; b; b = b->next_iv) |
5669 | if (back_branch_in_range_p (b->insn, loop_start, loop_end)) | |
5670 | { | |
5671 | v->replaceable = 0; | |
5672 | v->not_replaceable = 1; | |
5673 | break; | |
5674 | } | |
b4ad7b23 RS |
5675 | } |
5676 | else | |
5677 | { | |
5678 | /* May still be replaceable, we don't have enough info here to | |
5679 | decide. */ | |
5680 | v->replaceable = 0; | |
5681 | v->not_replaceable = 0; | |
5682 | } | |
5683 | } | |
5684 | ||
45f97e2e RH |
5685 | /* Record whether the add_val contains a const_int, for later use by |
5686 | combine_givs. */ | |
5687 | { | |
5688 | rtx tem = add_val; | |
5689 | ||
5690 | v->no_const_addval = 1; | |
5691 | if (tem == const0_rtx) | |
5692 | ; | |
5693 | else if (GET_CODE (tem) == CONST_INT) | |
5694 | v->no_const_addval = 0; | |
5695 | else if (GET_CODE (tem) == PLUS) | |
5696 | { | |
5697 | while (1) | |
5698 | { | |
5699 | if (GET_CODE (XEXP (tem, 0)) == PLUS) | |
5700 | tem = XEXP (tem, 0); | |
5701 | else if (GET_CODE (XEXP (tem, 1)) == PLUS) | |
5702 | tem = XEXP (tem, 1); | |
5703 | else | |
5704 | break; | |
5705 | } | |
5706 | if (GET_CODE (XEXP (tem, 1)) == CONST_INT) | |
5707 | v->no_const_addval = 0; | |
5708 | } | |
5709 | } | |
5710 | ||
b4ad7b23 RS |
5711 | if (loop_dump_stream) |
5712 | { | |
5713 | if (type == DEST_REG) | |
5714 | fprintf (loop_dump_stream, "Insn %d: giv reg %d", | |
5715 | INSN_UID (insn), REGNO (dest_reg)); | |
5716 | else | |
5717 | fprintf (loop_dump_stream, "Insn %d: dest address", | |
5718 | INSN_UID (insn)); | |
5719 | ||
5720 | fprintf (loop_dump_stream, " src reg %d benefit %d", | |
5721 | REGNO (src_reg), v->benefit); | |
4b259e3f R |
5722 | fprintf (loop_dump_stream, " lifetime %d", |
5723 | v->lifetime); | |
b4ad7b23 RS |
5724 | |
5725 | if (v->replaceable) | |
5726 | fprintf (loop_dump_stream, " replaceable"); | |
5727 | ||
45f97e2e RH |
5728 | if (v->no_const_addval) |
5729 | fprintf (loop_dump_stream, " ncav"); | |
5730 | ||
b4ad7b23 | 5731 | if (GET_CODE (mult_val) == CONST_INT) |
9ba7a303 JC |
5732 | { |
5733 | fprintf (loop_dump_stream, " mult "); | |
5734 | fprintf (loop_dump_stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (mult_val)); | |
5735 | } | |
b4ad7b23 RS |
5736 | else |
5737 | { | |
5738 | fprintf (loop_dump_stream, " mult "); | |
5739 | print_rtl (loop_dump_stream, mult_val); | |
5740 | } | |
5741 | ||
5742 | if (GET_CODE (add_val) == CONST_INT) | |
9ba7a303 JC |
5743 | { |
5744 | fprintf (loop_dump_stream, " add "); | |
5745 | fprintf (loop_dump_stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (add_val)); | |
5746 | } | |
b4ad7b23 RS |
5747 | else |
5748 | { | |
5749 | fprintf (loop_dump_stream, " add "); | |
5750 | print_rtl (loop_dump_stream, add_val); | |
5751 | } | |
5752 | } | |
5753 | ||
5754 | if (loop_dump_stream) | |
5755 | fprintf (loop_dump_stream, "\n"); | |
5756 | ||
5757 | } | |
5758 | ||
5759 | ||
5760 | /* All this does is determine whether a giv can be made replaceable because | |
5761 | its final value can be calculated. This code can not be part of record_giv | |
5762 | above, because final_giv_value requires that the number of loop iterations | |
5763 | be known, and that can not be accurately calculated until after all givs | |
5764 | have been identified. */ | |
5765 | ||
5766 | static void | |
302670f3 | 5767 | check_final_value (v, loop_start, loop_end, n_iterations) |
b4ad7b23 RS |
5768 | struct induction *v; |
5769 | rtx loop_start, loop_end; | |
302670f3 | 5770 | unsigned HOST_WIDE_INT n_iterations; |
b4ad7b23 RS |
5771 | { |
5772 | struct iv_class *bl; | |
5773 | rtx final_value = 0; | |
b4ad7b23 RS |
5774 | |
5775 | bl = reg_biv_class[REGNO (v->src_reg)]; | |
5776 | ||
5777 | /* DEST_ADDR givs will never reach here, because they are always marked | |
5778 | replaceable above in record_giv. */ | |
5779 | ||
5780 | /* The giv can be replaced outright by the reduced register only if all | |
5781 | of the following conditions are true: | |
5782 | - the insn that sets the giv is always executed on any iteration | |
5783 | on which the giv is used at all | |
5784 | (there are two ways to deduce this: | |
5785 | either the insn is executed on every iteration, | |
5786 | or all uses follow that insn in the same basic block), | |
5787 | - its final value can be calculated (this condition is different | |
5788 | than the one above in record_giv) | |
5789 | - no assignments to the biv occur during the giv's lifetime. */ | |
5790 | ||
5791 | #if 0 | |
5792 | /* This is only called now when replaceable is known to be false. */ | |
5793 | /* Clear replaceable, so that it won't confuse final_giv_value. */ | |
5794 | v->replaceable = 0; | |
5795 | #endif | |
5796 | ||
302670f3 | 5797 | if ((final_value = final_giv_value (v, loop_start, loop_end, n_iterations)) |
b4ad7b23 RS |
5798 | && (v->always_computable || last_use_this_basic_block (v->dest_reg, v->insn))) |
5799 | { | |
5800 | int biv_increment_seen = 0; | |
5801 | rtx p = v->insn; | |
5802 | rtx last_giv_use; | |
5803 | ||
5804 | v->replaceable = 1; | |
5805 | ||
5806 | /* When trying to determine whether or not a biv increment occurs | |
5807 | during the lifetime of the giv, we can ignore uses of the variable | |
5808 | outside the loop because final_value is true. Hence we can not | |
5809 | use regno_last_uid and regno_first_uid as above in record_giv. */ | |
5810 | ||
5811 | /* Search the loop to determine whether any assignments to the | |
5812 | biv occur during the giv's lifetime. Start with the insn | |
5813 | that sets the giv, and search around the loop until we come | |
5814 | back to that insn again. | |
5815 | ||
5816 | Also fail if there is a jump within the giv's lifetime that jumps | |
5817 | to somewhere outside the lifetime but still within the loop. This | |
5818 | catches spaghetti code where the execution order is not linear, and | |
5819 | hence the above test fails. Here we assume that the giv lifetime | |
5820 | does not extend from one iteration of the loop to the next, so as | |
5821 | to make the test easier. Since the lifetime isn't known yet, | |
5822 | this requires two loops. See also record_giv above. */ | |
5823 | ||
5824 | last_giv_use = v->insn; | |
5825 | ||
5826 | while (1) | |
5827 | { | |
5828 | p = NEXT_INSN (p); | |
5829 | if (p == loop_end) | |
5830 | p = NEXT_INSN (loop_start); | |
5831 | if (p == v->insn) | |
5832 | break; | |
5833 | ||
5834 | if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN | |
5835 | || GET_CODE (p) == CALL_INSN) | |
5836 | { | |
5837 | if (biv_increment_seen) | |
5838 | { | |
5839 | if (reg_mentioned_p (v->dest_reg, PATTERN (p))) | |
5840 | { | |
5841 | v->replaceable = 0; | |
5842 | v->not_replaceable = 1; | |
5843 | break; | |
5844 | } | |
5845 | } | |
c5da853f | 5846 | else if (reg_set_p (v->src_reg, PATTERN (p))) |
b4ad7b23 RS |
5847 | biv_increment_seen = 1; |
5848 | else if (reg_mentioned_p (v->dest_reg, PATTERN (p))) | |
5849 | last_giv_use = p; | |
5850 | } | |
5851 | } | |
5852 | ||
5853 | /* Now that the lifetime of the giv is known, check for branches | |
5854 | from within the lifetime to outside the lifetime if it is still | |
5855 | replaceable. */ | |
5856 | ||
5857 | if (v->replaceable) | |
5858 | { | |
5859 | p = v->insn; | |
5860 | while (1) | |
5861 | { | |
5862 | p = NEXT_INSN (p); | |
5863 | if (p == loop_end) | |
5864 | p = NEXT_INSN (loop_start); | |
5865 | if (p == last_giv_use) | |
5866 | break; | |
5867 | ||
5868 | if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) | |
5869 | && LABEL_NAME (JUMP_LABEL (p)) | |
1cb1fe66 R |
5870 | && ((loop_insn_first_p (JUMP_LABEL (p), v->insn) |
5871 | && loop_insn_first_p (loop_start, JUMP_LABEL (p))) | |
5872 | || (loop_insn_first_p (last_giv_use, JUMP_LABEL (p)) | |
5873 | && loop_insn_first_p (JUMP_LABEL (p), loop_end)))) | |
b4ad7b23 RS |
5874 | { |
5875 | v->replaceable = 0; | |
5876 | v->not_replaceable = 1; | |
5877 | ||
5878 | if (loop_dump_stream) | |
5879 | fprintf (loop_dump_stream, | |
5880 | "Found branch outside giv lifetime.\n"); | |
5881 | ||
5882 | break; | |
5883 | } | |
5884 | } | |
5885 | } | |
5886 | ||
5887 | /* If it is replaceable, then save the final value. */ | |
5888 | if (v->replaceable) | |
5889 | v->final_value = final_value; | |
5890 | } | |
5891 | ||
5892 | if (loop_dump_stream && v->replaceable) | |
5893 | fprintf (loop_dump_stream, "Insn %d: giv reg %d final_value replaceable\n", | |
5894 | INSN_UID (v->insn), REGNO (v->dest_reg)); | |
5895 | } | |
5896 | \f | |
5897 | /* Update the status of whether a giv can derive other givs. | |
5898 | ||
5899 | We need to do something special if there is or may be an update to the biv | |
5900 | between the time the giv is defined and the time it is used to derive | |
5901 | another giv. | |
5902 | ||
5903 | In addition, a giv that is only conditionally set is not allowed to | |
5904 | derive another giv once a label has been passed. | |
5905 | ||
5906 | The cases we look at are when a label or an update to a biv is passed. */ | |
5907 | ||
5908 | static void | |
5909 | update_giv_derive (p) | |
5910 | rtx p; | |
5911 | { | |
5912 | struct iv_class *bl; | |
5913 | struct induction *biv, *giv; | |
5914 | rtx tem; | |
5915 | int dummy; | |
5916 | ||
5917 | /* Search all IV classes, then all bivs, and finally all givs. | |
5918 | ||
7dcd3836 | 5919 | There are three cases we are concerned with. First we have the situation |
b4ad7b23 RS |
5920 | of a giv that is only updated conditionally. In that case, it may not |
5921 | derive any givs after a label is passed. | |
5922 | ||
5923 | The second case is when a biv update occurs, or may occur, after the | |
5924 | definition of a giv. For certain biv updates (see below) that are | |
5925 | known to occur between the giv definition and use, we can adjust the | |
5926 | giv definition. For others, or when the biv update is conditional, | |
5927 | we must prevent the giv from deriving any other givs. There are two | |
5928 | sub-cases within this case. | |
5929 | ||
5930 | If this is a label, we are concerned with any biv update that is done | |
5931 | conditionally, since it may be done after the giv is defined followed by | |
5932 | a branch here (actually, we need to pass both a jump and a label, but | |
5933 | this extra tracking doesn't seem worth it). | |
5934 | ||
7dcd3836 RK |
5935 | If this is a jump, we are concerned about any biv update that may be |
5936 | executed multiple times. We are actually only concerned about | |
5937 | backward jumps, but it is probably not worth performing the test | |
5938 | on the jump again here. | |
5939 | ||
5940 | If this is a biv update, we must adjust the giv status to show that a | |
b4ad7b23 RS |
5941 | subsequent biv update was performed. If this adjustment cannot be done, |
5942 | the giv cannot derive further givs. */ | |
5943 | ||
5944 | for (bl = loop_iv_list; bl; bl = bl->next) | |
5945 | for (biv = bl->biv; biv; biv = biv->next_iv) | |
7dcd3836 RK |
5946 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN |
5947 | || biv->insn == p) | |
b4ad7b23 RS |
5948 | { |
5949 | for (giv = bl->giv; giv; giv = giv->next_iv) | |
5950 | { | |
5951 | /* If cant_derive is already true, there is no point in | |
5952 | checking all of these conditions again. */ | |
5953 | if (giv->cant_derive) | |
5954 | continue; | |
5955 | ||
5956 | /* If this giv is conditionally set and we have passed a label, | |
5957 | it cannot derive anything. */ | |
5958 | if (GET_CODE (p) == CODE_LABEL && ! giv->always_computable) | |
5959 | giv->cant_derive = 1; | |
5960 | ||
5961 | /* Skip givs that have mult_val == 0, since | |
5962 | they are really invariants. Also skip those that are | |
5963 | replaceable, since we know their lifetime doesn't contain | |
5964 | any biv update. */ | |
5965 | else if (giv->mult_val == const0_rtx || giv->replaceable) | |
5966 | continue; | |
5967 | ||
5968 | /* The only way we can allow this giv to derive another | |
5969 | is if this is a biv increment and we can form the product | |
5970 | of biv->add_val and giv->mult_val. In this case, we will | |
5971 | be able to compute a compensation. */ | |
5972 | else if (biv->insn == p) | |
5973 | { | |
c160c628 RK |
5974 | tem = 0; |
5975 | ||
5976 | if (biv->mult_val == const1_rtx) | |
38a448ca RH |
5977 | tem = simplify_giv_expr (gen_rtx_MULT (giv->mode, |
5978 | biv->add_val, | |
5979 | giv->mult_val), | |
c160c628 RK |
5980 | &dummy); |
5981 | ||
5982 | if (tem && giv->derive_adjustment) | |
c5c76735 JL |
5983 | tem = simplify_giv_expr |
5984 | (gen_rtx_PLUS (giv->mode, tem, giv->derive_adjustment), | |
5985 | &dummy); | |
5986 | ||
c160c628 | 5987 | if (tem) |
b4ad7b23 RS |
5988 | giv->derive_adjustment = tem; |
5989 | else | |
5990 | giv->cant_derive = 1; | |
5991 | } | |
7dcd3836 RK |
5992 | else if ((GET_CODE (p) == CODE_LABEL && ! biv->always_computable) |
5993 | || (GET_CODE (p) == JUMP_INSN && biv->maybe_multiple)) | |
b4ad7b23 RS |
5994 | giv->cant_derive = 1; |
5995 | } | |
5996 | } | |
5997 | } | |
5998 | \f | |
5999 | /* Check whether an insn is an increment legitimate for a basic induction var. | |
7056f7e8 RS |
6000 | X is the source of insn P, or a part of it. |
6001 | MODE is the mode in which X should be interpreted. | |
6002 | ||
b4ad7b23 RS |
6003 | DEST_REG is the putative biv, also the destination of the insn. |
6004 | We accept patterns of these forms: | |
09d7f5a5 | 6005 | REG = REG + INVARIANT (includes REG = REG - CONSTANT) |
b4ad7b23 | 6006 | REG = INVARIANT + REG |
b4ad7b23 RS |
6007 | |
6008 | If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX, | |
3ec2b590 R |
6009 | store the additive term into *INC_VAL, and store the place where |
6010 | we found the additive term into *LOCATION. | |
b4ad7b23 RS |
6011 | |
6012 | If X is an assignment of an invariant into DEST_REG, we set | |
6013 | *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL. | |
6014 | ||
09d7f5a5 RK |
6015 | We also want to detect a BIV when it corresponds to a variable |
6016 | whose mode was promoted via PROMOTED_MODE. In that case, an increment | |
6017 | of the variable may be a PLUS that adds a SUBREG of that variable to | |
6018 | an invariant and then sign- or zero-extends the result of the PLUS | |
6019 | into the variable. | |
6020 | ||
6021 | Most GIVs in such cases will be in the promoted mode, since that is the | |
6022 | probably the natural computation mode (and almost certainly the mode | |
6023 | used for addresses) on the machine. So we view the pseudo-reg containing | |
6024 | the variable as the BIV, as if it were simply incremented. | |
6025 | ||
6026 | Note that treating the entire pseudo as a BIV will result in making | |
6027 | simple increments to any GIVs based on it. However, if the variable | |
6028 | overflows in its declared mode but not its promoted mode, the result will | |
6029 | be incorrect. This is acceptable if the variable is signed, since | |
6030 | overflows in such cases are undefined, but not if it is unsigned, since | |
6031 | those overflows are defined. So we only check for SIGN_EXTEND and | |
6032 | not ZERO_EXTEND. | |
6033 | ||
6034 | If we cannot find a biv, we return 0. */ | |
b4ad7b23 RS |
6035 | |
6036 | static int | |
a2be868f MH |
6037 | basic_induction_var (x, mode, dest_reg, p, level, inc_val, mult_val, |
6038 | location, multi_insn_incr) | |
b4ad7b23 | 6039 | register rtx x; |
7056f7e8 | 6040 | enum machine_mode mode; |
b4ad7b23 | 6041 | rtx dest_reg; |
a2be868f MH |
6042 | rtx p; |
6043 | int level; | |
b4ad7b23 RS |
6044 | rtx *inc_val; |
6045 | rtx *mult_val; | |
3ec2b590 | 6046 | rtx **location; |
60fb6df9 | 6047 | int *multi_insn_incr; |
b4ad7b23 RS |
6048 | { |
6049 | register enum rtx_code code; | |
3ec2b590 | 6050 | rtx *argp, arg; |
09d7f5a5 | 6051 | rtx insn, set = 0; |
b4ad7b23 RS |
6052 | |
6053 | code = GET_CODE (x); | |
69ba6af3 | 6054 | *location = NULL; |
b4ad7b23 RS |
6055 | switch (code) |
6056 | { | |
6057 | case PLUS: | |
45f97e2e | 6058 | if (rtx_equal_p (XEXP (x, 0), dest_reg) |
09d7f5a5 RK |
6059 | || (GET_CODE (XEXP (x, 0)) == SUBREG |
6060 | && SUBREG_PROMOTED_VAR_P (XEXP (x, 0)) | |
6061 | && SUBREG_REG (XEXP (x, 0)) == dest_reg)) | |
3ec2b590 R |
6062 | { |
6063 | argp = &XEXP (x, 1); | |
6064 | } | |
45f97e2e | 6065 | else if (rtx_equal_p (XEXP (x, 1), dest_reg) |
09d7f5a5 | 6066 | || (GET_CODE (XEXP (x, 1)) == SUBREG |
b81fd0f4 RS |
6067 | && SUBREG_PROMOTED_VAR_P (XEXP (x, 1)) |
6068 | && SUBREG_REG (XEXP (x, 1)) == dest_reg)) | |
3ec2b590 R |
6069 | { |
6070 | argp = &XEXP (x, 0); | |
6071 | } | |
b4ad7b23 RS |
6072 | else |
6073 | return 0; | |
6074 | ||
3ec2b590 | 6075 | arg = *argp; |
b4ad7b23 RS |
6076 | if (invariant_p (arg) != 1) |
6077 | return 0; | |
6078 | ||
7056f7e8 | 6079 | *inc_val = convert_modes (GET_MODE (dest_reg), GET_MODE (x), arg, 0); |
b4ad7b23 | 6080 | *mult_val = const1_rtx; |
3ec2b590 | 6081 | *location = argp; |
b4ad7b23 RS |
6082 | return 1; |
6083 | ||
09d7f5a5 RK |
6084 | case SUBREG: |
6085 | /* If this is a SUBREG for a promoted variable, check the inner | |
6086 | value. */ | |
6087 | if (SUBREG_PROMOTED_VAR_P (x)) | |
7056f7e8 | 6088 | return basic_induction_var (SUBREG_REG (x), GET_MODE (SUBREG_REG (x)), |
a2be868f MH |
6089 | dest_reg, p, level, |
6090 | inc_val, mult_val, location, | |
60fb6df9 | 6091 | multi_insn_incr); |
fe159061 | 6092 | return 0; |
b4ad7b23 | 6093 | |
09d7f5a5 | 6094 | case REG: |
45f97e2e | 6095 | /* If this register is assigned in a previous insn, look at its |
09d7f5a5 RK |
6096 | source, but don't go outside the loop or past a label. */ |
6097 | ||
45f97e2e RH |
6098 | insn = p; |
6099 | while (1) | |
6100 | { | |
6101 | do { | |
6102 | insn = PREV_INSN (insn); | |
6103 | } while (insn && GET_CODE (insn) == NOTE | |
6104 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG); | |
09d7f5a5 | 6105 | |
45f97e2e RH |
6106 | if (!insn) |
6107 | break; | |
6108 | set = single_set (insn); | |
6109 | if (set == 0) | |
6110 | break; | |
09d7f5a5 | 6111 | |
45f97e2e RH |
6112 | if ((SET_DEST (set) == x |
6113 | || (GET_CODE (SET_DEST (set)) == SUBREG | |
6114 | && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) | |
6115 | <= UNITS_PER_WORD) | |
7f6dae2a GK |
6116 | && (GET_MODE_CLASS (GET_MODE (SET_DEST (set))) |
6117 | == MODE_INT) | |
45f97e2e RH |
6118 | && SUBREG_REG (SET_DEST (set)) == x)) |
6119 | && basic_induction_var (SET_SRC (set), | |
6120 | (GET_MODE (SET_SRC (set)) == VOIDmode | |
6121 | ? GET_MODE (x) | |
6122 | : GET_MODE (SET_SRC (set))), | |
a2be868f | 6123 | dest_reg, insn, level, |
60fb6df9 RH |
6124 | inc_val, mult_val, location, |
6125 | multi_insn_incr)) | |
6126 | { | |
6127 | *multi_insn_incr = 1; | |
6128 | return 1; | |
6129 | } | |
45f97e2e | 6130 | } |
0f41302f | 6131 | /* ... fall through ... */ |
b4ad7b23 RS |
6132 | |
6133 | /* Can accept constant setting of biv only when inside inner most loop. | |
6134 | Otherwise, a biv of an inner loop may be incorrectly recognized | |
6135 | as a biv of the outer loop, | |
6136 | causing code to be moved INTO the inner loop. */ | |
6137 | case MEM: | |
b4ad7b23 RS |
6138 | if (invariant_p (x) != 1) |
6139 | return 0; | |
6140 | case CONST_INT: | |
6141 | case SYMBOL_REF: | |
6142 | case CONST: | |
829002bb BM |
6143 | /* convert_modes aborts if we try to convert to or from CCmode, so just |
6144 | exclude that case. It is very unlikely that a condition code value | |
6145 | would be a useful iterator anyways. */ | |
a2be868f | 6146 | if (level == 0 |
829002bb BM |
6147 | && GET_MODE_CLASS (mode) != MODE_CC |
6148 | && GET_MODE_CLASS (GET_MODE (dest_reg)) != MODE_CC) | |
b4ad7b23 | 6149 | { |
7056f7e8 RS |
6150 | /* Possible bug here? Perhaps we don't know the mode of X. */ |
6151 | *inc_val = convert_modes (GET_MODE (dest_reg), mode, x, 0); | |
b4ad7b23 RS |
6152 | *mult_val = const0_rtx; |
6153 | return 1; | |
6154 | } | |
6155 | else | |
6156 | return 0; | |
6157 | ||
09d7f5a5 | 6158 | case SIGN_EXTEND: |
7056f7e8 | 6159 | return basic_induction_var (XEXP (x, 0), GET_MODE (XEXP (x, 0)), |
a2be868f MH |
6160 | dest_reg, p, level, inc_val, mult_val, |
6161 | location, multi_insn_incr); | |
45f97e2e | 6162 | |
09d7f5a5 RK |
6163 | case ASHIFTRT: |
6164 | /* Similar, since this can be a sign extension. */ | |
6165 | for (insn = PREV_INSN (p); | |
6166 | (insn && GET_CODE (insn) == NOTE | |
6167 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG); | |
6168 | insn = PREV_INSN (insn)) | |
6169 | ; | |
6170 | ||
6171 | if (insn) | |
6172 | set = single_set (insn); | |
6173 | ||
6174 | if (set && SET_DEST (set) == XEXP (x, 0) | |
6175 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6176 | && INTVAL (XEXP (x, 1)) >= 0 | |
6177 | && GET_CODE (SET_SRC (set)) == ASHIFT | |
60fb6df9 RH |
6178 | && XEXP (x, 1) == XEXP (SET_SRC (set), 1) |
6179 | && basic_induction_var (XEXP (SET_SRC (set), 0), | |
6180 | GET_MODE (XEXP (x, 0)), | |
a2be868f | 6181 | dest_reg, insn, level, inc_val, mult_val, |
60fb6df9 RH |
6182 | location, multi_insn_incr)) |
6183 | { | |
6184 | *multi_insn_incr = 1; | |
6185 | return 1; | |
6186 | } | |
09d7f5a5 RK |
6187 | return 0; |
6188 | ||
b4ad7b23 RS |
6189 | default: |
6190 | return 0; | |
6191 | } | |
6192 | } | |
6193 | \f | |
6194 | /* A general induction variable (giv) is any quantity that is a linear | |
6195 | function of a basic induction variable, | |
6196 | i.e. giv = biv * mult_val + add_val. | |
6197 | The coefficients can be any loop invariant quantity. | |
6198 | A giv need not be computed directly from the biv; | |
6199 | it can be computed by way of other givs. */ | |
6200 | ||
6201 | /* Determine whether X computes a giv. | |
6202 | If it does, return a nonzero value | |
6203 | which is the benefit from eliminating the computation of X; | |
6204 | set *SRC_REG to the register of the biv that it is computed from; | |
6205 | set *ADD_VAL and *MULT_VAL to the coefficients, | |
6206 | such that the value of X is biv * mult + add; */ | |
6207 | ||
6208 | static int | |
45f97e2e | 6209 | general_induction_var (x, src_reg, add_val, mult_val, is_addr, pbenefit) |
b4ad7b23 RS |
6210 | rtx x; |
6211 | rtx *src_reg; | |
6212 | rtx *add_val; | |
6213 | rtx *mult_val; | |
45f97e2e RH |
6214 | int is_addr; |
6215 | int *pbenefit; | |
b4ad7b23 RS |
6216 | { |
6217 | rtx orig_x = x; | |
b4ad7b23 RS |
6218 | char *storage; |
6219 | ||
6220 | /* If this is an invariant, forget it, it isn't a giv. */ | |
6221 | if (invariant_p (x) == 1) | |
6222 | return 0; | |
6223 | ||
6224 | /* See if the expression could be a giv and get its form. | |
6225 | Mark our place on the obstack in case we don't find a giv. */ | |
6226 | storage = (char *) oballoc (0); | |
45f97e2e RH |
6227 | *pbenefit = 0; |
6228 | x = simplify_giv_expr (x, pbenefit); | |
b4ad7b23 RS |
6229 | if (x == 0) |
6230 | { | |
6231 | obfree (storage); | |
6232 | return 0; | |
6233 | } | |
6234 | ||
6235 | switch (GET_CODE (x)) | |
6236 | { | |
6237 | case USE: | |
6238 | case CONST_INT: | |
6239 | /* Since this is now an invariant and wasn't before, it must be a giv | |
6240 | with MULT_VAL == 0. It doesn't matter which BIV we associate this | |
6241 | with. */ | |
6242 | *src_reg = loop_iv_list->biv->dest_reg; | |
6243 | *mult_val = const0_rtx; | |
6244 | *add_val = x; | |
6245 | break; | |
6246 | ||
6247 | case REG: | |
6248 | /* This is equivalent to a BIV. */ | |
6249 | *src_reg = x; | |
6250 | *mult_val = const1_rtx; | |
6251 | *add_val = const0_rtx; | |
6252 | break; | |
6253 | ||
6254 | case PLUS: | |
6255 | /* Either (plus (biv) (invar)) or | |
6256 | (plus (mult (biv) (invar_1)) (invar_2)). */ | |
6257 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
6258 | { | |
6259 | *src_reg = XEXP (XEXP (x, 0), 0); | |
6260 | *mult_val = XEXP (XEXP (x, 0), 1); | |
6261 | } | |
6262 | else | |
6263 | { | |
6264 | *src_reg = XEXP (x, 0); | |
6265 | *mult_val = const1_rtx; | |
6266 | } | |
6267 | *add_val = XEXP (x, 1); | |
6268 | break; | |
6269 | ||
6270 | case MULT: | |
6271 | /* ADD_VAL is zero. */ | |
6272 | *src_reg = XEXP (x, 0); | |
6273 | *mult_val = XEXP (x, 1); | |
6274 | *add_val = const0_rtx; | |
6275 | break; | |
6276 | ||
6277 | default: | |
6278 | abort (); | |
6279 | } | |
6280 | ||
6281 | /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be | |
6282 | unless they are CONST_INT). */ | |
6283 | if (GET_CODE (*add_val) == USE) | |
6284 | *add_val = XEXP (*add_val, 0); | |
6285 | if (GET_CODE (*mult_val) == USE) | |
6286 | *mult_val = XEXP (*mult_val, 0); | |
6287 | ||
45f97e2e RH |
6288 | if (is_addr) |
6289 | { | |
6290 | #ifdef ADDRESS_COST | |
6291 | *pbenefit += ADDRESS_COST (orig_x) - reg_address_cost; | |
6292 | #else | |
6293 | *pbenefit += rtx_cost (orig_x, MEM) - reg_address_cost; | |
6294 | #endif | |
6295 | } | |
6296 | else | |
6297 | *pbenefit += rtx_cost (orig_x, SET); | |
b4ad7b23 | 6298 | |
45f97e2e RH |
6299 | /* Always return true if this is a giv so it will be detected as such, |
6300 | even if the benefit is zero or negative. This allows elimination | |
6301 | of bivs that might otherwise not be eliminated. */ | |
6302 | return 1; | |
b4ad7b23 RS |
6303 | } |
6304 | \f | |
6305 | /* Given an expression, X, try to form it as a linear function of a biv. | |
6306 | We will canonicalize it to be of the form | |
6307 | (plus (mult (BIV) (invar_1)) | |
6308 | (invar_2)) | |
c5b7917e | 6309 | with possible degeneracies. |
b4ad7b23 RS |
6310 | |
6311 | The invariant expressions must each be of a form that can be used as a | |
6312 | machine operand. We surround then with a USE rtx (a hack, but localized | |
6313 | and certainly unambiguous!) if not a CONST_INT for simplicity in this | |
6314 | routine; it is the caller's responsibility to strip them. | |
6315 | ||
6316 | If no such canonicalization is possible (i.e., two biv's are used or an | |
6317 | expression that is neither invariant nor a biv or giv), this routine | |
6318 | returns 0. | |
6319 | ||
6320 | For a non-zero return, the result will have a code of CONST_INT, USE, | |
6321 | REG (for a BIV), PLUS, or MULT. No other codes will occur. | |
6322 | ||
6323 | *BENEFIT will be incremented by the benefit of any sub-giv encountered. */ | |
6324 | ||
f428f252 KG |
6325 | static rtx sge_plus PARAMS ((enum machine_mode, rtx, rtx)); |
6326 | static rtx sge_plus_constant PARAMS ((rtx, rtx)); | |
6327 | static int cmp_combine_givs_stats PARAMS ((const PTR, const PTR)); | |
6328 | static int cmp_recombine_givs_stats PARAMS ((const PTR, const PTR)); | |
45f97e2e | 6329 | |
b4ad7b23 RS |
6330 | static rtx |
6331 | simplify_giv_expr (x, benefit) | |
6332 | rtx x; | |
6333 | int *benefit; | |
6334 | { | |
6335 | enum machine_mode mode = GET_MODE (x); | |
6336 | rtx arg0, arg1; | |
6337 | rtx tem; | |
6338 | ||
6339 | /* If this is not an integer mode, or if we cannot do arithmetic in this | |
6340 | mode, this can't be a giv. */ | |
6341 | if (mode != VOIDmode | |
6342 | && (GET_MODE_CLASS (mode) != MODE_INT | |
5fd8383e | 6343 | || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)) |
45f97e2e | 6344 | return NULL_RTX; |
b4ad7b23 RS |
6345 | |
6346 | switch (GET_CODE (x)) | |
6347 | { | |
6348 | case PLUS: | |
6349 | arg0 = simplify_giv_expr (XEXP (x, 0), benefit); | |
6350 | arg1 = simplify_giv_expr (XEXP (x, 1), benefit); | |
6351 | if (arg0 == 0 || arg1 == 0) | |
45f97e2e | 6352 | return NULL_RTX; |
b4ad7b23 RS |
6353 | |
6354 | /* Put constant last, CONST_INT last if both constant. */ | |
6355 | if ((GET_CODE (arg0) == USE | |
6356 | || GET_CODE (arg0) == CONST_INT) | |
45f97e2e RH |
6357 | && ! ((GET_CODE (arg0) == USE |
6358 | && GET_CODE (arg1) == USE) | |
6359 | || GET_CODE (arg1) == CONST_INT)) | |
b4ad7b23 RS |
6360 | tem = arg0, arg0 = arg1, arg1 = tem; |
6361 | ||
6362 | /* Handle addition of zero, then addition of an invariant. */ | |
6363 | if (arg1 == const0_rtx) | |
6364 | return arg0; | |
6365 | else if (GET_CODE (arg1) == CONST_INT || GET_CODE (arg1) == USE) | |
6366 | switch (GET_CODE (arg0)) | |
6367 | { | |
6368 | case CONST_INT: | |
6369 | case USE: | |
45f97e2e RH |
6370 | /* Adding two invariants must result in an invariant, so enclose |
6371 | addition operation inside a USE and return it. */ | |
b4ad7b23 RS |
6372 | if (GET_CODE (arg0) == USE) |
6373 | arg0 = XEXP (arg0, 0); | |
da0af5a5 JL |
6374 | if (GET_CODE (arg1) == USE) |
6375 | arg1 = XEXP (arg1, 0); | |
6376 | ||
45f97e2e RH |
6377 | if (GET_CODE (arg0) == CONST_INT) |
6378 | tem = arg0, arg0 = arg1, arg1 = tem; | |
6379 | if (GET_CODE (arg1) == CONST_INT) | |
6380 | tem = sge_plus_constant (arg0, arg1); | |
da0af5a5 | 6381 | else |
45f97e2e | 6382 | tem = sge_plus (mode, arg0, arg1); |
b4ad7b23 | 6383 | |
45f97e2e RH |
6384 | if (GET_CODE (tem) != CONST_INT) |
6385 | tem = gen_rtx_USE (mode, tem); | |
b4ad7b23 RS |
6386 | return tem; |
6387 | ||
6388 | case REG: | |
6389 | case MULT: | |
6390 | /* biv + invar or mult + invar. Return sum. */ | |
38a448ca | 6391 | return gen_rtx_PLUS (mode, arg0, arg1); |
b4ad7b23 RS |
6392 | |
6393 | case PLUS: | |
6394 | /* (a + invar_1) + invar_2. Associate. */ | |
c5c76735 JL |
6395 | return |
6396 | simplify_giv_expr (gen_rtx_PLUS (mode, | |
6397 | XEXP (arg0, 0), | |
6398 | gen_rtx_PLUS (mode, | |
6399 | XEXP (arg0, 1), | |
6400 | arg1)), | |
6401 | benefit); | |
b4ad7b23 RS |
6402 | |
6403 | default: | |
6404 | abort (); | |
6405 | } | |
6406 | ||
6407 | /* Each argument must be either REG, PLUS, or MULT. Convert REG to | |
6408 | MULT to reduce cases. */ | |
6409 | if (GET_CODE (arg0) == REG) | |
38a448ca | 6410 | arg0 = gen_rtx_MULT (mode, arg0, const1_rtx); |
b4ad7b23 | 6411 | if (GET_CODE (arg1) == REG) |
38a448ca | 6412 | arg1 = gen_rtx_MULT (mode, arg1, const1_rtx); |
b4ad7b23 RS |
6413 | |
6414 | /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT. | |
6415 | Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT. | |
6416 | Recurse to associate the second PLUS. */ | |
6417 | if (GET_CODE (arg1) == MULT) | |
6418 | tem = arg0, arg0 = arg1, arg1 = tem; | |
6419 | ||
6420 | if (GET_CODE (arg1) == PLUS) | |
c5c76735 JL |
6421 | return |
6422 | simplify_giv_expr (gen_rtx_PLUS (mode, | |
6423 | gen_rtx_PLUS (mode, arg0, | |
6424 | XEXP (arg1, 0)), | |
6425 | XEXP (arg1, 1)), | |
6426 | benefit); | |
b4ad7b23 RS |
6427 | |
6428 | /* Now must have MULT + MULT. Distribute if same biv, else not giv. */ | |
6429 | if (GET_CODE (arg0) != MULT || GET_CODE (arg1) != MULT) | |
45f97e2e | 6430 | return NULL_RTX; |
b4ad7b23 | 6431 | |
45f97e2e RH |
6432 | if (!rtx_equal_p (arg0, arg1)) |
6433 | return NULL_RTX; | |
b4ad7b23 | 6434 | |
38a448ca RH |
6435 | return simplify_giv_expr (gen_rtx_MULT (mode, |
6436 | XEXP (arg0, 0), | |
6437 | gen_rtx_PLUS (mode, | |
6438 | XEXP (arg0, 1), | |
6439 | XEXP (arg1, 1))), | |
b4ad7b23 RS |
6440 | benefit); |
6441 | ||
6442 | case MINUS: | |
0f41302f | 6443 | /* Handle "a - b" as "a + b * (-1)". */ |
38a448ca RH |
6444 | return simplify_giv_expr (gen_rtx_PLUS (mode, |
6445 | XEXP (x, 0), | |
c5c76735 JL |
6446 | gen_rtx_MULT (mode, |
6447 | XEXP (x, 1), | |
38a448ca | 6448 | constm1_rtx)), |
b4ad7b23 RS |
6449 | benefit); |
6450 | ||
6451 | case MULT: | |
6452 | arg0 = simplify_giv_expr (XEXP (x, 0), benefit); | |
6453 | arg1 = simplify_giv_expr (XEXP (x, 1), benefit); | |
6454 | if (arg0 == 0 || arg1 == 0) | |
45f97e2e | 6455 | return NULL_RTX; |
b4ad7b23 RS |
6456 | |
6457 | /* Put constant last, CONST_INT last if both constant. */ | |
6458 | if ((GET_CODE (arg0) == USE || GET_CODE (arg0) == CONST_INT) | |
6459 | && GET_CODE (arg1) != CONST_INT) | |
6460 | tem = arg0, arg0 = arg1, arg1 = tem; | |
6461 | ||
6462 | /* If second argument is not now constant, not giv. */ | |
6463 | if (GET_CODE (arg1) != USE && GET_CODE (arg1) != CONST_INT) | |
45f97e2e | 6464 | return NULL_RTX; |
b4ad7b23 RS |
6465 | |
6466 | /* Handle multiply by 0 or 1. */ | |
6467 | if (arg1 == const0_rtx) | |
6468 | return const0_rtx; | |
6469 | ||
6470 | else if (arg1 == const1_rtx) | |
6471 | return arg0; | |
6472 | ||
6473 | switch (GET_CODE (arg0)) | |
6474 | { | |
6475 | case REG: | |
6476 | /* biv * invar. Done. */ | |
38a448ca | 6477 | return gen_rtx_MULT (mode, arg0, arg1); |
b4ad7b23 RS |
6478 | |
6479 | case CONST_INT: | |
6480 | /* Product of two constants. */ | |
5fd8383e | 6481 | return GEN_INT (INTVAL (arg0) * INTVAL (arg1)); |
b4ad7b23 RS |
6482 | |
6483 | case USE: | |
45f97e2e RH |
6484 | /* invar * invar. It is a giv, but very few of these will |
6485 | actually pay off, so limit to simple registers. */ | |
6486 | if (GET_CODE (arg1) != CONST_INT) | |
6487 | return NULL_RTX; | |
6488 | ||
6489 | arg0 = XEXP (arg0, 0); | |
6490 | if (GET_CODE (arg0) == REG) | |
6491 | tem = gen_rtx_MULT (mode, arg0, arg1); | |
6492 | else if (GET_CODE (arg0) == MULT | |
6493 | && GET_CODE (XEXP (arg0, 0)) == REG | |
6494 | && GET_CODE (XEXP (arg0, 1)) == CONST_INT) | |
6495 | { | |
6496 | tem = gen_rtx_MULT (mode, XEXP (arg0, 0), | |
6497 | GEN_INT (INTVAL (XEXP (arg0, 1)) | |
6498 | * INTVAL (arg1))); | |
6499 | } | |
6500 | else | |
6501 | return NULL_RTX; | |
6502 | return gen_rtx_USE (mode, tem); | |
b4ad7b23 RS |
6503 | |
6504 | case MULT: | |
6505 | /* (a * invar_1) * invar_2. Associate. */ | |
c5c76735 JL |
6506 | return simplify_giv_expr (gen_rtx_MULT (mode, |
6507 | XEXP (arg0, 0), | |
38a448ca RH |
6508 | gen_rtx_MULT (mode, |
6509 | XEXP (arg0, 1), | |
6510 | arg1)), | |
b4ad7b23 RS |
6511 | benefit); |
6512 | ||
6513 | case PLUS: | |
6514 | /* (a + invar_1) * invar_2. Distribute. */ | |
38a448ca RH |
6515 | return simplify_giv_expr (gen_rtx_PLUS (mode, |
6516 | gen_rtx_MULT (mode, | |
6517 | XEXP (arg0, 0), | |
6518 | arg1), | |
6519 | gen_rtx_MULT (mode, | |
6520 | XEXP (arg0, 1), | |
6521 | arg1)), | |
b4ad7b23 RS |
6522 | benefit); |
6523 | ||
6524 | default: | |
6525 | abort (); | |
6526 | } | |
6527 | ||
6528 | case ASHIFT: | |
b4ad7b23 RS |
6529 | /* Shift by constant is multiply by power of two. */ |
6530 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6531 | return 0; | |
6532 | ||
c5c76735 JL |
6533 | return |
6534 | simplify_giv_expr (gen_rtx_MULT (mode, | |
6535 | XEXP (x, 0), | |
6536 | GEN_INT ((HOST_WIDE_INT) 1 | |
6537 | << INTVAL (XEXP (x, 1)))), | |
6538 | benefit); | |
b4ad7b23 RS |
6539 | |
6540 | case NEG: | |
6541 | /* "-a" is "a * (-1)" */ | |
38a448ca | 6542 | return simplify_giv_expr (gen_rtx_MULT (mode, XEXP (x, 0), constm1_rtx), |
b4ad7b23 RS |
6543 | benefit); |
6544 | ||
6545 | case NOT: | |
6546 | /* "~a" is "-a - 1". Silly, but easy. */ | |
38a448ca RH |
6547 | return simplify_giv_expr (gen_rtx_MINUS (mode, |
6548 | gen_rtx_NEG (mode, XEXP (x, 0)), | |
6549 | const1_rtx), | |
b4ad7b23 RS |
6550 | benefit); |
6551 | ||
6552 | case USE: | |
6553 | /* Already in proper form for invariant. */ | |
6554 | return x; | |
6555 | ||
6556 | case REG: | |
6557 | /* If this is a new register, we can't deal with it. */ | |
6558 | if (REGNO (x) >= max_reg_before_loop) | |
6559 | return 0; | |
6560 | ||
6561 | /* Check for biv or giv. */ | |
3ec2b590 | 6562 | switch (REG_IV_TYPE (REGNO (x))) |
b4ad7b23 RS |
6563 | { |
6564 | case BASIC_INDUCT: | |
6565 | return x; | |
6566 | case GENERAL_INDUCT: | |
6567 | { | |
3ec2b590 | 6568 | struct induction *v = REG_IV_INFO (REGNO (x)); |
b4ad7b23 RS |
6569 | |
6570 | /* Form expression from giv and add benefit. Ensure this giv | |
6571 | can derive another and subtract any needed adjustment if so. */ | |
6572 | *benefit += v->benefit; | |
6573 | if (v->cant_derive) | |
6574 | return 0; | |
6575 | ||
c5c76735 JL |
6576 | tem = gen_rtx_PLUS (mode, gen_rtx_MULT (mode, |
6577 | v->src_reg, v->mult_val), | |
6578 | v->add_val); | |
6579 | ||
b4ad7b23 | 6580 | if (v->derive_adjustment) |
38a448ca | 6581 | tem = gen_rtx_MINUS (mode, tem, v->derive_adjustment); |
b4ad7b23 RS |
6582 | return simplify_giv_expr (tem, benefit); |
6583 | } | |
e9a25f70 JL |
6584 | |
6585 | default: | |
45f97e2e RH |
6586 | /* If it isn't an induction variable, and it is invariant, we |
6587 | may be able to simplify things further by looking through | |
6588 | the bits we just moved outside the loop. */ | |
6589 | if (invariant_p (x) == 1) | |
6590 | { | |
6591 | struct movable *m; | |
6592 | ||
6593 | for (m = the_movables; m ; m = m->next) | |
6594 | if (rtx_equal_p (x, m->set_dest)) | |
6595 | { | |
6596 | /* Ok, we found a match. Substitute and simplify. */ | |
6597 | ||
6598 | /* If we match another movable, we must use that, as | |
6599 | this one is going away. */ | |
6600 | if (m->match) | |
6601 | return simplify_giv_expr (m->match->set_dest, benefit); | |
6602 | ||
6603 | /* If consec is non-zero, this is a member of a group of | |
6604 | instructions that were moved together. We handle this | |
6605 | case only to the point of seeking to the last insn and | |
6606 | looking for a REG_EQUAL. Fail if we don't find one. */ | |
6607 | if (m->consec != 0) | |
6608 | { | |
6609 | int i = m->consec; | |
6610 | tem = m->insn; | |
6611 | do { tem = NEXT_INSN (tem); } while (--i > 0); | |
6612 | ||
6613 | tem = find_reg_note (tem, REG_EQUAL, NULL_RTX); | |
6614 | if (tem) | |
6615 | tem = XEXP (tem, 0); | |
6616 | } | |
6617 | else | |
6618 | { | |
6619 | tem = single_set (m->insn); | |
6620 | if (tem) | |
6621 | tem = SET_SRC (tem); | |
6622 | } | |
6623 | ||
6624 | if (tem) | |
6625 | { | |
6626 | /* What we are most interested in is pointer | |
6627 | arithmetic on invariants -- only take | |
6628 | patterns we may be able to do something with. */ | |
6629 | if (GET_CODE (tem) == PLUS | |
6630 | || GET_CODE (tem) == MULT | |
6631 | || GET_CODE (tem) == ASHIFT | |
6632 | || GET_CODE (tem) == CONST_INT | |
6633 | || GET_CODE (tem) == SYMBOL_REF) | |
6634 | { | |
6635 | tem = simplify_giv_expr (tem, benefit); | |
6636 | if (tem) | |
6637 | return tem; | |
6638 | } | |
6639 | else if (GET_CODE (tem) == CONST | |
6640 | && GET_CODE (XEXP (tem, 0)) == PLUS | |
6641 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == SYMBOL_REF | |
6642 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT) | |
6643 | { | |
6644 | tem = simplify_giv_expr (XEXP (tem, 0), benefit); | |
6645 | if (tem) | |
6646 | return tem; | |
6647 | } | |
6648 | } | |
6649 | break; | |
6650 | } | |
6651 | } | |
e9a25f70 | 6652 | break; |
b4ad7b23 RS |
6653 | } |
6654 | ||
6655 | /* Fall through to general case. */ | |
6656 | default: | |
6657 | /* If invariant, return as USE (unless CONST_INT). | |
6658 | Otherwise, not giv. */ | |
6659 | if (GET_CODE (x) == USE) | |
6660 | x = XEXP (x, 0); | |
6661 | ||
6662 | if (invariant_p (x) == 1) | |
6663 | { | |
6664 | if (GET_CODE (x) == CONST_INT) | |
6665 | return x; | |
45f97e2e RH |
6666 | if (GET_CODE (x) == CONST |
6667 | && GET_CODE (XEXP (x, 0)) == PLUS | |
6668 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
6669 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
6670 | x = XEXP (x, 0); | |
6671 | return gen_rtx_USE (mode, x); | |
b4ad7b23 RS |
6672 | } |
6673 | else | |
6674 | return 0; | |
6675 | } | |
6676 | } | |
45f97e2e RH |
6677 | |
6678 | /* This routine folds invariants such that there is only ever one | |
6679 | CONST_INT in the summation. It is only used by simplify_giv_expr. */ | |
6680 | ||
6681 | static rtx | |
6682 | sge_plus_constant (x, c) | |
6683 | rtx x, c; | |
6684 | { | |
6685 | if (GET_CODE (x) == CONST_INT) | |
6686 | return GEN_INT (INTVAL (x) + INTVAL (c)); | |
6687 | else if (GET_CODE (x) != PLUS) | |
6688 | return gen_rtx_PLUS (GET_MODE (x), x, c); | |
6689 | else if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6690 | { | |
6691 | return gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
6692 | GEN_INT (INTVAL (XEXP (x, 1)) + INTVAL (c))); | |
6693 | } | |
6694 | else if (GET_CODE (XEXP (x, 0)) == PLUS | |
6695 | || GET_CODE (XEXP (x, 1)) != PLUS) | |
6696 | { | |
6697 | return gen_rtx_PLUS (GET_MODE (x), | |
6698 | sge_plus_constant (XEXP (x, 0), c), XEXP (x, 1)); | |
6699 | } | |
6700 | else | |
6701 | { | |
6702 | return gen_rtx_PLUS (GET_MODE (x), | |
6703 | sge_plus_constant (XEXP (x, 1), c), XEXP (x, 0)); | |
6704 | } | |
6705 | } | |
6706 | ||
6707 | static rtx | |
6708 | sge_plus (mode, x, y) | |
6709 | enum machine_mode mode; | |
6710 | rtx x, y; | |
6711 | { | |
6712 | while (GET_CODE (y) == PLUS) | |
6713 | { | |
6714 | rtx a = XEXP (y, 0); | |
6715 | if (GET_CODE (a) == CONST_INT) | |
6716 | x = sge_plus_constant (x, a); | |
6717 | else | |
6718 | x = gen_rtx_PLUS (mode, x, a); | |
6719 | y = XEXP (y, 1); | |
6720 | } | |
6721 | if (GET_CODE (y) == CONST_INT) | |
6722 | x = sge_plus_constant (x, y); | |
6723 | else | |
6724 | x = gen_rtx_PLUS (mode, x, y); | |
6725 | return x; | |
6726 | } | |
b4ad7b23 RS |
6727 | \f |
6728 | /* Help detect a giv that is calculated by several consecutive insns; | |
6729 | for example, | |
6730 | giv = biv * M | |
6731 | giv = giv + A | |
6732 | The caller has already identified the first insn P as having a giv as dest; | |
6733 | we check that all other insns that set the same register follow | |
6734 | immediately after P, that they alter nothing else, | |
6735 | and that the result of the last is still a giv. | |
6736 | ||
6737 | The value is 0 if the reg set in P is not really a giv. | |
6738 | Otherwise, the value is the amount gained by eliminating | |
6739 | all the consecutive insns that compute the value. | |
6740 | ||
6741 | FIRST_BENEFIT is the amount gained by eliminating the first insn, P. | |
6742 | SRC_REG is the reg of the biv; DEST_REG is the reg of the giv. | |
6743 | ||
6744 | The coefficients of the ultimate giv value are stored in | |
6745 | *MULT_VAL and *ADD_VAL. */ | |
6746 | ||
6747 | static int | |
6748 | consec_sets_giv (first_benefit, p, src_reg, dest_reg, | |
a07516d3 | 6749 | add_val, mult_val, last_consec_insn) |
b4ad7b23 RS |
6750 | int first_benefit; |
6751 | rtx p; | |
6752 | rtx src_reg; | |
6753 | rtx dest_reg; | |
6754 | rtx *add_val; | |
6755 | rtx *mult_val; | |
a07516d3 | 6756 | rtx *last_consec_insn; |
b4ad7b23 RS |
6757 | { |
6758 | int count; | |
6759 | enum rtx_code code; | |
6760 | int benefit; | |
6761 | rtx temp; | |
6762 | rtx set; | |
6763 | ||
6764 | /* Indicate that this is a giv so that we can update the value produced in | |
6765 | each insn of the multi-insn sequence. | |
6766 | ||
6767 | This induction structure will be used only by the call to | |
6768 | general_induction_var below, so we can allocate it on our stack. | |
6769 | If this is a giv, our caller will replace the induct var entry with | |
6770 | a new induction structure. */ | |
6771 | struct induction *v | |
6772 | = (struct induction *) alloca (sizeof (struct induction)); | |
6773 | v->src_reg = src_reg; | |
6774 | v->mult_val = *mult_val; | |
6775 | v->add_val = *add_val; | |
6776 | v->benefit = first_benefit; | |
6777 | v->cant_derive = 0; | |
6778 | v->derive_adjustment = 0; | |
6779 | ||
3ec2b590 R |
6780 | REG_IV_TYPE (REGNO (dest_reg)) = GENERAL_INDUCT; |
6781 | REG_IV_INFO (REGNO (dest_reg)) = v; | |
b4ad7b23 | 6782 | |
8deb8e2c | 6783 | count = VARRAY_INT (n_times_set, REGNO (dest_reg)) - 1; |
b4ad7b23 RS |
6784 | |
6785 | while (count > 0) | |
6786 | { | |
6787 | p = NEXT_INSN (p); | |
6788 | code = GET_CODE (p); | |
6789 | ||
6790 | /* If libcall, skip to end of call sequence. */ | |
5fd8383e | 6791 | if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX))) |
b4ad7b23 RS |
6792 | p = XEXP (temp, 0); |
6793 | ||
6794 | if (code == INSN | |
6795 | && (set = single_set (p)) | |
6796 | && GET_CODE (SET_DEST (set)) == REG | |
6797 | && SET_DEST (set) == dest_reg | |
45f97e2e RH |
6798 | && (general_induction_var (SET_SRC (set), &src_reg, |
6799 | add_val, mult_val, 0, &benefit) | |
b4ad7b23 | 6800 | /* Giv created by equivalent expression. */ |
5fd8383e | 6801 | || ((temp = find_reg_note (p, REG_EQUAL, NULL_RTX)) |
45f97e2e RH |
6802 | && general_induction_var (XEXP (temp, 0), &src_reg, |
6803 | add_val, mult_val, 0, &benefit))) | |
b4ad7b23 RS |
6804 | && src_reg == v->src_reg) |
6805 | { | |
5fd8383e | 6806 | if (find_reg_note (p, REG_RETVAL, NULL_RTX)) |
b4ad7b23 RS |
6807 | benefit += libcall_benefit (p); |
6808 | ||
6809 | count--; | |
6810 | v->mult_val = *mult_val; | |
6811 | v->add_val = *add_val; | |
6812 | v->benefit = benefit; | |
6813 | } | |
6814 | else if (code != NOTE) | |
6815 | { | |
6816 | /* Allow insns that set something other than this giv to a | |
6817 | constant. Such insns are needed on machines which cannot | |
6818 | include long constants and should not disqualify a giv. */ | |
6819 | if (code == INSN | |
6820 | && (set = single_set (p)) | |
6821 | && SET_DEST (set) != dest_reg | |
6822 | && CONSTANT_P (SET_SRC (set))) | |
6823 | continue; | |
6824 | ||
3ec2b590 | 6825 | REG_IV_TYPE (REGNO (dest_reg)) = UNKNOWN_INDUCT; |
b4ad7b23 RS |
6826 | return 0; |
6827 | } | |
6828 | } | |
6829 | ||
a07516d3 | 6830 | *last_consec_insn = p; |
b4ad7b23 RS |
6831 | return v->benefit; |
6832 | } | |
6833 | \f | |
6834 | /* Return an rtx, if any, that expresses giv G2 as a function of the register | |
6835 | represented by G1. If no such expression can be found, or it is clear that | |
6836 | it cannot possibly be a valid address, 0 is returned. | |
6837 | ||
6838 | To perform the computation, we note that | |
45f97e2e RH |
6839 | G1 = x * v + a and |
6840 | G2 = y * v + b | |
b4ad7b23 RS |
6841 | where `v' is the biv. |
6842 | ||
45f97e2e RH |
6843 | So G2 = (y/b) * G1 + (b - a*y/x). |
6844 | ||
6845 | Note that MULT = y/x. | |
6846 | ||
6847 | Update: A and B are now allowed to be additive expressions such that | |
6848 | B contains all variables in A. That is, computing B-A will not require | |
6849 | subtracting variables. */ | |
6850 | ||
6851 | static rtx | |
6852 | express_from_1 (a, b, mult) | |
6853 | rtx a, b, mult; | |
6854 | { | |
6855 | /* If MULT is zero, then A*MULT is zero, and our expression is B. */ | |
6856 | ||
6857 | if (mult == const0_rtx) | |
6858 | return b; | |
6859 | ||
6860 | /* If MULT is not 1, we cannot handle A with non-constants, since we | |
6861 | would then be required to subtract multiples of the registers in A. | |
6862 | This is theoretically possible, and may even apply to some Fortran | |
6863 | constructs, but it is a lot of work and we do not attempt it here. */ | |
6864 | ||
6865 | if (mult != const1_rtx && GET_CODE (a) != CONST_INT) | |
6866 | return NULL_RTX; | |
6867 | ||
6868 | /* In general these structures are sorted top to bottom (down the PLUS | |
6869 | chain), but not left to right across the PLUS. If B is a higher | |
6870 | order giv than A, we can strip one level and recurse. If A is higher | |
6871 | order, we'll eventually bail out, but won't know that until the end. | |
6872 | If they are the same, we'll strip one level around this loop. */ | |
6873 | ||
6874 | while (GET_CODE (a) == PLUS && GET_CODE (b) == PLUS) | |
6875 | { | |
6876 | rtx ra, rb, oa, ob, tmp; | |
6877 | ||
6878 | ra = XEXP (a, 0), oa = XEXP (a, 1); | |
6879 | if (GET_CODE (ra) == PLUS) | |
6880 | tmp = ra, ra = oa, oa = tmp; | |
6881 | ||
6882 | rb = XEXP (b, 0), ob = XEXP (b, 1); | |
6883 | if (GET_CODE (rb) == PLUS) | |
6884 | tmp = rb, rb = ob, ob = tmp; | |
6885 | ||
6886 | if (rtx_equal_p (ra, rb)) | |
6887 | /* We matched: remove one reg completely. */ | |
6888 | a = oa, b = ob; | |
6889 | else if (GET_CODE (ob) != PLUS && rtx_equal_p (ra, ob)) | |
6890 | /* An alternate match. */ | |
6891 | a = oa, b = rb; | |
6892 | else if (GET_CODE (oa) != PLUS && rtx_equal_p (oa, rb)) | |
6893 | /* An alternate match. */ | |
6894 | a = ra, b = ob; | |
6895 | else | |
6896 | { | |
6897 | /* Indicates an extra register in B. Strip one level from B and | |
6898 | recurse, hoping B was the higher order expression. */ | |
6899 | ob = express_from_1 (a, ob, mult); | |
6900 | if (ob == NULL_RTX) | |
6901 | return NULL_RTX; | |
6902 | return gen_rtx_PLUS (GET_MODE (b), rb, ob); | |
6903 | } | |
6904 | } | |
6905 | ||
6906 | /* Here we are at the last level of A, go through the cases hoping to | |
6907 | get rid of everything but a constant. */ | |
6908 | ||
6909 | if (GET_CODE (a) == PLUS) | |
6910 | { | |
efe3eb65 | 6911 | rtx ra, oa; |
45f97e2e RH |
6912 | |
6913 | ra = XEXP (a, 0), oa = XEXP (a, 1); | |
6914 | if (rtx_equal_p (oa, b)) | |
6915 | oa = ra; | |
6916 | else if (!rtx_equal_p (ra, b)) | |
6917 | return NULL_RTX; | |
6918 | ||
6919 | if (GET_CODE (oa) != CONST_INT) | |
6920 | return NULL_RTX; | |
6921 | ||
6922 | return GEN_INT (-INTVAL (oa) * INTVAL (mult)); | |
6923 | } | |
6924 | else if (GET_CODE (a) == CONST_INT) | |
6925 | { | |
6926 | return plus_constant (b, -INTVAL (a) * INTVAL (mult)); | |
6927 | } | |
6928 | else if (GET_CODE (b) == PLUS) | |
6929 | { | |
6930 | if (rtx_equal_p (a, XEXP (b, 0))) | |
6931 | return XEXP (b, 1); | |
6932 | else if (rtx_equal_p (a, XEXP (b, 1))) | |
6933 | return XEXP (b, 0); | |
6934 | else | |
6935 | return NULL_RTX; | |
6936 | } | |
6937 | else if (rtx_equal_p (a, b)) | |
6938 | return const0_rtx; | |
6939 | ||
6940 | return NULL_RTX; | |
6941 | } | |
b4ad7b23 | 6942 | |
4d87f7a7 | 6943 | rtx |
b4ad7b23 RS |
6944 | express_from (g1, g2) |
6945 | struct induction *g1, *g2; | |
6946 | { | |
6947 | rtx mult, add; | |
6948 | ||
6949 | /* The value that G1 will be multiplied by must be a constant integer. Also, | |
6950 | the only chance we have of getting a valid address is if b*c/a (see above | |
6951 | for notation) is also an integer. */ | |
45f97e2e RH |
6952 | if (GET_CODE (g1->mult_val) == CONST_INT |
6953 | && GET_CODE (g2->mult_val) == CONST_INT) | |
6954 | { | |
6955 | if (g1->mult_val == const0_rtx | |
6956 | || INTVAL (g2->mult_val) % INTVAL (g1->mult_val) != 0) | |
6957 | return NULL_RTX; | |
6958 | mult = GEN_INT (INTVAL (g2->mult_val) / INTVAL (g1->mult_val)); | |
6959 | } | |
6960 | else if (rtx_equal_p (g1->mult_val, g2->mult_val)) | |
6961 | mult = const1_rtx; | |
6962 | else | |
6963 | { | |
6964 | /* ??? Find out if the one is a multiple of the other? */ | |
6965 | return NULL_RTX; | |
6966 | } | |
b4ad7b23 | 6967 | |
45f97e2e | 6968 | add = express_from_1 (g1->add_val, g2->add_val, mult); |
e0485b85 RH |
6969 | if (add == NULL_RTX) |
6970 | { | |
6971 | /* Failed. If we've got a multiplication factor between G1 and G2, | |
6972 | scale G1's addend and try again. */ | |
6973 | if (INTVAL (mult) > 1) | |
6974 | { | |
6975 | rtx g1_add_val = g1->add_val; | |
6976 | if (GET_CODE (g1_add_val) == MULT | |
6977 | && GET_CODE (XEXP (g1_add_val, 1)) == CONST_INT) | |
6978 | { | |
6979 | HOST_WIDE_INT m; | |
6980 | m = INTVAL (mult) * INTVAL (XEXP (g1_add_val, 1)); | |
6981 | g1_add_val = gen_rtx_MULT (GET_MODE (g1_add_val), | |
6982 | XEXP (g1_add_val, 0), GEN_INT (m)); | |
6983 | } | |
6984 | else | |
6985 | { | |
6986 | g1_add_val = gen_rtx_MULT (GET_MODE (g1_add_val), g1_add_val, | |
6987 | mult); | |
6988 | } | |
6989 | ||
6990 | add = express_from_1 (g1_add_val, g2->add_val, const1_rtx); | |
6991 | } | |
6992 | } | |
45f97e2e RH |
6993 | if (add == NULL_RTX) |
6994 | return NULL_RTX; | |
b4ad7b23 RS |
6995 | |
6996 | /* Form simplified final result. */ | |
6997 | if (mult == const0_rtx) | |
6998 | return add; | |
6999 | else if (mult == const1_rtx) | |
7000 | mult = g1->dest_reg; | |
7001 | else | |
38a448ca | 7002 | mult = gen_rtx_MULT (g2->mode, g1->dest_reg, mult); |
b4ad7b23 RS |
7003 | |
7004 | if (add == const0_rtx) | |
7005 | return mult; | |
7006 | else | |
86219cc7 BS |
7007 | { |
7008 | if (GET_CODE (add) == PLUS | |
7009 | && CONSTANT_P (XEXP (add, 1))) | |
7010 | { | |
7011 | rtx tem = XEXP (add, 1); | |
7012 | mult = gen_rtx_PLUS (g2->mode, mult, XEXP (add, 0)); | |
7013 | add = tem; | |
7014 | } | |
7015 | ||
7016 | return gen_rtx_PLUS (g2->mode, mult, add); | |
7017 | } | |
7018 | ||
b4ad7b23 | 7019 | } |
b4ad7b23 | 7020 | \f |
da5a44b3 BS |
7021 | /* Return an rtx, if any, that expresses giv G2 as a function of the register |
7022 | represented by G1. This indicates that G2 should be combined with G1 and | |
7023 | that G2 can use (either directly or via an address expression) a register | |
7024 | used to represent G1. */ | |
b4ad7b23 | 7025 | |
45f97e2e | 7026 | static rtx |
b4ad7b23 RS |
7027 | combine_givs_p (g1, g2) |
7028 | struct induction *g1, *g2; | |
7029 | { | |
45f97e2e | 7030 | rtx tem = express_from (g1, g2); |
b4ad7b23 | 7031 | |
45f97e2e RH |
7032 | /* If these givs are identical, they can be combined. We use the results |
7033 | of express_from because the addends are not in a canonical form, so | |
7034 | rtx_equal_p is a weaker test. */ | |
3ec2b590 R |
7035 | /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the |
7036 | combination to be the other way round. */ | |
7037 | if (tem == g1->dest_reg | |
7038 | && (g1->giv_type == DEST_REG || g2->giv_type == DEST_ADDR)) | |
b4ad7b23 | 7039 | { |
45f97e2e | 7040 | return g1->dest_reg; |
b4ad7b23 RS |
7041 | } |
7042 | ||
b4ad7b23 RS |
7043 | /* If G2 can be expressed as a function of G1 and that function is valid |
7044 | as an address and no more expensive than using a register for G2, | |
7045 | the expression of G2 in terms of G1 can be used. */ | |
45f97e2e RH |
7046 | if (tem != NULL_RTX |
7047 | && g2->giv_type == DEST_ADDR | |
b4ad7b23 | 7048 | && memory_address_p (g2->mem_mode, tem) |
45f97e2e RH |
7049 | /* ??? Looses, especially with -fforce-addr, where *g2->location |
7050 | will always be a register, and so anything more complicated | |
7051 | gets discarded. */ | |
7052 | #if 0 | |
7053 | #ifdef ADDRESS_COST | |
7054 | && ADDRESS_COST (tem) <= ADDRESS_COST (*g2->location) | |
7055 | #else | |
7056 | && rtx_cost (tem, MEM) <= rtx_cost (*g2->location, MEM) | |
7057 | #endif | |
7058 | #endif | |
7059 | ) | |
b4ad7b23 | 7060 | { |
45f97e2e | 7061 | return tem; |
b4ad7b23 | 7062 | } |
b4ad7b23 | 7063 | |
45f97e2e | 7064 | return NULL_RTX; |
b4ad7b23 RS |
7065 | } |
7066 | \f | |
45f97e2e RH |
7067 | struct combine_givs_stats |
7068 | { | |
7069 | int giv_number; | |
7070 | int total_benefit; | |
7071 | }; | |
7072 | ||
7073 | static int | |
f428f252 KG |
7074 | cmp_combine_givs_stats (xp, yp) |
7075 | const PTR xp; | |
7076 | const PTR yp; | |
45f97e2e | 7077 | { |
f428f252 KG |
7078 | const struct combine_givs_stats * const x = |
7079 | (const struct combine_givs_stats *) xp; | |
7080 | const struct combine_givs_stats * const y = | |
7081 | (const struct combine_givs_stats *) yp; | |
45f97e2e RH |
7082 | int d; |
7083 | d = y->total_benefit - x->total_benefit; | |
7084 | /* Stabilize the sort. */ | |
7085 | if (!d) | |
7086 | d = x->giv_number - y->giv_number; | |
7087 | return d; | |
7088 | } | |
7089 | ||
b4ad7b23 RS |
7090 | /* Check all pairs of givs for iv_class BL and see if any can be combined with |
7091 | any other. If so, point SAME to the giv combined with and set NEW_REG to | |
7092 | be an expression (in terms of the other giv's DEST_REG) equivalent to the | |
7093 | giv. Also, update BENEFIT and related fields for cost/benefit analysis. */ | |
7094 | ||
7095 | static void | |
7096 | combine_givs (bl) | |
7097 | struct iv_class *bl; | |
7098 | { | |
ba12c883 RH |
7099 | /* Additional benefit to add for being combined multiple times. */ |
7100 | const int extra_benefit = 3; | |
7101 | ||
29a82058 | 7102 | struct induction *g1, *g2, **giv_array; |
45f97e2e RH |
7103 | int i, j, k, giv_count; |
7104 | struct combine_givs_stats *stats; | |
7105 | rtx *can_combine; | |
b4ad7b23 | 7106 | |
7027f90a JW |
7107 | /* Count givs, because bl->giv_count is incorrect here. */ |
7108 | giv_count = 0; | |
b4ad7b23 | 7109 | for (g1 = bl->giv; g1; g1 = g1->next_iv) |
45f97e2e RH |
7110 | if (!g1->ignore) |
7111 | giv_count++; | |
7027f90a JW |
7112 | |
7113 | giv_array | |
7114 | = (struct induction **) alloca (giv_count * sizeof (struct induction *)); | |
7115 | i = 0; | |
7116 | for (g1 = bl->giv; g1; g1 = g1->next_iv) | |
45f97e2e RH |
7117 | if (!g1->ignore) |
7118 | giv_array[i++] = g1; | |
7027f90a | 7119 | |
67289ea6 MM |
7120 | stats = (struct combine_givs_stats *) xcalloc (giv_count, sizeof (*stats)); |
7121 | can_combine = (rtx *) xcalloc (giv_count, giv_count * sizeof(rtx)); | |
7027f90a JW |
7122 | |
7123 | for (i = 0; i < giv_count; i++) | |
7124 | { | |
45f97e2e | 7125 | int this_benefit; |
ba12c883 | 7126 | rtx single_use; |
45f97e2e | 7127 | |
7027f90a | 7128 | g1 = giv_array[i]; |
ba12c883 RH |
7129 | stats[i].giv_number = i; |
7130 | ||
7131 | /* If a DEST_REG GIV is used only once, do not allow it to combine | |
7132 | with anything, for in doing so we will gain nothing that cannot | |
7133 | be had by simply letting the GIV with which we would have combined | |
7134 | to be reduced on its own. The losage shows up in particular with | |
7135 | DEST_ADDR targets on hosts with reg+reg addressing, though it can | |
7136 | be seen elsewhere as well. */ | |
7137 | if (g1->giv_type == DEST_REG | |
7138 | && (single_use = VARRAY_RTX (reg_single_usage, REGNO (g1->dest_reg))) | |
7139 | && single_use != const0_rtx) | |
7140 | continue; | |
45f97e2e RH |
7141 | |
7142 | this_benefit = g1->benefit; | |
7143 | /* Add an additional weight for zero addends. */ | |
7144 | if (g1->no_const_addval) | |
7145 | this_benefit += 1; | |
ba12c883 | 7146 | |
45f97e2e RH |
7147 | for (j = 0; j < giv_count; j++) |
7148 | { | |
7149 | rtx this_combine; | |
7150 | ||
7151 | g2 = giv_array[j]; | |
7152 | if (g1 != g2 | |
7153 | && (this_combine = combine_givs_p (g1, g2)) != NULL_RTX) | |
7154 | { | |
7155 | can_combine[i*giv_count + j] = this_combine; | |
ba12c883 | 7156 | this_benefit += g2->benefit + extra_benefit; |
45f97e2e RH |
7157 | } |
7158 | } | |
45f97e2e RH |
7159 | stats[i].total_benefit = this_benefit; |
7160 | } | |
7161 | ||
7162 | /* Iterate, combining until we can't. */ | |
7163 | restart: | |
7164 | qsort (stats, giv_count, sizeof(*stats), cmp_combine_givs_stats); | |
7165 | ||
7166 | if (loop_dump_stream) | |
7167 | { | |
7168 | fprintf (loop_dump_stream, "Sorted combine statistics:\n"); | |
7169 | for (k = 0; k < giv_count; k++) | |
7170 | { | |
7171 | g1 = giv_array[stats[k].giv_number]; | |
7172 | if (!g1->combined_with && !g1->same) | |
7173 | fprintf (loop_dump_stream, " {%d, %d}", | |
7174 | INSN_UID (giv_array[stats[k].giv_number]->insn), | |
7175 | stats[k].total_benefit); | |
7176 | } | |
7177 | putc ('\n', loop_dump_stream); | |
7178 | } | |
7179 | ||
7180 | for (k = 0; k < giv_count; k++) | |
7181 | { | |
7182 | int g1_add_benefit = 0; | |
7183 | ||
7184 | i = stats[k].giv_number; | |
7185 | g1 = giv_array[i]; | |
7186 | ||
7187 | /* If it has already been combined, skip. */ | |
7188 | if (g1->combined_with || g1->same) | |
7189 | continue; | |
7190 | ||
7191 | for (j = 0; j < giv_count; j++) | |
7192 | { | |
7193 | g2 = giv_array[j]; | |
7194 | if (g1 != g2 && can_combine[i*giv_count + j] | |
7195 | /* If it has already been combined, skip. */ | |
7196 | && ! g2->same && ! g2->combined_with) | |
7197 | { | |
7198 | int l; | |
7199 | ||
7200 | g2->new_reg = can_combine[i*giv_count + j]; | |
7201 | g2->same = g1; | |
3ec2b590 | 7202 | g1->combined_with++; |
45f97e2e RH |
7203 | g1->lifetime += g2->lifetime; |
7204 | ||
ba12c883 | 7205 | g1_add_benefit += g2->benefit; |
45f97e2e RH |
7206 | |
7207 | /* ??? The new final_[bg]iv_value code does a much better job | |
7208 | of finding replaceable giv's, and hence this code may no | |
7209 | longer be necessary. */ | |
7210 | if (! g2->replaceable && REG_USERVAR_P (g2->dest_reg)) | |
7211 | g1_add_benefit -= copy_cost; | |
7027f90a | 7212 | |
45f97e2e RH |
7213 | /* To help optimize the next set of combinations, remove |
7214 | this giv from the benefits of other potential mates. */ | |
7215 | for (l = 0; l < giv_count; ++l) | |
7216 | { | |
7217 | int m = stats[l].giv_number; | |
7218 | if (can_combine[m*giv_count + j]) | |
ba12c883 | 7219 | stats[l].total_benefit -= g2->benefit + extra_benefit; |
45f97e2e RH |
7220 | } |
7221 | ||
7222 | if (loop_dump_stream) | |
7223 | fprintf (loop_dump_stream, | |
7224 | "giv at %d combined with giv at %d\n", | |
7225 | INSN_UID (g2->insn), INSN_UID (g1->insn)); | |
7226 | } | |
7227 | } | |
7228 | ||
7229 | /* To help optimize the next set of combinations, remove | |
7230 | this giv from the benefits of other potential mates. */ | |
7231 | if (g1->combined_with) | |
7232 | { | |
7233 | for (j = 0; j < giv_count; ++j) | |
7234 | { | |
7235 | int m = stats[j].giv_number; | |
0466bdc4 | 7236 | if (can_combine[m*giv_count + i]) |
ba12c883 | 7237 | stats[j].total_benefit -= g1->benefit + extra_benefit; |
45f97e2e RH |
7238 | } |
7239 | ||
7240 | g1->benefit += g1_add_benefit; | |
7241 | ||
7242 | /* We've finished with this giv, and everything it touched. | |
7243 | Restart the combination so that proper weights for the | |
7244 | rest of the givs are properly taken into account. */ | |
7245 | /* ??? Ideally we would compact the arrays at this point, so | |
7246 | as to not cover old ground. But sanely compacting | |
7247 | can_combine is tricky. */ | |
7248 | goto restart; | |
7249 | } | |
7027f90a | 7250 | } |
67289ea6 MM |
7251 | |
7252 | /* Clean up. */ | |
7253 | free (stats); | |
7254 | free (can_combine); | |
b4ad7b23 RS |
7255 | } |
7256 | \f | |
3ec2b590 R |
7257 | struct recombine_givs_stats |
7258 | { | |
7259 | int giv_number; | |
7260 | int start_luid, end_luid; | |
7261 | }; | |
7262 | ||
7263 | /* Used below as comparison function for qsort. We want a ascending luid | |
7264 | when scanning the array starting at the end, thus the arguments are | |
7265 | used in reverse. */ | |
7266 | static int | |
f428f252 KG |
7267 | cmp_recombine_givs_stats (xp, yp) |
7268 | const PTR xp; | |
7269 | const PTR yp; | |
3ec2b590 | 7270 | { |
f428f252 KG |
7271 | const struct recombine_givs_stats * const x = |
7272 | (const struct recombine_givs_stats *) xp; | |
7273 | const struct recombine_givs_stats * const y = | |
7274 | (const struct recombine_givs_stats *) yp; | |
3ec2b590 R |
7275 | int d; |
7276 | d = y->start_luid - x->start_luid; | |
7277 | /* Stabilize the sort. */ | |
7278 | if (!d) | |
7279 | d = y->giv_number - x->giv_number; | |
7280 | return d; | |
7281 | } | |
7282 | ||
7283 | /* Scan X, which is a part of INSN, for the end of life of a giv. Also | |
7284 | look for the start of life of a giv where the start has not been seen | |
7285 | yet to unlock the search for the end of its life. | |
7286 | Only consider givs that belong to BIV. | |
7287 | Return the total number of lifetime ends that have been found. */ | |
7288 | static int | |
7289 | find_life_end (x, stats, insn, biv) | |
7290 | rtx x, insn, biv; | |
7291 | struct recombine_givs_stats *stats; | |
7292 | { | |
7293 | enum rtx_code code; | |
6f7d635c | 7294 | const char *fmt; |
3ec2b590 R |
7295 | int i, j; |
7296 | int retval; | |
7297 | ||
7298 | code = GET_CODE (x); | |
7299 | switch (code) | |
7300 | { | |
7301 | case SET: | |
7302 | { | |
7303 | rtx reg = SET_DEST (x); | |
7304 | if (GET_CODE (reg) == REG) | |
7305 | { | |
7306 | int regno = REGNO (reg); | |
7307 | struct induction *v = REG_IV_INFO (regno); | |
7308 | ||
7309 | if (REG_IV_TYPE (regno) == GENERAL_INDUCT | |
7310 | && ! v->ignore | |
7311 | && v->src_reg == biv | |
7312 | && stats[v->ix].end_luid <= 0) | |
7313 | { | |
7314 | /* If we see a 0 here for end_luid, it means that we have | |
7315 | scanned the entire loop without finding any use at all. | |
7316 | We must not predicate this code on a start_luid match | |
7317 | since that would make the test fail for givs that have | |
7318 | been hoisted out of inner loops. */ | |
7319 | if (stats[v->ix].end_luid == 0) | |
7320 | { | |
7321 | stats[v->ix].end_luid = stats[v->ix].start_luid; | |
7322 | return 1 + find_life_end (SET_SRC (x), stats, insn, biv); | |
7323 | } | |
7324 | else if (stats[v->ix].start_luid == INSN_LUID (insn)) | |
7325 | stats[v->ix].end_luid = 0; | |
7326 | } | |
7327 | return find_life_end (SET_SRC (x), stats, insn, biv); | |
7328 | } | |
7329 | break; | |
7330 | } | |
7331 | case REG: | |
7332 | { | |
7333 | int regno = REGNO (x); | |
7334 | struct induction *v = REG_IV_INFO (regno); | |
7335 | ||
7336 | if (REG_IV_TYPE (regno) == GENERAL_INDUCT | |
7337 | && ! v->ignore | |
7338 | && v->src_reg == biv | |
7339 | && stats[v->ix].end_luid == 0) | |
7340 | { | |
7341 | while (INSN_UID (insn) >= max_uid_for_loop) | |
7342 | insn = NEXT_INSN (insn); | |
7343 | stats[v->ix].end_luid = INSN_LUID (insn); | |
7344 | return 1; | |
7345 | } | |
7346 | return 0; | |
7347 | } | |
7348 | case LABEL_REF: | |
7349 | case CONST_DOUBLE: | |
7350 | case CONST_INT: | |
7351 | case CONST: | |
7352 | return 0; | |
7353 | default: | |
7354 | break; | |
7355 | } | |
7356 | fmt = GET_RTX_FORMAT (code); | |
7357 | retval = 0; | |
7358 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7359 | { | |
7360 | if (fmt[i] == 'e') | |
7361 | retval += find_life_end (XEXP (x, i), stats, insn, biv); | |
7362 | ||
7363 | else if (fmt[i] == 'E') | |
7364 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7365 | retval += find_life_end (XVECEXP (x, i, j), stats, insn, biv); | |
7366 | } | |
7367 | return retval; | |
7368 | } | |
7369 | ||
7370 | /* For each giv that has been combined with another, look if | |
7371 | we can combine it with the most recently used one instead. | |
7372 | This tends to shorten giv lifetimes, and helps the next step: | |
7373 | try to derive givs from other givs. */ | |
7374 | static void | |
53dc05e4 | 7375 | recombine_givs (bl, loop_start, loop_end, unroll_p) |
3ec2b590 R |
7376 | struct iv_class *bl; |
7377 | rtx loop_start, loop_end; | |
53dc05e4 | 7378 | int unroll_p; |
3ec2b590 R |
7379 | { |
7380 | struct induction *v, **giv_array, *last_giv; | |
7381 | struct recombine_givs_stats *stats; | |
7382 | int giv_count; | |
7383 | int i, rescan; | |
7384 | int ends_need_computing; | |
7385 | ||
7386 | for (giv_count = 0, v = bl->giv; v; v = v->next_iv) | |
7387 | { | |
7388 | if (! v->ignore) | |
7389 | giv_count++; | |
7390 | } | |
7391 | giv_array | |
67289ea6 MM |
7392 | = (struct induction **) xmalloc (giv_count * sizeof (struct induction *)); |
7393 | stats = (struct recombine_givs_stats *) xmalloc (giv_count * sizeof *stats); | |
3ec2b590 R |
7394 | |
7395 | /* Initialize stats and set up the ix field for each giv in stats to name | |
7396 | the corresponding index into stats. */ | |
7397 | for (i = 0, v = bl->giv; v; v = v->next_iv) | |
7398 | { | |
7399 | rtx p; | |
7400 | ||
7401 | if (v->ignore) | |
7402 | continue; | |
7403 | giv_array[i] = v; | |
7404 | stats[i].giv_number = i; | |
7405 | /* If this giv has been hoisted out of an inner loop, use the luid of | |
7406 | the previous insn. */ | |
7407 | for (p = v->insn; INSN_UID (p) >= max_uid_for_loop; ) | |
7408 | p = PREV_INSN (p); | |
7409 | stats[i].start_luid = INSN_LUID (p); | |
3ec2b590 R |
7410 | i++; |
7411 | } | |
7412 | ||
7413 | qsort (stats, giv_count, sizeof(*stats), cmp_recombine_givs_stats); | |
7414 | ||
0aa487d5 R |
7415 | /* Set up the ix field for each giv in stats to name |
7416 | the corresponding index into stats, and | |
7417 | do the actual most-recently-used recombination. */ | |
3ec2b590 R |
7418 | for (last_giv = 0, i = giv_count - 1; i >= 0; i--) |
7419 | { | |
7420 | v = giv_array[stats[i].giv_number]; | |
0aa487d5 | 7421 | v->ix = i; |
3ec2b590 R |
7422 | if (v->same) |
7423 | { | |
7424 | struct induction *old_same = v->same; | |
7425 | rtx new_combine; | |
7426 | ||
7427 | /* combine_givs_p actually says if we can make this transformation. | |
7428 | The other tests are here only to avoid keeping a giv alive | |
7429 | that could otherwise be eliminated. */ | |
7430 | if (last_giv | |
7431 | && ((old_same->maybe_dead && ! old_same->combined_with) | |
7432 | || ! last_giv->maybe_dead | |
7433 | || last_giv->combined_with) | |
7434 | && (new_combine = combine_givs_p (last_giv, v))) | |
7435 | { | |
7436 | old_same->combined_with--; | |
7437 | v->new_reg = new_combine; | |
7438 | v->same = last_giv; | |
7439 | last_giv->combined_with++; | |
7440 | /* No need to update lifetimes / benefits here since we have | |
7441 | already decided what to reduce. */ | |
516e5fa6 RH |
7442 | |
7443 | if (loop_dump_stream) | |
7444 | { | |
7445 | fprintf (loop_dump_stream, | |
7446 | "giv at %d recombined with giv at %d as ", | |
7447 | INSN_UID (v->insn), INSN_UID (last_giv->insn)); | |
7448 | print_rtl (loop_dump_stream, v->new_reg); | |
7449 | putc ('\n', loop_dump_stream); | |
7450 | } | |
3ec2b590 R |
7451 | continue; |
7452 | } | |
7453 | v = v->same; | |
7454 | } | |
7455 | else if (v->giv_type != DEST_REG) | |
7456 | continue; | |
7457 | if (! last_giv | |
7458 | || (last_giv->maybe_dead && ! last_giv->combined_with) | |
7459 | || ! v->maybe_dead | |
7460 | || v->combined_with) | |
7461 | last_giv = v; | |
7462 | } | |
7463 | ||
7464 | ends_need_computing = 0; | |
7465 | /* For each DEST_REG giv, compute lifetime starts, and try to compute | |
7466 | lifetime ends from regscan info. */ | |
0aa487d5 | 7467 | for (i = giv_count - 1; i >= 0; i--) |
3ec2b590 | 7468 | { |
0aa487d5 | 7469 | v = giv_array[stats[i].giv_number]; |
3ec2b590 R |
7470 | if (v->ignore) |
7471 | continue; | |
7472 | if (v->giv_type == DEST_ADDR) | |
7473 | { | |
7474 | /* Loop unrolling of an inner loop can even create new DEST_REG | |
7475 | givs. */ | |
7476 | rtx p; | |
7477 | for (p = v->insn; INSN_UID (p) >= max_uid_for_loop; ) | |
7478 | p = PREV_INSN (p); | |
7479 | stats[i].start_luid = stats[i].end_luid = INSN_LUID (p); | |
7480 | if (p != v->insn) | |
7481 | stats[i].end_luid++; | |
7482 | } | |
7483 | else /* v->giv_type == DEST_REG */ | |
7484 | { | |
7485 | if (v->last_use) | |
7486 | { | |
7487 | stats[i].start_luid = INSN_LUID (v->insn); | |
7488 | stats[i].end_luid = INSN_LUID (v->last_use); | |
7489 | } | |
7490 | else if (INSN_UID (v->insn) >= max_uid_for_loop) | |
7491 | { | |
7492 | rtx p; | |
7493 | /* This insn has been created by loop optimization on an inner | |
7494 | loop. We don't have a proper start_luid that will match | |
7495 | when we see the first set. But we do know that there will | |
7496 | be no use before the set, so we can set end_luid to 0 so that | |
7497 | we'll start looking for the last use right away. */ | |
7498 | for (p = PREV_INSN (v->insn); INSN_UID (p) >= max_uid_for_loop; ) | |
7499 | p = PREV_INSN (p); | |
7500 | stats[i].start_luid = INSN_LUID (p); | |
7501 | stats[i].end_luid = 0; | |
7502 | ends_need_computing++; | |
7503 | } | |
7504 | else | |
7505 | { | |
7506 | int regno = REGNO (v->dest_reg); | |
7507 | int count = VARRAY_INT (n_times_set, regno) - 1; | |
7508 | rtx p = v->insn; | |
7509 | ||
7510 | /* Find the first insn that sets the giv, so that we can verify | |
7511 | if this giv's lifetime wraps around the loop. We also need | |
7512 | the luid of the first setting insn in order to detect the | |
7513 | last use properly. */ | |
7514 | while (count) | |
7515 | { | |
7516 | p = prev_nonnote_insn (p); | |
7517 | if (reg_set_p (v->dest_reg, p)) | |
7518 | count--; | |
7519 | } | |
7520 | ||
7521 | stats[i].start_luid = INSN_LUID (p); | |
7522 | if (stats[i].start_luid > uid_luid[REGNO_FIRST_UID (regno)]) | |
7523 | { | |
7524 | stats[i].end_luid = -1; | |
7525 | ends_need_computing++; | |
7526 | } | |
7527 | else | |
7528 | { | |
7529 | stats[i].end_luid = uid_luid[REGNO_LAST_UID (regno)]; | |
7530 | if (stats[i].end_luid > INSN_LUID (loop_end)) | |
7531 | { | |
7532 | stats[i].end_luid = -1; | |
7533 | ends_need_computing++; | |
7534 | } | |
7535 | } | |
7536 | } | |
7537 | } | |
3ec2b590 R |
7538 | } |
7539 | ||
7540 | /* If the regscan information was unconclusive for one or more DEST_REG | |
7541 | givs, scan the all insn in the loop to find out lifetime ends. */ | |
7542 | if (ends_need_computing) | |
7543 | { | |
7544 | rtx biv = bl->biv->src_reg; | |
7545 | rtx p = loop_end; | |
7546 | ||
7547 | do | |
7548 | { | |
7549 | if (p == loop_start) | |
7550 | p = loop_end; | |
7551 | p = PREV_INSN (p); | |
7552 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
7553 | continue; | |
7554 | ends_need_computing -= find_life_end (PATTERN (p), stats, p, biv); | |
7555 | } | |
7556 | while (ends_need_computing); | |
7557 | } | |
7558 | ||
7559 | /* Set start_luid back to the last insn that sets the giv. This allows | |
7560 | more combinations. */ | |
0aa487d5 | 7561 | for (i = giv_count - 1; i >= 0; i--) |
3ec2b590 | 7562 | { |
0aa487d5 | 7563 | v = giv_array[stats[i].giv_number]; |
3ec2b590 R |
7564 | if (v->ignore) |
7565 | continue; | |
7566 | if (INSN_UID (v->insn) < max_uid_for_loop) | |
7567 | stats[i].start_luid = INSN_LUID (v->insn); | |
3ec2b590 R |
7568 | } |
7569 | ||
7570 | /* Now adjust lifetime ends by taking combined givs into account. */ | |
0aa487d5 | 7571 | for (i = giv_count - 1; i >= 0; i--) |
3ec2b590 R |
7572 | { |
7573 | unsigned luid; | |
7574 | int j; | |
7575 | ||
0aa487d5 | 7576 | v = giv_array[stats[i].giv_number]; |
3ec2b590 R |
7577 | if (v->ignore) |
7578 | continue; | |
7579 | if (v->same && ! v->same->ignore) | |
7580 | { | |
7581 | j = v->same->ix; | |
7582 | luid = stats[i].start_luid; | |
7583 | /* Use unsigned arithmetic to model loop wrap-around. */ | |
7584 | if (luid - stats[j].start_luid | |
7585 | > (unsigned) stats[j].end_luid - stats[j].start_luid) | |
7586 | stats[j].end_luid = luid; | |
7587 | } | |
3ec2b590 R |
7588 | } |
7589 | ||
7590 | qsort (stats, giv_count, sizeof(*stats), cmp_recombine_givs_stats); | |
7591 | ||
7592 | /* Try to derive DEST_REG givs from previous DEST_REG givs with the | |
7593 | same mult_val and non-overlapping lifetime. This reduces register | |
7594 | pressure. | |
7595 | Once we find a DEST_REG giv that is suitable to derive others from, | |
7596 | we set last_giv to this giv, and try to derive as many other DEST_REG | |
7597 | givs from it without joining overlapping lifetimes. If we then | |
7598 | encounter a DEST_REG giv that we can't derive, we set rescan to the | |
7599 | index for this giv (unless rescan is already set). | |
7600 | When we are finished with the current LAST_GIV (i.e. the inner loop | |
7601 | terminates), we start again with rescan, which then becomes the new | |
7602 | LAST_GIV. */ | |
7603 | for (i = giv_count - 1; i >= 0; i = rescan) | |
7604 | { | |
a544cfd2 | 7605 | int life_start = 0, life_end = 0; |
3ec2b590 R |
7606 | |
7607 | for (last_giv = 0, rescan = -1; i >= 0; i--) | |
7608 | { | |
7609 | rtx sum; | |
7610 | ||
7611 | v = giv_array[stats[i].giv_number]; | |
4d87f7a7 | 7612 | if (v->giv_type != DEST_REG || v->derived_from || v->same) |
3ec2b590 R |
7613 | continue; |
7614 | if (! last_giv) | |
7615 | { | |
7221f080 R |
7616 | /* Don't use a giv that's likely to be dead to derive |
7617 | others - that would be likely to keep that giv alive. */ | |
7618 | if (! v->maybe_dead || v->combined_with) | |
7619 | { | |
7620 | last_giv = v; | |
7621 | life_start = stats[i].start_luid; | |
7622 | life_end = stats[i].end_luid; | |
7623 | } | |
3ec2b590 R |
7624 | continue; |
7625 | } | |
7626 | /* Use unsigned arithmetic to model loop wrap around. */ | |
7627 | if (((unsigned) stats[i].start_luid - life_start | |
7628 | >= (unsigned) life_end - life_start) | |
7629 | && ((unsigned) stats[i].end_luid - life_start | |
7221f080 R |
7630 | > (unsigned) life_end - life_start) |
7631 | /* Check that the giv insn we're about to use for deriving | |
7632 | precedes all uses of that giv. Note that initializing the | |
7633 | derived giv would defeat the purpose of reducing register | |
7634 | pressure. | |
7635 | ??? We could arrange to move the insn. */ | |
7636 | && ((unsigned) stats[i].end_luid - INSN_LUID (loop_start) | |
7637 | > (unsigned) stats[i].start_luid - INSN_LUID (loop_start)) | |
3ec2b590 R |
7638 | && rtx_equal_p (last_giv->mult_val, v->mult_val) |
7639 | /* ??? Could handle libcalls, but would need more logic. */ | |
7640 | && ! find_reg_note (v->insn, REG_RETVAL, NULL_RTX) | |
7641 | /* We would really like to know if for any giv that v | |
7642 | is combined with, v->insn or any intervening biv increment | |
7643 | dominates that combined giv. However, we | |
7644 | don't have this detailed control flow information. | |
7645 | N.B. since last_giv will be reduced, it is valid | |
7646 | anywhere in the loop, so we don't need to check the | |
7221f080 R |
7647 | validity of last_giv. |
7648 | We rely here on the fact that v->always_executed implies that | |
7649 | there is no jump to someplace else in the loop before the | |
7650 | giv insn, and hence any insn that is executed before the | |
7651 | giv insn in the loop will have a lower luid. */ | |
3ec2b590 R |
7652 | && (v->always_executed || ! v->combined_with) |
7653 | && (sum = express_from (last_giv, v)) | |
53dc05e4 R |
7654 | /* Make sure we don't make the add more expensive. ADD_COST |
7655 | doesn't take different costs of registers and constants into | |
7656 | account, so compare the cost of the actual SET_SRCs. */ | |
7657 | && (rtx_cost (sum, SET) | |
7658 | <= rtx_cost (SET_SRC (single_set (v->insn)), SET)) | |
7659 | /* ??? unroll can't understand anything but reg + const_int | |
7660 | sums. It would be cleaner to fix unroll. */ | |
7661 | && ((GET_CODE (sum) == PLUS | |
7662 | && GET_CODE (XEXP (sum, 0)) == REG | |
7663 | && GET_CODE (XEXP (sum, 1)) == CONST_INT) | |
7664 | || ! unroll_p) | |
3ec2b590 | 7665 | && validate_change (v->insn, &PATTERN (v->insn), |
743f9f5d | 7666 | gen_rtx_SET (VOIDmode, v->dest_reg, sum), 0)) |
3ec2b590 | 7667 | { |
4d87f7a7 | 7668 | v->derived_from = last_giv; |
3ec2b590 | 7669 | life_end = stats[i].end_luid; |
516e5fa6 RH |
7670 | |
7671 | if (loop_dump_stream) | |
7672 | { | |
7673 | fprintf (loop_dump_stream, | |
7674 | "giv at %d derived from %d as ", | |
7675 | INSN_UID (v->insn), INSN_UID (last_giv->insn)); | |
743f9f5d | 7676 | print_rtl (loop_dump_stream, sum); |
516e5fa6 RH |
7677 | putc ('\n', loop_dump_stream); |
7678 | } | |
3ec2b590 R |
7679 | } |
7680 | else if (rescan < 0) | |
7681 | rescan = i; | |
7682 | } | |
7683 | } | |
67289ea6 MM |
7684 | |
7685 | /* Clean up. */ | |
7686 | free (giv_array); | |
7687 | free (stats); | |
3ec2b590 R |
7688 | } |
7689 | \f | |
b4ad7b23 RS |
7690 | /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */ |
7691 | ||
7692 | void | |
7693 | emit_iv_add_mult (b, m, a, reg, insert_before) | |
7694 | rtx b; /* initial value of basic induction variable */ | |
7695 | rtx m; /* multiplicative constant */ | |
7696 | rtx a; /* additive constant */ | |
7697 | rtx reg; /* destination register */ | |
7698 | rtx insert_before; | |
7699 | { | |
7700 | rtx seq; | |
7701 | rtx result; | |
7702 | ||
7703 | /* Prevent unexpected sharing of these rtx. */ | |
7704 | a = copy_rtx (a); | |
7705 | b = copy_rtx (b); | |
7706 | ||
0f41302f | 7707 | /* Increase the lifetime of any invariants moved further in code. */ |
b4ad7b23 RS |
7708 | update_reg_last_use (a, insert_before); |
7709 | update_reg_last_use (b, insert_before); | |
7710 | update_reg_last_use (m, insert_before); | |
7711 | ||
7712 | start_sequence (); | |
7713 | result = expand_mult_add (b, reg, m, a, GET_MODE (reg), 0); | |
7714 | if (reg != result) | |
7715 | emit_move_insn (reg, result); | |
7716 | seq = gen_sequence (); | |
7717 | end_sequence (); | |
7718 | ||
7719 | emit_insn_before (seq, insert_before); | |
9ae8ffe7 | 7720 | |
00116a7b RH |
7721 | /* It is entirely possible that the expansion created lots of new |
7722 | registers. Iterate over the sequence we just created and | |
7723 | record them all. */ | |
7724 | ||
7725 | if (GET_CODE (seq) == SEQUENCE) | |
7726 | { | |
7727 | int i; | |
7728 | for (i = 0; i < XVECLEN (seq, 0); ++i) | |
7729 | { | |
7730 | rtx set = single_set (XVECEXP (seq, 0, i)); | |
7731 | if (set && GET_CODE (SET_DEST (set)) == REG) | |
7732 | record_base_value (REGNO (SET_DEST (set)), SET_SRC (set), 0); | |
7733 | } | |
7734 | } | |
7735 | else if (GET_CODE (seq) == SET | |
7736 | && GET_CODE (SET_DEST (seq)) == REG) | |
7737 | record_base_value (REGNO (SET_DEST (seq)), SET_SRC (seq), 0); | |
b4ad7b23 RS |
7738 | } |
7739 | \f | |
7740 | /* Test whether A * B can be computed without | |
7741 | an actual multiply insn. Value is 1 if so. */ | |
7742 | ||
7743 | static int | |
7744 | product_cheap_p (a, b) | |
7745 | rtx a; | |
7746 | rtx b; | |
7747 | { | |
7748 | int i; | |
7749 | rtx tmp; | |
7750 | struct obstack *old_rtl_obstack = rtl_obstack; | |
7751 | char *storage = (char *) obstack_alloc (&temp_obstack, 0); | |
7752 | int win = 1; | |
7753 | ||
0f41302f | 7754 | /* If only one is constant, make it B. */ |
b4ad7b23 RS |
7755 | if (GET_CODE (a) == CONST_INT) |
7756 | tmp = a, a = b, b = tmp; | |
7757 | ||
7758 | /* If first constant, both constant, so don't need multiply. */ | |
7759 | if (GET_CODE (a) == CONST_INT) | |
7760 | return 1; | |
7761 | ||
7762 | /* If second not constant, neither is constant, so would need multiply. */ | |
7763 | if (GET_CODE (b) != CONST_INT) | |
7764 | return 0; | |
7765 | ||
7766 | /* One operand is constant, so might not need multiply insn. Generate the | |
7767 | code for the multiply and see if a call or multiply, or long sequence | |
7768 | of insns is generated. */ | |
7769 | ||
7770 | rtl_obstack = &temp_obstack; | |
7771 | start_sequence (); | |
5fd8383e | 7772 | expand_mult (GET_MODE (a), a, b, NULL_RTX, 0); |
b4ad7b23 RS |
7773 | tmp = gen_sequence (); |
7774 | end_sequence (); | |
7775 | ||
7776 | if (GET_CODE (tmp) == SEQUENCE) | |
7777 | { | |
7778 | if (XVEC (tmp, 0) == 0) | |
7779 | win = 1; | |
7780 | else if (XVECLEN (tmp, 0) > 3) | |
7781 | win = 0; | |
7782 | else | |
7783 | for (i = 0; i < XVECLEN (tmp, 0); i++) | |
7784 | { | |
7785 | rtx insn = XVECEXP (tmp, 0, i); | |
7786 | ||
7787 | if (GET_CODE (insn) != INSN | |
7788 | || (GET_CODE (PATTERN (insn)) == SET | |
7789 | && GET_CODE (SET_SRC (PATTERN (insn))) == MULT) | |
7790 | || (GET_CODE (PATTERN (insn)) == PARALLEL | |
7791 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET | |
7792 | && GET_CODE (SET_SRC (XVECEXP (PATTERN (insn), 0, 0))) == MULT)) | |
7793 | { | |
7794 | win = 0; | |
7795 | break; | |
7796 | } | |
7797 | } | |
7798 | } | |
7799 | else if (GET_CODE (tmp) == SET | |
7800 | && GET_CODE (SET_SRC (tmp)) == MULT) | |
7801 | win = 0; | |
7802 | else if (GET_CODE (tmp) == PARALLEL | |
7803 | && GET_CODE (XVECEXP (tmp, 0, 0)) == SET | |
7804 | && GET_CODE (SET_SRC (XVECEXP (tmp, 0, 0))) == MULT) | |
7805 | win = 0; | |
7806 | ||
7807 | /* Free any storage we obtained in generating this multiply and restore rtl | |
7808 | allocation to its normal obstack. */ | |
7809 | obstack_free (&temp_obstack, storage); | |
7810 | rtl_obstack = old_rtl_obstack; | |
7811 | ||
7812 | return win; | |
7813 | } | |
7814 | \f | |
7815 | /* Check to see if loop can be terminated by a "decrement and branch until | |
7816 | zero" instruction. If so, add a REG_NONNEG note to the branch insn if so. | |
7817 | Also try reversing an increment loop to a decrement loop | |
7818 | to see if the optimization can be performed. | |
7819 | Value is nonzero if optimization was performed. */ | |
7820 | ||
7821 | /* This is useful even if the architecture doesn't have such an insn, | |
7822 | because it might change a loops which increments from 0 to n to a loop | |
7823 | which decrements from n to 0. A loop that decrements to zero is usually | |
7824 | faster than one that increments from zero. */ | |
7825 | ||
7826 | /* ??? This could be rewritten to use some of the loop unrolling procedures, | |
7827 | such as approx_final_value, biv_total_increment, loop_iterations, and | |
7828 | final_[bg]iv_value. */ | |
7829 | ||
7830 | static int | |
a2be868f MH |
7831 | check_dbra_loop (loop, insn_count) |
7832 | struct loop *loop; | |
b4ad7b23 | 7833 | int insn_count; |
b4ad7b23 RS |
7834 | { |
7835 | struct iv_class *bl; | |
7836 | rtx reg; | |
7837 | rtx jump_label; | |
7838 | rtx final_value; | |
7839 | rtx start_value; | |
b4ad7b23 RS |
7840 | rtx new_add_val; |
7841 | rtx comparison; | |
7842 | rtx before_comparison; | |
7843 | rtx p; | |
0628fde6 JW |
7844 | rtx jump; |
7845 | rtx first_compare; | |
7846 | int compare_and_branch; | |
a2be868f MH |
7847 | rtx loop_start = loop->start; |
7848 | rtx loop_end = loop->end; | |
7849 | struct loop_info *loop_info = loop->info; | |
b4ad7b23 RS |
7850 | |
7851 | /* If last insn is a conditional branch, and the insn before tests a | |
7852 | register value, try to optimize it. Otherwise, we can't do anything. */ | |
7853 | ||
0628fde6 JW |
7854 | jump = PREV_INSN (loop_end); |
7855 | comparison = get_condition_for_loop (jump); | |
b4ad7b23 RS |
7856 | if (comparison == 0) |
7857 | return 0; | |
7858 | ||
0628fde6 JW |
7859 | /* Try to compute whether the compare/branch at the loop end is one or |
7860 | two instructions. */ | |
7861 | get_condition (jump, &first_compare); | |
7862 | if (first_compare == jump) | |
7863 | compare_and_branch = 1; | |
7864 | else if (first_compare == prev_nonnote_insn (jump)) | |
7865 | compare_and_branch = 2; | |
7866 | else | |
7867 | return 0; | |
7868 | ||
b4ad7b23 RS |
7869 | /* Check all of the bivs to see if the compare uses one of them. |
7870 | Skip biv's set more than once because we can't guarantee that | |
7871 | it will be zero on the last iteration. Also skip if the biv is | |
7872 | used between its update and the test insn. */ | |
7873 | ||
7874 | for (bl = loop_iv_list; bl; bl = bl->next) | |
7875 | { | |
7876 | if (bl->biv_count == 1 | |
6979065c | 7877 | && ! bl->biv->maybe_multiple |
b4ad7b23 RS |
7878 | && bl->biv->dest_reg == XEXP (comparison, 0) |
7879 | && ! reg_used_between_p (regno_reg_rtx[bl->regno], bl->biv->insn, | |
0628fde6 | 7880 | first_compare)) |
b4ad7b23 RS |
7881 | break; |
7882 | } | |
7883 | ||
7884 | if (! bl) | |
7885 | return 0; | |
7886 | ||
7887 | /* Look for the case where the basic induction variable is always | |
7888 | nonnegative, and equals zero on the last iteration. | |
7889 | In this case, add a reg_note REG_NONNEG, which allows the | |
7890 | m68k DBRA instruction to be used. */ | |
7891 | ||
7892 | if (((GET_CODE (comparison) == GT | |
7893 | && GET_CODE (XEXP (comparison, 1)) == CONST_INT | |
7894 | && INTVAL (XEXP (comparison, 1)) == -1) | |
7895 | || (GET_CODE (comparison) == NE && XEXP (comparison, 1) == const0_rtx)) | |
7896 | && GET_CODE (bl->biv->add_val) == CONST_INT | |
7897 | && INTVAL (bl->biv->add_val) < 0) | |
7898 | { | |
7899 | /* Initial value must be greater than 0, | |
7900 | init_val % -dec_value == 0 to ensure that it equals zero on | |
7901 | the last iteration */ | |
7902 | ||
7903 | if (GET_CODE (bl->initial_value) == CONST_INT | |
7904 | && INTVAL (bl->initial_value) > 0 | |
db3cf6fb MS |
7905 | && (INTVAL (bl->initial_value) |
7906 | % (-INTVAL (bl->biv->add_val))) == 0) | |
b4ad7b23 RS |
7907 | { |
7908 | /* register always nonnegative, add REG_NOTE to branch */ | |
7909 | REG_NOTES (PREV_INSN (loop_end)) | |
38a448ca RH |
7910 | = gen_rtx_EXPR_LIST (REG_NONNEG, NULL_RTX, |
7911 | REG_NOTES (PREV_INSN (loop_end))); | |
b4ad7b23 RS |
7912 | bl->nonneg = 1; |
7913 | ||
7914 | return 1; | |
7915 | } | |
7916 | ||
7917 | /* If the decrement is 1 and the value was tested as >= 0 before | |
7918 | the loop, then we can safely optimize. */ | |
7919 | for (p = loop_start; p; p = PREV_INSN (p)) | |
7920 | { | |
7921 | if (GET_CODE (p) == CODE_LABEL) | |
7922 | break; | |
7923 | if (GET_CODE (p) != JUMP_INSN) | |
7924 | continue; | |
7925 | ||
7926 | before_comparison = get_condition_for_loop (p); | |
7927 | if (before_comparison | |
7928 | && XEXP (before_comparison, 0) == bl->biv->dest_reg | |
7929 | && GET_CODE (before_comparison) == LT | |
7930 | && XEXP (before_comparison, 1) == const0_rtx | |
7931 | && ! reg_set_between_p (bl->biv->dest_reg, p, loop_start) | |
7932 | && INTVAL (bl->biv->add_val) == -1) | |
7933 | { | |
7934 | REG_NOTES (PREV_INSN (loop_end)) | |
38a448ca RH |
7935 | = gen_rtx_EXPR_LIST (REG_NONNEG, NULL_RTX, |
7936 | REG_NOTES (PREV_INSN (loop_end))); | |
b4ad7b23 RS |
7937 | bl->nonneg = 1; |
7938 | ||
7939 | return 1; | |
7940 | } | |
7941 | } | |
7942 | } | |
ef178af3 ZW |
7943 | else if (GET_CODE (bl->biv->add_val) == CONST_INT |
7944 | && INTVAL (bl->biv->add_val) > 0) | |
b4ad7b23 RS |
7945 | { |
7946 | /* Try to change inc to dec, so can apply above optimization. */ | |
7947 | /* Can do this if: | |
7948 | all registers modified are induction variables or invariant, | |
7949 | all memory references have non-overlapping addresses | |
7950 | (obviously true if only one write) | |
7951 | allow 2 insns for the compare/jump at the end of the loop. */ | |
45cc060e JW |
7952 | /* Also, we must avoid any instructions which use both the reversed |
7953 | biv and another biv. Such instructions will fail if the loop is | |
7954 | reversed. We meet this condition by requiring that either | |
7955 | no_use_except_counting is true, or else that there is only | |
7956 | one biv. */ | |
b4ad7b23 RS |
7957 | int num_nonfixed_reads = 0; |
7958 | /* 1 if the iteration var is used only to count iterations. */ | |
7959 | int no_use_except_counting = 0; | |
b418c26e JW |
7960 | /* 1 if the loop has no memory store, or it has a single memory store |
7961 | which is reversible. */ | |
7962 | int reversible_mem_store = 1; | |
b4ad7b23 | 7963 | |
b4ad7b23 | 7964 | if (bl->giv_count == 0 |
a2be868f | 7965 | && ! uid_loop[INSN_UID (loop_start)]->exit_count) |
b4ad7b23 RS |
7966 | { |
7967 | rtx bivreg = regno_reg_rtx[bl->regno]; | |
7968 | ||
7969 | /* If there are no givs for this biv, and the only exit is the | |
38e01259 | 7970 | fall through at the end of the loop, then |
b4ad7b23 RS |
7971 | see if perhaps there are no uses except to count. */ |
7972 | no_use_except_counting = 1; | |
7973 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) | |
7974 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
7975 | { | |
7976 | rtx set = single_set (p); | |
7977 | ||
7978 | if (set && GET_CODE (SET_DEST (set)) == REG | |
7979 | && REGNO (SET_DEST (set)) == bl->regno) | |
7980 | /* An insn that sets the biv is okay. */ | |
7981 | ; | |
59487769 JL |
7982 | else if ((p == prev_nonnote_insn (prev_nonnote_insn (loop_end)) |
7983 | || p == prev_nonnote_insn (loop_end)) | |
7984 | && reg_mentioned_p (bivreg, PATTERN (p))) | |
7985 | { | |
7986 | /* If either of these insns uses the biv and sets a pseudo | |
7987 | that has more than one usage, then the biv has uses | |
7988 | other than counting since it's used to derive a value | |
7989 | that is used more than one time. */ | |
84832317 MM |
7990 | int note_set_pseudo_multiple_uses_retval = 0; |
7991 | note_stores (PATTERN (p), note_set_pseudo_multiple_uses, | |
7992 | ¬e_set_pseudo_multiple_uses_retval); | |
59487769 JL |
7993 | if (note_set_pseudo_multiple_uses_retval) |
7994 | { | |
7995 | no_use_except_counting = 0; | |
7996 | break; | |
7997 | } | |
7998 | } | |
b4ad7b23 | 7999 | else if (reg_mentioned_p (bivreg, PATTERN (p))) |
b4ad7b23 RS |
8000 | { |
8001 | no_use_except_counting = 0; | |
8002 | break; | |
8003 | } | |
8004 | } | |
8005 | } | |
8006 | ||
c48ba252 R |
8007 | if (no_use_except_counting) |
8008 | ; /* no need to worry about MEMs. */ | |
8009 | else if (num_mem_sets <= 1) | |
8010 | { | |
8011 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) | |
8012 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
8013 | num_nonfixed_reads += count_nonfixed_reads (PATTERN (p)); | |
8014 | ||
8015 | /* If the loop has a single store, and the destination address is | |
8016 | invariant, then we can't reverse the loop, because this address | |
8017 | might then have the wrong value at loop exit. | |
8018 | This would work if the source was invariant also, however, in that | |
8019 | case, the insn should have been moved out of the loop. */ | |
8020 | ||
8021 | if (num_mem_sets == 1) | |
2d4fde68 R |
8022 | { |
8023 | struct induction *v; | |
8024 | ||
8025 | reversible_mem_store | |
8026 | = (! unknown_address_altered | |
14a774a9 | 8027 | && ! unknown_constant_address_altered |
ef1d4aec | 8028 | && ! invariant_p (XEXP (XEXP (loop_store_mems, 0), 0))); |
2d4fde68 R |
8029 | |
8030 | /* If the store depends on a register that is set after the | |
8031 | store, it depends on the initial value, and is thus not | |
8032 | reversible. */ | |
8033 | for (v = bl->giv; reversible_mem_store && v; v = v->next_iv) | |
8034 | { | |
8035 | if (v->giv_type == DEST_REG | |
8036 | && reg_mentioned_p (v->dest_reg, | |
8037 | XEXP (loop_store_mems, 0)) | |
1cb1fe66 | 8038 | && loop_insn_first_p (first_loop_store_insn, v->insn)) |
2d4fde68 R |
8039 | reversible_mem_store = 0; |
8040 | } | |
8041 | } | |
c48ba252 R |
8042 | } |
8043 | else | |
8044 | return 0; | |
b418c26e | 8045 | |
b4ad7b23 RS |
8046 | /* This code only acts for innermost loops. Also it simplifies |
8047 | the memory address check by only reversing loops with | |
8048 | zero or one memory access. | |
8049 | Two memory accesses could involve parts of the same array, | |
c48ba252 R |
8050 | and that can't be reversed. |
8051 | If the biv is used only for counting, than we don't need to worry | |
8052 | about all these things. */ | |
8053 | ||
8054 | if ((num_nonfixed_reads <= 1 | |
3c748bb6 MH |
8055 | && ! loop_info->has_call |
8056 | && ! loop_info->has_volatile | |
c48ba252 R |
8057 | && reversible_mem_store |
8058 | && (bl->giv_count + bl->biv_count + num_mem_sets | |
8059 | + num_movables + compare_and_branch == insn_count) | |
8060 | && (bl == loop_iv_list && bl->next == 0)) | |
8061 | || no_use_except_counting) | |
b4ad7b23 | 8062 | { |
b4ad7b23 RS |
8063 | rtx tem; |
8064 | ||
8065 | /* Loop can be reversed. */ | |
8066 | if (loop_dump_stream) | |
8067 | fprintf (loop_dump_stream, "Can reverse loop\n"); | |
8068 | ||
8069 | /* Now check other conditions: | |
e9a25f70 | 8070 | |
956d6950 JL |
8071 | The increment must be a constant, as must the initial value, |
8072 | and the comparison code must be LT. | |
b4ad7b23 RS |
8073 | |
8074 | This test can probably be improved since +/- 1 in the constant | |
8075 | can be obtained by changing LT to LE and vice versa; this is | |
8076 | confusing. */ | |
8077 | ||
e9a25f70 | 8078 | if (comparison |
c48ba252 R |
8079 | /* for constants, LE gets turned into LT */ |
8080 | && (GET_CODE (comparison) == LT | |
8081 | || (GET_CODE (comparison) == LE | |
8082 | && no_use_except_counting))) | |
b4ad7b23 | 8083 | { |
f428f252 | 8084 | HOST_WIDE_INT add_val, add_adjust, comparison_val = 0; |
c48ba252 R |
8085 | rtx initial_value, comparison_value; |
8086 | int nonneg = 0; | |
8087 | enum rtx_code cmp_code; | |
8088 | int comparison_const_width; | |
8089 | unsigned HOST_WIDE_INT comparison_sign_mask; | |
e9a25f70 JL |
8090 | |
8091 | add_val = INTVAL (bl->biv->add_val); | |
c48ba252 | 8092 | comparison_value = XEXP (comparison, 1); |
2c74fb2b AS |
8093 | if (GET_MODE (comparison_value) == VOIDmode) |
8094 | comparison_const_width | |
8095 | = GET_MODE_BITSIZE (GET_MODE (XEXP (comparison, 0))); | |
8096 | else | |
8097 | comparison_const_width | |
8098 | = GET_MODE_BITSIZE (GET_MODE (comparison_value)); | |
c48ba252 R |
8099 | if (comparison_const_width > HOST_BITS_PER_WIDE_INT) |
8100 | comparison_const_width = HOST_BITS_PER_WIDE_INT; | |
8101 | comparison_sign_mask | |
8102 | = (unsigned HOST_WIDE_INT)1 << (comparison_const_width - 1); | |
8103 | ||
3aa94dc8 JL |
8104 | /* If the comparison value is not a loop invariant, then we |
8105 | can not reverse this loop. | |
8106 | ||
8107 | ??? If the insns which initialize the comparison value as | |
8108 | a whole compute an invariant result, then we could move | |
8109 | them out of the loop and proceed with loop reversal. */ | |
9231189b | 8110 | if (!invariant_p (comparison_value)) |
3aa94dc8 JL |
8111 | return 0; |
8112 | ||
c48ba252 R |
8113 | if (GET_CODE (comparison_value) == CONST_INT) |
8114 | comparison_val = INTVAL (comparison_value); | |
e9a25f70 JL |
8115 | initial_value = bl->initial_value; |
8116 | ||
a8decb2c JL |
8117 | /* Normalize the initial value if it is an integer and |
8118 | has no other use except as a counter. This will allow | |
8119 | a few more loops to be reversed. */ | |
8120 | if (no_use_except_counting | |
c48ba252 | 8121 | && GET_CODE (comparison_value) == CONST_INT |
a8decb2c | 8122 | && GET_CODE (initial_value) == CONST_INT) |
e9a25f70 JL |
8123 | { |
8124 | comparison_val = comparison_val - INTVAL (bl->initial_value); | |
c48ba252 R |
8125 | /* The code below requires comparison_val to be a multiple |
8126 | of add_val in order to do the loop reversal, so | |
8127 | round up comparison_val to a multiple of add_val. | |
8128 | Since comparison_value is constant, we know that the | |
8129 | current comparison code is LT. */ | |
8130 | comparison_val = comparison_val + add_val - 1; | |
8131 | comparison_val | |
8132 | -= (unsigned HOST_WIDE_INT) comparison_val % add_val; | |
8133 | /* We postpone overflow checks for COMPARISON_VAL here; | |
8134 | even if there is an overflow, we might still be able to | |
8135 | reverse the loop, if converting the loop exit test to | |
8136 | NE is possible. */ | |
8137 | initial_value = const0_rtx; | |
e9a25f70 JL |
8138 | } |
8139 | ||
c48ba252 R |
8140 | /* First check if we can do a vanilla loop reversal. */ |
8141 | if (initial_value == const0_rtx | |
3c748bb6 MH |
8142 | /* If we have a decrement_and_branch_on_count, |
8143 | prefer the NE test, since this will allow that | |
8144 | instruction to be generated. Note that we must | |
8145 | use a vanilla loop reversal if the biv is used to | |
8146 | calculate a giv or has a non-counting use. */ | |
8147 | #if ! defined (HAVE_decrement_and_branch_until_zero) \ | |
8148 | && defined (HAVE_decrement_and_branch_on_count) | |
a2be868f | 8149 | && (! (add_val == 1 && loop->vtop |
c5cbf81e JL |
8150 | && (bl->biv_count == 0 |
8151 | || no_use_except_counting))) | |
c48ba252 R |
8152 | #endif |
8153 | && GET_CODE (comparison_value) == CONST_INT | |
8154 | /* Now do postponed overflow checks on COMPARISON_VAL. */ | |
8155 | && ! (((comparison_val - add_val) ^ INTVAL (comparison_value)) | |
8156 | & comparison_sign_mask)) | |
8157 | { | |
8158 | /* Register will always be nonnegative, with value | |
8159 | 0 on last iteration */ | |
8160 | add_adjust = add_val; | |
8161 | nonneg = 1; | |
8162 | cmp_code = GE; | |
8163 | } | |
a2be868f | 8164 | else if (add_val == 1 && loop->vtop |
c5cbf81e JL |
8165 | && (bl->biv_count == 0 |
8166 | || no_use_except_counting)) | |
c48ba252 R |
8167 | { |
8168 | add_adjust = 0; | |
8169 | cmp_code = NE; | |
8170 | } | |
8171 | else | |
8172 | return 0; | |
8173 | ||
8174 | if (GET_CODE (comparison) == LE) | |
8175 | add_adjust -= add_val; | |
8176 | ||
e9a25f70 JL |
8177 | /* If the initial value is not zero, or if the comparison |
8178 | value is not an exact multiple of the increment, then we | |
8179 | can not reverse this loop. */ | |
c48ba252 R |
8180 | if (initial_value == const0_rtx |
8181 | && GET_CODE (comparison_value) == CONST_INT) | |
8182 | { | |
8183 | if (((unsigned HOST_WIDE_INT) comparison_val % add_val) != 0) | |
8184 | return 0; | |
8185 | } | |
8186 | else | |
8187 | { | |
8188 | if (! no_use_except_counting || add_val != 1) | |
8189 | return 0; | |
8190 | } | |
e9a25f70 | 8191 | |
8ed69d09 R |
8192 | final_value = comparison_value; |
8193 | ||
e9a25f70 JL |
8194 | /* Reset these in case we normalized the initial value |
8195 | and comparison value above. */ | |
8ed69d09 R |
8196 | if (GET_CODE (comparison_value) == CONST_INT |
8197 | && GET_CODE (initial_value) == CONST_INT) | |
8198 | { | |
8199 | comparison_value = GEN_INT (comparison_val); | |
8200 | final_value | |
8201 | = GEN_INT (comparison_val + INTVAL (bl->initial_value)); | |
8202 | } | |
e9a25f70 | 8203 | bl->initial_value = initial_value; |
b4ad7b23 RS |
8204 | |
8205 | /* Save some info needed to produce the new insns. */ | |
8206 | reg = bl->biv->dest_reg; | |
8207 | jump_label = XEXP (SET_SRC (PATTERN (PREV_INSN (loop_end))), 1); | |
3c2f289c RK |
8208 | if (jump_label == pc_rtx) |
8209 | jump_label = XEXP (SET_SRC (PATTERN (PREV_INSN (loop_end))), 2); | |
5fd8383e | 8210 | new_add_val = GEN_INT (- INTVAL (bl->biv->add_val)); |
b4ad7b23 | 8211 | |
c48ba252 R |
8212 | /* Set start_value; if this is not a CONST_INT, we need |
8213 | to generate a SUB. | |
8214 | Initialize biv to start_value before loop start. | |
b4ad7b23 RS |
8215 | The old initializing insn will be deleted as a |
8216 | dead store by flow.c. */ | |
c48ba252 R |
8217 | if (initial_value == const0_rtx |
8218 | && GET_CODE (comparison_value) == CONST_INT) | |
8219 | { | |
8220 | start_value = GEN_INT (comparison_val - add_adjust); | |
8221 | emit_insn_before (gen_move_insn (reg, start_value), | |
8222 | loop_start); | |
8223 | } | |
8224 | else if (GET_CODE (initial_value) == CONST_INT) | |
8225 | { | |
8226 | rtx offset = GEN_INT (-INTVAL (initial_value) - add_adjust); | |
8227 | enum machine_mode mode = GET_MODE (reg); | |
8228 | enum insn_code icode | |
8229 | = add_optab->handlers[(int) mode].insn_code; | |
a995e389 RH |
8230 | |
8231 | if (! (*insn_data[icode].operand[0].predicate) (reg, mode) | |
8232 | || ! ((*insn_data[icode].operand[1].predicate) | |
c48ba252 | 8233 | (comparison_value, mode)) |
a995e389 RH |
8234 | || ! ((*insn_data[icode].operand[2].predicate) |
8235 | (offset, mode))) | |
c48ba252 R |
8236 | return 0; |
8237 | start_value | |
8238 | = gen_rtx_PLUS (mode, comparison_value, offset); | |
8239 | emit_insn_before ((GEN_FCN (icode) | |
8240 | (reg, comparison_value, offset)), | |
8241 | loop_start); | |
8242 | if (GET_CODE (comparison) == LE) | |
8243 | final_value = gen_rtx_PLUS (mode, comparison_value, | |
8244 | GEN_INT (add_val)); | |
8245 | } | |
8246 | else if (! add_adjust) | |
8247 | { | |
8248 | enum machine_mode mode = GET_MODE (reg); | |
8249 | enum insn_code icode | |
8250 | = sub_optab->handlers[(int) mode].insn_code; | |
a995e389 RH |
8251 | if (! (*insn_data[icode].operand[0].predicate) (reg, mode) |
8252 | || ! ((*insn_data[icode].operand[1].predicate) | |
c48ba252 | 8253 | (comparison_value, mode)) |
a995e389 | 8254 | || ! ((*insn_data[icode].operand[2].predicate) |
c48ba252 R |
8255 | (initial_value, mode))) |
8256 | return 0; | |
8257 | start_value | |
8258 | = gen_rtx_MINUS (mode, comparison_value, initial_value); | |
8259 | emit_insn_before ((GEN_FCN (icode) | |
8260 | (reg, comparison_value, initial_value)), | |
8261 | loop_start); | |
8262 | } | |
8263 | else | |
8264 | /* We could handle the other cases too, but it'll be | |
8265 | better to have a testcase first. */ | |
8266 | return 0; | |
b4ad7b23 | 8267 | |
225a7e3d JL |
8268 | /* We may not have a single insn which can increment a reg, so |
8269 | create a sequence to hold all the insns from expand_inc. */ | |
8270 | start_sequence (); | |
8271 | expand_inc (reg, new_add_val); | |
8272 | tem = gen_sequence (); | |
8273 | end_sequence (); | |
8274 | ||
8275 | p = emit_insn_before (tem, bl->biv->insn); | |
b4ad7b23 RS |
8276 | delete_insn (bl->biv->insn); |
8277 | ||
8278 | /* Update biv info to reflect its new status. */ | |
8279 | bl->biv->insn = p; | |
8280 | bl->initial_value = start_value; | |
8281 | bl->biv->add_val = new_add_val; | |
8282 | ||
5629b16c | 8283 | /* Update loop info. */ |
eb6a3bc0 MH |
8284 | loop_info->initial_value = reg; |
8285 | loop_info->initial_equiv_value = reg; | |
5629b16c MH |
8286 | loop_info->final_value = const0_rtx; |
8287 | loop_info->final_equiv_value = const0_rtx; | |
8288 | loop_info->comparison_value = const0_rtx; | |
8289 | loop_info->comparison_code = cmp_code; | |
8290 | loop_info->increment = new_add_val; | |
8291 | ||
b4ad7b23 RS |
8292 | /* Inc LABEL_NUSES so that delete_insn will |
8293 | not delete the label. */ | |
8294 | LABEL_NUSES (XEXP (jump_label, 0)) ++; | |
8295 | ||
8296 | /* Emit an insn after the end of the loop to set the biv's | |
8297 | proper exit value if it is used anywhere outside the loop. */ | |
0628fde6 | 8298 | if ((REGNO_LAST_UID (bl->regno) != INSN_UID (first_compare)) |
b4ad7b23 | 8299 | || ! bl->init_insn |
b1f21e0a | 8300 | || REGNO_FIRST_UID (bl->regno) != INSN_UID (bl->init_insn)) |
b4ad7b23 RS |
8301 | emit_insn_after (gen_move_insn (reg, final_value), |
8302 | loop_end); | |
8303 | ||
8304 | /* Delete compare/branch at end of loop. */ | |
8305 | delete_insn (PREV_INSN (loop_end)); | |
0628fde6 JW |
8306 | if (compare_and_branch == 2) |
8307 | delete_insn (first_compare); | |
b4ad7b23 RS |
8308 | |
8309 | /* Add new compare/branch insn at end of loop. */ | |
8310 | start_sequence (); | |
362cc3d4 MH |
8311 | emit_cmp_and_jump_insns (reg, const0_rtx, cmp_code, NULL_RTX, |
8312 | GET_MODE (reg), 0, 0, | |
8313 | XEXP (jump_label, 0)); | |
b4ad7b23 RS |
8314 | tem = gen_sequence (); |
8315 | end_sequence (); | |
8316 | emit_jump_insn_before (tem, loop_end); | |
8317 | ||
a7060368 MH |
8318 | for (tem = PREV_INSN (loop_end); |
8319 | tem && GET_CODE (tem) != JUMP_INSN; | |
8320 | tem = PREV_INSN (tem)) | |
8321 | ; | |
8322 | ||
8323 | if (tem) | |
8324 | JUMP_LABEL (tem) = XEXP (jump_label, 0); | |
8325 | ||
c48ba252 | 8326 | if (nonneg) |
b4ad7b23 | 8327 | { |
c48ba252 R |
8328 | if (tem) |
8329 | { | |
c48ba252 R |
8330 | /* Increment of LABEL_NUSES done above. */ |
8331 | /* Register is now always nonnegative, | |
8332 | so add REG_NONNEG note to the branch. */ | |
8333 | REG_NOTES (tem) = gen_rtx_EXPR_LIST (REG_NONNEG, NULL_RTX, | |
8334 | REG_NOTES (tem)); | |
8335 | } | |
8336 | bl->nonneg = 1; | |
b4ad7b23 RS |
8337 | } |
8338 | ||
22b452e7 BS |
8339 | /* No insn may reference both the reversed and another biv or it |
8340 | will fail (see comment near the top of the loop reversal | |
8341 | code). | |
8342 | Earlier on, we have verified that the biv has no use except | |
8343 | counting, or it is the only biv in this function. | |
8344 | However, the code that computes no_use_except_counting does | |
8345 | not verify reg notes. It's possible to have an insn that | |
8346 | references another biv, and has a REG_EQUAL note with an | |
8347 | expression based on the reversed biv. To avoid this case, | |
8348 | remove all REG_EQUAL notes based on the reversed biv | |
8349 | here. */ | |
8350 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) | |
8351 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
8352 | { | |
8353 | rtx *pnote; | |
8354 | rtx set = single_set (p); | |
8355 | /* If this is a set of a GIV based on the reversed biv, any | |
8356 | REG_EQUAL notes should still be correct. */ | |
8357 | if (! set | |
8358 | || GET_CODE (SET_DEST (set)) != REG | |
6a651371 | 8359 | || (size_t) REGNO (SET_DEST (set)) >= reg_iv_type->num_elements |
22b452e7 BS |
8360 | || REG_IV_TYPE (REGNO (SET_DEST (set))) != GENERAL_INDUCT |
8361 | || REG_IV_INFO (REGNO (SET_DEST (set)))->src_reg != bl->biv->src_reg) | |
8362 | for (pnote = ®_NOTES (p); *pnote;) | |
8363 | { | |
8364 | if (REG_NOTE_KIND (*pnote) == REG_EQUAL | |
8365 | && reg_mentioned_p (regno_reg_rtx[bl->regno], | |
8366 | XEXP (*pnote, 0))) | |
8367 | *pnote = XEXP (*pnote, 1); | |
8368 | else | |
8369 | pnote = &XEXP (*pnote, 1); | |
8370 | } | |
8371 | } | |
8372 | ||
b4ad7b23 RS |
8373 | /* Mark that this biv has been reversed. Each giv which depends |
8374 | on this biv, and which is also live past the end of the loop | |
8375 | will have to be fixed up. */ | |
8376 | ||
8377 | bl->reversed = 1; | |
8378 | ||
8379 | if (loop_dump_stream) | |
b50cb11f MH |
8380 | { |
8381 | fprintf (loop_dump_stream, "Reversed loop"); | |
8382 | if (bl->nonneg) | |
8383 | fprintf (loop_dump_stream, " and added reg_nonneg\n"); | |
8384 | else | |
8385 | fprintf (loop_dump_stream, "\n"); | |
8386 | } | |
b4ad7b23 RS |
8387 | |
8388 | return 1; | |
8389 | } | |
8390 | } | |
8391 | } | |
8392 | ||
8393 | return 0; | |
8394 | } | |
8395 | \f | |
8396 | /* Verify whether the biv BL appears to be eliminable, | |
8397 | based on the insns in the loop that refer to it. | |
8398 | LOOP_START is the first insn of the loop, and END is the end insn. | |
8399 | ||
8400 | If ELIMINATE_P is non-zero, actually do the elimination. | |
8401 | ||
8402 | THRESHOLD and INSN_COUNT are from loop_optimize and are used to | |
8403 | determine whether invariant insns should be placed inside or at the | |
8404 | start of the loop. */ | |
8405 | ||
8406 | static int | |
a2be868f MH |
8407 | maybe_eliminate_biv (bl, loop_start, loop_end, eliminate_p, threshold, |
8408 | insn_count) | |
b4ad7b23 RS |
8409 | struct iv_class *bl; |
8410 | rtx loop_start; | |
a2be868f | 8411 | rtx loop_end; |
b4ad7b23 RS |
8412 | int eliminate_p; |
8413 | int threshold, insn_count; | |
8414 | { | |
8415 | rtx reg = bl->biv->dest_reg; | |
bd5a664e | 8416 | rtx p; |
b4ad7b23 RS |
8417 | |
8418 | /* Scan all insns in the loop, stopping if we find one that uses the | |
8419 | biv in a way that we cannot eliminate. */ | |
8420 | ||
a2be868f | 8421 | for (p = loop_start; p != loop_end; p = NEXT_INSN (p)) |
b4ad7b23 RS |
8422 | { |
8423 | enum rtx_code code = GET_CODE (p); | |
8424 | rtx where = threshold >= insn_count ? loop_start : p; | |
8425 | ||
fdb1833a R |
8426 | /* If this is a libcall that sets a giv, skip ahead to its end. */ |
8427 | if (GET_RTX_CLASS (code) == 'i') | |
8428 | { | |
8429 | rtx note = find_reg_note (p, REG_LIBCALL, NULL_RTX); | |
8430 | ||
8431 | if (note) | |
8432 | { | |
8433 | rtx last = XEXP (note, 0); | |
8434 | rtx set = single_set (last); | |
8435 | ||
8436 | if (set && GET_CODE (SET_DEST (set)) == REG) | |
8437 | { | |
8438 | int regno = REGNO (SET_DEST (set)); | |
8439 | ||
ab519383 GS |
8440 | if (regno < max_reg_before_loop |
8441 | && REG_IV_TYPE (regno) == GENERAL_INDUCT | |
fdb1833a R |
8442 | && REG_IV_INFO (regno)->src_reg == bl->biv->src_reg) |
8443 | p = last; | |
8444 | } | |
8445 | } | |
8446 | } | |
b4ad7b23 RS |
8447 | if ((code == INSN || code == JUMP_INSN || code == CALL_INSN) |
8448 | && reg_mentioned_p (reg, PATTERN (p)) | |
8449 | && ! maybe_eliminate_biv_1 (PATTERN (p), p, bl, eliminate_p, where)) | |
8450 | { | |
8451 | if (loop_dump_stream) | |
8452 | fprintf (loop_dump_stream, | |
8453 | "Cannot eliminate biv %d: biv used in insn %d.\n", | |
8454 | bl->regno, INSN_UID (p)); | |
8455 | break; | |
8456 | } | |
8457 | } | |
8458 | ||
a2be868f | 8459 | if (p == loop_end) |
b4ad7b23 RS |
8460 | { |
8461 | if (loop_dump_stream) | |
8462 | fprintf (loop_dump_stream, "biv %d %s eliminated.\n", | |
8463 | bl->regno, eliminate_p ? "was" : "can be"); | |
8464 | return 1; | |
8465 | } | |
8466 | ||
8467 | return 0; | |
8468 | } | |
8469 | \f | |
a6207a2b | 8470 | /* INSN and REFERENCE are instructions in the same insn chain. |
f38cbf0f | 8471 | Return non-zero if INSN is first. */ |
a6207a2b | 8472 | |
c99f8c2a | 8473 | int |
a6207a2b R |
8474 | loop_insn_first_p (insn, reference) |
8475 | rtx insn, reference; | |
8476 | { | |
f38cbf0f R |
8477 | rtx p, q; |
8478 | ||
8479 | for (p = insn, q = reference; ;) | |
8480 | { | |
8481 | /* Start with test for not first so that INSN == REFERENCE yields not | |
8482 | first. */ | |
8483 | if (q == insn || ! p) | |
8484 | return 0; | |
8485 | if (p == reference || ! q) | |
8486 | return 1; | |
8487 | ||
7c2772f1 R |
8488 | /* Either of P or Q might be a NOTE. Notes have the same LUID as the |
8489 | previous insn, hence the <= comparison below does not work if | |
8490 | P is a note. */ | |
f38cbf0f | 8491 | if (INSN_UID (p) < max_uid_for_loop |
7c2772f1 R |
8492 | && INSN_UID (q) < max_uid_for_loop |
8493 | && GET_CODE (p) != NOTE) | |
8494 | return INSN_LUID (p) <= INSN_LUID (q); | |
f38cbf0f | 8495 | |
7c2772f1 R |
8496 | if (INSN_UID (p) >= max_uid_for_loop |
8497 | || GET_CODE (p) == NOTE) | |
f38cbf0f R |
8498 | p = NEXT_INSN (p); |
8499 | if (INSN_UID (q) >= max_uid_for_loop) | |
8500 | q = NEXT_INSN (q); | |
8501 | } | |
a6207a2b R |
8502 | } |
8503 | ||
8504 | /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if | |
8505 | the offset that we have to take into account due to auto-increment / | |
8506 | div derivation is zero. */ | |
8507 | static int | |
8508 | biv_elimination_giv_has_0_offset (biv, giv, insn) | |
8509 | struct induction *biv, *giv; | |
8510 | rtx insn; | |
8511 | { | |
8512 | /* If the giv V had the auto-inc address optimization applied | |
8513 | to it, and INSN occurs between the giv insn and the biv | |
8514 | insn, then we'd have to adjust the value used here. | |
8515 | This is rare, so we don't bother to make this possible. */ | |
8516 | if (giv->auto_inc_opt | |
8517 | && ((loop_insn_first_p (giv->insn, insn) | |
8518 | && loop_insn_first_p (insn, biv->insn)) | |
8519 | || (loop_insn_first_p (biv->insn, insn) | |
8520 | && loop_insn_first_p (insn, giv->insn)))) | |
8521 | return 0; | |
8522 | ||
8523 | /* If the giv V was derived from another giv, and INSN does | |
8524 | not occur between the giv insn and the biv insn, then we'd | |
8525 | have to adjust the value used here. This is rare, so we don't | |
8526 | bother to make this possible. */ | |
8527 | if (giv->derived_from | |
8528 | && ! (giv->always_executed | |
8529 | && loop_insn_first_p (giv->insn, insn) | |
8530 | && loop_insn_first_p (insn, biv->insn))) | |
8531 | return 0; | |
8532 | if (giv->same | |
8533 | && giv->same->derived_from | |
8534 | && ! (giv->same->always_executed | |
8535 | && loop_insn_first_p (giv->same->insn, insn) | |
8536 | && loop_insn_first_p (insn, biv->insn))) | |
8537 | return 0; | |
8538 | ||
8539 | return 1; | |
8540 | } | |
8541 | ||
b4ad7b23 RS |
8542 | /* If BL appears in X (part of the pattern of INSN), see if we can |
8543 | eliminate its use. If so, return 1. If not, return 0. | |
8544 | ||
8545 | If BIV does not appear in X, return 1. | |
8546 | ||
8547 | If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates | |
8548 | where extra insns should be added. Depending on how many items have been | |
8549 | moved out of the loop, it will either be before INSN or at the start of | |
8550 | the loop. */ | |
8551 | ||
8552 | static int | |
8553 | maybe_eliminate_biv_1 (x, insn, bl, eliminate_p, where) | |
8554 | rtx x, insn; | |
8555 | struct iv_class *bl; | |
8556 | int eliminate_p; | |
8557 | rtx where; | |
8558 | { | |
8559 | enum rtx_code code = GET_CODE (x); | |
8560 | rtx reg = bl->biv->dest_reg; | |
8561 | enum machine_mode mode = GET_MODE (reg); | |
8562 | struct induction *v; | |
51723711 KG |
8563 | rtx arg, tem; |
8564 | #ifdef HAVE_cc0 | |
8565 | rtx new; | |
8566 | #endif | |
b4ad7b23 | 8567 | int arg_operand; |
6f7d635c | 8568 | const char *fmt; |
b4ad7b23 RS |
8569 | int i, j; |
8570 | ||
8571 | switch (code) | |
8572 | { | |
8573 | case REG: | |
8574 | /* If we haven't already been able to do something with this BIV, | |
8575 | we can't eliminate it. */ | |
8576 | if (x == reg) | |
8577 | return 0; | |
8578 | return 1; | |
8579 | ||
8580 | case SET: | |
8581 | /* If this sets the BIV, it is not a problem. */ | |
8582 | if (SET_DEST (x) == reg) | |
8583 | return 1; | |
8584 | ||
8585 | /* If this is an insn that defines a giv, it is also ok because | |
8586 | it will go away when the giv is reduced. */ | |
8587 | for (v = bl->giv; v; v = v->next_iv) | |
8588 | if (v->giv_type == DEST_REG && SET_DEST (x) == v->dest_reg) | |
8589 | return 1; | |
8590 | ||
8591 | #ifdef HAVE_cc0 | |
8592 | if (SET_DEST (x) == cc0_rtx && SET_SRC (x) == reg) | |
8593 | { | |
8594 | /* Can replace with any giv that was reduced and | |
8595 | that has (MULT_VAL != 0) and (ADD_VAL == 0). | |
fbdc6da8 RK |
8596 | Require a constant for MULT_VAL, so we know it's nonzero. |
8597 | ??? We disable this optimization to avoid potential | |
8598 | overflows. */ | |
b4ad7b23 RS |
8599 | |
8600 | for (v = bl->giv; v; v = v->next_iv) | |
8601 | if (CONSTANT_P (v->mult_val) && v->mult_val != const0_rtx | |
8602 | && v->add_val == const0_rtx | |
453331a3 | 8603 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8604 | && v->mode == mode |
8605 | && 0) | |
b4ad7b23 | 8606 | { |
a6207a2b | 8607 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8608 | continue; |
8609 | ||
b4ad7b23 RS |
8610 | if (! eliminate_p) |
8611 | return 1; | |
8612 | ||
8613 | /* If the giv has the opposite direction of change, | |
8614 | then reverse the comparison. */ | |
8615 | if (INTVAL (v->mult_val) < 0) | |
38a448ca RH |
8616 | new = gen_rtx_COMPARE (GET_MODE (v->new_reg), |
8617 | const0_rtx, v->new_reg); | |
b4ad7b23 RS |
8618 | else |
8619 | new = v->new_reg; | |
8620 | ||
8621 | /* We can probably test that giv's reduced reg. */ | |
8622 | if (validate_change (insn, &SET_SRC (x), new, 0)) | |
8623 | return 1; | |
8624 | } | |
8625 | ||
8626 | /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0); | |
8627 | replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL). | |
fbdc6da8 RK |
8628 | Require a constant for MULT_VAL, so we know it's nonzero. |
8629 | ??? Do this only if ADD_VAL is a pointer to avoid a potential | |
8630 | overflow problem. */ | |
b4ad7b23 RS |
8631 | |
8632 | for (v = bl->giv; v; v = v->next_iv) | |
8633 | if (CONSTANT_P (v->mult_val) && v->mult_val != const0_rtx | |
453331a3 | 8634 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8635 | && v->mode == mode |
8636 | && (GET_CODE (v->add_val) == SYMBOL_REF | |
8637 | || GET_CODE (v->add_val) == LABEL_REF | |
8638 | || GET_CODE (v->add_val) == CONST | |
8639 | || (GET_CODE (v->add_val) == REG | |
8640 | && REGNO_POINTER_FLAG (REGNO (v->add_val))))) | |
b4ad7b23 | 8641 | { |
a6207a2b | 8642 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8643 | continue; |
8644 | ||
b4ad7b23 RS |
8645 | if (! eliminate_p) |
8646 | return 1; | |
8647 | ||
8648 | /* If the giv has the opposite direction of change, | |
8649 | then reverse the comparison. */ | |
8650 | if (INTVAL (v->mult_val) < 0) | |
38a448ca RH |
8651 | new = gen_rtx_COMPARE (VOIDmode, copy_rtx (v->add_val), |
8652 | v->new_reg); | |
b4ad7b23 | 8653 | else |
38a448ca RH |
8654 | new = gen_rtx_COMPARE (VOIDmode, v->new_reg, |
8655 | copy_rtx (v->add_val)); | |
b4ad7b23 RS |
8656 | |
8657 | /* Replace biv with the giv's reduced register. */ | |
8658 | update_reg_last_use (v->add_val, insn); | |
8659 | if (validate_change (insn, &SET_SRC (PATTERN (insn)), new, 0)) | |
8660 | return 1; | |
8661 | ||
8662 | /* Insn doesn't support that constant or invariant. Copy it | |
8663 | into a register (it will be a loop invariant.) */ | |
8664 | tem = gen_reg_rtx (GET_MODE (v->new_reg)); | |
8665 | ||
8666 | emit_insn_before (gen_move_insn (tem, copy_rtx (v->add_val)), | |
8667 | where); | |
8668 | ||
2ae3dcac RK |
8669 | /* Substitute the new register for its invariant value in |
8670 | the compare expression. */ | |
8671 | XEXP (new, (INTVAL (v->mult_val) < 0) ? 0 : 1) = tem; | |
8672 | if (validate_change (insn, &SET_SRC (PATTERN (insn)), new, 0)) | |
b4ad7b23 RS |
8673 | return 1; |
8674 | } | |
8675 | } | |
8676 | #endif | |
8677 | break; | |
8678 | ||
8679 | case COMPARE: | |
8680 | case EQ: case NE: | |
8681 | case GT: case GE: case GTU: case GEU: | |
8682 | case LT: case LE: case LTU: case LEU: | |
8683 | /* See if either argument is the biv. */ | |
8684 | if (XEXP (x, 0) == reg) | |
8685 | arg = XEXP (x, 1), arg_operand = 1; | |
8686 | else if (XEXP (x, 1) == reg) | |
8687 | arg = XEXP (x, 0), arg_operand = 0; | |
8688 | else | |
8689 | break; | |
8690 | ||
8691 | if (CONSTANT_P (arg)) | |
8692 | { | |
8693 | /* First try to replace with any giv that has constant positive | |
8694 | mult_val and constant add_val. We might be able to support | |
8695 | negative mult_val, but it seems complex to do it in general. */ | |
8696 | ||
8697 | for (v = bl->giv; v; v = v->next_iv) | |
8698 | if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0 | |
fbdc6da8 RK |
8699 | && (GET_CODE (v->add_val) == SYMBOL_REF |
8700 | || GET_CODE (v->add_val) == LABEL_REF | |
8701 | || GET_CODE (v->add_val) == CONST | |
8702 | || (GET_CODE (v->add_val) == REG | |
8703 | && REGNO_POINTER_FLAG (REGNO (v->add_val)))) | |
453331a3 | 8704 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
b4ad7b23 RS |
8705 | && v->mode == mode) |
8706 | { | |
a6207a2b | 8707 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8708 | continue; |
8709 | ||
b4ad7b23 RS |
8710 | if (! eliminate_p) |
8711 | return 1; | |
8712 | ||
8713 | /* Replace biv with the giv's reduced reg. */ | |
8714 | XEXP (x, 1-arg_operand) = v->new_reg; | |
8715 | ||
8716 | /* If all constants are actually constant integers and | |
8717 | the derived constant can be directly placed in the COMPARE, | |
8718 | do so. */ | |
8719 | if (GET_CODE (arg) == CONST_INT | |
8720 | && GET_CODE (v->mult_val) == CONST_INT | |
8721 | && GET_CODE (v->add_val) == CONST_INT | |
8722 | && validate_change (insn, &XEXP (x, arg_operand), | |
5fd8383e RK |
8723 | GEN_INT (INTVAL (arg) |
8724 | * INTVAL (v->mult_val) | |
8725 | + INTVAL (v->add_val)), 0)) | |
b4ad7b23 RS |
8726 | return 1; |
8727 | ||
8728 | /* Otherwise, load it into a register. */ | |
8729 | tem = gen_reg_rtx (mode); | |
8730 | emit_iv_add_mult (arg, v->mult_val, v->add_val, tem, where); | |
8731 | if (validate_change (insn, &XEXP (x, arg_operand), tem, 0)) | |
8732 | return 1; | |
8733 | ||
8734 | /* If that failed, put back the change we made above. */ | |
8735 | XEXP (x, 1-arg_operand) = reg; | |
8736 | } | |
8737 | ||
8738 | /* Look for giv with positive constant mult_val and nonconst add_val. | |
fbdc6da8 RK |
8739 | Insert insns to calculate new compare value. |
8740 | ??? Turn this off due to possible overflow. */ | |
b4ad7b23 RS |
8741 | |
8742 | for (v = bl->giv; v; v = v->next_iv) | |
d45cf215 | 8743 | if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0 |
453331a3 | 8744 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8745 | && v->mode == mode |
8746 | && 0) | |
b4ad7b23 RS |
8747 | { |
8748 | rtx tem; | |
8749 | ||
a6207a2b | 8750 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8751 | continue; |
8752 | ||
b4ad7b23 RS |
8753 | if (! eliminate_p) |
8754 | return 1; | |
8755 | ||
8756 | tem = gen_reg_rtx (mode); | |
8757 | ||
8758 | /* Replace biv with giv's reduced register. */ | |
8759 | validate_change (insn, &XEXP (x, 1 - arg_operand), | |
8760 | v->new_reg, 1); | |
8761 | ||
8762 | /* Compute value to compare against. */ | |
8763 | emit_iv_add_mult (arg, v->mult_val, v->add_val, tem, where); | |
8764 | /* Use it in this insn. */ | |
8765 | validate_change (insn, &XEXP (x, arg_operand), tem, 1); | |
8766 | if (apply_change_group ()) | |
8767 | return 1; | |
8768 | } | |
8769 | } | |
8770 | else if (GET_CODE (arg) == REG || GET_CODE (arg) == MEM) | |
8771 | { | |
8772 | if (invariant_p (arg) == 1) | |
8773 | { | |
8774 | /* Look for giv with constant positive mult_val and nonconst | |
fbdc6da8 RK |
8775 | add_val. Insert insns to compute new compare value. |
8776 | ??? Turn this off due to possible overflow. */ | |
b4ad7b23 RS |
8777 | |
8778 | for (v = bl->giv; v; v = v->next_iv) | |
8779 | if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0 | |
453331a3 | 8780 | && ! v->ignore && ! v->maybe_dead && v->always_computable |
fbdc6da8 RK |
8781 | && v->mode == mode |
8782 | && 0) | |
b4ad7b23 RS |
8783 | { |
8784 | rtx tem; | |
8785 | ||
a6207a2b | 8786 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8787 | continue; |
8788 | ||
b4ad7b23 RS |
8789 | if (! eliminate_p) |
8790 | return 1; | |
8791 | ||
8792 | tem = gen_reg_rtx (mode); | |
8793 | ||
8794 | /* Replace biv with giv's reduced register. */ | |
8795 | validate_change (insn, &XEXP (x, 1 - arg_operand), | |
8796 | v->new_reg, 1); | |
8797 | ||
8798 | /* Compute value to compare against. */ | |
8799 | emit_iv_add_mult (arg, v->mult_val, v->add_val, | |
8800 | tem, where); | |
8801 | validate_change (insn, &XEXP (x, arg_operand), tem, 1); | |
8802 | if (apply_change_group ()) | |
8803 | return 1; | |
8804 | } | |
8805 | } | |
8806 | ||
8807 | /* This code has problems. Basically, you can't know when | |
8808 | seeing if we will eliminate BL, whether a particular giv | |
8809 | of ARG will be reduced. If it isn't going to be reduced, | |
8810 | we can't eliminate BL. We can try forcing it to be reduced, | |
8811 | but that can generate poor code. | |
8812 | ||
8813 | The problem is that the benefit of reducing TV, below should | |
8814 | be increased if BL can actually be eliminated, but this means | |
8815 | we might have to do a topological sort of the order in which | |
8816 | we try to process biv. It doesn't seem worthwhile to do | |
8817 | this sort of thing now. */ | |
8818 | ||
8819 | #if 0 | |
8820 | /* Otherwise the reg compared with had better be a biv. */ | |
8821 | if (GET_CODE (arg) != REG | |
3ec2b590 | 8822 | || REG_IV_TYPE (REGNO (arg)) != BASIC_INDUCT) |
b4ad7b23 RS |
8823 | return 0; |
8824 | ||
8825 | /* Look for a pair of givs, one for each biv, | |
8826 | with identical coefficients. */ | |
8827 | for (v = bl->giv; v; v = v->next_iv) | |
8828 | { | |
8829 | struct induction *tv; | |
8830 | ||
8831 | if (v->ignore || v->maybe_dead || v->mode != mode) | |
8832 | continue; | |
8833 | ||
8834 | for (tv = reg_biv_class[REGNO (arg)]->giv; tv; tv = tv->next_iv) | |
8835 | if (! tv->ignore && ! tv->maybe_dead | |
8836 | && rtx_equal_p (tv->mult_val, v->mult_val) | |
8837 | && rtx_equal_p (tv->add_val, v->add_val) | |
8838 | && tv->mode == mode) | |
8839 | { | |
a6207a2b | 8840 | if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn)) |
8516af93 JW |
8841 | continue; |
8842 | ||
b4ad7b23 RS |
8843 | if (! eliminate_p) |
8844 | return 1; | |
8845 | ||
8846 | /* Replace biv with its giv's reduced reg. */ | |
8847 | XEXP (x, 1-arg_operand) = v->new_reg; | |
8848 | /* Replace other operand with the other giv's | |
8849 | reduced reg. */ | |
8850 | XEXP (x, arg_operand) = tv->new_reg; | |
8851 | return 1; | |
8852 | } | |
8853 | } | |
8854 | #endif | |
8855 | } | |
8856 | ||
8857 | /* If we get here, the biv can't be eliminated. */ | |
8858 | return 0; | |
8859 | ||
8860 | case MEM: | |
8861 | /* If this address is a DEST_ADDR giv, it doesn't matter if the | |
8862 | biv is used in it, since it will be replaced. */ | |
8863 | for (v = bl->giv; v; v = v->next_iv) | |
8864 | if (v->giv_type == DEST_ADDR && v->location == &XEXP (x, 0)) | |
8865 | return 1; | |
8866 | break; | |
e9a25f70 JL |
8867 | |
8868 | default: | |
8869 | break; | |
b4ad7b23 RS |
8870 | } |
8871 | ||
8872 | /* See if any subexpression fails elimination. */ | |
8873 | fmt = GET_RTX_FORMAT (code); | |
8874 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8875 | { | |
8876 | switch (fmt[i]) | |
8877 | { | |
8878 | case 'e': | |
8879 | if (! maybe_eliminate_biv_1 (XEXP (x, i), insn, bl, | |
8880 | eliminate_p, where)) | |
8881 | return 0; | |
8882 | break; | |
8883 | ||
8884 | case 'E': | |
8885 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8886 | if (! maybe_eliminate_biv_1 (XVECEXP (x, i, j), insn, bl, | |
8887 | eliminate_p, where)) | |
8888 | return 0; | |
8889 | break; | |
8890 | } | |
8891 | } | |
8892 | ||
8893 | return 1; | |
8894 | } | |
8895 | \f | |
8896 | /* Return nonzero if the last use of REG | |
8897 | is in an insn following INSN in the same basic block. */ | |
8898 | ||
8899 | static int | |
8900 | last_use_this_basic_block (reg, insn) | |
8901 | rtx reg; | |
8902 | rtx insn; | |
8903 | { | |
8904 | rtx n; | |
8905 | for (n = insn; | |
8906 | n && GET_CODE (n) != CODE_LABEL && GET_CODE (n) != JUMP_INSN; | |
8907 | n = NEXT_INSN (n)) | |
8908 | { | |
b1f21e0a | 8909 | if (REGNO_LAST_UID (REGNO (reg)) == INSN_UID (n)) |
b4ad7b23 RS |
8910 | return 1; |
8911 | } | |
8912 | return 0; | |
8913 | } | |
8914 | \f | |
8915 | /* Called via `note_stores' to record the initial value of a biv. Here we | |
8916 | just record the location of the set and process it later. */ | |
8917 | ||
8918 | static void | |
84832317 | 8919 | record_initial (dest, set, data) |
b4ad7b23 RS |
8920 | rtx dest; |
8921 | rtx set; | |
84832317 | 8922 | void *data ATTRIBUTE_UNUSED; |
b4ad7b23 RS |
8923 | { |
8924 | struct iv_class *bl; | |
8925 | ||
8926 | if (GET_CODE (dest) != REG | |
8927 | || REGNO (dest) >= max_reg_before_loop | |
3ec2b590 | 8928 | || REG_IV_TYPE (REGNO (dest)) != BASIC_INDUCT) |
b4ad7b23 RS |
8929 | return; |
8930 | ||
8931 | bl = reg_biv_class[REGNO (dest)]; | |
8932 | ||
8933 | /* If this is the first set found, record it. */ | |
8934 | if (bl->init_insn == 0) | |
8935 | { | |
8936 | bl->init_insn = note_insn; | |
8937 | bl->init_set = set; | |
8938 | } | |
8939 | } | |
8940 | \f | |
8941 | /* If any of the registers in X are "old" and currently have a last use earlier | |
8942 | than INSN, update them to have a last use of INSN. Their actual last use | |
8943 | will be the previous insn but it will not have a valid uid_luid so we can't | |
8944 | use it. */ | |
8945 | ||
8946 | static void | |
8947 | update_reg_last_use (x, insn) | |
8948 | rtx x; | |
8949 | rtx insn; | |
8950 | { | |
8951 | /* Check for the case where INSN does not have a valid luid. In this case, | |
8952 | there is no need to modify the regno_last_uid, as this can only happen | |
8953 | when code is inserted after the loop_end to set a pseudo's final value, | |
8954 | and hence this insn will never be the last use of x. */ | |
8955 | if (GET_CODE (x) == REG && REGNO (x) < max_reg_before_loop | |
8956 | && INSN_UID (insn) < max_uid_for_loop | |
b1f21e0a MM |
8957 | && uid_luid[REGNO_LAST_UID (REGNO (x))] < uid_luid[INSN_UID (insn)]) |
8958 | REGNO_LAST_UID (REGNO (x)) = INSN_UID (insn); | |
b4ad7b23 RS |
8959 | else |
8960 | { | |
8961 | register int i, j; | |
6f7d635c | 8962 | register const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); |
b4ad7b23 RS |
8963 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
8964 | { | |
8965 | if (fmt[i] == 'e') | |
8966 | update_reg_last_use (XEXP (x, i), insn); | |
8967 | else if (fmt[i] == 'E') | |
8968 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8969 | update_reg_last_use (XVECEXP (x, i, j), insn); | |
8970 | } | |
8971 | } | |
8972 | } | |
8973 | \f | |
8974 | /* Given a jump insn JUMP, return the condition that will cause it to branch | |
8975 | to its JUMP_LABEL. If the condition cannot be understood, or is an | |
8976 | inequality floating-point comparison which needs to be reversed, 0 will | |
8977 | be returned. | |
8978 | ||
8979 | If EARLIEST is non-zero, it is a pointer to a place where the earliest | |
8980 | insn used in locating the condition was found. If a replacement test | |
8981 | of the condition is desired, it should be placed in front of that | |
8982 | insn and we will be sure that the inputs are still valid. | |
8983 | ||
8984 | The condition will be returned in a canonical form to simplify testing by | |
8985 | callers. Specifically: | |
8986 | ||
8987 | (1) The code will always be a comparison operation (EQ, NE, GT, etc.). | |
8988 | (2) Both operands will be machine operands; (cc0) will have been replaced. | |
8989 | (3) If an operand is a constant, it will be the second operand. | |
8990 | (4) (LE x const) will be replaced with (LT x <const+1>) and similarly | |
8991 | for GE, GEU, and LEU. */ | |
8992 | ||
8993 | rtx | |
8994 | get_condition (jump, earliest) | |
8995 | rtx jump; | |
8996 | rtx *earliest; | |
8997 | { | |
8998 | enum rtx_code code; | |
8999 | rtx prev = jump; | |
9000 | rtx set; | |
9001 | rtx tem; | |
9002 | rtx op0, op1; | |
9003 | int reverse_code = 0; | |
9004 | int did_reverse_condition = 0; | |
f283421d | 9005 | enum machine_mode mode; |
b4ad7b23 RS |
9006 | |
9007 | /* If this is not a standard conditional jump, we can't parse it. */ | |
9008 | if (GET_CODE (jump) != JUMP_INSN | |
9009 | || ! condjump_p (jump) || simplejump_p (jump)) | |
9010 | return 0; | |
9011 | ||
9012 | code = GET_CODE (XEXP (SET_SRC (PATTERN (jump)), 0)); | |
f283421d | 9013 | mode = GET_MODE (XEXP (SET_SRC (PATTERN (jump)), 0)); |
b4ad7b23 RS |
9014 | op0 = XEXP (XEXP (SET_SRC (PATTERN (jump)), 0), 0); |
9015 | op1 = XEXP (XEXP (SET_SRC (PATTERN (jump)), 0), 1); | |
9016 | ||
9017 | if (earliest) | |
9018 | *earliest = jump; | |
9019 | ||
9020 | /* If this branches to JUMP_LABEL when the condition is false, reverse | |
9021 | the condition. */ | |
b5d27be7 RS |
9022 | if (GET_CODE (XEXP (SET_SRC (PATTERN (jump)), 2)) == LABEL_REF |
9023 | && XEXP (XEXP (SET_SRC (PATTERN (jump)), 2), 0) == JUMP_LABEL (jump)) | |
b4ad7b23 RS |
9024 | code = reverse_condition (code), did_reverse_condition ^= 1; |
9025 | ||
9026 | /* If we are comparing a register with zero, see if the register is set | |
9027 | in the previous insn to a COMPARE or a comparison operation. Perform | |
9028 | the same tests as a function of STORE_FLAG_VALUE as find_comparison_args | |
9029 | in cse.c */ | |
9030 | ||
a18b5d98 | 9031 | while (GET_RTX_CLASS (code) == '<' && op1 == CONST0_RTX (GET_MODE (op0))) |
b4ad7b23 RS |
9032 | { |
9033 | /* Set non-zero when we find something of interest. */ | |
9034 | rtx x = 0; | |
9035 | ||
9036 | #ifdef HAVE_cc0 | |
9037 | /* If comparison with cc0, import actual comparison from compare | |
9038 | insn. */ | |
9039 | if (op0 == cc0_rtx) | |
9040 | { | |
9041 | if ((prev = prev_nonnote_insn (prev)) == 0 | |
9042 | || GET_CODE (prev) != INSN | |
9043 | || (set = single_set (prev)) == 0 | |
9044 | || SET_DEST (set) != cc0_rtx) | |
9045 | return 0; | |
9046 | ||
9047 | op0 = SET_SRC (set); | |
9048 | op1 = CONST0_RTX (GET_MODE (op0)); | |
9049 | if (earliest) | |
9050 | *earliest = prev; | |
9051 | } | |
9052 | #endif | |
9053 | ||
9054 | /* If this is a COMPARE, pick up the two things being compared. */ | |
9055 | if (GET_CODE (op0) == COMPARE) | |
9056 | { | |
9057 | op1 = XEXP (op0, 1); | |
9058 | op0 = XEXP (op0, 0); | |
9059 | continue; | |
9060 | } | |
9061 | else if (GET_CODE (op0) != REG) | |
9062 | break; | |
9063 | ||
9064 | /* Go back to the previous insn. Stop if it is not an INSN. We also | |
9065 | stop if it isn't a single set or if it has a REG_INC note because | |
9066 | we don't want to bother dealing with it. */ | |
9067 | ||
9068 | if ((prev = prev_nonnote_insn (prev)) == 0 | |
9069 | || GET_CODE (prev) != INSN | |
9070 | || FIND_REG_INC_NOTE (prev, 0) | |
9071 | || (set = single_set (prev)) == 0) | |
9072 | break; | |
9073 | ||
9074 | /* If this is setting OP0, get what it sets it to if it looks | |
9075 | relevant. */ | |
a95c317b | 9076 | if (rtx_equal_p (SET_DEST (set), op0)) |
b4ad7b23 RS |
9077 | { |
9078 | enum machine_mode inner_mode = GET_MODE (SET_SRC (set)); | |
9079 | ||
f283421d RH |
9080 | /* ??? We may not combine comparisons done in a CCmode with |
9081 | comparisons not done in a CCmode. This is to aid targets | |
9082 | like Alpha that have an IEEE compliant EQ instruction, and | |
9083 | a non-IEEE compliant BEQ instruction. The use of CCmode is | |
9084 | actually artificial, simply to prevent the combination, but | |
12f289ac JW |
9085 | should not affect other platforms. |
9086 | ||
9087 | However, we must allow VOIDmode comparisons to match either | |
9088 | CCmode or non-CCmode comparison, because some ports have | |
9089 | modeless comparisons inside branch patterns. | |
9090 | ||
9091 | ??? This mode check should perhaps look more like the mode check | |
9092 | in simplify_comparison in combine. */ | |
f283421d | 9093 | |
b4ad7b23 | 9094 | if ((GET_CODE (SET_SRC (set)) == COMPARE |
b565a316 RK |
9095 | || (((code == NE |
9096 | || (code == LT | |
9097 | && GET_MODE_CLASS (inner_mode) == MODE_INT | |
5fd8383e RK |
9098 | && (GET_MODE_BITSIZE (inner_mode) |
9099 | <= HOST_BITS_PER_WIDE_INT) | |
b565a316 | 9100 | && (STORE_FLAG_VALUE |
5fd8383e RK |
9101 | & ((HOST_WIDE_INT) 1 |
9102 | << (GET_MODE_BITSIZE (inner_mode) - 1)))) | |
b565a316 RK |
9103 | #ifdef FLOAT_STORE_FLAG_VALUE |
9104 | || (code == LT | |
9105 | && GET_MODE_CLASS (inner_mode) == MODE_FLOAT | |
9106 | && FLOAT_STORE_FLAG_VALUE < 0) | |
9107 | #endif | |
9108 | )) | |
f283421d | 9109 | && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<')) |
12f289ac JW |
9110 | && (((GET_MODE_CLASS (mode) == MODE_CC) |
9111 | == (GET_MODE_CLASS (inner_mode) == MODE_CC)) | |
9112 | || mode == VOIDmode || inner_mode == VOIDmode)) | |
b4ad7b23 | 9113 | x = SET_SRC (set); |
b565a316 RK |
9114 | else if (((code == EQ |
9115 | || (code == GE | |
5fd8383e RK |
9116 | && (GET_MODE_BITSIZE (inner_mode) |
9117 | <= HOST_BITS_PER_WIDE_INT) | |
b565a316 RK |
9118 | && GET_MODE_CLASS (inner_mode) == MODE_INT |
9119 | && (STORE_FLAG_VALUE | |
5fd8383e RK |
9120 | & ((HOST_WIDE_INT) 1 |
9121 | << (GET_MODE_BITSIZE (inner_mode) - 1)))) | |
b565a316 RK |
9122 | #ifdef FLOAT_STORE_FLAG_VALUE |
9123 | || (code == GE | |
9124 | && GET_MODE_CLASS (inner_mode) == MODE_FLOAT | |
9125 | && FLOAT_STORE_FLAG_VALUE < 0) | |
fb8ca0a4 | 9126 | #endif |
b565a316 | 9127 | )) |
f283421d | 9128 | && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<' |
12f289ac JW |
9129 | && (((GET_MODE_CLASS (mode) == MODE_CC) |
9130 | == (GET_MODE_CLASS (inner_mode) == MODE_CC)) | |
9131 | || mode == VOIDmode || inner_mode == VOIDmode)) | |
9132 | ||
b4ad7b23 RS |
9133 | { |
9134 | /* We might have reversed a LT to get a GE here. But this wasn't | |
9135 | actually the comparison of data, so we don't flag that we | |
9136 | have had to reverse the condition. */ | |
9137 | did_reverse_condition ^= 1; | |
9138 | reverse_code = 1; | |
9139 | x = SET_SRC (set); | |
9140 | } | |
71ef37f6 RK |
9141 | else |
9142 | break; | |
b4ad7b23 RS |
9143 | } |
9144 | ||
9145 | else if (reg_set_p (op0, prev)) | |
9146 | /* If this sets OP0, but not directly, we have to give up. */ | |
9147 | break; | |
9148 | ||
9149 | if (x) | |
9150 | { | |
9151 | if (GET_RTX_CLASS (GET_CODE (x)) == '<') | |
9152 | code = GET_CODE (x); | |
9153 | if (reverse_code) | |
9154 | { | |
9155 | code = reverse_condition (code); | |
9156 | did_reverse_condition ^= 1; | |
9157 | reverse_code = 0; | |
9158 | } | |
9159 | ||
9160 | op0 = XEXP (x, 0), op1 = XEXP (x, 1); | |
9161 | if (earliest) | |
9162 | *earliest = prev; | |
9163 | } | |
9164 | } | |
9165 | ||
9166 | /* If constant is first, put it last. */ | |
9167 | if (CONSTANT_P (op0)) | |
9168 | code = swap_condition (code), tem = op0, op0 = op1, op1 = tem; | |
9169 | ||
9170 | /* If OP0 is the result of a comparison, we weren't able to find what | |
9171 | was really being compared, so fail. */ | |
9172 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) | |
9173 | return 0; | |
9174 | ||
d8cfa4ee RK |
9175 | /* Canonicalize any ordered comparison with integers involving equality |
9176 | if we can do computations in the relevant mode and we do not | |
9177 | overflow. */ | |
9178 | ||
9179 | if (GET_CODE (op1) == CONST_INT | |
9180 | && GET_MODE (op0) != VOIDmode | |
9181 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT) | |
b4ad7b23 | 9182 | { |
5fd8383e RK |
9183 | HOST_WIDE_INT const_val = INTVAL (op1); |
9184 | unsigned HOST_WIDE_INT uconst_val = const_val; | |
d8cfa4ee RK |
9185 | unsigned HOST_WIDE_INT max_val |
9186 | = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0)); | |
b4ad7b23 RS |
9187 | |
9188 | switch (code) | |
d8cfa4ee RK |
9189 | { |
9190 | case LE: | |
e51712db | 9191 | if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) |
d8cfa4ee RK |
9192 | code = LT, op1 = GEN_INT (const_val + 1); |
9193 | break; | |
b4ad7b23 | 9194 | |
460f50dc R |
9195 | /* When cross-compiling, const_val might be sign-extended from |
9196 | BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */ | |
d8cfa4ee | 9197 | case GE: |
e51712db | 9198 | if ((HOST_WIDE_INT) (const_val & max_val) |
d8cfa4ee RK |
9199 | != (((HOST_WIDE_INT) 1 |
9200 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
9201 | code = GT, op1 = GEN_INT (const_val - 1); | |
9202 | break; | |
b4ad7b23 | 9203 | |
d8cfa4ee | 9204 | case LEU: |
460f50dc | 9205 | if (uconst_val < max_val) |
d8cfa4ee RK |
9206 | code = LTU, op1 = GEN_INT (uconst_val + 1); |
9207 | break; | |
b4ad7b23 | 9208 | |
d8cfa4ee RK |
9209 | case GEU: |
9210 | if (uconst_val != 0) | |
9211 | code = GTU, op1 = GEN_INT (uconst_val - 1); | |
9212 | break; | |
e9a25f70 JL |
9213 | |
9214 | default: | |
9215 | break; | |
d8cfa4ee | 9216 | } |
b4ad7b23 RS |
9217 | } |
9218 | ||
9219 | /* If this was floating-point and we reversed anything other than an | |
9220 | EQ or NE, return zero. */ | |
9221 | if (TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT | |
9222 | && did_reverse_condition && code != NE && code != EQ | |
1fc3d466 | 9223 | && ! flag_fast_math |
b4ad7b23 RS |
9224 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT) |
9225 | return 0; | |
9226 | ||
9227 | #ifdef HAVE_cc0 | |
9228 | /* Never return CC0; return zero instead. */ | |
9229 | if (op0 == cc0_rtx) | |
9230 | return 0; | |
9231 | #endif | |
9232 | ||
38a448ca | 9233 | return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
b4ad7b23 RS |
9234 | } |
9235 | ||
9236 | /* Similar to above routine, except that we also put an invariant last | |
9237 | unless both operands are invariants. */ | |
9238 | ||
9239 | rtx | |
9240 | get_condition_for_loop (x) | |
9241 | rtx x; | |
9242 | { | |
5fd8383e | 9243 | rtx comparison = get_condition (x, NULL_PTR); |
b4ad7b23 RS |
9244 | |
9245 | if (comparison == 0 | |
9246 | || ! invariant_p (XEXP (comparison, 0)) | |
9247 | || invariant_p (XEXP (comparison, 1))) | |
9248 | return comparison; | |
9249 | ||
38a448ca RH |
9250 | return gen_rtx_fmt_ee (swap_condition (GET_CODE (comparison)), VOIDmode, |
9251 | XEXP (comparison, 1), XEXP (comparison, 0)); | |
b4ad7b23 | 9252 | } |
8c660648 | 9253 | |
51723711 | 9254 | #ifdef HAVE_decrement_and_branch_on_count |
cac8ce95 DE |
9255 | /* Instrument loop for insertion of bct instruction. We distinguish between |
9256 | loops with compile-time bounds and those with run-time bounds. | |
9257 | Information from loop_iterations() is used to compute compile-time bounds. | |
9258 | Run-time bounds should use loop preconditioning, but currently ignored. | |
9259 | */ | |
9260 | ||
45f97e2e | 9261 | static void |
a2be868f MH |
9262 | insert_bct (loop) |
9263 | struct loop *loop; | |
8c660648 | 9264 | { |
cac8ce95 | 9265 | unsigned HOST_WIDE_INT n_iterations; |
a2be868f MH |
9266 | rtx loop_start = loop->start; |
9267 | rtx loop_end = loop->end; | |
9268 | struct loop_info *loop_info = loop->info; | |
9269 | int loop_num = loop->num; | |
8c660648 | 9270 | |
272df862 | 9271 | #if 0 |
cac8ce95 | 9272 | int increment_direction, compare_direction; |
cac8ce95 DE |
9273 | /* If the loop condition is <= or >=, the number of iteration |
9274 | is 1 more than the range of the bounds of the loop. */ | |
9275 | int add_iteration = 0; | |
cac8ce95 | 9276 | enum machine_mode loop_var_mode = word_mode; |
272df862 | 9277 | #endif |
8c660648 | 9278 | |
cac8ce95 | 9279 | /* It's impossible to instrument a competely unrolled loop. */ |
3c748bb6 | 9280 | if (loop_info->unroll_number == loop_info->n_iterations) |
8c660648 | 9281 | return; |
8c660648 | 9282 | |
cac8ce95 | 9283 | /* Make sure that the count register is not in use. */ |
a2be868f | 9284 | if (loop_info->used_count_register) |
8c660648 | 9285 | { |
cac8ce95 | 9286 | if (loop_dump_stream) |
8c660648 | 9287 | fprintf (loop_dump_stream, |
cac8ce95 DE |
9288 | "insert_bct %d: BCT instrumentation failed: count register already in use\n", |
9289 | loop_num); | |
8c660648 JL |
9290 | return; |
9291 | } | |
9292 | ||
cac8ce95 DE |
9293 | /* Make sure that the function has no indirect jumps. */ |
9294 | if (indirect_jump_in_function) | |
9295 | { | |
8c660648 JL |
9296 | if (loop_dump_stream) |
9297 | fprintf (loop_dump_stream, | |
cac8ce95 DE |
9298 | "insert_bct %d: BCT instrumentation failed: indirect jump in function\n", |
9299 | loop_num); | |
8c660648 JL |
9300 | return; |
9301 | } | |
9302 | ||
cac8ce95 DE |
9303 | /* Make sure that the last loop insn is a conditional jump. */ |
9304 | if (GET_CODE (PREV_INSN (loop_end)) != JUMP_INSN | |
9305 | || ! condjump_p (PREV_INSN (loop_end)) | |
9306 | || simplejump_p (PREV_INSN (loop_end))) | |
9307 | { | |
8c660648 JL |
9308 | if (loop_dump_stream) |
9309 | fprintf (loop_dump_stream, | |
cac8ce95 DE |
9310 | "insert_bct %d: BCT instrumentation failed: invalid jump at loop end\n", |
9311 | loop_num); | |
8c660648 JL |
9312 | return; |
9313 | } | |
8c660648 | 9314 | |
cac8ce95 DE |
9315 | /* Make sure that the loop does not contain a function call |
9316 | (the count register might be altered by the called function). */ | |
3c748bb6 | 9317 | if (loop_info->has_call) |
8c660648 | 9318 | { |
cac8ce95 DE |
9319 | if (loop_dump_stream) |
9320 | fprintf (loop_dump_stream, | |
9321 | "insert_bct %d: BCT instrumentation failed: function call in loop\n", | |
9322 | loop_num); | |
9323 | return; | |
9324 | } | |
8c660648 | 9325 | |
cac8ce95 DE |
9326 | /* Make sure that the loop does not jump via a table. |
9327 | (the count register might be used to perform the branch on table). */ | |
3c748bb6 | 9328 | if (loop_info->has_tablejump) |
cac8ce95 | 9329 | { |
8c368ee2 DE |
9330 | if (loop_dump_stream) |
9331 | fprintf (loop_dump_stream, | |
9332 | "insert_bct %d: BCT instrumentation failed: computed branch in the loop\n", | |
9333 | loop_num); | |
9334 | return; | |
cac8ce95 | 9335 | } |
8c660648 | 9336 | |
cac8ce95 | 9337 | /* Account for loop unrolling in instrumented iteration count. */ |
302670f3 MH |
9338 | if (loop_info->unroll_number > 1) |
9339 | n_iterations = loop_info->n_iterations / loop_info->unroll_number; | |
cac8ce95 | 9340 | else |
302670f3 | 9341 | n_iterations = loop_info->n_iterations; |
8c660648 | 9342 | |
cac8ce95 DE |
9343 | if (n_iterations != 0 && n_iterations < 3) |
9344 | { | |
9345 | /* Allow an enclosing outer loop to benefit if possible. */ | |
9346 | if (loop_dump_stream) | |
9347 | fprintf (loop_dump_stream, | |
9348 | "insert_bct %d: Too few iterations to benefit from BCT optimization\n", | |
9349 | loop_num); | |
9350 | return; | |
9351 | } | |
8c660648 | 9352 | |
cac8ce95 | 9353 | /* Try to instrument the loop. */ |
8c660648 | 9354 | |
cac8ce95 DE |
9355 | /* Handle the simpler case, where the bounds are known at compile time. */ |
9356 | if (n_iterations > 0) | |
9357 | { | |
a2be868f MH |
9358 | struct loop *outer_loop; |
9359 | struct loop_info *outer_loop_info; | |
9360 | ||
cac8ce95 | 9361 | /* Mark all enclosing loops that they cannot use count register. */ |
a2be868f MH |
9362 | for (outer_loop = loop; outer_loop; outer_loop = outer_loop->outer) |
9363 | { | |
9364 | outer_loop_info = outer_loop->info; | |
9365 | outer_loop_info->used_count_register = 1; | |
9366 | } | |
8c660648 | 9367 | instrument_loop_bct (loop_start, loop_end, GEN_INT (n_iterations)); |
8c660648 JL |
9368 | return; |
9369 | } | |
9370 | ||
cac8ce95 DE |
9371 | /* Handle the more complex case, that the bounds are NOT known |
9372 | at compile time. In this case we generate run_time calculation | |
9373 | of the number of iterations. */ | |
9374 | ||
302670f3 | 9375 | if (loop_info->iteration_var == 0) |
400d6322 DE |
9376 | { |
9377 | if (loop_dump_stream) | |
9378 | fprintf (loop_dump_stream, | |
9379 | "insert_bct %d: BCT Runtime Instrumentation failed: no loop iteration variable found\n", | |
9380 | loop_num); | |
9381 | return; | |
9382 | } | |
9383 | ||
302670f3 MH |
9384 | if (GET_MODE_CLASS (GET_MODE (loop_info->iteration_var)) != MODE_INT |
9385 | || GET_MODE_SIZE (GET_MODE (loop_info->iteration_var)) != UNITS_PER_WORD) | |
cac8ce95 DE |
9386 | { |
9387 | if (loop_dump_stream) | |
9388 | fprintf (loop_dump_stream, | |
400d6322 | 9389 | "insert_bct %d: BCT Runtime Instrumentation failed: loop variable not integer\n", |
cac8ce95 DE |
9390 | loop_num); |
9391 | return; | |
9392 | } | |
8c660648 JL |
9393 | |
9394 | /* With runtime bounds, if the compare is of the form '!=' we give up */ | |
302670f3 | 9395 | if (loop_info->comparison_code == NE) |
cac8ce95 DE |
9396 | { |
9397 | if (loop_dump_stream) | |
9398 | fprintf (loop_dump_stream, | |
400d6322 | 9399 | "insert_bct %d: BCT Runtime Instrumentation failed: runtime bounds with != comparison\n", |
cac8ce95 DE |
9400 | loop_num); |
9401 | return; | |
9402 | } | |
9403 | /* Use common loop preconditioning code instead. */ | |
9404 | #if 0 | |
9405 | else | |
9406 | { | |
9407 | /* We rely on the existence of run-time guard to ensure that the | |
9408 | loop executes at least once. */ | |
9409 | rtx sequence; | |
9410 | rtx iterations_num_reg; | |
8c660648 | 9411 | |
cac8ce95 DE |
9412 | unsigned HOST_WIDE_INT increment_value_abs |
9413 | = INTVAL (increment) * increment_direction; | |
8c660648 | 9414 | |
cac8ce95 DE |
9415 | /* make sure that the increment is a power of two, otherwise (an |
9416 | expensive) divide is needed. */ | |
9417 | if (exact_log2 (increment_value_abs) == -1) | |
9418 | { | |
9419 | if (loop_dump_stream) | |
9420 | fprintf (loop_dump_stream, | |
9421 | "insert_bct: not instrumenting BCT because the increment is not power of 2\n"); | |
9422 | return; | |
9423 | } | |
8c660648 | 9424 | |
cac8ce95 DE |
9425 | /* compute the number of iterations */ |
9426 | start_sequence (); | |
8c660648 | 9427 | { |
cac8ce95 | 9428 | rtx temp_reg; |
8c660648 | 9429 | |
cac8ce95 DE |
9430 | /* Again, the number of iterations is calculated by: |
9431 | ; | |
9432 | ; compare-val - initial-val + (increment -1) + additional-iteration | |
9433 | ; num_iterations = ----------------------------------------------------------------- | |
9434 | ; increment | |
8c660648 | 9435 | */ |
cac8ce95 DE |
9436 | /* ??? Do we have to call copy_rtx here before passing rtx to |
9437 | expand_binop? */ | |
9438 | if (compare_direction > 0) | |
9439 | { | |
9440 | /* <, <= :the loop variable is increasing */ | |
9441 | temp_reg = expand_binop (loop_var_mode, sub_optab, | |
9442 | comparison_value, initial_value, | |
9443 | NULL_RTX, 0, OPTAB_LIB_WIDEN); | |
9444 | } | |
9445 | else | |
9446 | { | |
9447 | temp_reg = expand_binop (loop_var_mode, sub_optab, | |
9448 | initial_value, comparison_value, | |
9449 | NULL_RTX, 0, OPTAB_LIB_WIDEN); | |
9450 | } | |
8c660648 | 9451 | |
cac8ce95 DE |
9452 | if (increment_value_abs - 1 + add_iteration != 0) |
9453 | temp_reg = expand_binop (loop_var_mode, add_optab, temp_reg, | |
9454 | GEN_INT (increment_value_abs - 1 | |
9455 | + add_iteration), | |
9456 | NULL_RTX, 0, OPTAB_LIB_WIDEN); | |
8c660648 | 9457 | |
cac8ce95 | 9458 | if (increment_value_abs != 1) |
66b9b71f MT |
9459 | iterations_num_reg = expand_binop (loop_var_mode, asr_optab, |
9460 | temp_reg, | |
9461 | GEN_INT (exact_log2 (increment_value_abs)), | |
9462 | NULL_RTX, 0, OPTAB_LIB_WIDEN); | |
cac8ce95 DE |
9463 | else |
9464 | iterations_num_reg = temp_reg; | |
9465 | } | |
9466 | sequence = gen_sequence (); | |
9467 | end_sequence (); | |
9468 | emit_insn_before (sequence, loop_start); | |
9469 | instrument_loop_bct (loop_start, loop_end, iterations_num_reg); | |
8c660648 | 9470 | } |
cac8ce95 DE |
9471 | |
9472 | return; | |
9473 | #endif /* Complex case */ | |
8c660648 JL |
9474 | } |
9475 | ||
cac8ce95 DE |
9476 | /* Instrument loop by inserting a bct in it as follows: |
9477 | 1. A new counter register is created. | |
9478 | 2. In the head of the loop the new variable is initialized to the value | |
9479 | passed in the loop_num_iterations parameter. | |
8c660648 | 9480 | 3. At the end of the loop, comparison of the register with 0 is generated. |
cac8ce95 DE |
9481 | The created comparison follows the pattern defined for the |
9482 | decrement_and_branch_on_count insn, so this insn will be generated. | |
9483 | 4. The branch on the old variable are deleted. The compare must remain | |
9484 | because it might be used elsewhere. If the loop-variable or condition | |
9485 | register are used elsewhere, they will be eliminated by flow. */ | |
8c660648 JL |
9486 | |
9487 | static void | |
9488 | instrument_loop_bct (loop_start, loop_end, loop_num_iterations) | |
9489 | rtx loop_start, loop_end; | |
9490 | rtx loop_num_iterations; | |
9491 | { | |
cac8ce95 | 9492 | rtx counter_reg; |
8c660648 | 9493 | rtx start_label; |
8c660648 | 9494 | rtx sequence; |
8c660648 | 9495 | |
8c660648 JL |
9496 | if (HAVE_decrement_and_branch_on_count) |
9497 | { | |
9498 | if (loop_dump_stream) | |
cac8ce95 DE |
9499 | { |
9500 | fputs ("instrument_bct: Inserting BCT (", loop_dump_stream); | |
9501 | if (GET_CODE (loop_num_iterations) == CONST_INT) | |
9502 | fprintf (loop_dump_stream, HOST_WIDE_INT_PRINT_DEC, | |
9503 | INTVAL (loop_num_iterations)); | |
9504 | else | |
9505 | fputs ("runtime", loop_dump_stream); | |
9506 | fputs (" iterations)", loop_dump_stream); | |
9507 | } | |
8c660648 | 9508 | |
5accd822 DE |
9509 | /* Discard original jump to continue loop. Original compare result |
9510 | may still be live, so it cannot be discarded explicitly. */ | |
8c660648 JL |
9511 | delete_insn (PREV_INSN (loop_end)); |
9512 | ||
cac8ce95 | 9513 | /* Insert the label which will delimit the start of the loop. */ |
8c660648 JL |
9514 | start_label = gen_label_rtx (); |
9515 | emit_label_after (start_label, loop_start); | |
9516 | ||
cac8ce95 | 9517 | /* Insert initialization of the count register into the loop header. */ |
8c660648 | 9518 | start_sequence (); |
cac8ce95 DE |
9519 | counter_reg = gen_reg_rtx (word_mode); |
9520 | emit_insn (gen_move_insn (counter_reg, loop_num_iterations)); | |
8c660648 JL |
9521 | sequence = gen_sequence (); |
9522 | end_sequence (); | |
5accd822 | 9523 | emit_insn_before (sequence, loop_start); |
8c660648 | 9524 | |
cac8ce95 | 9525 | /* Insert new comparison on the count register instead of the |
8c660648 JL |
9526 | old one, generating the needed BCT pattern (that will be |
9527 | later recognized by assembly generation phase). */ | |
cac8ce95 | 9528 | emit_jump_insn_before (gen_decrement_and_branch_on_count (counter_reg, |
5accd822 | 9529 | start_label), |
8c660648 JL |
9530 | loop_end); |
9531 | LABEL_NUSES (start_label)++; | |
9532 | } | |
9533 | ||
8c660648 | 9534 | } |
51723711 KG |
9535 | #endif /* HAVE_decrement_and_branch_on_count */ |
9536 | ||
2a1777af | 9537 | /* Scan the function and determine whether it has indirect (computed) jumps. |
8c660648 | 9538 | |
2a1777af JL |
9539 | This is taken mostly from flow.c; similar code exists elsewhere |
9540 | in the compiler. It may be useful to put this into rtlanal.c. */ | |
8c660648 JL |
9541 | static int |
9542 | indirect_jump_in_function_p (start) | |
9543 | rtx start; | |
9544 | { | |
9545 | rtx insn; | |
8c660648 | 9546 | |
2a1777af JL |
9547 | for (insn = start; insn; insn = NEXT_INSN (insn)) |
9548 | if (computed_jump_p (insn)) | |
9549 | return 1; | |
7019d00e L |
9550 | |
9551 | return 0; | |
8c660648 | 9552 | } |
41a972a9 MM |
9553 | |
9554 | /* Add MEM to the LOOP_MEMS array, if appropriate. See the | |
9555 | documentation for LOOP_MEMS for the definition of `appropriate'. | |
9556 | This function is called from prescan_loop via for_each_rtx. */ | |
9557 | ||
9558 | static int | |
9559 | insert_loop_mem (mem, data) | |
9560 | rtx *mem; | |
e51712db | 9561 | void *data ATTRIBUTE_UNUSED; |
41a972a9 MM |
9562 | { |
9563 | int i; | |
9564 | rtx m = *mem; | |
9565 | ||
9566 | if (m == NULL_RTX) | |
9567 | return 0; | |
9568 | ||
9569 | switch (GET_CODE (m)) | |
9570 | { | |
9571 | case MEM: | |
9572 | break; | |
9573 | ||
27114460 RH |
9574 | case CLOBBER: |
9575 | /* We're not interested in MEMs that are only clobbered. */ | |
9576 | return -1; | |
9577 | ||
41a972a9 MM |
9578 | case CONST_DOUBLE: |
9579 | /* We're not interested in the MEM associated with a | |
9580 | CONST_DOUBLE, so there's no need to traverse into this. */ | |
9581 | return -1; | |
9582 | ||
4ce580a2 RE |
9583 | case EXPR_LIST: |
9584 | /* We're not interested in any MEMs that only appear in notes. */ | |
9585 | return -1; | |
9586 | ||
41a972a9 MM |
9587 | default: |
9588 | /* This is not a MEM. */ | |
9589 | return 0; | |
9590 | } | |
9591 | ||
9592 | /* See if we've already seen this MEM. */ | |
9593 | for (i = 0; i < loop_mems_idx; ++i) | |
9594 | if (rtx_equal_p (m, loop_mems[i].mem)) | |
9595 | { | |
9596 | if (GET_MODE (m) != GET_MODE (loop_mems[i].mem)) | |
9597 | /* The modes of the two memory accesses are different. If | |
9598 | this happens, something tricky is going on, and we just | |
9599 | don't optimize accesses to this MEM. */ | |
9600 | loop_mems[i].optimize = 0; | |
9601 | ||
9602 | return 0; | |
9603 | } | |
9604 | ||
9605 | /* Resize the array, if necessary. */ | |
9606 | if (loop_mems_idx == loop_mems_allocated) | |
9607 | { | |
9608 | if (loop_mems_allocated != 0) | |
9609 | loop_mems_allocated *= 2; | |
9610 | else | |
9611 | loop_mems_allocated = 32; | |
9612 | ||
9613 | loop_mems = (loop_mem_info*) | |
9614 | xrealloc (loop_mems, | |
9615 | loop_mems_allocated * sizeof (loop_mem_info)); | |
9616 | } | |
9617 | ||
9618 | /* Actually insert the MEM. */ | |
9619 | loop_mems[loop_mems_idx].mem = m; | |
9620 | /* We can't hoist this MEM out of the loop if it's a BLKmode MEM | |
9621 | because we can't put it in a register. We still store it in the | |
9622 | table, though, so that if we see the same address later, but in a | |
9623 | non-BLK mode, we'll not think we can optimize it at that point. */ | |
22d37998 | 9624 | loop_mems[loop_mems_idx].optimize = (GET_MODE (m) != BLKmode); |
41a972a9 MM |
9625 | loop_mems[loop_mems_idx].reg = NULL_RTX; |
9626 | ++loop_mems_idx; | |
8deb8e2c MM |
9627 | |
9628 | return 0; | |
41a972a9 MM |
9629 | } |
9630 | ||
4b259e3f | 9631 | /* Like load_mems, but also ensures that SET_IN_LOOP, |
41a972a9 MM |
9632 | MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct |
9633 | values after load_mems. */ | |
9634 | ||
9635 | static void | |
a2be868f MH |
9636 | load_mems_and_recount_loop_regs_set (loop, insn_count) |
9637 | const struct loop *loop; | |
41a972a9 MM |
9638 | int *insn_count; |
9639 | { | |
9640 | int nregs = max_reg_num (); | |
9641 | ||
a2be868f | 9642 | load_mems (loop); |
41a972a9 | 9643 | |
4b259e3f | 9644 | /* Recalculate set_in_loop and friends since load_mems may have |
41a972a9 MM |
9645 | created new registers. */ |
9646 | if (max_reg_num () > nregs) | |
9647 | { | |
9648 | int i; | |
9649 | int old_nregs; | |
9650 | ||
9651 | old_nregs = nregs; | |
9652 | nregs = max_reg_num (); | |
9653 | ||
4b259e3f | 9654 | if ((unsigned) nregs > set_in_loop->num_elements) |
8deb8e2c MM |
9655 | { |
9656 | /* Grow all the arrays. */ | |
4b259e3f | 9657 | VARRAY_GROW (set_in_loop, nregs); |
8deb8e2c | 9658 | VARRAY_GROW (n_times_set, nregs); |
8deb8e2c | 9659 | VARRAY_GROW (may_not_optimize, nregs); |
d6b44532 | 9660 | VARRAY_GROW (reg_single_usage, nregs); |
8deb8e2c MM |
9661 | } |
9662 | /* Clear the arrays */ | |
4b259e3f | 9663 | bzero ((char *) &set_in_loop->data, nregs * sizeof (int)); |
8deb8e2c | 9664 | bzero ((char *) &may_not_optimize->data, nregs * sizeof (char)); |
d6b44532 | 9665 | bzero ((char *) ®_single_usage->data, nregs * sizeof (rtx)); |
41a972a9 | 9666 | |
a2be868f | 9667 | count_loop_regs_set (loop->top ? loop->top : loop->start, loop->end, |
41a972a9 MM |
9668 | may_not_optimize, reg_single_usage, |
9669 | insn_count, nregs); | |
9670 | ||
9671 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
8deb8e2c MM |
9672 | { |
9673 | VARRAY_CHAR (may_not_optimize, i) = 1; | |
4b259e3f | 9674 | VARRAY_INT (set_in_loop, i) = 1; |
8deb8e2c | 9675 | } |
41a972a9 | 9676 | |
dd0208b9 DM |
9677 | #ifdef AVOID_CCMODE_COPIES |
9678 | /* Don't try to move insns which set CC registers if we should not | |
9679 | create CCmode register copies. */ | |
78b87d18 | 9680 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) |
dd0208b9 | 9681 | if (GET_MODE_CLASS (GET_MODE (regno_reg_rtx[i])) == MODE_CC) |
8deb8e2c | 9682 | VARRAY_CHAR (may_not_optimize, i) = 1; |
dd0208b9 DM |
9683 | #endif |
9684 | ||
4b259e3f R |
9685 | /* Set n_times_set for the new registers. */ |
9686 | bcopy ((char *) (&set_in_loop->data.i[0] + old_nregs), | |
9687 | (char *) (&n_times_set->data.i[0] + old_nregs), | |
41a972a9 MM |
9688 | (nregs - old_nregs) * sizeof (int)); |
9689 | } | |
9690 | } | |
9691 | ||
a2be868f | 9692 | /* Move MEMs into registers for the duration of the loop. */ |
41a972a9 MM |
9693 | |
9694 | static void | |
a2be868f MH |
9695 | load_mems (loop) |
9696 | const struct loop *loop; | |
41a972a9 MM |
9697 | { |
9698 | int maybe_never = 0; | |
9699 | int i; | |
9700 | rtx p; | |
9701 | rtx label = NULL_RTX; | |
6a651371 | 9702 | rtx end_label = NULL_RTX; |
328f4006 BS |
9703 | /* Nonzero if the next instruction may never be executed. */ |
9704 | int next_maybe_never = 0; | |
c29f60c0 | 9705 | int last_max_reg = max_reg_num (); |
41a972a9 | 9706 | |
328f4006 BS |
9707 | if (loop_mems_idx == 0) |
9708 | return; | |
41a972a9 | 9709 | |
328f4006 BS |
9710 | /* Check to see if it's possible that some instructions in the |
9711 | loop are never executed. */ | |
a2be868f MH |
9712 | for (p = next_insn_in_loop (loop, loop->scan_start); |
9713 | p != NULL_RTX && ! maybe_never; | |
9714 | p = next_insn_in_loop (loop, p)) | |
328f4006 BS |
9715 | { |
9716 | if (GET_CODE (p) == CODE_LABEL) | |
9717 | maybe_never = 1; | |
9718 | else if (GET_CODE (p) == JUMP_INSN | |
9719 | /* If we enter the loop in the middle, and scan | |
9720 | around to the beginning, don't set maybe_never | |
9721 | for that. This must be an unconditional jump, | |
9722 | otherwise the code at the top of the loop might | |
9723 | never be executed. Unconditional jumps are | |
9724 | followed a by barrier then loop end. */ | |
9725 | && ! (GET_CODE (p) == JUMP_INSN | |
a2be868f MH |
9726 | && JUMP_LABEL (p) == loop->top |
9727 | && NEXT_INSN (NEXT_INSN (p)) == loop->end | |
328f4006 | 9728 | && simplejump_p (p))) |
41a972a9 | 9729 | { |
328f4006 BS |
9730 | if (!condjump_p (p)) |
9731 | /* Something complicated. */ | |
41a972a9 | 9732 | maybe_never = 1; |
328f4006 BS |
9733 | else |
9734 | /* If there are any more instructions in the loop, they | |
9735 | might not be reached. */ | |
9736 | next_maybe_never = 1; | |
9737 | } | |
9738 | else if (next_maybe_never) | |
9739 | maybe_never = 1; | |
9740 | } | |
9741 | ||
9742 | /* Actually move the MEMs. */ | |
9743 | for (i = 0; i < loop_mems_idx; ++i) | |
9744 | { | |
c29f60c0 | 9745 | regset_head copies; |
328f4006 BS |
9746 | int written = 0; |
9747 | rtx reg; | |
9748 | rtx mem = loop_mems[i].mem; | |
9749 | rtx mem_list_entry; | |
41a972a9 | 9750 | |
328f4006 BS |
9751 | if (MEM_VOLATILE_P (mem) |
9752 | || invariant_p (XEXP (mem, 0)) != 1) | |
9753 | /* There's no telling whether or not MEM is modified. */ | |
9754 | loop_mems[i].optimize = 0; | |
9755 | ||
9756 | /* Go through the MEMs written to in the loop to see if this | |
9757 | one is aliased by one of them. */ | |
9758 | mem_list_entry = loop_store_mems; | |
9759 | while (mem_list_entry) | |
41a972a9 | 9760 | { |
328f4006 BS |
9761 | if (rtx_equal_p (mem, XEXP (mem_list_entry, 0))) |
9762 | written = 1; | |
9763 | else if (true_dependence (XEXP (mem_list_entry, 0), VOIDmode, | |
9764 | mem, rtx_varies_p)) | |
41a972a9 | 9765 | { |
328f4006 BS |
9766 | /* MEM is indeed aliased by this store. */ |
9767 | loop_mems[i].optimize = 0; | |
9768 | break; | |
41a972a9 | 9769 | } |
328f4006 BS |
9770 | mem_list_entry = XEXP (mem_list_entry, 1); |
9771 | } | |
f0b60c1c SM |
9772 | |
9773 | if (flag_float_store && written | |
9774 | && GET_MODE_CLASS (GET_MODE (mem)) == MODE_FLOAT) | |
9775 | loop_mems[i].optimize = 0; | |
9776 | ||
328f4006 BS |
9777 | /* If this MEM is written to, we must be sure that there |
9778 | are no reads from another MEM that aliases this one. */ | |
9779 | if (loop_mems[i].optimize && written) | |
9780 | { | |
9781 | int j; | |
41a972a9 | 9782 | |
328f4006 BS |
9783 | for (j = 0; j < loop_mems_idx; ++j) |
9784 | { | |
9785 | if (j == i) | |
9786 | continue; | |
9787 | else if (true_dependence (mem, | |
9788 | VOIDmode, | |
9789 | loop_mems[j].mem, | |
9790 | rtx_varies_p)) | |
41a972a9 | 9791 | { |
328f4006 BS |
9792 | /* It's not safe to hoist loop_mems[i] out of |
9793 | the loop because writes to it might not be | |
9794 | seen by reads from loop_mems[j]. */ | |
9795 | loop_mems[i].optimize = 0; | |
9796 | break; | |
41a972a9 MM |
9797 | } |
9798 | } | |
328f4006 | 9799 | } |
41a972a9 | 9800 | |
328f4006 BS |
9801 | if (maybe_never && may_trap_p (mem)) |
9802 | /* We can't access the MEM outside the loop; it might | |
9803 | cause a trap that wouldn't have happened otherwise. */ | |
9804 | loop_mems[i].optimize = 0; | |
41a972a9 | 9805 | |
328f4006 BS |
9806 | if (!loop_mems[i].optimize) |
9807 | /* We thought we were going to lift this MEM out of the | |
9808 | loop, but later discovered that we could not. */ | |
9809 | continue; | |
41a972a9 | 9810 | |
c29f60c0 BS |
9811 | INIT_REG_SET (&copies); |
9812 | ||
328f4006 BS |
9813 | /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in |
9814 | order to keep scan_loop from moving stores to this MEM | |
9815 | out of the loop just because this REG is neither a | |
9816 | user-variable nor used in the loop test. */ | |
9817 | reg = gen_reg_rtx (GET_MODE (mem)); | |
9818 | REG_USERVAR_P (reg) = 1; | |
9819 | loop_mems[i].reg = reg; | |
9820 | ||
9821 | /* Now, replace all references to the MEM with the | |
9822 | corresponding pesudos. */ | |
c29f60c0 | 9823 | maybe_never = 0; |
a2be868f | 9824 | for (p = next_insn_in_loop (loop, loop->scan_start); |
328f4006 | 9825 | p != NULL_RTX; |
a2be868f | 9826 | p = next_insn_in_loop (loop, p)) |
328f4006 BS |
9827 | { |
9828 | rtx_and_int ri; | |
c29f60c0 BS |
9829 | rtx set; |
9830 | ||
9831 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
9832 | { | |
9833 | /* See if this copies the mem into a register that isn't | |
9834 | modified afterwards. We'll try to do copy propagation | |
9835 | a little further on. */ | |
9836 | set = single_set (p); | |
9837 | if (set | |
9838 | /* @@@ This test is _way_ too conservative. */ | |
9839 | && ! maybe_never | |
9840 | && GET_CODE (SET_DEST (set)) == REG | |
9841 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER | |
9842 | && REGNO (SET_DEST (set)) < last_max_reg | |
9843 | && VARRAY_INT (n_times_set, REGNO (SET_DEST (set))) == 1 | |
9844 | && rtx_equal_p (SET_SRC (set), loop_mems[i].mem)) | |
9845 | SET_REGNO_REG_SET (&copies, REGNO (SET_DEST (set))); | |
9846 | ri.r = p; | |
9847 | ri.i = i; | |
9848 | for_each_rtx (&p, replace_loop_mem, &ri); | |
9849 | } | |
9850 | ||
9851 | if (GET_CODE (p) == CODE_LABEL | |
9852 | || GET_CODE (p) == JUMP_INSN) | |
9853 | maybe_never = 1; | |
328f4006 | 9854 | } |
41a972a9 | 9855 | |
328f4006 BS |
9856 | if (! apply_change_group ()) |
9857 | /* We couldn't replace all occurrences of the MEM. */ | |
9858 | loop_mems[i].optimize = 0; | |
9859 | else | |
9860 | { | |
c29f60c0 | 9861 | int j; |
328f4006 | 9862 | rtx set; |
41a972a9 | 9863 | |
328f4006 BS |
9864 | /* Load the memory immediately before START, which is |
9865 | the NOTE_LOOP_BEG. */ | |
9866 | set = gen_move_insn (reg, mem); | |
a2be868f | 9867 | emit_insn_before (set, loop->start); |
41a972a9 | 9868 | |
328f4006 BS |
9869 | if (written) |
9870 | { | |
9871 | if (label == NULL_RTX) | |
41a972a9 | 9872 | { |
328f4006 BS |
9873 | /* We must compute the former |
9874 | right-after-the-end label before we insert | |
9875 | the new one. */ | |
a2be868f | 9876 | end_label = next_label (loop->end); |
328f4006 | 9877 | label = gen_label_rtx (); |
a2be868f | 9878 | emit_label_after (label, loop->end); |
41a972a9 MM |
9879 | } |
9880 | ||
328f4006 BS |
9881 | /* Store the memory immediately after END, which is |
9882 | the NOTE_LOOP_END. */ | |
9883 | set = gen_move_insn (copy_rtx (mem), reg); | |
9884 | emit_insn_after (set, label); | |
9885 | } | |
9886 | ||
9887 | if (loop_dump_stream) | |
9888 | { | |
9889 | fprintf (loop_dump_stream, "Hoisted regno %d %s from ", | |
9890 | REGNO (reg), (written ? "r/w" : "r/o")); | |
9891 | print_rtl (loop_dump_stream, mem); | |
9892 | fputc ('\n', loop_dump_stream); | |
41a972a9 | 9893 | } |
c29f60c0 BS |
9894 | |
9895 | /* Attempt a bit of copy propagation. This helps untangle the | |
9896 | data flow, and enables {basic,general}_induction_var to find | |
9897 | more bivs/givs. */ | |
9898 | EXECUTE_IF_SET_IN_REG_SET | |
9899 | (&copies, FIRST_PSEUDO_REGISTER, j, | |
9900 | { | |
a2be868f | 9901 | try_copy_prop (loop, loop_mems[i].reg, j); |
c29f60c0 BS |
9902 | }); |
9903 | CLEAR_REG_SET (&copies); | |
41a972a9 MM |
9904 | } |
9905 | } | |
9906 | ||
9907 | if (label != NULL_RTX) | |
9908 | { | |
9909 | /* Now, we need to replace all references to the previous exit | |
9910 | label with the new one. */ | |
59d4e481 KGA |
9911 | rtx_pair rr; |
9912 | rr.r1 = end_label; | |
9913 | rr.r2 = label; | |
41a972a9 | 9914 | |
a2be868f | 9915 | for (p = loop->start; p != loop->end; p = NEXT_INSN (p)) |
7940acc4 JW |
9916 | { |
9917 | for_each_rtx (&p, replace_label, &rr); | |
9918 | ||
9919 | /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL | |
9920 | field. This is not handled by for_each_rtx because it doesn't | |
9921 | handle unprinted ('0') fields. We need to update JUMP_LABEL | |
9922 | because the immediately following unroll pass will use it. | |
9923 | replace_label would not work anyways, because that only handles | |
9924 | LABEL_REFs. */ | |
9925 | if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == end_label) | |
9926 | JUMP_LABEL (p) = label; | |
9927 | } | |
41a972a9 MM |
9928 | } |
9929 | } | |
9930 | ||
8571e492 BS |
9931 | /* For communication between note_reg_stored and its caller. */ |
9932 | struct note_reg_stored_arg | |
9933 | { | |
9934 | int set_seen; | |
9935 | rtx reg; | |
9936 | }; | |
9937 | ||
9938 | /* Called via note_stores, record in SET_SEEN whether X, which is written, | |
9939 | is equal to ARG. */ | |
9940 | static void | |
9941 | note_reg_stored (x, setter, arg) | |
272df862 | 9942 | rtx x, setter ATTRIBUTE_UNUSED; |
8571e492 BS |
9943 | void *arg; |
9944 | { | |
9945 | struct note_reg_stored_arg *t = (struct note_reg_stored_arg *)arg; | |
9946 | if (t->reg == x) | |
9947 | t->set_seen = 1; | |
9948 | } | |
9949 | ||
c29f60c0 BS |
9950 | /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT. |
9951 | There must be exactly one insn that sets this pseudo; it will be | |
9952 | deleted if all replacements succeed and we can prove that the register | |
9953 | is not used after the loop. | |
9954 | The arguments SCAN_START, LOOP_TOP and END are as in load_mems. */ | |
9955 | static void | |
a2be868f MH |
9956 | try_copy_prop (loop, replacement, regno) |
9957 | const struct loop *loop; | |
9958 | rtx replacement; | |
c29f60c0 BS |
9959 | int regno; |
9960 | { | |
8571e492 BS |
9961 | /* This is the reg that we are copying from. */ |
9962 | rtx reg_rtx = regno_reg_rtx[regno]; | |
c29f60c0 BS |
9963 | rtx init_insn = 0; |
9964 | rtx insn; | |
8571e492 BS |
9965 | /* These help keep track of whether we replaced all uses of the reg. */ |
9966 | int replaced_last = 0; | |
9967 | int store_is_first = 0; | |
9968 | ||
a2be868f | 9969 | for (insn = next_insn_in_loop (loop, loop->scan_start); |
c29f60c0 | 9970 | insn != NULL_RTX; |
a2be868f | 9971 | insn = next_insn_in_loop (loop, insn)) |
c29f60c0 BS |
9972 | { |
9973 | rtx set; | |
d42971c4 | 9974 | |
8571e492 BS |
9975 | /* Only substitute within one extended basic block from the initializing |
9976 | insn. */ | |
9977 | if (GET_CODE (insn) == CODE_LABEL && init_insn) | |
9978 | break; | |
d42971c4 | 9979 | |
c29f60c0 BS |
9980 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') |
9981 | continue; | |
8571e492 BS |
9982 | |
9983 | /* Is this the initializing insn? */ | |
c29f60c0 BS |
9984 | set = single_set (insn); |
9985 | if (set | |
9986 | && GET_CODE (SET_DEST (set)) == REG | |
9987 | && REGNO (SET_DEST (set)) == regno) | |
9988 | { | |
9989 | if (init_insn) | |
9990 | abort (); | |
8571e492 | 9991 | |
c29f60c0 | 9992 | init_insn = insn; |
8571e492 BS |
9993 | if (REGNO_FIRST_UID (regno) == INSN_UID (insn)) |
9994 | store_is_first = 1; | |
9995 | } | |
9996 | ||
9997 | /* Only substitute after seeing the initializing insn. */ | |
9998 | if (init_insn && insn != init_insn) | |
9999 | { | |
10000 | struct note_reg_stored_arg arg; | |
10001 | rtx array[3]; | |
10002 | array[0] = reg_rtx; | |
10003 | array[1] = replacement; | |
10004 | array[2] = insn; | |
10005 | ||
10006 | for_each_rtx (&insn, replace_loop_reg, array); | |
10007 | if (REGNO_LAST_UID (regno) == INSN_UID (insn)) | |
10008 | replaced_last = 1; | |
10009 | ||
10010 | /* Stop replacing when REPLACEMENT is modified. */ | |
10011 | arg.reg = replacement; | |
10012 | arg.set_seen = 0; | |
10013 | note_stores (PATTERN (insn), note_reg_stored, &arg); | |
10014 | if (arg.set_seen) | |
10015 | break; | |
c29f60c0 | 10016 | } |
c29f60c0 BS |
10017 | } |
10018 | if (! init_insn) | |
10019 | abort (); | |
10020 | if (apply_change_group ()) | |
10021 | { | |
8571e492 BS |
10022 | if (loop_dump_stream) |
10023 | fprintf (loop_dump_stream, " Replaced reg %d", regno); | |
10024 | if (store_is_first && replaced_last) | |
c29f60c0 BS |
10025 | { |
10026 | PUT_CODE (init_insn, NOTE); | |
10027 | NOTE_LINE_NUMBER (init_insn) = NOTE_INSN_DELETED; | |
8571e492 BS |
10028 | if (loop_dump_stream) |
10029 | fprintf (loop_dump_stream, ", deleting init_insn (%d)", | |
10030 | INSN_UID (init_insn)); | |
c29f60c0 BS |
10031 | } |
10032 | if (loop_dump_stream) | |
8571e492 | 10033 | fprintf (loop_dump_stream, ".\n"); |
c29f60c0 BS |
10034 | } |
10035 | } | |
10036 | ||
41a972a9 MM |
10037 | /* Replace MEM with its associated pseudo register. This function is |
10038 | called from load_mems via for_each_rtx. DATA is actually an | |
10039 | rtx_and_int * describing the instruction currently being scanned | |
10040 | and the MEM we are currently replacing. */ | |
10041 | ||
10042 | static int | |
10043 | replace_loop_mem (mem, data) | |
10044 | rtx *mem; | |
10045 | void *data; | |
10046 | { | |
10047 | rtx_and_int *ri; | |
10048 | rtx insn; | |
10049 | int i; | |
10050 | rtx m = *mem; | |
10051 | ||
10052 | if (m == NULL_RTX) | |
10053 | return 0; | |
10054 | ||
10055 | switch (GET_CODE (m)) | |
10056 | { | |
10057 | case MEM: | |
10058 | break; | |
10059 | ||
10060 | case CONST_DOUBLE: | |
10061 | /* We're not interested in the MEM associated with a | |
10062 | CONST_DOUBLE, so there's no need to traverse into one. */ | |
10063 | return -1; | |
10064 | ||
10065 | default: | |
10066 | /* This is not a MEM. */ | |
10067 | return 0; | |
10068 | } | |
10069 | ||
10070 | ri = (rtx_and_int*) data; | |
10071 | i = ri->i; | |
10072 | ||
10073 | if (!rtx_equal_p (loop_mems[i].mem, m)) | |
10074 | /* This is not the MEM we are currently replacing. */ | |
10075 | return 0; | |
10076 | ||
10077 | insn = ri->r; | |
10078 | ||
10079 | /* Actually replace the MEM. */ | |
10080 | validate_change (insn, mem, loop_mems[i].reg, 1); | |
10081 | ||
10082 | return 0; | |
10083 | } | |
10084 | ||
c29f60c0 BS |
10085 | /* Replace one register with another. Called through for_each_rtx; PX points |
10086 | to the rtx being scanned. DATA is actually an array of three rtx's; the | |
10087 | first one is the one to be replaced, and the second one the replacement. | |
10088 | The third one is the current insn. */ | |
10089 | ||
10090 | static int | |
10091 | replace_loop_reg (px, data) | |
10092 | rtx *px; | |
10093 | void *data; | |
10094 | { | |
10095 | rtx x = *px; | |
10096 | rtx *array = (rtx *)data; | |
10097 | ||
10098 | if (x == NULL_RTX) | |
10099 | return 0; | |
10100 | ||
10101 | if (x == array[0]) | |
10102 | validate_change (array[2], px, array[1], 1); | |
10103 | ||
10104 | return 0; | |
10105 | } | |
10106 | ||
41a972a9 MM |
10107 | /* Replace occurrences of the old exit label for the loop with the new |
10108 | one. DATA is an rtx_pair containing the old and new labels, | |
10109 | respectively. */ | |
10110 | ||
10111 | static int | |
10112 | replace_label (x, data) | |
10113 | rtx *x; | |
10114 | void *data; | |
10115 | { | |
10116 | rtx l = *x; | |
10117 | rtx old_label = ((rtx_pair*) data)->r1; | |
10118 | rtx new_label = ((rtx_pair*) data)->r2; | |
10119 | ||
10120 | if (l == NULL_RTX) | |
10121 | return 0; | |
10122 | ||
10123 | if (GET_CODE (l) != LABEL_REF) | |
10124 | return 0; | |
10125 | ||
10126 | if (XEXP (l, 0) != old_label) | |
10127 | return 0; | |
10128 | ||
10129 | XEXP (l, 0) = new_label; | |
10130 | ++LABEL_NUSES (new_label); | |
10131 | --LABEL_NUSES (old_label); | |
10132 | ||
10133 | return 0; | |
10134 | } |