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2bbd3819 | 1 | /* Allocate registers within a basic block, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
6fb5fa3c DB |
3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
4 | Free Software Foundation, Inc. | |
2bbd3819 | 5 | |
1322177d | 6 | This file is part of GCC. |
2bbd3819 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
2bbd3819 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
2bbd3819 RS |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
2bbd3819 | 21 | |
2bbd3819 RS |
22 | /* Allocation of hard register numbers to pseudo registers is done in |
23 | two passes. In this pass we consider only regs that are born and | |
24 | die once within one basic block. We do this one basic block at a | |
25 | time. Then the next pass allocates the registers that remain. | |
26 | Two passes are used because this pass uses methods that work only | |
27 | on linear code, but that do a better job than the general methods | |
28 | used in global_alloc, and more quickly too. | |
29 | ||
30 | The assignments made are recorded in the vector reg_renumber | |
31 | whose space is allocated here. The rtl code itself is not altered. | |
32 | ||
33 | We assign each instruction in the basic block a number | |
34 | which is its order from the beginning of the block. | |
35 | Then we can represent the lifetime of a pseudo register with | |
36 | a pair of numbers, and check for conflicts easily. | |
37 | We can record the availability of hard registers with a | |
38 | HARD_REG_SET for each instruction. The HARD_REG_SET | |
39 | contains 0 or 1 for each hard reg. | |
40 | ||
41 | To avoid register shuffling, we tie registers together when one | |
42 | dies by being copied into another, or dies in an instruction that | |
43 | does arithmetic to produce another. The tied registers are | |
44 | allocated as one. Registers with different reg class preferences | |
45 | can never be tied unless the class preferred by one is a subclass | |
46 | of the one preferred by the other. | |
47 | ||
48 | Tying is represented with "quantity numbers". | |
49 | A non-tied register is given a new quantity number. | |
50 | Tied registers have the same quantity number. | |
64e3a413 | 51 | |
2bbd3819 RS |
52 | We have provision to exempt registers, even when they are contained |
53 | within the block, that can be tied to others that are not contained in it. | |
54 | This is so that global_alloc could process them both and tie them then. | |
55 | But this is currently disabled since tying in global_alloc is not | |
56 | yet implemented. */ | |
57 | ||
a300b8d9 JW |
58 | /* Pseudos allocated here can be reallocated by global.c if the hard register |
59 | is used as a spill register. Currently we don't allocate such pseudos | |
6cad67d2 JL |
60 | here if their preferred class is likely to be used by spills. */ |
61 | ||
2bbd3819 | 62 | #include "config.h" |
670ee920 | 63 | #include "system.h" |
4977bab6 ZW |
64 | #include "coretypes.h" |
65 | #include "tm.h" | |
cff9f8d5 | 66 | #include "hard-reg-set.h" |
2bbd3819 | 67 | #include "rtl.h" |
6baf1cc8 | 68 | #include "tm_p.h" |
2bbd3819 | 69 | #include "flags.h" |
2bbd3819 | 70 | #include "regs.h" |
49ad7cfa | 71 | #include "function.h" |
2bbd3819 | 72 | #include "insn-config.h" |
624a8b3a | 73 | #include "insn-attr.h" |
2bbd3819 RS |
74 | #include "recog.h" |
75 | #include "output.h" | |
2e107e9e | 76 | #include "toplev.h" |
a4d3961a | 77 | #include "except.h" |
902197eb | 78 | #include "integrate.h" |
d7f88d86 BS |
79 | #include "reload.h" |
80 | #include "ggc.h" | |
ef330312 PB |
81 | #include "timevar.h" |
82 | #include "tree-pass.h" | |
6fb5fa3c DB |
83 | #include "df.h" |
84 | #include "dbgcnt.h" | |
85 | ||
2bbd3819 RS |
86 | \f |
87 | /* Next quantity number available for allocation. */ | |
88 | ||
89 | static int next_qty; | |
90 | ||
f5143c46 | 91 | /* Information we maintain about each quantity. */ |
a1ed7bdb JH |
92 | struct qty |
93 | { | |
94 | /* The number of refs to quantity Q. */ | |
2bbd3819 | 95 | |
a1ed7bdb | 96 | int n_refs; |
2bbd3819 | 97 | |
b2aec5c0 JH |
98 | /* The frequency of uses of quantity Q. */ |
99 | ||
100 | int freq; | |
101 | ||
a1ed7bdb JH |
102 | /* Insn number (counting from head of basic block) |
103 | where quantity Q was born. -1 if birth has not been recorded. */ | |
2bbd3819 | 104 | |
a1ed7bdb | 105 | int birth; |
2bbd3819 | 106 | |
a1ed7bdb JH |
107 | /* Insn number (counting from head of basic block) |
108 | where given quantity died. Due to the way tying is done, | |
109 | and the fact that we consider in this pass only regs that die but once, | |
110 | a quantity can die only once. Each quantity's life span | |
111 | is a set of consecutive insns. -1 if death has not been recorded. */ | |
2bbd3819 | 112 | |
a1ed7bdb | 113 | int death; |
2bbd3819 | 114 | |
a1ed7bdb JH |
115 | /* Number of words needed to hold the data in given quantity. |
116 | This depends on its machine mode. It is used for these purposes: | |
ba228239 | 117 | 1. It is used in computing the relative importance of qtys, |
a1ed7bdb JH |
118 | which determines the order in which we look for regs for them. |
119 | 2. It is used in rules that prevent tying several registers of | |
120 | different sizes in a way that is geometrically impossible | |
121 | (see combine_regs). */ | |
2bbd3819 | 122 | |
a1ed7bdb | 123 | int size; |
2bbd3819 | 124 | |
a1ed7bdb | 125 | /* Number of times a reg tied to given qty lives across a CALL_INSN. */ |
2bbd3819 | 126 | |
a1ed7bdb | 127 | int n_calls_crossed; |
2bbd3819 | 128 | |
a03c6d64 JH |
129 | /* Number of times a reg tied to given qty lives across a CALL_INSN. */ |
130 | ||
131 | int freq_calls_crossed; | |
132 | ||
95c37cdb JJ |
133 | /* Number of times a reg tied to given qty lives across a CALL_INSN |
134 | that might throw. */ | |
135 | ||
136 | int n_throwing_calls_crossed; | |
137 | ||
a1ed7bdb JH |
138 | /* The register number of one pseudo register whose reg_qty value is Q. |
139 | This register should be the head of the chain | |
140 | maintained in reg_next_in_qty. */ | |
2bbd3819 | 141 | |
a1ed7bdb | 142 | int first_reg; |
2bbd3819 | 143 | |
a1ed7bdb JH |
144 | /* Reg class contained in (smaller than) the preferred classes of all |
145 | the pseudo regs that are tied in given quantity. | |
146 | This is the preferred class for allocating that quantity. */ | |
147 | ||
148 | enum reg_class min_class; | |
2bbd3819 | 149 | |
a1ed7bdb JH |
150 | /* Register class within which we allocate given qty if we can't get |
151 | its preferred class. */ | |
2bbd3819 | 152 | |
a1ed7bdb | 153 | enum reg_class alternate_class; |
2bbd3819 | 154 | |
a1ed7bdb JH |
155 | /* This holds the mode of the registers that are tied to given qty, |
156 | or VOIDmode if registers with differing modes are tied together. */ | |
2bbd3819 | 157 | |
a1ed7bdb | 158 | enum machine_mode mode; |
2bbd3819 | 159 | |
a1ed7bdb JH |
160 | /* the hard reg number chosen for given quantity, |
161 | or -1 if none was found. */ | |
2bbd3819 | 162 | |
a1ed7bdb | 163 | short phys_reg; |
a1ed7bdb | 164 | }; |
2bbd3819 | 165 | |
a1ed7bdb | 166 | static struct qty *qty; |
2bbd3819 | 167 | |
a1ed7bdb | 168 | /* These fields are kept separately to speedup their clearing. */ |
2bbd3819 | 169 | |
a1ed7bdb JH |
170 | /* We maintain two hard register sets that indicate suggested hard registers |
171 | for each quantity. The first, phys_copy_sugg, contains hard registers | |
172 | that are tied to the quantity by a simple copy. The second contains all | |
173 | hard registers that are tied to the quantity via an arithmetic operation. | |
2bbd3819 | 174 | |
a1ed7bdb JH |
175 | The former register set is given priority for allocation. This tends to |
176 | eliminate copy insns. */ | |
2bbd3819 | 177 | |
a1ed7bdb JH |
178 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
179 | copy insns. */ | |
2bbd3819 | 180 | |
a1ed7bdb | 181 | static HARD_REG_SET *qty_phys_copy_sugg; |
2bbd3819 | 182 | |
a1ed7bdb JH |
183 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
184 | arithmetic insns. */ | |
185 | ||
186 | static HARD_REG_SET *qty_phys_sugg; | |
187 | ||
188 | /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ | |
2bbd3819 | 189 | |
a1ed7bdb | 190 | static short *qty_phys_num_copy_sugg; |
0f64b8f6 | 191 | |
a1ed7bdb | 192 | /* Element Q is the number of suggested registers in qty_phys_sugg. */ |
0f64b8f6 | 193 | |
a1ed7bdb | 194 | static short *qty_phys_num_sugg; |
2bbd3819 | 195 | |
2bbd3819 RS |
196 | /* If (REG N) has been assigned a quantity number, is a register number |
197 | of another register assigned the same quantity number, or -1 for the | |
a1ed7bdb | 198 | end of the chain. qty->first_reg point to the head of this chain. */ |
2bbd3819 | 199 | |
aabf56ce | 200 | static int *reg_next_in_qty; |
2bbd3819 RS |
201 | |
202 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg | |
203 | if it is >= 0, | |
204 | of -1 if this register cannot be allocated by local-alloc, | |
205 | or -2 if not known yet. | |
206 | ||
207 | Note that if we see a use or death of pseudo register N with | |
208 | reg_qty[N] == -2, register N must be local to the current block. If | |
209 | it were used in more than one block, we would have reg_qty[N] == -1. | |
210 | This relies on the fact that if reg_basic_block[N] is >= 0, register N | |
211 | will not appear in any other block. We save a considerable number of | |
212 | tests by exploiting this. | |
213 | ||
214 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not | |
215 | be referenced. */ | |
216 | ||
217 | static int *reg_qty; | |
218 | ||
219 | /* The offset (in words) of register N within its quantity. | |
220 | This can be nonzero if register N is SImode, and has been tied | |
221 | to a subreg of a DImode register. */ | |
222 | ||
223 | static char *reg_offset; | |
224 | ||
225 | /* Vector of substitutions of register numbers, | |
226 | used to map pseudo regs into hardware regs. | |
227 | This is set up as a result of register allocation. | |
228 | Element N is the hard reg assigned to pseudo reg N, | |
229 | or is -1 if no hard reg was assigned. | |
230 | If N is a hard reg number, element N is N. */ | |
231 | ||
232 | short *reg_renumber; | |
233 | ||
234 | /* Set of hard registers live at the current point in the scan | |
235 | of the instructions in a basic block. */ | |
236 | ||
237 | static HARD_REG_SET regs_live; | |
238 | ||
239 | /* Each set of hard registers indicates registers live at a particular | |
240 | point in the basic block. For N even, regs_live_at[N] says which | |
241 | hard registers are needed *after* insn N/2 (i.e., they may not | |
242 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. | |
243 | ||
244 | If an object is to conflict with the inputs of insn J but not the | |
245 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, | |
246 | if it is to conflict with the outputs of insn J but not the inputs of | |
247 | insn J + 1, it is said to die at index J*2 + 1. */ | |
248 | ||
249 | static HARD_REG_SET *regs_live_at; | |
250 | ||
251 | /* Communicate local vars `insn_number' and `insn' | |
252 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ | |
253 | static int this_insn_number; | |
254 | static rtx this_insn; | |
255 | ||
bf6d9fd7 JW |
256 | struct equivalence |
257 | { | |
258 | /* Set when an attempt should be made to replace a register | |
5ca9299f | 259 | with the associated src_p entry. */ |
bf6d9fd7 JW |
260 | |
261 | char replace; | |
262 | ||
263 | /* Set when a REG_EQUIV note is found or created. Use to | |
264 | keep track of what memory accesses might be created later, | |
265 | e.g. by reload. */ | |
266 | ||
267 | rtx replacement; | |
68342d36 | 268 | |
5ca9299f | 269 | rtx *src_p; |
c25a4c25 | 270 | |
bf6d9fd7 JW |
271 | /* Loop depth is used to recognize equivalences which appear |
272 | to be present within the same loop (or in an inner loop). */ | |
273 | ||
274 | int loop_depth; | |
275 | ||
276 | /* The list of each instruction which initializes this register. */ | |
277 | ||
278 | rtx init_insns; | |
d7f88d86 BS |
279 | |
280 | /* Nonzero if this had a preexisting REG_EQUIV note. */ | |
281 | ||
282 | int is_arg_equivalence; | |
bf6d9fd7 JW |
283 | }; |
284 | ||
285 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
286 | structure for that register. */ | |
287 | ||
288 | static struct equivalence *reg_equiv; | |
135eb61c | 289 | |
3f1b9b1b JL |
290 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
291 | static int recorded_label_ref; | |
292 | ||
0c20a65f | 293 | static void alloc_qty (int, enum machine_mode, int, int); |
7bc980e1 | 294 | static void validate_equiv_mem_from_store (rtx, const_rtx, void *); |
0c20a65f AJ |
295 | static int validate_equiv_mem (rtx, rtx, rtx); |
296 | static int equiv_init_varies_p (rtx); | |
297 | static int equiv_init_movable_p (rtx, int); | |
298 | static int contains_replace_regs (rtx); | |
299 | static int memref_referenced_p (rtx, rtx); | |
300 | static int memref_used_between_p (rtx, rtx, rtx); | |
301 | static void update_equiv_regs (void); | |
7bc980e1 | 302 | static void no_equiv (rtx, const_rtx, void *); |
0c20a65f AJ |
303 | static void block_alloc (int); |
304 | static int qty_sugg_compare (int, int); | |
305 | static int qty_sugg_compare_1 (const void *, const void *); | |
306 | static int qty_compare (int, int); | |
307 | static int qty_compare_1 (const void *, const void *); | |
d70dcf29 | 308 | static int combine_regs (rtx, rtx, int, int, rtx); |
0c20a65f AJ |
309 | static int reg_meets_class_p (int, enum reg_class); |
310 | static void update_qty_class (int, int); | |
7bc980e1 | 311 | static void reg_is_set (rtx, const_rtx, void *); |
0c20a65f AJ |
312 | static void reg_is_born (rtx, int); |
313 | static void wipe_dead_reg (rtx, int); | |
314 | static int find_free_reg (enum reg_class, enum machine_mode, int, int, int, | |
315 | int, int); | |
316 | static void mark_life (int, enum machine_mode, int); | |
317 | static void post_mark_life (int, enum machine_mode, int, int, int); | |
0c20a65f | 318 | static int requires_inout (const char *); |
2bbd3819 RS |
319 | \f |
320 | /* Allocate a new quantity (new within current basic block) | |
321 | for register number REGNO which is born at index BIRTH | |
322 | within the block. MODE and SIZE are info on reg REGNO. */ | |
323 | ||
324 | static void | |
0c20a65f | 325 | alloc_qty (int regno, enum machine_mode mode, int size, int birth) |
2bbd3819 | 326 | { |
b3694847 | 327 | int qtyno = next_qty++; |
2bbd3819 | 328 | |
a1ed7bdb | 329 | reg_qty[regno] = qtyno; |
2bbd3819 RS |
330 | reg_offset[regno] = 0; |
331 | reg_next_in_qty[regno] = -1; | |
332 | ||
a1ed7bdb JH |
333 | qty[qtyno].first_reg = regno; |
334 | qty[qtyno].size = size; | |
335 | qty[qtyno].mode = mode; | |
336 | qty[qtyno].birth = birth; | |
337 | qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno); | |
a03c6d64 | 338 | qty[qtyno].freq_calls_crossed = REG_FREQ_CALLS_CROSSED (regno); |
95c37cdb | 339 | qty[qtyno].n_throwing_calls_crossed = REG_N_THROWING_CALLS_CROSSED (regno); |
a1ed7bdb JH |
340 | qty[qtyno].min_class = reg_preferred_class (regno); |
341 | qty[qtyno].alternate_class = reg_alternate_class (regno); | |
342 | qty[qtyno].n_refs = REG_N_REFS (regno); | |
b2aec5c0 | 343 | qty[qtyno].freq = REG_FREQ (regno); |
2bbd3819 RS |
344 | } |
345 | \f | |
2bbd3819 RS |
346 | /* Main entry point of this file. */ |
347 | ||
57c8b089 | 348 | static int |
0c20a65f | 349 | local_alloc (void) |
2bbd3819 | 350 | { |
e0082a72 | 351 | int i; |
2bbd3819 | 352 | int max_qty; |
e0082a72 | 353 | basic_block b; |
2bbd3819 | 354 | |
3f1b9b1b JL |
355 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
356 | that we know if the jump optimizer needs to be rerun. */ | |
357 | recorded_label_ref = 0; | |
358 | ||
2bbd3819 RS |
359 | /* Leaf functions and non-leaf functions have different needs. |
360 | If defined, let the machine say what kind of ordering we | |
361 | should use. */ | |
362 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC | |
363 | ORDER_REGS_FOR_LOCAL_ALLOC; | |
364 | #endif | |
365 | ||
366 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected | |
367 | registers. */ | |
d7f88d86 | 368 | update_equiv_regs (); |
2bbd3819 RS |
369 | |
370 | /* This sets the maximum number of quantities we can have. Quantity | |
34f89b5f BS |
371 | numbers start at zero and we can have one for each pseudo. */ |
372 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER); | |
2bbd3819 RS |
373 | |
374 | /* Allocate vectors of temporary data. | |
375 | See the declarations of these variables, above, | |
376 | for what they mean. */ | |
377 | ||
5ed6ace5 MD |
378 | qty = XNEWVEC (struct qty, max_qty); |
379 | qty_phys_copy_sugg = XNEWVEC (HARD_REG_SET, max_qty); | |
380 | qty_phys_num_copy_sugg = XNEWVEC (short, max_qty); | |
381 | qty_phys_sugg = XNEWVEC (HARD_REG_SET, max_qty); | |
382 | qty_phys_num_sugg = XNEWVEC (short, max_qty); | |
2bbd3819 | 383 | |
5ed6ace5 MD |
384 | reg_qty = XNEWVEC (int, max_regno); |
385 | reg_offset = XNEWVEC (char, max_regno); | |
386 | reg_next_in_qty = XNEWVEC (int, max_regno); | |
2bbd3819 | 387 | |
2bbd3819 RS |
388 | /* Determine which pseudo-registers can be allocated by local-alloc. |
389 | In general, these are the registers used only in a single block and | |
611bbf2a | 390 | which only die once. |
2bbd3819 RS |
391 | |
392 | We need not be concerned with which block actually uses the register | |
393 | since we will never see it outside that block. */ | |
394 | ||
395 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
396 | { | |
6fb5fa3c | 397 | if (REG_BASIC_BLOCK (i) >= NUM_FIXED_BLOCKS && REG_N_DEATHS (i) == 1) |
2bbd3819 RS |
398 | reg_qty[i] = -2; |
399 | else | |
400 | reg_qty[i] = -1; | |
401 | } | |
402 | ||
403 | /* Force loop below to initialize entire quantity array. */ | |
404 | next_qty = max_qty; | |
405 | ||
406 | /* Allocate each block's local registers, block by block. */ | |
407 | ||
e0082a72 | 408 | FOR_EACH_BB (b) |
2bbd3819 RS |
409 | { |
410 | /* NEXT_QTY indicates which elements of the `qty_...' | |
411 | vectors might need to be initialized because they were used | |
412 | for the previous block; it is set to the entire array before | |
413 | block 0. Initialize those, with explicit loop if there are few, | |
414 | else with bzero and bcopy. Do not initialize vectors that are | |
415 | explicit set by `alloc_qty'. */ | |
416 | ||
417 | if (next_qty < 6) | |
418 | { | |
419 | for (i = 0; i < next_qty; i++) | |
420 | { | |
2bbd3819 | 421 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); |
51b86d8b | 422 | qty_phys_num_copy_sugg[i] = 0; |
2bbd3819 | 423 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); |
51b86d8b | 424 | qty_phys_num_sugg[i] = 0; |
2bbd3819 RS |
425 | } |
426 | } | |
427 | else | |
428 | { | |
429 | #define CLEAR(vector) \ | |
703ad42b | 430 | memset ((vector), 0, (sizeof (*(vector))) * next_qty); |
2bbd3819 | 431 | |
2bbd3819 | 432 | CLEAR (qty_phys_copy_sugg); |
51b86d8b | 433 | CLEAR (qty_phys_num_copy_sugg); |
2bbd3819 | 434 | CLEAR (qty_phys_sugg); |
51b86d8b | 435 | CLEAR (qty_phys_num_sugg); |
2bbd3819 RS |
436 | } |
437 | ||
438 | next_qty = 0; | |
439 | ||
e0082a72 | 440 | block_alloc (b->index); |
2bbd3819 | 441 | } |
83cbe7e4 | 442 | |
a1ed7bdb | 443 | free (qty); |
75c6bd46 RH |
444 | free (qty_phys_copy_sugg); |
445 | free (qty_phys_num_copy_sugg); | |
446 | free (qty_phys_sugg); | |
e7749837 | 447 | free (qty_phys_num_sugg); |
75c6bd46 | 448 | |
83cbe7e4 RH |
449 | free (reg_qty); |
450 | free (reg_offset); | |
451 | free (reg_next_in_qty); | |
75c6bd46 | 452 | |
3f1b9b1b | 453 | return recorded_label_ref; |
2bbd3819 RS |
454 | } |
455 | \f | |
2bbd3819 RS |
456 | /* Used for communication between the following two functions: contains |
457 | a MEM that we wish to ensure remains unchanged. */ | |
458 | static rtx equiv_mem; | |
459 | ||
460 | /* Set nonzero if EQUIV_MEM is modified. */ | |
461 | static int equiv_mem_modified; | |
462 | ||
463 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
464 | Called via note_stores. */ | |
465 | ||
466 | static void | |
7bc980e1 | 467 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, |
0c20a65f | 468 | void *data ATTRIBUTE_UNUSED) |
2bbd3819 | 469 | { |
f8cfc6aa | 470 | if ((REG_P (dest) |
2bbd3819 | 471 | && reg_overlap_mentioned_p (dest, equiv_mem)) |
3c0cb5de | 472 | || (MEM_P (dest) |
9ae8ffe7 | 473 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) |
2bbd3819 RS |
474 | equiv_mem_modified = 1; |
475 | } | |
476 | ||
477 | /* Verify that no store between START and the death of REG invalidates | |
478 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
479 | by storing into an overlapping memory location, or with a non-const | |
480 | CALL_INSN. | |
481 | ||
482 | Return 1 if MEMREF remains valid. */ | |
483 | ||
484 | static int | |
0c20a65f | 485 | validate_equiv_mem (rtx start, rtx reg, rtx memref) |
2bbd3819 RS |
486 | { |
487 | rtx insn; | |
488 | rtx note; | |
489 | ||
490 | equiv_mem = memref; | |
491 | equiv_mem_modified = 0; | |
492 | ||
493 | /* If the memory reference has side effects or is volatile, it isn't a | |
494 | valid equivalence. */ | |
495 | if (side_effects_p (memref)) | |
496 | return 0; | |
497 | ||
498 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
499 | { | |
2c3c49de | 500 | if (! INSN_P (insn)) |
2bbd3819 RS |
501 | continue; |
502 | ||
503 | if (find_reg_note (insn, REG_DEAD, reg)) | |
504 | return 1; | |
505 | ||
389fdba0 | 506 | if (CALL_P (insn) && ! MEM_READONLY_P (memref) |
becfd6e5 | 507 | && ! RTL_CONST_OR_PURE_CALL_P (insn)) |
2bbd3819 RS |
508 | return 0; |
509 | ||
84832317 | 510 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); |
2bbd3819 RS |
511 | |
512 | /* If a register mentioned in MEMREF is modified via an | |
513 | auto-increment, we lose the equivalence. Do the same if one | |
514 | dies; although we could extend the life, it doesn't seem worth | |
515 | the trouble. */ | |
516 | ||
517 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
518 | if ((REG_NOTE_KIND (note) == REG_INC | |
519 | || REG_NOTE_KIND (note) == REG_DEAD) | |
f8cfc6aa | 520 | && REG_P (XEXP (note, 0)) |
2bbd3819 RS |
521 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) |
522 | return 0; | |
523 | } | |
524 | ||
525 | return 0; | |
526 | } | |
a1729519 | 527 | |
bf6d9fd7 JW |
528 | /* Returns zero if X is known to be invariant. */ |
529 | ||
530 | static int | |
0c20a65f | 531 | equiv_init_varies_p (rtx x) |
bf6d9fd7 | 532 | { |
b3694847 SS |
533 | RTX_CODE code = GET_CODE (x); |
534 | int i; | |
535 | const char *fmt; | |
bf6d9fd7 JW |
536 | |
537 | switch (code) | |
538 | { | |
539 | case MEM: | |
389fdba0 | 540 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); |
bf6d9fd7 | 541 | |
bf6d9fd7 JW |
542 | case CONST: |
543 | case CONST_INT: | |
544 | case CONST_DOUBLE: | |
091a3ac7 | 545 | case CONST_FIXED: |
69ef87e2 | 546 | case CONST_VECTOR: |
bf6d9fd7 JW |
547 | case SYMBOL_REF: |
548 | case LABEL_REF: | |
549 | return 0; | |
550 | ||
551 | case REG: | |
e38fe8e0 | 552 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); |
bf6d9fd7 JW |
553 | |
554 | case ASM_OPERANDS: | |
555 | if (MEM_VOLATILE_P (x)) | |
556 | return 1; | |
557 | ||
5d3cc252 | 558 | /* Fall through. */ |
bf6d9fd7 JW |
559 | |
560 | default: | |
561 | break; | |
562 | } | |
563 | ||
564 | fmt = GET_RTX_FORMAT (code); | |
565 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
566 | if (fmt[i] == 'e') | |
567 | { | |
568 | if (equiv_init_varies_p (XEXP (x, i))) | |
569 | return 1; | |
570 | } | |
571 | else if (fmt[i] == 'E') | |
572 | { | |
573 | int j; | |
574 | for (j = 0; j < XVECLEN (x, i); j++) | |
575 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
576 | return 1; | |
577 | } | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
cc2902df | 582 | /* Returns nonzero if X (used to initialize register REGNO) is movable. |
bf6d9fd7 JW |
583 | X is only movable if the registers it uses have equivalent initializations |
584 | which appear to be within the same loop (or in an inner loop) and movable | |
585 | or if they are not candidates for local_alloc and don't vary. */ | |
a1729519 JW |
586 | |
587 | static int | |
0c20a65f | 588 | equiv_init_movable_p (rtx x, int regno) |
bf6d9fd7 JW |
589 | { |
590 | int i, j; | |
591 | const char *fmt; | |
592 | enum rtx_code code = GET_CODE (x); | |
593 | ||
594 | switch (code) | |
595 | { | |
596 | case SET: | |
597 | return equiv_init_movable_p (SET_SRC (x), regno); | |
598 | ||
d9068c61 | 599 | case CC0: |
bf6d9fd7 JW |
600 | case CLOBBER: |
601 | return 0; | |
602 | ||
603 | case PRE_INC: | |
604 | case PRE_DEC: | |
605 | case POST_INC: | |
606 | case POST_DEC: | |
607 | case PRE_MODIFY: | |
608 | case POST_MODIFY: | |
609 | return 0; | |
610 | ||
611 | case REG: | |
612 | return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth | |
613 | && reg_equiv[REGNO (x)].replace) | |
6fb5fa3c | 614 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS && ! rtx_varies_p (x, 0)); |
bf6d9fd7 JW |
615 | |
616 | case UNSPEC_VOLATILE: | |
617 | return 0; | |
618 | ||
619 | case ASM_OPERANDS: | |
620 | if (MEM_VOLATILE_P (x)) | |
621 | return 0; | |
622 | ||
5d3cc252 | 623 | /* Fall through. */ |
bf6d9fd7 JW |
624 | |
625 | default: | |
626 | break; | |
627 | } | |
628 | ||
629 | fmt = GET_RTX_FORMAT (code); | |
630 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
631 | switch (fmt[i]) | |
632 | { | |
633 | case 'e': | |
634 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
635 | return 0; | |
636 | break; | |
637 | case 'E': | |
638 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
639 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
640 | return 0; | |
641 | break; | |
642 | } | |
643 | ||
644 | return 1; | |
645 | } | |
646 | ||
647 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */ | |
648 | ||
649 | static int | |
0c20a65f | 650 | contains_replace_regs (rtx x) |
a1729519 JW |
651 | { |
652 | int i, j; | |
6f7d635c | 653 | const char *fmt; |
a1729519 JW |
654 | enum rtx_code code = GET_CODE (x); |
655 | ||
656 | switch (code) | |
657 | { | |
658 | case CONST_INT: | |
659 | case CONST: | |
660 | case LABEL_REF: | |
661 | case SYMBOL_REF: | |
662 | case CONST_DOUBLE: | |
091a3ac7 | 663 | case CONST_FIXED: |
69ef87e2 | 664 | case CONST_VECTOR: |
a1729519 JW |
665 | case PC: |
666 | case CC0: | |
667 | case HIGH: | |
a1729519 JW |
668 | return 0; |
669 | ||
670 | case REG: | |
bf6d9fd7 | 671 | return reg_equiv[REGNO (x)].replace; |
1d300e19 KG |
672 | |
673 | default: | |
674 | break; | |
a1729519 JW |
675 | } |
676 | ||
677 | fmt = GET_RTX_FORMAT (code); | |
678 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
679 | switch (fmt[i]) | |
680 | { | |
681 | case 'e': | |
bf6d9fd7 | 682 | if (contains_replace_regs (XEXP (x, i))) |
a1729519 JW |
683 | return 1; |
684 | break; | |
685 | case 'E': | |
686 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
bf6d9fd7 | 687 | if (contains_replace_regs (XVECEXP (x, i, j))) |
a1729519 JW |
688 | return 1; |
689 | break; | |
690 | } | |
691 | ||
692 | return 0; | |
693 | } | |
2bbd3819 RS |
694 | \f |
695 | /* TRUE if X references a memory location that would be affected by a store | |
696 | to MEMREF. */ | |
697 | ||
698 | static int | |
0c20a65f | 699 | memref_referenced_p (rtx memref, rtx x) |
2bbd3819 RS |
700 | { |
701 | int i, j; | |
6f7d635c | 702 | const char *fmt; |
2bbd3819 RS |
703 | enum rtx_code code = GET_CODE (x); |
704 | ||
705 | switch (code) | |
706 | { | |
2bbd3819 RS |
707 | case CONST_INT: |
708 | case CONST: | |
709 | case LABEL_REF: | |
710 | case SYMBOL_REF: | |
711 | case CONST_DOUBLE: | |
091a3ac7 | 712 | case CONST_FIXED: |
69ef87e2 | 713 | case CONST_VECTOR: |
2bbd3819 RS |
714 | case PC: |
715 | case CC0: | |
716 | case HIGH: | |
717 | case LO_SUM: | |
718 | return 0; | |
719 | ||
c25a4c25 | 720 | case REG: |
bf6d9fd7 | 721 | return (reg_equiv[REGNO (x)].replacement |
3298a1b1 | 722 | && memref_referenced_p (memref, |
bf6d9fd7 | 723 | reg_equiv[REGNO (x)].replacement)); |
c25a4c25 | 724 | |
2bbd3819 | 725 | case MEM: |
9ae8ffe7 | 726 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) |
2bbd3819 RS |
727 | return 1; |
728 | break; | |
729 | ||
730 | case SET: | |
731 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
732 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
3c0cb5de | 733 | if (MEM_P (SET_DEST (x))) |
2bbd3819 RS |
734 | { |
735 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
736 | return 1; | |
737 | } | |
738 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
739 | return 1; | |
740 | ||
741 | return memref_referenced_p (memref, SET_SRC (x)); | |
64e3a413 | 742 | |
e9a25f70 JL |
743 | default: |
744 | break; | |
2bbd3819 RS |
745 | } |
746 | ||
747 | fmt = GET_RTX_FORMAT (code); | |
748 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
749 | switch (fmt[i]) | |
750 | { | |
751 | case 'e': | |
752 | if (memref_referenced_p (memref, XEXP (x, i))) | |
753 | return 1; | |
754 | break; | |
755 | case 'E': | |
756 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
757 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
758 | return 1; | |
759 | break; | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | /* TRUE if some insn in the range (START, END] references a memory location | |
766 | that would be affected by a store to MEMREF. */ | |
767 | ||
768 | static int | |
0c20a65f | 769 | memref_used_between_p (rtx memref, rtx start, rtx end) |
2bbd3819 RS |
770 | { |
771 | rtx insn; | |
772 | ||
773 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
774 | insn = NEXT_INSN (insn)) | |
301a8f95 ZD |
775 | { |
776 | if (!INSN_P (insn)) | |
777 | continue; | |
778 | ||
779 | if (memref_referenced_p (memref, PATTERN (insn))) | |
780 | return 1; | |
781 | ||
782 | /* Nonconst functions may access memory. */ | |
becfd6e5 | 783 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) |
301a8f95 ZD |
784 | return 1; |
785 | } | |
2bbd3819 RS |
786 | |
787 | return 0; | |
788 | } | |
789 | \f | |
2bbd3819 RS |
790 | /* Find registers that are equivalent to a single value throughout the |
791 | compilation (either because they can be referenced in memory or are set once | |
792 | from a single constant). Lower their priority for a register. | |
793 | ||
794 | If such a register is only referenced once, try substituting its value | |
795 | into the using insn. If it succeeds, we can eliminate the register | |
d7f88d86 BS |
796 | completely. |
797 | ||
798 | Initialize the REG_EQUIV_INIT array of initializing insns. */ | |
2bbd3819 RS |
799 | |
800 | static void | |
0c20a65f | 801 | update_equiv_regs (void) |
2bbd3819 | 802 | { |
2bbd3819 | 803 | rtx insn; |
e0082a72 | 804 | basic_block bb; |
bf6d9fd7 | 805 | int loop_depth; |
6fb5fa3c DB |
806 | bitmap cleared_regs; |
807 | ||
5ed6ace5 | 808 | reg_equiv = XCNEWVEC (struct equivalence, max_regno); |
d3bfe4de | 809 | reg_equiv_init = GGC_CNEWVEC (rtx, max_regno); |
d7f88d86 | 810 | reg_equiv_init_size = max_regno; |
2bbd3819 RS |
811 | |
812 | init_alias_analysis (); | |
813 | ||
2bbd3819 RS |
814 | /* Scan the insns and find which registers have equivalences. Do this |
815 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
816 | a register can be set below its use. */ | |
e0082a72 | 817 | FOR_EACH_BB (bb) |
2bbd3819 | 818 | { |
2ab0437e | 819 | loop_depth = bb->loop_depth; |
2bbd3819 | 820 | |
a813c111 SB |
821 | for (insn = BB_HEAD (bb); |
822 | insn != NEXT_INSN (BB_END (bb)); | |
823 | insn = NEXT_INSN (insn)) | |
2bbd3819 | 824 | { |
2ab0437e JH |
825 | rtx note; |
826 | rtx set; | |
827 | rtx dest, src; | |
828 | int regno; | |
2bbd3819 | 829 | |
2ab0437e JH |
830 | if (! INSN_P (insn)) |
831 | continue; | |
135eb61c | 832 | |
2ab0437e JH |
833 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
834 | if (REG_NOTE_KIND (note) == REG_INC) | |
835 | no_equiv (XEXP (note, 0), note, NULL); | |
135eb61c | 836 | |
2ab0437e | 837 | set = single_set (insn); |
135eb61c | 838 | |
2ab0437e JH |
839 | /* If this insn contains more (or less) than a single SET, |
840 | only mark all destinations as having no known equivalence. */ | |
841 | if (set == 0) | |
135eb61c | 842 | { |
2ab0437e JH |
843 | note_stores (PATTERN (insn), no_equiv, NULL); |
844 | continue; | |
135eb61c | 845 | } |
2ab0437e JH |
846 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
847 | { | |
848 | int i; | |
135eb61c | 849 | |
2ab0437e JH |
850 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
851 | { | |
852 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
853 | if (part != set) | |
854 | note_stores (part, no_equiv, NULL); | |
855 | } | |
856 | } | |
2bbd3819 | 857 | |
2ab0437e JH |
858 | dest = SET_DEST (set); |
859 | src = SET_SRC (set); | |
860 | ||
d7f88d86 BS |
861 | /* See if this is setting up the equivalence between an argument |
862 | register and its stack slot. */ | |
863 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
864 | if (note) | |
2ab0437e | 865 | { |
d7f88d86 BS |
866 | gcc_assert (REG_P (dest)); |
867 | regno = REGNO (dest); | |
868 | ||
869 | /* Note that we don't want to clear reg_equiv_init even if there | |
870 | are multiple sets of this register. */ | |
871 | reg_equiv[regno].is_arg_equivalence = 1; | |
872 | ||
873 | /* Record for reload that this is an equivalencing insn. */ | |
874 | if (rtx_equal_p (src, XEXP (note, 0))) | |
875 | reg_equiv_init[regno] | |
876 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); | |
877 | ||
878 | /* Continue normally in case this is a candidate for | |
879 | replacements. */ | |
2ab0437e | 880 | } |
2bbd3819 | 881 | |
d7f88d86 BS |
882 | if (!optimize) |
883 | continue; | |
884 | ||
2ab0437e JH |
885 | /* We only handle the case of a pseudo register being set |
886 | once, or always to the same value. */ | |
887 | /* ??? The mn10200 port breaks if we add equivalences for | |
888 | values that need an ADDRESS_REGS register and set them equivalent | |
889 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
890 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
891 | calculate_needs, but we traditionally work around this problem | |
892 | here by rejecting equivalences when the destination is in a register | |
893 | that's likely spilled. This is fragile, of course, since the | |
894 | preferred class of a pseudo depends on all instructions that set | |
895 | or use it. */ | |
896 | ||
f8cfc6aa | 897 | if (!REG_P (dest) |
2ab0437e JH |
898 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER |
899 | || reg_equiv[regno].init_insns == const0_rtx | |
900 | || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) | |
d7f88d86 | 901 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2ab0437e | 902 | { |
4d6922ee | 903 | /* This might be setting a SUBREG of a pseudo, a pseudo that is |
2ab0437e JH |
904 | also set somewhere else to a constant. */ |
905 | note_stores (set, no_equiv, NULL); | |
906 | continue; | |
907 | } | |
908 | ||
909 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
910 | ||
911 | /* cse sometimes generates function invariants, but doesn't put a | |
912 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3d238248 JJ |
913 | there's no point creating it earlier than here. */ |
914 | if (! note && ! rtx_varies_p (src, 0)) | |
3e916873 | 915 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); |
2ab0437e JH |
916 | |
917 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
918 | since it represents a function call */ | |
919 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
920 | note = NULL_RTX; | |
921 | ||
6fb5fa3c | 922 | if (DF_REG_DEF_COUNT (regno) != 1 |
2ab0437e JH |
923 | && (! note |
924 | || rtx_varies_p (XEXP (note, 0), 0) | |
925 | || (reg_equiv[regno].replacement | |
926 | && ! rtx_equal_p (XEXP (note, 0), | |
927 | reg_equiv[regno].replacement)))) | |
928 | { | |
929 | no_equiv (dest, set, NULL); | |
930 | continue; | |
931 | } | |
932 | /* Record this insn as initializing this register. */ | |
933 | reg_equiv[regno].init_insns | |
934 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
935 | ||
936 | /* If this register is known to be equal to a constant, record that | |
937 | it is always equivalent to the constant. */ | |
6fb5fa3c | 938 | if (DF_REG_DEF_COUNT (regno) == 1 |
a31830a7 SB |
939 | && note && ! rtx_varies_p (XEXP (note, 0), 0)) |
940 | { | |
941 | rtx note_value = XEXP (note, 0); | |
942 | remove_note (insn, note); | |
943 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
944 | } | |
2ab0437e JH |
945 | |
946 | /* If this insn introduces a "constant" register, decrease the priority | |
947 | of that register. Record this insn if the register is only used once | |
948 | more and the equivalence value is the same as our source. | |
949 | ||
950 | The latter condition is checked for two reasons: First, it is an | |
951 | indication that it may be more efficient to actually emit the insn | |
952 | as written (if no registers are available, reload will substitute | |
953 | the equivalence). Secondly, it avoids problems with any registers | |
954 | dying in this insn whose death notes would be missed. | |
955 | ||
956 | If we don't have a REG_EQUIV note, see if this insn is loading | |
957 | a register used only in one basic block from a MEM. If so, and the | |
958 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
959 | note. */ | |
960 | ||
961 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
962 | ||
6fb5fa3c | 963 | if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS |
3c0cb5de | 964 | && MEM_P (SET_SRC (set)) |
2ab0437e | 965 | && validate_equiv_mem (insn, dest, SET_SRC (set))) |
a31830a7 | 966 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); |
2ab0437e JH |
967 | |
968 | if (note) | |
68342d36 | 969 | { |
2ab0437e | 970 | int regno = REGNO (dest); |
d7f88d86 BS |
971 | rtx x = XEXP (note, 0); |
972 | ||
973 | /* If we haven't done so, record for reload that this is an | |
974 | equivalencing insn. */ | |
1929b998 | 975 | if (!reg_equiv[regno].is_arg_equivalence) |
d7f88d86 BS |
976 | reg_equiv_init[regno] |
977 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); | |
2ab0437e JH |
978 | |
979 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
980 | We might end up substituting the LABEL_REF for uses of the | |
981 | pseudo here or later. That kind of transformation may turn an | |
982 | indirect jump into a direct jump, in which case we must rerun the | |
983 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
d7f88d86 BS |
984 | if (GET_CODE (x) == LABEL_REF |
985 | || (GET_CODE (x) == CONST | |
986 | && GET_CODE (XEXP (x, 0)) == PLUS | |
987 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
2ab0437e JH |
988 | recorded_label_ref = 1; |
989 | ||
d7f88d86 | 990 | reg_equiv[regno].replacement = x; |
5ca9299f | 991 | reg_equiv[regno].src_p = &SET_SRC (set); |
2ab0437e JH |
992 | reg_equiv[regno].loop_depth = loop_depth; |
993 | ||
994 | /* Don't mess with things live during setjmp. */ | |
995 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
996 | { | |
997 | /* Note that the statement below does not affect the priority | |
998 | in local-alloc! */ | |
999 | REG_LIVE_LENGTH (regno) *= 2; | |
1000 | ||
2ab0437e JH |
1001 | /* If the register is referenced exactly twice, meaning it is |
1002 | set once and used once, indicate that the reference may be | |
1003 | replaced by the equivalence we computed above. Do this | |
1004 | even if the register is only used in one block so that | |
1005 | dependencies can be handled where the last register is | |
1006 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
1007 | and to reduce the number of registers alive across | |
1008 | calls. */ | |
1009 | ||
d7f88d86 BS |
1010 | if (REG_N_REFS (regno) == 2 |
1011 | && (rtx_equal_p (x, src) | |
1012 | || ! equiv_init_varies_p (src)) | |
1013 | && NONJUMP_INSN_P (insn) | |
1014 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
1015 | reg_equiv[regno].replace = 1; | |
2ab0437e | 1016 | } |
68342d36 | 1017 | } |
2bbd3819 RS |
1018 | } |
1019 | } | |
1020 | ||
d7f88d86 BS |
1021 | if (!optimize) |
1022 | goto out; | |
1023 | ||
1024 | /* A second pass, to gather additional equivalences with memory. This needs | |
1025 | to be done after we know which registers we are going to replace. */ | |
1026 | ||
1027 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
1028 | { | |
1029 | rtx set, src, dest; | |
1030 | unsigned regno; | |
1031 | ||
1032 | if (! INSN_P (insn)) | |
1033 | continue; | |
1034 | ||
1035 | set = single_set (insn); | |
1036 | if (! set) | |
1037 | continue; | |
1038 | ||
1039 | dest = SET_DEST (set); | |
1040 | src = SET_SRC (set); | |
1041 | ||
1042 | /* If this sets a MEM to the contents of a REG that is only used | |
1043 | in a single basic block, see if the register is always equivalent | |
1044 | to that memory location and if moving the store from INSN to the | |
1045 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
1046 | initializing insn. | |
1047 | ||
1048 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
1049 | REG_EQUIV is likely more useful than the one we are adding. | |
1050 | ||
1051 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
1052 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
1053 | optimization may move the set of this register immediately before | |
1054 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
1055 | the mention in the REG_EQUIV note would be to an uninitialized | |
1056 | pseudo. */ | |
1057 | ||
1058 | if (MEM_P (dest) && REG_P (src) | |
1059 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
6fb5fa3c DB |
1060 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS |
1061 | && DF_REG_DEF_COUNT (regno) == 1 | |
d7f88d86 BS |
1062 | && reg_equiv[regno].init_insns != 0 |
1063 | && reg_equiv[regno].init_insns != const0_rtx | |
1064 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
1065 | REG_EQUIV, NULL_RTX) | |
1066 | && ! contains_replace_regs (XEXP (dest, 0))) | |
1067 | { | |
1068 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
1069 | if (validate_equiv_mem (init_insn, src, dest) | |
8800a9b3 SB |
1070 | && ! memref_used_between_p (dest, init_insn, insn) |
1071 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
1072 | multiple sets. */ | |
1073 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
d7f88d86 | 1074 | { |
d7f88d86 BS |
1075 | /* This insn makes the equivalence, not the one initializing |
1076 | the register. */ | |
1077 | reg_equiv_init[regno] | |
1078 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); | |
6fb5fa3c | 1079 | df_notes_rescan (init_insn); |
d7f88d86 BS |
1080 | } |
1081 | } | |
1082 | } | |
1083 | ||
6fb5fa3c | 1084 | cleared_regs = BITMAP_ALLOC (NULL); |
2e1253f3 ILT |
1085 | /* Now scan all regs killed in an insn to see if any of them are |
1086 | registers only used that once. If so, see if we can replace the | |
ccb4e87e | 1087 | reference with the equivalent form. If we can, delete the |
2e1253f3 | 1088 | initializing reference and this register will go away. If we |
4d6922ee | 1089 | can't replace the reference, and the initializing reference is |
bf6d9fd7 JW |
1090 | within the same loop (or in an inner loop), then move the register |
1091 | initialization just before the use, so that they are in the same | |
2ab0437e | 1092 | basic block. */ |
e0082a72 | 1093 | FOR_EACH_BB_REVERSE (bb) |
2bbd3819 | 1094 | { |
2ab0437e | 1095 | loop_depth = bb->loop_depth; |
a813c111 SB |
1096 | for (insn = BB_END (bb); |
1097 | insn != PREV_INSN (BB_HEAD (bb)); | |
1098 | insn = PREV_INSN (insn)) | |
2e1253f3 | 1099 | { |
2ab0437e JH |
1100 | rtx link; |
1101 | ||
1102 | if (! INSN_P (insn)) | |
1103 | continue; | |
1104 | ||
2f39b6ca UW |
1105 | /* Don't substitute into a non-local goto, this confuses CFG. */ |
1106 | if (JUMP_P (insn) | |
1107 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
1108 | continue; | |
1109 | ||
2ab0437e | 1110 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
2e1253f3 | 1111 | { |
2ab0437e JH |
1112 | if (REG_NOTE_KIND (link) == REG_DEAD |
1113 | /* Make sure this insn still refers to the register. */ | |
1114 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
2e1253f3 | 1115 | { |
2ab0437e JH |
1116 | int regno = REGNO (XEXP (link, 0)); |
1117 | rtx equiv_insn; | |
1118 | ||
1119 | if (! reg_equiv[regno].replace | |
1120 | || reg_equiv[regno].loop_depth < loop_depth) | |
1121 | continue; | |
1122 | ||
1123 | /* reg_equiv[REGNO].replace gets set only when | |
1124 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
1125 | once and used once. (If it were only set, but not used, | |
1126 | flow would have deleted the setting insns.) Hence | |
1127 | there can only be one insn in reg_equiv[REGNO].init_insns. */ | |
b5e624c6 NS |
1128 | gcc_assert (reg_equiv[regno].init_insns |
1129 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
2ab0437e | 1130 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); |
2e1253f3 | 1131 | |
2ab0437e JH |
1132 | /* We may not move instructions that can throw, since |
1133 | that changes basic block boundaries and we are not | |
1134 | prepared to adjust the CFG to match. */ | |
1135 | if (can_throw_internal (equiv_insn)) | |
1136 | continue; | |
2e1253f3 | 1137 | |
2ab0437e JH |
1138 | if (asm_noperands (PATTERN (equiv_insn)) < 0 |
1139 | && validate_replace_rtx (regno_reg_rtx[regno], | |
5ca9299f | 1140 | *(reg_equiv[regno].src_p), insn)) |
bf6d9fd7 | 1141 | { |
2ab0437e JH |
1142 | rtx equiv_link; |
1143 | rtx last_link; | |
1144 | rtx note; | |
1145 | ||
1146 | /* Find the last note. */ | |
1147 | for (last_link = link; XEXP (last_link, 1); | |
1148 | last_link = XEXP (last_link, 1)) | |
1149 | ; | |
1150 | ||
1151 | /* Append the REG_DEAD notes from equiv_insn. */ | |
1152 | equiv_link = REG_NOTES (equiv_insn); | |
1153 | while (equiv_link) | |
bf6d9fd7 | 1154 | { |
2ab0437e JH |
1155 | note = equiv_link; |
1156 | equiv_link = XEXP (equiv_link, 1); | |
1157 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
1158 | { | |
1159 | remove_note (equiv_insn, note); | |
1160 | XEXP (last_link, 1) = note; | |
1161 | XEXP (note, 1) = NULL_RTX; | |
1162 | last_link = note; | |
1163 | } | |
bf6d9fd7 | 1164 | } |
bf6d9fd7 | 1165 | |
2ab0437e | 1166 | remove_death (regno, insn); |
6fb5fa3c | 1167 | SET_REG_N_REFS (regno, 0); |
2ab0437e | 1168 | REG_FREQ (regno) = 0; |
ca6c03ca | 1169 | delete_insn (equiv_insn); |
e11e816e | 1170 | |
2ab0437e JH |
1171 | reg_equiv[regno].init_insns |
1172 | = XEXP (reg_equiv[regno].init_insns, 1); | |
ccb4e87e | 1173 | |
d7f88d86 | 1174 | reg_equiv_init[regno] = NULL_RTX; |
6fb5fa3c | 1175 | bitmap_set_bit (cleared_regs, regno); |
2ab0437e JH |
1176 | } |
1177 | /* Move the initialization of the register to just before | |
1178 | INSN. Update the flow information. */ | |
1179 | else if (PREV_INSN (insn) != equiv_insn) | |
1180 | { | |
1181 | rtx new_insn; | |
2e1253f3 | 1182 | |
2ab0437e JH |
1183 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); |
1184 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
1185 | REG_NOTES (equiv_insn) = 0; | |
2e1253f3 | 1186 | |
41806d92 NS |
1187 | /* Make sure this insn is recognized before |
1188 | reload begins, otherwise | |
1189 | eliminate_regs_in_insn will die. */ | |
2ab0437e | 1190 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); |
cad33336 | 1191 | |
ca6c03ca | 1192 | delete_insn (equiv_insn); |
2e1253f3 | 1193 | |
2ab0437e | 1194 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; |
96af667a | 1195 | |
e0082a72 | 1196 | REG_BASIC_BLOCK (regno) = bb->index; |
2ab0437e | 1197 | REG_N_CALLS_CROSSED (regno) = 0; |
a03c6d64 | 1198 | REG_FREQ_CALLS_CROSSED (regno) = 0; |
95c37cdb | 1199 | REG_N_THROWING_CALLS_CROSSED (regno) = 0; |
2ab0437e | 1200 | REG_LIVE_LENGTH (regno) = 2; |
2e1253f3 | 1201 | |
a813c111 SB |
1202 | if (insn == BB_HEAD (bb)) |
1203 | BB_HEAD (bb) = PREV_INSN (insn); | |
2e1253f3 | 1204 | |
599c25e2 RH |
1205 | reg_equiv_init[regno] |
1206 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); | |
6fb5fa3c | 1207 | bitmap_set_bit (cleared_regs, regno); |
2ab0437e | 1208 | } |
2e1253f3 ILT |
1209 | } |
1210 | } | |
1211 | } | |
2bbd3819 | 1212 | } |
e05e2395 | 1213 | |
6fb5fa3c DB |
1214 | if (!bitmap_empty_p (cleared_regs)) |
1215 | FOR_EACH_BB (bb) | |
1216 | { | |
ba49cb7b KZ |
1217 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); |
1218 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
6fb5fa3c | 1219 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); |
6fb5fa3c DB |
1220 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); |
1221 | } | |
1222 | ||
1223 | BITMAP_FREE (cleared_regs); | |
25e4379f | 1224 | |
d7f88d86 | 1225 | out: |
e05e2395 | 1226 | /* Clean up. */ |
6fb5fa3c | 1227 | |
e05e2395 | 1228 | end_alias_analysis (); |
bf6d9fd7 | 1229 | free (reg_equiv); |
2bbd3819 | 1230 | } |
135eb61c R |
1231 | |
1232 | /* Mark REG as having no known equivalence. | |
3d042e77 | 1233 | Some instructions might have been processed before and furnished |
135eb61c R |
1234 | with REG_EQUIV notes for this register; these notes will have to be |
1235 | removed. | |
1236 | STORE is the piece of RTL that does the non-constant / conflicting | |
1237 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
1238 | but needs to be there because this function is called from note_stores. */ | |
1239 | static void | |
7bc980e1 | 1240 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED) |
135eb61c R |
1241 | { |
1242 | int regno; | |
1243 | rtx list; | |
1244 | ||
f8cfc6aa | 1245 | if (!REG_P (reg)) |
135eb61c R |
1246 | return; |
1247 | regno = REGNO (reg); | |
bf6d9fd7 | 1248 | list = reg_equiv[regno].init_insns; |
135eb61c R |
1249 | if (list == const0_rtx) |
1250 | return; | |
d7f88d86 BS |
1251 | reg_equiv[regno].init_insns = const0_rtx; |
1252 | reg_equiv[regno].replacement = NULL_RTX; | |
1253 | /* This doesn't matter for equivalences made for argument registers, we | |
1254 | should keep their initialization insns. */ | |
1255 | if (reg_equiv[regno].is_arg_equivalence) | |
1256 | return; | |
1257 | reg_equiv_init[regno] = NULL_RTX; | |
135eb61c R |
1258 | for (; list; list = XEXP (list, 1)) |
1259 | { | |
1260 | rtx insn = XEXP (list, 0); | |
1261 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
1262 | } | |
135eb61c | 1263 | } |
2bbd3819 RS |
1264 | \f |
1265 | /* Allocate hard regs to the pseudo regs used only within block number B. | |
1266 | Only the pseudos that die but once can be handled. */ | |
1267 | ||
1268 | static void | |
0c20a65f | 1269 | block_alloc (int b) |
2bbd3819 | 1270 | { |
b3694847 SS |
1271 | int i, q; |
1272 | rtx insn; | |
d70dcf29 | 1273 | rtx hard_reg; |
2bbd3819 RS |
1274 | int insn_number = 0; |
1275 | int insn_count = 0; | |
1276 | int max_uid = get_max_uid (); | |
aabf56ce | 1277 | int *qty_order; |
ba49cb7b | 1278 | struct df_ref ** def_rec; |
2bbd3819 RS |
1279 | |
1280 | /* Count the instructions in the basic block. */ | |
1281 | ||
a813c111 | 1282 | insn = BB_END (BASIC_BLOCK (b)); |
2bbd3819 RS |
1283 | while (1) |
1284 | { | |
4b4bf941 | 1285 | if (!NOTE_P (insn)) |
b5e624c6 NS |
1286 | { |
1287 | ++insn_count; | |
1288 | gcc_assert (insn_count <= max_uid); | |
1289 | } | |
a813c111 | 1290 | if (insn == BB_HEAD (BASIC_BLOCK (b))) |
2bbd3819 RS |
1291 | break; |
1292 | insn = PREV_INSN (insn); | |
1293 | } | |
1294 | ||
1295 | /* +2 to leave room for a post_mark_life at the last insn and for | |
1296 | the birth of a CLOBBER in the first insn. */ | |
5ed6ace5 | 1297 | regs_live_at = XCNEWVEC (HARD_REG_SET, 2 * insn_count + 2); |
2bbd3819 RS |
1298 | |
1299 | /* Initialize table of hardware registers currently live. */ | |
1300 | ||
ba49cb7b KZ |
1301 | REG_SET_TO_HARD_REG_SET (regs_live, DF_LR_IN (BASIC_BLOCK (b))); |
1302 | ||
1303 | /* This is conservative, as this would include registers that are | |
1304 | artificial-def'ed-but-not-used. However, artificial-defs are | |
1305 | rare, and such uninitialized use is rarer still, and the chance | |
1306 | of this having any performance impact is even less, while the | |
1307 | benefit is not having to compute and keep the TOP set around. */ | |
1308 | for (def_rec = df_get_artificial_defs (b); *def_rec; def_rec++) | |
1309 | { | |
1310 | int regno = DF_REF_REGNO (*def_rec); | |
1311 | if (regno < FIRST_PSEUDO_REGISTER) | |
1312 | SET_HARD_REG_BIT (regs_live, regno); | |
1313 | } | |
2bbd3819 RS |
1314 | |
1315 | /* This loop scans the instructions of the basic block | |
1316 | and assigns quantities to registers. | |
1317 | It computes which registers to tie. */ | |
1318 | ||
a813c111 | 1319 | insn = BB_HEAD (BASIC_BLOCK (b)); |
2bbd3819 RS |
1320 | while (1) |
1321 | { | |
4b4bf941 | 1322 | if (!NOTE_P (insn)) |
2bbd3819 RS |
1323 | insn_number++; |
1324 | ||
2c3c49de | 1325 | if (INSN_P (insn)) |
2bbd3819 | 1326 | { |
d70dcf29 | 1327 | rtx link; |
b3694847 SS |
1328 | int win = 0; |
1329 | rtx r0, r1 = NULL_RTX; | |
2bbd3819 RS |
1330 | int combined_regno = -1; |
1331 | int i; | |
2bbd3819 RS |
1332 | |
1333 | this_insn_number = insn_number; | |
1334 | this_insn = insn; | |
1335 | ||
0a578fee | 1336 | extract_insn (insn); |
2bbd3819 RS |
1337 | which_alternative = -1; |
1338 | ||
1339 | /* Is this insn suitable for tying two registers? | |
1340 | If so, try doing that. | |
1341 | Suitable insns are those with at least two operands and where | |
1342 | operand 0 is an output that is a register that is not | |
1343 | earlyclobber. | |
7aba0f0b RK |
1344 | |
1345 | We can tie operand 0 with some operand that dies in this insn. | |
1346 | First look for operands that are required to be in the same | |
1347 | register as operand 0. If we find such, only try tying that | |
1348 | operand or one that can be put into that operand if the | |
1349 | operation is commutative. If we don't find an operand | |
1350 | that is required to be in the same register as operand 0, | |
1351 | we can tie with any operand. | |
1352 | ||
2bbd3819 RS |
1353 | Subregs in place of regs are also ok. |
1354 | ||
1355 | If tying is done, WIN is set nonzero. */ | |
1356 | ||
d29c259b RH |
1357 | if (optimize |
1358 | && recog_data.n_operands > 1 | |
1ccbefce | 1359 | && recog_data.constraints[0][0] == '=' |
19af6455 | 1360 | && recog_data.constraints[0][1] != '&') |
2bbd3819 | 1361 | { |
3061cc54 | 1362 | /* If non-negative, is an operand that must match operand 0. */ |
7aba0f0b | 1363 | int must_match_0 = -1; |
3061cc54 RK |
1364 | /* Counts number of alternatives that require a match with |
1365 | operand 0. */ | |
1366 | int n_matching_alts = 0; | |
7aba0f0b | 1367 | |
1ccbefce | 1368 | for (i = 1; i < recog_data.n_operands; i++) |
3061cc54 | 1369 | { |
1ccbefce | 1370 | const char *p = recog_data.constraints[i]; |
84b72302 | 1371 | int this_match = requires_inout (p); |
3061cc54 RK |
1372 | |
1373 | n_matching_alts += this_match; | |
1ccbefce | 1374 | if (this_match == recog_data.n_alternatives) |
3061cc54 RK |
1375 | must_match_0 = i; |
1376 | } | |
2bbd3819 | 1377 | |
1ccbefce RH |
1378 | r0 = recog_data.operand[0]; |
1379 | for (i = 1; i < recog_data.n_operands; i++) | |
2bbd3819 | 1380 | { |
7aba0f0b RK |
1381 | /* Skip this operand if we found an operand that |
1382 | must match operand 0 and this operand isn't it | |
1383 | and can't be made to be it by commutativity. */ | |
1384 | ||
1385 | if (must_match_0 >= 0 && i != must_match_0 | |
1386 | && ! (i == must_match_0 + 1 | |
1ccbefce | 1387 | && recog_data.constraints[i-1][0] == '%') |
7aba0f0b | 1388 | && ! (i == must_match_0 - 1 |
1ccbefce | 1389 | && recog_data.constraints[i][0] == '%')) |
7aba0f0b | 1390 | continue; |
3061cc54 RK |
1391 | |
1392 | /* Likewise if each alternative has some operand that | |
64e3a413 | 1393 | must match operand zero. In that case, skip any |
3061cc54 RK |
1394 | operand that doesn't list operand 0 since we know that |
1395 | the operand always conflicts with operand 0. We | |
3d042e77 | 1396 | ignore commutativity in this case to keep things simple. */ |
1ccbefce RH |
1397 | if (n_matching_alts == recog_data.n_alternatives |
1398 | && 0 == requires_inout (recog_data.constraints[i])) | |
3061cc54 | 1399 | continue; |
2bbd3819 | 1400 | |
1ccbefce | 1401 | r1 = recog_data.operand[i]; |
2bbd3819 | 1402 | |
7aba0f0b RK |
1403 | /* If the operand is an address, find a register in it. |
1404 | There may be more than one register, but we only try one | |
1405 | of them. */ | |
ccfc6cc8 | 1406 | if (recog_data.constraints[i][0] == 'p' |
97488870 R |
1407 | || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0], |
1408 | recog_data.constraints[i])) | |
7aba0f0b RK |
1409 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) |
1410 | r1 = XEXP (r1, 0); | |
1411 | ||
902197eb DD |
1412 | /* Avoid making a call-saved register unnecessarily |
1413 | clobbered. */ | |
38173d38 | 1414 | hard_reg = get_hard_reg_initial_reg (r1); |
902197eb DD |
1415 | if (hard_reg != NULL_RTX) |
1416 | { | |
f8cfc6aa | 1417 | if (REG_P (hard_reg) |
f85d8f69 NS |
1418 | && REGNO (hard_reg) < FIRST_PSEUDO_REGISTER |
1419 | && !call_used_regs[REGNO (hard_reg)]) | |
902197eb DD |
1420 | continue; |
1421 | } | |
1422 | ||
f8cfc6aa | 1423 | if (REG_P (r0) || GET_CODE (r0) == SUBREG) |
7aba0f0b RK |
1424 | { |
1425 | /* We have two priorities for hard register preferences. | |
1426 | If we have a move insn or an insn whose first input | |
1427 | can only be in the same register as the output, give | |
1428 | priority to an equivalence found from that insn. */ | |
1429 | int may_save_copy | |
1ccbefce | 1430 | = (r1 == recog_data.operand[i] && must_match_0 >= 0); |
64e3a413 | 1431 | |
f8cfc6aa | 1432 | if (REG_P (r1) || GET_CODE (r1) == SUBREG) |
7aba0f0b | 1433 | win = combine_regs (r1, r0, may_save_copy, |
d70dcf29 | 1434 | insn_number, insn); |
7aba0f0b | 1435 | } |
662347c5 JL |
1436 | if (win) |
1437 | break; | |
2bbd3819 RS |
1438 | } |
1439 | } | |
1440 | ||
2bbd3819 RS |
1441 | /* If registers were just tied, set COMBINED_REGNO |
1442 | to the number of the register used in this insn | |
1443 | that was tied to the register set in this insn. | |
1444 | This register's qty should not be "killed". */ | |
1445 | ||
1446 | if (win) | |
1447 | { | |
1448 | while (GET_CODE (r1) == SUBREG) | |
1449 | r1 = SUBREG_REG (r1); | |
1450 | combined_regno = REGNO (r1); | |
1451 | } | |
1452 | ||
d70dcf29 | 1453 | /* Mark the death of everything that dies in this instruction. */ |
2bbd3819 RS |
1454 | |
1455 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1456 | if (REG_NOTE_KIND (link) == REG_DEAD | |
f8cfc6aa | 1457 | && REG_P (XEXP (link, 0)) |
d70dcf29 | 1458 | && combined_regno != (int) REGNO (XEXP (link, 0))) |
2bbd3819 RS |
1459 | wipe_dead_reg (XEXP (link, 0), 0); |
1460 | ||
1461 | /* Allocate qty numbers for all registers local to this block | |
1462 | that are born (set) in this instruction. | |
1463 | A pseudo that already has a qty is not changed. */ | |
1464 | ||
84832317 | 1465 | note_stores (PATTERN (insn), reg_is_set, NULL); |
2bbd3819 RS |
1466 | |
1467 | /* If anything is set in this insn and then unused, mark it as dying | |
1468 | after this insn, so it will conflict with our outputs. This | |
1469 | can't match with something that combined, and it doesn't matter | |
1470 | if it did. Do this after the calls to reg_is_set since these | |
1471 | die after, not during, the current insn. */ | |
1472 | ||
1473 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1474 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
f8cfc6aa | 1475 | && REG_P (XEXP (link, 0))) |
2bbd3819 | 1476 | wipe_dead_reg (XEXP (link, 0), 1); |
2bbd3819 RS |
1477 | } |
1478 | ||
1479 | /* Set the registers live after INSN_NUMBER. Note that we never | |
1480 | record the registers live before the block's first insn, since no | |
1481 | pseudos we care about are live before that insn. */ | |
1482 | ||
1483 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); | |
1484 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); | |
1485 | ||
a813c111 | 1486 | if (insn == BB_END (BASIC_BLOCK (b))) |
2bbd3819 RS |
1487 | break; |
1488 | ||
1489 | insn = NEXT_INSN (insn); | |
1490 | } | |
1491 | ||
1492 | /* Now every register that is local to this basic block | |
1493 | should have been given a quantity, or else -1 meaning ignore it. | |
64e3a413 | 1494 | Every quantity should have a known birth and death. |
2bbd3819 | 1495 | |
51b86d8b RK |
1496 | Order the qtys so we assign them registers in order of the |
1497 | number of suggested registers they need so we allocate those with | |
1498 | the most restrictive needs first. */ | |
2bbd3819 | 1499 | |
5ed6ace5 | 1500 | qty_order = XNEWVEC (int, next_qty); |
2bbd3819 RS |
1501 | for (i = 0; i < next_qty; i++) |
1502 | qty_order[i] = i; | |
1503 | ||
1504 | #define EXCHANGE(I1, I2) \ | |
1505 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1506 | ||
1507 | switch (next_qty) | |
1508 | { | |
1509 | case 3: | |
1510 | /* Make qty_order[2] be the one to allocate last. */ | |
51b86d8b | 1511 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 | 1512 | EXCHANGE (0, 1); |
51b86d8b | 1513 | if (qty_sugg_compare (1, 2) > 0) |
2bbd3819 RS |
1514 | EXCHANGE (2, 1); |
1515 | ||
0f41302f | 1516 | /* ... Fall through ... */ |
2bbd3819 RS |
1517 | case 2: |
1518 | /* Put the best one to allocate in qty_order[0]. */ | |
51b86d8b | 1519 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 RS |
1520 | EXCHANGE (0, 1); |
1521 | ||
0f41302f | 1522 | /* ... Fall through ... */ |
2bbd3819 RS |
1523 | |
1524 | case 1: | |
1525 | case 0: | |
1526 | /* Nothing to do here. */ | |
1527 | break; | |
1528 | ||
1529 | default: | |
51b86d8b | 1530 | qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); |
2bbd3819 RS |
1531 | } |
1532 | ||
1533 | /* Try to put each quantity in a suggested physical register, if it has one. | |
1534 | This may cause registers to be allocated that otherwise wouldn't be, but | |
1535 | this seems acceptable in local allocation (unlike global allocation). */ | |
1536 | for (i = 0; i < next_qty; i++) | |
1537 | { | |
1538 | q = qty_order[i]; | |
51b86d8b | 1539 | if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) |
a1ed7bdb JH |
1540 | qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q, |
1541 | 0, 1, qty[q].birth, qty[q].death); | |
2bbd3819 | 1542 | else |
a1ed7bdb | 1543 | qty[q].phys_reg = -1; |
2bbd3819 RS |
1544 | } |
1545 | ||
64e3a413 KH |
1546 | /* Order the qtys so we assign them registers in order of |
1547 | decreasing length of life. Normally call qsort, but if we | |
51b86d8b RK |
1548 | have only a very small number of quantities, sort them ourselves. */ |
1549 | ||
1550 | for (i = 0; i < next_qty; i++) | |
1551 | qty_order[i] = i; | |
1552 | ||
1553 | #define EXCHANGE(I1, I2) \ | |
1554 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1555 | ||
1556 | switch (next_qty) | |
1557 | { | |
1558 | case 3: | |
1559 | /* Make qty_order[2] be the one to allocate last. */ | |
1560 | if (qty_compare (0, 1) > 0) | |
1561 | EXCHANGE (0, 1); | |
1562 | if (qty_compare (1, 2) > 0) | |
1563 | EXCHANGE (2, 1); | |
1564 | ||
0f41302f | 1565 | /* ... Fall through ... */ |
51b86d8b RK |
1566 | case 2: |
1567 | /* Put the best one to allocate in qty_order[0]. */ | |
1568 | if (qty_compare (0, 1) > 0) | |
1569 | EXCHANGE (0, 1); | |
1570 | ||
0f41302f | 1571 | /* ... Fall through ... */ |
51b86d8b RK |
1572 | |
1573 | case 1: | |
1574 | case 0: | |
1575 | /* Nothing to do here. */ | |
1576 | break; | |
1577 | ||
1578 | default: | |
1579 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); | |
1580 | } | |
1581 | ||
2bbd3819 RS |
1582 | /* Now for each qty that is not a hardware register, |
1583 | look for a hardware register to put it in. | |
1584 | First try the register class that is cheapest for this qty, | |
1585 | if there is more than one class. */ | |
1586 | ||
1587 | for (i = 0; i < next_qty; i++) | |
1588 | { | |
1589 | q = qty_order[i]; | |
a1ed7bdb | 1590 | if (qty[q].phys_reg < 0) |
2bbd3819 | 1591 | { |
624a8b3a JL |
1592 | #ifdef INSN_SCHEDULING |
1593 | /* These values represent the adjusted lifetime of a qty so | |
1594 | that it conflicts with qtys which appear near the start/end | |
1595 | of this qty's lifetime. | |
1596 | ||
1597 | The purpose behind extending the lifetime of this qty is to | |
1598 | discourage the register allocator from creating false | |
1599 | dependencies. | |
64e3a413 | 1600 | |
f63d1bf7 | 1601 | The adjustment value is chosen to indicate that this qty |
996e9683 | 1602 | conflicts with all the qtys in the instructions immediately |
624a8b3a JL |
1603 | before and after the lifetime of this qty. |
1604 | ||
1605 | Experiments have shown that higher values tend to hurt | |
1606 | overall code performance. | |
1607 | ||
1608 | If allocation using the extended lifetime fails we will try | |
1609 | again with the qty's unadjusted lifetime. */ | |
a1ed7bdb | 1610 | int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2); |
996e9683 | 1611 | int fake_death = MIN (insn_number * 2 + 1, |
a1ed7bdb | 1612 | qty[q].death + 2 - qty[q].death % 2); |
624a8b3a JL |
1613 | #endif |
1614 | ||
2bbd3819 RS |
1615 | if (N_REG_CLASSES > 1) |
1616 | { | |
624a8b3a JL |
1617 | #ifdef INSN_SCHEDULING |
1618 | /* We try to avoid using hard registers allocated to qtys which | |
1619 | are born immediately after this qty or die immediately before | |
1620 | this qty. | |
1621 | ||
1622 | This optimization is only appropriate when we will run | |
1623 | a scheduling pass after reload and we are not optimizing | |
1624 | for code size. */ | |
6fb5fa3c | 1625 | if (flag_schedule_insns_after_reload && dbg_cnt (local_alloc_for_sched) |
c358412f JL |
1626 | && !optimize_size |
1627 | && !SMALL_REGISTER_CLASSES) | |
624a8b3a | 1628 | { |
64e3a413 | 1629 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb | 1630 | qty[q].mode, q, 0, 0, |
624a8b3a | 1631 | fake_birth, fake_death); |
a1ed7bdb | 1632 | if (qty[q].phys_reg >= 0) |
624a8b3a JL |
1633 | continue; |
1634 | } | |
1635 | #endif | |
64e3a413 | 1636 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb JH |
1637 | qty[q].mode, q, 0, 0, |
1638 | qty[q].birth, qty[q].death); | |
1639 | if (qty[q].phys_reg >= 0) | |
2bbd3819 RS |
1640 | continue; |
1641 | } | |
1642 | ||
624a8b3a JL |
1643 | #ifdef INSN_SCHEDULING |
1644 | /* Similarly, avoid false dependencies. */ | |
6fb5fa3c | 1645 | if (flag_schedule_insns_after_reload && dbg_cnt (local_alloc_for_sched) |
c358412f JL |
1646 | && !optimize_size |
1647 | && !SMALL_REGISTER_CLASSES | |
a1ed7bdb JH |
1648 | && qty[q].alternate_class != NO_REGS) |
1649 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1650 | qty[q].mode, q, 0, 0, | |
624a8b3a JL |
1651 | fake_birth, fake_death); |
1652 | #endif | |
a1ed7bdb JH |
1653 | if (qty[q].alternate_class != NO_REGS) |
1654 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1655 | qty[q].mode, q, 0, 0, | |
1656 | qty[q].birth, qty[q].death); | |
2bbd3819 RS |
1657 | } |
1658 | } | |
1659 | ||
1660 | /* Now propagate the register assignments | |
1661 | to the pseudo regs belonging to the qtys. */ | |
1662 | ||
1663 | for (q = 0; q < next_qty; q++) | |
a1ed7bdb | 1664 | if (qty[q].phys_reg >= 0) |
2bbd3819 | 1665 | { |
a1ed7bdb JH |
1666 | for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i]) |
1667 | reg_renumber[i] = qty[q].phys_reg + reg_offset[i]; | |
2bbd3819 | 1668 | } |
ff154f78 MM |
1669 | |
1670 | /* Clean up. */ | |
1671 | free (regs_live_at); | |
1672 | free (qty_order); | |
2bbd3819 RS |
1673 | } |
1674 | \f | |
1675 | /* Compare two quantities' priority for getting real registers. | |
1676 | We give shorter-lived quantities higher priority. | |
6dc42e49 RS |
1677 | Quantities with more references are also preferred, as are quantities that |
1678 | require multiple registers. This is the identical prioritization as | |
2bbd3819 RS |
1679 | done by global-alloc. |
1680 | ||
1681 | We used to give preference to registers with *longer* lives, but using | |
1682 | the same algorithm in both local- and global-alloc can speed up execution | |
1683 | of some programs by as much as a factor of three! */ | |
1684 | ||
2f23fcc9 RK |
1685 | /* Note that the quotient will never be bigger than |
1686 | the value of floor_log2 times the maximum number of | |
a08b2604 JH |
1687 | times a register can occur in one insn (surely less than 100) |
1688 | weighted by frequency (max REG_FREQ_MAX). | |
1689 | Multiplying this by 10000/REG_FREQ_MAX can't overflow. | |
2f23fcc9 RK |
1690 | QTY_CMP_PRI is also used by qty_sugg_compare. */ |
1691 | ||
1692 | #define QTY_CMP_PRI(q) \ | |
b2aec5c0 | 1693 | ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \ |
a08b2604 | 1694 | / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX))) |
2f23fcc9 | 1695 | |
2bbd3819 | 1696 | static int |
0c20a65f | 1697 | qty_compare (int q1, int q2) |
2bbd3819 | 1698 | { |
2f23fcc9 | 1699 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
2bbd3819 RS |
1700 | } |
1701 | ||
1702 | static int | |
0c20a65f | 1703 | qty_compare_1 (const void *q1p, const void *q2p) |
2bbd3819 | 1704 | { |
b3694847 SS |
1705 | int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
1706 | int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
2f23fcc9 RK |
1707 | |
1708 | if (tem != 0) | |
1709 | return tem; | |
1710 | ||
2bbd3819 RS |
1711 | /* If qtys are equally good, sort by qty number, |
1712 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1713 | return q1 - q2; |
2bbd3819 RS |
1714 | } |
1715 | \f | |
51b86d8b RK |
1716 | /* Compare two quantities' priority for getting real registers. This version |
1717 | is called for quantities that have suggested hard registers. First priority | |
1718 | goes to quantities that have copy preferences, then to those that have | |
1719 | normal preferences. Within those groups, quantities with the lower | |
9faa82d8 | 1720 | number of preferences have the highest priority. Of those, we use the same |
51b86d8b RK |
1721 | algorithm as above. */ |
1722 | ||
2f23fcc9 RK |
1723 | #define QTY_CMP_SUGG(q) \ |
1724 | (qty_phys_num_copy_sugg[q] \ | |
1725 | ? qty_phys_num_copy_sugg[q] \ | |
1726 | : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER) | |
1727 | ||
51b86d8b | 1728 | static int |
0c20a65f | 1729 | qty_sugg_compare (int q1, int q2) |
51b86d8b | 1730 | { |
b3694847 | 1731 | int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
2f23fcc9 RK |
1732 | |
1733 | if (tem != 0) | |
1734 | return tem; | |
64e3a413 | 1735 | |
2f23fcc9 | 1736 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
51b86d8b RK |
1737 | } |
1738 | ||
1739 | static int | |
0c20a65f | 1740 | qty_sugg_compare_1 (const void *q1p, const void *q2p) |
51b86d8b | 1741 | { |
b3694847 SS |
1742 | int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
1743 | int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); | |
2f23fcc9 RK |
1744 | |
1745 | if (tem != 0) | |
1746 | return tem; | |
1747 | ||
1748 | tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
1749 | if (tem != 0) | |
1750 | return tem; | |
51b86d8b RK |
1751 | |
1752 | /* If qtys are equally good, sort by qty number, | |
1753 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1754 | return q1 - q2; |
51b86d8b | 1755 | } |
2f23fcc9 RK |
1756 | |
1757 | #undef QTY_CMP_SUGG | |
1758 | #undef QTY_CMP_PRI | |
51b86d8b | 1759 | \f |
2bbd3819 RS |
1760 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. |
1761 | Returns 1 if have done so, or 0 if cannot. | |
1762 | ||
1763 | Combining registers means marking them as having the same quantity | |
1764 | and adjusting the offsets within the quantity if either of | |
a5342656 | 1765 | them is a SUBREG. |
2bbd3819 RS |
1766 | |
1767 | We don't actually combine a hard reg with a pseudo; instead | |
1768 | we just record the hard reg as the suggestion for the pseudo's quantity. | |
1769 | If we really combined them, we could lose if the pseudo lives | |
70128ad9 | 1770 | across an insn that clobbers the hard reg (eg, movmem). |
2bbd3819 | 1771 | |
a5342656 | 1772 | MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to |
2bbd3819 RS |
1773 | SETREG or if the input and output must share a register. |
1774 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. | |
64e3a413 | 1775 | |
2bbd3819 RS |
1776 | There are elaborate checks for the validity of combining. */ |
1777 | ||
2bbd3819 | 1778 | static int |
0c20a65f | 1779 | combine_regs (rtx usedreg, rtx setreg, int may_save_copy, int insn_number, |
d70dcf29 | 1780 | rtx insn) |
2bbd3819 | 1781 | { |
b3694847 SS |
1782 | int ureg, sreg; |
1783 | int offset = 0; | |
2bbd3819 | 1784 | int usize, ssize; |
b3694847 | 1785 | int sqty; |
2bbd3819 RS |
1786 | |
1787 | /* Determine the numbers and sizes of registers being used. If a subreg | |
6dc42e49 | 1788 | is present that does not change the entire register, don't consider |
2bbd3819 RS |
1789 | this a copy insn. */ |
1790 | ||
1791 | while (GET_CODE (usedreg) == SUBREG) | |
1792 | { | |
44a5da09 GS |
1793 | rtx subreg = SUBREG_REG (usedreg); |
1794 | ||
f8cfc6aa | 1795 | if (REG_P (subreg)) |
44a5da09 GS |
1796 | { |
1797 | if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD) | |
1798 | may_save_copy = 0; | |
1799 | ||
1800 | if (REGNO (subreg) < FIRST_PSEUDO_REGISTER) | |
1801 | offset += subreg_regno_offset (REGNO (subreg), | |
1802 | GET_MODE (subreg), | |
1803 | SUBREG_BYTE (usedreg), | |
1804 | GET_MODE (usedreg)); | |
1805 | else | |
1806 | offset += (SUBREG_BYTE (usedreg) | |
1807 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
1808 | } | |
1809 | ||
1810 | usedreg = subreg; | |
2bbd3819 | 1811 | } |
44a5da09 | 1812 | |
f8cfc6aa | 1813 | if (!REG_P (usedreg)) |
2bbd3819 | 1814 | return 0; |
44a5da09 | 1815 | |
2bbd3819 | 1816 | ureg = REGNO (usedreg); |
ddef6bc7 | 1817 | if (ureg < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 1818 | usize = hard_regno_nregs[ureg][GET_MODE (usedreg)]; |
ddef6bc7 JJ |
1819 | else |
1820 | usize = ((GET_MODE_SIZE (GET_MODE (usedreg)) | |
1821 | + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1)) | |
1822 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
2bbd3819 RS |
1823 | |
1824 | while (GET_CODE (setreg) == SUBREG) | |
1825 | { | |
44a5da09 GS |
1826 | rtx subreg = SUBREG_REG (setreg); |
1827 | ||
f8cfc6aa | 1828 | if (REG_P (subreg)) |
44a5da09 GS |
1829 | { |
1830 | if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD) | |
1831 | may_save_copy = 0; | |
1832 | ||
1833 | if (REGNO (subreg) < FIRST_PSEUDO_REGISTER) | |
1834 | offset -= subreg_regno_offset (REGNO (subreg), | |
1835 | GET_MODE (subreg), | |
1836 | SUBREG_BYTE (setreg), | |
1837 | GET_MODE (setreg)); | |
1838 | else | |
1839 | offset -= (SUBREG_BYTE (setreg) | |
1840 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
1841 | } | |
1842 | ||
1843 | setreg = subreg; | |
2bbd3819 | 1844 | } |
44a5da09 | 1845 | |
f8cfc6aa | 1846 | if (!REG_P (setreg)) |
2bbd3819 | 1847 | return 0; |
44a5da09 | 1848 | |
2bbd3819 | 1849 | sreg = REGNO (setreg); |
ddef6bc7 | 1850 | if (sreg < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 1851 | ssize = hard_regno_nregs[sreg][GET_MODE (setreg)]; |
ddef6bc7 JJ |
1852 | else |
1853 | ssize = ((GET_MODE_SIZE (GET_MODE (setreg)) | |
1854 | + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1)) | |
1855 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
2bbd3819 RS |
1856 | |
1857 | /* If UREG is a pseudo-register that hasn't already been assigned a | |
1858 | quantity number, it means that it is not local to this block or dies | |
1859 | more than once. In either event, we can't do anything with it. */ | |
1860 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) | |
1861 | /* Do not combine registers unless one fits within the other. */ | |
1862 | || (offset > 0 && usize + offset > ssize) | |
1863 | || (offset < 0 && usize + offset < ssize) | |
1864 | /* Do not combine with a smaller already-assigned object | |
0f41302f | 1865 | if that smaller object is already combined with something bigger. */ |
2bbd3819 | 1866 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER |
a1ed7bdb | 1867 | && usize < qty[reg_qty[ureg]].size) |
2bbd3819 RS |
1868 | /* Can't combine if SREG is not a register we can allocate. */ |
1869 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) | |
2bbd3819 RS |
1870 | /* Don't tie something to itself. In most cases it would make no |
1871 | difference, but it would screw up if the reg being tied to itself | |
1872 | also dies in this insn. */ | |
1873 | || ureg == sreg | |
1874 | /* Don't try to connect two different hardware registers. */ | |
1875 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) | |
1876 | /* Don't connect two different machine modes if they have different | |
1877 | implications as to which registers may be used. */ | |
1878 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) | |
1879 | return 0; | |
1880 | ||
1881 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in | |
1882 | qty_phys_sugg for the pseudo instead of tying them. | |
1883 | ||
1884 | Return "failure" so that the lifespan of UREG is terminated here; | |
1885 | that way the two lifespans will be disjoint and nothing will prevent | |
1886 | the pseudo reg from being given this hard reg. */ | |
1887 | ||
1888 | if (ureg < FIRST_PSEUDO_REGISTER) | |
1889 | { | |
1890 | /* Allocate a quantity number so we have a place to put our | |
1891 | suggestions. */ | |
1892 | if (reg_qty[sreg] == -2) | |
1893 | reg_is_born (setreg, 2 * insn_number); | |
1894 | ||
1895 | if (reg_qty[sreg] >= 0) | |
1896 | { | |
51b86d8b RK |
1897 | if (may_save_copy |
1898 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) | |
2bbd3819 RS |
1899 | { |
1900 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1901 | qty_phys_num_copy_sugg[reg_qty[sreg]]++; |
2bbd3819 | 1902 | } |
51b86d8b | 1903 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) |
2bbd3819 RS |
1904 | { |
1905 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1906 | qty_phys_num_sugg[reg_qty[sreg]]++; |
2bbd3819 RS |
1907 | } |
1908 | } | |
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | /* Similarly for SREG a hard register and UREG a pseudo register. */ | |
1913 | ||
1914 | if (sreg < FIRST_PSEUDO_REGISTER) | |
1915 | { | |
51b86d8b RK |
1916 | if (may_save_copy |
1917 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) | |
2bbd3819 RS |
1918 | { |
1919 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1920 | qty_phys_num_copy_sugg[reg_qty[ureg]]++; |
2bbd3819 | 1921 | } |
51b86d8b | 1922 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) |
2bbd3819 RS |
1923 | { |
1924 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1925 | qty_phys_num_sugg[reg_qty[ureg]]++; |
2bbd3819 RS |
1926 | } |
1927 | return 0; | |
1928 | } | |
1929 | ||
1930 | /* At this point we know that SREG and UREG are both pseudos. | |
1931 | Do nothing if SREG already has a quantity or is a register that we | |
1932 | don't allocate. */ | |
1933 | if (reg_qty[sreg] >= -1 | |
1934 | /* If we are not going to let any regs live across calls, | |
1935 | don't tie a call-crossing reg to a non-call-crossing reg. */ | |
e3b5732b | 1936 | || (cfun->has_nonlocal_label |
b1f21e0a MM |
1937 | && ((REG_N_CALLS_CROSSED (ureg) > 0) |
1938 | != (REG_N_CALLS_CROSSED (sreg) > 0)))) | |
2bbd3819 RS |
1939 | return 0; |
1940 | ||
1941 | /* We don't already know about SREG, so tie it to UREG | |
1942 | if this is the last use of UREG, provided the classes they want | |
1943 | are compatible. */ | |
1944 | ||
d70dcf29 | 1945 | if (find_regno_note (insn, REG_DEAD, ureg) |
a1ed7bdb | 1946 | && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class)) |
2bbd3819 RS |
1947 | { |
1948 | /* Add SREG to UREG's quantity. */ | |
1949 | sqty = reg_qty[ureg]; | |
1950 | reg_qty[sreg] = sqty; | |
1951 | reg_offset[sreg] = reg_offset[ureg] + offset; | |
a1ed7bdb JH |
1952 | reg_next_in_qty[sreg] = qty[sqty].first_reg; |
1953 | qty[sqty].first_reg = sreg; | |
2bbd3819 | 1954 | |
a1ed7bdb | 1955 | /* If SREG's reg class is smaller, set qty[SQTY].min_class. */ |
2bbd3819 RS |
1956 | update_qty_class (sqty, sreg); |
1957 | ||
1958 | /* Update info about quantity SQTY. */ | |
a1ed7bdb | 1959 | qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg); |
a03c6d64 | 1960 | qty[sqty].freq_calls_crossed += REG_FREQ_CALLS_CROSSED (sreg); |
95c37cdb JJ |
1961 | qty[sqty].n_throwing_calls_crossed |
1962 | += REG_N_THROWING_CALLS_CROSSED (sreg); | |
a1ed7bdb | 1963 | qty[sqty].n_refs += REG_N_REFS (sreg); |
b2aec5c0 | 1964 | qty[sqty].freq += REG_FREQ (sreg); |
2bbd3819 RS |
1965 | if (usize < ssize) |
1966 | { | |
b3694847 | 1967 | int i; |
2bbd3819 | 1968 | |
a1ed7bdb | 1969 | for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i]) |
2bbd3819 RS |
1970 | reg_offset[i] -= offset; |
1971 | ||
a1ed7bdb JH |
1972 | qty[sqty].size = ssize; |
1973 | qty[sqty].mode = GET_MODE (setreg); | |
2bbd3819 RS |
1974 | } |
1975 | } | |
1976 | else | |
1977 | return 0; | |
1978 | ||
1979 | return 1; | |
1980 | } | |
1981 | \f | |
1982 | /* Return 1 if the preferred class of REG allows it to be tied | |
1983 | to a quantity or register whose class is CLASS. | |
1984 | True if REG's reg class either contains or is contained in CLASS. */ | |
1985 | ||
1986 | static int | |
0c20a65f | 1987 | reg_meets_class_p (int reg, enum reg_class class) |
2bbd3819 | 1988 | { |
b3694847 | 1989 | enum reg_class rclass = reg_preferred_class (reg); |
2bbd3819 RS |
1990 | return (reg_class_subset_p (rclass, class) |
1991 | || reg_class_subset_p (class, rclass)); | |
1992 | } | |
1993 | ||
a1ed7bdb | 1994 | /* Update the class of QTYNO assuming that REG is being tied to it. */ |
2bbd3819 RS |
1995 | |
1996 | static void | |
0c20a65f | 1997 | update_qty_class (int qtyno, int reg) |
2bbd3819 RS |
1998 | { |
1999 | enum reg_class rclass = reg_preferred_class (reg); | |
a1ed7bdb JH |
2000 | if (reg_class_subset_p (rclass, qty[qtyno].min_class)) |
2001 | qty[qtyno].min_class = rclass; | |
e4600702 RK |
2002 | |
2003 | rclass = reg_alternate_class (reg); | |
a1ed7bdb JH |
2004 | if (reg_class_subset_p (rclass, qty[qtyno].alternate_class)) |
2005 | qty[qtyno].alternate_class = rclass; | |
2bbd3819 RS |
2006 | } |
2007 | \f | |
2008 | /* Handle something which alters the value of an rtx REG. | |
2009 | ||
2010 | REG is whatever is set or clobbered. SETTER is the rtx that | |
2011 | is modifying the register. | |
2012 | ||
2013 | If it is not really a register, we do nothing. | |
2014 | The file-global variables `this_insn' and `this_insn_number' | |
2015 | carry info from `block_alloc'. */ | |
2016 | ||
2017 | static void | |
7bc980e1 | 2018 | reg_is_set (rtx reg, const_rtx setter, void *data ATTRIBUTE_UNUSED) |
2bbd3819 RS |
2019 | { |
2020 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of | |
2021 | a hard register. These may actually not exist any more. */ | |
2022 | ||
2023 | if (GET_CODE (reg) != SUBREG | |
f8cfc6aa | 2024 | && !REG_P (reg)) |
2bbd3819 RS |
2025 | return; |
2026 | ||
2027 | /* Mark this register as being born. If it is used in a CLOBBER, mark | |
2028 | it as being born halfway between the previous insn and this insn so that | |
2029 | it conflicts with our inputs but not the outputs of the previous insn. */ | |
2030 | ||
2031 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); | |
2032 | } | |
2033 | \f | |
2034 | /* Handle beginning of the life of register REG. | |
2035 | BIRTH is the index at which this is happening. */ | |
2036 | ||
2037 | static void | |
0c20a65f | 2038 | reg_is_born (rtx reg, int birth) |
2bbd3819 | 2039 | { |
b3694847 | 2040 | int regno; |
64e3a413 | 2041 | |
2bbd3819 | 2042 | if (GET_CODE (reg) == SUBREG) |
ddef6bc7 JJ |
2043 | { |
2044 | regno = REGNO (SUBREG_REG (reg)); | |
2045 | if (regno < FIRST_PSEUDO_REGISTER) | |
6f9e3578 | 2046 | regno = subreg_regno (reg); |
ddef6bc7 | 2047 | } |
2bbd3819 RS |
2048 | else |
2049 | regno = REGNO (reg); | |
2050 | ||
2051 | if (regno < FIRST_PSEUDO_REGISTER) | |
2052 | { | |
2053 | mark_life (regno, GET_MODE (reg), 1); | |
2054 | ||
2055 | /* If the register was to have been born earlier that the present | |
2056 | insn, mark it as live where it is actually born. */ | |
2057 | if (birth < 2 * this_insn_number) | |
2058 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); | |
2059 | } | |
2060 | else | |
2061 | { | |
2062 | if (reg_qty[regno] == -2) | |
2063 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); | |
2064 | ||
2065 | /* If this register has a quantity number, show that it isn't dead. */ | |
2066 | if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2067 | qty[reg_qty[regno]].death = -1; |
2bbd3819 RS |
2068 | } |
2069 | } | |
2070 | ||
cc2902df | 2071 | /* Record the death of REG in the current insn. If OUTPUT_P is nonzero, |
2bbd3819 | 2072 | REG is an output that is dying (i.e., it is never used), otherwise it |
333e0f7d RS |
2073 | is an input (the normal case). |
2074 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ | |
2bbd3819 RS |
2075 | |
2076 | static void | |
0c20a65f | 2077 | wipe_dead_reg (rtx reg, int output_p) |
2bbd3819 | 2078 | { |
b3694847 | 2079 | int regno = REGNO (reg); |
2bbd3819 | 2080 | |
333e0f7d RS |
2081 | /* If this insn has multiple results, |
2082 | and the dead reg is used in one of the results, | |
2083 | extend its life to after this insn, | |
64e3a413 | 2084 | so it won't get allocated together with any other result of this insn. |
941c63ac JL |
2085 | |
2086 | It is unsafe to use !single_set here since it will ignore an unused | |
2087 | output. Just because an output is unused does not mean the compiler | |
2088 | can assume the side effect will not occur. Consider if REG appears | |
2089 | in the address of an output and we reload the output. If we allocate | |
2090 | REG to the same hard register as an unused output we could set the hard | |
2091 | register before the output reload insn. */ | |
333e0f7d | 2092 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL |
941c63ac | 2093 | && multiple_sets (this_insn)) |
333e0f7d RS |
2094 | { |
2095 | int i; | |
2096 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) | |
2097 | { | |
2098 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); | |
2099 | if (GET_CODE (set) == SET | |
f8cfc6aa | 2100 | && !REG_P (SET_DEST (set)) |
333e0f7d RS |
2101 | && !rtx_equal_p (reg, SET_DEST (set)) |
2102 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2103 | output_p = 1; | |
2104 | } | |
2105 | } | |
2106 | ||
c182df0b RK |
2107 | /* If this register is used in an auto-increment address, then extend its |
2108 | life to after this insn, so that it won't get allocated together with | |
2109 | the result of this insn. */ | |
2110 | if (! output_p && find_regno_note (this_insn, REG_INC, regno)) | |
2111 | output_p = 1; | |
2112 | ||
2bbd3819 RS |
2113 | if (regno < FIRST_PSEUDO_REGISTER) |
2114 | { | |
2115 | mark_life (regno, GET_MODE (reg), 0); | |
2116 | ||
2117 | /* If a hard register is dying as an output, mark it as in use at | |
2118 | the beginning of this insn (the above statement would cause this | |
2119 | not to happen). */ | |
2120 | if (output_p) | |
2121 | post_mark_life (regno, GET_MODE (reg), 1, | |
64e3a413 | 2122 | 2 * this_insn_number, 2 * this_insn_number + 1); |
2bbd3819 RS |
2123 | } |
2124 | ||
2125 | else if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2126 | qty[reg_qty[regno]].death = 2 * this_insn_number + output_p; |
2bbd3819 RS |
2127 | } |
2128 | \f | |
2129 | /* Find a block of SIZE words of hard regs in reg_class CLASS | |
2130 | that can hold something of machine-mode MODE | |
2131 | (but actually we test only the first of the block for holding MODE) | |
2132 | and still free between insn BORN_INDEX and insn DEAD_INDEX, | |
2133 | and return the number of the first of them. | |
64e3a413 | 2134 | Return -1 if such a block cannot be found. |
a1ed7bdb | 2135 | If QTYNO crosses calls, insist on a register preserved by calls, |
2bbd3819 RS |
2136 | unless ACCEPT_CALL_CLOBBERED is nonzero. |
2137 | ||
cc2902df | 2138 | If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested |
2bbd3819 RS |
2139 | register is available. If not, return -1. */ |
2140 | ||
2141 | static int | |
0c20a65f AJ |
2142 | find_free_reg (enum reg_class class, enum machine_mode mode, int qtyno, |
2143 | int accept_call_clobbered, int just_try_suggested, | |
2144 | int born_index, int dead_index) | |
2bbd3819 | 2145 | { |
b3694847 | 2146 | int i, ins; |
cff9f8d5 | 2147 | HARD_REG_SET first_used, used; |
2bbd3819 | 2148 | #ifdef ELIMINABLE_REGS |
8b60264b | 2149 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
2bbd3819 RS |
2150 | #endif |
2151 | ||
2152 | /* Validate our parameters. */ | |
b5e624c6 | 2153 | gcc_assert (born_index >= 0 && born_index <= dead_index); |
2bbd3819 RS |
2154 | |
2155 | /* Don't let a pseudo live in a reg across a function call | |
2156 | if we might get a nonlocal goto. */ | |
e3b5732b | 2157 | if (cfun->has_nonlocal_label |
a1ed7bdb | 2158 | && qty[qtyno].n_calls_crossed > 0) |
2bbd3819 RS |
2159 | return -1; |
2160 | ||
2161 | if (accept_call_clobbered) | |
2162 | COPY_HARD_REG_SET (used, call_fixed_reg_set); | |
a1ed7bdb | 2163 | else if (qty[qtyno].n_calls_crossed == 0) |
2bbd3819 RS |
2164 | COPY_HARD_REG_SET (used, fixed_reg_set); |
2165 | else | |
2166 | COPY_HARD_REG_SET (used, call_used_reg_set); | |
2167 | ||
6cad67d2 | 2168 | if (accept_call_clobbered) |
c09be6c4 | 2169 | IOR_HARD_REG_SET (used, losing_caller_save_reg_set); |
6cad67d2 | 2170 | |
2bbd3819 RS |
2171 | for (ins = born_index; ins < dead_index; ins++) |
2172 | IOR_HARD_REG_SET (used, regs_live_at[ins]); | |
2173 | ||
2174 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); | |
2175 | ||
2176 | /* Don't use the frame pointer reg in local-alloc even if | |
2177 | we may omit the frame pointer, because if we do that and then we | |
2178 | need a frame pointer, reload won't know how to move the pseudo | |
2179 | to another hard reg. It can move only regs made by global-alloc. | |
2180 | ||
2181 | This is true of any register that can be eliminated. */ | |
2182 | #ifdef ELIMINABLE_REGS | |
b6a1cbae | 2183 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) |
2bbd3819 | 2184 | SET_HARD_REG_BIT (used, eliminables[i].from); |
c2618f05 DE |
2185 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
2186 | /* If FRAME_POINTER_REGNUM is not a real register, then protect the one | |
0f41302f | 2187 | that it might be eliminated into. */ |
c2618f05 DE |
2188 | SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); |
2189 | #endif | |
2bbd3819 RS |
2190 | #else |
2191 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); | |
2192 | #endif | |
2193 | ||
cff9f8d5 AH |
2194 | #ifdef CANNOT_CHANGE_MODE_CLASS |
2195 | cannot_change_mode_set_regs (&used, mode, qty[qtyno].first_reg); | |
0f64b8f6 RK |
2196 | #endif |
2197 | ||
2bbd3819 RS |
2198 | /* Normally, the registers that can be used for the first register in |
2199 | a multi-register quantity are the same as those that can be used for | |
2200 | subsequent registers. However, if just trying suggested registers, | |
2201 | restrict our consideration to them. If there are copy-suggested | |
2202 | register, try them. Otherwise, try the arithmetic-suggested | |
2203 | registers. */ | |
2204 | COPY_HARD_REG_SET (first_used, used); | |
2205 | ||
2206 | if (just_try_suggested) | |
2207 | { | |
a1ed7bdb JH |
2208 | if (qty_phys_num_copy_sugg[qtyno] != 0) |
2209 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]); | |
2bbd3819 | 2210 | else |
a1ed7bdb | 2211 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]); |
2bbd3819 RS |
2212 | } |
2213 | ||
2bbd3819 | 2214 | /* If at least one would be suitable, test each hard reg. */ |
56b138ae RS |
2215 | if (!hard_reg_set_subset_p (reg_class_contents[(int) ALL_REGS], first_used)) |
2216 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2217 | { | |
2bbd3819 | 2218 | #ifdef REG_ALLOC_ORDER |
56b138ae | 2219 | int regno = reg_alloc_order[i]; |
2bbd3819 | 2220 | #else |
56b138ae | 2221 | int regno = i; |
2bbd3819 | 2222 | #endif |
56b138ae RS |
2223 | if (!TEST_HARD_REG_BIT (first_used, regno) |
2224 | && HARD_REGNO_MODE_OK (regno, mode) | |
2225 | && (qty[qtyno].n_calls_crossed == 0 | |
2226 | || accept_call_clobbered | |
2227 | || !HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
2228 | { | |
2229 | int j; | |
2230 | int size1 = hard_regno_nregs[regno][mode]; | |
2231 | j = 1; | |
2232 | while (j < size1 && !TEST_HARD_REG_BIT (used, regno + j)) | |
2233 | j++; | |
2234 | if (j == size1) | |
2235 | { | |
2236 | /* Mark that this register is in use between its birth | |
2237 | and death insns. */ | |
2238 | post_mark_life (regno, mode, 1, born_index, dead_index); | |
2239 | return regno; | |
2240 | } | |
2bbd3819 | 2241 | #ifndef REG_ALLOC_ORDER |
56b138ae RS |
2242 | /* Skip starting points we know will lose. */ |
2243 | i += j; | |
2bbd3819 | 2244 | #endif |
56b138ae RS |
2245 | } |
2246 | } | |
2bbd3819 | 2247 | |
2bbd3819 RS |
2248 | /* If we are just trying suggested register, we have just tried copy- |
2249 | suggested registers, and there are arithmetic-suggested registers, | |
2250 | try them. */ | |
64e3a413 | 2251 | |
2bbd3819 RS |
2252 | /* If it would be profitable to allocate a call-clobbered register |
2253 | and save and restore it around calls, do that. */ | |
a1ed7bdb JH |
2254 | if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0 |
2255 | && qty_phys_num_sugg[qtyno] != 0) | |
2bbd3819 RS |
2256 | { |
2257 | /* Don't try the copy-suggested regs again. */ | |
a1ed7bdb JH |
2258 | qty_phys_num_copy_sugg[qtyno] = 0; |
2259 | return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1, | |
2bbd3819 RS |
2260 | born_index, dead_index); |
2261 | } | |
2262 | ||
e19f5192 RK |
2263 | /* We need not check to see if the current function has nonlocal |
2264 | labels because we don't put any pseudos that are live over calls in | |
95c37cdb JJ |
2265 | registers in that case. Avoid putting pseudos crossing calls that |
2266 | might throw into call used registers. */ | |
e19f5192 | 2267 | |
2bbd3819 RS |
2268 | if (! accept_call_clobbered |
2269 | && flag_caller_saves | |
2270 | && ! just_try_suggested | |
a1ed7bdb | 2271 | && qty[qtyno].n_calls_crossed != 0 |
95c37cdb | 2272 | && qty[qtyno].n_throwing_calls_crossed == 0 |
a03c6d64 JH |
2273 | && CALLER_SAVE_PROFITABLE (optimize_size ? qty[qtyno].n_refs : qty[qtyno].freq, |
2274 | optimize_size ? qty[qtyno].n_calls_crossed | |
2275 | : qty[qtyno].freq_calls_crossed)) | |
2bbd3819 | 2276 | { |
a1ed7bdb | 2277 | i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index); |
2bbd3819 RS |
2278 | if (i >= 0) |
2279 | caller_save_needed = 1; | |
2280 | return i; | |
2281 | } | |
2282 | return -1; | |
2283 | } | |
2284 | \f | |
2285 | /* Mark that REGNO with machine-mode MODE is live starting from the current | |
cc2902df | 2286 | insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE |
2bbd3819 RS |
2287 | is zero). */ |
2288 | ||
2289 | static void | |
0c20a65f | 2290 | mark_life (int regno, enum machine_mode mode, int life) |
2bbd3819 | 2291 | { |
2bbd3819 | 2292 | if (life) |
09e18274 | 2293 | add_to_hard_reg_set (®s_live, mode, regno); |
2bbd3819 | 2294 | else |
09e18274 | 2295 | remove_from_hard_reg_set (®s_live, mode, regno); |
2bbd3819 RS |
2296 | } |
2297 | ||
2298 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE | |
cc2902df | 2299 | is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) |
2bbd3819 RS |
2300 | to insn number DEATH (exclusive). */ |
2301 | ||
2302 | static void | |
0c20a65f AJ |
2303 | post_mark_life (int regno, enum machine_mode mode, int life, int birth, |
2304 | int death) | |
2bbd3819 | 2305 | { |
49a27995 | 2306 | HARD_REG_SET this_reg; |
2bbd3819 RS |
2307 | |
2308 | CLEAR_HARD_REG_SET (this_reg); | |
09e18274 | 2309 | add_to_hard_reg_set (&this_reg, mode, regno); |
2bbd3819 RS |
2310 | |
2311 | if (life) | |
2312 | while (birth < death) | |
2313 | { | |
2314 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2315 | birth++; | |
2316 | } | |
2317 | else | |
2318 | while (birth < death) | |
2319 | { | |
2320 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2321 | birth++; | |
2322 | } | |
2323 | } | |
2324 | \f | |
3061cc54 RK |
2325 | /* Return the number of alternatives for which the constraint string P |
2326 | indicates that the operand must be equal to operand 0 and that no register | |
2327 | is acceptable. */ | |
2bbd3819 RS |
2328 | |
2329 | static int | |
0c20a65f | 2330 | requires_inout (const char *p) |
2bbd3819 RS |
2331 | { |
2332 | char c; | |
2333 | int found_zero = 0; | |
3061cc54 RK |
2334 | int reg_allowed = 0; |
2335 | int num_matching_alts = 0; | |
97488870 | 2336 | int len; |
2bbd3819 | 2337 | |
dd1b7476 | 2338 | for ( ; (c = *p); p += len) |
97488870 R |
2339 | { |
2340 | len = CONSTRAINT_LEN (c, p); | |
2341 | switch (c) | |
2342 | { | |
2343 | case '=': case '+': case '?': | |
2344 | case '#': case '&': case '!': | |
2345 | case '*': case '%': | |
2346 | case 'm': case '<': case '>': case 'V': case 'o': | |
2347 | case 'E': case 'F': case 'G': case 'H': | |
2348 | case 's': case 'i': case 'n': | |
2349 | case 'I': case 'J': case 'K': case 'L': | |
2350 | case 'M': case 'N': case 'O': case 'P': | |
2351 | case 'X': | |
2352 | /* These don't say anything we care about. */ | |
2353 | break; | |
2bbd3819 | 2354 | |
97488870 R |
2355 | case ',': |
2356 | if (found_zero && ! reg_allowed) | |
2357 | num_matching_alts++; | |
3061cc54 | 2358 | |
97488870 R |
2359 | found_zero = reg_allowed = 0; |
2360 | break; | |
3061cc54 | 2361 | |
97488870 R |
2362 | case '0': |
2363 | found_zero = 1; | |
2364 | break; | |
3061cc54 | 2365 | |
97488870 R |
2366 | case '1': case '2': case '3': case '4': case '5': |
2367 | case '6': case '7': case '8': case '9': | |
2368 | /* Skip the balance of the matching constraint. */ | |
2369 | do | |
2370 | p++; | |
2371 | while (ISDIGIT (*p)); | |
2372 | len = 0; | |
2373 | break; | |
84b72302 | 2374 | |
97488870 R |
2375 | default: |
2376 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS | |
2377 | && !EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
2378 | break; | |
5d3cc252 | 2379 | /* Fall through. */ |
97488870 R |
2380 | case 'p': |
2381 | case 'g': case 'r': | |
2382 | reg_allowed = 1; | |
c2cba7a9 | 2383 | break; |
97488870 R |
2384 | } |
2385 | } | |
2bbd3819 | 2386 | |
3061cc54 RK |
2387 | if (found_zero && ! reg_allowed) |
2388 | num_matching_alts++; | |
2389 | ||
2390 | return num_matching_alts; | |
2bbd3819 RS |
2391 | } |
2392 | \f | |
2393 | void | |
0c20a65f | 2394 | dump_local_alloc (FILE *file) |
2bbd3819 | 2395 | { |
b3694847 | 2396 | int i; |
2bbd3819 RS |
2397 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
2398 | if (reg_renumber[i] != -1) | |
2399 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); | |
2400 | } | |
ef330312 | 2401 | |
ba49cb7b KZ |
2402 | #ifdef STACK_REGS |
2403 | static void | |
2404 | find_stack_regs (void) | |
2405 | { | |
2406 | bitmap stack_regs = BITMAP_ALLOC (NULL); | |
2407 | int i; | |
2408 | HARD_REG_SET stack_hard_regs, used; | |
2409 | basic_block bb; | |
2410 | ||
2411 | /* Any register that MAY be allocated to a register stack (like the | |
2412 | 387) is treated poorly. Each such register is marked as being | |
2413 | live everywhere. This keeps the register allocator and the | |
2414 | subsequent passes from doing anything useful with these values. | |
2415 | ||
2416 | FIXME: This seems like an incredibly poor idea. */ | |
2417 | ||
2418 | CLEAR_HARD_REG_SET (stack_hard_regs); | |
2419 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
2420 | SET_HARD_REG_BIT (stack_hard_regs, i); | |
2421 | ||
2422 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
2423 | { | |
2424 | COPY_HARD_REG_SET (used, reg_class_contents[reg_preferred_class (i)]); | |
2425 | IOR_HARD_REG_SET (used, reg_class_contents[reg_alternate_class (i)]); | |
2426 | AND_HARD_REG_SET (used, stack_hard_regs); | |
2427 | if (!hard_reg_set_empty_p (used)) | |
2428 | bitmap_set_bit (stack_regs, i); | |
2429 | } | |
2430 | ||
2431 | if (dump_file) | |
2432 | bitmap_print (dump_file, stack_regs, "stack regs:", "\n"); | |
2433 | ||
2434 | FOR_EACH_BB (bb) | |
2435 | { | |
2436 | bitmap_ior_into (DF_LIVE_IN (bb), stack_regs); | |
2437 | bitmap_and_into (DF_LIVE_IN (bb), DF_LR_IN (bb)); | |
2438 | bitmap_ior_into (DF_LIVE_OUT (bb), stack_regs); | |
2439 | bitmap_and_into (DF_LIVE_OUT (bb), DF_LR_OUT (bb)); | |
2440 | } | |
2441 | BITMAP_FREE (stack_regs); | |
2442 | } | |
2443 | #endif | |
2444 | ||
ef330312 PB |
2445 | /* Run old register allocator. Return TRUE if we must exit |
2446 | rest_of_compilation upon return. */ | |
c2924966 | 2447 | static unsigned int |
ef330312 PB |
2448 | rest_of_handle_local_alloc (void) |
2449 | { | |
2450 | int rebuild_notes; | |
6fb5fa3c DB |
2451 | int max_regno = max_reg_num (); |
2452 | ||
2453 | df_note_add_problem (); | |
89a95777 | 2454 | |
ba49cb7b KZ |
2455 | if (optimize == 1) |
2456 | { | |
2457 | df_live_add_problem (); | |
2458 | df_live_set_all_dirty (); | |
2459 | } | |
0d475361 PB |
2460 | #ifdef ENABLE_CHECKING |
2461 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
2462 | #endif | |
6fb5fa3c | 2463 | df_analyze (); |
ba49cb7b KZ |
2464 | #ifdef STACK_REGS |
2465 | if (optimize) | |
2466 | find_stack_regs (); | |
2467 | #endif | |
6fb5fa3c DB |
2468 | regstat_init_n_sets_and_refs (); |
2469 | regstat_compute_ri (); | |
2470 | ||
6fb5fa3c DB |
2471 | /* If we are not optimizing, then this is the only place before |
2472 | register allocation where dataflow is done. And that is needed | |
2473 | to generate these warnings. */ | |
2474 | if (warn_clobbered) | |
2475 | generate_setjmp_warnings (); | |
ef330312 PB |
2476 | |
2477 | /* Determine if the current function is a leaf before running reload | |
2478 | since this can impact optimizations done by the prologue and | |
2479 | epilogue thus changing register elimination offsets. */ | |
2480 | current_function_is_leaf = leaf_function_p (); | |
2481 | ||
ef330312 | 2482 | /* And the reg_equiv_memory_loc array. */ |
43b373a2 KH |
2483 | VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); |
2484 | memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, | |
2485 | sizeof (rtx) * max_regno); | |
2486 | reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); | |
ef330312 PB |
2487 | |
2488 | allocate_initial_values (reg_equiv_memory_loc); | |
2489 | ||
6fb5fa3c | 2490 | regclass (get_insns (), max_regno); |
ef330312 PB |
2491 | rebuild_notes = local_alloc (); |
2492 | ||
2493 | /* Local allocation may have turned an indirect jump into a direct | |
2494 | jump. If so, we must rebuild the JUMP_LABEL fields of jumping | |
2495 | instructions. */ | |
2496 | if (rebuild_notes) | |
2497 | { | |
2498 | timevar_push (TV_JUMP); | |
2499 | ||
2500 | rebuild_jump_labels (get_insns ()); | |
2501 | purge_all_dead_edges (); | |
ef330312 PB |
2502 | timevar_pop (TV_JUMP); |
2503 | } | |
2504 | ||
5b4fdb20 | 2505 | if (dump_file && (dump_flags & TDF_DETAILS)) |
ef330312 PB |
2506 | { |
2507 | timevar_push (TV_DUMP); | |
5b4fdb20 | 2508 | dump_flow_info (dump_file, dump_flags); |
ef330312 PB |
2509 | dump_local_alloc (dump_file); |
2510 | timevar_pop (TV_DUMP); | |
2511 | } | |
c2924966 | 2512 | return 0; |
ef330312 PB |
2513 | } |
2514 | ||
8ddbbcae | 2515 | struct rtl_opt_pass pass_local_alloc = |
ef330312 | 2516 | { |
8ddbbcae JH |
2517 | { |
2518 | RTL_PASS, | |
ef330312 PB |
2519 | "lreg", /* name */ |
2520 | NULL, /* gate */ | |
2521 | rest_of_handle_local_alloc, /* execute */ | |
2522 | NULL, /* sub */ | |
2523 | NULL, /* next */ | |
2524 | 0, /* static_pass_number */ | |
2525 | TV_LOCAL_ALLOC, /* tv_id */ | |
2526 | 0, /* properties_required */ | |
2527 | 0, /* properties_provided */ | |
2528 | 0, /* properties_destroyed */ | |
2529 | 0, /* todo_flags_start */ | |
2530 | TODO_dump_func | | |
8ddbbcae JH |
2531 | TODO_ggc_collect /* todo_flags_finish */ |
2532 | } | |
ef330312 PB |
2533 | }; |
2534 |