]>
Commit | Line | Data |
---|---|---|
2bbd3819 | 1 | /* Allocate registers within a basic block, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
58b23af8 | 3 | 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
2bbd3819 | 4 | |
1322177d | 5 | This file is part of GCC. |
2bbd3819 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
2bbd3819 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
2bbd3819 RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
2bbd3819 | 21 | |
2bbd3819 RS |
22 | /* Allocation of hard register numbers to pseudo registers is done in |
23 | two passes. In this pass we consider only regs that are born and | |
24 | die once within one basic block. We do this one basic block at a | |
25 | time. Then the next pass allocates the registers that remain. | |
26 | Two passes are used because this pass uses methods that work only | |
27 | on linear code, but that do a better job than the general methods | |
28 | used in global_alloc, and more quickly too. | |
29 | ||
30 | The assignments made are recorded in the vector reg_renumber | |
31 | whose space is allocated here. The rtl code itself is not altered. | |
32 | ||
33 | We assign each instruction in the basic block a number | |
34 | which is its order from the beginning of the block. | |
35 | Then we can represent the lifetime of a pseudo register with | |
36 | a pair of numbers, and check for conflicts easily. | |
37 | We can record the availability of hard registers with a | |
38 | HARD_REG_SET for each instruction. The HARD_REG_SET | |
39 | contains 0 or 1 for each hard reg. | |
40 | ||
41 | To avoid register shuffling, we tie registers together when one | |
42 | dies by being copied into another, or dies in an instruction that | |
43 | does arithmetic to produce another. The tied registers are | |
44 | allocated as one. Registers with different reg class preferences | |
45 | can never be tied unless the class preferred by one is a subclass | |
46 | of the one preferred by the other. | |
47 | ||
48 | Tying is represented with "quantity numbers". | |
49 | A non-tied register is given a new quantity number. | |
50 | Tied registers have the same quantity number. | |
64e3a413 | 51 | |
2bbd3819 RS |
52 | We have provision to exempt registers, even when they are contained |
53 | within the block, that can be tied to others that are not contained in it. | |
54 | This is so that global_alloc could process them both and tie them then. | |
55 | But this is currently disabled since tying in global_alloc is not | |
56 | yet implemented. */ | |
57 | ||
a300b8d9 JW |
58 | /* Pseudos allocated here can be reallocated by global.c if the hard register |
59 | is used as a spill register. Currently we don't allocate such pseudos | |
6cad67d2 JL |
60 | here if their preferred class is likely to be used by spills. */ |
61 | ||
2bbd3819 | 62 | #include "config.h" |
670ee920 | 63 | #include "system.h" |
4977bab6 ZW |
64 | #include "coretypes.h" |
65 | #include "tm.h" | |
cff9f8d5 | 66 | #include "hard-reg-set.h" |
2bbd3819 | 67 | #include "rtl.h" |
6baf1cc8 | 68 | #include "tm_p.h" |
2bbd3819 RS |
69 | #include "flags.h" |
70 | #include "basic-block.h" | |
71 | #include "regs.h" | |
49ad7cfa | 72 | #include "function.h" |
2bbd3819 | 73 | #include "insn-config.h" |
624a8b3a | 74 | #include "insn-attr.h" |
2bbd3819 RS |
75 | #include "recog.h" |
76 | #include "output.h" | |
2e107e9e | 77 | #include "toplev.h" |
a4d3961a | 78 | #include "except.h" |
902197eb | 79 | #include "integrate.h" |
2bbd3819 RS |
80 | \f |
81 | /* Next quantity number available for allocation. */ | |
82 | ||
83 | static int next_qty; | |
84 | ||
f5143c46 | 85 | /* Information we maintain about each quantity. */ |
a1ed7bdb JH |
86 | struct qty |
87 | { | |
88 | /* The number of refs to quantity Q. */ | |
2bbd3819 | 89 | |
a1ed7bdb | 90 | int n_refs; |
2bbd3819 | 91 | |
b2aec5c0 JH |
92 | /* The frequency of uses of quantity Q. */ |
93 | ||
94 | int freq; | |
95 | ||
a1ed7bdb JH |
96 | /* Insn number (counting from head of basic block) |
97 | where quantity Q was born. -1 if birth has not been recorded. */ | |
2bbd3819 | 98 | |
a1ed7bdb | 99 | int birth; |
2bbd3819 | 100 | |
a1ed7bdb JH |
101 | /* Insn number (counting from head of basic block) |
102 | where given quantity died. Due to the way tying is done, | |
103 | and the fact that we consider in this pass only regs that die but once, | |
104 | a quantity can die only once. Each quantity's life span | |
105 | is a set of consecutive insns. -1 if death has not been recorded. */ | |
2bbd3819 | 106 | |
a1ed7bdb | 107 | int death; |
2bbd3819 | 108 | |
a1ed7bdb JH |
109 | /* Number of words needed to hold the data in given quantity. |
110 | This depends on its machine mode. It is used for these purposes: | |
ba228239 | 111 | 1. It is used in computing the relative importance of qtys, |
a1ed7bdb JH |
112 | which determines the order in which we look for regs for them. |
113 | 2. It is used in rules that prevent tying several registers of | |
114 | different sizes in a way that is geometrically impossible | |
115 | (see combine_regs). */ | |
2bbd3819 | 116 | |
a1ed7bdb | 117 | int size; |
2bbd3819 | 118 | |
a1ed7bdb | 119 | /* Number of times a reg tied to given qty lives across a CALL_INSN. */ |
2bbd3819 | 120 | |
a1ed7bdb | 121 | int n_calls_crossed; |
2bbd3819 | 122 | |
a1ed7bdb JH |
123 | /* The register number of one pseudo register whose reg_qty value is Q. |
124 | This register should be the head of the chain | |
125 | maintained in reg_next_in_qty. */ | |
2bbd3819 | 126 | |
a1ed7bdb | 127 | int first_reg; |
2bbd3819 | 128 | |
a1ed7bdb JH |
129 | /* Reg class contained in (smaller than) the preferred classes of all |
130 | the pseudo regs that are tied in given quantity. | |
131 | This is the preferred class for allocating that quantity. */ | |
132 | ||
133 | enum reg_class min_class; | |
2bbd3819 | 134 | |
a1ed7bdb JH |
135 | /* Register class within which we allocate given qty if we can't get |
136 | its preferred class. */ | |
2bbd3819 | 137 | |
a1ed7bdb | 138 | enum reg_class alternate_class; |
2bbd3819 | 139 | |
a1ed7bdb JH |
140 | /* This holds the mode of the registers that are tied to given qty, |
141 | or VOIDmode if registers with differing modes are tied together. */ | |
2bbd3819 | 142 | |
a1ed7bdb | 143 | enum machine_mode mode; |
2bbd3819 | 144 | |
a1ed7bdb JH |
145 | /* the hard reg number chosen for given quantity, |
146 | or -1 if none was found. */ | |
2bbd3819 | 147 | |
a1ed7bdb | 148 | short phys_reg; |
a1ed7bdb | 149 | }; |
2bbd3819 | 150 | |
a1ed7bdb | 151 | static struct qty *qty; |
2bbd3819 | 152 | |
a1ed7bdb | 153 | /* These fields are kept separately to speedup their clearing. */ |
2bbd3819 | 154 | |
a1ed7bdb JH |
155 | /* We maintain two hard register sets that indicate suggested hard registers |
156 | for each quantity. The first, phys_copy_sugg, contains hard registers | |
157 | that are tied to the quantity by a simple copy. The second contains all | |
158 | hard registers that are tied to the quantity via an arithmetic operation. | |
2bbd3819 | 159 | |
a1ed7bdb JH |
160 | The former register set is given priority for allocation. This tends to |
161 | eliminate copy insns. */ | |
2bbd3819 | 162 | |
a1ed7bdb JH |
163 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
164 | copy insns. */ | |
2bbd3819 | 165 | |
a1ed7bdb | 166 | static HARD_REG_SET *qty_phys_copy_sugg; |
2bbd3819 | 167 | |
a1ed7bdb JH |
168 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
169 | arithmetic insns. */ | |
170 | ||
171 | static HARD_REG_SET *qty_phys_sugg; | |
172 | ||
173 | /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ | |
2bbd3819 | 174 | |
a1ed7bdb | 175 | static short *qty_phys_num_copy_sugg; |
0f64b8f6 | 176 | |
a1ed7bdb | 177 | /* Element Q is the number of suggested registers in qty_phys_sugg. */ |
0f64b8f6 | 178 | |
a1ed7bdb | 179 | static short *qty_phys_num_sugg; |
2bbd3819 | 180 | |
2bbd3819 RS |
181 | /* If (REG N) has been assigned a quantity number, is a register number |
182 | of another register assigned the same quantity number, or -1 for the | |
a1ed7bdb | 183 | end of the chain. qty->first_reg point to the head of this chain. */ |
2bbd3819 | 184 | |
aabf56ce | 185 | static int *reg_next_in_qty; |
2bbd3819 RS |
186 | |
187 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg | |
188 | if it is >= 0, | |
189 | of -1 if this register cannot be allocated by local-alloc, | |
190 | or -2 if not known yet. | |
191 | ||
192 | Note that if we see a use or death of pseudo register N with | |
193 | reg_qty[N] == -2, register N must be local to the current block. If | |
194 | it were used in more than one block, we would have reg_qty[N] == -1. | |
195 | This relies on the fact that if reg_basic_block[N] is >= 0, register N | |
196 | will not appear in any other block. We save a considerable number of | |
197 | tests by exploiting this. | |
198 | ||
199 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not | |
200 | be referenced. */ | |
201 | ||
202 | static int *reg_qty; | |
203 | ||
204 | /* The offset (in words) of register N within its quantity. | |
205 | This can be nonzero if register N is SImode, and has been tied | |
206 | to a subreg of a DImode register. */ | |
207 | ||
208 | static char *reg_offset; | |
209 | ||
210 | /* Vector of substitutions of register numbers, | |
211 | used to map pseudo regs into hardware regs. | |
212 | This is set up as a result of register allocation. | |
213 | Element N is the hard reg assigned to pseudo reg N, | |
214 | or is -1 if no hard reg was assigned. | |
215 | If N is a hard reg number, element N is N. */ | |
216 | ||
217 | short *reg_renumber; | |
218 | ||
219 | /* Set of hard registers live at the current point in the scan | |
220 | of the instructions in a basic block. */ | |
221 | ||
222 | static HARD_REG_SET regs_live; | |
223 | ||
224 | /* Each set of hard registers indicates registers live at a particular | |
225 | point in the basic block. For N even, regs_live_at[N] says which | |
226 | hard registers are needed *after* insn N/2 (i.e., they may not | |
227 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. | |
228 | ||
229 | If an object is to conflict with the inputs of insn J but not the | |
230 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, | |
231 | if it is to conflict with the outputs of insn J but not the inputs of | |
232 | insn J + 1, it is said to die at index J*2 + 1. */ | |
233 | ||
234 | static HARD_REG_SET *regs_live_at; | |
235 | ||
236 | /* Communicate local vars `insn_number' and `insn' | |
237 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ | |
238 | static int this_insn_number; | |
239 | static rtx this_insn; | |
240 | ||
bf6d9fd7 JW |
241 | struct equivalence |
242 | { | |
243 | /* Set when an attempt should be made to replace a register | |
5ca9299f | 244 | with the associated src_p entry. */ |
bf6d9fd7 JW |
245 | |
246 | char replace; | |
247 | ||
248 | /* Set when a REG_EQUIV note is found or created. Use to | |
249 | keep track of what memory accesses might be created later, | |
250 | e.g. by reload. */ | |
251 | ||
252 | rtx replacement; | |
68342d36 | 253 | |
5ca9299f | 254 | rtx *src_p; |
c25a4c25 | 255 | |
bf6d9fd7 JW |
256 | /* Loop depth is used to recognize equivalences which appear |
257 | to be present within the same loop (or in an inner loop). */ | |
258 | ||
259 | int loop_depth; | |
260 | ||
261 | /* The list of each instruction which initializes this register. */ | |
262 | ||
263 | rtx init_insns; | |
264 | }; | |
265 | ||
266 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
267 | structure for that register. */ | |
268 | ||
269 | static struct equivalence *reg_equiv; | |
135eb61c | 270 | |
3f1b9b1b JL |
271 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
272 | static int recorded_label_ref; | |
273 | ||
0c20a65f AJ |
274 | static void alloc_qty (int, enum machine_mode, int, int); |
275 | static void validate_equiv_mem_from_store (rtx, rtx, void *); | |
276 | static int validate_equiv_mem (rtx, rtx, rtx); | |
277 | static int equiv_init_varies_p (rtx); | |
278 | static int equiv_init_movable_p (rtx, int); | |
279 | static int contains_replace_regs (rtx); | |
280 | static int memref_referenced_p (rtx, rtx); | |
281 | static int memref_used_between_p (rtx, rtx, rtx); | |
282 | static void update_equiv_regs (void); | |
283 | static void no_equiv (rtx, rtx, void *); | |
284 | static void block_alloc (int); | |
285 | static int qty_sugg_compare (int, int); | |
286 | static int qty_sugg_compare_1 (const void *, const void *); | |
287 | static int qty_compare (int, int); | |
288 | static int qty_compare_1 (const void *, const void *); | |
289 | static int combine_regs (rtx, rtx, int, int, rtx, int); | |
290 | static int reg_meets_class_p (int, enum reg_class); | |
291 | static void update_qty_class (int, int); | |
292 | static void reg_is_set (rtx, rtx, void *); | |
293 | static void reg_is_born (rtx, int); | |
294 | static void wipe_dead_reg (rtx, int); | |
295 | static int find_free_reg (enum reg_class, enum machine_mode, int, int, int, | |
296 | int, int); | |
297 | static void mark_life (int, enum machine_mode, int); | |
298 | static void post_mark_life (int, enum machine_mode, int, int, int); | |
299 | static int no_conflict_p (rtx, rtx, rtx); | |
300 | static int requires_inout (const char *); | |
2bbd3819 RS |
301 | \f |
302 | /* Allocate a new quantity (new within current basic block) | |
303 | for register number REGNO which is born at index BIRTH | |
304 | within the block. MODE and SIZE are info on reg REGNO. */ | |
305 | ||
306 | static void | |
0c20a65f | 307 | alloc_qty (int regno, enum machine_mode mode, int size, int birth) |
2bbd3819 | 308 | { |
b3694847 | 309 | int qtyno = next_qty++; |
2bbd3819 | 310 | |
a1ed7bdb | 311 | reg_qty[regno] = qtyno; |
2bbd3819 RS |
312 | reg_offset[regno] = 0; |
313 | reg_next_in_qty[regno] = -1; | |
314 | ||
a1ed7bdb JH |
315 | qty[qtyno].first_reg = regno; |
316 | qty[qtyno].size = size; | |
317 | qty[qtyno].mode = mode; | |
318 | qty[qtyno].birth = birth; | |
319 | qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno); | |
320 | qty[qtyno].min_class = reg_preferred_class (regno); | |
321 | qty[qtyno].alternate_class = reg_alternate_class (regno); | |
322 | qty[qtyno].n_refs = REG_N_REFS (regno); | |
b2aec5c0 | 323 | qty[qtyno].freq = REG_FREQ (regno); |
2bbd3819 RS |
324 | } |
325 | \f | |
2bbd3819 RS |
326 | /* Main entry point of this file. */ |
327 | ||
3f1b9b1b | 328 | int |
0c20a65f | 329 | local_alloc (void) |
2bbd3819 | 330 | { |
e0082a72 | 331 | int i; |
2bbd3819 | 332 | int max_qty; |
e0082a72 | 333 | basic_block b; |
2bbd3819 | 334 | |
3f1b9b1b JL |
335 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
336 | that we know if the jump optimizer needs to be rerun. */ | |
337 | recorded_label_ref = 0; | |
338 | ||
2bbd3819 RS |
339 | /* Leaf functions and non-leaf functions have different needs. |
340 | If defined, let the machine say what kind of ordering we | |
341 | should use. */ | |
342 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC | |
343 | ORDER_REGS_FOR_LOCAL_ALLOC; | |
344 | #endif | |
345 | ||
346 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected | |
347 | registers. */ | |
1540f9eb JH |
348 | if (optimize) |
349 | update_equiv_regs (); | |
2bbd3819 RS |
350 | |
351 | /* This sets the maximum number of quantities we can have. Quantity | |
34f89b5f BS |
352 | numbers start at zero and we can have one for each pseudo. */ |
353 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER); | |
2bbd3819 RS |
354 | |
355 | /* Allocate vectors of temporary data. | |
356 | See the declarations of these variables, above, | |
357 | for what they mean. */ | |
358 | ||
703ad42b KG |
359 | qty = xmalloc (max_qty * sizeof (struct qty)); |
360 | qty_phys_copy_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET)); | |
361 | qty_phys_num_copy_sugg = xmalloc (max_qty * sizeof (short)); | |
362 | qty_phys_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET)); | |
363 | qty_phys_num_sugg = xmalloc (max_qty * sizeof (short)); | |
2bbd3819 | 364 | |
703ad42b KG |
365 | reg_qty = xmalloc (max_regno * sizeof (int)); |
366 | reg_offset = xmalloc (max_regno * sizeof (char)); | |
367 | reg_next_in_qty = xmalloc (max_regno * sizeof (int)); | |
2bbd3819 | 368 | |
2bbd3819 RS |
369 | /* Determine which pseudo-registers can be allocated by local-alloc. |
370 | In general, these are the registers used only in a single block and | |
611bbf2a | 371 | which only die once. |
2bbd3819 RS |
372 | |
373 | We need not be concerned with which block actually uses the register | |
374 | since we will never see it outside that block. */ | |
375 | ||
376 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
377 | { | |
611bbf2a | 378 | if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1) |
2bbd3819 RS |
379 | reg_qty[i] = -2; |
380 | else | |
381 | reg_qty[i] = -1; | |
382 | } | |
383 | ||
384 | /* Force loop below to initialize entire quantity array. */ | |
385 | next_qty = max_qty; | |
386 | ||
387 | /* Allocate each block's local registers, block by block. */ | |
388 | ||
e0082a72 | 389 | FOR_EACH_BB (b) |
2bbd3819 RS |
390 | { |
391 | /* NEXT_QTY indicates which elements of the `qty_...' | |
392 | vectors might need to be initialized because they were used | |
393 | for the previous block; it is set to the entire array before | |
394 | block 0. Initialize those, with explicit loop if there are few, | |
395 | else with bzero and bcopy. Do not initialize vectors that are | |
396 | explicit set by `alloc_qty'. */ | |
397 | ||
398 | if (next_qty < 6) | |
399 | { | |
400 | for (i = 0; i < next_qty; i++) | |
401 | { | |
2bbd3819 | 402 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); |
51b86d8b | 403 | qty_phys_num_copy_sugg[i] = 0; |
2bbd3819 | 404 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); |
51b86d8b | 405 | qty_phys_num_sugg[i] = 0; |
2bbd3819 RS |
406 | } |
407 | } | |
408 | else | |
409 | { | |
410 | #define CLEAR(vector) \ | |
703ad42b | 411 | memset ((vector), 0, (sizeof (*(vector))) * next_qty); |
2bbd3819 | 412 | |
2bbd3819 | 413 | CLEAR (qty_phys_copy_sugg); |
51b86d8b | 414 | CLEAR (qty_phys_num_copy_sugg); |
2bbd3819 | 415 | CLEAR (qty_phys_sugg); |
51b86d8b | 416 | CLEAR (qty_phys_num_sugg); |
2bbd3819 RS |
417 | } |
418 | ||
419 | next_qty = 0; | |
420 | ||
e0082a72 | 421 | block_alloc (b->index); |
2bbd3819 | 422 | } |
83cbe7e4 | 423 | |
a1ed7bdb | 424 | free (qty); |
75c6bd46 RH |
425 | free (qty_phys_copy_sugg); |
426 | free (qty_phys_num_copy_sugg); | |
427 | free (qty_phys_sugg); | |
e7749837 | 428 | free (qty_phys_num_sugg); |
75c6bd46 | 429 | |
83cbe7e4 RH |
430 | free (reg_qty); |
431 | free (reg_offset); | |
432 | free (reg_next_in_qty); | |
75c6bd46 | 433 | |
3f1b9b1b | 434 | return recorded_label_ref; |
2bbd3819 RS |
435 | } |
436 | \f | |
2bbd3819 RS |
437 | /* Used for communication between the following two functions: contains |
438 | a MEM that we wish to ensure remains unchanged. */ | |
439 | static rtx equiv_mem; | |
440 | ||
441 | /* Set nonzero if EQUIV_MEM is modified. */ | |
442 | static int equiv_mem_modified; | |
443 | ||
444 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
445 | Called via note_stores. */ | |
446 | ||
447 | static void | |
0c20a65f AJ |
448 | validate_equiv_mem_from_store (rtx dest, rtx set ATTRIBUTE_UNUSED, |
449 | void *data ATTRIBUTE_UNUSED) | |
2bbd3819 RS |
450 | { |
451 | if ((GET_CODE (dest) == REG | |
452 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
453 | || (GET_CODE (dest) == MEM | |
9ae8ffe7 | 454 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) |
2bbd3819 RS |
455 | equiv_mem_modified = 1; |
456 | } | |
457 | ||
458 | /* Verify that no store between START and the death of REG invalidates | |
459 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
460 | by storing into an overlapping memory location, or with a non-const | |
461 | CALL_INSN. | |
462 | ||
463 | Return 1 if MEMREF remains valid. */ | |
464 | ||
465 | static int | |
0c20a65f | 466 | validate_equiv_mem (rtx start, rtx reg, rtx memref) |
2bbd3819 RS |
467 | { |
468 | rtx insn; | |
469 | rtx note; | |
470 | ||
471 | equiv_mem = memref; | |
472 | equiv_mem_modified = 0; | |
473 | ||
474 | /* If the memory reference has side effects or is volatile, it isn't a | |
475 | valid equivalence. */ | |
476 | if (side_effects_p (memref)) | |
477 | return 0; | |
478 | ||
479 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
480 | { | |
2c3c49de | 481 | if (! INSN_P (insn)) |
2bbd3819 RS |
482 | continue; |
483 | ||
484 | if (find_reg_note (insn, REG_DEAD, reg)) | |
485 | return 1; | |
486 | ||
487 | if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) | |
24a28584 | 488 | && ! CONST_OR_PURE_CALL_P (insn)) |
2bbd3819 RS |
489 | return 0; |
490 | ||
84832317 | 491 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); |
2bbd3819 RS |
492 | |
493 | /* If a register mentioned in MEMREF is modified via an | |
494 | auto-increment, we lose the equivalence. Do the same if one | |
495 | dies; although we could extend the life, it doesn't seem worth | |
496 | the trouble. */ | |
497 | ||
498 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
499 | if ((REG_NOTE_KIND (note) == REG_INC | |
500 | || REG_NOTE_KIND (note) == REG_DEAD) | |
501 | && GET_CODE (XEXP (note, 0)) == REG | |
502 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
503 | return 0; | |
504 | } | |
505 | ||
506 | return 0; | |
507 | } | |
a1729519 | 508 | |
bf6d9fd7 JW |
509 | /* Returns zero if X is known to be invariant. */ |
510 | ||
511 | static int | |
0c20a65f | 512 | equiv_init_varies_p (rtx x) |
bf6d9fd7 | 513 | { |
b3694847 SS |
514 | RTX_CODE code = GET_CODE (x); |
515 | int i; | |
516 | const char *fmt; | |
bf6d9fd7 JW |
517 | |
518 | switch (code) | |
519 | { | |
520 | case MEM: | |
521 | return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
522 | ||
523 | case QUEUED: | |
524 | return 1; | |
525 | ||
526 | case CONST: | |
527 | case CONST_INT: | |
528 | case CONST_DOUBLE: | |
69ef87e2 | 529 | case CONST_VECTOR: |
bf6d9fd7 JW |
530 | case SYMBOL_REF: |
531 | case LABEL_REF: | |
532 | return 0; | |
533 | ||
534 | case REG: | |
e38fe8e0 | 535 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); |
bf6d9fd7 JW |
536 | |
537 | case ASM_OPERANDS: | |
538 | if (MEM_VOLATILE_P (x)) | |
539 | return 1; | |
540 | ||
541 | /* FALLTHROUGH */ | |
542 | ||
543 | default: | |
544 | break; | |
545 | } | |
546 | ||
547 | fmt = GET_RTX_FORMAT (code); | |
548 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
549 | if (fmt[i] == 'e') | |
550 | { | |
551 | if (equiv_init_varies_p (XEXP (x, i))) | |
552 | return 1; | |
553 | } | |
554 | else if (fmt[i] == 'E') | |
555 | { | |
556 | int j; | |
557 | for (j = 0; j < XVECLEN (x, i); j++) | |
558 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
559 | return 1; | |
560 | } | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
cc2902df | 565 | /* Returns nonzero if X (used to initialize register REGNO) is movable. |
bf6d9fd7 JW |
566 | X is only movable if the registers it uses have equivalent initializations |
567 | which appear to be within the same loop (or in an inner loop) and movable | |
568 | or if they are not candidates for local_alloc and don't vary. */ | |
a1729519 JW |
569 | |
570 | static int | |
0c20a65f | 571 | equiv_init_movable_p (rtx x, int regno) |
bf6d9fd7 JW |
572 | { |
573 | int i, j; | |
574 | const char *fmt; | |
575 | enum rtx_code code = GET_CODE (x); | |
576 | ||
577 | switch (code) | |
578 | { | |
579 | case SET: | |
580 | return equiv_init_movable_p (SET_SRC (x), regno); | |
581 | ||
d9068c61 | 582 | case CC0: |
bf6d9fd7 JW |
583 | case CLOBBER: |
584 | return 0; | |
585 | ||
586 | case PRE_INC: | |
587 | case PRE_DEC: | |
588 | case POST_INC: | |
589 | case POST_DEC: | |
590 | case PRE_MODIFY: | |
591 | case POST_MODIFY: | |
592 | return 0; | |
593 | ||
594 | case REG: | |
595 | return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth | |
596 | && reg_equiv[REGNO (x)].replace) | |
e38fe8e0 | 597 | || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0)); |
bf6d9fd7 JW |
598 | |
599 | case UNSPEC_VOLATILE: | |
600 | return 0; | |
601 | ||
602 | case ASM_OPERANDS: | |
603 | if (MEM_VOLATILE_P (x)) | |
604 | return 0; | |
605 | ||
606 | /* FALLTHROUGH */ | |
607 | ||
608 | default: | |
609 | break; | |
610 | } | |
611 | ||
612 | fmt = GET_RTX_FORMAT (code); | |
613 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
614 | switch (fmt[i]) | |
615 | { | |
616 | case 'e': | |
617 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
618 | return 0; | |
619 | break; | |
620 | case 'E': | |
621 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
622 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
623 | return 0; | |
624 | break; | |
625 | } | |
626 | ||
627 | return 1; | |
628 | } | |
629 | ||
630 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */ | |
631 | ||
632 | static int | |
0c20a65f | 633 | contains_replace_regs (rtx x) |
a1729519 JW |
634 | { |
635 | int i, j; | |
6f7d635c | 636 | const char *fmt; |
a1729519 JW |
637 | enum rtx_code code = GET_CODE (x); |
638 | ||
639 | switch (code) | |
640 | { | |
641 | case CONST_INT: | |
642 | case CONST: | |
643 | case LABEL_REF: | |
644 | case SYMBOL_REF: | |
645 | case CONST_DOUBLE: | |
69ef87e2 | 646 | case CONST_VECTOR: |
a1729519 JW |
647 | case PC: |
648 | case CC0: | |
649 | case HIGH: | |
a1729519 JW |
650 | return 0; |
651 | ||
652 | case REG: | |
bf6d9fd7 | 653 | return reg_equiv[REGNO (x)].replace; |
1d300e19 KG |
654 | |
655 | default: | |
656 | break; | |
a1729519 JW |
657 | } |
658 | ||
659 | fmt = GET_RTX_FORMAT (code); | |
660 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
661 | switch (fmt[i]) | |
662 | { | |
663 | case 'e': | |
bf6d9fd7 | 664 | if (contains_replace_regs (XEXP (x, i))) |
a1729519 JW |
665 | return 1; |
666 | break; | |
667 | case 'E': | |
668 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
bf6d9fd7 | 669 | if (contains_replace_regs (XVECEXP (x, i, j))) |
a1729519 JW |
670 | return 1; |
671 | break; | |
672 | } | |
673 | ||
674 | return 0; | |
675 | } | |
2bbd3819 RS |
676 | \f |
677 | /* TRUE if X references a memory location that would be affected by a store | |
678 | to MEMREF. */ | |
679 | ||
680 | static int | |
0c20a65f | 681 | memref_referenced_p (rtx memref, rtx x) |
2bbd3819 RS |
682 | { |
683 | int i, j; | |
6f7d635c | 684 | const char *fmt; |
2bbd3819 RS |
685 | enum rtx_code code = GET_CODE (x); |
686 | ||
687 | switch (code) | |
688 | { | |
2bbd3819 RS |
689 | case CONST_INT: |
690 | case CONST: | |
691 | case LABEL_REF: | |
692 | case SYMBOL_REF: | |
693 | case CONST_DOUBLE: | |
69ef87e2 | 694 | case CONST_VECTOR: |
2bbd3819 RS |
695 | case PC: |
696 | case CC0: | |
697 | case HIGH: | |
698 | case LO_SUM: | |
699 | return 0; | |
700 | ||
c25a4c25 | 701 | case REG: |
bf6d9fd7 | 702 | return (reg_equiv[REGNO (x)].replacement |
3298a1b1 | 703 | && memref_referenced_p (memref, |
bf6d9fd7 | 704 | reg_equiv[REGNO (x)].replacement)); |
c25a4c25 | 705 | |
2bbd3819 | 706 | case MEM: |
9ae8ffe7 | 707 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) |
2bbd3819 RS |
708 | return 1; |
709 | break; | |
710 | ||
711 | case SET: | |
712 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
713 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
714 | if (GET_CODE (SET_DEST (x)) == MEM) | |
715 | { | |
716 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
717 | return 1; | |
718 | } | |
719 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
720 | return 1; | |
721 | ||
722 | return memref_referenced_p (memref, SET_SRC (x)); | |
64e3a413 | 723 | |
e9a25f70 JL |
724 | default: |
725 | break; | |
2bbd3819 RS |
726 | } |
727 | ||
728 | fmt = GET_RTX_FORMAT (code); | |
729 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
730 | switch (fmt[i]) | |
731 | { | |
732 | case 'e': | |
733 | if (memref_referenced_p (memref, XEXP (x, i))) | |
734 | return 1; | |
735 | break; | |
736 | case 'E': | |
737 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
738 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
739 | return 1; | |
740 | break; | |
741 | } | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
746 | /* TRUE if some insn in the range (START, END] references a memory location | |
747 | that would be affected by a store to MEMREF. */ | |
748 | ||
749 | static int | |
0c20a65f | 750 | memref_used_between_p (rtx memref, rtx start, rtx end) |
2bbd3819 RS |
751 | { |
752 | rtx insn; | |
753 | ||
754 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
755 | insn = NEXT_INSN (insn)) | |
2c3c49de | 756 | if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn))) |
2bbd3819 RS |
757 | return 1; |
758 | ||
759 | return 0; | |
760 | } | |
761 | \f | |
2b49ee39 | 762 | /* Return nonzero if the rtx X is invariant over the current function. */ |
1eaea054 RH |
763 | /* ??? Actually, the places this is used in reload expect exactly what |
764 | is tested here, and not everything that is function invariant. In | |
765 | particular, the frame pointer and arg pointer are special cased; | |
766 | pic_offset_table_rtx is not, and this will cause aborts when we | |
767 | go to spill these things to memory. */ | |
768 | ||
2b49ee39 | 769 | int |
0c20a65f | 770 | function_invariant_p (rtx x) |
2b49ee39 R |
771 | { |
772 | if (CONSTANT_P (x)) | |
773 | return 1; | |
774 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
775 | return 1; | |
776 | if (GET_CODE (x) == PLUS | |
777 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
778 | && CONSTANT_P (XEXP (x, 1))) | |
779 | return 1; | |
780 | return 0; | |
781 | } | |
782 | ||
2bbd3819 RS |
783 | /* Find registers that are equivalent to a single value throughout the |
784 | compilation (either because they can be referenced in memory or are set once | |
785 | from a single constant). Lower their priority for a register. | |
786 | ||
787 | If such a register is only referenced once, try substituting its value | |
788 | into the using insn. If it succeeds, we can eliminate the register | |
789 | completely. */ | |
790 | ||
791 | static void | |
0c20a65f | 792 | update_equiv_regs (void) |
2bbd3819 | 793 | { |
2bbd3819 | 794 | rtx insn; |
e0082a72 | 795 | basic_block bb; |
bf6d9fd7 | 796 | int loop_depth; |
25e4379f MM |
797 | regset_head cleared_regs; |
798 | int clear_regnos = 0; | |
2bbd3819 | 799 | |
703ad42b | 800 | reg_equiv = xcalloc (max_regno, sizeof *reg_equiv); |
25e4379f | 801 | INIT_REG_SET (&cleared_regs); |
2bbd3819 RS |
802 | |
803 | init_alias_analysis (); | |
804 | ||
2bbd3819 RS |
805 | /* Scan the insns and find which registers have equivalences. Do this |
806 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
807 | a register can be set below its use. */ | |
e0082a72 | 808 | FOR_EACH_BB (bb) |
2bbd3819 | 809 | { |
2ab0437e | 810 | loop_depth = bb->loop_depth; |
2bbd3819 | 811 | |
a813c111 SB |
812 | for (insn = BB_HEAD (bb); |
813 | insn != NEXT_INSN (BB_END (bb)); | |
814 | insn = NEXT_INSN (insn)) | |
2bbd3819 | 815 | { |
2ab0437e JH |
816 | rtx note; |
817 | rtx set; | |
818 | rtx dest, src; | |
819 | int regno; | |
2bbd3819 | 820 | |
2ab0437e JH |
821 | if (! INSN_P (insn)) |
822 | continue; | |
135eb61c | 823 | |
2ab0437e JH |
824 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
825 | if (REG_NOTE_KIND (note) == REG_INC) | |
826 | no_equiv (XEXP (note, 0), note, NULL); | |
135eb61c | 827 | |
2ab0437e | 828 | set = single_set (insn); |
135eb61c | 829 | |
2ab0437e JH |
830 | /* If this insn contains more (or less) than a single SET, |
831 | only mark all destinations as having no known equivalence. */ | |
832 | if (set == 0) | |
135eb61c | 833 | { |
2ab0437e JH |
834 | note_stores (PATTERN (insn), no_equiv, NULL); |
835 | continue; | |
135eb61c | 836 | } |
2ab0437e JH |
837 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
838 | { | |
839 | int i; | |
135eb61c | 840 | |
2ab0437e JH |
841 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
842 | { | |
843 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
844 | if (part != set) | |
845 | note_stores (part, no_equiv, NULL); | |
846 | } | |
847 | } | |
2bbd3819 | 848 | |
2ab0437e JH |
849 | dest = SET_DEST (set); |
850 | src = SET_SRC (set); | |
851 | ||
852 | /* If this sets a MEM to the contents of a REG that is only used | |
853 | in a single basic block, see if the register is always equivalent | |
854 | to that memory location and if moving the store from INSN to the | |
855 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
856 | initializing insn. | |
857 | ||
858 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
859 | REG_EQUIV is likely more useful than the one we are adding. | |
860 | ||
861 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
862 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
863 | optimization may move the set of this register immediately before | |
864 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
865 | the mention in the REG_EQUIV note would be to an uninitialized | |
866 | pseudo. */ | |
867 | /* ????? This test isn't good enough; we might see a MEM with a use of | |
868 | a pseudo register before we see its setting insn that will cause | |
869 | reg_equiv[].replace for that pseudo to be set. | |
870 | Equivalences to MEMs should be made in another pass, after the | |
871 | reg_equiv[].replace information has been gathered. */ | |
872 | ||
873 | if (GET_CODE (dest) == MEM && GET_CODE (src) == REG | |
874 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
875 | && REG_BASIC_BLOCK (regno) >= 0 | |
876 | && REG_N_SETS (regno) == 1 | |
877 | && reg_equiv[regno].init_insns != 0 | |
878 | && reg_equiv[regno].init_insns != const0_rtx | |
879 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
880 | REG_EQUIV, NULL_RTX) | |
881 | && ! contains_replace_regs (XEXP (dest, 0))) | |
882 | { | |
883 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
884 | if (validate_equiv_mem (init_insn, src, dest) | |
885 | && ! memref_used_between_p (dest, init_insn, insn)) | |
886 | REG_NOTES (init_insn) | |
887 | = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn)); | |
888 | } | |
2bbd3819 | 889 | |
2ab0437e JH |
890 | /* We only handle the case of a pseudo register being set |
891 | once, or always to the same value. */ | |
892 | /* ??? The mn10200 port breaks if we add equivalences for | |
893 | values that need an ADDRESS_REGS register and set them equivalent | |
894 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
895 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
896 | calculate_needs, but we traditionally work around this problem | |
897 | here by rejecting equivalences when the destination is in a register | |
898 | that's likely spilled. This is fragile, of course, since the | |
899 | preferred class of a pseudo depends on all instructions that set | |
900 | or use it. */ | |
901 | ||
902 | if (GET_CODE (dest) != REG | |
903 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
904 | || reg_equiv[regno].init_insns == const0_rtx | |
905 | || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) | |
906 | && GET_CODE (src) == MEM)) | |
907 | { | |
4d6922ee | 908 | /* This might be setting a SUBREG of a pseudo, a pseudo that is |
2ab0437e JH |
909 | also set somewhere else to a constant. */ |
910 | note_stores (set, no_equiv, NULL); | |
911 | continue; | |
912 | } | |
913 | ||
914 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
915 | ||
916 | /* cse sometimes generates function invariants, but doesn't put a | |
917 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3d238248 JJ |
918 | there's no point creating it earlier than here. */ |
919 | if (! note && ! rtx_varies_p (src, 0)) | |
920 | note = set_unique_reg_note (insn, REG_EQUAL, src); | |
2ab0437e JH |
921 | |
922 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
923 | since it represents a function call */ | |
924 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
925 | note = NULL_RTX; | |
926 | ||
927 | if (REG_N_SETS (regno) != 1 | |
928 | && (! note | |
929 | || rtx_varies_p (XEXP (note, 0), 0) | |
930 | || (reg_equiv[regno].replacement | |
931 | && ! rtx_equal_p (XEXP (note, 0), | |
932 | reg_equiv[regno].replacement)))) | |
933 | { | |
934 | no_equiv (dest, set, NULL); | |
935 | continue; | |
936 | } | |
937 | /* Record this insn as initializing this register. */ | |
938 | reg_equiv[regno].init_insns | |
939 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
940 | ||
941 | /* If this register is known to be equal to a constant, record that | |
942 | it is always equivalent to the constant. */ | |
943 | if (note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
944 | PUT_MODE (note, (enum machine_mode) REG_EQUIV); | |
945 | ||
946 | /* If this insn introduces a "constant" register, decrease the priority | |
947 | of that register. Record this insn if the register is only used once | |
948 | more and the equivalence value is the same as our source. | |
949 | ||
950 | The latter condition is checked for two reasons: First, it is an | |
951 | indication that it may be more efficient to actually emit the insn | |
952 | as written (if no registers are available, reload will substitute | |
953 | the equivalence). Secondly, it avoids problems with any registers | |
954 | dying in this insn whose death notes would be missed. | |
955 | ||
956 | If we don't have a REG_EQUIV note, see if this insn is loading | |
957 | a register used only in one basic block from a MEM. If so, and the | |
958 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
959 | note. */ | |
960 | ||
961 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
962 | ||
963 | if (note == 0 && REG_BASIC_BLOCK (regno) >= 0 | |
964 | && GET_CODE (SET_SRC (set)) == MEM | |
965 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
966 | REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set), | |
967 | REG_NOTES (insn)); | |
968 | ||
969 | if (note) | |
68342d36 | 970 | { |
2ab0437e JH |
971 | int regno = REGNO (dest); |
972 | ||
973 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
974 | We might end up substituting the LABEL_REF for uses of the | |
975 | pseudo here or later. That kind of transformation may turn an | |
976 | indirect jump into a direct jump, in which case we must rerun the | |
977 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
978 | if (GET_CODE (XEXP (note, 0)) == LABEL_REF | |
979 | || (GET_CODE (XEXP (note, 0)) == CONST | |
980 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
981 | && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) | |
982 | == LABEL_REF))) | |
983 | recorded_label_ref = 1; | |
984 | ||
985 | reg_equiv[regno].replacement = XEXP (note, 0); | |
5ca9299f | 986 | reg_equiv[regno].src_p = &SET_SRC (set); |
2ab0437e JH |
987 | reg_equiv[regno].loop_depth = loop_depth; |
988 | ||
989 | /* Don't mess with things live during setjmp. */ | |
990 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
991 | { | |
992 | /* Note that the statement below does not affect the priority | |
993 | in local-alloc! */ | |
994 | REG_LIVE_LENGTH (regno) *= 2; | |
995 | ||
996 | ||
997 | /* If the register is referenced exactly twice, meaning it is | |
998 | set once and used once, indicate that the reference may be | |
999 | replaced by the equivalence we computed above. Do this | |
1000 | even if the register is only used in one block so that | |
1001 | dependencies can be handled where the last register is | |
1002 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
1003 | and to reduce the number of registers alive across | |
1004 | calls. */ | |
1005 | ||
1006 | if (REG_N_REFS (regno) == 2 | |
1007 | && (rtx_equal_p (XEXP (note, 0), src) | |
1008 | || ! equiv_init_varies_p (src)) | |
1009 | && GET_CODE (insn) == INSN | |
1010 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
1011 | reg_equiv[regno].replace = 1; | |
1012 | } | |
68342d36 | 1013 | } |
2bbd3819 RS |
1014 | } |
1015 | } | |
1016 | ||
2e1253f3 ILT |
1017 | /* Now scan all regs killed in an insn to see if any of them are |
1018 | registers only used that once. If so, see if we can replace the | |
1019 | reference with the equivalent from. If we can, delete the | |
1020 | initializing reference and this register will go away. If we | |
4d6922ee | 1021 | can't replace the reference, and the initializing reference is |
bf6d9fd7 JW |
1022 | within the same loop (or in an inner loop), then move the register |
1023 | initialization just before the use, so that they are in the same | |
2ab0437e | 1024 | basic block. */ |
e0082a72 | 1025 | FOR_EACH_BB_REVERSE (bb) |
2bbd3819 | 1026 | { |
2ab0437e | 1027 | loop_depth = bb->loop_depth; |
a813c111 SB |
1028 | for (insn = BB_END (bb); |
1029 | insn != PREV_INSN (BB_HEAD (bb)); | |
1030 | insn = PREV_INSN (insn)) | |
2e1253f3 | 1031 | { |
2ab0437e JH |
1032 | rtx link; |
1033 | ||
1034 | if (! INSN_P (insn)) | |
1035 | continue; | |
1036 | ||
1037 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
2e1253f3 | 1038 | { |
2ab0437e JH |
1039 | if (REG_NOTE_KIND (link) == REG_DEAD |
1040 | /* Make sure this insn still refers to the register. */ | |
1041 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
2e1253f3 | 1042 | { |
2ab0437e JH |
1043 | int regno = REGNO (XEXP (link, 0)); |
1044 | rtx equiv_insn; | |
1045 | ||
1046 | if (! reg_equiv[regno].replace | |
1047 | || reg_equiv[regno].loop_depth < loop_depth) | |
1048 | continue; | |
1049 | ||
1050 | /* reg_equiv[REGNO].replace gets set only when | |
1051 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
1052 | once and used once. (If it were only set, but not used, | |
1053 | flow would have deleted the setting insns.) Hence | |
1054 | there can only be one insn in reg_equiv[REGNO].init_insns. */ | |
1055 | if (reg_equiv[regno].init_insns == NULL_RTX | |
1056 | || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX) | |
2e1253f3 | 1057 | abort (); |
2ab0437e | 1058 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); |
2e1253f3 | 1059 | |
2ab0437e JH |
1060 | /* We may not move instructions that can throw, since |
1061 | that changes basic block boundaries and we are not | |
1062 | prepared to adjust the CFG to match. */ | |
1063 | if (can_throw_internal (equiv_insn)) | |
1064 | continue; | |
2e1253f3 | 1065 | |
2ab0437e JH |
1066 | if (asm_noperands (PATTERN (equiv_insn)) < 0 |
1067 | && validate_replace_rtx (regno_reg_rtx[regno], | |
5ca9299f | 1068 | *(reg_equiv[regno].src_p), insn)) |
bf6d9fd7 | 1069 | { |
2ab0437e JH |
1070 | rtx equiv_link; |
1071 | rtx last_link; | |
1072 | rtx note; | |
1073 | ||
1074 | /* Find the last note. */ | |
1075 | for (last_link = link; XEXP (last_link, 1); | |
1076 | last_link = XEXP (last_link, 1)) | |
1077 | ; | |
1078 | ||
1079 | /* Append the REG_DEAD notes from equiv_insn. */ | |
1080 | equiv_link = REG_NOTES (equiv_insn); | |
1081 | while (equiv_link) | |
bf6d9fd7 | 1082 | { |
2ab0437e JH |
1083 | note = equiv_link; |
1084 | equiv_link = XEXP (equiv_link, 1); | |
1085 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
1086 | { | |
1087 | remove_note (equiv_insn, note); | |
1088 | XEXP (last_link, 1) = note; | |
1089 | XEXP (note, 1) = NULL_RTX; | |
1090 | last_link = note; | |
1091 | } | |
bf6d9fd7 | 1092 | } |
bf6d9fd7 | 1093 | |
2ab0437e JH |
1094 | remove_death (regno, insn); |
1095 | REG_N_REFS (regno) = 0; | |
1096 | REG_FREQ (regno) = 0; | |
ca6c03ca | 1097 | delete_insn (equiv_insn); |
e11e816e | 1098 | |
2ab0437e JH |
1099 | reg_equiv[regno].init_insns |
1100 | = XEXP (reg_equiv[regno].init_insns, 1); | |
1101 | } | |
1102 | /* Move the initialization of the register to just before | |
1103 | INSN. Update the flow information. */ | |
1104 | else if (PREV_INSN (insn) != equiv_insn) | |
1105 | { | |
1106 | rtx new_insn; | |
2e1253f3 | 1107 | |
2ab0437e JH |
1108 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); |
1109 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
1110 | REG_NOTES (equiv_insn) = 0; | |
2e1253f3 | 1111 | |
2ab0437e JH |
1112 | /* Make sure this insn is recognized before reload begins, |
1113 | otherwise eliminate_regs_in_insn will abort. */ | |
1114 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
cad33336 | 1115 | |
ca6c03ca | 1116 | delete_insn (equiv_insn); |
2e1253f3 | 1117 | |
2ab0437e | 1118 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; |
96af667a | 1119 | |
e0082a72 | 1120 | REG_BASIC_BLOCK (regno) = bb->index; |
2ab0437e JH |
1121 | REG_N_CALLS_CROSSED (regno) = 0; |
1122 | REG_LIVE_LENGTH (regno) = 2; | |
2e1253f3 | 1123 | |
a813c111 SB |
1124 | if (insn == BB_HEAD (bb)) |
1125 | BB_HEAD (bb) = PREV_INSN (insn); | |
2e1253f3 | 1126 | |
2ab0437e JH |
1127 | /* Remember to clear REGNO from all basic block's live |
1128 | info. */ | |
1129 | SET_REGNO_REG_SET (&cleared_regs, regno); | |
1130 | clear_regnos++; | |
1131 | } | |
2e1253f3 ILT |
1132 | } |
1133 | } | |
1134 | } | |
2bbd3819 | 1135 | } |
e05e2395 | 1136 | |
25e4379f MM |
1137 | /* Clear all dead REGNOs from all basic block's live info. */ |
1138 | if (clear_regnos) | |
1139 | { | |
e0082a72 | 1140 | int j; |
25e4379f | 1141 | if (clear_regnos > 8) |
e11e816e | 1142 | { |
e0082a72 | 1143 | FOR_EACH_BB (bb) |
25e4379f | 1144 | { |
e0082a72 ZD |
1145 | AND_COMPL_REG_SET (bb->global_live_at_start, &cleared_regs); |
1146 | AND_COMPL_REG_SET (bb->global_live_at_end, &cleared_regs); | |
25e4379f MM |
1147 | } |
1148 | } | |
1149 | else | |
e11e816e KH |
1150 | EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j, |
1151 | { | |
e0082a72 | 1152 | FOR_EACH_BB (bb) |
25e4379f | 1153 | { |
e0082a72 ZD |
1154 | CLEAR_REGNO_REG_SET (bb->global_live_at_start, j); |
1155 | CLEAR_REGNO_REG_SET (bb->global_live_at_end, j); | |
25e4379f MM |
1156 | } |
1157 | }); | |
1158 | } | |
1159 | ||
e05e2395 MM |
1160 | /* Clean up. */ |
1161 | end_alias_analysis (); | |
25e4379f | 1162 | CLEAR_REG_SET (&cleared_regs); |
bf6d9fd7 | 1163 | free (reg_equiv); |
2bbd3819 | 1164 | } |
135eb61c R |
1165 | |
1166 | /* Mark REG as having no known equivalence. | |
3d042e77 | 1167 | Some instructions might have been processed before and furnished |
135eb61c R |
1168 | with REG_EQUIV notes for this register; these notes will have to be |
1169 | removed. | |
1170 | STORE is the piece of RTL that does the non-constant / conflicting | |
1171 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
1172 | but needs to be there because this function is called from note_stores. */ | |
1173 | static void | |
0c20a65f | 1174 | no_equiv (rtx reg, rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED) |
135eb61c R |
1175 | { |
1176 | int regno; | |
1177 | rtx list; | |
1178 | ||
1179 | if (GET_CODE (reg) != REG) | |
1180 | return; | |
1181 | regno = REGNO (reg); | |
bf6d9fd7 | 1182 | list = reg_equiv[regno].init_insns; |
135eb61c R |
1183 | if (list == const0_rtx) |
1184 | return; | |
1185 | for (; list; list = XEXP (list, 1)) | |
1186 | { | |
1187 | rtx insn = XEXP (list, 0); | |
1188 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
1189 | } | |
bf6d9fd7 JW |
1190 | reg_equiv[regno].init_insns = const0_rtx; |
1191 | reg_equiv[regno].replacement = NULL_RTX; | |
135eb61c | 1192 | } |
2bbd3819 RS |
1193 | \f |
1194 | /* Allocate hard regs to the pseudo regs used only within block number B. | |
1195 | Only the pseudos that die but once can be handled. */ | |
1196 | ||
1197 | static void | |
0c20a65f | 1198 | block_alloc (int b) |
2bbd3819 | 1199 | { |
b3694847 SS |
1200 | int i, q; |
1201 | rtx insn; | |
902197eb | 1202 | rtx note, hard_reg; |
2bbd3819 RS |
1203 | int insn_number = 0; |
1204 | int insn_count = 0; | |
1205 | int max_uid = get_max_uid (); | |
aabf56ce | 1206 | int *qty_order; |
2bbd3819 RS |
1207 | int no_conflict_combined_regno = -1; |
1208 | ||
1209 | /* Count the instructions in the basic block. */ | |
1210 | ||
a813c111 | 1211 | insn = BB_END (BASIC_BLOCK (b)); |
2bbd3819 RS |
1212 | while (1) |
1213 | { | |
1214 | if (GET_CODE (insn) != NOTE) | |
1215 | if (++insn_count > max_uid) | |
1216 | abort (); | |
a813c111 | 1217 | if (insn == BB_HEAD (BASIC_BLOCK (b))) |
2bbd3819 RS |
1218 | break; |
1219 | insn = PREV_INSN (insn); | |
1220 | } | |
1221 | ||
1222 | /* +2 to leave room for a post_mark_life at the last insn and for | |
1223 | the birth of a CLOBBER in the first insn. */ | |
703ad42b | 1224 | regs_live_at = xcalloc ((2 * insn_count + 2), sizeof (HARD_REG_SET)); |
2bbd3819 RS |
1225 | |
1226 | /* Initialize table of hardware registers currently live. */ | |
1227 | ||
e881bb1b | 1228 | REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start); |
2bbd3819 RS |
1229 | |
1230 | /* This loop scans the instructions of the basic block | |
1231 | and assigns quantities to registers. | |
1232 | It computes which registers to tie. */ | |
1233 | ||
a813c111 | 1234 | insn = BB_HEAD (BASIC_BLOCK (b)); |
2bbd3819 RS |
1235 | while (1) |
1236 | { | |
2bbd3819 RS |
1237 | if (GET_CODE (insn) != NOTE) |
1238 | insn_number++; | |
1239 | ||
2c3c49de | 1240 | if (INSN_P (insn)) |
2bbd3819 | 1241 | { |
b3694847 SS |
1242 | rtx link, set; |
1243 | int win = 0; | |
1244 | rtx r0, r1 = NULL_RTX; | |
2bbd3819 RS |
1245 | int combined_regno = -1; |
1246 | int i; | |
2bbd3819 RS |
1247 | |
1248 | this_insn_number = insn_number; | |
1249 | this_insn = insn; | |
1250 | ||
0a578fee | 1251 | extract_insn (insn); |
2bbd3819 RS |
1252 | which_alternative = -1; |
1253 | ||
1254 | /* Is this insn suitable for tying two registers? | |
1255 | If so, try doing that. | |
1256 | Suitable insns are those with at least two operands and where | |
1257 | operand 0 is an output that is a register that is not | |
1258 | earlyclobber. | |
7aba0f0b RK |
1259 | |
1260 | We can tie operand 0 with some operand that dies in this insn. | |
1261 | First look for operands that are required to be in the same | |
1262 | register as operand 0. If we find such, only try tying that | |
1263 | operand or one that can be put into that operand if the | |
1264 | operation is commutative. If we don't find an operand | |
1265 | that is required to be in the same register as operand 0, | |
1266 | we can tie with any operand. | |
1267 | ||
2bbd3819 RS |
1268 | Subregs in place of regs are also ok. |
1269 | ||
1270 | If tying is done, WIN is set nonzero. */ | |
1271 | ||
d29c259b RH |
1272 | if (optimize |
1273 | && recog_data.n_operands > 1 | |
1ccbefce | 1274 | && recog_data.constraints[0][0] == '=' |
19af6455 | 1275 | && recog_data.constraints[0][1] != '&') |
2bbd3819 | 1276 | { |
3061cc54 | 1277 | /* If non-negative, is an operand that must match operand 0. */ |
7aba0f0b | 1278 | int must_match_0 = -1; |
3061cc54 RK |
1279 | /* Counts number of alternatives that require a match with |
1280 | operand 0. */ | |
1281 | int n_matching_alts = 0; | |
7aba0f0b | 1282 | |
1ccbefce | 1283 | for (i = 1; i < recog_data.n_operands; i++) |
3061cc54 | 1284 | { |
1ccbefce | 1285 | const char *p = recog_data.constraints[i]; |
84b72302 | 1286 | int this_match = requires_inout (p); |
3061cc54 RK |
1287 | |
1288 | n_matching_alts += this_match; | |
1ccbefce | 1289 | if (this_match == recog_data.n_alternatives) |
3061cc54 RK |
1290 | must_match_0 = i; |
1291 | } | |
2bbd3819 | 1292 | |
1ccbefce RH |
1293 | r0 = recog_data.operand[0]; |
1294 | for (i = 1; i < recog_data.n_operands; i++) | |
2bbd3819 | 1295 | { |
7aba0f0b RK |
1296 | /* Skip this operand if we found an operand that |
1297 | must match operand 0 and this operand isn't it | |
1298 | and can't be made to be it by commutativity. */ | |
1299 | ||
1300 | if (must_match_0 >= 0 && i != must_match_0 | |
1301 | && ! (i == must_match_0 + 1 | |
1ccbefce | 1302 | && recog_data.constraints[i-1][0] == '%') |
7aba0f0b | 1303 | && ! (i == must_match_0 - 1 |
1ccbefce | 1304 | && recog_data.constraints[i][0] == '%')) |
7aba0f0b | 1305 | continue; |
3061cc54 RK |
1306 | |
1307 | /* Likewise if each alternative has some operand that | |
64e3a413 | 1308 | must match operand zero. In that case, skip any |
3061cc54 RK |
1309 | operand that doesn't list operand 0 since we know that |
1310 | the operand always conflicts with operand 0. We | |
3d042e77 | 1311 | ignore commutativity in this case to keep things simple. */ |
1ccbefce RH |
1312 | if (n_matching_alts == recog_data.n_alternatives |
1313 | && 0 == requires_inout (recog_data.constraints[i])) | |
3061cc54 | 1314 | continue; |
2bbd3819 | 1315 | |
1ccbefce | 1316 | r1 = recog_data.operand[i]; |
2bbd3819 | 1317 | |
7aba0f0b RK |
1318 | /* If the operand is an address, find a register in it. |
1319 | There may be more than one register, but we only try one | |
1320 | of them. */ | |
ccfc6cc8 | 1321 | if (recog_data.constraints[i][0] == 'p' |
97488870 R |
1322 | || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0], |
1323 | recog_data.constraints[i])) | |
7aba0f0b RK |
1324 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) |
1325 | r1 = XEXP (r1, 0); | |
1326 | ||
902197eb DD |
1327 | /* Avoid making a call-saved register unnecessarily |
1328 | clobbered. */ | |
1329 | hard_reg = get_hard_reg_initial_reg (cfun, r1); | |
1330 | if (hard_reg != NULL_RTX) | |
1331 | { | |
1332 | if (GET_CODE (hard_reg) == REG | |
710af899 KG |
1333 | && IN_RANGE (REGNO (hard_reg), |
1334 | 0, FIRST_PSEUDO_REGISTER - 1) | |
902197eb DD |
1335 | && ! call_used_regs[REGNO (hard_reg)]) |
1336 | continue; | |
1337 | } | |
1338 | ||
7aba0f0b RK |
1339 | if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) |
1340 | { | |
1341 | /* We have two priorities for hard register preferences. | |
1342 | If we have a move insn or an insn whose first input | |
1343 | can only be in the same register as the output, give | |
1344 | priority to an equivalence found from that insn. */ | |
1345 | int may_save_copy | |
1ccbefce | 1346 | = (r1 == recog_data.operand[i] && must_match_0 >= 0); |
64e3a413 | 1347 | |
7aba0f0b RK |
1348 | if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) |
1349 | win = combine_regs (r1, r0, may_save_copy, | |
1350 | insn_number, insn, 0); | |
1351 | } | |
662347c5 JL |
1352 | if (win) |
1353 | break; | |
2bbd3819 RS |
1354 | } |
1355 | } | |
1356 | ||
1357 | /* Recognize an insn sequence with an ultimate result | |
1358 | which can safely overlap one of the inputs. | |
1359 | The sequence begins with a CLOBBER of its result, | |
1360 | and ends with an insn that copies the result to itself | |
1361 | and has a REG_EQUAL note for an equivalent formula. | |
1362 | That note indicates what the inputs are. | |
1363 | The result and the input can overlap if each insn in | |
1364 | the sequence either doesn't mention the input | |
1365 | or has a REG_NO_CONFLICT note to inhibit the conflict. | |
1366 | ||
1367 | We do the combining test at the CLOBBER so that the | |
1368 | destination register won't have had a quantity number | |
1369 | assigned, since that would prevent combining. */ | |
1370 | ||
d29c259b RH |
1371 | if (optimize |
1372 | && GET_CODE (PATTERN (insn)) == CLOBBER | |
2bbd3819 RS |
1373 | && (r0 = XEXP (PATTERN (insn), 0), |
1374 | GET_CODE (r0) == REG) | |
b1ec3c92 | 1375 | && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 |
a6665f8c | 1376 | && XEXP (link, 0) != 0 |
2bbd3819 RS |
1377 | && GET_CODE (XEXP (link, 0)) == INSN |
1378 | && (set = single_set (XEXP (link, 0))) != 0 | |
1379 | && SET_DEST (set) == r0 && SET_SRC (set) == r0 | |
b1ec3c92 CH |
1380 | && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, |
1381 | NULL_RTX)) != 0) | |
2bbd3819 RS |
1382 | { |
1383 | if (r1 = XEXP (note, 0), GET_CODE (r1) == REG | |
1384 | /* Check that we have such a sequence. */ | |
1385 | && no_conflict_p (insn, r0, r1)) | |
1386 | win = combine_regs (r1, r0, 1, insn_number, insn, 1); | |
1387 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' | |
1388 | && (r1 = XEXP (XEXP (note, 0), 0), | |
1389 | GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) | |
1390 | && no_conflict_p (insn, r0, r1)) | |
1391 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1392 | ||
1393 | /* Here we care if the operation to be computed is | |
1394 | commutative. */ | |
1395 | else if ((GET_CODE (XEXP (note, 0)) == EQ | |
1396 | || GET_CODE (XEXP (note, 0)) == NE | |
1397 | || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') | |
1398 | && (r1 = XEXP (XEXP (note, 0), 1), | |
1399 | (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) | |
1400 | && no_conflict_p (insn, r0, r1)) | |
1401 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1402 | ||
1403 | /* If we did combine something, show the register number | |
1404 | in question so that we know to ignore its death. */ | |
1405 | if (win) | |
1406 | no_conflict_combined_regno = REGNO (r1); | |
1407 | } | |
1408 | ||
1409 | /* If registers were just tied, set COMBINED_REGNO | |
1410 | to the number of the register used in this insn | |
1411 | that was tied to the register set in this insn. | |
1412 | This register's qty should not be "killed". */ | |
1413 | ||
1414 | if (win) | |
1415 | { | |
1416 | while (GET_CODE (r1) == SUBREG) | |
1417 | r1 = SUBREG_REG (r1); | |
1418 | combined_regno = REGNO (r1); | |
1419 | } | |
1420 | ||
1421 | /* Mark the death of everything that dies in this instruction, | |
1422 | except for anything that was just combined. */ | |
1423 | ||
1424 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1425 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1426 | && GET_CODE (XEXP (link, 0)) == REG | |
770ae6cc RK |
1427 | && combined_regno != (int) REGNO (XEXP (link, 0)) |
1428 | && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0)) | |
1429 | || ! find_reg_note (insn, REG_NO_CONFLICT, | |
1430 | XEXP (link, 0)))) | |
2bbd3819 RS |
1431 | wipe_dead_reg (XEXP (link, 0), 0); |
1432 | ||
1433 | /* Allocate qty numbers for all registers local to this block | |
1434 | that are born (set) in this instruction. | |
1435 | A pseudo that already has a qty is not changed. */ | |
1436 | ||
84832317 | 1437 | note_stores (PATTERN (insn), reg_is_set, NULL); |
2bbd3819 RS |
1438 | |
1439 | /* If anything is set in this insn and then unused, mark it as dying | |
1440 | after this insn, so it will conflict with our outputs. This | |
1441 | can't match with something that combined, and it doesn't matter | |
1442 | if it did. Do this after the calls to reg_is_set since these | |
1443 | die after, not during, the current insn. */ | |
1444 | ||
1445 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1446 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
1447 | && GET_CODE (XEXP (link, 0)) == REG) | |
1448 | wipe_dead_reg (XEXP (link, 0), 1); | |
1449 | ||
64e3a413 | 1450 | /* If this is an insn that has a REG_RETVAL note pointing at a |
2bbd3819 RS |
1451 | CLOBBER insn, we have reached the end of a REG_NO_CONFLICT |
1452 | block, so clear any register number that combined within it. */ | |
b1ec3c92 | 1453 | if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 |
2bbd3819 RS |
1454 | && GET_CODE (XEXP (note, 0)) == INSN |
1455 | && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) | |
1456 | no_conflict_combined_regno = -1; | |
1457 | } | |
1458 | ||
1459 | /* Set the registers live after INSN_NUMBER. Note that we never | |
1460 | record the registers live before the block's first insn, since no | |
1461 | pseudos we care about are live before that insn. */ | |
1462 | ||
1463 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); | |
1464 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); | |
1465 | ||
a813c111 | 1466 | if (insn == BB_END (BASIC_BLOCK (b))) |
2bbd3819 RS |
1467 | break; |
1468 | ||
1469 | insn = NEXT_INSN (insn); | |
1470 | } | |
1471 | ||
1472 | /* Now every register that is local to this basic block | |
1473 | should have been given a quantity, or else -1 meaning ignore it. | |
64e3a413 | 1474 | Every quantity should have a known birth and death. |
2bbd3819 | 1475 | |
51b86d8b RK |
1476 | Order the qtys so we assign them registers in order of the |
1477 | number of suggested registers they need so we allocate those with | |
1478 | the most restrictive needs first. */ | |
2bbd3819 | 1479 | |
703ad42b | 1480 | qty_order = xmalloc (next_qty * sizeof (int)); |
2bbd3819 RS |
1481 | for (i = 0; i < next_qty; i++) |
1482 | qty_order[i] = i; | |
1483 | ||
1484 | #define EXCHANGE(I1, I2) \ | |
1485 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1486 | ||
1487 | switch (next_qty) | |
1488 | { | |
1489 | case 3: | |
1490 | /* Make qty_order[2] be the one to allocate last. */ | |
51b86d8b | 1491 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 | 1492 | EXCHANGE (0, 1); |
51b86d8b | 1493 | if (qty_sugg_compare (1, 2) > 0) |
2bbd3819 RS |
1494 | EXCHANGE (2, 1); |
1495 | ||
0f41302f | 1496 | /* ... Fall through ... */ |
2bbd3819 RS |
1497 | case 2: |
1498 | /* Put the best one to allocate in qty_order[0]. */ | |
51b86d8b | 1499 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 RS |
1500 | EXCHANGE (0, 1); |
1501 | ||
0f41302f | 1502 | /* ... Fall through ... */ |
2bbd3819 RS |
1503 | |
1504 | case 1: | |
1505 | case 0: | |
1506 | /* Nothing to do here. */ | |
1507 | break; | |
1508 | ||
1509 | default: | |
51b86d8b | 1510 | qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); |
2bbd3819 RS |
1511 | } |
1512 | ||
1513 | /* Try to put each quantity in a suggested physical register, if it has one. | |
1514 | This may cause registers to be allocated that otherwise wouldn't be, but | |
1515 | this seems acceptable in local allocation (unlike global allocation). */ | |
1516 | for (i = 0; i < next_qty; i++) | |
1517 | { | |
1518 | q = qty_order[i]; | |
51b86d8b | 1519 | if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) |
a1ed7bdb JH |
1520 | qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q, |
1521 | 0, 1, qty[q].birth, qty[q].death); | |
2bbd3819 | 1522 | else |
a1ed7bdb | 1523 | qty[q].phys_reg = -1; |
2bbd3819 RS |
1524 | } |
1525 | ||
64e3a413 KH |
1526 | /* Order the qtys so we assign them registers in order of |
1527 | decreasing length of life. Normally call qsort, but if we | |
51b86d8b RK |
1528 | have only a very small number of quantities, sort them ourselves. */ |
1529 | ||
1530 | for (i = 0; i < next_qty; i++) | |
1531 | qty_order[i] = i; | |
1532 | ||
1533 | #define EXCHANGE(I1, I2) \ | |
1534 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1535 | ||
1536 | switch (next_qty) | |
1537 | { | |
1538 | case 3: | |
1539 | /* Make qty_order[2] be the one to allocate last. */ | |
1540 | if (qty_compare (0, 1) > 0) | |
1541 | EXCHANGE (0, 1); | |
1542 | if (qty_compare (1, 2) > 0) | |
1543 | EXCHANGE (2, 1); | |
1544 | ||
0f41302f | 1545 | /* ... Fall through ... */ |
51b86d8b RK |
1546 | case 2: |
1547 | /* Put the best one to allocate in qty_order[0]. */ | |
1548 | if (qty_compare (0, 1) > 0) | |
1549 | EXCHANGE (0, 1); | |
1550 | ||
0f41302f | 1551 | /* ... Fall through ... */ |
51b86d8b RK |
1552 | |
1553 | case 1: | |
1554 | case 0: | |
1555 | /* Nothing to do here. */ | |
1556 | break; | |
1557 | ||
1558 | default: | |
1559 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); | |
1560 | } | |
1561 | ||
2bbd3819 RS |
1562 | /* Now for each qty that is not a hardware register, |
1563 | look for a hardware register to put it in. | |
1564 | First try the register class that is cheapest for this qty, | |
1565 | if there is more than one class. */ | |
1566 | ||
1567 | for (i = 0; i < next_qty; i++) | |
1568 | { | |
1569 | q = qty_order[i]; | |
a1ed7bdb | 1570 | if (qty[q].phys_reg < 0) |
2bbd3819 | 1571 | { |
624a8b3a JL |
1572 | #ifdef INSN_SCHEDULING |
1573 | /* These values represent the adjusted lifetime of a qty so | |
1574 | that it conflicts with qtys which appear near the start/end | |
1575 | of this qty's lifetime. | |
1576 | ||
1577 | The purpose behind extending the lifetime of this qty is to | |
1578 | discourage the register allocator from creating false | |
1579 | dependencies. | |
64e3a413 | 1580 | |
f63d1bf7 | 1581 | The adjustment value is chosen to indicate that this qty |
996e9683 | 1582 | conflicts with all the qtys in the instructions immediately |
624a8b3a JL |
1583 | before and after the lifetime of this qty. |
1584 | ||
1585 | Experiments have shown that higher values tend to hurt | |
1586 | overall code performance. | |
1587 | ||
1588 | If allocation using the extended lifetime fails we will try | |
1589 | again with the qty's unadjusted lifetime. */ | |
a1ed7bdb | 1590 | int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2); |
996e9683 | 1591 | int fake_death = MIN (insn_number * 2 + 1, |
a1ed7bdb | 1592 | qty[q].death + 2 - qty[q].death % 2); |
624a8b3a JL |
1593 | #endif |
1594 | ||
2bbd3819 RS |
1595 | if (N_REG_CLASSES > 1) |
1596 | { | |
624a8b3a JL |
1597 | #ifdef INSN_SCHEDULING |
1598 | /* We try to avoid using hard registers allocated to qtys which | |
1599 | are born immediately after this qty or die immediately before | |
1600 | this qty. | |
1601 | ||
1602 | This optimization is only appropriate when we will run | |
1603 | a scheduling pass after reload and we are not optimizing | |
1604 | for code size. */ | |
c358412f JL |
1605 | if (flag_schedule_insns_after_reload |
1606 | && !optimize_size | |
1607 | && !SMALL_REGISTER_CLASSES) | |
624a8b3a | 1608 | { |
64e3a413 | 1609 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb | 1610 | qty[q].mode, q, 0, 0, |
624a8b3a | 1611 | fake_birth, fake_death); |
a1ed7bdb | 1612 | if (qty[q].phys_reg >= 0) |
624a8b3a JL |
1613 | continue; |
1614 | } | |
1615 | #endif | |
64e3a413 | 1616 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb JH |
1617 | qty[q].mode, q, 0, 0, |
1618 | qty[q].birth, qty[q].death); | |
1619 | if (qty[q].phys_reg >= 0) | |
2bbd3819 RS |
1620 | continue; |
1621 | } | |
1622 | ||
624a8b3a JL |
1623 | #ifdef INSN_SCHEDULING |
1624 | /* Similarly, avoid false dependencies. */ | |
c358412f JL |
1625 | if (flag_schedule_insns_after_reload |
1626 | && !optimize_size | |
1627 | && !SMALL_REGISTER_CLASSES | |
a1ed7bdb JH |
1628 | && qty[q].alternate_class != NO_REGS) |
1629 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1630 | qty[q].mode, q, 0, 0, | |
624a8b3a JL |
1631 | fake_birth, fake_death); |
1632 | #endif | |
a1ed7bdb JH |
1633 | if (qty[q].alternate_class != NO_REGS) |
1634 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1635 | qty[q].mode, q, 0, 0, | |
1636 | qty[q].birth, qty[q].death); | |
2bbd3819 RS |
1637 | } |
1638 | } | |
1639 | ||
1640 | /* Now propagate the register assignments | |
1641 | to the pseudo regs belonging to the qtys. */ | |
1642 | ||
1643 | for (q = 0; q < next_qty; q++) | |
a1ed7bdb | 1644 | if (qty[q].phys_reg >= 0) |
2bbd3819 | 1645 | { |
a1ed7bdb JH |
1646 | for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i]) |
1647 | reg_renumber[i] = qty[q].phys_reg + reg_offset[i]; | |
2bbd3819 | 1648 | } |
ff154f78 MM |
1649 | |
1650 | /* Clean up. */ | |
1651 | free (regs_live_at); | |
1652 | free (qty_order); | |
2bbd3819 RS |
1653 | } |
1654 | \f | |
1655 | /* Compare two quantities' priority for getting real registers. | |
1656 | We give shorter-lived quantities higher priority. | |
6dc42e49 RS |
1657 | Quantities with more references are also preferred, as are quantities that |
1658 | require multiple registers. This is the identical prioritization as | |
2bbd3819 RS |
1659 | done by global-alloc. |
1660 | ||
1661 | We used to give preference to registers with *longer* lives, but using | |
1662 | the same algorithm in both local- and global-alloc can speed up execution | |
1663 | of some programs by as much as a factor of three! */ | |
1664 | ||
2f23fcc9 RK |
1665 | /* Note that the quotient will never be bigger than |
1666 | the value of floor_log2 times the maximum number of | |
a08b2604 JH |
1667 | times a register can occur in one insn (surely less than 100) |
1668 | weighted by frequency (max REG_FREQ_MAX). | |
1669 | Multiplying this by 10000/REG_FREQ_MAX can't overflow. | |
2f23fcc9 RK |
1670 | QTY_CMP_PRI is also used by qty_sugg_compare. */ |
1671 | ||
1672 | #define QTY_CMP_PRI(q) \ | |
b2aec5c0 | 1673 | ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \ |
a08b2604 | 1674 | / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX))) |
2f23fcc9 | 1675 | |
2bbd3819 | 1676 | static int |
0c20a65f | 1677 | qty_compare (int q1, int q2) |
2bbd3819 | 1678 | { |
2f23fcc9 | 1679 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
2bbd3819 RS |
1680 | } |
1681 | ||
1682 | static int | |
0c20a65f | 1683 | qty_compare_1 (const void *q1p, const void *q2p) |
2bbd3819 | 1684 | { |
b3694847 SS |
1685 | int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
1686 | int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
2f23fcc9 RK |
1687 | |
1688 | if (tem != 0) | |
1689 | return tem; | |
1690 | ||
2bbd3819 RS |
1691 | /* If qtys are equally good, sort by qty number, |
1692 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1693 | return q1 - q2; |
2bbd3819 RS |
1694 | } |
1695 | \f | |
51b86d8b RK |
1696 | /* Compare two quantities' priority for getting real registers. This version |
1697 | is called for quantities that have suggested hard registers. First priority | |
1698 | goes to quantities that have copy preferences, then to those that have | |
1699 | normal preferences. Within those groups, quantities with the lower | |
9faa82d8 | 1700 | number of preferences have the highest priority. Of those, we use the same |
51b86d8b RK |
1701 | algorithm as above. */ |
1702 | ||
2f23fcc9 RK |
1703 | #define QTY_CMP_SUGG(q) \ |
1704 | (qty_phys_num_copy_sugg[q] \ | |
1705 | ? qty_phys_num_copy_sugg[q] \ | |
1706 | : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER) | |
1707 | ||
51b86d8b | 1708 | static int |
0c20a65f | 1709 | qty_sugg_compare (int q1, int q2) |
51b86d8b | 1710 | { |
b3694847 | 1711 | int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
2f23fcc9 RK |
1712 | |
1713 | if (tem != 0) | |
1714 | return tem; | |
64e3a413 | 1715 | |
2f23fcc9 | 1716 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
51b86d8b RK |
1717 | } |
1718 | ||
1719 | static int | |
0c20a65f | 1720 | qty_sugg_compare_1 (const void *q1p, const void *q2p) |
51b86d8b | 1721 | { |
b3694847 SS |
1722 | int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
1723 | int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); | |
2f23fcc9 RK |
1724 | |
1725 | if (tem != 0) | |
1726 | return tem; | |
1727 | ||
1728 | tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
1729 | if (tem != 0) | |
1730 | return tem; | |
51b86d8b RK |
1731 | |
1732 | /* If qtys are equally good, sort by qty number, | |
1733 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1734 | return q1 - q2; |
51b86d8b | 1735 | } |
2f23fcc9 RK |
1736 | |
1737 | #undef QTY_CMP_SUGG | |
1738 | #undef QTY_CMP_PRI | |
51b86d8b | 1739 | \f |
2bbd3819 RS |
1740 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. |
1741 | Returns 1 if have done so, or 0 if cannot. | |
1742 | ||
1743 | Combining registers means marking them as having the same quantity | |
1744 | and adjusting the offsets within the quantity if either of | |
a5342656 | 1745 | them is a SUBREG. |
2bbd3819 RS |
1746 | |
1747 | We don't actually combine a hard reg with a pseudo; instead | |
1748 | we just record the hard reg as the suggestion for the pseudo's quantity. | |
1749 | If we really combined them, we could lose if the pseudo lives | |
1750 | across an insn that clobbers the hard reg (eg, movstr). | |
1751 | ||
cc2902df | 1752 | ALREADY_DEAD is nonzero if USEDREG is known to be dead even though |
2bbd3819 RS |
1753 | there is no REG_DEAD note on INSN. This occurs during the processing |
1754 | of REG_NO_CONFLICT blocks. | |
1755 | ||
a5342656 | 1756 | MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to |
2bbd3819 RS |
1757 | SETREG or if the input and output must share a register. |
1758 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. | |
64e3a413 | 1759 | |
2bbd3819 RS |
1760 | There are elaborate checks for the validity of combining. */ |
1761 | ||
2bbd3819 | 1762 | static int |
0c20a65f AJ |
1763 | combine_regs (rtx usedreg, rtx setreg, int may_save_copy, int insn_number, |
1764 | rtx insn, int already_dead) | |
2bbd3819 | 1765 | { |
b3694847 SS |
1766 | int ureg, sreg; |
1767 | int offset = 0; | |
2bbd3819 | 1768 | int usize, ssize; |
b3694847 | 1769 | int sqty; |
2bbd3819 RS |
1770 | |
1771 | /* Determine the numbers and sizes of registers being used. If a subreg | |
6dc42e49 | 1772 | is present that does not change the entire register, don't consider |
2bbd3819 RS |
1773 | this a copy insn. */ |
1774 | ||
1775 | while (GET_CODE (usedreg) == SUBREG) | |
1776 | { | |
44a5da09 GS |
1777 | rtx subreg = SUBREG_REG (usedreg); |
1778 | ||
1779 | if (GET_CODE (subreg) == REG) | |
1780 | { | |
1781 | if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD) | |
1782 | may_save_copy = 0; | |
1783 | ||
1784 | if (REGNO (subreg) < FIRST_PSEUDO_REGISTER) | |
1785 | offset += subreg_regno_offset (REGNO (subreg), | |
1786 | GET_MODE (subreg), | |
1787 | SUBREG_BYTE (usedreg), | |
1788 | GET_MODE (usedreg)); | |
1789 | else | |
1790 | offset += (SUBREG_BYTE (usedreg) | |
1791 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
1792 | } | |
1793 | ||
1794 | usedreg = subreg; | |
2bbd3819 | 1795 | } |
44a5da09 | 1796 | |
2bbd3819 RS |
1797 | if (GET_CODE (usedreg) != REG) |
1798 | return 0; | |
44a5da09 | 1799 | |
2bbd3819 | 1800 | ureg = REGNO (usedreg); |
ddef6bc7 JJ |
1801 | if (ureg < FIRST_PSEUDO_REGISTER) |
1802 | usize = HARD_REGNO_NREGS (ureg, GET_MODE (usedreg)); | |
1803 | else | |
1804 | usize = ((GET_MODE_SIZE (GET_MODE (usedreg)) | |
1805 | + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1)) | |
1806 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
2bbd3819 RS |
1807 | |
1808 | while (GET_CODE (setreg) == SUBREG) | |
1809 | { | |
44a5da09 GS |
1810 | rtx subreg = SUBREG_REG (setreg); |
1811 | ||
1812 | if (GET_CODE (subreg) == REG) | |
1813 | { | |
1814 | if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD) | |
1815 | may_save_copy = 0; | |
1816 | ||
1817 | if (REGNO (subreg) < FIRST_PSEUDO_REGISTER) | |
1818 | offset -= subreg_regno_offset (REGNO (subreg), | |
1819 | GET_MODE (subreg), | |
1820 | SUBREG_BYTE (setreg), | |
1821 | GET_MODE (setreg)); | |
1822 | else | |
1823 | offset -= (SUBREG_BYTE (setreg) | |
1824 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
1825 | } | |
1826 | ||
1827 | setreg = subreg; | |
2bbd3819 | 1828 | } |
44a5da09 | 1829 | |
2bbd3819 RS |
1830 | if (GET_CODE (setreg) != REG) |
1831 | return 0; | |
44a5da09 | 1832 | |
2bbd3819 | 1833 | sreg = REGNO (setreg); |
ddef6bc7 JJ |
1834 | if (sreg < FIRST_PSEUDO_REGISTER) |
1835 | ssize = HARD_REGNO_NREGS (sreg, GET_MODE (setreg)); | |
1836 | else | |
1837 | ssize = ((GET_MODE_SIZE (GET_MODE (setreg)) | |
1838 | + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1)) | |
1839 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
2bbd3819 RS |
1840 | |
1841 | /* If UREG is a pseudo-register that hasn't already been assigned a | |
1842 | quantity number, it means that it is not local to this block or dies | |
1843 | more than once. In either event, we can't do anything with it. */ | |
1844 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) | |
1845 | /* Do not combine registers unless one fits within the other. */ | |
1846 | || (offset > 0 && usize + offset > ssize) | |
1847 | || (offset < 0 && usize + offset < ssize) | |
1848 | /* Do not combine with a smaller already-assigned object | |
0f41302f | 1849 | if that smaller object is already combined with something bigger. */ |
2bbd3819 | 1850 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER |
a1ed7bdb | 1851 | && usize < qty[reg_qty[ureg]].size) |
2bbd3819 RS |
1852 | /* Can't combine if SREG is not a register we can allocate. */ |
1853 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) | |
1854 | /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. | |
1855 | These have already been taken care of. This probably wouldn't | |
1856 | combine anyway, but don't take any chances. */ | |
1857 | || (ureg >= FIRST_PSEUDO_REGISTER | |
1858 | && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) | |
1859 | /* Don't tie something to itself. In most cases it would make no | |
1860 | difference, but it would screw up if the reg being tied to itself | |
1861 | also dies in this insn. */ | |
1862 | || ureg == sreg | |
1863 | /* Don't try to connect two different hardware registers. */ | |
1864 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) | |
1865 | /* Don't connect two different machine modes if they have different | |
1866 | implications as to which registers may be used. */ | |
1867 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) | |
1868 | return 0; | |
1869 | ||
1870 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in | |
1871 | qty_phys_sugg for the pseudo instead of tying them. | |
1872 | ||
1873 | Return "failure" so that the lifespan of UREG is terminated here; | |
1874 | that way the two lifespans will be disjoint and nothing will prevent | |
1875 | the pseudo reg from being given this hard reg. */ | |
1876 | ||
1877 | if (ureg < FIRST_PSEUDO_REGISTER) | |
1878 | { | |
1879 | /* Allocate a quantity number so we have a place to put our | |
1880 | suggestions. */ | |
1881 | if (reg_qty[sreg] == -2) | |
1882 | reg_is_born (setreg, 2 * insn_number); | |
1883 | ||
1884 | if (reg_qty[sreg] >= 0) | |
1885 | { | |
51b86d8b RK |
1886 | if (may_save_copy |
1887 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) | |
2bbd3819 RS |
1888 | { |
1889 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1890 | qty_phys_num_copy_sugg[reg_qty[sreg]]++; |
2bbd3819 | 1891 | } |
51b86d8b | 1892 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) |
2bbd3819 RS |
1893 | { |
1894 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1895 | qty_phys_num_sugg[reg_qty[sreg]]++; |
2bbd3819 RS |
1896 | } |
1897 | } | |
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | /* Similarly for SREG a hard register and UREG a pseudo register. */ | |
1902 | ||
1903 | if (sreg < FIRST_PSEUDO_REGISTER) | |
1904 | { | |
51b86d8b RK |
1905 | if (may_save_copy |
1906 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) | |
2bbd3819 RS |
1907 | { |
1908 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1909 | qty_phys_num_copy_sugg[reg_qty[ureg]]++; |
2bbd3819 | 1910 | } |
51b86d8b | 1911 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) |
2bbd3819 RS |
1912 | { |
1913 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1914 | qty_phys_num_sugg[reg_qty[ureg]]++; |
2bbd3819 RS |
1915 | } |
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | /* At this point we know that SREG and UREG are both pseudos. | |
1920 | Do nothing if SREG already has a quantity or is a register that we | |
1921 | don't allocate. */ | |
1922 | if (reg_qty[sreg] >= -1 | |
1923 | /* If we are not going to let any regs live across calls, | |
1924 | don't tie a call-crossing reg to a non-call-crossing reg. */ | |
1925 | || (current_function_has_nonlocal_label | |
b1f21e0a MM |
1926 | && ((REG_N_CALLS_CROSSED (ureg) > 0) |
1927 | != (REG_N_CALLS_CROSSED (sreg) > 0)))) | |
2bbd3819 RS |
1928 | return 0; |
1929 | ||
1930 | /* We don't already know about SREG, so tie it to UREG | |
1931 | if this is the last use of UREG, provided the classes they want | |
1932 | are compatible. */ | |
1933 | ||
1934 | if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) | |
a1ed7bdb | 1935 | && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class)) |
2bbd3819 RS |
1936 | { |
1937 | /* Add SREG to UREG's quantity. */ | |
1938 | sqty = reg_qty[ureg]; | |
1939 | reg_qty[sreg] = sqty; | |
1940 | reg_offset[sreg] = reg_offset[ureg] + offset; | |
a1ed7bdb JH |
1941 | reg_next_in_qty[sreg] = qty[sqty].first_reg; |
1942 | qty[sqty].first_reg = sreg; | |
2bbd3819 | 1943 | |
a1ed7bdb | 1944 | /* If SREG's reg class is smaller, set qty[SQTY].min_class. */ |
2bbd3819 RS |
1945 | update_qty_class (sqty, sreg); |
1946 | ||
1947 | /* Update info about quantity SQTY. */ | |
a1ed7bdb JH |
1948 | qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg); |
1949 | qty[sqty].n_refs += REG_N_REFS (sreg); | |
b2aec5c0 | 1950 | qty[sqty].freq += REG_FREQ (sreg); |
2bbd3819 RS |
1951 | if (usize < ssize) |
1952 | { | |
b3694847 | 1953 | int i; |
2bbd3819 | 1954 | |
a1ed7bdb | 1955 | for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i]) |
2bbd3819 RS |
1956 | reg_offset[i] -= offset; |
1957 | ||
a1ed7bdb JH |
1958 | qty[sqty].size = ssize; |
1959 | qty[sqty].mode = GET_MODE (setreg); | |
2bbd3819 RS |
1960 | } |
1961 | } | |
1962 | else | |
1963 | return 0; | |
1964 | ||
1965 | return 1; | |
1966 | } | |
1967 | \f | |
1968 | /* Return 1 if the preferred class of REG allows it to be tied | |
1969 | to a quantity or register whose class is CLASS. | |
1970 | True if REG's reg class either contains or is contained in CLASS. */ | |
1971 | ||
1972 | static int | |
0c20a65f | 1973 | reg_meets_class_p (int reg, enum reg_class class) |
2bbd3819 | 1974 | { |
b3694847 | 1975 | enum reg_class rclass = reg_preferred_class (reg); |
2bbd3819 RS |
1976 | return (reg_class_subset_p (rclass, class) |
1977 | || reg_class_subset_p (class, rclass)); | |
1978 | } | |
1979 | ||
a1ed7bdb | 1980 | /* Update the class of QTYNO assuming that REG is being tied to it. */ |
2bbd3819 RS |
1981 | |
1982 | static void | |
0c20a65f | 1983 | update_qty_class (int qtyno, int reg) |
2bbd3819 RS |
1984 | { |
1985 | enum reg_class rclass = reg_preferred_class (reg); | |
a1ed7bdb JH |
1986 | if (reg_class_subset_p (rclass, qty[qtyno].min_class)) |
1987 | qty[qtyno].min_class = rclass; | |
e4600702 RK |
1988 | |
1989 | rclass = reg_alternate_class (reg); | |
a1ed7bdb JH |
1990 | if (reg_class_subset_p (rclass, qty[qtyno].alternate_class)) |
1991 | qty[qtyno].alternate_class = rclass; | |
2bbd3819 RS |
1992 | } |
1993 | \f | |
1994 | /* Handle something which alters the value of an rtx REG. | |
1995 | ||
1996 | REG is whatever is set or clobbered. SETTER is the rtx that | |
1997 | is modifying the register. | |
1998 | ||
1999 | If it is not really a register, we do nothing. | |
2000 | The file-global variables `this_insn' and `this_insn_number' | |
2001 | carry info from `block_alloc'. */ | |
2002 | ||
2003 | static void | |
0c20a65f | 2004 | reg_is_set (rtx reg, rtx setter, void *data ATTRIBUTE_UNUSED) |
2bbd3819 RS |
2005 | { |
2006 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of | |
2007 | a hard register. These may actually not exist any more. */ | |
2008 | ||
2009 | if (GET_CODE (reg) != SUBREG | |
2010 | && GET_CODE (reg) != REG) | |
2011 | return; | |
2012 | ||
2013 | /* Mark this register as being born. If it is used in a CLOBBER, mark | |
2014 | it as being born halfway between the previous insn and this insn so that | |
2015 | it conflicts with our inputs but not the outputs of the previous insn. */ | |
2016 | ||
2017 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); | |
2018 | } | |
2019 | \f | |
2020 | /* Handle beginning of the life of register REG. | |
2021 | BIRTH is the index at which this is happening. */ | |
2022 | ||
2023 | static void | |
0c20a65f | 2024 | reg_is_born (rtx reg, int birth) |
2bbd3819 | 2025 | { |
b3694847 | 2026 | int regno; |
64e3a413 | 2027 | |
2bbd3819 | 2028 | if (GET_CODE (reg) == SUBREG) |
ddef6bc7 JJ |
2029 | { |
2030 | regno = REGNO (SUBREG_REG (reg)); | |
2031 | if (regno < FIRST_PSEUDO_REGISTER) | |
2032 | regno = subreg_hard_regno (reg, 1); | |
2033 | } | |
2bbd3819 RS |
2034 | else |
2035 | regno = REGNO (reg); | |
2036 | ||
2037 | if (regno < FIRST_PSEUDO_REGISTER) | |
2038 | { | |
2039 | mark_life (regno, GET_MODE (reg), 1); | |
2040 | ||
2041 | /* If the register was to have been born earlier that the present | |
2042 | insn, mark it as live where it is actually born. */ | |
2043 | if (birth < 2 * this_insn_number) | |
2044 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); | |
2045 | } | |
2046 | else | |
2047 | { | |
2048 | if (reg_qty[regno] == -2) | |
2049 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); | |
2050 | ||
2051 | /* If this register has a quantity number, show that it isn't dead. */ | |
2052 | if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2053 | qty[reg_qty[regno]].death = -1; |
2bbd3819 RS |
2054 | } |
2055 | } | |
2056 | ||
cc2902df | 2057 | /* Record the death of REG in the current insn. If OUTPUT_P is nonzero, |
2bbd3819 | 2058 | REG is an output that is dying (i.e., it is never used), otherwise it |
333e0f7d RS |
2059 | is an input (the normal case). |
2060 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ | |
2bbd3819 RS |
2061 | |
2062 | static void | |
0c20a65f | 2063 | wipe_dead_reg (rtx reg, int output_p) |
2bbd3819 | 2064 | { |
b3694847 | 2065 | int regno = REGNO (reg); |
2bbd3819 | 2066 | |
333e0f7d RS |
2067 | /* If this insn has multiple results, |
2068 | and the dead reg is used in one of the results, | |
2069 | extend its life to after this insn, | |
64e3a413 | 2070 | so it won't get allocated together with any other result of this insn. |
941c63ac JL |
2071 | |
2072 | It is unsafe to use !single_set here since it will ignore an unused | |
2073 | output. Just because an output is unused does not mean the compiler | |
2074 | can assume the side effect will not occur. Consider if REG appears | |
2075 | in the address of an output and we reload the output. If we allocate | |
2076 | REG to the same hard register as an unused output we could set the hard | |
2077 | register before the output reload insn. */ | |
333e0f7d | 2078 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL |
941c63ac | 2079 | && multiple_sets (this_insn)) |
333e0f7d RS |
2080 | { |
2081 | int i; | |
2082 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) | |
2083 | { | |
2084 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); | |
2085 | if (GET_CODE (set) == SET | |
2086 | && GET_CODE (SET_DEST (set)) != REG | |
2087 | && !rtx_equal_p (reg, SET_DEST (set)) | |
2088 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2089 | output_p = 1; | |
2090 | } | |
2091 | } | |
2092 | ||
c182df0b RK |
2093 | /* If this register is used in an auto-increment address, then extend its |
2094 | life to after this insn, so that it won't get allocated together with | |
2095 | the result of this insn. */ | |
2096 | if (! output_p && find_regno_note (this_insn, REG_INC, regno)) | |
2097 | output_p = 1; | |
2098 | ||
2bbd3819 RS |
2099 | if (regno < FIRST_PSEUDO_REGISTER) |
2100 | { | |
2101 | mark_life (regno, GET_MODE (reg), 0); | |
2102 | ||
2103 | /* If a hard register is dying as an output, mark it as in use at | |
2104 | the beginning of this insn (the above statement would cause this | |
2105 | not to happen). */ | |
2106 | if (output_p) | |
2107 | post_mark_life (regno, GET_MODE (reg), 1, | |
64e3a413 | 2108 | 2 * this_insn_number, 2 * this_insn_number + 1); |
2bbd3819 RS |
2109 | } |
2110 | ||
2111 | else if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2112 | qty[reg_qty[regno]].death = 2 * this_insn_number + output_p; |
2bbd3819 RS |
2113 | } |
2114 | \f | |
2115 | /* Find a block of SIZE words of hard regs in reg_class CLASS | |
2116 | that can hold something of machine-mode MODE | |
2117 | (but actually we test only the first of the block for holding MODE) | |
2118 | and still free between insn BORN_INDEX and insn DEAD_INDEX, | |
2119 | and return the number of the first of them. | |
64e3a413 | 2120 | Return -1 if such a block cannot be found. |
a1ed7bdb | 2121 | If QTYNO crosses calls, insist on a register preserved by calls, |
2bbd3819 RS |
2122 | unless ACCEPT_CALL_CLOBBERED is nonzero. |
2123 | ||
cc2902df | 2124 | If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested |
2bbd3819 RS |
2125 | register is available. If not, return -1. */ |
2126 | ||
2127 | static int | |
0c20a65f AJ |
2128 | find_free_reg (enum reg_class class, enum machine_mode mode, int qtyno, |
2129 | int accept_call_clobbered, int just_try_suggested, | |
2130 | int born_index, int dead_index) | |
2bbd3819 | 2131 | { |
b3694847 | 2132 | int i, ins; |
cff9f8d5 | 2133 | HARD_REG_SET first_used, used; |
2bbd3819 | 2134 | #ifdef ELIMINABLE_REGS |
8b60264b | 2135 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
2bbd3819 RS |
2136 | #endif |
2137 | ||
2138 | /* Validate our parameters. */ | |
2139 | if (born_index < 0 || born_index > dead_index) | |
2140 | abort (); | |
2141 | ||
2142 | /* Don't let a pseudo live in a reg across a function call | |
2143 | if we might get a nonlocal goto. */ | |
2144 | if (current_function_has_nonlocal_label | |
a1ed7bdb | 2145 | && qty[qtyno].n_calls_crossed > 0) |
2bbd3819 RS |
2146 | return -1; |
2147 | ||
2148 | if (accept_call_clobbered) | |
2149 | COPY_HARD_REG_SET (used, call_fixed_reg_set); | |
a1ed7bdb | 2150 | else if (qty[qtyno].n_calls_crossed == 0) |
2bbd3819 RS |
2151 | COPY_HARD_REG_SET (used, fixed_reg_set); |
2152 | else | |
2153 | COPY_HARD_REG_SET (used, call_used_reg_set); | |
2154 | ||
6cad67d2 | 2155 | if (accept_call_clobbered) |
c09be6c4 | 2156 | IOR_HARD_REG_SET (used, losing_caller_save_reg_set); |
6cad67d2 | 2157 | |
2bbd3819 RS |
2158 | for (ins = born_index; ins < dead_index; ins++) |
2159 | IOR_HARD_REG_SET (used, regs_live_at[ins]); | |
2160 | ||
2161 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); | |
2162 | ||
2163 | /* Don't use the frame pointer reg in local-alloc even if | |
2164 | we may omit the frame pointer, because if we do that and then we | |
2165 | need a frame pointer, reload won't know how to move the pseudo | |
2166 | to another hard reg. It can move only regs made by global-alloc. | |
2167 | ||
2168 | This is true of any register that can be eliminated. */ | |
2169 | #ifdef ELIMINABLE_REGS | |
b6a1cbae | 2170 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) |
2bbd3819 | 2171 | SET_HARD_REG_BIT (used, eliminables[i].from); |
c2618f05 DE |
2172 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
2173 | /* If FRAME_POINTER_REGNUM is not a real register, then protect the one | |
0f41302f | 2174 | that it might be eliminated into. */ |
c2618f05 DE |
2175 | SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); |
2176 | #endif | |
2bbd3819 RS |
2177 | #else |
2178 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); | |
2179 | #endif | |
2180 | ||
cff9f8d5 AH |
2181 | #ifdef CANNOT_CHANGE_MODE_CLASS |
2182 | cannot_change_mode_set_regs (&used, mode, qty[qtyno].first_reg); | |
0f64b8f6 RK |
2183 | #endif |
2184 | ||
2bbd3819 RS |
2185 | /* Normally, the registers that can be used for the first register in |
2186 | a multi-register quantity are the same as those that can be used for | |
2187 | subsequent registers. However, if just trying suggested registers, | |
2188 | restrict our consideration to them. If there are copy-suggested | |
2189 | register, try them. Otherwise, try the arithmetic-suggested | |
2190 | registers. */ | |
2191 | COPY_HARD_REG_SET (first_used, used); | |
2192 | ||
2193 | if (just_try_suggested) | |
2194 | { | |
a1ed7bdb JH |
2195 | if (qty_phys_num_copy_sugg[qtyno] != 0) |
2196 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]); | |
2bbd3819 | 2197 | else |
a1ed7bdb | 2198 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]); |
2bbd3819 RS |
2199 | } |
2200 | ||
2201 | /* If all registers are excluded, we can't do anything. */ | |
2202 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); | |
2203 | ||
2204 | /* If at least one would be suitable, test each hard reg. */ | |
2205 | ||
2206 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2207 | { | |
2208 | #ifdef REG_ALLOC_ORDER | |
2209 | int regno = reg_alloc_order[i]; | |
2210 | #else | |
2211 | int regno = i; | |
2212 | #endif | |
2213 | if (! TEST_HARD_REG_BIT (first_used, regno) | |
1e326708 | 2214 | && HARD_REGNO_MODE_OK (regno, mode) |
a1ed7bdb | 2215 | && (qty[qtyno].n_calls_crossed == 0 |
1e326708 MH |
2216 | || accept_call_clobbered |
2217 | || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
2bbd3819 | 2218 | { |
b3694847 SS |
2219 | int j; |
2220 | int size1 = HARD_REGNO_NREGS (regno, mode); | |
2bbd3819 RS |
2221 | for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); |
2222 | if (j == size1) | |
2223 | { | |
2224 | /* Mark that this register is in use between its birth and death | |
2225 | insns. */ | |
2226 | post_mark_life (regno, mode, 1, born_index, dead_index); | |
2227 | return regno; | |
2228 | } | |
2229 | #ifndef REG_ALLOC_ORDER | |
64e3a413 KH |
2230 | /* Skip starting points we know will lose. */ |
2231 | i += j; | |
2bbd3819 RS |
2232 | #endif |
2233 | } | |
2234 | } | |
2235 | ||
2236 | fail: | |
2bbd3819 RS |
2237 | /* If we are just trying suggested register, we have just tried copy- |
2238 | suggested registers, and there are arithmetic-suggested registers, | |
2239 | try them. */ | |
64e3a413 | 2240 | |
2bbd3819 RS |
2241 | /* If it would be profitable to allocate a call-clobbered register |
2242 | and save and restore it around calls, do that. */ | |
a1ed7bdb JH |
2243 | if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0 |
2244 | && qty_phys_num_sugg[qtyno] != 0) | |
2bbd3819 RS |
2245 | { |
2246 | /* Don't try the copy-suggested regs again. */ | |
a1ed7bdb JH |
2247 | qty_phys_num_copy_sugg[qtyno] = 0; |
2248 | return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1, | |
2bbd3819 RS |
2249 | born_index, dead_index); |
2250 | } | |
2251 | ||
e19f5192 RK |
2252 | /* We need not check to see if the current function has nonlocal |
2253 | labels because we don't put any pseudos that are live over calls in | |
2254 | registers in that case. */ | |
2255 | ||
2bbd3819 RS |
2256 | if (! accept_call_clobbered |
2257 | && flag_caller_saves | |
2258 | && ! just_try_suggested | |
a1ed7bdb | 2259 | && qty[qtyno].n_calls_crossed != 0 |
64e3a413 KH |
2260 | && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs, |
2261 | qty[qtyno].n_calls_crossed)) | |
2bbd3819 | 2262 | { |
a1ed7bdb | 2263 | i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index); |
2bbd3819 RS |
2264 | if (i >= 0) |
2265 | caller_save_needed = 1; | |
2266 | return i; | |
2267 | } | |
2268 | return -1; | |
2269 | } | |
2270 | \f | |
2271 | /* Mark that REGNO with machine-mode MODE is live starting from the current | |
cc2902df | 2272 | insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE |
2bbd3819 RS |
2273 | is zero). */ |
2274 | ||
2275 | static void | |
0c20a65f | 2276 | mark_life (int regno, enum machine_mode mode, int life) |
2bbd3819 | 2277 | { |
b3694847 | 2278 | int j = HARD_REGNO_NREGS (regno, mode); |
2bbd3819 RS |
2279 | if (life) |
2280 | while (--j >= 0) | |
2281 | SET_HARD_REG_BIT (regs_live, regno + j); | |
2282 | else | |
2283 | while (--j >= 0) | |
2284 | CLEAR_HARD_REG_BIT (regs_live, regno + j); | |
2285 | } | |
2286 | ||
2287 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE | |
cc2902df | 2288 | is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) |
2bbd3819 RS |
2289 | to insn number DEATH (exclusive). */ |
2290 | ||
2291 | static void | |
0c20a65f AJ |
2292 | post_mark_life (int regno, enum machine_mode mode, int life, int birth, |
2293 | int death) | |
2bbd3819 | 2294 | { |
b3694847 | 2295 | int j = HARD_REGNO_NREGS (regno, mode); |
2bbd3819 | 2296 | #ifdef HARD_REG_SET |
64e3a413 KH |
2297 | /* Declare it register if it's a scalar. */ |
2298 | register | |
2bbd3819 RS |
2299 | #endif |
2300 | HARD_REG_SET this_reg; | |
2301 | ||
2302 | CLEAR_HARD_REG_SET (this_reg); | |
2303 | while (--j >= 0) | |
2304 | SET_HARD_REG_BIT (this_reg, regno + j); | |
2305 | ||
2306 | if (life) | |
2307 | while (birth < death) | |
2308 | { | |
2309 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2310 | birth++; | |
2311 | } | |
2312 | else | |
2313 | while (birth < death) | |
2314 | { | |
2315 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2316 | birth++; | |
2317 | } | |
2318 | } | |
2319 | \f | |
2320 | /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 | |
2321 | is the register being clobbered, and R1 is a register being used in | |
2322 | the equivalent expression. | |
2323 | ||
2324 | If R1 dies in the block and has a REG_NO_CONFLICT note on every insn | |
2325 | in which it is used, return 1. | |
2326 | ||
2327 | Otherwise, return 0. */ | |
2328 | ||
2329 | static int | |
0c20a65f | 2330 | no_conflict_p (rtx insn, rtx r0 ATTRIBUTE_UNUSED, rtx r1) |
2bbd3819 RS |
2331 | { |
2332 | int ok = 0; | |
b1ec3c92 | 2333 | rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); |
2bbd3819 RS |
2334 | rtx p, last; |
2335 | ||
2336 | /* If R1 is a hard register, return 0 since we handle this case | |
2337 | when we scan the insns that actually use it. */ | |
2338 | ||
2339 | if (note == 0 | |
2340 | || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) | |
2341 | || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG | |
2342 | && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) | |
2343 | return 0; | |
2344 | ||
2345 | last = XEXP (note, 0); | |
2346 | ||
2347 | for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) | |
2c3c49de | 2348 | if (INSN_P (p)) |
2bbd3819 RS |
2349 | { |
2350 | if (find_reg_note (p, REG_DEAD, r1)) | |
2351 | ok = 1; | |
2352 | ||
8bb19658 JW |
2353 | /* There must be a REG_NO_CONFLICT note on every insn, otherwise |
2354 | some earlier optimization pass has inserted instructions into | |
2355 | the sequence, and it is not safe to perform this optimization. | |
2356 | Note that emit_no_conflict_block always ensures that this is | |
2357 | true when these sequences are created. */ | |
2358 | if (! find_reg_note (p, REG_NO_CONFLICT, r1)) | |
2bbd3819 RS |
2359 | return 0; |
2360 | } | |
64e3a413 | 2361 | |
2bbd3819 RS |
2362 | return ok; |
2363 | } | |
2364 | \f | |
3061cc54 RK |
2365 | /* Return the number of alternatives for which the constraint string P |
2366 | indicates that the operand must be equal to operand 0 and that no register | |
2367 | is acceptable. */ | |
2bbd3819 RS |
2368 | |
2369 | static int | |
0c20a65f | 2370 | requires_inout (const char *p) |
2bbd3819 RS |
2371 | { |
2372 | char c; | |
2373 | int found_zero = 0; | |
3061cc54 RK |
2374 | int reg_allowed = 0; |
2375 | int num_matching_alts = 0; | |
97488870 | 2376 | int len; |
2bbd3819 | 2377 | |
dd1b7476 | 2378 | for ( ; (c = *p); p += len) |
97488870 R |
2379 | { |
2380 | len = CONSTRAINT_LEN (c, p); | |
2381 | switch (c) | |
2382 | { | |
2383 | case '=': case '+': case '?': | |
2384 | case '#': case '&': case '!': | |
2385 | case '*': case '%': | |
2386 | case 'm': case '<': case '>': case 'V': case 'o': | |
2387 | case 'E': case 'F': case 'G': case 'H': | |
2388 | case 's': case 'i': case 'n': | |
2389 | case 'I': case 'J': case 'K': case 'L': | |
2390 | case 'M': case 'N': case 'O': case 'P': | |
2391 | case 'X': | |
2392 | /* These don't say anything we care about. */ | |
2393 | break; | |
2bbd3819 | 2394 | |
97488870 R |
2395 | case ',': |
2396 | if (found_zero && ! reg_allowed) | |
2397 | num_matching_alts++; | |
3061cc54 | 2398 | |
97488870 R |
2399 | found_zero = reg_allowed = 0; |
2400 | break; | |
3061cc54 | 2401 | |
97488870 R |
2402 | case '0': |
2403 | found_zero = 1; | |
2404 | break; | |
3061cc54 | 2405 | |
97488870 R |
2406 | case '1': case '2': case '3': case '4': case '5': |
2407 | case '6': case '7': case '8': case '9': | |
2408 | /* Skip the balance of the matching constraint. */ | |
2409 | do | |
2410 | p++; | |
2411 | while (ISDIGIT (*p)); | |
2412 | len = 0; | |
2413 | break; | |
84b72302 | 2414 | |
97488870 R |
2415 | default: |
2416 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS | |
2417 | && !EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
2418 | break; | |
2419 | /* FALLTHRU */ | |
2420 | case 'p': | |
2421 | case 'g': case 'r': | |
2422 | reg_allowed = 1; | |
c2cba7a9 | 2423 | break; |
97488870 R |
2424 | } |
2425 | } | |
2bbd3819 | 2426 | |
3061cc54 RK |
2427 | if (found_zero && ! reg_allowed) |
2428 | num_matching_alts++; | |
2429 | ||
2430 | return num_matching_alts; | |
2bbd3819 RS |
2431 | } |
2432 | \f | |
2433 | void | |
0c20a65f | 2434 | dump_local_alloc (FILE *file) |
2bbd3819 | 2435 | { |
b3694847 | 2436 | int i; |
2bbd3819 RS |
2437 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
2438 | if (reg_renumber[i] != -1) | |
2439 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); | |
2440 | } |