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2bbd3819 | 1 | /* Allocate registers within a basic block, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
fe9565ed | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
2bbd3819 | 4 | |
1322177d | 5 | This file is part of GCC. |
2bbd3819 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
2bbd3819 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
2bbd3819 RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d | 18 | along with GCC; see the file COPYING. If not, write to the Free |
366ccddb KC |
19 | Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
2bbd3819 | 21 | |
2bbd3819 RS |
22 | /* Allocation of hard register numbers to pseudo registers is done in |
23 | two passes. In this pass we consider only regs that are born and | |
24 | die once within one basic block. We do this one basic block at a | |
25 | time. Then the next pass allocates the registers that remain. | |
26 | Two passes are used because this pass uses methods that work only | |
27 | on linear code, but that do a better job than the general methods | |
28 | used in global_alloc, and more quickly too. | |
29 | ||
30 | The assignments made are recorded in the vector reg_renumber | |
31 | whose space is allocated here. The rtl code itself is not altered. | |
32 | ||
33 | We assign each instruction in the basic block a number | |
34 | which is its order from the beginning of the block. | |
35 | Then we can represent the lifetime of a pseudo register with | |
36 | a pair of numbers, and check for conflicts easily. | |
37 | We can record the availability of hard registers with a | |
38 | HARD_REG_SET for each instruction. The HARD_REG_SET | |
39 | contains 0 or 1 for each hard reg. | |
40 | ||
41 | To avoid register shuffling, we tie registers together when one | |
42 | dies by being copied into another, or dies in an instruction that | |
43 | does arithmetic to produce another. The tied registers are | |
44 | allocated as one. Registers with different reg class preferences | |
45 | can never be tied unless the class preferred by one is a subclass | |
46 | of the one preferred by the other. | |
47 | ||
48 | Tying is represented with "quantity numbers". | |
49 | A non-tied register is given a new quantity number. | |
50 | Tied registers have the same quantity number. | |
64e3a413 | 51 | |
2bbd3819 RS |
52 | We have provision to exempt registers, even when they are contained |
53 | within the block, that can be tied to others that are not contained in it. | |
54 | This is so that global_alloc could process them both and tie them then. | |
55 | But this is currently disabled since tying in global_alloc is not | |
56 | yet implemented. */ | |
57 | ||
a300b8d9 JW |
58 | /* Pseudos allocated here can be reallocated by global.c if the hard register |
59 | is used as a spill register. Currently we don't allocate such pseudos | |
6cad67d2 JL |
60 | here if their preferred class is likely to be used by spills. */ |
61 | ||
2bbd3819 | 62 | #include "config.h" |
670ee920 | 63 | #include "system.h" |
4977bab6 ZW |
64 | #include "coretypes.h" |
65 | #include "tm.h" | |
cff9f8d5 | 66 | #include "hard-reg-set.h" |
2bbd3819 | 67 | #include "rtl.h" |
6baf1cc8 | 68 | #include "tm_p.h" |
2bbd3819 | 69 | #include "flags.h" |
2bbd3819 | 70 | #include "regs.h" |
49ad7cfa | 71 | #include "function.h" |
2bbd3819 | 72 | #include "insn-config.h" |
624a8b3a | 73 | #include "insn-attr.h" |
2bbd3819 RS |
74 | #include "recog.h" |
75 | #include "output.h" | |
2e107e9e | 76 | #include "toplev.h" |
a4d3961a | 77 | #include "except.h" |
902197eb | 78 | #include "integrate.h" |
d7f88d86 BS |
79 | #include "reload.h" |
80 | #include "ggc.h" | |
2bbd3819 RS |
81 | \f |
82 | /* Next quantity number available for allocation. */ | |
83 | ||
84 | static int next_qty; | |
85 | ||
f5143c46 | 86 | /* Information we maintain about each quantity. */ |
a1ed7bdb JH |
87 | struct qty |
88 | { | |
89 | /* The number of refs to quantity Q. */ | |
2bbd3819 | 90 | |
a1ed7bdb | 91 | int n_refs; |
2bbd3819 | 92 | |
b2aec5c0 JH |
93 | /* The frequency of uses of quantity Q. */ |
94 | ||
95 | int freq; | |
96 | ||
a1ed7bdb JH |
97 | /* Insn number (counting from head of basic block) |
98 | where quantity Q was born. -1 if birth has not been recorded. */ | |
2bbd3819 | 99 | |
a1ed7bdb | 100 | int birth; |
2bbd3819 | 101 | |
a1ed7bdb JH |
102 | /* Insn number (counting from head of basic block) |
103 | where given quantity died. Due to the way tying is done, | |
104 | and the fact that we consider in this pass only regs that die but once, | |
105 | a quantity can die only once. Each quantity's life span | |
106 | is a set of consecutive insns. -1 if death has not been recorded. */ | |
2bbd3819 | 107 | |
a1ed7bdb | 108 | int death; |
2bbd3819 | 109 | |
a1ed7bdb JH |
110 | /* Number of words needed to hold the data in given quantity. |
111 | This depends on its machine mode. It is used for these purposes: | |
ba228239 | 112 | 1. It is used in computing the relative importance of qtys, |
a1ed7bdb JH |
113 | which determines the order in which we look for regs for them. |
114 | 2. It is used in rules that prevent tying several registers of | |
115 | different sizes in a way that is geometrically impossible | |
116 | (see combine_regs). */ | |
2bbd3819 | 117 | |
a1ed7bdb | 118 | int size; |
2bbd3819 | 119 | |
a1ed7bdb | 120 | /* Number of times a reg tied to given qty lives across a CALL_INSN. */ |
2bbd3819 | 121 | |
a1ed7bdb | 122 | int n_calls_crossed; |
2bbd3819 | 123 | |
a1ed7bdb JH |
124 | /* The register number of one pseudo register whose reg_qty value is Q. |
125 | This register should be the head of the chain | |
126 | maintained in reg_next_in_qty. */ | |
2bbd3819 | 127 | |
a1ed7bdb | 128 | int first_reg; |
2bbd3819 | 129 | |
a1ed7bdb JH |
130 | /* Reg class contained in (smaller than) the preferred classes of all |
131 | the pseudo regs that are tied in given quantity. | |
132 | This is the preferred class for allocating that quantity. */ | |
133 | ||
134 | enum reg_class min_class; | |
2bbd3819 | 135 | |
a1ed7bdb JH |
136 | /* Register class within which we allocate given qty if we can't get |
137 | its preferred class. */ | |
2bbd3819 | 138 | |
a1ed7bdb | 139 | enum reg_class alternate_class; |
2bbd3819 | 140 | |
a1ed7bdb JH |
141 | /* This holds the mode of the registers that are tied to given qty, |
142 | or VOIDmode if registers with differing modes are tied together. */ | |
2bbd3819 | 143 | |
a1ed7bdb | 144 | enum machine_mode mode; |
2bbd3819 | 145 | |
a1ed7bdb JH |
146 | /* the hard reg number chosen for given quantity, |
147 | or -1 if none was found. */ | |
2bbd3819 | 148 | |
a1ed7bdb | 149 | short phys_reg; |
a1ed7bdb | 150 | }; |
2bbd3819 | 151 | |
a1ed7bdb | 152 | static struct qty *qty; |
2bbd3819 | 153 | |
a1ed7bdb | 154 | /* These fields are kept separately to speedup their clearing. */ |
2bbd3819 | 155 | |
a1ed7bdb JH |
156 | /* We maintain two hard register sets that indicate suggested hard registers |
157 | for each quantity. The first, phys_copy_sugg, contains hard registers | |
158 | that are tied to the quantity by a simple copy. The second contains all | |
159 | hard registers that are tied to the quantity via an arithmetic operation. | |
2bbd3819 | 160 | |
a1ed7bdb JH |
161 | The former register set is given priority for allocation. This tends to |
162 | eliminate copy insns. */ | |
2bbd3819 | 163 | |
a1ed7bdb JH |
164 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
165 | copy insns. */ | |
2bbd3819 | 166 | |
a1ed7bdb | 167 | static HARD_REG_SET *qty_phys_copy_sugg; |
2bbd3819 | 168 | |
a1ed7bdb JH |
169 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
170 | arithmetic insns. */ | |
171 | ||
172 | static HARD_REG_SET *qty_phys_sugg; | |
173 | ||
174 | /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ | |
2bbd3819 | 175 | |
a1ed7bdb | 176 | static short *qty_phys_num_copy_sugg; |
0f64b8f6 | 177 | |
a1ed7bdb | 178 | /* Element Q is the number of suggested registers in qty_phys_sugg. */ |
0f64b8f6 | 179 | |
a1ed7bdb | 180 | static short *qty_phys_num_sugg; |
2bbd3819 | 181 | |
2bbd3819 RS |
182 | /* If (REG N) has been assigned a quantity number, is a register number |
183 | of another register assigned the same quantity number, or -1 for the | |
a1ed7bdb | 184 | end of the chain. qty->first_reg point to the head of this chain. */ |
2bbd3819 | 185 | |
aabf56ce | 186 | static int *reg_next_in_qty; |
2bbd3819 RS |
187 | |
188 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg | |
189 | if it is >= 0, | |
190 | of -1 if this register cannot be allocated by local-alloc, | |
191 | or -2 if not known yet. | |
192 | ||
193 | Note that if we see a use or death of pseudo register N with | |
194 | reg_qty[N] == -2, register N must be local to the current block. If | |
195 | it were used in more than one block, we would have reg_qty[N] == -1. | |
196 | This relies on the fact that if reg_basic_block[N] is >= 0, register N | |
197 | will not appear in any other block. We save a considerable number of | |
198 | tests by exploiting this. | |
199 | ||
200 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not | |
201 | be referenced. */ | |
202 | ||
203 | static int *reg_qty; | |
204 | ||
205 | /* The offset (in words) of register N within its quantity. | |
206 | This can be nonzero if register N is SImode, and has been tied | |
207 | to a subreg of a DImode register. */ | |
208 | ||
209 | static char *reg_offset; | |
210 | ||
211 | /* Vector of substitutions of register numbers, | |
212 | used to map pseudo regs into hardware regs. | |
213 | This is set up as a result of register allocation. | |
214 | Element N is the hard reg assigned to pseudo reg N, | |
215 | or is -1 if no hard reg was assigned. | |
216 | If N is a hard reg number, element N is N. */ | |
217 | ||
218 | short *reg_renumber; | |
219 | ||
220 | /* Set of hard registers live at the current point in the scan | |
221 | of the instructions in a basic block. */ | |
222 | ||
223 | static HARD_REG_SET regs_live; | |
224 | ||
225 | /* Each set of hard registers indicates registers live at a particular | |
226 | point in the basic block. For N even, regs_live_at[N] says which | |
227 | hard registers are needed *after* insn N/2 (i.e., they may not | |
228 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. | |
229 | ||
230 | If an object is to conflict with the inputs of insn J but not the | |
231 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, | |
232 | if it is to conflict with the outputs of insn J but not the inputs of | |
233 | insn J + 1, it is said to die at index J*2 + 1. */ | |
234 | ||
235 | static HARD_REG_SET *regs_live_at; | |
236 | ||
237 | /* Communicate local vars `insn_number' and `insn' | |
238 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ | |
239 | static int this_insn_number; | |
240 | static rtx this_insn; | |
241 | ||
bf6d9fd7 JW |
242 | struct equivalence |
243 | { | |
244 | /* Set when an attempt should be made to replace a register | |
5ca9299f | 245 | with the associated src_p entry. */ |
bf6d9fd7 JW |
246 | |
247 | char replace; | |
248 | ||
249 | /* Set when a REG_EQUIV note is found or created. Use to | |
250 | keep track of what memory accesses might be created later, | |
251 | e.g. by reload. */ | |
252 | ||
253 | rtx replacement; | |
68342d36 | 254 | |
5ca9299f | 255 | rtx *src_p; |
c25a4c25 | 256 | |
bf6d9fd7 JW |
257 | /* Loop depth is used to recognize equivalences which appear |
258 | to be present within the same loop (or in an inner loop). */ | |
259 | ||
260 | int loop_depth; | |
261 | ||
262 | /* The list of each instruction which initializes this register. */ | |
263 | ||
264 | rtx init_insns; | |
d7f88d86 BS |
265 | |
266 | /* Nonzero if this had a preexisting REG_EQUIV note. */ | |
267 | ||
268 | int is_arg_equivalence; | |
bf6d9fd7 JW |
269 | }; |
270 | ||
271 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
272 | structure for that register. */ | |
273 | ||
274 | static struct equivalence *reg_equiv; | |
135eb61c | 275 | |
3f1b9b1b JL |
276 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
277 | static int recorded_label_ref; | |
278 | ||
0c20a65f AJ |
279 | static void alloc_qty (int, enum machine_mode, int, int); |
280 | static void validate_equiv_mem_from_store (rtx, rtx, void *); | |
281 | static int validate_equiv_mem (rtx, rtx, rtx); | |
282 | static int equiv_init_varies_p (rtx); | |
283 | static int equiv_init_movable_p (rtx, int); | |
284 | static int contains_replace_regs (rtx); | |
285 | static int memref_referenced_p (rtx, rtx); | |
286 | static int memref_used_between_p (rtx, rtx, rtx); | |
287 | static void update_equiv_regs (void); | |
288 | static void no_equiv (rtx, rtx, void *); | |
289 | static void block_alloc (int); | |
290 | static int qty_sugg_compare (int, int); | |
291 | static int qty_sugg_compare_1 (const void *, const void *); | |
292 | static int qty_compare (int, int); | |
293 | static int qty_compare_1 (const void *, const void *); | |
294 | static int combine_regs (rtx, rtx, int, int, rtx, int); | |
295 | static int reg_meets_class_p (int, enum reg_class); | |
296 | static void update_qty_class (int, int); | |
297 | static void reg_is_set (rtx, rtx, void *); | |
298 | static void reg_is_born (rtx, int); | |
299 | static void wipe_dead_reg (rtx, int); | |
300 | static int find_free_reg (enum reg_class, enum machine_mode, int, int, int, | |
301 | int, int); | |
302 | static void mark_life (int, enum machine_mode, int); | |
303 | static void post_mark_life (int, enum machine_mode, int, int, int); | |
304 | static int no_conflict_p (rtx, rtx, rtx); | |
305 | static int requires_inout (const char *); | |
2bbd3819 RS |
306 | \f |
307 | /* Allocate a new quantity (new within current basic block) | |
308 | for register number REGNO which is born at index BIRTH | |
309 | within the block. MODE and SIZE are info on reg REGNO. */ | |
310 | ||
311 | static void | |
0c20a65f | 312 | alloc_qty (int regno, enum machine_mode mode, int size, int birth) |
2bbd3819 | 313 | { |
b3694847 | 314 | int qtyno = next_qty++; |
2bbd3819 | 315 | |
a1ed7bdb | 316 | reg_qty[regno] = qtyno; |
2bbd3819 RS |
317 | reg_offset[regno] = 0; |
318 | reg_next_in_qty[regno] = -1; | |
319 | ||
a1ed7bdb JH |
320 | qty[qtyno].first_reg = regno; |
321 | qty[qtyno].size = size; | |
322 | qty[qtyno].mode = mode; | |
323 | qty[qtyno].birth = birth; | |
324 | qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno); | |
325 | qty[qtyno].min_class = reg_preferred_class (regno); | |
326 | qty[qtyno].alternate_class = reg_alternate_class (regno); | |
327 | qty[qtyno].n_refs = REG_N_REFS (regno); | |
b2aec5c0 | 328 | qty[qtyno].freq = REG_FREQ (regno); |
2bbd3819 RS |
329 | } |
330 | \f | |
2bbd3819 RS |
331 | /* Main entry point of this file. */ |
332 | ||
3f1b9b1b | 333 | int |
0c20a65f | 334 | local_alloc (void) |
2bbd3819 | 335 | { |
e0082a72 | 336 | int i; |
2bbd3819 | 337 | int max_qty; |
e0082a72 | 338 | basic_block b; |
2bbd3819 | 339 | |
3f1b9b1b JL |
340 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
341 | that we know if the jump optimizer needs to be rerun. */ | |
342 | recorded_label_ref = 0; | |
343 | ||
2bbd3819 RS |
344 | /* Leaf functions and non-leaf functions have different needs. |
345 | If defined, let the machine say what kind of ordering we | |
346 | should use. */ | |
347 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC | |
348 | ORDER_REGS_FOR_LOCAL_ALLOC; | |
349 | #endif | |
350 | ||
351 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected | |
352 | registers. */ | |
d7f88d86 | 353 | update_equiv_regs (); |
2bbd3819 RS |
354 | |
355 | /* This sets the maximum number of quantities we can have. Quantity | |
34f89b5f BS |
356 | numbers start at zero and we can have one for each pseudo. */ |
357 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER); | |
2bbd3819 RS |
358 | |
359 | /* Allocate vectors of temporary data. | |
360 | See the declarations of these variables, above, | |
361 | for what they mean. */ | |
362 | ||
703ad42b KG |
363 | qty = xmalloc (max_qty * sizeof (struct qty)); |
364 | qty_phys_copy_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET)); | |
365 | qty_phys_num_copy_sugg = xmalloc (max_qty * sizeof (short)); | |
366 | qty_phys_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET)); | |
367 | qty_phys_num_sugg = xmalloc (max_qty * sizeof (short)); | |
2bbd3819 | 368 | |
703ad42b KG |
369 | reg_qty = xmalloc (max_regno * sizeof (int)); |
370 | reg_offset = xmalloc (max_regno * sizeof (char)); | |
371 | reg_next_in_qty = xmalloc (max_regno * sizeof (int)); | |
2bbd3819 | 372 | |
2bbd3819 RS |
373 | /* Determine which pseudo-registers can be allocated by local-alloc. |
374 | In general, these are the registers used only in a single block and | |
611bbf2a | 375 | which only die once. |
2bbd3819 RS |
376 | |
377 | We need not be concerned with which block actually uses the register | |
378 | since we will never see it outside that block. */ | |
379 | ||
380 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
381 | { | |
611bbf2a | 382 | if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1) |
2bbd3819 RS |
383 | reg_qty[i] = -2; |
384 | else | |
385 | reg_qty[i] = -1; | |
386 | } | |
387 | ||
388 | /* Force loop below to initialize entire quantity array. */ | |
389 | next_qty = max_qty; | |
390 | ||
391 | /* Allocate each block's local registers, block by block. */ | |
392 | ||
e0082a72 | 393 | FOR_EACH_BB (b) |
2bbd3819 RS |
394 | { |
395 | /* NEXT_QTY indicates which elements of the `qty_...' | |
396 | vectors might need to be initialized because they were used | |
397 | for the previous block; it is set to the entire array before | |
398 | block 0. Initialize those, with explicit loop if there are few, | |
399 | else with bzero and bcopy. Do not initialize vectors that are | |
400 | explicit set by `alloc_qty'. */ | |
401 | ||
402 | if (next_qty < 6) | |
403 | { | |
404 | for (i = 0; i < next_qty; i++) | |
405 | { | |
2bbd3819 | 406 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); |
51b86d8b | 407 | qty_phys_num_copy_sugg[i] = 0; |
2bbd3819 | 408 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); |
51b86d8b | 409 | qty_phys_num_sugg[i] = 0; |
2bbd3819 RS |
410 | } |
411 | } | |
412 | else | |
413 | { | |
414 | #define CLEAR(vector) \ | |
703ad42b | 415 | memset ((vector), 0, (sizeof (*(vector))) * next_qty); |
2bbd3819 | 416 | |
2bbd3819 | 417 | CLEAR (qty_phys_copy_sugg); |
51b86d8b | 418 | CLEAR (qty_phys_num_copy_sugg); |
2bbd3819 | 419 | CLEAR (qty_phys_sugg); |
51b86d8b | 420 | CLEAR (qty_phys_num_sugg); |
2bbd3819 RS |
421 | } |
422 | ||
423 | next_qty = 0; | |
424 | ||
e0082a72 | 425 | block_alloc (b->index); |
2bbd3819 | 426 | } |
83cbe7e4 | 427 | |
a1ed7bdb | 428 | free (qty); |
75c6bd46 RH |
429 | free (qty_phys_copy_sugg); |
430 | free (qty_phys_num_copy_sugg); | |
431 | free (qty_phys_sugg); | |
e7749837 | 432 | free (qty_phys_num_sugg); |
75c6bd46 | 433 | |
83cbe7e4 RH |
434 | free (reg_qty); |
435 | free (reg_offset); | |
436 | free (reg_next_in_qty); | |
75c6bd46 | 437 | |
3f1b9b1b | 438 | return recorded_label_ref; |
2bbd3819 RS |
439 | } |
440 | \f | |
2bbd3819 RS |
441 | /* Used for communication between the following two functions: contains |
442 | a MEM that we wish to ensure remains unchanged. */ | |
443 | static rtx equiv_mem; | |
444 | ||
445 | /* Set nonzero if EQUIV_MEM is modified. */ | |
446 | static int equiv_mem_modified; | |
447 | ||
448 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
449 | Called via note_stores. */ | |
450 | ||
451 | static void | |
0c20a65f AJ |
452 | validate_equiv_mem_from_store (rtx dest, rtx set ATTRIBUTE_UNUSED, |
453 | void *data ATTRIBUTE_UNUSED) | |
2bbd3819 | 454 | { |
f8cfc6aa | 455 | if ((REG_P (dest) |
2bbd3819 | 456 | && reg_overlap_mentioned_p (dest, equiv_mem)) |
3c0cb5de | 457 | || (MEM_P (dest) |
9ae8ffe7 | 458 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) |
2bbd3819 RS |
459 | equiv_mem_modified = 1; |
460 | } | |
461 | ||
462 | /* Verify that no store between START and the death of REG invalidates | |
463 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
464 | by storing into an overlapping memory location, or with a non-const | |
465 | CALL_INSN. | |
466 | ||
467 | Return 1 if MEMREF remains valid. */ | |
468 | ||
469 | static int | |
0c20a65f | 470 | validate_equiv_mem (rtx start, rtx reg, rtx memref) |
2bbd3819 RS |
471 | { |
472 | rtx insn; | |
473 | rtx note; | |
474 | ||
475 | equiv_mem = memref; | |
476 | equiv_mem_modified = 0; | |
477 | ||
478 | /* If the memory reference has side effects or is volatile, it isn't a | |
479 | valid equivalence. */ | |
480 | if (side_effects_p (memref)) | |
481 | return 0; | |
482 | ||
483 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
484 | { | |
2c3c49de | 485 | if (! INSN_P (insn)) |
2bbd3819 RS |
486 | continue; |
487 | ||
488 | if (find_reg_note (insn, REG_DEAD, reg)) | |
489 | return 1; | |
490 | ||
389fdba0 | 491 | if (CALL_P (insn) && ! MEM_READONLY_P (memref) |
24a28584 | 492 | && ! CONST_OR_PURE_CALL_P (insn)) |
2bbd3819 RS |
493 | return 0; |
494 | ||
84832317 | 495 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); |
2bbd3819 RS |
496 | |
497 | /* If a register mentioned in MEMREF is modified via an | |
498 | auto-increment, we lose the equivalence. Do the same if one | |
499 | dies; although we could extend the life, it doesn't seem worth | |
500 | the trouble. */ | |
501 | ||
502 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
503 | if ((REG_NOTE_KIND (note) == REG_INC | |
504 | || REG_NOTE_KIND (note) == REG_DEAD) | |
f8cfc6aa | 505 | && REG_P (XEXP (note, 0)) |
2bbd3819 RS |
506 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) |
507 | return 0; | |
508 | } | |
509 | ||
510 | return 0; | |
511 | } | |
a1729519 | 512 | |
bf6d9fd7 JW |
513 | /* Returns zero if X is known to be invariant. */ |
514 | ||
515 | static int | |
0c20a65f | 516 | equiv_init_varies_p (rtx x) |
bf6d9fd7 | 517 | { |
b3694847 SS |
518 | RTX_CODE code = GET_CODE (x); |
519 | int i; | |
520 | const char *fmt; | |
bf6d9fd7 JW |
521 | |
522 | switch (code) | |
523 | { | |
524 | case MEM: | |
389fdba0 | 525 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); |
bf6d9fd7 | 526 | |
bf6d9fd7 JW |
527 | case CONST: |
528 | case CONST_INT: | |
529 | case CONST_DOUBLE: | |
69ef87e2 | 530 | case CONST_VECTOR: |
bf6d9fd7 JW |
531 | case SYMBOL_REF: |
532 | case LABEL_REF: | |
533 | return 0; | |
534 | ||
535 | case REG: | |
e38fe8e0 | 536 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); |
bf6d9fd7 JW |
537 | |
538 | case ASM_OPERANDS: | |
539 | if (MEM_VOLATILE_P (x)) | |
540 | return 1; | |
541 | ||
5d3cc252 | 542 | /* Fall through. */ |
bf6d9fd7 JW |
543 | |
544 | default: | |
545 | break; | |
546 | } | |
547 | ||
548 | fmt = GET_RTX_FORMAT (code); | |
549 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
550 | if (fmt[i] == 'e') | |
551 | { | |
552 | if (equiv_init_varies_p (XEXP (x, i))) | |
553 | return 1; | |
554 | } | |
555 | else if (fmt[i] == 'E') | |
556 | { | |
557 | int j; | |
558 | for (j = 0; j < XVECLEN (x, i); j++) | |
559 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
560 | return 1; | |
561 | } | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
cc2902df | 566 | /* Returns nonzero if X (used to initialize register REGNO) is movable. |
bf6d9fd7 JW |
567 | X is only movable if the registers it uses have equivalent initializations |
568 | which appear to be within the same loop (or in an inner loop) and movable | |
569 | or if they are not candidates for local_alloc and don't vary. */ | |
a1729519 JW |
570 | |
571 | static int | |
0c20a65f | 572 | equiv_init_movable_p (rtx x, int regno) |
bf6d9fd7 JW |
573 | { |
574 | int i, j; | |
575 | const char *fmt; | |
576 | enum rtx_code code = GET_CODE (x); | |
577 | ||
578 | switch (code) | |
579 | { | |
580 | case SET: | |
581 | return equiv_init_movable_p (SET_SRC (x), regno); | |
582 | ||
d9068c61 | 583 | case CC0: |
bf6d9fd7 JW |
584 | case CLOBBER: |
585 | return 0; | |
586 | ||
587 | case PRE_INC: | |
588 | case PRE_DEC: | |
589 | case POST_INC: | |
590 | case POST_DEC: | |
591 | case PRE_MODIFY: | |
592 | case POST_MODIFY: | |
593 | return 0; | |
594 | ||
595 | case REG: | |
596 | return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth | |
597 | && reg_equiv[REGNO (x)].replace) | |
e38fe8e0 | 598 | || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0)); |
bf6d9fd7 JW |
599 | |
600 | case UNSPEC_VOLATILE: | |
601 | return 0; | |
602 | ||
603 | case ASM_OPERANDS: | |
604 | if (MEM_VOLATILE_P (x)) | |
605 | return 0; | |
606 | ||
5d3cc252 | 607 | /* Fall through. */ |
bf6d9fd7 JW |
608 | |
609 | default: | |
610 | break; | |
611 | } | |
612 | ||
613 | fmt = GET_RTX_FORMAT (code); | |
614 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
615 | switch (fmt[i]) | |
616 | { | |
617 | case 'e': | |
618 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
619 | return 0; | |
620 | break; | |
621 | case 'E': | |
622 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
623 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
624 | return 0; | |
625 | break; | |
626 | } | |
627 | ||
628 | return 1; | |
629 | } | |
630 | ||
631 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */ | |
632 | ||
633 | static int | |
0c20a65f | 634 | contains_replace_regs (rtx x) |
a1729519 JW |
635 | { |
636 | int i, j; | |
6f7d635c | 637 | const char *fmt; |
a1729519 JW |
638 | enum rtx_code code = GET_CODE (x); |
639 | ||
640 | switch (code) | |
641 | { | |
642 | case CONST_INT: | |
643 | case CONST: | |
644 | case LABEL_REF: | |
645 | case SYMBOL_REF: | |
646 | case CONST_DOUBLE: | |
69ef87e2 | 647 | case CONST_VECTOR: |
a1729519 JW |
648 | case PC: |
649 | case CC0: | |
650 | case HIGH: | |
a1729519 JW |
651 | return 0; |
652 | ||
653 | case REG: | |
bf6d9fd7 | 654 | return reg_equiv[REGNO (x)].replace; |
1d300e19 KG |
655 | |
656 | default: | |
657 | break; | |
a1729519 JW |
658 | } |
659 | ||
660 | fmt = GET_RTX_FORMAT (code); | |
661 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
662 | switch (fmt[i]) | |
663 | { | |
664 | case 'e': | |
bf6d9fd7 | 665 | if (contains_replace_regs (XEXP (x, i))) |
a1729519 JW |
666 | return 1; |
667 | break; | |
668 | case 'E': | |
669 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
bf6d9fd7 | 670 | if (contains_replace_regs (XVECEXP (x, i, j))) |
a1729519 JW |
671 | return 1; |
672 | break; | |
673 | } | |
674 | ||
675 | return 0; | |
676 | } | |
2bbd3819 RS |
677 | \f |
678 | /* TRUE if X references a memory location that would be affected by a store | |
679 | to MEMREF. */ | |
680 | ||
681 | static int | |
0c20a65f | 682 | memref_referenced_p (rtx memref, rtx x) |
2bbd3819 RS |
683 | { |
684 | int i, j; | |
6f7d635c | 685 | const char *fmt; |
2bbd3819 RS |
686 | enum rtx_code code = GET_CODE (x); |
687 | ||
688 | switch (code) | |
689 | { | |
2bbd3819 RS |
690 | case CONST_INT: |
691 | case CONST: | |
692 | case LABEL_REF: | |
693 | case SYMBOL_REF: | |
694 | case CONST_DOUBLE: | |
69ef87e2 | 695 | case CONST_VECTOR: |
2bbd3819 RS |
696 | case PC: |
697 | case CC0: | |
698 | case HIGH: | |
699 | case LO_SUM: | |
700 | return 0; | |
701 | ||
c25a4c25 | 702 | case REG: |
bf6d9fd7 | 703 | return (reg_equiv[REGNO (x)].replacement |
3298a1b1 | 704 | && memref_referenced_p (memref, |
bf6d9fd7 | 705 | reg_equiv[REGNO (x)].replacement)); |
c25a4c25 | 706 | |
2bbd3819 | 707 | case MEM: |
9ae8ffe7 | 708 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) |
2bbd3819 RS |
709 | return 1; |
710 | break; | |
711 | ||
712 | case SET: | |
713 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
714 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
3c0cb5de | 715 | if (MEM_P (SET_DEST (x))) |
2bbd3819 RS |
716 | { |
717 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
718 | return 1; | |
719 | } | |
720 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
721 | return 1; | |
722 | ||
723 | return memref_referenced_p (memref, SET_SRC (x)); | |
64e3a413 | 724 | |
e9a25f70 JL |
725 | default: |
726 | break; | |
2bbd3819 RS |
727 | } |
728 | ||
729 | fmt = GET_RTX_FORMAT (code); | |
730 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
731 | switch (fmt[i]) | |
732 | { | |
733 | case 'e': | |
734 | if (memref_referenced_p (memref, XEXP (x, i))) | |
735 | return 1; | |
736 | break; | |
737 | case 'E': | |
738 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
739 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
740 | return 1; | |
741 | break; | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | /* TRUE if some insn in the range (START, END] references a memory location | |
748 | that would be affected by a store to MEMREF. */ | |
749 | ||
750 | static int | |
0c20a65f | 751 | memref_used_between_p (rtx memref, rtx start, rtx end) |
2bbd3819 RS |
752 | { |
753 | rtx insn; | |
754 | ||
755 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
756 | insn = NEXT_INSN (insn)) | |
2c3c49de | 757 | if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn))) |
2bbd3819 RS |
758 | return 1; |
759 | ||
760 | return 0; | |
761 | } | |
762 | \f | |
2bbd3819 RS |
763 | /* Find registers that are equivalent to a single value throughout the |
764 | compilation (either because they can be referenced in memory or are set once | |
765 | from a single constant). Lower their priority for a register. | |
766 | ||
767 | If such a register is only referenced once, try substituting its value | |
768 | into the using insn. If it succeeds, we can eliminate the register | |
d7f88d86 BS |
769 | completely. |
770 | ||
771 | Initialize the REG_EQUIV_INIT array of initializing insns. */ | |
2bbd3819 RS |
772 | |
773 | static void | |
0c20a65f | 774 | update_equiv_regs (void) |
2bbd3819 | 775 | { |
2bbd3819 | 776 | rtx insn; |
e0082a72 | 777 | basic_block bb; |
bf6d9fd7 | 778 | int loop_depth; |
25e4379f MM |
779 | regset_head cleared_regs; |
780 | int clear_regnos = 0; | |
2bbd3819 | 781 | |
703ad42b | 782 | reg_equiv = xcalloc (max_regno, sizeof *reg_equiv); |
25e4379f | 783 | INIT_REG_SET (&cleared_regs); |
d7f88d86 BS |
784 | reg_equiv_init = ggc_alloc_cleared (max_regno * sizeof (rtx)); |
785 | reg_equiv_init_size = max_regno; | |
2bbd3819 RS |
786 | |
787 | init_alias_analysis (); | |
788 | ||
2bbd3819 RS |
789 | /* Scan the insns and find which registers have equivalences. Do this |
790 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
791 | a register can be set below its use. */ | |
e0082a72 | 792 | FOR_EACH_BB (bb) |
2bbd3819 | 793 | { |
2ab0437e | 794 | loop_depth = bb->loop_depth; |
2bbd3819 | 795 | |
a813c111 SB |
796 | for (insn = BB_HEAD (bb); |
797 | insn != NEXT_INSN (BB_END (bb)); | |
798 | insn = NEXT_INSN (insn)) | |
2bbd3819 | 799 | { |
2ab0437e JH |
800 | rtx note; |
801 | rtx set; | |
802 | rtx dest, src; | |
803 | int regno; | |
2bbd3819 | 804 | |
2ab0437e JH |
805 | if (! INSN_P (insn)) |
806 | continue; | |
135eb61c | 807 | |
2ab0437e JH |
808 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
809 | if (REG_NOTE_KIND (note) == REG_INC) | |
810 | no_equiv (XEXP (note, 0), note, NULL); | |
135eb61c | 811 | |
2ab0437e | 812 | set = single_set (insn); |
135eb61c | 813 | |
2ab0437e JH |
814 | /* If this insn contains more (or less) than a single SET, |
815 | only mark all destinations as having no known equivalence. */ | |
816 | if (set == 0) | |
135eb61c | 817 | { |
2ab0437e JH |
818 | note_stores (PATTERN (insn), no_equiv, NULL); |
819 | continue; | |
135eb61c | 820 | } |
2ab0437e JH |
821 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
822 | { | |
823 | int i; | |
135eb61c | 824 | |
2ab0437e JH |
825 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
826 | { | |
827 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
828 | if (part != set) | |
829 | note_stores (part, no_equiv, NULL); | |
830 | } | |
831 | } | |
2bbd3819 | 832 | |
2ab0437e JH |
833 | dest = SET_DEST (set); |
834 | src = SET_SRC (set); | |
835 | ||
d7f88d86 BS |
836 | /* See if this is setting up the equivalence between an argument |
837 | register and its stack slot. */ | |
838 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
839 | if (note) | |
2ab0437e | 840 | { |
d7f88d86 BS |
841 | gcc_assert (REG_P (dest)); |
842 | regno = REGNO (dest); | |
843 | ||
844 | /* Note that we don't want to clear reg_equiv_init even if there | |
845 | are multiple sets of this register. */ | |
846 | reg_equiv[regno].is_arg_equivalence = 1; | |
847 | ||
848 | /* Record for reload that this is an equivalencing insn. */ | |
849 | if (rtx_equal_p (src, XEXP (note, 0))) | |
850 | reg_equiv_init[regno] | |
851 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); | |
852 | ||
853 | /* Continue normally in case this is a candidate for | |
854 | replacements. */ | |
2ab0437e | 855 | } |
2bbd3819 | 856 | |
d7f88d86 BS |
857 | if (!optimize) |
858 | continue; | |
859 | ||
2ab0437e JH |
860 | /* We only handle the case of a pseudo register being set |
861 | once, or always to the same value. */ | |
862 | /* ??? The mn10200 port breaks if we add equivalences for | |
863 | values that need an ADDRESS_REGS register and set them equivalent | |
864 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
865 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
866 | calculate_needs, but we traditionally work around this problem | |
867 | here by rejecting equivalences when the destination is in a register | |
868 | that's likely spilled. This is fragile, of course, since the | |
869 | preferred class of a pseudo depends on all instructions that set | |
870 | or use it. */ | |
871 | ||
f8cfc6aa | 872 | if (!REG_P (dest) |
2ab0437e JH |
873 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER |
874 | || reg_equiv[regno].init_insns == const0_rtx | |
875 | || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) | |
d7f88d86 | 876 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2ab0437e | 877 | { |
4d6922ee | 878 | /* This might be setting a SUBREG of a pseudo, a pseudo that is |
2ab0437e JH |
879 | also set somewhere else to a constant. */ |
880 | note_stores (set, no_equiv, NULL); | |
881 | continue; | |
882 | } | |
883 | ||
884 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
885 | ||
886 | /* cse sometimes generates function invariants, but doesn't put a | |
887 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3d238248 JJ |
888 | there's no point creating it earlier than here. */ |
889 | if (! note && ! rtx_varies_p (src, 0)) | |
890 | note = set_unique_reg_note (insn, REG_EQUAL, src); | |
2ab0437e JH |
891 | |
892 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
893 | since it represents a function call */ | |
894 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
895 | note = NULL_RTX; | |
896 | ||
897 | if (REG_N_SETS (regno) != 1 | |
898 | && (! note | |
899 | || rtx_varies_p (XEXP (note, 0), 0) | |
900 | || (reg_equiv[regno].replacement | |
901 | && ! rtx_equal_p (XEXP (note, 0), | |
902 | reg_equiv[regno].replacement)))) | |
903 | { | |
904 | no_equiv (dest, set, NULL); | |
905 | continue; | |
906 | } | |
907 | /* Record this insn as initializing this register. */ | |
908 | reg_equiv[regno].init_insns | |
909 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
910 | ||
911 | /* If this register is known to be equal to a constant, record that | |
912 | it is always equivalent to the constant. */ | |
913 | if (note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
914 | PUT_MODE (note, (enum machine_mode) REG_EQUIV); | |
915 | ||
916 | /* If this insn introduces a "constant" register, decrease the priority | |
917 | of that register. Record this insn if the register is only used once | |
918 | more and the equivalence value is the same as our source. | |
919 | ||
920 | The latter condition is checked for two reasons: First, it is an | |
921 | indication that it may be more efficient to actually emit the insn | |
922 | as written (if no registers are available, reload will substitute | |
923 | the equivalence). Secondly, it avoids problems with any registers | |
924 | dying in this insn whose death notes would be missed. | |
925 | ||
926 | If we don't have a REG_EQUIV note, see if this insn is loading | |
927 | a register used only in one basic block from a MEM. If so, and the | |
928 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
929 | note. */ | |
930 | ||
931 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
932 | ||
933 | if (note == 0 && REG_BASIC_BLOCK (regno) >= 0 | |
3c0cb5de | 934 | && MEM_P (SET_SRC (set)) |
2ab0437e JH |
935 | && validate_equiv_mem (insn, dest, SET_SRC (set))) |
936 | REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set), | |
937 | REG_NOTES (insn)); | |
938 | ||
939 | if (note) | |
68342d36 | 940 | { |
2ab0437e | 941 | int regno = REGNO (dest); |
d7f88d86 BS |
942 | rtx x = XEXP (note, 0); |
943 | ||
944 | /* If we haven't done so, record for reload that this is an | |
945 | equivalencing insn. */ | |
946 | if (!reg_equiv[regno].is_arg_equivalence | |
947 | && (!MEM_P (x) || rtx_equal_p (src, x))) | |
948 | reg_equiv_init[regno] | |
949 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); | |
2ab0437e JH |
950 | |
951 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
952 | We might end up substituting the LABEL_REF for uses of the | |
953 | pseudo here or later. That kind of transformation may turn an | |
954 | indirect jump into a direct jump, in which case we must rerun the | |
955 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
d7f88d86 BS |
956 | if (GET_CODE (x) == LABEL_REF |
957 | || (GET_CODE (x) == CONST | |
958 | && GET_CODE (XEXP (x, 0)) == PLUS | |
959 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
2ab0437e JH |
960 | recorded_label_ref = 1; |
961 | ||
d7f88d86 | 962 | reg_equiv[regno].replacement = x; |
5ca9299f | 963 | reg_equiv[regno].src_p = &SET_SRC (set); |
2ab0437e JH |
964 | reg_equiv[regno].loop_depth = loop_depth; |
965 | ||
966 | /* Don't mess with things live during setjmp. */ | |
967 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
968 | { | |
969 | /* Note that the statement below does not affect the priority | |
970 | in local-alloc! */ | |
971 | REG_LIVE_LENGTH (regno) *= 2; | |
972 | ||
2ab0437e JH |
973 | /* If the register is referenced exactly twice, meaning it is |
974 | set once and used once, indicate that the reference may be | |
975 | replaced by the equivalence we computed above. Do this | |
976 | even if the register is only used in one block so that | |
977 | dependencies can be handled where the last register is | |
978 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
979 | and to reduce the number of registers alive across | |
980 | calls. */ | |
981 | ||
d7f88d86 BS |
982 | if (REG_N_REFS (regno) == 2 |
983 | && (rtx_equal_p (x, src) | |
984 | || ! equiv_init_varies_p (src)) | |
985 | && NONJUMP_INSN_P (insn) | |
986 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
987 | reg_equiv[regno].replace = 1; | |
2ab0437e | 988 | } |
68342d36 | 989 | } |
2bbd3819 RS |
990 | } |
991 | } | |
992 | ||
d7f88d86 BS |
993 | if (!optimize) |
994 | goto out; | |
995 | ||
996 | /* A second pass, to gather additional equivalences with memory. This needs | |
997 | to be done after we know which registers we are going to replace. */ | |
998 | ||
999 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
1000 | { | |
1001 | rtx set, src, dest; | |
1002 | unsigned regno; | |
1003 | ||
1004 | if (! INSN_P (insn)) | |
1005 | continue; | |
1006 | ||
1007 | set = single_set (insn); | |
1008 | if (! set) | |
1009 | continue; | |
1010 | ||
1011 | dest = SET_DEST (set); | |
1012 | src = SET_SRC (set); | |
1013 | ||
1014 | /* If this sets a MEM to the contents of a REG that is only used | |
1015 | in a single basic block, see if the register is always equivalent | |
1016 | to that memory location and if moving the store from INSN to the | |
1017 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
1018 | initializing insn. | |
1019 | ||
1020 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
1021 | REG_EQUIV is likely more useful than the one we are adding. | |
1022 | ||
1023 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
1024 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
1025 | optimization may move the set of this register immediately before | |
1026 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
1027 | the mention in the REG_EQUIV note would be to an uninitialized | |
1028 | pseudo. */ | |
1029 | ||
1030 | if (MEM_P (dest) && REG_P (src) | |
1031 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
1032 | && REG_BASIC_BLOCK (regno) >= 0 | |
1033 | && REG_N_SETS (regno) == 1 | |
1034 | && reg_equiv[regno].init_insns != 0 | |
1035 | && reg_equiv[regno].init_insns != const0_rtx | |
1036 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
1037 | REG_EQUIV, NULL_RTX) | |
1038 | && ! contains_replace_regs (XEXP (dest, 0))) | |
1039 | { | |
1040 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
1041 | if (validate_equiv_mem (init_insn, src, dest) | |
1042 | && ! memref_used_between_p (dest, init_insn, insn)) | |
1043 | { | |
1044 | REG_NOTES (init_insn) | |
1045 | = gen_rtx_EXPR_LIST (REG_EQUIV, dest, | |
1046 | REG_NOTES (init_insn)); | |
1047 | /* This insn makes the equivalence, not the one initializing | |
1048 | the register. */ | |
1049 | reg_equiv_init[regno] | |
1050 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); | |
1051 | } | |
1052 | } | |
1053 | } | |
1054 | ||
2e1253f3 ILT |
1055 | /* Now scan all regs killed in an insn to see if any of them are |
1056 | registers only used that once. If so, see if we can replace the | |
ccb4e87e | 1057 | reference with the equivalent form. If we can, delete the |
2e1253f3 | 1058 | initializing reference and this register will go away. If we |
4d6922ee | 1059 | can't replace the reference, and the initializing reference is |
bf6d9fd7 JW |
1060 | within the same loop (or in an inner loop), then move the register |
1061 | initialization just before the use, so that they are in the same | |
2ab0437e | 1062 | basic block. */ |
e0082a72 | 1063 | FOR_EACH_BB_REVERSE (bb) |
2bbd3819 | 1064 | { |
2ab0437e | 1065 | loop_depth = bb->loop_depth; |
a813c111 SB |
1066 | for (insn = BB_END (bb); |
1067 | insn != PREV_INSN (BB_HEAD (bb)); | |
1068 | insn = PREV_INSN (insn)) | |
2e1253f3 | 1069 | { |
2ab0437e JH |
1070 | rtx link; |
1071 | ||
1072 | if (! INSN_P (insn)) | |
1073 | continue; | |
1074 | ||
2f39b6ca UW |
1075 | /* Don't substitute into a non-local goto, this confuses CFG. */ |
1076 | if (JUMP_P (insn) | |
1077 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
1078 | continue; | |
1079 | ||
2ab0437e | 1080 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
2e1253f3 | 1081 | { |
2ab0437e JH |
1082 | if (REG_NOTE_KIND (link) == REG_DEAD |
1083 | /* Make sure this insn still refers to the register. */ | |
1084 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
2e1253f3 | 1085 | { |
2ab0437e JH |
1086 | int regno = REGNO (XEXP (link, 0)); |
1087 | rtx equiv_insn; | |
1088 | ||
1089 | if (! reg_equiv[regno].replace | |
1090 | || reg_equiv[regno].loop_depth < loop_depth) | |
1091 | continue; | |
1092 | ||
1093 | /* reg_equiv[REGNO].replace gets set only when | |
1094 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
1095 | once and used once. (If it were only set, but not used, | |
1096 | flow would have deleted the setting insns.) Hence | |
1097 | there can only be one insn in reg_equiv[REGNO].init_insns. */ | |
b5e624c6 NS |
1098 | gcc_assert (reg_equiv[regno].init_insns |
1099 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
2ab0437e | 1100 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); |
2e1253f3 | 1101 | |
2ab0437e JH |
1102 | /* We may not move instructions that can throw, since |
1103 | that changes basic block boundaries and we are not | |
1104 | prepared to adjust the CFG to match. */ | |
1105 | if (can_throw_internal (equiv_insn)) | |
1106 | continue; | |
2e1253f3 | 1107 | |
2ab0437e JH |
1108 | if (asm_noperands (PATTERN (equiv_insn)) < 0 |
1109 | && validate_replace_rtx (regno_reg_rtx[regno], | |
5ca9299f | 1110 | *(reg_equiv[regno].src_p), insn)) |
bf6d9fd7 | 1111 | { |
2ab0437e JH |
1112 | rtx equiv_link; |
1113 | rtx last_link; | |
1114 | rtx note; | |
1115 | ||
1116 | /* Find the last note. */ | |
1117 | for (last_link = link; XEXP (last_link, 1); | |
1118 | last_link = XEXP (last_link, 1)) | |
1119 | ; | |
1120 | ||
1121 | /* Append the REG_DEAD notes from equiv_insn. */ | |
1122 | equiv_link = REG_NOTES (equiv_insn); | |
1123 | while (equiv_link) | |
bf6d9fd7 | 1124 | { |
2ab0437e JH |
1125 | note = equiv_link; |
1126 | equiv_link = XEXP (equiv_link, 1); | |
1127 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
1128 | { | |
1129 | remove_note (equiv_insn, note); | |
1130 | XEXP (last_link, 1) = note; | |
1131 | XEXP (note, 1) = NULL_RTX; | |
1132 | last_link = note; | |
1133 | } | |
bf6d9fd7 | 1134 | } |
bf6d9fd7 | 1135 | |
2ab0437e JH |
1136 | remove_death (regno, insn); |
1137 | REG_N_REFS (regno) = 0; | |
1138 | REG_FREQ (regno) = 0; | |
ca6c03ca | 1139 | delete_insn (equiv_insn); |
e11e816e | 1140 | |
2ab0437e JH |
1141 | reg_equiv[regno].init_insns |
1142 | = XEXP (reg_equiv[regno].init_insns, 1); | |
ccb4e87e BS |
1143 | |
1144 | /* Remember to clear REGNO from all basic block's live | |
1145 | info. */ | |
1146 | SET_REGNO_REG_SET (&cleared_regs, regno); | |
1147 | clear_regnos++; | |
d7f88d86 | 1148 | reg_equiv_init[regno] = NULL_RTX; |
2ab0437e JH |
1149 | } |
1150 | /* Move the initialization of the register to just before | |
1151 | INSN. Update the flow information. */ | |
1152 | else if (PREV_INSN (insn) != equiv_insn) | |
1153 | { | |
1154 | rtx new_insn; | |
2e1253f3 | 1155 | |
2ab0437e JH |
1156 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); |
1157 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
1158 | REG_NOTES (equiv_insn) = 0; | |
2e1253f3 | 1159 | |
41806d92 NS |
1160 | /* Make sure this insn is recognized before |
1161 | reload begins, otherwise | |
1162 | eliminate_regs_in_insn will die. */ | |
2ab0437e | 1163 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); |
cad33336 | 1164 | |
ca6c03ca | 1165 | delete_insn (equiv_insn); |
2e1253f3 | 1166 | |
2ab0437e | 1167 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; |
96af667a | 1168 | |
e0082a72 | 1169 | REG_BASIC_BLOCK (regno) = bb->index; |
2ab0437e JH |
1170 | REG_N_CALLS_CROSSED (regno) = 0; |
1171 | REG_LIVE_LENGTH (regno) = 2; | |
2e1253f3 | 1172 | |
a813c111 SB |
1173 | if (insn == BB_HEAD (bb)) |
1174 | BB_HEAD (bb) = PREV_INSN (insn); | |
2e1253f3 | 1175 | |
2ab0437e JH |
1176 | /* Remember to clear REGNO from all basic block's live |
1177 | info. */ | |
1178 | SET_REGNO_REG_SET (&cleared_regs, regno); | |
1179 | clear_regnos++; | |
599c25e2 RH |
1180 | reg_equiv_init[regno] |
1181 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); | |
2ab0437e | 1182 | } |
2e1253f3 ILT |
1183 | } |
1184 | } | |
1185 | } | |
2bbd3819 | 1186 | } |
e05e2395 | 1187 | |
25e4379f MM |
1188 | /* Clear all dead REGNOs from all basic block's live info. */ |
1189 | if (clear_regnos) | |
1190 | { | |
3cd8c58a NS |
1191 | unsigned j; |
1192 | ||
25e4379f | 1193 | if (clear_regnos > 8) |
e11e816e | 1194 | { |
e0082a72 | 1195 | FOR_EACH_BB (bb) |
25e4379f | 1196 | { |
5e2d947c JH |
1197 | AND_COMPL_REG_SET (bb->il.rtl->global_live_at_start, |
1198 | &cleared_regs); | |
1199 | AND_COMPL_REG_SET (bb->il.rtl->global_live_at_end, | |
1200 | &cleared_regs); | |
25e4379f MM |
1201 | } |
1202 | } | |
1203 | else | |
a2041967 KH |
1204 | { |
1205 | reg_set_iterator rsi; | |
1206 | EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j, rsi) | |
1207 | { | |
1208 | FOR_EACH_BB (bb) | |
1209 | { | |
5e2d947c JH |
1210 | CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start, j); |
1211 | CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_end, j); | |
a2041967 KH |
1212 | } |
1213 | } | |
1214 | } | |
25e4379f MM |
1215 | } |
1216 | ||
d7f88d86 | 1217 | out: |
e05e2395 MM |
1218 | /* Clean up. */ |
1219 | end_alias_analysis (); | |
25e4379f | 1220 | CLEAR_REG_SET (&cleared_regs); |
bf6d9fd7 | 1221 | free (reg_equiv); |
2bbd3819 | 1222 | } |
135eb61c R |
1223 | |
1224 | /* Mark REG as having no known equivalence. | |
3d042e77 | 1225 | Some instructions might have been processed before and furnished |
135eb61c R |
1226 | with REG_EQUIV notes for this register; these notes will have to be |
1227 | removed. | |
1228 | STORE is the piece of RTL that does the non-constant / conflicting | |
1229 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
1230 | but needs to be there because this function is called from note_stores. */ | |
1231 | static void | |
0c20a65f | 1232 | no_equiv (rtx reg, rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED) |
135eb61c R |
1233 | { |
1234 | int regno; | |
1235 | rtx list; | |
1236 | ||
f8cfc6aa | 1237 | if (!REG_P (reg)) |
135eb61c R |
1238 | return; |
1239 | regno = REGNO (reg); | |
bf6d9fd7 | 1240 | list = reg_equiv[regno].init_insns; |
135eb61c R |
1241 | if (list == const0_rtx) |
1242 | return; | |
d7f88d86 BS |
1243 | reg_equiv[regno].init_insns = const0_rtx; |
1244 | reg_equiv[regno].replacement = NULL_RTX; | |
1245 | /* This doesn't matter for equivalences made for argument registers, we | |
1246 | should keep their initialization insns. */ | |
1247 | if (reg_equiv[regno].is_arg_equivalence) | |
1248 | return; | |
1249 | reg_equiv_init[regno] = NULL_RTX; | |
135eb61c R |
1250 | for (; list; list = XEXP (list, 1)) |
1251 | { | |
1252 | rtx insn = XEXP (list, 0); | |
1253 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
1254 | } | |
135eb61c | 1255 | } |
2bbd3819 RS |
1256 | \f |
1257 | /* Allocate hard regs to the pseudo regs used only within block number B. | |
1258 | Only the pseudos that die but once can be handled. */ | |
1259 | ||
1260 | static void | |
0c20a65f | 1261 | block_alloc (int b) |
2bbd3819 | 1262 | { |
b3694847 SS |
1263 | int i, q; |
1264 | rtx insn; | |
902197eb | 1265 | rtx note, hard_reg; |
2bbd3819 RS |
1266 | int insn_number = 0; |
1267 | int insn_count = 0; | |
1268 | int max_uid = get_max_uid (); | |
aabf56ce | 1269 | int *qty_order; |
2bbd3819 RS |
1270 | int no_conflict_combined_regno = -1; |
1271 | ||
1272 | /* Count the instructions in the basic block. */ | |
1273 | ||
a813c111 | 1274 | insn = BB_END (BASIC_BLOCK (b)); |
2bbd3819 RS |
1275 | while (1) |
1276 | { | |
4b4bf941 | 1277 | if (!NOTE_P (insn)) |
b5e624c6 NS |
1278 | { |
1279 | ++insn_count; | |
1280 | gcc_assert (insn_count <= max_uid); | |
1281 | } | |
a813c111 | 1282 | if (insn == BB_HEAD (BASIC_BLOCK (b))) |
2bbd3819 RS |
1283 | break; |
1284 | insn = PREV_INSN (insn); | |
1285 | } | |
1286 | ||
1287 | /* +2 to leave room for a post_mark_life at the last insn and for | |
1288 | the birth of a CLOBBER in the first insn. */ | |
703ad42b | 1289 | regs_live_at = xcalloc ((2 * insn_count + 2), sizeof (HARD_REG_SET)); |
2bbd3819 RS |
1290 | |
1291 | /* Initialize table of hardware registers currently live. */ | |
1292 | ||
5e2d947c JH |
1293 | REG_SET_TO_HARD_REG_SET (regs_live, |
1294 | BASIC_BLOCK (b)->il.rtl->global_live_at_start); | |
2bbd3819 RS |
1295 | |
1296 | /* This loop scans the instructions of the basic block | |
1297 | and assigns quantities to registers. | |
1298 | It computes which registers to tie. */ | |
1299 | ||
a813c111 | 1300 | insn = BB_HEAD (BASIC_BLOCK (b)); |
2bbd3819 RS |
1301 | while (1) |
1302 | { | |
4b4bf941 | 1303 | if (!NOTE_P (insn)) |
2bbd3819 RS |
1304 | insn_number++; |
1305 | ||
2c3c49de | 1306 | if (INSN_P (insn)) |
2bbd3819 | 1307 | { |
b3694847 SS |
1308 | rtx link, set; |
1309 | int win = 0; | |
1310 | rtx r0, r1 = NULL_RTX; | |
2bbd3819 RS |
1311 | int combined_regno = -1; |
1312 | int i; | |
2bbd3819 RS |
1313 | |
1314 | this_insn_number = insn_number; | |
1315 | this_insn = insn; | |
1316 | ||
0a578fee | 1317 | extract_insn (insn); |
2bbd3819 RS |
1318 | which_alternative = -1; |
1319 | ||
1320 | /* Is this insn suitable for tying two registers? | |
1321 | If so, try doing that. | |
1322 | Suitable insns are those with at least two operands and where | |
1323 | operand 0 is an output that is a register that is not | |
1324 | earlyclobber. | |
7aba0f0b RK |
1325 | |
1326 | We can tie operand 0 with some operand that dies in this insn. | |
1327 | First look for operands that are required to be in the same | |
1328 | register as operand 0. If we find such, only try tying that | |
1329 | operand or one that can be put into that operand if the | |
1330 | operation is commutative. If we don't find an operand | |
1331 | that is required to be in the same register as operand 0, | |
1332 | we can tie with any operand. | |
1333 | ||
2bbd3819 RS |
1334 | Subregs in place of regs are also ok. |
1335 | ||
1336 | If tying is done, WIN is set nonzero. */ | |
1337 | ||
d29c259b RH |
1338 | if (optimize |
1339 | && recog_data.n_operands > 1 | |
1ccbefce | 1340 | && recog_data.constraints[0][0] == '=' |
19af6455 | 1341 | && recog_data.constraints[0][1] != '&') |
2bbd3819 | 1342 | { |
3061cc54 | 1343 | /* If non-negative, is an operand that must match operand 0. */ |
7aba0f0b | 1344 | int must_match_0 = -1; |
3061cc54 RK |
1345 | /* Counts number of alternatives that require a match with |
1346 | operand 0. */ | |
1347 | int n_matching_alts = 0; | |
7aba0f0b | 1348 | |
1ccbefce | 1349 | for (i = 1; i < recog_data.n_operands; i++) |
3061cc54 | 1350 | { |
1ccbefce | 1351 | const char *p = recog_data.constraints[i]; |
84b72302 | 1352 | int this_match = requires_inout (p); |
3061cc54 RK |
1353 | |
1354 | n_matching_alts += this_match; | |
1ccbefce | 1355 | if (this_match == recog_data.n_alternatives) |
3061cc54 RK |
1356 | must_match_0 = i; |
1357 | } | |
2bbd3819 | 1358 | |
1ccbefce RH |
1359 | r0 = recog_data.operand[0]; |
1360 | for (i = 1; i < recog_data.n_operands; i++) | |
2bbd3819 | 1361 | { |
7aba0f0b RK |
1362 | /* Skip this operand if we found an operand that |
1363 | must match operand 0 and this operand isn't it | |
1364 | and can't be made to be it by commutativity. */ | |
1365 | ||
1366 | if (must_match_0 >= 0 && i != must_match_0 | |
1367 | && ! (i == must_match_0 + 1 | |
1ccbefce | 1368 | && recog_data.constraints[i-1][0] == '%') |
7aba0f0b | 1369 | && ! (i == must_match_0 - 1 |
1ccbefce | 1370 | && recog_data.constraints[i][0] == '%')) |
7aba0f0b | 1371 | continue; |
3061cc54 RK |
1372 | |
1373 | /* Likewise if each alternative has some operand that | |
64e3a413 | 1374 | must match operand zero. In that case, skip any |
3061cc54 RK |
1375 | operand that doesn't list operand 0 since we know that |
1376 | the operand always conflicts with operand 0. We | |
3d042e77 | 1377 | ignore commutativity in this case to keep things simple. */ |
1ccbefce RH |
1378 | if (n_matching_alts == recog_data.n_alternatives |
1379 | && 0 == requires_inout (recog_data.constraints[i])) | |
3061cc54 | 1380 | continue; |
2bbd3819 | 1381 | |
1ccbefce | 1382 | r1 = recog_data.operand[i]; |
2bbd3819 | 1383 | |
7aba0f0b RK |
1384 | /* If the operand is an address, find a register in it. |
1385 | There may be more than one register, but we only try one | |
1386 | of them. */ | |
ccfc6cc8 | 1387 | if (recog_data.constraints[i][0] == 'p' |
97488870 R |
1388 | || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0], |
1389 | recog_data.constraints[i])) | |
7aba0f0b RK |
1390 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) |
1391 | r1 = XEXP (r1, 0); | |
1392 | ||
902197eb DD |
1393 | /* Avoid making a call-saved register unnecessarily |
1394 | clobbered. */ | |
1395 | hard_reg = get_hard_reg_initial_reg (cfun, r1); | |
1396 | if (hard_reg != NULL_RTX) | |
1397 | { | |
f8cfc6aa | 1398 | if (REG_P (hard_reg) |
f85d8f69 NS |
1399 | && REGNO (hard_reg) < FIRST_PSEUDO_REGISTER |
1400 | && !call_used_regs[REGNO (hard_reg)]) | |
902197eb DD |
1401 | continue; |
1402 | } | |
1403 | ||
f8cfc6aa | 1404 | if (REG_P (r0) || GET_CODE (r0) == SUBREG) |
7aba0f0b RK |
1405 | { |
1406 | /* We have two priorities for hard register preferences. | |
1407 | If we have a move insn or an insn whose first input | |
1408 | can only be in the same register as the output, give | |
1409 | priority to an equivalence found from that insn. */ | |
1410 | int may_save_copy | |
1ccbefce | 1411 | = (r1 == recog_data.operand[i] && must_match_0 >= 0); |
64e3a413 | 1412 | |
f8cfc6aa | 1413 | if (REG_P (r1) || GET_CODE (r1) == SUBREG) |
7aba0f0b RK |
1414 | win = combine_regs (r1, r0, may_save_copy, |
1415 | insn_number, insn, 0); | |
1416 | } | |
662347c5 JL |
1417 | if (win) |
1418 | break; | |
2bbd3819 RS |
1419 | } |
1420 | } | |
1421 | ||
1422 | /* Recognize an insn sequence with an ultimate result | |
1423 | which can safely overlap one of the inputs. | |
1424 | The sequence begins with a CLOBBER of its result, | |
1425 | and ends with an insn that copies the result to itself | |
1426 | and has a REG_EQUAL note for an equivalent formula. | |
1427 | That note indicates what the inputs are. | |
1428 | The result and the input can overlap if each insn in | |
1429 | the sequence either doesn't mention the input | |
1430 | or has a REG_NO_CONFLICT note to inhibit the conflict. | |
1431 | ||
1432 | We do the combining test at the CLOBBER so that the | |
1433 | destination register won't have had a quantity number | |
1434 | assigned, since that would prevent combining. */ | |
1435 | ||
d29c259b RH |
1436 | if (optimize |
1437 | && GET_CODE (PATTERN (insn)) == CLOBBER | |
2bbd3819 | 1438 | && (r0 = XEXP (PATTERN (insn), 0), |
f8cfc6aa | 1439 | REG_P (r0)) |
b1ec3c92 | 1440 | && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 |
a6665f8c | 1441 | && XEXP (link, 0) != 0 |
4b4bf941 | 1442 | && NONJUMP_INSN_P (XEXP (link, 0)) |
2bbd3819 RS |
1443 | && (set = single_set (XEXP (link, 0))) != 0 |
1444 | && SET_DEST (set) == r0 && SET_SRC (set) == r0 | |
b1ec3c92 CH |
1445 | && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, |
1446 | NULL_RTX)) != 0) | |
2bbd3819 | 1447 | { |
f8cfc6aa | 1448 | if (r1 = XEXP (note, 0), REG_P (r1) |
2bbd3819 RS |
1449 | /* Check that we have such a sequence. */ |
1450 | && no_conflict_p (insn, r0, r1)) | |
1451 | win = combine_regs (r1, r0, 1, insn_number, insn, 1); | |
1452 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' | |
1453 | && (r1 = XEXP (XEXP (note, 0), 0), | |
f8cfc6aa | 1454 | REG_P (r1) || GET_CODE (r1) == SUBREG) |
2bbd3819 RS |
1455 | && no_conflict_p (insn, r0, r1)) |
1456 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1457 | ||
1458 | /* Here we care if the operation to be computed is | |
1459 | commutative. */ | |
ec8e098d | 1460 | else if (COMMUTATIVE_P (XEXP (note, 0)) |
2bbd3819 | 1461 | && (r1 = XEXP (XEXP (note, 0), 1), |
f8cfc6aa | 1462 | (REG_P (r1) || GET_CODE (r1) == SUBREG)) |
2bbd3819 RS |
1463 | && no_conflict_p (insn, r0, r1)) |
1464 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1465 | ||
1466 | /* If we did combine something, show the register number | |
1467 | in question so that we know to ignore its death. */ | |
1468 | if (win) | |
1469 | no_conflict_combined_regno = REGNO (r1); | |
1470 | } | |
1471 | ||
1472 | /* If registers were just tied, set COMBINED_REGNO | |
1473 | to the number of the register used in this insn | |
1474 | that was tied to the register set in this insn. | |
1475 | This register's qty should not be "killed". */ | |
1476 | ||
1477 | if (win) | |
1478 | { | |
1479 | while (GET_CODE (r1) == SUBREG) | |
1480 | r1 = SUBREG_REG (r1); | |
1481 | combined_regno = REGNO (r1); | |
1482 | } | |
1483 | ||
1484 | /* Mark the death of everything that dies in this instruction, | |
1485 | except for anything that was just combined. */ | |
1486 | ||
1487 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1488 | if (REG_NOTE_KIND (link) == REG_DEAD | |
f8cfc6aa | 1489 | && REG_P (XEXP (link, 0)) |
770ae6cc RK |
1490 | && combined_regno != (int) REGNO (XEXP (link, 0)) |
1491 | && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0)) | |
1492 | || ! find_reg_note (insn, REG_NO_CONFLICT, | |
1493 | XEXP (link, 0)))) | |
2bbd3819 RS |
1494 | wipe_dead_reg (XEXP (link, 0), 0); |
1495 | ||
1496 | /* Allocate qty numbers for all registers local to this block | |
1497 | that are born (set) in this instruction. | |
1498 | A pseudo that already has a qty is not changed. */ | |
1499 | ||
84832317 | 1500 | note_stores (PATTERN (insn), reg_is_set, NULL); |
2bbd3819 RS |
1501 | |
1502 | /* If anything is set in this insn and then unused, mark it as dying | |
1503 | after this insn, so it will conflict with our outputs. This | |
1504 | can't match with something that combined, and it doesn't matter | |
1505 | if it did. Do this after the calls to reg_is_set since these | |
1506 | die after, not during, the current insn. */ | |
1507 | ||
1508 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1509 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
f8cfc6aa | 1510 | && REG_P (XEXP (link, 0))) |
2bbd3819 RS |
1511 | wipe_dead_reg (XEXP (link, 0), 1); |
1512 | ||
64e3a413 | 1513 | /* If this is an insn that has a REG_RETVAL note pointing at a |
2bbd3819 RS |
1514 | CLOBBER insn, we have reached the end of a REG_NO_CONFLICT |
1515 | block, so clear any register number that combined within it. */ | |
b1ec3c92 | 1516 | if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 |
4b4bf941 | 1517 | && NONJUMP_INSN_P (XEXP (note, 0)) |
2bbd3819 RS |
1518 | && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) |
1519 | no_conflict_combined_regno = -1; | |
1520 | } | |
1521 | ||
1522 | /* Set the registers live after INSN_NUMBER. Note that we never | |
1523 | record the registers live before the block's first insn, since no | |
1524 | pseudos we care about are live before that insn. */ | |
1525 | ||
1526 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); | |
1527 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); | |
1528 | ||
a813c111 | 1529 | if (insn == BB_END (BASIC_BLOCK (b))) |
2bbd3819 RS |
1530 | break; |
1531 | ||
1532 | insn = NEXT_INSN (insn); | |
1533 | } | |
1534 | ||
1535 | /* Now every register that is local to this basic block | |
1536 | should have been given a quantity, or else -1 meaning ignore it. | |
64e3a413 | 1537 | Every quantity should have a known birth and death. |
2bbd3819 | 1538 | |
51b86d8b RK |
1539 | Order the qtys so we assign them registers in order of the |
1540 | number of suggested registers they need so we allocate those with | |
1541 | the most restrictive needs first. */ | |
2bbd3819 | 1542 | |
703ad42b | 1543 | qty_order = xmalloc (next_qty * sizeof (int)); |
2bbd3819 RS |
1544 | for (i = 0; i < next_qty; i++) |
1545 | qty_order[i] = i; | |
1546 | ||
1547 | #define EXCHANGE(I1, I2) \ | |
1548 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1549 | ||
1550 | switch (next_qty) | |
1551 | { | |
1552 | case 3: | |
1553 | /* Make qty_order[2] be the one to allocate last. */ | |
51b86d8b | 1554 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 | 1555 | EXCHANGE (0, 1); |
51b86d8b | 1556 | if (qty_sugg_compare (1, 2) > 0) |
2bbd3819 RS |
1557 | EXCHANGE (2, 1); |
1558 | ||
0f41302f | 1559 | /* ... Fall through ... */ |
2bbd3819 RS |
1560 | case 2: |
1561 | /* Put the best one to allocate in qty_order[0]. */ | |
51b86d8b | 1562 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 RS |
1563 | EXCHANGE (0, 1); |
1564 | ||
0f41302f | 1565 | /* ... Fall through ... */ |
2bbd3819 RS |
1566 | |
1567 | case 1: | |
1568 | case 0: | |
1569 | /* Nothing to do here. */ | |
1570 | break; | |
1571 | ||
1572 | default: | |
51b86d8b | 1573 | qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); |
2bbd3819 RS |
1574 | } |
1575 | ||
1576 | /* Try to put each quantity in a suggested physical register, if it has one. | |
1577 | This may cause registers to be allocated that otherwise wouldn't be, but | |
1578 | this seems acceptable in local allocation (unlike global allocation). */ | |
1579 | for (i = 0; i < next_qty; i++) | |
1580 | { | |
1581 | q = qty_order[i]; | |
51b86d8b | 1582 | if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) |
a1ed7bdb JH |
1583 | qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q, |
1584 | 0, 1, qty[q].birth, qty[q].death); | |
2bbd3819 | 1585 | else |
a1ed7bdb | 1586 | qty[q].phys_reg = -1; |
2bbd3819 RS |
1587 | } |
1588 | ||
64e3a413 KH |
1589 | /* Order the qtys so we assign them registers in order of |
1590 | decreasing length of life. Normally call qsort, but if we | |
51b86d8b RK |
1591 | have only a very small number of quantities, sort them ourselves. */ |
1592 | ||
1593 | for (i = 0; i < next_qty; i++) | |
1594 | qty_order[i] = i; | |
1595 | ||
1596 | #define EXCHANGE(I1, I2) \ | |
1597 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1598 | ||
1599 | switch (next_qty) | |
1600 | { | |
1601 | case 3: | |
1602 | /* Make qty_order[2] be the one to allocate last. */ | |
1603 | if (qty_compare (0, 1) > 0) | |
1604 | EXCHANGE (0, 1); | |
1605 | if (qty_compare (1, 2) > 0) | |
1606 | EXCHANGE (2, 1); | |
1607 | ||
0f41302f | 1608 | /* ... Fall through ... */ |
51b86d8b RK |
1609 | case 2: |
1610 | /* Put the best one to allocate in qty_order[0]. */ | |
1611 | if (qty_compare (0, 1) > 0) | |
1612 | EXCHANGE (0, 1); | |
1613 | ||
0f41302f | 1614 | /* ... Fall through ... */ |
51b86d8b RK |
1615 | |
1616 | case 1: | |
1617 | case 0: | |
1618 | /* Nothing to do here. */ | |
1619 | break; | |
1620 | ||
1621 | default: | |
1622 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); | |
1623 | } | |
1624 | ||
2bbd3819 RS |
1625 | /* Now for each qty that is not a hardware register, |
1626 | look for a hardware register to put it in. | |
1627 | First try the register class that is cheapest for this qty, | |
1628 | if there is more than one class. */ | |
1629 | ||
1630 | for (i = 0; i < next_qty; i++) | |
1631 | { | |
1632 | q = qty_order[i]; | |
a1ed7bdb | 1633 | if (qty[q].phys_reg < 0) |
2bbd3819 | 1634 | { |
624a8b3a JL |
1635 | #ifdef INSN_SCHEDULING |
1636 | /* These values represent the adjusted lifetime of a qty so | |
1637 | that it conflicts with qtys which appear near the start/end | |
1638 | of this qty's lifetime. | |
1639 | ||
1640 | The purpose behind extending the lifetime of this qty is to | |
1641 | discourage the register allocator from creating false | |
1642 | dependencies. | |
64e3a413 | 1643 | |
f63d1bf7 | 1644 | The adjustment value is chosen to indicate that this qty |
996e9683 | 1645 | conflicts with all the qtys in the instructions immediately |
624a8b3a JL |
1646 | before and after the lifetime of this qty. |
1647 | ||
1648 | Experiments have shown that higher values tend to hurt | |
1649 | overall code performance. | |
1650 | ||
1651 | If allocation using the extended lifetime fails we will try | |
1652 | again with the qty's unadjusted lifetime. */ | |
a1ed7bdb | 1653 | int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2); |
996e9683 | 1654 | int fake_death = MIN (insn_number * 2 + 1, |
a1ed7bdb | 1655 | qty[q].death + 2 - qty[q].death % 2); |
624a8b3a JL |
1656 | #endif |
1657 | ||
2bbd3819 RS |
1658 | if (N_REG_CLASSES > 1) |
1659 | { | |
624a8b3a JL |
1660 | #ifdef INSN_SCHEDULING |
1661 | /* We try to avoid using hard registers allocated to qtys which | |
1662 | are born immediately after this qty or die immediately before | |
1663 | this qty. | |
1664 | ||
1665 | This optimization is only appropriate when we will run | |
1666 | a scheduling pass after reload and we are not optimizing | |
1667 | for code size. */ | |
c358412f JL |
1668 | if (flag_schedule_insns_after_reload |
1669 | && !optimize_size | |
1670 | && !SMALL_REGISTER_CLASSES) | |
624a8b3a | 1671 | { |
64e3a413 | 1672 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb | 1673 | qty[q].mode, q, 0, 0, |
624a8b3a | 1674 | fake_birth, fake_death); |
a1ed7bdb | 1675 | if (qty[q].phys_reg >= 0) |
624a8b3a JL |
1676 | continue; |
1677 | } | |
1678 | #endif | |
64e3a413 | 1679 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb JH |
1680 | qty[q].mode, q, 0, 0, |
1681 | qty[q].birth, qty[q].death); | |
1682 | if (qty[q].phys_reg >= 0) | |
2bbd3819 RS |
1683 | continue; |
1684 | } | |
1685 | ||
624a8b3a JL |
1686 | #ifdef INSN_SCHEDULING |
1687 | /* Similarly, avoid false dependencies. */ | |
c358412f JL |
1688 | if (flag_schedule_insns_after_reload |
1689 | && !optimize_size | |
1690 | && !SMALL_REGISTER_CLASSES | |
a1ed7bdb JH |
1691 | && qty[q].alternate_class != NO_REGS) |
1692 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1693 | qty[q].mode, q, 0, 0, | |
624a8b3a JL |
1694 | fake_birth, fake_death); |
1695 | #endif | |
a1ed7bdb JH |
1696 | if (qty[q].alternate_class != NO_REGS) |
1697 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1698 | qty[q].mode, q, 0, 0, | |
1699 | qty[q].birth, qty[q].death); | |
2bbd3819 RS |
1700 | } |
1701 | } | |
1702 | ||
1703 | /* Now propagate the register assignments | |
1704 | to the pseudo regs belonging to the qtys. */ | |
1705 | ||
1706 | for (q = 0; q < next_qty; q++) | |
a1ed7bdb | 1707 | if (qty[q].phys_reg >= 0) |
2bbd3819 | 1708 | { |
a1ed7bdb JH |
1709 | for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i]) |
1710 | reg_renumber[i] = qty[q].phys_reg + reg_offset[i]; | |
2bbd3819 | 1711 | } |
ff154f78 MM |
1712 | |
1713 | /* Clean up. */ | |
1714 | free (regs_live_at); | |
1715 | free (qty_order); | |
2bbd3819 RS |
1716 | } |
1717 | \f | |
1718 | /* Compare two quantities' priority for getting real registers. | |
1719 | We give shorter-lived quantities higher priority. | |
6dc42e49 RS |
1720 | Quantities with more references are also preferred, as are quantities that |
1721 | require multiple registers. This is the identical prioritization as | |
2bbd3819 RS |
1722 | done by global-alloc. |
1723 | ||
1724 | We used to give preference to registers with *longer* lives, but using | |
1725 | the same algorithm in both local- and global-alloc can speed up execution | |
1726 | of some programs by as much as a factor of three! */ | |
1727 | ||
2f23fcc9 RK |
1728 | /* Note that the quotient will never be bigger than |
1729 | the value of floor_log2 times the maximum number of | |
a08b2604 JH |
1730 | times a register can occur in one insn (surely less than 100) |
1731 | weighted by frequency (max REG_FREQ_MAX). | |
1732 | Multiplying this by 10000/REG_FREQ_MAX can't overflow. | |
2f23fcc9 RK |
1733 | QTY_CMP_PRI is also used by qty_sugg_compare. */ |
1734 | ||
1735 | #define QTY_CMP_PRI(q) \ | |
b2aec5c0 | 1736 | ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \ |
a08b2604 | 1737 | / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX))) |
2f23fcc9 | 1738 | |
2bbd3819 | 1739 | static int |
0c20a65f | 1740 | qty_compare (int q1, int q2) |
2bbd3819 | 1741 | { |
2f23fcc9 | 1742 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
2bbd3819 RS |
1743 | } |
1744 | ||
1745 | static int | |
0c20a65f | 1746 | qty_compare_1 (const void *q1p, const void *q2p) |
2bbd3819 | 1747 | { |
b3694847 SS |
1748 | int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
1749 | int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
2f23fcc9 RK |
1750 | |
1751 | if (tem != 0) | |
1752 | return tem; | |
1753 | ||
2bbd3819 RS |
1754 | /* If qtys are equally good, sort by qty number, |
1755 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1756 | return q1 - q2; |
2bbd3819 RS |
1757 | } |
1758 | \f | |
51b86d8b RK |
1759 | /* Compare two quantities' priority for getting real registers. This version |
1760 | is called for quantities that have suggested hard registers. First priority | |
1761 | goes to quantities that have copy preferences, then to those that have | |
1762 | normal preferences. Within those groups, quantities with the lower | |
9faa82d8 | 1763 | number of preferences have the highest priority. Of those, we use the same |
51b86d8b RK |
1764 | algorithm as above. */ |
1765 | ||
2f23fcc9 RK |
1766 | #define QTY_CMP_SUGG(q) \ |
1767 | (qty_phys_num_copy_sugg[q] \ | |
1768 | ? qty_phys_num_copy_sugg[q] \ | |
1769 | : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER) | |
1770 | ||
51b86d8b | 1771 | static int |
0c20a65f | 1772 | qty_sugg_compare (int q1, int q2) |
51b86d8b | 1773 | { |
b3694847 | 1774 | int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
2f23fcc9 RK |
1775 | |
1776 | if (tem != 0) | |
1777 | return tem; | |
64e3a413 | 1778 | |
2f23fcc9 | 1779 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
51b86d8b RK |
1780 | } |
1781 | ||
1782 | static int | |
0c20a65f | 1783 | qty_sugg_compare_1 (const void *q1p, const void *q2p) |
51b86d8b | 1784 | { |
b3694847 SS |
1785 | int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
1786 | int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); | |
2f23fcc9 RK |
1787 | |
1788 | if (tem != 0) | |
1789 | return tem; | |
1790 | ||
1791 | tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
1792 | if (tem != 0) | |
1793 | return tem; | |
51b86d8b RK |
1794 | |
1795 | /* If qtys are equally good, sort by qty number, | |
1796 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1797 | return q1 - q2; |
51b86d8b | 1798 | } |
2f23fcc9 RK |
1799 | |
1800 | #undef QTY_CMP_SUGG | |
1801 | #undef QTY_CMP_PRI | |
51b86d8b | 1802 | \f |
2bbd3819 RS |
1803 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. |
1804 | Returns 1 if have done so, or 0 if cannot. | |
1805 | ||
1806 | Combining registers means marking them as having the same quantity | |
1807 | and adjusting the offsets within the quantity if either of | |
a5342656 | 1808 | them is a SUBREG. |
2bbd3819 RS |
1809 | |
1810 | We don't actually combine a hard reg with a pseudo; instead | |
1811 | we just record the hard reg as the suggestion for the pseudo's quantity. | |
1812 | If we really combined them, we could lose if the pseudo lives | |
70128ad9 | 1813 | across an insn that clobbers the hard reg (eg, movmem). |
2bbd3819 | 1814 | |
cc2902df | 1815 | ALREADY_DEAD is nonzero if USEDREG is known to be dead even though |
2bbd3819 RS |
1816 | there is no REG_DEAD note on INSN. This occurs during the processing |
1817 | of REG_NO_CONFLICT blocks. | |
1818 | ||
a5342656 | 1819 | MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to |
2bbd3819 RS |
1820 | SETREG or if the input and output must share a register. |
1821 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. | |
64e3a413 | 1822 | |
2bbd3819 RS |
1823 | There are elaborate checks for the validity of combining. */ |
1824 | ||
2bbd3819 | 1825 | static int |
0c20a65f AJ |
1826 | combine_regs (rtx usedreg, rtx setreg, int may_save_copy, int insn_number, |
1827 | rtx insn, int already_dead) | |
2bbd3819 | 1828 | { |
b3694847 SS |
1829 | int ureg, sreg; |
1830 | int offset = 0; | |
2bbd3819 | 1831 | int usize, ssize; |
b3694847 | 1832 | int sqty; |
2bbd3819 RS |
1833 | |
1834 | /* Determine the numbers and sizes of registers being used. If a subreg | |
6dc42e49 | 1835 | is present that does not change the entire register, don't consider |
2bbd3819 RS |
1836 | this a copy insn. */ |
1837 | ||
1838 | while (GET_CODE (usedreg) == SUBREG) | |
1839 | { | |
44a5da09 GS |
1840 | rtx subreg = SUBREG_REG (usedreg); |
1841 | ||
f8cfc6aa | 1842 | if (REG_P (subreg)) |
44a5da09 GS |
1843 | { |
1844 | if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD) | |
1845 | may_save_copy = 0; | |
1846 | ||
1847 | if (REGNO (subreg) < FIRST_PSEUDO_REGISTER) | |
1848 | offset += subreg_regno_offset (REGNO (subreg), | |
1849 | GET_MODE (subreg), | |
1850 | SUBREG_BYTE (usedreg), | |
1851 | GET_MODE (usedreg)); | |
1852 | else | |
1853 | offset += (SUBREG_BYTE (usedreg) | |
1854 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
1855 | } | |
1856 | ||
1857 | usedreg = subreg; | |
2bbd3819 | 1858 | } |
44a5da09 | 1859 | |
f8cfc6aa | 1860 | if (!REG_P (usedreg)) |
2bbd3819 | 1861 | return 0; |
44a5da09 | 1862 | |
2bbd3819 | 1863 | ureg = REGNO (usedreg); |
ddef6bc7 | 1864 | if (ureg < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 1865 | usize = hard_regno_nregs[ureg][GET_MODE (usedreg)]; |
ddef6bc7 JJ |
1866 | else |
1867 | usize = ((GET_MODE_SIZE (GET_MODE (usedreg)) | |
1868 | + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1)) | |
1869 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
2bbd3819 RS |
1870 | |
1871 | while (GET_CODE (setreg) == SUBREG) | |
1872 | { | |
44a5da09 GS |
1873 | rtx subreg = SUBREG_REG (setreg); |
1874 | ||
f8cfc6aa | 1875 | if (REG_P (subreg)) |
44a5da09 GS |
1876 | { |
1877 | if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD) | |
1878 | may_save_copy = 0; | |
1879 | ||
1880 | if (REGNO (subreg) < FIRST_PSEUDO_REGISTER) | |
1881 | offset -= subreg_regno_offset (REGNO (subreg), | |
1882 | GET_MODE (subreg), | |
1883 | SUBREG_BYTE (setreg), | |
1884 | GET_MODE (setreg)); | |
1885 | else | |
1886 | offset -= (SUBREG_BYTE (setreg) | |
1887 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
1888 | } | |
1889 | ||
1890 | setreg = subreg; | |
2bbd3819 | 1891 | } |
44a5da09 | 1892 | |
f8cfc6aa | 1893 | if (!REG_P (setreg)) |
2bbd3819 | 1894 | return 0; |
44a5da09 | 1895 | |
2bbd3819 | 1896 | sreg = REGNO (setreg); |
ddef6bc7 | 1897 | if (sreg < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 1898 | ssize = hard_regno_nregs[sreg][GET_MODE (setreg)]; |
ddef6bc7 JJ |
1899 | else |
1900 | ssize = ((GET_MODE_SIZE (GET_MODE (setreg)) | |
1901 | + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1)) | |
1902 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
2bbd3819 RS |
1903 | |
1904 | /* If UREG is a pseudo-register that hasn't already been assigned a | |
1905 | quantity number, it means that it is not local to this block or dies | |
1906 | more than once. In either event, we can't do anything with it. */ | |
1907 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) | |
1908 | /* Do not combine registers unless one fits within the other. */ | |
1909 | || (offset > 0 && usize + offset > ssize) | |
1910 | || (offset < 0 && usize + offset < ssize) | |
1911 | /* Do not combine with a smaller already-assigned object | |
0f41302f | 1912 | if that smaller object is already combined with something bigger. */ |
2bbd3819 | 1913 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER |
a1ed7bdb | 1914 | && usize < qty[reg_qty[ureg]].size) |
2bbd3819 RS |
1915 | /* Can't combine if SREG is not a register we can allocate. */ |
1916 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) | |
1917 | /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. | |
1918 | These have already been taken care of. This probably wouldn't | |
1919 | combine anyway, but don't take any chances. */ | |
1920 | || (ureg >= FIRST_PSEUDO_REGISTER | |
1921 | && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) | |
1922 | /* Don't tie something to itself. In most cases it would make no | |
1923 | difference, but it would screw up if the reg being tied to itself | |
1924 | also dies in this insn. */ | |
1925 | || ureg == sreg | |
1926 | /* Don't try to connect two different hardware registers. */ | |
1927 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) | |
1928 | /* Don't connect two different machine modes if they have different | |
1929 | implications as to which registers may be used. */ | |
1930 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) | |
1931 | return 0; | |
1932 | ||
1933 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in | |
1934 | qty_phys_sugg for the pseudo instead of tying them. | |
1935 | ||
1936 | Return "failure" so that the lifespan of UREG is terminated here; | |
1937 | that way the two lifespans will be disjoint and nothing will prevent | |
1938 | the pseudo reg from being given this hard reg. */ | |
1939 | ||
1940 | if (ureg < FIRST_PSEUDO_REGISTER) | |
1941 | { | |
1942 | /* Allocate a quantity number so we have a place to put our | |
1943 | suggestions. */ | |
1944 | if (reg_qty[sreg] == -2) | |
1945 | reg_is_born (setreg, 2 * insn_number); | |
1946 | ||
1947 | if (reg_qty[sreg] >= 0) | |
1948 | { | |
51b86d8b RK |
1949 | if (may_save_copy |
1950 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) | |
2bbd3819 RS |
1951 | { |
1952 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1953 | qty_phys_num_copy_sugg[reg_qty[sreg]]++; |
2bbd3819 | 1954 | } |
51b86d8b | 1955 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) |
2bbd3819 RS |
1956 | { |
1957 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1958 | qty_phys_num_sugg[reg_qty[sreg]]++; |
2bbd3819 RS |
1959 | } |
1960 | } | |
1961 | return 0; | |
1962 | } | |
1963 | ||
1964 | /* Similarly for SREG a hard register and UREG a pseudo register. */ | |
1965 | ||
1966 | if (sreg < FIRST_PSEUDO_REGISTER) | |
1967 | { | |
51b86d8b RK |
1968 | if (may_save_copy |
1969 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) | |
2bbd3819 RS |
1970 | { |
1971 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1972 | qty_phys_num_copy_sugg[reg_qty[ureg]]++; |
2bbd3819 | 1973 | } |
51b86d8b | 1974 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) |
2bbd3819 RS |
1975 | { |
1976 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1977 | qty_phys_num_sugg[reg_qty[ureg]]++; |
2bbd3819 RS |
1978 | } |
1979 | return 0; | |
1980 | } | |
1981 | ||
1982 | /* At this point we know that SREG and UREG are both pseudos. | |
1983 | Do nothing if SREG already has a quantity or is a register that we | |
1984 | don't allocate. */ | |
1985 | if (reg_qty[sreg] >= -1 | |
1986 | /* If we are not going to let any regs live across calls, | |
1987 | don't tie a call-crossing reg to a non-call-crossing reg. */ | |
1988 | || (current_function_has_nonlocal_label | |
b1f21e0a MM |
1989 | && ((REG_N_CALLS_CROSSED (ureg) > 0) |
1990 | != (REG_N_CALLS_CROSSED (sreg) > 0)))) | |
2bbd3819 RS |
1991 | return 0; |
1992 | ||
1993 | /* We don't already know about SREG, so tie it to UREG | |
1994 | if this is the last use of UREG, provided the classes they want | |
1995 | are compatible. */ | |
1996 | ||
1997 | if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) | |
a1ed7bdb | 1998 | && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class)) |
2bbd3819 RS |
1999 | { |
2000 | /* Add SREG to UREG's quantity. */ | |
2001 | sqty = reg_qty[ureg]; | |
2002 | reg_qty[sreg] = sqty; | |
2003 | reg_offset[sreg] = reg_offset[ureg] + offset; | |
a1ed7bdb JH |
2004 | reg_next_in_qty[sreg] = qty[sqty].first_reg; |
2005 | qty[sqty].first_reg = sreg; | |
2bbd3819 | 2006 | |
a1ed7bdb | 2007 | /* If SREG's reg class is smaller, set qty[SQTY].min_class. */ |
2bbd3819 RS |
2008 | update_qty_class (sqty, sreg); |
2009 | ||
2010 | /* Update info about quantity SQTY. */ | |
a1ed7bdb JH |
2011 | qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg); |
2012 | qty[sqty].n_refs += REG_N_REFS (sreg); | |
b2aec5c0 | 2013 | qty[sqty].freq += REG_FREQ (sreg); |
2bbd3819 RS |
2014 | if (usize < ssize) |
2015 | { | |
b3694847 | 2016 | int i; |
2bbd3819 | 2017 | |
a1ed7bdb | 2018 | for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i]) |
2bbd3819 RS |
2019 | reg_offset[i] -= offset; |
2020 | ||
a1ed7bdb JH |
2021 | qty[sqty].size = ssize; |
2022 | qty[sqty].mode = GET_MODE (setreg); | |
2bbd3819 RS |
2023 | } |
2024 | } | |
2025 | else | |
2026 | return 0; | |
2027 | ||
2028 | return 1; | |
2029 | } | |
2030 | \f | |
2031 | /* Return 1 if the preferred class of REG allows it to be tied | |
2032 | to a quantity or register whose class is CLASS. | |
2033 | True if REG's reg class either contains or is contained in CLASS. */ | |
2034 | ||
2035 | static int | |
0c20a65f | 2036 | reg_meets_class_p (int reg, enum reg_class class) |
2bbd3819 | 2037 | { |
b3694847 | 2038 | enum reg_class rclass = reg_preferred_class (reg); |
2bbd3819 RS |
2039 | return (reg_class_subset_p (rclass, class) |
2040 | || reg_class_subset_p (class, rclass)); | |
2041 | } | |
2042 | ||
a1ed7bdb | 2043 | /* Update the class of QTYNO assuming that REG is being tied to it. */ |
2bbd3819 RS |
2044 | |
2045 | static void | |
0c20a65f | 2046 | update_qty_class (int qtyno, int reg) |
2bbd3819 RS |
2047 | { |
2048 | enum reg_class rclass = reg_preferred_class (reg); | |
a1ed7bdb JH |
2049 | if (reg_class_subset_p (rclass, qty[qtyno].min_class)) |
2050 | qty[qtyno].min_class = rclass; | |
e4600702 RK |
2051 | |
2052 | rclass = reg_alternate_class (reg); | |
a1ed7bdb JH |
2053 | if (reg_class_subset_p (rclass, qty[qtyno].alternate_class)) |
2054 | qty[qtyno].alternate_class = rclass; | |
2bbd3819 RS |
2055 | } |
2056 | \f | |
2057 | /* Handle something which alters the value of an rtx REG. | |
2058 | ||
2059 | REG is whatever is set or clobbered. SETTER is the rtx that | |
2060 | is modifying the register. | |
2061 | ||
2062 | If it is not really a register, we do nothing. | |
2063 | The file-global variables `this_insn' and `this_insn_number' | |
2064 | carry info from `block_alloc'. */ | |
2065 | ||
2066 | static void | |
0c20a65f | 2067 | reg_is_set (rtx reg, rtx setter, void *data ATTRIBUTE_UNUSED) |
2bbd3819 RS |
2068 | { |
2069 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of | |
2070 | a hard register. These may actually not exist any more. */ | |
2071 | ||
2072 | if (GET_CODE (reg) != SUBREG | |
f8cfc6aa | 2073 | && !REG_P (reg)) |
2bbd3819 RS |
2074 | return; |
2075 | ||
2076 | /* Mark this register as being born. If it is used in a CLOBBER, mark | |
2077 | it as being born halfway between the previous insn and this insn so that | |
2078 | it conflicts with our inputs but not the outputs of the previous insn. */ | |
2079 | ||
2080 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); | |
2081 | } | |
2082 | \f | |
2083 | /* Handle beginning of the life of register REG. | |
2084 | BIRTH is the index at which this is happening. */ | |
2085 | ||
2086 | static void | |
0c20a65f | 2087 | reg_is_born (rtx reg, int birth) |
2bbd3819 | 2088 | { |
b3694847 | 2089 | int regno; |
64e3a413 | 2090 | |
2bbd3819 | 2091 | if (GET_CODE (reg) == SUBREG) |
ddef6bc7 JJ |
2092 | { |
2093 | regno = REGNO (SUBREG_REG (reg)); | |
2094 | if (regno < FIRST_PSEUDO_REGISTER) | |
6f9e3578 | 2095 | regno = subreg_regno (reg); |
ddef6bc7 | 2096 | } |
2bbd3819 RS |
2097 | else |
2098 | regno = REGNO (reg); | |
2099 | ||
2100 | if (regno < FIRST_PSEUDO_REGISTER) | |
2101 | { | |
2102 | mark_life (regno, GET_MODE (reg), 1); | |
2103 | ||
2104 | /* If the register was to have been born earlier that the present | |
2105 | insn, mark it as live where it is actually born. */ | |
2106 | if (birth < 2 * this_insn_number) | |
2107 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); | |
2108 | } | |
2109 | else | |
2110 | { | |
2111 | if (reg_qty[regno] == -2) | |
2112 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); | |
2113 | ||
2114 | /* If this register has a quantity number, show that it isn't dead. */ | |
2115 | if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2116 | qty[reg_qty[regno]].death = -1; |
2bbd3819 RS |
2117 | } |
2118 | } | |
2119 | ||
cc2902df | 2120 | /* Record the death of REG in the current insn. If OUTPUT_P is nonzero, |
2bbd3819 | 2121 | REG is an output that is dying (i.e., it is never used), otherwise it |
333e0f7d RS |
2122 | is an input (the normal case). |
2123 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ | |
2bbd3819 RS |
2124 | |
2125 | static void | |
0c20a65f | 2126 | wipe_dead_reg (rtx reg, int output_p) |
2bbd3819 | 2127 | { |
b3694847 | 2128 | int regno = REGNO (reg); |
2bbd3819 | 2129 | |
333e0f7d RS |
2130 | /* If this insn has multiple results, |
2131 | and the dead reg is used in one of the results, | |
2132 | extend its life to after this insn, | |
64e3a413 | 2133 | so it won't get allocated together with any other result of this insn. |
941c63ac JL |
2134 | |
2135 | It is unsafe to use !single_set here since it will ignore an unused | |
2136 | output. Just because an output is unused does not mean the compiler | |
2137 | can assume the side effect will not occur. Consider if REG appears | |
2138 | in the address of an output and we reload the output. If we allocate | |
2139 | REG to the same hard register as an unused output we could set the hard | |
2140 | register before the output reload insn. */ | |
333e0f7d | 2141 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL |
941c63ac | 2142 | && multiple_sets (this_insn)) |
333e0f7d RS |
2143 | { |
2144 | int i; | |
2145 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) | |
2146 | { | |
2147 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); | |
2148 | if (GET_CODE (set) == SET | |
f8cfc6aa | 2149 | && !REG_P (SET_DEST (set)) |
333e0f7d RS |
2150 | && !rtx_equal_p (reg, SET_DEST (set)) |
2151 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2152 | output_p = 1; | |
2153 | } | |
2154 | } | |
2155 | ||
c182df0b RK |
2156 | /* If this register is used in an auto-increment address, then extend its |
2157 | life to after this insn, so that it won't get allocated together with | |
2158 | the result of this insn. */ | |
2159 | if (! output_p && find_regno_note (this_insn, REG_INC, regno)) | |
2160 | output_p = 1; | |
2161 | ||
2bbd3819 RS |
2162 | if (regno < FIRST_PSEUDO_REGISTER) |
2163 | { | |
2164 | mark_life (regno, GET_MODE (reg), 0); | |
2165 | ||
2166 | /* If a hard register is dying as an output, mark it as in use at | |
2167 | the beginning of this insn (the above statement would cause this | |
2168 | not to happen). */ | |
2169 | if (output_p) | |
2170 | post_mark_life (regno, GET_MODE (reg), 1, | |
64e3a413 | 2171 | 2 * this_insn_number, 2 * this_insn_number + 1); |
2bbd3819 RS |
2172 | } |
2173 | ||
2174 | else if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2175 | qty[reg_qty[regno]].death = 2 * this_insn_number + output_p; |
2bbd3819 RS |
2176 | } |
2177 | \f | |
2178 | /* Find a block of SIZE words of hard regs in reg_class CLASS | |
2179 | that can hold something of machine-mode MODE | |
2180 | (but actually we test only the first of the block for holding MODE) | |
2181 | and still free between insn BORN_INDEX and insn DEAD_INDEX, | |
2182 | and return the number of the first of them. | |
64e3a413 | 2183 | Return -1 if such a block cannot be found. |
a1ed7bdb | 2184 | If QTYNO crosses calls, insist on a register preserved by calls, |
2bbd3819 RS |
2185 | unless ACCEPT_CALL_CLOBBERED is nonzero. |
2186 | ||
cc2902df | 2187 | If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested |
2bbd3819 RS |
2188 | register is available. If not, return -1. */ |
2189 | ||
2190 | static int | |
0c20a65f AJ |
2191 | find_free_reg (enum reg_class class, enum machine_mode mode, int qtyno, |
2192 | int accept_call_clobbered, int just_try_suggested, | |
2193 | int born_index, int dead_index) | |
2bbd3819 | 2194 | { |
b3694847 | 2195 | int i, ins; |
cff9f8d5 | 2196 | HARD_REG_SET first_used, used; |
2bbd3819 | 2197 | #ifdef ELIMINABLE_REGS |
8b60264b | 2198 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
2bbd3819 RS |
2199 | #endif |
2200 | ||
2201 | /* Validate our parameters. */ | |
b5e624c6 | 2202 | gcc_assert (born_index >= 0 && born_index <= dead_index); |
2bbd3819 RS |
2203 | |
2204 | /* Don't let a pseudo live in a reg across a function call | |
2205 | if we might get a nonlocal goto. */ | |
2206 | if (current_function_has_nonlocal_label | |
a1ed7bdb | 2207 | && qty[qtyno].n_calls_crossed > 0) |
2bbd3819 RS |
2208 | return -1; |
2209 | ||
2210 | if (accept_call_clobbered) | |
2211 | COPY_HARD_REG_SET (used, call_fixed_reg_set); | |
a1ed7bdb | 2212 | else if (qty[qtyno].n_calls_crossed == 0) |
2bbd3819 RS |
2213 | COPY_HARD_REG_SET (used, fixed_reg_set); |
2214 | else | |
2215 | COPY_HARD_REG_SET (used, call_used_reg_set); | |
2216 | ||
6cad67d2 | 2217 | if (accept_call_clobbered) |
c09be6c4 | 2218 | IOR_HARD_REG_SET (used, losing_caller_save_reg_set); |
6cad67d2 | 2219 | |
2bbd3819 RS |
2220 | for (ins = born_index; ins < dead_index; ins++) |
2221 | IOR_HARD_REG_SET (used, regs_live_at[ins]); | |
2222 | ||
2223 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); | |
2224 | ||
2225 | /* Don't use the frame pointer reg in local-alloc even if | |
2226 | we may omit the frame pointer, because if we do that and then we | |
2227 | need a frame pointer, reload won't know how to move the pseudo | |
2228 | to another hard reg. It can move only regs made by global-alloc. | |
2229 | ||
2230 | This is true of any register that can be eliminated. */ | |
2231 | #ifdef ELIMINABLE_REGS | |
b6a1cbae | 2232 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) |
2bbd3819 | 2233 | SET_HARD_REG_BIT (used, eliminables[i].from); |
c2618f05 DE |
2234 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
2235 | /* If FRAME_POINTER_REGNUM is not a real register, then protect the one | |
0f41302f | 2236 | that it might be eliminated into. */ |
c2618f05 DE |
2237 | SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); |
2238 | #endif | |
2bbd3819 RS |
2239 | #else |
2240 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); | |
2241 | #endif | |
2242 | ||
cff9f8d5 AH |
2243 | #ifdef CANNOT_CHANGE_MODE_CLASS |
2244 | cannot_change_mode_set_regs (&used, mode, qty[qtyno].first_reg); | |
0f64b8f6 RK |
2245 | #endif |
2246 | ||
2bbd3819 RS |
2247 | /* Normally, the registers that can be used for the first register in |
2248 | a multi-register quantity are the same as those that can be used for | |
2249 | subsequent registers. However, if just trying suggested registers, | |
2250 | restrict our consideration to them. If there are copy-suggested | |
2251 | register, try them. Otherwise, try the arithmetic-suggested | |
2252 | registers. */ | |
2253 | COPY_HARD_REG_SET (first_used, used); | |
2254 | ||
2255 | if (just_try_suggested) | |
2256 | { | |
a1ed7bdb JH |
2257 | if (qty_phys_num_copy_sugg[qtyno] != 0) |
2258 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]); | |
2bbd3819 | 2259 | else |
a1ed7bdb | 2260 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]); |
2bbd3819 RS |
2261 | } |
2262 | ||
2263 | /* If all registers are excluded, we can't do anything. */ | |
2264 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); | |
2265 | ||
2266 | /* If at least one would be suitable, test each hard reg. */ | |
2267 | ||
2268 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2269 | { | |
2270 | #ifdef REG_ALLOC_ORDER | |
2271 | int regno = reg_alloc_order[i]; | |
2272 | #else | |
2273 | int regno = i; | |
2274 | #endif | |
2275 | if (! TEST_HARD_REG_BIT (first_used, regno) | |
1e326708 | 2276 | && HARD_REGNO_MODE_OK (regno, mode) |
a1ed7bdb | 2277 | && (qty[qtyno].n_calls_crossed == 0 |
1e326708 MH |
2278 | || accept_call_clobbered |
2279 | || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
2bbd3819 | 2280 | { |
b3694847 | 2281 | int j; |
66fd46b6 | 2282 | int size1 = hard_regno_nregs[regno][mode]; |
2bbd3819 RS |
2283 | for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); |
2284 | if (j == size1) | |
2285 | { | |
2286 | /* Mark that this register is in use between its birth and death | |
2287 | insns. */ | |
2288 | post_mark_life (regno, mode, 1, born_index, dead_index); | |
2289 | return regno; | |
2290 | } | |
2291 | #ifndef REG_ALLOC_ORDER | |
64e3a413 KH |
2292 | /* Skip starting points we know will lose. */ |
2293 | i += j; | |
2bbd3819 RS |
2294 | #endif |
2295 | } | |
2296 | } | |
2297 | ||
2298 | fail: | |
2bbd3819 RS |
2299 | /* If we are just trying suggested register, we have just tried copy- |
2300 | suggested registers, and there are arithmetic-suggested registers, | |
2301 | try them. */ | |
64e3a413 | 2302 | |
2bbd3819 RS |
2303 | /* If it would be profitable to allocate a call-clobbered register |
2304 | and save and restore it around calls, do that. */ | |
a1ed7bdb JH |
2305 | if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0 |
2306 | && qty_phys_num_sugg[qtyno] != 0) | |
2bbd3819 RS |
2307 | { |
2308 | /* Don't try the copy-suggested regs again. */ | |
a1ed7bdb JH |
2309 | qty_phys_num_copy_sugg[qtyno] = 0; |
2310 | return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1, | |
2bbd3819 RS |
2311 | born_index, dead_index); |
2312 | } | |
2313 | ||
e19f5192 RK |
2314 | /* We need not check to see if the current function has nonlocal |
2315 | labels because we don't put any pseudos that are live over calls in | |
2316 | registers in that case. */ | |
2317 | ||
2bbd3819 RS |
2318 | if (! accept_call_clobbered |
2319 | && flag_caller_saves | |
2320 | && ! just_try_suggested | |
a1ed7bdb | 2321 | && qty[qtyno].n_calls_crossed != 0 |
64e3a413 KH |
2322 | && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs, |
2323 | qty[qtyno].n_calls_crossed)) | |
2bbd3819 | 2324 | { |
a1ed7bdb | 2325 | i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index); |
2bbd3819 RS |
2326 | if (i >= 0) |
2327 | caller_save_needed = 1; | |
2328 | return i; | |
2329 | } | |
2330 | return -1; | |
2331 | } | |
2332 | \f | |
2333 | /* Mark that REGNO with machine-mode MODE is live starting from the current | |
cc2902df | 2334 | insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE |
2bbd3819 RS |
2335 | is zero). */ |
2336 | ||
2337 | static void | |
0c20a65f | 2338 | mark_life (int regno, enum machine_mode mode, int life) |
2bbd3819 | 2339 | { |
66fd46b6 | 2340 | int j = hard_regno_nregs[regno][mode]; |
2bbd3819 RS |
2341 | if (life) |
2342 | while (--j >= 0) | |
2343 | SET_HARD_REG_BIT (regs_live, regno + j); | |
2344 | else | |
2345 | while (--j >= 0) | |
2346 | CLEAR_HARD_REG_BIT (regs_live, regno + j); | |
2347 | } | |
2348 | ||
2349 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE | |
cc2902df | 2350 | is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) |
2bbd3819 RS |
2351 | to insn number DEATH (exclusive). */ |
2352 | ||
2353 | static void | |
0c20a65f AJ |
2354 | post_mark_life (int regno, enum machine_mode mode, int life, int birth, |
2355 | int death) | |
2bbd3819 | 2356 | { |
66fd46b6 | 2357 | int j = hard_regno_nregs[regno][mode]; |
49a27995 | 2358 | HARD_REG_SET this_reg; |
2bbd3819 RS |
2359 | |
2360 | CLEAR_HARD_REG_SET (this_reg); | |
2361 | while (--j >= 0) | |
2362 | SET_HARD_REG_BIT (this_reg, regno + j); | |
2363 | ||
2364 | if (life) | |
2365 | while (birth < death) | |
2366 | { | |
2367 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2368 | birth++; | |
2369 | } | |
2370 | else | |
2371 | while (birth < death) | |
2372 | { | |
2373 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2374 | birth++; | |
2375 | } | |
2376 | } | |
2377 | \f | |
2378 | /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 | |
2379 | is the register being clobbered, and R1 is a register being used in | |
2380 | the equivalent expression. | |
2381 | ||
2382 | If R1 dies in the block and has a REG_NO_CONFLICT note on every insn | |
2383 | in which it is used, return 1. | |
2384 | ||
2385 | Otherwise, return 0. */ | |
2386 | ||
2387 | static int | |
0c20a65f | 2388 | no_conflict_p (rtx insn, rtx r0 ATTRIBUTE_UNUSED, rtx r1) |
2bbd3819 RS |
2389 | { |
2390 | int ok = 0; | |
b1ec3c92 | 2391 | rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); |
2bbd3819 RS |
2392 | rtx p, last; |
2393 | ||
2394 | /* If R1 is a hard register, return 0 since we handle this case | |
2395 | when we scan the insns that actually use it. */ | |
2396 | ||
2397 | if (note == 0 | |
f8cfc6aa JQ |
2398 | || (REG_P (r1) && REGNO (r1) < FIRST_PSEUDO_REGISTER) |
2399 | || (GET_CODE (r1) == SUBREG && REG_P (SUBREG_REG (r1)) | |
2bbd3819 RS |
2400 | && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) |
2401 | return 0; | |
2402 | ||
2403 | last = XEXP (note, 0); | |
2404 | ||
2405 | for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) | |
2c3c49de | 2406 | if (INSN_P (p)) |
2bbd3819 RS |
2407 | { |
2408 | if (find_reg_note (p, REG_DEAD, r1)) | |
2409 | ok = 1; | |
2410 | ||
8bb19658 JW |
2411 | /* There must be a REG_NO_CONFLICT note on every insn, otherwise |
2412 | some earlier optimization pass has inserted instructions into | |
2413 | the sequence, and it is not safe to perform this optimization. | |
2414 | Note that emit_no_conflict_block always ensures that this is | |
2415 | true when these sequences are created. */ | |
2416 | if (! find_reg_note (p, REG_NO_CONFLICT, r1)) | |
2bbd3819 RS |
2417 | return 0; |
2418 | } | |
64e3a413 | 2419 | |
2bbd3819 RS |
2420 | return ok; |
2421 | } | |
2422 | \f | |
3061cc54 RK |
2423 | /* Return the number of alternatives for which the constraint string P |
2424 | indicates that the operand must be equal to operand 0 and that no register | |
2425 | is acceptable. */ | |
2bbd3819 RS |
2426 | |
2427 | static int | |
0c20a65f | 2428 | requires_inout (const char *p) |
2bbd3819 RS |
2429 | { |
2430 | char c; | |
2431 | int found_zero = 0; | |
3061cc54 RK |
2432 | int reg_allowed = 0; |
2433 | int num_matching_alts = 0; | |
97488870 | 2434 | int len; |
2bbd3819 | 2435 | |
dd1b7476 | 2436 | for ( ; (c = *p); p += len) |
97488870 R |
2437 | { |
2438 | len = CONSTRAINT_LEN (c, p); | |
2439 | switch (c) | |
2440 | { | |
2441 | case '=': case '+': case '?': | |
2442 | case '#': case '&': case '!': | |
2443 | case '*': case '%': | |
2444 | case 'm': case '<': case '>': case 'V': case 'o': | |
2445 | case 'E': case 'F': case 'G': case 'H': | |
2446 | case 's': case 'i': case 'n': | |
2447 | case 'I': case 'J': case 'K': case 'L': | |
2448 | case 'M': case 'N': case 'O': case 'P': | |
2449 | case 'X': | |
2450 | /* These don't say anything we care about. */ | |
2451 | break; | |
2bbd3819 | 2452 | |
97488870 R |
2453 | case ',': |
2454 | if (found_zero && ! reg_allowed) | |
2455 | num_matching_alts++; | |
3061cc54 | 2456 | |
97488870 R |
2457 | found_zero = reg_allowed = 0; |
2458 | break; | |
3061cc54 | 2459 | |
97488870 R |
2460 | case '0': |
2461 | found_zero = 1; | |
2462 | break; | |
3061cc54 | 2463 | |
97488870 R |
2464 | case '1': case '2': case '3': case '4': case '5': |
2465 | case '6': case '7': case '8': case '9': | |
2466 | /* Skip the balance of the matching constraint. */ | |
2467 | do | |
2468 | p++; | |
2469 | while (ISDIGIT (*p)); | |
2470 | len = 0; | |
2471 | break; | |
84b72302 | 2472 | |
97488870 R |
2473 | default: |
2474 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS | |
2475 | && !EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
2476 | break; | |
5d3cc252 | 2477 | /* Fall through. */ |
97488870 R |
2478 | case 'p': |
2479 | case 'g': case 'r': | |
2480 | reg_allowed = 1; | |
c2cba7a9 | 2481 | break; |
97488870 R |
2482 | } |
2483 | } | |
2bbd3819 | 2484 | |
3061cc54 RK |
2485 | if (found_zero && ! reg_allowed) |
2486 | num_matching_alts++; | |
2487 | ||
2488 | return num_matching_alts; | |
2bbd3819 RS |
2489 | } |
2490 | \f | |
2491 | void | |
0c20a65f | 2492 | dump_local_alloc (FILE *file) |
2bbd3819 | 2493 | { |
b3694847 | 2494 | int i; |
2bbd3819 RS |
2495 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
2496 | if (reg_renumber[i] != -1) | |
2497 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); | |
2498 | } |