]>
Commit | Line | Data |
---|---|---|
2bbd3819 | 1 | /* Allocate registers within a basic block, for GNU compiler. |
d050d723 JL |
2 | Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
2bbd3819 RS |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
a35311b0 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
2bbd3819 | 21 | |
2bbd3819 RS |
22 | /* Allocation of hard register numbers to pseudo registers is done in |
23 | two passes. In this pass we consider only regs that are born and | |
24 | die once within one basic block. We do this one basic block at a | |
25 | time. Then the next pass allocates the registers that remain. | |
26 | Two passes are used because this pass uses methods that work only | |
27 | on linear code, but that do a better job than the general methods | |
28 | used in global_alloc, and more quickly too. | |
29 | ||
30 | The assignments made are recorded in the vector reg_renumber | |
31 | whose space is allocated here. The rtl code itself is not altered. | |
32 | ||
33 | We assign each instruction in the basic block a number | |
34 | which is its order from the beginning of the block. | |
35 | Then we can represent the lifetime of a pseudo register with | |
36 | a pair of numbers, and check for conflicts easily. | |
37 | We can record the availability of hard registers with a | |
38 | HARD_REG_SET for each instruction. The HARD_REG_SET | |
39 | contains 0 or 1 for each hard reg. | |
40 | ||
41 | To avoid register shuffling, we tie registers together when one | |
42 | dies by being copied into another, or dies in an instruction that | |
43 | does arithmetic to produce another. The tied registers are | |
44 | allocated as one. Registers with different reg class preferences | |
45 | can never be tied unless the class preferred by one is a subclass | |
46 | of the one preferred by the other. | |
47 | ||
48 | Tying is represented with "quantity numbers". | |
49 | A non-tied register is given a new quantity number. | |
50 | Tied registers have the same quantity number. | |
64e3a413 | 51 | |
2bbd3819 RS |
52 | We have provision to exempt registers, even when they are contained |
53 | within the block, that can be tied to others that are not contained in it. | |
54 | This is so that global_alloc could process them both and tie them then. | |
55 | But this is currently disabled since tying in global_alloc is not | |
56 | yet implemented. */ | |
57 | ||
a300b8d9 JW |
58 | /* Pseudos allocated here can be reallocated by global.c if the hard register |
59 | is used as a spill register. Currently we don't allocate such pseudos | |
6cad67d2 JL |
60 | here if their preferred class is likely to be used by spills. */ |
61 | ||
2bbd3819 | 62 | #include "config.h" |
670ee920 | 63 | #include "system.h" |
2bbd3819 | 64 | #include "rtl.h" |
6baf1cc8 | 65 | #include "tm_p.h" |
2bbd3819 | 66 | #include "flags.h" |
efc9bd41 | 67 | #include "hard-reg-set.h" |
2bbd3819 RS |
68 | #include "basic-block.h" |
69 | #include "regs.h" | |
49ad7cfa | 70 | #include "function.h" |
2bbd3819 | 71 | #include "insn-config.h" |
624a8b3a | 72 | #include "insn-attr.h" |
2bbd3819 RS |
73 | #include "recog.h" |
74 | #include "output.h" | |
2e107e9e | 75 | #include "toplev.h" |
2bbd3819 RS |
76 | \f |
77 | /* Next quantity number available for allocation. */ | |
78 | ||
79 | static int next_qty; | |
80 | ||
a1ed7bdb JH |
81 | /* Information we maitain about each quantity. */ |
82 | struct qty | |
83 | { | |
84 | /* The number of refs to quantity Q. */ | |
2bbd3819 | 85 | |
a1ed7bdb | 86 | int n_refs; |
2bbd3819 | 87 | |
a1ed7bdb JH |
88 | /* Insn number (counting from head of basic block) |
89 | where quantity Q was born. -1 if birth has not been recorded. */ | |
2bbd3819 | 90 | |
a1ed7bdb | 91 | int birth; |
2bbd3819 | 92 | |
a1ed7bdb JH |
93 | /* Insn number (counting from head of basic block) |
94 | where given quantity died. Due to the way tying is done, | |
95 | and the fact that we consider in this pass only regs that die but once, | |
96 | a quantity can die only once. Each quantity's life span | |
97 | is a set of consecutive insns. -1 if death has not been recorded. */ | |
2bbd3819 | 98 | |
a1ed7bdb | 99 | int death; |
2bbd3819 | 100 | |
a1ed7bdb JH |
101 | /* Number of words needed to hold the data in given quantity. |
102 | This depends on its machine mode. It is used for these purposes: | |
103 | 1. It is used in computing the relative importances of qtys, | |
104 | which determines the order in which we look for regs for them. | |
105 | 2. It is used in rules that prevent tying several registers of | |
106 | different sizes in a way that is geometrically impossible | |
107 | (see combine_regs). */ | |
2bbd3819 | 108 | |
a1ed7bdb | 109 | int size; |
2bbd3819 | 110 | |
a1ed7bdb | 111 | /* Number of times a reg tied to given qty lives across a CALL_INSN. */ |
2bbd3819 | 112 | |
a1ed7bdb | 113 | int n_calls_crossed; |
2bbd3819 | 114 | |
a1ed7bdb JH |
115 | /* The register number of one pseudo register whose reg_qty value is Q. |
116 | This register should be the head of the chain | |
117 | maintained in reg_next_in_qty. */ | |
2bbd3819 | 118 | |
a1ed7bdb | 119 | int first_reg; |
2bbd3819 | 120 | |
a1ed7bdb JH |
121 | /* Reg class contained in (smaller than) the preferred classes of all |
122 | the pseudo regs that are tied in given quantity. | |
123 | This is the preferred class for allocating that quantity. */ | |
124 | ||
125 | enum reg_class min_class; | |
2bbd3819 | 126 | |
a1ed7bdb JH |
127 | /* Register class within which we allocate given qty if we can't get |
128 | its preferred class. */ | |
2bbd3819 | 129 | |
a1ed7bdb | 130 | enum reg_class alternate_class; |
2bbd3819 | 131 | |
a1ed7bdb JH |
132 | /* This holds the mode of the registers that are tied to given qty, |
133 | or VOIDmode if registers with differing modes are tied together. */ | |
2bbd3819 | 134 | |
a1ed7bdb | 135 | enum machine_mode mode; |
2bbd3819 | 136 | |
a1ed7bdb JH |
137 | /* the hard reg number chosen for given quantity, |
138 | or -1 if none was found. */ | |
2bbd3819 | 139 | |
a1ed7bdb | 140 | short phys_reg; |
2bbd3819 | 141 | |
02188693 RH |
142 | /* Nonzero if this quantity has been used in a SUBREG in some |
143 | way that is illegal. */ | |
2bbd3819 | 144 | |
02188693 | 145 | char changes_mode; |
2bbd3819 | 146 | |
a1ed7bdb | 147 | }; |
2bbd3819 | 148 | |
a1ed7bdb | 149 | static struct qty *qty; |
2bbd3819 | 150 | |
a1ed7bdb | 151 | /* These fields are kept separately to speedup their clearing. */ |
2bbd3819 | 152 | |
a1ed7bdb JH |
153 | /* We maintain two hard register sets that indicate suggested hard registers |
154 | for each quantity. The first, phys_copy_sugg, contains hard registers | |
155 | that are tied to the quantity by a simple copy. The second contains all | |
156 | hard registers that are tied to the quantity via an arithmetic operation. | |
2bbd3819 | 157 | |
a1ed7bdb JH |
158 | The former register set is given priority for allocation. This tends to |
159 | eliminate copy insns. */ | |
2bbd3819 | 160 | |
a1ed7bdb JH |
161 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
162 | copy insns. */ | |
2bbd3819 | 163 | |
a1ed7bdb | 164 | static HARD_REG_SET *qty_phys_copy_sugg; |
2bbd3819 | 165 | |
a1ed7bdb JH |
166 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
167 | arithmetic insns. */ | |
168 | ||
169 | static HARD_REG_SET *qty_phys_sugg; | |
170 | ||
171 | /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ | |
2bbd3819 | 172 | |
a1ed7bdb | 173 | static short *qty_phys_num_copy_sugg; |
0f64b8f6 | 174 | |
a1ed7bdb | 175 | /* Element Q is the number of suggested registers in qty_phys_sugg. */ |
0f64b8f6 | 176 | |
a1ed7bdb | 177 | static short *qty_phys_num_sugg; |
2bbd3819 | 178 | |
2bbd3819 RS |
179 | /* If (REG N) has been assigned a quantity number, is a register number |
180 | of another register assigned the same quantity number, or -1 for the | |
a1ed7bdb | 181 | end of the chain. qty->first_reg point to the head of this chain. */ |
2bbd3819 | 182 | |
aabf56ce | 183 | static int *reg_next_in_qty; |
2bbd3819 RS |
184 | |
185 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg | |
186 | if it is >= 0, | |
187 | of -1 if this register cannot be allocated by local-alloc, | |
188 | or -2 if not known yet. | |
189 | ||
190 | Note that if we see a use or death of pseudo register N with | |
191 | reg_qty[N] == -2, register N must be local to the current block. If | |
192 | it were used in more than one block, we would have reg_qty[N] == -1. | |
193 | This relies on the fact that if reg_basic_block[N] is >= 0, register N | |
194 | will not appear in any other block. We save a considerable number of | |
195 | tests by exploiting this. | |
196 | ||
197 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not | |
198 | be referenced. */ | |
199 | ||
200 | static int *reg_qty; | |
201 | ||
202 | /* The offset (in words) of register N within its quantity. | |
203 | This can be nonzero if register N is SImode, and has been tied | |
204 | to a subreg of a DImode register. */ | |
205 | ||
206 | static char *reg_offset; | |
207 | ||
208 | /* Vector of substitutions of register numbers, | |
209 | used to map pseudo regs into hardware regs. | |
210 | This is set up as a result of register allocation. | |
211 | Element N is the hard reg assigned to pseudo reg N, | |
212 | or is -1 if no hard reg was assigned. | |
213 | If N is a hard reg number, element N is N. */ | |
214 | ||
215 | short *reg_renumber; | |
216 | ||
217 | /* Set of hard registers live at the current point in the scan | |
218 | of the instructions in a basic block. */ | |
219 | ||
220 | static HARD_REG_SET regs_live; | |
221 | ||
222 | /* Each set of hard registers indicates registers live at a particular | |
223 | point in the basic block. For N even, regs_live_at[N] says which | |
224 | hard registers are needed *after* insn N/2 (i.e., they may not | |
225 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. | |
226 | ||
227 | If an object is to conflict with the inputs of insn J but not the | |
228 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, | |
229 | if it is to conflict with the outputs of insn J but not the inputs of | |
230 | insn J + 1, it is said to die at index J*2 + 1. */ | |
231 | ||
232 | static HARD_REG_SET *regs_live_at; | |
233 | ||
234 | /* Communicate local vars `insn_number' and `insn' | |
235 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ | |
236 | static int this_insn_number; | |
237 | static rtx this_insn; | |
238 | ||
bf6d9fd7 JW |
239 | struct equivalence |
240 | { | |
241 | /* Set when an attempt should be made to replace a register | |
242 | with the associated src entry. */ | |
243 | ||
244 | char replace; | |
245 | ||
246 | /* Set when a REG_EQUIV note is found or created. Use to | |
247 | keep track of what memory accesses might be created later, | |
248 | e.g. by reload. */ | |
249 | ||
250 | rtx replacement; | |
68342d36 | 251 | |
bf6d9fd7 | 252 | rtx src; |
c25a4c25 | 253 | |
bf6d9fd7 JW |
254 | /* Loop depth is used to recognize equivalences which appear |
255 | to be present within the same loop (or in an inner loop). */ | |
256 | ||
257 | int loop_depth; | |
258 | ||
259 | /* The list of each instruction which initializes this register. */ | |
260 | ||
261 | rtx init_insns; | |
262 | }; | |
263 | ||
264 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
265 | structure for that register. */ | |
266 | ||
267 | static struct equivalence *reg_equiv; | |
135eb61c | 268 | |
3f1b9b1b JL |
269 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
270 | static int recorded_label_ref; | |
271 | ||
3fe41456 KG |
272 | static void alloc_qty PARAMS ((int, enum machine_mode, int, int)); |
273 | static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *)); | |
274 | static int validate_equiv_mem PARAMS ((rtx, rtx, rtx)); | |
bf6d9fd7 JW |
275 | static int equiv_init_varies_p PARAMS ((rtx)); |
276 | static int equiv_init_movable_p PARAMS ((rtx, int)); | |
277 | static int contains_replace_regs PARAMS ((rtx)); | |
3fe41456 KG |
278 | static int memref_referenced_p PARAMS ((rtx, rtx)); |
279 | static int memref_used_between_p PARAMS ((rtx, rtx, rtx)); | |
280 | static void update_equiv_regs PARAMS ((void)); | |
281 | static void no_equiv PARAMS ((rtx, rtx, void *)); | |
282 | static void block_alloc PARAMS ((int)); | |
283 | static int qty_sugg_compare PARAMS ((int, int)); | |
284 | static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR)); | |
285 | static int qty_compare PARAMS ((int, int)); | |
286 | static int qty_compare_1 PARAMS ((const PTR, const PTR)); | |
287 | static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int)); | |
288 | static int reg_meets_class_p PARAMS ((int, enum reg_class)); | |
289 | static void update_qty_class PARAMS ((int, int)); | |
290 | static void reg_is_set PARAMS ((rtx, rtx, void *)); | |
291 | static void reg_is_born PARAMS ((rtx, int)); | |
292 | static void wipe_dead_reg PARAMS ((rtx, int)); | |
293 | static int find_free_reg PARAMS ((enum reg_class, enum machine_mode, | |
82c68a78 | 294 | int, int, int, int, int)); |
3fe41456 KG |
295 | static void mark_life PARAMS ((int, enum machine_mode, int)); |
296 | static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int)); | |
297 | static int no_conflict_p PARAMS ((rtx, rtx, rtx)); | |
298 | static int requires_inout PARAMS ((const char *)); | |
2bbd3819 RS |
299 | \f |
300 | /* Allocate a new quantity (new within current basic block) | |
301 | for register number REGNO which is born at index BIRTH | |
302 | within the block. MODE and SIZE are info on reg REGNO. */ | |
303 | ||
304 | static void | |
305 | alloc_qty (regno, mode, size, birth) | |
306 | int regno; | |
307 | enum machine_mode mode; | |
308 | int size, birth; | |
309 | { | |
a1ed7bdb | 310 | register int qtyno = next_qty++; |
2bbd3819 | 311 | |
a1ed7bdb | 312 | reg_qty[regno] = qtyno; |
2bbd3819 RS |
313 | reg_offset[regno] = 0; |
314 | reg_next_in_qty[regno] = -1; | |
315 | ||
a1ed7bdb JH |
316 | qty[qtyno].first_reg = regno; |
317 | qty[qtyno].size = size; | |
318 | qty[qtyno].mode = mode; | |
319 | qty[qtyno].birth = birth; | |
320 | qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno); | |
321 | qty[qtyno].min_class = reg_preferred_class (regno); | |
322 | qty[qtyno].alternate_class = reg_alternate_class (regno); | |
323 | qty[qtyno].n_refs = REG_N_REFS (regno); | |
02188693 | 324 | qty[qtyno].changes_mode = REG_CHANGES_MODE (regno); |
2bbd3819 RS |
325 | } |
326 | \f | |
2bbd3819 RS |
327 | /* Main entry point of this file. */ |
328 | ||
3f1b9b1b | 329 | int |
2bbd3819 RS |
330 | local_alloc () |
331 | { | |
332 | register int b, i; | |
333 | int max_qty; | |
334 | ||
3f1b9b1b JL |
335 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
336 | that we know if the jump optimizer needs to be rerun. */ | |
337 | recorded_label_ref = 0; | |
338 | ||
2bbd3819 RS |
339 | /* Leaf functions and non-leaf functions have different needs. |
340 | If defined, let the machine say what kind of ordering we | |
341 | should use. */ | |
342 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC | |
343 | ORDER_REGS_FOR_LOCAL_ALLOC; | |
344 | #endif | |
345 | ||
346 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected | |
347 | registers. */ | |
348 | update_equiv_regs (); | |
349 | ||
350 | /* This sets the maximum number of quantities we can have. Quantity | |
34f89b5f BS |
351 | numbers start at zero and we can have one for each pseudo. */ |
352 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER); | |
2bbd3819 RS |
353 | |
354 | /* Allocate vectors of temporary data. | |
355 | See the declarations of these variables, above, | |
356 | for what they mean. */ | |
357 | ||
a1ed7bdb | 358 | qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty)); |
4c9a05bc | 359 | qty_phys_copy_sugg |
75c6bd46 RH |
360 | = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET)); |
361 | qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short)); | |
362 | qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET)); | |
363 | qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short)); | |
2bbd3819 | 364 | |
83cbe7e4 RH |
365 | reg_qty = (int *) xmalloc (max_regno * sizeof (int)); |
366 | reg_offset = (char *) xmalloc (max_regno * sizeof (char)); | |
64e3a413 | 367 | reg_next_in_qty = (int *) xmalloc (max_regno * sizeof (int)); |
2bbd3819 | 368 | |
64e3a413 | 369 | /* Allocate the reg_renumber array. */ |
39379e67 | 370 | allocate_reg_info (max_regno, FALSE, TRUE); |
2bbd3819 RS |
371 | |
372 | /* Determine which pseudo-registers can be allocated by local-alloc. | |
373 | In general, these are the registers used only in a single block and | |
611bbf2a | 374 | which only die once. |
2bbd3819 RS |
375 | |
376 | We need not be concerned with which block actually uses the register | |
377 | since we will never see it outside that block. */ | |
378 | ||
379 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
380 | { | |
611bbf2a | 381 | if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1) |
2bbd3819 RS |
382 | reg_qty[i] = -2; |
383 | else | |
384 | reg_qty[i] = -1; | |
385 | } | |
386 | ||
387 | /* Force loop below to initialize entire quantity array. */ | |
388 | next_qty = max_qty; | |
389 | ||
390 | /* Allocate each block's local registers, block by block. */ | |
391 | ||
392 | for (b = 0; b < n_basic_blocks; b++) | |
393 | { | |
394 | /* NEXT_QTY indicates which elements of the `qty_...' | |
395 | vectors might need to be initialized because they were used | |
396 | for the previous block; it is set to the entire array before | |
397 | block 0. Initialize those, with explicit loop if there are few, | |
398 | else with bzero and bcopy. Do not initialize vectors that are | |
399 | explicit set by `alloc_qty'. */ | |
400 | ||
401 | if (next_qty < 6) | |
402 | { | |
403 | for (i = 0; i < next_qty; i++) | |
404 | { | |
2bbd3819 | 405 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); |
51b86d8b | 406 | qty_phys_num_copy_sugg[i] = 0; |
2bbd3819 | 407 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); |
51b86d8b | 408 | qty_phys_num_sugg[i] = 0; |
2bbd3819 RS |
409 | } |
410 | } | |
411 | else | |
412 | { | |
413 | #define CLEAR(vector) \ | |
961192e1 | 414 | memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty); |
2bbd3819 | 415 | |
2bbd3819 | 416 | CLEAR (qty_phys_copy_sugg); |
51b86d8b | 417 | CLEAR (qty_phys_num_copy_sugg); |
2bbd3819 | 418 | CLEAR (qty_phys_sugg); |
51b86d8b | 419 | CLEAR (qty_phys_num_sugg); |
2bbd3819 RS |
420 | } |
421 | ||
422 | next_qty = 0; | |
423 | ||
424 | block_alloc (b); | |
2bbd3819 | 425 | } |
83cbe7e4 | 426 | |
a1ed7bdb | 427 | free (qty); |
75c6bd46 RH |
428 | free (qty_phys_copy_sugg); |
429 | free (qty_phys_num_copy_sugg); | |
430 | free (qty_phys_sugg); | |
e7749837 | 431 | free (qty_phys_num_sugg); |
75c6bd46 | 432 | |
83cbe7e4 RH |
433 | free (reg_qty); |
434 | free (reg_offset); | |
435 | free (reg_next_in_qty); | |
75c6bd46 | 436 | |
3f1b9b1b | 437 | return recorded_label_ref; |
2bbd3819 RS |
438 | } |
439 | \f | |
2bbd3819 RS |
440 | /* Used for communication between the following two functions: contains |
441 | a MEM that we wish to ensure remains unchanged. */ | |
442 | static rtx equiv_mem; | |
443 | ||
444 | /* Set nonzero if EQUIV_MEM is modified. */ | |
445 | static int equiv_mem_modified; | |
446 | ||
447 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
448 | Called via note_stores. */ | |
449 | ||
450 | static void | |
84832317 | 451 | validate_equiv_mem_from_store (dest, set, data) |
2bbd3819 | 452 | rtx dest; |
e51712db | 453 | rtx set ATTRIBUTE_UNUSED; |
84832317 | 454 | void *data ATTRIBUTE_UNUSED; |
2bbd3819 RS |
455 | { |
456 | if ((GET_CODE (dest) == REG | |
457 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
458 | || (GET_CODE (dest) == MEM | |
9ae8ffe7 | 459 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) |
2bbd3819 RS |
460 | equiv_mem_modified = 1; |
461 | } | |
462 | ||
463 | /* Verify that no store between START and the death of REG invalidates | |
464 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
465 | by storing into an overlapping memory location, or with a non-const | |
466 | CALL_INSN. | |
467 | ||
468 | Return 1 if MEMREF remains valid. */ | |
469 | ||
470 | static int | |
471 | validate_equiv_mem (start, reg, memref) | |
472 | rtx start; | |
473 | rtx reg; | |
474 | rtx memref; | |
475 | { | |
476 | rtx insn; | |
477 | rtx note; | |
478 | ||
479 | equiv_mem = memref; | |
480 | equiv_mem_modified = 0; | |
481 | ||
482 | /* If the memory reference has side effects or is volatile, it isn't a | |
483 | valid equivalence. */ | |
484 | if (side_effects_p (memref)) | |
485 | return 0; | |
486 | ||
487 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
488 | { | |
2c3c49de | 489 | if (! INSN_P (insn)) |
2bbd3819 RS |
490 | continue; |
491 | ||
492 | if (find_reg_note (insn, REG_DEAD, reg)) | |
493 | return 1; | |
494 | ||
495 | if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) | |
496 | && ! CONST_CALL_P (insn)) | |
497 | return 0; | |
498 | ||
84832317 | 499 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); |
2bbd3819 RS |
500 | |
501 | /* If a register mentioned in MEMREF is modified via an | |
502 | auto-increment, we lose the equivalence. Do the same if one | |
503 | dies; although we could extend the life, it doesn't seem worth | |
504 | the trouble. */ | |
505 | ||
506 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
507 | if ((REG_NOTE_KIND (note) == REG_INC | |
508 | || REG_NOTE_KIND (note) == REG_DEAD) | |
509 | && GET_CODE (XEXP (note, 0)) == REG | |
510 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
511 | return 0; | |
512 | } | |
513 | ||
514 | return 0; | |
515 | } | |
a1729519 | 516 | |
bf6d9fd7 JW |
517 | /* Returns zero if X is known to be invariant. */ |
518 | ||
519 | static int | |
520 | equiv_init_varies_p (x) | |
521 | rtx x; | |
522 | { | |
523 | register RTX_CODE code = GET_CODE (x); | |
524 | register int i; | |
525 | register const char *fmt; | |
526 | ||
527 | switch (code) | |
528 | { | |
529 | case MEM: | |
530 | return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
531 | ||
532 | case QUEUED: | |
533 | return 1; | |
534 | ||
535 | case CONST: | |
536 | case CONST_INT: | |
537 | case CONST_DOUBLE: | |
538 | case SYMBOL_REF: | |
539 | case LABEL_REF: | |
540 | return 0; | |
541 | ||
542 | case REG: | |
543 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x); | |
544 | ||
545 | case ASM_OPERANDS: | |
546 | if (MEM_VOLATILE_P (x)) | |
547 | return 1; | |
548 | ||
549 | /* FALLTHROUGH */ | |
550 | ||
551 | default: | |
552 | break; | |
553 | } | |
554 | ||
555 | fmt = GET_RTX_FORMAT (code); | |
556 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
557 | if (fmt[i] == 'e') | |
558 | { | |
559 | if (equiv_init_varies_p (XEXP (x, i))) | |
560 | return 1; | |
561 | } | |
562 | else if (fmt[i] == 'E') | |
563 | { | |
564 | int j; | |
565 | for (j = 0; j < XVECLEN (x, i); j++) | |
566 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
567 | return 1; | |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | /* Returns non-zero if X (used to initialize register REGNO) is movable. | |
574 | X is only movable if the registers it uses have equivalent initializations | |
575 | which appear to be within the same loop (or in an inner loop) and movable | |
576 | or if they are not candidates for local_alloc and don't vary. */ | |
a1729519 JW |
577 | |
578 | static int | |
bf6d9fd7 JW |
579 | equiv_init_movable_p (x, regno) |
580 | rtx x; | |
581 | int regno; | |
582 | { | |
583 | int i, j; | |
584 | const char *fmt; | |
585 | enum rtx_code code = GET_CODE (x); | |
586 | ||
587 | switch (code) | |
588 | { | |
589 | case SET: | |
590 | return equiv_init_movable_p (SET_SRC (x), regno); | |
591 | ||
d9068c61 | 592 | case CC0: |
bf6d9fd7 JW |
593 | case CLOBBER: |
594 | return 0; | |
595 | ||
596 | case PRE_INC: | |
597 | case PRE_DEC: | |
598 | case POST_INC: | |
599 | case POST_DEC: | |
600 | case PRE_MODIFY: | |
601 | case POST_MODIFY: | |
602 | return 0; | |
603 | ||
604 | case REG: | |
605 | return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth | |
606 | && reg_equiv[REGNO (x)].replace) | |
607 | || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x)); | |
608 | ||
609 | case UNSPEC_VOLATILE: | |
610 | return 0; | |
611 | ||
612 | case ASM_OPERANDS: | |
613 | if (MEM_VOLATILE_P (x)) | |
614 | return 0; | |
615 | ||
616 | /* FALLTHROUGH */ | |
617 | ||
618 | default: | |
619 | break; | |
620 | } | |
621 | ||
622 | fmt = GET_RTX_FORMAT (code); | |
623 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
624 | switch (fmt[i]) | |
625 | { | |
626 | case 'e': | |
627 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
628 | return 0; | |
629 | break; | |
630 | case 'E': | |
631 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
632 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
633 | return 0; | |
634 | break; | |
635 | } | |
636 | ||
637 | return 1; | |
638 | } | |
639 | ||
640 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */ | |
641 | ||
642 | static int | |
643 | contains_replace_regs (x) | |
a1729519 | 644 | rtx x; |
a1729519 JW |
645 | { |
646 | int i, j; | |
6f7d635c | 647 | const char *fmt; |
a1729519 JW |
648 | enum rtx_code code = GET_CODE (x); |
649 | ||
650 | switch (code) | |
651 | { | |
652 | case CONST_INT: | |
653 | case CONST: | |
654 | case LABEL_REF: | |
655 | case SYMBOL_REF: | |
656 | case CONST_DOUBLE: | |
657 | case PC: | |
658 | case CC0: | |
659 | case HIGH: | |
660 | case LO_SUM: | |
661 | return 0; | |
662 | ||
663 | case REG: | |
bf6d9fd7 | 664 | return reg_equiv[REGNO (x)].replace; |
1d300e19 KG |
665 | |
666 | default: | |
667 | break; | |
a1729519 JW |
668 | } |
669 | ||
670 | fmt = GET_RTX_FORMAT (code); | |
671 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
672 | switch (fmt[i]) | |
673 | { | |
674 | case 'e': | |
bf6d9fd7 | 675 | if (contains_replace_regs (XEXP (x, i))) |
a1729519 JW |
676 | return 1; |
677 | break; | |
678 | case 'E': | |
679 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
bf6d9fd7 | 680 | if (contains_replace_regs (XVECEXP (x, i, j))) |
a1729519 JW |
681 | return 1; |
682 | break; | |
683 | } | |
684 | ||
685 | return 0; | |
686 | } | |
2bbd3819 RS |
687 | \f |
688 | /* TRUE if X references a memory location that would be affected by a store | |
689 | to MEMREF. */ | |
690 | ||
691 | static int | |
692 | memref_referenced_p (memref, x) | |
693 | rtx x; | |
694 | rtx memref; | |
695 | { | |
696 | int i, j; | |
6f7d635c | 697 | const char *fmt; |
2bbd3819 RS |
698 | enum rtx_code code = GET_CODE (x); |
699 | ||
700 | switch (code) | |
701 | { | |
2bbd3819 RS |
702 | case CONST_INT: |
703 | case CONST: | |
704 | case LABEL_REF: | |
705 | case SYMBOL_REF: | |
706 | case CONST_DOUBLE: | |
707 | case PC: | |
708 | case CC0: | |
709 | case HIGH: | |
710 | case LO_SUM: | |
711 | return 0; | |
712 | ||
c25a4c25 | 713 | case REG: |
bf6d9fd7 | 714 | return (reg_equiv[REGNO (x)].replacement |
3298a1b1 | 715 | && memref_referenced_p (memref, |
bf6d9fd7 | 716 | reg_equiv[REGNO (x)].replacement)); |
c25a4c25 | 717 | |
2bbd3819 | 718 | case MEM: |
9ae8ffe7 | 719 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) |
2bbd3819 RS |
720 | return 1; |
721 | break; | |
722 | ||
723 | case SET: | |
724 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
725 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
726 | if (GET_CODE (SET_DEST (x)) == MEM) | |
727 | { | |
728 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
729 | return 1; | |
730 | } | |
731 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
732 | return 1; | |
733 | ||
734 | return memref_referenced_p (memref, SET_SRC (x)); | |
64e3a413 | 735 | |
e9a25f70 JL |
736 | default: |
737 | break; | |
2bbd3819 RS |
738 | } |
739 | ||
740 | fmt = GET_RTX_FORMAT (code); | |
741 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
742 | switch (fmt[i]) | |
743 | { | |
744 | case 'e': | |
745 | if (memref_referenced_p (memref, XEXP (x, i))) | |
746 | return 1; | |
747 | break; | |
748 | case 'E': | |
749 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
750 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
751 | return 1; | |
752 | break; | |
753 | } | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
758 | /* TRUE if some insn in the range (START, END] references a memory location | |
759 | that would be affected by a store to MEMREF. */ | |
760 | ||
761 | static int | |
762 | memref_used_between_p (memref, start, end) | |
763 | rtx memref; | |
764 | rtx start; | |
765 | rtx end; | |
766 | { | |
767 | rtx insn; | |
768 | ||
769 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
770 | insn = NEXT_INSN (insn)) | |
2c3c49de | 771 | if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn))) |
2bbd3819 RS |
772 | return 1; |
773 | ||
774 | return 0; | |
775 | } | |
776 | \f | |
2b49ee39 R |
777 | /* Return nonzero if the rtx X is invariant over the current function. */ |
778 | int | |
779 | function_invariant_p (x) | |
780 | rtx x; | |
781 | { | |
782 | if (CONSTANT_P (x)) | |
783 | return 1; | |
784 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
785 | return 1; | |
786 | if (GET_CODE (x) == PLUS | |
787 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
788 | && CONSTANT_P (XEXP (x, 1))) | |
789 | return 1; | |
790 | return 0; | |
791 | } | |
792 | ||
2bbd3819 RS |
793 | /* Find registers that are equivalent to a single value throughout the |
794 | compilation (either because they can be referenced in memory or are set once | |
795 | from a single constant). Lower their priority for a register. | |
796 | ||
797 | If such a register is only referenced once, try substituting its value | |
798 | into the using insn. If it succeeds, we can eliminate the register | |
799 | completely. */ | |
800 | ||
801 | static void | |
802 | update_equiv_regs () | |
803 | { | |
2bbd3819 | 804 | rtx insn; |
bf6d9fd7 JW |
805 | int block; |
806 | int loop_depth; | |
25e4379f MM |
807 | regset_head cleared_regs; |
808 | int clear_regnos = 0; | |
2bbd3819 | 809 | |
bf6d9fd7 | 810 | reg_equiv = (struct equivalence *) xcalloc (max_regno, sizeof *reg_equiv); |
25e4379f | 811 | INIT_REG_SET (&cleared_regs); |
2bbd3819 RS |
812 | |
813 | init_alias_analysis (); | |
814 | ||
2bbd3819 RS |
815 | /* Scan the insns and find which registers have equivalences. Do this |
816 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
817 | a register can be set below its use. */ | |
bf6d9fd7 | 818 | loop_depth = 0; |
2bbd3819 RS |
819 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
820 | { | |
821 | rtx note; | |
135eb61c | 822 | rtx set; |
49ddab16 | 823 | rtx dest, src; |
2bbd3819 RS |
824 | int regno; |
825 | ||
826 | if (GET_CODE (insn) == NOTE) | |
827 | { | |
828 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
bf6d9fd7 | 829 | ++loop_depth; |
2bbd3819 | 830 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) |
bf6d9fd7 JW |
831 | { |
832 | if (! loop_depth) | |
833 | abort (); | |
834 | --loop_depth; | |
835 | } | |
2bbd3819 RS |
836 | } |
837 | ||
2c3c49de | 838 | if (! INSN_P (insn)) |
2bbd3819 RS |
839 | continue; |
840 | ||
135eb61c R |
841 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
842 | if (REG_NOTE_KIND (note) == REG_INC) | |
84832317 | 843 | no_equiv (XEXP (note, 0), note, NULL); |
135eb61c R |
844 | |
845 | set = single_set (insn); | |
846 | ||
847 | /* If this insn contains more (or less) than a single SET, | |
848 | only mark all destinations as having no known equivalence. */ | |
849 | if (set == 0) | |
850 | { | |
84832317 | 851 | note_stores (PATTERN (insn), no_equiv, NULL); |
135eb61c R |
852 | continue; |
853 | } | |
854 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
855 | { | |
856 | int i; | |
857 | ||
858 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
859 | { | |
860 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
861 | if (part != set) | |
84832317 | 862 | note_stores (part, no_equiv, NULL); |
135eb61c R |
863 | } |
864 | } | |
865 | ||
2bbd3819 | 866 | dest = SET_DEST (set); |
49ddab16 | 867 | src = SET_SRC (set); |
2bbd3819 RS |
868 | |
869 | /* If this sets a MEM to the contents of a REG that is only used | |
870 | in a single basic block, see if the register is always equivalent | |
871 | to that memory location and if moving the store from INSN to the | |
872 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
a1729519 JW |
873 | initializing insn. |
874 | ||
875 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
876 | REG_EQUIV is likely more useful than the one we are adding. | |
877 | ||
bf6d9fd7 JW |
878 | If one of the regs in the address has reg_equiv[REGNO].replace set, |
879 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
a1729519 | 880 | optimization may move the set of this register immediately before |
bf6d9fd7 | 881 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence |
a1729519 JW |
882 | the mention in the REG_EQUIV note would be to an uninitialized |
883 | pseudo. */ | |
135eb61c R |
884 | /* ????? This test isn't good enough; we might see a MEM with a use of |
885 | a pseudo register before we see its setting insn that will cause | |
bf6d9fd7 | 886 | reg_equiv[].replace for that pseudo to be set. |
135eb61c | 887 | Equivalences to MEMs should be made in another pass, after the |
bf6d9fd7 | 888 | reg_equiv[].replace information has been gathered. */ |
135eb61c R |
889 | |
890 | if (GET_CODE (dest) == MEM && GET_CODE (src) == REG | |
891 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
b1f21e0a | 892 | && REG_BASIC_BLOCK (regno) >= 0 |
135eb61c | 893 | && REG_N_SETS (regno) == 1 |
bf6d9fd7 JW |
894 | && reg_equiv[regno].init_insns != 0 |
895 | && reg_equiv[regno].init_insns != const0_rtx | |
896 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
b768aa38 | 897 | REG_EQUIV, NULL_RTX) |
bf6d9fd7 | 898 | && ! contains_replace_regs (XEXP (dest, 0))) |
135eb61c | 899 | { |
bf6d9fd7 | 900 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); |
135eb61c R |
901 | if (validate_equiv_mem (init_insn, src, dest) |
902 | && ! memref_used_between_p (dest, init_insn, insn)) | |
903 | REG_NOTES (init_insn) | |
904 | = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn)); | |
905 | } | |
2bbd3819 | 906 | |
1230327b | 907 | /* We only handle the case of a pseudo register being set |
135eb61c R |
908 | once, or always to the same value. */ |
909 | /* ??? The mn10200 port breaks if we add equivalences for | |
910 | values that need an ADDRESS_REGS register and set them equivalent | |
911 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
912 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
913 | calculate_needs, but we traditionally work around this problem | |
914 | here by rejecting equivalences when the destination is in a register | |
915 | that's likely spilled. This is fragile, of course, since the | |
8585f8f1 | 916 | preferred class of a pseudo depends on all instructions that set |
135eb61c R |
917 | or use it. */ |
918 | ||
2bbd3819 RS |
919 | if (GET_CODE (dest) != REG |
920 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
bf6d9fd7 | 921 | || reg_equiv[regno].init_insns == const0_rtx |
135eb61c R |
922 | || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) |
923 | && GET_CODE (src) == MEM)) | |
924 | { | |
925 | /* This might be seting a SUBREG of a pseudo, a pseudo that is | |
926 | also set somewhere else to a constant. */ | |
84832317 | 927 | note_stores (set, no_equiv, NULL); |
135eb61c R |
928 | continue; |
929 | } | |
2bbd3819 | 930 | |
b1ec3c92 | 931 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
2bbd3819 | 932 | |
2f93c5c3 BS |
933 | /* cse sometimes generates function invariants, but doesn't put a |
934 | REG_EQUAL note on the insn. Since this note would be redundant, | |
935 | there's no point creating it earlier than here. */ | |
bf6d9fd7 | 936 | if (! note && ! rtx_varies_p (src)) |
2f93c5c3 BS |
937 | REG_NOTES (insn) |
938 | = note = gen_rtx_EXPR_LIST (REG_EQUAL, src, REG_NOTES (insn)); | |
939 | ||
bf6d9fd7 JW |
940 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST |
941 | since it represents a function call */ | |
942 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
943 | note = NULL_RTX; | |
944 | ||
135eb61c R |
945 | if (REG_N_SETS (regno) != 1 |
946 | && (! note | |
bf6d9fd7 JW |
947 | || rtx_varies_p (XEXP (note, 0)) |
948 | || (reg_equiv[regno].replacement | |
135eb61c | 949 | && ! rtx_equal_p (XEXP (note, 0), |
bf6d9fd7 | 950 | reg_equiv[regno].replacement)))) |
135eb61c | 951 | { |
84832317 | 952 | no_equiv (dest, set, NULL); |
135eb61c R |
953 | continue; |
954 | } | |
2bbd3819 | 955 | /* Record this insn as initializing this register. */ |
bf6d9fd7 JW |
956 | reg_equiv[regno].init_insns |
957 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
2bbd3819 RS |
958 | |
959 | /* If this register is known to be equal to a constant, record that | |
960 | it is always equivalent to the constant. */ | |
bf6d9fd7 | 961 | if (note && ! rtx_varies_p (XEXP (note, 0))) |
2bbd3819 RS |
962 | PUT_MODE (note, (enum machine_mode) REG_EQUIV); |
963 | ||
964 | /* If this insn introduces a "constant" register, decrease the priority | |
965 | of that register. Record this insn if the register is only used once | |
966 | more and the equivalence value is the same as our source. | |
967 | ||
968 | The latter condition is checked for two reasons: First, it is an | |
969 | indication that it may be more efficient to actually emit the insn | |
970 | as written (if no registers are available, reload will substitute | |
971 | the equivalence). Secondly, it avoids problems with any registers | |
972 | dying in this insn whose death notes would be missed. | |
973 | ||
974 | If we don't have a REG_EQUIV note, see if this insn is loading | |
975 | a register used only in one basic block from a MEM. If so, and the | |
976 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
977 | note. */ | |
64e3a413 | 978 | |
b1ec3c92 | 979 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
2bbd3819 | 980 | |
b1f21e0a | 981 | if (note == 0 && REG_BASIC_BLOCK (regno) >= 0 |
2bbd3819 RS |
982 | && GET_CODE (SET_SRC (set)) == MEM |
983 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
38a448ca RH |
984 | REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set), |
985 | REG_NOTES (insn)); | |
2bbd3819 | 986 | |
68342d36 | 987 | if (note) |
2bbd3819 RS |
988 | { |
989 | int regno = REGNO (dest); | |
990 | ||
3f1b9b1b JL |
991 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. |
992 | We might end up substituting the LABEL_REF for uses of the | |
993 | pseudo here or later. That kind of transformation may turn an | |
994 | indirect jump into a direct jump, in which case we must rerun the | |
995 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
996 | if (GET_CODE (XEXP (note, 0)) == LABEL_REF | |
997 | || (GET_CODE (XEXP (note, 0)) == CONST | |
998 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
999 | && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) | |
1000 | == LABEL_REF))) | |
1001 | recorded_label_ref = 1; | |
64e3a413 | 1002 | |
bf6d9fd7 JW |
1003 | reg_equiv[regno].replacement = XEXP (note, 0); |
1004 | reg_equiv[regno].src = src; | |
1005 | reg_equiv[regno].loop_depth = loop_depth; | |
68342d36 RK |
1006 | |
1007 | /* Don't mess with things live during setjmp. */ | |
b1f21e0a | 1008 | if (REG_LIVE_LENGTH (regno) >= 0) |
68342d36 RK |
1009 | { |
1010 | /* Note that the statement below does not affect the priority | |
1011 | in local-alloc! */ | |
b1f21e0a | 1012 | REG_LIVE_LENGTH (regno) *= 2; |
2bbd3819 | 1013 | |
2bbd3819 | 1014 | |
68342d36 RK |
1015 | /* If the register is referenced exactly twice, meaning it is |
1016 | set once and used once, indicate that the reference may be | |
bf6d9fd7 JW |
1017 | replaced by the equivalence we computed above. Do this |
1018 | even if the register is only used in one block so that | |
1019 | dependencies can be handled where the last register is | |
1020 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
1021 | and to reduce the number of registers alive across calls. | |
2bbd3819 | 1022 | |
68342d36 RK |
1023 | It would be nice to use "loop_depth * 2" in the compare |
1024 | below. Unfortunately, LOOP_DEPTH need not be constant within | |
1025 | a basic block so this would be too complicated. | |
2bbd3819 | 1026 | |
68342d36 RK |
1027 | This case normally occurs when a parameter is read from |
1028 | memory and then used exactly once, not in a loop. */ | |
1029 | ||
b1f21e0a | 1030 | if (REG_N_REFS (regno) == 2 |
bf6d9fd7 JW |
1031 | && (rtx_equal_p (XEXP (note, 0), src) |
1032 | || ! equiv_init_varies_p (src)) | |
1033 | && GET_CODE (insn) == INSN | |
1034 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
1035 | reg_equiv[regno].replace = 1; | |
68342d36 | 1036 | } |
2bbd3819 RS |
1037 | } |
1038 | } | |
1039 | ||
2e1253f3 ILT |
1040 | /* Now scan all regs killed in an insn to see if any of them are |
1041 | registers only used that once. If so, see if we can replace the | |
1042 | reference with the equivalent from. If we can, delete the | |
1043 | initializing reference and this register will go away. If we | |
bf6d9fd7 JW |
1044 | can't replace the reference, and the initialzing reference is |
1045 | within the same loop (or in an inner loop), then move the register | |
1046 | initialization just before the use, so that they are in the same | |
1047 | basic block. | |
1048 | ||
1049 | Skip this optimization if loop_depth isn't initially zero since | |
1050 | that indicates a mismatch between loop begin and loop end notes | |
1051 | (i.e. gcc.dg/noncompile/920721-2.c). */ | |
1052 | block = n_basic_blocks - 1; | |
1053 | for (insn = (loop_depth == 0) ? get_last_insn () : NULL_RTX; | |
1054 | insn; insn = PREV_INSN (insn)) | |
2bbd3819 RS |
1055 | { |
1056 | rtx link; | |
1057 | ||
2c3c49de | 1058 | if (! INSN_P (insn)) |
2e1253f3 ILT |
1059 | { |
1060 | if (GET_CODE (insn) == NOTE) | |
1061 | { | |
bf6d9fd7 JW |
1062 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
1063 | block = NOTE_BASIC_BLOCK (insn)->index - 1; | |
1064 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
2e1253f3 | 1065 | { |
bf6d9fd7 | 1066 | if (! loop_depth) |
2e1253f3 | 1067 | abort (); |
bf6d9fd7 | 1068 | --loop_depth; |
2e1253f3 | 1069 | } |
bf6d9fd7 JW |
1070 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) |
1071 | ++loop_depth; | |
2e1253f3 ILT |
1072 | } |
1073 | ||
1074 | continue; | |
1075 | } | |
1076 | ||
2bbd3819 | 1077 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
2e1253f3 ILT |
1078 | { |
1079 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1080 | /* Make sure this insn still refers to the register. */ | |
1081 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
1082 | { | |
1083 | int regno = REGNO (XEXP (link, 0)); | |
1084 | rtx equiv_insn; | |
2bbd3819 | 1085 | |
bf6d9fd7 JW |
1086 | if (! reg_equiv[regno].replace |
1087 | || reg_equiv[regno].loop_depth < loop_depth) | |
2e1253f3 ILT |
1088 | continue; |
1089 | ||
bf6d9fd7 | 1090 | /* reg_equiv[REGNO].replace gets set only when |
135eb61c R |
1091 | REG_N_REFS[REGNO] is 2, i.e. the register is set |
1092 | once and used once. (If it were only set, but not used, | |
64e3a413 | 1093 | flow would have deleted the setting insns.) Hence |
bf6d9fd7 | 1094 | there can only be one insn in reg_equiv[REGNO].init_insns. */ |
96af667a GK |
1095 | if (reg_equiv[regno].init_insns == NULL_RTX |
1096 | || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX) | |
1097 | abort (); | |
bf6d9fd7 | 1098 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); |
2e1253f3 | 1099 | |
bf6d9fd7 JW |
1100 | if (asm_noperands (PATTERN (equiv_insn)) < 0 |
1101 | && validate_replace_rtx (regno_reg_rtx[regno], | |
1102 | reg_equiv[regno].src, insn)) | |
2e1253f3 | 1103 | { |
bf6d9fd7 JW |
1104 | rtx equiv_link; |
1105 | rtx last_link; | |
1106 | rtx note; | |
1107 | ||
1108 | /* Find the last note. */ | |
1109 | for (last_link = link; XEXP (last_link, 1); | |
1110 | last_link = XEXP (last_link, 1)) | |
1111 | ; | |
1112 | ||
1113 | /* Append the REG_DEAD notes from equiv_insn. */ | |
1114 | equiv_link = REG_NOTES (equiv_insn); | |
1115 | while (equiv_link) | |
1116 | { | |
1117 | note = equiv_link; | |
1118 | equiv_link = XEXP (equiv_link, 1); | |
1119 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
1120 | { | |
1121 | remove_note (equiv_insn, note); | |
1122 | XEXP (last_link, 1) = note; | |
1123 | XEXP (note, 1) = NULL_RTX; | |
1124 | last_link = note; | |
1125 | } | |
1126 | } | |
1127 | ||
2e1253f3 | 1128 | remove_death (regno, insn); |
b1f21e0a | 1129 | REG_N_REFS (regno) = 0; |
2e1253f3 ILT |
1130 | PUT_CODE (equiv_insn, NOTE); |
1131 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1132 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
96af667a GK |
1133 | |
1134 | reg_equiv[regno].init_insns = | |
1135 | XEXP (reg_equiv[regno].init_insns, 1); | |
2e1253f3 | 1136 | } |
bf6d9fd7 JW |
1137 | /* Move the initialization of the register to just before |
1138 | INSN. Update the flow information. */ | |
1139 | else if (PREV_INSN (insn) != equiv_insn) | |
2e1253f3 | 1140 | { |
96af667a | 1141 | rtx new_insn; |
2e1253f3 | 1142 | |
96af667a GK |
1143 | new_insn = emit_insn_before (copy_rtx (PATTERN (equiv_insn)), |
1144 | insn); | |
9956bfc0 | 1145 | REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn); |
ef178af3 | 1146 | REG_NOTES (equiv_insn) = 0; |
2e1253f3 ILT |
1147 | |
1148 | PUT_CODE (equiv_insn, NOTE); | |
1149 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1150 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
2e1253f3 | 1151 | |
96af667a GK |
1152 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; |
1153 | ||
bf6d9fd7 | 1154 | REG_BASIC_BLOCK (regno) = block >= 0 ? block : 0; |
b1f21e0a MM |
1155 | REG_N_CALLS_CROSSED (regno) = 0; |
1156 | REG_LIVE_LENGTH (regno) = 2; | |
2e1253f3 | 1157 | |
3b413743 RH |
1158 | if (block >= 0 && insn == BLOCK_HEAD (block)) |
1159 | BLOCK_HEAD (block) = PREV_INSN (insn); | |
2e1253f3 | 1160 | |
25e4379f MM |
1161 | /* Remember to clear REGNO from all basic block's live |
1162 | info. */ | |
1163 | SET_REGNO_REG_SET (&cleared_regs, regno); | |
1164 | clear_regnos++; | |
2e1253f3 ILT |
1165 | } |
1166 | } | |
1167 | } | |
2bbd3819 | 1168 | } |
e05e2395 | 1169 | |
25e4379f MM |
1170 | /* Clear all dead REGNOs from all basic block's live info. */ |
1171 | if (clear_regnos) | |
1172 | { | |
1173 | int j, l; | |
1174 | if (clear_regnos > 8) | |
1175 | { | |
1176 | for (l = 0; l < n_basic_blocks; l++) | |
1177 | { | |
1178 | AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_start, | |
1179 | &cleared_regs); | |
1180 | AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_end, | |
1181 | &cleared_regs); | |
1182 | } | |
1183 | } | |
1184 | else | |
1185 | EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j, | |
1186 | { | |
1187 | for (l = 0; l < n_basic_blocks; l++) | |
1188 | { | |
1189 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start, j); | |
1190 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_end, j); | |
1191 | } | |
1192 | }); | |
1193 | } | |
1194 | ||
e05e2395 MM |
1195 | /* Clean up. */ |
1196 | end_alias_analysis (); | |
25e4379f | 1197 | CLEAR_REG_SET (&cleared_regs); |
bf6d9fd7 | 1198 | free (reg_equiv); |
2bbd3819 | 1199 | } |
135eb61c R |
1200 | |
1201 | /* Mark REG as having no known equivalence. | |
1202 | Some instructions might have been proceessed before and furnished | |
1203 | with REG_EQUIV notes for this register; these notes will have to be | |
1204 | removed. | |
1205 | STORE is the piece of RTL that does the non-constant / conflicting | |
1206 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
1207 | but needs to be there because this function is called from note_stores. */ | |
1208 | static void | |
84832317 | 1209 | no_equiv (reg, store, data) |
54ea1de9 | 1210 | rtx reg, store ATTRIBUTE_UNUSED; |
84832317 | 1211 | void *data ATTRIBUTE_UNUSED; |
135eb61c R |
1212 | { |
1213 | int regno; | |
1214 | rtx list; | |
1215 | ||
1216 | if (GET_CODE (reg) != REG) | |
1217 | return; | |
1218 | regno = REGNO (reg); | |
bf6d9fd7 | 1219 | list = reg_equiv[regno].init_insns; |
135eb61c R |
1220 | if (list == const0_rtx) |
1221 | return; | |
1222 | for (; list; list = XEXP (list, 1)) | |
1223 | { | |
1224 | rtx insn = XEXP (list, 0); | |
1225 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
1226 | } | |
bf6d9fd7 JW |
1227 | reg_equiv[regno].init_insns = const0_rtx; |
1228 | reg_equiv[regno].replacement = NULL_RTX; | |
135eb61c | 1229 | } |
2bbd3819 RS |
1230 | \f |
1231 | /* Allocate hard regs to the pseudo regs used only within block number B. | |
1232 | Only the pseudos that die but once can be handled. */ | |
1233 | ||
1234 | static void | |
1235 | block_alloc (b) | |
1236 | int b; | |
1237 | { | |
1238 | register int i, q; | |
1239 | register rtx insn; | |
1240 | rtx note; | |
1241 | int insn_number = 0; | |
1242 | int insn_count = 0; | |
1243 | int max_uid = get_max_uid (); | |
aabf56ce | 1244 | int *qty_order; |
2bbd3819 RS |
1245 | int no_conflict_combined_regno = -1; |
1246 | ||
1247 | /* Count the instructions in the basic block. */ | |
1248 | ||
3b413743 | 1249 | insn = BLOCK_END (b); |
2bbd3819 RS |
1250 | while (1) |
1251 | { | |
1252 | if (GET_CODE (insn) != NOTE) | |
1253 | if (++insn_count > max_uid) | |
1254 | abort (); | |
3b413743 | 1255 | if (insn == BLOCK_HEAD (b)) |
2bbd3819 RS |
1256 | break; |
1257 | insn = PREV_INSN (insn); | |
1258 | } | |
1259 | ||
1260 | /* +2 to leave room for a post_mark_life at the last insn and for | |
1261 | the birth of a CLOBBER in the first insn. */ | |
ff154f78 MM |
1262 | regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2), |
1263 | sizeof (HARD_REG_SET)); | |
2bbd3819 RS |
1264 | |
1265 | /* Initialize table of hardware registers currently live. */ | |
1266 | ||
e881bb1b | 1267 | REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start); |
2bbd3819 RS |
1268 | |
1269 | /* This loop scans the instructions of the basic block | |
1270 | and assigns quantities to registers. | |
1271 | It computes which registers to tie. */ | |
1272 | ||
3b413743 | 1273 | insn = BLOCK_HEAD (b); |
2bbd3819 RS |
1274 | while (1) |
1275 | { | |
2bbd3819 RS |
1276 | if (GET_CODE (insn) != NOTE) |
1277 | insn_number++; | |
1278 | ||
2c3c49de | 1279 | if (INSN_P (insn)) |
2bbd3819 RS |
1280 | { |
1281 | register rtx link, set; | |
1282 | register int win = 0; | |
a544cfd2 | 1283 | register rtx r0, r1 = NULL_RTX; |
2bbd3819 RS |
1284 | int combined_regno = -1; |
1285 | int i; | |
2bbd3819 RS |
1286 | |
1287 | this_insn_number = insn_number; | |
1288 | this_insn = insn; | |
1289 | ||
0a578fee | 1290 | extract_insn (insn); |
2bbd3819 RS |
1291 | which_alternative = -1; |
1292 | ||
1293 | /* Is this insn suitable for tying two registers? | |
1294 | If so, try doing that. | |
1295 | Suitable insns are those with at least two operands and where | |
1296 | operand 0 is an output that is a register that is not | |
1297 | earlyclobber. | |
7aba0f0b RK |
1298 | |
1299 | We can tie operand 0 with some operand that dies in this insn. | |
1300 | First look for operands that are required to be in the same | |
1301 | register as operand 0. If we find such, only try tying that | |
1302 | operand or one that can be put into that operand if the | |
1303 | operation is commutative. If we don't find an operand | |
1304 | that is required to be in the same register as operand 0, | |
1305 | we can tie with any operand. | |
1306 | ||
2bbd3819 RS |
1307 | Subregs in place of regs are also ok. |
1308 | ||
1309 | If tying is done, WIN is set nonzero. */ | |
1310 | ||
d29c259b RH |
1311 | if (optimize |
1312 | && recog_data.n_operands > 1 | |
1ccbefce | 1313 | && recog_data.constraints[0][0] == '=' |
19af6455 | 1314 | && recog_data.constraints[0][1] != '&') |
2bbd3819 | 1315 | { |
3061cc54 | 1316 | /* If non-negative, is an operand that must match operand 0. */ |
7aba0f0b | 1317 | int must_match_0 = -1; |
3061cc54 RK |
1318 | /* Counts number of alternatives that require a match with |
1319 | operand 0. */ | |
1320 | int n_matching_alts = 0; | |
7aba0f0b | 1321 | |
1ccbefce | 1322 | for (i = 1; i < recog_data.n_operands; i++) |
3061cc54 | 1323 | { |
1ccbefce | 1324 | const char *p = recog_data.constraints[i]; |
3061cc54 RK |
1325 | int this_match = (requires_inout (p)); |
1326 | ||
1327 | n_matching_alts += this_match; | |
1ccbefce | 1328 | if (this_match == recog_data.n_alternatives) |
3061cc54 RK |
1329 | must_match_0 = i; |
1330 | } | |
2bbd3819 | 1331 | |
1ccbefce RH |
1332 | r0 = recog_data.operand[0]; |
1333 | for (i = 1; i < recog_data.n_operands; i++) | |
2bbd3819 | 1334 | { |
7aba0f0b RK |
1335 | /* Skip this operand if we found an operand that |
1336 | must match operand 0 and this operand isn't it | |
1337 | and can't be made to be it by commutativity. */ | |
1338 | ||
1339 | if (must_match_0 >= 0 && i != must_match_0 | |
1340 | && ! (i == must_match_0 + 1 | |
1ccbefce | 1341 | && recog_data.constraints[i-1][0] == '%') |
7aba0f0b | 1342 | && ! (i == must_match_0 - 1 |
1ccbefce | 1343 | && recog_data.constraints[i][0] == '%')) |
7aba0f0b | 1344 | continue; |
3061cc54 RK |
1345 | |
1346 | /* Likewise if each alternative has some operand that | |
64e3a413 | 1347 | must match operand zero. In that case, skip any |
3061cc54 RK |
1348 | operand that doesn't list operand 0 since we know that |
1349 | the operand always conflicts with operand 0. We | |
1350 | ignore commutatity in this case to keep things simple. */ | |
1ccbefce RH |
1351 | if (n_matching_alts == recog_data.n_alternatives |
1352 | && 0 == requires_inout (recog_data.constraints[i])) | |
3061cc54 | 1353 | continue; |
2bbd3819 | 1354 | |
1ccbefce | 1355 | r1 = recog_data.operand[i]; |
2bbd3819 | 1356 | |
7aba0f0b RK |
1357 | /* If the operand is an address, find a register in it. |
1358 | There may be more than one register, but we only try one | |
1359 | of them. */ | |
19af6455 | 1360 | if (recog_data.constraints[i][0] == 'p') |
7aba0f0b RK |
1361 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) |
1362 | r1 = XEXP (r1, 0); | |
1363 | ||
1364 | if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) | |
1365 | { | |
1366 | /* We have two priorities for hard register preferences. | |
1367 | If we have a move insn or an insn whose first input | |
1368 | can only be in the same register as the output, give | |
1369 | priority to an equivalence found from that insn. */ | |
1370 | int may_save_copy | |
1ccbefce | 1371 | = (r1 == recog_data.operand[i] && must_match_0 >= 0); |
64e3a413 | 1372 | |
7aba0f0b RK |
1373 | if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) |
1374 | win = combine_regs (r1, r0, may_save_copy, | |
1375 | insn_number, insn, 0); | |
1376 | } | |
662347c5 JL |
1377 | if (win) |
1378 | break; | |
2bbd3819 RS |
1379 | } |
1380 | } | |
1381 | ||
1382 | /* Recognize an insn sequence with an ultimate result | |
1383 | which can safely overlap one of the inputs. | |
1384 | The sequence begins with a CLOBBER of its result, | |
1385 | and ends with an insn that copies the result to itself | |
1386 | and has a REG_EQUAL note for an equivalent formula. | |
1387 | That note indicates what the inputs are. | |
1388 | The result and the input can overlap if each insn in | |
1389 | the sequence either doesn't mention the input | |
1390 | or has a REG_NO_CONFLICT note to inhibit the conflict. | |
1391 | ||
1392 | We do the combining test at the CLOBBER so that the | |
1393 | destination register won't have had a quantity number | |
1394 | assigned, since that would prevent combining. */ | |
1395 | ||
d29c259b RH |
1396 | if (optimize |
1397 | && GET_CODE (PATTERN (insn)) == CLOBBER | |
2bbd3819 RS |
1398 | && (r0 = XEXP (PATTERN (insn), 0), |
1399 | GET_CODE (r0) == REG) | |
b1ec3c92 | 1400 | && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 |
a6665f8c | 1401 | && XEXP (link, 0) != 0 |
2bbd3819 RS |
1402 | && GET_CODE (XEXP (link, 0)) == INSN |
1403 | && (set = single_set (XEXP (link, 0))) != 0 | |
1404 | && SET_DEST (set) == r0 && SET_SRC (set) == r0 | |
b1ec3c92 CH |
1405 | && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, |
1406 | NULL_RTX)) != 0) | |
2bbd3819 RS |
1407 | { |
1408 | if (r1 = XEXP (note, 0), GET_CODE (r1) == REG | |
1409 | /* Check that we have such a sequence. */ | |
1410 | && no_conflict_p (insn, r0, r1)) | |
1411 | win = combine_regs (r1, r0, 1, insn_number, insn, 1); | |
1412 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' | |
1413 | && (r1 = XEXP (XEXP (note, 0), 0), | |
1414 | GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) | |
1415 | && no_conflict_p (insn, r0, r1)) | |
1416 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1417 | ||
1418 | /* Here we care if the operation to be computed is | |
1419 | commutative. */ | |
1420 | else if ((GET_CODE (XEXP (note, 0)) == EQ | |
1421 | || GET_CODE (XEXP (note, 0)) == NE | |
1422 | || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') | |
1423 | && (r1 = XEXP (XEXP (note, 0), 1), | |
1424 | (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) | |
1425 | && no_conflict_p (insn, r0, r1)) | |
1426 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1427 | ||
1428 | /* If we did combine something, show the register number | |
1429 | in question so that we know to ignore its death. */ | |
1430 | if (win) | |
1431 | no_conflict_combined_regno = REGNO (r1); | |
1432 | } | |
1433 | ||
1434 | /* If registers were just tied, set COMBINED_REGNO | |
1435 | to the number of the register used in this insn | |
1436 | that was tied to the register set in this insn. | |
1437 | This register's qty should not be "killed". */ | |
1438 | ||
1439 | if (win) | |
1440 | { | |
1441 | while (GET_CODE (r1) == SUBREG) | |
1442 | r1 = SUBREG_REG (r1); | |
1443 | combined_regno = REGNO (r1); | |
1444 | } | |
1445 | ||
1446 | /* Mark the death of everything that dies in this instruction, | |
1447 | except for anything that was just combined. */ | |
1448 | ||
1449 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1450 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1451 | && GET_CODE (XEXP (link, 0)) == REG | |
770ae6cc RK |
1452 | && combined_regno != (int) REGNO (XEXP (link, 0)) |
1453 | && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0)) | |
1454 | || ! find_reg_note (insn, REG_NO_CONFLICT, | |
1455 | XEXP (link, 0)))) | |
2bbd3819 RS |
1456 | wipe_dead_reg (XEXP (link, 0), 0); |
1457 | ||
1458 | /* Allocate qty numbers for all registers local to this block | |
1459 | that are born (set) in this instruction. | |
1460 | A pseudo that already has a qty is not changed. */ | |
1461 | ||
84832317 | 1462 | note_stores (PATTERN (insn), reg_is_set, NULL); |
2bbd3819 RS |
1463 | |
1464 | /* If anything is set in this insn and then unused, mark it as dying | |
1465 | after this insn, so it will conflict with our outputs. This | |
1466 | can't match with something that combined, and it doesn't matter | |
1467 | if it did. Do this after the calls to reg_is_set since these | |
1468 | die after, not during, the current insn. */ | |
1469 | ||
1470 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1471 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
1472 | && GET_CODE (XEXP (link, 0)) == REG) | |
1473 | wipe_dead_reg (XEXP (link, 0), 1); | |
1474 | ||
64e3a413 | 1475 | /* If this is an insn that has a REG_RETVAL note pointing at a |
2bbd3819 RS |
1476 | CLOBBER insn, we have reached the end of a REG_NO_CONFLICT |
1477 | block, so clear any register number that combined within it. */ | |
b1ec3c92 | 1478 | if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 |
2bbd3819 RS |
1479 | && GET_CODE (XEXP (note, 0)) == INSN |
1480 | && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) | |
1481 | no_conflict_combined_regno = -1; | |
1482 | } | |
1483 | ||
1484 | /* Set the registers live after INSN_NUMBER. Note that we never | |
1485 | record the registers live before the block's first insn, since no | |
1486 | pseudos we care about are live before that insn. */ | |
1487 | ||
1488 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); | |
1489 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); | |
1490 | ||
3b413743 | 1491 | if (insn == BLOCK_END (b)) |
2bbd3819 RS |
1492 | break; |
1493 | ||
1494 | insn = NEXT_INSN (insn); | |
1495 | } | |
1496 | ||
1497 | /* Now every register that is local to this basic block | |
1498 | should have been given a quantity, or else -1 meaning ignore it. | |
64e3a413 | 1499 | Every quantity should have a known birth and death. |
2bbd3819 | 1500 | |
51b86d8b RK |
1501 | Order the qtys so we assign them registers in order of the |
1502 | number of suggested registers they need so we allocate those with | |
1503 | the most restrictive needs first. */ | |
2bbd3819 | 1504 | |
ff154f78 | 1505 | qty_order = (int *) xmalloc (next_qty * sizeof (int)); |
2bbd3819 RS |
1506 | for (i = 0; i < next_qty; i++) |
1507 | qty_order[i] = i; | |
1508 | ||
1509 | #define EXCHANGE(I1, I2) \ | |
1510 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1511 | ||
1512 | switch (next_qty) | |
1513 | { | |
1514 | case 3: | |
1515 | /* Make qty_order[2] be the one to allocate last. */ | |
51b86d8b | 1516 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 | 1517 | EXCHANGE (0, 1); |
51b86d8b | 1518 | if (qty_sugg_compare (1, 2) > 0) |
2bbd3819 RS |
1519 | EXCHANGE (2, 1); |
1520 | ||
0f41302f | 1521 | /* ... Fall through ... */ |
2bbd3819 RS |
1522 | case 2: |
1523 | /* Put the best one to allocate in qty_order[0]. */ | |
51b86d8b | 1524 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 RS |
1525 | EXCHANGE (0, 1); |
1526 | ||
0f41302f | 1527 | /* ... Fall through ... */ |
2bbd3819 RS |
1528 | |
1529 | case 1: | |
1530 | case 0: | |
1531 | /* Nothing to do here. */ | |
1532 | break; | |
1533 | ||
1534 | default: | |
51b86d8b | 1535 | qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); |
2bbd3819 RS |
1536 | } |
1537 | ||
1538 | /* Try to put each quantity in a suggested physical register, if it has one. | |
1539 | This may cause registers to be allocated that otherwise wouldn't be, but | |
1540 | this seems acceptable in local allocation (unlike global allocation). */ | |
1541 | for (i = 0; i < next_qty; i++) | |
1542 | { | |
1543 | q = qty_order[i]; | |
51b86d8b | 1544 | if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) |
a1ed7bdb JH |
1545 | qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q, |
1546 | 0, 1, qty[q].birth, qty[q].death); | |
2bbd3819 | 1547 | else |
a1ed7bdb | 1548 | qty[q].phys_reg = -1; |
2bbd3819 RS |
1549 | } |
1550 | ||
64e3a413 KH |
1551 | /* Order the qtys so we assign them registers in order of |
1552 | decreasing length of life. Normally call qsort, but if we | |
51b86d8b RK |
1553 | have only a very small number of quantities, sort them ourselves. */ |
1554 | ||
1555 | for (i = 0; i < next_qty; i++) | |
1556 | qty_order[i] = i; | |
1557 | ||
1558 | #define EXCHANGE(I1, I2) \ | |
1559 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1560 | ||
1561 | switch (next_qty) | |
1562 | { | |
1563 | case 3: | |
1564 | /* Make qty_order[2] be the one to allocate last. */ | |
1565 | if (qty_compare (0, 1) > 0) | |
1566 | EXCHANGE (0, 1); | |
1567 | if (qty_compare (1, 2) > 0) | |
1568 | EXCHANGE (2, 1); | |
1569 | ||
0f41302f | 1570 | /* ... Fall through ... */ |
51b86d8b RK |
1571 | case 2: |
1572 | /* Put the best one to allocate in qty_order[0]. */ | |
1573 | if (qty_compare (0, 1) > 0) | |
1574 | EXCHANGE (0, 1); | |
1575 | ||
0f41302f | 1576 | /* ... Fall through ... */ |
51b86d8b RK |
1577 | |
1578 | case 1: | |
1579 | case 0: | |
1580 | /* Nothing to do here. */ | |
1581 | break; | |
1582 | ||
1583 | default: | |
1584 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); | |
1585 | } | |
1586 | ||
2bbd3819 RS |
1587 | /* Now for each qty that is not a hardware register, |
1588 | look for a hardware register to put it in. | |
1589 | First try the register class that is cheapest for this qty, | |
1590 | if there is more than one class. */ | |
1591 | ||
1592 | for (i = 0; i < next_qty; i++) | |
1593 | { | |
1594 | q = qty_order[i]; | |
a1ed7bdb | 1595 | if (qty[q].phys_reg < 0) |
2bbd3819 | 1596 | { |
624a8b3a JL |
1597 | #ifdef INSN_SCHEDULING |
1598 | /* These values represent the adjusted lifetime of a qty so | |
1599 | that it conflicts with qtys which appear near the start/end | |
1600 | of this qty's lifetime. | |
1601 | ||
1602 | The purpose behind extending the lifetime of this qty is to | |
1603 | discourage the register allocator from creating false | |
1604 | dependencies. | |
64e3a413 | 1605 | |
996e9683 JL |
1606 | The adjustment value is choosen to indicate that this qty |
1607 | conflicts with all the qtys in the instructions immediately | |
624a8b3a JL |
1608 | before and after the lifetime of this qty. |
1609 | ||
1610 | Experiments have shown that higher values tend to hurt | |
1611 | overall code performance. | |
1612 | ||
1613 | If allocation using the extended lifetime fails we will try | |
1614 | again with the qty's unadjusted lifetime. */ | |
a1ed7bdb | 1615 | int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2); |
996e9683 | 1616 | int fake_death = MIN (insn_number * 2 + 1, |
a1ed7bdb | 1617 | qty[q].death + 2 - qty[q].death % 2); |
624a8b3a JL |
1618 | #endif |
1619 | ||
2bbd3819 RS |
1620 | if (N_REG_CLASSES > 1) |
1621 | { | |
624a8b3a JL |
1622 | #ifdef INSN_SCHEDULING |
1623 | /* We try to avoid using hard registers allocated to qtys which | |
1624 | are born immediately after this qty or die immediately before | |
1625 | this qty. | |
1626 | ||
1627 | This optimization is only appropriate when we will run | |
1628 | a scheduling pass after reload and we are not optimizing | |
1629 | for code size. */ | |
c358412f JL |
1630 | if (flag_schedule_insns_after_reload |
1631 | && !optimize_size | |
1632 | && !SMALL_REGISTER_CLASSES) | |
624a8b3a | 1633 | { |
64e3a413 | 1634 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb | 1635 | qty[q].mode, q, 0, 0, |
624a8b3a | 1636 | fake_birth, fake_death); |
a1ed7bdb | 1637 | if (qty[q].phys_reg >= 0) |
624a8b3a JL |
1638 | continue; |
1639 | } | |
1640 | #endif | |
64e3a413 | 1641 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb JH |
1642 | qty[q].mode, q, 0, 0, |
1643 | qty[q].birth, qty[q].death); | |
1644 | if (qty[q].phys_reg >= 0) | |
2bbd3819 RS |
1645 | continue; |
1646 | } | |
1647 | ||
624a8b3a JL |
1648 | #ifdef INSN_SCHEDULING |
1649 | /* Similarly, avoid false dependencies. */ | |
c358412f JL |
1650 | if (flag_schedule_insns_after_reload |
1651 | && !optimize_size | |
1652 | && !SMALL_REGISTER_CLASSES | |
a1ed7bdb JH |
1653 | && qty[q].alternate_class != NO_REGS) |
1654 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1655 | qty[q].mode, q, 0, 0, | |
624a8b3a JL |
1656 | fake_birth, fake_death); |
1657 | #endif | |
a1ed7bdb JH |
1658 | if (qty[q].alternate_class != NO_REGS) |
1659 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1660 | qty[q].mode, q, 0, 0, | |
1661 | qty[q].birth, qty[q].death); | |
2bbd3819 RS |
1662 | } |
1663 | } | |
1664 | ||
1665 | /* Now propagate the register assignments | |
1666 | to the pseudo regs belonging to the qtys. */ | |
1667 | ||
1668 | for (q = 0; q < next_qty; q++) | |
a1ed7bdb | 1669 | if (qty[q].phys_reg >= 0) |
2bbd3819 | 1670 | { |
a1ed7bdb JH |
1671 | for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i]) |
1672 | reg_renumber[i] = qty[q].phys_reg + reg_offset[i]; | |
2bbd3819 | 1673 | } |
ff154f78 MM |
1674 | |
1675 | /* Clean up. */ | |
1676 | free (regs_live_at); | |
1677 | free (qty_order); | |
2bbd3819 RS |
1678 | } |
1679 | \f | |
1680 | /* Compare two quantities' priority for getting real registers. | |
1681 | We give shorter-lived quantities higher priority. | |
6dc42e49 RS |
1682 | Quantities with more references are also preferred, as are quantities that |
1683 | require multiple registers. This is the identical prioritization as | |
2bbd3819 RS |
1684 | done by global-alloc. |
1685 | ||
1686 | We used to give preference to registers with *longer* lives, but using | |
1687 | the same algorithm in both local- and global-alloc can speed up execution | |
1688 | of some programs by as much as a factor of three! */ | |
1689 | ||
2f23fcc9 RK |
1690 | /* Note that the quotient will never be bigger than |
1691 | the value of floor_log2 times the maximum number of | |
1692 | times a register can occur in one insn (surely less than 100). | |
1693 | Multiplying this by 10000 can't overflow. | |
1694 | QTY_CMP_PRI is also used by qty_sugg_compare. */ | |
1695 | ||
1696 | #define QTY_CMP_PRI(q) \ | |
a1ed7bdb JH |
1697 | ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \ |
1698 | / (qty[q].death - qty[q].birth)) * 10000)) | |
2f23fcc9 | 1699 | |
2bbd3819 RS |
1700 | static int |
1701 | qty_compare (q1, q2) | |
1702 | int q1, q2; | |
1703 | { | |
2f23fcc9 | 1704 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
2bbd3819 RS |
1705 | } |
1706 | ||
1707 | static int | |
2f23fcc9 | 1708 | qty_compare_1 (q1p, q2p) |
e1b6684c KG |
1709 | const PTR q1p; |
1710 | const PTR q2p; | |
2bbd3819 | 1711 | { |
64e3a413 | 1712 | register int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
2f23fcc9 RK |
1713 | register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
1714 | ||
1715 | if (tem != 0) | |
1716 | return tem; | |
1717 | ||
2bbd3819 RS |
1718 | /* If qtys are equally good, sort by qty number, |
1719 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1720 | return q1 - q2; |
2bbd3819 RS |
1721 | } |
1722 | \f | |
51b86d8b RK |
1723 | /* Compare two quantities' priority for getting real registers. This version |
1724 | is called for quantities that have suggested hard registers. First priority | |
1725 | goes to quantities that have copy preferences, then to those that have | |
1726 | normal preferences. Within those groups, quantities with the lower | |
9faa82d8 | 1727 | number of preferences have the highest priority. Of those, we use the same |
51b86d8b RK |
1728 | algorithm as above. */ |
1729 | ||
2f23fcc9 RK |
1730 | #define QTY_CMP_SUGG(q) \ |
1731 | (qty_phys_num_copy_sugg[q] \ | |
1732 | ? qty_phys_num_copy_sugg[q] \ | |
1733 | : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER) | |
1734 | ||
51b86d8b RK |
1735 | static int |
1736 | qty_sugg_compare (q1, q2) | |
1737 | int q1, q2; | |
1738 | { | |
2f23fcc9 RK |
1739 | register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
1740 | ||
1741 | if (tem != 0) | |
1742 | return tem; | |
64e3a413 | 1743 | |
2f23fcc9 | 1744 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
51b86d8b RK |
1745 | } |
1746 | ||
1747 | static int | |
2f23fcc9 | 1748 | qty_sugg_compare_1 (q1p, q2p) |
e1b6684c KG |
1749 | const PTR q1p; |
1750 | const PTR q2p; | |
51b86d8b | 1751 | { |
64e3a413 | 1752 | register int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
2f23fcc9 RK |
1753 | register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
1754 | ||
1755 | if (tem != 0) | |
1756 | return tem; | |
1757 | ||
1758 | tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
1759 | if (tem != 0) | |
1760 | return tem; | |
51b86d8b RK |
1761 | |
1762 | /* If qtys are equally good, sort by qty number, | |
1763 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1764 | return q1 - q2; |
51b86d8b | 1765 | } |
2f23fcc9 RK |
1766 | |
1767 | #undef QTY_CMP_SUGG | |
1768 | #undef QTY_CMP_PRI | |
51b86d8b | 1769 | \f |
2bbd3819 RS |
1770 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. |
1771 | Returns 1 if have done so, or 0 if cannot. | |
1772 | ||
1773 | Combining registers means marking them as having the same quantity | |
1774 | and adjusting the offsets within the quantity if either of | |
1775 | them is a SUBREG). | |
1776 | ||
1777 | We don't actually combine a hard reg with a pseudo; instead | |
1778 | we just record the hard reg as the suggestion for the pseudo's quantity. | |
1779 | If we really combined them, we could lose if the pseudo lives | |
1780 | across an insn that clobbers the hard reg (eg, movstr). | |
1781 | ||
1782 | ALREADY_DEAD is non-zero if USEDREG is known to be dead even though | |
1783 | there is no REG_DEAD note on INSN. This occurs during the processing | |
1784 | of REG_NO_CONFLICT blocks. | |
1785 | ||
1786 | MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to | |
1787 | SETREG or if the input and output must share a register. | |
1788 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. | |
64e3a413 | 1789 | |
2bbd3819 RS |
1790 | There are elaborate checks for the validity of combining. */ |
1791 | ||
2bbd3819 RS |
1792 | static int |
1793 | combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) | |
1794 | rtx usedreg, setreg; | |
1795 | int may_save_copy; | |
1796 | int insn_number; | |
1797 | rtx insn; | |
1798 | int already_dead; | |
1799 | { | |
1800 | register int ureg, sreg; | |
1801 | register int offset = 0; | |
1802 | int usize, ssize; | |
1803 | register int sqty; | |
1804 | ||
1805 | /* Determine the numbers and sizes of registers being used. If a subreg | |
6dc42e49 | 1806 | is present that does not change the entire register, don't consider |
2bbd3819 RS |
1807 | this a copy insn. */ |
1808 | ||
1809 | while (GET_CODE (usedreg) == SUBREG) | |
1810 | { | |
1811 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) | |
1812 | may_save_copy = 0; | |
1813 | offset += SUBREG_WORD (usedreg); | |
1814 | usedreg = SUBREG_REG (usedreg); | |
1815 | } | |
1816 | if (GET_CODE (usedreg) != REG) | |
1817 | return 0; | |
1818 | ureg = REGNO (usedreg); | |
1819 | usize = REG_SIZE (usedreg); | |
1820 | ||
1821 | while (GET_CODE (setreg) == SUBREG) | |
1822 | { | |
1823 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) | |
1824 | may_save_copy = 0; | |
1825 | offset -= SUBREG_WORD (setreg); | |
1826 | setreg = SUBREG_REG (setreg); | |
1827 | } | |
1828 | if (GET_CODE (setreg) != REG) | |
1829 | return 0; | |
1830 | sreg = REGNO (setreg); | |
1831 | ssize = REG_SIZE (setreg); | |
1832 | ||
1833 | /* If UREG is a pseudo-register that hasn't already been assigned a | |
1834 | quantity number, it means that it is not local to this block or dies | |
1835 | more than once. In either event, we can't do anything with it. */ | |
1836 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) | |
1837 | /* Do not combine registers unless one fits within the other. */ | |
1838 | || (offset > 0 && usize + offset > ssize) | |
1839 | || (offset < 0 && usize + offset < ssize) | |
1840 | /* Do not combine with a smaller already-assigned object | |
0f41302f | 1841 | if that smaller object is already combined with something bigger. */ |
2bbd3819 | 1842 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER |
a1ed7bdb | 1843 | && usize < qty[reg_qty[ureg]].size) |
2bbd3819 RS |
1844 | /* Can't combine if SREG is not a register we can allocate. */ |
1845 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) | |
1846 | /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. | |
1847 | These have already been taken care of. This probably wouldn't | |
1848 | combine anyway, but don't take any chances. */ | |
1849 | || (ureg >= FIRST_PSEUDO_REGISTER | |
1850 | && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) | |
1851 | /* Don't tie something to itself. In most cases it would make no | |
1852 | difference, but it would screw up if the reg being tied to itself | |
1853 | also dies in this insn. */ | |
1854 | || ureg == sreg | |
1855 | /* Don't try to connect two different hardware registers. */ | |
1856 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) | |
1857 | /* Don't connect two different machine modes if they have different | |
1858 | implications as to which registers may be used. */ | |
1859 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) | |
1860 | return 0; | |
1861 | ||
1862 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in | |
1863 | qty_phys_sugg for the pseudo instead of tying them. | |
1864 | ||
1865 | Return "failure" so that the lifespan of UREG is terminated here; | |
1866 | that way the two lifespans will be disjoint and nothing will prevent | |
1867 | the pseudo reg from being given this hard reg. */ | |
1868 | ||
1869 | if (ureg < FIRST_PSEUDO_REGISTER) | |
1870 | { | |
1871 | /* Allocate a quantity number so we have a place to put our | |
1872 | suggestions. */ | |
1873 | if (reg_qty[sreg] == -2) | |
1874 | reg_is_born (setreg, 2 * insn_number); | |
1875 | ||
1876 | if (reg_qty[sreg] >= 0) | |
1877 | { | |
51b86d8b RK |
1878 | if (may_save_copy |
1879 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) | |
2bbd3819 RS |
1880 | { |
1881 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1882 | qty_phys_num_copy_sugg[reg_qty[sreg]]++; |
2bbd3819 | 1883 | } |
51b86d8b | 1884 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) |
2bbd3819 RS |
1885 | { |
1886 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1887 | qty_phys_num_sugg[reg_qty[sreg]]++; |
2bbd3819 RS |
1888 | } |
1889 | } | |
1890 | return 0; | |
1891 | } | |
1892 | ||
1893 | /* Similarly for SREG a hard register and UREG a pseudo register. */ | |
1894 | ||
1895 | if (sreg < FIRST_PSEUDO_REGISTER) | |
1896 | { | |
51b86d8b RK |
1897 | if (may_save_copy |
1898 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) | |
2bbd3819 RS |
1899 | { |
1900 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1901 | qty_phys_num_copy_sugg[reg_qty[ureg]]++; |
2bbd3819 | 1902 | } |
51b86d8b | 1903 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) |
2bbd3819 RS |
1904 | { |
1905 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1906 | qty_phys_num_sugg[reg_qty[ureg]]++; |
2bbd3819 RS |
1907 | } |
1908 | return 0; | |
1909 | } | |
1910 | ||
1911 | /* At this point we know that SREG and UREG are both pseudos. | |
1912 | Do nothing if SREG already has a quantity or is a register that we | |
1913 | don't allocate. */ | |
1914 | if (reg_qty[sreg] >= -1 | |
1915 | /* If we are not going to let any regs live across calls, | |
1916 | don't tie a call-crossing reg to a non-call-crossing reg. */ | |
1917 | || (current_function_has_nonlocal_label | |
b1f21e0a MM |
1918 | && ((REG_N_CALLS_CROSSED (ureg) > 0) |
1919 | != (REG_N_CALLS_CROSSED (sreg) > 0)))) | |
2bbd3819 RS |
1920 | return 0; |
1921 | ||
1922 | /* We don't already know about SREG, so tie it to UREG | |
1923 | if this is the last use of UREG, provided the classes they want | |
1924 | are compatible. */ | |
1925 | ||
1926 | if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) | |
a1ed7bdb | 1927 | && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class)) |
2bbd3819 RS |
1928 | { |
1929 | /* Add SREG to UREG's quantity. */ | |
1930 | sqty = reg_qty[ureg]; | |
1931 | reg_qty[sreg] = sqty; | |
1932 | reg_offset[sreg] = reg_offset[ureg] + offset; | |
a1ed7bdb JH |
1933 | reg_next_in_qty[sreg] = qty[sqty].first_reg; |
1934 | qty[sqty].first_reg = sreg; | |
2bbd3819 | 1935 | |
a1ed7bdb | 1936 | /* If SREG's reg class is smaller, set qty[SQTY].min_class. */ |
2bbd3819 RS |
1937 | update_qty_class (sqty, sreg); |
1938 | ||
1939 | /* Update info about quantity SQTY. */ | |
a1ed7bdb JH |
1940 | qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg); |
1941 | qty[sqty].n_refs += REG_N_REFS (sreg); | |
2bbd3819 RS |
1942 | if (usize < ssize) |
1943 | { | |
1944 | register int i; | |
1945 | ||
a1ed7bdb | 1946 | for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i]) |
2bbd3819 RS |
1947 | reg_offset[i] -= offset; |
1948 | ||
a1ed7bdb JH |
1949 | qty[sqty].size = ssize; |
1950 | qty[sqty].mode = GET_MODE (setreg); | |
2bbd3819 RS |
1951 | } |
1952 | } | |
1953 | else | |
1954 | return 0; | |
1955 | ||
1956 | return 1; | |
1957 | } | |
1958 | \f | |
1959 | /* Return 1 if the preferred class of REG allows it to be tied | |
1960 | to a quantity or register whose class is CLASS. | |
1961 | True if REG's reg class either contains or is contained in CLASS. */ | |
1962 | ||
1963 | static int | |
1964 | reg_meets_class_p (reg, class) | |
1965 | int reg; | |
1966 | enum reg_class class; | |
1967 | { | |
1968 | register enum reg_class rclass = reg_preferred_class (reg); | |
1969 | return (reg_class_subset_p (rclass, class) | |
1970 | || reg_class_subset_p (class, rclass)); | |
1971 | } | |
1972 | ||
a1ed7bdb | 1973 | /* Update the class of QTYNO assuming that REG is being tied to it. */ |
2bbd3819 RS |
1974 | |
1975 | static void | |
a1ed7bdb JH |
1976 | update_qty_class (qtyno, reg) |
1977 | int qtyno; | |
2bbd3819 RS |
1978 | int reg; |
1979 | { | |
1980 | enum reg_class rclass = reg_preferred_class (reg); | |
a1ed7bdb JH |
1981 | if (reg_class_subset_p (rclass, qty[qtyno].min_class)) |
1982 | qty[qtyno].min_class = rclass; | |
e4600702 RK |
1983 | |
1984 | rclass = reg_alternate_class (reg); | |
a1ed7bdb JH |
1985 | if (reg_class_subset_p (rclass, qty[qtyno].alternate_class)) |
1986 | qty[qtyno].alternate_class = rclass; | |
0f64b8f6 | 1987 | |
02188693 RH |
1988 | if (REG_CHANGES_MODE (reg)) |
1989 | qty[qtyno].changes_mode = 1; | |
2bbd3819 RS |
1990 | } |
1991 | \f | |
1992 | /* Handle something which alters the value of an rtx REG. | |
1993 | ||
1994 | REG is whatever is set or clobbered. SETTER is the rtx that | |
1995 | is modifying the register. | |
1996 | ||
1997 | If it is not really a register, we do nothing. | |
1998 | The file-global variables `this_insn' and `this_insn_number' | |
1999 | carry info from `block_alloc'. */ | |
2000 | ||
2001 | static void | |
84832317 | 2002 | reg_is_set (reg, setter, data) |
2bbd3819 RS |
2003 | rtx reg; |
2004 | rtx setter; | |
84832317 | 2005 | void *data ATTRIBUTE_UNUSED; |
2bbd3819 RS |
2006 | { |
2007 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of | |
2008 | a hard register. These may actually not exist any more. */ | |
2009 | ||
2010 | if (GET_CODE (reg) != SUBREG | |
2011 | && GET_CODE (reg) != REG) | |
2012 | return; | |
2013 | ||
2014 | /* Mark this register as being born. If it is used in a CLOBBER, mark | |
2015 | it as being born halfway between the previous insn and this insn so that | |
2016 | it conflicts with our inputs but not the outputs of the previous insn. */ | |
2017 | ||
2018 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); | |
2019 | } | |
2020 | \f | |
2021 | /* Handle beginning of the life of register REG. | |
2022 | BIRTH is the index at which this is happening. */ | |
2023 | ||
2024 | static void | |
2025 | reg_is_born (reg, birth) | |
2026 | rtx reg; | |
2027 | int birth; | |
2028 | { | |
2029 | register int regno; | |
64e3a413 | 2030 | |
2bbd3819 RS |
2031 | if (GET_CODE (reg) == SUBREG) |
2032 | regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg); | |
2033 | else | |
2034 | regno = REGNO (reg); | |
2035 | ||
2036 | if (regno < FIRST_PSEUDO_REGISTER) | |
2037 | { | |
2038 | mark_life (regno, GET_MODE (reg), 1); | |
2039 | ||
2040 | /* If the register was to have been born earlier that the present | |
2041 | insn, mark it as live where it is actually born. */ | |
2042 | if (birth < 2 * this_insn_number) | |
2043 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); | |
2044 | } | |
2045 | else | |
2046 | { | |
2047 | if (reg_qty[regno] == -2) | |
2048 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); | |
2049 | ||
2050 | /* If this register has a quantity number, show that it isn't dead. */ | |
2051 | if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2052 | qty[reg_qty[regno]].death = -1; |
2bbd3819 RS |
2053 | } |
2054 | } | |
2055 | ||
2056 | /* Record the death of REG in the current insn. If OUTPUT_P is non-zero, | |
2057 | REG is an output that is dying (i.e., it is never used), otherwise it | |
333e0f7d RS |
2058 | is an input (the normal case). |
2059 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ | |
2bbd3819 RS |
2060 | |
2061 | static void | |
2062 | wipe_dead_reg (reg, output_p) | |
2063 | register rtx reg; | |
2064 | int output_p; | |
2065 | { | |
2066 | register int regno = REGNO (reg); | |
2067 | ||
333e0f7d RS |
2068 | /* If this insn has multiple results, |
2069 | and the dead reg is used in one of the results, | |
2070 | extend its life to after this insn, | |
64e3a413 | 2071 | so it won't get allocated together with any other result of this insn. |
941c63ac JL |
2072 | |
2073 | It is unsafe to use !single_set here since it will ignore an unused | |
2074 | output. Just because an output is unused does not mean the compiler | |
2075 | can assume the side effect will not occur. Consider if REG appears | |
2076 | in the address of an output and we reload the output. If we allocate | |
2077 | REG to the same hard register as an unused output we could set the hard | |
2078 | register before the output reload insn. */ | |
333e0f7d | 2079 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL |
941c63ac | 2080 | && multiple_sets (this_insn)) |
333e0f7d RS |
2081 | { |
2082 | int i; | |
2083 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) | |
2084 | { | |
2085 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); | |
2086 | if (GET_CODE (set) == SET | |
2087 | && GET_CODE (SET_DEST (set)) != REG | |
2088 | && !rtx_equal_p (reg, SET_DEST (set)) | |
2089 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2090 | output_p = 1; | |
2091 | } | |
2092 | } | |
2093 | ||
c182df0b RK |
2094 | /* If this register is used in an auto-increment address, then extend its |
2095 | life to after this insn, so that it won't get allocated together with | |
2096 | the result of this insn. */ | |
2097 | if (! output_p && find_regno_note (this_insn, REG_INC, regno)) | |
2098 | output_p = 1; | |
2099 | ||
2bbd3819 RS |
2100 | if (regno < FIRST_PSEUDO_REGISTER) |
2101 | { | |
2102 | mark_life (regno, GET_MODE (reg), 0); | |
2103 | ||
2104 | /* If a hard register is dying as an output, mark it as in use at | |
2105 | the beginning of this insn (the above statement would cause this | |
2106 | not to happen). */ | |
2107 | if (output_p) | |
2108 | post_mark_life (regno, GET_MODE (reg), 1, | |
64e3a413 | 2109 | 2 * this_insn_number, 2 * this_insn_number + 1); |
2bbd3819 RS |
2110 | } |
2111 | ||
2112 | else if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2113 | qty[reg_qty[regno]].death = 2 * this_insn_number + output_p; |
2bbd3819 RS |
2114 | } |
2115 | \f | |
2116 | /* Find a block of SIZE words of hard regs in reg_class CLASS | |
2117 | that can hold something of machine-mode MODE | |
2118 | (but actually we test only the first of the block for holding MODE) | |
2119 | and still free between insn BORN_INDEX and insn DEAD_INDEX, | |
2120 | and return the number of the first of them. | |
64e3a413 | 2121 | Return -1 if such a block cannot be found. |
a1ed7bdb | 2122 | If QTYNO crosses calls, insist on a register preserved by calls, |
2bbd3819 RS |
2123 | unless ACCEPT_CALL_CLOBBERED is nonzero. |
2124 | ||
2125 | If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested | |
2126 | register is available. If not, return -1. */ | |
2127 | ||
2128 | static int | |
a1ed7bdb | 2129 | find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested, |
2bbd3819 RS |
2130 | born_index, dead_index) |
2131 | enum reg_class class; | |
2132 | enum machine_mode mode; | |
a1ed7bdb | 2133 | int qtyno; |
2bbd3819 RS |
2134 | int accept_call_clobbered; |
2135 | int just_try_suggested; | |
2bbd3819 RS |
2136 | int born_index, dead_index; |
2137 | { | |
2138 | register int i, ins; | |
2139 | #ifdef HARD_REG_SET | |
64e3a413 KH |
2140 | /* Declare it register if it's a scalar. */ |
2141 | register | |
2bbd3819 RS |
2142 | #endif |
2143 | HARD_REG_SET used, first_used; | |
2144 | #ifdef ELIMINABLE_REGS | |
2145 | static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; | |
2146 | #endif | |
2147 | ||
2148 | /* Validate our parameters. */ | |
2149 | if (born_index < 0 || born_index > dead_index) | |
2150 | abort (); | |
2151 | ||
2152 | /* Don't let a pseudo live in a reg across a function call | |
2153 | if we might get a nonlocal goto. */ | |
2154 | if (current_function_has_nonlocal_label | |
a1ed7bdb | 2155 | && qty[qtyno].n_calls_crossed > 0) |
2bbd3819 RS |
2156 | return -1; |
2157 | ||
2158 | if (accept_call_clobbered) | |
2159 | COPY_HARD_REG_SET (used, call_fixed_reg_set); | |
a1ed7bdb | 2160 | else if (qty[qtyno].n_calls_crossed == 0) |
2bbd3819 RS |
2161 | COPY_HARD_REG_SET (used, fixed_reg_set); |
2162 | else | |
2163 | COPY_HARD_REG_SET (used, call_used_reg_set); | |
2164 | ||
6cad67d2 | 2165 | if (accept_call_clobbered) |
c09be6c4 | 2166 | IOR_HARD_REG_SET (used, losing_caller_save_reg_set); |
6cad67d2 | 2167 | |
2bbd3819 RS |
2168 | for (ins = born_index; ins < dead_index; ins++) |
2169 | IOR_HARD_REG_SET (used, regs_live_at[ins]); | |
2170 | ||
2171 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); | |
2172 | ||
2173 | /* Don't use the frame pointer reg in local-alloc even if | |
2174 | we may omit the frame pointer, because if we do that and then we | |
2175 | need a frame pointer, reload won't know how to move the pseudo | |
2176 | to another hard reg. It can move only regs made by global-alloc. | |
2177 | ||
2178 | This is true of any register that can be eliminated. */ | |
2179 | #ifdef ELIMINABLE_REGS | |
b6a1cbae | 2180 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) |
2bbd3819 | 2181 | SET_HARD_REG_BIT (used, eliminables[i].from); |
c2618f05 DE |
2182 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
2183 | /* If FRAME_POINTER_REGNUM is not a real register, then protect the one | |
0f41302f | 2184 | that it might be eliminated into. */ |
c2618f05 DE |
2185 | SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); |
2186 | #endif | |
2bbd3819 RS |
2187 | #else |
2188 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); | |
2189 | #endif | |
2190 | ||
02188693 RH |
2191 | #ifdef CLASS_CANNOT_CHANGE_MODE |
2192 | if (qty[qtyno].changes_mode) | |
899d4140 | 2193 | IOR_HARD_REG_SET (used, |
02188693 | 2194 | reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]); |
0f64b8f6 RK |
2195 | #endif |
2196 | ||
2bbd3819 RS |
2197 | /* Normally, the registers that can be used for the first register in |
2198 | a multi-register quantity are the same as those that can be used for | |
2199 | subsequent registers. However, if just trying suggested registers, | |
2200 | restrict our consideration to them. If there are copy-suggested | |
2201 | register, try them. Otherwise, try the arithmetic-suggested | |
2202 | registers. */ | |
2203 | COPY_HARD_REG_SET (first_used, used); | |
2204 | ||
2205 | if (just_try_suggested) | |
2206 | { | |
a1ed7bdb JH |
2207 | if (qty_phys_num_copy_sugg[qtyno] != 0) |
2208 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]); | |
2bbd3819 | 2209 | else |
a1ed7bdb | 2210 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]); |
2bbd3819 RS |
2211 | } |
2212 | ||
2213 | /* If all registers are excluded, we can't do anything. */ | |
2214 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); | |
2215 | ||
2216 | /* If at least one would be suitable, test each hard reg. */ | |
2217 | ||
2218 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2219 | { | |
2220 | #ifdef REG_ALLOC_ORDER | |
2221 | int regno = reg_alloc_order[i]; | |
2222 | #else | |
2223 | int regno = i; | |
2224 | #endif | |
2225 | if (! TEST_HARD_REG_BIT (first_used, regno) | |
1e326708 | 2226 | && HARD_REGNO_MODE_OK (regno, mode) |
a1ed7bdb | 2227 | && (qty[qtyno].n_calls_crossed == 0 |
1e326708 MH |
2228 | || accept_call_clobbered |
2229 | || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
2bbd3819 RS |
2230 | { |
2231 | register int j; | |
2232 | register int size1 = HARD_REGNO_NREGS (regno, mode); | |
2233 | for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); | |
2234 | if (j == size1) | |
2235 | { | |
2236 | /* Mark that this register is in use between its birth and death | |
2237 | insns. */ | |
2238 | post_mark_life (regno, mode, 1, born_index, dead_index); | |
2239 | return regno; | |
2240 | } | |
2241 | #ifndef REG_ALLOC_ORDER | |
64e3a413 KH |
2242 | /* Skip starting points we know will lose. */ |
2243 | i += j; | |
2bbd3819 RS |
2244 | #endif |
2245 | } | |
2246 | } | |
2247 | ||
2248 | fail: | |
2bbd3819 RS |
2249 | /* If we are just trying suggested register, we have just tried copy- |
2250 | suggested registers, and there are arithmetic-suggested registers, | |
2251 | try them. */ | |
64e3a413 | 2252 | |
2bbd3819 RS |
2253 | /* If it would be profitable to allocate a call-clobbered register |
2254 | and save and restore it around calls, do that. */ | |
a1ed7bdb JH |
2255 | if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0 |
2256 | && qty_phys_num_sugg[qtyno] != 0) | |
2bbd3819 RS |
2257 | { |
2258 | /* Don't try the copy-suggested regs again. */ | |
a1ed7bdb JH |
2259 | qty_phys_num_copy_sugg[qtyno] = 0; |
2260 | return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1, | |
2bbd3819 RS |
2261 | born_index, dead_index); |
2262 | } | |
2263 | ||
e19f5192 RK |
2264 | /* We need not check to see if the current function has nonlocal |
2265 | labels because we don't put any pseudos that are live over calls in | |
2266 | registers in that case. */ | |
2267 | ||
2bbd3819 RS |
2268 | if (! accept_call_clobbered |
2269 | && flag_caller_saves | |
2270 | && ! just_try_suggested | |
a1ed7bdb | 2271 | && qty[qtyno].n_calls_crossed != 0 |
64e3a413 KH |
2272 | && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs, |
2273 | qty[qtyno].n_calls_crossed)) | |
2bbd3819 | 2274 | { |
a1ed7bdb | 2275 | i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index); |
2bbd3819 RS |
2276 | if (i >= 0) |
2277 | caller_save_needed = 1; | |
2278 | return i; | |
2279 | } | |
2280 | return -1; | |
2281 | } | |
2282 | \f | |
2283 | /* Mark that REGNO with machine-mode MODE is live starting from the current | |
2284 | insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE | |
2285 | is zero). */ | |
2286 | ||
2287 | static void | |
2288 | mark_life (regno, mode, life) | |
2289 | register int regno; | |
2290 | enum machine_mode mode; | |
2291 | int life; | |
2292 | { | |
2293 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2294 | if (life) | |
2295 | while (--j >= 0) | |
2296 | SET_HARD_REG_BIT (regs_live, regno + j); | |
2297 | else | |
2298 | while (--j >= 0) | |
2299 | CLEAR_HARD_REG_BIT (regs_live, regno + j); | |
2300 | } | |
2301 | ||
2302 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE | |
2303 | is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) | |
2304 | to insn number DEATH (exclusive). */ | |
2305 | ||
2306 | static void | |
2307 | post_mark_life (regno, mode, life, birth, death) | |
82c68a78 | 2308 | int regno; |
2bbd3819 | 2309 | enum machine_mode mode; |
82c68a78 | 2310 | int life, birth, death; |
2bbd3819 RS |
2311 | { |
2312 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2313 | #ifdef HARD_REG_SET | |
64e3a413 KH |
2314 | /* Declare it register if it's a scalar. */ |
2315 | register | |
2bbd3819 RS |
2316 | #endif |
2317 | HARD_REG_SET this_reg; | |
2318 | ||
2319 | CLEAR_HARD_REG_SET (this_reg); | |
2320 | while (--j >= 0) | |
2321 | SET_HARD_REG_BIT (this_reg, regno + j); | |
2322 | ||
2323 | if (life) | |
2324 | while (birth < death) | |
2325 | { | |
2326 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2327 | birth++; | |
2328 | } | |
2329 | else | |
2330 | while (birth < death) | |
2331 | { | |
2332 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2333 | birth++; | |
2334 | } | |
2335 | } | |
2336 | \f | |
2337 | /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 | |
2338 | is the register being clobbered, and R1 is a register being used in | |
2339 | the equivalent expression. | |
2340 | ||
2341 | If R1 dies in the block and has a REG_NO_CONFLICT note on every insn | |
2342 | in which it is used, return 1. | |
2343 | ||
2344 | Otherwise, return 0. */ | |
2345 | ||
2346 | static int | |
2347 | no_conflict_p (insn, r0, r1) | |
272df862 | 2348 | rtx insn, r0 ATTRIBUTE_UNUSED, r1; |
2bbd3819 RS |
2349 | { |
2350 | int ok = 0; | |
b1ec3c92 | 2351 | rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); |
2bbd3819 RS |
2352 | rtx p, last; |
2353 | ||
2354 | /* If R1 is a hard register, return 0 since we handle this case | |
2355 | when we scan the insns that actually use it. */ | |
2356 | ||
2357 | if (note == 0 | |
2358 | || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) | |
2359 | || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG | |
2360 | && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) | |
2361 | return 0; | |
2362 | ||
2363 | last = XEXP (note, 0); | |
2364 | ||
2365 | for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) | |
2c3c49de | 2366 | if (INSN_P (p)) |
2bbd3819 RS |
2367 | { |
2368 | if (find_reg_note (p, REG_DEAD, r1)) | |
2369 | ok = 1; | |
2370 | ||
8bb19658 JW |
2371 | /* There must be a REG_NO_CONFLICT note on every insn, otherwise |
2372 | some earlier optimization pass has inserted instructions into | |
2373 | the sequence, and it is not safe to perform this optimization. | |
2374 | Note that emit_no_conflict_block always ensures that this is | |
2375 | true when these sequences are created. */ | |
2376 | if (! find_reg_note (p, REG_NO_CONFLICT, r1)) | |
2bbd3819 RS |
2377 | return 0; |
2378 | } | |
64e3a413 | 2379 | |
2bbd3819 RS |
2380 | return ok; |
2381 | } | |
2382 | \f | |
3061cc54 RK |
2383 | /* Return the number of alternatives for which the constraint string P |
2384 | indicates that the operand must be equal to operand 0 and that no register | |
2385 | is acceptable. */ | |
2bbd3819 RS |
2386 | |
2387 | static int | |
3061cc54 | 2388 | requires_inout (p) |
64e3a413 | 2389 | const char *p; |
2bbd3819 RS |
2390 | { |
2391 | char c; | |
2392 | int found_zero = 0; | |
3061cc54 RK |
2393 | int reg_allowed = 0; |
2394 | int num_matching_alts = 0; | |
2bbd3819 | 2395 | |
51723711 | 2396 | while ((c = *p++)) |
2bbd3819 RS |
2397 | switch (c) |
2398 | { | |
2bbd3819 RS |
2399 | case '=': case '+': case '?': |
2400 | case '#': case '&': case '!': | |
3061cc54 | 2401 | case '*': case '%': |
c5c76735 JL |
2402 | case '1': case '2': case '3': case '4': case '5': |
2403 | case '6': case '7': case '8': case '9': | |
2bbd3819 RS |
2404 | case 'm': case '<': case '>': case 'V': case 'o': |
2405 | case 'E': case 'F': case 'G': case 'H': | |
2406 | case 's': case 'i': case 'n': | |
2407 | case 'I': case 'J': case 'K': case 'L': | |
2408 | case 'M': case 'N': case 'O': case 'P': | |
2bbd3819 RS |
2409 | case 'X': |
2410 | /* These don't say anything we care about. */ | |
2411 | break; | |
2412 | ||
3061cc54 RK |
2413 | case ',': |
2414 | if (found_zero && ! reg_allowed) | |
2415 | num_matching_alts++; | |
2416 | ||
2417 | found_zero = reg_allowed = 0; | |
2418 | break; | |
2419 | ||
2420 | case '0': | |
2421 | found_zero = 1; | |
2422 | break; | |
2423 | ||
c2cba7a9 RH |
2424 | default: |
2425 | if (REG_CLASS_FROM_LETTER (c) == NO_REGS) | |
2426 | break; | |
2427 | /* FALLTHRU */ | |
2bbd3819 RS |
2428 | case 'p': |
2429 | case 'g': case 'r': | |
3061cc54 RK |
2430 | reg_allowed = 1; |
2431 | break; | |
2bbd3819 RS |
2432 | } |
2433 | ||
3061cc54 RK |
2434 | if (found_zero && ! reg_allowed) |
2435 | num_matching_alts++; | |
2436 | ||
2437 | return num_matching_alts; | |
2bbd3819 RS |
2438 | } |
2439 | \f | |
2440 | void | |
2441 | dump_local_alloc (file) | |
2442 | FILE *file; | |
2443 | { | |
2444 | register int i; | |
2445 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
2446 | if (reg_renumber[i] != -1) | |
2447 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); | |
2448 | } |