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2bbd3819 RS |
1 | /* Allocate registers within a basic block, for GNU compiler. |
2 | Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | /* Allocation of hard register numbers to pseudo registers is done in | |
22 | two passes. In this pass we consider only regs that are born and | |
23 | die once within one basic block. We do this one basic block at a | |
24 | time. Then the next pass allocates the registers that remain. | |
25 | Two passes are used because this pass uses methods that work only | |
26 | on linear code, but that do a better job than the general methods | |
27 | used in global_alloc, and more quickly too. | |
28 | ||
29 | The assignments made are recorded in the vector reg_renumber | |
30 | whose space is allocated here. The rtl code itself is not altered. | |
31 | ||
32 | We assign each instruction in the basic block a number | |
33 | which is its order from the beginning of the block. | |
34 | Then we can represent the lifetime of a pseudo register with | |
35 | a pair of numbers, and check for conflicts easily. | |
36 | We can record the availability of hard registers with a | |
37 | HARD_REG_SET for each instruction. The HARD_REG_SET | |
38 | contains 0 or 1 for each hard reg. | |
39 | ||
40 | To avoid register shuffling, we tie registers together when one | |
41 | dies by being copied into another, or dies in an instruction that | |
42 | does arithmetic to produce another. The tied registers are | |
43 | allocated as one. Registers with different reg class preferences | |
44 | can never be tied unless the class preferred by one is a subclass | |
45 | of the one preferred by the other. | |
46 | ||
47 | Tying is represented with "quantity numbers". | |
48 | A non-tied register is given a new quantity number. | |
49 | Tied registers have the same quantity number. | |
50 | ||
51 | We have provision to exempt registers, even when they are contained | |
52 | within the block, that can be tied to others that are not contained in it. | |
53 | This is so that global_alloc could process them both and tie them then. | |
54 | But this is currently disabled since tying in global_alloc is not | |
55 | yet implemented. */ | |
56 | ||
57 | #include <stdio.h> | |
58 | #include "config.h" | |
59 | #include "rtl.h" | |
60 | #include "flags.h" | |
61 | #include "basic-block.h" | |
62 | #include "regs.h" | |
63 | #include "hard-reg-set.h" | |
64 | #include "insn-config.h" | |
65 | #include "recog.h" | |
66 | #include "output.h" | |
67 | \f | |
cde62d1a RK |
68 | /* Pseudos allocated here cannot be reallocated by global.c if the hard |
69 | register is used as a spill register. So we don't allocate such pseudos | |
70 | here if their preferred class is likely to be used by spills. | |
71 | ||
72 | On most machines, the appropriate test is if the class has one | |
73 | register, so we default to that. */ | |
74 | ||
75 | #ifndef CLASS_LIKELY_SPILLED_P | |
76 | #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1) | |
77 | #endif | |
78 | ||
2bbd3819 RS |
79 | /* Next quantity number available for allocation. */ |
80 | ||
81 | static int next_qty; | |
82 | ||
83 | /* In all the following vectors indexed by quantity number. */ | |
84 | ||
85 | /* Element Q is the hard reg number chosen for quantity Q, | |
86 | or -1 if none was found. */ | |
87 | ||
88 | static short *qty_phys_reg; | |
89 | ||
90 | /* We maintain two hard register sets that indicate suggested hard registers | |
91 | for each quantity. The first, qty_phys_copy_sugg, contains hard registers | |
92 | that are tied to the quantity by a simple copy. The second contains all | |
93 | hard registers that are tied to the quantity via an arithmetic operation. | |
94 | ||
95 | The former register set is given priority for allocation. This tends to | |
96 | eliminate copy insns. */ | |
97 | ||
98 | /* Element Q is a set of hard registers that are suggested for quantity Q by | |
99 | copy insns. */ | |
100 | ||
101 | static HARD_REG_SET *qty_phys_copy_sugg; | |
102 | ||
103 | /* Element Q is a set of hard registers that are suggested for quantity Q by | |
104 | arithmetic insns. */ | |
105 | ||
106 | static HARD_REG_SET *qty_phys_sugg; | |
107 | ||
108 | /* Element Q is non-zero if there is a suggested register in | |
109 | qty_phys_copy_sugg. */ | |
110 | ||
111 | static char *qty_phys_has_copy_sugg; | |
112 | ||
113 | /* Element Q is non-zero if there is a suggested register in qty_phys_sugg. */ | |
114 | ||
115 | static char *qty_phys_has_sugg; | |
116 | ||
117 | /* Element Q is the number of refs to quantity Q. */ | |
118 | ||
aabf56ce | 119 | static int *qty_n_refs; |
2bbd3819 RS |
120 | |
121 | /* Element Q is a reg class contained in (smaller than) the | |
122 | preferred classes of all the pseudo regs that are tied in quantity Q. | |
123 | This is the preferred class for allocating that quantity. */ | |
124 | ||
125 | static enum reg_class *qty_min_class; | |
126 | ||
127 | /* Insn number (counting from head of basic block) | |
128 | where quantity Q was born. -1 if birth has not been recorded. */ | |
129 | ||
130 | static int *qty_birth; | |
131 | ||
132 | /* Insn number (counting from head of basic block) | |
133 | where quantity Q died. Due to the way tying is done, | |
134 | and the fact that we consider in this pass only regs that die but once, | |
135 | a quantity can die only once. Each quantity's life span | |
136 | is a set of consecutive insns. -1 if death has not been recorded. */ | |
137 | ||
138 | static int *qty_death; | |
139 | ||
140 | /* Number of words needed to hold the data in quantity Q. | |
141 | This depends on its machine mode. It is used for these purposes: | |
142 | 1. It is used in computing the relative importances of qtys, | |
143 | which determines the order in which we look for regs for them. | |
144 | 2. It is used in rules that prevent tying several registers of | |
145 | different sizes in a way that is geometrically impossible | |
146 | (see combine_regs). */ | |
147 | ||
148 | static int *qty_size; | |
149 | ||
150 | /* This holds the mode of the registers that are tied to qty Q, | |
151 | or VOIDmode if registers with differing modes are tied together. */ | |
152 | ||
153 | static enum machine_mode *qty_mode; | |
154 | ||
155 | /* Number of times a reg tied to qty Q lives across a CALL_INSN. */ | |
156 | ||
157 | static int *qty_n_calls_crossed; | |
158 | ||
e4600702 RK |
159 | /* Register class within which we allocate qty Q if we can't get |
160 | its preferred class. */ | |
2bbd3819 | 161 | |
e4600702 | 162 | static enum reg_class *qty_alternate_class; |
2bbd3819 RS |
163 | |
164 | /* Element Q is the SCRATCH expression for which this quantity is being | |
165 | allocated or 0 if this quantity is allocating registers. */ | |
166 | ||
167 | static rtx *qty_scratch_rtx; | |
168 | ||
169 | /* Element Q is the register number of one pseudo register whose | |
170 | reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This | |
171 | register should be the head of the chain maintained in reg_next_in_qty. */ | |
172 | ||
aabf56ce | 173 | static int *qty_first_reg; |
2bbd3819 RS |
174 | |
175 | /* If (REG N) has been assigned a quantity number, is a register number | |
176 | of another register assigned the same quantity number, or -1 for the | |
177 | end of the chain. qty_first_reg point to the head of this chain. */ | |
178 | ||
aabf56ce | 179 | static int *reg_next_in_qty; |
2bbd3819 RS |
180 | |
181 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg | |
182 | if it is >= 0, | |
183 | of -1 if this register cannot be allocated by local-alloc, | |
184 | or -2 if not known yet. | |
185 | ||
186 | Note that if we see a use or death of pseudo register N with | |
187 | reg_qty[N] == -2, register N must be local to the current block. If | |
188 | it were used in more than one block, we would have reg_qty[N] == -1. | |
189 | This relies on the fact that if reg_basic_block[N] is >= 0, register N | |
190 | will not appear in any other block. We save a considerable number of | |
191 | tests by exploiting this. | |
192 | ||
193 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not | |
194 | be referenced. */ | |
195 | ||
196 | static int *reg_qty; | |
197 | ||
198 | /* The offset (in words) of register N within its quantity. | |
199 | This can be nonzero if register N is SImode, and has been tied | |
200 | to a subreg of a DImode register. */ | |
201 | ||
202 | static char *reg_offset; | |
203 | ||
204 | /* Vector of substitutions of register numbers, | |
205 | used to map pseudo regs into hardware regs. | |
206 | This is set up as a result of register allocation. | |
207 | Element N is the hard reg assigned to pseudo reg N, | |
208 | or is -1 if no hard reg was assigned. | |
209 | If N is a hard reg number, element N is N. */ | |
210 | ||
211 | short *reg_renumber; | |
212 | ||
213 | /* Set of hard registers live at the current point in the scan | |
214 | of the instructions in a basic block. */ | |
215 | ||
216 | static HARD_REG_SET regs_live; | |
217 | ||
218 | /* Each set of hard registers indicates registers live at a particular | |
219 | point in the basic block. For N even, regs_live_at[N] says which | |
220 | hard registers are needed *after* insn N/2 (i.e., they may not | |
221 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. | |
222 | ||
223 | If an object is to conflict with the inputs of insn J but not the | |
224 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, | |
225 | if it is to conflict with the outputs of insn J but not the inputs of | |
226 | insn J + 1, it is said to die at index J*2 + 1. */ | |
227 | ||
228 | static HARD_REG_SET *regs_live_at; | |
229 | ||
bd5f197a RK |
230 | int *scratch_block; |
231 | rtx *scratch_list; | |
232 | int scratch_list_length; | |
233 | static int scratch_index; | |
234 | ||
2bbd3819 RS |
235 | /* Communicate local vars `insn_number' and `insn' |
236 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ | |
237 | static int this_insn_number; | |
238 | static rtx this_insn; | |
239 | ||
240 | static void block_alloc (); | |
241 | static void update_equiv_regs (); | |
242 | static int no_conflict_p (); | |
243 | static int combine_regs (); | |
244 | static void wipe_dead_reg (); | |
245 | static int find_free_reg (); | |
246 | static void reg_is_born (); | |
247 | static void reg_is_set (); | |
248 | static void mark_life (); | |
249 | static void post_mark_life (); | |
250 | static int qty_compare (); | |
251 | static int qty_compare_1 (); | |
252 | static int reg_meets_class_p (); | |
253 | static void update_qty_class (); | |
254 | static int requires_inout_p (); | |
255 | \f | |
256 | /* Allocate a new quantity (new within current basic block) | |
257 | for register number REGNO which is born at index BIRTH | |
258 | within the block. MODE and SIZE are info on reg REGNO. */ | |
259 | ||
260 | static void | |
261 | alloc_qty (regno, mode, size, birth) | |
262 | int regno; | |
263 | enum machine_mode mode; | |
264 | int size, birth; | |
265 | { | |
266 | register int qty = next_qty++; | |
267 | ||
268 | reg_qty[regno] = qty; | |
269 | reg_offset[regno] = 0; | |
270 | reg_next_in_qty[regno] = -1; | |
271 | ||
272 | qty_first_reg[qty] = regno; | |
273 | qty_size[qty] = size; | |
274 | qty_mode[qty] = mode; | |
275 | qty_birth[qty] = birth; | |
276 | qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno]; | |
277 | qty_min_class[qty] = reg_preferred_class (regno); | |
e4600702 | 278 | qty_alternate_class[qty] = reg_alternate_class (regno); |
2bbd3819 RS |
279 | qty_n_refs[qty] = reg_n_refs[regno]; |
280 | } | |
281 | \f | |
282 | /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx | |
283 | used as operand N in INSN. We assume here that the SCRATCH is used in | |
284 | a CLOBBER. */ | |
285 | ||
286 | static void | |
287 | alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number) | |
288 | rtx scratch; | |
289 | int n; | |
290 | rtx insn; | |
291 | int insn_code_num, insn_number; | |
292 | { | |
293 | register int qty; | |
294 | enum reg_class class; | |
295 | char *p, c; | |
296 | int i; | |
297 | ||
7fe4336e | 298 | #ifdef REGISTER_CONSTRAINTS |
2bbd3819 RS |
299 | /* If we haven't yet computed which alternative will be used, do so now. |
300 | Then set P to the constraints for that alternative. */ | |
301 | if (which_alternative == -1) | |
302 | if (! constrain_operands (insn_code_num, 0)) | |
303 | return; | |
304 | ||
305 | for (p = insn_operand_constraint[insn_code_num][n], i = 0; | |
306 | *p && i < which_alternative; p++) | |
307 | if (*p == ',') | |
308 | i++; | |
309 | ||
310 | /* Compute the class required for this SCRATCH. If we don't need a | |
311 | register, the class will remain NO_REGS. If we guessed the alternative | |
312 | number incorrectly, reload will fix things up for us. */ | |
313 | ||
314 | class = NO_REGS; | |
315 | while ((c = *p++) != '\0' && c != ',') | |
316 | switch (c) | |
317 | { | |
318 | case '=': case '+': case '?': | |
319 | case '#': case '&': case '!': | |
320 | case '*': case '%': | |
321 | case '0': case '1': case '2': case '3': case '4': | |
322 | case 'm': case '<': case '>': case 'V': case 'o': | |
323 | case 'E': case 'F': case 'G': case 'H': | |
324 | case 's': case 'i': case 'n': | |
325 | case 'I': case 'J': case 'K': case 'L': | |
326 | case 'M': case 'N': case 'O': case 'P': | |
327 | #ifdef EXTRA_CONSTRAINT | |
328 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
329 | #endif | |
330 | case 'p': | |
331 | /* These don't say anything we care about. */ | |
332 | break; | |
333 | ||
334 | case 'X': | |
335 | /* We don't need to allocate this SCRATCH. */ | |
336 | return; | |
337 | ||
338 | case 'g': case 'r': | |
339 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
340 | break; | |
341 | ||
342 | default: | |
343 | class | |
344 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)]; | |
345 | break; | |
346 | } | |
347 | ||
cde62d1a | 348 | /* If CLASS has only a few registers, don't allocate the SCRATCH here since |
2bbd3819 RS |
349 | it will prevent that register from being used as a spill register. |
350 | reload will do the allocation. */ | |
351 | ||
cde62d1a | 352 | if (class == NO_REGS || CLASS_LIKELY_SPILLED_P (class)) |
2bbd3819 RS |
353 | return; |
354 | ||
7fe4336e RK |
355 | #else /* REGISTER_CONSTRAINTS */ |
356 | ||
357 | class = GENERAL_REGS; | |
358 | #endif | |
359 | ||
360 | ||
2bbd3819 RS |
361 | qty = next_qty++; |
362 | ||
363 | qty_first_reg[qty] = -1; | |
364 | qty_scratch_rtx[qty] = scratch; | |
365 | qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch)); | |
366 | qty_mode[qty] = GET_MODE (scratch); | |
367 | qty_birth[qty] = 2 * insn_number - 1; | |
368 | qty_death[qty] = 2 * insn_number + 1; | |
369 | qty_n_calls_crossed[qty] = 0; | |
370 | qty_min_class[qty] = class; | |
e4600702 | 371 | qty_alternate_class[qty] = NO_REGS; |
2bbd3819 RS |
372 | qty_n_refs[qty] = 1; |
373 | } | |
374 | \f | |
375 | /* Main entry point of this file. */ | |
376 | ||
377 | void | |
378 | local_alloc () | |
379 | { | |
380 | register int b, i; | |
381 | int max_qty; | |
382 | ||
383 | /* Leaf functions and non-leaf functions have different needs. | |
384 | If defined, let the machine say what kind of ordering we | |
385 | should use. */ | |
386 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC | |
387 | ORDER_REGS_FOR_LOCAL_ALLOC; | |
388 | #endif | |
389 | ||
390 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected | |
391 | registers. */ | |
392 | update_equiv_regs (); | |
393 | ||
394 | /* This sets the maximum number of quantities we can have. Quantity | |
d45cf215 | 395 | numbers start at zero and we can have one for each pseudo plus the |
6dc42e49 | 396 | number of SCRATCHes in the largest block, in the worst case. */ |
2bbd3819 RS |
397 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch; |
398 | ||
399 | /* Allocate vectors of temporary data. | |
400 | See the declarations of these variables, above, | |
401 | for what they mean. */ | |
402 | ||
bd5f197a RK |
403 | scratch_list_length = max_qty; |
404 | scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx)); | |
405 | bzero (scratch_list, scratch_list_length * sizeof (rtx)); | |
406 | scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int)); | |
407 | bzero (scratch_block, scratch_list_length * sizeof (int)); | |
408 | scratch_index = 0; | |
409 | ||
2bbd3819 RS |
410 | qty_phys_reg = (short *) alloca (max_qty * sizeof (short)); |
411 | qty_phys_copy_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); | |
412 | qty_phys_has_copy_sugg = (char *) alloca (max_qty * sizeof (char)); | |
413 | qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); | |
414 | qty_phys_has_sugg = (char *) alloca (max_qty * sizeof (char)); | |
415 | qty_birth = (int *) alloca (max_qty * sizeof (int)); | |
416 | qty_death = (int *) alloca (max_qty * sizeof (int)); | |
417 | qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx)); | |
aabf56ce | 418 | qty_first_reg = (int *) alloca (max_qty * sizeof (int)); |
2bbd3819 RS |
419 | qty_size = (int *) alloca (max_qty * sizeof (int)); |
420 | qty_mode = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode)); | |
421 | qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int)); | |
422 | qty_min_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); | |
e4600702 | 423 | qty_alternate_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); |
aabf56ce | 424 | qty_n_refs = (int *) alloca (max_qty * sizeof (int)); |
2bbd3819 RS |
425 | |
426 | reg_qty = (int *) alloca (max_regno * sizeof (int)); | |
427 | reg_offset = (char *) alloca (max_regno * sizeof (char)); | |
aabf56ce | 428 | reg_next_in_qty = (int *) alloca (max_regno * sizeof (int)); |
2bbd3819 RS |
429 | |
430 | reg_renumber = (short *) oballoc (max_regno * sizeof (short)); | |
431 | for (i = 0; i < max_regno; i++) | |
432 | reg_renumber[i] = -1; | |
433 | ||
434 | /* Determine which pseudo-registers can be allocated by local-alloc. | |
435 | In general, these are the registers used only in a single block and | |
436 | which only die once. However, if a register's preferred class has only | |
cde62d1a | 437 | a few entries, don't allocate this register here unless it is preferred |
2bbd3819 RS |
438 | or nothing since retry_global_alloc won't be able to move it to |
439 | GENERAL_REGS if a reload register of this class is needed. | |
440 | ||
441 | We need not be concerned with which block actually uses the register | |
442 | since we will never see it outside that block. */ | |
443 | ||
444 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
445 | { | |
446 | if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1 | |
e4600702 | 447 | && (reg_alternate_class (i) == NO_REGS |
cde62d1a | 448 | || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i)))) |
2bbd3819 RS |
449 | reg_qty[i] = -2; |
450 | else | |
451 | reg_qty[i] = -1; | |
452 | } | |
453 | ||
454 | /* Force loop below to initialize entire quantity array. */ | |
455 | next_qty = max_qty; | |
456 | ||
457 | /* Allocate each block's local registers, block by block. */ | |
458 | ||
459 | for (b = 0; b < n_basic_blocks; b++) | |
460 | { | |
461 | /* NEXT_QTY indicates which elements of the `qty_...' | |
462 | vectors might need to be initialized because they were used | |
463 | for the previous block; it is set to the entire array before | |
464 | block 0. Initialize those, with explicit loop if there are few, | |
465 | else with bzero and bcopy. Do not initialize vectors that are | |
466 | explicit set by `alloc_qty'. */ | |
467 | ||
468 | if (next_qty < 6) | |
469 | { | |
470 | for (i = 0; i < next_qty; i++) | |
471 | { | |
472 | qty_scratch_rtx[i] = 0; | |
473 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); | |
474 | qty_phys_has_copy_sugg[i] = 0; | |
475 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); | |
476 | qty_phys_has_sugg[i] = 0; | |
477 | } | |
478 | } | |
479 | else | |
480 | { | |
481 | #define CLEAR(vector) \ | |
482 | bzero ((vector), (sizeof (*(vector))) * next_qty); | |
483 | ||
484 | CLEAR (qty_scratch_rtx); | |
485 | CLEAR (qty_phys_copy_sugg); | |
486 | CLEAR (qty_phys_has_copy_sugg); | |
487 | CLEAR (qty_phys_sugg); | |
488 | CLEAR (qty_phys_has_sugg); | |
489 | } | |
490 | ||
491 | next_qty = 0; | |
492 | ||
493 | block_alloc (b); | |
494 | #ifdef USE_C_ALLOCA | |
495 | alloca (0); | |
496 | #endif | |
497 | } | |
498 | } | |
499 | \f | |
500 | /* Depth of loops we are in while in update_equiv_regs. */ | |
501 | static int loop_depth; | |
502 | ||
503 | /* Used for communication between the following two functions: contains | |
504 | a MEM that we wish to ensure remains unchanged. */ | |
505 | static rtx equiv_mem; | |
506 | ||
507 | /* Set nonzero if EQUIV_MEM is modified. */ | |
508 | static int equiv_mem_modified; | |
509 | ||
510 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
511 | Called via note_stores. */ | |
512 | ||
513 | static void | |
514 | validate_equiv_mem_from_store (dest, set) | |
515 | rtx dest; | |
516 | rtx set; | |
517 | { | |
518 | if ((GET_CODE (dest) == REG | |
519 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
520 | || (GET_CODE (dest) == MEM | |
521 | && true_dependence (dest, equiv_mem))) | |
522 | equiv_mem_modified = 1; | |
523 | } | |
524 | ||
525 | /* Verify that no store between START and the death of REG invalidates | |
526 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
527 | by storing into an overlapping memory location, or with a non-const | |
528 | CALL_INSN. | |
529 | ||
530 | Return 1 if MEMREF remains valid. */ | |
531 | ||
532 | static int | |
533 | validate_equiv_mem (start, reg, memref) | |
534 | rtx start; | |
535 | rtx reg; | |
536 | rtx memref; | |
537 | { | |
538 | rtx insn; | |
539 | rtx note; | |
540 | ||
541 | equiv_mem = memref; | |
542 | equiv_mem_modified = 0; | |
543 | ||
544 | /* If the memory reference has side effects or is volatile, it isn't a | |
545 | valid equivalence. */ | |
546 | if (side_effects_p (memref)) | |
547 | return 0; | |
548 | ||
549 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
550 | { | |
551 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
552 | continue; | |
553 | ||
554 | if (find_reg_note (insn, REG_DEAD, reg)) | |
555 | return 1; | |
556 | ||
557 | if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) | |
558 | && ! CONST_CALL_P (insn)) | |
559 | return 0; | |
560 | ||
561 | note_stores (PATTERN (insn), validate_equiv_mem_from_store); | |
562 | ||
563 | /* If a register mentioned in MEMREF is modified via an | |
564 | auto-increment, we lose the equivalence. Do the same if one | |
565 | dies; although we could extend the life, it doesn't seem worth | |
566 | the trouble. */ | |
567 | ||
568 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
569 | if ((REG_NOTE_KIND (note) == REG_INC | |
570 | || REG_NOTE_KIND (note) == REG_DEAD) | |
571 | && GET_CODE (XEXP (note, 0)) == REG | |
572 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
573 | return 0; | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | \f | |
579 | /* TRUE if X references a memory location that would be affected by a store | |
580 | to MEMREF. */ | |
581 | ||
582 | static int | |
583 | memref_referenced_p (memref, x) | |
584 | rtx x; | |
585 | rtx memref; | |
586 | { | |
587 | int i, j; | |
588 | char *fmt; | |
589 | enum rtx_code code = GET_CODE (x); | |
590 | ||
591 | switch (code) | |
592 | { | |
593 | case REG: | |
594 | case CONST_INT: | |
595 | case CONST: | |
596 | case LABEL_REF: | |
597 | case SYMBOL_REF: | |
598 | case CONST_DOUBLE: | |
599 | case PC: | |
600 | case CC0: | |
601 | case HIGH: | |
602 | case LO_SUM: | |
603 | return 0; | |
604 | ||
605 | case MEM: | |
606 | if (true_dependence (memref, x)) | |
607 | return 1; | |
608 | break; | |
609 | ||
610 | case SET: | |
611 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
612 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
613 | if (GET_CODE (SET_DEST (x)) == MEM) | |
614 | { | |
615 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
616 | return 1; | |
617 | } | |
618 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
619 | return 1; | |
620 | ||
621 | return memref_referenced_p (memref, SET_SRC (x)); | |
622 | } | |
623 | ||
624 | fmt = GET_RTX_FORMAT (code); | |
625 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
626 | switch (fmt[i]) | |
627 | { | |
628 | case 'e': | |
629 | if (memref_referenced_p (memref, XEXP (x, i))) | |
630 | return 1; | |
631 | break; | |
632 | case 'E': | |
633 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
634 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
635 | return 1; | |
636 | break; | |
637 | } | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
642 | /* TRUE if some insn in the range (START, END] references a memory location | |
643 | that would be affected by a store to MEMREF. */ | |
644 | ||
645 | static int | |
646 | memref_used_between_p (memref, start, end) | |
647 | rtx memref; | |
648 | rtx start; | |
649 | rtx end; | |
650 | { | |
651 | rtx insn; | |
652 | ||
653 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
654 | insn = NEXT_INSN (insn)) | |
655 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
656 | && memref_referenced_p (memref, PATTERN (insn))) | |
657 | return 1; | |
658 | ||
659 | return 0; | |
660 | } | |
661 | \f | |
662 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die | |
663 | in INSN. | |
664 | ||
665 | Search forward to see if SRC dies before either it or DEST is modified, | |
666 | but don't scan past the end of a basic block. If so, we can replace SRC | |
667 | with DEST and let SRC die in INSN. | |
668 | ||
669 | This will reduce the number of registers live in that range and may enable | |
670 | DEST to be tied to SRC, thus often saving one register in addition to a | |
671 | register-register copy. */ | |
672 | ||
673 | static void | |
d45cf215 | 674 | optimize_reg_copy_1 (insn, dest, src) |
2bbd3819 RS |
675 | rtx insn; |
676 | rtx dest; | |
677 | rtx src; | |
678 | { | |
679 | rtx p, q; | |
680 | rtx note; | |
681 | rtx dest_death = 0; | |
682 | int sregno = REGNO (src); | |
683 | int dregno = REGNO (dest); | |
684 | ||
685 | if (sregno == dregno | |
686 | #ifdef SMALL_REGISTER_CLASSES | |
687 | /* We don't want to mess with hard regs if register classes are small. */ | |
688 | || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER | |
689 | #endif | |
690 | /* We don't see all updates to SP if they are in an auto-inc memory | |
691 | reference, so we must disallow this optimization on them. */ | |
692 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) | |
693 | return; | |
694 | ||
695 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
696 | { | |
697 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN | |
698 | || (GET_CODE (p) == NOTE | |
699 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
700 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
701 | break; | |
702 | ||
703 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
704 | continue; | |
705 | ||
706 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
707 | /* Don't change a USE of a register. */ | |
708 | || (GET_CODE (PATTERN (p)) == USE | |
709 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
710 | break; | |
711 | ||
d9983d6c RK |
712 | /* See if all of SRC dies in P. This test is slightly more |
713 | conservative than it needs to be. */ | |
714 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 | |
715 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
2bbd3819 RS |
716 | { |
717 | int failed = 0; | |
718 | int length = 0; | |
d9983d6c | 719 | int d_length = 0; |
2bbd3819 | 720 | int n_calls = 0; |
d9983d6c | 721 | int d_n_calls = 0; |
2bbd3819 RS |
722 | |
723 | /* We can do the optimization. Scan forward from INSN again, | |
724 | replacing regs as we go. Set FAILED if a replacement can't | |
725 | be done. In that case, we can't move the death note for SRC. | |
726 | This should be rare. */ | |
727 | ||
728 | /* Set to stop at next insn. */ | |
729 | for (q = next_real_insn (insn); | |
730 | q != next_real_insn (p); | |
731 | q = next_real_insn (q)) | |
732 | { | |
d9983d6c | 733 | if (reg_overlap_mentioned_p (src, PATTERN (q))) |
2bbd3819 | 734 | { |
d9983d6c RK |
735 | /* If SRC is a hard register, we might miss some |
736 | overlapping registers with validate_replace_rtx, | |
737 | so we would have to undo it. We can't if DEST is | |
738 | present in the insn, so fail in that combination | |
739 | of cases. */ | |
740 | if (sregno < FIRST_PSEUDO_REGISTER | |
741 | && reg_mentioned_p (dest, PATTERN (q))) | |
742 | failed = 1; | |
743 | ||
744 | /* Replace all uses and make sure that the register | |
745 | isn't still present. */ | |
746 | else if (validate_replace_rtx (src, dest, q) | |
747 | && (sregno >= FIRST_PSEUDO_REGISTER | |
748 | || ! reg_overlap_mentioned_p (src, | |
749 | PATTERN (q)))) | |
2bbd3819 RS |
750 | { |
751 | /* We assume that a register is used exactly once per | |
752 | insn in the updates below. If this is not correct, | |
753 | no great harm is done. */ | |
754 | if (sregno >= FIRST_PSEUDO_REGISTER) | |
755 | reg_n_refs[sregno] -= loop_depth; | |
756 | if (dregno >= FIRST_PSEUDO_REGISTER) | |
757 | reg_n_refs[dregno] += loop_depth; | |
758 | } | |
759 | else | |
d9983d6c RK |
760 | { |
761 | validate_replace_rtx (dest, src, q); | |
762 | failed = 1; | |
763 | } | |
2bbd3819 RS |
764 | } |
765 | ||
766 | /* Count the insns and CALL_INSNs passed. If we passed the | |
767 | death note of DEST, show increased live length. */ | |
768 | length++; | |
769 | if (dest_death) | |
d9983d6c | 770 | d_length++; |
2bbd3819 RS |
771 | |
772 | if (GET_CODE (q) == CALL_INSN) | |
773 | { | |
774 | n_calls++; | |
775 | if (dest_death) | |
d9983d6c | 776 | d_n_calls++; |
2bbd3819 RS |
777 | } |
778 | ||
779 | /* If DEST dies here, remove the death note and save it for | |
d9983d6c RK |
780 | later. Make sure ALL of DEST dies here; again, this is |
781 | overly conservative. */ | |
2bbd3819 | 782 | if (dest_death == 0 |
d9983d6c RK |
783 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0 |
784 | && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) | |
2bbd3819 RS |
785 | remove_note (q, dest_death); |
786 | } | |
787 | ||
788 | if (! failed) | |
789 | { | |
790 | if (sregno >= FIRST_PSEUDO_REGISTER) | |
791 | { | |
792 | reg_live_length[sregno] -= length; | |
793 | reg_n_calls_crossed[sregno] -= n_calls; | |
794 | } | |
795 | ||
d9983d6c RK |
796 | if (dregno >= FIRST_PSEUDO_REGISTER) |
797 | { | |
798 | reg_live_length[dregno] += d_length; | |
799 | reg_n_calls_crossed[dregno] += d_n_calls; | |
800 | } | |
801 | ||
2bbd3819 RS |
802 | /* Move death note of SRC from P to INSN. */ |
803 | remove_note (p, note); | |
804 | XEXP (note, 1) = REG_NOTES (insn); | |
805 | REG_NOTES (insn) = note; | |
806 | } | |
807 | ||
808 | /* Put death note of DEST on P if we saw it die. */ | |
809 | if (dest_death) | |
810 | { | |
811 | XEXP (dest_death, 1) = REG_NOTES (p); | |
812 | REG_NOTES (p) = dest_death; | |
813 | } | |
814 | ||
815 | return; | |
816 | } | |
d9983d6c RK |
817 | |
818 | /* If SRC is a hard register which is set or killed in some other | |
819 | way, we can't do this optimization. */ | |
820 | else if (sregno < FIRST_PSEUDO_REGISTER | |
821 | && dead_or_set_p (p, src)) | |
822 | break; | |
2bbd3819 RS |
823 | } |
824 | } | |
d45cf215 RS |
825 | \f |
826 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have | |
827 | a sequence of insns that modify DEST followed by an insn that sets | |
828 | SRC to DEST in which DEST dies, with no prior modification of DEST. | |
829 | (There is no need to check if the insns in between actually modify | |
830 | DEST. We should not have cases where DEST is not modified, but | |
831 | the optimization is safe if no such modification is detected.) | |
832 | In that case, we can replace all uses of DEST, starting with INSN and | |
833 | ending with the set of SRC to DEST, with SRC. We do not do this | |
834 | optimization if a CALL_INSN is crossed unless SRC already crosses a | |
835 | call. | |
836 | ||
837 | It is assumed that DEST and SRC are pseudos; it is too complicated to do | |
838 | this for hard registers since the substitutions we may make might fail. */ | |
839 | ||
840 | static void | |
841 | optimize_reg_copy_2 (insn, dest, src) | |
842 | rtx insn; | |
843 | rtx dest; | |
844 | rtx src; | |
845 | { | |
846 | rtx p, q; | |
847 | rtx set; | |
848 | int sregno = REGNO (src); | |
849 | int dregno = REGNO (dest); | |
850 | ||
851 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
852 | { | |
853 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN | |
854 | || (GET_CODE (p) == NOTE | |
855 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG | |
856 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) | |
857 | break; | |
858 | ||
859 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') | |
860 | continue; | |
861 | ||
862 | set = single_set (p); | |
863 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src | |
864 | && find_reg_note (p, REG_DEAD, dest)) | |
865 | { | |
866 | /* We can do the optimization. Scan forward from INSN again, | |
867 | replacing regs as we go. */ | |
868 | ||
869 | /* Set to stop at next insn. */ | |
870 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) | |
871 | if (GET_RTX_CLASS (GET_CODE (q)) == 'i') | |
872 | { | |
873 | if (reg_mentioned_p (dest, PATTERN (q))) | |
874 | { | |
875 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); | |
876 | ||
877 | /* We assume that a register is used exactly once per | |
878 | insn in the updates below. If this is not correct, | |
879 | no great harm is done. */ | |
6102fe95 JW |
880 | reg_n_refs[dregno] -= loop_depth; |
881 | reg_n_refs[sregno] += loop_depth; | |
d45cf215 RS |
882 | } |
883 | ||
884 | ||
885 | if (GET_CODE (q) == CALL_INSN) | |
886 | { | |
887 | reg_n_calls_crossed[dregno]--; | |
888 | reg_n_calls_crossed[sregno]++; | |
889 | } | |
890 | } | |
891 | ||
892 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); | |
893 | reg_n_deaths[dregno]--; | |
894 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); | |
895 | reg_n_deaths[sregno]--; | |
896 | return; | |
897 | } | |
898 | ||
899 | if (reg_set_p (src, p) | |
900 | || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0)) | |
901 | break; | |
902 | } | |
903 | } | |
2bbd3819 RS |
904 | \f |
905 | /* Find registers that are equivalent to a single value throughout the | |
906 | compilation (either because they can be referenced in memory or are set once | |
907 | from a single constant). Lower their priority for a register. | |
908 | ||
909 | If such a register is only referenced once, try substituting its value | |
910 | into the using insn. If it succeeds, we can eliminate the register | |
911 | completely. */ | |
912 | ||
913 | static void | |
914 | update_equiv_regs () | |
915 | { | |
916 | rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *)); | |
917 | rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *)); | |
918 | rtx insn; | |
919 | ||
920 | bzero (reg_equiv_init_insn, max_regno * sizeof (rtx *)); | |
921 | bzero (reg_equiv_replacement, max_regno * sizeof (rtx *)); | |
922 | ||
923 | init_alias_analysis (); | |
924 | ||
925 | loop_depth = 1; | |
926 | ||
927 | /* Scan the insns and find which registers have equivalences. Do this | |
928 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
929 | a register can be set below its use. */ | |
930 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
931 | { | |
932 | rtx note; | |
933 | rtx set = single_set (insn); | |
934 | rtx dest; | |
935 | int regno; | |
936 | ||
937 | if (GET_CODE (insn) == NOTE) | |
938 | { | |
939 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
940 | loop_depth++; | |
941 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
942 | loop_depth--; | |
943 | } | |
944 | ||
945 | /* If this insn contains more (or less) than a single SET, ignore it. */ | |
946 | if (set == 0) | |
947 | continue; | |
948 | ||
949 | dest = SET_DEST (set); | |
950 | ||
951 | /* If this sets a MEM to the contents of a REG that is only used | |
952 | in a single basic block, see if the register is always equivalent | |
953 | to that memory location and if moving the store from INSN to the | |
954 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
955 | initializing insn. */ | |
956 | ||
957 | if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG | |
958 | && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER | |
959 | && reg_basic_block[regno] >= 0 | |
960 | && reg_equiv_init_insn[regno] != 0 | |
961 | && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set), | |
962 | dest) | |
963 | && ! memref_used_between_p (SET_DEST (set), | |
964 | reg_equiv_init_insn[regno], insn)) | |
965 | REG_NOTES (reg_equiv_init_insn[regno]) | |
966 | = gen_rtx (EXPR_LIST, REG_EQUIV, dest, | |
967 | REG_NOTES (reg_equiv_init_insn[regno])); | |
968 | ||
969 | /* If this is a register-register copy where SRC is not dead, see if we | |
970 | can optimize it. */ | |
971 | if (flag_expensive_optimizations && GET_CODE (dest) == REG | |
972 | && GET_CODE (SET_SRC (set)) == REG | |
973 | && ! find_reg_note (insn, REG_DEAD, SET_SRC (set))) | |
d45cf215 RS |
974 | optimize_reg_copy_1 (insn, dest, SET_SRC (set)); |
975 | ||
976 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ | |
977 | else if (flag_expensive_optimizations && GET_CODE (dest) == REG | |
978 | && REGNO (dest) >= FIRST_PSEUDO_REGISTER | |
979 | && GET_CODE (SET_SRC (set)) == REG | |
980 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER | |
981 | && find_reg_note (insn, REG_DEAD, SET_SRC (set))) | |
982 | optimize_reg_copy_2 (insn, dest, SET_SRC (set)); | |
2bbd3819 RS |
983 | |
984 | /* Otherwise, we only handle the case of a pseudo register being set | |
985 | once. */ | |
986 | if (GET_CODE (dest) != REG | |
987 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
988 | || reg_n_sets[regno] != 1) | |
989 | continue; | |
990 | ||
b1ec3c92 | 991 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
2bbd3819 RS |
992 | |
993 | /* Record this insn as initializing this register. */ | |
994 | reg_equiv_init_insn[regno] = insn; | |
995 | ||
996 | /* If this register is known to be equal to a constant, record that | |
997 | it is always equivalent to the constant. */ | |
998 | if (note && CONSTANT_P (XEXP (note, 0))) | |
999 | PUT_MODE (note, (enum machine_mode) REG_EQUIV); | |
1000 | ||
1001 | /* If this insn introduces a "constant" register, decrease the priority | |
1002 | of that register. Record this insn if the register is only used once | |
1003 | more and the equivalence value is the same as our source. | |
1004 | ||
1005 | The latter condition is checked for two reasons: First, it is an | |
1006 | indication that it may be more efficient to actually emit the insn | |
1007 | as written (if no registers are available, reload will substitute | |
1008 | the equivalence). Secondly, it avoids problems with any registers | |
1009 | dying in this insn whose death notes would be missed. | |
1010 | ||
1011 | If we don't have a REG_EQUIV note, see if this insn is loading | |
1012 | a register used only in one basic block from a MEM. If so, and the | |
1013 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
1014 | note. */ | |
1015 | ||
b1ec3c92 | 1016 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
2bbd3819 RS |
1017 | |
1018 | if (note == 0 && reg_basic_block[regno] >= 0 | |
1019 | && GET_CODE (SET_SRC (set)) == MEM | |
1020 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
1021 | REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set), | |
1022 | REG_NOTES (insn)); | |
1023 | ||
1024 | /* Don't mess with things live during setjmp. */ | |
1025 | if (note && reg_live_length[regno] >= 0) | |
1026 | { | |
1027 | int regno = REGNO (dest); | |
1028 | ||
1029 | /* Note that the statement below does not affect the priority | |
1030 | in local-alloc! */ | |
1031 | reg_live_length[regno] *= 2; | |
1032 | ||
1033 | /* If the register is referenced exactly twice, meaning it is set | |
1034 | once and used once, indicate that the reference may be replaced | |
1035 | by the equivalence we computed above. If the register is only | |
1036 | used in one basic block, this can't succeed or combine would | |
1037 | have done it. | |
1038 | ||
1039 | It would be nice to use "loop_depth * 2" in the compare | |
1040 | below. Unfortunately, LOOP_DEPTH need not be constant within | |
1041 | a basic block so this would be too complicated. | |
1042 | ||
1043 | This case normally occurs when a parameter is read from memory | |
1044 | and then used exactly once, not in a loop. */ | |
1045 | ||
1046 | if (reg_n_refs[regno] == 2 | |
1047 | && reg_basic_block[regno] < 0 | |
1048 | && rtx_equal_p (XEXP (note, 0), SET_SRC (set))) | |
1049 | reg_equiv_replacement[regno] = SET_SRC (set); | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | /* Now scan all regs killed in an insn to see if any of them are registers | |
1054 | only used that once. If so, see if we can replace the reference with | |
1055 | the equivalent from. If we can, delete the initializing reference | |
1056 | and this register will go away. */ | |
1057 | for (insn = next_active_insn (get_insns ()); | |
1058 | insn; | |
1059 | insn = next_active_insn (insn)) | |
1060 | { | |
1061 | rtx link; | |
1062 | ||
1063 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1064 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1065 | /* Make sure this insn still refers to the register. */ | |
1066 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
1067 | { | |
1068 | int regno = REGNO (XEXP (link, 0)); | |
1069 | ||
1070 | if (reg_equiv_replacement[regno] | |
1071 | && validate_replace_rtx (regno_reg_rtx[regno], | |
1072 | reg_equiv_replacement[regno], insn)) | |
1073 | { | |
1074 | rtx equiv_insn = reg_equiv_init_insn[regno]; | |
1075 | ||
1076 | remove_death (regno, insn); | |
1077 | reg_n_refs[regno] = 0; | |
1078 | PUT_CODE (equiv_insn, NOTE); | |
1079 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1080 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1081 | } | |
1082 | } | |
1083 | } | |
1084 | } | |
1085 | \f | |
1086 | /* Allocate hard regs to the pseudo regs used only within block number B. | |
1087 | Only the pseudos that die but once can be handled. */ | |
1088 | ||
1089 | static void | |
1090 | block_alloc (b) | |
1091 | int b; | |
1092 | { | |
1093 | register int i, q; | |
1094 | register rtx insn; | |
1095 | rtx note; | |
1096 | int insn_number = 0; | |
1097 | int insn_count = 0; | |
1098 | int max_uid = get_max_uid (); | |
aabf56ce | 1099 | int *qty_order; |
2bbd3819 RS |
1100 | int no_conflict_combined_regno = -1; |
1101 | ||
1102 | /* Count the instructions in the basic block. */ | |
1103 | ||
1104 | insn = basic_block_end[b]; | |
1105 | while (1) | |
1106 | { | |
1107 | if (GET_CODE (insn) != NOTE) | |
1108 | if (++insn_count > max_uid) | |
1109 | abort (); | |
1110 | if (insn == basic_block_head[b]) | |
1111 | break; | |
1112 | insn = PREV_INSN (insn); | |
1113 | } | |
1114 | ||
1115 | /* +2 to leave room for a post_mark_life at the last insn and for | |
1116 | the birth of a CLOBBER in the first insn. */ | |
1117 | regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2) | |
1118 | * sizeof (HARD_REG_SET)); | |
1119 | bzero (regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET)); | |
1120 | ||
1121 | /* Initialize table of hardware registers currently live. */ | |
1122 | ||
1123 | #ifdef HARD_REG_SET | |
1124 | regs_live = *basic_block_live_at_start[b]; | |
1125 | #else | |
1126 | COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]); | |
1127 | #endif | |
1128 | ||
1129 | /* This loop scans the instructions of the basic block | |
1130 | and assigns quantities to registers. | |
1131 | It computes which registers to tie. */ | |
1132 | ||
1133 | insn = basic_block_head[b]; | |
1134 | while (1) | |
1135 | { | |
1136 | register rtx body = PATTERN (insn); | |
1137 | ||
1138 | if (GET_CODE (insn) != NOTE) | |
1139 | insn_number++; | |
1140 | ||
1141 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1142 | { | |
1143 | register rtx link, set; | |
1144 | register int win = 0; | |
1145 | register rtx r0, r1; | |
1146 | int combined_regno = -1; | |
1147 | int i; | |
1148 | int insn_code_number = recog_memoized (insn); | |
1149 | ||
1150 | this_insn_number = insn_number; | |
1151 | this_insn = insn; | |
1152 | ||
1153 | if (insn_code_number >= 0) | |
1154 | insn_extract (insn); | |
1155 | which_alternative = -1; | |
1156 | ||
1157 | /* Is this insn suitable for tying two registers? | |
1158 | If so, try doing that. | |
1159 | Suitable insns are those with at least two operands and where | |
1160 | operand 0 is an output that is a register that is not | |
1161 | earlyclobber. | |
7aba0f0b RK |
1162 | |
1163 | We can tie operand 0 with some operand that dies in this insn. | |
1164 | First look for operands that are required to be in the same | |
1165 | register as operand 0. If we find such, only try tying that | |
1166 | operand or one that can be put into that operand if the | |
1167 | operation is commutative. If we don't find an operand | |
1168 | that is required to be in the same register as operand 0, | |
1169 | we can tie with any operand. | |
1170 | ||
2bbd3819 RS |
1171 | Subregs in place of regs are also ok. |
1172 | ||
1173 | If tying is done, WIN is set nonzero. */ | |
1174 | ||
1175 | if (insn_code_number >= 0 | |
7fe4336e | 1176 | #ifdef REGISTER_CONSTRAINTS |
2bbd3819 RS |
1177 | && insn_n_operands[insn_code_number] > 1 |
1178 | && insn_operand_constraint[insn_code_number][0][0] == '=' | |
7fe4336e RK |
1179 | && insn_operand_constraint[insn_code_number][0][1] != '&' |
1180 | #else | |
1181 | && GET_CODE (PATTERN (insn)) == SET | |
1182 | && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0]) | |
1183 | #endif | |
1184 | ) | |
2bbd3819 | 1185 | { |
7fe4336e | 1186 | #ifdef REGISTER_CONSTRAINTS |
7aba0f0b RK |
1187 | int must_match_0 = -1; |
1188 | ||
1189 | ||
1190 | for (i = 1; i < insn_n_operands[insn_code_number]; i++) | |
1191 | if (requires_inout_p | |
1192 | (insn_operand_constraint[insn_code_number][i])) | |
1193 | must_match_0 = i; | |
7fe4336e | 1194 | #endif |
2bbd3819 | 1195 | |
7aba0f0b RK |
1196 | r0 = recog_operand[0]; |
1197 | for (i = 1; i < insn_n_operands[insn_code_number]; i++) | |
2bbd3819 | 1198 | { |
7fe4336e | 1199 | #ifdef REGISTER_CONSTRAINTS |
7aba0f0b RK |
1200 | /* Skip this operand if we found an operand that |
1201 | must match operand 0 and this operand isn't it | |
1202 | and can't be made to be it by commutativity. */ | |
1203 | ||
1204 | if (must_match_0 >= 0 && i != must_match_0 | |
1205 | && ! (i == must_match_0 + 1 | |
1206 | && insn_operand_constraint[insn_code_number][i-1][0] == '%') | |
1207 | && ! (i == must_match_0 - 1 | |
1208 | && insn_operand_constraint[insn_code_number][i][0] == '%')) | |
1209 | continue; | |
7fe4336e | 1210 | #endif |
2bbd3819 | 1211 | |
7aba0f0b | 1212 | r1 = recog_operand[i]; |
2bbd3819 | 1213 | |
7aba0f0b RK |
1214 | /* If the operand is an address, find a register in it. |
1215 | There may be more than one register, but we only try one | |
1216 | of them. */ | |
1217 | if ( | |
7fe4336e | 1218 | #ifdef REGISTER_CONSTRAINTS |
7aba0f0b | 1219 | insn_operand_constraint[insn_code_number][i][0] == 'p' |
7fe4336e | 1220 | #else |
7aba0f0b | 1221 | insn_operand_address_p[insn_code_number][i] |
7fe4336e | 1222 | #endif |
7aba0f0b RK |
1223 | ) |
1224 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) | |
1225 | r1 = XEXP (r1, 0); | |
1226 | ||
1227 | if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) | |
1228 | { | |
1229 | /* We have two priorities for hard register preferences. | |
1230 | If we have a move insn or an insn whose first input | |
1231 | can only be in the same register as the output, give | |
1232 | priority to an equivalence found from that insn. */ | |
1233 | int may_save_copy | |
1234 | = ((SET_DEST (body) == r0 && SET_SRC (body) == r1) | |
1235 | #ifdef REGISTER_CONSTRAINTS | |
1236 | || (r1 == recog_operand[i] && must_match_0 >= 0) | |
1237 | #endif | |
1238 | ); | |
1239 | ||
1240 | if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) | |
1241 | win = combine_regs (r1, r0, may_save_copy, | |
1242 | insn_number, insn, 0); | |
1243 | } | |
2bbd3819 RS |
1244 | } |
1245 | } | |
1246 | ||
1247 | /* Recognize an insn sequence with an ultimate result | |
1248 | which can safely overlap one of the inputs. | |
1249 | The sequence begins with a CLOBBER of its result, | |
1250 | and ends with an insn that copies the result to itself | |
1251 | and has a REG_EQUAL note for an equivalent formula. | |
1252 | That note indicates what the inputs are. | |
1253 | The result and the input can overlap if each insn in | |
1254 | the sequence either doesn't mention the input | |
1255 | or has a REG_NO_CONFLICT note to inhibit the conflict. | |
1256 | ||
1257 | We do the combining test at the CLOBBER so that the | |
1258 | destination register won't have had a quantity number | |
1259 | assigned, since that would prevent combining. */ | |
1260 | ||
1261 | if (GET_CODE (PATTERN (insn)) == CLOBBER | |
1262 | && (r0 = XEXP (PATTERN (insn), 0), | |
1263 | GET_CODE (r0) == REG) | |
b1ec3c92 | 1264 | && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 |
a6665f8c | 1265 | && XEXP (link, 0) != 0 |
2bbd3819 RS |
1266 | && GET_CODE (XEXP (link, 0)) == INSN |
1267 | && (set = single_set (XEXP (link, 0))) != 0 | |
1268 | && SET_DEST (set) == r0 && SET_SRC (set) == r0 | |
b1ec3c92 CH |
1269 | && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, |
1270 | NULL_RTX)) != 0) | |
2bbd3819 RS |
1271 | { |
1272 | if (r1 = XEXP (note, 0), GET_CODE (r1) == REG | |
1273 | /* Check that we have such a sequence. */ | |
1274 | && no_conflict_p (insn, r0, r1)) | |
1275 | win = combine_regs (r1, r0, 1, insn_number, insn, 1); | |
1276 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' | |
1277 | && (r1 = XEXP (XEXP (note, 0), 0), | |
1278 | GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) | |
1279 | && no_conflict_p (insn, r0, r1)) | |
1280 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1281 | ||
1282 | /* Here we care if the operation to be computed is | |
1283 | commutative. */ | |
1284 | else if ((GET_CODE (XEXP (note, 0)) == EQ | |
1285 | || GET_CODE (XEXP (note, 0)) == NE | |
1286 | || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') | |
1287 | && (r1 = XEXP (XEXP (note, 0), 1), | |
1288 | (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) | |
1289 | && no_conflict_p (insn, r0, r1)) | |
1290 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1291 | ||
1292 | /* If we did combine something, show the register number | |
1293 | in question so that we know to ignore its death. */ | |
1294 | if (win) | |
1295 | no_conflict_combined_regno = REGNO (r1); | |
1296 | } | |
1297 | ||
1298 | /* If registers were just tied, set COMBINED_REGNO | |
1299 | to the number of the register used in this insn | |
1300 | that was tied to the register set in this insn. | |
1301 | This register's qty should not be "killed". */ | |
1302 | ||
1303 | if (win) | |
1304 | { | |
1305 | while (GET_CODE (r1) == SUBREG) | |
1306 | r1 = SUBREG_REG (r1); | |
1307 | combined_regno = REGNO (r1); | |
1308 | } | |
1309 | ||
1310 | /* Mark the death of everything that dies in this instruction, | |
1311 | except for anything that was just combined. */ | |
1312 | ||
1313 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1314 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1315 | && GET_CODE (XEXP (link, 0)) == REG | |
1316 | && combined_regno != REGNO (XEXP (link, 0)) | |
1317 | && (no_conflict_combined_regno != REGNO (XEXP (link, 0)) | |
1318 | || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0)))) | |
1319 | wipe_dead_reg (XEXP (link, 0), 0); | |
1320 | ||
1321 | /* Allocate qty numbers for all registers local to this block | |
1322 | that are born (set) in this instruction. | |
1323 | A pseudo that already has a qty is not changed. */ | |
1324 | ||
1325 | note_stores (PATTERN (insn), reg_is_set); | |
1326 | ||
1327 | /* If anything is set in this insn and then unused, mark it as dying | |
1328 | after this insn, so it will conflict with our outputs. This | |
1329 | can't match with something that combined, and it doesn't matter | |
1330 | if it did. Do this after the calls to reg_is_set since these | |
1331 | die after, not during, the current insn. */ | |
1332 | ||
1333 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1334 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
1335 | && GET_CODE (XEXP (link, 0)) == REG) | |
1336 | wipe_dead_reg (XEXP (link, 0), 1); | |
1337 | ||
1338 | #ifndef SMALL_REGISTER_CLASSES | |
1339 | /* Allocate quantities for any SCRATCH operands of this insn. We | |
1340 | don't do this for machines with small register classes because | |
1341 | those machines can use registers explicitly mentioned in the | |
1342 | RTL as spill registers and our usage of hard registers | |
1343 | explicitly for SCRATCH operands will conflict. On those machines, | |
1344 | reload will allocate the SCRATCH. */ | |
1345 | ||
1346 | if (insn_code_number >= 0) | |
1347 | for (i = 0; i < insn_n_operands[insn_code_number]; i++) | |
bd5f197a RK |
1348 | if (GET_CODE (recog_operand[i]) == SCRATCH |
1349 | && scratch_index < scratch_list_length - 1) | |
2bbd3819 RS |
1350 | alloc_qty_for_scratch (recog_operand[i], i, insn, |
1351 | insn_code_number, insn_number); | |
1352 | #endif | |
1353 | ||
1354 | /* If this is an insn that has a REG_RETVAL note pointing at a | |
1355 | CLOBBER insn, we have reached the end of a REG_NO_CONFLICT | |
1356 | block, so clear any register number that combined within it. */ | |
b1ec3c92 | 1357 | if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 |
2bbd3819 RS |
1358 | && GET_CODE (XEXP (note, 0)) == INSN |
1359 | && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) | |
1360 | no_conflict_combined_regno = -1; | |
1361 | } | |
1362 | ||
1363 | /* Set the registers live after INSN_NUMBER. Note that we never | |
1364 | record the registers live before the block's first insn, since no | |
1365 | pseudos we care about are live before that insn. */ | |
1366 | ||
1367 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); | |
1368 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); | |
1369 | ||
1370 | if (insn == basic_block_end[b]) | |
1371 | break; | |
1372 | ||
1373 | insn = NEXT_INSN (insn); | |
1374 | } | |
1375 | ||
1376 | /* Now every register that is local to this basic block | |
1377 | should have been given a quantity, or else -1 meaning ignore it. | |
1378 | Every quantity should have a known birth and death. | |
1379 | ||
1380 | Order the qtys so we assign them registers in order of | |
1381 | decreasing length of life. Normally call qsort, but if we | |
1382 | have only a very small number of quantities, sort them ourselves. */ | |
1383 | ||
aabf56ce | 1384 | qty_order = (int *) alloca (next_qty * sizeof (int)); |
2bbd3819 RS |
1385 | for (i = 0; i < next_qty; i++) |
1386 | qty_order[i] = i; | |
1387 | ||
1388 | #define EXCHANGE(I1, I2) \ | |
1389 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1390 | ||
1391 | switch (next_qty) | |
1392 | { | |
1393 | case 3: | |
1394 | /* Make qty_order[2] be the one to allocate last. */ | |
1395 | if (qty_compare (0, 1) > 0) | |
1396 | EXCHANGE (0, 1); | |
1397 | if (qty_compare (1, 2) > 0) | |
1398 | EXCHANGE (2, 1); | |
1399 | ||
1400 | /* ... Fall through ... */ | |
1401 | case 2: | |
1402 | /* Put the best one to allocate in qty_order[0]. */ | |
1403 | if (qty_compare (0, 1) > 0) | |
1404 | EXCHANGE (0, 1); | |
1405 | ||
1406 | /* ... Fall through ... */ | |
1407 | ||
1408 | case 1: | |
1409 | case 0: | |
1410 | /* Nothing to do here. */ | |
1411 | break; | |
1412 | ||
1413 | default: | |
aabf56ce | 1414 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); |
2bbd3819 RS |
1415 | } |
1416 | ||
1417 | /* Try to put each quantity in a suggested physical register, if it has one. | |
1418 | This may cause registers to be allocated that otherwise wouldn't be, but | |
1419 | this seems acceptable in local allocation (unlike global allocation). */ | |
1420 | for (i = 0; i < next_qty; i++) | |
1421 | { | |
1422 | q = qty_order[i]; | |
1423 | if (qty_phys_has_sugg[q] || qty_phys_has_copy_sugg[q]) | |
1424 | qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q, | |
1425 | 0, 1, qty_birth[q], qty_death[q]); | |
1426 | else | |
1427 | qty_phys_reg[q] = -1; | |
1428 | } | |
1429 | ||
1430 | /* Now for each qty that is not a hardware register, | |
1431 | look for a hardware register to put it in. | |
1432 | First try the register class that is cheapest for this qty, | |
1433 | if there is more than one class. */ | |
1434 | ||
1435 | for (i = 0; i < next_qty; i++) | |
1436 | { | |
1437 | q = qty_order[i]; | |
1438 | if (qty_phys_reg[q] < 0) | |
1439 | { | |
1440 | if (N_REG_CLASSES > 1) | |
1441 | { | |
1442 | qty_phys_reg[q] = find_free_reg (qty_min_class[q], | |
1443 | qty_mode[q], q, 0, 0, | |
1444 | qty_birth[q], qty_death[q]); | |
1445 | if (qty_phys_reg[q] >= 0) | |
1446 | continue; | |
1447 | } | |
1448 | ||
e4600702 RK |
1449 | if (qty_alternate_class[q] != NO_REGS) |
1450 | qty_phys_reg[q] = find_free_reg (qty_alternate_class[q], | |
2bbd3819 RS |
1451 | qty_mode[q], q, 0, 0, |
1452 | qty_birth[q], qty_death[q]); | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | /* Now propagate the register assignments | |
1457 | to the pseudo regs belonging to the qtys. */ | |
1458 | ||
1459 | for (q = 0; q < next_qty; q++) | |
1460 | if (qty_phys_reg[q] >= 0) | |
1461 | { | |
1462 | for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i]) | |
1463 | reg_renumber[i] = qty_phys_reg[q] + reg_offset[i]; | |
1464 | if (qty_scratch_rtx[q]) | |
1465 | { | |
bd5f197a RK |
1466 | if (GET_CODE (qty_scratch_rtx[q]) == REG) |
1467 | abort (); | |
2bbd3819 RS |
1468 | PUT_CODE (qty_scratch_rtx[q], REG); |
1469 | REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q]; | |
1470 | ||
bd5f197a RK |
1471 | scratch_block[scratch_index] = b; |
1472 | scratch_list[scratch_index++] = qty_scratch_rtx[q]; | |
2bbd3819 RS |
1473 | |
1474 | /* Must clear the USED field, because it will have been set by | |
1475 | copy_rtx_if_shared, but the leaf_register code expects that | |
1476 | it is zero in all REG rtx. copy_rtx_if_shared does not set the | |
1477 | used bit for REGs, but does for SCRATCHes. */ | |
1478 | qty_scratch_rtx[q]->used = 0; | |
1479 | } | |
1480 | } | |
1481 | } | |
1482 | \f | |
1483 | /* Compare two quantities' priority for getting real registers. | |
1484 | We give shorter-lived quantities higher priority. | |
6dc42e49 RS |
1485 | Quantities with more references are also preferred, as are quantities that |
1486 | require multiple registers. This is the identical prioritization as | |
2bbd3819 RS |
1487 | done by global-alloc. |
1488 | ||
1489 | We used to give preference to registers with *longer* lives, but using | |
1490 | the same algorithm in both local- and global-alloc can speed up execution | |
1491 | of some programs by as much as a factor of three! */ | |
1492 | ||
1493 | static int | |
1494 | qty_compare (q1, q2) | |
1495 | int q1, q2; | |
1496 | { | |
1497 | /* Note that the quotient will never be bigger than | |
1498 | the value of floor_log2 times the maximum number of | |
1499 | times a register can occur in one insn (surely less than 100). | |
1500 | Multiplying this by 10000 can't overflow. */ | |
1501 | register int pri1 | |
1502 | = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1]) | |
1503 | / ((qty_death[q1] - qty_birth[q1]) * qty_size[q1])) | |
1504 | * 10000); | |
1505 | register int pri2 | |
1506 | = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2]) | |
1507 | / ((qty_death[q2] - qty_birth[q2]) * qty_size[q2])) | |
1508 | * 10000); | |
1509 | return pri2 - pri1; | |
1510 | } | |
1511 | ||
1512 | static int | |
1513 | qty_compare_1 (q1, q2) | |
aabf56ce | 1514 | int *q1, *q2; |
2bbd3819 RS |
1515 | { |
1516 | register int tem; | |
1517 | ||
1518 | /* Note that the quotient will never be bigger than | |
1519 | the value of floor_log2 times the maximum number of | |
1520 | times a register can occur in one insn (surely less than 100). | |
1521 | Multiplying this by 10000 can't overflow. */ | |
1522 | register int pri1 | |
1523 | = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]) | |
1524 | / ((qty_death[*q1] - qty_birth[*q1]) * qty_size[*q1])) | |
1525 | * 10000); | |
1526 | register int pri2 | |
1527 | = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]) | |
1528 | / ((qty_death[*q2] - qty_birth[*q2]) * qty_size[*q2])) | |
1529 | * 10000); | |
1530 | ||
1531 | tem = pri2 - pri1; | |
1532 | if (tem != 0) return tem; | |
1533 | /* If qtys are equally good, sort by qty number, | |
1534 | so that the results of qsort leave nothing to chance. */ | |
1535 | return *q1 - *q2; | |
1536 | } | |
1537 | \f | |
1538 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. | |
1539 | Returns 1 if have done so, or 0 if cannot. | |
1540 | ||
1541 | Combining registers means marking them as having the same quantity | |
1542 | and adjusting the offsets within the quantity if either of | |
1543 | them is a SUBREG). | |
1544 | ||
1545 | We don't actually combine a hard reg with a pseudo; instead | |
1546 | we just record the hard reg as the suggestion for the pseudo's quantity. | |
1547 | If we really combined them, we could lose if the pseudo lives | |
1548 | across an insn that clobbers the hard reg (eg, movstr). | |
1549 | ||
1550 | ALREADY_DEAD is non-zero if USEDREG is known to be dead even though | |
1551 | there is no REG_DEAD note on INSN. This occurs during the processing | |
1552 | of REG_NO_CONFLICT blocks. | |
1553 | ||
1554 | MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to | |
1555 | SETREG or if the input and output must share a register. | |
1556 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. | |
1557 | ||
1558 | There are elaborate checks for the validity of combining. */ | |
1559 | ||
1560 | ||
1561 | static int | |
1562 | combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) | |
1563 | rtx usedreg, setreg; | |
1564 | int may_save_copy; | |
1565 | int insn_number; | |
1566 | rtx insn; | |
1567 | int already_dead; | |
1568 | { | |
1569 | register int ureg, sreg; | |
1570 | register int offset = 0; | |
1571 | int usize, ssize; | |
1572 | register int sqty; | |
1573 | ||
1574 | /* Determine the numbers and sizes of registers being used. If a subreg | |
6dc42e49 | 1575 | is present that does not change the entire register, don't consider |
2bbd3819 RS |
1576 | this a copy insn. */ |
1577 | ||
1578 | while (GET_CODE (usedreg) == SUBREG) | |
1579 | { | |
1580 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) | |
1581 | may_save_copy = 0; | |
1582 | offset += SUBREG_WORD (usedreg); | |
1583 | usedreg = SUBREG_REG (usedreg); | |
1584 | } | |
1585 | if (GET_CODE (usedreg) != REG) | |
1586 | return 0; | |
1587 | ureg = REGNO (usedreg); | |
1588 | usize = REG_SIZE (usedreg); | |
1589 | ||
1590 | while (GET_CODE (setreg) == SUBREG) | |
1591 | { | |
1592 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) | |
1593 | may_save_copy = 0; | |
1594 | offset -= SUBREG_WORD (setreg); | |
1595 | setreg = SUBREG_REG (setreg); | |
1596 | } | |
1597 | if (GET_CODE (setreg) != REG) | |
1598 | return 0; | |
1599 | sreg = REGNO (setreg); | |
1600 | ssize = REG_SIZE (setreg); | |
1601 | ||
1602 | /* If UREG is a pseudo-register that hasn't already been assigned a | |
1603 | quantity number, it means that it is not local to this block or dies | |
1604 | more than once. In either event, we can't do anything with it. */ | |
1605 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) | |
1606 | /* Do not combine registers unless one fits within the other. */ | |
1607 | || (offset > 0 && usize + offset > ssize) | |
1608 | || (offset < 0 && usize + offset < ssize) | |
1609 | /* Do not combine with a smaller already-assigned object | |
1610 | if that smaller object is already combined with something bigger. */ | |
1611 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER | |
1612 | && usize < qty_size[reg_qty[ureg]]) | |
1613 | /* Can't combine if SREG is not a register we can allocate. */ | |
1614 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) | |
1615 | /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. | |
1616 | These have already been taken care of. This probably wouldn't | |
1617 | combine anyway, but don't take any chances. */ | |
1618 | || (ureg >= FIRST_PSEUDO_REGISTER | |
1619 | && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) | |
1620 | /* Don't tie something to itself. In most cases it would make no | |
1621 | difference, but it would screw up if the reg being tied to itself | |
1622 | also dies in this insn. */ | |
1623 | || ureg == sreg | |
1624 | /* Don't try to connect two different hardware registers. */ | |
1625 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) | |
1626 | /* Don't connect two different machine modes if they have different | |
1627 | implications as to which registers may be used. */ | |
1628 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) | |
1629 | return 0; | |
1630 | ||
1631 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in | |
1632 | qty_phys_sugg for the pseudo instead of tying them. | |
1633 | ||
1634 | Return "failure" so that the lifespan of UREG is terminated here; | |
1635 | that way the two lifespans will be disjoint and nothing will prevent | |
1636 | the pseudo reg from being given this hard reg. */ | |
1637 | ||
1638 | if (ureg < FIRST_PSEUDO_REGISTER) | |
1639 | { | |
1640 | /* Allocate a quantity number so we have a place to put our | |
1641 | suggestions. */ | |
1642 | if (reg_qty[sreg] == -2) | |
1643 | reg_is_born (setreg, 2 * insn_number); | |
1644 | ||
1645 | if (reg_qty[sreg] >= 0) | |
1646 | { | |
1647 | if (may_save_copy) | |
1648 | { | |
1649 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); | |
1650 | qty_phys_has_copy_sugg[reg_qty[sreg]] = 1; | |
1651 | } | |
1652 | else | |
1653 | { | |
1654 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); | |
1655 | qty_phys_has_sugg[reg_qty[sreg]] = 1; | |
1656 | } | |
1657 | } | |
1658 | return 0; | |
1659 | } | |
1660 | ||
1661 | /* Similarly for SREG a hard register and UREG a pseudo register. */ | |
1662 | ||
1663 | if (sreg < FIRST_PSEUDO_REGISTER) | |
1664 | { | |
1665 | if (may_save_copy) | |
1666 | { | |
1667 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); | |
1668 | qty_phys_has_copy_sugg[reg_qty[ureg]] = 1; | |
1669 | } | |
1670 | else | |
1671 | { | |
1672 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); | |
1673 | qty_phys_has_sugg[reg_qty[ureg]] = 1; | |
1674 | } | |
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | /* At this point we know that SREG and UREG are both pseudos. | |
1679 | Do nothing if SREG already has a quantity or is a register that we | |
1680 | don't allocate. */ | |
1681 | if (reg_qty[sreg] >= -1 | |
1682 | /* If we are not going to let any regs live across calls, | |
1683 | don't tie a call-crossing reg to a non-call-crossing reg. */ | |
1684 | || (current_function_has_nonlocal_label | |
1685 | && ((reg_n_calls_crossed[ureg] > 0) | |
1686 | != (reg_n_calls_crossed[sreg] > 0)))) | |
1687 | return 0; | |
1688 | ||
1689 | /* We don't already know about SREG, so tie it to UREG | |
1690 | if this is the last use of UREG, provided the classes they want | |
1691 | are compatible. */ | |
1692 | ||
1693 | if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) | |
1694 | && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]])) | |
1695 | { | |
1696 | /* Add SREG to UREG's quantity. */ | |
1697 | sqty = reg_qty[ureg]; | |
1698 | reg_qty[sreg] = sqty; | |
1699 | reg_offset[sreg] = reg_offset[ureg] + offset; | |
1700 | reg_next_in_qty[sreg] = qty_first_reg[sqty]; | |
1701 | qty_first_reg[sqty] = sreg; | |
1702 | ||
1703 | /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */ | |
1704 | update_qty_class (sqty, sreg); | |
1705 | ||
1706 | /* Update info about quantity SQTY. */ | |
1707 | qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg]; | |
1708 | qty_n_refs[sqty] += reg_n_refs[sreg]; | |
2bbd3819 RS |
1709 | if (usize < ssize) |
1710 | { | |
1711 | register int i; | |
1712 | ||
1713 | for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i]) | |
1714 | reg_offset[i] -= offset; | |
1715 | ||
1716 | qty_size[sqty] = ssize; | |
1717 | qty_mode[sqty] = GET_MODE (setreg); | |
1718 | } | |
1719 | } | |
1720 | else | |
1721 | return 0; | |
1722 | ||
1723 | return 1; | |
1724 | } | |
1725 | \f | |
1726 | /* Return 1 if the preferred class of REG allows it to be tied | |
1727 | to a quantity or register whose class is CLASS. | |
1728 | True if REG's reg class either contains or is contained in CLASS. */ | |
1729 | ||
1730 | static int | |
1731 | reg_meets_class_p (reg, class) | |
1732 | int reg; | |
1733 | enum reg_class class; | |
1734 | { | |
1735 | register enum reg_class rclass = reg_preferred_class (reg); | |
1736 | return (reg_class_subset_p (rclass, class) | |
1737 | || reg_class_subset_p (class, rclass)); | |
1738 | } | |
1739 | ||
1740 | /* Return 1 if the two specified classes have registers in common. | |
1741 | If CALL_SAVED, then consider only call-saved registers. */ | |
1742 | ||
1743 | static int | |
1744 | reg_classes_overlap_p (c1, c2, call_saved) | |
1745 | register enum reg_class c1; | |
1746 | register enum reg_class c2; | |
1747 | int call_saved; | |
1748 | { | |
1749 | HARD_REG_SET c; | |
1750 | int i; | |
1751 | ||
1752 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
1753 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
1754 | ||
1755 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1756 | if (TEST_HARD_REG_BIT (c, i) | |
1757 | && (! call_saved || ! call_used_regs[i])) | |
1758 | return 1; | |
1759 | ||
1760 | return 0; | |
1761 | } | |
1762 | ||
1763 | /* Update the class of QTY assuming that REG is being tied to it. */ | |
1764 | ||
1765 | static void | |
1766 | update_qty_class (qty, reg) | |
1767 | int qty; | |
1768 | int reg; | |
1769 | { | |
1770 | enum reg_class rclass = reg_preferred_class (reg); | |
1771 | if (reg_class_subset_p (rclass, qty_min_class[qty])) | |
1772 | qty_min_class[qty] = rclass; | |
e4600702 RK |
1773 | |
1774 | rclass = reg_alternate_class (reg); | |
1775 | if (reg_class_subset_p (rclass, qty_alternate_class[qty])) | |
1776 | qty_alternate_class[qty] = rclass; | |
2bbd3819 RS |
1777 | } |
1778 | \f | |
1779 | /* Handle something which alters the value of an rtx REG. | |
1780 | ||
1781 | REG is whatever is set or clobbered. SETTER is the rtx that | |
1782 | is modifying the register. | |
1783 | ||
1784 | If it is not really a register, we do nothing. | |
1785 | The file-global variables `this_insn' and `this_insn_number' | |
1786 | carry info from `block_alloc'. */ | |
1787 | ||
1788 | static void | |
1789 | reg_is_set (reg, setter) | |
1790 | rtx reg; | |
1791 | rtx setter; | |
1792 | { | |
1793 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of | |
1794 | a hard register. These may actually not exist any more. */ | |
1795 | ||
1796 | if (GET_CODE (reg) != SUBREG | |
1797 | && GET_CODE (reg) != REG) | |
1798 | return; | |
1799 | ||
1800 | /* Mark this register as being born. If it is used in a CLOBBER, mark | |
1801 | it as being born halfway between the previous insn and this insn so that | |
1802 | it conflicts with our inputs but not the outputs of the previous insn. */ | |
1803 | ||
1804 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); | |
1805 | } | |
1806 | \f | |
1807 | /* Handle beginning of the life of register REG. | |
1808 | BIRTH is the index at which this is happening. */ | |
1809 | ||
1810 | static void | |
1811 | reg_is_born (reg, birth) | |
1812 | rtx reg; | |
1813 | int birth; | |
1814 | { | |
1815 | register int regno; | |
1816 | ||
1817 | if (GET_CODE (reg) == SUBREG) | |
1818 | regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg); | |
1819 | else | |
1820 | regno = REGNO (reg); | |
1821 | ||
1822 | if (regno < FIRST_PSEUDO_REGISTER) | |
1823 | { | |
1824 | mark_life (regno, GET_MODE (reg), 1); | |
1825 | ||
1826 | /* If the register was to have been born earlier that the present | |
1827 | insn, mark it as live where it is actually born. */ | |
1828 | if (birth < 2 * this_insn_number) | |
1829 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); | |
1830 | } | |
1831 | else | |
1832 | { | |
1833 | if (reg_qty[regno] == -2) | |
1834 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); | |
1835 | ||
1836 | /* If this register has a quantity number, show that it isn't dead. */ | |
1837 | if (reg_qty[regno] >= 0) | |
1838 | qty_death[reg_qty[regno]] = -1; | |
1839 | } | |
1840 | } | |
1841 | ||
1842 | /* Record the death of REG in the current insn. If OUTPUT_P is non-zero, | |
1843 | REG is an output that is dying (i.e., it is never used), otherwise it | |
333e0f7d RS |
1844 | is an input (the normal case). |
1845 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ | |
2bbd3819 RS |
1846 | |
1847 | static void | |
1848 | wipe_dead_reg (reg, output_p) | |
1849 | register rtx reg; | |
1850 | int output_p; | |
1851 | { | |
1852 | register int regno = REGNO (reg); | |
1853 | ||
333e0f7d RS |
1854 | /* If this insn has multiple results, |
1855 | and the dead reg is used in one of the results, | |
1856 | extend its life to after this insn, | |
1857 | so it won't get allocated together with any other result of this insn. */ | |
1858 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL | |
1859 | && !single_set (this_insn)) | |
1860 | { | |
1861 | int i; | |
1862 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) | |
1863 | { | |
1864 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); | |
1865 | if (GET_CODE (set) == SET | |
1866 | && GET_CODE (SET_DEST (set)) != REG | |
1867 | && !rtx_equal_p (reg, SET_DEST (set)) | |
1868 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1869 | output_p = 1; | |
1870 | } | |
1871 | } | |
1872 | ||
2bbd3819 RS |
1873 | if (regno < FIRST_PSEUDO_REGISTER) |
1874 | { | |
1875 | mark_life (regno, GET_MODE (reg), 0); | |
1876 | ||
1877 | /* If a hard register is dying as an output, mark it as in use at | |
1878 | the beginning of this insn (the above statement would cause this | |
1879 | not to happen). */ | |
1880 | if (output_p) | |
1881 | post_mark_life (regno, GET_MODE (reg), 1, | |
1882 | 2 * this_insn_number, 2 * this_insn_number+ 1); | |
1883 | } | |
1884 | ||
1885 | else if (reg_qty[regno] >= 0) | |
1886 | qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p; | |
1887 | } | |
1888 | \f | |
1889 | /* Find a block of SIZE words of hard regs in reg_class CLASS | |
1890 | that can hold something of machine-mode MODE | |
1891 | (but actually we test only the first of the block for holding MODE) | |
1892 | and still free between insn BORN_INDEX and insn DEAD_INDEX, | |
1893 | and return the number of the first of them. | |
1894 | Return -1 if such a block cannot be found. | |
1895 | If QTY crosses calls, insist on a register preserved by calls, | |
1896 | unless ACCEPT_CALL_CLOBBERED is nonzero. | |
1897 | ||
1898 | If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested | |
1899 | register is available. If not, return -1. */ | |
1900 | ||
1901 | static int | |
1902 | find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested, | |
1903 | born_index, dead_index) | |
1904 | enum reg_class class; | |
1905 | enum machine_mode mode; | |
1906 | int accept_call_clobbered; | |
1907 | int just_try_suggested; | |
1908 | int qty; | |
1909 | int born_index, dead_index; | |
1910 | { | |
1911 | register int i, ins; | |
1912 | #ifdef HARD_REG_SET | |
1913 | register /* Declare it register if it's a scalar. */ | |
1914 | #endif | |
1915 | HARD_REG_SET used, first_used; | |
1916 | #ifdef ELIMINABLE_REGS | |
1917 | static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; | |
1918 | #endif | |
1919 | ||
1920 | /* Validate our parameters. */ | |
1921 | if (born_index < 0 || born_index > dead_index) | |
1922 | abort (); | |
1923 | ||
1924 | /* Don't let a pseudo live in a reg across a function call | |
1925 | if we might get a nonlocal goto. */ | |
1926 | if (current_function_has_nonlocal_label | |
1927 | && qty_n_calls_crossed[qty] > 0) | |
1928 | return -1; | |
1929 | ||
1930 | if (accept_call_clobbered) | |
1931 | COPY_HARD_REG_SET (used, call_fixed_reg_set); | |
1932 | else if (qty_n_calls_crossed[qty] == 0) | |
1933 | COPY_HARD_REG_SET (used, fixed_reg_set); | |
1934 | else | |
1935 | COPY_HARD_REG_SET (used, call_used_reg_set); | |
1936 | ||
1937 | for (ins = born_index; ins < dead_index; ins++) | |
1938 | IOR_HARD_REG_SET (used, regs_live_at[ins]); | |
1939 | ||
1940 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); | |
1941 | ||
1942 | /* Don't use the frame pointer reg in local-alloc even if | |
1943 | we may omit the frame pointer, because if we do that and then we | |
1944 | need a frame pointer, reload won't know how to move the pseudo | |
1945 | to another hard reg. It can move only regs made by global-alloc. | |
1946 | ||
1947 | This is true of any register that can be eliminated. */ | |
1948 | #ifdef ELIMINABLE_REGS | |
1949 | for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++) | |
1950 | SET_HARD_REG_BIT (used, eliminables[i].from); | |
1951 | #else | |
1952 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); | |
1953 | #endif | |
1954 | ||
1955 | /* Normally, the registers that can be used for the first register in | |
1956 | a multi-register quantity are the same as those that can be used for | |
1957 | subsequent registers. However, if just trying suggested registers, | |
1958 | restrict our consideration to them. If there are copy-suggested | |
1959 | register, try them. Otherwise, try the arithmetic-suggested | |
1960 | registers. */ | |
1961 | COPY_HARD_REG_SET (first_used, used); | |
1962 | ||
1963 | if (just_try_suggested) | |
1964 | { | |
1965 | if (qty_phys_has_copy_sugg[qty]) | |
1966 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]); | |
1967 | else | |
1968 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]); | |
1969 | } | |
1970 | ||
1971 | /* If all registers are excluded, we can't do anything. */ | |
1972 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); | |
1973 | ||
1974 | /* If at least one would be suitable, test each hard reg. */ | |
1975 | ||
1976 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1977 | { | |
1978 | #ifdef REG_ALLOC_ORDER | |
1979 | int regno = reg_alloc_order[i]; | |
1980 | #else | |
1981 | int regno = i; | |
1982 | #endif | |
1983 | if (! TEST_HARD_REG_BIT (first_used, regno) | |
1984 | && HARD_REGNO_MODE_OK (regno, mode)) | |
1985 | { | |
1986 | register int j; | |
1987 | register int size1 = HARD_REGNO_NREGS (regno, mode); | |
1988 | for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); | |
1989 | if (j == size1) | |
1990 | { | |
1991 | /* Mark that this register is in use between its birth and death | |
1992 | insns. */ | |
1993 | post_mark_life (regno, mode, 1, born_index, dead_index); | |
1994 | return regno; | |
1995 | } | |
1996 | #ifndef REG_ALLOC_ORDER | |
1997 | i += j; /* Skip starting points we know will lose */ | |
1998 | #endif | |
1999 | } | |
2000 | } | |
2001 | ||
2002 | fail: | |
2003 | ||
2004 | /* If we are just trying suggested register, we have just tried copy- | |
2005 | suggested registers, and there are arithmetic-suggested registers, | |
2006 | try them. */ | |
2007 | ||
2008 | /* If it would be profitable to allocate a call-clobbered register | |
2009 | and save and restore it around calls, do that. */ | |
2010 | if (just_try_suggested && qty_phys_has_copy_sugg[qty] | |
2011 | && qty_phys_has_sugg[qty]) | |
2012 | { | |
2013 | /* Don't try the copy-suggested regs again. */ | |
2014 | qty_phys_has_copy_sugg[qty] = 0; | |
2015 | return find_free_reg (class, mode, qty, accept_call_clobbered, 1, | |
2016 | born_index, dead_index); | |
2017 | } | |
2018 | ||
e19f5192 RK |
2019 | /* We need not check to see if the current function has nonlocal |
2020 | labels because we don't put any pseudos that are live over calls in | |
2021 | registers in that case. */ | |
2022 | ||
2bbd3819 RS |
2023 | if (! accept_call_clobbered |
2024 | && flag_caller_saves | |
2025 | && ! just_try_suggested | |
2026 | && qty_n_calls_crossed[qty] != 0 | |
2027 | && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty])) | |
2028 | { | |
2029 | i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index); | |
2030 | if (i >= 0) | |
2031 | caller_save_needed = 1; | |
2032 | return i; | |
2033 | } | |
2034 | return -1; | |
2035 | } | |
2036 | \f | |
2037 | /* Mark that REGNO with machine-mode MODE is live starting from the current | |
2038 | insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE | |
2039 | is zero). */ | |
2040 | ||
2041 | static void | |
2042 | mark_life (regno, mode, life) | |
2043 | register int regno; | |
2044 | enum machine_mode mode; | |
2045 | int life; | |
2046 | { | |
2047 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2048 | if (life) | |
2049 | while (--j >= 0) | |
2050 | SET_HARD_REG_BIT (regs_live, regno + j); | |
2051 | else | |
2052 | while (--j >= 0) | |
2053 | CLEAR_HARD_REG_BIT (regs_live, regno + j); | |
2054 | } | |
2055 | ||
2056 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE | |
2057 | is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) | |
2058 | to insn number DEATH (exclusive). */ | |
2059 | ||
2060 | static void | |
2061 | post_mark_life (regno, mode, life, birth, death) | |
2062 | register int regno, life, birth; | |
2063 | enum machine_mode mode; | |
2064 | int death; | |
2065 | { | |
2066 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2067 | #ifdef HARD_REG_SET | |
2068 | register /* Declare it register if it's a scalar. */ | |
2069 | #endif | |
2070 | HARD_REG_SET this_reg; | |
2071 | ||
2072 | CLEAR_HARD_REG_SET (this_reg); | |
2073 | while (--j >= 0) | |
2074 | SET_HARD_REG_BIT (this_reg, regno + j); | |
2075 | ||
2076 | if (life) | |
2077 | while (birth < death) | |
2078 | { | |
2079 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2080 | birth++; | |
2081 | } | |
2082 | else | |
2083 | while (birth < death) | |
2084 | { | |
2085 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2086 | birth++; | |
2087 | } | |
2088 | } | |
2089 | \f | |
2090 | /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 | |
2091 | is the register being clobbered, and R1 is a register being used in | |
2092 | the equivalent expression. | |
2093 | ||
2094 | If R1 dies in the block and has a REG_NO_CONFLICT note on every insn | |
2095 | in which it is used, return 1. | |
2096 | ||
2097 | Otherwise, return 0. */ | |
2098 | ||
2099 | static int | |
2100 | no_conflict_p (insn, r0, r1) | |
2101 | rtx insn, r0, r1; | |
2102 | { | |
2103 | int ok = 0; | |
b1ec3c92 | 2104 | rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); |
2bbd3819 RS |
2105 | rtx p, last; |
2106 | ||
2107 | /* If R1 is a hard register, return 0 since we handle this case | |
2108 | when we scan the insns that actually use it. */ | |
2109 | ||
2110 | if (note == 0 | |
2111 | || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) | |
2112 | || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG | |
2113 | && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) | |
2114 | return 0; | |
2115 | ||
2116 | last = XEXP (note, 0); | |
2117 | ||
2118 | for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) | |
2119 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
2120 | { | |
2121 | if (find_reg_note (p, REG_DEAD, r1)) | |
2122 | ok = 1; | |
2123 | ||
2124 | if (reg_mentioned_p (r1, PATTERN (p)) | |
2125 | && ! find_reg_note (p, REG_NO_CONFLICT, r1)) | |
2126 | return 0; | |
2127 | } | |
2128 | ||
2129 | return ok; | |
2130 | } | |
2131 | \f | |
7fe4336e RK |
2132 | #ifdef REGISTER_CONSTRAINTS |
2133 | ||
2bbd3819 RS |
2134 | /* Return 1 if the constraint string P indicates that the a the operand |
2135 | must be equal to operand 0 and that no register is acceptable. */ | |
2136 | ||
2137 | static int | |
2138 | requires_inout_p (p) | |
2139 | char *p; | |
2140 | { | |
2141 | char c; | |
2142 | int found_zero = 0; | |
2143 | ||
2144 | while (c = *p++) | |
2145 | switch (c) | |
2146 | { | |
2147 | case '0': | |
2148 | found_zero = 1; | |
2149 | break; | |
2150 | ||
2151 | case '=': case '+': case '?': | |
2152 | case '#': case '&': case '!': | |
2153 | case '*': case '%': case ',': | |
2154 | case '1': case '2': case '3': case '4': | |
2155 | case 'm': case '<': case '>': case 'V': case 'o': | |
2156 | case 'E': case 'F': case 'G': case 'H': | |
2157 | case 's': case 'i': case 'n': | |
2158 | case 'I': case 'J': case 'K': case 'L': | |
2159 | case 'M': case 'N': case 'O': case 'P': | |
2160 | #ifdef EXTRA_CONSTRAINT | |
2161 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
2162 | #endif | |
2163 | case 'X': | |
2164 | /* These don't say anything we care about. */ | |
2165 | break; | |
2166 | ||
2167 | case 'p': | |
2168 | case 'g': case 'r': | |
2169 | default: | |
2170 | /* These mean a register is allowed. Fail if so. */ | |
2171 | return 0; | |
2172 | } | |
2173 | ||
2174 | return found_zero; | |
2175 | } | |
7fe4336e | 2176 | #endif /* REGISTER_CONSTRAINTS */ |
2bbd3819 RS |
2177 | \f |
2178 | void | |
2179 | dump_local_alloc (file) | |
2180 | FILE *file; | |
2181 | { | |
2182 | register int i; | |
2183 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
2184 | if (reg_renumber[i] != -1) | |
2185 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); | |
2186 | } |