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2bbd3819 | 1 | /* Allocate registers within a basic block, for GNU compiler. |
d050d723 JL |
2 | Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
2bbd3819 RS |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
a35311b0 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
2bbd3819 RS |
21 | |
22 | ||
23 | /* Allocation of hard register numbers to pseudo registers is done in | |
24 | two passes. In this pass we consider only regs that are born and | |
25 | die once within one basic block. We do this one basic block at a | |
26 | time. Then the next pass allocates the registers that remain. | |
27 | Two passes are used because this pass uses methods that work only | |
28 | on linear code, but that do a better job than the general methods | |
29 | used in global_alloc, and more quickly too. | |
30 | ||
31 | The assignments made are recorded in the vector reg_renumber | |
32 | whose space is allocated here. The rtl code itself is not altered. | |
33 | ||
34 | We assign each instruction in the basic block a number | |
35 | which is its order from the beginning of the block. | |
36 | Then we can represent the lifetime of a pseudo register with | |
37 | a pair of numbers, and check for conflicts easily. | |
38 | We can record the availability of hard registers with a | |
39 | HARD_REG_SET for each instruction. The HARD_REG_SET | |
40 | contains 0 or 1 for each hard reg. | |
41 | ||
42 | To avoid register shuffling, we tie registers together when one | |
43 | dies by being copied into another, or dies in an instruction that | |
44 | does arithmetic to produce another. The tied registers are | |
45 | allocated as one. Registers with different reg class preferences | |
46 | can never be tied unless the class preferred by one is a subclass | |
47 | of the one preferred by the other. | |
48 | ||
49 | Tying is represented with "quantity numbers". | |
50 | A non-tied register is given a new quantity number. | |
51 | Tied registers have the same quantity number. | |
52 | ||
53 | We have provision to exempt registers, even when they are contained | |
54 | within the block, that can be tied to others that are not contained in it. | |
55 | This is so that global_alloc could process them both and tie them then. | |
56 | But this is currently disabled since tying in global_alloc is not | |
57 | yet implemented. */ | |
58 | ||
a300b8d9 JW |
59 | /* Pseudos allocated here can be reallocated by global.c if the hard register |
60 | is used as a spill register. Currently we don't allocate such pseudos | |
6cad67d2 JL |
61 | here if their preferred class is likely to be used by spills. */ |
62 | ||
2bbd3819 | 63 | #include "config.h" |
670ee920 | 64 | #include "system.h" |
2bbd3819 | 65 | #include "rtl.h" |
6baf1cc8 | 66 | #include "tm_p.h" |
2bbd3819 RS |
67 | #include "flags.h" |
68 | #include "basic-block.h" | |
69 | #include "regs.h" | |
49ad7cfa | 70 | #include "function.h" |
2bbd3819 RS |
71 | #include "hard-reg-set.h" |
72 | #include "insn-config.h" | |
624a8b3a | 73 | #include "insn-attr.h" |
2bbd3819 RS |
74 | #include "recog.h" |
75 | #include "output.h" | |
2e107e9e | 76 | #include "toplev.h" |
2bbd3819 RS |
77 | \f |
78 | /* Next quantity number available for allocation. */ | |
79 | ||
80 | static int next_qty; | |
81 | ||
a1ed7bdb JH |
82 | /* Information we maitain about each quantity. */ |
83 | struct qty | |
84 | { | |
85 | /* The number of refs to quantity Q. */ | |
2bbd3819 | 86 | |
a1ed7bdb | 87 | int n_refs; |
2bbd3819 | 88 | |
a1ed7bdb JH |
89 | /* Insn number (counting from head of basic block) |
90 | where quantity Q was born. -1 if birth has not been recorded. */ | |
2bbd3819 | 91 | |
a1ed7bdb | 92 | int birth; |
2bbd3819 | 93 | |
a1ed7bdb JH |
94 | /* Insn number (counting from head of basic block) |
95 | where given quantity died. Due to the way tying is done, | |
96 | and the fact that we consider in this pass only regs that die but once, | |
97 | a quantity can die only once. Each quantity's life span | |
98 | is a set of consecutive insns. -1 if death has not been recorded. */ | |
2bbd3819 | 99 | |
a1ed7bdb | 100 | int death; |
2bbd3819 | 101 | |
a1ed7bdb JH |
102 | /* Number of words needed to hold the data in given quantity. |
103 | This depends on its machine mode. It is used for these purposes: | |
104 | 1. It is used in computing the relative importances of qtys, | |
105 | which determines the order in which we look for regs for them. | |
106 | 2. It is used in rules that prevent tying several registers of | |
107 | different sizes in a way that is geometrically impossible | |
108 | (see combine_regs). */ | |
2bbd3819 | 109 | |
a1ed7bdb | 110 | int size; |
2bbd3819 | 111 | |
a1ed7bdb | 112 | /* Number of times a reg tied to given qty lives across a CALL_INSN. */ |
2bbd3819 | 113 | |
a1ed7bdb | 114 | int n_calls_crossed; |
2bbd3819 | 115 | |
a1ed7bdb JH |
116 | /* The register number of one pseudo register whose reg_qty value is Q. |
117 | This register should be the head of the chain | |
118 | maintained in reg_next_in_qty. */ | |
2bbd3819 | 119 | |
a1ed7bdb | 120 | int first_reg; |
2bbd3819 | 121 | |
a1ed7bdb JH |
122 | /* Reg class contained in (smaller than) the preferred classes of all |
123 | the pseudo regs that are tied in given quantity. | |
124 | This is the preferred class for allocating that quantity. */ | |
125 | ||
126 | enum reg_class min_class; | |
2bbd3819 | 127 | |
a1ed7bdb JH |
128 | /* Register class within which we allocate given qty if we can't get |
129 | its preferred class. */ | |
2bbd3819 | 130 | |
a1ed7bdb | 131 | enum reg_class alternate_class; |
2bbd3819 | 132 | |
a1ed7bdb JH |
133 | /* This holds the mode of the registers that are tied to given qty, |
134 | or VOIDmode if registers with differing modes are tied together. */ | |
2bbd3819 | 135 | |
a1ed7bdb | 136 | enum machine_mode mode; |
2bbd3819 | 137 | |
a1ed7bdb JH |
138 | /* the hard reg number chosen for given quantity, |
139 | or -1 if none was found. */ | |
2bbd3819 | 140 | |
a1ed7bdb | 141 | short phys_reg; |
2bbd3819 | 142 | |
a1ed7bdb JH |
143 | /* Nonzero if this quantity has been used in a SUBREG that changes |
144 | its size. */ | |
2bbd3819 | 145 | |
a1ed7bdb | 146 | char changes_size; |
2bbd3819 | 147 | |
a1ed7bdb | 148 | }; |
2bbd3819 | 149 | |
a1ed7bdb | 150 | static struct qty *qty; |
2bbd3819 | 151 | |
a1ed7bdb | 152 | /* These fields are kept separately to speedup their clearing. */ |
2bbd3819 | 153 | |
a1ed7bdb JH |
154 | /* We maintain two hard register sets that indicate suggested hard registers |
155 | for each quantity. The first, phys_copy_sugg, contains hard registers | |
156 | that are tied to the quantity by a simple copy. The second contains all | |
157 | hard registers that are tied to the quantity via an arithmetic operation. | |
2bbd3819 | 158 | |
a1ed7bdb JH |
159 | The former register set is given priority for allocation. This tends to |
160 | eliminate copy insns. */ | |
2bbd3819 | 161 | |
a1ed7bdb JH |
162 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
163 | copy insns. */ | |
2bbd3819 | 164 | |
a1ed7bdb | 165 | static HARD_REG_SET *qty_phys_copy_sugg; |
2bbd3819 | 166 | |
a1ed7bdb JH |
167 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
168 | arithmetic insns. */ | |
169 | ||
170 | static HARD_REG_SET *qty_phys_sugg; | |
171 | ||
172 | /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ | |
2bbd3819 | 173 | |
a1ed7bdb | 174 | static short *qty_phys_num_copy_sugg; |
0f64b8f6 | 175 | |
a1ed7bdb | 176 | /* Element Q is the number of suggested registers in qty_phys_sugg. */ |
0f64b8f6 | 177 | |
a1ed7bdb | 178 | static short *qty_phys_num_sugg; |
2bbd3819 | 179 | |
2bbd3819 RS |
180 | |
181 | /* If (REG N) has been assigned a quantity number, is a register number | |
182 | of another register assigned the same quantity number, or -1 for the | |
a1ed7bdb | 183 | end of the chain. qty->first_reg point to the head of this chain. */ |
2bbd3819 | 184 | |
aabf56ce | 185 | static int *reg_next_in_qty; |
2bbd3819 RS |
186 | |
187 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg | |
188 | if it is >= 0, | |
189 | of -1 if this register cannot be allocated by local-alloc, | |
190 | or -2 if not known yet. | |
191 | ||
192 | Note that if we see a use or death of pseudo register N with | |
193 | reg_qty[N] == -2, register N must be local to the current block. If | |
194 | it were used in more than one block, we would have reg_qty[N] == -1. | |
195 | This relies on the fact that if reg_basic_block[N] is >= 0, register N | |
196 | will not appear in any other block. We save a considerable number of | |
197 | tests by exploiting this. | |
198 | ||
199 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not | |
200 | be referenced. */ | |
201 | ||
202 | static int *reg_qty; | |
203 | ||
204 | /* The offset (in words) of register N within its quantity. | |
205 | This can be nonzero if register N is SImode, and has been tied | |
206 | to a subreg of a DImode register. */ | |
207 | ||
208 | static char *reg_offset; | |
209 | ||
210 | /* Vector of substitutions of register numbers, | |
211 | used to map pseudo regs into hardware regs. | |
212 | This is set up as a result of register allocation. | |
213 | Element N is the hard reg assigned to pseudo reg N, | |
214 | or is -1 if no hard reg was assigned. | |
215 | If N is a hard reg number, element N is N. */ | |
216 | ||
217 | short *reg_renumber; | |
218 | ||
219 | /* Set of hard registers live at the current point in the scan | |
220 | of the instructions in a basic block. */ | |
221 | ||
222 | static HARD_REG_SET regs_live; | |
223 | ||
224 | /* Each set of hard registers indicates registers live at a particular | |
225 | point in the basic block. For N even, regs_live_at[N] says which | |
226 | hard registers are needed *after* insn N/2 (i.e., they may not | |
227 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. | |
228 | ||
229 | If an object is to conflict with the inputs of insn J but not the | |
230 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, | |
231 | if it is to conflict with the outputs of insn J but not the inputs of | |
232 | insn J + 1, it is said to die at index J*2 + 1. */ | |
233 | ||
234 | static HARD_REG_SET *regs_live_at; | |
235 | ||
236 | /* Communicate local vars `insn_number' and `insn' | |
237 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ | |
238 | static int this_insn_number; | |
239 | static rtx this_insn; | |
240 | ||
c25a4c25 | 241 | /* Used to communicate changes made by update_equiv_regs to |
68342d36 RK |
242 | memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note |
243 | found or created, so that we can keep track of what memory accesses might | |
244 | be created later, e.g. by reload. */ | |
245 | ||
c25a4c25 RK |
246 | static rtx *reg_equiv_replacement; |
247 | ||
135eb61c R |
248 | /* Used for communication between update_equiv_regs and no_equiv. */ |
249 | static rtx *reg_equiv_init_insns; | |
250 | ||
3f1b9b1b JL |
251 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
252 | static int recorded_label_ref; | |
253 | ||
3fe41456 KG |
254 | static void alloc_qty PARAMS ((int, enum machine_mode, int, int)); |
255 | static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *)); | |
256 | static int validate_equiv_mem PARAMS ((rtx, rtx, rtx)); | |
257 | static int contains_replace_regs PARAMS ((rtx, char *)); | |
258 | static int memref_referenced_p PARAMS ((rtx, rtx)); | |
259 | static int memref_used_between_p PARAMS ((rtx, rtx, rtx)); | |
260 | static void update_equiv_regs PARAMS ((void)); | |
261 | static void no_equiv PARAMS ((rtx, rtx, void *)); | |
262 | static void block_alloc PARAMS ((int)); | |
263 | static int qty_sugg_compare PARAMS ((int, int)); | |
264 | static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR)); | |
265 | static int qty_compare PARAMS ((int, int)); | |
266 | static int qty_compare_1 PARAMS ((const PTR, const PTR)); | |
267 | static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int)); | |
268 | static int reg_meets_class_p PARAMS ((int, enum reg_class)); | |
269 | static void update_qty_class PARAMS ((int, int)); | |
270 | static void reg_is_set PARAMS ((rtx, rtx, void *)); | |
271 | static void reg_is_born PARAMS ((rtx, int)); | |
272 | static void wipe_dead_reg PARAMS ((rtx, int)); | |
273 | static int find_free_reg PARAMS ((enum reg_class, enum machine_mode, | |
82c68a78 | 274 | int, int, int, int, int)); |
3fe41456 KG |
275 | static void mark_life PARAMS ((int, enum machine_mode, int)); |
276 | static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int)); | |
277 | static int no_conflict_p PARAMS ((rtx, rtx, rtx)); | |
278 | static int requires_inout PARAMS ((const char *)); | |
2bbd3819 RS |
279 | \f |
280 | /* Allocate a new quantity (new within current basic block) | |
281 | for register number REGNO which is born at index BIRTH | |
282 | within the block. MODE and SIZE are info on reg REGNO. */ | |
283 | ||
284 | static void | |
285 | alloc_qty (regno, mode, size, birth) | |
286 | int regno; | |
287 | enum machine_mode mode; | |
288 | int size, birth; | |
289 | { | |
a1ed7bdb | 290 | register int qtyno = next_qty++; |
2bbd3819 | 291 | |
a1ed7bdb | 292 | reg_qty[regno] = qtyno; |
2bbd3819 RS |
293 | reg_offset[regno] = 0; |
294 | reg_next_in_qty[regno] = -1; | |
295 | ||
a1ed7bdb JH |
296 | qty[qtyno].first_reg = regno; |
297 | qty[qtyno].size = size; | |
298 | qty[qtyno].mode = mode; | |
299 | qty[qtyno].birth = birth; | |
300 | qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno); | |
301 | qty[qtyno].min_class = reg_preferred_class (regno); | |
302 | qty[qtyno].alternate_class = reg_alternate_class (regno); | |
303 | qty[qtyno].n_refs = REG_N_REFS (regno); | |
304 | qty[qtyno].changes_size = REG_CHANGES_SIZE (regno); | |
2bbd3819 RS |
305 | } |
306 | \f | |
2bbd3819 RS |
307 | /* Main entry point of this file. */ |
308 | ||
3f1b9b1b | 309 | int |
2bbd3819 RS |
310 | local_alloc () |
311 | { | |
312 | register int b, i; | |
313 | int max_qty; | |
314 | ||
3f1b9b1b JL |
315 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
316 | that we know if the jump optimizer needs to be rerun. */ | |
317 | recorded_label_ref = 0; | |
318 | ||
2bbd3819 RS |
319 | /* Leaf functions and non-leaf functions have different needs. |
320 | If defined, let the machine say what kind of ordering we | |
321 | should use. */ | |
322 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC | |
323 | ORDER_REGS_FOR_LOCAL_ALLOC; | |
324 | #endif | |
325 | ||
326 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected | |
327 | registers. */ | |
328 | update_equiv_regs (); | |
329 | ||
330 | /* This sets the maximum number of quantities we can have. Quantity | |
34f89b5f BS |
331 | numbers start at zero and we can have one for each pseudo. */ |
332 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER); | |
2bbd3819 RS |
333 | |
334 | /* Allocate vectors of temporary data. | |
335 | See the declarations of these variables, above, | |
336 | for what they mean. */ | |
337 | ||
a1ed7bdb | 338 | qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty)); |
4c9a05bc | 339 | qty_phys_copy_sugg |
75c6bd46 RH |
340 | = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET)); |
341 | qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short)); | |
342 | qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET)); | |
343 | qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short)); | |
2bbd3819 | 344 | |
83cbe7e4 RH |
345 | reg_qty = (int *) xmalloc (max_regno * sizeof (int)); |
346 | reg_offset = (char *) xmalloc (max_regno * sizeof (char)); | |
347 | reg_next_in_qty = (int *) xmalloc(max_regno * sizeof (int)); | |
2bbd3819 | 348 | |
39379e67 MM |
349 | /* Allocate the reg_renumber array */ |
350 | allocate_reg_info (max_regno, FALSE, TRUE); | |
2bbd3819 RS |
351 | |
352 | /* Determine which pseudo-registers can be allocated by local-alloc. | |
353 | In general, these are the registers used only in a single block and | |
354 | which only die once. However, if a register's preferred class has only | |
cde62d1a | 355 | a few entries, don't allocate this register here unless it is preferred |
2bbd3819 RS |
356 | or nothing since retry_global_alloc won't be able to move it to |
357 | GENERAL_REGS if a reload register of this class is needed. | |
358 | ||
359 | We need not be concerned with which block actually uses the register | |
360 | since we will never see it outside that block. */ | |
361 | ||
362 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
363 | { | |
b1f21e0a | 364 | if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1 |
e4600702 | 365 | && (reg_alternate_class (i) == NO_REGS |
cde62d1a | 366 | || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i)))) |
2bbd3819 RS |
367 | reg_qty[i] = -2; |
368 | else | |
369 | reg_qty[i] = -1; | |
370 | } | |
371 | ||
372 | /* Force loop below to initialize entire quantity array. */ | |
373 | next_qty = max_qty; | |
374 | ||
375 | /* Allocate each block's local registers, block by block. */ | |
376 | ||
377 | for (b = 0; b < n_basic_blocks; b++) | |
378 | { | |
379 | /* NEXT_QTY indicates which elements of the `qty_...' | |
380 | vectors might need to be initialized because they were used | |
381 | for the previous block; it is set to the entire array before | |
382 | block 0. Initialize those, with explicit loop if there are few, | |
383 | else with bzero and bcopy. Do not initialize vectors that are | |
384 | explicit set by `alloc_qty'. */ | |
385 | ||
386 | if (next_qty < 6) | |
387 | { | |
388 | for (i = 0; i < next_qty; i++) | |
389 | { | |
2bbd3819 | 390 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); |
51b86d8b | 391 | qty_phys_num_copy_sugg[i] = 0; |
2bbd3819 | 392 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); |
51b86d8b | 393 | qty_phys_num_sugg[i] = 0; |
2bbd3819 RS |
394 | } |
395 | } | |
396 | else | |
397 | { | |
398 | #define CLEAR(vector) \ | |
4c9a05bc | 399 | bzero ((char *) (vector), (sizeof (*(vector))) * next_qty); |
2bbd3819 | 400 | |
2bbd3819 | 401 | CLEAR (qty_phys_copy_sugg); |
51b86d8b | 402 | CLEAR (qty_phys_num_copy_sugg); |
2bbd3819 | 403 | CLEAR (qty_phys_sugg); |
51b86d8b | 404 | CLEAR (qty_phys_num_sugg); |
2bbd3819 RS |
405 | } |
406 | ||
407 | next_qty = 0; | |
408 | ||
409 | block_alloc (b); | |
2bbd3819 | 410 | } |
83cbe7e4 | 411 | |
a1ed7bdb | 412 | free (qty); |
75c6bd46 RH |
413 | free (qty_phys_copy_sugg); |
414 | free (qty_phys_num_copy_sugg); | |
415 | free (qty_phys_sugg); | |
e7749837 | 416 | free (qty_phys_num_sugg); |
75c6bd46 | 417 | |
83cbe7e4 RH |
418 | free (reg_qty); |
419 | free (reg_offset); | |
420 | free (reg_next_in_qty); | |
75c6bd46 | 421 | |
3f1b9b1b | 422 | return recorded_label_ref; |
2bbd3819 RS |
423 | } |
424 | \f | |
425 | /* Depth of loops we are in while in update_equiv_regs. */ | |
426 | static int loop_depth; | |
427 | ||
428 | /* Used for communication between the following two functions: contains | |
429 | a MEM that we wish to ensure remains unchanged. */ | |
430 | static rtx equiv_mem; | |
431 | ||
432 | /* Set nonzero if EQUIV_MEM is modified. */ | |
433 | static int equiv_mem_modified; | |
434 | ||
435 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
436 | Called via note_stores. */ | |
437 | ||
438 | static void | |
84832317 | 439 | validate_equiv_mem_from_store (dest, set, data) |
2bbd3819 | 440 | rtx dest; |
e51712db | 441 | rtx set ATTRIBUTE_UNUSED; |
84832317 | 442 | void *data ATTRIBUTE_UNUSED; |
2bbd3819 RS |
443 | { |
444 | if ((GET_CODE (dest) == REG | |
445 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
446 | || (GET_CODE (dest) == MEM | |
9ae8ffe7 | 447 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) |
2bbd3819 RS |
448 | equiv_mem_modified = 1; |
449 | } | |
450 | ||
451 | /* Verify that no store between START and the death of REG invalidates | |
452 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
453 | by storing into an overlapping memory location, or with a non-const | |
454 | CALL_INSN. | |
455 | ||
456 | Return 1 if MEMREF remains valid. */ | |
457 | ||
458 | static int | |
459 | validate_equiv_mem (start, reg, memref) | |
460 | rtx start; | |
461 | rtx reg; | |
462 | rtx memref; | |
463 | { | |
464 | rtx insn; | |
465 | rtx note; | |
466 | ||
467 | equiv_mem = memref; | |
468 | equiv_mem_modified = 0; | |
469 | ||
470 | /* If the memory reference has side effects or is volatile, it isn't a | |
471 | valid equivalence. */ | |
472 | if (side_effects_p (memref)) | |
473 | return 0; | |
474 | ||
475 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
476 | { | |
477 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
478 | continue; | |
479 | ||
480 | if (find_reg_note (insn, REG_DEAD, reg)) | |
481 | return 1; | |
482 | ||
483 | if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) | |
484 | && ! CONST_CALL_P (insn)) | |
485 | return 0; | |
486 | ||
84832317 | 487 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); |
2bbd3819 RS |
488 | |
489 | /* If a register mentioned in MEMREF is modified via an | |
490 | auto-increment, we lose the equivalence. Do the same if one | |
491 | dies; although we could extend the life, it doesn't seem worth | |
492 | the trouble. */ | |
493 | ||
494 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
495 | if ((REG_NOTE_KIND (note) == REG_INC | |
496 | || REG_NOTE_KIND (note) == REG_DEAD) | |
497 | && GET_CODE (XEXP (note, 0)) == REG | |
498 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
499 | return 0; | |
500 | } | |
501 | ||
502 | return 0; | |
503 | } | |
a1729519 JW |
504 | |
505 | /* TRUE if X uses any registers for which reg_equiv_replace is true. */ | |
506 | ||
507 | static int | |
508 | contains_replace_regs (x, reg_equiv_replace) | |
509 | rtx x; | |
510 | char *reg_equiv_replace; | |
511 | { | |
512 | int i, j; | |
6f7d635c | 513 | const char *fmt; |
a1729519 JW |
514 | enum rtx_code code = GET_CODE (x); |
515 | ||
516 | switch (code) | |
517 | { | |
518 | case CONST_INT: | |
519 | case CONST: | |
520 | case LABEL_REF: | |
521 | case SYMBOL_REF: | |
522 | case CONST_DOUBLE: | |
523 | case PC: | |
524 | case CC0: | |
525 | case HIGH: | |
526 | case LO_SUM: | |
527 | return 0; | |
528 | ||
529 | case REG: | |
530 | return reg_equiv_replace[REGNO (x)]; | |
1d300e19 KG |
531 | |
532 | default: | |
533 | break; | |
a1729519 JW |
534 | } |
535 | ||
536 | fmt = GET_RTX_FORMAT (code); | |
537 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
538 | switch (fmt[i]) | |
539 | { | |
540 | case 'e': | |
541 | if (contains_replace_regs (XEXP (x, i), reg_equiv_replace)) | |
542 | return 1; | |
543 | break; | |
544 | case 'E': | |
545 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
546 | if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace)) | |
547 | return 1; | |
548 | break; | |
549 | } | |
550 | ||
551 | return 0; | |
552 | } | |
2bbd3819 RS |
553 | \f |
554 | /* TRUE if X references a memory location that would be affected by a store | |
555 | to MEMREF. */ | |
556 | ||
557 | static int | |
558 | memref_referenced_p (memref, x) | |
559 | rtx x; | |
560 | rtx memref; | |
561 | { | |
562 | int i, j; | |
6f7d635c | 563 | const char *fmt; |
2bbd3819 RS |
564 | enum rtx_code code = GET_CODE (x); |
565 | ||
566 | switch (code) | |
567 | { | |
2bbd3819 RS |
568 | case CONST_INT: |
569 | case CONST: | |
570 | case LABEL_REF: | |
571 | case SYMBOL_REF: | |
572 | case CONST_DOUBLE: | |
573 | case PC: | |
574 | case CC0: | |
575 | case HIGH: | |
576 | case LO_SUM: | |
577 | return 0; | |
578 | ||
c25a4c25 | 579 | case REG: |
3298a1b1 RK |
580 | return (reg_equiv_replacement[REGNO (x)] |
581 | && memref_referenced_p (memref, | |
c25a4c25 RK |
582 | reg_equiv_replacement[REGNO (x)])); |
583 | ||
2bbd3819 | 584 | case MEM: |
9ae8ffe7 | 585 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) |
2bbd3819 RS |
586 | return 1; |
587 | break; | |
588 | ||
589 | case SET: | |
590 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
591 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
592 | if (GET_CODE (SET_DEST (x)) == MEM) | |
593 | { | |
594 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
595 | return 1; | |
596 | } | |
597 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
598 | return 1; | |
599 | ||
600 | return memref_referenced_p (memref, SET_SRC (x)); | |
e9a25f70 JL |
601 | |
602 | default: | |
603 | break; | |
2bbd3819 RS |
604 | } |
605 | ||
606 | fmt = GET_RTX_FORMAT (code); | |
607 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
608 | switch (fmt[i]) | |
609 | { | |
610 | case 'e': | |
611 | if (memref_referenced_p (memref, XEXP (x, i))) | |
612 | return 1; | |
613 | break; | |
614 | case 'E': | |
615 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
616 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
617 | return 1; | |
618 | break; | |
619 | } | |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
624 | /* TRUE if some insn in the range (START, END] references a memory location | |
625 | that would be affected by a store to MEMREF. */ | |
626 | ||
627 | static int | |
628 | memref_used_between_p (memref, start, end) | |
629 | rtx memref; | |
630 | rtx start; | |
631 | rtx end; | |
632 | { | |
633 | rtx insn; | |
634 | ||
635 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
636 | insn = NEXT_INSN (insn)) | |
637 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
638 | && memref_referenced_p (memref, PATTERN (insn))) | |
639 | return 1; | |
640 | ||
641 | return 0; | |
642 | } | |
643 | \f | |
2b49ee39 R |
644 | /* Return nonzero if the rtx X is invariant over the current function. */ |
645 | int | |
646 | function_invariant_p (x) | |
647 | rtx x; | |
648 | { | |
649 | if (CONSTANT_P (x)) | |
650 | return 1; | |
651 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
652 | return 1; | |
653 | if (GET_CODE (x) == PLUS | |
654 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
655 | && CONSTANT_P (XEXP (x, 1))) | |
656 | return 1; | |
657 | return 0; | |
658 | } | |
659 | ||
2bbd3819 RS |
660 | /* Find registers that are equivalent to a single value throughout the |
661 | compilation (either because they can be referenced in memory or are set once | |
662 | from a single constant). Lower their priority for a register. | |
663 | ||
664 | If such a register is only referenced once, try substituting its value | |
665 | into the using insn. If it succeeds, we can eliminate the register | |
666 | completely. */ | |
667 | ||
668 | static void | |
669 | update_equiv_regs () | |
670 | { | |
68342d36 RK |
671 | /* Set when an attempt should be made to replace a register with the |
672 | associated reg_equiv_replacement entry at the end of this function. */ | |
ff154f78 | 673 | char *reg_equiv_replace; |
2bbd3819 | 674 | rtx insn; |
2e1253f3 | 675 | int block, depth; |
2bbd3819 | 676 | |
ff154f78 MM |
677 | reg_equiv_replace = (char *) xcalloc (max_regno, sizeof *reg_equiv_replace); |
678 | reg_equiv_init_insns = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
679 | reg_equiv_replacement = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
2bbd3819 RS |
680 | |
681 | init_alias_analysis (); | |
682 | ||
9b15c17f | 683 | loop_depth = 0; |
2bbd3819 RS |
684 | |
685 | /* Scan the insns and find which registers have equivalences. Do this | |
686 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
687 | a register can be set below its use. */ | |
688 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
689 | { | |
690 | rtx note; | |
135eb61c | 691 | rtx set; |
49ddab16 | 692 | rtx dest, src; |
2bbd3819 RS |
693 | int regno; |
694 | ||
695 | if (GET_CODE (insn) == NOTE) | |
696 | { | |
697 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
698 | loop_depth++; | |
699 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
700 | loop_depth--; | |
701 | } | |
702 | ||
135eb61c | 703 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') |
2bbd3819 RS |
704 | continue; |
705 | ||
135eb61c R |
706 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
707 | if (REG_NOTE_KIND (note) == REG_INC) | |
84832317 | 708 | no_equiv (XEXP (note, 0), note, NULL); |
135eb61c R |
709 | |
710 | set = single_set (insn); | |
711 | ||
712 | /* If this insn contains more (or less) than a single SET, | |
713 | only mark all destinations as having no known equivalence. */ | |
714 | if (set == 0) | |
715 | { | |
84832317 | 716 | note_stores (PATTERN (insn), no_equiv, NULL); |
135eb61c R |
717 | continue; |
718 | } | |
719 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
720 | { | |
721 | int i; | |
722 | ||
723 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
724 | { | |
725 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
726 | if (part != set) | |
84832317 | 727 | note_stores (part, no_equiv, NULL); |
135eb61c R |
728 | } |
729 | } | |
730 | ||
2bbd3819 | 731 | dest = SET_DEST (set); |
49ddab16 | 732 | src = SET_SRC (set); |
2bbd3819 RS |
733 | |
734 | /* If this sets a MEM to the contents of a REG that is only used | |
735 | in a single basic block, see if the register is always equivalent | |
736 | to that memory location and if moving the store from INSN to the | |
737 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
a1729519 JW |
738 | initializing insn. |
739 | ||
740 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
741 | REG_EQUIV is likely more useful than the one we are adding. | |
742 | ||
743 | If one of the regs in the address is marked as reg_equiv_replace, | |
744 | then we can't add this REG_EQUIV note. The reg_equiv_replace | |
745 | optimization may move the set of this register immediately before | |
135eb61c | 746 | insn, which puts it after reg_equiv_init_insns[regno], and hence |
a1729519 JW |
747 | the mention in the REG_EQUIV note would be to an uninitialized |
748 | pseudo. */ | |
135eb61c R |
749 | /* ????? This test isn't good enough; we might see a MEM with a use of |
750 | a pseudo register before we see its setting insn that will cause | |
751 | reg_equiv_replace for that pseudo to be set. | |
752 | Equivalences to MEMs should be made in another pass, after the | |
753 | reg_equiv_replace information has been gathered. */ | |
754 | ||
755 | if (GET_CODE (dest) == MEM && GET_CODE (src) == REG | |
756 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
b1f21e0a | 757 | && REG_BASIC_BLOCK (regno) >= 0 |
135eb61c R |
758 | && REG_N_SETS (regno) == 1 |
759 | && reg_equiv_init_insns[regno] != 0 | |
760 | && reg_equiv_init_insns[regno] != const0_rtx | |
b768aa38 JL |
761 | && ! find_reg_note (XEXP (reg_equiv_init_insns[regno], 0), |
762 | REG_EQUIV, NULL_RTX) | |
135eb61c R |
763 | && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)) |
764 | { | |
765 | rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0); | |
766 | if (validate_equiv_mem (init_insn, src, dest) | |
767 | && ! memref_used_between_p (dest, init_insn, insn)) | |
768 | REG_NOTES (init_insn) | |
769 | = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn)); | |
770 | } | |
2bbd3819 | 771 | |
1230327b | 772 | /* We only handle the case of a pseudo register being set |
135eb61c R |
773 | once, or always to the same value. */ |
774 | /* ??? The mn10200 port breaks if we add equivalences for | |
775 | values that need an ADDRESS_REGS register and set them equivalent | |
776 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
777 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
778 | calculate_needs, but we traditionally work around this problem | |
779 | here by rejecting equivalences when the destination is in a register | |
780 | that's likely spilled. This is fragile, of course, since the | |
8585f8f1 | 781 | preferred class of a pseudo depends on all instructions that set |
135eb61c R |
782 | or use it. */ |
783 | ||
2bbd3819 RS |
784 | if (GET_CODE (dest) != REG |
785 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
135eb61c R |
786 | || reg_equiv_init_insns[regno] == const0_rtx |
787 | || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) | |
788 | && GET_CODE (src) == MEM)) | |
789 | { | |
790 | /* This might be seting a SUBREG of a pseudo, a pseudo that is | |
791 | also set somewhere else to a constant. */ | |
84832317 | 792 | note_stores (set, no_equiv, NULL); |
135eb61c R |
793 | continue; |
794 | } | |
795 | /* Don't handle the equivalence if the source is in a register | |
796 | class that's likely to be spilled. */ | |
797 | if (GET_CODE (src) == REG | |
798 | && REGNO (src) >= FIRST_PSEUDO_REGISTER | |
799 | && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))) | |
800 | { | |
84832317 | 801 | no_equiv (dest, set, NULL); |
135eb61c R |
802 | continue; |
803 | } | |
2bbd3819 | 804 | |
b1ec3c92 | 805 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
2bbd3819 | 806 | |
135eb61c R |
807 | if (REG_N_SETS (regno) != 1 |
808 | && (! note | |
2b49ee39 | 809 | || ! function_invariant_p (XEXP (note, 0)) |
135eb61c R |
810 | || (reg_equiv_replacement[regno] |
811 | && ! rtx_equal_p (XEXP (note, 0), | |
812 | reg_equiv_replacement[regno])))) | |
813 | { | |
84832317 | 814 | no_equiv (dest, set, NULL); |
135eb61c R |
815 | continue; |
816 | } | |
2bbd3819 | 817 | /* Record this insn as initializing this register. */ |
135eb61c R |
818 | reg_equiv_init_insns[regno] |
819 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]); | |
2bbd3819 RS |
820 | |
821 | /* If this register is known to be equal to a constant, record that | |
822 | it is always equivalent to the constant. */ | |
2b49ee39 | 823 | if (note && function_invariant_p (XEXP (note, 0))) |
2bbd3819 RS |
824 | PUT_MODE (note, (enum machine_mode) REG_EQUIV); |
825 | ||
826 | /* If this insn introduces a "constant" register, decrease the priority | |
827 | of that register. Record this insn if the register is only used once | |
828 | more and the equivalence value is the same as our source. | |
829 | ||
830 | The latter condition is checked for two reasons: First, it is an | |
831 | indication that it may be more efficient to actually emit the insn | |
832 | as written (if no registers are available, reload will substitute | |
833 | the equivalence). Secondly, it avoids problems with any registers | |
834 | dying in this insn whose death notes would be missed. | |
835 | ||
836 | If we don't have a REG_EQUIV note, see if this insn is loading | |
837 | a register used only in one basic block from a MEM. If so, and the | |
838 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
839 | note. */ | |
840 | ||
b1ec3c92 | 841 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
2bbd3819 | 842 | |
b1f21e0a | 843 | if (note == 0 && REG_BASIC_BLOCK (regno) >= 0 |
2bbd3819 RS |
844 | && GET_CODE (SET_SRC (set)) == MEM |
845 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
38a448ca RH |
846 | REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set), |
847 | REG_NOTES (insn)); | |
2bbd3819 | 848 | |
68342d36 | 849 | if (note) |
2bbd3819 RS |
850 | { |
851 | int regno = REGNO (dest); | |
852 | ||
3f1b9b1b JL |
853 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. |
854 | We might end up substituting the LABEL_REF for uses of the | |
855 | pseudo here or later. That kind of transformation may turn an | |
856 | indirect jump into a direct jump, in which case we must rerun the | |
857 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
858 | if (GET_CODE (XEXP (note, 0)) == LABEL_REF | |
859 | || (GET_CODE (XEXP (note, 0)) == CONST | |
860 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
861 | && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) | |
862 | == LABEL_REF))) | |
863 | recorded_label_ref = 1; | |
864 | ||
865 | ||
68342d36 RK |
866 | reg_equiv_replacement[regno] = XEXP (note, 0); |
867 | ||
868 | /* Don't mess with things live during setjmp. */ | |
b1f21e0a | 869 | if (REG_LIVE_LENGTH (regno) >= 0) |
68342d36 RK |
870 | { |
871 | /* Note that the statement below does not affect the priority | |
872 | in local-alloc! */ | |
b1f21e0a | 873 | REG_LIVE_LENGTH (regno) *= 2; |
2bbd3819 | 874 | |
2bbd3819 | 875 | |
68342d36 RK |
876 | /* If the register is referenced exactly twice, meaning it is |
877 | set once and used once, indicate that the reference may be | |
878 | replaced by the equivalence we computed above. If the | |
879 | register is only used in one basic block, this can't succeed | |
880 | or combine would have done it. | |
2bbd3819 | 881 | |
68342d36 RK |
882 | It would be nice to use "loop_depth * 2" in the compare |
883 | below. Unfortunately, LOOP_DEPTH need not be constant within | |
884 | a basic block so this would be too complicated. | |
2bbd3819 | 885 | |
68342d36 RK |
886 | This case normally occurs when a parameter is read from |
887 | memory and then used exactly once, not in a loop. */ | |
888 | ||
b1f21e0a MM |
889 | if (REG_N_REFS (regno) == 2 |
890 | && REG_BASIC_BLOCK (regno) < 0 | |
68342d36 RK |
891 | && rtx_equal_p (XEXP (note, 0), SET_SRC (set))) |
892 | reg_equiv_replace[regno] = 1; | |
893 | } | |
2bbd3819 RS |
894 | } |
895 | } | |
896 | ||
2e1253f3 ILT |
897 | /* Now scan all regs killed in an insn to see if any of them are |
898 | registers only used that once. If so, see if we can replace the | |
899 | reference with the equivalent from. If we can, delete the | |
900 | initializing reference and this register will go away. If we | |
901 | can't replace the reference, and the instruction is not in a | |
902 | loop, then move the register initialization just before the use, | |
903 | so that they are in the same basic block. */ | |
904 | block = -1; | |
905 | depth = 0; | |
906 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2bbd3819 RS |
907 | { |
908 | rtx link; | |
909 | ||
2e1253f3 ILT |
910 | /* Keep track of which basic block we are in. */ |
911 | if (block + 1 < n_basic_blocks | |
3b413743 | 912 | && BLOCK_HEAD (block + 1) == insn) |
2e1253f3 ILT |
913 | ++block; |
914 | ||
915 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
916 | { | |
917 | if (GET_CODE (insn) == NOTE) | |
918 | { | |
919 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
920 | ++depth; | |
921 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
922 | { | |
923 | --depth; | |
924 | if (depth < 0) | |
925 | abort (); | |
926 | } | |
927 | } | |
928 | ||
929 | continue; | |
930 | } | |
931 | ||
2bbd3819 | 932 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
2e1253f3 ILT |
933 | { |
934 | if (REG_NOTE_KIND (link) == REG_DEAD | |
935 | /* Make sure this insn still refers to the register. */ | |
936 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
937 | { | |
938 | int regno = REGNO (XEXP (link, 0)); | |
939 | rtx equiv_insn; | |
2bbd3819 | 940 | |
2e1253f3 ILT |
941 | if (! reg_equiv_replace[regno]) |
942 | continue; | |
943 | ||
135eb61c R |
944 | /* reg_equiv_replace[REGNO] gets set only when |
945 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
946 | once and used once. (If it were only set, but not used, | |
947 | flow would have deleted the setting insns.) Hence | |
948 | there can only be one insn in reg_equiv_init_insns. */ | |
949 | equiv_insn = XEXP (reg_equiv_init_insns[regno], 0); | |
2e1253f3 ILT |
950 | |
951 | if (validate_replace_rtx (regno_reg_rtx[regno], | |
952 | reg_equiv_replacement[regno], insn)) | |
953 | { | |
954 | remove_death (regno, insn); | |
b1f21e0a | 955 | REG_N_REFS (regno) = 0; |
2e1253f3 ILT |
956 | PUT_CODE (equiv_insn, NOTE); |
957 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
958 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
959 | } | |
960 | /* If we aren't in a loop, and there are no calls in | |
961 | INSN or in the initialization of the register, then | |
962 | move the initialization of the register to just | |
963 | before INSN. Update the flow information. */ | |
964 | else if (depth == 0 | |
965 | && GET_CODE (equiv_insn) == INSN | |
966 | && GET_CODE (insn) == INSN | |
b1f21e0a | 967 | && REG_BASIC_BLOCK (regno) < 0) |
2e1253f3 | 968 | { |
8e08106d | 969 | int l; |
2e1253f3 | 970 | |
9956bfc0 RK |
971 | emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn); |
972 | REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn); | |
ef178af3 | 973 | REG_NOTES (equiv_insn) = 0; |
2e1253f3 ILT |
974 | |
975 | PUT_CODE (equiv_insn, NOTE); | |
976 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
977 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
2e1253f3 ILT |
978 | |
979 | if (block < 0) | |
b1f21e0a | 980 | REG_BASIC_BLOCK (regno) = 0; |
2e1253f3 | 981 | else |
b1f21e0a MM |
982 | REG_BASIC_BLOCK (regno) = block; |
983 | REG_N_CALLS_CROSSED (regno) = 0; | |
984 | REG_LIVE_LENGTH (regno) = 2; | |
2e1253f3 | 985 | |
3b413743 RH |
986 | if (block >= 0 && insn == BLOCK_HEAD (block)) |
987 | BLOCK_HEAD (block) = PREV_INSN (insn); | |
2e1253f3 | 988 | |
2e1253f3 | 989 | for (l = 0; l < n_basic_blocks; l++) |
e881bb1b RH |
990 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start, |
991 | regno); | |
2e1253f3 ILT |
992 | } |
993 | } | |
994 | } | |
2bbd3819 | 995 | } |
e05e2395 MM |
996 | |
997 | /* Clean up. */ | |
998 | end_alias_analysis (); | |
ff154f78 MM |
999 | free (reg_equiv_replace); |
1000 | free (reg_equiv_init_insns); | |
1001 | free (reg_equiv_replacement); | |
2bbd3819 | 1002 | } |
135eb61c R |
1003 | |
1004 | /* Mark REG as having no known equivalence. | |
1005 | Some instructions might have been proceessed before and furnished | |
1006 | with REG_EQUIV notes for this register; these notes will have to be | |
1007 | removed. | |
1008 | STORE is the piece of RTL that does the non-constant / conflicting | |
1009 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
1010 | but needs to be there because this function is called from note_stores. */ | |
1011 | static void | |
84832317 | 1012 | no_equiv (reg, store, data) |
54ea1de9 | 1013 | rtx reg, store ATTRIBUTE_UNUSED; |
84832317 | 1014 | void *data ATTRIBUTE_UNUSED; |
135eb61c R |
1015 | { |
1016 | int regno; | |
1017 | rtx list; | |
1018 | ||
1019 | if (GET_CODE (reg) != REG) | |
1020 | return; | |
1021 | regno = REGNO (reg); | |
1022 | list = reg_equiv_init_insns[regno]; | |
1023 | if (list == const0_rtx) | |
1024 | return; | |
1025 | for (; list; list = XEXP (list, 1)) | |
1026 | { | |
1027 | rtx insn = XEXP (list, 0); | |
1028 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
1029 | } | |
1030 | reg_equiv_init_insns[regno] = const0_rtx; | |
1031 | reg_equiv_replacement[regno] = NULL_RTX; | |
1032 | } | |
2bbd3819 RS |
1033 | \f |
1034 | /* Allocate hard regs to the pseudo regs used only within block number B. | |
1035 | Only the pseudos that die but once can be handled. */ | |
1036 | ||
1037 | static void | |
1038 | block_alloc (b) | |
1039 | int b; | |
1040 | { | |
1041 | register int i, q; | |
1042 | register rtx insn; | |
1043 | rtx note; | |
1044 | int insn_number = 0; | |
1045 | int insn_count = 0; | |
1046 | int max_uid = get_max_uid (); | |
aabf56ce | 1047 | int *qty_order; |
2bbd3819 RS |
1048 | int no_conflict_combined_regno = -1; |
1049 | ||
1050 | /* Count the instructions in the basic block. */ | |
1051 | ||
3b413743 | 1052 | insn = BLOCK_END (b); |
2bbd3819 RS |
1053 | while (1) |
1054 | { | |
1055 | if (GET_CODE (insn) != NOTE) | |
1056 | if (++insn_count > max_uid) | |
1057 | abort (); | |
3b413743 | 1058 | if (insn == BLOCK_HEAD (b)) |
2bbd3819 RS |
1059 | break; |
1060 | insn = PREV_INSN (insn); | |
1061 | } | |
1062 | ||
1063 | /* +2 to leave room for a post_mark_life at the last insn and for | |
1064 | the birth of a CLOBBER in the first insn. */ | |
ff154f78 MM |
1065 | regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2), |
1066 | sizeof (HARD_REG_SET)); | |
2bbd3819 RS |
1067 | |
1068 | /* Initialize table of hardware registers currently live. */ | |
1069 | ||
e881bb1b | 1070 | REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start); |
2bbd3819 RS |
1071 | |
1072 | /* This loop scans the instructions of the basic block | |
1073 | and assigns quantities to registers. | |
1074 | It computes which registers to tie. */ | |
1075 | ||
3b413743 | 1076 | insn = BLOCK_HEAD (b); |
2bbd3819 RS |
1077 | while (1) |
1078 | { | |
2bbd3819 RS |
1079 | if (GET_CODE (insn) != NOTE) |
1080 | insn_number++; | |
1081 | ||
1082 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1083 | { | |
1084 | register rtx link, set; | |
1085 | register int win = 0; | |
a544cfd2 | 1086 | register rtx r0, r1 = NULL_RTX; |
2bbd3819 RS |
1087 | int combined_regno = -1; |
1088 | int i; | |
2bbd3819 RS |
1089 | |
1090 | this_insn_number = insn_number; | |
1091 | this_insn = insn; | |
1092 | ||
0a578fee | 1093 | extract_insn (insn); |
2bbd3819 RS |
1094 | which_alternative = -1; |
1095 | ||
1096 | /* Is this insn suitable for tying two registers? | |
1097 | If so, try doing that. | |
1098 | Suitable insns are those with at least two operands and where | |
1099 | operand 0 is an output that is a register that is not | |
1100 | earlyclobber. | |
7aba0f0b RK |
1101 | |
1102 | We can tie operand 0 with some operand that dies in this insn. | |
1103 | First look for operands that are required to be in the same | |
1104 | register as operand 0. If we find such, only try tying that | |
1105 | operand or one that can be put into that operand if the | |
1106 | operation is commutative. If we don't find an operand | |
1107 | that is required to be in the same register as operand 0, | |
1108 | we can tie with any operand. | |
1109 | ||
2bbd3819 RS |
1110 | Subregs in place of regs are also ok. |
1111 | ||
1112 | If tying is done, WIN is set nonzero. */ | |
1113 | ||
d29c259b RH |
1114 | if (optimize |
1115 | && recog_data.n_operands > 1 | |
1ccbefce | 1116 | && recog_data.constraints[0][0] == '=' |
19af6455 | 1117 | && recog_data.constraints[0][1] != '&') |
2bbd3819 | 1118 | { |
3061cc54 | 1119 | /* If non-negative, is an operand that must match operand 0. */ |
7aba0f0b | 1120 | int must_match_0 = -1; |
3061cc54 RK |
1121 | /* Counts number of alternatives that require a match with |
1122 | operand 0. */ | |
1123 | int n_matching_alts = 0; | |
7aba0f0b | 1124 | |
1ccbefce | 1125 | for (i = 1; i < recog_data.n_operands; i++) |
3061cc54 | 1126 | { |
1ccbefce | 1127 | const char *p = recog_data.constraints[i]; |
3061cc54 RK |
1128 | int this_match = (requires_inout (p)); |
1129 | ||
1130 | n_matching_alts += this_match; | |
1ccbefce | 1131 | if (this_match == recog_data.n_alternatives) |
3061cc54 RK |
1132 | must_match_0 = i; |
1133 | } | |
2bbd3819 | 1134 | |
1ccbefce RH |
1135 | r0 = recog_data.operand[0]; |
1136 | for (i = 1; i < recog_data.n_operands; i++) | |
2bbd3819 | 1137 | { |
7aba0f0b RK |
1138 | /* Skip this operand if we found an operand that |
1139 | must match operand 0 and this operand isn't it | |
1140 | and can't be made to be it by commutativity. */ | |
1141 | ||
1142 | if (must_match_0 >= 0 && i != must_match_0 | |
1143 | && ! (i == must_match_0 + 1 | |
1ccbefce | 1144 | && recog_data.constraints[i-1][0] == '%') |
7aba0f0b | 1145 | && ! (i == must_match_0 - 1 |
1ccbefce | 1146 | && recog_data.constraints[i][0] == '%')) |
7aba0f0b | 1147 | continue; |
3061cc54 RK |
1148 | |
1149 | /* Likewise if each alternative has some operand that | |
1150 | must match operand zero. In that case, skip any | |
1151 | operand that doesn't list operand 0 since we know that | |
1152 | the operand always conflicts with operand 0. We | |
1153 | ignore commutatity in this case to keep things simple. */ | |
1ccbefce RH |
1154 | if (n_matching_alts == recog_data.n_alternatives |
1155 | && 0 == requires_inout (recog_data.constraints[i])) | |
3061cc54 | 1156 | continue; |
2bbd3819 | 1157 | |
1ccbefce | 1158 | r1 = recog_data.operand[i]; |
2bbd3819 | 1159 | |
7aba0f0b RK |
1160 | /* If the operand is an address, find a register in it. |
1161 | There may be more than one register, but we only try one | |
1162 | of them. */ | |
19af6455 | 1163 | if (recog_data.constraints[i][0] == 'p') |
7aba0f0b RK |
1164 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) |
1165 | r1 = XEXP (r1, 0); | |
1166 | ||
1167 | if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) | |
1168 | { | |
1169 | /* We have two priorities for hard register preferences. | |
1170 | If we have a move insn or an insn whose first input | |
1171 | can only be in the same register as the output, give | |
1172 | priority to an equivalence found from that insn. */ | |
1173 | int may_save_copy | |
1ccbefce | 1174 | = (r1 == recog_data.operand[i] && must_match_0 >= 0); |
7aba0f0b RK |
1175 | |
1176 | if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) | |
1177 | win = combine_regs (r1, r0, may_save_copy, | |
1178 | insn_number, insn, 0); | |
1179 | } | |
662347c5 JL |
1180 | if (win) |
1181 | break; | |
2bbd3819 RS |
1182 | } |
1183 | } | |
1184 | ||
1185 | /* Recognize an insn sequence with an ultimate result | |
1186 | which can safely overlap one of the inputs. | |
1187 | The sequence begins with a CLOBBER of its result, | |
1188 | and ends with an insn that copies the result to itself | |
1189 | and has a REG_EQUAL note for an equivalent formula. | |
1190 | That note indicates what the inputs are. | |
1191 | The result and the input can overlap if each insn in | |
1192 | the sequence either doesn't mention the input | |
1193 | or has a REG_NO_CONFLICT note to inhibit the conflict. | |
1194 | ||
1195 | We do the combining test at the CLOBBER so that the | |
1196 | destination register won't have had a quantity number | |
1197 | assigned, since that would prevent combining. */ | |
1198 | ||
d29c259b RH |
1199 | if (optimize |
1200 | && GET_CODE (PATTERN (insn)) == CLOBBER | |
2bbd3819 RS |
1201 | && (r0 = XEXP (PATTERN (insn), 0), |
1202 | GET_CODE (r0) == REG) | |
b1ec3c92 | 1203 | && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 |
a6665f8c | 1204 | && XEXP (link, 0) != 0 |
2bbd3819 RS |
1205 | && GET_CODE (XEXP (link, 0)) == INSN |
1206 | && (set = single_set (XEXP (link, 0))) != 0 | |
1207 | && SET_DEST (set) == r0 && SET_SRC (set) == r0 | |
b1ec3c92 CH |
1208 | && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, |
1209 | NULL_RTX)) != 0) | |
2bbd3819 RS |
1210 | { |
1211 | if (r1 = XEXP (note, 0), GET_CODE (r1) == REG | |
1212 | /* Check that we have such a sequence. */ | |
1213 | && no_conflict_p (insn, r0, r1)) | |
1214 | win = combine_regs (r1, r0, 1, insn_number, insn, 1); | |
1215 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' | |
1216 | && (r1 = XEXP (XEXP (note, 0), 0), | |
1217 | GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) | |
1218 | && no_conflict_p (insn, r0, r1)) | |
1219 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1220 | ||
1221 | /* Here we care if the operation to be computed is | |
1222 | commutative. */ | |
1223 | else if ((GET_CODE (XEXP (note, 0)) == EQ | |
1224 | || GET_CODE (XEXP (note, 0)) == NE | |
1225 | || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') | |
1226 | && (r1 = XEXP (XEXP (note, 0), 1), | |
1227 | (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) | |
1228 | && no_conflict_p (insn, r0, r1)) | |
1229 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1230 | ||
1231 | /* If we did combine something, show the register number | |
1232 | in question so that we know to ignore its death. */ | |
1233 | if (win) | |
1234 | no_conflict_combined_regno = REGNO (r1); | |
1235 | } | |
1236 | ||
1237 | /* If registers were just tied, set COMBINED_REGNO | |
1238 | to the number of the register used in this insn | |
1239 | that was tied to the register set in this insn. | |
1240 | This register's qty should not be "killed". */ | |
1241 | ||
1242 | if (win) | |
1243 | { | |
1244 | while (GET_CODE (r1) == SUBREG) | |
1245 | r1 = SUBREG_REG (r1); | |
1246 | combined_regno = REGNO (r1); | |
1247 | } | |
1248 | ||
1249 | /* Mark the death of everything that dies in this instruction, | |
1250 | except for anything that was just combined. */ | |
1251 | ||
1252 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1253 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1254 | && GET_CODE (XEXP (link, 0)) == REG | |
1255 | && combined_regno != REGNO (XEXP (link, 0)) | |
1256 | && (no_conflict_combined_regno != REGNO (XEXP (link, 0)) | |
1257 | || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0)))) | |
1258 | wipe_dead_reg (XEXP (link, 0), 0); | |
1259 | ||
1260 | /* Allocate qty numbers for all registers local to this block | |
1261 | that are born (set) in this instruction. | |
1262 | A pseudo that already has a qty is not changed. */ | |
1263 | ||
84832317 | 1264 | note_stores (PATTERN (insn), reg_is_set, NULL); |
2bbd3819 RS |
1265 | |
1266 | /* If anything is set in this insn and then unused, mark it as dying | |
1267 | after this insn, so it will conflict with our outputs. This | |
1268 | can't match with something that combined, and it doesn't matter | |
1269 | if it did. Do this after the calls to reg_is_set since these | |
1270 | die after, not during, the current insn. */ | |
1271 | ||
1272 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1273 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
1274 | && GET_CODE (XEXP (link, 0)) == REG) | |
1275 | wipe_dead_reg (XEXP (link, 0), 1); | |
1276 | ||
2bbd3819 RS |
1277 | /* If this is an insn that has a REG_RETVAL note pointing at a |
1278 | CLOBBER insn, we have reached the end of a REG_NO_CONFLICT | |
1279 | block, so clear any register number that combined within it. */ | |
b1ec3c92 | 1280 | if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 |
2bbd3819 RS |
1281 | && GET_CODE (XEXP (note, 0)) == INSN |
1282 | && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) | |
1283 | no_conflict_combined_regno = -1; | |
1284 | } | |
1285 | ||
1286 | /* Set the registers live after INSN_NUMBER. Note that we never | |
1287 | record the registers live before the block's first insn, since no | |
1288 | pseudos we care about are live before that insn. */ | |
1289 | ||
1290 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); | |
1291 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); | |
1292 | ||
3b413743 | 1293 | if (insn == BLOCK_END (b)) |
2bbd3819 RS |
1294 | break; |
1295 | ||
1296 | insn = NEXT_INSN (insn); | |
1297 | } | |
1298 | ||
1299 | /* Now every register that is local to this basic block | |
1300 | should have been given a quantity, or else -1 meaning ignore it. | |
1301 | Every quantity should have a known birth and death. | |
1302 | ||
51b86d8b RK |
1303 | Order the qtys so we assign them registers in order of the |
1304 | number of suggested registers they need so we allocate those with | |
1305 | the most restrictive needs first. */ | |
2bbd3819 | 1306 | |
ff154f78 | 1307 | qty_order = (int *) xmalloc (next_qty * sizeof (int)); |
2bbd3819 RS |
1308 | for (i = 0; i < next_qty; i++) |
1309 | qty_order[i] = i; | |
1310 | ||
1311 | #define EXCHANGE(I1, I2) \ | |
1312 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1313 | ||
1314 | switch (next_qty) | |
1315 | { | |
1316 | case 3: | |
1317 | /* Make qty_order[2] be the one to allocate last. */ | |
51b86d8b | 1318 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 | 1319 | EXCHANGE (0, 1); |
51b86d8b | 1320 | if (qty_sugg_compare (1, 2) > 0) |
2bbd3819 RS |
1321 | EXCHANGE (2, 1); |
1322 | ||
0f41302f | 1323 | /* ... Fall through ... */ |
2bbd3819 RS |
1324 | case 2: |
1325 | /* Put the best one to allocate in qty_order[0]. */ | |
51b86d8b | 1326 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 RS |
1327 | EXCHANGE (0, 1); |
1328 | ||
0f41302f | 1329 | /* ... Fall through ... */ |
2bbd3819 RS |
1330 | |
1331 | case 1: | |
1332 | case 0: | |
1333 | /* Nothing to do here. */ | |
1334 | break; | |
1335 | ||
1336 | default: | |
51b86d8b | 1337 | qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); |
2bbd3819 RS |
1338 | } |
1339 | ||
1340 | /* Try to put each quantity in a suggested physical register, if it has one. | |
1341 | This may cause registers to be allocated that otherwise wouldn't be, but | |
1342 | this seems acceptable in local allocation (unlike global allocation). */ | |
1343 | for (i = 0; i < next_qty; i++) | |
1344 | { | |
1345 | q = qty_order[i]; | |
51b86d8b | 1346 | if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) |
a1ed7bdb JH |
1347 | qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q, |
1348 | 0, 1, qty[q].birth, qty[q].death); | |
2bbd3819 | 1349 | else |
a1ed7bdb | 1350 | qty[q].phys_reg = -1; |
2bbd3819 RS |
1351 | } |
1352 | ||
51b86d8b RK |
1353 | /* Order the qtys so we assign them registers in order of |
1354 | decreasing length of life. Normally call qsort, but if we | |
1355 | have only a very small number of quantities, sort them ourselves. */ | |
1356 | ||
1357 | for (i = 0; i < next_qty; i++) | |
1358 | qty_order[i] = i; | |
1359 | ||
1360 | #define EXCHANGE(I1, I2) \ | |
1361 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1362 | ||
1363 | switch (next_qty) | |
1364 | { | |
1365 | case 3: | |
1366 | /* Make qty_order[2] be the one to allocate last. */ | |
1367 | if (qty_compare (0, 1) > 0) | |
1368 | EXCHANGE (0, 1); | |
1369 | if (qty_compare (1, 2) > 0) | |
1370 | EXCHANGE (2, 1); | |
1371 | ||
0f41302f | 1372 | /* ... Fall through ... */ |
51b86d8b RK |
1373 | case 2: |
1374 | /* Put the best one to allocate in qty_order[0]. */ | |
1375 | if (qty_compare (0, 1) > 0) | |
1376 | EXCHANGE (0, 1); | |
1377 | ||
0f41302f | 1378 | /* ... Fall through ... */ |
51b86d8b RK |
1379 | |
1380 | case 1: | |
1381 | case 0: | |
1382 | /* Nothing to do here. */ | |
1383 | break; | |
1384 | ||
1385 | default: | |
1386 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); | |
1387 | } | |
1388 | ||
2bbd3819 RS |
1389 | /* Now for each qty that is not a hardware register, |
1390 | look for a hardware register to put it in. | |
1391 | First try the register class that is cheapest for this qty, | |
1392 | if there is more than one class. */ | |
1393 | ||
1394 | for (i = 0; i < next_qty; i++) | |
1395 | { | |
1396 | q = qty_order[i]; | |
a1ed7bdb | 1397 | if (qty[q].phys_reg < 0) |
2bbd3819 | 1398 | { |
624a8b3a JL |
1399 | #ifdef INSN_SCHEDULING |
1400 | /* These values represent the adjusted lifetime of a qty so | |
1401 | that it conflicts with qtys which appear near the start/end | |
1402 | of this qty's lifetime. | |
1403 | ||
1404 | The purpose behind extending the lifetime of this qty is to | |
1405 | discourage the register allocator from creating false | |
1406 | dependencies. | |
1407 | ||
996e9683 JL |
1408 | The adjustment value is choosen to indicate that this qty |
1409 | conflicts with all the qtys in the instructions immediately | |
624a8b3a JL |
1410 | before and after the lifetime of this qty. |
1411 | ||
1412 | Experiments have shown that higher values tend to hurt | |
1413 | overall code performance. | |
1414 | ||
1415 | If allocation using the extended lifetime fails we will try | |
1416 | again with the qty's unadjusted lifetime. */ | |
a1ed7bdb | 1417 | int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2); |
996e9683 | 1418 | int fake_death = MIN (insn_number * 2 + 1, |
a1ed7bdb | 1419 | qty[q].death + 2 - qty[q].death % 2); |
624a8b3a JL |
1420 | #endif |
1421 | ||
2bbd3819 RS |
1422 | if (N_REG_CLASSES > 1) |
1423 | { | |
624a8b3a JL |
1424 | #ifdef INSN_SCHEDULING |
1425 | /* We try to avoid using hard registers allocated to qtys which | |
1426 | are born immediately after this qty or die immediately before | |
1427 | this qty. | |
1428 | ||
1429 | This optimization is only appropriate when we will run | |
1430 | a scheduling pass after reload and we are not optimizing | |
1431 | for code size. */ | |
c358412f JL |
1432 | if (flag_schedule_insns_after_reload |
1433 | && !optimize_size | |
1434 | && !SMALL_REGISTER_CLASSES) | |
624a8b3a JL |
1435 | { |
1436 | ||
a1ed7bdb JH |
1437 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
1438 | qty[q].mode, q, 0, 0, | |
624a8b3a | 1439 | fake_birth, fake_death); |
a1ed7bdb | 1440 | if (qty[q].phys_reg >= 0) |
624a8b3a JL |
1441 | continue; |
1442 | } | |
1443 | #endif | |
a1ed7bdb JH |
1444 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
1445 | qty[q].mode, q, 0, 0, | |
1446 | qty[q].birth, qty[q].death); | |
1447 | if (qty[q].phys_reg >= 0) | |
2bbd3819 RS |
1448 | continue; |
1449 | } | |
1450 | ||
624a8b3a JL |
1451 | #ifdef INSN_SCHEDULING |
1452 | /* Similarly, avoid false dependencies. */ | |
c358412f JL |
1453 | if (flag_schedule_insns_after_reload |
1454 | && !optimize_size | |
1455 | && !SMALL_REGISTER_CLASSES | |
a1ed7bdb JH |
1456 | && qty[q].alternate_class != NO_REGS) |
1457 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1458 | qty[q].mode, q, 0, 0, | |
624a8b3a JL |
1459 | fake_birth, fake_death); |
1460 | #endif | |
a1ed7bdb JH |
1461 | if (qty[q].alternate_class != NO_REGS) |
1462 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1463 | qty[q].mode, q, 0, 0, | |
1464 | qty[q].birth, qty[q].death); | |
2bbd3819 RS |
1465 | } |
1466 | } | |
1467 | ||
1468 | /* Now propagate the register assignments | |
1469 | to the pseudo regs belonging to the qtys. */ | |
1470 | ||
1471 | for (q = 0; q < next_qty; q++) | |
a1ed7bdb | 1472 | if (qty[q].phys_reg >= 0) |
2bbd3819 | 1473 | { |
a1ed7bdb JH |
1474 | for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i]) |
1475 | reg_renumber[i] = qty[q].phys_reg + reg_offset[i]; | |
2bbd3819 | 1476 | } |
ff154f78 MM |
1477 | |
1478 | /* Clean up. */ | |
1479 | free (regs_live_at); | |
1480 | free (qty_order); | |
2bbd3819 RS |
1481 | } |
1482 | \f | |
1483 | /* Compare two quantities' priority for getting real registers. | |
1484 | We give shorter-lived quantities higher priority. | |
6dc42e49 RS |
1485 | Quantities with more references are also preferred, as are quantities that |
1486 | require multiple registers. This is the identical prioritization as | |
2bbd3819 RS |
1487 | done by global-alloc. |
1488 | ||
1489 | We used to give preference to registers with *longer* lives, but using | |
1490 | the same algorithm in both local- and global-alloc can speed up execution | |
1491 | of some programs by as much as a factor of three! */ | |
1492 | ||
2f23fcc9 RK |
1493 | /* Note that the quotient will never be bigger than |
1494 | the value of floor_log2 times the maximum number of | |
1495 | times a register can occur in one insn (surely less than 100). | |
1496 | Multiplying this by 10000 can't overflow. | |
1497 | QTY_CMP_PRI is also used by qty_sugg_compare. */ | |
1498 | ||
1499 | #define QTY_CMP_PRI(q) \ | |
a1ed7bdb JH |
1500 | ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \ |
1501 | / (qty[q].death - qty[q].birth)) * 10000)) | |
2f23fcc9 | 1502 | |
2bbd3819 RS |
1503 | static int |
1504 | qty_compare (q1, q2) | |
1505 | int q1, q2; | |
1506 | { | |
2f23fcc9 | 1507 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
2bbd3819 RS |
1508 | } |
1509 | ||
1510 | static int | |
2f23fcc9 | 1511 | qty_compare_1 (q1p, q2p) |
e1b6684c KG |
1512 | const PTR q1p; |
1513 | const PTR q2p; | |
2bbd3819 | 1514 | { |
ec0ce6e2 | 1515 | register int q1 = *(const int *)q1p, q2 = *(const int *)q2p; |
2f23fcc9 RK |
1516 | register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
1517 | ||
1518 | if (tem != 0) | |
1519 | return tem; | |
1520 | ||
2bbd3819 RS |
1521 | /* If qtys are equally good, sort by qty number, |
1522 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1523 | return q1 - q2; |
2bbd3819 RS |
1524 | } |
1525 | \f | |
51b86d8b RK |
1526 | /* Compare two quantities' priority for getting real registers. This version |
1527 | is called for quantities that have suggested hard registers. First priority | |
1528 | goes to quantities that have copy preferences, then to those that have | |
1529 | normal preferences. Within those groups, quantities with the lower | |
9faa82d8 | 1530 | number of preferences have the highest priority. Of those, we use the same |
51b86d8b RK |
1531 | algorithm as above. */ |
1532 | ||
2f23fcc9 RK |
1533 | #define QTY_CMP_SUGG(q) \ |
1534 | (qty_phys_num_copy_sugg[q] \ | |
1535 | ? qty_phys_num_copy_sugg[q] \ | |
1536 | : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER) | |
1537 | ||
51b86d8b RK |
1538 | static int |
1539 | qty_sugg_compare (q1, q2) | |
1540 | int q1, q2; | |
1541 | { | |
2f23fcc9 RK |
1542 | register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
1543 | ||
1544 | if (tem != 0) | |
1545 | return tem; | |
51b86d8b | 1546 | |
2f23fcc9 | 1547 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
51b86d8b RK |
1548 | } |
1549 | ||
1550 | static int | |
2f23fcc9 | 1551 | qty_sugg_compare_1 (q1p, q2p) |
e1b6684c KG |
1552 | const PTR q1p; |
1553 | const PTR q2p; | |
51b86d8b | 1554 | { |
ec0ce6e2 | 1555 | register int q1 = *(const int *)q1p, q2 = *(const int *)q2p; |
2f23fcc9 RK |
1556 | register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
1557 | ||
1558 | if (tem != 0) | |
1559 | return tem; | |
1560 | ||
1561 | tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
1562 | if (tem != 0) | |
1563 | return tem; | |
51b86d8b RK |
1564 | |
1565 | /* If qtys are equally good, sort by qty number, | |
1566 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1567 | return q1 - q2; |
51b86d8b | 1568 | } |
2f23fcc9 RK |
1569 | |
1570 | #undef QTY_CMP_SUGG | |
1571 | #undef QTY_CMP_PRI | |
51b86d8b | 1572 | \f |
2bbd3819 RS |
1573 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. |
1574 | Returns 1 if have done so, or 0 if cannot. | |
1575 | ||
1576 | Combining registers means marking them as having the same quantity | |
1577 | and adjusting the offsets within the quantity if either of | |
1578 | them is a SUBREG). | |
1579 | ||
1580 | We don't actually combine a hard reg with a pseudo; instead | |
1581 | we just record the hard reg as the suggestion for the pseudo's quantity. | |
1582 | If we really combined them, we could lose if the pseudo lives | |
1583 | across an insn that clobbers the hard reg (eg, movstr). | |
1584 | ||
1585 | ALREADY_DEAD is non-zero if USEDREG is known to be dead even though | |
1586 | there is no REG_DEAD note on INSN. This occurs during the processing | |
1587 | of REG_NO_CONFLICT blocks. | |
1588 | ||
1589 | MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to | |
1590 | SETREG or if the input and output must share a register. | |
1591 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. | |
1592 | ||
1593 | There are elaborate checks for the validity of combining. */ | |
1594 | ||
1595 | ||
1596 | static int | |
1597 | combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) | |
1598 | rtx usedreg, setreg; | |
1599 | int may_save_copy; | |
1600 | int insn_number; | |
1601 | rtx insn; | |
1602 | int already_dead; | |
1603 | { | |
1604 | register int ureg, sreg; | |
1605 | register int offset = 0; | |
1606 | int usize, ssize; | |
1607 | register int sqty; | |
1608 | ||
1609 | /* Determine the numbers and sizes of registers being used. If a subreg | |
6dc42e49 | 1610 | is present that does not change the entire register, don't consider |
2bbd3819 RS |
1611 | this a copy insn. */ |
1612 | ||
1613 | while (GET_CODE (usedreg) == SUBREG) | |
1614 | { | |
1615 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) | |
1616 | may_save_copy = 0; | |
1617 | offset += SUBREG_WORD (usedreg); | |
1618 | usedreg = SUBREG_REG (usedreg); | |
1619 | } | |
1620 | if (GET_CODE (usedreg) != REG) | |
1621 | return 0; | |
1622 | ureg = REGNO (usedreg); | |
1623 | usize = REG_SIZE (usedreg); | |
1624 | ||
1625 | while (GET_CODE (setreg) == SUBREG) | |
1626 | { | |
1627 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) | |
1628 | may_save_copy = 0; | |
1629 | offset -= SUBREG_WORD (setreg); | |
1630 | setreg = SUBREG_REG (setreg); | |
1631 | } | |
1632 | if (GET_CODE (setreg) != REG) | |
1633 | return 0; | |
1634 | sreg = REGNO (setreg); | |
1635 | ssize = REG_SIZE (setreg); | |
1636 | ||
1637 | /* If UREG is a pseudo-register that hasn't already been assigned a | |
1638 | quantity number, it means that it is not local to this block or dies | |
1639 | more than once. In either event, we can't do anything with it. */ | |
1640 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) | |
1641 | /* Do not combine registers unless one fits within the other. */ | |
1642 | || (offset > 0 && usize + offset > ssize) | |
1643 | || (offset < 0 && usize + offset < ssize) | |
1644 | /* Do not combine with a smaller already-assigned object | |
0f41302f | 1645 | if that smaller object is already combined with something bigger. */ |
2bbd3819 | 1646 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER |
a1ed7bdb | 1647 | && usize < qty[reg_qty[ureg]].size) |
2bbd3819 RS |
1648 | /* Can't combine if SREG is not a register we can allocate. */ |
1649 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) | |
1650 | /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. | |
1651 | These have already been taken care of. This probably wouldn't | |
1652 | combine anyway, but don't take any chances. */ | |
1653 | || (ureg >= FIRST_PSEUDO_REGISTER | |
1654 | && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) | |
1655 | /* Don't tie something to itself. In most cases it would make no | |
1656 | difference, but it would screw up if the reg being tied to itself | |
1657 | also dies in this insn. */ | |
1658 | || ureg == sreg | |
1659 | /* Don't try to connect two different hardware registers. */ | |
1660 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) | |
49071ddc JW |
1661 | /* Don't use a hard reg that might be spilled. */ |
1662 | || (ureg < FIRST_PSEUDO_REGISTER | |
1663 | && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg))) | |
1664 | || (sreg < FIRST_PSEUDO_REGISTER | |
1665 | && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg))) | |
2bbd3819 RS |
1666 | /* Don't connect two different machine modes if they have different |
1667 | implications as to which registers may be used. */ | |
1668 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) | |
1669 | return 0; | |
1670 | ||
1671 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in | |
1672 | qty_phys_sugg for the pseudo instead of tying them. | |
1673 | ||
1674 | Return "failure" so that the lifespan of UREG is terminated here; | |
1675 | that way the two lifespans will be disjoint and nothing will prevent | |
1676 | the pseudo reg from being given this hard reg. */ | |
1677 | ||
1678 | if (ureg < FIRST_PSEUDO_REGISTER) | |
1679 | { | |
1680 | /* Allocate a quantity number so we have a place to put our | |
1681 | suggestions. */ | |
1682 | if (reg_qty[sreg] == -2) | |
1683 | reg_is_born (setreg, 2 * insn_number); | |
1684 | ||
1685 | if (reg_qty[sreg] >= 0) | |
1686 | { | |
51b86d8b RK |
1687 | if (may_save_copy |
1688 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) | |
2bbd3819 RS |
1689 | { |
1690 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1691 | qty_phys_num_copy_sugg[reg_qty[sreg]]++; |
2bbd3819 | 1692 | } |
51b86d8b | 1693 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) |
2bbd3819 RS |
1694 | { |
1695 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1696 | qty_phys_num_sugg[reg_qty[sreg]]++; |
2bbd3819 RS |
1697 | } |
1698 | } | |
1699 | return 0; | |
1700 | } | |
1701 | ||
1702 | /* Similarly for SREG a hard register and UREG a pseudo register. */ | |
1703 | ||
1704 | if (sreg < FIRST_PSEUDO_REGISTER) | |
1705 | { | |
51b86d8b RK |
1706 | if (may_save_copy |
1707 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) | |
2bbd3819 RS |
1708 | { |
1709 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1710 | qty_phys_num_copy_sugg[reg_qty[ureg]]++; |
2bbd3819 | 1711 | } |
51b86d8b | 1712 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) |
2bbd3819 RS |
1713 | { |
1714 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1715 | qty_phys_num_sugg[reg_qty[ureg]]++; |
2bbd3819 RS |
1716 | } |
1717 | return 0; | |
1718 | } | |
1719 | ||
1720 | /* At this point we know that SREG and UREG are both pseudos. | |
1721 | Do nothing if SREG already has a quantity or is a register that we | |
1722 | don't allocate. */ | |
1723 | if (reg_qty[sreg] >= -1 | |
1724 | /* If we are not going to let any regs live across calls, | |
1725 | don't tie a call-crossing reg to a non-call-crossing reg. */ | |
1726 | || (current_function_has_nonlocal_label | |
b1f21e0a MM |
1727 | && ((REG_N_CALLS_CROSSED (ureg) > 0) |
1728 | != (REG_N_CALLS_CROSSED (sreg) > 0)))) | |
2bbd3819 RS |
1729 | return 0; |
1730 | ||
1731 | /* We don't already know about SREG, so tie it to UREG | |
1732 | if this is the last use of UREG, provided the classes they want | |
1733 | are compatible. */ | |
1734 | ||
1735 | if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) | |
a1ed7bdb | 1736 | && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class)) |
2bbd3819 RS |
1737 | { |
1738 | /* Add SREG to UREG's quantity. */ | |
1739 | sqty = reg_qty[ureg]; | |
1740 | reg_qty[sreg] = sqty; | |
1741 | reg_offset[sreg] = reg_offset[ureg] + offset; | |
a1ed7bdb JH |
1742 | reg_next_in_qty[sreg] = qty[sqty].first_reg; |
1743 | qty[sqty].first_reg = sreg; | |
2bbd3819 | 1744 | |
a1ed7bdb | 1745 | /* If SREG's reg class is smaller, set qty[SQTY].min_class. */ |
2bbd3819 RS |
1746 | update_qty_class (sqty, sreg); |
1747 | ||
1748 | /* Update info about quantity SQTY. */ | |
a1ed7bdb JH |
1749 | qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg); |
1750 | qty[sqty].n_refs += REG_N_REFS (sreg); | |
2bbd3819 RS |
1751 | if (usize < ssize) |
1752 | { | |
1753 | register int i; | |
1754 | ||
a1ed7bdb | 1755 | for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i]) |
2bbd3819 RS |
1756 | reg_offset[i] -= offset; |
1757 | ||
a1ed7bdb JH |
1758 | qty[sqty].size = ssize; |
1759 | qty[sqty].mode = GET_MODE (setreg); | |
2bbd3819 RS |
1760 | } |
1761 | } | |
1762 | else | |
1763 | return 0; | |
1764 | ||
1765 | return 1; | |
1766 | } | |
1767 | \f | |
1768 | /* Return 1 if the preferred class of REG allows it to be tied | |
1769 | to a quantity or register whose class is CLASS. | |
1770 | True if REG's reg class either contains or is contained in CLASS. */ | |
1771 | ||
1772 | static int | |
1773 | reg_meets_class_p (reg, class) | |
1774 | int reg; | |
1775 | enum reg_class class; | |
1776 | { | |
1777 | register enum reg_class rclass = reg_preferred_class (reg); | |
1778 | return (reg_class_subset_p (rclass, class) | |
1779 | || reg_class_subset_p (class, rclass)); | |
1780 | } | |
1781 | ||
a1ed7bdb | 1782 | /* Update the class of QTYNO assuming that REG is being tied to it. */ |
2bbd3819 RS |
1783 | |
1784 | static void | |
a1ed7bdb JH |
1785 | update_qty_class (qtyno, reg) |
1786 | int qtyno; | |
2bbd3819 RS |
1787 | int reg; |
1788 | { | |
1789 | enum reg_class rclass = reg_preferred_class (reg); | |
a1ed7bdb JH |
1790 | if (reg_class_subset_p (rclass, qty[qtyno].min_class)) |
1791 | qty[qtyno].min_class = rclass; | |
e4600702 RK |
1792 | |
1793 | rclass = reg_alternate_class (reg); | |
a1ed7bdb JH |
1794 | if (reg_class_subset_p (rclass, qty[qtyno].alternate_class)) |
1795 | qty[qtyno].alternate_class = rclass; | |
0f64b8f6 | 1796 | |
b1f21e0a | 1797 | if (REG_CHANGES_SIZE (reg)) |
a1ed7bdb | 1798 | qty[qtyno].changes_size = 1; |
2bbd3819 RS |
1799 | } |
1800 | \f | |
1801 | /* Handle something which alters the value of an rtx REG. | |
1802 | ||
1803 | REG is whatever is set or clobbered. SETTER is the rtx that | |
1804 | is modifying the register. | |
1805 | ||
1806 | If it is not really a register, we do nothing. | |
1807 | The file-global variables `this_insn' and `this_insn_number' | |
1808 | carry info from `block_alloc'. */ | |
1809 | ||
1810 | static void | |
84832317 | 1811 | reg_is_set (reg, setter, data) |
2bbd3819 RS |
1812 | rtx reg; |
1813 | rtx setter; | |
84832317 | 1814 | void *data ATTRIBUTE_UNUSED; |
2bbd3819 RS |
1815 | { |
1816 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of | |
1817 | a hard register. These may actually not exist any more. */ | |
1818 | ||
1819 | if (GET_CODE (reg) != SUBREG | |
1820 | && GET_CODE (reg) != REG) | |
1821 | return; | |
1822 | ||
1823 | /* Mark this register as being born. If it is used in a CLOBBER, mark | |
1824 | it as being born halfway between the previous insn and this insn so that | |
1825 | it conflicts with our inputs but not the outputs of the previous insn. */ | |
1826 | ||
1827 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); | |
1828 | } | |
1829 | \f | |
1830 | /* Handle beginning of the life of register REG. | |
1831 | BIRTH is the index at which this is happening. */ | |
1832 | ||
1833 | static void | |
1834 | reg_is_born (reg, birth) | |
1835 | rtx reg; | |
1836 | int birth; | |
1837 | { | |
1838 | register int regno; | |
1839 | ||
1840 | if (GET_CODE (reg) == SUBREG) | |
1841 | regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg); | |
1842 | else | |
1843 | regno = REGNO (reg); | |
1844 | ||
1845 | if (regno < FIRST_PSEUDO_REGISTER) | |
1846 | { | |
1847 | mark_life (regno, GET_MODE (reg), 1); | |
1848 | ||
1849 | /* If the register was to have been born earlier that the present | |
1850 | insn, mark it as live where it is actually born. */ | |
1851 | if (birth < 2 * this_insn_number) | |
1852 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); | |
1853 | } | |
1854 | else | |
1855 | { | |
1856 | if (reg_qty[regno] == -2) | |
1857 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); | |
1858 | ||
1859 | /* If this register has a quantity number, show that it isn't dead. */ | |
1860 | if (reg_qty[regno] >= 0) | |
a1ed7bdb | 1861 | qty[reg_qty[regno]].death = -1; |
2bbd3819 RS |
1862 | } |
1863 | } | |
1864 | ||
1865 | /* Record the death of REG in the current insn. If OUTPUT_P is non-zero, | |
1866 | REG is an output that is dying (i.e., it is never used), otherwise it | |
333e0f7d RS |
1867 | is an input (the normal case). |
1868 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ | |
2bbd3819 RS |
1869 | |
1870 | static void | |
1871 | wipe_dead_reg (reg, output_p) | |
1872 | register rtx reg; | |
1873 | int output_p; | |
1874 | { | |
1875 | register int regno = REGNO (reg); | |
1876 | ||
333e0f7d RS |
1877 | /* If this insn has multiple results, |
1878 | and the dead reg is used in one of the results, | |
1879 | extend its life to after this insn, | |
941c63ac JL |
1880 | so it won't get allocated together with any other result of this insn. |
1881 | ||
1882 | It is unsafe to use !single_set here since it will ignore an unused | |
1883 | output. Just because an output is unused does not mean the compiler | |
1884 | can assume the side effect will not occur. Consider if REG appears | |
1885 | in the address of an output and we reload the output. If we allocate | |
1886 | REG to the same hard register as an unused output we could set the hard | |
1887 | register before the output reload insn. */ | |
333e0f7d | 1888 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL |
941c63ac | 1889 | && multiple_sets (this_insn)) |
333e0f7d RS |
1890 | { |
1891 | int i; | |
1892 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) | |
1893 | { | |
1894 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); | |
1895 | if (GET_CODE (set) == SET | |
1896 | && GET_CODE (SET_DEST (set)) != REG | |
1897 | && !rtx_equal_p (reg, SET_DEST (set)) | |
1898 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1899 | output_p = 1; | |
1900 | } | |
1901 | } | |
1902 | ||
c182df0b RK |
1903 | /* If this register is used in an auto-increment address, then extend its |
1904 | life to after this insn, so that it won't get allocated together with | |
1905 | the result of this insn. */ | |
1906 | if (! output_p && find_regno_note (this_insn, REG_INC, regno)) | |
1907 | output_p = 1; | |
1908 | ||
2bbd3819 RS |
1909 | if (regno < FIRST_PSEUDO_REGISTER) |
1910 | { | |
1911 | mark_life (regno, GET_MODE (reg), 0); | |
1912 | ||
1913 | /* If a hard register is dying as an output, mark it as in use at | |
1914 | the beginning of this insn (the above statement would cause this | |
1915 | not to happen). */ | |
1916 | if (output_p) | |
1917 | post_mark_life (regno, GET_MODE (reg), 1, | |
1918 | 2 * this_insn_number, 2 * this_insn_number+ 1); | |
1919 | } | |
1920 | ||
1921 | else if (reg_qty[regno] >= 0) | |
a1ed7bdb | 1922 | qty[reg_qty[regno]].death = 2 * this_insn_number + output_p; |
2bbd3819 RS |
1923 | } |
1924 | \f | |
1925 | /* Find a block of SIZE words of hard regs in reg_class CLASS | |
1926 | that can hold something of machine-mode MODE | |
1927 | (but actually we test only the first of the block for holding MODE) | |
1928 | and still free between insn BORN_INDEX and insn DEAD_INDEX, | |
1929 | and return the number of the first of them. | |
1930 | Return -1 if such a block cannot be found. | |
a1ed7bdb | 1931 | If QTYNO crosses calls, insist on a register preserved by calls, |
2bbd3819 RS |
1932 | unless ACCEPT_CALL_CLOBBERED is nonzero. |
1933 | ||
1934 | If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested | |
1935 | register is available. If not, return -1. */ | |
1936 | ||
1937 | static int | |
a1ed7bdb | 1938 | find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested, |
2bbd3819 RS |
1939 | born_index, dead_index) |
1940 | enum reg_class class; | |
1941 | enum machine_mode mode; | |
a1ed7bdb | 1942 | int qtyno; |
2bbd3819 RS |
1943 | int accept_call_clobbered; |
1944 | int just_try_suggested; | |
2bbd3819 RS |
1945 | int born_index, dead_index; |
1946 | { | |
1947 | register int i, ins; | |
1948 | #ifdef HARD_REG_SET | |
1949 | register /* Declare it register if it's a scalar. */ | |
1950 | #endif | |
1951 | HARD_REG_SET used, first_used; | |
1952 | #ifdef ELIMINABLE_REGS | |
1953 | static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; | |
1954 | #endif | |
1955 | ||
1956 | /* Validate our parameters. */ | |
1957 | if (born_index < 0 || born_index > dead_index) | |
1958 | abort (); | |
1959 | ||
1960 | /* Don't let a pseudo live in a reg across a function call | |
1961 | if we might get a nonlocal goto. */ | |
1962 | if (current_function_has_nonlocal_label | |
a1ed7bdb | 1963 | && qty[qtyno].n_calls_crossed > 0) |
2bbd3819 RS |
1964 | return -1; |
1965 | ||
1966 | if (accept_call_clobbered) | |
1967 | COPY_HARD_REG_SET (used, call_fixed_reg_set); | |
a1ed7bdb | 1968 | else if (qty[qtyno].n_calls_crossed == 0) |
2bbd3819 RS |
1969 | COPY_HARD_REG_SET (used, fixed_reg_set); |
1970 | else | |
1971 | COPY_HARD_REG_SET (used, call_used_reg_set); | |
1972 | ||
6cad67d2 | 1973 | if (accept_call_clobbered) |
c09be6c4 | 1974 | IOR_HARD_REG_SET (used, losing_caller_save_reg_set); |
6cad67d2 | 1975 | |
2bbd3819 RS |
1976 | for (ins = born_index; ins < dead_index; ins++) |
1977 | IOR_HARD_REG_SET (used, regs_live_at[ins]); | |
1978 | ||
1979 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); | |
1980 | ||
1981 | /* Don't use the frame pointer reg in local-alloc even if | |
1982 | we may omit the frame pointer, because if we do that and then we | |
1983 | need a frame pointer, reload won't know how to move the pseudo | |
1984 | to another hard reg. It can move only regs made by global-alloc. | |
1985 | ||
1986 | This is true of any register that can be eliminated. */ | |
1987 | #ifdef ELIMINABLE_REGS | |
e51712db | 1988 | for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++) |
2bbd3819 | 1989 | SET_HARD_REG_BIT (used, eliminables[i].from); |
c2618f05 DE |
1990 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
1991 | /* If FRAME_POINTER_REGNUM is not a real register, then protect the one | |
0f41302f | 1992 | that it might be eliminated into. */ |
c2618f05 DE |
1993 | SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); |
1994 | #endif | |
2bbd3819 RS |
1995 | #else |
1996 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); | |
1997 | #endif | |
1998 | ||
0f64b8f6 | 1999 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
a1ed7bdb | 2000 | if (qty[qtyno].changes_size) |
899d4140 | 2001 | IOR_HARD_REG_SET (used, |
0f64b8f6 RK |
2002 | reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]); |
2003 | #endif | |
2004 | ||
2bbd3819 RS |
2005 | /* Normally, the registers that can be used for the first register in |
2006 | a multi-register quantity are the same as those that can be used for | |
2007 | subsequent registers. However, if just trying suggested registers, | |
2008 | restrict our consideration to them. If there are copy-suggested | |
2009 | register, try them. Otherwise, try the arithmetic-suggested | |
2010 | registers. */ | |
2011 | COPY_HARD_REG_SET (first_used, used); | |
2012 | ||
2013 | if (just_try_suggested) | |
2014 | { | |
a1ed7bdb JH |
2015 | if (qty_phys_num_copy_sugg[qtyno] != 0) |
2016 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]); | |
2bbd3819 | 2017 | else |
a1ed7bdb | 2018 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]); |
2bbd3819 RS |
2019 | } |
2020 | ||
2021 | /* If all registers are excluded, we can't do anything. */ | |
2022 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); | |
2023 | ||
2024 | /* If at least one would be suitable, test each hard reg. */ | |
2025 | ||
2026 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2027 | { | |
2028 | #ifdef REG_ALLOC_ORDER | |
2029 | int regno = reg_alloc_order[i]; | |
2030 | #else | |
2031 | int regno = i; | |
2032 | #endif | |
2033 | if (! TEST_HARD_REG_BIT (first_used, regno) | |
1e326708 | 2034 | && HARD_REGNO_MODE_OK (regno, mode) |
a1ed7bdb | 2035 | && (qty[qtyno].n_calls_crossed == 0 |
1e326708 MH |
2036 | || accept_call_clobbered |
2037 | || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
2bbd3819 RS |
2038 | { |
2039 | register int j; | |
2040 | register int size1 = HARD_REGNO_NREGS (regno, mode); | |
2041 | for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); | |
2042 | if (j == size1) | |
2043 | { | |
2044 | /* Mark that this register is in use between its birth and death | |
2045 | insns. */ | |
2046 | post_mark_life (regno, mode, 1, born_index, dead_index); | |
2047 | return regno; | |
2048 | } | |
2049 | #ifndef REG_ALLOC_ORDER | |
2050 | i += j; /* Skip starting points we know will lose */ | |
2051 | #endif | |
2052 | } | |
2053 | } | |
2054 | ||
2055 | fail: | |
2056 | ||
2057 | /* If we are just trying suggested register, we have just tried copy- | |
2058 | suggested registers, and there are arithmetic-suggested registers, | |
2059 | try them. */ | |
2060 | ||
2061 | /* If it would be profitable to allocate a call-clobbered register | |
2062 | and save and restore it around calls, do that. */ | |
a1ed7bdb JH |
2063 | if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0 |
2064 | && qty_phys_num_sugg[qtyno] != 0) | |
2bbd3819 RS |
2065 | { |
2066 | /* Don't try the copy-suggested regs again. */ | |
a1ed7bdb JH |
2067 | qty_phys_num_copy_sugg[qtyno] = 0; |
2068 | return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1, | |
2bbd3819 RS |
2069 | born_index, dead_index); |
2070 | } | |
2071 | ||
e19f5192 RK |
2072 | /* We need not check to see if the current function has nonlocal |
2073 | labels because we don't put any pseudos that are live over calls in | |
2074 | registers in that case. */ | |
2075 | ||
2bbd3819 RS |
2076 | if (! accept_call_clobbered |
2077 | && flag_caller_saves | |
2078 | && ! just_try_suggested | |
a1ed7bdb JH |
2079 | && qty[qtyno].n_calls_crossed != 0 |
2080 | && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs, qty[qtyno].n_calls_crossed)) | |
2bbd3819 | 2081 | { |
a1ed7bdb | 2082 | i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index); |
2bbd3819 RS |
2083 | if (i >= 0) |
2084 | caller_save_needed = 1; | |
2085 | return i; | |
2086 | } | |
2087 | return -1; | |
2088 | } | |
2089 | \f | |
2090 | /* Mark that REGNO with machine-mode MODE is live starting from the current | |
2091 | insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE | |
2092 | is zero). */ | |
2093 | ||
2094 | static void | |
2095 | mark_life (regno, mode, life) | |
2096 | register int regno; | |
2097 | enum machine_mode mode; | |
2098 | int life; | |
2099 | { | |
2100 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2101 | if (life) | |
2102 | while (--j >= 0) | |
2103 | SET_HARD_REG_BIT (regs_live, regno + j); | |
2104 | else | |
2105 | while (--j >= 0) | |
2106 | CLEAR_HARD_REG_BIT (regs_live, regno + j); | |
2107 | } | |
2108 | ||
2109 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE | |
2110 | is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) | |
2111 | to insn number DEATH (exclusive). */ | |
2112 | ||
2113 | static void | |
2114 | post_mark_life (regno, mode, life, birth, death) | |
82c68a78 | 2115 | int regno; |
2bbd3819 | 2116 | enum machine_mode mode; |
82c68a78 | 2117 | int life, birth, death; |
2bbd3819 RS |
2118 | { |
2119 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2120 | #ifdef HARD_REG_SET | |
2121 | register /* Declare it register if it's a scalar. */ | |
2122 | #endif | |
2123 | HARD_REG_SET this_reg; | |
2124 | ||
2125 | CLEAR_HARD_REG_SET (this_reg); | |
2126 | while (--j >= 0) | |
2127 | SET_HARD_REG_BIT (this_reg, regno + j); | |
2128 | ||
2129 | if (life) | |
2130 | while (birth < death) | |
2131 | { | |
2132 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2133 | birth++; | |
2134 | } | |
2135 | else | |
2136 | while (birth < death) | |
2137 | { | |
2138 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2139 | birth++; | |
2140 | } | |
2141 | } | |
2142 | \f | |
2143 | /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 | |
2144 | is the register being clobbered, and R1 is a register being used in | |
2145 | the equivalent expression. | |
2146 | ||
2147 | If R1 dies in the block and has a REG_NO_CONFLICT note on every insn | |
2148 | in which it is used, return 1. | |
2149 | ||
2150 | Otherwise, return 0. */ | |
2151 | ||
2152 | static int | |
2153 | no_conflict_p (insn, r0, r1) | |
272df862 | 2154 | rtx insn, r0 ATTRIBUTE_UNUSED, r1; |
2bbd3819 RS |
2155 | { |
2156 | int ok = 0; | |
b1ec3c92 | 2157 | rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); |
2bbd3819 RS |
2158 | rtx p, last; |
2159 | ||
2160 | /* If R1 is a hard register, return 0 since we handle this case | |
2161 | when we scan the insns that actually use it. */ | |
2162 | ||
2163 | if (note == 0 | |
2164 | || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) | |
2165 | || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG | |
2166 | && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) | |
2167 | return 0; | |
2168 | ||
2169 | last = XEXP (note, 0); | |
2170 | ||
2171 | for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) | |
2172 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
2173 | { | |
2174 | if (find_reg_note (p, REG_DEAD, r1)) | |
2175 | ok = 1; | |
2176 | ||
8bb19658 JW |
2177 | /* There must be a REG_NO_CONFLICT note on every insn, otherwise |
2178 | some earlier optimization pass has inserted instructions into | |
2179 | the sequence, and it is not safe to perform this optimization. | |
2180 | Note that emit_no_conflict_block always ensures that this is | |
2181 | true when these sequences are created. */ | |
2182 | if (! find_reg_note (p, REG_NO_CONFLICT, r1)) | |
2bbd3819 RS |
2183 | return 0; |
2184 | } | |
2185 | ||
2186 | return ok; | |
2187 | } | |
2188 | \f | |
3061cc54 RK |
2189 | /* Return the number of alternatives for which the constraint string P |
2190 | indicates that the operand must be equal to operand 0 and that no register | |
2191 | is acceptable. */ | |
2bbd3819 RS |
2192 | |
2193 | static int | |
3061cc54 | 2194 | requires_inout (p) |
9b3142b3 | 2195 | const char *p; |
2bbd3819 RS |
2196 | { |
2197 | char c; | |
2198 | int found_zero = 0; | |
3061cc54 RK |
2199 | int reg_allowed = 0; |
2200 | int num_matching_alts = 0; | |
2bbd3819 | 2201 | |
51723711 | 2202 | while ((c = *p++)) |
2bbd3819 RS |
2203 | switch (c) |
2204 | { | |
2bbd3819 RS |
2205 | case '=': case '+': case '?': |
2206 | case '#': case '&': case '!': | |
3061cc54 | 2207 | case '*': case '%': |
c5c76735 JL |
2208 | case '1': case '2': case '3': case '4': case '5': |
2209 | case '6': case '7': case '8': case '9': | |
2bbd3819 RS |
2210 | case 'm': case '<': case '>': case 'V': case 'o': |
2211 | case 'E': case 'F': case 'G': case 'H': | |
2212 | case 's': case 'i': case 'n': | |
2213 | case 'I': case 'J': case 'K': case 'L': | |
2214 | case 'M': case 'N': case 'O': case 'P': | |
2215 | #ifdef EXTRA_CONSTRAINT | |
2216 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
2217 | #endif | |
2218 | case 'X': | |
2219 | /* These don't say anything we care about. */ | |
2220 | break; | |
2221 | ||
3061cc54 RK |
2222 | case ',': |
2223 | if (found_zero && ! reg_allowed) | |
2224 | num_matching_alts++; | |
2225 | ||
2226 | found_zero = reg_allowed = 0; | |
2227 | break; | |
2228 | ||
2229 | case '0': | |
2230 | found_zero = 1; | |
2231 | break; | |
2232 | ||
2bbd3819 RS |
2233 | case 'p': |
2234 | case 'g': case 'r': | |
2235 | default: | |
3061cc54 RK |
2236 | reg_allowed = 1; |
2237 | break; | |
2bbd3819 RS |
2238 | } |
2239 | ||
3061cc54 RK |
2240 | if (found_zero && ! reg_allowed) |
2241 | num_matching_alts++; | |
2242 | ||
2243 | return num_matching_alts; | |
2bbd3819 RS |
2244 | } |
2245 | \f | |
2246 | void | |
2247 | dump_local_alloc (file) | |
2248 | FILE *file; | |
2249 | { | |
2250 | register int i; | |
2251 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
2252 | if (reg_renumber[i] != -1) | |
2253 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); | |
2254 | } |