]>
Commit | Line | Data |
---|---|---|
8c660648 | 1 | /* Instruction scheduling pass. |
a5cad800 | 2 | Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc. |
8c660648 JL |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
4 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, but | |
14 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to the Free | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | ||
24 | /* Instruction scheduling pass. | |
25 | ||
26 | This pass implements list scheduling within basic blocks. It is | |
27 | run twice: (1) after flow analysis, but before register allocation, | |
28 | and (2) after register allocation. | |
29 | ||
30 | The first run performs interblock scheduling, moving insns between | |
31 | different blocks in the same "region", and the second runs only | |
32 | basic block scheduling. | |
33 | ||
34 | Interblock motions performed are useful motions and speculative | |
35 | motions, including speculative loads. Motions requiring code | |
36 | duplication are not supported. The identification of motion type | |
37 | and the check for validity of speculative motions requires | |
38 | construction and analysis of the function's control flow graph. | |
39 | The scheduler works as follows: | |
40 | ||
41 | We compute insn priorities based on data dependencies. Flow | |
42 | analysis only creates a fraction of the data-dependencies we must | |
43 | observe: namely, only those dependencies which the combiner can be | |
44 | expected to use. For this pass, we must therefore create the | |
45 | remaining dependencies we need to observe: register dependencies, | |
46 | memory dependencies, dependencies to keep function calls in order, | |
47 | and the dependence between a conditional branch and the setting of | |
48 | condition codes are all dealt with here. | |
49 | ||
50 | The scheduler first traverses the data flow graph, starting with | |
51 | the last instruction, and proceeding to the first, assigning values | |
52 | to insn_priority as it goes. This sorts the instructions | |
53 | topologically by data dependence. | |
54 | ||
55 | Once priorities have been established, we order the insns using | |
56 | list scheduling. This works as follows: starting with a list of | |
57 | all the ready insns, and sorted according to priority number, we | |
58 | schedule the insn from the end of the list by placing its | |
59 | predecessors in the list according to their priority order. We | |
60 | consider this insn scheduled by setting the pointer to the "end" of | |
61 | the list to point to the previous insn. When an insn has no | |
62 | predecessors, we either queue it until sufficient time has elapsed | |
63 | or add it to the ready list. As the instructions are scheduled or | |
64 | when stalls are introduced, the queue advances and dumps insns into | |
65 | the ready list. When all insns down to the lowest priority have | |
66 | been scheduled, the critical path of the basic block has been made | |
67 | as short as possible. The remaining insns are then scheduled in | |
68 | remaining slots. | |
69 | ||
70 | Function unit conflicts are resolved during forward list scheduling | |
71 | by tracking the time when each insn is committed to the schedule | |
72 | and from that, the time the function units it uses must be free. | |
73 | As insns on the ready list are considered for scheduling, those | |
74 | that would result in a blockage of the already committed insns are | |
75 | queued until no blockage will result. | |
76 | ||
77 | The following list shows the order in which we want to break ties | |
78 | among insns in the ready list: | |
79 | ||
80 | 1. choose insn with the longest path to end of bb, ties | |
81 | broken by | |
82 | 2. choose insn with least contribution to register pressure, | |
83 | ties broken by | |
84 | 3. prefer in-block upon interblock motion, ties broken by | |
85 | 4. prefer useful upon speculative motion, ties broken by | |
86 | 5. choose insn with largest control flow probability, ties | |
87 | broken by | |
88 | 6. choose insn with the least dependences upon the previously | |
89 | scheduled insn, or finally | |
2db45993 JL |
90 | 7 choose the insn which has the most insns dependent on it. |
91 | 8. choose insn with lowest UID. | |
8c660648 JL |
92 | |
93 | Memory references complicate matters. Only if we can be certain | |
94 | that memory references are not part of the data dependency graph | |
95 | (via true, anti, or output dependence), can we move operations past | |
96 | memory references. To first approximation, reads can be done | |
97 | independently, while writes introduce dependencies. Better | |
98 | approximations will yield fewer dependencies. | |
99 | ||
100 | Before reload, an extended analysis of interblock data dependences | |
101 | is required for interblock scheduling. This is performed in | |
102 | compute_block_backward_dependences (). | |
103 | ||
104 | Dependencies set up by memory references are treated in exactly the | |
105 | same way as other dependencies, by using LOG_LINKS backward | |
106 | dependences. LOG_LINKS are translated into INSN_DEPEND forward | |
107 | dependences for the purpose of forward list scheduling. | |
108 | ||
109 | Having optimized the critical path, we may have also unduly | |
110 | extended the lifetimes of some registers. If an operation requires | |
111 | that constants be loaded into registers, it is certainly desirable | |
112 | to load those constants as early as necessary, but no earlier. | |
113 | I.e., it will not do to load up a bunch of registers at the | |
114 | beginning of a basic block only to use them at the end, if they | |
115 | could be loaded later, since this may result in excessive register | |
116 | utilization. | |
117 | ||
118 | Note that since branches are never in basic blocks, but only end | |
119 | basic blocks, this pass will not move branches. But that is ok, | |
120 | since we can use GNU's delayed branch scheduling pass to take care | |
121 | of this case. | |
122 | ||
123 | Also note that no further optimizations based on algebraic | |
124 | identities are performed, so this pass would be a good one to | |
125 | perform instruction splitting, such as breaking up a multiply | |
126 | instruction into shifts and adds where that is profitable. | |
127 | ||
128 | Given the memory aliasing analysis that this pass should perform, | |
129 | it should be possible to remove redundant stores to memory, and to | |
130 | load values from registers instead of hitting memory. | |
131 | ||
132 | Before reload, speculative insns are moved only if a 'proof' exists | |
133 | that no exception will be caused by this, and if no live registers | |
134 | exist that inhibit the motion (live registers constraints are not | |
135 | represented by data dependence edges). | |
136 | ||
137 | This pass must update information that subsequent passes expect to | |
138 | be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths, | |
3b413743 RH |
139 | reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD, |
140 | BLOCK_END. | |
8c660648 JL |
141 | |
142 | The information in the line number notes is carefully retained by | |
143 | this pass. Notes that refer to the starting and ending of | |
144 | exception regions are also carefully retained by this pass. All | |
145 | other NOTE insns are grouped in their same relative order at the | |
146 | beginning of basic blocks and regions that have been scheduled. | |
147 | ||
148 | The main entry point for this pass is schedule_insns(), called for | |
149 | each function. The work of the scheduler is organized in three | |
150 | levels: (1) function level: insns are subject to splitting, | |
151 | control-flow-graph is constructed, regions are computed (after | |
152 | reload, each region is of one block), (2) region level: control | |
153 | flow graph attributes required for interblock scheduling are | |
154 | computed (dominators, reachability, etc.), data dependences and | |
155 | priorities are computed, and (3) block level: insns in the block | |
156 | are actually scheduled. */ | |
157 | \f | |
8c660648 | 158 | #include "config.h" |
5835e573 | 159 | #include "system.h" |
01198c2f | 160 | #include "toplev.h" |
8c660648 | 161 | #include "rtl.h" |
6baf1cc8 | 162 | #include "tm_p.h" |
8c660648 JL |
163 | #include "basic-block.h" |
164 | #include "regs.h" | |
49ad7cfa | 165 | #include "function.h" |
8c660648 JL |
166 | #include "hard-reg-set.h" |
167 | #include "flags.h" | |
168 | #include "insn-config.h" | |
169 | #include "insn-attr.h" | |
170 | #include "except.h" | |
487a6e06 | 171 | #include "toplev.h" |
79c9824e | 172 | #include "recog.h" |
8c660648 JL |
173 | |
174 | extern char *reg_known_equiv_p; | |
175 | extern rtx *reg_known_value; | |
176 | ||
177 | #ifdef INSN_SCHEDULING | |
178 | ||
8c660648 JL |
179 | /* target_units bitmask has 1 for each unit in the cpu. It should be |
180 | possible to compute this variable from the machine description. | |
63de6c74 | 181 | But currently it is computed by examining the insn list. Since |
8c660648 JL |
182 | this is only needed for visualization, it seems an acceptable |
183 | solution. (For understanding the mapping of bits to units, see | |
63de6c74 | 184 | definition of function_units[] in "insn-attrtab.c".) */ |
8c660648 | 185 | |
61822835 | 186 | static int target_units = 0; |
8c660648 JL |
187 | |
188 | /* issue_rate is the number of insns that can be scheduled in the same | |
189 | machine cycle. It can be defined in the config/mach/mach.h file, | |
190 | otherwise we set it to 1. */ | |
191 | ||
192 | static int issue_rate; | |
193 | ||
62d65906 JL |
194 | #ifndef ISSUE_RATE |
195 | #define ISSUE_RATE 1 | |
8c660648 JL |
196 | #endif |
197 | ||
cc132865 | 198 | /* sched-verbose controls the amount of debugging output the |
8c660648 JL |
199 | scheduler prints. It is controlled by -fsched-verbose-N: |
200 | N>0 and no -DSR : the output is directed to stderr. | |
201 | N>=10 will direct the printouts to stderr (regardless of -dSR). | |
202 | N=1: same as -dSR. | |
203 | N=2: bb's probabilities, detailed ready list info, unit/insn info. | |
204 | N=3: rtl at abort point, control-flow, regions info. | |
cc132865 | 205 | N=5: dependences info. */ |
8c660648 JL |
206 | |
207 | #define MAX_RGN_BLOCKS 10 | |
208 | #define MAX_RGN_INSNS 100 | |
209 | ||
8c660648 JL |
210 | static int sched_verbose_param = 0; |
211 | static int sched_verbose = 0; | |
8c660648 | 212 | |
63de6c74 | 213 | /* nr_inter/spec counts interblock/speculative motion for the function. */ |
8c660648 JL |
214 | static int nr_inter, nr_spec; |
215 | ||
216 | ||
63de6c74 | 217 | /* Debugging file. All printouts are sent to dump, which is always set, |
8c660648 JL |
218 | either to stderr, or to the dump listing file (-dRS). */ |
219 | static FILE *dump = 0; | |
220 | ||
221 | /* fix_sched_param() is called from toplev.c upon detection | |
222 | of the -fsched-***-N options. */ | |
223 | ||
224 | void | |
225 | fix_sched_param (param, val) | |
5f06c983 | 226 | const char *param, *val; |
8c660648 | 227 | { |
cc132865 | 228 | if (!strcmp (param, "verbose")) |
8c660648 | 229 | sched_verbose_param = atoi (val); |
8c660648 JL |
230 | else |
231 | warning ("fix_sched_param: unknown param: %s", param); | |
232 | } | |
233 | ||
234 | ||
235 | /* Arrays set up by scheduling for the same respective purposes as | |
236 | similar-named arrays set up by flow analysis. We work with these | |
237 | arrays during the scheduling pass so we can compare values against | |
238 | unscheduled code. | |
239 | ||
240 | Values of these arrays are copied at the end of this pass into the | |
241 | arrays set up by flow analysis. */ | |
242 | static int *sched_reg_n_calls_crossed; | |
243 | static int *sched_reg_live_length; | |
244 | static int *sched_reg_basic_block; | |
245 | ||
246 | /* We need to know the current block number during the post scheduling | |
247 | update of live register information so that we can also update | |
248 | REG_BASIC_BLOCK if a register changes blocks. */ | |
249 | static int current_block_num; | |
250 | ||
251 | /* Element N is the next insn that sets (hard or pseudo) register | |
252 | N within the current basic block; or zero, if there is no | |
253 | such insn. Needed for new registers which may be introduced | |
254 | by splitting insns. */ | |
255 | static rtx *reg_last_uses; | |
256 | static rtx *reg_last_sets; | |
28c95eff | 257 | static rtx *reg_last_clobbers; |
8c660648 | 258 | static regset reg_pending_sets; |
28c95eff | 259 | static regset reg_pending_clobbers; |
8c660648 JL |
260 | static int reg_pending_sets_all; |
261 | ||
262 | /* Vector indexed by INSN_UID giving the original ordering of the insns. */ | |
263 | static int *insn_luid; | |
264 | #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)]) | |
265 | ||
266 | /* Vector indexed by INSN_UID giving each instruction a priority. */ | |
267 | static int *insn_priority; | |
268 | #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)]) | |
269 | ||
270 | static short *insn_costs; | |
271 | #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)] | |
272 | ||
273 | /* Vector indexed by INSN_UID giving an encoding of the function units | |
274 | used. */ | |
275 | static short *insn_units; | |
276 | #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)] | |
277 | ||
63de6c74 MH |
278 | /* Vector indexed by INSN_UID giving each instruction a |
279 | register-weight. This weight is an estimation of the insn | |
280 | contribution to registers pressure. */ | |
8c660648 JL |
281 | static int *insn_reg_weight; |
282 | #define INSN_REG_WEIGHT(INSN) (insn_reg_weight[INSN_UID (INSN)]) | |
283 | ||
284 | /* Vector indexed by INSN_UID giving list of insns which | |
285 | depend upon INSN. Unlike LOG_LINKS, it represents forward dependences. */ | |
286 | static rtx *insn_depend; | |
287 | #define INSN_DEPEND(INSN) insn_depend[INSN_UID (INSN)] | |
288 | ||
289 | /* Vector indexed by INSN_UID. Initialized to the number of incoming | |
290 | edges in forward dependence graph (= number of LOG_LINKS). As | |
291 | scheduling procedes, dependence counts are decreased. An | |
292 | instruction moves to the ready list when its counter is zero. */ | |
293 | static int *insn_dep_count; | |
294 | #define INSN_DEP_COUNT(INSN) (insn_dep_count[INSN_UID (INSN)]) | |
295 | ||
296 | /* Vector indexed by INSN_UID giving an encoding of the blockage range | |
297 | function. The unit and the range are encoded. */ | |
298 | static unsigned int *insn_blockage; | |
299 | #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)] | |
300 | #define UNIT_BITS 5 | |
301 | #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1) | |
302 | #define ENCODE_BLOCKAGE(U, R) \ | |
f4b94256 | 303 | (((U) << BLOCKAGE_BITS \ |
8c660648 | 304 | | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \ |
f4b94256 | 305 | | MAX_BLOCKAGE_COST (R)) |
8c660648 JL |
306 | #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS)) |
307 | #define BLOCKAGE_RANGE(B) \ | |
308 | (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \ | |
5835e573 | 309 | | ((B) & BLOCKAGE_MASK)) |
8c660648 JL |
310 | |
311 | /* Encodings of the `<name>_unit_blockage_range' function. */ | |
312 | #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2)) | |
313 | #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1)) | |
314 | ||
315 | #define DONE_PRIORITY -1 | |
316 | #define MAX_PRIORITY 0x7fffffff | |
317 | #define TAIL_PRIORITY 0x7ffffffe | |
318 | #define LAUNCH_PRIORITY 0x7f000001 | |
319 | #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0) | |
320 | #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0) | |
321 | ||
63de6c74 MH |
322 | /* Vector indexed by INSN_UID giving number of insns referring to this |
323 | insn. */ | |
8c660648 JL |
324 | static int *insn_ref_count; |
325 | #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)]) | |
326 | ||
327 | /* Vector indexed by INSN_UID giving line-number note in effect for each | |
328 | insn. For line-number notes, this indicates whether the note may be | |
329 | reused. */ | |
330 | static rtx *line_note; | |
331 | #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)]) | |
332 | ||
333 | /* Vector indexed by basic block number giving the starting line-number | |
334 | for each basic block. */ | |
335 | static rtx *line_note_head; | |
336 | ||
337 | /* List of important notes we must keep around. This is a pointer to the | |
338 | last element in the list. */ | |
339 | static rtx note_list; | |
340 | ||
341 | /* Regsets telling whether a given register is live or dead before the last | |
342 | scheduled insn. Must scan the instructions once before scheduling to | |
343 | determine what registers are live or dead at the end of the block. */ | |
344 | static regset bb_live_regs; | |
345 | ||
346 | /* Regset telling whether a given register is live after the insn currently | |
347 | being scheduled. Before processing an insn, this is equal to bb_live_regs | |
348 | above. This is used so that we can find registers that are newly born/dead | |
349 | after processing an insn. */ | |
350 | static regset old_live_regs; | |
351 | ||
352 | /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns | |
353 | during the initial scan and reused later. If there are not exactly as | |
354 | many REG_DEAD notes in the post scheduled code as there were in the | |
355 | prescheduled code then we trigger an abort because this indicates a bug. */ | |
356 | static rtx dead_notes; | |
357 | ||
358 | /* Queues, etc. */ | |
359 | ||
360 | /* An instruction is ready to be scheduled when all insns preceding it | |
361 | have already been scheduled. It is important to ensure that all | |
362 | insns which use its result will not be executed until its result | |
363 | has been computed. An insn is maintained in one of four structures: | |
364 | ||
365 | (P) the "Pending" set of insns which cannot be scheduled until | |
366 | their dependencies have been satisfied. | |
367 | (Q) the "Queued" set of insns that can be scheduled when sufficient | |
368 | time has passed. | |
369 | (R) the "Ready" list of unscheduled, uncommitted insns. | |
370 | (S) the "Scheduled" list of insns. | |
371 | ||
372 | Initially, all insns are either "Pending" or "Ready" depending on | |
373 | whether their dependencies are satisfied. | |
374 | ||
375 | Insns move from the "Ready" list to the "Scheduled" list as they | |
376 | are committed to the schedule. As this occurs, the insns in the | |
377 | "Pending" list have their dependencies satisfied and move to either | |
378 | the "Ready" list or the "Queued" set depending on whether | |
379 | sufficient time has passed to make them ready. As time passes, | |
380 | insns move from the "Queued" set to the "Ready" list. Insns may | |
381 | move from the "Ready" list to the "Queued" set if they are blocked | |
382 | due to a function unit conflict. | |
383 | ||
384 | The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled | |
385 | insns, i.e., those that are ready, queued, and pending. | |
386 | The "Queued" set (Q) is implemented by the variable `insn_queue'. | |
387 | The "Ready" list (R) is implemented by the variables `ready' and | |
388 | `n_ready'. | |
389 | The "Scheduled" list (S) is the new insn chain built by this pass. | |
390 | ||
391 | The transition (R->S) is implemented in the scheduling loop in | |
392 | `schedule_block' when the best insn to schedule is chosen. | |
393 | The transition (R->Q) is implemented in `queue_insn' when an | |
38e01259 | 394 | insn is found to have a function unit conflict with the already |
8c660648 JL |
395 | committed insns. |
396 | The transitions (P->R and P->Q) are implemented in `schedule_insn' as | |
397 | insns move from the ready list to the scheduled list. | |
398 | The transition (Q->R) is implemented in 'queue_to_insn' as time | |
399 | passes or stalls are introduced. */ | |
400 | ||
401 | /* Implement a circular buffer to delay instructions until sufficient | |
402 | time has passed. INSN_QUEUE_SIZE is a power of two larger than | |
403 | MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the | |
404 | longest time an isnsn may be queued. */ | |
405 | static rtx insn_queue[INSN_QUEUE_SIZE]; | |
406 | static int q_ptr = 0; | |
407 | static int q_size = 0; | |
408 | #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1)) | |
409 | #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1)) | |
410 | ||
411 | /* Vector indexed by INSN_UID giving the minimum clock tick at which | |
412 | the insn becomes ready. This is used to note timing constraints for | |
413 | insns in the pending list. */ | |
414 | static int *insn_tick; | |
415 | #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)]) | |
416 | ||
417 | /* Data structure for keeping track of register information | |
418 | during that register's life. */ | |
419 | ||
420 | struct sometimes | |
421 | { | |
422 | int regno; | |
423 | int live_length; | |
424 | int calls_crossed; | |
425 | }; | |
426 | ||
427 | /* Forward declarations. */ | |
428 | static void add_dependence PROTO ((rtx, rtx, enum reg_note)); | |
429 | static void remove_dependence PROTO ((rtx, rtx)); | |
430 | static rtx find_insn_list PROTO ((rtx, rtx)); | |
431 | static int insn_unit PROTO ((rtx)); | |
432 | static unsigned int blockage_range PROTO ((int, rtx)); | |
433 | static void clear_units PROTO ((void)); | |
434 | static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int)); | |
435 | static void schedule_unit PROTO ((int, rtx, int)); | |
436 | static int actual_hazard PROTO ((int, rtx, int, int)); | |
437 | static int potential_hazard PROTO ((int, rtx, int)); | |
438 | static int insn_cost PROTO ((rtx, rtx, rtx)); | |
439 | static int priority PROTO ((rtx)); | |
440 | static void free_pending_lists PROTO ((void)); | |
441 | static void add_insn_mem_dependence PROTO ((rtx *, rtx *, rtx, rtx)); | |
442 | static void flush_pending_lists PROTO ((rtx, int)); | |
443 | static void sched_analyze_1 PROTO ((rtx, rtx)); | |
444 | static void sched_analyze_2 PROTO ((rtx, rtx)); | |
445 | static void sched_analyze_insn PROTO ((rtx, rtx, rtx)); | |
446 | static void sched_analyze PROTO ((rtx, rtx)); | |
5835e573 | 447 | static void sched_note_set PROTO ((rtx, int)); |
e1b6684c | 448 | static int rank_for_schedule PROTO ((const PTR, const PTR)); |
8c660648 JL |
449 | static void swap_sort PROTO ((rtx *, int)); |
450 | static void queue_insn PROTO ((rtx, int)); | |
451 | static int schedule_insn PROTO ((rtx, rtx *, int, int)); | |
452 | static void create_reg_dead_note PROTO ((rtx, rtx)); | |
453 | static void attach_deaths PROTO ((rtx, rtx, int)); | |
454 | static void attach_deaths_insn PROTO ((rtx)); | |
455 | static int new_sometimes_live PROTO ((struct sometimes *, int, int)); | |
456 | static void finish_sometimes_live PROTO ((struct sometimes *, int)); | |
5835e573 | 457 | static int schedule_block PROTO ((int, int)); |
5f06c983 | 458 | static char *safe_concat PROTO ((char *, char *, const char *)); |
cc4fe0e2 L |
459 | static int insn_issue_delay PROTO ((rtx)); |
460 | static int birthing_insn_p PROTO ((rtx)); | |
461 | static void adjust_priority PROTO ((rtx)); | |
8c660648 JL |
462 | |
463 | /* Mapping of insns to their original block prior to scheduling. */ | |
464 | static int *insn_orig_block; | |
465 | #define INSN_BLOCK(insn) (insn_orig_block[INSN_UID (insn)]) | |
466 | ||
467 | /* Some insns (e.g. call) are not allowed to move across blocks. */ | |
468 | static char *cant_move; | |
469 | #define CANT_MOVE(insn) (cant_move[INSN_UID (insn)]) | |
470 | ||
471 | /* Control flow graph edges are kept in circular lists. */ | |
472 | typedef struct | |
473 | { | |
474 | int from_block; | |
475 | int to_block; | |
476 | int next_in; | |
477 | int next_out; | |
478 | } | |
e881bb1b RH |
479 | haifa_edge; |
480 | static haifa_edge *edge_table; | |
8c660648 JL |
481 | |
482 | #define NEXT_IN(edge) (edge_table[edge].next_in) | |
483 | #define NEXT_OUT(edge) (edge_table[edge].next_out) | |
484 | #define FROM_BLOCK(edge) (edge_table[edge].from_block) | |
485 | #define TO_BLOCK(edge) (edge_table[edge].to_block) | |
486 | ||
63de6c74 MH |
487 | /* Number of edges in the control flow graph. (In fact, larger than |
488 | that by 1, since edge 0 is unused.) */ | |
8c660648 JL |
489 | static int nr_edges; |
490 | ||
63de6c74 | 491 | /* Circular list of incoming/outgoing edges of a block. */ |
8c660648 JL |
492 | static int *in_edges; |
493 | static int *out_edges; | |
494 | ||
495 | #define IN_EDGES(block) (in_edges[block]) | |
496 | #define OUT_EDGES(block) (out_edges[block]) | |
497 | ||
8c660648 JL |
498 | |
499 | ||
168cbdf9 | 500 | static int is_cfg_nonregular PROTO ((void)); |
a2e68776 JL |
501 | static int build_control_flow PROTO ((int_list_ptr *, int_list_ptr *, |
502 | int *, int *)); | |
8c660648 JL |
503 | static void new_edge PROTO ((int, int)); |
504 | ||
505 | ||
506 | /* A region is the main entity for interblock scheduling: insns | |
507 | are allowed to move between blocks in the same region, along | |
508 | control flow graph edges, in the 'up' direction. */ | |
509 | typedef struct | |
510 | { | |
63de6c74 MH |
511 | int rgn_nr_blocks; /* Number of blocks in region. */ |
512 | int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */ | |
8c660648 JL |
513 | } |
514 | region; | |
515 | ||
63de6c74 | 516 | /* Number of regions in the procedure. */ |
8c660648 JL |
517 | static int nr_regions; |
518 | ||
63de6c74 | 519 | /* Table of region descriptions. */ |
8c660648 JL |
520 | static region *rgn_table; |
521 | ||
63de6c74 | 522 | /* Array of lists of regions' blocks. */ |
8c660648 JL |
523 | static int *rgn_bb_table; |
524 | ||
525 | /* Topological order of blocks in the region (if b2 is reachable from | |
63de6c74 MH |
526 | b1, block_to_bb[b2] > block_to_bb[b1]). Note: A basic block is |
527 | always referred to by either block or b, while its topological | |
528 | order name (in the region) is refered to by bb. */ | |
8c660648 JL |
529 | static int *block_to_bb; |
530 | ||
531 | /* The number of the region containing a block. */ | |
532 | static int *containing_rgn; | |
533 | ||
534 | #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks) | |
535 | #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks) | |
536 | #define BLOCK_TO_BB(block) (block_to_bb[block]) | |
537 | #define CONTAINING_RGN(block) (containing_rgn[block]) | |
538 | ||
539 | void debug_regions PROTO ((void)); | |
540 | static void find_single_block_region PROTO ((void)); | |
a2e68776 JL |
541 | static void find_rgns PROTO ((int_list_ptr *, int_list_ptr *, |
542 | int *, int *, sbitmap *)); | |
8c660648 JL |
543 | static int too_large PROTO ((int, int *, int *)); |
544 | ||
545 | extern void debug_live PROTO ((int, int)); | |
546 | ||
547 | /* Blocks of the current region being scheduled. */ | |
548 | static int current_nr_blocks; | |
549 | static int current_blocks; | |
550 | ||
63de6c74 | 551 | /* The mapping from bb to block. */ |
8c660648 JL |
552 | #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)]) |
553 | ||
554 | ||
555 | /* Bit vectors and bitset operations are needed for computations on | |
556 | the control flow graph. */ | |
557 | ||
558 | typedef unsigned HOST_WIDE_INT *bitset; | |
559 | typedef struct | |
560 | { | |
63de6c74 MH |
561 | int *first_member; /* Pointer to the list start in bitlst_table. */ |
562 | int nr_members; /* The number of members of the bit list. */ | |
8c660648 JL |
563 | } |
564 | bitlst; | |
565 | ||
61822835 JL |
566 | static int bitlst_table_last; |
567 | static int bitlst_table_size; | |
8c660648 JL |
568 | static int *bitlst_table; |
569 | ||
570 | static char bitset_member PROTO ((bitset, int, int)); | |
571 | static void extract_bitlst PROTO ((bitset, int, bitlst *)); | |
572 | ||
63de6c74 | 573 | /* Target info declarations. |
8c660648 JL |
574 | |
575 | The block currently being scheduled is referred to as the "target" block, | |
576 | while other blocks in the region from which insns can be moved to the | |
577 | target are called "source" blocks. The candidate structure holds info | |
578 | about such sources: are they valid? Speculative? Etc. */ | |
579 | typedef bitlst bblst; | |
580 | typedef struct | |
581 | { | |
582 | char is_valid; | |
583 | char is_speculative; | |
584 | int src_prob; | |
585 | bblst split_bbs; | |
586 | bblst update_bbs; | |
587 | } | |
588 | candidate; | |
589 | ||
590 | static candidate *candidate_table; | |
591 | ||
592 | /* A speculative motion requires checking live information on the path | |
593 | from 'source' to 'target'. The split blocks are those to be checked. | |
594 | After a speculative motion, live information should be modified in | |
595 | the 'update' blocks. | |
596 | ||
63de6c74 MH |
597 | Lists of split and update blocks for each candidate of the current |
598 | target are in array bblst_table. */ | |
61822835 | 599 | static int *bblst_table, bblst_size, bblst_last; |
8c660648 JL |
600 | |
601 | #define IS_VALID(src) ( candidate_table[src].is_valid ) | |
602 | #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative ) | |
603 | #define SRC_PROB(src) ( candidate_table[src].src_prob ) | |
604 | ||
605 | /* The bb being currently scheduled. */ | |
61822835 | 606 | static int target_bb; |
8c660648 JL |
607 | |
608 | /* List of edges. */ | |
609 | typedef bitlst edgelst; | |
610 | ||
63de6c74 | 611 | /* Target info functions. */ |
8c660648 JL |
612 | static void split_edges PROTO ((int, int, edgelst *)); |
613 | static void compute_trg_info PROTO ((int)); | |
614 | void debug_candidate PROTO ((int)); | |
615 | void debug_candidates PROTO ((int)); | |
616 | ||
617 | ||
618 | /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */ | |
619 | typedef bitset bbset; | |
620 | ||
621 | /* Number of words of the bbset. */ | |
61822835 | 622 | static int bbset_size; |
8c660648 JL |
623 | |
624 | /* Dominators array: dom[i] contains the bbset of dominators of | |
625 | bb i in the region. */ | |
61822835 | 626 | static bbset *dom; |
8c660648 | 627 | |
63de6c74 | 628 | /* bb 0 is the only region entry. */ |
8c660648 JL |
629 | #define IS_RGN_ENTRY(bb) (!bb) |
630 | ||
631 | /* Is bb_src dominated by bb_trg. */ | |
632 | #define IS_DOMINATED(bb_src, bb_trg) \ | |
633 | ( bitset_member (dom[bb_src], bb_trg, bbset_size) ) | |
634 | ||
635 | /* Probability: Prob[i] is a float in [0, 1] which is the probability | |
636 | of bb i relative to the region entry. */ | |
61822835 | 637 | static float *prob; |
8c660648 | 638 | |
63de6c74 | 639 | /* The probability of bb_src, relative to bb_trg. Note, that while the |
8c660648 JL |
640 | 'prob[bb]' is a float in [0, 1], this macro returns an integer |
641 | in [0, 100]. */ | |
642 | #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \ | |
643 | prob[bb_trg]))) | |
644 | ||
645 | /* Bit-set of edges, where bit i stands for edge i. */ | |
646 | typedef bitset edgeset; | |
647 | ||
648 | /* Number of edges in the region. */ | |
61822835 | 649 | static int rgn_nr_edges; |
8c660648 | 650 | |
63de6c74 | 651 | /* Array of size rgn_nr_edges. */ |
61822835 | 652 | static int *rgn_edges; |
8c660648 | 653 | |
63de6c74 | 654 | /* Number of words in an edgeset. */ |
61822835 | 655 | static int edgeset_size; |
8c660648 JL |
656 | |
657 | /* Mapping from each edge in the graph to its number in the rgn. */ | |
61822835 | 658 | static int *edge_to_bit; |
8c660648 JL |
659 | #define EDGE_TO_BIT(edge) (edge_to_bit[edge]) |
660 | ||
661 | /* The split edges of a source bb is different for each target | |
662 | bb. In order to compute this efficiently, the 'potential-split edges' | |
663 | are computed for each bb prior to scheduling a region. This is actually | |
664 | the split edges of each bb relative to the region entry. | |
665 | ||
666 | pot_split[bb] is the set of potential split edges of bb. */ | |
61822835 | 667 | static edgeset *pot_split; |
8c660648 JL |
668 | |
669 | /* For every bb, a set of its ancestor edges. */ | |
61822835 | 670 | static edgeset *ancestor_edges; |
8c660648 JL |
671 | |
672 | static void compute_dom_prob_ps PROTO ((int)); | |
673 | ||
674 | #define ABS_VALUE(x) (((x)<0)?(-(x)):(x)) | |
675 | #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (INSN_BLOCK (INSN)))) | |
676 | #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (INSN_BLOCK (INSN)))) | |
677 | #define INSN_BB(INSN) (BLOCK_TO_BB (INSN_BLOCK (INSN))) | |
678 | ||
63de6c74 | 679 | /* Parameters affecting the decision of rank_for_schedule(). */ |
8c660648 JL |
680 | #define MIN_DIFF_PRIORITY 2 |
681 | #define MIN_PROBABILITY 40 | |
682 | #define MIN_PROB_DIFF 10 | |
683 | ||
63de6c74 | 684 | /* Speculative scheduling functions. */ |
8c660648 JL |
685 | static int check_live_1 PROTO ((int, rtx)); |
686 | static void update_live_1 PROTO ((int, rtx)); | |
5835e573 KG |
687 | static int check_live PROTO ((rtx, int)); |
688 | static void update_live PROTO ((rtx, int)); | |
8c660648 JL |
689 | static void set_spec_fed PROTO ((rtx)); |
690 | static int is_pfree PROTO ((rtx, int, int)); | |
691 | static int find_conditional_protection PROTO ((rtx, int)); | |
692 | static int is_conditionally_protected PROTO ((rtx, int, int)); | |
693 | static int may_trap_exp PROTO ((rtx, int)); | |
ac957f13 | 694 | static int haifa_classify_insn PROTO ((rtx)); |
e009aaf3 | 695 | static int is_prisky PROTO ((rtx, int, int)); |
8c660648 JL |
696 | static int is_exception_free PROTO ((rtx, int, int)); |
697 | ||
698 | static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx)); | |
699 | static void compute_block_forward_dependences PROTO ((int)); | |
700 | static void init_rgn_data_dependences PROTO ((int)); | |
701 | static void add_branch_dependences PROTO ((rtx, rtx)); | |
702 | static void compute_block_backward_dependences PROTO ((int)); | |
703 | void debug_dependencies PROTO ((void)); | |
704 | ||
705 | /* Notes handling mechanism: | |
706 | ========================= | |
707 | Generally, NOTES are saved before scheduling and restored after scheduling. | |
708 | The scheduler distinguishes between three types of notes: | |
709 | ||
710 | (1) LINE_NUMBER notes, generated and used for debugging. Here, | |
711 | before scheduling a region, a pointer to the LINE_NUMBER note is | |
712 | added to the insn following it (in save_line_notes()), and the note | |
713 | is removed (in rm_line_notes() and unlink_line_notes()). After | |
714 | scheduling the region, this pointer is used for regeneration of | |
715 | the LINE_NUMBER note (in restore_line_notes()). | |
716 | ||
717 | (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes: | |
718 | Before scheduling a region, a pointer to the note is added to the insn | |
719 | that follows or precedes it. (This happens as part of the data dependence | |
720 | computation). After scheduling an insn, the pointer contained in it is | |
721 | used for regenerating the corresponding note (in reemit_notes). | |
722 | ||
723 | (3) All other notes (e.g. INSN_DELETED): Before scheduling a block, | |
724 | these notes are put in a list (in rm_other_notes() and | |
725 | unlink_other_notes ()). After scheduling the block, these notes are | |
726 | inserted at the beginning of the block (in schedule_block()). */ | |
727 | ||
728 | static rtx unlink_other_notes PROTO ((rtx, rtx)); | |
729 | static rtx unlink_line_notes PROTO ((rtx, rtx)); | |
730 | static void rm_line_notes PROTO ((int)); | |
731 | static void save_line_notes PROTO ((int)); | |
732 | static void restore_line_notes PROTO ((int)); | |
733 | static void rm_redundant_line_notes PROTO ((void)); | |
734 | static void rm_other_notes PROTO ((rtx, rtx)); | |
735 | static rtx reemit_notes PROTO ((rtx, rtx)); | |
736 | ||
737 | static void get_block_head_tail PROTO ((int, rtx *, rtx *)); | |
738 | ||
739 | static void find_pre_sched_live PROTO ((int)); | |
740 | static void find_post_sched_live PROTO ((int)); | |
741 | static void update_reg_usage PROTO ((void)); | |
c6a754f2 | 742 | static int queue_to_ready PROTO ((rtx [], int)); |
8c660648 | 743 | |
9a8b0889 | 744 | static void debug_ready_list PROTO ((rtx[], int)); |
cc4fe0e2 | 745 | static void init_target_units PROTO ((void)); |
8c660648 | 746 | static void insn_print_units PROTO ((rtx)); |
cc4fe0e2 L |
747 | static int get_visual_tbl_length PROTO ((void)); |
748 | static void init_block_visualization PROTO ((void)); | |
5f06c983 | 749 | static void print_block_visualization PROTO ((int, const char *)); |
8c660648 JL |
750 | static void visualize_scheduled_insns PROTO ((int, int)); |
751 | static void visualize_no_unit PROTO ((rtx)); | |
752 | static void visualize_stall_cycles PROTO ((int, int)); | |
753 | static void print_exp PROTO ((char *, rtx, int)); | |
754 | static void print_value PROTO ((char *, rtx, int)); | |
755 | static void print_pattern PROTO ((char *, rtx, int)); | |
756 | static void print_insn PROTO ((char *, rtx, int)); | |
757 | void debug_reg_vector PROTO ((regset)); | |
758 | ||
759 | static rtx move_insn1 PROTO ((rtx, rtx)); | |
760 | static rtx move_insn PROTO ((rtx, rtx)); | |
761 | static rtx group_leader PROTO ((rtx)); | |
762 | static int set_priorities PROTO ((int)); | |
763 | static void init_rtx_vector PROTO ((rtx **, rtx *, int, int)); | |
764 | static void schedule_region PROTO ((int)); | |
8c660648 JL |
765 | |
766 | #endif /* INSN_SCHEDULING */ | |
767 | \f | |
768 | #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X))) | |
769 | ||
8c660648 JL |
770 | /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the |
771 | LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type | |
772 | of dependence that this link represents. */ | |
773 | ||
774 | static void | |
775 | add_dependence (insn, elem, dep_type) | |
776 | rtx insn; | |
777 | rtx elem; | |
778 | enum reg_note dep_type; | |
779 | { | |
780 | rtx link, next; | |
781 | ||
782 | /* Don't depend an insn on itself. */ | |
783 | if (insn == elem) | |
784 | return; | |
785 | ||
342d9c89 JL |
786 | /* We can get a dependency on deleted insns due to optimizations in |
787 | the register allocation and reloading or due to splitting. Any | |
788 | such dependency is useless and can be ignored. */ | |
789 | if (GET_CODE (elem) == NOTE) | |
790 | return; | |
791 | ||
8c660648 JL |
792 | /* If elem is part of a sequence that must be scheduled together, then |
793 | make the dependence point to the last insn of the sequence. | |
794 | When HAVE_cc0, it is possible for NOTEs to exist between users and | |
795 | setters of the condition codes, so we must skip past notes here. | |
796 | Otherwise, NOTEs are impossible here. */ | |
797 | ||
798 | next = NEXT_INSN (elem); | |
799 | ||
800 | #ifdef HAVE_cc0 | |
801 | while (next && GET_CODE (next) == NOTE) | |
802 | next = NEXT_INSN (next); | |
803 | #endif | |
804 | ||
805 | if (next && SCHED_GROUP_P (next) | |
806 | && GET_CODE (next) != CODE_LABEL) | |
807 | { | |
808 | /* Notes will never intervene here though, so don't bother checking | |
809 | for them. */ | |
810 | /* We must reject CODE_LABELs, so that we don't get confused by one | |
811 | that has LABEL_PRESERVE_P set, which is represented by the same | |
812 | bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be | |
813 | SCHED_GROUP_P. */ | |
814 | while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next)) | |
815 | && GET_CODE (NEXT_INSN (next)) != CODE_LABEL) | |
816 | next = NEXT_INSN (next); | |
817 | ||
818 | /* Again, don't depend an insn on itself. */ | |
819 | if (insn == next) | |
820 | return; | |
821 | ||
822 | /* Make the dependence to NEXT, the last insn of the group, instead | |
823 | of the original ELEM. */ | |
824 | elem = next; | |
825 | } | |
826 | ||
827 | #ifdef INSN_SCHEDULING | |
828 | /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.) | |
829 | No need for interblock dependences with calls, since | |
830 | calls are not moved between blocks. Note: the edge where | |
831 | elem is a CALL is still required. */ | |
832 | if (GET_CODE (insn) == CALL_INSN | |
833 | && (INSN_BB (elem) != INSN_BB (insn))) | |
834 | return; | |
835 | ||
836 | #endif | |
837 | ||
838 | /* Check that we don't already have this dependence. */ | |
839 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
840 | if (XEXP (link, 0) == elem) | |
841 | { | |
842 | /* If this is a more restrictive type of dependence than the existing | |
843 | one, then change the existing dependence to this type. */ | |
844 | if ((int) dep_type < (int) REG_NOTE_KIND (link)) | |
845 | PUT_REG_NOTE_KIND (link, dep_type); | |
846 | return; | |
847 | } | |
848 | /* Might want to check one level of transitivity to save conses. */ | |
849 | ||
ebb7b10b RH |
850 | link = alloc_INSN_LIST (elem, LOG_LINKS (insn)); |
851 | LOG_LINKS (insn) = link; | |
852 | ||
8c660648 JL |
853 | /* Insn dependency, not data dependency. */ |
854 | PUT_REG_NOTE_KIND (link, dep_type); | |
8c660648 JL |
855 | } |
856 | ||
857 | /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS | |
858 | of INSN. Abort if not found. */ | |
859 | ||
860 | static void | |
861 | remove_dependence (insn, elem) | |
862 | rtx insn; | |
863 | rtx elem; | |
864 | { | |
ebb7b10b | 865 | rtx prev, link, next; |
8c660648 JL |
866 | int found = 0; |
867 | ||
ebb7b10b | 868 | for (prev = 0, link = LOG_LINKS (insn); link; link = next) |
8c660648 | 869 | { |
ebb7b10b | 870 | next = XEXP (link, 1); |
8c660648 JL |
871 | if (XEXP (link, 0) == elem) |
872 | { | |
873 | if (prev) | |
ebb7b10b | 874 | XEXP (prev, 1) = next; |
8c660648 | 875 | else |
ebb7b10b | 876 | LOG_LINKS (insn) = next; |
5a4f6418 | 877 | free_INSN_LIST_node (link); |
ebb7b10b | 878 | |
8c660648 JL |
879 | found = 1; |
880 | } | |
6d8ccdbb JL |
881 | else |
882 | prev = link; | |
8c660648 JL |
883 | } |
884 | ||
885 | if (!found) | |
886 | abort (); | |
887 | return; | |
888 | } | |
889 | \f | |
890 | #ifndef INSN_SCHEDULING | |
891 | void | |
892 | schedule_insns (dump_file) | |
893 | FILE *dump_file; | |
894 | { | |
895 | } | |
896 | #else | |
897 | #ifndef __GNUC__ | |
898 | #define __inline | |
899 | #endif | |
900 | ||
cbb13457 MM |
901 | #ifndef HAIFA_INLINE |
902 | #define HAIFA_INLINE __inline | |
903 | #endif | |
904 | ||
8c660648 JL |
905 | /* Computation of memory dependencies. */ |
906 | ||
907 | /* The *_insns and *_mems are paired lists. Each pending memory operation | |
908 | will have a pointer to the MEM rtx on one list and a pointer to the | |
909 | containing insn on the other list in the same place in the list. */ | |
910 | ||
911 | /* We can't use add_dependence like the old code did, because a single insn | |
912 | may have multiple memory accesses, and hence needs to be on the list | |
913 | once for each memory access. Add_dependence won't let you add an insn | |
914 | to a list more than once. */ | |
915 | ||
916 | /* An INSN_LIST containing all insns with pending read operations. */ | |
917 | static rtx pending_read_insns; | |
918 | ||
919 | /* An EXPR_LIST containing all MEM rtx's which are pending reads. */ | |
920 | static rtx pending_read_mems; | |
921 | ||
922 | /* An INSN_LIST containing all insns with pending write operations. */ | |
923 | static rtx pending_write_insns; | |
924 | ||
925 | /* An EXPR_LIST containing all MEM rtx's which are pending writes. */ | |
926 | static rtx pending_write_mems; | |
927 | ||
928 | /* Indicates the combined length of the two pending lists. We must prevent | |
929 | these lists from ever growing too large since the number of dependencies | |
930 | produced is at least O(N*N), and execution time is at least O(4*N*N), as | |
931 | a function of the length of these pending lists. */ | |
932 | ||
933 | static int pending_lists_length; | |
934 | ||
8c660648 JL |
935 | /* The last insn upon which all memory references must depend. |
936 | This is an insn which flushed the pending lists, creating a dependency | |
937 | between it and all previously pending memory references. This creates | |
938 | a barrier (or a checkpoint) which no memory reference is allowed to cross. | |
939 | ||
940 | This includes all non constant CALL_INSNs. When we do interprocedural | |
941 | alias analysis, this restriction can be relaxed. | |
942 | This may also be an INSN that writes memory if the pending lists grow | |
943 | too large. */ | |
944 | ||
945 | static rtx last_pending_memory_flush; | |
946 | ||
947 | /* The last function call we have seen. All hard regs, and, of course, | |
948 | the last function call, must depend on this. */ | |
949 | ||
950 | static rtx last_function_call; | |
951 | ||
952 | /* The LOG_LINKS field of this is a list of insns which use a pseudo register | |
953 | that does not already cross a call. We create dependencies between each | |
954 | of those insn and the next call insn, to ensure that they won't cross a call | |
955 | after scheduling is done. */ | |
956 | ||
957 | static rtx sched_before_next_call; | |
958 | ||
959 | /* Pointer to the last instruction scheduled. Used by rank_for_schedule, | |
960 | so that insns independent of the last scheduled insn will be preferred | |
961 | over dependent instructions. */ | |
962 | ||
963 | static rtx last_scheduled_insn; | |
964 | ||
965 | /* Data structures for the computation of data dependences in a regions. We | |
966 | keep one copy of each of the declared above variables for each bb in the | |
967 | region. Before analyzing the data dependences for a bb, its variables | |
968 | are initialized as a function of the variables of its predecessors. When | |
969 | the analysis for a bb completes, we save the contents of each variable X | |
970 | to a corresponding bb_X[bb] variable. For example, pending_read_insns is | |
971 | copied to bb_pending_read_insns[bb]. Another change is that few | |
972 | variables are now a list of insns rather than a single insn: | |
973 | last_pending_memory_flash, last_function_call, reg_last_sets. The | |
974 | manipulation of these variables was changed appropriately. */ | |
975 | ||
976 | static rtx **bb_reg_last_uses; | |
977 | static rtx **bb_reg_last_sets; | |
28c95eff | 978 | static rtx **bb_reg_last_clobbers; |
8c660648 JL |
979 | |
980 | static rtx *bb_pending_read_insns; | |
981 | static rtx *bb_pending_read_mems; | |
982 | static rtx *bb_pending_write_insns; | |
983 | static rtx *bb_pending_write_mems; | |
984 | static int *bb_pending_lists_length; | |
985 | ||
986 | static rtx *bb_last_pending_memory_flush; | |
987 | static rtx *bb_last_function_call; | |
988 | static rtx *bb_sched_before_next_call; | |
989 | ||
63de6c74 | 990 | /* Functions for construction of the control flow graph. */ |
8c660648 JL |
991 | |
992 | /* Return 1 if control flow graph should not be constructed, 0 otherwise. | |
168cbdf9 | 993 | |
8c660648 | 994 | We decide not to build the control flow graph if there is possibly more |
168cbdf9 JL |
995 | than one entry to the function, if computed branches exist, of if we |
996 | have nonlocal gotos. */ | |
8c660648 | 997 | |
168cbdf9 | 998 | static int |
8c660648 JL |
999 | is_cfg_nonregular () |
1000 | { | |
1001 | int b; | |
1002 | rtx insn; | |
1003 | RTX_CODE code; | |
1004 | ||
168cbdf9 JL |
1005 | /* If we have a label that could be the target of a nonlocal goto, then |
1006 | the cfg is not well structured. */ | |
e881bb1b | 1007 | if (nonlocal_goto_handler_labels) |
168cbdf9 | 1008 | return 1; |
8c660648 | 1009 | |
168cbdf9 | 1010 | /* If we have any forced labels, then the cfg is not well structured. */ |
8c660648 | 1011 | if (forced_labels) |
168cbdf9 | 1012 | return 1; |
8c660648 | 1013 | |
4d1d8045 BS |
1014 | /* If this function has a computed jump, then we consider the cfg |
1015 | not well structured. */ | |
1016 | if (current_function_has_computed_jump) | |
1017 | return 1; | |
1018 | ||
168cbdf9 JL |
1019 | /* If we have exception handlers, then we consider the cfg not well |
1020 | structured. ?!? We should be able to handle this now that flow.c | |
1021 | computes an accurate cfg for EH. */ | |
8c660648 | 1022 | if (exception_handler_labels) |
168cbdf9 | 1023 | return 1; |
8c660648 | 1024 | |
168cbdf9 JL |
1025 | /* If we have non-jumping insns which refer to labels, then we consider |
1026 | the cfg not well structured. */ | |
63de6c74 | 1027 | /* Check for labels referred to other thn by jumps. */ |
8c660648 | 1028 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 1029 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
1030 | { |
1031 | code = GET_CODE (insn); | |
1032 | if (GET_RTX_CLASS (code) == 'i') | |
1033 | { | |
1034 | rtx note; | |
1035 | ||
1036 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1037 | if (REG_NOTE_KIND (note) == REG_LABEL) | |
168cbdf9 | 1038 | return 1; |
8c660648 JL |
1039 | } |
1040 | ||
3b413743 | 1041 | if (insn == BLOCK_END (b)) |
8c660648 JL |
1042 | break; |
1043 | } | |
1044 | ||
168cbdf9 | 1045 | /* All the tests passed. Consider the cfg well structured. */ |
8c660648 JL |
1046 | return 0; |
1047 | } | |
1048 | ||
5ece9746 JL |
1049 | /* Build the control flow graph and set nr_edges. |
1050 | ||
1051 | Instead of trying to build a cfg ourselves, we rely on flow to | |
168cbdf9 | 1052 | do it for us. Stamp out useless code (and bug) duplication. |
8c660648 | 1053 | |
168cbdf9 JL |
1054 | Return nonzero if an irregularity in the cfg is found which would |
1055 | prevent cross block scheduling. */ | |
1056 | ||
1057 | static int | |
a2e68776 JL |
1058 | build_control_flow (s_preds, s_succs, num_preds, num_succs) |
1059 | int_list_ptr *s_preds; | |
1060 | int_list_ptr *s_succs; | |
1061 | int *num_preds; | |
1062 | int *num_succs; | |
8c660648 | 1063 | { |
081f5e7e | 1064 | int i; |
5ece9746 | 1065 | int_list_ptr succ; |
168cbdf9 | 1066 | int unreachable; |
5ece9746 | 1067 | |
168cbdf9 JL |
1068 | /* Count the number of edges in the cfg. */ |
1069 | nr_edges = 0; | |
1070 | unreachable = 0; | |
1071 | for (i = 0; i < n_basic_blocks; i++) | |
1072 | { | |
1073 | nr_edges += num_succs[i]; | |
15ebe47d JL |
1074 | |
1075 | /* Unreachable loops with more than one basic block are detected | |
1076 | during the DFS traversal in find_rgns. | |
1077 | ||
1078 | Unreachable loops with a single block are detected here. This | |
1079 | test is redundant with the one in find_rgns, but it's much | |
1080 | cheaper to go ahead and catch the trivial case here. */ | |
a8afd67b JW |
1081 | if (num_preds[i] == 0 |
1082 | || (num_preds[i] == 1 && INT_LIST_VAL (s_preds[i]) == i)) | |
168cbdf9 JL |
1083 | unreachable = 1; |
1084 | } | |
1085 | ||
1086 | /* Account for entry/exit edges. */ | |
1087 | nr_edges += 2; | |
1088 | ||
3de90026 RH |
1089 | in_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); |
1090 | out_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); | |
1091 | edge_table = (haifa_edge *) xcalloc (nr_edges, sizeof (haifa_edge)); | |
168cbdf9 | 1092 | |
8c660648 JL |
1093 | nr_edges = 0; |
1094 | for (i = 0; i < n_basic_blocks; i++) | |
5ece9746 JL |
1095 | for (succ = s_succs[i]; succ; succ = succ->next) |
1096 | { | |
1097 | if (INT_LIST_VAL (succ) != EXIT_BLOCK) | |
1098 | new_edge (i, INT_LIST_VAL (succ)); | |
1099 | } | |
8c660648 | 1100 | |
63de6c74 | 1101 | /* Increment by 1, since edge 0 is unused. */ |
8c660648 JL |
1102 | nr_edges++; |
1103 | ||
168cbdf9 | 1104 | return unreachable; |
8c660648 JL |
1105 | } |
1106 | ||
1107 | ||
5ece9746 | 1108 | /* Record an edge in the control flow graph from SOURCE to TARGET. |
8c660648 | 1109 | |
5ece9746 JL |
1110 | In theory, this is redundant with the s_succs computed above, but |
1111 | we have not converted all of haifa to use information from the | |
1112 | integer lists. */ | |
8c660648 JL |
1113 | |
1114 | static void | |
1115 | new_edge (source, target) | |
1116 | int source, target; | |
1117 | { | |
1118 | int e, next_edge; | |
1119 | int curr_edge, fst_edge; | |
1120 | ||
63de6c74 | 1121 | /* Check for duplicates. */ |
8c660648 JL |
1122 | fst_edge = curr_edge = OUT_EDGES (source); |
1123 | while (curr_edge) | |
1124 | { | |
1125 | if (FROM_BLOCK (curr_edge) == source | |
1126 | && TO_BLOCK (curr_edge) == target) | |
1127 | { | |
1128 | return; | |
1129 | } | |
1130 | ||
1131 | curr_edge = NEXT_OUT (curr_edge); | |
1132 | ||
1133 | if (fst_edge == curr_edge) | |
1134 | break; | |
1135 | } | |
1136 | ||
1137 | e = ++nr_edges; | |
1138 | ||
1139 | FROM_BLOCK (e) = source; | |
1140 | TO_BLOCK (e) = target; | |
1141 | ||
1142 | if (OUT_EDGES (source)) | |
1143 | { | |
1144 | next_edge = NEXT_OUT (OUT_EDGES (source)); | |
1145 | NEXT_OUT (OUT_EDGES (source)) = e; | |
1146 | NEXT_OUT (e) = next_edge; | |
1147 | } | |
1148 | else | |
1149 | { | |
1150 | OUT_EDGES (source) = e; | |
1151 | NEXT_OUT (e) = e; | |
1152 | } | |
1153 | ||
1154 | if (IN_EDGES (target)) | |
1155 | { | |
1156 | next_edge = NEXT_IN (IN_EDGES (target)); | |
1157 | NEXT_IN (IN_EDGES (target)) = e; | |
1158 | NEXT_IN (e) = next_edge; | |
1159 | } | |
1160 | else | |
1161 | { | |
1162 | IN_EDGES (target) = e; | |
1163 | NEXT_IN (e) = e; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | ||
1168 | /* BITSET macros for operations on the control flow graph. */ | |
1169 | ||
63de6c74 | 1170 | /* Compute bitwise union of two bitsets. */ |
8c660648 JL |
1171 | #define BITSET_UNION(set1, set2, len) \ |
1172 | do { register bitset tp = set1, sp = set2; \ | |
1173 | register int i; \ | |
1174 | for (i = 0; i < len; i++) \ | |
1175 | *(tp++) |= *(sp++); } while (0) | |
1176 | ||
63de6c74 | 1177 | /* Compute bitwise intersection of two bitsets. */ |
8c660648 JL |
1178 | #define BITSET_INTER(set1, set2, len) \ |
1179 | do { register bitset tp = set1, sp = set2; \ | |
1180 | register int i; \ | |
1181 | for (i = 0; i < len; i++) \ | |
1182 | *(tp++) &= *(sp++); } while (0) | |
1183 | ||
63de6c74 | 1184 | /* Compute bitwise difference of two bitsets. */ |
8c660648 JL |
1185 | #define BITSET_DIFFER(set1, set2, len) \ |
1186 | do { register bitset tp = set1, sp = set2; \ | |
1187 | register int i; \ | |
1188 | for (i = 0; i < len; i++) \ | |
1189 | *(tp++) &= ~*(sp++); } while (0) | |
1190 | ||
63de6c74 | 1191 | /* Inverts every bit of bitset 'set'. */ |
8c660648 JL |
1192 | #define BITSET_INVERT(set, len) \ |
1193 | do { register bitset tmpset = set; \ | |
1194 | register int i; \ | |
1195 | for (i = 0; i < len; i++, tmpset++) \ | |
1196 | *tmpset = ~*tmpset; } while (0) | |
1197 | ||
1198 | /* Turn on the index'th bit in bitset set. */ | |
1199 | #define BITSET_ADD(set, index, len) \ | |
1200 | { \ | |
1201 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1202 | abort (); \ | |
1203 | else \ | |
1204 | set[index/HOST_BITS_PER_WIDE_INT] |= \ | |
1205 | 1 << (index % HOST_BITS_PER_WIDE_INT); \ | |
1206 | } | |
1207 | ||
1208 | /* Turn off the index'th bit in set. */ | |
1209 | #define BITSET_REMOVE(set, index, len) \ | |
1210 | { \ | |
1211 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1212 | abort (); \ | |
1213 | else \ | |
1214 | set[index/HOST_BITS_PER_WIDE_INT] &= \ | |
1215 | ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \ | |
1216 | } | |
1217 | ||
1218 | ||
63de6c74 | 1219 | /* Check if the index'th bit in bitset set is on. */ |
8c660648 JL |
1220 | |
1221 | static char | |
1222 | bitset_member (set, index, len) | |
1223 | bitset set; | |
1224 | int index, len; | |
1225 | { | |
1226 | if (index >= HOST_BITS_PER_WIDE_INT * len) | |
1227 | abort (); | |
1228 | return (set[index / HOST_BITS_PER_WIDE_INT] & | |
1229 | 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0; | |
1230 | } | |
1231 | ||
1232 | ||
1233 | /* Translate a bit-set SET to a list BL of the bit-set members. */ | |
1234 | ||
1235 | static void | |
1236 | extract_bitlst (set, len, bl) | |
1237 | bitset set; | |
1238 | int len; | |
1239 | bitlst *bl; | |
1240 | { | |
1241 | int i, j, offset; | |
1242 | unsigned HOST_WIDE_INT word; | |
1243 | ||
63de6c74 | 1244 | /* bblst table space is reused in each call to extract_bitlst. */ |
8c660648 JL |
1245 | bitlst_table_last = 0; |
1246 | ||
1247 | bl->first_member = &bitlst_table[bitlst_table_last]; | |
1248 | bl->nr_members = 0; | |
1249 | ||
1250 | for (i = 0; i < len; i++) | |
1251 | { | |
1252 | word = set[i]; | |
1253 | offset = i * HOST_BITS_PER_WIDE_INT; | |
1254 | for (j = 0; word; j++) | |
1255 | { | |
1256 | if (word & 1) | |
1257 | { | |
1258 | bitlst_table[bitlst_table_last++] = offset; | |
1259 | (bl->nr_members)++; | |
1260 | } | |
1261 | word >>= 1; | |
1262 | ++offset; | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | } | |
1267 | ||
1268 | ||
63de6c74 | 1269 | /* Functions for the construction of regions. */ |
8c660648 JL |
1270 | |
1271 | /* Print the regions, for debugging purposes. Callable from debugger. */ | |
1272 | ||
1273 | void | |
1274 | debug_regions () | |
1275 | { | |
1276 | int rgn, bb; | |
1277 | ||
1278 | fprintf (dump, "\n;; ------------ REGIONS ----------\n\n"); | |
1279 | for (rgn = 0; rgn < nr_regions; rgn++) | |
1280 | { | |
1281 | fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn, | |
1282 | rgn_table[rgn].rgn_nr_blocks); | |
1283 | fprintf (dump, ";;\tbb/block: "); | |
1284 | ||
1285 | for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++) | |
1286 | { | |
1287 | current_blocks = RGN_BLOCKS (rgn); | |
1288 | ||
1289 | if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb))) | |
1290 | abort (); | |
1291 | ||
1292 | fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb)); | |
1293 | } | |
1294 | ||
1295 | fprintf (dump, "\n\n"); | |
1296 | } | |
1297 | } | |
1298 | ||
1299 | ||
1300 | /* Build a single block region for each basic block in the function. | |
1301 | This allows for using the same code for interblock and basic block | |
1302 | scheduling. */ | |
1303 | ||
1304 | static void | |
1305 | find_single_block_region () | |
1306 | { | |
1307 | int i; | |
1308 | ||
1309 | for (i = 0; i < n_basic_blocks; i++) | |
1310 | { | |
1311 | rgn_bb_table[i] = i; | |
1312 | RGN_NR_BLOCKS (i) = 1; | |
1313 | RGN_BLOCKS (i) = i; | |
1314 | CONTAINING_RGN (i) = i; | |
1315 | BLOCK_TO_BB (i) = 0; | |
1316 | } | |
1317 | nr_regions = n_basic_blocks; | |
1318 | } | |
1319 | ||
1320 | ||
1321 | /* Update number of blocks and the estimate for number of insns | |
1322 | in the region. Return 1 if the region is "too large" for interblock | |
1323 | scheduling (compile time considerations), otherwise return 0. */ | |
1324 | ||
1325 | static int | |
1326 | too_large (block, num_bbs, num_insns) | |
1327 | int block, *num_bbs, *num_insns; | |
1328 | { | |
1329 | (*num_bbs)++; | |
3b413743 RH |
1330 | (*num_insns) += (INSN_LUID (BLOCK_END (block)) - |
1331 | INSN_LUID (BLOCK_HEAD (block))); | |
cc132865 | 1332 | if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS)) |
8c660648 JL |
1333 | return 1; |
1334 | else | |
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | ||
1339 | /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk] | |
1340 | is still an inner loop. Put in max_hdr[blk] the header of the most inner | |
1341 | loop containing blk. */ | |
1342 | #define UPDATE_LOOP_RELATIONS(blk, hdr) \ | |
1343 | { \ | |
1344 | if (max_hdr[blk] == -1) \ | |
1345 | max_hdr[blk] = hdr; \ | |
1346 | else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \ | |
a2e68776 | 1347 | RESET_BIT (inner, hdr); \ |
8c660648 JL |
1348 | else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \ |
1349 | { \ | |
a2e68776 | 1350 | RESET_BIT (inner,max_hdr[blk]); \ |
8c660648 JL |
1351 | max_hdr[blk] = hdr; \ |
1352 | } \ | |
1353 | } | |
1354 | ||
1355 | ||
a2e68776 JL |
1356 | /* Find regions for interblock scheduling. |
1357 | ||
1358 | A region for scheduling can be: | |
1359 | ||
1360 | * A loop-free procedure, or | |
1361 | ||
1362 | * A reducible inner loop, or | |
1363 | ||
1364 | * A basic block not contained in any other region. | |
1365 | ||
1366 | ||
1367 | ?!? In theory we could build other regions based on extended basic | |
1368 | blocks or reverse extended basic blocks. Is it worth the trouble? | |
1369 | ||
1370 | Loop blocks that form a region are put into the region's block list | |
1371 | in topological order. | |
1372 | ||
1373 | This procedure stores its results into the following global (ick) variables | |
1374 | ||
1375 | * rgn_nr | |
1376 | * rgn_table | |
1377 | * rgn_bb_table | |
1378 | * block_to_bb | |
1379 | * containing region | |
1380 | ||
1381 | ||
1382 | We use dominator relationships to avoid making regions out of non-reducible | |
1383 | loops. | |
8c660648 | 1384 | |
a2e68776 JL |
1385 | This procedure needs to be converted to work on pred/succ lists instead |
1386 | of edge tables. That would simplify it somewhat. */ | |
8c660648 JL |
1387 | |
1388 | static void | |
a2e68776 JL |
1389 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom) |
1390 | int_list_ptr *s_preds; | |
1391 | int_list_ptr *s_succs; | |
1392 | int *num_preds; | |
1393 | int *num_succs; | |
1394 | sbitmap *dom; | |
8c660648 JL |
1395 | { |
1396 | int *max_hdr, *dfs_nr, *stack, *queue, *degree; | |
a2e68776 | 1397 | char no_loops = 1; |
487a6e06 | 1398 | int node, child, loop_head, i, head, tail; |
8c660648 | 1399 | int count = 0, sp, idx = 0, current_edge = out_edges[0]; |
15ebe47d | 1400 | int num_bbs, num_insns, unreachable; |
8c660648 | 1401 | int too_large_failure; |
8c660648 | 1402 | |
a2e68776 JL |
1403 | /* Note if an edge has been passed. */ |
1404 | sbitmap passed; | |
1405 | ||
1406 | /* Note if a block is a natural loop header. */ | |
1407 | sbitmap header; | |
1408 | ||
1409 | /* Note if a block is an natural inner loop header. */ | |
1410 | sbitmap inner; | |
1411 | ||
1412 | /* Note if a block is in the block queue. */ | |
1413 | sbitmap in_queue; | |
1414 | ||
cc132865 JL |
1415 | /* Note if a block is in the block queue. */ |
1416 | sbitmap in_stack; | |
1417 | ||
a2e68776 JL |
1418 | /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops |
1419 | and a mapping from block to its loop header (if the block is contained | |
1420 | in a loop, else -1). | |
1421 | ||
1422 | Store results in HEADER, INNER, and MAX_HDR respectively, these will | |
1423 | be used as inputs to the second traversal. | |
1424 | ||
1425 | STACK, SP and DFS_NR are only used during the first traversal. */ | |
1426 | ||
1427 | /* Allocate and initialize variables for the first traversal. */ | |
8c660648 JL |
1428 | max_hdr = (int *) alloca (n_basic_blocks * sizeof (int)); |
1429 | dfs_nr = (int *) alloca (n_basic_blocks * sizeof (int)); | |
52b7724b | 1430 | bzero ((char *) dfs_nr, n_basic_blocks * sizeof (int)); |
8c660648 | 1431 | stack = (int *) alloca (nr_edges * sizeof (int)); |
8c660648 | 1432 | |
a2e68776 JL |
1433 | inner = sbitmap_alloc (n_basic_blocks); |
1434 | sbitmap_ones (inner); | |
1435 | ||
1436 | header = sbitmap_alloc (n_basic_blocks); | |
1437 | sbitmap_zero (header); | |
8c660648 | 1438 | |
a2e68776 JL |
1439 | passed = sbitmap_alloc (nr_edges); |
1440 | sbitmap_zero (passed); | |
1441 | ||
1442 | in_queue = sbitmap_alloc (n_basic_blocks); | |
1443 | sbitmap_zero (in_queue); | |
8c660648 | 1444 | |
cc132865 JL |
1445 | in_stack = sbitmap_alloc (n_basic_blocks); |
1446 | sbitmap_zero (in_stack); | |
1447 | ||
8c660648 | 1448 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 | 1449 | max_hdr[i] = -1; |
8c660648 | 1450 | |
a2e68776 | 1451 | /* DFS traversal to find inner loops in the cfg. */ |
8c660648 | 1452 | |
8c660648 JL |
1453 | sp = -1; |
1454 | while (1) | |
1455 | { | |
a2e68776 | 1456 | if (current_edge == 0 || TEST_BIT (passed, current_edge)) |
8c660648 | 1457 | { |
a2e68776 | 1458 | /* We have reached a leaf node or a node that was already |
cc132865 | 1459 | processed. Pop edges off the stack until we find |
a2e68776 JL |
1460 | an edge that has not yet been processed. */ |
1461 | while (sp >= 0 | |
1462 | && (current_edge == 0 || TEST_BIT (passed, current_edge))) | |
8c660648 | 1463 | { |
a2e68776 | 1464 | /* Pop entry off the stack. */ |
8c660648 JL |
1465 | current_edge = stack[sp--]; |
1466 | node = FROM_BLOCK (current_edge); | |
1467 | child = TO_BLOCK (current_edge); | |
cc132865 JL |
1468 | RESET_BIT (in_stack, child); |
1469 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) | |
8c660648 JL |
1470 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
1471 | current_edge = NEXT_OUT (current_edge); | |
1472 | } | |
1473 | ||
a2e68776 JL |
1474 | /* See if have finished the DFS tree traversal. */ |
1475 | if (sp < 0 && TEST_BIT (passed, current_edge)) | |
8c660648 | 1476 | break; |
a2e68776 JL |
1477 | |
1478 | /* Nope, continue the traversal with the popped node. */ | |
8c660648 JL |
1479 | continue; |
1480 | } | |
1481 | ||
a2e68776 | 1482 | /* Process a node. */ |
8c660648 | 1483 | node = FROM_BLOCK (current_edge); |
8c660648 | 1484 | child = TO_BLOCK (current_edge); |
cc132865 | 1485 | SET_BIT (in_stack, node); |
a2e68776 | 1486 | dfs_nr[node] = ++count; |
8c660648 | 1487 | |
cc132865 JL |
1488 | /* If the successor is in the stack, then we've found a loop. |
1489 | Mark the loop, if it is not a natural loop, then it will | |
1490 | be rejected during the second traversal. */ | |
1491 | if (TEST_BIT (in_stack, child)) | |
8c660648 JL |
1492 | { |
1493 | no_loops = 0; | |
a2e68776 | 1494 | SET_BIT (header, child); |
8c660648 | 1495 | UPDATE_LOOP_RELATIONS (node, child); |
a2e68776 | 1496 | SET_BIT (passed, current_edge); |
8c660648 JL |
1497 | current_edge = NEXT_OUT (current_edge); |
1498 | continue; | |
1499 | } | |
1500 | ||
a2e68776 JL |
1501 | /* If the child was already visited, then there is no need to visit |
1502 | it again. Just update the loop relationships and restart | |
1503 | with a new edge. */ | |
8c660648 JL |
1504 | if (dfs_nr[child]) |
1505 | { | |
cc132865 | 1506 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) |
8c660648 | 1507 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
a2e68776 | 1508 | SET_BIT (passed, current_edge); |
8c660648 JL |
1509 | current_edge = NEXT_OUT (current_edge); |
1510 | continue; | |
1511 | } | |
1512 | ||
a2e68776 | 1513 | /* Push an entry on the stack and continue DFS traversal. */ |
8c660648 | 1514 | stack[++sp] = current_edge; |
a2e68776 | 1515 | SET_BIT (passed, current_edge); |
8c660648 | 1516 | current_edge = OUT_EDGES (child); |
50f71e6f JL |
1517 | |
1518 | /* This is temporary until haifa is converted to use rth's new | |
1519 | cfg routines which have true entry/exit blocks and the | |
1520 | appropriate edges from/to those blocks. | |
1521 | ||
1522 | Generally we update dfs_nr for a node when we process its | |
1523 | out edge. However, if the node has no out edge then we will | |
1524 | not set dfs_nr for that node. This can confuse the scheduler | |
1525 | into thinking that we have unreachable blocks, which in turn | |
1526 | disables cross block scheduling. | |
1527 | ||
1528 | So, if we have a node with no out edges, go ahead and mark it | |
1529 | as reachable now. */ | |
1530 | if (current_edge == 0) | |
1531 | dfs_nr[child] = ++count; | |
a2e68776 | 1532 | } |
8c660648 | 1533 | |
15ebe47d JL |
1534 | /* Another check for unreachable blocks. The earlier test in |
1535 | is_cfg_nonregular only finds unreachable blocks that do not | |
1536 | form a loop. | |
a2e68776 | 1537 | |
15ebe47d JL |
1538 | The DFS traversal will mark every block that is reachable from |
1539 | the entry node by placing a nonzero value in dfs_nr. Thus if | |
1540 | dfs_nr is zero for any block, then it must be unreachable. */ | |
1541 | unreachable = 0; | |
1542 | for (i = 0; i < n_basic_blocks; i++) | |
1543 | if (dfs_nr[i] == 0) | |
1544 | { | |
1545 | unreachable = 1; | |
1546 | break; | |
1547 | } | |
a2e68776 JL |
1548 | |
1549 | /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array | |
1550 | to hold degree counts. */ | |
1551 | degree = dfs_nr; | |
8c660648 | 1552 | |
63de6c74 | 1553 | /* Compute the in-degree of every block in the graph. */ |
8c660648 | 1554 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 JL |
1555 | degree[i] = num_preds[i]; |
1556 | ||
15ebe47d JL |
1557 | /* Do not perform region scheduling if there are any unreachable |
1558 | blocks. */ | |
1559 | if (!unreachable) | |
8c660648 | 1560 | { |
15ebe47d JL |
1561 | if (no_loops) |
1562 | SET_BIT (header, 0); | |
8c660648 | 1563 | |
15ebe47d JL |
1564 | /* Second travsersal:find reducible inner loops and topologically sort |
1565 | block of each region. */ | |
8c660648 | 1566 | |
15ebe47d | 1567 | queue = (int *) alloca (n_basic_blocks * sizeof (int)); |
8c660648 | 1568 | |
cc132865 JL |
1569 | /* Find blocks which are inner loop headers. We still have non-reducible |
1570 | loops to consider at this point. */ | |
15ebe47d JL |
1571 | for (i = 0; i < n_basic_blocks; i++) |
1572 | { | |
1573 | if (TEST_BIT (header, i) && TEST_BIT (inner, i)) | |
1574 | { | |
1575 | int_list_ptr ps; | |
cc132865 JL |
1576 | int j; |
1577 | ||
1578 | /* Now check that the loop is reducible. We do this separate | |
1579 | from finding inner loops so that we do not find a reducible | |
63de6c74 | 1580 | loop which contains an inner non-reducible loop. |
cc132865 | 1581 | |
63de6c74 | 1582 | A simple way to find reducible/natural loops is to verify |
cc132865 JL |
1583 | that each block in the loop is dominated by the loop |
1584 | header. | |
1585 | ||
1586 | If there exists a block that is not dominated by the loop | |
1587 | header, then the block is reachable from outside the loop | |
1588 | and thus the loop is not a natural loop. */ | |
1589 | for (j = 0; j < n_basic_blocks; j++) | |
1590 | { | |
1591 | /* First identify blocks in the loop, except for the loop | |
1592 | entry block. */ | |
1593 | if (i == max_hdr[j] && i != j) | |
1594 | { | |
1595 | /* Now verify that the block is dominated by the loop | |
1596 | header. */ | |
1597 | if (!TEST_BIT (dom[j], i)) | |
1598 | break; | |
1599 | } | |
1600 | } | |
1601 | ||
63de6c74 MH |
1602 | /* If we exited the loop early, then I is the header of |
1603 | a non-reducible loop and we should quit processing it | |
1604 | now. */ | |
cc132865 JL |
1605 | if (j != n_basic_blocks) |
1606 | continue; | |
8c660648 | 1607 | |
cc132865 JL |
1608 | /* I is a header of an inner loop, or block 0 in a subroutine |
1609 | with no loops at all. */ | |
15ebe47d JL |
1610 | head = tail = -1; |
1611 | too_large_failure = 0; | |
1612 | loop_head = max_hdr[i]; | |
8c660648 | 1613 | |
15ebe47d | 1614 | /* Decrease degree of all I's successors for topological |
a59bfd78 | 1615 | ordering. */ |
15ebe47d JL |
1616 | for (ps = s_succs[i]; ps; ps = ps->next) |
1617 | if (INT_LIST_VAL (ps) != EXIT_BLOCK | |
1618 | && INT_LIST_VAL (ps) != ENTRY_BLOCK) | |
cc132865 | 1619 | --degree[INT_LIST_VAL(ps)]; |
a2e68776 | 1620 | |
15ebe47d JL |
1621 | /* Estimate # insns, and count # blocks in the region. */ |
1622 | num_bbs = 1; | |
3b413743 RH |
1623 | num_insns = (INSN_LUID (BLOCK_END (i)) |
1624 | - INSN_LUID (BLOCK_HEAD (i))); | |
8c660648 | 1625 | |
15ebe47d | 1626 | |
63de6c74 | 1627 | /* Find all loop latches (blocks with back edges to the loop |
15ebe47d JL |
1628 | header) or all the leaf blocks in the cfg has no loops. |
1629 | ||
1630 | Place those blocks into the queue. */ | |
1631 | if (no_loops) | |
1632 | { | |
1633 | for (j = 0; j < n_basic_blocks; j++) | |
1634 | /* Leaf nodes have only a single successor which must | |
1635 | be EXIT_BLOCK. */ | |
1636 | if (num_succs[j] == 1 | |
1637 | && INT_LIST_VAL (s_succs[j]) == EXIT_BLOCK) | |
8c660648 | 1638 | { |
15ebe47d JL |
1639 | queue[++tail] = j; |
1640 | SET_BIT (in_queue, j); | |
1641 | ||
1642 | if (too_large (j, &num_bbs, &num_insns)) | |
1643 | { | |
1644 | too_large_failure = 1; | |
1645 | break; | |
1646 | } | |
8c660648 | 1647 | } |
15ebe47d JL |
1648 | } |
1649 | else | |
8c660648 | 1650 | { |
15ebe47d | 1651 | int_list_ptr ps; |
a2e68776 | 1652 | |
15ebe47d | 1653 | for (ps = s_preds[i]; ps; ps = ps->next) |
8c660648 | 1654 | { |
15ebe47d | 1655 | node = INT_LIST_VAL (ps); |
8c660648 | 1656 | |
15ebe47d JL |
1657 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK) |
1658 | continue; | |
1659 | ||
1660 | if (max_hdr[node] == loop_head && node != i) | |
8c660648 | 1661 | { |
15ebe47d JL |
1662 | /* This is a loop latch. */ |
1663 | queue[++tail] = node; | |
1664 | SET_BIT (in_queue, node); | |
1665 | ||
1666 | if (too_large (node, &num_bbs, &num_insns)) | |
1667 | { | |
1668 | too_large_failure = 1; | |
1669 | break; | |
1670 | } | |
8c660648 | 1671 | } |
15ebe47d | 1672 | |
8c660648 | 1673 | } |
8c660648 | 1674 | } |
8c660648 | 1675 | |
15ebe47d | 1676 | /* Now add all the blocks in the loop to the queue. |
a2e68776 JL |
1677 | |
1678 | We know the loop is a natural loop; however the algorithm | |
1679 | above will not always mark certain blocks as being in the | |
1680 | loop. Consider: | |
1681 | node children | |
1682 | a b,c | |
1683 | b c | |
1684 | c a,d | |
1685 | d b | |
1686 | ||
1687 | ||
1688 | The algorithm in the DFS traversal may not mark B & D as part | |
1689 | of the loop (ie they will not have max_hdr set to A). | |
1690 | ||
1691 | We know they can not be loop latches (else they would have | |
1692 | had max_hdr set since they'd have a backedge to a dominator | |
1693 | block). So we don't need them on the initial queue. | |
1694 | ||
1695 | We know they are part of the loop because they are dominated | |
1696 | by the loop header and can be reached by a backwards walk of | |
1697 | the edges starting with nodes on the initial queue. | |
1698 | ||
1699 | It is safe and desirable to include those nodes in the | |
1700 | loop/scheduling region. To do so we would need to decrease | |
1701 | the degree of a node if it is the target of a backedge | |
1702 | within the loop itself as the node is placed in the queue. | |
1703 | ||
1704 | We do not do this because I'm not sure that the actual | |
1705 | scheduling code will properly handle this case. ?!? */ | |
1706 | ||
15ebe47d | 1707 | while (head < tail && !too_large_failure) |
8c660648 | 1708 | { |
15ebe47d JL |
1709 | int_list_ptr ps; |
1710 | child = queue[++head]; | |
8c660648 | 1711 | |
15ebe47d | 1712 | for (ps = s_preds[child]; ps; ps = ps->next) |
8c660648 | 1713 | { |
15ebe47d | 1714 | node = INT_LIST_VAL (ps); |
8c660648 | 1715 | |
15ebe47d JL |
1716 | /* See discussion above about nodes not marked as in |
1717 | this loop during the initial DFS traversal. */ | |
1718 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK | |
1719 | || max_hdr[node] != loop_head) | |
8c660648 | 1720 | { |
15ebe47d | 1721 | tail = -1; |
8c660648 JL |
1722 | break; |
1723 | } | |
15ebe47d JL |
1724 | else if (!TEST_BIT (in_queue, node) && node != i) |
1725 | { | |
1726 | queue[++tail] = node; | |
1727 | SET_BIT (in_queue, node); | |
1728 | ||
1729 | if (too_large (node, &num_bbs, &num_insns)) | |
1730 | { | |
1731 | too_large_failure = 1; | |
1732 | break; | |
1733 | } | |
1734 | } | |
8c660648 | 1735 | } |
8c660648 | 1736 | } |
8c660648 | 1737 | |
15ebe47d JL |
1738 | if (tail >= 0 && !too_large_failure) |
1739 | { | |
1740 | /* Place the loop header into list of region blocks. */ | |
1741 | degree[i] = -1; | |
1742 | rgn_bb_table[idx] = i; | |
1743 | RGN_NR_BLOCKS (nr_regions) = num_bbs; | |
1744 | RGN_BLOCKS (nr_regions) = idx++; | |
1745 | CONTAINING_RGN (i) = nr_regions; | |
1746 | BLOCK_TO_BB (i) = count = 0; | |
1747 | ||
63de6c74 MH |
1748 | /* Remove blocks from queue[] when their in degree |
1749 | becomes zero. Repeat until no blocks are left on the | |
1750 | list. This produces a topological list of blocks in | |
1751 | the region. */ | |
15ebe47d | 1752 | while (tail >= 0) |
8c660648 | 1753 | { |
15ebe47d JL |
1754 | int_list_ptr ps; |
1755 | ||
1756 | if (head < 0) | |
1757 | head = tail; | |
1758 | child = queue[head]; | |
1759 | if (degree[child] == 0) | |
1760 | { | |
1761 | degree[child] = -1; | |
1762 | rgn_bb_table[idx++] = child; | |
1763 | BLOCK_TO_BB (child) = ++count; | |
1764 | CONTAINING_RGN (child) = nr_regions; | |
1765 | queue[head] = queue[tail--]; | |
1766 | ||
1767 | for (ps = s_succs[child]; ps; ps = ps->next) | |
1768 | if (INT_LIST_VAL (ps) != ENTRY_BLOCK | |
1769 | && INT_LIST_VAL (ps) != EXIT_BLOCK) | |
1770 | --degree[INT_LIST_VAL (ps)]; | |
1771 | } | |
1772 | else | |
1773 | --head; | |
8c660648 | 1774 | } |
15ebe47d | 1775 | ++nr_regions; |
8c660648 | 1776 | } |
8c660648 JL |
1777 | } |
1778 | } | |
1779 | } | |
1780 | ||
a2e68776 JL |
1781 | /* Any block that did not end up in a region is placed into a region |
1782 | by itself. */ | |
8c660648 JL |
1783 | for (i = 0; i < n_basic_blocks; i++) |
1784 | if (degree[i] >= 0) | |
1785 | { | |
1786 | rgn_bb_table[idx] = i; | |
1787 | RGN_NR_BLOCKS (nr_regions) = 1; | |
1788 | RGN_BLOCKS (nr_regions) = idx++; | |
1789 | CONTAINING_RGN (i) = nr_regions++; | |
1790 | BLOCK_TO_BB (i) = 0; | |
1791 | } | |
1792 | ||
a2e68776 JL |
1793 | free (passed); |
1794 | free (header); | |
1795 | free (inner); | |
1796 | free (in_queue); | |
cc132865 | 1797 | free (in_stack); |
a2e68776 | 1798 | } |
8c660648 JL |
1799 | |
1800 | ||
63de6c74 | 1801 | /* Functions for regions scheduling information. */ |
8c660648 JL |
1802 | |
1803 | /* Compute dominators, probability, and potential-split-edges of bb. | |
1804 | Assume that these values were already computed for bb's predecessors. */ | |
1805 | ||
1806 | static void | |
1807 | compute_dom_prob_ps (bb) | |
1808 | int bb; | |
1809 | { | |
1810 | int nxt_in_edge, fst_in_edge, pred; | |
1811 | int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges; | |
1812 | ||
1813 | prob[bb] = 0.0; | |
1814 | if (IS_RGN_ENTRY (bb)) | |
1815 | { | |
1816 | BITSET_ADD (dom[bb], 0, bbset_size); | |
1817 | prob[bb] = 1.0; | |
1818 | return; | |
1819 | } | |
1820 | ||
1821 | fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb)); | |
1822 | ||
63de6c74 | 1823 | /* Intialize dom[bb] to '111..1'. */ |
8c660648 JL |
1824 | BITSET_INVERT (dom[bb], bbset_size); |
1825 | ||
1826 | do | |
1827 | { | |
1828 | pred = FROM_BLOCK (nxt_in_edge); | |
1829 | BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size); | |
1830 | ||
1831 | BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)], | |
1832 | edgeset_size); | |
1833 | ||
1834 | BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size); | |
1835 | ||
1836 | nr_out_edges = 1; | |
1837 | nr_rgn_out_edges = 0; | |
1838 | fst_out_edge = OUT_EDGES (pred); | |
1839 | nxt_out_edge = NEXT_OUT (fst_out_edge); | |
1840 | BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)], | |
1841 | edgeset_size); | |
1842 | ||
1843 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size); | |
1844 | ||
63de6c74 | 1845 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1846 | if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) != |
1847 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1848 | ++nr_rgn_out_edges; | |
1849 | ||
1850 | while (fst_out_edge != nxt_out_edge) | |
1851 | { | |
1852 | ++nr_out_edges; | |
63de6c74 | 1853 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1854 | if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) != |
1855 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1856 | ++nr_rgn_out_edges; | |
1857 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size); | |
1858 | nxt_out_edge = NEXT_OUT (nxt_out_edge); | |
1859 | ||
1860 | } | |
1861 | ||
63de6c74 MH |
1862 | /* Now nr_rgn_out_edges is the number of region-exit edges from |
1863 | pred, and nr_out_edges will be the number of pred out edges | |
1864 | not leaving the region. */ | |
8c660648 JL |
1865 | nr_out_edges -= nr_rgn_out_edges; |
1866 | if (nr_rgn_out_edges > 0) | |
1867 | prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1868 | else | |
1869 | prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1870 | nxt_in_edge = NEXT_IN (nxt_in_edge); | |
1871 | } | |
1872 | while (fst_in_edge != nxt_in_edge); | |
1873 | ||
1874 | BITSET_ADD (dom[bb], bb, bbset_size); | |
1875 | BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size); | |
1876 | ||
1877 | if (sched_verbose >= 2) | |
1878 | fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb])); | |
1879 | } /* compute_dom_prob_ps */ | |
1880 | ||
63de6c74 | 1881 | /* Functions for target info. */ |
8c660648 JL |
1882 | |
1883 | /* Compute in BL the list of split-edges of bb_src relatively to bb_trg. | |
1884 | Note that bb_trg dominates bb_src. */ | |
1885 | ||
1886 | static void | |
1887 | split_edges (bb_src, bb_trg, bl) | |
1888 | int bb_src; | |
1889 | int bb_trg; | |
1890 | edgelst *bl; | |
1891 | { | |
1892 | int es = edgeset_size; | |
1893 | edgeset src = (edgeset) alloca (es * sizeof (HOST_WIDE_INT)); | |
1894 | ||
1895 | while (es--) | |
1896 | src[es] = (pot_split[bb_src])[es]; | |
1897 | BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size); | |
1898 | extract_bitlst (src, edgeset_size, bl); | |
1899 | } | |
1900 | ||
1901 | ||
1902 | /* Find the valid candidate-source-blocks for the target block TRG, compute | |
1903 | their probability, and check if they are speculative or not. | |
1904 | For speculative sources, compute their update-blocks and split-blocks. */ | |
1905 | ||
1906 | static void | |
1907 | compute_trg_info (trg) | |
1908 | int trg; | |
1909 | { | |
1910 | register candidate *sp; | |
1911 | edgelst el; | |
1912 | int check_block, update_idx; | |
1913 | int i, j, k, fst_edge, nxt_edge; | |
1914 | ||
63de6c74 | 1915 | /* Define some of the fields for the target bb as well. */ |
8c660648 JL |
1916 | sp = candidate_table + trg; |
1917 | sp->is_valid = 1; | |
1918 | sp->is_speculative = 0; | |
1919 | sp->src_prob = 100; | |
1920 | ||
1921 | for (i = trg + 1; i < current_nr_blocks; i++) | |
1922 | { | |
1923 | sp = candidate_table + i; | |
1924 | ||
1925 | sp->is_valid = IS_DOMINATED (i, trg); | |
1926 | if (sp->is_valid) | |
1927 | { | |
1928 | sp->src_prob = GET_SRC_PROB (i, trg); | |
1929 | sp->is_valid = (sp->src_prob >= MIN_PROBABILITY); | |
1930 | } | |
1931 | ||
1932 | if (sp->is_valid) | |
1933 | { | |
1934 | split_edges (i, trg, &el); | |
1935 | sp->is_speculative = (el.nr_members) ? 1 : 0; | |
1936 | if (sp->is_speculative && !flag_schedule_speculative) | |
1937 | sp->is_valid = 0; | |
1938 | } | |
1939 | ||
1940 | if (sp->is_valid) | |
1941 | { | |
1942 | sp->split_bbs.first_member = &bblst_table[bblst_last]; | |
1943 | sp->split_bbs.nr_members = el.nr_members; | |
1944 | for (j = 0; j < el.nr_members; bblst_last++, j++) | |
1945 | bblst_table[bblst_last] = | |
1946 | TO_BLOCK (rgn_edges[el.first_member[j]]); | |
1947 | sp->update_bbs.first_member = &bblst_table[bblst_last]; | |
1948 | update_idx = 0; | |
1949 | for (j = 0; j < el.nr_members; j++) | |
1950 | { | |
1951 | check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]); | |
1952 | fst_edge = nxt_edge = OUT_EDGES (check_block); | |
1953 | do | |
1954 | { | |
1955 | for (k = 0; k < el.nr_members; k++) | |
1956 | if (EDGE_TO_BIT (nxt_edge) == el.first_member[k]) | |
1957 | break; | |
1958 | ||
1959 | if (k >= el.nr_members) | |
1960 | { | |
1961 | bblst_table[bblst_last++] = TO_BLOCK (nxt_edge); | |
1962 | update_idx++; | |
1963 | } | |
1964 | ||
1965 | nxt_edge = NEXT_OUT (nxt_edge); | |
1966 | } | |
1967 | while (fst_edge != nxt_edge); | |
1968 | } | |
1969 | sp->update_bbs.nr_members = update_idx; | |
1970 | ||
1971 | } | |
1972 | else | |
1973 | { | |
1974 | sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0; | |
1975 | ||
1976 | sp->is_speculative = 0; | |
1977 | sp->src_prob = 0; | |
1978 | } | |
1979 | } | |
1980 | } /* compute_trg_info */ | |
1981 | ||
1982 | ||
1983 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
1984 | ||
1985 | void | |
1986 | debug_candidate (i) | |
1987 | int i; | |
1988 | { | |
1989 | if (!candidate_table[i].is_valid) | |
1990 | return; | |
1991 | ||
1992 | if (candidate_table[i].is_speculative) | |
1993 | { | |
1994 | int j; | |
1995 | fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i); | |
1996 | ||
1997 | fprintf (dump, "split path: "); | |
1998 | for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++) | |
1999 | { | |
2000 | int b = candidate_table[i].split_bbs.first_member[j]; | |
2001 | ||
2002 | fprintf (dump, " %d ", b); | |
2003 | } | |
2004 | fprintf (dump, "\n"); | |
2005 | ||
2006 | fprintf (dump, "update path: "); | |
2007 | for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++) | |
2008 | { | |
2009 | int b = candidate_table[i].update_bbs.first_member[j]; | |
2010 | ||
2011 | fprintf (dump, " %d ", b); | |
2012 | } | |
2013 | fprintf (dump, "\n"); | |
2014 | } | |
2015 | else | |
2016 | { | |
2017 | fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i)); | |
2018 | } | |
2019 | } | |
2020 | ||
2021 | ||
2022 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
2023 | ||
2024 | void | |
2025 | debug_candidates (trg) | |
2026 | int trg; | |
2027 | { | |
2028 | int i; | |
2029 | ||
2030 | fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n", | |
2031 | BB_TO_BLOCK (trg), trg); | |
2032 | for (i = trg + 1; i < current_nr_blocks; i++) | |
2033 | debug_candidate (i); | |
2034 | } | |
2035 | ||
2036 | ||
63de6c74 | 2037 | /* Functions for speculative scheduing. */ |
8c660648 JL |
2038 | |
2039 | /* Return 0 if x is a set of a register alive in the beginning of one | |
2040 | of the split-blocks of src, otherwise return 1. */ | |
2041 | ||
2042 | static int | |
2043 | check_live_1 (src, x) | |
2044 | int src; | |
2045 | rtx x; | |
2046 | { | |
5835e573 | 2047 | register int i; |
8c660648 JL |
2048 | register int regno; |
2049 | register rtx reg = SET_DEST (x); | |
2050 | ||
2051 | if (reg == 0) | |
2052 | return 1; | |
2053 | ||
2054 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2055 | || GET_CODE (reg) == SIGN_EXTRACT | |
2056 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2057 | reg = XEXP (reg, 0); | |
2058 | ||
c0222c21 DM |
2059 | if (GET_CODE (reg) == PARALLEL |
2060 | && GET_MODE (reg) == BLKmode) | |
2061 | { | |
2062 | register int i; | |
2063 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2064 | if (check_live_1 (src, XVECEXP (reg, 0, i))) | |
2065 | return 1; | |
2066 | return 0; | |
2067 | } | |
2068 | ||
8c660648 JL |
2069 | if (GET_CODE (reg) != REG) |
2070 | return 1; | |
2071 | ||
2072 | regno = REGNO (reg); | |
2073 | ||
2074 | if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno]) | |
2075 | { | |
63de6c74 | 2076 | /* Global registers are assumed live. */ |
8c660648 JL |
2077 | return 0; |
2078 | } | |
2079 | else | |
2080 | { | |
2081 | if (regno < FIRST_PSEUDO_REGISTER) | |
2082 | { | |
63de6c74 | 2083 | /* Check for hard registers. */ |
8c660648 JL |
2084 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); |
2085 | while (--j >= 0) | |
2086 | { | |
2087 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) | |
2088 | { | |
2089 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2090 | ||
e881bb1b RH |
2091 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, |
2092 | regno + j)) | |
8c660648 JL |
2093 | { |
2094 | return 0; | |
2095 | } | |
2096 | } | |
2097 | } | |
2098 | } | |
2099 | else | |
2100 | { | |
63de6c74 | 2101 | /* Check for psuedo registers. */ |
8c660648 JL |
2102 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) |
2103 | { | |
2104 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2105 | ||
e881bb1b | 2106 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, regno)) |
8c660648 JL |
2107 | { |
2108 | return 0; | |
2109 | } | |
2110 | } | |
2111 | } | |
2112 | } | |
2113 | ||
2114 | return 1; | |
2115 | } | |
2116 | ||
2117 | ||
2118 | /* If x is a set of a register R, mark that R is alive in the beginning | |
2119 | of every update-block of src. */ | |
2120 | ||
2121 | static void | |
2122 | update_live_1 (src, x) | |
2123 | int src; | |
2124 | rtx x; | |
2125 | { | |
5835e573 | 2126 | register int i; |
8c660648 JL |
2127 | register int regno; |
2128 | register rtx reg = SET_DEST (x); | |
2129 | ||
2130 | if (reg == 0) | |
2131 | return; | |
2132 | ||
2133 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2134 | || GET_CODE (reg) == SIGN_EXTRACT | |
2135 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2136 | reg = XEXP (reg, 0); | |
2137 | ||
c0222c21 DM |
2138 | if (GET_CODE (reg) == PARALLEL |
2139 | && GET_MODE (reg) == BLKmode) | |
2140 | { | |
2141 | register int i; | |
2142 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2143 | update_live_1 (src, XVECEXP (reg, 0, i)); | |
2144 | return; | |
2145 | } | |
2146 | ||
8c660648 JL |
2147 | if (GET_CODE (reg) != REG) |
2148 | return; | |
2149 | ||
2150 | /* Global registers are always live, so the code below does not apply | |
2151 | to them. */ | |
2152 | ||
2153 | regno = REGNO (reg); | |
2154 | ||
2155 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
2156 | { | |
2157 | if (regno < FIRST_PSEUDO_REGISTER) | |
2158 | { | |
2159 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2160 | while (--j >= 0) | |
2161 | { | |
2162 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2163 | { | |
2164 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2165 | ||
e881bb1b RH |
2166 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, |
2167 | regno + j); | |
8c660648 JL |
2168 | } |
2169 | } | |
2170 | } | |
2171 | else | |
2172 | { | |
2173 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2174 | { | |
2175 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2176 | ||
e881bb1b | 2177 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, regno); |
8c660648 JL |
2178 | } |
2179 | } | |
2180 | } | |
2181 | } | |
2182 | ||
2183 | ||
2184 | /* Return 1 if insn can be speculatively moved from block src to trg, | |
2185 | otherwise return 0. Called before first insertion of insn to | |
2186 | ready-list or before the scheduling. */ | |
2187 | ||
2188 | static int | |
5835e573 | 2189 | check_live (insn, src) |
8c660648 JL |
2190 | rtx insn; |
2191 | int src; | |
8c660648 | 2192 | { |
63de6c74 | 2193 | /* Find the registers set by instruction. */ |
8c660648 JL |
2194 | if (GET_CODE (PATTERN (insn)) == SET |
2195 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2196 | return check_live_1 (src, PATTERN (insn)); | |
2197 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2198 | { | |
2199 | int j; | |
2200 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2201 | if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2202 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2203 | && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j))) | |
2204 | return 0; | |
2205 | ||
2206 | return 1; | |
2207 | } | |
2208 | ||
2209 | return 1; | |
2210 | } | |
2211 | ||
2212 | ||
2213 | /* Update the live registers info after insn was moved speculatively from | |
2214 | block src to trg. */ | |
2215 | ||
2216 | static void | |
5835e573 | 2217 | update_live (insn, src) |
8c660648 | 2218 | rtx insn; |
5835e573 | 2219 | int src; |
8c660648 | 2220 | { |
63de6c74 | 2221 | /* Find the registers set by instruction. */ |
8c660648 JL |
2222 | if (GET_CODE (PATTERN (insn)) == SET |
2223 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2224 | update_live_1 (src, PATTERN (insn)); | |
2225 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2226 | { | |
2227 | int j; | |
2228 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2229 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2230 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2231 | update_live_1 (src, XVECEXP (PATTERN (insn), 0, j)); | |
2232 | } | |
2233 | } | |
2234 | ||
2235 | /* Exception Free Loads: | |
2236 | ||
2237 | We define five classes of speculative loads: IFREE, IRISKY, | |
2238 | PFREE, PRISKY, and MFREE. | |
2239 | ||
2240 | IFREE loads are loads that are proved to be exception-free, just | |
2241 | by examining the load insn. Examples for such loads are loads | |
2242 | from TOC and loads of global data. | |
2243 | ||
2244 | IRISKY loads are loads that are proved to be exception-risky, | |
2245 | just by examining the load insn. Examples for such loads are | |
2246 | volatile loads and loads from shared memory. | |
2247 | ||
2248 | PFREE loads are loads for which we can prove, by examining other | |
2249 | insns, that they are exception-free. Currently, this class consists | |
2250 | of loads for which we are able to find a "similar load", either in | |
2251 | the target block, or, if only one split-block exists, in that split | |
2252 | block. Load2 is similar to load1 if both have same single base | |
2253 | register. We identify only part of the similar loads, by finding | |
2254 | an insn upon which both load1 and load2 have a DEF-USE dependence. | |
2255 | ||
2256 | PRISKY loads are loads for which we can prove, by examining other | |
2257 | insns, that they are exception-risky. Currently we have two proofs for | |
2258 | such loads. The first proof detects loads that are probably guarded by a | |
2259 | test on the memory address. This proof is based on the | |
2260 | backward and forward data dependence information for the region. | |
2261 | Let load-insn be the examined load. | |
2262 | Load-insn is PRISKY iff ALL the following hold: | |
2263 | ||
2264 | - insn1 is not in the same block as load-insn | |
2265 | - there is a DEF-USE dependence chain (insn1, ..., load-insn) | |
63de6c74 MH |
2266 | - test-insn is either a compare or a branch, not in the same block |
2267 | as load-insn | |
8c660648 JL |
2268 | - load-insn is reachable from test-insn |
2269 | - there is a DEF-USE dependence chain (insn1, ..., test-insn) | |
2270 | ||
2271 | This proof might fail when the compare and the load are fed | |
2272 | by an insn not in the region. To solve this, we will add to this | |
2273 | group all loads that have no input DEF-USE dependence. | |
2274 | ||
2275 | The second proof detects loads that are directly or indirectly | |
2276 | fed by a speculative load. This proof is affected by the | |
2277 | scheduling process. We will use the flag fed_by_spec_load. | |
2278 | Initially, all insns have this flag reset. After a speculative | |
2279 | motion of an insn, if insn is either a load, or marked as | |
2280 | fed_by_spec_load, we will also mark as fed_by_spec_load every | |
2281 | insn1 for which a DEF-USE dependence (insn, insn1) exists. A | |
2282 | load which is fed_by_spec_load is also PRISKY. | |
2283 | ||
2284 | MFREE (maybe-free) loads are all the remaining loads. They may be | |
2285 | exception-free, but we cannot prove it. | |
2286 | ||
2287 | Now, all loads in IFREE and PFREE classes are considered | |
2288 | exception-free, while all loads in IRISKY and PRISKY classes are | |
2289 | considered exception-risky. As for loads in the MFREE class, | |
2290 | these are considered either exception-free or exception-risky, | |
2291 | depending on whether we are pessimistic or optimistic. We have | |
2292 | to take the pessimistic approach to assure the safety of | |
2293 | speculative scheduling, but we can take the optimistic approach | |
2294 | by invoking the -fsched_spec_load_dangerous option. */ | |
2295 | ||
2296 | enum INSN_TRAP_CLASS | |
2297 | { | |
2298 | TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2, | |
2299 | PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5 | |
2300 | }; | |
2301 | ||
2302 | #define WORST_CLASS(class1, class2) \ | |
2303 | ((class1 > class2) ? class1 : class2) | |
2304 | ||
63de6c74 MH |
2305 | /* Indexed by INSN_UID, and set if there's DEF-USE dependence between |
2306 | some speculatively moved load insn and this one. */ | |
8c660648 JL |
2307 | char *fed_by_spec_load; |
2308 | char *is_load_insn; | |
2309 | ||
2310 | /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */ | |
2311 | #define IS_REACHABLE(bb_from, bb_to) \ | |
2312 | (bb_from == bb_to \ | |
2313 | || IS_RGN_ENTRY (bb_from) \ | |
2314 | || (bitset_member (ancestor_edges[bb_to], \ | |
2315 | EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \ | |
2316 | edgeset_size))) | |
2317 | #define FED_BY_SPEC_LOAD(insn) (fed_by_spec_load[INSN_UID (insn)]) | |
2318 | #define IS_LOAD_INSN(insn) (is_load_insn[INSN_UID (insn)]) | |
2319 | ||
63de6c74 | 2320 | /* Non-zero iff the address is comprised from at most 1 register. */ |
8c660648 JL |
2321 | #define CONST_BASED_ADDRESS_P(x) \ |
2322 | (GET_CODE (x) == REG \ | |
2323 | || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \ | |
2324 | || (GET_CODE (x) == LO_SUM)) \ | |
2325 | && (GET_CODE (XEXP (x, 0)) == CONST_INT \ | |
2326 | || GET_CODE (XEXP (x, 1)) == CONST_INT))) | |
2327 | ||
2328 | /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */ | |
2329 | ||
2330 | static void | |
2331 | set_spec_fed (load_insn) | |
2332 | rtx load_insn; | |
2333 | { | |
2334 | rtx link; | |
2335 | ||
2336 | for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1)) | |
2337 | if (GET_MODE (link) == VOIDmode) | |
2338 | FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1; | |
2339 | } /* set_spec_fed */ | |
2340 | ||
63de6c74 MH |
2341 | /* On the path from the insn to load_insn_bb, find a conditional |
2342 | branch depending on insn, that guards the speculative load. */ | |
8c660648 JL |
2343 | |
2344 | static int | |
2345 | find_conditional_protection (insn, load_insn_bb) | |
2346 | rtx insn; | |
2347 | int load_insn_bb; | |
2348 | { | |
2349 | rtx link; | |
2350 | ||
63de6c74 | 2351 | /* Iterate through DEF-USE forward dependences. */ |
8c660648 JL |
2352 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) |
2353 | { | |
2354 | rtx next = XEXP (link, 0); | |
2355 | if ((CONTAINING_RGN (INSN_BLOCK (next)) == | |
2356 | CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb))) | |
2357 | && IS_REACHABLE (INSN_BB (next), load_insn_bb) | |
2358 | && load_insn_bb != INSN_BB (next) | |
2359 | && GET_MODE (link) == VOIDmode | |
2360 | && (GET_CODE (next) == JUMP_INSN | |
2361 | || find_conditional_protection (next, load_insn_bb))) | |
2362 | return 1; | |
2363 | } | |
2364 | return 0; | |
2365 | } /* find_conditional_protection */ | |
2366 | ||
2367 | /* Returns 1 if the same insn1 that participates in the computation | |
2368 | of load_insn's address is feeding a conditional branch that is | |
2369 | guarding on load_insn. This is true if we find a the two DEF-USE | |
2370 | chains: | |
2371 | insn1 -> ... -> conditional-branch | |
2372 | insn1 -> ... -> load_insn, | |
2373 | and if a flow path exist: | |
2374 | insn1 -> ... -> conditional-branch -> ... -> load_insn, | |
2375 | and if insn1 is on the path | |
2376 | region-entry -> ... -> bb_trg -> ... load_insn. | |
2377 | ||
2378 | Locate insn1 by climbing on LOG_LINKS from load_insn. | |
2379 | Locate the branch by following INSN_DEPEND from insn1. */ | |
2380 | ||
2381 | static int | |
2382 | is_conditionally_protected (load_insn, bb_src, bb_trg) | |
2383 | rtx load_insn; | |
2384 | int bb_src, bb_trg; | |
2385 | { | |
2386 | rtx link; | |
2387 | ||
2388 | for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1)) | |
2389 | { | |
2390 | rtx insn1 = XEXP (link, 0); | |
2391 | ||
63de6c74 | 2392 | /* Must be a DEF-USE dependence upon non-branch. */ |
8c660648 JL |
2393 | if (GET_MODE (link) != VOIDmode |
2394 | || GET_CODE (insn1) == JUMP_INSN) | |
2395 | continue; | |
2396 | ||
63de6c74 | 2397 | /* Must exist a path: region-entry -> ... -> bb_trg -> ... load_insn. */ |
8c660648 JL |
2398 | if (INSN_BB (insn1) == bb_src |
2399 | || (CONTAINING_RGN (INSN_BLOCK (insn1)) | |
2400 | != CONTAINING_RGN (BB_TO_BLOCK (bb_src))) | |
2401 | || (!IS_REACHABLE (bb_trg, INSN_BB (insn1)) | |
2402 | && !IS_REACHABLE (INSN_BB (insn1), bb_trg))) | |
2403 | continue; | |
2404 | ||
63de6c74 | 2405 | /* Now search for the conditional-branch. */ |
8c660648 JL |
2406 | if (find_conditional_protection (insn1, bb_src)) |
2407 | return 1; | |
2408 | ||
63de6c74 | 2409 | /* Recursive step: search another insn1, "above" current insn1. */ |
8c660648 JL |
2410 | return is_conditionally_protected (insn1, bb_src, bb_trg); |
2411 | } | |
2412 | ||
63de6c74 | 2413 | /* The chain does not exist. */ |
8c660648 JL |
2414 | return 0; |
2415 | } /* is_conditionally_protected */ | |
2416 | ||
2417 | /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence | |
2418 | load_insn can move speculatively from bb_src to bb_trg. All the | |
2419 | following must hold: | |
2420 | ||
2421 | (1) both loads have 1 base register (PFREE_CANDIDATEs). | |
2422 | (2) load_insn and load1 have a def-use dependence upon | |
2423 | the same insn 'insn1'. | |
2424 | (3) either load2 is in bb_trg, or: | |
2425 | - there's only one split-block, and | |
2426 | - load1 is on the escape path, and | |
2427 | ||
2428 | From all these we can conclude that the two loads access memory | |
2429 | addresses that differ at most by a constant, and hence if moving | |
2430 | load_insn would cause an exception, it would have been caused by | |
2431 | load2 anyhow. */ | |
2432 | ||
2433 | static int | |
2434 | is_pfree (load_insn, bb_src, bb_trg) | |
2435 | rtx load_insn; | |
2436 | int bb_src, bb_trg; | |
2437 | { | |
2438 | rtx back_link; | |
2439 | register candidate *candp = candidate_table + bb_src; | |
2440 | ||
2441 | if (candp->split_bbs.nr_members != 1) | |
63de6c74 | 2442 | /* Must have exactly one escape block. */ |
8c660648 JL |
2443 | return 0; |
2444 | ||
2445 | for (back_link = LOG_LINKS (load_insn); | |
2446 | back_link; back_link = XEXP (back_link, 1)) | |
2447 | { | |
2448 | rtx insn1 = XEXP (back_link, 0); | |
2449 | ||
2450 | if (GET_MODE (back_link) == VOIDmode) | |
2451 | { | |
63de6c74 | 2452 | /* Found a DEF-USE dependence (insn1, load_insn). */ |
8c660648 JL |
2453 | rtx fore_link; |
2454 | ||
2455 | for (fore_link = INSN_DEPEND (insn1); | |
2456 | fore_link; fore_link = XEXP (fore_link, 1)) | |
2457 | { | |
2458 | rtx insn2 = XEXP (fore_link, 0); | |
2459 | if (GET_MODE (fore_link) == VOIDmode) | |
2460 | { | |
63de6c74 | 2461 | /* Found a DEF-USE dependence (insn1, insn2). */ |
ac957f13 | 2462 | if (haifa_classify_insn (insn2) != PFREE_CANDIDATE) |
63de6c74 | 2463 | /* insn2 not guaranteed to be a 1 base reg load. */ |
8c660648 JL |
2464 | continue; |
2465 | ||
2466 | if (INSN_BB (insn2) == bb_trg) | |
63de6c74 | 2467 | /* insn2 is the similar load, in the target block. */ |
8c660648 JL |
2468 | return 1; |
2469 | ||
2470 | if (*(candp->split_bbs.first_member) == INSN_BLOCK (insn2)) | |
63de6c74 | 2471 | /* insn2 is a similar load, in a split-block. */ |
8c660648 JL |
2472 | return 1; |
2473 | } | |
2474 | } | |
2475 | } | |
2476 | } | |
2477 | ||
63de6c74 | 2478 | /* Couldn't find a similar load. */ |
8c660648 JL |
2479 | return 0; |
2480 | } /* is_pfree */ | |
2481 | ||
2482 | /* Returns a class that insn with GET_DEST(insn)=x may belong to, | |
2483 | as found by analyzing insn's expression. */ | |
2484 | ||
2485 | static int | |
2486 | may_trap_exp (x, is_store) | |
2487 | rtx x; | |
2488 | int is_store; | |
2489 | { | |
2490 | enum rtx_code code; | |
2491 | ||
2492 | if (x == 0) | |
2493 | return TRAP_FREE; | |
2494 | code = GET_CODE (x); | |
2495 | if (is_store) | |
2496 | { | |
2497 | if (code == MEM) | |
2498 | return TRAP_RISKY; | |
2499 | else | |
2500 | return TRAP_FREE; | |
2501 | } | |
2502 | if (code == MEM) | |
2503 | { | |
63de6c74 | 2504 | /* The insn uses memory: a volatile load. */ |
8c660648 JL |
2505 | if (MEM_VOLATILE_P (x)) |
2506 | return IRISKY; | |
63de6c74 | 2507 | /* An exception-free load. */ |
8c660648 JL |
2508 | if (!may_trap_p (x)) |
2509 | return IFREE; | |
63de6c74 | 2510 | /* A load with 1 base register, to be further checked. */ |
8c660648 JL |
2511 | if (CONST_BASED_ADDRESS_P (XEXP (x, 0))) |
2512 | return PFREE_CANDIDATE; | |
63de6c74 | 2513 | /* No info on the load, to be further checked. */ |
8c660648 JL |
2514 | return PRISKY_CANDIDATE; |
2515 | } | |
2516 | else | |
2517 | { | |
6f7d635c | 2518 | const char *fmt; |
8c660648 JL |
2519 | int i, insn_class = TRAP_FREE; |
2520 | ||
63de6c74 | 2521 | /* Neither store nor load, check if it may cause a trap. */ |
8c660648 JL |
2522 | if (may_trap_p (x)) |
2523 | return TRAP_RISKY; | |
63de6c74 | 2524 | /* Recursive step: walk the insn... */ |
8c660648 JL |
2525 | fmt = GET_RTX_FORMAT (code); |
2526 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2527 | { | |
2528 | if (fmt[i] == 'e') | |
2529 | { | |
2530 | int tmp_class = may_trap_exp (XEXP (x, i), is_store); | |
2531 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2532 | } | |
2533 | else if (fmt[i] == 'E') | |
2534 | { | |
2535 | int j; | |
2536 | for (j = 0; j < XVECLEN (x, i); j++) | |
2537 | { | |
2538 | int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store); | |
2539 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2540 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2541 | break; | |
2542 | } | |
2543 | } | |
2544 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2545 | break; | |
2546 | } | |
2547 | return insn_class; | |
2548 | } | |
2549 | } /* may_trap_exp */ | |
2550 | ||
2551 | ||
2552 | /* Classifies insn for the purpose of verifying that it can be | |
2553 | moved speculatively, by examining it's patterns, returning: | |
2554 | TRAP_RISKY: store, or risky non-load insn (e.g. division by variable). | |
2555 | TRAP_FREE: non-load insn. | |
2556 | IFREE: load from a globaly safe location. | |
2557 | IRISKY: volatile load. | |
2558 | PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for | |
2559 | being either PFREE or PRISKY. */ | |
2560 | ||
2561 | static int | |
ac957f13 | 2562 | haifa_classify_insn (insn) |
8c660648 JL |
2563 | rtx insn; |
2564 | { | |
2565 | rtx pat = PATTERN (insn); | |
2566 | int tmp_class = TRAP_FREE; | |
2567 | int insn_class = TRAP_FREE; | |
2568 | enum rtx_code code; | |
2569 | ||
2570 | if (GET_CODE (pat) == PARALLEL) | |
2571 | { | |
2572 | int i, len = XVECLEN (pat, 0); | |
2573 | ||
2574 | for (i = len - 1; i >= 0; i--) | |
2575 | { | |
2576 | code = GET_CODE (XVECEXP (pat, 0, i)); | |
2577 | switch (code) | |
2578 | { | |
2579 | case CLOBBER: | |
63de6c74 | 2580 | /* Test if it is a 'store'. */ |
8c660648 JL |
2581 | tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1); |
2582 | break; | |
2583 | case SET: | |
63de6c74 | 2584 | /* Test if it is a store. */ |
8c660648 JL |
2585 | tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1); |
2586 | if (tmp_class == TRAP_RISKY) | |
2587 | break; | |
63de6c74 | 2588 | /* Test if it is a load. */ |
8c660648 JL |
2589 | tmp_class = |
2590 | WORST_CLASS (tmp_class, | |
2591 | may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0)); | |
e0cd0770 JC |
2592 | break; |
2593 | case TRAP_IF: | |
2594 | tmp_class = TRAP_RISKY; | |
2595 | break; | |
8c660648 JL |
2596 | default:; |
2597 | } | |
2598 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2599 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2600 | break; | |
2601 | } | |
2602 | } | |
2603 | else | |
2604 | { | |
2605 | code = GET_CODE (pat); | |
2606 | switch (code) | |
2607 | { | |
2608 | case CLOBBER: | |
63de6c74 | 2609 | /* Test if it is a 'store'. */ |
8c660648 JL |
2610 | tmp_class = may_trap_exp (XEXP (pat, 0), 1); |
2611 | break; | |
2612 | case SET: | |
63de6c74 | 2613 | /* Test if it is a store. */ |
8c660648 JL |
2614 | tmp_class = may_trap_exp (SET_DEST (pat), 1); |
2615 | if (tmp_class == TRAP_RISKY) | |
2616 | break; | |
63de6c74 | 2617 | /* Test if it is a load. */ |
8c660648 JL |
2618 | tmp_class = |
2619 | WORST_CLASS (tmp_class, | |
2620 | may_trap_exp (SET_SRC (pat), 0)); | |
e0cd0770 JC |
2621 | break; |
2622 | case TRAP_IF: | |
2623 | tmp_class = TRAP_RISKY; | |
2624 | break; | |
8c660648 JL |
2625 | default:; |
2626 | } | |
2627 | insn_class = tmp_class; | |
2628 | } | |
2629 | ||
2630 | return insn_class; | |
2631 | ||
ac957f13 | 2632 | } /* haifa_classify_insn */ |
8c660648 JL |
2633 | |
2634 | /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by | |
2635 | a load moved speculatively, or if load_insn is protected by | |
2636 | a compare on load_insn's address). */ | |
2637 | ||
2638 | static int | |
2639 | is_prisky (load_insn, bb_src, bb_trg) | |
2640 | rtx load_insn; | |
2641 | int bb_src, bb_trg; | |
2642 | { | |
2643 | if (FED_BY_SPEC_LOAD (load_insn)) | |
2644 | return 1; | |
2645 | ||
2646 | if (LOG_LINKS (load_insn) == NULL) | |
63de6c74 | 2647 | /* Dependence may 'hide' out of the region. */ |
8c660648 JL |
2648 | return 1; |
2649 | ||
2650 | if (is_conditionally_protected (load_insn, bb_src, bb_trg)) | |
2651 | return 1; | |
2652 | ||
2653 | return 0; | |
2654 | } /* is_prisky */ | |
2655 | ||
2656 | /* Insn is a candidate to be moved speculatively from bb_src to bb_trg. | |
2657 | Return 1 if insn is exception-free (and the motion is valid) | |
2658 | and 0 otherwise. */ | |
2659 | ||
2660 | static int | |
2661 | is_exception_free (insn, bb_src, bb_trg) | |
2662 | rtx insn; | |
2663 | int bb_src, bb_trg; | |
2664 | { | |
ac957f13 | 2665 | int insn_class = haifa_classify_insn (insn); |
8c660648 | 2666 | |
63de6c74 | 2667 | /* Handle non-load insns. */ |
8c660648 JL |
2668 | switch (insn_class) |
2669 | { | |
2670 | case TRAP_FREE: | |
2671 | return 1; | |
2672 | case TRAP_RISKY: | |
2673 | return 0; | |
2674 | default:; | |
2675 | } | |
2676 | ||
63de6c74 | 2677 | /* Handle loads. */ |
8c660648 JL |
2678 | if (!flag_schedule_speculative_load) |
2679 | return 0; | |
2680 | IS_LOAD_INSN (insn) = 1; | |
2681 | switch (insn_class) | |
2682 | { | |
2683 | case IFREE: | |
2684 | return (1); | |
2685 | case IRISKY: | |
2686 | return 0; | |
2687 | case PFREE_CANDIDATE: | |
2688 | if (is_pfree (insn, bb_src, bb_trg)) | |
2689 | return 1; | |
63de6c74 | 2690 | /* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */ |
8c660648 JL |
2691 | case PRISKY_CANDIDATE: |
2692 | if (!flag_schedule_speculative_load_dangerous | |
2693 | || is_prisky (insn, bb_src, bb_trg)) | |
2694 | return 0; | |
2695 | break; | |
2696 | default:; | |
2697 | } | |
2698 | ||
2699 | return flag_schedule_speculative_load_dangerous; | |
2700 | } /* is_exception_free */ | |
2701 | ||
2702 | ||
2703 | /* Process an insn's memory dependencies. There are four kinds of | |
2704 | dependencies: | |
2705 | ||
2706 | (0) read dependence: read follows read | |
2707 | (1) true dependence: read follows write | |
2708 | (2) anti dependence: write follows read | |
2709 | (3) output dependence: write follows write | |
2710 | ||
2711 | We are careful to build only dependencies which actually exist, and | |
2712 | use transitivity to avoid building too many links. */ | |
2713 | \f | |
2714 | /* Return the INSN_LIST containing INSN in LIST, or NULL | |
2715 | if LIST does not contain INSN. */ | |
2716 | ||
cbb13457 | 2717 | HAIFA_INLINE static rtx |
8c660648 JL |
2718 | find_insn_list (insn, list) |
2719 | rtx insn; | |
2720 | rtx list; | |
2721 | { | |
2722 | while (list) | |
2723 | { | |
2724 | if (XEXP (list, 0) == insn) | |
2725 | return list; | |
2726 | list = XEXP (list, 1); | |
2727 | } | |
2728 | return 0; | |
2729 | } | |
2730 | ||
2731 | ||
63de6c74 MH |
2732 | /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 |
2733 | otherwise. */ | |
8c660648 | 2734 | |
cbb13457 | 2735 | HAIFA_INLINE static char |
8c660648 JL |
2736 | find_insn_mem_list (insn, x, list, list1) |
2737 | rtx insn, x; | |
2738 | rtx list, list1; | |
2739 | { | |
2740 | while (list) | |
2741 | { | |
2742 | if (XEXP (list, 0) == insn | |
2743 | && XEXP (list1, 0) == x) | |
2744 | return 1; | |
2745 | list = XEXP (list, 1); | |
2746 | list1 = XEXP (list1, 1); | |
2747 | } | |
2748 | return 0; | |
2749 | } | |
2750 | ||
2751 | ||
2752 | /* Compute the function units used by INSN. This caches the value | |
2753 | returned by function_units_used. A function unit is encoded as the | |
2754 | unit number if the value is non-negative and the compliment of a | |
2755 | mask if the value is negative. A function unit index is the | |
2756 | non-negative encoding. */ | |
2757 | ||
cbb13457 | 2758 | HAIFA_INLINE static int |
8c660648 JL |
2759 | insn_unit (insn) |
2760 | rtx insn; | |
2761 | { | |
2762 | register int unit = INSN_UNIT (insn); | |
2763 | ||
2764 | if (unit == 0) | |
2765 | { | |
2766 | recog_memoized (insn); | |
2767 | ||
2768 | /* A USE insn, or something else we don't need to understand. | |
2769 | We can't pass these directly to function_units_used because it will | |
2770 | trigger a fatal error for unrecognizable insns. */ | |
2771 | if (INSN_CODE (insn) < 0) | |
2772 | unit = -1; | |
2773 | else | |
2774 | { | |
2775 | unit = function_units_used (insn); | |
2776 | /* Increment non-negative values so we can cache zero. */ | |
2777 | if (unit >= 0) | |
2778 | unit++; | |
2779 | } | |
2780 | /* We only cache 16 bits of the result, so if the value is out of | |
2781 | range, don't cache it. */ | |
2782 | if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT | |
2783 | || unit >= 0 | |
77f3d48a | 2784 | || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0) |
8c660648 JL |
2785 | INSN_UNIT (insn) = unit; |
2786 | } | |
2787 | return (unit > 0 ? unit - 1 : unit); | |
2788 | } | |
2789 | ||
2790 | /* Compute the blockage range for executing INSN on UNIT. This caches | |
2791 | the value returned by the blockage_range_function for the unit. | |
2792 | These values are encoded in an int where the upper half gives the | |
2793 | minimum value and the lower half gives the maximum value. */ | |
2794 | ||
cbb13457 | 2795 | HAIFA_INLINE static unsigned int |
8c660648 JL |
2796 | blockage_range (unit, insn) |
2797 | int unit; | |
2798 | rtx insn; | |
2799 | { | |
2800 | unsigned int blockage = INSN_BLOCKAGE (insn); | |
2801 | unsigned int range; | |
2802 | ||
79c9824e | 2803 | if ((int) UNIT_BLOCKED (blockage) != unit + 1) |
8c660648 JL |
2804 | { |
2805 | range = function_units[unit].blockage_range_function (insn); | |
2806 | /* We only cache the blockage range for one unit and then only if | |
2807 | the values fit. */ | |
2808 | if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS) | |
2809 | INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range); | |
2810 | } | |
2811 | else | |
2812 | range = BLOCKAGE_RANGE (blockage); | |
2813 | ||
2814 | return range; | |
2815 | } | |
2816 | ||
2817 | /* A vector indexed by function unit instance giving the last insn to use | |
2818 | the unit. The value of the function unit instance index for unit U | |
2819 | instance I is (U + I * FUNCTION_UNITS_SIZE). */ | |
2820 | static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2821 | ||
2822 | /* A vector indexed by function unit instance giving the minimum time when | |
2823 | the unit will unblock based on the maximum blockage cost. */ | |
2824 | static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2825 | ||
2826 | /* A vector indexed by function unit number giving the number of insns | |
2827 | that remain to use the unit. */ | |
2828 | static int unit_n_insns[FUNCTION_UNITS_SIZE]; | |
2829 | ||
2830 | /* Reset the function unit state to the null state. */ | |
2831 | ||
2832 | static void | |
2833 | clear_units () | |
2834 | { | |
2835 | bzero ((char *) unit_last_insn, sizeof (unit_last_insn)); | |
2836 | bzero ((char *) unit_tick, sizeof (unit_tick)); | |
2837 | bzero ((char *) unit_n_insns, sizeof (unit_n_insns)); | |
2838 | } | |
2839 | ||
63de6c74 | 2840 | /* Return the issue-delay of an insn. */ |
8c660648 | 2841 | |
cbb13457 | 2842 | HAIFA_INLINE static int |
8c660648 JL |
2843 | insn_issue_delay (insn) |
2844 | rtx insn; | |
2845 | { | |
8c660648 JL |
2846 | int i, delay = 0; |
2847 | int unit = insn_unit (insn); | |
2848 | ||
63de6c74 | 2849 | /* Efficiency note: in fact, we are working 'hard' to compute a |
8c660648 JL |
2850 | value that was available in md file, and is not available in |
2851 | function_units[] structure. It would be nice to have this | |
2852 | value there, too. */ | |
2853 | if (unit >= 0) | |
2854 | { | |
2855 | if (function_units[unit].blockage_range_function && | |
2856 | function_units[unit].blockage_function) | |
2857 | delay = function_units[unit].blockage_function (insn, insn); | |
2858 | } | |
2859 | else | |
2860 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2861 | if ((unit & 1) != 0 && function_units[i].blockage_range_function | |
2862 | && function_units[i].blockage_function) | |
2863 | delay = MAX (delay, function_units[i].blockage_function (insn, insn)); | |
2864 | ||
2865 | return delay; | |
2866 | } | |
2867 | ||
2868 | /* Return the actual hazard cost of executing INSN on the unit UNIT, | |
2869 | instance INSTANCE at time CLOCK if the previous actual hazard cost | |
2870 | was COST. */ | |
2871 | ||
cbb13457 | 2872 | HAIFA_INLINE static int |
8c660648 JL |
2873 | actual_hazard_this_instance (unit, instance, insn, clock, cost) |
2874 | int unit, instance, clock, cost; | |
2875 | rtx insn; | |
2876 | { | |
63de6c74 | 2877 | int tick = unit_tick[instance]; /* Issue time of the last issued insn. */ |
8c660648 JL |
2878 | |
2879 | if (tick - clock > cost) | |
2880 | { | |
2881 | /* The scheduler is operating forward, so unit's last insn is the | |
2882 | executing insn and INSN is the candidate insn. We want a | |
2883 | more exact measure of the blockage if we execute INSN at CLOCK | |
2884 | given when we committed the execution of the unit's last insn. | |
2885 | ||
2886 | The blockage value is given by either the unit's max blockage | |
2887 | constant, blockage range function, or blockage function. Use | |
2888 | the most exact form for the given unit. */ | |
2889 | ||
2890 | if (function_units[unit].blockage_range_function) | |
2891 | { | |
2892 | if (function_units[unit].blockage_function) | |
2893 | tick += (function_units[unit].blockage_function | |
2894 | (unit_last_insn[instance], insn) | |
2895 | - function_units[unit].max_blockage); | |
2896 | else | |
2897 | tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn)) | |
2898 | - function_units[unit].max_blockage); | |
2899 | } | |
2900 | if (tick - clock > cost) | |
2901 | cost = tick - clock; | |
2902 | } | |
2903 | return cost; | |
2904 | } | |
2905 | ||
2906 | /* Record INSN as having begun execution on the units encoded by UNIT at | |
2907 | time CLOCK. */ | |
2908 | ||
cbb13457 | 2909 | HAIFA_INLINE static void |
8c660648 JL |
2910 | schedule_unit (unit, insn, clock) |
2911 | int unit, clock; | |
2912 | rtx insn; | |
2913 | { | |
2914 | int i; | |
2915 | ||
2916 | if (unit >= 0) | |
2917 | { | |
2918 | int instance = unit; | |
2919 | #if MAX_MULTIPLICITY > 1 | |
2920 | /* Find the first free instance of the function unit and use that | |
2921 | one. We assume that one is free. */ | |
2922 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2923 | { | |
2924 | if (!actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
2925 | break; | |
2926 | instance += FUNCTION_UNITS_SIZE; | |
2927 | } | |
2928 | #endif | |
2929 | unit_last_insn[instance] = insn; | |
2930 | unit_tick[instance] = (clock + function_units[unit].max_blockage); | |
2931 | } | |
2932 | else | |
2933 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2934 | if ((unit & 1) != 0) | |
2935 | schedule_unit (i, insn, clock); | |
2936 | } | |
2937 | ||
2938 | /* Return the actual hazard cost of executing INSN on the units encoded by | |
2939 | UNIT at time CLOCK if the previous actual hazard cost was COST. */ | |
2940 | ||
cbb13457 | 2941 | HAIFA_INLINE static int |
8c660648 JL |
2942 | actual_hazard (unit, insn, clock, cost) |
2943 | int unit, clock, cost; | |
2944 | rtx insn; | |
2945 | { | |
2946 | int i; | |
2947 | ||
2948 | if (unit >= 0) | |
2949 | { | |
2950 | /* Find the instance of the function unit with the minimum hazard. */ | |
2951 | int instance = unit; | |
2952 | int best_cost = actual_hazard_this_instance (unit, instance, insn, | |
2953 | clock, cost); | |
1eda7a81 | 2954 | #if MAX_MULTIPLICITY > 1 |
8c660648 JL |
2955 | int this_cost; |
2956 | ||
8c660648 JL |
2957 | if (best_cost > cost) |
2958 | { | |
2959 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2960 | { | |
2961 | instance += FUNCTION_UNITS_SIZE; | |
2962 | this_cost = actual_hazard_this_instance (unit, instance, insn, | |
2963 | clock, cost); | |
2964 | if (this_cost < best_cost) | |
2965 | { | |
2966 | best_cost = this_cost; | |
2967 | if (this_cost <= cost) | |
2968 | break; | |
2969 | } | |
2970 | } | |
2971 | } | |
2972 | #endif | |
2973 | cost = MAX (cost, best_cost); | |
2974 | } | |
2975 | else | |
2976 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2977 | if ((unit & 1) != 0) | |
2978 | cost = actual_hazard (i, insn, clock, cost); | |
2979 | ||
2980 | return cost; | |
2981 | } | |
2982 | ||
2983 | /* Return the potential hazard cost of executing an instruction on the | |
2984 | units encoded by UNIT if the previous potential hazard cost was COST. | |
2985 | An insn with a large blockage time is chosen in preference to one | |
2986 | with a smaller time; an insn that uses a unit that is more likely | |
2987 | to be used is chosen in preference to one with a unit that is less | |
2988 | used. We are trying to minimize a subsequent actual hazard. */ | |
2989 | ||
cbb13457 | 2990 | HAIFA_INLINE static int |
8c660648 JL |
2991 | potential_hazard (unit, insn, cost) |
2992 | int unit, cost; | |
2993 | rtx insn; | |
2994 | { | |
2995 | int i, ncost; | |
2996 | unsigned int minb, maxb; | |
2997 | ||
2998 | if (unit >= 0) | |
2999 | { | |
3000 | minb = maxb = function_units[unit].max_blockage; | |
3001 | if (maxb > 1) | |
3002 | { | |
3003 | if (function_units[unit].blockage_range_function) | |
3004 | { | |
3005 | maxb = minb = blockage_range (unit, insn); | |
3006 | maxb = MAX_BLOCKAGE_COST (maxb); | |
3007 | minb = MIN_BLOCKAGE_COST (minb); | |
3008 | } | |
3009 | ||
3010 | if (maxb > 1) | |
3011 | { | |
3012 | /* Make the number of instructions left dominate. Make the | |
3013 | minimum delay dominate the maximum delay. If all these | |
3014 | are the same, use the unit number to add an arbitrary | |
3015 | ordering. Other terms can be added. */ | |
3016 | ncost = minb * 0x40 + maxb; | |
3017 | ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit; | |
3018 | if (ncost > cost) | |
3019 | cost = ncost; | |
3020 | } | |
3021 | } | |
3022 | } | |
3023 | else | |
3024 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3025 | if ((unit & 1) != 0) | |
3026 | cost = potential_hazard (i, insn, cost); | |
3027 | ||
3028 | return cost; | |
3029 | } | |
3030 | ||
3031 | /* Compute cost of executing INSN given the dependence LINK on the insn USED. | |
3032 | This is the number of cycles between instruction issue and | |
3033 | instruction results. */ | |
3034 | ||
cbb13457 | 3035 | HAIFA_INLINE static int |
8c660648 JL |
3036 | insn_cost (insn, link, used) |
3037 | rtx insn, link, used; | |
3038 | { | |
3039 | register int cost = INSN_COST (insn); | |
3040 | ||
3041 | if (cost == 0) | |
3042 | { | |
3043 | recog_memoized (insn); | |
3044 | ||
3045 | /* A USE insn, or something else we don't need to understand. | |
3046 | We can't pass these directly to result_ready_cost because it will | |
3047 | trigger a fatal error for unrecognizable insns. */ | |
3048 | if (INSN_CODE (insn) < 0) | |
3049 | { | |
3050 | INSN_COST (insn) = 1; | |
3051 | return 1; | |
3052 | } | |
3053 | else | |
3054 | { | |
3055 | cost = result_ready_cost (insn); | |
3056 | ||
3057 | if (cost < 1) | |
3058 | cost = 1; | |
3059 | ||
3060 | INSN_COST (insn) = cost; | |
3061 | } | |
3062 | } | |
3063 | ||
63de6c74 | 3064 | /* In this case estimate cost without caring how insn is used. */ |
8c660648 JL |
3065 | if (link == 0 && used == 0) |
3066 | return cost; | |
3067 | ||
3068 | /* A USE insn should never require the value used to be computed. This | |
3069 | allows the computation of a function's result and parameter values to | |
3070 | overlap the return and call. */ | |
3071 | recog_memoized (used); | |
3072 | if (INSN_CODE (used) < 0) | |
3073 | LINK_COST_FREE (link) = 1; | |
3074 | ||
3075 | /* If some dependencies vary the cost, compute the adjustment. Most | |
3076 | commonly, the adjustment is complete: either the cost is ignored | |
3077 | (in the case of an output- or anti-dependence), or the cost is | |
3078 | unchanged. These values are cached in the link as LINK_COST_FREE | |
3079 | and LINK_COST_ZERO. */ | |
3080 | ||
3081 | if (LINK_COST_FREE (link)) | |
197043f5 | 3082 | cost = 0; |
8c660648 JL |
3083 | #ifdef ADJUST_COST |
3084 | else if (!LINK_COST_ZERO (link)) | |
3085 | { | |
3086 | int ncost = cost; | |
3087 | ||
3088 | ADJUST_COST (used, link, insn, ncost); | |
197043f5 RH |
3089 | if (ncost < 1) |
3090 | { | |
3091 | LINK_COST_FREE (link) = 1; | |
3092 | ncost = 0; | |
3093 | } | |
8c660648 JL |
3094 | if (cost == ncost) |
3095 | LINK_COST_ZERO (link) = 1; | |
3096 | cost = ncost; | |
3097 | } | |
3098 | #endif | |
3099 | return cost; | |
3100 | } | |
3101 | ||
3102 | /* Compute the priority number for INSN. */ | |
3103 | ||
3104 | static int | |
3105 | priority (insn) | |
3106 | rtx insn; | |
3107 | { | |
3108 | int this_priority; | |
3109 | rtx link; | |
3110 | ||
3111 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
3112 | return 0; | |
3113 | ||
3114 | if ((this_priority = INSN_PRIORITY (insn)) == 0) | |
3115 | { | |
3116 | if (INSN_DEPEND (insn) == 0) | |
3117 | this_priority = insn_cost (insn, 0, 0); | |
3118 | else | |
3119 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
3120 | { | |
3121 | rtx next; | |
3122 | int next_priority; | |
3123 | ||
6d8ccdbb JL |
3124 | if (RTX_INTEGRATED_P (link)) |
3125 | continue; | |
3126 | ||
8c660648 JL |
3127 | next = XEXP (link, 0); |
3128 | ||
63de6c74 | 3129 | /* Critical path is meaningful in block boundaries only. */ |
8c660648 JL |
3130 | if (INSN_BLOCK (next) != INSN_BLOCK (insn)) |
3131 | continue; | |
3132 | ||
3133 | next_priority = insn_cost (insn, link, next) + priority (next); | |
3134 | if (next_priority > this_priority) | |
3135 | this_priority = next_priority; | |
3136 | } | |
3137 | INSN_PRIORITY (insn) = this_priority; | |
3138 | } | |
3139 | return this_priority; | |
3140 | } | |
3141 | \f | |
3142 | ||
3143 | /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add | |
3144 | them to the unused_*_list variables, so that they can be reused. */ | |
3145 | ||
8c660648 JL |
3146 | static void |
3147 | free_pending_lists () | |
3148 | { | |
8c660648 JL |
3149 | if (current_nr_blocks <= 1) |
3150 | { | |
5a4f6418 AM |
3151 | free_INSN_LIST_list (&pending_read_insns); |
3152 | free_INSN_LIST_list (&pending_write_insns); | |
3153 | free_EXPR_LIST_list (&pending_read_mems); | |
3154 | free_EXPR_LIST_list (&pending_write_mems); | |
8c660648 JL |
3155 | } |
3156 | else | |
3157 | { | |
63de6c74 | 3158 | /* Interblock scheduling. */ |
8c660648 JL |
3159 | int bb; |
3160 | ||
3161 | for (bb = 0; bb < current_nr_blocks; bb++) | |
3162 | { | |
5a4f6418 AM |
3163 | free_INSN_LIST_list (&bb_pending_read_insns[bb]); |
3164 | free_INSN_LIST_list (&bb_pending_write_insns[bb]); | |
3165 | free_EXPR_LIST_list (&bb_pending_read_mems[bb]); | |
3166 | free_EXPR_LIST_list (&bb_pending_write_mems[bb]); | |
8c660648 JL |
3167 | } |
3168 | } | |
3169 | } | |
3170 | ||
3171 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
3172 | The MEM is a memory reference contained within INSN, which we are saving | |
3173 | so that we can do memory aliasing on it. */ | |
3174 | ||
3175 | static void | |
3176 | add_insn_mem_dependence (insn_list, mem_list, insn, mem) | |
3177 | rtx *insn_list, *mem_list, insn, mem; | |
3178 | { | |
3179 | register rtx link; | |
3180 | ||
ebb7b10b | 3181 | link = alloc_INSN_LIST (insn, *insn_list); |
8c660648 JL |
3182 | *insn_list = link; |
3183 | ||
ebb7b10b | 3184 | link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list); |
8c660648 JL |
3185 | *mem_list = link; |
3186 | ||
3187 | pending_lists_length++; | |
3188 | } | |
3189 | \f | |
3190 | ||
3191 | /* Make a dependency between every memory reference on the pending lists | |
3192 | and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush | |
3193 | the read list. */ | |
3194 | ||
3195 | static void | |
3196 | flush_pending_lists (insn, only_write) | |
3197 | rtx insn; | |
3198 | int only_write; | |
3199 | { | |
3200 | rtx u; | |
3201 | rtx link; | |
3202 | ||
3203 | while (pending_read_insns && ! only_write) | |
3204 | { | |
3205 | add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI); | |
3206 | ||
3207 | link = pending_read_insns; | |
3208 | pending_read_insns = XEXP (pending_read_insns, 1); | |
5a4f6418 | 3209 | free_INSN_LIST_node (link); |
8c660648 JL |
3210 | |
3211 | link = pending_read_mems; | |
3212 | pending_read_mems = XEXP (pending_read_mems, 1); | |
5a4f6418 | 3213 | free_EXPR_LIST_node (link); |
8c660648 JL |
3214 | } |
3215 | while (pending_write_insns) | |
3216 | { | |
3217 | add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI); | |
3218 | ||
3219 | link = pending_write_insns; | |
3220 | pending_write_insns = XEXP (pending_write_insns, 1); | |
5a4f6418 | 3221 | free_INSN_LIST_node (link); |
8c660648 JL |
3222 | |
3223 | link = pending_write_mems; | |
3224 | pending_write_mems = XEXP (pending_write_mems, 1); | |
5a4f6418 | 3225 | free_EXPR_LIST_node (link); |
8c660648 JL |
3226 | } |
3227 | pending_lists_length = 0; | |
3228 | ||
63de6c74 | 3229 | /* last_pending_memory_flush is now a list of insns. */ |
8c660648 JL |
3230 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
3231 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3232 | ||
5a4f6418 | 3233 | free_INSN_LIST_list (&last_pending_memory_flush); |
ebb7b10b | 3234 | last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3235 | } |
3236 | ||
355fca3e AB |
3237 | /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC |
3238 | rtx, X, creating all dependencies generated by the write to the | |
3239 | destination of X, and reads of everything mentioned. */ | |
8c660648 JL |
3240 | |
3241 | static void | |
3242 | sched_analyze_1 (x, insn) | |
3243 | rtx x; | |
3244 | rtx insn; | |
3245 | { | |
3246 | register int regno; | |
355fca3e | 3247 | register rtx dest = XEXP (x, 0); |
28c95eff | 3248 | enum rtx_code code = GET_CODE (x); |
8c660648 JL |
3249 | |
3250 | if (dest == 0) | |
3251 | return; | |
3252 | ||
c0222c21 DM |
3253 | if (GET_CODE (dest) == PARALLEL |
3254 | && GET_MODE (dest) == BLKmode) | |
3255 | { | |
3256 | register int i; | |
3257 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
3258 | sched_analyze_1 (XVECEXP (dest, 0, i), insn); | |
3259 | if (GET_CODE (x) == SET) | |
3260 | sched_analyze_2 (SET_SRC (x), insn); | |
3261 | return; | |
3262 | } | |
3263 | ||
8c660648 JL |
3264 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG |
3265 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3266 | { | |
3267 | if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3268 | { | |
3269 | /* The second and third arguments are values read by this insn. */ | |
3270 | sched_analyze_2 (XEXP (dest, 1), insn); | |
3271 | sched_analyze_2 (XEXP (dest, 2), insn); | |
3272 | } | |
355fca3e | 3273 | dest = XEXP (dest, 0); |
8c660648 JL |
3274 | } |
3275 | ||
3276 | if (GET_CODE (dest) == REG) | |
3277 | { | |
3278 | register int i; | |
3279 | ||
3280 | regno = REGNO (dest); | |
3281 | ||
3282 | /* A hard reg in a wide mode may really be multiple registers. | |
3283 | If so, mark all of them just like the first. */ | |
3284 | if (regno < FIRST_PSEUDO_REGISTER) | |
3285 | { | |
3286 | i = HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
3287 | while (--i >= 0) | |
3288 | { | |
3289 | rtx u; | |
3290 | ||
3291 | for (u = reg_last_uses[regno + i]; u; u = XEXP (u, 1)) | |
3292 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3293 | |
3294 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3295 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3296 | ||
63de6c74 MH |
3297 | /* Clobbers need not be ordered with respect to one |
3298 | another, but sets must be ordered with respect to a | |
3299 | pending clobber. */ | |
28c95eff RH |
3300 | if (code == SET) |
3301 | { | |
5a4f6418 | 3302 | free_INSN_LIST_list (®_last_uses[regno + i]); |
28c95eff RH |
3303 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) |
3304 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3305 | SET_REGNO_REG_SET (reg_pending_sets, regno + i); | |
3306 | } | |
3307 | else | |
3308 | SET_REGNO_REG_SET (reg_pending_clobbers, regno + i); | |
8c660648 | 3309 | |
28c95eff RH |
3310 | /* Function calls clobber all call_used regs. */ |
3311 | if (global_regs[regno + i] | |
3312 | || (code == SET && call_used_regs[regno + i])) | |
8c660648 JL |
3313 | for (u = last_function_call; u; u = XEXP (u, 1)) |
3314 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3315 | } | |
3316 | } | |
3317 | else | |
3318 | { | |
3319 | rtx u; | |
3320 | ||
3321 | for (u = reg_last_uses[regno]; u; u = XEXP (u, 1)) | |
3322 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3323 | |
3324 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3325 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3326 | ||
28c95eff | 3327 | if (code == SET) |
7399257b | 3328 | { |
5a4f6418 | 3329 | free_INSN_LIST_list (®_last_uses[regno]); |
7399257b RH |
3330 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) |
3331 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3332 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
3333 | } | |
28c95eff RH |
3334 | else |
3335 | SET_REGNO_REG_SET (reg_pending_clobbers, regno); | |
8c660648 JL |
3336 | |
3337 | /* Pseudos that are REG_EQUIV to something may be replaced | |
3338 | by that during reloading. We need only add dependencies for | |
3339 | the address in the REG_EQUIV note. */ | |
3340 | if (!reload_completed | |
3341 | && reg_known_equiv_p[regno] | |
3342 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3343 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3344 | ||
3345 | /* Don't let it cross a call after scheduling if it doesn't | |
3346 | already cross one. */ | |
3347 | ||
3348 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3349 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3350 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3351 | } | |
3352 | } | |
3353 | else if (GET_CODE (dest) == MEM) | |
3354 | { | |
3355 | /* Writing memory. */ | |
3356 | ||
3357 | if (pending_lists_length > 32) | |
3358 | { | |
3359 | /* Flush all pending reads and writes to prevent the pending lists | |
3360 | from getting any larger. Insn scheduling runs too slowly when | |
3361 | these lists get long. The number 32 was chosen because it | |
3362 | seems like a reasonable number. When compiling GCC with itself, | |
3363 | this flush occurs 8 times for sparc, and 10 times for m88k using | |
3364 | the number 32. */ | |
3365 | flush_pending_lists (insn, 0); | |
3366 | } | |
3367 | else | |
3368 | { | |
3369 | rtx u; | |
3370 | rtx pending, pending_mem; | |
3371 | ||
3372 | pending = pending_read_insns; | |
3373 | pending_mem = pending_read_mems; | |
3374 | while (pending) | |
3375 | { | |
87373fba RH |
3376 | if (anti_dependence (XEXP (pending_mem, 0), dest)) |
3377 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3378 | |
3379 | pending = XEXP (pending, 1); | |
3380 | pending_mem = XEXP (pending_mem, 1); | |
3381 | } | |
3382 | ||
3383 | pending = pending_write_insns; | |
3384 | pending_mem = pending_write_mems; | |
3385 | while (pending) | |
3386 | { | |
87373fba RH |
3387 | if (output_dependence (XEXP (pending_mem, 0), dest)) |
3388 | add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT); | |
8c660648 JL |
3389 | |
3390 | pending = XEXP (pending, 1); | |
3391 | pending_mem = XEXP (pending_mem, 1); | |
3392 | } | |
3393 | ||
3394 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3395 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3396 | ||
3397 | add_insn_mem_dependence (&pending_write_insns, &pending_write_mems, | |
3398 | insn, dest); | |
3399 | } | |
3400 | sched_analyze_2 (XEXP (dest, 0), insn); | |
3401 | } | |
3402 | ||
3403 | /* Analyze reads. */ | |
3404 | if (GET_CODE (x) == SET) | |
3405 | sched_analyze_2 (SET_SRC (x), insn); | |
3406 | } | |
3407 | ||
3408 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
3409 | ||
3410 | static void | |
3411 | sched_analyze_2 (x, insn) | |
3412 | rtx x; | |
3413 | rtx insn; | |
3414 | { | |
3415 | register int i; | |
3416 | register int j; | |
3417 | register enum rtx_code code; | |
6f7d635c | 3418 | register const char *fmt; |
8c660648 JL |
3419 | |
3420 | if (x == 0) | |
3421 | return; | |
3422 | ||
3423 | code = GET_CODE (x); | |
3424 | ||
3425 | switch (code) | |
3426 | { | |
3427 | case CONST_INT: | |
3428 | case CONST_DOUBLE: | |
3429 | case SYMBOL_REF: | |
3430 | case CONST: | |
3431 | case LABEL_REF: | |
3432 | /* Ignore constants. Note that we must handle CONST_DOUBLE here | |
3433 | because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but | |
3434 | this does not mean that this insn is using cc0. */ | |
3435 | return; | |
3436 | ||
3437 | #ifdef HAVE_cc0 | |
3438 | case CC0: | |
3439 | { | |
3440 | rtx link, prev; | |
3441 | ||
3442 | /* User of CC0 depends on immediately preceding insn. */ | |
3443 | SCHED_GROUP_P (insn) = 1; | |
3444 | ||
3445 | /* There may be a note before this insn now, but all notes will | |
3446 | be removed before we actually try to schedule the insns, so | |
3447 | it won't cause a problem later. We must avoid it here though. */ | |
3448 | prev = prev_nonnote_insn (insn); | |
3449 | ||
3450 | /* Make a copy of all dependencies on the immediately previous insn, | |
3451 | and add to this insn. This is so that all the dependencies will | |
3452 | apply to the group. Remove an explicit dependence on this insn | |
3453 | as SCHED_GROUP_P now represents it. */ | |
3454 | ||
3455 | if (find_insn_list (prev, LOG_LINKS (insn))) | |
3456 | remove_dependence (insn, prev); | |
3457 | ||
3458 | for (link = LOG_LINKS (prev); link; link = XEXP (link, 1)) | |
3459 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3460 | ||
3461 | return; | |
3462 | } | |
3463 | #endif | |
3464 | ||
3465 | case REG: | |
3466 | { | |
3467 | rtx u; | |
3468 | int regno = REGNO (x); | |
3469 | if (regno < FIRST_PSEUDO_REGISTER) | |
3470 | { | |
3471 | int i; | |
3472 | ||
3473 | i = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3474 | while (--i >= 0) | |
3475 | { | |
3476 | reg_last_uses[regno + i] | |
ebb7b10b | 3477 | = alloc_INSN_LIST (insn, reg_last_uses[regno + i]); |
8c660648 JL |
3478 | |
3479 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3480 | add_dependence (insn, XEXP (u, 0), 0); | |
3481 | ||
28c95eff RH |
3482 | /* ??? This should never happen. */ |
3483 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) | |
3484 | add_dependence (insn, XEXP (u, 0), 0); | |
3485 | ||
8c660648 JL |
3486 | if ((call_used_regs[regno + i] || global_regs[regno + i])) |
3487 | /* Function calls clobber all call_used regs. */ | |
3488 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3489 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3490 | } | |
3491 | } | |
3492 | else | |
3493 | { | |
63de6c74 MH |
3494 | reg_last_uses[regno] = alloc_INSN_LIST (insn, |
3495 | reg_last_uses[regno]); | |
8c660648 JL |
3496 | |
3497 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3498 | add_dependence (insn, XEXP (u, 0), 0); | |
3499 | ||
28c95eff RH |
3500 | /* ??? This should never happen. */ |
3501 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) | |
3502 | add_dependence (insn, XEXP (u, 0), 0); | |
3503 | ||
8c660648 JL |
3504 | /* Pseudos that are REG_EQUIV to something may be replaced |
3505 | by that during reloading. We need only add dependencies for | |
3506 | the address in the REG_EQUIV note. */ | |
3507 | if (!reload_completed | |
3508 | && reg_known_equiv_p[regno] | |
3509 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3510 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3511 | ||
3512 | /* If the register does not already cross any calls, then add this | |
3513 | insn to the sched_before_next_call list so that it will still | |
3514 | not cross calls after scheduling. */ | |
3515 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3516 | add_dependence (sched_before_next_call, insn, REG_DEP_ANTI); | |
3517 | } | |
3518 | return; | |
3519 | } | |
3520 | ||
3521 | case MEM: | |
3522 | { | |
3523 | /* Reading memory. */ | |
3524 | rtx u; | |
3525 | rtx pending, pending_mem; | |
3526 | ||
3527 | pending = pending_read_insns; | |
3528 | pending_mem = pending_read_mems; | |
3529 | while (pending) | |
3530 | { | |
87373fba RH |
3531 | if (read_dependence (XEXP (pending_mem, 0), x)) |
3532 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3533 | |
3534 | pending = XEXP (pending, 1); | |
3535 | pending_mem = XEXP (pending_mem, 1); | |
3536 | } | |
3537 | ||
3538 | pending = pending_write_insns; | |
3539 | pending_mem = pending_write_mems; | |
3540 | while (pending) | |
3541 | { | |
87373fba RH |
3542 | if (true_dependence (XEXP (pending_mem, 0), VOIDmode, |
3543 | x, rtx_varies_p)) | |
3544 | add_dependence (insn, XEXP (pending, 0), 0); | |
8c660648 JL |
3545 | |
3546 | pending = XEXP (pending, 1); | |
3547 | pending_mem = XEXP (pending_mem, 1); | |
3548 | } | |
3549 | ||
3550 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3551 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3552 | ||
3553 | /* Always add these dependencies to pending_reads, since | |
3554 | this insn may be followed by a write. */ | |
3555 | add_insn_mem_dependence (&pending_read_insns, &pending_read_mems, | |
3556 | insn, x); | |
3557 | ||
3558 | /* Take advantage of tail recursion here. */ | |
3559 | sched_analyze_2 (XEXP (x, 0), insn); | |
3560 | return; | |
3561 | } | |
3562 | ||
e0cd0770 JC |
3563 | /* Force pending stores to memory in case a trap handler needs them. */ |
3564 | case TRAP_IF: | |
3565 | flush_pending_lists (insn, 1); | |
3566 | break; | |
3567 | ||
8c660648 JL |
3568 | case ASM_OPERANDS: |
3569 | case ASM_INPUT: | |
3570 | case UNSPEC_VOLATILE: | |
8c660648 JL |
3571 | { |
3572 | rtx u; | |
3573 | ||
3574 | /* Traditional and volatile asm instructions must be considered to use | |
3575 | and clobber all hard registers, all pseudo-registers and all of | |
3576 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
3577 | ||
3578 | Consider for instance a volatile asm that changes the fpu rounding | |
3579 | mode. An insn should not be moved across this even if it only uses | |
3580 | pseudo-regs because it might give an incorrectly rounded result. */ | |
3581 | if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) | |
3582 | { | |
3583 | int max_reg = max_reg_num (); | |
3584 | for (i = 0; i < max_reg; i++) | |
3585 | { | |
3586 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3587 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3588 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3589 | |
8c660648 JL |
3590 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3591 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3592 | |
3593 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3594 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3595 | } |
3596 | reg_pending_sets_all = 1; | |
3597 | ||
3598 | flush_pending_lists (insn, 0); | |
3599 | } | |
3600 | ||
3601 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
3602 | We can not just fall through here since then we would be confused | |
3603 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
3604 | traditional asms unlike their normal usage. */ | |
3605 | ||
3606 | if (code == ASM_OPERANDS) | |
3607 | { | |
3608 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
3609 | sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn); | |
3610 | return; | |
3611 | } | |
3612 | break; | |
3613 | } | |
3614 | ||
3615 | case PRE_DEC: | |
3616 | case POST_DEC: | |
3617 | case PRE_INC: | |
3618 | case POST_INC: | |
3619 | /* These both read and modify the result. We must handle them as writes | |
3620 | to get proper dependencies for following instructions. We must handle | |
3621 | them as reads to get proper dependencies from this to previous | |
3622 | instructions. Thus we need to pass them to both sched_analyze_1 | |
3623 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
3624 | to get the proper antecedent for the read. */ | |
3625 | sched_analyze_2 (XEXP (x, 0), insn); | |
3626 | sched_analyze_1 (x, insn); | |
3627 | return; | |
5835e573 KG |
3628 | |
3629 | default: | |
3630 | break; | |
8c660648 JL |
3631 | } |
3632 | ||
3633 | /* Other cases: walk the insn. */ | |
3634 | fmt = GET_RTX_FORMAT (code); | |
3635 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3636 | { | |
3637 | if (fmt[i] == 'e') | |
3638 | sched_analyze_2 (XEXP (x, i), insn); | |
3639 | else if (fmt[i] == 'E') | |
3640 | for (j = 0; j < XVECLEN (x, i); j++) | |
3641 | sched_analyze_2 (XVECEXP (x, i, j), insn); | |
3642 | } | |
3643 | } | |
3644 | ||
3645 | /* Analyze an INSN with pattern X to find all dependencies. */ | |
3646 | ||
3647 | static void | |
3648 | sched_analyze_insn (x, insn, loop_notes) | |
3649 | rtx x, insn; | |
3650 | rtx loop_notes; | |
3651 | { | |
3652 | register RTX_CODE code = GET_CODE (x); | |
3653 | rtx link; | |
3654 | int maxreg = max_reg_num (); | |
3655 | int i; | |
3656 | ||
3657 | if (code == SET || code == CLOBBER) | |
3658 | sched_analyze_1 (x, insn); | |
3659 | else if (code == PARALLEL) | |
3660 | { | |
3661 | register int i; | |
3662 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
3663 | { | |
3664 | code = GET_CODE (XVECEXP (x, 0, i)); | |
3665 | if (code == SET || code == CLOBBER) | |
3666 | sched_analyze_1 (XVECEXP (x, 0, i), insn); | |
3667 | else | |
3668 | sched_analyze_2 (XVECEXP (x, 0, i), insn); | |
3669 | } | |
3670 | } | |
3671 | else | |
3672 | sched_analyze_2 (x, insn); | |
3673 | ||
3674 | /* Mark registers CLOBBERED or used by called function. */ | |
3675 | if (GET_CODE (insn) == CALL_INSN) | |
3676 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
3677 | { | |
3678 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
3679 | sched_analyze_1 (XEXP (link, 0), insn); | |
3680 | else | |
3681 | sched_analyze_2 (XEXP (link, 0), insn); | |
3682 | } | |
3683 | ||
1f1ed00c JL |
3684 | /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic |
3685 | block, then we must be sure that no instructions are scheduled across it. | |
8c660648 JL |
3686 | Otherwise, the reg_n_refs info (which depends on loop_depth) would |
3687 | become incorrect. */ | |
3688 | ||
3689 | if (loop_notes) | |
3690 | { | |
3691 | int max_reg = max_reg_num (); | |
1f1ed00c | 3692 | int schedule_barrier_found = 0; |
8c660648 JL |
3693 | rtx link; |
3694 | ||
1f1ed00c JL |
3695 | /* Update loop_notes with any notes from this insn. Also determine |
3696 | if any of the notes on the list correspond to instruction scheduling | |
3697 | barriers (loop, eh & setjmp notes, but not range notes. */ | |
8c660648 JL |
3698 | link = loop_notes; |
3699 | while (XEXP (link, 1)) | |
1f1ed00c | 3700 | { |
54c3cf4b JL |
3701 | if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG |
3702 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END | |
3703 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG | |
3704 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END | |
3705 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP) | |
1f1ed00c JL |
3706 | schedule_barrier_found = 1; |
3707 | ||
3708 | link = XEXP (link, 1); | |
3709 | } | |
8c660648 JL |
3710 | XEXP (link, 1) = REG_NOTES (insn); |
3711 | REG_NOTES (insn) = loop_notes; | |
1f1ed00c JL |
3712 | |
3713 | /* Add dependencies if a scheduling barrier was found. */ | |
3714 | if (schedule_barrier_found) | |
3715 | { | |
3716 | for (i = 0; i < max_reg; i++) | |
3717 | { | |
3718 | rtx u; | |
3719 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3720 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3721 | free_INSN_LIST_list (®_last_uses[i]); |
1f1ed00c | 3722 | |
1f1ed00c JL |
3723 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3724 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3725 | |
3726 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3727 | add_dependence (insn, XEXP (u, 0), 0); | |
1f1ed00c JL |
3728 | } |
3729 | reg_pending_sets_all = 1; | |
3730 | ||
3731 | flush_pending_lists (insn, 0); | |
3732 | } | |
3733 | ||
8c660648 JL |
3734 | } |
3735 | ||
63de6c74 | 3736 | /* Accumulate clobbers until the next set so that it will be output dependent |
28c95eff | 3737 | on all of them. At the next set we can clear the clobber list, since |
63de6c74 | 3738 | subsequent sets will be output dependent on it. */ |
8c660648 JL |
3739 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, |
3740 | { | |
5a4f6418 AM |
3741 | free_INSN_LIST_list (®_last_sets[i]); |
3742 | free_INSN_LIST_list (®_last_clobbers[i]); | |
8c660648 | 3743 | reg_last_sets[i] |
ebb7b10b | 3744 | = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 | 3745 | }); |
28c95eff RH |
3746 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, |
3747 | { | |
3748 | reg_last_clobbers[i] | |
63de6c74 MH |
3749 | = alloc_INSN_LIST (insn, |
3750 | reg_last_clobbers[i]); | |
28c95eff | 3751 | }); |
8c660648 | 3752 | CLEAR_REG_SET (reg_pending_sets); |
28c95eff | 3753 | CLEAR_REG_SET (reg_pending_clobbers); |
8c660648 JL |
3754 | |
3755 | if (reg_pending_sets_all) | |
3756 | { | |
3757 | for (i = 0; i < maxreg; i++) | |
ebb7b10b | 3758 | { |
5a4f6418 | 3759 | free_INSN_LIST_list (®_last_sets[i]); |
ebb7b10b RH |
3760 | reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX); |
3761 | } | |
8c660648 JL |
3762 | |
3763 | reg_pending_sets_all = 0; | |
3764 | } | |
3765 | ||
3766 | /* Handle function calls and function returns created by the epilogue | |
3767 | threading code. */ | |
3768 | if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
3769 | { | |
3770 | rtx dep_insn; | |
3771 | rtx prev_dep_insn; | |
3772 | ||
3773 | /* When scheduling instructions, we make sure calls don't lose their | |
3774 | accompanying USE insns by depending them one on another in order. | |
3775 | ||
3776 | Also, we must do the same thing for returns created by the epilogue | |
3777 | threading code. Note this code works only in this special case, | |
3778 | because other passes make no guarantee that they will never emit | |
3779 | an instruction between a USE and a RETURN. There is such a guarantee | |
3780 | for USE instructions immediately before a call. */ | |
3781 | ||
3782 | prev_dep_insn = insn; | |
3783 | dep_insn = PREV_INSN (insn); | |
3784 | while (GET_CODE (dep_insn) == INSN | |
3785 | && GET_CODE (PATTERN (dep_insn)) == USE | |
3786 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG) | |
3787 | { | |
3788 | SCHED_GROUP_P (prev_dep_insn) = 1; | |
3789 | ||
3790 | /* Make a copy of all dependencies on dep_insn, and add to insn. | |
3791 | This is so that all of the dependencies will apply to the | |
3792 | group. */ | |
3793 | ||
3794 | for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1)) | |
3795 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3796 | ||
3797 | prev_dep_insn = dep_insn; | |
3798 | dep_insn = PREV_INSN (dep_insn); | |
3799 | } | |
3800 | } | |
3801 | } | |
3802 | ||
3803 | /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS | |
3804 | for every dependency. */ | |
3805 | ||
3806 | static void | |
3807 | sched_analyze (head, tail) | |
3808 | rtx head, tail; | |
3809 | { | |
3810 | register rtx insn; | |
3811 | register rtx u; | |
3812 | rtx loop_notes = 0; | |
3813 | ||
3814 | for (insn = head;; insn = NEXT_INSN (insn)) | |
3815 | { | |
3816 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) | |
3817 | { | |
87373fba RH |
3818 | /* Clear out the stale LOG_LINKS from flow. */ |
3819 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3820 | ||
63de6c74 MH |
3821 | /* Make each JUMP_INSN a scheduling barrier for memory |
3822 | references. */ | |
062ae7ed JL |
3823 | if (GET_CODE (insn) == JUMP_INSN) |
3824 | last_pending_memory_flush | |
3825 | = alloc_INSN_LIST (insn, last_pending_memory_flush); | |
8c660648 JL |
3826 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); |
3827 | loop_notes = 0; | |
3828 | } | |
3829 | else if (GET_CODE (insn) == CALL_INSN) | |
3830 | { | |
3831 | rtx x; | |
3832 | register int i; | |
3833 | ||
3834 | CANT_MOVE (insn) = 1; | |
3835 | ||
87373fba RH |
3836 | /* Clear out the stale LOG_LINKS from flow. */ |
3837 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3838 | ||
8c660648 JL |
3839 | /* Any instruction using a hard register which may get clobbered |
3840 | by a call needs to be marked as dependent on this call. | |
3841 | This prevents a use of a hard return reg from being moved | |
3842 | past a void call (i.e. it does not explicitly set the hard | |
3843 | return reg). */ | |
3844 | ||
3845 | /* If this call is followed by a NOTE_INSN_SETJMP, then assume that | |
3846 | all registers, not just hard registers, may be clobbered by this | |
3847 | call. */ | |
3848 | ||
3849 | /* Insn, being a CALL_INSN, magically depends on | |
3850 | `last_function_call' already. */ | |
3851 | ||
3852 | if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE | |
3853 | && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP) | |
3854 | { | |
3855 | int max_reg = max_reg_num (); | |
3856 | for (i = 0; i < max_reg; i++) | |
3857 | { | |
3858 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3859 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3860 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3861 | |
8c660648 JL |
3862 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3863 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3864 | |
3865 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3866 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3867 | } |
3868 | reg_pending_sets_all = 1; | |
3869 | ||
63de6c74 | 3870 | /* Add a pair of fake REG_NOTEs which we will later |
8c660648 JL |
3871 | convert back into a NOTE_INSN_SETJMP note. See |
3872 | reemit_notes for why we use a pair of NOTEs. */ | |
ebb7b10b RH |
3873 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD, |
3874 | GEN_INT (0), | |
3875 | REG_NOTES (insn)); | |
3876 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD, | |
3877 | GEN_INT (NOTE_INSN_SETJMP), | |
3878 | REG_NOTES (insn)); | |
8c660648 JL |
3879 | } |
3880 | else | |
3881 | { | |
3882 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3883 | if (call_used_regs[i] || global_regs[i]) | |
3884 | { | |
3885 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3886 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 | 3887 | |
8c660648 JL |
3888 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3889 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3890 | ||
c1cb76e9 | 3891 | SET_REGNO_REG_SET (reg_pending_clobbers, i); |
8c660648 JL |
3892 | } |
3893 | } | |
3894 | ||
3895 | /* For each insn which shouldn't cross a call, add a dependence | |
3896 | between that insn and this call insn. */ | |
3897 | x = LOG_LINKS (sched_before_next_call); | |
3898 | while (x) | |
3899 | { | |
3900 | add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI); | |
3901 | x = XEXP (x, 1); | |
3902 | } | |
2a780534 | 3903 | free_INSN_LIST_list (&LOG_LINKS (sched_before_next_call)); |
8c660648 JL |
3904 | |
3905 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); | |
3906 | loop_notes = 0; | |
3907 | ||
3908 | /* In the absence of interprocedural alias analysis, we must flush | |
3909 | all pending reads and writes, and start new dependencies starting | |
3910 | from here. But only flush writes for constant calls (which may | |
3911 | be passed a pointer to something we haven't written yet). */ | |
3912 | flush_pending_lists (insn, CONST_CALL_P (insn)); | |
3913 | ||
3914 | /* Depend this function call (actually, the user of this | |
3915 | function call) on all hard register clobberage. */ | |
3916 | ||
63de6c74 | 3917 | /* last_function_call is now a list of insns. */ |
5a4f6418 | 3918 | free_INSN_LIST_list(&last_function_call); |
ebb7b10b | 3919 | last_function_call = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3920 | } |
3921 | ||
63de6c74 MH |
3922 | /* See comments on reemit_notes as to why we do this. |
3923 | ??? Actually, the reemit_notes just say what is done, not why. */ | |
6dfdecdb RH |
3924 | |
3925 | else if (GET_CODE (insn) == NOTE | |
3926 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START | |
3927 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END)) | |
3928 | { | |
3929 | loop_notes = alloc_EXPR_LIST (REG_DEAD, NOTE_RANGE_INFO (insn), | |
3930 | loop_notes); | |
3931 | loop_notes = alloc_EXPR_LIST (REG_DEAD, | |
3932 | GEN_INT (NOTE_LINE_NUMBER (insn)), | |
3933 | loop_notes); | |
3934 | } | |
8c660648 JL |
3935 | else if (GET_CODE (insn) == NOTE |
3936 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG | |
3937 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END | |
3938 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG | |
3939 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END | |
3940 | || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP | |
3941 | && GET_CODE (PREV_INSN (insn)) != CALL_INSN))) | |
3942 | { | |
f5db61ef | 3943 | rtx rtx_region; |
7bd41ea6 | 3944 | |
1a4450c7 MM |
3945 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG |
3946 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END) | |
f5db61ef | 3947 | rtx_region = GEN_INT (NOTE_EH_HANDLER (insn)); |
7bd41ea6 | 3948 | else |
f5db61ef | 3949 | rtx_region = GEN_INT (0); |
1a4450c7 | 3950 | |
7bd41ea6 | 3951 | loop_notes = alloc_EXPR_LIST (REG_DEAD, |
f5db61ef | 3952 | rtx_region, |
7bd41ea6 | 3953 | loop_notes); |
ebb7b10b RH |
3954 | loop_notes = alloc_EXPR_LIST (REG_DEAD, |
3955 | GEN_INT (NOTE_LINE_NUMBER (insn)), | |
3956 | loop_notes); | |
8c660648 JL |
3957 | CONST_CALL_P (loop_notes) = CONST_CALL_P (insn); |
3958 | } | |
3959 | ||
3960 | if (insn == tail) | |
3961 | return; | |
3962 | } | |
3963 | abort (); | |
3964 | } | |
3965 | \f | |
3966 | /* Called when we see a set of a register. If death is true, then we are | |
3967 | scanning backwards. Mark that register as unborn. If nobody says | |
3968 | otherwise, that is how things will remain. If death is false, then we | |
3969 | are scanning forwards. Mark that register as being born. */ | |
3970 | ||
3971 | static void | |
5835e573 | 3972 | sched_note_set (x, death) |
8c660648 JL |
3973 | rtx x; |
3974 | int death; | |
3975 | { | |
3976 | register int regno; | |
3977 | register rtx reg = SET_DEST (x); | |
3978 | int subreg_p = 0; | |
3979 | ||
3980 | if (reg == 0) | |
3981 | return; | |
3982 | ||
c0222c21 DM |
3983 | if (GET_CODE (reg) == PARALLEL |
3984 | && GET_MODE (reg) == BLKmode) | |
3985 | { | |
3986 | register int i; | |
3987 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
3988 | sched_note_set (XVECEXP (reg, 0, i), death); | |
3989 | return; | |
3990 | } | |
3991 | ||
8c660648 JL |
3992 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART |
3993 | || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT) | |
3994 | { | |
3995 | /* Must treat modification of just one hardware register of a multi-reg | |
3996 | value or just a byte field of a register exactly the same way that | |
3997 | mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg | |
3998 | does not kill the entire register. */ | |
3999 | if (GET_CODE (reg) != SUBREG | |
4000 | || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg)) | |
4001 | subreg_p = 1; | |
4002 | ||
4003 | reg = SUBREG_REG (reg); | |
4004 | } | |
4005 | ||
4006 | if (GET_CODE (reg) != REG) | |
4007 | return; | |
4008 | ||
4009 | /* Global registers are always live, so the code below does not apply | |
4010 | to them. */ | |
4011 | ||
4012 | regno = REGNO (reg); | |
4013 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
4014 | { | |
4015 | if (death) | |
4016 | { | |
4017 | /* If we only set part of the register, then this set does not | |
4018 | kill it. */ | |
4019 | if (subreg_p) | |
4020 | return; | |
4021 | ||
4022 | /* Try killing this register. */ | |
4023 | if (regno < FIRST_PSEUDO_REGISTER) | |
4024 | { | |
4025 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
4026 | while (--j >= 0) | |
4027 | { | |
4028 | CLEAR_REGNO_REG_SET (bb_live_regs, regno + j); | |
4029 | } | |
4030 | } | |
4031 | else | |
4032 | { | |
4033 | /* Recompute REG_BASIC_BLOCK as we update all the other | |
4034 | dataflow information. */ | |
4035 | if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN) | |
4036 | sched_reg_basic_block[regno] = current_block_num; | |
4037 | else if (sched_reg_basic_block[regno] != current_block_num) | |
4038 | sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL; | |
4039 | ||
4040 | CLEAR_REGNO_REG_SET (bb_live_regs, regno); | |
4041 | } | |
4042 | } | |
4043 | else | |
4044 | { | |
4045 | /* Make the register live again. */ | |
4046 | if (regno < FIRST_PSEUDO_REGISTER) | |
4047 | { | |
4048 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
4049 | while (--j >= 0) | |
4050 | { | |
4051 | SET_REGNO_REG_SET (bb_live_regs, regno + j); | |
4052 | } | |
4053 | } | |
4054 | else | |
4055 | { | |
4056 | SET_REGNO_REG_SET (bb_live_regs, regno); | |
4057 | } | |
4058 | } | |
4059 | } | |
4060 | } | |
4061 | \f | |
4062 | /* Macros and functions for keeping the priority queue sorted, and | |
4063 | dealing with queueing and dequeueing of instructions. */ | |
4064 | ||
4065 | #define SCHED_SORT(READY, N_READY) \ | |
4066 | do { if ((N_READY) == 2) \ | |
4067 | swap_sort (READY, N_READY); \ | |
4068 | else if ((N_READY) > 2) \ | |
4069 | qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ | |
4070 | while (0) | |
4071 | ||
4072 | /* Returns a positive value if x is preferred; returns a negative value if | |
4073 | y is preferred. Should never return 0, since that will make the sort | |
4074 | unstable. */ | |
4075 | ||
4076 | static int | |
4077 | rank_for_schedule (x, y) | |
e1b6684c KG |
4078 | const PTR x; |
4079 | const PTR y; | |
8c660648 | 4080 | { |
01c7f350 MM |
4081 | rtx tmp = *(rtx *)y; |
4082 | rtx tmp2 = *(rtx *)x; | |
8c660648 | 4083 | rtx link; |
2db45993 | 4084 | int tmp_class, tmp2_class, depend_count1, depend_count2; |
8c660648 JL |
4085 | int val, priority_val, spec_val, prob_val, weight_val; |
4086 | ||
4087 | ||
63de6c74 | 4088 | /* Prefer insn with higher priority. */ |
8c660648 JL |
4089 | priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp); |
4090 | if (priority_val) | |
4091 | return priority_val; | |
4092 | ||
63de6c74 | 4093 | /* Prefer an insn with smaller contribution to registers-pressure. */ |
8c660648 JL |
4094 | if (!reload_completed && |
4095 | (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2))) | |
4096 | return (weight_val); | |
4097 | ||
63de6c74 | 4098 | /* Some comparison make sense in interblock scheduling only. */ |
8c660648 JL |
4099 | if (INSN_BB (tmp) != INSN_BB (tmp2)) |
4100 | { | |
63de6c74 | 4101 | /* Prefer an inblock motion on an interblock motion. */ |
8c660648 JL |
4102 | if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb)) |
4103 | return 1; | |
4104 | if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb)) | |
4105 | return -1; | |
4106 | ||
63de6c74 | 4107 | /* Prefer a useful motion on a speculative one. */ |
8c660648 JL |
4108 | if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2))) |
4109 | return (spec_val); | |
4110 | ||
63de6c74 | 4111 | /* Prefer a more probable (speculative) insn. */ |
8c660648 JL |
4112 | prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp); |
4113 | if (prob_val) | |
4114 | return (prob_val); | |
4115 | } | |
4116 | ||
63de6c74 | 4117 | /* Compare insns based on their relation to the last-scheduled-insn. */ |
8c660648 JL |
4118 | if (last_scheduled_insn) |
4119 | { | |
4120 | /* Classify the instructions into three classes: | |
4121 | 1) Data dependent on last schedule insn. | |
4122 | 2) Anti/Output dependent on last scheduled insn. | |
4123 | 3) Independent of last scheduled insn, or has latency of one. | |
4124 | Choose the insn from the highest numbered class if different. */ | |
4125 | link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn)); | |
4126 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1) | |
4127 | tmp_class = 3; | |
4128 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4129 | tmp_class = 1; | |
4130 | else | |
4131 | tmp_class = 2; | |
4132 | ||
4133 | link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn)); | |
4134 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1) | |
4135 | tmp2_class = 3; | |
4136 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4137 | tmp2_class = 1; | |
4138 | else | |
4139 | tmp2_class = 2; | |
4140 | ||
4141 | if ((val = tmp2_class - tmp_class)) | |
4142 | return val; | |
4143 | } | |
4144 | ||
2db45993 JL |
4145 | /* Prefer the insn which has more later insns that depend on it. |
4146 | This gives the scheduler more freedom when scheduling later | |
4147 | instructions at the expense of added register pressure. */ | |
4148 | depend_count1 = 0; | |
4149 | for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1)) | |
4150 | depend_count1++; | |
4151 | ||
4152 | depend_count2 = 0; | |
4153 | for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1)) | |
4154 | depend_count2++; | |
4155 | ||
4156 | val = depend_count2 - depend_count1; | |
4157 | if (val) | |
4158 | return val; | |
4159 | ||
8c660648 JL |
4160 | /* If insns are equally good, sort by INSN_LUID (original insn order), |
4161 | so that we make the sort stable. This minimizes instruction movement, | |
4162 | thus minimizing sched's effect on debugging and cross-jumping. */ | |
4163 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
4164 | } | |
4165 | ||
4166 | /* Resort the array A in which only element at index N may be out of order. */ | |
4167 | ||
cbb13457 | 4168 | HAIFA_INLINE static void |
8c660648 JL |
4169 | swap_sort (a, n) |
4170 | rtx *a; | |
4171 | int n; | |
4172 | { | |
4173 | rtx insn = a[n - 1]; | |
4174 | int i = n - 2; | |
4175 | ||
4176 | while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0) | |
4177 | { | |
4178 | a[i + 1] = a[i]; | |
4179 | i -= 1; | |
4180 | } | |
4181 | a[i + 1] = insn; | |
4182 | } | |
4183 | ||
4184 | static int max_priority; | |
4185 | ||
4186 | /* Add INSN to the insn queue so that it can be executed at least | |
4187 | N_CYCLES after the currently executing insn. Preserve insns | |
4188 | chain for debugging purposes. */ | |
4189 | ||
cbb13457 | 4190 | HAIFA_INLINE static void |
8c660648 JL |
4191 | queue_insn (insn, n_cycles) |
4192 | rtx insn; | |
4193 | int n_cycles; | |
4194 | { | |
4195 | int next_q = NEXT_Q_AFTER (q_ptr, n_cycles); | |
ebb7b10b | 4196 | rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]); |
8c660648 JL |
4197 | insn_queue[next_q] = link; |
4198 | q_size += 1; | |
4199 | ||
4200 | if (sched_verbose >= 2) | |
4201 | { | |
4202 | fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn)); | |
4203 | ||
4204 | if (INSN_BB (insn) != target_bb) | |
4205 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
4206 | ||
4207 | fprintf (dump, "queued for %d cycles.\n", n_cycles); | |
4208 | } | |
4209 | ||
4210 | } | |
4211 | ||
4212 | /* Return nonzero if PAT is the pattern of an insn which makes a | |
4213 | register live. */ | |
4214 | ||
cbb13457 | 4215 | HAIFA_INLINE static int |
8c660648 JL |
4216 | birthing_insn_p (pat) |
4217 | rtx pat; | |
4218 | { | |
4219 | int j; | |
4220 | ||
4221 | if (reload_completed == 1) | |
4222 | return 0; | |
4223 | ||
4224 | if (GET_CODE (pat) == SET | |
c0222c21 DM |
4225 | && (GET_CODE (SET_DEST (pat)) == REG |
4226 | || (GET_CODE (SET_DEST (pat)) == PARALLEL | |
4227 | && GET_MODE (SET_DEST (pat)) == BLKmode))) | |
8c660648 JL |
4228 | { |
4229 | rtx dest = SET_DEST (pat); | |
c0222c21 | 4230 | int i; |
8c660648 JL |
4231 | |
4232 | /* It would be more accurate to use refers_to_regno_p or | |
c0222c21 DM |
4233 | reg_mentioned_p to determine when the dest is not live before this |
4234 | insn. */ | |
4235 | if (GET_CODE (dest) == REG) | |
4236 | { | |
4237 | i = REGNO (dest); | |
4238 | if (REGNO_REG_SET_P (bb_live_regs, i)) | |
4239 | return (REG_N_SETS (i) == 1); | |
4240 | } | |
4241 | else | |
4242 | { | |
4243 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
4244 | { | |
4245 | int regno = REGNO (SET_DEST (XVECEXP (dest, 0, i))); | |
4246 | if (REGNO_REG_SET_P (bb_live_regs, regno)) | |
4247 | return (REG_N_SETS (regno) == 1); | |
4248 | } | |
4249 | } | |
8c660648 JL |
4250 | return 0; |
4251 | } | |
4252 | if (GET_CODE (pat) == PARALLEL) | |
4253 | { | |
4254 | for (j = 0; j < XVECLEN (pat, 0); j++) | |
4255 | if (birthing_insn_p (XVECEXP (pat, 0, j))) | |
4256 | return 1; | |
4257 | } | |
4258 | return 0; | |
4259 | } | |
4260 | ||
4261 | /* PREV is an insn that is ready to execute. Adjust its priority if that | |
4262 | will help shorten register lifetimes. */ | |
4263 | ||
cbb13457 | 4264 | HAIFA_INLINE static void |
8c660648 JL |
4265 | adjust_priority (prev) |
4266 | rtx prev; | |
4267 | { | |
4268 | /* Trying to shorten register lives after reload has completed | |
4269 | is useless and wrong. It gives inaccurate schedules. */ | |
4270 | if (reload_completed == 0) | |
4271 | { | |
4272 | rtx note; | |
4273 | int n_deaths = 0; | |
4274 | ||
4275 | /* ??? This code has no effect, because REG_DEAD notes are removed | |
4276 | before we ever get here. */ | |
4277 | for (note = REG_NOTES (prev); note; note = XEXP (note, 1)) | |
4278 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
4279 | n_deaths += 1; | |
4280 | ||
4281 | /* Defer scheduling insns which kill registers, since that | |
4282 | shortens register lives. Prefer scheduling insns which | |
4283 | make registers live for the same reason. */ | |
4284 | switch (n_deaths) | |
4285 | { | |
4286 | default: | |
4287 | INSN_PRIORITY (prev) >>= 3; | |
4288 | break; | |
4289 | case 3: | |
4290 | INSN_PRIORITY (prev) >>= 2; | |
4291 | break; | |
4292 | case 2: | |
4293 | case 1: | |
4294 | INSN_PRIORITY (prev) >>= 1; | |
4295 | break; | |
4296 | case 0: | |
4297 | if (birthing_insn_p (PATTERN (prev))) | |
4298 | { | |
4299 | int max = max_priority; | |
4300 | ||
4301 | if (max > INSN_PRIORITY (prev)) | |
4302 | INSN_PRIORITY (prev) = max; | |
4303 | } | |
4304 | break; | |
4305 | } | |
197043f5 RH |
4306 | } |
4307 | ||
4308 | /* That said, a target might have it's own reasons for adjusting | |
4309 | priority after reload. */ | |
8c660648 | 4310 | #ifdef ADJUST_PRIORITY |
197043f5 | 4311 | ADJUST_PRIORITY (prev); |
8c660648 | 4312 | #endif |
8c660648 JL |
4313 | } |
4314 | ||
4bdc8810 RH |
4315 | /* Clock at which the previous instruction was issued. */ |
4316 | static int last_clock_var; | |
4317 | ||
8c660648 JL |
4318 | /* INSN is the "currently executing insn". Launch each insn which was |
4319 | waiting on INSN. READY is a vector of insns which are ready to fire. | |
4320 | N_READY is the number of elements in READY. CLOCK is the current | |
4321 | cycle. */ | |
4322 | ||
4323 | static int | |
4324 | schedule_insn (insn, ready, n_ready, clock) | |
4325 | rtx insn; | |
4326 | rtx *ready; | |
4327 | int n_ready; | |
4328 | int clock; | |
4329 | { | |
4330 | rtx link; | |
4331 | int unit; | |
4332 | ||
4333 | unit = insn_unit (insn); | |
4334 | ||
4335 | if (sched_verbose >= 2) | |
4336 | { | |
63de6c74 MH |
4337 | fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", |
4338 | INSN_UID (insn)); | |
8c660648 JL |
4339 | insn_print_units (insn); |
4340 | fprintf (dump, "\n"); | |
4341 | } | |
4342 | ||
4343 | if (sched_verbose && unit == -1) | |
4344 | visualize_no_unit (insn); | |
4345 | ||
4346 | if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose) | |
4347 | schedule_unit (unit, insn, clock); | |
4348 | ||
4349 | if (INSN_DEPEND (insn) == 0) | |
4350 | return n_ready; | |
4351 | ||
4352 | /* This is used by the function adjust_priority above. */ | |
4353 | if (n_ready > 0) | |
4354 | max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn)); | |
4355 | else | |
4356 | max_priority = INSN_PRIORITY (insn); | |
4357 | ||
4358 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
4359 | { | |
4360 | rtx next = XEXP (link, 0); | |
4361 | int cost = insn_cost (insn, link, next); | |
4362 | ||
4363 | INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost); | |
4364 | ||
4365 | if ((INSN_DEP_COUNT (next) -= 1) == 0) | |
4366 | { | |
4367 | int effective_cost = INSN_TICK (next) - clock; | |
4368 | ||
4369 | /* For speculative insns, before inserting to ready/queue, | |
63de6c74 | 4370 | check live, exception-free, and issue-delay. */ |
8c660648 JL |
4371 | if (INSN_BB (next) != target_bb |
4372 | && (!IS_VALID (INSN_BB (next)) | |
4373 | || CANT_MOVE (next) | |
4374 | || (IS_SPECULATIVE_INSN (next) | |
4375 | && (insn_issue_delay (next) > 3 | |
5835e573 | 4376 | || !check_live (next, INSN_BB (next)) |
8c660648 JL |
4377 | || !is_exception_free (next, INSN_BB (next), target_bb))))) |
4378 | continue; | |
4379 | ||
4380 | if (sched_verbose >= 2) | |
4381 | { | |
63de6c74 MH |
4382 | fprintf (dump, ";;\t\tdependences resolved: insn %d ", |
4383 | INSN_UID (next)); | |
8c660648 JL |
4384 | |
4385 | if (current_nr_blocks > 1 && INSN_BB (next) != target_bb) | |
4386 | fprintf (dump, "/b%d ", INSN_BLOCK (next)); | |
4387 | ||
197043f5 | 4388 | if (effective_cost < 1) |
8c660648 JL |
4389 | fprintf (dump, "into ready\n"); |
4390 | else | |
4391 | fprintf (dump, "into queue with cost=%d\n", effective_cost); | |
4392 | } | |
4393 | ||
4394 | /* Adjust the priority of NEXT and either put it on the ready | |
4395 | list or queue it. */ | |
4396 | adjust_priority (next); | |
197043f5 | 4397 | if (effective_cost < 1) |
8c660648 JL |
4398 | ready[n_ready++] = next; |
4399 | else | |
4400 | queue_insn (next, effective_cost); | |
4401 | } | |
4402 | } | |
4403 | ||
4bdc8810 RH |
4404 | /* Annotate the instruction with issue information -- TImode |
4405 | indicates that the instruction is expected not to be able | |
4406 | to issue on the same cycle as the previous insn. A machine | |
4407 | may use this information to decide how the instruction should | |
4408 | be aligned. */ | |
4409 | if (reload_completed && issue_rate > 1) | |
4410 | { | |
4411 | PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode); | |
4412 | last_clock_var = clock; | |
4413 | } | |
4414 | ||
8c660648 JL |
4415 | return n_ready; |
4416 | } | |
4417 | ||
4418 | ||
4419 | /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the | |
4420 | dead_notes list. */ | |
4421 | ||
4422 | static void | |
4423 | create_reg_dead_note (reg, insn) | |
4424 | rtx reg, insn; | |
4425 | { | |
4426 | rtx link; | |
4427 | ||
4428 | /* The number of registers killed after scheduling must be the same as the | |
4429 | number of registers killed before scheduling. The number of REG_DEAD | |
4430 | notes may not be conserved, i.e. two SImode hard register REG_DEAD notes | |
4431 | might become one DImode hard register REG_DEAD note, but the number of | |
4432 | registers killed will be conserved. | |
4433 | ||
4434 | We carefully remove REG_DEAD notes from the dead_notes list, so that | |
4435 | there will be none left at the end. If we run out early, then there | |
4436 | is a bug somewhere in flow, combine and/or sched. */ | |
4437 | ||
4438 | if (dead_notes == 0) | |
4439 | { | |
4440 | if (current_nr_blocks <= 1) | |
4441 | abort (); | |
4442 | else | |
ebb7b10b | 4443 | link = alloc_EXPR_LIST (REG_DEAD, NULL_RTX, NULL_RTX); |
8c660648 JL |
4444 | } |
4445 | else | |
4446 | { | |
4447 | /* Number of regs killed by REG. */ | |
4448 | int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1 | |
4449 | : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg))); | |
4450 | /* Number of regs killed by REG_DEAD notes taken off the list. */ | |
4451 | int reg_note_regs; | |
4452 | ||
4453 | link = dead_notes; | |
4454 | reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 | |
4455 | : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), | |
4456 | GET_MODE (XEXP (link, 0)))); | |
4457 | while (reg_note_regs < regs_killed) | |
4458 | { | |
4459 | link = XEXP (link, 1); | |
04029ca2 JL |
4460 | |
4461 | /* LINK might be zero if we killed more registers after scheduling | |
4462 | than before, and the last hard register we kill is actually | |
4463 | multiple hard regs. | |
4464 | ||
4465 | This is normal for interblock scheduling, so deal with it in | |
4466 | that case, else abort. */ | |
4467 | if (link == NULL_RTX && current_nr_blocks <= 1) | |
4468 | abort (); | |
4469 | else if (link == NULL_RTX) | |
ebb7b10b RH |
4470 | link = alloc_EXPR_LIST (REG_DEAD, gen_rtx_REG (word_mode, 0), |
4471 | NULL_RTX); | |
04029ca2 | 4472 | |
8c660648 JL |
4473 | reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 |
4474 | : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), | |
4475 | GET_MODE (XEXP (link, 0)))); | |
4476 | } | |
4477 | dead_notes = XEXP (link, 1); | |
4478 | ||
4479 | /* If we took too many regs kills off, put the extra ones back. */ | |
4480 | while (reg_note_regs > regs_killed) | |
4481 | { | |
4482 | rtx temp_reg, temp_link; | |
4483 | ||
38a448ca | 4484 | temp_reg = gen_rtx_REG (word_mode, 0); |
ebb7b10b | 4485 | temp_link = alloc_EXPR_LIST (REG_DEAD, temp_reg, dead_notes); |
8c660648 JL |
4486 | dead_notes = temp_link; |
4487 | reg_note_regs--; | |
4488 | } | |
4489 | } | |
4490 | ||
4491 | XEXP (link, 0) = reg; | |
4492 | XEXP (link, 1) = REG_NOTES (insn); | |
4493 | REG_NOTES (insn) = link; | |
4494 | } | |
4495 | ||
4496 | /* Subroutine on attach_deaths_insn--handles the recursive search | |
4497 | through INSN. If SET_P is true, then x is being modified by the insn. */ | |
4498 | ||
4499 | static void | |
4500 | attach_deaths (x, insn, set_p) | |
4501 | rtx x; | |
4502 | rtx insn; | |
4503 | int set_p; | |
4504 | { | |
4505 | register int i; | |
4506 | register int j; | |
4507 | register enum rtx_code code; | |
6f7d635c | 4508 | register const char *fmt; |
8c660648 JL |
4509 | |
4510 | if (x == 0) | |
4511 | return; | |
4512 | ||
4513 | code = GET_CODE (x); | |
4514 | ||
4515 | switch (code) | |
4516 | { | |
4517 | case CONST_INT: | |
4518 | case CONST_DOUBLE: | |
4519 | case LABEL_REF: | |
4520 | case SYMBOL_REF: | |
4521 | case CONST: | |
4522 | case CODE_LABEL: | |
4523 | case PC: | |
4524 | case CC0: | |
4525 | /* Get rid of the easy cases first. */ | |
4526 | return; | |
4527 | ||
4528 | case REG: | |
4529 | { | |
4530 | /* If the register dies in this insn, queue that note, and mark | |
4531 | this register as needing to die. */ | |
4532 | /* This code is very similar to mark_used_1 (if set_p is false) | |
4533 | and mark_set_1 (if set_p is true) in flow.c. */ | |
4534 | ||
4535 | register int regno; | |
4536 | int some_needed; | |
4537 | int all_needed; | |
4538 | ||
4539 | if (set_p) | |
4540 | return; | |
4541 | ||
4542 | regno = REGNO (x); | |
4543 | all_needed = some_needed = REGNO_REG_SET_P (old_live_regs, regno); | |
4544 | if (regno < FIRST_PSEUDO_REGISTER) | |
4545 | { | |
4546 | int n; | |
4547 | ||
4548 | n = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4549 | while (--n > 0) | |
4550 | { | |
4551 | int needed = (REGNO_REG_SET_P (old_live_regs, regno + n)); | |
4552 | some_needed |= needed; | |
4553 | all_needed &= needed; | |
4554 | } | |
4555 | } | |
4556 | ||
4557 | /* If it wasn't live before we started, then add a REG_DEAD note. | |
4558 | We must check the previous lifetime info not the current info, | |
4559 | because we may have to execute this code several times, e.g. | |
4560 | once for a clobber (which doesn't add a note) and later | |
4561 | for a use (which does add a note). | |
4562 | ||
4563 | Always make the register live. We must do this even if it was | |
4564 | live before, because this may be an insn which sets and uses | |
4565 | the same register, in which case the register has already been | |
4566 | killed, so we must make it live again. | |
4567 | ||
4568 | Global registers are always live, and should never have a REG_DEAD | |
4569 | note added for them, so none of the code below applies to them. */ | |
4570 | ||
4571 | if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno]) | |
4572 | { | |
e4b8a413 JW |
4573 | /* Never add REG_DEAD notes for STACK_POINTER_REGNUM |
4574 | since it's always considered to be live. Similarly | |
4575 | for FRAME_POINTER_REGNUM if a frame pointer is needed | |
4576 | and for ARG_POINTER_REGNUM if it is fixed. */ | |
4577 | if (! (regno == FRAME_POINTER_REGNUM | |
4578 | && (! reload_completed || frame_pointer_needed)) | |
8c660648 | 4579 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
e4b8a413 JW |
4580 | && ! (regno == HARD_FRAME_POINTER_REGNUM |
4581 | && (! reload_completed || frame_pointer_needed)) | |
8c660648 JL |
4582 | #endif |
4583 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
4584 | && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
4585 | #endif | |
4586 | && regno != STACK_POINTER_REGNUM) | |
4587 | { | |
d6df9efb | 4588 | if (! all_needed && ! dead_or_set_p (insn, x)) |
8c660648 JL |
4589 | { |
4590 | /* Check for the case where the register dying partially | |
4591 | overlaps the register set by this insn. */ | |
4592 | if (regno < FIRST_PSEUDO_REGISTER | |
4593 | && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) | |
4594 | { | |
4595 | int n = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4596 | while (--n >= 0) | |
4597 | some_needed |= dead_or_set_regno_p (insn, regno + n); | |
4598 | } | |
4599 | ||
4600 | /* If none of the words in X is needed, make a REG_DEAD | |
4601 | note. Otherwise, we must make partial REG_DEAD | |
4602 | notes. */ | |
4603 | if (! some_needed) | |
4604 | create_reg_dead_note (x, insn); | |
4605 | else | |
4606 | { | |
4607 | int i; | |
4608 | ||
4609 | /* Don't make a REG_DEAD note for a part of a | |
4610 | register that is set in the insn. */ | |
4611 | for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1; | |
4612 | i >= 0; i--) | |
4613 | if (! REGNO_REG_SET_P (old_live_regs, regno+i) | |
4614 | && ! dead_or_set_regno_p (insn, regno + i)) | |
38a448ca RH |
4615 | create_reg_dead_note (gen_rtx_REG (reg_raw_mode[regno + i], |
4616 | regno + i), | |
8c660648 JL |
4617 | insn); |
4618 | } | |
4619 | } | |
4620 | } | |
4621 | ||
4622 | if (regno < FIRST_PSEUDO_REGISTER) | |
4623 | { | |
4624 | int j = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4625 | while (--j >= 0) | |
4626 | { | |
4627 | SET_REGNO_REG_SET (bb_live_regs, regno + j); | |
4628 | } | |
4629 | } | |
4630 | else | |
4631 | { | |
4632 | /* Recompute REG_BASIC_BLOCK as we update all the other | |
4633 | dataflow information. */ | |
4634 | if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN) | |
4635 | sched_reg_basic_block[regno] = current_block_num; | |
4636 | else if (sched_reg_basic_block[regno] != current_block_num) | |
4637 | sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL; | |
4638 | ||
4639 | SET_REGNO_REG_SET (bb_live_regs, regno); | |
4640 | } | |
4641 | } | |
4642 | return; | |
4643 | } | |
4644 | ||
4645 | case MEM: | |
4646 | /* Handle tail-recursive case. */ | |
4647 | attach_deaths (XEXP (x, 0), insn, 0); | |
4648 | return; | |
4649 | ||
4650 | case SUBREG: | |
d6df9efb JL |
4651 | attach_deaths (SUBREG_REG (x), insn, |
4652 | set_p && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
4653 | <= UNITS_PER_WORD) | |
4654 | || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
4655 | == GET_MODE_SIZE (GET_MODE ((x)))))); | |
4656 | return; | |
4657 | ||
8c660648 | 4658 | case STRICT_LOW_PART: |
d6df9efb | 4659 | attach_deaths (XEXP (x, 0), insn, 0); |
8c660648 JL |
4660 | return; |
4661 | ||
4662 | case ZERO_EXTRACT: | |
4663 | case SIGN_EXTRACT: | |
d6df9efb | 4664 | attach_deaths (XEXP (x, 0), insn, 0); |
8c660648 JL |
4665 | attach_deaths (XEXP (x, 1), insn, 0); |
4666 | attach_deaths (XEXP (x, 2), insn, 0); | |
4667 | return; | |
4668 | ||
c0222c21 DM |
4669 | case PARALLEL: |
4670 | if (set_p | |
4671 | && GET_MODE (x) == BLKmode) | |
4672 | { | |
4673 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4674 | attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1); | |
4675 | return; | |
4676 | } | |
4677 | ||
63de6c74 | 4678 | /* Fallthrough. */ |
8c660648 JL |
4679 | default: |
4680 | /* Other cases: walk the insn. */ | |
4681 | fmt = GET_RTX_FORMAT (code); | |
4682 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4683 | { | |
4684 | if (fmt[i] == 'e') | |
4685 | attach_deaths (XEXP (x, i), insn, 0); | |
4686 | else if (fmt[i] == 'E') | |
4687 | for (j = 0; j < XVECLEN (x, i); j++) | |
4688 | attach_deaths (XVECEXP (x, i, j), insn, 0); | |
4689 | } | |
4690 | } | |
4691 | } | |
4692 | ||
4693 | /* After INSN has executed, add register death notes for each register | |
4694 | that is dead after INSN. */ | |
4695 | ||
4696 | static void | |
4697 | attach_deaths_insn (insn) | |
4698 | rtx insn; | |
4699 | { | |
4700 | rtx x = PATTERN (insn); | |
4701 | register RTX_CODE code = GET_CODE (x); | |
4702 | rtx link; | |
4703 | ||
4704 | if (code == SET) | |
4705 | { | |
4706 | attach_deaths (SET_SRC (x), insn, 0); | |
4707 | ||
4708 | /* A register might die here even if it is the destination, e.g. | |
4709 | it is the target of a volatile read and is otherwise unused. | |
4710 | Hence we must always call attach_deaths for the SET_DEST. */ | |
4711 | attach_deaths (SET_DEST (x), insn, 1); | |
4712 | } | |
4713 | else if (code == PARALLEL) | |
4714 | { | |
4715 | register int i; | |
4716 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4717 | { | |
4718 | code = GET_CODE (XVECEXP (x, 0, i)); | |
4719 | if (code == SET) | |
4720 | { | |
4721 | attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0); | |
4722 | ||
4723 | attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1); | |
4724 | } | |
4725 | /* Flow does not add REG_DEAD notes to registers that die in | |
4726 | clobbers, so we can't either. */ | |
4727 | else if (code != CLOBBER) | |
4728 | attach_deaths (XVECEXP (x, 0, i), insn, 0); | |
4729 | } | |
4730 | } | |
4731 | /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a | |
4732 | MEM being clobbered, just like flow. */ | |
4733 | else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == MEM) | |
4734 | attach_deaths (XEXP (XEXP (x, 0), 0), insn, 0); | |
4735 | /* Otherwise don't add a death note to things being clobbered. */ | |
4736 | else if (code != CLOBBER) | |
4737 | attach_deaths (x, insn, 0); | |
4738 | ||
4739 | /* Make death notes for things used in the called function. */ | |
4740 | if (GET_CODE (insn) == CALL_INSN) | |
4741 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
4742 | attach_deaths (XEXP (XEXP (link, 0), 0), insn, | |
4743 | GET_CODE (XEXP (link, 0)) == CLOBBER); | |
4744 | } | |
4745 | ||
63de6c74 | 4746 | /* Functions for handling of notes. */ |
8c660648 JL |
4747 | |
4748 | /* Delete notes beginning with INSN and put them in the chain | |
4749 | of notes ended by NOTE_LIST. | |
4750 | Returns the insn following the notes. */ | |
4751 | ||
4752 | static rtx | |
4753 | unlink_other_notes (insn, tail) | |
4754 | rtx insn, tail; | |
4755 | { | |
4756 | rtx prev = PREV_INSN (insn); | |
4757 | ||
4758 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4759 | { | |
4760 | rtx next = NEXT_INSN (insn); | |
4761 | /* Delete the note from its current position. */ | |
4762 | if (prev) | |
4763 | NEXT_INSN (prev) = next; | |
4764 | if (next) | |
4765 | PREV_INSN (next) = prev; | |
4766 | ||
4767 | /* Don't save away NOTE_INSN_SETJMPs, because they must remain | |
4768 | immediately after the call they follow. We use a fake | |
4769 | (REG_DEAD (const_int -1)) note to remember them. | |
4770 | Likewise with NOTE_INSN_{LOOP,EHREGION}_{BEG, END}. */ | |
4771 | if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP | |
4772 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG | |
4773 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END | |
0dfa1860 MM |
4774 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START |
4775 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END | |
8c660648 JL |
4776 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG |
4777 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END) | |
4778 | { | |
4779 | /* Insert the note at the end of the notes list. */ | |
4780 | PREV_INSN (insn) = note_list; | |
4781 | if (note_list) | |
4782 | NEXT_INSN (note_list) = insn; | |
4783 | note_list = insn; | |
4784 | } | |
4785 | ||
4786 | insn = next; | |
4787 | } | |
4788 | return insn; | |
4789 | } | |
4790 | ||
4791 | /* Delete line notes beginning with INSN. Record line-number notes so | |
4792 | they can be reused. Returns the insn following the notes. */ | |
4793 | ||
4794 | static rtx | |
4795 | unlink_line_notes (insn, tail) | |
4796 | rtx insn, tail; | |
4797 | { | |
4798 | rtx prev = PREV_INSN (insn); | |
4799 | ||
4800 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4801 | { | |
4802 | rtx next = NEXT_INSN (insn); | |
4803 | ||
4804 | if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0) | |
4805 | { | |
4806 | /* Delete the note from its current position. */ | |
4807 | if (prev) | |
4808 | NEXT_INSN (prev) = next; | |
4809 | if (next) | |
4810 | PREV_INSN (next) = prev; | |
4811 | ||
4812 | /* Record line-number notes so they can be reused. */ | |
4813 | LINE_NOTE (insn) = insn; | |
4814 | } | |
4815 | else | |
4816 | prev = insn; | |
4817 | ||
4818 | insn = next; | |
4819 | } | |
4820 | return insn; | |
4821 | } | |
4822 | ||
4823 | /* Return the head and tail pointers of BB. */ | |
4824 | ||
cbb13457 | 4825 | HAIFA_INLINE static void |
8c660648 JL |
4826 | get_block_head_tail (bb, headp, tailp) |
4827 | int bb; | |
4828 | rtx *headp; | |
4829 | rtx *tailp; | |
4830 | { | |
4831 | ||
55d89719 TK |
4832 | rtx head; |
4833 | rtx tail; | |
8c660648 JL |
4834 | int b; |
4835 | ||
4836 | b = BB_TO_BLOCK (bb); | |
4837 | ||
4838 | /* HEAD and TAIL delimit the basic block being scheduled. */ | |
3b413743 RH |
4839 | head = BLOCK_HEAD (b); |
4840 | tail = BLOCK_END (b); | |
8c660648 JL |
4841 | |
4842 | /* Don't include any notes or labels at the beginning of the | |
4843 | basic block, or notes at the ends of basic blocks. */ | |
4844 | while (head != tail) | |
4845 | { | |
4846 | if (GET_CODE (head) == NOTE) | |
4847 | head = NEXT_INSN (head); | |
4848 | else if (GET_CODE (tail) == NOTE) | |
4849 | tail = PREV_INSN (tail); | |
4850 | else if (GET_CODE (head) == CODE_LABEL) | |
4851 | head = NEXT_INSN (head); | |
4852 | else | |
4853 | break; | |
4854 | } | |
4855 | ||
4856 | *headp = head; | |
4857 | *tailp = tail; | |
4858 | } | |
4859 | ||
4860 | /* Delete line notes from bb. Save them so they can be later restored | |
4861 | (in restore_line_notes ()). */ | |
4862 | ||
4863 | static void | |
4864 | rm_line_notes (bb) | |
4865 | int bb; | |
4866 | { | |
4867 | rtx next_tail; | |
4868 | rtx tail; | |
4869 | rtx head; | |
4870 | rtx insn; | |
4871 | ||
4872 | get_block_head_tail (bb, &head, &tail); | |
4873 | ||
4874 | if (head == tail | |
4875 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
4876 | return; | |
4877 | ||
4878 | next_tail = NEXT_INSN (tail); | |
4879 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4880 | { | |
4881 | rtx prev; | |
4882 | ||
4883 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4884 | This is needed to keep the debugger from | |
4885 | getting completely deranged. */ | |
4886 | if (GET_CODE (insn) == NOTE) | |
4887 | { | |
4888 | prev = insn; | |
4889 | insn = unlink_line_notes (insn, next_tail); | |
4890 | ||
4891 | if (prev == tail) | |
4892 | abort (); | |
4893 | if (prev == head) | |
4894 | abort (); | |
4895 | if (insn == next_tail) | |
4896 | abort (); | |
4897 | } | |
4898 | } | |
4899 | } | |
4900 | ||
4901 | /* Save line number notes for each insn in bb. */ | |
4902 | ||
4903 | static void | |
4904 | save_line_notes (bb) | |
4905 | int bb; | |
4906 | { | |
4907 | rtx head, tail; | |
4908 | rtx next_tail; | |
4909 | ||
4910 | /* We must use the true line number for the first insn in the block | |
4911 | that was computed and saved at the start of this pass. We can't | |
4912 | use the current line number, because scheduling of the previous | |
4913 | block may have changed the current line number. */ | |
4914 | ||
4915 | rtx line = line_note_head[BB_TO_BLOCK (bb)]; | |
4916 | rtx insn; | |
4917 | ||
4918 | get_block_head_tail (bb, &head, &tail); | |
4919 | next_tail = NEXT_INSN (tail); | |
4920 | ||
3b413743 | 4921 | for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb)); |
8c660648 JL |
4922 | insn != next_tail; |
4923 | insn = NEXT_INSN (insn)) | |
4924 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4925 | line = insn; | |
4926 | else | |
4927 | LINE_NOTE (insn) = line; | |
4928 | } | |
4929 | ||
4930 | ||
4931 | /* After bb was scheduled, insert line notes into the insns list. */ | |
4932 | ||
4933 | static void | |
4934 | restore_line_notes (bb) | |
4935 | int bb; | |
4936 | { | |
4937 | rtx line, note, prev, new; | |
4938 | int added_notes = 0; | |
4939 | int b; | |
4940 | rtx head, next_tail, insn; | |
4941 | ||
4942 | b = BB_TO_BLOCK (bb); | |
4943 | ||
3b413743 RH |
4944 | head = BLOCK_HEAD (b); |
4945 | next_tail = NEXT_INSN (BLOCK_END (b)); | |
8c660648 JL |
4946 | |
4947 | /* Determine the current line-number. We want to know the current | |
4948 | line number of the first insn of the block here, in case it is | |
4949 | different from the true line number that was saved earlier. If | |
4950 | different, then we need a line number note before the first insn | |
4951 | of this block. If it happens to be the same, then we don't want to | |
4952 | emit another line number note here. */ | |
4953 | for (line = head; line; line = PREV_INSN (line)) | |
4954 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) | |
4955 | break; | |
4956 | ||
4957 | /* Walk the insns keeping track of the current line-number and inserting | |
4958 | the line-number notes as needed. */ | |
4959 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4960 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4961 | line = insn; | |
4962 | /* This used to emit line number notes before every non-deleted note. | |
4963 | However, this confuses a debugger, because line notes not separated | |
4964 | by real instructions all end up at the same address. I can find no | |
4965 | use for line number notes before other notes, so none are emitted. */ | |
4966 | else if (GET_CODE (insn) != NOTE | |
4967 | && (note = LINE_NOTE (insn)) != 0 | |
4968 | && note != line | |
4969 | && (line == 0 | |
4970 | || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line) | |
4971 | || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line))) | |
4972 | { | |
4973 | line = note; | |
4974 | prev = PREV_INSN (insn); | |
4975 | if (LINE_NOTE (note)) | |
4976 | { | |
4977 | /* Re-use the original line-number note. */ | |
4978 | LINE_NOTE (note) = 0; | |
4979 | PREV_INSN (note) = prev; | |
4980 | NEXT_INSN (prev) = note; | |
4981 | PREV_INSN (insn) = note; | |
4982 | NEXT_INSN (note) = insn; | |
4983 | } | |
4984 | else | |
4985 | { | |
4986 | added_notes++; | |
4987 | new = emit_note_after (NOTE_LINE_NUMBER (note), prev); | |
4988 | NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note); | |
4989 | RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note); | |
4990 | } | |
4991 | } | |
4992 | if (sched_verbose && added_notes) | |
4993 | fprintf (dump, ";; added %d line-number notes\n", added_notes); | |
4994 | } | |
4995 | ||
4996 | /* After scheduling the function, delete redundant line notes from the | |
4997 | insns list. */ | |
4998 | ||
4999 | static void | |
5000 | rm_redundant_line_notes () | |
5001 | { | |
5002 | rtx line = 0; | |
5003 | rtx insn = get_insns (); | |
5004 | int active_insn = 0; | |
5005 | int notes = 0; | |
5006 | ||
5007 | /* Walk the insns deleting redundant line-number notes. Many of these | |
5008 | are already present. The remainder tend to occur at basic | |
5009 | block boundaries. */ | |
5010 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
5011 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
5012 | { | |
5013 | /* If there are no active insns following, INSN is redundant. */ | |
5014 | if (active_insn == 0) | |
5015 | { | |
5016 | notes++; | |
5017 | NOTE_SOURCE_FILE (insn) = 0; | |
5018 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
5019 | } | |
5020 | /* If the line number is unchanged, LINE is redundant. */ | |
5021 | else if (line | |
5022 | && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn) | |
5023 | && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn)) | |
5024 | { | |
5025 | notes++; | |
5026 | NOTE_SOURCE_FILE (line) = 0; | |
5027 | NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED; | |
5028 | line = insn; | |
5029 | } | |
5030 | else | |
5031 | line = insn; | |
5032 | active_insn = 0; | |
5033 | } | |
5034 | else if (!((GET_CODE (insn) == NOTE | |
5035 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) | |
5036 | || (GET_CODE (insn) == INSN | |
5037 | && (GET_CODE (PATTERN (insn)) == USE | |
5038 | || GET_CODE (PATTERN (insn)) == CLOBBER)))) | |
5039 | active_insn++; | |
5040 | ||
5041 | if (sched_verbose && notes) | |
5042 | fprintf (dump, ";; deleted %d line-number notes\n", notes); | |
5043 | } | |
5044 | ||
5045 | /* Delete notes between head and tail and put them in the chain | |
5046 | of notes ended by NOTE_LIST. */ | |
5047 | ||
5048 | static void | |
5049 | rm_other_notes (head, tail) | |
5050 | rtx head; | |
5051 | rtx tail; | |
5052 | { | |
5053 | rtx next_tail; | |
5054 | rtx insn; | |
5055 | ||
5056 | if (head == tail | |
5057 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
5058 | return; | |
5059 | ||
5060 | next_tail = NEXT_INSN (tail); | |
5061 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5062 | { | |
5063 | rtx prev; | |
5064 | ||
5065 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
5066 | This is needed to keep the debugger from | |
5067 | getting completely deranged. */ | |
5068 | if (GET_CODE (insn) == NOTE) | |
5069 | { | |
5070 | prev = insn; | |
5071 | ||
5072 | insn = unlink_other_notes (insn, next_tail); | |
5073 | ||
5074 | if (prev == tail) | |
5075 | abort (); | |
5076 | if (prev == head) | |
5077 | abort (); | |
5078 | if (insn == next_tail) | |
5079 | abort (); | |
5080 | } | |
5081 | } | |
5082 | } | |
5083 | ||
5084 | /* Constructor for `sometimes' data structure. */ | |
5085 | ||
5086 | static int | |
5087 | new_sometimes_live (regs_sometimes_live, regno, sometimes_max) | |
5088 | struct sometimes *regs_sometimes_live; | |
5089 | int regno; | |
5090 | int sometimes_max; | |
5091 | { | |
5092 | register struct sometimes *p; | |
5093 | ||
5094 | /* There should never be a register greater than max_regno here. If there | |
5095 | is, it means that a define_split has created a new pseudo reg. This | |
5096 | is not allowed, since there will not be flow info available for any | |
5097 | new register, so catch the error here. */ | |
5098 | if (regno >= max_regno) | |
5099 | abort (); | |
5100 | ||
5101 | p = ®s_sometimes_live[sometimes_max]; | |
5102 | p->regno = regno; | |
5103 | p->live_length = 0; | |
5104 | p->calls_crossed = 0; | |
5105 | sometimes_max++; | |
5106 | return sometimes_max; | |
5107 | } | |
5108 | ||
5109 | /* Count lengths of all regs we are currently tracking, | |
5110 | and find new registers no longer live. */ | |
5111 | ||
5112 | static void | |
5113 | finish_sometimes_live (regs_sometimes_live, sometimes_max) | |
5114 | struct sometimes *regs_sometimes_live; | |
5115 | int sometimes_max; | |
5116 | { | |
5117 | int i; | |
5118 | ||
5119 | for (i = 0; i < sometimes_max; i++) | |
5120 | { | |
5121 | register struct sometimes *p = ®s_sometimes_live[i]; | |
5122 | int regno = p->regno; | |
5123 | ||
5124 | sched_reg_live_length[regno] += p->live_length; | |
5125 | sched_reg_n_calls_crossed[regno] += p->calls_crossed; | |
5126 | } | |
5127 | } | |
5128 | ||
63de6c74 | 5129 | /* Functions for computation of registers live/usage info. */ |
8c660648 | 5130 | |
e881bb1b | 5131 | /* It is assumed that prior to scheduling BASIC_BLOCK (b)->global_live_at_start |
8c660648 JL |
5132 | contains the registers that are alive at the entry to b. |
5133 | ||
5134 | Two passes follow: The first pass is performed before the scheduling | |
5135 | of a region. It scans each block of the region forward, computing | |
5136 | the set of registers alive at the end of the basic block and | |
5137 | discard REG_DEAD notes (done by find_pre_sched_live ()). | |
5138 | ||
5139 | The second path is invoked after scheduling all region blocks. | |
5140 | It scans each block of the region backward, a block being traversed | |
5141 | only after its succesors in the region. When the set of registers | |
5142 | live at the end of a basic block may be changed by the scheduling | |
5143 | (this may happen for multiple blocks region), it is computed as | |
5144 | the union of the registers live at the start of its succesors. | |
5145 | The last-use information is updated by inserting REG_DEAD notes. | |
5146 | (done by find_post_sched_live ()) */ | |
5147 | ||
5148 | /* Scan all the insns to be scheduled, removing register death notes. | |
5149 | Register death notes end up in DEAD_NOTES. | |
5150 | Recreate the register life information for the end of this basic | |
5151 | block. */ | |
5152 | ||
5153 | static void | |
5154 | find_pre_sched_live (bb) | |
5155 | int bb; | |
5156 | { | |
5157 | rtx insn, next_tail, head, tail; | |
5158 | int b = BB_TO_BLOCK (bb); | |
5159 | ||
5160 | get_block_head_tail (bb, &head, &tail); | |
e881bb1b | 5161 | COPY_REG_SET (bb_live_regs, BASIC_BLOCK (b)->global_live_at_start); |
8c660648 JL |
5162 | next_tail = NEXT_INSN (tail); |
5163 | ||
5164 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5165 | { | |
5166 | rtx prev, next, link; | |
5167 | int reg_weight = 0; | |
5168 | ||
5169 | /* Handle register life information. */ | |
5170 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
5171 | { | |
5172 | /* See if the register gets born here. */ | |
5173 | /* We must check for registers being born before we check for | |
5174 | registers dying. It is possible for a register to be born and | |
5175 | die in the same insn, e.g. reading from a volatile memory | |
5176 | location into an otherwise unused register. Such a register | |
5177 | must be marked as dead after this insn. */ | |
5178 | if (GET_CODE (PATTERN (insn)) == SET | |
5179 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
5180 | { | |
5835e573 | 5181 | sched_note_set (PATTERN (insn), 0); |
8c660648 JL |
5182 | reg_weight++; |
5183 | } | |
5184 | ||
5185 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
5186 | { | |
5187 | int j; | |
5188 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5189 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
5190 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
5191 | { | |
5835e573 | 5192 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0); |
8c660648 JL |
5193 | reg_weight++; |
5194 | } | |
5195 | ||
5196 | /* ??? This code is obsolete and should be deleted. It | |
5197 | is harmless though, so we will leave it in for now. */ | |
5198 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5199 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE) | |
5835e573 | 5200 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0); |
8c660648 JL |
5201 | } |
5202 | ||
5203 | /* Each call cobbers (makes live) all call-clobbered regs | |
5204 | that are not global or fixed. Note that the function-value | |
5205 | reg is a call_clobbered reg. */ | |
5206 | if (GET_CODE (insn) == CALL_INSN) | |
5207 | { | |
5208 | int j; | |
5209 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
5210 | if (call_used_regs[j] && !global_regs[j] | |
5211 | && ! fixed_regs[j]) | |
5212 | { | |
5213 | SET_REGNO_REG_SET (bb_live_regs, j); | |
8c660648 JL |
5214 | } |
5215 | } | |
5216 | ||
5217 | /* Need to know what registers this insn kills. */ | |
5218 | for (prev = 0, link = REG_NOTES (insn); link; link = next) | |
5219 | { | |
5220 | next = XEXP (link, 1); | |
5221 | if ((REG_NOTE_KIND (link) == REG_DEAD | |
5222 | || REG_NOTE_KIND (link) == REG_UNUSED) | |
5223 | /* Verify that the REG_NOTE has a valid value. */ | |
5224 | && GET_CODE (XEXP (link, 0)) == REG) | |
5225 | { | |
5226 | register int regno = REGNO (XEXP (link, 0)); | |
5227 | ||
5228 | reg_weight--; | |
5229 | ||
5230 | /* Only unlink REG_DEAD notes; leave REG_UNUSED notes | |
5231 | alone. */ | |
5232 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
5233 | { | |
5234 | if (prev) | |
5235 | XEXP (prev, 1) = next; | |
5236 | else | |
5237 | REG_NOTES (insn) = next; | |
5238 | XEXP (link, 1) = dead_notes; | |
5239 | dead_notes = link; | |
5240 | } | |
5241 | else | |
5242 | prev = link; | |
5243 | ||
5244 | if (regno < FIRST_PSEUDO_REGISTER) | |
5245 | { | |
5246 | int j = HARD_REGNO_NREGS (regno, | |
5247 | GET_MODE (XEXP (link, 0))); | |
5248 | while (--j >= 0) | |
5249 | { | |
5250 | CLEAR_REGNO_REG_SET (bb_live_regs, regno+j); | |
5251 | } | |
5252 | } | |
5253 | else | |
5254 | { | |
5255 | CLEAR_REGNO_REG_SET (bb_live_regs, regno); | |
5256 | } | |
5257 | } | |
5258 | else | |
5259 | prev = link; | |
5260 | } | |
5261 | } | |
5262 | ||
5263 | INSN_REG_WEIGHT (insn) = reg_weight; | |
5264 | } | |
5265 | } | |
5266 | ||
5267 | /* Update register life and usage information for block bb | |
5268 | after scheduling. Put register dead notes back in the code. */ | |
5269 | ||
5270 | static void | |
5271 | find_post_sched_live (bb) | |
5272 | int bb; | |
5273 | { | |
5274 | int sometimes_max; | |
5275 | int j, i; | |
5276 | int b; | |
5277 | rtx insn; | |
5278 | rtx head, tail, prev_head, next_tail; | |
5279 | ||
5280 | register struct sometimes *regs_sometimes_live; | |
5281 | ||
5282 | b = BB_TO_BLOCK (bb); | |
5283 | ||
63de6c74 | 5284 | /* Compute live regs at the end of bb as a function of its successors. */ |
8c660648 JL |
5285 | if (current_nr_blocks > 1) |
5286 | { | |
5287 | int e; | |
5288 | int first_edge; | |
5289 | ||
5290 | first_edge = e = OUT_EDGES (b); | |
5291 | CLEAR_REG_SET (bb_live_regs); | |
5292 | ||
5293 | if (e) | |
5294 | do | |
5295 | { | |
5296 | int b_succ; | |
5297 | ||
5298 | b_succ = TO_BLOCK (e); | |
e881bb1b RH |
5299 | IOR_REG_SET (bb_live_regs, |
5300 | BASIC_BLOCK (b_succ)->global_live_at_start); | |
8c660648 JL |
5301 | e = NEXT_OUT (e); |
5302 | } | |
5303 | while (e != first_edge); | |
5304 | } | |
5305 | ||
5306 | get_block_head_tail (bb, &head, &tail); | |
5307 | next_tail = NEXT_INSN (tail); | |
5308 | prev_head = PREV_INSN (head); | |
5309 | ||
7eea6443 JL |
5310 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, i, |
5311 | { | |
5312 | sched_reg_basic_block[i] = REG_BLOCK_GLOBAL; | |
5313 | }); | |
8c660648 | 5314 | |
63de6c74 | 5315 | /* If the block is empty, same regs are alive at its end and its start. |
8c660648 JL |
5316 | since this is not guaranteed after interblock scheduling, make sure they |
5317 | are truly identical. */ | |
5318 | if (NEXT_INSN (prev_head) == tail | |
5319 | && (GET_RTX_CLASS (GET_CODE (tail)) != 'i')) | |
5320 | { | |
5321 | if (current_nr_blocks > 1) | |
e881bb1b | 5322 | COPY_REG_SET (BASIC_BLOCK (b)->global_live_at_start, bb_live_regs); |
8c660648 JL |
5323 | |
5324 | return; | |
5325 | } | |
5326 | ||
5327 | b = BB_TO_BLOCK (bb); | |
5328 | current_block_num = b; | |
5329 | ||
5330 | /* Keep track of register lives. */ | |
5331 | old_live_regs = ALLOCA_REG_SET (); | |
5332 | regs_sometimes_live | |
5333 | = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes)); | |
5334 | sometimes_max = 0; | |
5335 | ||
63de6c74 | 5336 | /* Initiate "sometimes" data, starting with registers live at end. */ |
8c660648 JL |
5337 | sometimes_max = 0; |
5338 | COPY_REG_SET (old_live_regs, bb_live_regs); | |
5339 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, 0, j, | |
5340 | { | |
5341 | sometimes_max | |
5342 | = new_sometimes_live (regs_sometimes_live, | |
5343 | j, sometimes_max); | |
5344 | }); | |
5345 | ||
63de6c74 | 5346 | /* Scan insns back, computing regs live info. */ |
8c660648 JL |
5347 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) |
5348 | { | |
5349 | /* First we kill registers set by this insn, and then we | |
5350 | make registers used by this insn live. This is the opposite | |
5351 | order used above because we are traversing the instructions | |
5352 | backwards. */ | |
5353 | ||
5354 | /* Strictly speaking, we should scan REG_UNUSED notes and make | |
5355 | every register mentioned there live, however, we will just | |
5356 | kill them again immediately below, so there doesn't seem to | |
5357 | be any reason why we bother to do this. */ | |
5358 | ||
5359 | /* See if this is the last notice we must take of a register. */ | |
5360 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5361 | continue; | |
5362 | ||
5363 | if (GET_CODE (PATTERN (insn)) == SET | |
5364 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
5835e573 | 5365 | sched_note_set (PATTERN (insn), 1); |
8c660648 JL |
5366 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
5367 | { | |
5368 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5369 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
5370 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
5835e573 | 5371 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 1); |
8c660648 JL |
5372 | } |
5373 | ||
5374 | /* This code keeps life analysis information up to date. */ | |
5375 | if (GET_CODE (insn) == CALL_INSN) | |
5376 | { | |
5377 | register struct sometimes *p; | |
5378 | ||
5379 | /* A call kills all call used registers that are not | |
5380 | global or fixed, except for those mentioned in the call | |
5381 | pattern which will be made live again later. */ | |
5382 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5383 | if (call_used_regs[i] && ! global_regs[i] | |
5384 | && ! fixed_regs[i]) | |
5385 | { | |
5386 | CLEAR_REGNO_REG_SET (bb_live_regs, i); | |
8c660648 JL |
5387 | } |
5388 | ||
5389 | /* Regs live at the time of a call instruction must not | |
5390 | go in a register clobbered by calls. Record this for | |
5391 | all regs now live. Note that insns which are born or | |
5392 | die in a call do not cross a call, so this must be done | |
5393 | after the killings (above) and before the births | |
5394 | (below). */ | |
5395 | p = regs_sometimes_live; | |
5396 | for (i = 0; i < sometimes_max; i++, p++) | |
5397 | if (REGNO_REG_SET_P (bb_live_regs, p->regno)) | |
5398 | p->calls_crossed += 1; | |
5399 | } | |
5400 | ||
5401 | /* Make every register used live, and add REG_DEAD notes for | |
5402 | registers which were not live before we started. */ | |
5403 | attach_deaths_insn (insn); | |
5404 | ||
5405 | /* Find registers now made live by that instruction. */ | |
5406 | EXECUTE_IF_AND_COMPL_IN_REG_SET (bb_live_regs, old_live_regs, 0, j, | |
5407 | { | |
5408 | sometimes_max | |
5409 | = new_sometimes_live (regs_sometimes_live, | |
5410 | j, sometimes_max); | |
5411 | }); | |
5412 | IOR_REG_SET (old_live_regs, bb_live_regs); | |
5413 | ||
5414 | /* Count lengths of all regs we are worrying about now, | |
5415 | and handle registers no longer live. */ | |
5416 | ||
5417 | for (i = 0; i < sometimes_max; i++) | |
5418 | { | |
5419 | register struct sometimes *p = ®s_sometimes_live[i]; | |
5420 | int regno = p->regno; | |
5421 | ||
5422 | p->live_length += 1; | |
5423 | ||
5424 | if (!REGNO_REG_SET_P (bb_live_regs, regno)) | |
5425 | { | |
5426 | /* This is the end of one of this register's lifetime | |
5427 | segments. Save the lifetime info collected so far, | |
5428 | and clear its bit in the old_live_regs entry. */ | |
5429 | sched_reg_live_length[regno] += p->live_length; | |
5430 | sched_reg_n_calls_crossed[regno] += p->calls_crossed; | |
5431 | CLEAR_REGNO_REG_SET (old_live_regs, p->regno); | |
5432 | ||
5433 | /* Delete the reg_sometimes_live entry for this reg by | |
5434 | copying the last entry over top of it. */ | |
5435 | *p = regs_sometimes_live[--sometimes_max]; | |
5436 | /* ...and decrement i so that this newly copied entry | |
5437 | will be processed. */ | |
5438 | i--; | |
5439 | } | |
5440 | } | |
5441 | } | |
5442 | ||
5443 | finish_sometimes_live (regs_sometimes_live, sometimes_max); | |
5444 | ||
e881bb1b | 5445 | /* In interblock scheduling, global_live_at_start may have changed. */ |
8c660648 | 5446 | if (current_nr_blocks > 1) |
e881bb1b | 5447 | COPY_REG_SET (BASIC_BLOCK (b)->global_live_at_start, bb_live_regs); |
8c660648 | 5448 | |
f187056f JL |
5449 | |
5450 | FREE_REG_SET (old_live_regs); | |
8c660648 JL |
5451 | } /* find_post_sched_live */ |
5452 | ||
5453 | /* After scheduling the subroutine, restore information about uses of | |
5454 | registers. */ | |
5455 | ||
5456 | static void | |
5457 | update_reg_usage () | |
5458 | { | |
5459 | int regno; | |
5460 | ||
5461 | if (n_basic_blocks > 0) | |
7eea6443 JL |
5462 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, regno, |
5463 | { | |
5464 | sched_reg_basic_block[regno] | |
5465 | = REG_BLOCK_GLOBAL; | |
5466 | }); | |
8c660648 JL |
5467 | |
5468 | for (regno = 0; regno < max_regno; regno++) | |
5469 | if (sched_reg_live_length[regno]) | |
5470 | { | |
5471 | if (sched_verbose) | |
5472 | { | |
5473 | if (REG_LIVE_LENGTH (regno) > sched_reg_live_length[regno]) | |
5474 | fprintf (dump, | |
5475 | ";; register %d life shortened from %d to %d\n", | |
5476 | regno, REG_LIVE_LENGTH (regno), | |
5477 | sched_reg_live_length[regno]); | |
5478 | /* Negative values are special; don't overwrite the current | |
5479 | reg_live_length value if it is negative. */ | |
5480 | else if (REG_LIVE_LENGTH (regno) < sched_reg_live_length[regno] | |
5481 | && REG_LIVE_LENGTH (regno) >= 0) | |
5482 | fprintf (dump, | |
5483 | ";; register %d life extended from %d to %d\n", | |
5484 | regno, REG_LIVE_LENGTH (regno), | |
5485 | sched_reg_live_length[regno]); | |
5486 | ||
5487 | if (!REG_N_CALLS_CROSSED (regno) | |
5488 | && sched_reg_n_calls_crossed[regno]) | |
5489 | fprintf (dump, | |
5490 | ";; register %d now crosses calls\n", regno); | |
5491 | else if (REG_N_CALLS_CROSSED (regno) | |
5492 | && !sched_reg_n_calls_crossed[regno] | |
5493 | && REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL) | |
5494 | fprintf (dump, | |
5495 | ";; register %d no longer crosses calls\n", regno); | |
5496 | ||
5497 | if (REG_BASIC_BLOCK (regno) != sched_reg_basic_block[regno] | |
5498 | && sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN | |
5499 | && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN) | |
5500 | fprintf (dump, | |
5501 | ";; register %d changed basic block from %d to %d\n", | |
5502 | regno, REG_BASIC_BLOCK(regno), | |
5503 | sched_reg_basic_block[regno]); | |
5504 | ||
5505 | } | |
5506 | /* Negative values are special; don't overwrite the current | |
5507 | reg_live_length value if it is negative. */ | |
5508 | if (REG_LIVE_LENGTH (regno) >= 0) | |
5509 | REG_LIVE_LENGTH (regno) = sched_reg_live_length[regno]; | |
5510 | ||
5511 | if (sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN | |
5512 | && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN) | |
5513 | REG_BASIC_BLOCK(regno) = sched_reg_basic_block[regno]; | |
5514 | ||
5515 | /* We can't change the value of reg_n_calls_crossed to zero for | |
5516 | pseudos which are live in more than one block. | |
5517 | ||
5518 | This is because combine might have made an optimization which | |
e881bb1b | 5519 | invalidated global_live_at_start and reg_n_calls_crossed, |
8c660648 JL |
5520 | but it does not update them. If we update reg_n_calls_crossed |
5521 | here, the two variables are now inconsistent, and this might | |
5522 | confuse the caller-save code into saving a register that doesn't | |
5523 | need to be saved. This is only a problem when we zero calls | |
5524 | crossed for a pseudo live in multiple basic blocks. | |
5525 | ||
5526 | Alternatively, we could try to correctly update basic block live | |
5527 | at start here in sched, but that seems complicated. | |
5528 | ||
63de6c74 MH |
5529 | Note: it is possible that a global register became local, |
5530 | as result of interblock motion, but will remain marked as a | |
5531 | global register. */ | |
8c660648 JL |
5532 | if (sched_reg_n_calls_crossed[regno] |
5533 | || REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL) | |
5534 | REG_N_CALLS_CROSSED (regno) = sched_reg_n_calls_crossed[regno]; | |
5535 | ||
5536 | } | |
5537 | } | |
5538 | ||
63de6c74 | 5539 | /* Scheduling clock, modified in schedule_block() and queue_to_ready (). */ |
8c660648 JL |
5540 | static int clock_var; |
5541 | ||
5542 | /* Move insns that became ready to fire from queue to ready list. */ | |
5543 | ||
5544 | static int | |
5545 | queue_to_ready (ready, n_ready) | |
5546 | rtx ready[]; | |
5547 | int n_ready; | |
5548 | { | |
5549 | rtx insn; | |
5550 | rtx link; | |
5551 | ||
5552 | q_ptr = NEXT_Q (q_ptr); | |
5553 | ||
5554 | /* Add all pending insns that can be scheduled without stalls to the | |
5555 | ready list. */ | |
5556 | for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1)) | |
5557 | { | |
5558 | ||
5559 | insn = XEXP (link, 0); | |
5560 | q_size -= 1; | |
5561 | ||
5562 | if (sched_verbose >= 2) | |
5563 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
5564 | ||
5565 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
5566 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
5567 | ||
5568 | ready[n_ready++] = insn; | |
5569 | if (sched_verbose >= 2) | |
5570 | fprintf (dump, "moving to ready without stalls\n"); | |
5571 | } | |
5572 | insn_queue[q_ptr] = 0; | |
5573 | ||
5574 | /* If there are no ready insns, stall until one is ready and add all | |
5575 | of the pending insns at that point to the ready list. */ | |
5576 | if (n_ready == 0) | |
5577 | { | |
5578 | register int stalls; | |
5579 | ||
5580 | for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++) | |
5581 | { | |
5582 | if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])) | |
5583 | { | |
5584 | for (; link; link = XEXP (link, 1)) | |
5585 | { | |
5586 | insn = XEXP (link, 0); | |
5587 | q_size -= 1; | |
5588 | ||
5589 | if (sched_verbose >= 2) | |
5590 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
5591 | ||
5592 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
5593 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
5594 | ||
5595 | ready[n_ready++] = insn; | |
5596 | if (sched_verbose >= 2) | |
5597 | fprintf (dump, "moving to ready with %d stalls\n", stalls); | |
5598 | } | |
5599 | insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0; | |
5600 | ||
5601 | if (n_ready) | |
5602 | break; | |
5603 | } | |
5604 | } | |
5605 | ||
5606 | if (sched_verbose && stalls) | |
5607 | visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls); | |
5608 | q_ptr = NEXT_Q_AFTER (q_ptr, stalls); | |
5609 | clock_var += stalls; | |
5610 | } | |
5611 | return n_ready; | |
5612 | } | |
5613 | ||
63de6c74 | 5614 | /* Print the ready list for debugging purposes. Callable from debugger. */ |
8c660648 | 5615 | |
9a8b0889 | 5616 | static void |
8c660648 JL |
5617 | debug_ready_list (ready, n_ready) |
5618 | rtx ready[]; | |
5619 | int n_ready; | |
5620 | { | |
5621 | int i; | |
5622 | ||
5623 | for (i = 0; i < n_ready; i++) | |
5624 | { | |
5625 | fprintf (dump, " %d", INSN_UID (ready[i])); | |
5626 | if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb) | |
5627 | fprintf (dump, "/b%d", INSN_BLOCK (ready[i])); | |
5628 | } | |
5629 | fprintf (dump, "\n"); | |
5630 | } | |
5631 | ||
5632 | /* Print names of units on which insn can/should execute, for debugging. */ | |
5633 | ||
5634 | static void | |
5635 | insn_print_units (insn) | |
5636 | rtx insn; | |
5637 | { | |
5638 | int i; | |
5639 | int unit = insn_unit (insn); | |
5640 | ||
5641 | if (unit == -1) | |
5642 | fprintf (dump, "none"); | |
5643 | else if (unit >= 0) | |
5644 | fprintf (dump, "%s", function_units[unit].name); | |
5645 | else | |
5646 | { | |
5647 | fprintf (dump, "["); | |
5648 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
5649 | if (unit & 1) | |
5650 | { | |
5651 | fprintf (dump, "%s", function_units[i].name); | |
5652 | if (unit != 1) | |
5653 | fprintf (dump, " "); | |
5654 | } | |
5655 | fprintf (dump, "]"); | |
5656 | } | |
5657 | } | |
5658 | ||
5659 | /* MAX_VISUAL_LINES is the maximum number of lines in visualization table | |
5660 | of a basic block. If more lines are needed, table is splitted to two. | |
5661 | n_visual_lines is the number of lines printed so far for a block. | |
5662 | visual_tbl contains the block visualization info. | |
5663 | vis_no_unit holds insns in a cycle that are not mapped to any unit. */ | |
5664 | #define MAX_VISUAL_LINES 100 | |
5665 | #define INSN_LEN 30 | |
5666 | int n_visual_lines; | |
5667 | char *visual_tbl; | |
5668 | int n_vis_no_unit; | |
5669 | rtx vis_no_unit[10]; | |
5670 | ||
63de6c74 | 5671 | /* Finds units that are in use in this fuction. Required only |
8c660648 JL |
5672 | for visualization. */ |
5673 | ||
5674 | static void | |
5675 | init_target_units () | |
5676 | { | |
5677 | rtx insn; | |
5678 | int unit; | |
5679 | ||
5680 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
5681 | { | |
5682 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5683 | continue; | |
5684 | ||
5685 | unit = insn_unit (insn); | |
5686 | ||
5687 | if (unit < 0) | |
5688 | target_units |= ~unit; | |
5689 | else | |
5690 | target_units |= (1 << unit); | |
5691 | } | |
5692 | } | |
5693 | ||
63de6c74 | 5694 | /* Return the length of the visualization table. */ |
8c660648 JL |
5695 | |
5696 | static int | |
5697 | get_visual_tbl_length () | |
5698 | { | |
5699 | int unit, i; | |
5700 | int n, n1; | |
5701 | char *s; | |
5702 | ||
63de6c74 | 5703 | /* Compute length of one field in line. */ |
8f04d345 | 5704 | s = (char *) alloca (INSN_LEN + 6); |
8c660648 JL |
5705 | sprintf (s, " %33s", "uname"); |
5706 | n1 = strlen (s); | |
5707 | ||
63de6c74 | 5708 | /* Compute length of one line. */ |
8c660648 JL |
5709 | n = strlen (";; "); |
5710 | n += n1; | |
5711 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5712 | if (function_units[unit].bitmask & target_units) | |
5713 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5714 | n += n1; | |
5715 | n += n1; | |
5716 | n += strlen ("\n") + 2; | |
5717 | ||
63de6c74 | 5718 | /* Compute length of visualization string. */ |
8c660648 JL |
5719 | return (MAX_VISUAL_LINES * n); |
5720 | } | |
5721 | ||
63de6c74 | 5722 | /* Init block visualization debugging info. */ |
8c660648 JL |
5723 | |
5724 | static void | |
5725 | init_block_visualization () | |
5726 | { | |
5727 | strcpy (visual_tbl, ""); | |
5728 | n_visual_lines = 0; | |
5729 | n_vis_no_unit = 0; | |
5730 | } | |
5731 | ||
5732 | #define BUF_LEN 256 | |
5733 | ||
459b3825 MM |
5734 | static char * |
5735 | safe_concat (buf, cur, str) | |
5736 | char *buf; | |
5737 | char *cur; | |
5f06c983 | 5738 | const char *str; |
459b3825 | 5739 | { |
63de6c74 | 5740 | char *end = buf + BUF_LEN - 2; /* Leave room for null. */ |
459b3825 MM |
5741 | int c; |
5742 | ||
5743 | if (cur > end) | |
5744 | { | |
5745 | *end = '\0'; | |
5746 | return end; | |
5747 | } | |
5748 | ||
5749 | while (cur < end && (c = *str++) != '\0') | |
5750 | *cur++ = c; | |
5751 | ||
5752 | *cur = '\0'; | |
5753 | return cur; | |
5754 | } | |
5755 | ||
63de6c74 MH |
5756 | /* This recognizes rtx, I classified as expressions. These are always |
5757 | represent some action on values or results of other expression, that | |
5758 | may be stored in objects representing values. */ | |
8c660648 JL |
5759 | |
5760 | static void | |
5761 | print_exp (buf, x, verbose) | |
5762 | char *buf; | |
5763 | rtx x; | |
5764 | int verbose; | |
5765 | { | |
459b3825 | 5766 | char tmp[BUF_LEN]; |
5f06c983 | 5767 | const char *st[4]; |
459b3825 | 5768 | char *cur = buf; |
5f06c983 KG |
5769 | const char *fun = (char *)0; |
5770 | const char *sep; | |
459b3825 MM |
5771 | rtx op[4]; |
5772 | int i; | |
5773 | ||
5774 | for (i = 0; i < 4; i++) | |
5775 | { | |
5776 | st[i] = (char *)0; | |
5777 | op[i] = NULL_RTX; | |
5778 | } | |
8c660648 JL |
5779 | |
5780 | switch (GET_CODE (x)) | |
5781 | { | |
5782 | case PLUS: | |
459b3825 | 5783 | op[0] = XEXP (x, 0); |
f4b94256 RH |
5784 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
5785 | && INTVAL (XEXP (x, 1)) < 0) | |
5786 | { | |
5787 | st[1] = "-"; | |
5788 | op[1] = GEN_INT (-INTVAL (XEXP (x, 1))); | |
5789 | } | |
5790 | else | |
5791 | { | |
5792 | st[1] = "+"; | |
5793 | op[1] = XEXP (x, 1); | |
5794 | } | |
8c660648 JL |
5795 | break; |
5796 | case LO_SUM: | |
459b3825 MM |
5797 | op[0] = XEXP (x, 0); |
5798 | st[1] = "+low("; | |
5799 | op[1] = XEXP (x, 1); | |
5800 | st[2] = ")"; | |
8c660648 JL |
5801 | break; |
5802 | case MINUS: | |
459b3825 MM |
5803 | op[0] = XEXP (x, 0); |
5804 | st[1] = "-"; | |
5805 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5806 | break; |
5807 | case COMPARE: | |
459b3825 MM |
5808 | fun = "cmp"; |
5809 | op[0] = XEXP (x, 0); | |
5810 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5811 | break; |
5812 | case NEG: | |
459b3825 MM |
5813 | st[0] = "-"; |
5814 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5815 | break; |
5816 | case MULT: | |
459b3825 MM |
5817 | op[0] = XEXP (x, 0); |
5818 | st[1] = "*"; | |
5819 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5820 | break; |
5821 | case DIV: | |
459b3825 MM |
5822 | op[0] = XEXP (x, 0); |
5823 | st[1] = "/"; | |
5824 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5825 | break; |
5826 | case UDIV: | |
459b3825 MM |
5827 | fun = "udiv"; |
5828 | op[0] = XEXP (x, 0); | |
5829 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5830 | break; |
5831 | case MOD: | |
459b3825 MM |
5832 | op[0] = XEXP (x, 0); |
5833 | st[1] = "%"; | |
5834 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5835 | break; |
5836 | case UMOD: | |
459b3825 MM |
5837 | fun = "umod"; |
5838 | op[0] = XEXP (x, 0); | |
5839 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5840 | break; |
5841 | case SMIN: | |
459b3825 MM |
5842 | fun = "smin"; |
5843 | op[0] = XEXP (x, 0); | |
5844 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5845 | break; |
5846 | case SMAX: | |
459b3825 MM |
5847 | fun = "smax"; |
5848 | op[0] = XEXP (x, 0); | |
5849 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5850 | break; |
5851 | case UMIN: | |
459b3825 MM |
5852 | fun = "umin"; |
5853 | op[0] = XEXP (x, 0); | |
5854 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5855 | break; |
5856 | case UMAX: | |
459b3825 MM |
5857 | fun = "umax"; |
5858 | op[0] = XEXP (x, 0); | |
5859 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5860 | break; |
5861 | case NOT: | |
459b3825 MM |
5862 | st[0] = "!"; |
5863 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5864 | break; |
5865 | case AND: | |
459b3825 MM |
5866 | op[0] = XEXP (x, 0); |
5867 | st[1] = "&"; | |
5868 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5869 | break; |
5870 | case IOR: | |
459b3825 MM |
5871 | op[0] = XEXP (x, 0); |
5872 | st[1] = "|"; | |
5873 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5874 | break; |
5875 | case XOR: | |
459b3825 MM |
5876 | op[0] = XEXP (x, 0); |
5877 | st[1] = "^"; | |
5878 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5879 | break; |
5880 | case ASHIFT: | |
459b3825 MM |
5881 | op[0] = XEXP (x, 0); |
5882 | st[1] = "<<"; | |
5883 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5884 | break; |
5885 | case LSHIFTRT: | |
459b3825 MM |
5886 | op[0] = XEXP (x, 0); |
5887 | st[1] = " 0>>"; | |
5888 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5889 | break; |
5890 | case ASHIFTRT: | |
459b3825 MM |
5891 | op[0] = XEXP (x, 0); |
5892 | st[1] = ">>"; | |
5893 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5894 | break; |
5895 | case ROTATE: | |
459b3825 MM |
5896 | op[0] = XEXP (x, 0); |
5897 | st[1] = "<-<"; | |
5898 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5899 | break; |
5900 | case ROTATERT: | |
459b3825 MM |
5901 | op[0] = XEXP (x, 0); |
5902 | st[1] = ">->"; | |
5903 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5904 | break; |
5905 | case ABS: | |
459b3825 MM |
5906 | fun = "abs"; |
5907 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5908 | break; |
5909 | case SQRT: | |
459b3825 MM |
5910 | fun = "sqrt"; |
5911 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5912 | break; |
5913 | case FFS: | |
459b3825 MM |
5914 | fun = "ffs"; |
5915 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5916 | break; |
5917 | case EQ: | |
459b3825 MM |
5918 | op[0] = XEXP (x, 0); |
5919 | st[1] = "=="; | |
5920 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5921 | break; |
5922 | case NE: | |
459b3825 MM |
5923 | op[0] = XEXP (x, 0); |
5924 | st[1] = "!="; | |
5925 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5926 | break; |
5927 | case GT: | |
459b3825 MM |
5928 | op[0] = XEXP (x, 0); |
5929 | st[1] = ">"; | |
5930 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5931 | break; |
5932 | case GTU: | |
459b3825 MM |
5933 | fun = "gtu"; |
5934 | op[0] = XEXP (x, 0); | |
5935 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5936 | break; |
5937 | case LT: | |
459b3825 MM |
5938 | op[0] = XEXP (x, 0); |
5939 | st[1] = "<"; | |
5940 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5941 | break; |
5942 | case LTU: | |
459b3825 MM |
5943 | fun = "ltu"; |
5944 | op[0] = XEXP (x, 0); | |
5945 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5946 | break; |
5947 | case GE: | |
459b3825 MM |
5948 | op[0] = XEXP (x, 0); |
5949 | st[1] = ">="; | |
5950 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5951 | break; |
5952 | case GEU: | |
459b3825 MM |
5953 | fun = "geu"; |
5954 | op[0] = XEXP (x, 0); | |
5955 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5956 | break; |
5957 | case LE: | |
459b3825 MM |
5958 | op[0] = XEXP (x, 0); |
5959 | st[1] = "<="; | |
5960 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5961 | break; |
5962 | case LEU: | |
459b3825 MM |
5963 | fun = "leu"; |
5964 | op[0] = XEXP (x, 0); | |
5965 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5966 | break; |
5967 | case SIGN_EXTRACT: | |
459b3825 MM |
5968 | fun = (verbose) ? "sign_extract" : "sxt"; |
5969 | op[0] = XEXP (x, 0); | |
5970 | op[1] = XEXP (x, 1); | |
5971 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5972 | break; |
5973 | case ZERO_EXTRACT: | |
459b3825 MM |
5974 | fun = (verbose) ? "zero_extract" : "zxt"; |
5975 | op[0] = XEXP (x, 0); | |
5976 | op[1] = XEXP (x, 1); | |
5977 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5978 | break; |
5979 | case SIGN_EXTEND: | |
459b3825 MM |
5980 | fun = (verbose) ? "sign_extend" : "sxn"; |
5981 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5982 | break; |
5983 | case ZERO_EXTEND: | |
459b3825 MM |
5984 | fun = (verbose) ? "zero_extend" : "zxn"; |
5985 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5986 | break; |
5987 | case FLOAT_EXTEND: | |
459b3825 MM |
5988 | fun = (verbose) ? "float_extend" : "fxn"; |
5989 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5990 | break; |
5991 | case TRUNCATE: | |
459b3825 MM |
5992 | fun = (verbose) ? "trunc" : "trn"; |
5993 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5994 | break; |
5995 | case FLOAT_TRUNCATE: | |
459b3825 MM |
5996 | fun = (verbose) ? "float_trunc" : "ftr"; |
5997 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5998 | break; |
5999 | case FLOAT: | |
459b3825 MM |
6000 | fun = (verbose) ? "float" : "flt"; |
6001 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6002 | break; |
6003 | case UNSIGNED_FLOAT: | |
459b3825 MM |
6004 | fun = (verbose) ? "uns_float" : "ufl"; |
6005 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6006 | break; |
6007 | case FIX: | |
459b3825 MM |
6008 | fun = "fix"; |
6009 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6010 | break; |
6011 | case UNSIGNED_FIX: | |
459b3825 MM |
6012 | fun = (verbose) ? "uns_fix" : "ufx"; |
6013 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6014 | break; |
6015 | case PRE_DEC: | |
459b3825 MM |
6016 | st[0] = "--"; |
6017 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6018 | break; |
6019 | case PRE_INC: | |
459b3825 MM |
6020 | st[0] = "++"; |
6021 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6022 | break; |
6023 | case POST_DEC: | |
459b3825 MM |
6024 | op[0] = XEXP (x, 0); |
6025 | st[1] = "--"; | |
8c660648 JL |
6026 | break; |
6027 | case POST_INC: | |
459b3825 MM |
6028 | op[0] = XEXP (x, 0); |
6029 | st[1] = "++"; | |
8c660648 JL |
6030 | break; |
6031 | case CALL: | |
459b3825 MM |
6032 | st[0] = "call "; |
6033 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6034 | if (verbose) |
6035 | { | |
459b3825 MM |
6036 | st[1] = " argc:"; |
6037 | op[1] = XEXP (x, 1); | |
8c660648 | 6038 | } |
8c660648 JL |
6039 | break; |
6040 | case IF_THEN_ELSE: | |
459b3825 MM |
6041 | st[0] = "{("; |
6042 | op[0] = XEXP (x, 0); | |
6043 | st[1] = ")?"; | |
6044 | op[1] = XEXP (x, 1); | |
6045 | st[2] = ":"; | |
6046 | op[2] = XEXP (x, 2); | |
6047 | st[3] = "}"; | |
8c660648 JL |
6048 | break; |
6049 | case TRAP_IF: | |
459b3825 MM |
6050 | fun = "trap_if"; |
6051 | op[0] = TRAP_CONDITION (x); | |
8c660648 JL |
6052 | break; |
6053 | case UNSPEC: | |
8c660648 JL |
6054 | case UNSPEC_VOLATILE: |
6055 | { | |
459b3825 MM |
6056 | cur = safe_concat (buf, cur, "unspec"); |
6057 | if (GET_CODE (x) == UNSPEC_VOLATILE) | |
6058 | cur = safe_concat (buf, cur, "/v"); | |
6059 | cur = safe_concat (buf, cur, "["); | |
6060 | sep = ""; | |
8c660648 JL |
6061 | for (i = 0; i < XVECLEN (x, 0); i++) |
6062 | { | |
459b3825 MM |
6063 | print_pattern (tmp, XVECEXP (x, 0, i), verbose); |
6064 | cur = safe_concat (buf, cur, sep); | |
6065 | cur = safe_concat (buf, cur, tmp); | |
6066 | sep = ","; | |
8c660648 | 6067 | } |
459b3825 MM |
6068 | cur = safe_concat (buf, cur, "] "); |
6069 | sprintf (tmp, "%d", XINT (x, 1)); | |
6070 | cur = safe_concat (buf, cur, tmp); | |
8c660648 JL |
6071 | } |
6072 | break; | |
6073 | default: | |
63de6c74 | 6074 | /* If (verbose) debug_rtx (x); */ |
53c0919d | 6075 | st[0] = GET_RTX_NAME (GET_CODE (x)); |
459b3825 MM |
6076 | break; |
6077 | } | |
6078 | ||
63de6c74 | 6079 | /* Print this as a function? */ |
459b3825 MM |
6080 | if (fun) |
6081 | { | |
6082 | cur = safe_concat (buf, cur, fun); | |
6083 | cur = safe_concat (buf, cur, "("); | |
6084 | } | |
6085 | ||
6086 | for (i = 0; i < 4; i++) | |
6087 | { | |
6088 | if (st[i]) | |
6089 | cur = safe_concat (buf, cur, st[i]); | |
6090 | ||
6091 | if (op[i]) | |
6092 | { | |
6093 | if (fun && i != 0) | |
6094 | cur = safe_concat (buf, cur, ","); | |
6095 | ||
6096 | print_value (tmp, op[i], verbose); | |
6097 | cur = safe_concat (buf, cur, tmp); | |
6098 | } | |
8c660648 | 6099 | } |
459b3825 MM |
6100 | |
6101 | if (fun) | |
6102 | cur = safe_concat (buf, cur, ")"); | |
6103 | } /* print_exp */ | |
8c660648 | 6104 | |
63de6c74 MH |
6105 | /* Prints rtxes, I customly classified as values. They're constants, |
6106 | registers, labels, symbols and memory accesses. */ | |
8c660648 JL |
6107 | |
6108 | static void | |
6109 | print_value (buf, x, verbose) | |
6110 | char *buf; | |
6111 | rtx x; | |
6112 | int verbose; | |
6113 | { | |
6114 | char t[BUF_LEN]; | |
459b3825 | 6115 | char *cur = buf; |
8c660648 JL |
6116 | |
6117 | switch (GET_CODE (x)) | |
6118 | { | |
6119 | case CONST_INT: | |
f4b94256 | 6120 | sprintf (t, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); |
459b3825 | 6121 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
6122 | break; |
6123 | case CONST_DOUBLE: | |
459b3825 MM |
6124 | sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); |
6125 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
6126 | break; |
6127 | case CONST_STRING: | |
459b3825 MM |
6128 | cur = safe_concat (buf, cur, "\""); |
6129 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
6130 | cur = safe_concat (buf, cur, "\""); | |
8c660648 JL |
6131 | break; |
6132 | case SYMBOL_REF: | |
459b3825 MM |
6133 | cur = safe_concat (buf, cur, "`"); |
6134 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
6135 | cur = safe_concat (buf, cur, "'"); | |
8c660648 JL |
6136 | break; |
6137 | case LABEL_REF: | |
459b3825 MM |
6138 | sprintf (t, "L%d", INSN_UID (XEXP (x, 0))); |
6139 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
6140 | break; |
6141 | case CONST: | |
459b3825 MM |
6142 | print_value (t, XEXP (x, 0), verbose); |
6143 | cur = safe_concat (buf, cur, "const("); | |
6144 | cur = safe_concat (buf, cur, t); | |
6145 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
6146 | break; |
6147 | case HIGH: | |
459b3825 MM |
6148 | print_value (t, XEXP (x, 0), verbose); |
6149 | cur = safe_concat (buf, cur, "high("); | |
6150 | cur = safe_concat (buf, cur, t); | |
6151 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
6152 | break; |
6153 | case REG: | |
459b3825 MM |
6154 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) |
6155 | { | |
6156 | int c = reg_names[ REGNO (x) ][0]; | |
6157 | if (c >= '0' && c <= '9') | |
6158 | cur = safe_concat (buf, cur, "%"); | |
6159 | ||
6160 | cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]); | |
6161 | } | |
8c660648 | 6162 | else |
459b3825 MM |
6163 | { |
6164 | sprintf (t, "r%d", REGNO (x)); | |
6165 | cur = safe_concat (buf, cur, t); | |
6166 | } | |
8c660648 JL |
6167 | break; |
6168 | case SUBREG: | |
459b3825 MM |
6169 | print_value (t, SUBREG_REG (x), verbose); |
6170 | cur = safe_concat (buf, cur, t); | |
6b879bcc | 6171 | sprintf (t, "#%d", SUBREG_WORD (x)); |
459b3825 | 6172 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
6173 | break; |
6174 | case SCRATCH: | |
459b3825 | 6175 | cur = safe_concat (buf, cur, "scratch"); |
8c660648 JL |
6176 | break; |
6177 | case CC0: | |
459b3825 | 6178 | cur = safe_concat (buf, cur, "cc0"); |
8c660648 JL |
6179 | break; |
6180 | case PC: | |
459b3825 | 6181 | cur = safe_concat (buf, cur, "pc"); |
8c660648 JL |
6182 | break; |
6183 | case MEM: | |
6184 | print_value (t, XEXP (x, 0), verbose); | |
459b3825 MM |
6185 | cur = safe_concat (buf, cur, "["); |
6186 | cur = safe_concat (buf, cur, t); | |
6187 | cur = safe_concat (buf, cur, "]"); | |
8c660648 JL |
6188 | break; |
6189 | default: | |
459b3825 MM |
6190 | print_exp (t, x, verbose); |
6191 | cur = safe_concat (buf, cur, t); | |
6192 | break; | |
8c660648 JL |
6193 | } |
6194 | } /* print_value */ | |
6195 | ||
63de6c74 | 6196 | /* The next step in insn detalization, its pattern recognition. */ |
8c660648 JL |
6197 | |
6198 | static void | |
6199 | print_pattern (buf, x, verbose) | |
6200 | char *buf; | |
6201 | rtx x; | |
6202 | int verbose; | |
6203 | { | |
6204 | char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN]; | |
6205 | ||
6206 | switch (GET_CODE (x)) | |
6207 | { | |
6208 | case SET: | |
6209 | print_value (t1, SET_DEST (x), verbose); | |
6210 | print_value (t2, SET_SRC (x), verbose); | |
6211 | sprintf (buf, "%s=%s", t1, t2); | |
6212 | break; | |
6213 | case RETURN: | |
6214 | sprintf (buf, "return"); | |
6215 | break; | |
6216 | case CALL: | |
6217 | print_exp (buf, x, verbose); | |
6218 | break; | |
6219 | case CLOBBER: | |
6220 | print_value (t1, XEXP (x, 0), verbose); | |
6221 | sprintf (buf, "clobber %s", t1); | |
6222 | break; | |
6223 | case USE: | |
6224 | print_value (t1, XEXP (x, 0), verbose); | |
6225 | sprintf (buf, "use %s", t1); | |
6226 | break; | |
6227 | case PARALLEL: | |
6228 | { | |
6229 | int i; | |
6230 | ||
6231 | sprintf (t1, "{"); | |
6232 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6233 | { | |
6234 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6235 | sprintf (t3, "%s%s;", t1, t2); | |
6236 | strcpy (t1, t3); | |
6237 | } | |
6238 | sprintf (buf, "%s}", t1); | |
6239 | } | |
6240 | break; | |
6241 | case SEQUENCE: | |
6242 | { | |
6243 | int i; | |
6244 | ||
6245 | sprintf (t1, "%%{"); | |
6246 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6247 | { | |
6248 | print_insn (t2, XVECEXP (x, 0, i), verbose); | |
6249 | sprintf (t3, "%s%s;", t1, t2); | |
6250 | strcpy (t1, t3); | |
6251 | } | |
6252 | sprintf (buf, "%s%%}", t1); | |
6253 | } | |
6254 | break; | |
6255 | case ASM_INPUT: | |
c4fa3460 | 6256 | sprintf (buf, "asm {%s}", XSTR (x, 0)); |
8c660648 JL |
6257 | break; |
6258 | case ADDR_VEC: | |
6259 | break; | |
6260 | case ADDR_DIFF_VEC: | |
6261 | print_value (buf, XEXP (x, 0), verbose); | |
6262 | break; | |
6263 | case TRAP_IF: | |
6264 | print_value (t1, TRAP_CONDITION (x), verbose); | |
6265 | sprintf (buf, "trap_if %s", t1); | |
6266 | break; | |
6267 | case UNSPEC: | |
6268 | { | |
6269 | int i; | |
6270 | ||
6271 | sprintf (t1, "unspec{"); | |
6272 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6273 | { | |
6274 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6275 | sprintf (t3, "%s%s;", t1, t2); | |
6276 | strcpy (t1, t3); | |
6277 | } | |
6278 | sprintf (buf, "%s}", t1); | |
6279 | } | |
6280 | break; | |
6281 | case UNSPEC_VOLATILE: | |
6282 | { | |
6283 | int i; | |
6284 | ||
6285 | sprintf (t1, "unspec/v{"); | |
6286 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6287 | { | |
6288 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6289 | sprintf (t3, "%s%s;", t1, t2); | |
6290 | strcpy (t1, t3); | |
6291 | } | |
6292 | sprintf (buf, "%s}", t1); | |
6293 | } | |
6294 | break; | |
6295 | default: | |
6296 | print_value (buf, x, verbose); | |
6297 | } | |
6298 | } /* print_pattern */ | |
6299 | ||
6300 | /* This is the main function in rtl visualization mechanism. It | |
6301 | accepts an rtx and tries to recognize it as an insn, then prints it | |
63de6c74 MH |
6302 | properly in human readable form, resembling assembler mnemonics. |
6303 | For every insn it prints its UID and BB the insn belongs too. | |
6304 | (Probably the last "option" should be extended somehow, since it | |
6305 | depends now on sched.c inner variables ...) */ | |
8c660648 JL |
6306 | |
6307 | static void | |
6308 | print_insn (buf, x, verbose) | |
6309 | char *buf; | |
6310 | rtx x; | |
6311 | int verbose; | |
6312 | { | |
6313 | char t[BUF_LEN]; | |
6314 | rtx insn = x; | |
6315 | ||
6316 | switch (GET_CODE (x)) | |
6317 | { | |
6318 | case INSN: | |
6319 | print_pattern (t, PATTERN (x), verbose); | |
6320 | if (verbose) | |
6321 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x), | |
6322 | INSN_UID (x), t); | |
6323 | else | |
6324 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
6325 | break; | |
6326 | case JUMP_INSN: | |
6327 | print_pattern (t, PATTERN (x), verbose); | |
6328 | if (verbose) | |
6329 | sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x), | |
6330 | INSN_UID (x), t); | |
6331 | else | |
6332 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
6333 | break; | |
6334 | case CALL_INSN: | |
6335 | x = PATTERN (insn); | |
6336 | if (GET_CODE (x) == PARALLEL) | |
6337 | { | |
6338 | x = XVECEXP (x, 0, 0); | |
6339 | print_pattern (t, x, verbose); | |
6340 | } | |
6341 | else | |
6342 | strcpy (t, "call <...>"); | |
6343 | if (verbose) | |
6344 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn), | |
6345 | INSN_UID (insn), t); | |
6346 | else | |
6347 | sprintf (buf, "%-4d %s", INSN_UID (insn), t); | |
6348 | break; | |
6349 | case CODE_LABEL: | |
6350 | sprintf (buf, "L%d:", INSN_UID (x)); | |
6351 | break; | |
6352 | case BARRIER: | |
6353 | sprintf (buf, "i% 4d: barrier", INSN_UID (x)); | |
6354 | break; | |
6355 | case NOTE: | |
6356 | if (NOTE_LINE_NUMBER (x) > 0) | |
6357 | sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x), | |
6358 | NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x)); | |
6359 | else | |
6360 | sprintf (buf, "%4d %s", INSN_UID (x), | |
6361 | GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x))); | |
6362 | break; | |
6363 | default: | |
6364 | if (verbose) | |
6365 | { | |
6366 | sprintf (buf, "Not an INSN at all\n"); | |
6367 | debug_rtx (x); | |
6368 | } | |
6369 | else | |
6370 | sprintf (buf, "i%-4d <What?>", INSN_UID (x)); | |
6371 | } | |
6372 | } /* print_insn */ | |
6373 | ||
63de6c74 | 6374 | /* Print visualization debugging info. */ |
8c660648 JL |
6375 | |
6376 | static void | |
6377 | print_block_visualization (b, s) | |
6378 | int b; | |
5f06c983 | 6379 | const char *s; |
8c660648 JL |
6380 | { |
6381 | int unit, i; | |
8c660648 | 6382 | |
63de6c74 | 6383 | /* Print header. */ |
8c660648 JL |
6384 | fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s); |
6385 | ||
63de6c74 | 6386 | /* Print names of units. */ |
2f308fec | 6387 | fprintf (dump, ";; %-8s", "clock"); |
8c660648 JL |
6388 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) |
6389 | if (function_units[unit].bitmask & target_units) | |
6390 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
2f308fec RH |
6391 | fprintf (dump, " %-33s", function_units[unit].name); |
6392 | fprintf (dump, " %-8s\n", "no-unit"); | |
6393 | ||
6394 | fprintf (dump, ";; %-8s", "====="); | |
6395 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
6396 | if (function_units[unit].bitmask & target_units) | |
6397 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
6398 | fprintf (dump, " %-33s", "=============================="); | |
6399 | fprintf (dump, " %-8s\n", "======="); | |
8c660648 | 6400 | |
63de6c74 | 6401 | /* Print insns in each cycle. */ |
8c660648 JL |
6402 | fprintf (dump, "%s\n", visual_tbl); |
6403 | } | |
6404 | ||
63de6c74 | 6405 | /* Print insns in the 'no_unit' column of visualization. */ |
8c660648 JL |
6406 | |
6407 | static void | |
6408 | visualize_no_unit (insn) | |
6409 | rtx insn; | |
6410 | { | |
6411 | vis_no_unit[n_vis_no_unit] = insn; | |
6412 | n_vis_no_unit++; | |
6413 | } | |
6414 | ||
6415 | /* Print insns scheduled in clock, for visualization. */ | |
6416 | ||
6417 | static void | |
6418 | visualize_scheduled_insns (b, clock) | |
6419 | int b, clock; | |
6420 | { | |
6421 | int i, unit; | |
6422 | ||
63de6c74 | 6423 | /* If no more room, split table into two. */ |
8c660648 JL |
6424 | if (n_visual_lines >= MAX_VISUAL_LINES) |
6425 | { | |
6426 | print_block_visualization (b, "(incomplete)"); | |
6427 | init_block_visualization (); | |
6428 | } | |
6429 | ||
6430 | n_visual_lines++; | |
6431 | ||
6432 | sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock); | |
6433 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
6434 | if (function_units[unit].bitmask & target_units) | |
6435 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
6436 | { | |
6437 | int instance = unit + i * FUNCTION_UNITS_SIZE; | |
6438 | rtx insn = unit_last_insn[instance]; | |
6439 | ||
63de6c74 | 6440 | /* Print insns that still keep the unit busy. */ |
8c660648 JL |
6441 | if (insn && |
6442 | actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
6443 | { | |
6444 | char str[BUF_LEN]; | |
6445 | print_insn (str, insn, 0); | |
6446 | str[INSN_LEN] = '\0'; | |
6447 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str); | |
6448 | } | |
6449 | else | |
6450 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------"); | |
6451 | } | |
6452 | ||
63de6c74 | 6453 | /* Print insns that are not assigned to any unit. */ |
8c660648 JL |
6454 | for (i = 0; i < n_vis_no_unit; i++) |
6455 | sprintf (visual_tbl + strlen (visual_tbl), " %-8d", | |
6456 | INSN_UID (vis_no_unit[i])); | |
6457 | n_vis_no_unit = 0; | |
6458 | ||
6459 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
6460 | } | |
6461 | ||
63de6c74 | 6462 | /* Print stalled cycles. */ |
8c660648 JL |
6463 | |
6464 | static void | |
6465 | visualize_stall_cycles (b, stalls) | |
6466 | int b, stalls; | |
6467 | { | |
6468 | int i; | |
6469 | ||
63de6c74 | 6470 | /* If no more room, split table into two. */ |
8c660648 JL |
6471 | if (n_visual_lines >= MAX_VISUAL_LINES) |
6472 | { | |
6473 | print_block_visualization (b, "(incomplete)"); | |
6474 | init_block_visualization (); | |
6475 | } | |
6476 | ||
6477 | n_visual_lines++; | |
6478 | ||
6479 | sprintf (visual_tbl + strlen (visual_tbl), ";; "); | |
6480 | for (i = 0; i < stalls; i++) | |
6481 | sprintf (visual_tbl + strlen (visual_tbl), "."); | |
6482 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
6483 | } | |
6484 | ||
63de6c74 | 6485 | /* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */ |
8c660648 JL |
6486 | |
6487 | static rtx | |
6488 | move_insn1 (insn, last) | |
6489 | rtx insn, last; | |
6490 | { | |
6491 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
6492 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
6493 | ||
6494 | NEXT_INSN (insn) = NEXT_INSN (last); | |
6495 | PREV_INSN (NEXT_INSN (last)) = insn; | |
6496 | ||
6497 | NEXT_INSN (last) = insn; | |
6498 | PREV_INSN (insn) = last; | |
6499 | ||
6500 | return insn; | |
6501 | } | |
6502 | ||
6503 | /* Search INSN for fake REG_DEAD note pairs for NOTE_INSN_SETJMP, | |
6504 | NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into | |
6505 | NOTEs. The REG_DEAD note following first one is contains the saved | |
7bd41ea6 | 6506 | value for NOTE_BLOCK_NUMBER which is useful for |
8c660648 JL |
6507 | NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction |
6508 | output by the instruction scheduler. Return the new value of LAST. */ | |
6509 | ||
6510 | static rtx | |
6511 | reemit_notes (insn, last) | |
6512 | rtx insn; | |
6513 | rtx last; | |
6514 | { | |
6515 | rtx note, retval; | |
6516 | ||
6517 | retval = last; | |
6518 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
6519 | { | |
6520 | if (REG_NOTE_KIND (note) == REG_DEAD | |
6521 | && GET_CODE (XEXP (note, 0)) == CONST_INT) | |
6522 | { | |
6dfdecdb RH |
6523 | int note_type = INTVAL (XEXP (note, 0)); |
6524 | if (note_type == NOTE_INSN_SETJMP) | |
8c660648 | 6525 | { |
6dfdecdb | 6526 | retval = emit_note_after (NOTE_INSN_SETJMP, insn); |
8c660648 | 6527 | CONST_CALL_P (retval) = CONST_CALL_P (note); |
7bd41ea6 MM |
6528 | remove_note (insn, note); |
6529 | note = XEXP (note, 1); | |
8c660648 | 6530 | } |
6dfdecdb RH |
6531 | else if (note_type == NOTE_INSN_RANGE_START |
6532 | || note_type == NOTE_INSN_RANGE_END) | |
6533 | { | |
6534 | last = emit_note_before (note_type, last); | |
6535 | remove_note (insn, note); | |
6536 | note = XEXP (note, 1); | |
6537 | NOTE_RANGE_INFO (last) = XEXP (note, 0); | |
6538 | } | |
8c660648 JL |
6539 | else |
6540 | { | |
19699da4 | 6541 | last = emit_note_before (note_type, last); |
7bd41ea6 MM |
6542 | remove_note (insn, note); |
6543 | note = XEXP (note, 1); | |
1a4450c7 MM |
6544 | if (note_type == NOTE_INSN_EH_REGION_BEG |
6545 | || note_type == NOTE_INSN_EH_REGION_END) | |
7bd41ea6 | 6546 | NOTE_EH_HANDLER (last) = INTVAL (XEXP (note, 0)); |
8c660648 JL |
6547 | } |
6548 | remove_note (insn, note); | |
6549 | } | |
6550 | } | |
6551 | return retval; | |
6552 | } | |
6553 | ||
6554 | /* Move INSN, and all insns which should be issued before it, | |
c9e03727 JL |
6555 | due to SCHED_GROUP_P flag. Reemit notes if needed. |
6556 | ||
6557 | Return the last insn emitted by the scheduler, which is the | |
6558 | return value from the first call to reemit_notes. */ | |
8c660648 JL |
6559 | |
6560 | static rtx | |
6561 | move_insn (insn, last) | |
6562 | rtx insn, last; | |
6563 | { | |
c9e03727 | 6564 | rtx retval = NULL; |
8c660648 | 6565 | |
c9e03727 JL |
6566 | /* If INSN has SCHED_GROUP_P set, then issue it and any other |
6567 | insns with SCHED_GROUP_P set first. */ | |
8c660648 JL |
6568 | while (SCHED_GROUP_P (insn)) |
6569 | { | |
6570 | rtx prev = PREV_INSN (insn); | |
c9e03727 JL |
6571 | |
6572 | /* Move a SCHED_GROUP_P insn. */ | |
8c660648 | 6573 | move_insn1 (insn, last); |
c9e03727 JL |
6574 | /* If this is the first call to reemit_notes, then record |
6575 | its return value. */ | |
6576 | if (retval == NULL_RTX) | |
6577 | retval = reemit_notes (insn, insn); | |
6578 | else | |
6579 | reemit_notes (insn, insn); | |
8c660648 JL |
6580 | insn = prev; |
6581 | } | |
6582 | ||
c9e03727 | 6583 | /* Now move the first non SCHED_GROUP_P insn. */ |
8c660648 | 6584 | move_insn1 (insn, last); |
c9e03727 JL |
6585 | |
6586 | /* If this is the first call to reemit_notes, then record | |
6587 | its return value. */ | |
6588 | if (retval == NULL_RTX) | |
6589 | retval = reemit_notes (insn, insn); | |
6590 | else | |
6591 | reemit_notes (insn, insn); | |
6592 | ||
6593 | return retval; | |
8c660648 JL |
6594 | } |
6595 | ||
6596 | /* Return an insn which represents a SCHED_GROUP, which is | |
6597 | the last insn in the group. */ | |
6598 | ||
6599 | static rtx | |
6600 | group_leader (insn) | |
6601 | rtx insn; | |
6602 | { | |
6603 | rtx prev; | |
6604 | ||
6605 | do | |
6606 | { | |
6607 | prev = insn; | |
6608 | insn = next_nonnote_insn (insn); | |
6609 | } | |
6610 | while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL)); | |
6611 | ||
6612 | return prev; | |
6613 | } | |
6614 | ||
6615 | /* Use forward list scheduling to rearrange insns of block BB in region RGN, | |
6616 | possibly bringing insns from subsequent blocks in the same region. | |
6617 | Return number of insns scheduled. */ | |
6618 | ||
6619 | static int | |
5835e573 | 6620 | schedule_block (bb, rgn_n_insns) |
8c660648 | 6621 | int bb; |
8c660648 JL |
6622 | int rgn_n_insns; |
6623 | { | |
6624 | /* Local variables. */ | |
6625 | rtx insn, last; | |
6626 | rtx *ready; | |
8c660648 JL |
6627 | int n_ready = 0; |
6628 | int can_issue_more; | |
6629 | ||
63de6c74 | 6630 | /* Flow block of this bb. */ |
8c660648 JL |
6631 | int b = BB_TO_BLOCK (bb); |
6632 | ||
6633 | /* target_n_insns == number of insns in b before scheduling starts. | |
6634 | sched_target_n_insns == how many of b's insns were scheduled. | |
63de6c74 | 6635 | sched_n_insns == how many insns were scheduled in b. */ |
8c660648 JL |
6636 | int target_n_insns = 0; |
6637 | int sched_target_n_insns = 0; | |
6638 | int sched_n_insns = 0; | |
6639 | ||
6640 | #define NEED_NOTHING 0 | |
6641 | #define NEED_HEAD 1 | |
6642 | #define NEED_TAIL 2 | |
6643 | int new_needs; | |
6644 | ||
63de6c74 | 6645 | /* Head/tail info for this block. */ |
8c660648 JL |
6646 | rtx prev_head; |
6647 | rtx next_tail; | |
6648 | rtx head; | |
6649 | rtx tail; | |
6650 | int bb_src; | |
6651 | ||
484df988 JL |
6652 | /* We used to have code to avoid getting parameters moved from hard |
6653 | argument registers into pseudos. | |
8c660648 | 6654 | |
484df988 JL |
6655 | However, it was removed when it proved to be of marginal benefit |
6656 | and caused problems because schedule_block and compute_forward_dependences | |
6657 | had different notions of what the "head" insn was. */ | |
6658 | get_block_head_tail (bb, &head, &tail); | |
8c660648 | 6659 | |
1447b516 JL |
6660 | /* Interblock scheduling could have moved the original head insn from this |
6661 | block into a proceeding block. This may also cause schedule_block and | |
6662 | compute_forward_dependences to have different notions of what the | |
6663 | "head" insn was. | |
6664 | ||
6665 | If the interblock movement happened to make this block start with | |
6666 | some notes (LOOP, EH or SETJMP) before the first real insn, then | |
6667 | HEAD will have various special notes attached to it which must be | |
6668 | removed so that we don't end up with extra copies of the notes. */ | |
6669 | if (GET_RTX_CLASS (GET_CODE (head)) == 'i') | |
6670 | { | |
6671 | rtx note; | |
6672 | ||
6673 | for (note = REG_NOTES (head); note; note = XEXP (note, 1)) | |
6674 | if (REG_NOTE_KIND (note) == REG_DEAD | |
6675 | && GET_CODE (XEXP (note, 0)) == CONST_INT) | |
6676 | remove_note (head, note); | |
6677 | } | |
6678 | ||
8c660648 JL |
6679 | next_tail = NEXT_INSN (tail); |
6680 | prev_head = PREV_INSN (head); | |
6681 | ||
6682 | /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need | |
6683 | to schedule this block. */ | |
6684 | if (head == tail | |
6685 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6686 | return (sched_n_insns); | |
6687 | ||
63de6c74 | 6688 | /* Debug info. */ |
8c660648 JL |
6689 | if (sched_verbose) |
6690 | { | |
6691 | fprintf (dump, ";; ======================================================\n"); | |
6692 | fprintf (dump, | |
6693 | ";; -- basic block %d from %d to %d -- %s reload\n", | |
3b413743 | 6694 | b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)), |
8c660648 JL |
6695 | (reload_completed ? "after" : "before")); |
6696 | fprintf (dump, ";; ======================================================\n"); | |
8c660648 JL |
6697 | fprintf (dump, "\n"); |
6698 | ||
6699 | visual_tbl = (char *) alloca (get_visual_tbl_length ()); | |
6700 | init_block_visualization (); | |
6701 | } | |
6702 | ||
63de6c74 | 6703 | /* Remove remaining note insns from the block, save them in |
8c660648 JL |
6704 | note_list. These notes are restored at the end of |
6705 | schedule_block (). */ | |
6706 | note_list = 0; | |
6707 | rm_other_notes (head, tail); | |
6708 | ||
6709 | target_bb = bb; | |
6710 | ||
63de6c74 | 6711 | /* Prepare current target block info. */ |
8c660648 JL |
6712 | if (current_nr_blocks > 1) |
6713 | { | |
63de6c74 MH |
6714 | candidate_table = (candidate *) alloca (current_nr_blocks |
6715 | * sizeof (candidate)); | |
8c660648 JL |
6716 | |
6717 | bblst_last = 0; | |
6718 | /* ??? It is not clear why bblst_size is computed this way. The original | |
6719 | number was clearly too small as it resulted in compiler failures. | |
6720 | Multiplying by the original number by 2 (to account for update_bbs | |
6721 | members) seems to be a reasonable solution. */ | |
6722 | /* ??? Or perhaps there is a bug somewhere else in this file? */ | |
6723 | bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2; | |
6724 | bblst_table = (int *) alloca (bblst_size * sizeof (int)); | |
6725 | ||
6726 | bitlst_table_last = 0; | |
6727 | bitlst_table_size = rgn_nr_edges; | |
6728 | bitlst_table = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
6729 | ||
6730 | compute_trg_info (bb); | |
6731 | } | |
6732 | ||
6733 | clear_units (); | |
6734 | ||
63de6c74 | 6735 | /* Allocate the ready list. */ |
8c660648 JL |
6736 | ready = (rtx *) alloca ((rgn_n_insns + 1) * sizeof (rtx)); |
6737 | ||
6738 | /* Print debugging information. */ | |
6739 | if (sched_verbose >= 5) | |
6740 | debug_dependencies (); | |
6741 | ||
6742 | ||
6743 | /* Initialize ready list with all 'ready' insns in target block. | |
6744 | Count number of insns in the target block being scheduled. */ | |
6745 | n_ready = 0; | |
6746 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6747 | { | |
6748 | rtx next; | |
6749 | ||
6750 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6751 | continue; | |
6752 | next = NEXT_INSN (insn); | |
6753 | ||
6754 | if (INSN_DEP_COUNT (insn) == 0 | |
6755 | && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
6756 | ready[n_ready++] = insn; | |
6757 | if (!(SCHED_GROUP_P (insn))) | |
6758 | target_n_insns++; | |
6759 | } | |
6760 | ||
6761 | /* Add to ready list all 'ready' insns in valid source blocks. | |
6762 | For speculative insns, check-live, exception-free, and | |
6763 | issue-delay. */ | |
6764 | for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++) | |
6765 | if (IS_VALID (bb_src)) | |
6766 | { | |
6767 | rtx src_head; | |
6768 | rtx src_next_tail; | |
6769 | rtx tail, head; | |
6770 | ||
6771 | get_block_head_tail (bb_src, &head, &tail); | |
6772 | src_next_tail = NEXT_INSN (tail); | |
6773 | src_head = head; | |
6774 | ||
6775 | if (head == tail | |
6776 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6777 | continue; | |
6778 | ||
6779 | for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn)) | |
6780 | { | |
6781 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6782 | continue; | |
6783 | ||
6784 | if (!CANT_MOVE (insn) | |
6785 | && (!IS_SPECULATIVE_INSN (insn) | |
6786 | || (insn_issue_delay (insn) <= 3 | |
5835e573 | 6787 | && check_live (insn, bb_src) |
8c660648 JL |
6788 | && is_exception_free (insn, bb_src, target_bb)))) |
6789 | ||
6790 | { | |
6791 | rtx next; | |
6792 | ||
0d8b2ca1 RH |
6793 | /* Note that we havn't squirrled away the notes for |
6794 | blocks other than the current. So if this is a | |
6795 | speculative insn, NEXT might otherwise be a note. */ | |
6796 | next = next_nonnote_insn (insn); | |
8c660648 JL |
6797 | if (INSN_DEP_COUNT (insn) == 0 |
6798 | && (SCHED_GROUP_P (next) == 0 | |
6799 | || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
6800 | ready[n_ready++] = insn; | |
6801 | } | |
6802 | } | |
6803 | } | |
6804 | ||
e4da5f6d MM |
6805 | #ifdef MD_SCHED_INIT |
6806 | MD_SCHED_INIT (dump, sched_verbose); | |
6807 | #endif | |
6808 | ||
63de6c74 | 6809 | /* No insns scheduled in this block yet. */ |
8c660648 JL |
6810 | last_scheduled_insn = 0; |
6811 | ||
8c660648 JL |
6812 | /* Q_SIZE is the total number of insns in the queue. */ |
6813 | q_ptr = 0; | |
6814 | q_size = 0; | |
4bdc8810 | 6815 | last_clock_var = 0; |
8c660648 JL |
6816 | bzero ((char *) insn_queue, sizeof (insn_queue)); |
6817 | ||
197043f5 RH |
6818 | /* Start just before the beginning of time. */ |
6819 | clock_var = -1; | |
6820 | ||
8c660648 JL |
6821 | /* We start inserting insns after PREV_HEAD. */ |
6822 | last = prev_head; | |
6823 | ||
6824 | /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */ | |
3b413743 | 6825 | new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b) |
8c660648 | 6826 | ? NEED_HEAD : NEED_NOTHING); |
3b413743 | 6827 | if (PREV_INSN (next_tail) == BLOCK_END (b)) |
8c660648 JL |
6828 | new_needs |= NEED_TAIL; |
6829 | ||
63de6c74 | 6830 | /* Loop until all the insns in BB are scheduled. */ |
8c660648 JL |
6831 | while (sched_target_n_insns < target_n_insns) |
6832 | { | |
6833 | int b1; | |
6834 | ||
8c660648 JL |
6835 | clock_var++; |
6836 | ||
6837 | /* Add to the ready list all pending insns that can be issued now. | |
6838 | If there are no ready insns, increment clock until one | |
6839 | is ready and add all pending insns at that point to the ready | |
6840 | list. */ | |
6841 | n_ready = queue_to_ready (ready, n_ready); | |
6842 | ||
6843 | if (n_ready == 0) | |
6844 | abort (); | |
6845 | ||
6846 | if (sched_verbose >= 2) | |
6847 | { | |
6848 | fprintf (dump, ";;\t\tReady list after queue_to_ready: "); | |
6849 | debug_ready_list (ready, n_ready); | |
6850 | } | |
6851 | ||
197043f5 | 6852 | /* Sort the ready list based on priority. */ |
8c660648 | 6853 | SCHED_SORT (ready, n_ready); |
197043f5 RH |
6854 | |
6855 | /* Allow the target to reorder the list, typically for | |
6856 | better instruction bundling. */ | |
e4da5f6d | 6857 | #ifdef MD_SCHED_REORDER |
197043f5 RH |
6858 | MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var, |
6859 | can_issue_more); | |
6860 | #else | |
6861 | can_issue_more = issue_rate; | |
e4da5f6d | 6862 | #endif |
8c660648 JL |
6863 | |
6864 | if (sched_verbose) | |
6865 | { | |
47312d84 | 6866 | fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var); |
8c660648 JL |
6867 | debug_ready_list (ready, n_ready); |
6868 | } | |
6869 | ||
197043f5 RH |
6870 | /* Issue insns from ready list. */ |
6871 | while (n_ready != 0 && can_issue_more) | |
8c660648 | 6872 | { |
197043f5 RH |
6873 | /* Select and remove the insn from the ready list. */ |
6874 | rtx insn = ready[--n_ready]; | |
8c660648 JL |
6875 | int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0); |
6876 | ||
197043f5 | 6877 | if (cost >= 1) |
8c660648 JL |
6878 | { |
6879 | queue_insn (insn, cost); | |
197043f5 | 6880 | continue; |
8c660648 | 6881 | } |
4f64eaca | 6882 | |
197043f5 RH |
6883 | /* An interblock motion? */ |
6884 | if (INSN_BB (insn) != target_bb) | |
6885 | { | |
6886 | rtx temp; | |
8c660648 | 6887 | |
197043f5 RH |
6888 | if (IS_SPECULATIVE_INSN (insn)) |
6889 | { | |
6890 | if (!check_live (insn, INSN_BB (insn))) | |
6891 | continue; | |
6892 | update_live (insn, INSN_BB (insn)); | |
8c660648 | 6893 | |
197043f5 RH |
6894 | /* For speculative load, mark insns fed by it. */ |
6895 | if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn)) | |
6896 | set_spec_fed (insn); | |
8c660648 | 6897 | |
197043f5 RH |
6898 | nr_spec++; |
6899 | } | |
6900 | nr_inter++; | |
8c660648 | 6901 | |
197043f5 RH |
6902 | temp = insn; |
6903 | while (SCHED_GROUP_P (temp)) | |
6904 | temp = PREV_INSN (temp); | |
4f64eaca | 6905 | |
197043f5 RH |
6906 | /* Update source block boundaries. */ |
6907 | b1 = INSN_BLOCK (temp); | |
6908 | if (temp == BLOCK_HEAD (b1) | |
6909 | && insn == BLOCK_END (b1)) | |
6910 | { | |
6911 | /* We moved all the insns in the basic block. | |
6912 | Emit a note after the last insn and update the | |
6913 | begin/end boundaries to point to the note. */ | |
6914 | emit_note_after (NOTE_INSN_DELETED, insn); | |
6915 | BLOCK_END (b1) = NEXT_INSN (insn); | |
6916 | BLOCK_HEAD (b1) = NEXT_INSN (insn); | |
8c660648 | 6917 | } |
197043f5 | 6918 | else if (insn == BLOCK_END (b1)) |
8c660648 | 6919 | { |
197043f5 RH |
6920 | /* We took insns from the end of the basic block, |
6921 | so update the end of block boundary so that it | |
6922 | points to the first insn we did not move. */ | |
6923 | BLOCK_END (b1) = PREV_INSN (temp); | |
8c660648 | 6924 | } |
197043f5 RH |
6925 | else if (temp == BLOCK_HEAD (b1)) |
6926 | { | |
6927 | /* We took insns from the start of the basic block, | |
6928 | so update the start of block boundary so that | |
6929 | it points to the first insn we did not move. */ | |
6930 | BLOCK_HEAD (b1) = NEXT_INSN (insn); | |
6931 | } | |
6932 | } | |
6933 | else | |
6934 | { | |
6935 | /* In block motion. */ | |
6936 | sched_target_n_insns++; | |
6937 | } | |
8c660648 | 6938 | |
197043f5 RH |
6939 | last_scheduled_insn = insn; |
6940 | last = move_insn (insn, last); | |
6941 | sched_n_insns++; | |
8c660648 | 6942 | |
e4da5f6d | 6943 | #ifdef MD_SCHED_VARIABLE_ISSUE |
197043f5 RH |
6944 | MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, |
6945 | can_issue_more); | |
e4da5f6d | 6946 | #else |
197043f5 | 6947 | can_issue_more--; |
e4da5f6d | 6948 | #endif |
8c660648 | 6949 | |
197043f5 | 6950 | n_ready = schedule_insn (insn, ready, n_ready, clock_var); |
8c660648 | 6951 | |
197043f5 RH |
6952 | /* Close this block after scheduling its jump. */ |
6953 | if (GET_CODE (last_scheduled_insn) == JUMP_INSN) | |
6954 | break; | |
8c660648 JL |
6955 | } |
6956 | ||
197043f5 | 6957 | /* Debug info. */ |
8c660648 | 6958 | if (sched_verbose) |
197043f5 | 6959 | visualize_scheduled_insns (b, clock_var); |
8c660648 JL |
6960 | } |
6961 | ||
63de6c74 | 6962 | /* Debug info. */ |
8c660648 JL |
6963 | if (sched_verbose) |
6964 | { | |
6965 | fprintf (dump, ";;\tReady list (final): "); | |
6966 | debug_ready_list (ready, n_ready); | |
6967 | print_block_visualization (b, ""); | |
6968 | } | |
6969 | ||
6970 | /* Sanity check -- queue must be empty now. Meaningless if region has | |
cc132865 | 6971 | multiple bbs. */ |
8c660648 | 6972 | if (current_nr_blocks > 1) |
cc132865 JL |
6973 | if (!flag_schedule_interblock && q_size != 0) |
6974 | abort (); | |
8c660648 | 6975 | |
63de6c74 | 6976 | /* Update head/tail boundaries. */ |
8c660648 JL |
6977 | head = NEXT_INSN (prev_head); |
6978 | tail = last; | |
6979 | ||
8c660648 JL |
6980 | /* Restore-other-notes: NOTE_LIST is the end of a chain of notes |
6981 | previously found among the insns. Insert them at the beginning | |
6982 | of the insns. */ | |
6983 | if (note_list != 0) | |
6984 | { | |
6985 | rtx note_head = note_list; | |
6986 | ||
6987 | while (PREV_INSN (note_head)) | |
6988 | { | |
6989 | note_head = PREV_INSN (note_head); | |
6990 | } | |
6991 | ||
6992 | PREV_INSN (note_head) = PREV_INSN (head); | |
6993 | NEXT_INSN (PREV_INSN (head)) = note_head; | |
6994 | PREV_INSN (head) = note_list; | |
6995 | NEXT_INSN (note_list) = head; | |
6996 | head = note_head; | |
6997 | } | |
6998 | ||
63de6c74 | 6999 | /* Update target block boundaries. */ |
8c660648 | 7000 | if (new_needs & NEED_HEAD) |
3b413743 | 7001 | BLOCK_HEAD (b) = head; |
8c660648 JL |
7002 | |
7003 | if (new_needs & NEED_TAIL) | |
3b413743 | 7004 | BLOCK_END (b) = tail; |
8c660648 | 7005 | |
63de6c74 | 7006 | /* Debugging. */ |
8c660648 JL |
7007 | if (sched_verbose) |
7008 | { | |
7009 | fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n", | |
3b413743 | 7010 | clock_var, INSN_UID (BLOCK_HEAD (b))); |
8c660648 | 7011 | fprintf (dump, ";; new basic block end = %d\n\n", |
3b413743 | 7012 | INSN_UID (BLOCK_END (b))); |
8c660648 JL |
7013 | } |
7014 | ||
7015 | return (sched_n_insns); | |
7016 | } /* schedule_block () */ | |
7017 | \f | |
7018 | ||
63de6c74 | 7019 | /* Print the bit-set of registers, S, callable from debugger. */ |
8c660648 JL |
7020 | |
7021 | extern void | |
7022 | debug_reg_vector (s) | |
7023 | regset s; | |
7024 | { | |
7025 | int regno; | |
7026 | ||
7027 | EXECUTE_IF_SET_IN_REG_SET (s, 0, regno, | |
7028 | { | |
7029 | fprintf (dump, " %d", regno); | |
7030 | }); | |
7031 | ||
7032 | fprintf (dump, "\n"); | |
7033 | } | |
7034 | ||
7035 | /* Use the backward dependences from LOG_LINKS to build | |
7036 | forward dependences in INSN_DEPEND. */ | |
7037 | ||
7038 | static void | |
7039 | compute_block_forward_dependences (bb) | |
7040 | int bb; | |
7041 | { | |
7042 | rtx insn, link; | |
7043 | rtx tail, head; | |
7044 | rtx next_tail; | |
7045 | enum reg_note dep_type; | |
7046 | ||
7047 | get_block_head_tail (bb, &head, &tail); | |
7048 | next_tail = NEXT_INSN (tail); | |
7049 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7050 | { | |
7051 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
7052 | continue; | |
7053 | ||
7054 | insn = group_leader (insn); | |
7055 | ||
7056 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
7057 | { | |
7058 | rtx x = group_leader (XEXP (link, 0)); | |
7059 | rtx new_link; | |
7060 | ||
7061 | if (x != XEXP (link, 0)) | |
7062 | continue; | |
7063 | ||
63de6c74 | 7064 | /* Ignore dependences upon deleted insn. */ |
8c660648 JL |
7065 | if (GET_CODE (x) == NOTE || INSN_DELETED_P (x)) |
7066 | continue; | |
7067 | if (find_insn_list (insn, INSN_DEPEND (x))) | |
7068 | continue; | |
7069 | ||
ebb7b10b | 7070 | new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x)); |
8c660648 JL |
7071 | |
7072 | dep_type = REG_NOTE_KIND (link); | |
7073 | PUT_REG_NOTE_KIND (new_link, dep_type); | |
7074 | ||
8c660648 JL |
7075 | INSN_DEPEND (x) = new_link; |
7076 | INSN_DEP_COUNT (insn) += 1; | |
7077 | } | |
7078 | } | |
7079 | } | |
7080 | ||
7081 | /* Initialize variables for region data dependence analysis. | |
63de6c74 | 7082 | n_bbs is the number of region blocks. */ |
8c660648 | 7083 | |
6d3352d9 | 7084 | __inline static void |
8c660648 JL |
7085 | init_rgn_data_dependences (n_bbs) |
7086 | int n_bbs; | |
7087 | { | |
7088 | int bb; | |
7089 | ||
63de6c74 | 7090 | /* Variables for which one copy exists for each block. */ |
8c660648 JL |
7091 | bzero ((char *) bb_pending_read_insns, n_bbs * sizeof (rtx)); |
7092 | bzero ((char *) bb_pending_read_mems, n_bbs * sizeof (rtx)); | |
7093 | bzero ((char *) bb_pending_write_insns, n_bbs * sizeof (rtx)); | |
7094 | bzero ((char *) bb_pending_write_mems, n_bbs * sizeof (rtx)); | |
7095 | bzero ((char *) bb_pending_lists_length, n_bbs * sizeof (rtx)); | |
7096 | bzero ((char *) bb_last_pending_memory_flush, n_bbs * sizeof (rtx)); | |
7097 | bzero ((char *) bb_last_function_call, n_bbs * sizeof (rtx)); | |
7098 | bzero ((char *) bb_sched_before_next_call, n_bbs * sizeof (rtx)); | |
7099 | ||
7100 | /* Create an insn here so that we can hang dependencies off of it later. */ | |
7101 | for (bb = 0; bb < n_bbs; bb++) | |
7102 | { | |
7103 | bb_sched_before_next_call[bb] = | |
38a448ca RH |
7104 | gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
7105 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
7106 | LOG_LINKS (bb_sched_before_next_call[bb]) = 0; |
7107 | } | |
7108 | } | |
7109 | ||
63de6c74 MH |
7110 | /* Add dependences so that branches are scheduled to run last in their |
7111 | block. */ | |
8c660648 JL |
7112 | |
7113 | static void | |
7114 | add_branch_dependences (head, tail) | |
7115 | rtx head, tail; | |
7116 | { | |
7117 | ||
7118 | rtx insn, last; | |
7119 | ||
7120 | /* For all branches, calls, uses, and cc0 setters, force them to remain | |
7121 | in order at the end of the block by adding dependencies and giving | |
7122 | the last a high priority. There may be notes present, and prev_head | |
7123 | may also be a note. | |
7124 | ||
7125 | Branches must obviously remain at the end. Calls should remain at the | |
7126 | end since moving them results in worse register allocation. Uses remain | |
7127 | at the end to ensure proper register allocation. cc0 setters remaim | |
7128 | at the end because they can't be moved away from their cc0 user. */ | |
7129 | insn = tail; | |
7130 | last = 0; | |
7131 | while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
7132 | || (GET_CODE (insn) == INSN | |
7133 | && (GET_CODE (PATTERN (insn)) == USE | |
7134 | #ifdef HAVE_cc0 | |
7135 | || sets_cc0_p (PATTERN (insn)) | |
7136 | #endif | |
7137 | )) | |
7138 | || GET_CODE (insn) == NOTE) | |
7139 | { | |
7140 | if (GET_CODE (insn) != NOTE) | |
7141 | { | |
7142 | if (last != 0 | |
7143 | && !find_insn_list (insn, LOG_LINKS (last))) | |
7144 | { | |
7145 | add_dependence (last, insn, REG_DEP_ANTI); | |
7146 | INSN_REF_COUNT (insn)++; | |
7147 | } | |
7148 | ||
7149 | CANT_MOVE (insn) = 1; | |
7150 | ||
7151 | last = insn; | |
326ee7a3 JL |
7152 | /* Skip over insns that are part of a group. |
7153 | Make each insn explicitly depend on the previous insn. | |
7154 | This ensures that only the group header will ever enter | |
7155 | the ready queue (and, when scheduled, will automatically | |
7156 | schedule the SCHED_GROUP_P block). */ | |
8c660648 | 7157 | while (SCHED_GROUP_P (insn)) |
326ee7a3 JL |
7158 | { |
7159 | rtx temp = prev_nonnote_insn (insn); | |
7160 | add_dependence (insn, temp, REG_DEP_ANTI); | |
7161 | insn = temp; | |
7162 | } | |
8c660648 JL |
7163 | } |
7164 | ||
7165 | /* Don't overrun the bounds of the basic block. */ | |
7166 | if (insn == head) | |
7167 | break; | |
7168 | ||
7169 | insn = PREV_INSN (insn); | |
7170 | } | |
7171 | ||
63de6c74 | 7172 | /* Make sure these insns are scheduled last in their block. */ |
8c660648 JL |
7173 | insn = last; |
7174 | if (insn != 0) | |
7175 | while (insn != head) | |
7176 | { | |
7177 | insn = prev_nonnote_insn (insn); | |
7178 | ||
7179 | if (INSN_REF_COUNT (insn) != 0) | |
7180 | continue; | |
7181 | ||
87373fba | 7182 | add_dependence (last, insn, REG_DEP_ANTI); |
8c660648 JL |
7183 | INSN_REF_COUNT (insn) = 1; |
7184 | ||
7185 | /* Skip over insns that are part of a group. */ | |
7186 | while (SCHED_GROUP_P (insn)) | |
7187 | insn = prev_nonnote_insn (insn); | |
7188 | } | |
7189 | } | |
7190 | ||
63de6c74 | 7191 | /* Compute backward dependences inside bb. In a multiple blocks region: |
8c660648 JL |
7192 | (1) a bb is analyzed after its predecessors, and (2) the lists in |
7193 | effect at the end of bb (after analyzing for bb) are inherited by | |
7194 | bb's successrs. | |
7195 | ||
7196 | Specifically for reg-reg data dependences, the block insns are | |
7197 | scanned by sched_analyze () top-to-bottom. Two lists are | |
63de6c74 | 7198 | maintained by sched_analyze (): reg_last_sets[] for register DEFs, |
8c660648 JL |
7199 | and reg_last_uses[] for register USEs. |
7200 | ||
7201 | When analysis is completed for bb, we update for its successors: | |
7202 | ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb]) | |
7203 | ; - USES[succ] = Union (USES [succ], DEFS [bb]) | |
7204 | ||
7205 | The mechanism for computing mem-mem data dependence is very | |
7206 | similar, and the result is interblock dependences in the region. */ | |
7207 | ||
7208 | static void | |
7209 | compute_block_backward_dependences (bb) | |
7210 | int bb; | |
7211 | { | |
7212 | int b; | |
7213 | rtx x; | |
7214 | rtx head, tail; | |
7215 | int max_reg = max_reg_num (); | |
7216 | ||
7217 | b = BB_TO_BLOCK (bb); | |
7218 | ||
7219 | if (current_nr_blocks == 1) | |
7220 | { | |
7221 | reg_last_uses = (rtx *) alloca (max_reg * sizeof (rtx)); | |
7222 | reg_last_sets = (rtx *) alloca (max_reg * sizeof (rtx)); | |
28c95eff | 7223 | reg_last_clobbers = (rtx *) alloca (max_reg * sizeof (rtx)); |
8c660648 JL |
7224 | |
7225 | bzero ((char *) reg_last_uses, max_reg * sizeof (rtx)); | |
7226 | bzero ((char *) reg_last_sets, max_reg * sizeof (rtx)); | |
28c95eff | 7227 | bzero ((char *) reg_last_clobbers, max_reg * sizeof (rtx)); |
8c660648 JL |
7228 | |
7229 | pending_read_insns = 0; | |
7230 | pending_read_mems = 0; | |
7231 | pending_write_insns = 0; | |
7232 | pending_write_mems = 0; | |
7233 | pending_lists_length = 0; | |
7234 | last_function_call = 0; | |
7235 | last_pending_memory_flush = 0; | |
7236 | sched_before_next_call | |
38a448ca RH |
7237 | = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
7238 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
7239 | LOG_LINKS (sched_before_next_call) = 0; |
7240 | } | |
7241 | else | |
7242 | { | |
7243 | reg_last_uses = bb_reg_last_uses[bb]; | |
7244 | reg_last_sets = bb_reg_last_sets[bb]; | |
28c95eff | 7245 | reg_last_clobbers = bb_reg_last_clobbers[bb]; |
8c660648 JL |
7246 | |
7247 | pending_read_insns = bb_pending_read_insns[bb]; | |
7248 | pending_read_mems = bb_pending_read_mems[bb]; | |
7249 | pending_write_insns = bb_pending_write_insns[bb]; | |
7250 | pending_write_mems = bb_pending_write_mems[bb]; | |
7251 | pending_lists_length = bb_pending_lists_length[bb]; | |
7252 | last_function_call = bb_last_function_call[bb]; | |
7253 | last_pending_memory_flush = bb_last_pending_memory_flush[bb]; | |
7254 | ||
7255 | sched_before_next_call = bb_sched_before_next_call[bb]; | |
7256 | } | |
7257 | ||
63de6c74 | 7258 | /* Do the analysis for this block. */ |
8c660648 JL |
7259 | get_block_head_tail (bb, &head, &tail); |
7260 | sched_analyze (head, tail); | |
7261 | add_branch_dependences (head, tail); | |
7262 | ||
7263 | if (current_nr_blocks > 1) | |
7264 | { | |
7265 | int e, first_edge; | |
7266 | int b_succ, bb_succ; | |
7267 | int reg; | |
7268 | rtx link_insn, link_mem; | |
7269 | rtx u; | |
7270 | ||
63de6c74 MH |
7271 | /* These lists should point to the right place, for correct |
7272 | freeing later. */ | |
8c660648 JL |
7273 | bb_pending_read_insns[bb] = pending_read_insns; |
7274 | bb_pending_read_mems[bb] = pending_read_mems; | |
7275 | bb_pending_write_insns[bb] = pending_write_insns; | |
7276 | bb_pending_write_mems[bb] = pending_write_mems; | |
7277 | ||
63de6c74 | 7278 | /* bb's structures are inherited by it's successors. */ |
8c660648 JL |
7279 | first_edge = e = OUT_EDGES (b); |
7280 | if (e > 0) | |
7281 | do | |
7282 | { | |
7283 | b_succ = TO_BLOCK (e); | |
7284 | bb_succ = BLOCK_TO_BB (b_succ); | |
7285 | ||
63de6c74 | 7286 | /* Only bbs "below" bb, in the same region, are interesting. */ |
8c660648 JL |
7287 | if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ) |
7288 | || bb_succ <= bb) | |
7289 | { | |
7290 | e = NEXT_OUT (e); | |
7291 | continue; | |
7292 | } | |
7293 | ||
7294 | for (reg = 0; reg < max_reg; reg++) | |
7295 | { | |
7296 | ||
63de6c74 | 7297 | /* reg-last-uses lists are inherited by bb_succ. */ |
8c660648 JL |
7298 | for (u = reg_last_uses[reg]; u; u = XEXP (u, 1)) |
7299 | { | |
63de6c74 MH |
7300 | if (find_insn_list (XEXP (u, 0), |
7301 | (bb_reg_last_uses[bb_succ])[reg])) | |
8c660648 JL |
7302 | continue; |
7303 | ||
7304 | (bb_reg_last_uses[bb_succ])[reg] | |
ebb7b10b RH |
7305 | = alloc_INSN_LIST (XEXP (u, 0), |
7306 | (bb_reg_last_uses[bb_succ])[reg]); | |
8c660648 JL |
7307 | } |
7308 | ||
63de6c74 | 7309 | /* reg-last-defs lists are inherited by bb_succ. */ |
8c660648 JL |
7310 | for (u = reg_last_sets[reg]; u; u = XEXP (u, 1)) |
7311 | { | |
63de6c74 MH |
7312 | if (find_insn_list (XEXP (u, 0), |
7313 | (bb_reg_last_sets[bb_succ])[reg])) | |
8c660648 JL |
7314 | continue; |
7315 | ||
7316 | (bb_reg_last_sets[bb_succ])[reg] | |
ebb7b10b RH |
7317 | = alloc_INSN_LIST (XEXP (u, 0), |
7318 | (bb_reg_last_sets[bb_succ])[reg]); | |
8c660648 | 7319 | } |
28c95eff RH |
7320 | |
7321 | for (u = reg_last_clobbers[reg]; u; u = XEXP (u, 1)) | |
7322 | { | |
63de6c74 MH |
7323 | if (find_insn_list (XEXP (u, 0), |
7324 | (bb_reg_last_clobbers[bb_succ])[reg])) | |
28c95eff RH |
7325 | continue; |
7326 | ||
7327 | (bb_reg_last_clobbers[bb_succ])[reg] | |
7328 | = alloc_INSN_LIST (XEXP (u, 0), | |
7329 | (bb_reg_last_clobbers[bb_succ])[reg]); | |
7330 | } | |
8c660648 JL |
7331 | } |
7332 | ||
63de6c74 | 7333 | /* Mem read/write lists are inherited by bb_succ. */ |
8c660648 JL |
7334 | link_insn = pending_read_insns; |
7335 | link_mem = pending_read_mems; | |
7336 | while (link_insn) | |
7337 | { | |
63de6c74 MH |
7338 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
7339 | XEXP (link_mem, 0), | |
8c660648 JL |
7340 | bb_pending_read_insns[bb_succ], |
7341 | bb_pending_read_mems[bb_succ]))) | |
7342 | add_insn_mem_dependence (&bb_pending_read_insns[bb_succ], | |
7343 | &bb_pending_read_mems[bb_succ], | |
7344 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
7345 | link_insn = XEXP (link_insn, 1); | |
7346 | link_mem = XEXP (link_mem, 1); | |
7347 | } | |
7348 | ||
7349 | link_insn = pending_write_insns; | |
7350 | link_mem = pending_write_mems; | |
7351 | while (link_insn) | |
7352 | { | |
63de6c74 MH |
7353 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
7354 | XEXP (link_mem, 0), | |
8c660648 JL |
7355 | bb_pending_write_insns[bb_succ], |
7356 | bb_pending_write_mems[bb_succ]))) | |
7357 | add_insn_mem_dependence (&bb_pending_write_insns[bb_succ], | |
7358 | &bb_pending_write_mems[bb_succ], | |
7359 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
7360 | ||
7361 | link_insn = XEXP (link_insn, 1); | |
7362 | link_mem = XEXP (link_mem, 1); | |
7363 | } | |
7364 | ||
63de6c74 | 7365 | /* last_function_call is inherited by bb_succ. */ |
8c660648 JL |
7366 | for (u = last_function_call; u; u = XEXP (u, 1)) |
7367 | { | |
63de6c74 MH |
7368 | if (find_insn_list (XEXP (u, 0), |
7369 | bb_last_function_call[bb_succ])) | |
8c660648 JL |
7370 | continue; |
7371 | ||
7372 | bb_last_function_call[bb_succ] | |
ebb7b10b RH |
7373 | = alloc_INSN_LIST (XEXP (u, 0), |
7374 | bb_last_function_call[bb_succ]); | |
8c660648 JL |
7375 | } |
7376 | ||
63de6c74 | 7377 | /* last_pending_memory_flush is inherited by bb_succ. */ |
8c660648 JL |
7378 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
7379 | { | |
63de6c74 MH |
7380 | if (find_insn_list (XEXP (u, 0), |
7381 | bb_last_pending_memory_flush[bb_succ])) | |
8c660648 JL |
7382 | continue; |
7383 | ||
7384 | bb_last_pending_memory_flush[bb_succ] | |
ebb7b10b RH |
7385 | = alloc_INSN_LIST (XEXP (u, 0), |
7386 | bb_last_pending_memory_flush[bb_succ]); | |
8c660648 JL |
7387 | } |
7388 | ||
63de6c74 | 7389 | /* sched_before_next_call is inherited by bb_succ. */ |
8c660648 JL |
7390 | x = LOG_LINKS (sched_before_next_call); |
7391 | for (; x; x = XEXP (x, 1)) | |
7392 | add_dependence (bb_sched_before_next_call[bb_succ], | |
7393 | XEXP (x, 0), REG_DEP_ANTI); | |
7394 | ||
7395 | e = NEXT_OUT (e); | |
7396 | } | |
7397 | while (e != first_edge); | |
7398 | } | |
ebb7b10b | 7399 | |
63de6c74 | 7400 | /* Free up the INSN_LISTs. |
7eea6443 JL |
7401 | |
7402 | Note this loop is executed max_reg * nr_regions times. It's first | |
5a4f6418 AM |
7403 | implementation accounted for over 90% of the calls to free_INSN_LIST_list. |
7404 | The list was empty for the vast majority of those calls. On the PA, not | |
7405 | calling free_INSN_LIST_list in those cases improves -O2 compile times by | |
7eea6443 | 7406 | 3-5% on average. */ |
ebb7b10b RH |
7407 | for (b = 0; b < max_reg; ++b) |
7408 | { | |
28c95eff | 7409 | if (reg_last_clobbers[b]) |
5a4f6418 | 7410 | free_INSN_LIST_list (®_last_clobbers[b]); |
7eea6443 | 7411 | if (reg_last_sets[b]) |
5a4f6418 | 7412 | free_INSN_LIST_list (®_last_sets[b]); |
7eea6443 | 7413 | if (reg_last_uses[b]) |
5a4f6418 | 7414 | free_INSN_LIST_list (®_last_uses[b]); |
ebb7b10b RH |
7415 | } |
7416 | ||
7417 | /* Assert that we won't need bb_reg_last_* for this block anymore. */ | |
7418 | if (current_nr_blocks > 1) | |
7419 | { | |
7420 | bb_reg_last_uses[bb] = (rtx *) NULL_RTX; | |
7421 | bb_reg_last_sets[bb] = (rtx *) NULL_RTX; | |
28c95eff | 7422 | bb_reg_last_clobbers[bb] = (rtx *) NULL_RTX; |
ebb7b10b | 7423 | } |
8c660648 JL |
7424 | } |
7425 | ||
63de6c74 | 7426 | /* Print dependences for debugging, callable from debugger. */ |
8c660648 JL |
7427 | |
7428 | void | |
7429 | debug_dependencies () | |
7430 | { | |
7431 | int bb; | |
7432 | ||
7433 | fprintf (dump, ";; --------------- forward dependences: ------------ \n"); | |
7434 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7435 | { | |
7436 | if (1) | |
7437 | { | |
7438 | rtx head, tail; | |
7439 | rtx next_tail; | |
7440 | rtx insn; | |
7441 | ||
7442 | get_block_head_tail (bb, &head, &tail); | |
7443 | next_tail = NEXT_INSN (tail); | |
7444 | fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n", | |
7445 | BB_TO_BLOCK (bb), bb); | |
7446 | ||
7447 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
7448 | "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units"); | |
7449 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
7450 | "----", "----", "--", "---", "----", "----", "--------", "-----"); | |
7451 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7452 | { | |
7453 | rtx link; | |
7454 | int unit, range; | |
7455 | ||
7456 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
7457 | { | |
7458 | int n; | |
7459 | fprintf (dump, ";; %6d ", INSN_UID (insn)); | |
7460 | if (GET_CODE (insn) == NOTE) | |
ebc25a17 MM |
7461 | { |
7462 | n = NOTE_LINE_NUMBER (insn); | |
7463 | if (n < 0) | |
7464 | fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n)); | |
7465 | else | |
7466 | fprintf (dump, "line %d, file %s\n", n, | |
7467 | NOTE_SOURCE_FILE (insn)); | |
7468 | } | |
7469 | else | |
4f64eaca | 7470 | fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn))); |
8c660648 JL |
7471 | continue; |
7472 | } | |
7473 | ||
7474 | unit = insn_unit (insn); | |
7475 | range = (unit < 0 | |
7476 | || function_units[unit].blockage_range_function == 0) ? 0 : | |
7477 | function_units[unit].blockage_range_function (insn); | |
7478 | fprintf (dump, | |
7479 | ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ", | |
7480 | (SCHED_GROUP_P (insn) ? "+" : " "), | |
7481 | INSN_UID (insn), | |
7482 | INSN_CODE (insn), | |
7483 | INSN_BB (insn), | |
7484 | INSN_DEP_COUNT (insn), | |
7485 | INSN_PRIORITY (insn), | |
7486 | insn_cost (insn, 0, 0), | |
7487 | (int) MIN_BLOCKAGE_COST (range), | |
7488 | (int) MAX_BLOCKAGE_COST (range)); | |
7489 | insn_print_units (insn); | |
7490 | fprintf (dump, "\t: "); | |
7491 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
7492 | fprintf (dump, "%d ", INSN_UID (XEXP (link, 0))); | |
7493 | fprintf (dump, "\n"); | |
7494 | } | |
7495 | } | |
7496 | } | |
7497 | fprintf (dump, "\n"); | |
7498 | } | |
7499 | ||
63de6c74 | 7500 | /* Set_priorities: compute priority of each insn in the block. */ |
8c660648 JL |
7501 | |
7502 | static int | |
7503 | set_priorities (bb) | |
7504 | int bb; | |
7505 | { | |
7506 | rtx insn; | |
7507 | int n_insn; | |
7508 | ||
7509 | rtx tail; | |
7510 | rtx prev_head; | |
7511 | rtx head; | |
7512 | ||
7513 | get_block_head_tail (bb, &head, &tail); | |
7514 | prev_head = PREV_INSN (head); | |
7515 | ||
7516 | if (head == tail | |
7517 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
7518 | return 0; | |
7519 | ||
7520 | n_insn = 0; | |
7521 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) | |
7522 | { | |
7523 | ||
7524 | if (GET_CODE (insn) == NOTE) | |
7525 | continue; | |
7526 | ||
7527 | if (!(SCHED_GROUP_P (insn))) | |
7528 | n_insn++; | |
7529 | (void) priority (insn); | |
7530 | } | |
7531 | ||
7532 | return n_insn; | |
7533 | } | |
7534 | ||
7535 | /* Make each element of VECTOR point at an rtx-vector, | |
7536 | taking the space for all those rtx-vectors from SPACE. | |
7537 | SPACE is of type (rtx *), but it is really as long as NELTS rtx-vectors. | |
7538 | BYTES_PER_ELT is the number of bytes in one rtx-vector. | |
63de6c74 | 7539 | (this is the same as init_regset_vector () in flow.c) */ |
8c660648 JL |
7540 | |
7541 | static void | |
7542 | init_rtx_vector (vector, space, nelts, bytes_per_elt) | |
7543 | rtx **vector; | |
7544 | rtx *space; | |
7545 | int nelts; | |
7546 | int bytes_per_elt; | |
7547 | { | |
7548 | register int i; | |
7549 | register rtx *p = space; | |
7550 | ||
7551 | for (i = 0; i < nelts; i++) | |
7552 | { | |
7553 | vector[i] = p; | |
7554 | p += bytes_per_elt / sizeof (*p); | |
7555 | } | |
7556 | } | |
7557 | ||
7558 | /* Schedule a region. A region is either an inner loop, a loop-free | |
7559 | subroutine, or a single basic block. Each bb in the region is | |
7560 | scheduled after its flow predecessors. */ | |
7561 | ||
7562 | static void | |
7563 | schedule_region (rgn) | |
7564 | int rgn; | |
7565 | { | |
7566 | int bb; | |
7567 | int rgn_n_insns = 0; | |
7568 | int sched_rgn_n_insns = 0; | |
7569 | ||
63de6c74 | 7570 | /* Set variables for the current region. */ |
8c660648 JL |
7571 | current_nr_blocks = RGN_NR_BLOCKS (rgn); |
7572 | current_blocks = RGN_BLOCKS (rgn); | |
7573 | ||
7574 | reg_pending_sets = ALLOCA_REG_SET (); | |
28c95eff | 7575 | reg_pending_clobbers = ALLOCA_REG_SET (); |
8c660648 JL |
7576 | reg_pending_sets_all = 0; |
7577 | ||
63de6c74 | 7578 | /* Initializations for region data dependence analyisis. */ |
8c660648 JL |
7579 | if (current_nr_blocks > 1) |
7580 | { | |
7581 | rtx *space; | |
7582 | int maxreg = max_reg_num (); | |
7583 | ||
7584 | bb_reg_last_uses = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7585 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7586 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
28c95eff RH |
7587 | init_rtx_vector (bb_reg_last_uses, space, current_nr_blocks, |
7588 | maxreg * sizeof (rtx *)); | |
8c660648 JL |
7589 | |
7590 | bb_reg_last_sets = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7591 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7592 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
28c95eff RH |
7593 | init_rtx_vector (bb_reg_last_sets, space, current_nr_blocks, |
7594 | maxreg * sizeof (rtx *)); | |
7595 | ||
7596 | bb_reg_last_clobbers = | |
7597 | (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7598 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7599 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
7600 | init_rtx_vector (bb_reg_last_clobbers, space, current_nr_blocks, | |
7601 | maxreg * sizeof (rtx *)); | |
8c660648 JL |
7602 | |
7603 | bb_pending_read_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7604 | bb_pending_read_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
28c95eff RH |
7605 | bb_pending_write_insns = |
7606 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 | 7607 | bb_pending_write_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); |
28c95eff RH |
7608 | bb_pending_lists_length = |
7609 | (int *) alloca (current_nr_blocks * sizeof (int)); | |
7610 | bb_last_pending_memory_flush = | |
7611 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 | 7612 | bb_last_function_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); |
28c95eff RH |
7613 | bb_sched_before_next_call = |
7614 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 JL |
7615 | |
7616 | init_rgn_data_dependences (current_nr_blocks); | |
7617 | } | |
7618 | ||
63de6c74 | 7619 | /* Compute LOG_LINKS. */ |
8c660648 JL |
7620 | for (bb = 0; bb < current_nr_blocks; bb++) |
7621 | compute_block_backward_dependences (bb); | |
7622 | ||
63de6c74 | 7623 | /* Compute INSN_DEPEND. */ |
8c660648 JL |
7624 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) |
7625 | compute_block_forward_dependences (bb); | |
7626 | ||
7627 | /* Delete line notes, compute live-regs at block end, and set priorities. */ | |
7628 | dead_notes = 0; | |
7629 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7630 | { | |
7631 | if (reload_completed == 0) | |
7632 | find_pre_sched_live (bb); | |
7633 | ||
7634 | if (write_symbols != NO_DEBUG) | |
7635 | { | |
7636 | save_line_notes (bb); | |
7637 | rm_line_notes (bb); | |
7638 | } | |
7639 | ||
7640 | rgn_n_insns += set_priorities (bb); | |
7641 | } | |
7642 | ||
63de6c74 | 7643 | /* Compute interblock info: probabilities, split-edges, dominators, etc. */ |
8c660648 JL |
7644 | if (current_nr_blocks > 1) |
7645 | { | |
7646 | int i; | |
7647 | ||
7648 | prob = (float *) alloca ((current_nr_blocks) * sizeof (float)); | |
7649 | ||
7650 | bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1; | |
7651 | dom = (bbset *) alloca (current_nr_blocks * sizeof (bbset)); | |
7652 | for (i = 0; i < current_nr_blocks; i++) | |
7653 | { | |
7654 | dom[i] = (bbset) alloca (bbset_size * sizeof (HOST_WIDE_INT)); | |
7655 | bzero ((char *) dom[i], bbset_size * sizeof (HOST_WIDE_INT)); | |
7656 | } | |
7657 | ||
63de6c74 | 7658 | /* Edge to bit. */ |
8c660648 JL |
7659 | rgn_nr_edges = 0; |
7660 | edge_to_bit = (int *) alloca (nr_edges * sizeof (int)); | |
7661 | for (i = 1; i < nr_edges; i++) | |
7662 | if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn) | |
7663 | EDGE_TO_BIT (i) = rgn_nr_edges++; | |
7664 | rgn_edges = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
7665 | ||
7666 | rgn_nr_edges = 0; | |
7667 | for (i = 1; i < nr_edges; i++) | |
7668 | if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn)) | |
7669 | rgn_edges[rgn_nr_edges++] = i; | |
7670 | ||
63de6c74 | 7671 | /* Split edges. */ |
8c660648 JL |
7672 | edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1; |
7673 | pot_split = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset)); | |
63de6c74 MH |
7674 | ancestor_edges = (edgeset *) alloca (current_nr_blocks |
7675 | * sizeof (edgeset)); | |
8c660648 JL |
7676 | for (i = 0; i < current_nr_blocks; i++) |
7677 | { | |
7678 | pot_split[i] = | |
7679 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
7680 | bzero ((char *) pot_split[i], | |
7681 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
7682 | ancestor_edges[i] = | |
7683 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
7684 | bzero ((char *) ancestor_edges[i], | |
7685 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
7686 | } | |
7687 | ||
63de6c74 | 7688 | /* Compute probabilities, dominators, split_edges. */ |
8c660648 JL |
7689 | for (bb = 0; bb < current_nr_blocks; bb++) |
7690 | compute_dom_prob_ps (bb); | |
7691 | } | |
7692 | ||
63de6c74 | 7693 | /* Now we can schedule all blocks. */ |
8c660648 JL |
7694 | for (bb = 0; bb < current_nr_blocks; bb++) |
7695 | { | |
5835e573 | 7696 | sched_rgn_n_insns += schedule_block (bb, rgn_n_insns); |
8c660648 JL |
7697 | |
7698 | #ifdef USE_C_ALLOCA | |
7699 | alloca (0); | |
7700 | #endif | |
7701 | } | |
7702 | ||
63de6c74 | 7703 | /* Sanity check: verify that all region insns were scheduled. */ |
cc132865 JL |
7704 | if (sched_rgn_n_insns != rgn_n_insns) |
7705 | abort (); | |
8c660648 | 7706 | |
63de6c74 | 7707 | /* Update register life and usage information. */ |
8c660648 JL |
7708 | if (reload_completed == 0) |
7709 | { | |
7710 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) | |
7711 | find_post_sched_live (bb); | |
7712 | ||
7713 | if (current_nr_blocks <= 1) | |
63de6c74 MH |
7714 | /* Sanity check. There should be no REG_DEAD notes leftover |
7715 | at the end. In practice, this can occur as the result of | |
7716 | bugs in flow, combine.c, and/or sched.c. The values of the | |
7717 | REG_DEAD notes remaining are meaningless, because | |
7718 | dead_notes is just used as a free list. */ | |
8c660648 JL |
7719 | if (dead_notes != 0) |
7720 | abort (); | |
7721 | } | |
7722 | ||
63de6c74 | 7723 | /* Restore line notes. */ |
8c660648 JL |
7724 | if (write_symbols != NO_DEBUG) |
7725 | { | |
7726 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7727 | restore_line_notes (bb); | |
7728 | } | |
7729 | ||
63de6c74 | 7730 | /* Done with this region. */ |
8c660648 | 7731 | free_pending_lists (); |
f187056f JL |
7732 | |
7733 | FREE_REG_SET (reg_pending_sets); | |
28c95eff | 7734 | FREE_REG_SET (reg_pending_clobbers); |
8c660648 JL |
7735 | } |
7736 | ||
8c660648 JL |
7737 | /* The one entry point in this file. DUMP_FILE is the dump file for |
7738 | this pass. */ | |
7739 | ||
7740 | void | |
7741 | schedule_insns (dump_file) | |
7742 | FILE *dump_file; | |
7743 | { | |
7744 | ||
7745 | int max_uid; | |
7746 | int b; | |
8c660648 JL |
7747 | rtx insn; |
7748 | int rgn; | |
7749 | ||
7750 | int luid; | |
7751 | ||
63de6c74 | 7752 | /* Disable speculative loads in their presence if cc0 defined. */ |
8c660648 JL |
7753 | #ifdef HAVE_cc0 |
7754 | flag_schedule_speculative_load = 0; | |
7755 | #endif | |
7756 | ||
7757 | /* Taking care of this degenerate case makes the rest of | |
7758 | this code simpler. */ | |
7759 | if (n_basic_blocks == 0) | |
7760 | return; | |
7761 | ||
63de6c74 | 7762 | /* Set dump and sched_verbose for the desired debugging output. If no |
8c660648 JL |
7763 | dump-file was specified, but -fsched-verbose-N (any N), print to stderr. |
7764 | For -fsched-verbose-N, N>=10, print everything to stderr. */ | |
7765 | sched_verbose = sched_verbose_param; | |
7766 | if (sched_verbose_param == 0 && dump_file) | |
7767 | sched_verbose = 1; | |
7768 | dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file); | |
7769 | ||
7770 | nr_inter = 0; | |
7771 | nr_spec = 0; | |
7772 | ||
63de6c74 | 7773 | /* Initialize issue_rate. */ |
62d65906 | 7774 | issue_rate = ISSUE_RATE; |
8c660648 | 7775 | |
d3a923ee | 7776 | split_all_insns (1); |
8c660648 JL |
7777 | |
7778 | max_uid = (get_max_uid () + 1); | |
7779 | ||
ad85216e KG |
7780 | cant_move = xcalloc (max_uid, sizeof (char)); |
7781 | fed_by_spec_load = xcalloc (max_uid, sizeof (char)); | |
7782 | is_load_insn = xcalloc (max_uid, sizeof (char)); | |
8c660648 | 7783 | |
7c74b010 JW |
7784 | insn_orig_block = (int *) xmalloc (max_uid * sizeof (int)); |
7785 | insn_luid = (int *) xmalloc (max_uid * sizeof (int)); | |
8c660648 JL |
7786 | |
7787 | luid = 0; | |
7788 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7789 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
7790 | { |
7791 | INSN_BLOCK (insn) = b; | |
7792 | INSN_LUID (insn) = luid++; | |
7793 | ||
3b413743 | 7794 | if (insn == BLOCK_END (b)) |
8c660648 JL |
7795 | break; |
7796 | } | |
7797 | ||
63de6c74 | 7798 | /* After reload, remove inter-blocks dependences computed before reload. */ |
8c660648 JL |
7799 | if (reload_completed) |
7800 | { | |
7801 | int b; | |
7802 | rtx insn; | |
7803 | ||
7804 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7805 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 | 7806 | { |
c995fea1 | 7807 | rtx link, prev; |
8c660648 JL |
7808 | |
7809 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
7810 | { | |
c995fea1 RH |
7811 | prev = NULL_RTX; |
7812 | link = LOG_LINKS (insn); | |
7813 | while (link) | |
8c660648 JL |
7814 | { |
7815 | rtx x = XEXP (link, 0); | |
7816 | ||
7817 | if (INSN_BLOCK (x) != b) | |
c995fea1 RH |
7818 | { |
7819 | remove_dependence (insn, x); | |
7820 | link = prev ? XEXP (prev, 1) : LOG_LINKS (insn); | |
7821 | } | |
7822 | else | |
7823 | prev = link, link = XEXP (prev, 1); | |
8c660648 JL |
7824 | } |
7825 | } | |
7826 | ||
3b413743 | 7827 | if (insn == BLOCK_END (b)) |
8c660648 JL |
7828 | break; |
7829 | } | |
7830 | } | |
7831 | ||
7832 | nr_regions = 0; | |
7833 | rgn_table = (region *) alloca ((n_basic_blocks) * sizeof (region)); | |
7834 | rgn_bb_table = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
7835 | block_to_bb = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
7836 | containing_rgn = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
7837 | ||
63de6c74 | 7838 | /* Compute regions for scheduling. */ |
8c660648 JL |
7839 | if (reload_completed |
7840 | || n_basic_blocks == 1 | |
7841 | || !flag_schedule_interblock) | |
7842 | { | |
7843 | find_single_block_region (); | |
7844 | } | |
7845 | else | |
7846 | { | |
63de6c74 | 7847 | /* Verify that a 'good' control flow graph can be built. */ |
168cbdf9 | 7848 | if (is_cfg_nonregular ()) |
8c660648 JL |
7849 | { |
7850 | find_single_block_region (); | |
7851 | } | |
7852 | else | |
7853 | { | |
a2e68776 JL |
7854 | int_list_ptr *s_preds, *s_succs; |
7855 | int *num_preds, *num_succs; | |
7856 | sbitmap *dom, *pdom; | |
7857 | ||
7858 | s_preds = (int_list_ptr *) alloca (n_basic_blocks | |
7859 | * sizeof (int_list_ptr)); | |
7860 | s_succs = (int_list_ptr *) alloca (n_basic_blocks | |
7861 | * sizeof (int_list_ptr)); | |
7862 | num_preds = (int *) alloca (n_basic_blocks * sizeof (int)); | |
7863 | num_succs = (int *) alloca (n_basic_blocks * sizeof (int)); | |
7864 | dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
7865 | pdom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
7866 | ||
7867 | /* The scheduler runs after flow; therefore, we can't blindly call | |
7868 | back into find_basic_blocks since doing so could invalidate the | |
e881bb1b | 7869 | info in global_live_at_start. |
a2e68776 JL |
7870 | |
7871 | Consider a block consisting entirely of dead stores; after life | |
7872 | analysis it would be a block of NOTE_INSN_DELETED notes. If | |
7873 | we call find_basic_blocks again, then the block would be removed | |
7874 | entirely and invalidate our the register live information. | |
7875 | ||
7876 | We could (should?) recompute register live information. Doing | |
7877 | so may even be beneficial. */ | |
7878 | ||
5d27de7d | 7879 | compute_preds_succs (s_preds, s_succs, num_preds, num_succs); |
a2e68776 | 7880 | |
63de6c74 MH |
7881 | /* Compute the dominators and post dominators. We don't |
7882 | currently use post dominators, but we should for | |
7883 | speculative motion analysis. */ | |
a2e68776 JL |
7884 | compute_dominators (dom, pdom, s_preds, s_succs); |
7885 | ||
168cbdf9 JL |
7886 | /* build_control_flow will return nonzero if it detects unreachable |
7887 | blocks or any other irregularity with the cfg which prevents | |
7888 | cross block scheduling. */ | |
a2e68776 | 7889 | if (build_control_flow (s_preds, s_succs, num_preds, num_succs) != 0) |
168cbdf9 JL |
7890 | find_single_block_region (); |
7891 | else | |
a2e68776 | 7892 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom); |
8c660648 JL |
7893 | |
7894 | if (sched_verbose >= 3) | |
a2e68776 | 7895 | debug_regions (); |
8c660648 | 7896 | |
a2e68776 | 7897 | /* For now. This will move as more and more of haifa is converted |
63de6c74 | 7898 | to using the cfg code in flow.c. */ |
a2e68776 JL |
7899 | free_bb_mem (); |
7900 | free (dom); | |
7901 | free (pdom); | |
8c660648 JL |
7902 | } |
7903 | } | |
7904 | ||
7905 | /* Allocate data for this pass. See comments, above, | |
7c74b010 JW |
7906 | for what these vectors do. |
7907 | ||
7908 | We use xmalloc instead of alloca, because max_uid can be very large | |
7909 | when there is a lot of function inlining. If we used alloca, we could | |
7910 | exceed stack limits on some hosts for some inputs. */ | |
ad85216e KG |
7911 | insn_priority = (int *) xcalloc (max_uid, sizeof (int)); |
7912 | insn_reg_weight = (int *) xcalloc (max_uid, sizeof (int)); | |
7913 | insn_tick = (int *) xcalloc (max_uid, sizeof (int)); | |
7914 | insn_costs = (short *) xcalloc (max_uid, sizeof (short)); | |
7915 | insn_units = (short *) xcalloc (max_uid, sizeof (short)); | |
7916 | insn_blockage = (unsigned int *) xcalloc (max_uid, sizeof (unsigned int)); | |
7917 | insn_ref_count = (int *) xcalloc (max_uid, sizeof (int)); | |
8c660648 | 7918 | |
63de6c74 | 7919 | /* Allocate for forward dependencies. */ |
ad85216e KG |
7920 | insn_dep_count = (int *) xcalloc (max_uid, sizeof (int)); |
7921 | insn_depend = (rtx *) xcalloc (max_uid, sizeof (rtx)); | |
8c660648 JL |
7922 | |
7923 | if (reload_completed == 0) | |
7924 | { | |
7925 | int i; | |
7926 | ||
7927 | sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int)); | |
7928 | sched_reg_live_length = (int *) alloca (max_regno * sizeof (int)); | |
7929 | sched_reg_basic_block = (int *) alloca (max_regno * sizeof (int)); | |
7930 | bb_live_regs = ALLOCA_REG_SET (); | |
7931 | bzero ((char *) sched_reg_n_calls_crossed, max_regno * sizeof (int)); | |
7932 | bzero ((char *) sched_reg_live_length, max_regno * sizeof (int)); | |
7933 | ||
7934 | for (i = 0; i < max_regno; i++) | |
7935 | sched_reg_basic_block[i] = REG_BLOCK_UNKNOWN; | |
7936 | } | |
7937 | else | |
7938 | { | |
7939 | sched_reg_n_calls_crossed = 0; | |
7940 | sched_reg_live_length = 0; | |
7941 | bb_live_regs = 0; | |
7942 | } | |
7943 | init_alias_analysis (); | |
7944 | ||
7945 | if (write_symbols != NO_DEBUG) | |
7946 | { | |
7947 | rtx line; | |
7948 | ||
ad85216e | 7949 | line_note = (rtx *) xcalloc (max_uid, sizeof (rtx)); |
8c660648 JL |
7950 | line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx)); |
7951 | bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx)); | |
7952 | ||
7953 | /* Save-line-note-head: | |
7954 | Determine the line-number at the start of each basic block. | |
7955 | This must be computed and saved now, because after a basic block's | |
7956 | predecessor has been scheduled, it is impossible to accurately | |
7957 | determine the correct line number for the first insn of the block. */ | |
7958 | ||
7959 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7960 | for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line)) |
8c660648 JL |
7961 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) |
7962 | { | |
7963 | line_note_head[b] = line; | |
7964 | break; | |
7965 | } | |
7966 | } | |
7967 | ||
63de6c74 | 7968 | /* Find units used in this fuction, for visualization. */ |
8c660648 JL |
7969 | if (sched_verbose) |
7970 | init_target_units (); | |
7971 | ||
7972 | /* ??? Add a NOTE after the last insn of the last basic block. It is not | |
7973 | known why this is done. */ | |
7974 | ||
3b413743 | 7975 | insn = BLOCK_END (n_basic_blocks - 1); |
8c660648 JL |
7976 | if (NEXT_INSN (insn) == 0 |
7977 | || (GET_CODE (insn) != NOTE | |
7978 | && GET_CODE (insn) != CODE_LABEL | |
3b413743 RH |
7979 | /* Don't emit a NOTE if it would end up between an unconditional |
7980 | jump and a BARRIER. */ | |
8c660648 JL |
7981 | && !(GET_CODE (insn) == JUMP_INSN |
7982 | && GET_CODE (NEXT_INSN (insn)) == BARRIER))) | |
3b413743 | 7983 | emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1)); |
8c660648 | 7984 | |
63de6c74 | 7985 | /* Schedule every region in the subroutine. */ |
8c660648 JL |
7986 | for (rgn = 0; rgn < nr_regions; rgn++) |
7987 | { | |
7988 | schedule_region (rgn); | |
7989 | ||
7990 | #ifdef USE_C_ALLOCA | |
7991 | alloca (0); | |
7992 | #endif | |
7993 | } | |
7994 | ||
7995 | /* Reposition the prologue and epilogue notes in case we moved the | |
7996 | prologue/epilogue insns. */ | |
7997 | if (reload_completed) | |
7998 | reposition_prologue_and_epilogue_notes (get_insns ()); | |
7999 | ||
63de6c74 | 8000 | /* Delete redundant line notes. */ |
8c660648 JL |
8001 | if (write_symbols != NO_DEBUG) |
8002 | rm_redundant_line_notes (); | |
8003 | ||
8004 | /* Update information about uses of registers in the subroutine. */ | |
8005 | if (reload_completed == 0) | |
8006 | update_reg_usage (); | |
8007 | ||
8008 | if (sched_verbose) | |
8009 | { | |
8010 | if (reload_completed == 0 && flag_schedule_interblock) | |
8011 | { | |
8012 | fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n", | |
8013 | nr_inter, nr_spec); | |
8014 | } | |
8015 | else | |
8016 | { | |
8017 | if (nr_inter > 0) | |
8018 | abort (); | |
8019 | } | |
8020 | fprintf (dump, "\n\n"); | |
8021 | } | |
f187056f | 8022 | |
7c74b010 JW |
8023 | free (cant_move); |
8024 | free (fed_by_spec_load); | |
8025 | free (is_load_insn); | |
8026 | free (insn_orig_block); | |
8027 | free (insn_luid); | |
8028 | ||
8029 | free (insn_priority); | |
8030 | free (insn_reg_weight); | |
8031 | free (insn_tick); | |
8032 | free (insn_costs); | |
8033 | free (insn_units); | |
8034 | free (insn_blockage); | |
8035 | free (insn_ref_count); | |
8036 | ||
8037 | free (insn_dep_count); | |
8038 | free (insn_depend); | |
8039 | ||
8040 | if (write_symbols != NO_DEBUG) | |
8041 | free (line_note); | |
8042 | ||
f187056f JL |
8043 | if (bb_live_regs) |
8044 | FREE_REG_SET (bb_live_regs); | |
168cbdf9 JL |
8045 | |
8046 | if (edge_table) | |
8047 | { | |
8048 | free (edge_table); | |
8049 | edge_table = NULL; | |
8050 | } | |
8051 | ||
8052 | if (in_edges) | |
8053 | { | |
8054 | free (in_edges); | |
8055 | in_edges = NULL; | |
8056 | } | |
8057 | if (out_edges) | |
8058 | { | |
8059 | free (out_edges); | |
8060 | out_edges = NULL; | |
8061 | } | |
8c660648 JL |
8062 | } |
8063 | #endif /* INSN_SCHEDULING */ |