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8c660648 | 1 | /* Instruction scheduling pass. |
a5cad800 | 2 | Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc. |
8c660648 JL |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
4 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, but | |
14 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to the Free | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | ||
24 | /* Instruction scheduling pass. | |
25 | ||
26 | This pass implements list scheduling within basic blocks. It is | |
27 | run twice: (1) after flow analysis, but before register allocation, | |
28 | and (2) after register allocation. | |
29 | ||
30 | The first run performs interblock scheduling, moving insns between | |
31 | different blocks in the same "region", and the second runs only | |
32 | basic block scheduling. | |
33 | ||
34 | Interblock motions performed are useful motions and speculative | |
35 | motions, including speculative loads. Motions requiring code | |
36 | duplication are not supported. The identification of motion type | |
37 | and the check for validity of speculative motions requires | |
38 | construction and analysis of the function's control flow graph. | |
39 | The scheduler works as follows: | |
40 | ||
41 | We compute insn priorities based on data dependencies. Flow | |
42 | analysis only creates a fraction of the data-dependencies we must | |
43 | observe: namely, only those dependencies which the combiner can be | |
44 | expected to use. For this pass, we must therefore create the | |
45 | remaining dependencies we need to observe: register dependencies, | |
46 | memory dependencies, dependencies to keep function calls in order, | |
47 | and the dependence between a conditional branch and the setting of | |
48 | condition codes are all dealt with here. | |
49 | ||
50 | The scheduler first traverses the data flow graph, starting with | |
51 | the last instruction, and proceeding to the first, assigning values | |
52 | to insn_priority as it goes. This sorts the instructions | |
53 | topologically by data dependence. | |
54 | ||
55 | Once priorities have been established, we order the insns using | |
56 | list scheduling. This works as follows: starting with a list of | |
57 | all the ready insns, and sorted according to priority number, we | |
58 | schedule the insn from the end of the list by placing its | |
59 | predecessors in the list according to their priority order. We | |
60 | consider this insn scheduled by setting the pointer to the "end" of | |
61 | the list to point to the previous insn. When an insn has no | |
62 | predecessors, we either queue it until sufficient time has elapsed | |
63 | or add it to the ready list. As the instructions are scheduled or | |
64 | when stalls are introduced, the queue advances and dumps insns into | |
65 | the ready list. When all insns down to the lowest priority have | |
66 | been scheduled, the critical path of the basic block has been made | |
67 | as short as possible. The remaining insns are then scheduled in | |
68 | remaining slots. | |
69 | ||
70 | Function unit conflicts are resolved during forward list scheduling | |
71 | by tracking the time when each insn is committed to the schedule | |
72 | and from that, the time the function units it uses must be free. | |
73 | As insns on the ready list are considered for scheduling, those | |
74 | that would result in a blockage of the already committed insns are | |
75 | queued until no blockage will result. | |
76 | ||
77 | The following list shows the order in which we want to break ties | |
78 | among insns in the ready list: | |
79 | ||
80 | 1. choose insn with the longest path to end of bb, ties | |
81 | broken by | |
82 | 2. choose insn with least contribution to register pressure, | |
83 | ties broken by | |
84 | 3. prefer in-block upon interblock motion, ties broken by | |
85 | 4. prefer useful upon speculative motion, ties broken by | |
86 | 5. choose insn with largest control flow probability, ties | |
87 | broken by | |
88 | 6. choose insn with the least dependences upon the previously | |
89 | scheduled insn, or finally | |
2db45993 JL |
90 | 7 choose the insn which has the most insns dependent on it. |
91 | 8. choose insn with lowest UID. | |
8c660648 JL |
92 | |
93 | Memory references complicate matters. Only if we can be certain | |
94 | that memory references are not part of the data dependency graph | |
95 | (via true, anti, or output dependence), can we move operations past | |
96 | memory references. To first approximation, reads can be done | |
97 | independently, while writes introduce dependencies. Better | |
98 | approximations will yield fewer dependencies. | |
99 | ||
100 | Before reload, an extended analysis of interblock data dependences | |
101 | is required for interblock scheduling. This is performed in | |
102 | compute_block_backward_dependences (). | |
103 | ||
104 | Dependencies set up by memory references are treated in exactly the | |
105 | same way as other dependencies, by using LOG_LINKS backward | |
106 | dependences. LOG_LINKS are translated into INSN_DEPEND forward | |
107 | dependences for the purpose of forward list scheduling. | |
108 | ||
109 | Having optimized the critical path, we may have also unduly | |
110 | extended the lifetimes of some registers. If an operation requires | |
111 | that constants be loaded into registers, it is certainly desirable | |
112 | to load those constants as early as necessary, but no earlier. | |
113 | I.e., it will not do to load up a bunch of registers at the | |
114 | beginning of a basic block only to use them at the end, if they | |
115 | could be loaded later, since this may result in excessive register | |
116 | utilization. | |
117 | ||
118 | Note that since branches are never in basic blocks, but only end | |
119 | basic blocks, this pass will not move branches. But that is ok, | |
120 | since we can use GNU's delayed branch scheduling pass to take care | |
121 | of this case. | |
122 | ||
123 | Also note that no further optimizations based on algebraic | |
124 | identities are performed, so this pass would be a good one to | |
125 | perform instruction splitting, such as breaking up a multiply | |
126 | instruction into shifts and adds where that is profitable. | |
127 | ||
128 | Given the memory aliasing analysis that this pass should perform, | |
129 | it should be possible to remove redundant stores to memory, and to | |
130 | load values from registers instead of hitting memory. | |
131 | ||
132 | Before reload, speculative insns are moved only if a 'proof' exists | |
133 | that no exception will be caused by this, and if no live registers | |
134 | exist that inhibit the motion (live registers constraints are not | |
135 | represented by data dependence edges). | |
136 | ||
137 | This pass must update information that subsequent passes expect to | |
138 | be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths, | |
3b413743 RH |
139 | reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD, |
140 | BLOCK_END. | |
8c660648 JL |
141 | |
142 | The information in the line number notes is carefully retained by | |
143 | this pass. Notes that refer to the starting and ending of | |
144 | exception regions are also carefully retained by this pass. All | |
145 | other NOTE insns are grouped in their same relative order at the | |
146 | beginning of basic blocks and regions that have been scheduled. | |
147 | ||
148 | The main entry point for this pass is schedule_insns(), called for | |
149 | each function. The work of the scheduler is organized in three | |
150 | levels: (1) function level: insns are subject to splitting, | |
151 | control-flow-graph is constructed, regions are computed (after | |
152 | reload, each region is of one block), (2) region level: control | |
153 | flow graph attributes required for interblock scheduling are | |
154 | computed (dominators, reachability, etc.), data dependences and | |
155 | priorities are computed, and (3) block level: insns in the block | |
156 | are actually scheduled. */ | |
157 | \f | |
8c660648 | 158 | #include "config.h" |
5835e573 | 159 | #include "system.h" |
01198c2f | 160 | #include "toplev.h" |
8c660648 | 161 | #include "rtl.h" |
6baf1cc8 | 162 | #include "tm_p.h" |
8c660648 JL |
163 | #include "basic-block.h" |
164 | #include "regs.h" | |
49ad7cfa | 165 | #include "function.h" |
8c660648 JL |
166 | #include "hard-reg-set.h" |
167 | #include "flags.h" | |
168 | #include "insn-config.h" | |
169 | #include "insn-attr.h" | |
170 | #include "except.h" | |
487a6e06 | 171 | #include "toplev.h" |
79c9824e | 172 | #include "recog.h" |
8c660648 JL |
173 | |
174 | extern char *reg_known_equiv_p; | |
175 | extern rtx *reg_known_value; | |
176 | ||
177 | #ifdef INSN_SCHEDULING | |
178 | ||
8c660648 JL |
179 | /* target_units bitmask has 1 for each unit in the cpu. It should be |
180 | possible to compute this variable from the machine description. | |
63de6c74 | 181 | But currently it is computed by examining the insn list. Since |
8c660648 JL |
182 | this is only needed for visualization, it seems an acceptable |
183 | solution. (For understanding the mapping of bits to units, see | |
63de6c74 | 184 | definition of function_units[] in "insn-attrtab.c".) */ |
8c660648 | 185 | |
61822835 | 186 | static int target_units = 0; |
8c660648 JL |
187 | |
188 | /* issue_rate is the number of insns that can be scheduled in the same | |
189 | machine cycle. It can be defined in the config/mach/mach.h file, | |
190 | otherwise we set it to 1. */ | |
191 | ||
192 | static int issue_rate; | |
193 | ||
62d65906 JL |
194 | #ifndef ISSUE_RATE |
195 | #define ISSUE_RATE 1 | |
8c660648 JL |
196 | #endif |
197 | ||
cc132865 | 198 | /* sched-verbose controls the amount of debugging output the |
8c660648 JL |
199 | scheduler prints. It is controlled by -fsched-verbose-N: |
200 | N>0 and no -DSR : the output is directed to stderr. | |
201 | N>=10 will direct the printouts to stderr (regardless of -dSR). | |
202 | N=1: same as -dSR. | |
203 | N=2: bb's probabilities, detailed ready list info, unit/insn info. | |
204 | N=3: rtl at abort point, control-flow, regions info. | |
cc132865 | 205 | N=5: dependences info. */ |
8c660648 JL |
206 | |
207 | #define MAX_RGN_BLOCKS 10 | |
208 | #define MAX_RGN_INSNS 100 | |
209 | ||
8c660648 JL |
210 | static int sched_verbose_param = 0; |
211 | static int sched_verbose = 0; | |
8c660648 | 212 | |
63de6c74 | 213 | /* nr_inter/spec counts interblock/speculative motion for the function. */ |
8c660648 JL |
214 | static int nr_inter, nr_spec; |
215 | ||
216 | ||
63de6c74 | 217 | /* Debugging file. All printouts are sent to dump, which is always set, |
8c660648 JL |
218 | either to stderr, or to the dump listing file (-dRS). */ |
219 | static FILE *dump = 0; | |
220 | ||
221 | /* fix_sched_param() is called from toplev.c upon detection | |
222 | of the -fsched-***-N options. */ | |
223 | ||
224 | void | |
225 | fix_sched_param (param, val) | |
5f06c983 | 226 | const char *param, *val; |
8c660648 | 227 | { |
cc132865 | 228 | if (!strcmp (param, "verbose")) |
8c660648 | 229 | sched_verbose_param = atoi (val); |
8c660648 JL |
230 | else |
231 | warning ("fix_sched_param: unknown param: %s", param); | |
232 | } | |
233 | ||
234 | ||
8c660648 JL |
235 | /* Element N is the next insn that sets (hard or pseudo) register |
236 | N within the current basic block; or zero, if there is no | |
237 | such insn. Needed for new registers which may be introduced | |
238 | by splitting insns. */ | |
239 | static rtx *reg_last_uses; | |
240 | static rtx *reg_last_sets; | |
28c95eff | 241 | static rtx *reg_last_clobbers; |
8c660648 | 242 | static regset reg_pending_sets; |
28c95eff | 243 | static regset reg_pending_clobbers; |
8c660648 JL |
244 | static int reg_pending_sets_all; |
245 | ||
246 | /* Vector indexed by INSN_UID giving the original ordering of the insns. */ | |
247 | static int *insn_luid; | |
248 | #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)]) | |
249 | ||
356edbd7 | 250 | /* To speed up the test for duplicate dependency links we keep a record |
aae0390e JL |
251 | of true dependencies created by add_dependence when the average number |
252 | of instructions in a basic block is very large. | |
356edbd7 | 253 | |
aae0390e JL |
254 | Studies have shown that there is typically around 5 instructions between |
255 | branches for typical C code. So we can make a guess that the average | |
256 | basic block is approximately 5 instructions long; we will choose 100X | |
257 | the average size as a very large basic block. | |
258 | ||
356edbd7 JL |
259 | Each insn has an associated bitmap for its dependencies. Each bitmap |
260 | has enough entries to represent a dependency on any other insn in the | |
261 | insn chain. */ | |
262 | static sbitmap *true_dependency_cache; | |
263 | ||
8c660648 JL |
264 | /* Vector indexed by INSN_UID giving each instruction a priority. */ |
265 | static int *insn_priority; | |
266 | #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)]) | |
267 | ||
268 | static short *insn_costs; | |
269 | #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)] | |
270 | ||
271 | /* Vector indexed by INSN_UID giving an encoding of the function units | |
272 | used. */ | |
273 | static short *insn_units; | |
274 | #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)] | |
275 | ||
63de6c74 MH |
276 | /* Vector indexed by INSN_UID giving each instruction a |
277 | register-weight. This weight is an estimation of the insn | |
278 | contribution to registers pressure. */ | |
8c660648 JL |
279 | static int *insn_reg_weight; |
280 | #define INSN_REG_WEIGHT(INSN) (insn_reg_weight[INSN_UID (INSN)]) | |
281 | ||
282 | /* Vector indexed by INSN_UID giving list of insns which | |
283 | depend upon INSN. Unlike LOG_LINKS, it represents forward dependences. */ | |
284 | static rtx *insn_depend; | |
285 | #define INSN_DEPEND(INSN) insn_depend[INSN_UID (INSN)] | |
286 | ||
287 | /* Vector indexed by INSN_UID. Initialized to the number of incoming | |
288 | edges in forward dependence graph (= number of LOG_LINKS). As | |
289 | scheduling procedes, dependence counts are decreased. An | |
290 | instruction moves to the ready list when its counter is zero. */ | |
291 | static int *insn_dep_count; | |
292 | #define INSN_DEP_COUNT(INSN) (insn_dep_count[INSN_UID (INSN)]) | |
293 | ||
294 | /* Vector indexed by INSN_UID giving an encoding of the blockage range | |
295 | function. The unit and the range are encoded. */ | |
296 | static unsigned int *insn_blockage; | |
297 | #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)] | |
298 | #define UNIT_BITS 5 | |
299 | #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1) | |
300 | #define ENCODE_BLOCKAGE(U, R) \ | |
f4b94256 | 301 | (((U) << BLOCKAGE_BITS \ |
8c660648 | 302 | | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \ |
f4b94256 | 303 | | MAX_BLOCKAGE_COST (R)) |
8c660648 JL |
304 | #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS)) |
305 | #define BLOCKAGE_RANGE(B) \ | |
306 | (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \ | |
5835e573 | 307 | | ((B) & BLOCKAGE_MASK)) |
8c660648 JL |
308 | |
309 | /* Encodings of the `<name>_unit_blockage_range' function. */ | |
310 | #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2)) | |
311 | #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1)) | |
312 | ||
313 | #define DONE_PRIORITY -1 | |
314 | #define MAX_PRIORITY 0x7fffffff | |
315 | #define TAIL_PRIORITY 0x7ffffffe | |
316 | #define LAUNCH_PRIORITY 0x7f000001 | |
317 | #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0) | |
318 | #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0) | |
319 | ||
63de6c74 MH |
320 | /* Vector indexed by INSN_UID giving number of insns referring to this |
321 | insn. */ | |
8c660648 JL |
322 | static int *insn_ref_count; |
323 | #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)]) | |
324 | ||
325 | /* Vector indexed by INSN_UID giving line-number note in effect for each | |
326 | insn. For line-number notes, this indicates whether the note may be | |
327 | reused. */ | |
328 | static rtx *line_note; | |
329 | #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)]) | |
330 | ||
331 | /* Vector indexed by basic block number giving the starting line-number | |
332 | for each basic block. */ | |
333 | static rtx *line_note_head; | |
334 | ||
335 | /* List of important notes we must keep around. This is a pointer to the | |
336 | last element in the list. */ | |
337 | static rtx note_list; | |
338 | ||
8c660648 JL |
339 | /* Queues, etc. */ |
340 | ||
341 | /* An instruction is ready to be scheduled when all insns preceding it | |
342 | have already been scheduled. It is important to ensure that all | |
343 | insns which use its result will not be executed until its result | |
344 | has been computed. An insn is maintained in one of four structures: | |
345 | ||
346 | (P) the "Pending" set of insns which cannot be scheduled until | |
347 | their dependencies have been satisfied. | |
348 | (Q) the "Queued" set of insns that can be scheduled when sufficient | |
349 | time has passed. | |
350 | (R) the "Ready" list of unscheduled, uncommitted insns. | |
351 | (S) the "Scheduled" list of insns. | |
352 | ||
353 | Initially, all insns are either "Pending" or "Ready" depending on | |
354 | whether their dependencies are satisfied. | |
355 | ||
356 | Insns move from the "Ready" list to the "Scheduled" list as they | |
357 | are committed to the schedule. As this occurs, the insns in the | |
358 | "Pending" list have their dependencies satisfied and move to either | |
359 | the "Ready" list or the "Queued" set depending on whether | |
360 | sufficient time has passed to make them ready. As time passes, | |
361 | insns move from the "Queued" set to the "Ready" list. Insns may | |
362 | move from the "Ready" list to the "Queued" set if they are blocked | |
363 | due to a function unit conflict. | |
364 | ||
365 | The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled | |
366 | insns, i.e., those that are ready, queued, and pending. | |
367 | The "Queued" set (Q) is implemented by the variable `insn_queue'. | |
368 | The "Ready" list (R) is implemented by the variables `ready' and | |
369 | `n_ready'. | |
370 | The "Scheduled" list (S) is the new insn chain built by this pass. | |
371 | ||
372 | The transition (R->S) is implemented in the scheduling loop in | |
373 | `schedule_block' when the best insn to schedule is chosen. | |
374 | The transition (R->Q) is implemented in `queue_insn' when an | |
38e01259 | 375 | insn is found to have a function unit conflict with the already |
8c660648 JL |
376 | committed insns. |
377 | The transitions (P->R and P->Q) are implemented in `schedule_insn' as | |
378 | insns move from the ready list to the scheduled list. | |
379 | The transition (Q->R) is implemented in 'queue_to_insn' as time | |
380 | passes or stalls are introduced. */ | |
381 | ||
382 | /* Implement a circular buffer to delay instructions until sufficient | |
383 | time has passed. INSN_QUEUE_SIZE is a power of two larger than | |
384 | MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the | |
385 | longest time an isnsn may be queued. */ | |
386 | static rtx insn_queue[INSN_QUEUE_SIZE]; | |
387 | static int q_ptr = 0; | |
388 | static int q_size = 0; | |
389 | #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1)) | |
390 | #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1)) | |
391 | ||
392 | /* Vector indexed by INSN_UID giving the minimum clock tick at which | |
393 | the insn becomes ready. This is used to note timing constraints for | |
394 | insns in the pending list. */ | |
395 | static int *insn_tick; | |
396 | #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)]) | |
397 | ||
8c660648 JL |
398 | /* Forward declarations. */ |
399 | static void add_dependence PROTO ((rtx, rtx, enum reg_note)); | |
c88e8206 | 400 | #ifdef HAVE_cc0 |
8c660648 | 401 | static void remove_dependence PROTO ((rtx, rtx)); |
c88e8206 | 402 | #endif |
8c660648 JL |
403 | static rtx find_insn_list PROTO ((rtx, rtx)); |
404 | static int insn_unit PROTO ((rtx)); | |
405 | static unsigned int blockage_range PROTO ((int, rtx)); | |
406 | static void clear_units PROTO ((void)); | |
407 | static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int)); | |
408 | static void schedule_unit PROTO ((int, rtx, int)); | |
409 | static int actual_hazard PROTO ((int, rtx, int, int)); | |
410 | static int potential_hazard PROTO ((int, rtx, int)); | |
411 | static int insn_cost PROTO ((rtx, rtx, rtx)); | |
412 | static int priority PROTO ((rtx)); | |
413 | static void free_pending_lists PROTO ((void)); | |
414 | static void add_insn_mem_dependence PROTO ((rtx *, rtx *, rtx, rtx)); | |
415 | static void flush_pending_lists PROTO ((rtx, int)); | |
416 | static void sched_analyze_1 PROTO ((rtx, rtx)); | |
417 | static void sched_analyze_2 PROTO ((rtx, rtx)); | |
418 | static void sched_analyze_insn PROTO ((rtx, rtx, rtx)); | |
419 | static void sched_analyze PROTO ((rtx, rtx)); | |
e1b6684c | 420 | static int rank_for_schedule PROTO ((const PTR, const PTR)); |
8c660648 JL |
421 | static void swap_sort PROTO ((rtx *, int)); |
422 | static void queue_insn PROTO ((rtx, int)); | |
423 | static int schedule_insn PROTO ((rtx, rtx *, int, int)); | |
c46a37c4 | 424 | static void find_insn_reg_weight PROTO ((int)); |
5835e573 | 425 | static int schedule_block PROTO ((int, int)); |
5f06c983 | 426 | static char *safe_concat PROTO ((char *, char *, const char *)); |
cc4fe0e2 | 427 | static int insn_issue_delay PROTO ((rtx)); |
cc4fe0e2 | 428 | static void adjust_priority PROTO ((rtx)); |
8c660648 | 429 | |
8c660648 JL |
430 | /* Some insns (e.g. call) are not allowed to move across blocks. */ |
431 | static char *cant_move; | |
432 | #define CANT_MOVE(insn) (cant_move[INSN_UID (insn)]) | |
433 | ||
434 | /* Control flow graph edges are kept in circular lists. */ | |
435 | typedef struct | |
436 | { | |
437 | int from_block; | |
438 | int to_block; | |
439 | int next_in; | |
440 | int next_out; | |
441 | } | |
e881bb1b RH |
442 | haifa_edge; |
443 | static haifa_edge *edge_table; | |
8c660648 JL |
444 | |
445 | #define NEXT_IN(edge) (edge_table[edge].next_in) | |
446 | #define NEXT_OUT(edge) (edge_table[edge].next_out) | |
447 | #define FROM_BLOCK(edge) (edge_table[edge].from_block) | |
448 | #define TO_BLOCK(edge) (edge_table[edge].to_block) | |
449 | ||
63de6c74 MH |
450 | /* Number of edges in the control flow graph. (In fact, larger than |
451 | that by 1, since edge 0 is unused.) */ | |
8c660648 JL |
452 | static int nr_edges; |
453 | ||
63de6c74 | 454 | /* Circular list of incoming/outgoing edges of a block. */ |
8c660648 JL |
455 | static int *in_edges; |
456 | static int *out_edges; | |
457 | ||
458 | #define IN_EDGES(block) (in_edges[block]) | |
459 | #define OUT_EDGES(block) (out_edges[block]) | |
460 | ||
8c660648 JL |
461 | |
462 | ||
168cbdf9 | 463 | static int is_cfg_nonregular PROTO ((void)); |
a2e68776 JL |
464 | static int build_control_flow PROTO ((int_list_ptr *, int_list_ptr *, |
465 | int *, int *)); | |
8c660648 JL |
466 | static void new_edge PROTO ((int, int)); |
467 | ||
468 | ||
469 | /* A region is the main entity for interblock scheduling: insns | |
470 | are allowed to move between blocks in the same region, along | |
471 | control flow graph edges, in the 'up' direction. */ | |
472 | typedef struct | |
473 | { | |
63de6c74 MH |
474 | int rgn_nr_blocks; /* Number of blocks in region. */ |
475 | int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */ | |
8c660648 JL |
476 | } |
477 | region; | |
478 | ||
63de6c74 | 479 | /* Number of regions in the procedure. */ |
8c660648 JL |
480 | static int nr_regions; |
481 | ||
63de6c74 | 482 | /* Table of region descriptions. */ |
8c660648 JL |
483 | static region *rgn_table; |
484 | ||
63de6c74 | 485 | /* Array of lists of regions' blocks. */ |
8c660648 JL |
486 | static int *rgn_bb_table; |
487 | ||
488 | /* Topological order of blocks in the region (if b2 is reachable from | |
63de6c74 MH |
489 | b1, block_to_bb[b2] > block_to_bb[b1]). Note: A basic block is |
490 | always referred to by either block or b, while its topological | |
491 | order name (in the region) is refered to by bb. */ | |
8c660648 JL |
492 | static int *block_to_bb; |
493 | ||
494 | /* The number of the region containing a block. */ | |
495 | static int *containing_rgn; | |
496 | ||
497 | #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks) | |
498 | #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks) | |
499 | #define BLOCK_TO_BB(block) (block_to_bb[block]) | |
500 | #define CONTAINING_RGN(block) (containing_rgn[block]) | |
501 | ||
502 | void debug_regions PROTO ((void)); | |
503 | static void find_single_block_region PROTO ((void)); | |
a2e68776 JL |
504 | static void find_rgns PROTO ((int_list_ptr *, int_list_ptr *, |
505 | int *, int *, sbitmap *)); | |
8c660648 JL |
506 | static int too_large PROTO ((int, int *, int *)); |
507 | ||
508 | extern void debug_live PROTO ((int, int)); | |
509 | ||
510 | /* Blocks of the current region being scheduled. */ | |
511 | static int current_nr_blocks; | |
512 | static int current_blocks; | |
513 | ||
63de6c74 | 514 | /* The mapping from bb to block. */ |
8c660648 JL |
515 | #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)]) |
516 | ||
517 | ||
518 | /* Bit vectors and bitset operations are needed for computations on | |
519 | the control flow graph. */ | |
520 | ||
521 | typedef unsigned HOST_WIDE_INT *bitset; | |
522 | typedef struct | |
523 | { | |
63de6c74 MH |
524 | int *first_member; /* Pointer to the list start in bitlst_table. */ |
525 | int nr_members; /* The number of members of the bit list. */ | |
8c660648 JL |
526 | } |
527 | bitlst; | |
528 | ||
61822835 JL |
529 | static int bitlst_table_last; |
530 | static int bitlst_table_size; | |
8c660648 JL |
531 | static int *bitlst_table; |
532 | ||
533 | static char bitset_member PROTO ((bitset, int, int)); | |
534 | static void extract_bitlst PROTO ((bitset, int, bitlst *)); | |
535 | ||
63de6c74 | 536 | /* Target info declarations. |
8c660648 JL |
537 | |
538 | The block currently being scheduled is referred to as the "target" block, | |
539 | while other blocks in the region from which insns can be moved to the | |
540 | target are called "source" blocks. The candidate structure holds info | |
541 | about such sources: are they valid? Speculative? Etc. */ | |
542 | typedef bitlst bblst; | |
543 | typedef struct | |
544 | { | |
545 | char is_valid; | |
546 | char is_speculative; | |
547 | int src_prob; | |
548 | bblst split_bbs; | |
549 | bblst update_bbs; | |
550 | } | |
551 | candidate; | |
552 | ||
553 | static candidate *candidate_table; | |
554 | ||
555 | /* A speculative motion requires checking live information on the path | |
556 | from 'source' to 'target'. The split blocks are those to be checked. | |
557 | After a speculative motion, live information should be modified in | |
558 | the 'update' blocks. | |
559 | ||
63de6c74 MH |
560 | Lists of split and update blocks for each candidate of the current |
561 | target are in array bblst_table. */ | |
61822835 | 562 | static int *bblst_table, bblst_size, bblst_last; |
8c660648 JL |
563 | |
564 | #define IS_VALID(src) ( candidate_table[src].is_valid ) | |
565 | #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative ) | |
566 | #define SRC_PROB(src) ( candidate_table[src].src_prob ) | |
567 | ||
568 | /* The bb being currently scheduled. */ | |
61822835 | 569 | static int target_bb; |
8c660648 JL |
570 | |
571 | /* List of edges. */ | |
572 | typedef bitlst edgelst; | |
573 | ||
63de6c74 | 574 | /* Target info functions. */ |
8c660648 JL |
575 | static void split_edges PROTO ((int, int, edgelst *)); |
576 | static void compute_trg_info PROTO ((int)); | |
577 | void debug_candidate PROTO ((int)); | |
578 | void debug_candidates PROTO ((int)); | |
579 | ||
580 | ||
581 | /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */ | |
582 | typedef bitset bbset; | |
583 | ||
584 | /* Number of words of the bbset. */ | |
61822835 | 585 | static int bbset_size; |
8c660648 JL |
586 | |
587 | /* Dominators array: dom[i] contains the bbset of dominators of | |
588 | bb i in the region. */ | |
61822835 | 589 | static bbset *dom; |
8c660648 | 590 | |
63de6c74 | 591 | /* bb 0 is the only region entry. */ |
8c660648 JL |
592 | #define IS_RGN_ENTRY(bb) (!bb) |
593 | ||
594 | /* Is bb_src dominated by bb_trg. */ | |
595 | #define IS_DOMINATED(bb_src, bb_trg) \ | |
596 | ( bitset_member (dom[bb_src], bb_trg, bbset_size) ) | |
597 | ||
598 | /* Probability: Prob[i] is a float in [0, 1] which is the probability | |
599 | of bb i relative to the region entry. */ | |
61822835 | 600 | static float *prob; |
8c660648 | 601 | |
63de6c74 | 602 | /* The probability of bb_src, relative to bb_trg. Note, that while the |
8c660648 JL |
603 | 'prob[bb]' is a float in [0, 1], this macro returns an integer |
604 | in [0, 100]. */ | |
605 | #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \ | |
606 | prob[bb_trg]))) | |
607 | ||
608 | /* Bit-set of edges, where bit i stands for edge i. */ | |
609 | typedef bitset edgeset; | |
610 | ||
611 | /* Number of edges in the region. */ | |
61822835 | 612 | static int rgn_nr_edges; |
8c660648 | 613 | |
63de6c74 | 614 | /* Array of size rgn_nr_edges. */ |
61822835 | 615 | static int *rgn_edges; |
8c660648 | 616 | |
63de6c74 | 617 | /* Number of words in an edgeset. */ |
61822835 | 618 | static int edgeset_size; |
8c660648 JL |
619 | |
620 | /* Mapping from each edge in the graph to its number in the rgn. */ | |
61822835 | 621 | static int *edge_to_bit; |
8c660648 JL |
622 | #define EDGE_TO_BIT(edge) (edge_to_bit[edge]) |
623 | ||
624 | /* The split edges of a source bb is different for each target | |
625 | bb. In order to compute this efficiently, the 'potential-split edges' | |
626 | are computed for each bb prior to scheduling a region. This is actually | |
627 | the split edges of each bb relative to the region entry. | |
628 | ||
629 | pot_split[bb] is the set of potential split edges of bb. */ | |
61822835 | 630 | static edgeset *pot_split; |
8c660648 JL |
631 | |
632 | /* For every bb, a set of its ancestor edges. */ | |
61822835 | 633 | static edgeset *ancestor_edges; |
8c660648 JL |
634 | |
635 | static void compute_dom_prob_ps PROTO ((int)); | |
636 | ||
637 | #define ABS_VALUE(x) (((x)<0)?(-(x)):(x)) | |
c88e8206 RH |
638 | #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (BLOCK_NUM (INSN)))) |
639 | #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (BLOCK_NUM (INSN)))) | |
640 | #define INSN_BB(INSN) (BLOCK_TO_BB (BLOCK_NUM (INSN))) | |
8c660648 | 641 | |
63de6c74 | 642 | /* Parameters affecting the decision of rank_for_schedule(). */ |
8c660648 JL |
643 | #define MIN_DIFF_PRIORITY 2 |
644 | #define MIN_PROBABILITY 40 | |
645 | #define MIN_PROB_DIFF 10 | |
646 | ||
63de6c74 | 647 | /* Speculative scheduling functions. */ |
8c660648 JL |
648 | static int check_live_1 PROTO ((int, rtx)); |
649 | static void update_live_1 PROTO ((int, rtx)); | |
5835e573 KG |
650 | static int check_live PROTO ((rtx, int)); |
651 | static void update_live PROTO ((rtx, int)); | |
8c660648 JL |
652 | static void set_spec_fed PROTO ((rtx)); |
653 | static int is_pfree PROTO ((rtx, int, int)); | |
654 | static int find_conditional_protection PROTO ((rtx, int)); | |
655 | static int is_conditionally_protected PROTO ((rtx, int, int)); | |
656 | static int may_trap_exp PROTO ((rtx, int)); | |
ac957f13 | 657 | static int haifa_classify_insn PROTO ((rtx)); |
e009aaf3 | 658 | static int is_prisky PROTO ((rtx, int, int)); |
8c660648 JL |
659 | static int is_exception_free PROTO ((rtx, int, int)); |
660 | ||
661 | static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx)); | |
662 | static void compute_block_forward_dependences PROTO ((int)); | |
663 | static void init_rgn_data_dependences PROTO ((int)); | |
664 | static void add_branch_dependences PROTO ((rtx, rtx)); | |
665 | static void compute_block_backward_dependences PROTO ((int)); | |
666 | void debug_dependencies PROTO ((void)); | |
667 | ||
668 | /* Notes handling mechanism: | |
669 | ========================= | |
670 | Generally, NOTES are saved before scheduling and restored after scheduling. | |
671 | The scheduler distinguishes between three types of notes: | |
672 | ||
673 | (1) LINE_NUMBER notes, generated and used for debugging. Here, | |
674 | before scheduling a region, a pointer to the LINE_NUMBER note is | |
675 | added to the insn following it (in save_line_notes()), and the note | |
676 | is removed (in rm_line_notes() and unlink_line_notes()). After | |
677 | scheduling the region, this pointer is used for regeneration of | |
678 | the LINE_NUMBER note (in restore_line_notes()). | |
679 | ||
680 | (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes: | |
681 | Before scheduling a region, a pointer to the note is added to the insn | |
682 | that follows or precedes it. (This happens as part of the data dependence | |
683 | computation). After scheduling an insn, the pointer contained in it is | |
684 | used for regenerating the corresponding note (in reemit_notes). | |
685 | ||
686 | (3) All other notes (e.g. INSN_DELETED): Before scheduling a block, | |
687 | these notes are put in a list (in rm_other_notes() and | |
688 | unlink_other_notes ()). After scheduling the block, these notes are | |
689 | inserted at the beginning of the block (in schedule_block()). */ | |
690 | ||
691 | static rtx unlink_other_notes PROTO ((rtx, rtx)); | |
692 | static rtx unlink_line_notes PROTO ((rtx, rtx)); | |
693 | static void rm_line_notes PROTO ((int)); | |
694 | static void save_line_notes PROTO ((int)); | |
695 | static void restore_line_notes PROTO ((int)); | |
696 | static void rm_redundant_line_notes PROTO ((void)); | |
697 | static void rm_other_notes PROTO ((rtx, rtx)); | |
698 | static rtx reemit_notes PROTO ((rtx, rtx)); | |
699 | ||
700 | static void get_block_head_tail PROTO ((int, rtx *, rtx *)); | |
701 | ||
c6a754f2 | 702 | static int queue_to_ready PROTO ((rtx [], int)); |
8c660648 | 703 | |
9a8b0889 | 704 | static void debug_ready_list PROTO ((rtx[], int)); |
cc4fe0e2 | 705 | static void init_target_units PROTO ((void)); |
8c660648 | 706 | static void insn_print_units PROTO ((rtx)); |
cc4fe0e2 L |
707 | static int get_visual_tbl_length PROTO ((void)); |
708 | static void init_block_visualization PROTO ((void)); | |
5f06c983 | 709 | static void print_block_visualization PROTO ((int, const char *)); |
8c660648 JL |
710 | static void visualize_scheduled_insns PROTO ((int, int)); |
711 | static void visualize_no_unit PROTO ((rtx)); | |
712 | static void visualize_stall_cycles PROTO ((int, int)); | |
713 | static void print_exp PROTO ((char *, rtx, int)); | |
714 | static void print_value PROTO ((char *, rtx, int)); | |
715 | static void print_pattern PROTO ((char *, rtx, int)); | |
716 | static void print_insn PROTO ((char *, rtx, int)); | |
717 | void debug_reg_vector PROTO ((regset)); | |
718 | ||
719 | static rtx move_insn1 PROTO ((rtx, rtx)); | |
720 | static rtx move_insn PROTO ((rtx, rtx)); | |
721 | static rtx group_leader PROTO ((rtx)); | |
722 | static int set_priorities PROTO ((int)); | |
723 | static void init_rtx_vector PROTO ((rtx **, rtx *, int, int)); | |
724 | static void schedule_region PROTO ((int)); | |
8c660648 JL |
725 | |
726 | #endif /* INSN_SCHEDULING */ | |
727 | \f | |
728 | #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X))) | |
729 | ||
8c660648 JL |
730 | /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the |
731 | LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type | |
732 | of dependence that this link represents. */ | |
733 | ||
734 | static void | |
735 | add_dependence (insn, elem, dep_type) | |
736 | rtx insn; | |
737 | rtx elem; | |
738 | enum reg_note dep_type; | |
739 | { | |
740 | rtx link, next; | |
741 | ||
742 | /* Don't depend an insn on itself. */ | |
743 | if (insn == elem) | |
744 | return; | |
745 | ||
342d9c89 JL |
746 | /* We can get a dependency on deleted insns due to optimizations in |
747 | the register allocation and reloading or due to splitting. Any | |
748 | such dependency is useless and can be ignored. */ | |
749 | if (GET_CODE (elem) == NOTE) | |
750 | return; | |
751 | ||
8c660648 JL |
752 | /* If elem is part of a sequence that must be scheduled together, then |
753 | make the dependence point to the last insn of the sequence. | |
754 | When HAVE_cc0, it is possible for NOTEs to exist between users and | |
755 | setters of the condition codes, so we must skip past notes here. | |
756 | Otherwise, NOTEs are impossible here. */ | |
757 | ||
758 | next = NEXT_INSN (elem); | |
759 | ||
760 | #ifdef HAVE_cc0 | |
761 | while (next && GET_CODE (next) == NOTE) | |
762 | next = NEXT_INSN (next); | |
763 | #endif | |
764 | ||
765 | if (next && SCHED_GROUP_P (next) | |
766 | && GET_CODE (next) != CODE_LABEL) | |
767 | { | |
768 | /* Notes will never intervene here though, so don't bother checking | |
769 | for them. */ | |
770 | /* We must reject CODE_LABELs, so that we don't get confused by one | |
771 | that has LABEL_PRESERVE_P set, which is represented by the same | |
772 | bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be | |
773 | SCHED_GROUP_P. */ | |
774 | while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next)) | |
775 | && GET_CODE (NEXT_INSN (next)) != CODE_LABEL) | |
776 | next = NEXT_INSN (next); | |
777 | ||
778 | /* Again, don't depend an insn on itself. */ | |
779 | if (insn == next) | |
780 | return; | |
781 | ||
782 | /* Make the dependence to NEXT, the last insn of the group, instead | |
783 | of the original ELEM. */ | |
784 | elem = next; | |
785 | } | |
786 | ||
787 | #ifdef INSN_SCHEDULING | |
788 | /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.) | |
789 | No need for interblock dependences with calls, since | |
790 | calls are not moved between blocks. Note: the edge where | |
791 | elem is a CALL is still required. */ | |
792 | if (GET_CODE (insn) == CALL_INSN | |
793 | && (INSN_BB (elem) != INSN_BB (insn))) | |
794 | return; | |
795 | ||
8c660648 | 796 | |
356edbd7 JL |
797 | /* If we already have a true dependency for ELEM, then we do not |
798 | need to do anything. Avoiding the list walk below can cut | |
799 | compile times dramatically for some code. */ | |
aae0390e JL |
800 | if (true_dependency_cache |
801 | && TEST_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem))) | |
356edbd7 | 802 | return; |
35c95c5a | 803 | #endif |
356edbd7 | 804 | |
8c660648 JL |
805 | /* Check that we don't already have this dependence. */ |
806 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
807 | if (XEXP (link, 0) == elem) | |
808 | { | |
809 | /* If this is a more restrictive type of dependence than the existing | |
810 | one, then change the existing dependence to this type. */ | |
811 | if ((int) dep_type < (int) REG_NOTE_KIND (link)) | |
812 | PUT_REG_NOTE_KIND (link, dep_type); | |
356edbd7 | 813 | |
35c95c5a | 814 | #ifdef INSN_SCHEDULING |
356edbd7 JL |
815 | /* If we are adding a true dependency to INSN's LOG_LINKs, then |
816 | note that in the bitmap cache of true dependency information. */ | |
aae0390e | 817 | if ((int)dep_type == 0 && true_dependency_cache) |
356edbd7 | 818 | SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)); |
35c95c5a | 819 | #endif |
8c660648 JL |
820 | return; |
821 | } | |
822 | /* Might want to check one level of transitivity to save conses. */ | |
823 | ||
ebb7b10b RH |
824 | link = alloc_INSN_LIST (elem, LOG_LINKS (insn)); |
825 | LOG_LINKS (insn) = link; | |
826 | ||
8c660648 JL |
827 | /* Insn dependency, not data dependency. */ |
828 | PUT_REG_NOTE_KIND (link, dep_type); | |
8c660648 JL |
829 | } |
830 | ||
c88e8206 | 831 | #ifdef HAVE_cc0 |
8c660648 JL |
832 | /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS |
833 | of INSN. Abort if not found. */ | |
834 | ||
835 | static void | |
836 | remove_dependence (insn, elem) | |
837 | rtx insn; | |
838 | rtx elem; | |
839 | { | |
ebb7b10b | 840 | rtx prev, link, next; |
8c660648 JL |
841 | int found = 0; |
842 | ||
ebb7b10b | 843 | for (prev = 0, link = LOG_LINKS (insn); link; link = next) |
8c660648 | 844 | { |
ebb7b10b | 845 | next = XEXP (link, 1); |
8c660648 JL |
846 | if (XEXP (link, 0) == elem) |
847 | { | |
848 | if (prev) | |
ebb7b10b | 849 | XEXP (prev, 1) = next; |
8c660648 | 850 | else |
ebb7b10b | 851 | LOG_LINKS (insn) = next; |
356edbd7 | 852 | |
35c95c5a | 853 | #ifdef INSN_SCHEDULING |
356edbd7 JL |
854 | /* If we are removing a true dependency from the LOG_LINKS list, |
855 | make sure to remove it from the cache too. */ | |
aae0390e | 856 | if (REG_NOTE_KIND (link) == 0 && true_dependency_cache) |
356edbd7 JL |
857 | RESET_BIT (true_dependency_cache[INSN_LUID (insn)], |
858 | INSN_LUID (elem)); | |
35c95c5a | 859 | #endif |
356edbd7 | 860 | |
5a4f6418 | 861 | free_INSN_LIST_node (link); |
ebb7b10b | 862 | |
8c660648 JL |
863 | found = 1; |
864 | } | |
6d8ccdbb JL |
865 | else |
866 | prev = link; | |
8c660648 JL |
867 | } |
868 | ||
869 | if (!found) | |
870 | abort (); | |
871 | return; | |
872 | } | |
c88e8206 | 873 | #endif /* HAVE_cc0 */ |
8c660648 JL |
874 | \f |
875 | #ifndef INSN_SCHEDULING | |
876 | void | |
877 | schedule_insns (dump_file) | |
878 | FILE *dump_file; | |
879 | { | |
880 | } | |
881 | #else | |
882 | #ifndef __GNUC__ | |
883 | #define __inline | |
884 | #endif | |
885 | ||
cbb13457 MM |
886 | #ifndef HAIFA_INLINE |
887 | #define HAIFA_INLINE __inline | |
888 | #endif | |
889 | ||
8c660648 JL |
890 | /* Computation of memory dependencies. */ |
891 | ||
892 | /* The *_insns and *_mems are paired lists. Each pending memory operation | |
893 | will have a pointer to the MEM rtx on one list and a pointer to the | |
894 | containing insn on the other list in the same place in the list. */ | |
895 | ||
896 | /* We can't use add_dependence like the old code did, because a single insn | |
897 | may have multiple memory accesses, and hence needs to be on the list | |
898 | once for each memory access. Add_dependence won't let you add an insn | |
899 | to a list more than once. */ | |
900 | ||
901 | /* An INSN_LIST containing all insns with pending read operations. */ | |
902 | static rtx pending_read_insns; | |
903 | ||
904 | /* An EXPR_LIST containing all MEM rtx's which are pending reads. */ | |
905 | static rtx pending_read_mems; | |
906 | ||
907 | /* An INSN_LIST containing all insns with pending write operations. */ | |
908 | static rtx pending_write_insns; | |
909 | ||
910 | /* An EXPR_LIST containing all MEM rtx's which are pending writes. */ | |
911 | static rtx pending_write_mems; | |
912 | ||
913 | /* Indicates the combined length of the two pending lists. We must prevent | |
914 | these lists from ever growing too large since the number of dependencies | |
915 | produced is at least O(N*N), and execution time is at least O(4*N*N), as | |
916 | a function of the length of these pending lists. */ | |
917 | ||
918 | static int pending_lists_length; | |
919 | ||
8c660648 JL |
920 | /* The last insn upon which all memory references must depend. |
921 | This is an insn which flushed the pending lists, creating a dependency | |
922 | between it and all previously pending memory references. This creates | |
923 | a barrier (or a checkpoint) which no memory reference is allowed to cross. | |
924 | ||
925 | This includes all non constant CALL_INSNs. When we do interprocedural | |
926 | alias analysis, this restriction can be relaxed. | |
927 | This may also be an INSN that writes memory if the pending lists grow | |
928 | too large. */ | |
929 | ||
930 | static rtx last_pending_memory_flush; | |
931 | ||
932 | /* The last function call we have seen. All hard regs, and, of course, | |
933 | the last function call, must depend on this. */ | |
934 | ||
935 | static rtx last_function_call; | |
936 | ||
937 | /* The LOG_LINKS field of this is a list of insns which use a pseudo register | |
938 | that does not already cross a call. We create dependencies between each | |
939 | of those insn and the next call insn, to ensure that they won't cross a call | |
940 | after scheduling is done. */ | |
941 | ||
942 | static rtx sched_before_next_call; | |
943 | ||
944 | /* Pointer to the last instruction scheduled. Used by rank_for_schedule, | |
945 | so that insns independent of the last scheduled insn will be preferred | |
946 | over dependent instructions. */ | |
947 | ||
948 | static rtx last_scheduled_insn; | |
949 | ||
950 | /* Data structures for the computation of data dependences in a regions. We | |
951 | keep one copy of each of the declared above variables for each bb in the | |
952 | region. Before analyzing the data dependences for a bb, its variables | |
953 | are initialized as a function of the variables of its predecessors. When | |
954 | the analysis for a bb completes, we save the contents of each variable X | |
955 | to a corresponding bb_X[bb] variable. For example, pending_read_insns is | |
956 | copied to bb_pending_read_insns[bb]. Another change is that few | |
957 | variables are now a list of insns rather than a single insn: | |
958 | last_pending_memory_flash, last_function_call, reg_last_sets. The | |
959 | manipulation of these variables was changed appropriately. */ | |
960 | ||
961 | static rtx **bb_reg_last_uses; | |
962 | static rtx **bb_reg_last_sets; | |
28c95eff | 963 | static rtx **bb_reg_last_clobbers; |
8c660648 JL |
964 | |
965 | static rtx *bb_pending_read_insns; | |
966 | static rtx *bb_pending_read_mems; | |
967 | static rtx *bb_pending_write_insns; | |
968 | static rtx *bb_pending_write_mems; | |
969 | static int *bb_pending_lists_length; | |
970 | ||
971 | static rtx *bb_last_pending_memory_flush; | |
972 | static rtx *bb_last_function_call; | |
973 | static rtx *bb_sched_before_next_call; | |
974 | ||
63de6c74 | 975 | /* Functions for construction of the control flow graph. */ |
8c660648 JL |
976 | |
977 | /* Return 1 if control flow graph should not be constructed, 0 otherwise. | |
168cbdf9 | 978 | |
8c660648 | 979 | We decide not to build the control flow graph if there is possibly more |
168cbdf9 JL |
980 | than one entry to the function, if computed branches exist, of if we |
981 | have nonlocal gotos. */ | |
8c660648 | 982 | |
168cbdf9 | 983 | static int |
8c660648 JL |
984 | is_cfg_nonregular () |
985 | { | |
986 | int b; | |
987 | rtx insn; | |
988 | RTX_CODE code; | |
989 | ||
168cbdf9 JL |
990 | /* If we have a label that could be the target of a nonlocal goto, then |
991 | the cfg is not well structured. */ | |
e881bb1b | 992 | if (nonlocal_goto_handler_labels) |
168cbdf9 | 993 | return 1; |
8c660648 | 994 | |
168cbdf9 | 995 | /* If we have any forced labels, then the cfg is not well structured. */ |
8c660648 | 996 | if (forced_labels) |
168cbdf9 | 997 | return 1; |
8c660648 | 998 | |
4d1d8045 BS |
999 | /* If this function has a computed jump, then we consider the cfg |
1000 | not well structured. */ | |
1001 | if (current_function_has_computed_jump) | |
1002 | return 1; | |
1003 | ||
168cbdf9 JL |
1004 | /* If we have exception handlers, then we consider the cfg not well |
1005 | structured. ?!? We should be able to handle this now that flow.c | |
1006 | computes an accurate cfg for EH. */ | |
8c660648 | 1007 | if (exception_handler_labels) |
168cbdf9 | 1008 | return 1; |
8c660648 | 1009 | |
168cbdf9 JL |
1010 | /* If we have non-jumping insns which refer to labels, then we consider |
1011 | the cfg not well structured. */ | |
63de6c74 | 1012 | /* Check for labels referred to other thn by jumps. */ |
8c660648 | 1013 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 1014 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
1015 | { |
1016 | code = GET_CODE (insn); | |
1017 | if (GET_RTX_CLASS (code) == 'i') | |
1018 | { | |
1019 | rtx note; | |
1020 | ||
1021 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1022 | if (REG_NOTE_KIND (note) == REG_LABEL) | |
168cbdf9 | 1023 | return 1; |
8c660648 JL |
1024 | } |
1025 | ||
3b413743 | 1026 | if (insn == BLOCK_END (b)) |
8c660648 JL |
1027 | break; |
1028 | } | |
1029 | ||
168cbdf9 | 1030 | /* All the tests passed. Consider the cfg well structured. */ |
8c660648 JL |
1031 | return 0; |
1032 | } | |
1033 | ||
5ece9746 JL |
1034 | /* Build the control flow graph and set nr_edges. |
1035 | ||
1036 | Instead of trying to build a cfg ourselves, we rely on flow to | |
168cbdf9 | 1037 | do it for us. Stamp out useless code (and bug) duplication. |
8c660648 | 1038 | |
168cbdf9 JL |
1039 | Return nonzero if an irregularity in the cfg is found which would |
1040 | prevent cross block scheduling. */ | |
1041 | ||
1042 | static int | |
a2e68776 JL |
1043 | build_control_flow (s_preds, s_succs, num_preds, num_succs) |
1044 | int_list_ptr *s_preds; | |
1045 | int_list_ptr *s_succs; | |
1046 | int *num_preds; | |
1047 | int *num_succs; | |
8c660648 | 1048 | { |
081f5e7e | 1049 | int i; |
5ece9746 | 1050 | int_list_ptr succ; |
168cbdf9 | 1051 | int unreachable; |
5ece9746 | 1052 | |
168cbdf9 JL |
1053 | /* Count the number of edges in the cfg. */ |
1054 | nr_edges = 0; | |
1055 | unreachable = 0; | |
1056 | for (i = 0; i < n_basic_blocks; i++) | |
1057 | { | |
1058 | nr_edges += num_succs[i]; | |
15ebe47d JL |
1059 | |
1060 | /* Unreachable loops with more than one basic block are detected | |
1061 | during the DFS traversal in find_rgns. | |
1062 | ||
1063 | Unreachable loops with a single block are detected here. This | |
1064 | test is redundant with the one in find_rgns, but it's much | |
1065 | cheaper to go ahead and catch the trivial case here. */ | |
a8afd67b JW |
1066 | if (num_preds[i] == 0 |
1067 | || (num_preds[i] == 1 && INT_LIST_VAL (s_preds[i]) == i)) | |
168cbdf9 JL |
1068 | unreachable = 1; |
1069 | } | |
1070 | ||
1071 | /* Account for entry/exit edges. */ | |
1072 | nr_edges += 2; | |
1073 | ||
3de90026 RH |
1074 | in_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); |
1075 | out_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); | |
1076 | edge_table = (haifa_edge *) xcalloc (nr_edges, sizeof (haifa_edge)); | |
168cbdf9 | 1077 | |
8c660648 JL |
1078 | nr_edges = 0; |
1079 | for (i = 0; i < n_basic_blocks; i++) | |
5ece9746 JL |
1080 | for (succ = s_succs[i]; succ; succ = succ->next) |
1081 | { | |
1082 | if (INT_LIST_VAL (succ) != EXIT_BLOCK) | |
1083 | new_edge (i, INT_LIST_VAL (succ)); | |
1084 | } | |
8c660648 | 1085 | |
63de6c74 | 1086 | /* Increment by 1, since edge 0 is unused. */ |
8c660648 JL |
1087 | nr_edges++; |
1088 | ||
168cbdf9 | 1089 | return unreachable; |
8c660648 JL |
1090 | } |
1091 | ||
1092 | ||
5ece9746 | 1093 | /* Record an edge in the control flow graph from SOURCE to TARGET. |
8c660648 | 1094 | |
5ece9746 JL |
1095 | In theory, this is redundant with the s_succs computed above, but |
1096 | we have not converted all of haifa to use information from the | |
1097 | integer lists. */ | |
8c660648 JL |
1098 | |
1099 | static void | |
1100 | new_edge (source, target) | |
1101 | int source, target; | |
1102 | { | |
1103 | int e, next_edge; | |
1104 | int curr_edge, fst_edge; | |
1105 | ||
63de6c74 | 1106 | /* Check for duplicates. */ |
8c660648 JL |
1107 | fst_edge = curr_edge = OUT_EDGES (source); |
1108 | while (curr_edge) | |
1109 | { | |
1110 | if (FROM_BLOCK (curr_edge) == source | |
1111 | && TO_BLOCK (curr_edge) == target) | |
1112 | { | |
1113 | return; | |
1114 | } | |
1115 | ||
1116 | curr_edge = NEXT_OUT (curr_edge); | |
1117 | ||
1118 | if (fst_edge == curr_edge) | |
1119 | break; | |
1120 | } | |
1121 | ||
1122 | e = ++nr_edges; | |
1123 | ||
1124 | FROM_BLOCK (e) = source; | |
1125 | TO_BLOCK (e) = target; | |
1126 | ||
1127 | if (OUT_EDGES (source)) | |
1128 | { | |
1129 | next_edge = NEXT_OUT (OUT_EDGES (source)); | |
1130 | NEXT_OUT (OUT_EDGES (source)) = e; | |
1131 | NEXT_OUT (e) = next_edge; | |
1132 | } | |
1133 | else | |
1134 | { | |
1135 | OUT_EDGES (source) = e; | |
1136 | NEXT_OUT (e) = e; | |
1137 | } | |
1138 | ||
1139 | if (IN_EDGES (target)) | |
1140 | { | |
1141 | next_edge = NEXT_IN (IN_EDGES (target)); | |
1142 | NEXT_IN (IN_EDGES (target)) = e; | |
1143 | NEXT_IN (e) = next_edge; | |
1144 | } | |
1145 | else | |
1146 | { | |
1147 | IN_EDGES (target) = e; | |
1148 | NEXT_IN (e) = e; | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | ||
1153 | /* BITSET macros for operations on the control flow graph. */ | |
1154 | ||
63de6c74 | 1155 | /* Compute bitwise union of two bitsets. */ |
8c660648 JL |
1156 | #define BITSET_UNION(set1, set2, len) \ |
1157 | do { register bitset tp = set1, sp = set2; \ | |
1158 | register int i; \ | |
1159 | for (i = 0; i < len; i++) \ | |
1160 | *(tp++) |= *(sp++); } while (0) | |
1161 | ||
63de6c74 | 1162 | /* Compute bitwise intersection of two bitsets. */ |
8c660648 JL |
1163 | #define BITSET_INTER(set1, set2, len) \ |
1164 | do { register bitset tp = set1, sp = set2; \ | |
1165 | register int i; \ | |
1166 | for (i = 0; i < len; i++) \ | |
1167 | *(tp++) &= *(sp++); } while (0) | |
1168 | ||
63de6c74 | 1169 | /* Compute bitwise difference of two bitsets. */ |
8c660648 JL |
1170 | #define BITSET_DIFFER(set1, set2, len) \ |
1171 | do { register bitset tp = set1, sp = set2; \ | |
1172 | register int i; \ | |
1173 | for (i = 0; i < len; i++) \ | |
1174 | *(tp++) &= ~*(sp++); } while (0) | |
1175 | ||
63de6c74 | 1176 | /* Inverts every bit of bitset 'set'. */ |
8c660648 JL |
1177 | #define BITSET_INVERT(set, len) \ |
1178 | do { register bitset tmpset = set; \ | |
1179 | register int i; \ | |
1180 | for (i = 0; i < len; i++, tmpset++) \ | |
1181 | *tmpset = ~*tmpset; } while (0) | |
1182 | ||
1183 | /* Turn on the index'th bit in bitset set. */ | |
1184 | #define BITSET_ADD(set, index, len) \ | |
1185 | { \ | |
1186 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1187 | abort (); \ | |
1188 | else \ | |
1189 | set[index/HOST_BITS_PER_WIDE_INT] |= \ | |
1190 | 1 << (index % HOST_BITS_PER_WIDE_INT); \ | |
1191 | } | |
1192 | ||
1193 | /* Turn off the index'th bit in set. */ | |
1194 | #define BITSET_REMOVE(set, index, len) \ | |
1195 | { \ | |
1196 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1197 | abort (); \ | |
1198 | else \ | |
1199 | set[index/HOST_BITS_PER_WIDE_INT] &= \ | |
1200 | ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \ | |
1201 | } | |
1202 | ||
1203 | ||
63de6c74 | 1204 | /* Check if the index'th bit in bitset set is on. */ |
8c660648 JL |
1205 | |
1206 | static char | |
1207 | bitset_member (set, index, len) | |
1208 | bitset set; | |
1209 | int index, len; | |
1210 | { | |
1211 | if (index >= HOST_BITS_PER_WIDE_INT * len) | |
1212 | abort (); | |
1213 | return (set[index / HOST_BITS_PER_WIDE_INT] & | |
1214 | 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0; | |
1215 | } | |
1216 | ||
1217 | ||
1218 | /* Translate a bit-set SET to a list BL of the bit-set members. */ | |
1219 | ||
1220 | static void | |
1221 | extract_bitlst (set, len, bl) | |
1222 | bitset set; | |
1223 | int len; | |
1224 | bitlst *bl; | |
1225 | { | |
1226 | int i, j, offset; | |
1227 | unsigned HOST_WIDE_INT word; | |
1228 | ||
63de6c74 | 1229 | /* bblst table space is reused in each call to extract_bitlst. */ |
8c660648 JL |
1230 | bitlst_table_last = 0; |
1231 | ||
1232 | bl->first_member = &bitlst_table[bitlst_table_last]; | |
1233 | bl->nr_members = 0; | |
1234 | ||
1235 | for (i = 0; i < len; i++) | |
1236 | { | |
1237 | word = set[i]; | |
1238 | offset = i * HOST_BITS_PER_WIDE_INT; | |
1239 | for (j = 0; word; j++) | |
1240 | { | |
1241 | if (word & 1) | |
1242 | { | |
1243 | bitlst_table[bitlst_table_last++] = offset; | |
1244 | (bl->nr_members)++; | |
1245 | } | |
1246 | word >>= 1; | |
1247 | ++offset; | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | } | |
1252 | ||
1253 | ||
63de6c74 | 1254 | /* Functions for the construction of regions. */ |
8c660648 JL |
1255 | |
1256 | /* Print the regions, for debugging purposes. Callable from debugger. */ | |
1257 | ||
1258 | void | |
1259 | debug_regions () | |
1260 | { | |
1261 | int rgn, bb; | |
1262 | ||
1263 | fprintf (dump, "\n;; ------------ REGIONS ----------\n\n"); | |
1264 | for (rgn = 0; rgn < nr_regions; rgn++) | |
1265 | { | |
1266 | fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn, | |
1267 | rgn_table[rgn].rgn_nr_blocks); | |
1268 | fprintf (dump, ";;\tbb/block: "); | |
1269 | ||
1270 | for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++) | |
1271 | { | |
1272 | current_blocks = RGN_BLOCKS (rgn); | |
1273 | ||
1274 | if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb))) | |
1275 | abort (); | |
1276 | ||
1277 | fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb)); | |
1278 | } | |
1279 | ||
1280 | fprintf (dump, "\n\n"); | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | ||
1285 | /* Build a single block region for each basic block in the function. | |
1286 | This allows for using the same code for interblock and basic block | |
1287 | scheduling. */ | |
1288 | ||
1289 | static void | |
1290 | find_single_block_region () | |
1291 | { | |
1292 | int i; | |
1293 | ||
1294 | for (i = 0; i < n_basic_blocks; i++) | |
1295 | { | |
1296 | rgn_bb_table[i] = i; | |
1297 | RGN_NR_BLOCKS (i) = 1; | |
1298 | RGN_BLOCKS (i) = i; | |
1299 | CONTAINING_RGN (i) = i; | |
1300 | BLOCK_TO_BB (i) = 0; | |
1301 | } | |
1302 | nr_regions = n_basic_blocks; | |
1303 | } | |
1304 | ||
1305 | ||
1306 | /* Update number of blocks and the estimate for number of insns | |
1307 | in the region. Return 1 if the region is "too large" for interblock | |
1308 | scheduling (compile time considerations), otherwise return 0. */ | |
1309 | ||
1310 | static int | |
1311 | too_large (block, num_bbs, num_insns) | |
1312 | int block, *num_bbs, *num_insns; | |
1313 | { | |
1314 | (*num_bbs)++; | |
3b413743 RH |
1315 | (*num_insns) += (INSN_LUID (BLOCK_END (block)) - |
1316 | INSN_LUID (BLOCK_HEAD (block))); | |
cc132865 | 1317 | if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS)) |
8c660648 JL |
1318 | return 1; |
1319 | else | |
1320 | return 0; | |
1321 | } | |
1322 | ||
1323 | ||
1324 | /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk] | |
1325 | is still an inner loop. Put in max_hdr[blk] the header of the most inner | |
1326 | loop containing blk. */ | |
1327 | #define UPDATE_LOOP_RELATIONS(blk, hdr) \ | |
1328 | { \ | |
1329 | if (max_hdr[blk] == -1) \ | |
1330 | max_hdr[blk] = hdr; \ | |
1331 | else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \ | |
a2e68776 | 1332 | RESET_BIT (inner, hdr); \ |
8c660648 JL |
1333 | else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \ |
1334 | { \ | |
a2e68776 | 1335 | RESET_BIT (inner,max_hdr[blk]); \ |
8c660648 JL |
1336 | max_hdr[blk] = hdr; \ |
1337 | } \ | |
1338 | } | |
1339 | ||
1340 | ||
a2e68776 JL |
1341 | /* Find regions for interblock scheduling. |
1342 | ||
1343 | A region for scheduling can be: | |
1344 | ||
1345 | * A loop-free procedure, or | |
1346 | ||
1347 | * A reducible inner loop, or | |
1348 | ||
1349 | * A basic block not contained in any other region. | |
1350 | ||
1351 | ||
1352 | ?!? In theory we could build other regions based on extended basic | |
1353 | blocks or reverse extended basic blocks. Is it worth the trouble? | |
1354 | ||
1355 | Loop blocks that form a region are put into the region's block list | |
1356 | in topological order. | |
1357 | ||
1358 | This procedure stores its results into the following global (ick) variables | |
1359 | ||
1360 | * rgn_nr | |
1361 | * rgn_table | |
1362 | * rgn_bb_table | |
1363 | * block_to_bb | |
1364 | * containing region | |
1365 | ||
1366 | ||
1367 | We use dominator relationships to avoid making regions out of non-reducible | |
1368 | loops. | |
8c660648 | 1369 | |
a2e68776 JL |
1370 | This procedure needs to be converted to work on pred/succ lists instead |
1371 | of edge tables. That would simplify it somewhat. */ | |
8c660648 JL |
1372 | |
1373 | static void | |
a2e68776 JL |
1374 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom) |
1375 | int_list_ptr *s_preds; | |
1376 | int_list_ptr *s_succs; | |
1377 | int *num_preds; | |
1378 | int *num_succs; | |
1379 | sbitmap *dom; | |
8c660648 JL |
1380 | { |
1381 | int *max_hdr, *dfs_nr, *stack, *queue, *degree; | |
a2e68776 | 1382 | char no_loops = 1; |
487a6e06 | 1383 | int node, child, loop_head, i, head, tail; |
8c660648 | 1384 | int count = 0, sp, idx = 0, current_edge = out_edges[0]; |
15ebe47d | 1385 | int num_bbs, num_insns, unreachable; |
8c660648 | 1386 | int too_large_failure; |
8c660648 | 1387 | |
a2e68776 JL |
1388 | /* Note if an edge has been passed. */ |
1389 | sbitmap passed; | |
1390 | ||
1391 | /* Note if a block is a natural loop header. */ | |
1392 | sbitmap header; | |
1393 | ||
1394 | /* Note if a block is an natural inner loop header. */ | |
1395 | sbitmap inner; | |
1396 | ||
1397 | /* Note if a block is in the block queue. */ | |
1398 | sbitmap in_queue; | |
1399 | ||
cc132865 JL |
1400 | /* Note if a block is in the block queue. */ |
1401 | sbitmap in_stack; | |
1402 | ||
a2e68776 JL |
1403 | /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops |
1404 | and a mapping from block to its loop header (if the block is contained | |
1405 | in a loop, else -1). | |
1406 | ||
1407 | Store results in HEADER, INNER, and MAX_HDR respectively, these will | |
1408 | be used as inputs to the second traversal. | |
1409 | ||
1410 | STACK, SP and DFS_NR are only used during the first traversal. */ | |
1411 | ||
1412 | /* Allocate and initialize variables for the first traversal. */ | |
8c660648 JL |
1413 | max_hdr = (int *) alloca (n_basic_blocks * sizeof (int)); |
1414 | dfs_nr = (int *) alloca (n_basic_blocks * sizeof (int)); | |
52b7724b | 1415 | bzero ((char *) dfs_nr, n_basic_blocks * sizeof (int)); |
8c660648 | 1416 | stack = (int *) alloca (nr_edges * sizeof (int)); |
8c660648 | 1417 | |
a2e68776 JL |
1418 | inner = sbitmap_alloc (n_basic_blocks); |
1419 | sbitmap_ones (inner); | |
1420 | ||
1421 | header = sbitmap_alloc (n_basic_blocks); | |
1422 | sbitmap_zero (header); | |
8c660648 | 1423 | |
a2e68776 JL |
1424 | passed = sbitmap_alloc (nr_edges); |
1425 | sbitmap_zero (passed); | |
1426 | ||
1427 | in_queue = sbitmap_alloc (n_basic_blocks); | |
1428 | sbitmap_zero (in_queue); | |
8c660648 | 1429 | |
cc132865 JL |
1430 | in_stack = sbitmap_alloc (n_basic_blocks); |
1431 | sbitmap_zero (in_stack); | |
1432 | ||
8c660648 | 1433 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 | 1434 | max_hdr[i] = -1; |
8c660648 | 1435 | |
a2e68776 | 1436 | /* DFS traversal to find inner loops in the cfg. */ |
8c660648 | 1437 | |
8c660648 JL |
1438 | sp = -1; |
1439 | while (1) | |
1440 | { | |
a2e68776 | 1441 | if (current_edge == 0 || TEST_BIT (passed, current_edge)) |
8c660648 | 1442 | { |
a2e68776 | 1443 | /* We have reached a leaf node or a node that was already |
cc132865 | 1444 | processed. Pop edges off the stack until we find |
a2e68776 JL |
1445 | an edge that has not yet been processed. */ |
1446 | while (sp >= 0 | |
1447 | && (current_edge == 0 || TEST_BIT (passed, current_edge))) | |
8c660648 | 1448 | { |
a2e68776 | 1449 | /* Pop entry off the stack. */ |
8c660648 JL |
1450 | current_edge = stack[sp--]; |
1451 | node = FROM_BLOCK (current_edge); | |
1452 | child = TO_BLOCK (current_edge); | |
cc132865 JL |
1453 | RESET_BIT (in_stack, child); |
1454 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) | |
8c660648 JL |
1455 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
1456 | current_edge = NEXT_OUT (current_edge); | |
1457 | } | |
1458 | ||
a2e68776 JL |
1459 | /* See if have finished the DFS tree traversal. */ |
1460 | if (sp < 0 && TEST_BIT (passed, current_edge)) | |
8c660648 | 1461 | break; |
a2e68776 JL |
1462 | |
1463 | /* Nope, continue the traversal with the popped node. */ | |
8c660648 JL |
1464 | continue; |
1465 | } | |
1466 | ||
a2e68776 | 1467 | /* Process a node. */ |
8c660648 | 1468 | node = FROM_BLOCK (current_edge); |
8c660648 | 1469 | child = TO_BLOCK (current_edge); |
cc132865 | 1470 | SET_BIT (in_stack, node); |
a2e68776 | 1471 | dfs_nr[node] = ++count; |
8c660648 | 1472 | |
cc132865 JL |
1473 | /* If the successor is in the stack, then we've found a loop. |
1474 | Mark the loop, if it is not a natural loop, then it will | |
1475 | be rejected during the second traversal. */ | |
1476 | if (TEST_BIT (in_stack, child)) | |
8c660648 JL |
1477 | { |
1478 | no_loops = 0; | |
a2e68776 | 1479 | SET_BIT (header, child); |
8c660648 | 1480 | UPDATE_LOOP_RELATIONS (node, child); |
a2e68776 | 1481 | SET_BIT (passed, current_edge); |
8c660648 JL |
1482 | current_edge = NEXT_OUT (current_edge); |
1483 | continue; | |
1484 | } | |
1485 | ||
a2e68776 JL |
1486 | /* If the child was already visited, then there is no need to visit |
1487 | it again. Just update the loop relationships and restart | |
1488 | with a new edge. */ | |
8c660648 JL |
1489 | if (dfs_nr[child]) |
1490 | { | |
cc132865 | 1491 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) |
8c660648 | 1492 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
a2e68776 | 1493 | SET_BIT (passed, current_edge); |
8c660648 JL |
1494 | current_edge = NEXT_OUT (current_edge); |
1495 | continue; | |
1496 | } | |
1497 | ||
a2e68776 | 1498 | /* Push an entry on the stack and continue DFS traversal. */ |
8c660648 | 1499 | stack[++sp] = current_edge; |
a2e68776 | 1500 | SET_BIT (passed, current_edge); |
8c660648 | 1501 | current_edge = OUT_EDGES (child); |
50f71e6f JL |
1502 | |
1503 | /* This is temporary until haifa is converted to use rth's new | |
1504 | cfg routines which have true entry/exit blocks and the | |
1505 | appropriate edges from/to those blocks. | |
1506 | ||
1507 | Generally we update dfs_nr for a node when we process its | |
1508 | out edge. However, if the node has no out edge then we will | |
1509 | not set dfs_nr for that node. This can confuse the scheduler | |
1510 | into thinking that we have unreachable blocks, which in turn | |
1511 | disables cross block scheduling. | |
1512 | ||
1513 | So, if we have a node with no out edges, go ahead and mark it | |
1514 | as reachable now. */ | |
1515 | if (current_edge == 0) | |
1516 | dfs_nr[child] = ++count; | |
a2e68776 | 1517 | } |
8c660648 | 1518 | |
15ebe47d JL |
1519 | /* Another check for unreachable blocks. The earlier test in |
1520 | is_cfg_nonregular only finds unreachable blocks that do not | |
1521 | form a loop. | |
a2e68776 | 1522 | |
15ebe47d JL |
1523 | The DFS traversal will mark every block that is reachable from |
1524 | the entry node by placing a nonzero value in dfs_nr. Thus if | |
1525 | dfs_nr is zero for any block, then it must be unreachable. */ | |
1526 | unreachable = 0; | |
1527 | for (i = 0; i < n_basic_blocks; i++) | |
1528 | if (dfs_nr[i] == 0) | |
1529 | { | |
1530 | unreachable = 1; | |
1531 | break; | |
1532 | } | |
a2e68776 JL |
1533 | |
1534 | /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array | |
1535 | to hold degree counts. */ | |
1536 | degree = dfs_nr; | |
8c660648 | 1537 | |
63de6c74 | 1538 | /* Compute the in-degree of every block in the graph. */ |
8c660648 | 1539 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 JL |
1540 | degree[i] = num_preds[i]; |
1541 | ||
15ebe47d JL |
1542 | /* Do not perform region scheduling if there are any unreachable |
1543 | blocks. */ | |
1544 | if (!unreachable) | |
8c660648 | 1545 | { |
15ebe47d JL |
1546 | if (no_loops) |
1547 | SET_BIT (header, 0); | |
8c660648 | 1548 | |
15ebe47d JL |
1549 | /* Second travsersal:find reducible inner loops and topologically sort |
1550 | block of each region. */ | |
8c660648 | 1551 | |
15ebe47d | 1552 | queue = (int *) alloca (n_basic_blocks * sizeof (int)); |
8c660648 | 1553 | |
cc132865 JL |
1554 | /* Find blocks which are inner loop headers. We still have non-reducible |
1555 | loops to consider at this point. */ | |
15ebe47d JL |
1556 | for (i = 0; i < n_basic_blocks; i++) |
1557 | { | |
1558 | if (TEST_BIT (header, i) && TEST_BIT (inner, i)) | |
1559 | { | |
1560 | int_list_ptr ps; | |
cc132865 JL |
1561 | int j; |
1562 | ||
1563 | /* Now check that the loop is reducible. We do this separate | |
1564 | from finding inner loops so that we do not find a reducible | |
63de6c74 | 1565 | loop which contains an inner non-reducible loop. |
cc132865 | 1566 | |
63de6c74 | 1567 | A simple way to find reducible/natural loops is to verify |
cc132865 JL |
1568 | that each block in the loop is dominated by the loop |
1569 | header. | |
1570 | ||
1571 | If there exists a block that is not dominated by the loop | |
1572 | header, then the block is reachable from outside the loop | |
1573 | and thus the loop is not a natural loop. */ | |
1574 | for (j = 0; j < n_basic_blocks; j++) | |
1575 | { | |
1576 | /* First identify blocks in the loop, except for the loop | |
1577 | entry block. */ | |
1578 | if (i == max_hdr[j] && i != j) | |
1579 | { | |
1580 | /* Now verify that the block is dominated by the loop | |
1581 | header. */ | |
1582 | if (!TEST_BIT (dom[j], i)) | |
1583 | break; | |
1584 | } | |
1585 | } | |
1586 | ||
63de6c74 MH |
1587 | /* If we exited the loop early, then I is the header of |
1588 | a non-reducible loop and we should quit processing it | |
1589 | now. */ | |
cc132865 JL |
1590 | if (j != n_basic_blocks) |
1591 | continue; | |
8c660648 | 1592 | |
cc132865 JL |
1593 | /* I is a header of an inner loop, or block 0 in a subroutine |
1594 | with no loops at all. */ | |
15ebe47d JL |
1595 | head = tail = -1; |
1596 | too_large_failure = 0; | |
1597 | loop_head = max_hdr[i]; | |
8c660648 | 1598 | |
15ebe47d | 1599 | /* Decrease degree of all I's successors for topological |
a59bfd78 | 1600 | ordering. */ |
15ebe47d JL |
1601 | for (ps = s_succs[i]; ps; ps = ps->next) |
1602 | if (INT_LIST_VAL (ps) != EXIT_BLOCK | |
1603 | && INT_LIST_VAL (ps) != ENTRY_BLOCK) | |
cc132865 | 1604 | --degree[INT_LIST_VAL(ps)]; |
a2e68776 | 1605 | |
15ebe47d JL |
1606 | /* Estimate # insns, and count # blocks in the region. */ |
1607 | num_bbs = 1; | |
3b413743 RH |
1608 | num_insns = (INSN_LUID (BLOCK_END (i)) |
1609 | - INSN_LUID (BLOCK_HEAD (i))); | |
8c660648 | 1610 | |
15ebe47d | 1611 | |
63de6c74 | 1612 | /* Find all loop latches (blocks with back edges to the loop |
15ebe47d JL |
1613 | header) or all the leaf blocks in the cfg has no loops. |
1614 | ||
1615 | Place those blocks into the queue. */ | |
1616 | if (no_loops) | |
1617 | { | |
1618 | for (j = 0; j < n_basic_blocks; j++) | |
1619 | /* Leaf nodes have only a single successor which must | |
1620 | be EXIT_BLOCK. */ | |
1621 | if (num_succs[j] == 1 | |
1622 | && INT_LIST_VAL (s_succs[j]) == EXIT_BLOCK) | |
8c660648 | 1623 | { |
15ebe47d JL |
1624 | queue[++tail] = j; |
1625 | SET_BIT (in_queue, j); | |
1626 | ||
1627 | if (too_large (j, &num_bbs, &num_insns)) | |
1628 | { | |
1629 | too_large_failure = 1; | |
1630 | break; | |
1631 | } | |
8c660648 | 1632 | } |
15ebe47d JL |
1633 | } |
1634 | else | |
8c660648 | 1635 | { |
15ebe47d | 1636 | int_list_ptr ps; |
a2e68776 | 1637 | |
15ebe47d | 1638 | for (ps = s_preds[i]; ps; ps = ps->next) |
8c660648 | 1639 | { |
15ebe47d | 1640 | node = INT_LIST_VAL (ps); |
8c660648 | 1641 | |
15ebe47d JL |
1642 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK) |
1643 | continue; | |
1644 | ||
1645 | if (max_hdr[node] == loop_head && node != i) | |
8c660648 | 1646 | { |
15ebe47d JL |
1647 | /* This is a loop latch. */ |
1648 | queue[++tail] = node; | |
1649 | SET_BIT (in_queue, node); | |
1650 | ||
1651 | if (too_large (node, &num_bbs, &num_insns)) | |
1652 | { | |
1653 | too_large_failure = 1; | |
1654 | break; | |
1655 | } | |
8c660648 | 1656 | } |
15ebe47d | 1657 | |
8c660648 | 1658 | } |
8c660648 | 1659 | } |
8c660648 | 1660 | |
15ebe47d | 1661 | /* Now add all the blocks in the loop to the queue. |
a2e68776 JL |
1662 | |
1663 | We know the loop is a natural loop; however the algorithm | |
1664 | above will not always mark certain blocks as being in the | |
1665 | loop. Consider: | |
1666 | node children | |
1667 | a b,c | |
1668 | b c | |
1669 | c a,d | |
1670 | d b | |
1671 | ||
1672 | ||
1673 | The algorithm in the DFS traversal may not mark B & D as part | |
1674 | of the loop (ie they will not have max_hdr set to A). | |
1675 | ||
1676 | We know they can not be loop latches (else they would have | |
1677 | had max_hdr set since they'd have a backedge to a dominator | |
1678 | block). So we don't need them on the initial queue. | |
1679 | ||
1680 | We know they are part of the loop because they are dominated | |
1681 | by the loop header and can be reached by a backwards walk of | |
1682 | the edges starting with nodes on the initial queue. | |
1683 | ||
1684 | It is safe and desirable to include those nodes in the | |
1685 | loop/scheduling region. To do so we would need to decrease | |
1686 | the degree of a node if it is the target of a backedge | |
1687 | within the loop itself as the node is placed in the queue. | |
1688 | ||
1689 | We do not do this because I'm not sure that the actual | |
1690 | scheduling code will properly handle this case. ?!? */ | |
1691 | ||
15ebe47d | 1692 | while (head < tail && !too_large_failure) |
8c660648 | 1693 | { |
15ebe47d JL |
1694 | int_list_ptr ps; |
1695 | child = queue[++head]; | |
8c660648 | 1696 | |
15ebe47d | 1697 | for (ps = s_preds[child]; ps; ps = ps->next) |
8c660648 | 1698 | { |
15ebe47d | 1699 | node = INT_LIST_VAL (ps); |
8c660648 | 1700 | |
15ebe47d JL |
1701 | /* See discussion above about nodes not marked as in |
1702 | this loop during the initial DFS traversal. */ | |
1703 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK | |
1704 | || max_hdr[node] != loop_head) | |
8c660648 | 1705 | { |
15ebe47d | 1706 | tail = -1; |
8c660648 JL |
1707 | break; |
1708 | } | |
15ebe47d JL |
1709 | else if (!TEST_BIT (in_queue, node) && node != i) |
1710 | { | |
1711 | queue[++tail] = node; | |
1712 | SET_BIT (in_queue, node); | |
1713 | ||
1714 | if (too_large (node, &num_bbs, &num_insns)) | |
1715 | { | |
1716 | too_large_failure = 1; | |
1717 | break; | |
1718 | } | |
1719 | } | |
8c660648 | 1720 | } |
8c660648 | 1721 | } |
8c660648 | 1722 | |
15ebe47d JL |
1723 | if (tail >= 0 && !too_large_failure) |
1724 | { | |
1725 | /* Place the loop header into list of region blocks. */ | |
1726 | degree[i] = -1; | |
1727 | rgn_bb_table[idx] = i; | |
1728 | RGN_NR_BLOCKS (nr_regions) = num_bbs; | |
1729 | RGN_BLOCKS (nr_regions) = idx++; | |
1730 | CONTAINING_RGN (i) = nr_regions; | |
1731 | BLOCK_TO_BB (i) = count = 0; | |
1732 | ||
63de6c74 MH |
1733 | /* Remove blocks from queue[] when their in degree |
1734 | becomes zero. Repeat until no blocks are left on the | |
1735 | list. This produces a topological list of blocks in | |
1736 | the region. */ | |
15ebe47d | 1737 | while (tail >= 0) |
8c660648 | 1738 | { |
15ebe47d JL |
1739 | int_list_ptr ps; |
1740 | ||
1741 | if (head < 0) | |
1742 | head = tail; | |
1743 | child = queue[head]; | |
1744 | if (degree[child] == 0) | |
1745 | { | |
1746 | degree[child] = -1; | |
1747 | rgn_bb_table[idx++] = child; | |
1748 | BLOCK_TO_BB (child) = ++count; | |
1749 | CONTAINING_RGN (child) = nr_regions; | |
1750 | queue[head] = queue[tail--]; | |
1751 | ||
1752 | for (ps = s_succs[child]; ps; ps = ps->next) | |
1753 | if (INT_LIST_VAL (ps) != ENTRY_BLOCK | |
1754 | && INT_LIST_VAL (ps) != EXIT_BLOCK) | |
1755 | --degree[INT_LIST_VAL (ps)]; | |
1756 | } | |
1757 | else | |
1758 | --head; | |
8c660648 | 1759 | } |
15ebe47d | 1760 | ++nr_regions; |
8c660648 | 1761 | } |
8c660648 JL |
1762 | } |
1763 | } | |
1764 | } | |
1765 | ||
a2e68776 JL |
1766 | /* Any block that did not end up in a region is placed into a region |
1767 | by itself. */ | |
8c660648 JL |
1768 | for (i = 0; i < n_basic_blocks; i++) |
1769 | if (degree[i] >= 0) | |
1770 | { | |
1771 | rgn_bb_table[idx] = i; | |
1772 | RGN_NR_BLOCKS (nr_regions) = 1; | |
1773 | RGN_BLOCKS (nr_regions) = idx++; | |
1774 | CONTAINING_RGN (i) = nr_regions++; | |
1775 | BLOCK_TO_BB (i) = 0; | |
1776 | } | |
1777 | ||
a2e68776 JL |
1778 | free (passed); |
1779 | free (header); | |
1780 | free (inner); | |
1781 | free (in_queue); | |
cc132865 | 1782 | free (in_stack); |
a2e68776 | 1783 | } |
8c660648 JL |
1784 | |
1785 | ||
63de6c74 | 1786 | /* Functions for regions scheduling information. */ |
8c660648 JL |
1787 | |
1788 | /* Compute dominators, probability, and potential-split-edges of bb. | |
1789 | Assume that these values were already computed for bb's predecessors. */ | |
1790 | ||
1791 | static void | |
1792 | compute_dom_prob_ps (bb) | |
1793 | int bb; | |
1794 | { | |
1795 | int nxt_in_edge, fst_in_edge, pred; | |
1796 | int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges; | |
1797 | ||
1798 | prob[bb] = 0.0; | |
1799 | if (IS_RGN_ENTRY (bb)) | |
1800 | { | |
1801 | BITSET_ADD (dom[bb], 0, bbset_size); | |
1802 | prob[bb] = 1.0; | |
1803 | return; | |
1804 | } | |
1805 | ||
1806 | fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb)); | |
1807 | ||
63de6c74 | 1808 | /* Intialize dom[bb] to '111..1'. */ |
8c660648 JL |
1809 | BITSET_INVERT (dom[bb], bbset_size); |
1810 | ||
1811 | do | |
1812 | { | |
1813 | pred = FROM_BLOCK (nxt_in_edge); | |
1814 | BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size); | |
1815 | ||
1816 | BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)], | |
1817 | edgeset_size); | |
1818 | ||
1819 | BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size); | |
1820 | ||
1821 | nr_out_edges = 1; | |
1822 | nr_rgn_out_edges = 0; | |
1823 | fst_out_edge = OUT_EDGES (pred); | |
1824 | nxt_out_edge = NEXT_OUT (fst_out_edge); | |
1825 | BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)], | |
1826 | edgeset_size); | |
1827 | ||
1828 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size); | |
1829 | ||
63de6c74 | 1830 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1831 | if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) != |
1832 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1833 | ++nr_rgn_out_edges; | |
1834 | ||
1835 | while (fst_out_edge != nxt_out_edge) | |
1836 | { | |
1837 | ++nr_out_edges; | |
63de6c74 | 1838 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1839 | if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) != |
1840 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1841 | ++nr_rgn_out_edges; | |
1842 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size); | |
1843 | nxt_out_edge = NEXT_OUT (nxt_out_edge); | |
1844 | ||
1845 | } | |
1846 | ||
63de6c74 MH |
1847 | /* Now nr_rgn_out_edges is the number of region-exit edges from |
1848 | pred, and nr_out_edges will be the number of pred out edges | |
1849 | not leaving the region. */ | |
8c660648 JL |
1850 | nr_out_edges -= nr_rgn_out_edges; |
1851 | if (nr_rgn_out_edges > 0) | |
1852 | prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1853 | else | |
1854 | prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1855 | nxt_in_edge = NEXT_IN (nxt_in_edge); | |
1856 | } | |
1857 | while (fst_in_edge != nxt_in_edge); | |
1858 | ||
1859 | BITSET_ADD (dom[bb], bb, bbset_size); | |
1860 | BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size); | |
1861 | ||
1862 | if (sched_verbose >= 2) | |
1863 | fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb])); | |
1864 | } /* compute_dom_prob_ps */ | |
1865 | ||
63de6c74 | 1866 | /* Functions for target info. */ |
8c660648 JL |
1867 | |
1868 | /* Compute in BL the list of split-edges of bb_src relatively to bb_trg. | |
1869 | Note that bb_trg dominates bb_src. */ | |
1870 | ||
1871 | static void | |
1872 | split_edges (bb_src, bb_trg, bl) | |
1873 | int bb_src; | |
1874 | int bb_trg; | |
1875 | edgelst *bl; | |
1876 | { | |
1877 | int es = edgeset_size; | |
1878 | edgeset src = (edgeset) alloca (es * sizeof (HOST_WIDE_INT)); | |
1879 | ||
1880 | while (es--) | |
1881 | src[es] = (pot_split[bb_src])[es]; | |
1882 | BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size); | |
1883 | extract_bitlst (src, edgeset_size, bl); | |
1884 | } | |
1885 | ||
1886 | ||
1887 | /* Find the valid candidate-source-blocks for the target block TRG, compute | |
1888 | their probability, and check if they are speculative or not. | |
1889 | For speculative sources, compute their update-blocks and split-blocks. */ | |
1890 | ||
1891 | static void | |
1892 | compute_trg_info (trg) | |
1893 | int trg; | |
1894 | { | |
1895 | register candidate *sp; | |
1896 | edgelst el; | |
1897 | int check_block, update_idx; | |
1898 | int i, j, k, fst_edge, nxt_edge; | |
1899 | ||
63de6c74 | 1900 | /* Define some of the fields for the target bb as well. */ |
8c660648 JL |
1901 | sp = candidate_table + trg; |
1902 | sp->is_valid = 1; | |
1903 | sp->is_speculative = 0; | |
1904 | sp->src_prob = 100; | |
1905 | ||
1906 | for (i = trg + 1; i < current_nr_blocks; i++) | |
1907 | { | |
1908 | sp = candidate_table + i; | |
1909 | ||
1910 | sp->is_valid = IS_DOMINATED (i, trg); | |
1911 | if (sp->is_valid) | |
1912 | { | |
1913 | sp->src_prob = GET_SRC_PROB (i, trg); | |
1914 | sp->is_valid = (sp->src_prob >= MIN_PROBABILITY); | |
1915 | } | |
1916 | ||
1917 | if (sp->is_valid) | |
1918 | { | |
1919 | split_edges (i, trg, &el); | |
1920 | sp->is_speculative = (el.nr_members) ? 1 : 0; | |
1921 | if (sp->is_speculative && !flag_schedule_speculative) | |
1922 | sp->is_valid = 0; | |
1923 | } | |
1924 | ||
1925 | if (sp->is_valid) | |
1926 | { | |
1927 | sp->split_bbs.first_member = &bblst_table[bblst_last]; | |
1928 | sp->split_bbs.nr_members = el.nr_members; | |
1929 | for (j = 0; j < el.nr_members; bblst_last++, j++) | |
1930 | bblst_table[bblst_last] = | |
1931 | TO_BLOCK (rgn_edges[el.first_member[j]]); | |
1932 | sp->update_bbs.first_member = &bblst_table[bblst_last]; | |
1933 | update_idx = 0; | |
1934 | for (j = 0; j < el.nr_members; j++) | |
1935 | { | |
1936 | check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]); | |
1937 | fst_edge = nxt_edge = OUT_EDGES (check_block); | |
1938 | do | |
1939 | { | |
1940 | for (k = 0; k < el.nr_members; k++) | |
1941 | if (EDGE_TO_BIT (nxt_edge) == el.first_member[k]) | |
1942 | break; | |
1943 | ||
1944 | if (k >= el.nr_members) | |
1945 | { | |
1946 | bblst_table[bblst_last++] = TO_BLOCK (nxt_edge); | |
1947 | update_idx++; | |
1948 | } | |
1949 | ||
1950 | nxt_edge = NEXT_OUT (nxt_edge); | |
1951 | } | |
1952 | while (fst_edge != nxt_edge); | |
1953 | } | |
1954 | sp->update_bbs.nr_members = update_idx; | |
1955 | ||
1956 | } | |
1957 | else | |
1958 | { | |
1959 | sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0; | |
1960 | ||
1961 | sp->is_speculative = 0; | |
1962 | sp->src_prob = 0; | |
1963 | } | |
1964 | } | |
1965 | } /* compute_trg_info */ | |
1966 | ||
1967 | ||
1968 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
1969 | ||
1970 | void | |
1971 | debug_candidate (i) | |
1972 | int i; | |
1973 | { | |
1974 | if (!candidate_table[i].is_valid) | |
1975 | return; | |
1976 | ||
1977 | if (candidate_table[i].is_speculative) | |
1978 | { | |
1979 | int j; | |
1980 | fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i); | |
1981 | ||
1982 | fprintf (dump, "split path: "); | |
1983 | for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++) | |
1984 | { | |
1985 | int b = candidate_table[i].split_bbs.first_member[j]; | |
1986 | ||
1987 | fprintf (dump, " %d ", b); | |
1988 | } | |
1989 | fprintf (dump, "\n"); | |
1990 | ||
1991 | fprintf (dump, "update path: "); | |
1992 | for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++) | |
1993 | { | |
1994 | int b = candidate_table[i].update_bbs.first_member[j]; | |
1995 | ||
1996 | fprintf (dump, " %d ", b); | |
1997 | } | |
1998 | fprintf (dump, "\n"); | |
1999 | } | |
2000 | else | |
2001 | { | |
2002 | fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i)); | |
2003 | } | |
2004 | } | |
2005 | ||
2006 | ||
2007 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
2008 | ||
2009 | void | |
2010 | debug_candidates (trg) | |
2011 | int trg; | |
2012 | { | |
2013 | int i; | |
2014 | ||
2015 | fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n", | |
2016 | BB_TO_BLOCK (trg), trg); | |
2017 | for (i = trg + 1; i < current_nr_blocks; i++) | |
2018 | debug_candidate (i); | |
2019 | } | |
2020 | ||
2021 | ||
63de6c74 | 2022 | /* Functions for speculative scheduing. */ |
8c660648 JL |
2023 | |
2024 | /* Return 0 if x is a set of a register alive in the beginning of one | |
2025 | of the split-blocks of src, otherwise return 1. */ | |
2026 | ||
2027 | static int | |
2028 | check_live_1 (src, x) | |
2029 | int src; | |
2030 | rtx x; | |
2031 | { | |
5835e573 | 2032 | register int i; |
8c660648 JL |
2033 | register int regno; |
2034 | register rtx reg = SET_DEST (x); | |
2035 | ||
2036 | if (reg == 0) | |
2037 | return 1; | |
2038 | ||
2039 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2040 | || GET_CODE (reg) == SIGN_EXTRACT | |
2041 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2042 | reg = XEXP (reg, 0); | |
2043 | ||
c0222c21 DM |
2044 | if (GET_CODE (reg) == PARALLEL |
2045 | && GET_MODE (reg) == BLKmode) | |
2046 | { | |
2047 | register int i; | |
2048 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2049 | if (check_live_1 (src, XVECEXP (reg, 0, i))) | |
2050 | return 1; | |
2051 | return 0; | |
2052 | } | |
2053 | ||
8c660648 JL |
2054 | if (GET_CODE (reg) != REG) |
2055 | return 1; | |
2056 | ||
2057 | regno = REGNO (reg); | |
2058 | ||
2059 | if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno]) | |
2060 | { | |
63de6c74 | 2061 | /* Global registers are assumed live. */ |
8c660648 JL |
2062 | return 0; |
2063 | } | |
2064 | else | |
2065 | { | |
2066 | if (regno < FIRST_PSEUDO_REGISTER) | |
2067 | { | |
63de6c74 | 2068 | /* Check for hard registers. */ |
8c660648 JL |
2069 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); |
2070 | while (--j >= 0) | |
2071 | { | |
2072 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) | |
2073 | { | |
2074 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2075 | ||
e881bb1b RH |
2076 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, |
2077 | regno + j)) | |
8c660648 JL |
2078 | { |
2079 | return 0; | |
2080 | } | |
2081 | } | |
2082 | } | |
2083 | } | |
2084 | else | |
2085 | { | |
63de6c74 | 2086 | /* Check for psuedo registers. */ |
8c660648 JL |
2087 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) |
2088 | { | |
2089 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2090 | ||
e881bb1b | 2091 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, regno)) |
8c660648 JL |
2092 | { |
2093 | return 0; | |
2094 | } | |
2095 | } | |
2096 | } | |
2097 | } | |
2098 | ||
2099 | return 1; | |
2100 | } | |
2101 | ||
2102 | ||
2103 | /* If x is a set of a register R, mark that R is alive in the beginning | |
2104 | of every update-block of src. */ | |
2105 | ||
2106 | static void | |
2107 | update_live_1 (src, x) | |
2108 | int src; | |
2109 | rtx x; | |
2110 | { | |
5835e573 | 2111 | register int i; |
8c660648 JL |
2112 | register int regno; |
2113 | register rtx reg = SET_DEST (x); | |
2114 | ||
2115 | if (reg == 0) | |
2116 | return; | |
2117 | ||
2118 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2119 | || GET_CODE (reg) == SIGN_EXTRACT | |
2120 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2121 | reg = XEXP (reg, 0); | |
2122 | ||
c0222c21 DM |
2123 | if (GET_CODE (reg) == PARALLEL |
2124 | && GET_MODE (reg) == BLKmode) | |
2125 | { | |
2126 | register int i; | |
2127 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2128 | update_live_1 (src, XVECEXP (reg, 0, i)); | |
2129 | return; | |
2130 | } | |
2131 | ||
8c660648 JL |
2132 | if (GET_CODE (reg) != REG) |
2133 | return; | |
2134 | ||
2135 | /* Global registers are always live, so the code below does not apply | |
2136 | to them. */ | |
2137 | ||
2138 | regno = REGNO (reg); | |
2139 | ||
2140 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
2141 | { | |
2142 | if (regno < FIRST_PSEUDO_REGISTER) | |
2143 | { | |
2144 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2145 | while (--j >= 0) | |
2146 | { | |
2147 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2148 | { | |
2149 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2150 | ||
e881bb1b RH |
2151 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, |
2152 | regno + j); | |
8c660648 JL |
2153 | } |
2154 | } | |
2155 | } | |
2156 | else | |
2157 | { | |
2158 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2159 | { | |
2160 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2161 | ||
e881bb1b | 2162 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, regno); |
8c660648 JL |
2163 | } |
2164 | } | |
2165 | } | |
2166 | } | |
2167 | ||
2168 | ||
2169 | /* Return 1 if insn can be speculatively moved from block src to trg, | |
2170 | otherwise return 0. Called before first insertion of insn to | |
2171 | ready-list or before the scheduling. */ | |
2172 | ||
2173 | static int | |
5835e573 | 2174 | check_live (insn, src) |
8c660648 JL |
2175 | rtx insn; |
2176 | int src; | |
8c660648 | 2177 | { |
63de6c74 | 2178 | /* Find the registers set by instruction. */ |
8c660648 JL |
2179 | if (GET_CODE (PATTERN (insn)) == SET |
2180 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2181 | return check_live_1 (src, PATTERN (insn)); | |
2182 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2183 | { | |
2184 | int j; | |
2185 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2186 | if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2187 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2188 | && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j))) | |
2189 | return 0; | |
2190 | ||
2191 | return 1; | |
2192 | } | |
2193 | ||
2194 | return 1; | |
2195 | } | |
2196 | ||
2197 | ||
2198 | /* Update the live registers info after insn was moved speculatively from | |
2199 | block src to trg. */ | |
2200 | ||
2201 | static void | |
5835e573 | 2202 | update_live (insn, src) |
8c660648 | 2203 | rtx insn; |
5835e573 | 2204 | int src; |
8c660648 | 2205 | { |
63de6c74 | 2206 | /* Find the registers set by instruction. */ |
8c660648 JL |
2207 | if (GET_CODE (PATTERN (insn)) == SET |
2208 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2209 | update_live_1 (src, PATTERN (insn)); | |
2210 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2211 | { | |
2212 | int j; | |
2213 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2214 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2215 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2216 | update_live_1 (src, XVECEXP (PATTERN (insn), 0, j)); | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | /* Exception Free Loads: | |
2221 | ||
2222 | We define five classes of speculative loads: IFREE, IRISKY, | |
2223 | PFREE, PRISKY, and MFREE. | |
2224 | ||
2225 | IFREE loads are loads that are proved to be exception-free, just | |
2226 | by examining the load insn. Examples for such loads are loads | |
2227 | from TOC and loads of global data. | |
2228 | ||
2229 | IRISKY loads are loads that are proved to be exception-risky, | |
2230 | just by examining the load insn. Examples for such loads are | |
2231 | volatile loads and loads from shared memory. | |
2232 | ||
2233 | PFREE loads are loads for which we can prove, by examining other | |
2234 | insns, that they are exception-free. Currently, this class consists | |
2235 | of loads for which we are able to find a "similar load", either in | |
2236 | the target block, or, if only one split-block exists, in that split | |
2237 | block. Load2 is similar to load1 if both have same single base | |
2238 | register. We identify only part of the similar loads, by finding | |
2239 | an insn upon which both load1 and load2 have a DEF-USE dependence. | |
2240 | ||
2241 | PRISKY loads are loads for which we can prove, by examining other | |
2242 | insns, that they are exception-risky. Currently we have two proofs for | |
2243 | such loads. The first proof detects loads that are probably guarded by a | |
2244 | test on the memory address. This proof is based on the | |
2245 | backward and forward data dependence information for the region. | |
2246 | Let load-insn be the examined load. | |
2247 | Load-insn is PRISKY iff ALL the following hold: | |
2248 | ||
2249 | - insn1 is not in the same block as load-insn | |
2250 | - there is a DEF-USE dependence chain (insn1, ..., load-insn) | |
63de6c74 MH |
2251 | - test-insn is either a compare or a branch, not in the same block |
2252 | as load-insn | |
8c660648 JL |
2253 | - load-insn is reachable from test-insn |
2254 | - there is a DEF-USE dependence chain (insn1, ..., test-insn) | |
2255 | ||
2256 | This proof might fail when the compare and the load are fed | |
2257 | by an insn not in the region. To solve this, we will add to this | |
2258 | group all loads that have no input DEF-USE dependence. | |
2259 | ||
2260 | The second proof detects loads that are directly or indirectly | |
2261 | fed by a speculative load. This proof is affected by the | |
2262 | scheduling process. We will use the flag fed_by_spec_load. | |
2263 | Initially, all insns have this flag reset. After a speculative | |
2264 | motion of an insn, if insn is either a load, or marked as | |
2265 | fed_by_spec_load, we will also mark as fed_by_spec_load every | |
2266 | insn1 for which a DEF-USE dependence (insn, insn1) exists. A | |
2267 | load which is fed_by_spec_load is also PRISKY. | |
2268 | ||
2269 | MFREE (maybe-free) loads are all the remaining loads. They may be | |
2270 | exception-free, but we cannot prove it. | |
2271 | ||
2272 | Now, all loads in IFREE and PFREE classes are considered | |
2273 | exception-free, while all loads in IRISKY and PRISKY classes are | |
2274 | considered exception-risky. As for loads in the MFREE class, | |
2275 | these are considered either exception-free or exception-risky, | |
2276 | depending on whether we are pessimistic or optimistic. We have | |
2277 | to take the pessimistic approach to assure the safety of | |
2278 | speculative scheduling, but we can take the optimistic approach | |
2279 | by invoking the -fsched_spec_load_dangerous option. */ | |
2280 | ||
2281 | enum INSN_TRAP_CLASS | |
2282 | { | |
2283 | TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2, | |
2284 | PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5 | |
2285 | }; | |
2286 | ||
2287 | #define WORST_CLASS(class1, class2) \ | |
2288 | ((class1 > class2) ? class1 : class2) | |
2289 | ||
63de6c74 MH |
2290 | /* Indexed by INSN_UID, and set if there's DEF-USE dependence between |
2291 | some speculatively moved load insn and this one. */ | |
8c660648 JL |
2292 | char *fed_by_spec_load; |
2293 | char *is_load_insn; | |
2294 | ||
2295 | /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */ | |
2296 | #define IS_REACHABLE(bb_from, bb_to) \ | |
2297 | (bb_from == bb_to \ | |
2298 | || IS_RGN_ENTRY (bb_from) \ | |
2299 | || (bitset_member (ancestor_edges[bb_to], \ | |
2300 | EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \ | |
2301 | edgeset_size))) | |
2302 | #define FED_BY_SPEC_LOAD(insn) (fed_by_spec_load[INSN_UID (insn)]) | |
2303 | #define IS_LOAD_INSN(insn) (is_load_insn[INSN_UID (insn)]) | |
2304 | ||
63de6c74 | 2305 | /* Non-zero iff the address is comprised from at most 1 register. */ |
8c660648 JL |
2306 | #define CONST_BASED_ADDRESS_P(x) \ |
2307 | (GET_CODE (x) == REG \ | |
2308 | || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \ | |
2309 | || (GET_CODE (x) == LO_SUM)) \ | |
2310 | && (GET_CODE (XEXP (x, 0)) == CONST_INT \ | |
2311 | || GET_CODE (XEXP (x, 1)) == CONST_INT))) | |
2312 | ||
2313 | /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */ | |
2314 | ||
2315 | static void | |
2316 | set_spec_fed (load_insn) | |
2317 | rtx load_insn; | |
2318 | { | |
2319 | rtx link; | |
2320 | ||
2321 | for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1)) | |
2322 | if (GET_MODE (link) == VOIDmode) | |
2323 | FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1; | |
2324 | } /* set_spec_fed */ | |
2325 | ||
63de6c74 MH |
2326 | /* On the path from the insn to load_insn_bb, find a conditional |
2327 | branch depending on insn, that guards the speculative load. */ | |
8c660648 JL |
2328 | |
2329 | static int | |
2330 | find_conditional_protection (insn, load_insn_bb) | |
2331 | rtx insn; | |
2332 | int load_insn_bb; | |
2333 | { | |
2334 | rtx link; | |
2335 | ||
63de6c74 | 2336 | /* Iterate through DEF-USE forward dependences. */ |
8c660648 JL |
2337 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) |
2338 | { | |
2339 | rtx next = XEXP (link, 0); | |
c88e8206 | 2340 | if ((CONTAINING_RGN (BLOCK_NUM (next)) == |
8c660648 JL |
2341 | CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb))) |
2342 | && IS_REACHABLE (INSN_BB (next), load_insn_bb) | |
2343 | && load_insn_bb != INSN_BB (next) | |
2344 | && GET_MODE (link) == VOIDmode | |
2345 | && (GET_CODE (next) == JUMP_INSN | |
2346 | || find_conditional_protection (next, load_insn_bb))) | |
2347 | return 1; | |
2348 | } | |
2349 | return 0; | |
2350 | } /* find_conditional_protection */ | |
2351 | ||
2352 | /* Returns 1 if the same insn1 that participates in the computation | |
2353 | of load_insn's address is feeding a conditional branch that is | |
2354 | guarding on load_insn. This is true if we find a the two DEF-USE | |
2355 | chains: | |
2356 | insn1 -> ... -> conditional-branch | |
2357 | insn1 -> ... -> load_insn, | |
2358 | and if a flow path exist: | |
2359 | insn1 -> ... -> conditional-branch -> ... -> load_insn, | |
2360 | and if insn1 is on the path | |
2361 | region-entry -> ... -> bb_trg -> ... load_insn. | |
2362 | ||
2363 | Locate insn1 by climbing on LOG_LINKS from load_insn. | |
2364 | Locate the branch by following INSN_DEPEND from insn1. */ | |
2365 | ||
2366 | static int | |
2367 | is_conditionally_protected (load_insn, bb_src, bb_trg) | |
2368 | rtx load_insn; | |
2369 | int bb_src, bb_trg; | |
2370 | { | |
2371 | rtx link; | |
2372 | ||
2373 | for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1)) | |
2374 | { | |
2375 | rtx insn1 = XEXP (link, 0); | |
2376 | ||
63de6c74 | 2377 | /* Must be a DEF-USE dependence upon non-branch. */ |
8c660648 JL |
2378 | if (GET_MODE (link) != VOIDmode |
2379 | || GET_CODE (insn1) == JUMP_INSN) | |
2380 | continue; | |
2381 | ||
63de6c74 | 2382 | /* Must exist a path: region-entry -> ... -> bb_trg -> ... load_insn. */ |
8c660648 | 2383 | if (INSN_BB (insn1) == bb_src |
c88e8206 | 2384 | || (CONTAINING_RGN (BLOCK_NUM (insn1)) |
8c660648 JL |
2385 | != CONTAINING_RGN (BB_TO_BLOCK (bb_src))) |
2386 | || (!IS_REACHABLE (bb_trg, INSN_BB (insn1)) | |
2387 | && !IS_REACHABLE (INSN_BB (insn1), bb_trg))) | |
2388 | continue; | |
2389 | ||
63de6c74 | 2390 | /* Now search for the conditional-branch. */ |
8c660648 JL |
2391 | if (find_conditional_protection (insn1, bb_src)) |
2392 | return 1; | |
2393 | ||
63de6c74 | 2394 | /* Recursive step: search another insn1, "above" current insn1. */ |
8c660648 JL |
2395 | return is_conditionally_protected (insn1, bb_src, bb_trg); |
2396 | } | |
2397 | ||
63de6c74 | 2398 | /* The chain does not exist. */ |
8c660648 JL |
2399 | return 0; |
2400 | } /* is_conditionally_protected */ | |
2401 | ||
2402 | /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence | |
2403 | load_insn can move speculatively from bb_src to bb_trg. All the | |
2404 | following must hold: | |
2405 | ||
2406 | (1) both loads have 1 base register (PFREE_CANDIDATEs). | |
2407 | (2) load_insn and load1 have a def-use dependence upon | |
2408 | the same insn 'insn1'. | |
2409 | (3) either load2 is in bb_trg, or: | |
2410 | - there's only one split-block, and | |
2411 | - load1 is on the escape path, and | |
2412 | ||
2413 | From all these we can conclude that the two loads access memory | |
2414 | addresses that differ at most by a constant, and hence if moving | |
2415 | load_insn would cause an exception, it would have been caused by | |
2416 | load2 anyhow. */ | |
2417 | ||
2418 | static int | |
2419 | is_pfree (load_insn, bb_src, bb_trg) | |
2420 | rtx load_insn; | |
2421 | int bb_src, bb_trg; | |
2422 | { | |
2423 | rtx back_link; | |
2424 | register candidate *candp = candidate_table + bb_src; | |
2425 | ||
2426 | if (candp->split_bbs.nr_members != 1) | |
63de6c74 | 2427 | /* Must have exactly one escape block. */ |
8c660648 JL |
2428 | return 0; |
2429 | ||
2430 | for (back_link = LOG_LINKS (load_insn); | |
2431 | back_link; back_link = XEXP (back_link, 1)) | |
2432 | { | |
2433 | rtx insn1 = XEXP (back_link, 0); | |
2434 | ||
2435 | if (GET_MODE (back_link) == VOIDmode) | |
2436 | { | |
63de6c74 | 2437 | /* Found a DEF-USE dependence (insn1, load_insn). */ |
8c660648 JL |
2438 | rtx fore_link; |
2439 | ||
2440 | for (fore_link = INSN_DEPEND (insn1); | |
2441 | fore_link; fore_link = XEXP (fore_link, 1)) | |
2442 | { | |
2443 | rtx insn2 = XEXP (fore_link, 0); | |
2444 | if (GET_MODE (fore_link) == VOIDmode) | |
2445 | { | |
63de6c74 | 2446 | /* Found a DEF-USE dependence (insn1, insn2). */ |
ac957f13 | 2447 | if (haifa_classify_insn (insn2) != PFREE_CANDIDATE) |
63de6c74 | 2448 | /* insn2 not guaranteed to be a 1 base reg load. */ |
8c660648 JL |
2449 | continue; |
2450 | ||
2451 | if (INSN_BB (insn2) == bb_trg) | |
63de6c74 | 2452 | /* insn2 is the similar load, in the target block. */ |
8c660648 JL |
2453 | return 1; |
2454 | ||
c88e8206 | 2455 | if (*(candp->split_bbs.first_member) == BLOCK_NUM (insn2)) |
63de6c74 | 2456 | /* insn2 is a similar load, in a split-block. */ |
8c660648 JL |
2457 | return 1; |
2458 | } | |
2459 | } | |
2460 | } | |
2461 | } | |
2462 | ||
63de6c74 | 2463 | /* Couldn't find a similar load. */ |
8c660648 JL |
2464 | return 0; |
2465 | } /* is_pfree */ | |
2466 | ||
2467 | /* Returns a class that insn with GET_DEST(insn)=x may belong to, | |
2468 | as found by analyzing insn's expression. */ | |
2469 | ||
2470 | static int | |
2471 | may_trap_exp (x, is_store) | |
2472 | rtx x; | |
2473 | int is_store; | |
2474 | { | |
2475 | enum rtx_code code; | |
2476 | ||
2477 | if (x == 0) | |
2478 | return TRAP_FREE; | |
2479 | code = GET_CODE (x); | |
2480 | if (is_store) | |
2481 | { | |
2482 | if (code == MEM) | |
2483 | return TRAP_RISKY; | |
2484 | else | |
2485 | return TRAP_FREE; | |
2486 | } | |
2487 | if (code == MEM) | |
2488 | { | |
63de6c74 | 2489 | /* The insn uses memory: a volatile load. */ |
8c660648 JL |
2490 | if (MEM_VOLATILE_P (x)) |
2491 | return IRISKY; | |
63de6c74 | 2492 | /* An exception-free load. */ |
8c660648 JL |
2493 | if (!may_trap_p (x)) |
2494 | return IFREE; | |
63de6c74 | 2495 | /* A load with 1 base register, to be further checked. */ |
8c660648 JL |
2496 | if (CONST_BASED_ADDRESS_P (XEXP (x, 0))) |
2497 | return PFREE_CANDIDATE; | |
63de6c74 | 2498 | /* No info on the load, to be further checked. */ |
8c660648 JL |
2499 | return PRISKY_CANDIDATE; |
2500 | } | |
2501 | else | |
2502 | { | |
6f7d635c | 2503 | const char *fmt; |
8c660648 JL |
2504 | int i, insn_class = TRAP_FREE; |
2505 | ||
63de6c74 | 2506 | /* Neither store nor load, check if it may cause a trap. */ |
8c660648 JL |
2507 | if (may_trap_p (x)) |
2508 | return TRAP_RISKY; | |
63de6c74 | 2509 | /* Recursive step: walk the insn... */ |
8c660648 JL |
2510 | fmt = GET_RTX_FORMAT (code); |
2511 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2512 | { | |
2513 | if (fmt[i] == 'e') | |
2514 | { | |
2515 | int tmp_class = may_trap_exp (XEXP (x, i), is_store); | |
2516 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2517 | } | |
2518 | else if (fmt[i] == 'E') | |
2519 | { | |
2520 | int j; | |
2521 | for (j = 0; j < XVECLEN (x, i); j++) | |
2522 | { | |
2523 | int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store); | |
2524 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2525 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2526 | break; | |
2527 | } | |
2528 | } | |
2529 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2530 | break; | |
2531 | } | |
2532 | return insn_class; | |
2533 | } | |
2534 | } /* may_trap_exp */ | |
2535 | ||
2536 | ||
2537 | /* Classifies insn for the purpose of verifying that it can be | |
2538 | moved speculatively, by examining it's patterns, returning: | |
2539 | TRAP_RISKY: store, or risky non-load insn (e.g. division by variable). | |
2540 | TRAP_FREE: non-load insn. | |
2541 | IFREE: load from a globaly safe location. | |
2542 | IRISKY: volatile load. | |
2543 | PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for | |
2544 | being either PFREE or PRISKY. */ | |
2545 | ||
2546 | static int | |
ac957f13 | 2547 | haifa_classify_insn (insn) |
8c660648 JL |
2548 | rtx insn; |
2549 | { | |
2550 | rtx pat = PATTERN (insn); | |
2551 | int tmp_class = TRAP_FREE; | |
2552 | int insn_class = TRAP_FREE; | |
2553 | enum rtx_code code; | |
2554 | ||
2555 | if (GET_CODE (pat) == PARALLEL) | |
2556 | { | |
2557 | int i, len = XVECLEN (pat, 0); | |
2558 | ||
2559 | for (i = len - 1; i >= 0; i--) | |
2560 | { | |
2561 | code = GET_CODE (XVECEXP (pat, 0, i)); | |
2562 | switch (code) | |
2563 | { | |
2564 | case CLOBBER: | |
63de6c74 | 2565 | /* Test if it is a 'store'. */ |
8c660648 JL |
2566 | tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1); |
2567 | break; | |
2568 | case SET: | |
63de6c74 | 2569 | /* Test if it is a store. */ |
8c660648 JL |
2570 | tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1); |
2571 | if (tmp_class == TRAP_RISKY) | |
2572 | break; | |
63de6c74 | 2573 | /* Test if it is a load. */ |
8c660648 JL |
2574 | tmp_class = |
2575 | WORST_CLASS (tmp_class, | |
2576 | may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0)); | |
e0cd0770 JC |
2577 | break; |
2578 | case TRAP_IF: | |
2579 | tmp_class = TRAP_RISKY; | |
2580 | break; | |
8c660648 JL |
2581 | default:; |
2582 | } | |
2583 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2584 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2585 | break; | |
2586 | } | |
2587 | } | |
2588 | else | |
2589 | { | |
2590 | code = GET_CODE (pat); | |
2591 | switch (code) | |
2592 | { | |
2593 | case CLOBBER: | |
63de6c74 | 2594 | /* Test if it is a 'store'. */ |
8c660648 JL |
2595 | tmp_class = may_trap_exp (XEXP (pat, 0), 1); |
2596 | break; | |
2597 | case SET: | |
63de6c74 | 2598 | /* Test if it is a store. */ |
8c660648 JL |
2599 | tmp_class = may_trap_exp (SET_DEST (pat), 1); |
2600 | if (tmp_class == TRAP_RISKY) | |
2601 | break; | |
63de6c74 | 2602 | /* Test if it is a load. */ |
8c660648 JL |
2603 | tmp_class = |
2604 | WORST_CLASS (tmp_class, | |
2605 | may_trap_exp (SET_SRC (pat), 0)); | |
e0cd0770 JC |
2606 | break; |
2607 | case TRAP_IF: | |
2608 | tmp_class = TRAP_RISKY; | |
2609 | break; | |
8c660648 JL |
2610 | default:; |
2611 | } | |
2612 | insn_class = tmp_class; | |
2613 | } | |
2614 | ||
2615 | return insn_class; | |
2616 | ||
ac957f13 | 2617 | } /* haifa_classify_insn */ |
8c660648 JL |
2618 | |
2619 | /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by | |
2620 | a load moved speculatively, or if load_insn is protected by | |
2621 | a compare on load_insn's address). */ | |
2622 | ||
2623 | static int | |
2624 | is_prisky (load_insn, bb_src, bb_trg) | |
2625 | rtx load_insn; | |
2626 | int bb_src, bb_trg; | |
2627 | { | |
2628 | if (FED_BY_SPEC_LOAD (load_insn)) | |
2629 | return 1; | |
2630 | ||
2631 | if (LOG_LINKS (load_insn) == NULL) | |
63de6c74 | 2632 | /* Dependence may 'hide' out of the region. */ |
8c660648 JL |
2633 | return 1; |
2634 | ||
2635 | if (is_conditionally_protected (load_insn, bb_src, bb_trg)) | |
2636 | return 1; | |
2637 | ||
2638 | return 0; | |
2639 | } /* is_prisky */ | |
2640 | ||
2641 | /* Insn is a candidate to be moved speculatively from bb_src to bb_trg. | |
2642 | Return 1 if insn is exception-free (and the motion is valid) | |
2643 | and 0 otherwise. */ | |
2644 | ||
2645 | static int | |
2646 | is_exception_free (insn, bb_src, bb_trg) | |
2647 | rtx insn; | |
2648 | int bb_src, bb_trg; | |
2649 | { | |
ac957f13 | 2650 | int insn_class = haifa_classify_insn (insn); |
8c660648 | 2651 | |
63de6c74 | 2652 | /* Handle non-load insns. */ |
8c660648 JL |
2653 | switch (insn_class) |
2654 | { | |
2655 | case TRAP_FREE: | |
2656 | return 1; | |
2657 | case TRAP_RISKY: | |
2658 | return 0; | |
2659 | default:; | |
2660 | } | |
2661 | ||
63de6c74 | 2662 | /* Handle loads. */ |
8c660648 JL |
2663 | if (!flag_schedule_speculative_load) |
2664 | return 0; | |
2665 | IS_LOAD_INSN (insn) = 1; | |
2666 | switch (insn_class) | |
2667 | { | |
2668 | case IFREE: | |
2669 | return (1); | |
2670 | case IRISKY: | |
2671 | return 0; | |
2672 | case PFREE_CANDIDATE: | |
2673 | if (is_pfree (insn, bb_src, bb_trg)) | |
2674 | return 1; | |
63de6c74 | 2675 | /* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */ |
8c660648 JL |
2676 | case PRISKY_CANDIDATE: |
2677 | if (!flag_schedule_speculative_load_dangerous | |
2678 | || is_prisky (insn, bb_src, bb_trg)) | |
2679 | return 0; | |
2680 | break; | |
2681 | default:; | |
2682 | } | |
2683 | ||
2684 | return flag_schedule_speculative_load_dangerous; | |
2685 | } /* is_exception_free */ | |
2686 | ||
2687 | ||
2688 | /* Process an insn's memory dependencies. There are four kinds of | |
2689 | dependencies: | |
2690 | ||
2691 | (0) read dependence: read follows read | |
2692 | (1) true dependence: read follows write | |
2693 | (2) anti dependence: write follows read | |
2694 | (3) output dependence: write follows write | |
2695 | ||
2696 | We are careful to build only dependencies which actually exist, and | |
2697 | use transitivity to avoid building too many links. */ | |
2698 | \f | |
2699 | /* Return the INSN_LIST containing INSN in LIST, or NULL | |
2700 | if LIST does not contain INSN. */ | |
2701 | ||
cbb13457 | 2702 | HAIFA_INLINE static rtx |
8c660648 JL |
2703 | find_insn_list (insn, list) |
2704 | rtx insn; | |
2705 | rtx list; | |
2706 | { | |
2707 | while (list) | |
2708 | { | |
2709 | if (XEXP (list, 0) == insn) | |
2710 | return list; | |
2711 | list = XEXP (list, 1); | |
2712 | } | |
2713 | return 0; | |
2714 | } | |
2715 | ||
2716 | ||
63de6c74 MH |
2717 | /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 |
2718 | otherwise. */ | |
8c660648 | 2719 | |
cbb13457 | 2720 | HAIFA_INLINE static char |
8c660648 JL |
2721 | find_insn_mem_list (insn, x, list, list1) |
2722 | rtx insn, x; | |
2723 | rtx list, list1; | |
2724 | { | |
2725 | while (list) | |
2726 | { | |
2727 | if (XEXP (list, 0) == insn | |
2728 | && XEXP (list1, 0) == x) | |
2729 | return 1; | |
2730 | list = XEXP (list, 1); | |
2731 | list1 = XEXP (list1, 1); | |
2732 | } | |
2733 | return 0; | |
2734 | } | |
2735 | ||
2736 | ||
2737 | /* Compute the function units used by INSN. This caches the value | |
2738 | returned by function_units_used. A function unit is encoded as the | |
2739 | unit number if the value is non-negative and the compliment of a | |
2740 | mask if the value is negative. A function unit index is the | |
2741 | non-negative encoding. */ | |
2742 | ||
cbb13457 | 2743 | HAIFA_INLINE static int |
8c660648 JL |
2744 | insn_unit (insn) |
2745 | rtx insn; | |
2746 | { | |
2747 | register int unit = INSN_UNIT (insn); | |
2748 | ||
2749 | if (unit == 0) | |
2750 | { | |
2751 | recog_memoized (insn); | |
2752 | ||
2753 | /* A USE insn, or something else we don't need to understand. | |
2754 | We can't pass these directly to function_units_used because it will | |
2755 | trigger a fatal error for unrecognizable insns. */ | |
2756 | if (INSN_CODE (insn) < 0) | |
2757 | unit = -1; | |
2758 | else | |
2759 | { | |
2760 | unit = function_units_used (insn); | |
2761 | /* Increment non-negative values so we can cache zero. */ | |
2762 | if (unit >= 0) | |
2763 | unit++; | |
2764 | } | |
2765 | /* We only cache 16 bits of the result, so if the value is out of | |
2766 | range, don't cache it. */ | |
2767 | if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT | |
2768 | || unit >= 0 | |
77f3d48a | 2769 | || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0) |
8c660648 JL |
2770 | INSN_UNIT (insn) = unit; |
2771 | } | |
2772 | return (unit > 0 ? unit - 1 : unit); | |
2773 | } | |
2774 | ||
2775 | /* Compute the blockage range for executing INSN on UNIT. This caches | |
2776 | the value returned by the blockage_range_function for the unit. | |
2777 | These values are encoded in an int where the upper half gives the | |
2778 | minimum value and the lower half gives the maximum value. */ | |
2779 | ||
cbb13457 | 2780 | HAIFA_INLINE static unsigned int |
8c660648 JL |
2781 | blockage_range (unit, insn) |
2782 | int unit; | |
2783 | rtx insn; | |
2784 | { | |
2785 | unsigned int blockage = INSN_BLOCKAGE (insn); | |
2786 | unsigned int range; | |
2787 | ||
79c9824e | 2788 | if ((int) UNIT_BLOCKED (blockage) != unit + 1) |
8c660648 JL |
2789 | { |
2790 | range = function_units[unit].blockage_range_function (insn); | |
2791 | /* We only cache the blockage range for one unit and then only if | |
2792 | the values fit. */ | |
2793 | if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS) | |
2794 | INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range); | |
2795 | } | |
2796 | else | |
2797 | range = BLOCKAGE_RANGE (blockage); | |
2798 | ||
2799 | return range; | |
2800 | } | |
2801 | ||
2802 | /* A vector indexed by function unit instance giving the last insn to use | |
2803 | the unit. The value of the function unit instance index for unit U | |
2804 | instance I is (U + I * FUNCTION_UNITS_SIZE). */ | |
2805 | static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2806 | ||
2807 | /* A vector indexed by function unit instance giving the minimum time when | |
2808 | the unit will unblock based on the maximum blockage cost. */ | |
2809 | static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2810 | ||
2811 | /* A vector indexed by function unit number giving the number of insns | |
2812 | that remain to use the unit. */ | |
2813 | static int unit_n_insns[FUNCTION_UNITS_SIZE]; | |
2814 | ||
2815 | /* Reset the function unit state to the null state. */ | |
2816 | ||
2817 | static void | |
2818 | clear_units () | |
2819 | { | |
2820 | bzero ((char *) unit_last_insn, sizeof (unit_last_insn)); | |
2821 | bzero ((char *) unit_tick, sizeof (unit_tick)); | |
2822 | bzero ((char *) unit_n_insns, sizeof (unit_n_insns)); | |
2823 | } | |
2824 | ||
63de6c74 | 2825 | /* Return the issue-delay of an insn. */ |
8c660648 | 2826 | |
cbb13457 | 2827 | HAIFA_INLINE static int |
8c660648 JL |
2828 | insn_issue_delay (insn) |
2829 | rtx insn; | |
2830 | { | |
8c660648 JL |
2831 | int i, delay = 0; |
2832 | int unit = insn_unit (insn); | |
2833 | ||
63de6c74 | 2834 | /* Efficiency note: in fact, we are working 'hard' to compute a |
8c660648 JL |
2835 | value that was available in md file, and is not available in |
2836 | function_units[] structure. It would be nice to have this | |
2837 | value there, too. */ | |
2838 | if (unit >= 0) | |
2839 | { | |
2840 | if (function_units[unit].blockage_range_function && | |
2841 | function_units[unit].blockage_function) | |
2842 | delay = function_units[unit].blockage_function (insn, insn); | |
2843 | } | |
2844 | else | |
2845 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2846 | if ((unit & 1) != 0 && function_units[i].blockage_range_function | |
2847 | && function_units[i].blockage_function) | |
2848 | delay = MAX (delay, function_units[i].blockage_function (insn, insn)); | |
2849 | ||
2850 | return delay; | |
2851 | } | |
2852 | ||
2853 | /* Return the actual hazard cost of executing INSN on the unit UNIT, | |
2854 | instance INSTANCE at time CLOCK if the previous actual hazard cost | |
2855 | was COST. */ | |
2856 | ||
cbb13457 | 2857 | HAIFA_INLINE static int |
8c660648 JL |
2858 | actual_hazard_this_instance (unit, instance, insn, clock, cost) |
2859 | int unit, instance, clock, cost; | |
2860 | rtx insn; | |
2861 | { | |
63de6c74 | 2862 | int tick = unit_tick[instance]; /* Issue time of the last issued insn. */ |
8c660648 JL |
2863 | |
2864 | if (tick - clock > cost) | |
2865 | { | |
2866 | /* The scheduler is operating forward, so unit's last insn is the | |
2867 | executing insn and INSN is the candidate insn. We want a | |
2868 | more exact measure of the blockage if we execute INSN at CLOCK | |
2869 | given when we committed the execution of the unit's last insn. | |
2870 | ||
2871 | The blockage value is given by either the unit's max blockage | |
2872 | constant, blockage range function, or blockage function. Use | |
2873 | the most exact form for the given unit. */ | |
2874 | ||
2875 | if (function_units[unit].blockage_range_function) | |
2876 | { | |
2877 | if (function_units[unit].blockage_function) | |
2878 | tick += (function_units[unit].blockage_function | |
2879 | (unit_last_insn[instance], insn) | |
2880 | - function_units[unit].max_blockage); | |
2881 | else | |
2882 | tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn)) | |
2883 | - function_units[unit].max_blockage); | |
2884 | } | |
2885 | if (tick - clock > cost) | |
2886 | cost = tick - clock; | |
2887 | } | |
2888 | return cost; | |
2889 | } | |
2890 | ||
2891 | /* Record INSN as having begun execution on the units encoded by UNIT at | |
2892 | time CLOCK. */ | |
2893 | ||
cbb13457 | 2894 | HAIFA_INLINE static void |
8c660648 JL |
2895 | schedule_unit (unit, insn, clock) |
2896 | int unit, clock; | |
2897 | rtx insn; | |
2898 | { | |
2899 | int i; | |
2900 | ||
2901 | if (unit >= 0) | |
2902 | { | |
2903 | int instance = unit; | |
2904 | #if MAX_MULTIPLICITY > 1 | |
2905 | /* Find the first free instance of the function unit and use that | |
2906 | one. We assume that one is free. */ | |
2907 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2908 | { | |
2909 | if (!actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
2910 | break; | |
2911 | instance += FUNCTION_UNITS_SIZE; | |
2912 | } | |
2913 | #endif | |
2914 | unit_last_insn[instance] = insn; | |
2915 | unit_tick[instance] = (clock + function_units[unit].max_blockage); | |
2916 | } | |
2917 | else | |
2918 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2919 | if ((unit & 1) != 0) | |
2920 | schedule_unit (i, insn, clock); | |
2921 | } | |
2922 | ||
2923 | /* Return the actual hazard cost of executing INSN on the units encoded by | |
2924 | UNIT at time CLOCK if the previous actual hazard cost was COST. */ | |
2925 | ||
cbb13457 | 2926 | HAIFA_INLINE static int |
8c660648 JL |
2927 | actual_hazard (unit, insn, clock, cost) |
2928 | int unit, clock, cost; | |
2929 | rtx insn; | |
2930 | { | |
2931 | int i; | |
2932 | ||
2933 | if (unit >= 0) | |
2934 | { | |
2935 | /* Find the instance of the function unit with the minimum hazard. */ | |
2936 | int instance = unit; | |
2937 | int best_cost = actual_hazard_this_instance (unit, instance, insn, | |
2938 | clock, cost); | |
1eda7a81 | 2939 | #if MAX_MULTIPLICITY > 1 |
8c660648 JL |
2940 | int this_cost; |
2941 | ||
8c660648 JL |
2942 | if (best_cost > cost) |
2943 | { | |
2944 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2945 | { | |
2946 | instance += FUNCTION_UNITS_SIZE; | |
2947 | this_cost = actual_hazard_this_instance (unit, instance, insn, | |
2948 | clock, cost); | |
2949 | if (this_cost < best_cost) | |
2950 | { | |
2951 | best_cost = this_cost; | |
2952 | if (this_cost <= cost) | |
2953 | break; | |
2954 | } | |
2955 | } | |
2956 | } | |
2957 | #endif | |
2958 | cost = MAX (cost, best_cost); | |
2959 | } | |
2960 | else | |
2961 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2962 | if ((unit & 1) != 0) | |
2963 | cost = actual_hazard (i, insn, clock, cost); | |
2964 | ||
2965 | return cost; | |
2966 | } | |
2967 | ||
2968 | /* Return the potential hazard cost of executing an instruction on the | |
2969 | units encoded by UNIT if the previous potential hazard cost was COST. | |
2970 | An insn with a large blockage time is chosen in preference to one | |
2971 | with a smaller time; an insn that uses a unit that is more likely | |
2972 | to be used is chosen in preference to one with a unit that is less | |
2973 | used. We are trying to minimize a subsequent actual hazard. */ | |
2974 | ||
cbb13457 | 2975 | HAIFA_INLINE static int |
8c660648 JL |
2976 | potential_hazard (unit, insn, cost) |
2977 | int unit, cost; | |
2978 | rtx insn; | |
2979 | { | |
2980 | int i, ncost; | |
2981 | unsigned int minb, maxb; | |
2982 | ||
2983 | if (unit >= 0) | |
2984 | { | |
2985 | minb = maxb = function_units[unit].max_blockage; | |
2986 | if (maxb > 1) | |
2987 | { | |
2988 | if (function_units[unit].blockage_range_function) | |
2989 | { | |
2990 | maxb = minb = blockage_range (unit, insn); | |
2991 | maxb = MAX_BLOCKAGE_COST (maxb); | |
2992 | minb = MIN_BLOCKAGE_COST (minb); | |
2993 | } | |
2994 | ||
2995 | if (maxb > 1) | |
2996 | { | |
2997 | /* Make the number of instructions left dominate. Make the | |
2998 | minimum delay dominate the maximum delay. If all these | |
2999 | are the same, use the unit number to add an arbitrary | |
3000 | ordering. Other terms can be added. */ | |
3001 | ncost = minb * 0x40 + maxb; | |
3002 | ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit; | |
3003 | if (ncost > cost) | |
3004 | cost = ncost; | |
3005 | } | |
3006 | } | |
3007 | } | |
3008 | else | |
3009 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3010 | if ((unit & 1) != 0) | |
3011 | cost = potential_hazard (i, insn, cost); | |
3012 | ||
3013 | return cost; | |
3014 | } | |
3015 | ||
3016 | /* Compute cost of executing INSN given the dependence LINK on the insn USED. | |
3017 | This is the number of cycles between instruction issue and | |
3018 | instruction results. */ | |
3019 | ||
cbb13457 | 3020 | HAIFA_INLINE static int |
8c660648 JL |
3021 | insn_cost (insn, link, used) |
3022 | rtx insn, link, used; | |
3023 | { | |
3024 | register int cost = INSN_COST (insn); | |
3025 | ||
3026 | if (cost == 0) | |
3027 | { | |
3028 | recog_memoized (insn); | |
3029 | ||
3030 | /* A USE insn, or something else we don't need to understand. | |
3031 | We can't pass these directly to result_ready_cost because it will | |
3032 | trigger a fatal error for unrecognizable insns. */ | |
3033 | if (INSN_CODE (insn) < 0) | |
3034 | { | |
3035 | INSN_COST (insn) = 1; | |
3036 | return 1; | |
3037 | } | |
3038 | else | |
3039 | { | |
3040 | cost = result_ready_cost (insn); | |
3041 | ||
3042 | if (cost < 1) | |
3043 | cost = 1; | |
3044 | ||
3045 | INSN_COST (insn) = cost; | |
3046 | } | |
3047 | } | |
3048 | ||
63de6c74 | 3049 | /* In this case estimate cost without caring how insn is used. */ |
8c660648 JL |
3050 | if (link == 0 && used == 0) |
3051 | return cost; | |
3052 | ||
3053 | /* A USE insn should never require the value used to be computed. This | |
3054 | allows the computation of a function's result and parameter values to | |
3055 | overlap the return and call. */ | |
3056 | recog_memoized (used); | |
3057 | if (INSN_CODE (used) < 0) | |
3058 | LINK_COST_FREE (link) = 1; | |
3059 | ||
3060 | /* If some dependencies vary the cost, compute the adjustment. Most | |
3061 | commonly, the adjustment is complete: either the cost is ignored | |
3062 | (in the case of an output- or anti-dependence), or the cost is | |
3063 | unchanged. These values are cached in the link as LINK_COST_FREE | |
3064 | and LINK_COST_ZERO. */ | |
3065 | ||
3066 | if (LINK_COST_FREE (link)) | |
197043f5 | 3067 | cost = 0; |
8c660648 JL |
3068 | #ifdef ADJUST_COST |
3069 | else if (!LINK_COST_ZERO (link)) | |
3070 | { | |
3071 | int ncost = cost; | |
3072 | ||
3073 | ADJUST_COST (used, link, insn, ncost); | |
197043f5 RH |
3074 | if (ncost < 1) |
3075 | { | |
3076 | LINK_COST_FREE (link) = 1; | |
3077 | ncost = 0; | |
3078 | } | |
8c660648 JL |
3079 | if (cost == ncost) |
3080 | LINK_COST_ZERO (link) = 1; | |
3081 | cost = ncost; | |
3082 | } | |
3083 | #endif | |
3084 | return cost; | |
3085 | } | |
3086 | ||
3087 | /* Compute the priority number for INSN. */ | |
3088 | ||
3089 | static int | |
3090 | priority (insn) | |
3091 | rtx insn; | |
3092 | { | |
3093 | int this_priority; | |
3094 | rtx link; | |
3095 | ||
3096 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
3097 | return 0; | |
3098 | ||
3099 | if ((this_priority = INSN_PRIORITY (insn)) == 0) | |
3100 | { | |
3101 | if (INSN_DEPEND (insn) == 0) | |
3102 | this_priority = insn_cost (insn, 0, 0); | |
3103 | else | |
3104 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
3105 | { | |
3106 | rtx next; | |
3107 | int next_priority; | |
3108 | ||
6d8ccdbb JL |
3109 | if (RTX_INTEGRATED_P (link)) |
3110 | continue; | |
3111 | ||
8c660648 JL |
3112 | next = XEXP (link, 0); |
3113 | ||
63de6c74 | 3114 | /* Critical path is meaningful in block boundaries only. */ |
c88e8206 | 3115 | if (BLOCK_NUM (next) != BLOCK_NUM (insn)) |
8c660648 JL |
3116 | continue; |
3117 | ||
3118 | next_priority = insn_cost (insn, link, next) + priority (next); | |
3119 | if (next_priority > this_priority) | |
3120 | this_priority = next_priority; | |
3121 | } | |
3122 | INSN_PRIORITY (insn) = this_priority; | |
3123 | } | |
3124 | return this_priority; | |
3125 | } | |
3126 | \f | |
3127 | ||
3128 | /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add | |
3129 | them to the unused_*_list variables, so that they can be reused. */ | |
3130 | ||
8c660648 JL |
3131 | static void |
3132 | free_pending_lists () | |
3133 | { | |
8c660648 JL |
3134 | if (current_nr_blocks <= 1) |
3135 | { | |
5a4f6418 AM |
3136 | free_INSN_LIST_list (&pending_read_insns); |
3137 | free_INSN_LIST_list (&pending_write_insns); | |
3138 | free_EXPR_LIST_list (&pending_read_mems); | |
3139 | free_EXPR_LIST_list (&pending_write_mems); | |
8c660648 JL |
3140 | } |
3141 | else | |
3142 | { | |
63de6c74 | 3143 | /* Interblock scheduling. */ |
8c660648 JL |
3144 | int bb; |
3145 | ||
3146 | for (bb = 0; bb < current_nr_blocks; bb++) | |
3147 | { | |
5a4f6418 AM |
3148 | free_INSN_LIST_list (&bb_pending_read_insns[bb]); |
3149 | free_INSN_LIST_list (&bb_pending_write_insns[bb]); | |
3150 | free_EXPR_LIST_list (&bb_pending_read_mems[bb]); | |
3151 | free_EXPR_LIST_list (&bb_pending_write_mems[bb]); | |
8c660648 JL |
3152 | } |
3153 | } | |
3154 | } | |
3155 | ||
3156 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
3157 | The MEM is a memory reference contained within INSN, which we are saving | |
3158 | so that we can do memory aliasing on it. */ | |
3159 | ||
3160 | static void | |
3161 | add_insn_mem_dependence (insn_list, mem_list, insn, mem) | |
3162 | rtx *insn_list, *mem_list, insn, mem; | |
3163 | { | |
3164 | register rtx link; | |
3165 | ||
ebb7b10b | 3166 | link = alloc_INSN_LIST (insn, *insn_list); |
8c660648 JL |
3167 | *insn_list = link; |
3168 | ||
ebb7b10b | 3169 | link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list); |
8c660648 JL |
3170 | *mem_list = link; |
3171 | ||
3172 | pending_lists_length++; | |
3173 | } | |
3174 | \f | |
3175 | ||
3176 | /* Make a dependency between every memory reference on the pending lists | |
3177 | and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush | |
3178 | the read list. */ | |
3179 | ||
3180 | static void | |
3181 | flush_pending_lists (insn, only_write) | |
3182 | rtx insn; | |
3183 | int only_write; | |
3184 | { | |
3185 | rtx u; | |
3186 | rtx link; | |
3187 | ||
3188 | while (pending_read_insns && ! only_write) | |
3189 | { | |
3190 | add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI); | |
3191 | ||
3192 | link = pending_read_insns; | |
3193 | pending_read_insns = XEXP (pending_read_insns, 1); | |
5a4f6418 | 3194 | free_INSN_LIST_node (link); |
8c660648 JL |
3195 | |
3196 | link = pending_read_mems; | |
3197 | pending_read_mems = XEXP (pending_read_mems, 1); | |
5a4f6418 | 3198 | free_EXPR_LIST_node (link); |
8c660648 JL |
3199 | } |
3200 | while (pending_write_insns) | |
3201 | { | |
3202 | add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI); | |
3203 | ||
3204 | link = pending_write_insns; | |
3205 | pending_write_insns = XEXP (pending_write_insns, 1); | |
5a4f6418 | 3206 | free_INSN_LIST_node (link); |
8c660648 JL |
3207 | |
3208 | link = pending_write_mems; | |
3209 | pending_write_mems = XEXP (pending_write_mems, 1); | |
5a4f6418 | 3210 | free_EXPR_LIST_node (link); |
8c660648 JL |
3211 | } |
3212 | pending_lists_length = 0; | |
3213 | ||
63de6c74 | 3214 | /* last_pending_memory_flush is now a list of insns. */ |
8c660648 JL |
3215 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
3216 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3217 | ||
5a4f6418 | 3218 | free_INSN_LIST_list (&last_pending_memory_flush); |
ebb7b10b | 3219 | last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3220 | } |
3221 | ||
355fca3e AB |
3222 | /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC |
3223 | rtx, X, creating all dependencies generated by the write to the | |
3224 | destination of X, and reads of everything mentioned. */ | |
8c660648 JL |
3225 | |
3226 | static void | |
3227 | sched_analyze_1 (x, insn) | |
3228 | rtx x; | |
3229 | rtx insn; | |
3230 | { | |
3231 | register int regno; | |
355fca3e | 3232 | register rtx dest = XEXP (x, 0); |
28c95eff | 3233 | enum rtx_code code = GET_CODE (x); |
8c660648 JL |
3234 | |
3235 | if (dest == 0) | |
3236 | return; | |
3237 | ||
c0222c21 DM |
3238 | if (GET_CODE (dest) == PARALLEL |
3239 | && GET_MODE (dest) == BLKmode) | |
3240 | { | |
3241 | register int i; | |
3242 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
3243 | sched_analyze_1 (XVECEXP (dest, 0, i), insn); | |
3244 | if (GET_CODE (x) == SET) | |
3245 | sched_analyze_2 (SET_SRC (x), insn); | |
3246 | return; | |
3247 | } | |
3248 | ||
8c660648 JL |
3249 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG |
3250 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3251 | { | |
3252 | if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3253 | { | |
3254 | /* The second and third arguments are values read by this insn. */ | |
3255 | sched_analyze_2 (XEXP (dest, 1), insn); | |
3256 | sched_analyze_2 (XEXP (dest, 2), insn); | |
3257 | } | |
355fca3e | 3258 | dest = XEXP (dest, 0); |
8c660648 JL |
3259 | } |
3260 | ||
3261 | if (GET_CODE (dest) == REG) | |
3262 | { | |
3263 | register int i; | |
3264 | ||
3265 | regno = REGNO (dest); | |
3266 | ||
3267 | /* A hard reg in a wide mode may really be multiple registers. | |
3268 | If so, mark all of them just like the first. */ | |
3269 | if (regno < FIRST_PSEUDO_REGISTER) | |
3270 | { | |
3271 | i = HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
3272 | while (--i >= 0) | |
3273 | { | |
3274 | rtx u; | |
3275 | ||
3276 | for (u = reg_last_uses[regno + i]; u; u = XEXP (u, 1)) | |
3277 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3278 | |
3279 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3280 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3281 | ||
63de6c74 MH |
3282 | /* Clobbers need not be ordered with respect to one |
3283 | another, but sets must be ordered with respect to a | |
3284 | pending clobber. */ | |
28c95eff RH |
3285 | if (code == SET) |
3286 | { | |
5a4f6418 | 3287 | free_INSN_LIST_list (®_last_uses[regno + i]); |
28c95eff RH |
3288 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) |
3289 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3290 | SET_REGNO_REG_SET (reg_pending_sets, regno + i); | |
3291 | } | |
3292 | else | |
3293 | SET_REGNO_REG_SET (reg_pending_clobbers, regno + i); | |
8c660648 | 3294 | |
28c95eff RH |
3295 | /* Function calls clobber all call_used regs. */ |
3296 | if (global_regs[regno + i] | |
3297 | || (code == SET && call_used_regs[regno + i])) | |
8c660648 JL |
3298 | for (u = last_function_call; u; u = XEXP (u, 1)) |
3299 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3300 | } | |
3301 | } | |
3302 | else | |
3303 | { | |
3304 | rtx u; | |
3305 | ||
3306 | for (u = reg_last_uses[regno]; u; u = XEXP (u, 1)) | |
3307 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3308 | |
3309 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3310 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3311 | ||
28c95eff | 3312 | if (code == SET) |
7399257b | 3313 | { |
5a4f6418 | 3314 | free_INSN_LIST_list (®_last_uses[regno]); |
7399257b RH |
3315 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) |
3316 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3317 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
3318 | } | |
28c95eff RH |
3319 | else |
3320 | SET_REGNO_REG_SET (reg_pending_clobbers, regno); | |
8c660648 JL |
3321 | |
3322 | /* Pseudos that are REG_EQUIV to something may be replaced | |
3323 | by that during reloading. We need only add dependencies for | |
3324 | the address in the REG_EQUIV note. */ | |
3325 | if (!reload_completed | |
3326 | && reg_known_equiv_p[regno] | |
3327 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3328 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3329 | ||
3330 | /* Don't let it cross a call after scheduling if it doesn't | |
3331 | already cross one. */ | |
3332 | ||
3333 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3334 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3335 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3336 | } | |
3337 | } | |
3338 | else if (GET_CODE (dest) == MEM) | |
3339 | { | |
3340 | /* Writing memory. */ | |
3341 | ||
3342 | if (pending_lists_length > 32) | |
3343 | { | |
3344 | /* Flush all pending reads and writes to prevent the pending lists | |
3345 | from getting any larger. Insn scheduling runs too slowly when | |
3346 | these lists get long. The number 32 was chosen because it | |
3347 | seems like a reasonable number. When compiling GCC with itself, | |
3348 | this flush occurs 8 times for sparc, and 10 times for m88k using | |
3349 | the number 32. */ | |
3350 | flush_pending_lists (insn, 0); | |
3351 | } | |
3352 | else | |
3353 | { | |
3354 | rtx u; | |
3355 | rtx pending, pending_mem; | |
3356 | ||
3357 | pending = pending_read_insns; | |
3358 | pending_mem = pending_read_mems; | |
3359 | while (pending) | |
3360 | { | |
87373fba RH |
3361 | if (anti_dependence (XEXP (pending_mem, 0), dest)) |
3362 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3363 | |
3364 | pending = XEXP (pending, 1); | |
3365 | pending_mem = XEXP (pending_mem, 1); | |
3366 | } | |
3367 | ||
3368 | pending = pending_write_insns; | |
3369 | pending_mem = pending_write_mems; | |
3370 | while (pending) | |
3371 | { | |
87373fba RH |
3372 | if (output_dependence (XEXP (pending_mem, 0), dest)) |
3373 | add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT); | |
8c660648 JL |
3374 | |
3375 | pending = XEXP (pending, 1); | |
3376 | pending_mem = XEXP (pending_mem, 1); | |
3377 | } | |
3378 | ||
3379 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3380 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3381 | ||
3382 | add_insn_mem_dependence (&pending_write_insns, &pending_write_mems, | |
3383 | insn, dest); | |
3384 | } | |
3385 | sched_analyze_2 (XEXP (dest, 0), insn); | |
3386 | } | |
3387 | ||
3388 | /* Analyze reads. */ | |
3389 | if (GET_CODE (x) == SET) | |
3390 | sched_analyze_2 (SET_SRC (x), insn); | |
3391 | } | |
3392 | ||
3393 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
3394 | ||
3395 | static void | |
3396 | sched_analyze_2 (x, insn) | |
3397 | rtx x; | |
3398 | rtx insn; | |
3399 | { | |
3400 | register int i; | |
3401 | register int j; | |
3402 | register enum rtx_code code; | |
6f7d635c | 3403 | register const char *fmt; |
8c660648 JL |
3404 | |
3405 | if (x == 0) | |
3406 | return; | |
3407 | ||
3408 | code = GET_CODE (x); | |
3409 | ||
3410 | switch (code) | |
3411 | { | |
3412 | case CONST_INT: | |
3413 | case CONST_DOUBLE: | |
3414 | case SYMBOL_REF: | |
3415 | case CONST: | |
3416 | case LABEL_REF: | |
3417 | /* Ignore constants. Note that we must handle CONST_DOUBLE here | |
3418 | because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but | |
3419 | this does not mean that this insn is using cc0. */ | |
3420 | return; | |
3421 | ||
3422 | #ifdef HAVE_cc0 | |
3423 | case CC0: | |
3424 | { | |
3425 | rtx link, prev; | |
3426 | ||
3427 | /* User of CC0 depends on immediately preceding insn. */ | |
3428 | SCHED_GROUP_P (insn) = 1; | |
3429 | ||
3430 | /* There may be a note before this insn now, but all notes will | |
3431 | be removed before we actually try to schedule the insns, so | |
3432 | it won't cause a problem later. We must avoid it here though. */ | |
3433 | prev = prev_nonnote_insn (insn); | |
3434 | ||
3435 | /* Make a copy of all dependencies on the immediately previous insn, | |
3436 | and add to this insn. This is so that all the dependencies will | |
3437 | apply to the group. Remove an explicit dependence on this insn | |
3438 | as SCHED_GROUP_P now represents it. */ | |
3439 | ||
3440 | if (find_insn_list (prev, LOG_LINKS (insn))) | |
3441 | remove_dependence (insn, prev); | |
3442 | ||
3443 | for (link = LOG_LINKS (prev); link; link = XEXP (link, 1)) | |
3444 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3445 | ||
3446 | return; | |
3447 | } | |
3448 | #endif | |
3449 | ||
3450 | case REG: | |
3451 | { | |
3452 | rtx u; | |
3453 | int regno = REGNO (x); | |
3454 | if (regno < FIRST_PSEUDO_REGISTER) | |
3455 | { | |
3456 | int i; | |
3457 | ||
3458 | i = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3459 | while (--i >= 0) | |
3460 | { | |
3461 | reg_last_uses[regno + i] | |
ebb7b10b | 3462 | = alloc_INSN_LIST (insn, reg_last_uses[regno + i]); |
8c660648 JL |
3463 | |
3464 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3465 | add_dependence (insn, XEXP (u, 0), 0); | |
3466 | ||
28c95eff RH |
3467 | /* ??? This should never happen. */ |
3468 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) | |
3469 | add_dependence (insn, XEXP (u, 0), 0); | |
3470 | ||
8c660648 JL |
3471 | if ((call_used_regs[regno + i] || global_regs[regno + i])) |
3472 | /* Function calls clobber all call_used regs. */ | |
3473 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3474 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3475 | } | |
3476 | } | |
3477 | else | |
3478 | { | |
63de6c74 MH |
3479 | reg_last_uses[regno] = alloc_INSN_LIST (insn, |
3480 | reg_last_uses[regno]); | |
8c660648 JL |
3481 | |
3482 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3483 | add_dependence (insn, XEXP (u, 0), 0); | |
3484 | ||
28c95eff RH |
3485 | /* ??? This should never happen. */ |
3486 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) | |
3487 | add_dependence (insn, XEXP (u, 0), 0); | |
3488 | ||
8c660648 JL |
3489 | /* Pseudos that are REG_EQUIV to something may be replaced |
3490 | by that during reloading. We need only add dependencies for | |
3491 | the address in the REG_EQUIV note. */ | |
3492 | if (!reload_completed | |
3493 | && reg_known_equiv_p[regno] | |
3494 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3495 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3496 | ||
3497 | /* If the register does not already cross any calls, then add this | |
3498 | insn to the sched_before_next_call list so that it will still | |
3499 | not cross calls after scheduling. */ | |
3500 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3501 | add_dependence (sched_before_next_call, insn, REG_DEP_ANTI); | |
3502 | } | |
3503 | return; | |
3504 | } | |
3505 | ||
3506 | case MEM: | |
3507 | { | |
3508 | /* Reading memory. */ | |
3509 | rtx u; | |
3510 | rtx pending, pending_mem; | |
3511 | ||
3512 | pending = pending_read_insns; | |
3513 | pending_mem = pending_read_mems; | |
3514 | while (pending) | |
3515 | { | |
87373fba RH |
3516 | if (read_dependence (XEXP (pending_mem, 0), x)) |
3517 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3518 | |
3519 | pending = XEXP (pending, 1); | |
3520 | pending_mem = XEXP (pending_mem, 1); | |
3521 | } | |
3522 | ||
3523 | pending = pending_write_insns; | |
3524 | pending_mem = pending_write_mems; | |
3525 | while (pending) | |
3526 | { | |
87373fba RH |
3527 | if (true_dependence (XEXP (pending_mem, 0), VOIDmode, |
3528 | x, rtx_varies_p)) | |
3529 | add_dependence (insn, XEXP (pending, 0), 0); | |
8c660648 JL |
3530 | |
3531 | pending = XEXP (pending, 1); | |
3532 | pending_mem = XEXP (pending_mem, 1); | |
3533 | } | |
3534 | ||
3535 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3536 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3537 | ||
3538 | /* Always add these dependencies to pending_reads, since | |
3539 | this insn may be followed by a write. */ | |
3540 | add_insn_mem_dependence (&pending_read_insns, &pending_read_mems, | |
3541 | insn, x); | |
3542 | ||
3543 | /* Take advantage of tail recursion here. */ | |
3544 | sched_analyze_2 (XEXP (x, 0), insn); | |
3545 | return; | |
3546 | } | |
3547 | ||
e0cd0770 JC |
3548 | /* Force pending stores to memory in case a trap handler needs them. */ |
3549 | case TRAP_IF: | |
3550 | flush_pending_lists (insn, 1); | |
3551 | break; | |
3552 | ||
8c660648 JL |
3553 | case ASM_OPERANDS: |
3554 | case ASM_INPUT: | |
3555 | case UNSPEC_VOLATILE: | |
8c660648 JL |
3556 | { |
3557 | rtx u; | |
3558 | ||
3559 | /* Traditional and volatile asm instructions must be considered to use | |
3560 | and clobber all hard registers, all pseudo-registers and all of | |
3561 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
3562 | ||
3563 | Consider for instance a volatile asm that changes the fpu rounding | |
3564 | mode. An insn should not be moved across this even if it only uses | |
3565 | pseudo-regs because it might give an incorrectly rounded result. */ | |
3566 | if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) | |
3567 | { | |
3568 | int max_reg = max_reg_num (); | |
3569 | for (i = 0; i < max_reg; i++) | |
3570 | { | |
3571 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3572 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3573 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3574 | |
8c660648 JL |
3575 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3576 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3577 | |
3578 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3579 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3580 | } |
3581 | reg_pending_sets_all = 1; | |
3582 | ||
3583 | flush_pending_lists (insn, 0); | |
3584 | } | |
3585 | ||
3586 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
3587 | We can not just fall through here since then we would be confused | |
3588 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
3589 | traditional asms unlike their normal usage. */ | |
3590 | ||
3591 | if (code == ASM_OPERANDS) | |
3592 | { | |
3593 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
3594 | sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn); | |
3595 | return; | |
3596 | } | |
3597 | break; | |
3598 | } | |
3599 | ||
3600 | case PRE_DEC: | |
3601 | case POST_DEC: | |
3602 | case PRE_INC: | |
3603 | case POST_INC: | |
3604 | /* These both read and modify the result. We must handle them as writes | |
3605 | to get proper dependencies for following instructions. We must handle | |
3606 | them as reads to get proper dependencies from this to previous | |
3607 | instructions. Thus we need to pass them to both sched_analyze_1 | |
3608 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
3609 | to get the proper antecedent for the read. */ | |
3610 | sched_analyze_2 (XEXP (x, 0), insn); | |
3611 | sched_analyze_1 (x, insn); | |
3612 | return; | |
5835e573 KG |
3613 | |
3614 | default: | |
3615 | break; | |
8c660648 JL |
3616 | } |
3617 | ||
3618 | /* Other cases: walk the insn. */ | |
3619 | fmt = GET_RTX_FORMAT (code); | |
3620 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3621 | { | |
3622 | if (fmt[i] == 'e') | |
3623 | sched_analyze_2 (XEXP (x, i), insn); | |
3624 | else if (fmt[i] == 'E') | |
3625 | for (j = 0; j < XVECLEN (x, i); j++) | |
3626 | sched_analyze_2 (XVECEXP (x, i, j), insn); | |
3627 | } | |
3628 | } | |
3629 | ||
3630 | /* Analyze an INSN with pattern X to find all dependencies. */ | |
3631 | ||
3632 | static void | |
3633 | sched_analyze_insn (x, insn, loop_notes) | |
3634 | rtx x, insn; | |
3635 | rtx loop_notes; | |
3636 | { | |
3637 | register RTX_CODE code = GET_CODE (x); | |
3638 | rtx link; | |
3639 | int maxreg = max_reg_num (); | |
3640 | int i; | |
3641 | ||
3642 | if (code == SET || code == CLOBBER) | |
3643 | sched_analyze_1 (x, insn); | |
3644 | else if (code == PARALLEL) | |
3645 | { | |
3646 | register int i; | |
3647 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
3648 | { | |
3649 | code = GET_CODE (XVECEXP (x, 0, i)); | |
3650 | if (code == SET || code == CLOBBER) | |
3651 | sched_analyze_1 (XVECEXP (x, 0, i), insn); | |
3652 | else | |
3653 | sched_analyze_2 (XVECEXP (x, 0, i), insn); | |
3654 | } | |
3655 | } | |
3656 | else | |
3657 | sched_analyze_2 (x, insn); | |
3658 | ||
3659 | /* Mark registers CLOBBERED or used by called function. */ | |
3660 | if (GET_CODE (insn) == CALL_INSN) | |
3661 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
3662 | { | |
3663 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
3664 | sched_analyze_1 (XEXP (link, 0), insn); | |
3665 | else | |
3666 | sched_analyze_2 (XEXP (link, 0), insn); | |
3667 | } | |
3668 | ||
1f1ed00c JL |
3669 | /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic |
3670 | block, then we must be sure that no instructions are scheduled across it. | |
8c660648 JL |
3671 | Otherwise, the reg_n_refs info (which depends on loop_depth) would |
3672 | become incorrect. */ | |
3673 | ||
3674 | if (loop_notes) | |
3675 | { | |
3676 | int max_reg = max_reg_num (); | |
1f1ed00c | 3677 | int schedule_barrier_found = 0; |
8c660648 JL |
3678 | rtx link; |
3679 | ||
1f1ed00c JL |
3680 | /* Update loop_notes with any notes from this insn. Also determine |
3681 | if any of the notes on the list correspond to instruction scheduling | |
3682 | barriers (loop, eh & setjmp notes, but not range notes. */ | |
8c660648 JL |
3683 | link = loop_notes; |
3684 | while (XEXP (link, 1)) | |
1f1ed00c | 3685 | { |
54c3cf4b JL |
3686 | if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG |
3687 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END | |
3688 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG | |
3689 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END | |
3690 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP) | |
1f1ed00c JL |
3691 | schedule_barrier_found = 1; |
3692 | ||
3693 | link = XEXP (link, 1); | |
3694 | } | |
8c660648 JL |
3695 | XEXP (link, 1) = REG_NOTES (insn); |
3696 | REG_NOTES (insn) = loop_notes; | |
1f1ed00c JL |
3697 | |
3698 | /* Add dependencies if a scheduling barrier was found. */ | |
3699 | if (schedule_barrier_found) | |
3700 | { | |
3701 | for (i = 0; i < max_reg; i++) | |
3702 | { | |
3703 | rtx u; | |
3704 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3705 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3706 | free_INSN_LIST_list (®_last_uses[i]); |
1f1ed00c | 3707 | |
1f1ed00c JL |
3708 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3709 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3710 | |
3711 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3712 | add_dependence (insn, XEXP (u, 0), 0); | |
1f1ed00c JL |
3713 | } |
3714 | reg_pending_sets_all = 1; | |
3715 | ||
3716 | flush_pending_lists (insn, 0); | |
3717 | } | |
3718 | ||
8c660648 JL |
3719 | } |
3720 | ||
63de6c74 | 3721 | /* Accumulate clobbers until the next set so that it will be output dependent |
28c95eff | 3722 | on all of them. At the next set we can clear the clobber list, since |
63de6c74 | 3723 | subsequent sets will be output dependent on it. */ |
8c660648 JL |
3724 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, |
3725 | { | |
5a4f6418 AM |
3726 | free_INSN_LIST_list (®_last_sets[i]); |
3727 | free_INSN_LIST_list (®_last_clobbers[i]); | |
8c660648 | 3728 | reg_last_sets[i] |
ebb7b10b | 3729 | = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 | 3730 | }); |
28c95eff RH |
3731 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, |
3732 | { | |
3733 | reg_last_clobbers[i] | |
63de6c74 MH |
3734 | = alloc_INSN_LIST (insn, |
3735 | reg_last_clobbers[i]); | |
28c95eff | 3736 | }); |
8c660648 | 3737 | CLEAR_REG_SET (reg_pending_sets); |
28c95eff | 3738 | CLEAR_REG_SET (reg_pending_clobbers); |
8c660648 JL |
3739 | |
3740 | if (reg_pending_sets_all) | |
3741 | { | |
3742 | for (i = 0; i < maxreg; i++) | |
ebb7b10b | 3743 | { |
5a4f6418 | 3744 | free_INSN_LIST_list (®_last_sets[i]); |
c88e8206 | 3745 | free_INSN_LIST_list (®_last_clobbers[i]); |
ebb7b10b RH |
3746 | reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX); |
3747 | } | |
8c660648 JL |
3748 | |
3749 | reg_pending_sets_all = 0; | |
3750 | } | |
3751 | ||
3752 | /* Handle function calls and function returns created by the epilogue | |
3753 | threading code. */ | |
3754 | if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
3755 | { | |
3756 | rtx dep_insn; | |
3757 | rtx prev_dep_insn; | |
3758 | ||
3759 | /* When scheduling instructions, we make sure calls don't lose their | |
3760 | accompanying USE insns by depending them one on another in order. | |
3761 | ||
3762 | Also, we must do the same thing for returns created by the epilogue | |
3763 | threading code. Note this code works only in this special case, | |
3764 | because other passes make no guarantee that they will never emit | |
3765 | an instruction between a USE and a RETURN. There is such a guarantee | |
3766 | for USE instructions immediately before a call. */ | |
3767 | ||
3768 | prev_dep_insn = insn; | |
3769 | dep_insn = PREV_INSN (insn); | |
3770 | while (GET_CODE (dep_insn) == INSN | |
3771 | && GET_CODE (PATTERN (dep_insn)) == USE | |
3772 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG) | |
3773 | { | |
3774 | SCHED_GROUP_P (prev_dep_insn) = 1; | |
3775 | ||
3776 | /* Make a copy of all dependencies on dep_insn, and add to insn. | |
3777 | This is so that all of the dependencies will apply to the | |
3778 | group. */ | |
3779 | ||
3780 | for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1)) | |
3781 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3782 | ||
3783 | prev_dep_insn = dep_insn; | |
3784 | dep_insn = PREV_INSN (dep_insn); | |
3785 | } | |
3786 | } | |
3787 | } | |
3788 | ||
3789 | /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS | |
3790 | for every dependency. */ | |
3791 | ||
3792 | static void | |
3793 | sched_analyze (head, tail) | |
3794 | rtx head, tail; | |
3795 | { | |
3796 | register rtx insn; | |
3797 | register rtx u; | |
3798 | rtx loop_notes = 0; | |
3799 | ||
3800 | for (insn = head;; insn = NEXT_INSN (insn)) | |
3801 | { | |
3802 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) | |
3803 | { | |
87373fba RH |
3804 | /* Clear out the stale LOG_LINKS from flow. */ |
3805 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3806 | ||
63de6c74 MH |
3807 | /* Make each JUMP_INSN a scheduling barrier for memory |
3808 | references. */ | |
062ae7ed JL |
3809 | if (GET_CODE (insn) == JUMP_INSN) |
3810 | last_pending_memory_flush | |
3811 | = alloc_INSN_LIST (insn, last_pending_memory_flush); | |
8c660648 JL |
3812 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); |
3813 | loop_notes = 0; | |
3814 | } | |
3815 | else if (GET_CODE (insn) == CALL_INSN) | |
3816 | { | |
3817 | rtx x; | |
3818 | register int i; | |
3819 | ||
3820 | CANT_MOVE (insn) = 1; | |
3821 | ||
87373fba RH |
3822 | /* Clear out the stale LOG_LINKS from flow. */ |
3823 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3824 | ||
8c660648 JL |
3825 | /* Any instruction using a hard register which may get clobbered |
3826 | by a call needs to be marked as dependent on this call. | |
3827 | This prevents a use of a hard return reg from being moved | |
3828 | past a void call (i.e. it does not explicitly set the hard | |
3829 | return reg). */ | |
3830 | ||
3831 | /* If this call is followed by a NOTE_INSN_SETJMP, then assume that | |
3832 | all registers, not just hard registers, may be clobbered by this | |
3833 | call. */ | |
3834 | ||
3835 | /* Insn, being a CALL_INSN, magically depends on | |
3836 | `last_function_call' already. */ | |
3837 | ||
3838 | if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE | |
3839 | && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP) | |
3840 | { | |
3841 | int max_reg = max_reg_num (); | |
3842 | for (i = 0; i < max_reg; i++) | |
3843 | { | |
3844 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3845 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3846 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3847 | |
8c660648 JL |
3848 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3849 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3850 | |
3851 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3852 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3853 | } |
3854 | reg_pending_sets_all = 1; | |
3855 | ||
c46a37c4 | 3856 | /* Add a pair of REG_SAVE_NOTEs which we will later |
8c660648 JL |
3857 | convert back into a NOTE_INSN_SETJMP note. See |
3858 | reemit_notes for why we use a pair of NOTEs. */ | |
c46a37c4 | 3859 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3860 | GEN_INT (0), |
3861 | REG_NOTES (insn)); | |
c46a37c4 | 3862 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3863 | GEN_INT (NOTE_INSN_SETJMP), |
3864 | REG_NOTES (insn)); | |
8c660648 JL |
3865 | } |
3866 | else | |
3867 | { | |
3868 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3869 | if (call_used_regs[i] || global_regs[i]) | |
3870 | { | |
3871 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3872 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 | 3873 | |
8c660648 JL |
3874 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3875 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3876 | ||
c1cb76e9 | 3877 | SET_REGNO_REG_SET (reg_pending_clobbers, i); |
8c660648 JL |
3878 | } |
3879 | } | |
3880 | ||
3881 | /* For each insn which shouldn't cross a call, add a dependence | |
3882 | between that insn and this call insn. */ | |
3883 | x = LOG_LINKS (sched_before_next_call); | |
3884 | while (x) | |
3885 | { | |
3886 | add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI); | |
3887 | x = XEXP (x, 1); | |
3888 | } | |
2a780534 | 3889 | free_INSN_LIST_list (&LOG_LINKS (sched_before_next_call)); |
8c660648 JL |
3890 | |
3891 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); | |
3892 | loop_notes = 0; | |
3893 | ||
3894 | /* In the absence of interprocedural alias analysis, we must flush | |
3895 | all pending reads and writes, and start new dependencies starting | |
3896 | from here. But only flush writes for constant calls (which may | |
3897 | be passed a pointer to something we haven't written yet). */ | |
3898 | flush_pending_lists (insn, CONST_CALL_P (insn)); | |
3899 | ||
3900 | /* Depend this function call (actually, the user of this | |
3901 | function call) on all hard register clobberage. */ | |
3902 | ||
63de6c74 | 3903 | /* last_function_call is now a list of insns. */ |
5a4f6418 | 3904 | free_INSN_LIST_list(&last_function_call); |
ebb7b10b | 3905 | last_function_call = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3906 | } |
3907 | ||
63de6c74 MH |
3908 | /* See comments on reemit_notes as to why we do this. |
3909 | ??? Actually, the reemit_notes just say what is done, not why. */ | |
6dfdecdb RH |
3910 | |
3911 | else if (GET_CODE (insn) == NOTE | |
3912 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START | |
3913 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END)) | |
3914 | { | |
c46a37c4 | 3915 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, NOTE_RANGE_INFO (insn), |
6dfdecdb | 3916 | loop_notes); |
c46a37c4 | 3917 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
6dfdecdb RH |
3918 | GEN_INT (NOTE_LINE_NUMBER (insn)), |
3919 | loop_notes); | |
3920 | } | |
8c660648 JL |
3921 | else if (GET_CODE (insn) == NOTE |
3922 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG | |
3923 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END | |
3924 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG | |
3925 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END | |
3926 | || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP | |
3927 | && GET_CODE (PREV_INSN (insn)) != CALL_INSN))) | |
3928 | { | |
f5db61ef | 3929 | rtx rtx_region; |
7bd41ea6 | 3930 | |
1a4450c7 MM |
3931 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG |
3932 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END) | |
f5db61ef | 3933 | rtx_region = GEN_INT (NOTE_EH_HANDLER (insn)); |
7bd41ea6 | 3934 | else |
f5db61ef | 3935 | rtx_region = GEN_INT (0); |
1a4450c7 | 3936 | |
c46a37c4 | 3937 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
f5db61ef | 3938 | rtx_region, |
7bd41ea6 | 3939 | loop_notes); |
c46a37c4 | 3940 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3941 | GEN_INT (NOTE_LINE_NUMBER (insn)), |
3942 | loop_notes); | |
8c660648 JL |
3943 | CONST_CALL_P (loop_notes) = CONST_CALL_P (insn); |
3944 | } | |
3945 | ||
3946 | if (insn == tail) | |
3947 | return; | |
3948 | } | |
3949 | abort (); | |
3950 | } | |
3951 | \f | |
8c660648 JL |
3952 | /* Macros and functions for keeping the priority queue sorted, and |
3953 | dealing with queueing and dequeueing of instructions. */ | |
3954 | ||
3955 | #define SCHED_SORT(READY, N_READY) \ | |
3956 | do { if ((N_READY) == 2) \ | |
3957 | swap_sort (READY, N_READY); \ | |
3958 | else if ((N_READY) > 2) \ | |
3959 | qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ | |
3960 | while (0) | |
3961 | ||
3962 | /* Returns a positive value if x is preferred; returns a negative value if | |
3963 | y is preferred. Should never return 0, since that will make the sort | |
3964 | unstable. */ | |
3965 | ||
3966 | static int | |
3967 | rank_for_schedule (x, y) | |
e1b6684c KG |
3968 | const PTR x; |
3969 | const PTR y; | |
8c660648 | 3970 | { |
01c7f350 MM |
3971 | rtx tmp = *(rtx *)y; |
3972 | rtx tmp2 = *(rtx *)x; | |
8c660648 | 3973 | rtx link; |
2db45993 | 3974 | int tmp_class, tmp2_class, depend_count1, depend_count2; |
8c660648 JL |
3975 | int val, priority_val, spec_val, prob_val, weight_val; |
3976 | ||
3977 | ||
63de6c74 | 3978 | /* Prefer insn with higher priority. */ |
8c660648 JL |
3979 | priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp); |
3980 | if (priority_val) | |
3981 | return priority_val; | |
3982 | ||
63de6c74 | 3983 | /* Prefer an insn with smaller contribution to registers-pressure. */ |
8c660648 JL |
3984 | if (!reload_completed && |
3985 | (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2))) | |
3986 | return (weight_val); | |
3987 | ||
63de6c74 | 3988 | /* Some comparison make sense in interblock scheduling only. */ |
8c660648 JL |
3989 | if (INSN_BB (tmp) != INSN_BB (tmp2)) |
3990 | { | |
63de6c74 | 3991 | /* Prefer an inblock motion on an interblock motion. */ |
8c660648 JL |
3992 | if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb)) |
3993 | return 1; | |
3994 | if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb)) | |
3995 | return -1; | |
3996 | ||
63de6c74 | 3997 | /* Prefer a useful motion on a speculative one. */ |
8c660648 JL |
3998 | if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2))) |
3999 | return (spec_val); | |
4000 | ||
63de6c74 | 4001 | /* Prefer a more probable (speculative) insn. */ |
8c660648 JL |
4002 | prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp); |
4003 | if (prob_val) | |
4004 | return (prob_val); | |
4005 | } | |
4006 | ||
63de6c74 | 4007 | /* Compare insns based on their relation to the last-scheduled-insn. */ |
8c660648 JL |
4008 | if (last_scheduled_insn) |
4009 | { | |
4010 | /* Classify the instructions into three classes: | |
4011 | 1) Data dependent on last schedule insn. | |
4012 | 2) Anti/Output dependent on last scheduled insn. | |
4013 | 3) Independent of last scheduled insn, or has latency of one. | |
4014 | Choose the insn from the highest numbered class if different. */ | |
4015 | link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn)); | |
4016 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1) | |
4017 | tmp_class = 3; | |
4018 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4019 | tmp_class = 1; | |
4020 | else | |
4021 | tmp_class = 2; | |
4022 | ||
4023 | link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn)); | |
4024 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1) | |
4025 | tmp2_class = 3; | |
4026 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4027 | tmp2_class = 1; | |
4028 | else | |
4029 | tmp2_class = 2; | |
4030 | ||
4031 | if ((val = tmp2_class - tmp_class)) | |
4032 | return val; | |
4033 | } | |
4034 | ||
2db45993 JL |
4035 | /* Prefer the insn which has more later insns that depend on it. |
4036 | This gives the scheduler more freedom when scheduling later | |
4037 | instructions at the expense of added register pressure. */ | |
4038 | depend_count1 = 0; | |
4039 | for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1)) | |
4040 | depend_count1++; | |
4041 | ||
4042 | depend_count2 = 0; | |
4043 | for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1)) | |
4044 | depend_count2++; | |
4045 | ||
4046 | val = depend_count2 - depend_count1; | |
4047 | if (val) | |
4048 | return val; | |
4049 | ||
8c660648 JL |
4050 | /* If insns are equally good, sort by INSN_LUID (original insn order), |
4051 | so that we make the sort stable. This minimizes instruction movement, | |
4052 | thus minimizing sched's effect on debugging and cross-jumping. */ | |
4053 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
4054 | } | |
4055 | ||
4056 | /* Resort the array A in which only element at index N may be out of order. */ | |
4057 | ||
cbb13457 | 4058 | HAIFA_INLINE static void |
8c660648 JL |
4059 | swap_sort (a, n) |
4060 | rtx *a; | |
4061 | int n; | |
4062 | { | |
4063 | rtx insn = a[n - 1]; | |
4064 | int i = n - 2; | |
4065 | ||
4066 | while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0) | |
4067 | { | |
4068 | a[i + 1] = a[i]; | |
4069 | i -= 1; | |
4070 | } | |
4071 | a[i + 1] = insn; | |
4072 | } | |
4073 | ||
4074 | static int max_priority; | |
4075 | ||
4076 | /* Add INSN to the insn queue so that it can be executed at least | |
4077 | N_CYCLES after the currently executing insn. Preserve insns | |
4078 | chain for debugging purposes. */ | |
4079 | ||
cbb13457 | 4080 | HAIFA_INLINE static void |
8c660648 JL |
4081 | queue_insn (insn, n_cycles) |
4082 | rtx insn; | |
4083 | int n_cycles; | |
4084 | { | |
4085 | int next_q = NEXT_Q_AFTER (q_ptr, n_cycles); | |
ebb7b10b | 4086 | rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]); |
8c660648 JL |
4087 | insn_queue[next_q] = link; |
4088 | q_size += 1; | |
4089 | ||
4090 | if (sched_verbose >= 2) | |
4091 | { | |
4092 | fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn)); | |
4093 | ||
4094 | if (INSN_BB (insn) != target_bb) | |
c88e8206 | 4095 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4096 | |
4097 | fprintf (dump, "queued for %d cycles.\n", n_cycles); | |
4098 | } | |
4099 | ||
4100 | } | |
4101 | ||
8c660648 | 4102 | /* PREV is an insn that is ready to execute. Adjust its priority if that |
c46a37c4 RH |
4103 | will help shorten or lengthen register lifetimes as appropriate. Also |
4104 | provide a hook for the target to tweek itself. */ | |
8c660648 | 4105 | |
cbb13457 | 4106 | HAIFA_INLINE static void |
8c660648 | 4107 | adjust_priority (prev) |
c46a37c4 | 4108 | rtx prev ATTRIBUTE_UNUSED; |
8c660648 | 4109 | { |
c46a37c4 RH |
4110 | /* ??? There used to be code here to try and estimate how an insn |
4111 | affected register lifetimes, but it did it by looking at REG_DEAD | |
4112 | notes, which we removed in schedule_region. Nor did it try to | |
4113 | take into account register pressure or anything useful like that. | |
8c660648 | 4114 | |
c46a37c4 | 4115 | Revisit when we have a machine model to work with and not before. */ |
197043f5 | 4116 | |
8c660648 | 4117 | #ifdef ADJUST_PRIORITY |
197043f5 | 4118 | ADJUST_PRIORITY (prev); |
8c660648 | 4119 | #endif |
8c660648 JL |
4120 | } |
4121 | ||
4bdc8810 RH |
4122 | /* Clock at which the previous instruction was issued. */ |
4123 | static int last_clock_var; | |
4124 | ||
8c660648 JL |
4125 | /* INSN is the "currently executing insn". Launch each insn which was |
4126 | waiting on INSN. READY is a vector of insns which are ready to fire. | |
4127 | N_READY is the number of elements in READY. CLOCK is the current | |
4128 | cycle. */ | |
4129 | ||
4130 | static int | |
4131 | schedule_insn (insn, ready, n_ready, clock) | |
4132 | rtx insn; | |
4133 | rtx *ready; | |
4134 | int n_ready; | |
4135 | int clock; | |
4136 | { | |
4137 | rtx link; | |
4138 | int unit; | |
4139 | ||
4140 | unit = insn_unit (insn); | |
4141 | ||
4142 | if (sched_verbose >= 2) | |
4143 | { | |
63de6c74 MH |
4144 | fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", |
4145 | INSN_UID (insn)); | |
8c660648 JL |
4146 | insn_print_units (insn); |
4147 | fprintf (dump, "\n"); | |
4148 | } | |
4149 | ||
4150 | if (sched_verbose && unit == -1) | |
4151 | visualize_no_unit (insn); | |
4152 | ||
4153 | if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose) | |
4154 | schedule_unit (unit, insn, clock); | |
4155 | ||
4156 | if (INSN_DEPEND (insn) == 0) | |
4157 | return n_ready; | |
4158 | ||
4159 | /* This is used by the function adjust_priority above. */ | |
4160 | if (n_ready > 0) | |
4161 | max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn)); | |
4162 | else | |
4163 | max_priority = INSN_PRIORITY (insn); | |
4164 | ||
4165 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
4166 | { | |
4167 | rtx next = XEXP (link, 0); | |
4168 | int cost = insn_cost (insn, link, next); | |
4169 | ||
4170 | INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost); | |
4171 | ||
4172 | if ((INSN_DEP_COUNT (next) -= 1) == 0) | |
4173 | { | |
4174 | int effective_cost = INSN_TICK (next) - clock; | |
4175 | ||
4176 | /* For speculative insns, before inserting to ready/queue, | |
63de6c74 | 4177 | check live, exception-free, and issue-delay. */ |
8c660648 JL |
4178 | if (INSN_BB (next) != target_bb |
4179 | && (!IS_VALID (INSN_BB (next)) | |
4180 | || CANT_MOVE (next) | |
4181 | || (IS_SPECULATIVE_INSN (next) | |
4182 | && (insn_issue_delay (next) > 3 | |
5835e573 | 4183 | || !check_live (next, INSN_BB (next)) |
8c660648 JL |
4184 | || !is_exception_free (next, INSN_BB (next), target_bb))))) |
4185 | continue; | |
4186 | ||
4187 | if (sched_verbose >= 2) | |
4188 | { | |
63de6c74 MH |
4189 | fprintf (dump, ";;\t\tdependences resolved: insn %d ", |
4190 | INSN_UID (next)); | |
8c660648 JL |
4191 | |
4192 | if (current_nr_blocks > 1 && INSN_BB (next) != target_bb) | |
c88e8206 | 4193 | fprintf (dump, "/b%d ", BLOCK_NUM (next)); |
8c660648 | 4194 | |
197043f5 | 4195 | if (effective_cost < 1) |
8c660648 JL |
4196 | fprintf (dump, "into ready\n"); |
4197 | else | |
4198 | fprintf (dump, "into queue with cost=%d\n", effective_cost); | |
4199 | } | |
4200 | ||
4201 | /* Adjust the priority of NEXT and either put it on the ready | |
4202 | list or queue it. */ | |
4203 | adjust_priority (next); | |
197043f5 | 4204 | if (effective_cost < 1) |
8c660648 JL |
4205 | ready[n_ready++] = next; |
4206 | else | |
4207 | queue_insn (next, effective_cost); | |
4208 | } | |
4209 | } | |
4210 | ||
4bdc8810 RH |
4211 | /* Annotate the instruction with issue information -- TImode |
4212 | indicates that the instruction is expected not to be able | |
4213 | to issue on the same cycle as the previous insn. A machine | |
4214 | may use this information to decide how the instruction should | |
4215 | be aligned. */ | |
4216 | if (reload_completed && issue_rate > 1) | |
4217 | { | |
4218 | PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode); | |
4219 | last_clock_var = clock; | |
4220 | } | |
4221 | ||
8c660648 JL |
4222 | return n_ready; |
4223 | } | |
4224 | ||
63de6c74 | 4225 | /* Functions for handling of notes. */ |
8c660648 JL |
4226 | |
4227 | /* Delete notes beginning with INSN and put them in the chain | |
4228 | of notes ended by NOTE_LIST. | |
4229 | Returns the insn following the notes. */ | |
4230 | ||
4231 | static rtx | |
4232 | unlink_other_notes (insn, tail) | |
4233 | rtx insn, tail; | |
4234 | { | |
4235 | rtx prev = PREV_INSN (insn); | |
4236 | ||
4237 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4238 | { | |
4239 | rtx next = NEXT_INSN (insn); | |
4240 | /* Delete the note from its current position. */ | |
4241 | if (prev) | |
4242 | NEXT_INSN (prev) = next; | |
4243 | if (next) | |
4244 | PREV_INSN (next) = prev; | |
4245 | ||
c46a37c4 | 4246 | /* See sched_analyze to see how these are handled. */ |
8c660648 JL |
4247 | if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP |
4248 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG | |
4249 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END | |
0dfa1860 MM |
4250 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START |
4251 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END | |
8c660648 JL |
4252 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG |
4253 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END) | |
4254 | { | |
4255 | /* Insert the note at the end of the notes list. */ | |
4256 | PREV_INSN (insn) = note_list; | |
4257 | if (note_list) | |
4258 | NEXT_INSN (note_list) = insn; | |
4259 | note_list = insn; | |
4260 | } | |
4261 | ||
4262 | insn = next; | |
4263 | } | |
4264 | return insn; | |
4265 | } | |
4266 | ||
4267 | /* Delete line notes beginning with INSN. Record line-number notes so | |
4268 | they can be reused. Returns the insn following the notes. */ | |
4269 | ||
4270 | static rtx | |
4271 | unlink_line_notes (insn, tail) | |
4272 | rtx insn, tail; | |
4273 | { | |
4274 | rtx prev = PREV_INSN (insn); | |
4275 | ||
4276 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4277 | { | |
4278 | rtx next = NEXT_INSN (insn); | |
4279 | ||
4280 | if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0) | |
4281 | { | |
4282 | /* Delete the note from its current position. */ | |
4283 | if (prev) | |
4284 | NEXT_INSN (prev) = next; | |
4285 | if (next) | |
4286 | PREV_INSN (next) = prev; | |
4287 | ||
4288 | /* Record line-number notes so they can be reused. */ | |
4289 | LINE_NOTE (insn) = insn; | |
4290 | } | |
4291 | else | |
4292 | prev = insn; | |
4293 | ||
4294 | insn = next; | |
4295 | } | |
4296 | return insn; | |
4297 | } | |
4298 | ||
4299 | /* Return the head and tail pointers of BB. */ | |
4300 | ||
cbb13457 | 4301 | HAIFA_INLINE static void |
8c660648 JL |
4302 | get_block_head_tail (bb, headp, tailp) |
4303 | int bb; | |
4304 | rtx *headp; | |
4305 | rtx *tailp; | |
4306 | { | |
4307 | ||
55d89719 TK |
4308 | rtx head; |
4309 | rtx tail; | |
8c660648 JL |
4310 | int b; |
4311 | ||
4312 | b = BB_TO_BLOCK (bb); | |
4313 | ||
4314 | /* HEAD and TAIL delimit the basic block being scheduled. */ | |
3b413743 RH |
4315 | head = BLOCK_HEAD (b); |
4316 | tail = BLOCK_END (b); | |
8c660648 JL |
4317 | |
4318 | /* Don't include any notes or labels at the beginning of the | |
4319 | basic block, or notes at the ends of basic blocks. */ | |
4320 | while (head != tail) | |
4321 | { | |
4322 | if (GET_CODE (head) == NOTE) | |
4323 | head = NEXT_INSN (head); | |
4324 | else if (GET_CODE (tail) == NOTE) | |
4325 | tail = PREV_INSN (tail); | |
4326 | else if (GET_CODE (head) == CODE_LABEL) | |
4327 | head = NEXT_INSN (head); | |
4328 | else | |
4329 | break; | |
4330 | } | |
4331 | ||
4332 | *headp = head; | |
4333 | *tailp = tail; | |
4334 | } | |
4335 | ||
4336 | /* Delete line notes from bb. Save them so they can be later restored | |
4337 | (in restore_line_notes ()). */ | |
4338 | ||
4339 | static void | |
4340 | rm_line_notes (bb) | |
4341 | int bb; | |
4342 | { | |
4343 | rtx next_tail; | |
4344 | rtx tail; | |
4345 | rtx head; | |
4346 | rtx insn; | |
4347 | ||
4348 | get_block_head_tail (bb, &head, &tail); | |
4349 | ||
4350 | if (head == tail | |
4351 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
4352 | return; | |
4353 | ||
4354 | next_tail = NEXT_INSN (tail); | |
4355 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4356 | { | |
4357 | rtx prev; | |
4358 | ||
4359 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4360 | This is needed to keep the debugger from | |
4361 | getting completely deranged. */ | |
4362 | if (GET_CODE (insn) == NOTE) | |
4363 | { | |
4364 | prev = insn; | |
4365 | insn = unlink_line_notes (insn, next_tail); | |
4366 | ||
4367 | if (prev == tail) | |
4368 | abort (); | |
4369 | if (prev == head) | |
4370 | abort (); | |
4371 | if (insn == next_tail) | |
4372 | abort (); | |
4373 | } | |
4374 | } | |
4375 | } | |
4376 | ||
4377 | /* Save line number notes for each insn in bb. */ | |
4378 | ||
4379 | static void | |
4380 | save_line_notes (bb) | |
4381 | int bb; | |
4382 | { | |
4383 | rtx head, tail; | |
4384 | rtx next_tail; | |
4385 | ||
4386 | /* We must use the true line number for the first insn in the block | |
4387 | that was computed and saved at the start of this pass. We can't | |
4388 | use the current line number, because scheduling of the previous | |
4389 | block may have changed the current line number. */ | |
4390 | ||
4391 | rtx line = line_note_head[BB_TO_BLOCK (bb)]; | |
4392 | rtx insn; | |
4393 | ||
4394 | get_block_head_tail (bb, &head, &tail); | |
4395 | next_tail = NEXT_INSN (tail); | |
4396 | ||
3b413743 | 4397 | for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb)); |
8c660648 JL |
4398 | insn != next_tail; |
4399 | insn = NEXT_INSN (insn)) | |
4400 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4401 | line = insn; | |
4402 | else | |
4403 | LINE_NOTE (insn) = line; | |
4404 | } | |
4405 | ||
4406 | ||
4407 | /* After bb was scheduled, insert line notes into the insns list. */ | |
4408 | ||
4409 | static void | |
4410 | restore_line_notes (bb) | |
4411 | int bb; | |
4412 | { | |
4413 | rtx line, note, prev, new; | |
4414 | int added_notes = 0; | |
4415 | int b; | |
4416 | rtx head, next_tail, insn; | |
4417 | ||
4418 | b = BB_TO_BLOCK (bb); | |
4419 | ||
3b413743 RH |
4420 | head = BLOCK_HEAD (b); |
4421 | next_tail = NEXT_INSN (BLOCK_END (b)); | |
8c660648 JL |
4422 | |
4423 | /* Determine the current line-number. We want to know the current | |
4424 | line number of the first insn of the block here, in case it is | |
4425 | different from the true line number that was saved earlier. If | |
4426 | different, then we need a line number note before the first insn | |
4427 | of this block. If it happens to be the same, then we don't want to | |
4428 | emit another line number note here. */ | |
4429 | for (line = head; line; line = PREV_INSN (line)) | |
4430 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) | |
4431 | break; | |
4432 | ||
4433 | /* Walk the insns keeping track of the current line-number and inserting | |
4434 | the line-number notes as needed. */ | |
4435 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4436 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4437 | line = insn; | |
4438 | /* This used to emit line number notes before every non-deleted note. | |
4439 | However, this confuses a debugger, because line notes not separated | |
4440 | by real instructions all end up at the same address. I can find no | |
4441 | use for line number notes before other notes, so none are emitted. */ | |
4442 | else if (GET_CODE (insn) != NOTE | |
4443 | && (note = LINE_NOTE (insn)) != 0 | |
4444 | && note != line | |
4445 | && (line == 0 | |
4446 | || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line) | |
4447 | || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line))) | |
4448 | { | |
4449 | line = note; | |
4450 | prev = PREV_INSN (insn); | |
4451 | if (LINE_NOTE (note)) | |
4452 | { | |
4453 | /* Re-use the original line-number note. */ | |
4454 | LINE_NOTE (note) = 0; | |
4455 | PREV_INSN (note) = prev; | |
4456 | NEXT_INSN (prev) = note; | |
4457 | PREV_INSN (insn) = note; | |
4458 | NEXT_INSN (note) = insn; | |
4459 | } | |
4460 | else | |
4461 | { | |
4462 | added_notes++; | |
4463 | new = emit_note_after (NOTE_LINE_NUMBER (note), prev); | |
4464 | NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note); | |
4465 | RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note); | |
4466 | } | |
4467 | } | |
4468 | if (sched_verbose && added_notes) | |
4469 | fprintf (dump, ";; added %d line-number notes\n", added_notes); | |
4470 | } | |
4471 | ||
4472 | /* After scheduling the function, delete redundant line notes from the | |
4473 | insns list. */ | |
4474 | ||
4475 | static void | |
4476 | rm_redundant_line_notes () | |
4477 | { | |
4478 | rtx line = 0; | |
4479 | rtx insn = get_insns (); | |
4480 | int active_insn = 0; | |
4481 | int notes = 0; | |
4482 | ||
4483 | /* Walk the insns deleting redundant line-number notes. Many of these | |
4484 | are already present. The remainder tend to occur at basic | |
4485 | block boundaries. */ | |
4486 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
4487 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4488 | { | |
4489 | /* If there are no active insns following, INSN is redundant. */ | |
4490 | if (active_insn == 0) | |
4491 | { | |
4492 | notes++; | |
4493 | NOTE_SOURCE_FILE (insn) = 0; | |
4494 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
4495 | } | |
4496 | /* If the line number is unchanged, LINE is redundant. */ | |
4497 | else if (line | |
4498 | && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn) | |
4499 | && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn)) | |
4500 | { | |
4501 | notes++; | |
4502 | NOTE_SOURCE_FILE (line) = 0; | |
4503 | NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED; | |
4504 | line = insn; | |
4505 | } | |
4506 | else | |
4507 | line = insn; | |
4508 | active_insn = 0; | |
4509 | } | |
4510 | else if (!((GET_CODE (insn) == NOTE | |
4511 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) | |
4512 | || (GET_CODE (insn) == INSN | |
4513 | && (GET_CODE (PATTERN (insn)) == USE | |
4514 | || GET_CODE (PATTERN (insn)) == CLOBBER)))) | |
4515 | active_insn++; | |
4516 | ||
4517 | if (sched_verbose && notes) | |
4518 | fprintf (dump, ";; deleted %d line-number notes\n", notes); | |
4519 | } | |
4520 | ||
4521 | /* Delete notes between head and tail and put them in the chain | |
4522 | of notes ended by NOTE_LIST. */ | |
4523 | ||
4524 | static void | |
4525 | rm_other_notes (head, tail) | |
4526 | rtx head; | |
4527 | rtx tail; | |
4528 | { | |
4529 | rtx next_tail; | |
4530 | rtx insn; | |
4531 | ||
4532 | if (head == tail | |
4533 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
4534 | return; | |
4535 | ||
4536 | next_tail = NEXT_INSN (tail); | |
4537 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4538 | { | |
4539 | rtx prev; | |
4540 | ||
4541 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4542 | This is needed to keep the debugger from | |
4543 | getting completely deranged. */ | |
4544 | if (GET_CODE (insn) == NOTE) | |
4545 | { | |
4546 | prev = insn; | |
4547 | ||
4548 | insn = unlink_other_notes (insn, next_tail); | |
4549 | ||
4550 | if (prev == tail) | |
4551 | abort (); | |
4552 | if (prev == head) | |
4553 | abort (); | |
4554 | if (insn == next_tail) | |
4555 | abort (); | |
4556 | } | |
4557 | } | |
4558 | } | |
4559 | ||
63de6c74 | 4560 | /* Functions for computation of registers live/usage info. */ |
8c660648 | 4561 | |
c46a37c4 | 4562 | /* Calculate INSN_REG_WEIGHT for all insns of a block. */ |
8c660648 JL |
4563 | |
4564 | static void | |
c46a37c4 RH |
4565 | find_insn_reg_weight (bb) |
4566 | int bb; | |
8c660648 JL |
4567 | { |
4568 | rtx insn, next_tail, head, tail; | |
8c660648 JL |
4569 | |
4570 | get_block_head_tail (bb, &head, &tail); | |
8c660648 JL |
4571 | next_tail = NEXT_INSN (tail); |
4572 | ||
4573 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4574 | { | |
8c660648 | 4575 | int reg_weight = 0; |
c46a37c4 | 4576 | rtx x; |
8c660648 JL |
4577 | |
4578 | /* Handle register life information. */ | |
8c660648 JL |
4579 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') |
4580 | continue; | |
4581 | ||
c46a37c4 RH |
4582 | /* Increment weight for each register born here. */ |
4583 | x = PATTERN (insn); | |
4584 | if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
4585 | && register_operand (SET_DEST (x), VOIDmode)) | |
4586 | reg_weight++; | |
4587 | else if (GET_CODE (x) == PARALLEL) | |
8c660648 | 4588 | { |
c46a37c4 RH |
4589 | int j; |
4590 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
4591 | { | |
4592 | x = XVECEXP (PATTERN (insn), 0, j); | |
4593 | if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
4594 | && register_operand (SET_DEST (x), VOIDmode)) | |
4595 | reg_weight++; | |
4596 | } | |
8c660648 JL |
4597 | } |
4598 | ||
c46a37c4 RH |
4599 | /* Decrement weight for each register that dies here. */ |
4600 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
8c660648 | 4601 | { |
c46a37c4 RH |
4602 | if (REG_NOTE_KIND (x) == REG_DEAD |
4603 | || REG_NOTE_KIND (x) == REG_UNUSED) | |
4604 | reg_weight--; | |
8c660648 JL |
4605 | } |
4606 | ||
c46a37c4 | 4607 | INSN_REG_WEIGHT (insn) = reg_weight; |
8c660648 | 4608 | } |
8c660648 JL |
4609 | } |
4610 | ||
63de6c74 | 4611 | /* Scheduling clock, modified in schedule_block() and queue_to_ready (). */ |
8c660648 JL |
4612 | static int clock_var; |
4613 | ||
4614 | /* Move insns that became ready to fire from queue to ready list. */ | |
4615 | ||
4616 | static int | |
4617 | queue_to_ready (ready, n_ready) | |
4618 | rtx ready[]; | |
4619 | int n_ready; | |
4620 | { | |
4621 | rtx insn; | |
4622 | rtx link; | |
4623 | ||
4624 | q_ptr = NEXT_Q (q_ptr); | |
4625 | ||
4626 | /* Add all pending insns that can be scheduled without stalls to the | |
4627 | ready list. */ | |
4628 | for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1)) | |
4629 | { | |
4630 | ||
4631 | insn = XEXP (link, 0); | |
4632 | q_size -= 1; | |
4633 | ||
4634 | if (sched_verbose >= 2) | |
4635 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
4636 | ||
4637 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
c88e8206 | 4638 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4639 | |
4640 | ready[n_ready++] = insn; | |
4641 | if (sched_verbose >= 2) | |
4642 | fprintf (dump, "moving to ready without stalls\n"); | |
4643 | } | |
4644 | insn_queue[q_ptr] = 0; | |
4645 | ||
4646 | /* If there are no ready insns, stall until one is ready and add all | |
4647 | of the pending insns at that point to the ready list. */ | |
4648 | if (n_ready == 0) | |
4649 | { | |
4650 | register int stalls; | |
4651 | ||
4652 | for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++) | |
4653 | { | |
4654 | if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])) | |
4655 | { | |
4656 | for (; link; link = XEXP (link, 1)) | |
4657 | { | |
4658 | insn = XEXP (link, 0); | |
4659 | q_size -= 1; | |
4660 | ||
4661 | if (sched_verbose >= 2) | |
4662 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
4663 | ||
4664 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
c88e8206 | 4665 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4666 | |
4667 | ready[n_ready++] = insn; | |
4668 | if (sched_verbose >= 2) | |
4669 | fprintf (dump, "moving to ready with %d stalls\n", stalls); | |
4670 | } | |
4671 | insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0; | |
4672 | ||
4673 | if (n_ready) | |
4674 | break; | |
4675 | } | |
4676 | } | |
4677 | ||
4678 | if (sched_verbose && stalls) | |
4679 | visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls); | |
4680 | q_ptr = NEXT_Q_AFTER (q_ptr, stalls); | |
4681 | clock_var += stalls; | |
4682 | } | |
4683 | return n_ready; | |
4684 | } | |
4685 | ||
63de6c74 | 4686 | /* Print the ready list for debugging purposes. Callable from debugger. */ |
8c660648 | 4687 | |
9a8b0889 | 4688 | static void |
8c660648 JL |
4689 | debug_ready_list (ready, n_ready) |
4690 | rtx ready[]; | |
4691 | int n_ready; | |
4692 | { | |
4693 | int i; | |
4694 | ||
4695 | for (i = 0; i < n_ready; i++) | |
4696 | { | |
4697 | fprintf (dump, " %d", INSN_UID (ready[i])); | |
4698 | if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb) | |
c88e8206 | 4699 | fprintf (dump, "/b%d", BLOCK_NUM (ready[i])); |
8c660648 JL |
4700 | } |
4701 | fprintf (dump, "\n"); | |
4702 | } | |
4703 | ||
4704 | /* Print names of units on which insn can/should execute, for debugging. */ | |
4705 | ||
4706 | static void | |
4707 | insn_print_units (insn) | |
4708 | rtx insn; | |
4709 | { | |
4710 | int i; | |
4711 | int unit = insn_unit (insn); | |
4712 | ||
4713 | if (unit == -1) | |
4714 | fprintf (dump, "none"); | |
4715 | else if (unit >= 0) | |
4716 | fprintf (dump, "%s", function_units[unit].name); | |
4717 | else | |
4718 | { | |
4719 | fprintf (dump, "["); | |
4720 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
4721 | if (unit & 1) | |
4722 | { | |
4723 | fprintf (dump, "%s", function_units[i].name); | |
4724 | if (unit != 1) | |
4725 | fprintf (dump, " "); | |
4726 | } | |
4727 | fprintf (dump, "]"); | |
4728 | } | |
4729 | } | |
4730 | ||
4731 | /* MAX_VISUAL_LINES is the maximum number of lines in visualization table | |
4732 | of a basic block. If more lines are needed, table is splitted to two. | |
4733 | n_visual_lines is the number of lines printed so far for a block. | |
4734 | visual_tbl contains the block visualization info. | |
4735 | vis_no_unit holds insns in a cycle that are not mapped to any unit. */ | |
4736 | #define MAX_VISUAL_LINES 100 | |
4737 | #define INSN_LEN 30 | |
4738 | int n_visual_lines; | |
4739 | char *visual_tbl; | |
4740 | int n_vis_no_unit; | |
4741 | rtx vis_no_unit[10]; | |
4742 | ||
63de6c74 | 4743 | /* Finds units that are in use in this fuction. Required only |
8c660648 JL |
4744 | for visualization. */ |
4745 | ||
4746 | static void | |
4747 | init_target_units () | |
4748 | { | |
4749 | rtx insn; | |
4750 | int unit; | |
4751 | ||
4752 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
4753 | { | |
4754 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
4755 | continue; | |
4756 | ||
4757 | unit = insn_unit (insn); | |
4758 | ||
4759 | if (unit < 0) | |
4760 | target_units |= ~unit; | |
4761 | else | |
4762 | target_units |= (1 << unit); | |
4763 | } | |
4764 | } | |
4765 | ||
63de6c74 | 4766 | /* Return the length of the visualization table. */ |
8c660648 JL |
4767 | |
4768 | static int | |
4769 | get_visual_tbl_length () | |
4770 | { | |
4771 | int unit, i; | |
4772 | int n, n1; | |
4773 | char *s; | |
4774 | ||
63de6c74 | 4775 | /* Compute length of one field in line. */ |
8f04d345 | 4776 | s = (char *) alloca (INSN_LEN + 6); |
8c660648 JL |
4777 | sprintf (s, " %33s", "uname"); |
4778 | n1 = strlen (s); | |
4779 | ||
63de6c74 | 4780 | /* Compute length of one line. */ |
8c660648 JL |
4781 | n = strlen (";; "); |
4782 | n += n1; | |
4783 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
4784 | if (function_units[unit].bitmask & target_units) | |
4785 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
4786 | n += n1; | |
4787 | n += n1; | |
4788 | n += strlen ("\n") + 2; | |
4789 | ||
63de6c74 | 4790 | /* Compute length of visualization string. */ |
8c660648 JL |
4791 | return (MAX_VISUAL_LINES * n); |
4792 | } | |
4793 | ||
63de6c74 | 4794 | /* Init block visualization debugging info. */ |
8c660648 JL |
4795 | |
4796 | static void | |
4797 | init_block_visualization () | |
4798 | { | |
4799 | strcpy (visual_tbl, ""); | |
4800 | n_visual_lines = 0; | |
4801 | n_vis_no_unit = 0; | |
4802 | } | |
4803 | ||
4804 | #define BUF_LEN 256 | |
4805 | ||
459b3825 MM |
4806 | static char * |
4807 | safe_concat (buf, cur, str) | |
4808 | char *buf; | |
4809 | char *cur; | |
5f06c983 | 4810 | const char *str; |
459b3825 | 4811 | { |
63de6c74 | 4812 | char *end = buf + BUF_LEN - 2; /* Leave room for null. */ |
459b3825 MM |
4813 | int c; |
4814 | ||
4815 | if (cur > end) | |
4816 | { | |
4817 | *end = '\0'; | |
4818 | return end; | |
4819 | } | |
4820 | ||
4821 | while (cur < end && (c = *str++) != '\0') | |
4822 | *cur++ = c; | |
4823 | ||
4824 | *cur = '\0'; | |
4825 | return cur; | |
4826 | } | |
4827 | ||
63de6c74 MH |
4828 | /* This recognizes rtx, I classified as expressions. These are always |
4829 | represent some action on values or results of other expression, that | |
4830 | may be stored in objects representing values. */ | |
8c660648 JL |
4831 | |
4832 | static void | |
4833 | print_exp (buf, x, verbose) | |
4834 | char *buf; | |
4835 | rtx x; | |
4836 | int verbose; | |
4837 | { | |
459b3825 | 4838 | char tmp[BUF_LEN]; |
5f06c983 | 4839 | const char *st[4]; |
459b3825 | 4840 | char *cur = buf; |
5f06c983 KG |
4841 | const char *fun = (char *)0; |
4842 | const char *sep; | |
459b3825 MM |
4843 | rtx op[4]; |
4844 | int i; | |
4845 | ||
4846 | for (i = 0; i < 4; i++) | |
4847 | { | |
4848 | st[i] = (char *)0; | |
4849 | op[i] = NULL_RTX; | |
4850 | } | |
8c660648 JL |
4851 | |
4852 | switch (GET_CODE (x)) | |
4853 | { | |
4854 | case PLUS: | |
459b3825 | 4855 | op[0] = XEXP (x, 0); |
f4b94256 RH |
4856 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
4857 | && INTVAL (XEXP (x, 1)) < 0) | |
4858 | { | |
4859 | st[1] = "-"; | |
4860 | op[1] = GEN_INT (-INTVAL (XEXP (x, 1))); | |
4861 | } | |
4862 | else | |
4863 | { | |
4864 | st[1] = "+"; | |
4865 | op[1] = XEXP (x, 1); | |
4866 | } | |
8c660648 JL |
4867 | break; |
4868 | case LO_SUM: | |
459b3825 MM |
4869 | op[0] = XEXP (x, 0); |
4870 | st[1] = "+low("; | |
4871 | op[1] = XEXP (x, 1); | |
4872 | st[2] = ")"; | |
8c660648 JL |
4873 | break; |
4874 | case MINUS: | |
459b3825 MM |
4875 | op[0] = XEXP (x, 0); |
4876 | st[1] = "-"; | |
4877 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4878 | break; |
4879 | case COMPARE: | |
459b3825 MM |
4880 | fun = "cmp"; |
4881 | op[0] = XEXP (x, 0); | |
4882 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4883 | break; |
4884 | case NEG: | |
459b3825 MM |
4885 | st[0] = "-"; |
4886 | op[0] = XEXP (x, 0); | |
8c660648 JL |
4887 | break; |
4888 | case MULT: | |
459b3825 MM |
4889 | op[0] = XEXP (x, 0); |
4890 | st[1] = "*"; | |
4891 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4892 | break; |
4893 | case DIV: | |
459b3825 MM |
4894 | op[0] = XEXP (x, 0); |
4895 | st[1] = "/"; | |
4896 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4897 | break; |
4898 | case UDIV: | |
459b3825 MM |
4899 | fun = "udiv"; |
4900 | op[0] = XEXP (x, 0); | |
4901 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4902 | break; |
4903 | case MOD: | |
459b3825 MM |
4904 | op[0] = XEXP (x, 0); |
4905 | st[1] = "%"; | |
4906 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4907 | break; |
4908 | case UMOD: | |
459b3825 MM |
4909 | fun = "umod"; |
4910 | op[0] = XEXP (x, 0); | |
4911 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4912 | break; |
4913 | case SMIN: | |
459b3825 MM |
4914 | fun = "smin"; |
4915 | op[0] = XEXP (x, 0); | |
4916 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4917 | break; |
4918 | case SMAX: | |
459b3825 MM |
4919 | fun = "smax"; |
4920 | op[0] = XEXP (x, 0); | |
4921 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4922 | break; |
4923 | case UMIN: | |
459b3825 MM |
4924 | fun = "umin"; |
4925 | op[0] = XEXP (x, 0); | |
4926 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4927 | break; |
4928 | case UMAX: | |
459b3825 MM |
4929 | fun = "umax"; |
4930 | op[0] = XEXP (x, 0); | |
4931 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4932 | break; |
4933 | case NOT: | |
459b3825 MM |
4934 | st[0] = "!"; |
4935 | op[0] = XEXP (x, 0); | |
8c660648 JL |
4936 | break; |
4937 | case AND: | |
459b3825 MM |
4938 | op[0] = XEXP (x, 0); |
4939 | st[1] = "&"; | |
4940 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4941 | break; |
4942 | case IOR: | |
459b3825 MM |
4943 | op[0] = XEXP (x, 0); |
4944 | st[1] = "|"; | |
4945 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4946 | break; |
4947 | case XOR: | |
459b3825 MM |
4948 | op[0] = XEXP (x, 0); |
4949 | st[1] = "^"; | |
4950 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4951 | break; |
4952 | case ASHIFT: | |
459b3825 MM |
4953 | op[0] = XEXP (x, 0); |
4954 | st[1] = "<<"; | |
4955 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4956 | break; |
4957 | case LSHIFTRT: | |
459b3825 MM |
4958 | op[0] = XEXP (x, 0); |
4959 | st[1] = " 0>>"; | |
4960 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4961 | break; |
4962 | case ASHIFTRT: | |
459b3825 MM |
4963 | op[0] = XEXP (x, 0); |
4964 | st[1] = ">>"; | |
4965 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4966 | break; |
4967 | case ROTATE: | |
459b3825 MM |
4968 | op[0] = XEXP (x, 0); |
4969 | st[1] = "<-<"; | |
4970 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4971 | break; |
4972 | case ROTATERT: | |
459b3825 MM |
4973 | op[0] = XEXP (x, 0); |
4974 | st[1] = ">->"; | |
4975 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4976 | break; |
4977 | case ABS: | |
459b3825 MM |
4978 | fun = "abs"; |
4979 | op[0] = XEXP (x, 0); | |
8c660648 JL |
4980 | break; |
4981 | case SQRT: | |
459b3825 MM |
4982 | fun = "sqrt"; |
4983 | op[0] = XEXP (x, 0); | |
8c660648 JL |
4984 | break; |
4985 | case FFS: | |
459b3825 MM |
4986 | fun = "ffs"; |
4987 | op[0] = XEXP (x, 0); | |
8c660648 JL |
4988 | break; |
4989 | case EQ: | |
459b3825 MM |
4990 | op[0] = XEXP (x, 0); |
4991 | st[1] = "=="; | |
4992 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4993 | break; |
4994 | case NE: | |
459b3825 MM |
4995 | op[0] = XEXP (x, 0); |
4996 | st[1] = "!="; | |
4997 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4998 | break; |
4999 | case GT: | |
459b3825 MM |
5000 | op[0] = XEXP (x, 0); |
5001 | st[1] = ">"; | |
5002 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5003 | break; |
5004 | case GTU: | |
459b3825 MM |
5005 | fun = "gtu"; |
5006 | op[0] = XEXP (x, 0); | |
5007 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5008 | break; |
5009 | case LT: | |
459b3825 MM |
5010 | op[0] = XEXP (x, 0); |
5011 | st[1] = "<"; | |
5012 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5013 | break; |
5014 | case LTU: | |
459b3825 MM |
5015 | fun = "ltu"; |
5016 | op[0] = XEXP (x, 0); | |
5017 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5018 | break; |
5019 | case GE: | |
459b3825 MM |
5020 | op[0] = XEXP (x, 0); |
5021 | st[1] = ">="; | |
5022 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5023 | break; |
5024 | case GEU: | |
459b3825 MM |
5025 | fun = "geu"; |
5026 | op[0] = XEXP (x, 0); | |
5027 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5028 | break; |
5029 | case LE: | |
459b3825 MM |
5030 | op[0] = XEXP (x, 0); |
5031 | st[1] = "<="; | |
5032 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5033 | break; |
5034 | case LEU: | |
459b3825 MM |
5035 | fun = "leu"; |
5036 | op[0] = XEXP (x, 0); | |
5037 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5038 | break; |
5039 | case SIGN_EXTRACT: | |
459b3825 MM |
5040 | fun = (verbose) ? "sign_extract" : "sxt"; |
5041 | op[0] = XEXP (x, 0); | |
5042 | op[1] = XEXP (x, 1); | |
5043 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5044 | break; |
5045 | case ZERO_EXTRACT: | |
459b3825 MM |
5046 | fun = (verbose) ? "zero_extract" : "zxt"; |
5047 | op[0] = XEXP (x, 0); | |
5048 | op[1] = XEXP (x, 1); | |
5049 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5050 | break; |
5051 | case SIGN_EXTEND: | |
459b3825 MM |
5052 | fun = (verbose) ? "sign_extend" : "sxn"; |
5053 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5054 | break; |
5055 | case ZERO_EXTEND: | |
459b3825 MM |
5056 | fun = (verbose) ? "zero_extend" : "zxn"; |
5057 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5058 | break; |
5059 | case FLOAT_EXTEND: | |
459b3825 MM |
5060 | fun = (verbose) ? "float_extend" : "fxn"; |
5061 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5062 | break; |
5063 | case TRUNCATE: | |
459b3825 MM |
5064 | fun = (verbose) ? "trunc" : "trn"; |
5065 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5066 | break; |
5067 | case FLOAT_TRUNCATE: | |
459b3825 MM |
5068 | fun = (verbose) ? "float_trunc" : "ftr"; |
5069 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5070 | break; |
5071 | case FLOAT: | |
459b3825 MM |
5072 | fun = (verbose) ? "float" : "flt"; |
5073 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5074 | break; |
5075 | case UNSIGNED_FLOAT: | |
459b3825 MM |
5076 | fun = (verbose) ? "uns_float" : "ufl"; |
5077 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5078 | break; |
5079 | case FIX: | |
459b3825 MM |
5080 | fun = "fix"; |
5081 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5082 | break; |
5083 | case UNSIGNED_FIX: | |
459b3825 MM |
5084 | fun = (verbose) ? "uns_fix" : "ufx"; |
5085 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5086 | break; |
5087 | case PRE_DEC: | |
459b3825 MM |
5088 | st[0] = "--"; |
5089 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5090 | break; |
5091 | case PRE_INC: | |
459b3825 MM |
5092 | st[0] = "++"; |
5093 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5094 | break; |
5095 | case POST_DEC: | |
459b3825 MM |
5096 | op[0] = XEXP (x, 0); |
5097 | st[1] = "--"; | |
8c660648 JL |
5098 | break; |
5099 | case POST_INC: | |
459b3825 MM |
5100 | op[0] = XEXP (x, 0); |
5101 | st[1] = "++"; | |
8c660648 JL |
5102 | break; |
5103 | case CALL: | |
459b3825 MM |
5104 | st[0] = "call "; |
5105 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5106 | if (verbose) |
5107 | { | |
459b3825 MM |
5108 | st[1] = " argc:"; |
5109 | op[1] = XEXP (x, 1); | |
8c660648 | 5110 | } |
8c660648 JL |
5111 | break; |
5112 | case IF_THEN_ELSE: | |
459b3825 MM |
5113 | st[0] = "{("; |
5114 | op[0] = XEXP (x, 0); | |
5115 | st[1] = ")?"; | |
5116 | op[1] = XEXP (x, 1); | |
5117 | st[2] = ":"; | |
5118 | op[2] = XEXP (x, 2); | |
5119 | st[3] = "}"; | |
8c660648 JL |
5120 | break; |
5121 | case TRAP_IF: | |
459b3825 MM |
5122 | fun = "trap_if"; |
5123 | op[0] = TRAP_CONDITION (x); | |
8c660648 JL |
5124 | break; |
5125 | case UNSPEC: | |
8c660648 JL |
5126 | case UNSPEC_VOLATILE: |
5127 | { | |
459b3825 MM |
5128 | cur = safe_concat (buf, cur, "unspec"); |
5129 | if (GET_CODE (x) == UNSPEC_VOLATILE) | |
5130 | cur = safe_concat (buf, cur, "/v"); | |
5131 | cur = safe_concat (buf, cur, "["); | |
5132 | sep = ""; | |
8c660648 JL |
5133 | for (i = 0; i < XVECLEN (x, 0); i++) |
5134 | { | |
459b3825 MM |
5135 | print_pattern (tmp, XVECEXP (x, 0, i), verbose); |
5136 | cur = safe_concat (buf, cur, sep); | |
5137 | cur = safe_concat (buf, cur, tmp); | |
5138 | sep = ","; | |
8c660648 | 5139 | } |
459b3825 MM |
5140 | cur = safe_concat (buf, cur, "] "); |
5141 | sprintf (tmp, "%d", XINT (x, 1)); | |
5142 | cur = safe_concat (buf, cur, tmp); | |
8c660648 JL |
5143 | } |
5144 | break; | |
5145 | default: | |
63de6c74 | 5146 | /* If (verbose) debug_rtx (x); */ |
53c0919d | 5147 | st[0] = GET_RTX_NAME (GET_CODE (x)); |
459b3825 MM |
5148 | break; |
5149 | } | |
5150 | ||
63de6c74 | 5151 | /* Print this as a function? */ |
459b3825 MM |
5152 | if (fun) |
5153 | { | |
5154 | cur = safe_concat (buf, cur, fun); | |
5155 | cur = safe_concat (buf, cur, "("); | |
5156 | } | |
5157 | ||
5158 | for (i = 0; i < 4; i++) | |
5159 | { | |
5160 | if (st[i]) | |
5161 | cur = safe_concat (buf, cur, st[i]); | |
5162 | ||
5163 | if (op[i]) | |
5164 | { | |
5165 | if (fun && i != 0) | |
5166 | cur = safe_concat (buf, cur, ","); | |
5167 | ||
5168 | print_value (tmp, op[i], verbose); | |
5169 | cur = safe_concat (buf, cur, tmp); | |
5170 | } | |
8c660648 | 5171 | } |
459b3825 MM |
5172 | |
5173 | if (fun) | |
5174 | cur = safe_concat (buf, cur, ")"); | |
5175 | } /* print_exp */ | |
8c660648 | 5176 | |
63de6c74 MH |
5177 | /* Prints rtxes, I customly classified as values. They're constants, |
5178 | registers, labels, symbols and memory accesses. */ | |
8c660648 JL |
5179 | |
5180 | static void | |
5181 | print_value (buf, x, verbose) | |
5182 | char *buf; | |
5183 | rtx x; | |
5184 | int verbose; | |
5185 | { | |
5186 | char t[BUF_LEN]; | |
459b3825 | 5187 | char *cur = buf; |
8c660648 JL |
5188 | |
5189 | switch (GET_CODE (x)) | |
5190 | { | |
5191 | case CONST_INT: | |
f4b94256 | 5192 | sprintf (t, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); |
459b3825 | 5193 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
5194 | break; |
5195 | case CONST_DOUBLE: | |
459b3825 MM |
5196 | sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); |
5197 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
5198 | break; |
5199 | case CONST_STRING: | |
459b3825 MM |
5200 | cur = safe_concat (buf, cur, "\""); |
5201 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
5202 | cur = safe_concat (buf, cur, "\""); | |
8c660648 JL |
5203 | break; |
5204 | case SYMBOL_REF: | |
459b3825 MM |
5205 | cur = safe_concat (buf, cur, "`"); |
5206 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
5207 | cur = safe_concat (buf, cur, "'"); | |
8c660648 JL |
5208 | break; |
5209 | case LABEL_REF: | |
459b3825 MM |
5210 | sprintf (t, "L%d", INSN_UID (XEXP (x, 0))); |
5211 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
5212 | break; |
5213 | case CONST: | |
459b3825 MM |
5214 | print_value (t, XEXP (x, 0), verbose); |
5215 | cur = safe_concat (buf, cur, "const("); | |
5216 | cur = safe_concat (buf, cur, t); | |
5217 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
5218 | break; |
5219 | case HIGH: | |
459b3825 MM |
5220 | print_value (t, XEXP (x, 0), verbose); |
5221 | cur = safe_concat (buf, cur, "high("); | |
5222 | cur = safe_concat (buf, cur, t); | |
5223 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
5224 | break; |
5225 | case REG: | |
459b3825 MM |
5226 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) |
5227 | { | |
5228 | int c = reg_names[ REGNO (x) ][0]; | |
5229 | if (c >= '0' && c <= '9') | |
5230 | cur = safe_concat (buf, cur, "%"); | |
5231 | ||
5232 | cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]); | |
5233 | } | |
8c660648 | 5234 | else |
459b3825 MM |
5235 | { |
5236 | sprintf (t, "r%d", REGNO (x)); | |
5237 | cur = safe_concat (buf, cur, t); | |
5238 | } | |
8c660648 JL |
5239 | break; |
5240 | case SUBREG: | |
459b3825 MM |
5241 | print_value (t, SUBREG_REG (x), verbose); |
5242 | cur = safe_concat (buf, cur, t); | |
6b879bcc | 5243 | sprintf (t, "#%d", SUBREG_WORD (x)); |
459b3825 | 5244 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
5245 | break; |
5246 | case SCRATCH: | |
459b3825 | 5247 | cur = safe_concat (buf, cur, "scratch"); |
8c660648 JL |
5248 | break; |
5249 | case CC0: | |
459b3825 | 5250 | cur = safe_concat (buf, cur, "cc0"); |
8c660648 JL |
5251 | break; |
5252 | case PC: | |
459b3825 | 5253 | cur = safe_concat (buf, cur, "pc"); |
8c660648 JL |
5254 | break; |
5255 | case MEM: | |
5256 | print_value (t, XEXP (x, 0), verbose); | |
459b3825 MM |
5257 | cur = safe_concat (buf, cur, "["); |
5258 | cur = safe_concat (buf, cur, t); | |
5259 | cur = safe_concat (buf, cur, "]"); | |
8c660648 JL |
5260 | break; |
5261 | default: | |
459b3825 MM |
5262 | print_exp (t, x, verbose); |
5263 | cur = safe_concat (buf, cur, t); | |
5264 | break; | |
8c660648 JL |
5265 | } |
5266 | } /* print_value */ | |
5267 | ||
63de6c74 | 5268 | /* The next step in insn detalization, its pattern recognition. */ |
8c660648 JL |
5269 | |
5270 | static void | |
5271 | print_pattern (buf, x, verbose) | |
5272 | char *buf; | |
5273 | rtx x; | |
5274 | int verbose; | |
5275 | { | |
5276 | char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN]; | |
5277 | ||
5278 | switch (GET_CODE (x)) | |
5279 | { | |
5280 | case SET: | |
5281 | print_value (t1, SET_DEST (x), verbose); | |
5282 | print_value (t2, SET_SRC (x), verbose); | |
5283 | sprintf (buf, "%s=%s", t1, t2); | |
5284 | break; | |
5285 | case RETURN: | |
5286 | sprintf (buf, "return"); | |
5287 | break; | |
5288 | case CALL: | |
5289 | print_exp (buf, x, verbose); | |
5290 | break; | |
5291 | case CLOBBER: | |
5292 | print_value (t1, XEXP (x, 0), verbose); | |
5293 | sprintf (buf, "clobber %s", t1); | |
5294 | break; | |
5295 | case USE: | |
5296 | print_value (t1, XEXP (x, 0), verbose); | |
5297 | sprintf (buf, "use %s", t1); | |
5298 | break; | |
5299 | case PARALLEL: | |
5300 | { | |
5301 | int i; | |
5302 | ||
5303 | sprintf (t1, "{"); | |
5304 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5305 | { | |
5306 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5307 | sprintf (t3, "%s%s;", t1, t2); | |
5308 | strcpy (t1, t3); | |
5309 | } | |
5310 | sprintf (buf, "%s}", t1); | |
5311 | } | |
5312 | break; | |
5313 | case SEQUENCE: | |
5314 | { | |
5315 | int i; | |
5316 | ||
5317 | sprintf (t1, "%%{"); | |
5318 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5319 | { | |
5320 | print_insn (t2, XVECEXP (x, 0, i), verbose); | |
5321 | sprintf (t3, "%s%s;", t1, t2); | |
5322 | strcpy (t1, t3); | |
5323 | } | |
5324 | sprintf (buf, "%s%%}", t1); | |
5325 | } | |
5326 | break; | |
5327 | case ASM_INPUT: | |
c4fa3460 | 5328 | sprintf (buf, "asm {%s}", XSTR (x, 0)); |
8c660648 JL |
5329 | break; |
5330 | case ADDR_VEC: | |
5331 | break; | |
5332 | case ADDR_DIFF_VEC: | |
5333 | print_value (buf, XEXP (x, 0), verbose); | |
5334 | break; | |
5335 | case TRAP_IF: | |
5336 | print_value (t1, TRAP_CONDITION (x), verbose); | |
5337 | sprintf (buf, "trap_if %s", t1); | |
5338 | break; | |
5339 | case UNSPEC: | |
5340 | { | |
5341 | int i; | |
5342 | ||
5343 | sprintf (t1, "unspec{"); | |
5344 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5345 | { | |
5346 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5347 | sprintf (t3, "%s%s;", t1, t2); | |
5348 | strcpy (t1, t3); | |
5349 | } | |
5350 | sprintf (buf, "%s}", t1); | |
5351 | } | |
5352 | break; | |
5353 | case UNSPEC_VOLATILE: | |
5354 | { | |
5355 | int i; | |
5356 | ||
5357 | sprintf (t1, "unspec/v{"); | |
5358 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5359 | { | |
5360 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5361 | sprintf (t3, "%s%s;", t1, t2); | |
5362 | strcpy (t1, t3); | |
5363 | } | |
5364 | sprintf (buf, "%s}", t1); | |
5365 | } | |
5366 | break; | |
5367 | default: | |
5368 | print_value (buf, x, verbose); | |
5369 | } | |
5370 | } /* print_pattern */ | |
5371 | ||
5372 | /* This is the main function in rtl visualization mechanism. It | |
5373 | accepts an rtx and tries to recognize it as an insn, then prints it | |
63de6c74 MH |
5374 | properly in human readable form, resembling assembler mnemonics. |
5375 | For every insn it prints its UID and BB the insn belongs too. | |
5376 | (Probably the last "option" should be extended somehow, since it | |
5377 | depends now on sched.c inner variables ...) */ | |
8c660648 JL |
5378 | |
5379 | static void | |
5380 | print_insn (buf, x, verbose) | |
5381 | char *buf; | |
5382 | rtx x; | |
5383 | int verbose; | |
5384 | { | |
5385 | char t[BUF_LEN]; | |
5386 | rtx insn = x; | |
5387 | ||
5388 | switch (GET_CODE (x)) | |
5389 | { | |
5390 | case INSN: | |
5391 | print_pattern (t, PATTERN (x), verbose); | |
5392 | if (verbose) | |
5393 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x), | |
5394 | INSN_UID (x), t); | |
5395 | else | |
5396 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
5397 | break; | |
5398 | case JUMP_INSN: | |
5399 | print_pattern (t, PATTERN (x), verbose); | |
5400 | if (verbose) | |
5401 | sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x), | |
5402 | INSN_UID (x), t); | |
5403 | else | |
5404 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
5405 | break; | |
5406 | case CALL_INSN: | |
5407 | x = PATTERN (insn); | |
5408 | if (GET_CODE (x) == PARALLEL) | |
5409 | { | |
5410 | x = XVECEXP (x, 0, 0); | |
5411 | print_pattern (t, x, verbose); | |
5412 | } | |
5413 | else | |
5414 | strcpy (t, "call <...>"); | |
5415 | if (verbose) | |
5416 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn), | |
5417 | INSN_UID (insn), t); | |
5418 | else | |
5419 | sprintf (buf, "%-4d %s", INSN_UID (insn), t); | |
5420 | break; | |
5421 | case CODE_LABEL: | |
5422 | sprintf (buf, "L%d:", INSN_UID (x)); | |
5423 | break; | |
5424 | case BARRIER: | |
5425 | sprintf (buf, "i% 4d: barrier", INSN_UID (x)); | |
5426 | break; | |
5427 | case NOTE: | |
5428 | if (NOTE_LINE_NUMBER (x) > 0) | |
5429 | sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x), | |
5430 | NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x)); | |
5431 | else | |
5432 | sprintf (buf, "%4d %s", INSN_UID (x), | |
5433 | GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x))); | |
5434 | break; | |
5435 | default: | |
5436 | if (verbose) | |
5437 | { | |
5438 | sprintf (buf, "Not an INSN at all\n"); | |
5439 | debug_rtx (x); | |
5440 | } | |
5441 | else | |
5442 | sprintf (buf, "i%-4d <What?>", INSN_UID (x)); | |
5443 | } | |
5444 | } /* print_insn */ | |
5445 | ||
63de6c74 | 5446 | /* Print visualization debugging info. */ |
8c660648 JL |
5447 | |
5448 | static void | |
5449 | print_block_visualization (b, s) | |
5450 | int b; | |
5f06c983 | 5451 | const char *s; |
8c660648 JL |
5452 | { |
5453 | int unit, i; | |
8c660648 | 5454 | |
63de6c74 | 5455 | /* Print header. */ |
8c660648 JL |
5456 | fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s); |
5457 | ||
63de6c74 | 5458 | /* Print names of units. */ |
2f308fec | 5459 | fprintf (dump, ";; %-8s", "clock"); |
8c660648 JL |
5460 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) |
5461 | if (function_units[unit].bitmask & target_units) | |
5462 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
2f308fec RH |
5463 | fprintf (dump, " %-33s", function_units[unit].name); |
5464 | fprintf (dump, " %-8s\n", "no-unit"); | |
5465 | ||
5466 | fprintf (dump, ";; %-8s", "====="); | |
5467 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5468 | if (function_units[unit].bitmask & target_units) | |
5469 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5470 | fprintf (dump, " %-33s", "=============================="); | |
5471 | fprintf (dump, " %-8s\n", "======="); | |
8c660648 | 5472 | |
63de6c74 | 5473 | /* Print insns in each cycle. */ |
8c660648 JL |
5474 | fprintf (dump, "%s\n", visual_tbl); |
5475 | } | |
5476 | ||
63de6c74 | 5477 | /* Print insns in the 'no_unit' column of visualization. */ |
8c660648 JL |
5478 | |
5479 | static void | |
5480 | visualize_no_unit (insn) | |
5481 | rtx insn; | |
5482 | { | |
5483 | vis_no_unit[n_vis_no_unit] = insn; | |
5484 | n_vis_no_unit++; | |
5485 | } | |
5486 | ||
5487 | /* Print insns scheduled in clock, for visualization. */ | |
5488 | ||
5489 | static void | |
5490 | visualize_scheduled_insns (b, clock) | |
5491 | int b, clock; | |
5492 | { | |
5493 | int i, unit; | |
5494 | ||
63de6c74 | 5495 | /* If no more room, split table into two. */ |
8c660648 JL |
5496 | if (n_visual_lines >= MAX_VISUAL_LINES) |
5497 | { | |
5498 | print_block_visualization (b, "(incomplete)"); | |
5499 | init_block_visualization (); | |
5500 | } | |
5501 | ||
5502 | n_visual_lines++; | |
5503 | ||
5504 | sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock); | |
5505 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5506 | if (function_units[unit].bitmask & target_units) | |
5507 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5508 | { | |
5509 | int instance = unit + i * FUNCTION_UNITS_SIZE; | |
5510 | rtx insn = unit_last_insn[instance]; | |
5511 | ||
63de6c74 | 5512 | /* Print insns that still keep the unit busy. */ |
8c660648 JL |
5513 | if (insn && |
5514 | actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
5515 | { | |
5516 | char str[BUF_LEN]; | |
5517 | print_insn (str, insn, 0); | |
5518 | str[INSN_LEN] = '\0'; | |
5519 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str); | |
5520 | } | |
5521 | else | |
5522 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------"); | |
5523 | } | |
5524 | ||
63de6c74 | 5525 | /* Print insns that are not assigned to any unit. */ |
8c660648 JL |
5526 | for (i = 0; i < n_vis_no_unit; i++) |
5527 | sprintf (visual_tbl + strlen (visual_tbl), " %-8d", | |
5528 | INSN_UID (vis_no_unit[i])); | |
5529 | n_vis_no_unit = 0; | |
5530 | ||
5531 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
5532 | } | |
5533 | ||
63de6c74 | 5534 | /* Print stalled cycles. */ |
8c660648 JL |
5535 | |
5536 | static void | |
5537 | visualize_stall_cycles (b, stalls) | |
5538 | int b, stalls; | |
5539 | { | |
5540 | int i; | |
5541 | ||
63de6c74 | 5542 | /* If no more room, split table into two. */ |
8c660648 JL |
5543 | if (n_visual_lines >= MAX_VISUAL_LINES) |
5544 | { | |
5545 | print_block_visualization (b, "(incomplete)"); | |
5546 | init_block_visualization (); | |
5547 | } | |
5548 | ||
5549 | n_visual_lines++; | |
5550 | ||
5551 | sprintf (visual_tbl + strlen (visual_tbl), ";; "); | |
5552 | for (i = 0; i < stalls; i++) | |
5553 | sprintf (visual_tbl + strlen (visual_tbl), "."); | |
5554 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
5555 | } | |
5556 | ||
63de6c74 | 5557 | /* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */ |
8c660648 JL |
5558 | |
5559 | static rtx | |
5560 | move_insn1 (insn, last) | |
5561 | rtx insn, last; | |
5562 | { | |
5563 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
5564 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
5565 | ||
5566 | NEXT_INSN (insn) = NEXT_INSN (last); | |
5567 | PREV_INSN (NEXT_INSN (last)) = insn; | |
5568 | ||
5569 | NEXT_INSN (last) = insn; | |
5570 | PREV_INSN (insn) = last; | |
5571 | ||
5572 | return insn; | |
5573 | } | |
5574 | ||
c46a37c4 | 5575 | /* Search INSN for REG_SAVE_NOTE note pairs for NOTE_INSN_SETJMP, |
8c660648 | 5576 | NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into |
c46a37c4 RH |
5577 | NOTEs. The REG_SAVE_NOTE note following first one is contains the |
5578 | saved value for NOTE_BLOCK_NUMBER which is useful for | |
8c660648 JL |
5579 | NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction |
5580 | output by the instruction scheduler. Return the new value of LAST. */ | |
5581 | ||
5582 | static rtx | |
5583 | reemit_notes (insn, last) | |
5584 | rtx insn; | |
5585 | rtx last; | |
5586 | { | |
5587 | rtx note, retval; | |
5588 | ||
5589 | retval = last; | |
5590 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
5591 | { | |
c46a37c4 | 5592 | if (REG_NOTE_KIND (note) == REG_SAVE_NOTE) |
8c660648 | 5593 | { |
6dfdecdb RH |
5594 | int note_type = INTVAL (XEXP (note, 0)); |
5595 | if (note_type == NOTE_INSN_SETJMP) | |
8c660648 | 5596 | { |
6dfdecdb | 5597 | retval = emit_note_after (NOTE_INSN_SETJMP, insn); |
8c660648 | 5598 | CONST_CALL_P (retval) = CONST_CALL_P (note); |
7bd41ea6 MM |
5599 | remove_note (insn, note); |
5600 | note = XEXP (note, 1); | |
8c660648 | 5601 | } |
6dfdecdb RH |
5602 | else if (note_type == NOTE_INSN_RANGE_START |
5603 | || note_type == NOTE_INSN_RANGE_END) | |
5604 | { | |
5605 | last = emit_note_before (note_type, last); | |
5606 | remove_note (insn, note); | |
5607 | note = XEXP (note, 1); | |
5608 | NOTE_RANGE_INFO (last) = XEXP (note, 0); | |
5609 | } | |
8c660648 JL |
5610 | else |
5611 | { | |
19699da4 | 5612 | last = emit_note_before (note_type, last); |
7bd41ea6 MM |
5613 | remove_note (insn, note); |
5614 | note = XEXP (note, 1); | |
1a4450c7 MM |
5615 | if (note_type == NOTE_INSN_EH_REGION_BEG |
5616 | || note_type == NOTE_INSN_EH_REGION_END) | |
7bd41ea6 | 5617 | NOTE_EH_HANDLER (last) = INTVAL (XEXP (note, 0)); |
8c660648 JL |
5618 | } |
5619 | remove_note (insn, note); | |
5620 | } | |
5621 | } | |
5622 | return retval; | |
5623 | } | |
5624 | ||
5625 | /* Move INSN, and all insns which should be issued before it, | |
c9e03727 JL |
5626 | due to SCHED_GROUP_P flag. Reemit notes if needed. |
5627 | ||
5628 | Return the last insn emitted by the scheduler, which is the | |
5629 | return value from the first call to reemit_notes. */ | |
8c660648 JL |
5630 | |
5631 | static rtx | |
5632 | move_insn (insn, last) | |
5633 | rtx insn, last; | |
5634 | { | |
c9e03727 | 5635 | rtx retval = NULL; |
8c660648 | 5636 | |
c9e03727 JL |
5637 | /* If INSN has SCHED_GROUP_P set, then issue it and any other |
5638 | insns with SCHED_GROUP_P set first. */ | |
8c660648 JL |
5639 | while (SCHED_GROUP_P (insn)) |
5640 | { | |
5641 | rtx prev = PREV_INSN (insn); | |
c9e03727 JL |
5642 | |
5643 | /* Move a SCHED_GROUP_P insn. */ | |
8c660648 | 5644 | move_insn1 (insn, last); |
c9e03727 JL |
5645 | /* If this is the first call to reemit_notes, then record |
5646 | its return value. */ | |
5647 | if (retval == NULL_RTX) | |
5648 | retval = reemit_notes (insn, insn); | |
5649 | else | |
5650 | reemit_notes (insn, insn); | |
8c660648 JL |
5651 | insn = prev; |
5652 | } | |
5653 | ||
c9e03727 | 5654 | /* Now move the first non SCHED_GROUP_P insn. */ |
8c660648 | 5655 | move_insn1 (insn, last); |
c9e03727 JL |
5656 | |
5657 | /* If this is the first call to reemit_notes, then record | |
5658 | its return value. */ | |
5659 | if (retval == NULL_RTX) | |
5660 | retval = reemit_notes (insn, insn); | |
5661 | else | |
5662 | reemit_notes (insn, insn); | |
5663 | ||
5664 | return retval; | |
8c660648 JL |
5665 | } |
5666 | ||
5667 | /* Return an insn which represents a SCHED_GROUP, which is | |
5668 | the last insn in the group. */ | |
5669 | ||
5670 | static rtx | |
5671 | group_leader (insn) | |
5672 | rtx insn; | |
5673 | { | |
5674 | rtx prev; | |
5675 | ||
5676 | do | |
5677 | { | |
5678 | prev = insn; | |
5679 | insn = next_nonnote_insn (insn); | |
5680 | } | |
5681 | while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL)); | |
5682 | ||
5683 | return prev; | |
5684 | } | |
5685 | ||
5686 | /* Use forward list scheduling to rearrange insns of block BB in region RGN, | |
5687 | possibly bringing insns from subsequent blocks in the same region. | |
5688 | Return number of insns scheduled. */ | |
5689 | ||
5690 | static int | |
5835e573 | 5691 | schedule_block (bb, rgn_n_insns) |
8c660648 | 5692 | int bb; |
8c660648 JL |
5693 | int rgn_n_insns; |
5694 | { | |
5695 | /* Local variables. */ | |
5696 | rtx insn, last; | |
5697 | rtx *ready; | |
8c660648 JL |
5698 | int n_ready = 0; |
5699 | int can_issue_more; | |
5700 | ||
63de6c74 | 5701 | /* Flow block of this bb. */ |
8c660648 JL |
5702 | int b = BB_TO_BLOCK (bb); |
5703 | ||
5704 | /* target_n_insns == number of insns in b before scheduling starts. | |
5705 | sched_target_n_insns == how many of b's insns were scheduled. | |
63de6c74 | 5706 | sched_n_insns == how many insns were scheduled in b. */ |
8c660648 JL |
5707 | int target_n_insns = 0; |
5708 | int sched_target_n_insns = 0; | |
5709 | int sched_n_insns = 0; | |
5710 | ||
5711 | #define NEED_NOTHING 0 | |
5712 | #define NEED_HEAD 1 | |
5713 | #define NEED_TAIL 2 | |
5714 | int new_needs; | |
5715 | ||
63de6c74 | 5716 | /* Head/tail info for this block. */ |
8c660648 JL |
5717 | rtx prev_head; |
5718 | rtx next_tail; | |
5719 | rtx head; | |
5720 | rtx tail; | |
5721 | int bb_src; | |
5722 | ||
484df988 JL |
5723 | /* We used to have code to avoid getting parameters moved from hard |
5724 | argument registers into pseudos. | |
8c660648 | 5725 | |
484df988 JL |
5726 | However, it was removed when it proved to be of marginal benefit |
5727 | and caused problems because schedule_block and compute_forward_dependences | |
5728 | had different notions of what the "head" insn was. */ | |
5729 | get_block_head_tail (bb, &head, &tail); | |
8c660648 | 5730 | |
1447b516 JL |
5731 | /* Interblock scheduling could have moved the original head insn from this |
5732 | block into a proceeding block. This may also cause schedule_block and | |
5733 | compute_forward_dependences to have different notions of what the | |
5734 | "head" insn was. | |
5735 | ||
5736 | If the interblock movement happened to make this block start with | |
5737 | some notes (LOOP, EH or SETJMP) before the first real insn, then | |
5738 | HEAD will have various special notes attached to it which must be | |
5739 | removed so that we don't end up with extra copies of the notes. */ | |
5740 | if (GET_RTX_CLASS (GET_CODE (head)) == 'i') | |
5741 | { | |
5742 | rtx note; | |
5743 | ||
5744 | for (note = REG_NOTES (head); note; note = XEXP (note, 1)) | |
c46a37c4 | 5745 | if (REG_NOTE_KIND (note) == REG_SAVE_NOTE) |
1447b516 JL |
5746 | remove_note (head, note); |
5747 | } | |
5748 | ||
8c660648 JL |
5749 | next_tail = NEXT_INSN (tail); |
5750 | prev_head = PREV_INSN (head); | |
5751 | ||
5752 | /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need | |
5753 | to schedule this block. */ | |
5754 | if (head == tail | |
5755 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
5756 | return (sched_n_insns); | |
5757 | ||
63de6c74 | 5758 | /* Debug info. */ |
8c660648 JL |
5759 | if (sched_verbose) |
5760 | { | |
5761 | fprintf (dump, ";; ======================================================\n"); | |
5762 | fprintf (dump, | |
5763 | ";; -- basic block %d from %d to %d -- %s reload\n", | |
3b413743 | 5764 | b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)), |
8c660648 JL |
5765 | (reload_completed ? "after" : "before")); |
5766 | fprintf (dump, ";; ======================================================\n"); | |
8c660648 JL |
5767 | fprintf (dump, "\n"); |
5768 | ||
5769 | visual_tbl = (char *) alloca (get_visual_tbl_length ()); | |
5770 | init_block_visualization (); | |
5771 | } | |
5772 | ||
63de6c74 | 5773 | /* Remove remaining note insns from the block, save them in |
8c660648 JL |
5774 | note_list. These notes are restored at the end of |
5775 | schedule_block (). */ | |
5776 | note_list = 0; | |
5777 | rm_other_notes (head, tail); | |
5778 | ||
5779 | target_bb = bb; | |
5780 | ||
63de6c74 | 5781 | /* Prepare current target block info. */ |
8c660648 JL |
5782 | if (current_nr_blocks > 1) |
5783 | { | |
63de6c74 MH |
5784 | candidate_table = (candidate *) alloca (current_nr_blocks |
5785 | * sizeof (candidate)); | |
8c660648 JL |
5786 | |
5787 | bblst_last = 0; | |
5788 | /* ??? It is not clear why bblst_size is computed this way. The original | |
5789 | number was clearly too small as it resulted in compiler failures. | |
5790 | Multiplying by the original number by 2 (to account for update_bbs | |
5791 | members) seems to be a reasonable solution. */ | |
5792 | /* ??? Or perhaps there is a bug somewhere else in this file? */ | |
5793 | bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2; | |
5794 | bblst_table = (int *) alloca (bblst_size * sizeof (int)); | |
5795 | ||
5796 | bitlst_table_last = 0; | |
5797 | bitlst_table_size = rgn_nr_edges; | |
5798 | bitlst_table = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
5799 | ||
5800 | compute_trg_info (bb); | |
5801 | } | |
5802 | ||
5803 | clear_units (); | |
5804 | ||
63de6c74 | 5805 | /* Allocate the ready list. */ |
8c660648 JL |
5806 | ready = (rtx *) alloca ((rgn_n_insns + 1) * sizeof (rtx)); |
5807 | ||
5808 | /* Print debugging information. */ | |
5809 | if (sched_verbose >= 5) | |
5810 | debug_dependencies (); | |
5811 | ||
5812 | ||
5813 | /* Initialize ready list with all 'ready' insns in target block. | |
5814 | Count number of insns in the target block being scheduled. */ | |
5815 | n_ready = 0; | |
5816 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5817 | { | |
5818 | rtx next; | |
5819 | ||
5820 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5821 | continue; | |
5822 | next = NEXT_INSN (insn); | |
5823 | ||
5824 | if (INSN_DEP_COUNT (insn) == 0 | |
5825 | && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
5826 | ready[n_ready++] = insn; | |
5827 | if (!(SCHED_GROUP_P (insn))) | |
5828 | target_n_insns++; | |
5829 | } | |
5830 | ||
5831 | /* Add to ready list all 'ready' insns in valid source blocks. | |
5832 | For speculative insns, check-live, exception-free, and | |
5833 | issue-delay. */ | |
5834 | for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++) | |
5835 | if (IS_VALID (bb_src)) | |
5836 | { | |
5837 | rtx src_head; | |
5838 | rtx src_next_tail; | |
5839 | rtx tail, head; | |
5840 | ||
5841 | get_block_head_tail (bb_src, &head, &tail); | |
5842 | src_next_tail = NEXT_INSN (tail); | |
5843 | src_head = head; | |
5844 | ||
5845 | if (head == tail | |
5846 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
5847 | continue; | |
5848 | ||
5849 | for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn)) | |
5850 | { | |
5851 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5852 | continue; | |
5853 | ||
5854 | if (!CANT_MOVE (insn) | |
5855 | && (!IS_SPECULATIVE_INSN (insn) | |
5856 | || (insn_issue_delay (insn) <= 3 | |
5835e573 | 5857 | && check_live (insn, bb_src) |
8c660648 JL |
5858 | && is_exception_free (insn, bb_src, target_bb)))) |
5859 | ||
5860 | { | |
5861 | rtx next; | |
5862 | ||
0d8b2ca1 RH |
5863 | /* Note that we havn't squirrled away the notes for |
5864 | blocks other than the current. So if this is a | |
5865 | speculative insn, NEXT might otherwise be a note. */ | |
5866 | next = next_nonnote_insn (insn); | |
8c660648 JL |
5867 | if (INSN_DEP_COUNT (insn) == 0 |
5868 | && (SCHED_GROUP_P (next) == 0 | |
5869 | || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
5870 | ready[n_ready++] = insn; | |
5871 | } | |
5872 | } | |
5873 | } | |
5874 | ||
e4da5f6d MM |
5875 | #ifdef MD_SCHED_INIT |
5876 | MD_SCHED_INIT (dump, sched_verbose); | |
5877 | #endif | |
5878 | ||
63de6c74 | 5879 | /* No insns scheduled in this block yet. */ |
8c660648 JL |
5880 | last_scheduled_insn = 0; |
5881 | ||
8c660648 JL |
5882 | /* Q_SIZE is the total number of insns in the queue. */ |
5883 | q_ptr = 0; | |
5884 | q_size = 0; | |
4bdc8810 | 5885 | last_clock_var = 0; |
8c660648 JL |
5886 | bzero ((char *) insn_queue, sizeof (insn_queue)); |
5887 | ||
197043f5 RH |
5888 | /* Start just before the beginning of time. */ |
5889 | clock_var = -1; | |
5890 | ||
8c660648 JL |
5891 | /* We start inserting insns after PREV_HEAD. */ |
5892 | last = prev_head; | |
5893 | ||
5894 | /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */ | |
3b413743 | 5895 | new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b) |
8c660648 | 5896 | ? NEED_HEAD : NEED_NOTHING); |
3b413743 | 5897 | if (PREV_INSN (next_tail) == BLOCK_END (b)) |
8c660648 JL |
5898 | new_needs |= NEED_TAIL; |
5899 | ||
63de6c74 | 5900 | /* Loop until all the insns in BB are scheduled. */ |
8c660648 JL |
5901 | while (sched_target_n_insns < target_n_insns) |
5902 | { | |
8c660648 JL |
5903 | clock_var++; |
5904 | ||
5905 | /* Add to the ready list all pending insns that can be issued now. | |
5906 | If there are no ready insns, increment clock until one | |
5907 | is ready and add all pending insns at that point to the ready | |
5908 | list. */ | |
5909 | n_ready = queue_to_ready (ready, n_ready); | |
5910 | ||
5911 | if (n_ready == 0) | |
5912 | abort (); | |
5913 | ||
5914 | if (sched_verbose >= 2) | |
5915 | { | |
5916 | fprintf (dump, ";;\t\tReady list after queue_to_ready: "); | |
5917 | debug_ready_list (ready, n_ready); | |
5918 | } | |
5919 | ||
197043f5 | 5920 | /* Sort the ready list based on priority. */ |
8c660648 | 5921 | SCHED_SORT (ready, n_ready); |
197043f5 RH |
5922 | |
5923 | /* Allow the target to reorder the list, typically for | |
5924 | better instruction bundling. */ | |
e4da5f6d | 5925 | #ifdef MD_SCHED_REORDER |
197043f5 RH |
5926 | MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var, |
5927 | can_issue_more); | |
5928 | #else | |
5929 | can_issue_more = issue_rate; | |
e4da5f6d | 5930 | #endif |
8c660648 JL |
5931 | |
5932 | if (sched_verbose) | |
5933 | { | |
47312d84 | 5934 | fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var); |
8c660648 JL |
5935 | debug_ready_list (ready, n_ready); |
5936 | } | |
5937 | ||
197043f5 RH |
5938 | /* Issue insns from ready list. */ |
5939 | while (n_ready != 0 && can_issue_more) | |
8c660648 | 5940 | { |
197043f5 RH |
5941 | /* Select and remove the insn from the ready list. */ |
5942 | rtx insn = ready[--n_ready]; | |
8c660648 JL |
5943 | int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0); |
5944 | ||
197043f5 | 5945 | if (cost >= 1) |
8c660648 JL |
5946 | { |
5947 | queue_insn (insn, cost); | |
197043f5 | 5948 | continue; |
8c660648 | 5949 | } |
4f64eaca | 5950 | |
197043f5 RH |
5951 | /* An interblock motion? */ |
5952 | if (INSN_BB (insn) != target_bb) | |
5953 | { | |
5954 | rtx temp; | |
c88e8206 | 5955 | basic_block b1; |
8c660648 | 5956 | |
197043f5 RH |
5957 | if (IS_SPECULATIVE_INSN (insn)) |
5958 | { | |
5959 | if (!check_live (insn, INSN_BB (insn))) | |
5960 | continue; | |
5961 | update_live (insn, INSN_BB (insn)); | |
8c660648 | 5962 | |
197043f5 RH |
5963 | /* For speculative load, mark insns fed by it. */ |
5964 | if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn)) | |
5965 | set_spec_fed (insn); | |
8c660648 | 5966 | |
197043f5 RH |
5967 | nr_spec++; |
5968 | } | |
5969 | nr_inter++; | |
8c660648 | 5970 | |
c88e8206 RH |
5971 | /* Find the beginning of the scheduling group; update the |
5972 | containing block number for the insns. */ | |
197043f5 | 5973 | temp = insn; |
c88e8206 RH |
5974 | set_block_num (temp, target_bb); |
5975 | while (SCHED_GROUP_P (insn)) | |
5976 | { | |
5977 | temp = PREV_INSN (temp); | |
5978 | set_block_num (temp, target_bb); | |
5979 | } | |
4f64eaca | 5980 | |
197043f5 | 5981 | /* Update source block boundaries. */ |
c88e8206 RH |
5982 | b1 = BLOCK_FOR_INSN (temp); |
5983 | if (temp == b1->head && insn == b1->end) | |
197043f5 RH |
5984 | { |
5985 | /* We moved all the insns in the basic block. | |
5986 | Emit a note after the last insn and update the | |
5987 | begin/end boundaries to point to the note. */ | |
c88e8206 RH |
5988 | rtx note = emit_note_after (NOTE_INSN_DELETED, insn); |
5989 | b1->head = note; | |
5990 | b1->end = note; | |
8c660648 | 5991 | } |
c88e8206 | 5992 | else if (insn == b1->end) |
8c660648 | 5993 | { |
197043f5 RH |
5994 | /* We took insns from the end of the basic block, |
5995 | so update the end of block boundary so that it | |
5996 | points to the first insn we did not move. */ | |
c88e8206 | 5997 | b1->end = PREV_INSN (temp); |
8c660648 | 5998 | } |
c88e8206 | 5999 | else if (temp == b1->head) |
197043f5 RH |
6000 | { |
6001 | /* We took insns from the start of the basic block, | |
6002 | so update the start of block boundary so that | |
6003 | it points to the first insn we did not move. */ | |
c88e8206 | 6004 | b1->head = NEXT_INSN (insn); |
197043f5 RH |
6005 | } |
6006 | } | |
6007 | else | |
6008 | { | |
6009 | /* In block motion. */ | |
6010 | sched_target_n_insns++; | |
6011 | } | |
8c660648 | 6012 | |
197043f5 RH |
6013 | last_scheduled_insn = insn; |
6014 | last = move_insn (insn, last); | |
6015 | sched_n_insns++; | |
8c660648 | 6016 | |
e4da5f6d | 6017 | #ifdef MD_SCHED_VARIABLE_ISSUE |
197043f5 RH |
6018 | MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, |
6019 | can_issue_more); | |
e4da5f6d | 6020 | #else |
197043f5 | 6021 | can_issue_more--; |
e4da5f6d | 6022 | #endif |
8c660648 | 6023 | |
197043f5 | 6024 | n_ready = schedule_insn (insn, ready, n_ready, clock_var); |
8c660648 | 6025 | |
197043f5 RH |
6026 | /* Close this block after scheduling its jump. */ |
6027 | if (GET_CODE (last_scheduled_insn) == JUMP_INSN) | |
6028 | break; | |
8c660648 JL |
6029 | } |
6030 | ||
197043f5 | 6031 | /* Debug info. */ |
8c660648 | 6032 | if (sched_verbose) |
197043f5 | 6033 | visualize_scheduled_insns (b, clock_var); |
8c660648 JL |
6034 | } |
6035 | ||
63de6c74 | 6036 | /* Debug info. */ |
8c660648 JL |
6037 | if (sched_verbose) |
6038 | { | |
6039 | fprintf (dump, ";;\tReady list (final): "); | |
6040 | debug_ready_list (ready, n_ready); | |
6041 | print_block_visualization (b, ""); | |
6042 | } | |
6043 | ||
6044 | /* Sanity check -- queue must be empty now. Meaningless if region has | |
cc132865 | 6045 | multiple bbs. */ |
8c660648 | 6046 | if (current_nr_blocks > 1) |
cc132865 JL |
6047 | if (!flag_schedule_interblock && q_size != 0) |
6048 | abort (); | |
8c660648 | 6049 | |
63de6c74 | 6050 | /* Update head/tail boundaries. */ |
8c660648 JL |
6051 | head = NEXT_INSN (prev_head); |
6052 | tail = last; | |
6053 | ||
8c660648 JL |
6054 | /* Restore-other-notes: NOTE_LIST is the end of a chain of notes |
6055 | previously found among the insns. Insert them at the beginning | |
6056 | of the insns. */ | |
6057 | if (note_list != 0) | |
6058 | { | |
6059 | rtx note_head = note_list; | |
6060 | ||
6061 | while (PREV_INSN (note_head)) | |
6062 | { | |
6063 | note_head = PREV_INSN (note_head); | |
6064 | } | |
6065 | ||
6066 | PREV_INSN (note_head) = PREV_INSN (head); | |
6067 | NEXT_INSN (PREV_INSN (head)) = note_head; | |
6068 | PREV_INSN (head) = note_list; | |
6069 | NEXT_INSN (note_list) = head; | |
6070 | head = note_head; | |
6071 | } | |
6072 | ||
63de6c74 | 6073 | /* Update target block boundaries. */ |
8c660648 | 6074 | if (new_needs & NEED_HEAD) |
3b413743 | 6075 | BLOCK_HEAD (b) = head; |
8c660648 JL |
6076 | |
6077 | if (new_needs & NEED_TAIL) | |
3b413743 | 6078 | BLOCK_END (b) = tail; |
8c660648 | 6079 | |
63de6c74 | 6080 | /* Debugging. */ |
8c660648 JL |
6081 | if (sched_verbose) |
6082 | { | |
6083 | fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n", | |
3b413743 | 6084 | clock_var, INSN_UID (BLOCK_HEAD (b))); |
8c660648 | 6085 | fprintf (dump, ";; new basic block end = %d\n\n", |
3b413743 | 6086 | INSN_UID (BLOCK_END (b))); |
8c660648 JL |
6087 | } |
6088 | ||
6089 | return (sched_n_insns); | |
6090 | } /* schedule_block () */ | |
6091 | \f | |
6092 | ||
63de6c74 | 6093 | /* Print the bit-set of registers, S, callable from debugger. */ |
8c660648 JL |
6094 | |
6095 | extern void | |
6096 | debug_reg_vector (s) | |
6097 | regset s; | |
6098 | { | |
6099 | int regno; | |
6100 | ||
6101 | EXECUTE_IF_SET_IN_REG_SET (s, 0, regno, | |
6102 | { | |
6103 | fprintf (dump, " %d", regno); | |
6104 | }); | |
6105 | ||
6106 | fprintf (dump, "\n"); | |
6107 | } | |
6108 | ||
6109 | /* Use the backward dependences from LOG_LINKS to build | |
6110 | forward dependences in INSN_DEPEND. */ | |
6111 | ||
6112 | static void | |
6113 | compute_block_forward_dependences (bb) | |
6114 | int bb; | |
6115 | { | |
6116 | rtx insn, link; | |
6117 | rtx tail, head; | |
6118 | rtx next_tail; | |
6119 | enum reg_note dep_type; | |
6120 | ||
6121 | get_block_head_tail (bb, &head, &tail); | |
6122 | next_tail = NEXT_INSN (tail); | |
6123 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6124 | { | |
6125 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6126 | continue; | |
6127 | ||
6128 | insn = group_leader (insn); | |
6129 | ||
6130 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
6131 | { | |
6132 | rtx x = group_leader (XEXP (link, 0)); | |
6133 | rtx new_link; | |
6134 | ||
6135 | if (x != XEXP (link, 0)) | |
6136 | continue; | |
6137 | ||
706c5c2f JL |
6138 | #ifdef ENABLE_CHECKING |
6139 | /* If add_dependence is working properly there should never | |
6140 | be notes, deleted insns or duplicates in the backward | |
6141 | links. Thus we need not check for them here. | |
6142 | ||
6143 | However, if we have enabled checking we might as well go | |
6144 | ahead and verify that add_dependence worked properly. */ | |
6145 | if (GET_CODE (x) == NOTE | |
6146 | || INSN_DELETED_P (x) | |
6147 | || find_insn_list (insn, INSN_DEPEND (x))) | |
6148 | abort (); | |
6149 | #endif | |
8c660648 | 6150 | |
ebb7b10b | 6151 | new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x)); |
8c660648 JL |
6152 | |
6153 | dep_type = REG_NOTE_KIND (link); | |
6154 | PUT_REG_NOTE_KIND (new_link, dep_type); | |
6155 | ||
8c660648 JL |
6156 | INSN_DEPEND (x) = new_link; |
6157 | INSN_DEP_COUNT (insn) += 1; | |
6158 | } | |
6159 | } | |
6160 | } | |
6161 | ||
6162 | /* Initialize variables for region data dependence analysis. | |
63de6c74 | 6163 | n_bbs is the number of region blocks. */ |
8c660648 | 6164 | |
6d3352d9 | 6165 | __inline static void |
8c660648 JL |
6166 | init_rgn_data_dependences (n_bbs) |
6167 | int n_bbs; | |
6168 | { | |
6169 | int bb; | |
6170 | ||
63de6c74 | 6171 | /* Variables for which one copy exists for each block. */ |
8c660648 JL |
6172 | bzero ((char *) bb_pending_read_insns, n_bbs * sizeof (rtx)); |
6173 | bzero ((char *) bb_pending_read_mems, n_bbs * sizeof (rtx)); | |
6174 | bzero ((char *) bb_pending_write_insns, n_bbs * sizeof (rtx)); | |
6175 | bzero ((char *) bb_pending_write_mems, n_bbs * sizeof (rtx)); | |
6176 | bzero ((char *) bb_pending_lists_length, n_bbs * sizeof (rtx)); | |
6177 | bzero ((char *) bb_last_pending_memory_flush, n_bbs * sizeof (rtx)); | |
6178 | bzero ((char *) bb_last_function_call, n_bbs * sizeof (rtx)); | |
6179 | bzero ((char *) bb_sched_before_next_call, n_bbs * sizeof (rtx)); | |
6180 | ||
6181 | /* Create an insn here so that we can hang dependencies off of it later. */ | |
6182 | for (bb = 0; bb < n_bbs; bb++) | |
6183 | { | |
6184 | bb_sched_before_next_call[bb] = | |
38a448ca RH |
6185 | gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
6186 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
6187 | LOG_LINKS (bb_sched_before_next_call[bb]) = 0; |
6188 | } | |
6189 | } | |
6190 | ||
63de6c74 MH |
6191 | /* Add dependences so that branches are scheduled to run last in their |
6192 | block. */ | |
8c660648 JL |
6193 | |
6194 | static void | |
6195 | add_branch_dependences (head, tail) | |
6196 | rtx head, tail; | |
6197 | { | |
6198 | ||
6199 | rtx insn, last; | |
6200 | ||
6201 | /* For all branches, calls, uses, and cc0 setters, force them to remain | |
6202 | in order at the end of the block by adding dependencies and giving | |
6203 | the last a high priority. There may be notes present, and prev_head | |
6204 | may also be a note. | |
6205 | ||
6206 | Branches must obviously remain at the end. Calls should remain at the | |
6207 | end since moving them results in worse register allocation. Uses remain | |
6208 | at the end to ensure proper register allocation. cc0 setters remaim | |
6209 | at the end because they can't be moved away from their cc0 user. */ | |
6210 | insn = tail; | |
6211 | last = 0; | |
6212 | while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
6213 | || (GET_CODE (insn) == INSN | |
6214 | && (GET_CODE (PATTERN (insn)) == USE | |
6215 | #ifdef HAVE_cc0 | |
6216 | || sets_cc0_p (PATTERN (insn)) | |
6217 | #endif | |
6218 | )) | |
6219 | || GET_CODE (insn) == NOTE) | |
6220 | { | |
6221 | if (GET_CODE (insn) != NOTE) | |
6222 | { | |
6223 | if (last != 0 | |
6224 | && !find_insn_list (insn, LOG_LINKS (last))) | |
6225 | { | |
6226 | add_dependence (last, insn, REG_DEP_ANTI); | |
6227 | INSN_REF_COUNT (insn)++; | |
6228 | } | |
6229 | ||
6230 | CANT_MOVE (insn) = 1; | |
6231 | ||
6232 | last = insn; | |
326ee7a3 JL |
6233 | /* Skip over insns that are part of a group. |
6234 | Make each insn explicitly depend on the previous insn. | |
6235 | This ensures that only the group header will ever enter | |
6236 | the ready queue (and, when scheduled, will automatically | |
6237 | schedule the SCHED_GROUP_P block). */ | |
8c660648 | 6238 | while (SCHED_GROUP_P (insn)) |
326ee7a3 JL |
6239 | { |
6240 | rtx temp = prev_nonnote_insn (insn); | |
6241 | add_dependence (insn, temp, REG_DEP_ANTI); | |
6242 | insn = temp; | |
6243 | } | |
8c660648 JL |
6244 | } |
6245 | ||
6246 | /* Don't overrun the bounds of the basic block. */ | |
6247 | if (insn == head) | |
6248 | break; | |
6249 | ||
6250 | insn = PREV_INSN (insn); | |
6251 | } | |
6252 | ||
63de6c74 | 6253 | /* Make sure these insns are scheduled last in their block. */ |
8c660648 JL |
6254 | insn = last; |
6255 | if (insn != 0) | |
6256 | while (insn != head) | |
6257 | { | |
6258 | insn = prev_nonnote_insn (insn); | |
6259 | ||
6260 | if (INSN_REF_COUNT (insn) != 0) | |
6261 | continue; | |
6262 | ||
87373fba | 6263 | add_dependence (last, insn, REG_DEP_ANTI); |
8c660648 JL |
6264 | INSN_REF_COUNT (insn) = 1; |
6265 | ||
6266 | /* Skip over insns that are part of a group. */ | |
6267 | while (SCHED_GROUP_P (insn)) | |
6268 | insn = prev_nonnote_insn (insn); | |
6269 | } | |
6270 | } | |
6271 | ||
63de6c74 | 6272 | /* Compute backward dependences inside bb. In a multiple blocks region: |
8c660648 JL |
6273 | (1) a bb is analyzed after its predecessors, and (2) the lists in |
6274 | effect at the end of bb (after analyzing for bb) are inherited by | |
6275 | bb's successrs. | |
6276 | ||
6277 | Specifically for reg-reg data dependences, the block insns are | |
6278 | scanned by sched_analyze () top-to-bottom. Two lists are | |
63de6c74 | 6279 | maintained by sched_analyze (): reg_last_sets[] for register DEFs, |
8c660648 JL |
6280 | and reg_last_uses[] for register USEs. |
6281 | ||
6282 | When analysis is completed for bb, we update for its successors: | |
6283 | ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb]) | |
6284 | ; - USES[succ] = Union (USES [succ], DEFS [bb]) | |
6285 | ||
6286 | The mechanism for computing mem-mem data dependence is very | |
6287 | similar, and the result is interblock dependences in the region. */ | |
6288 | ||
6289 | static void | |
6290 | compute_block_backward_dependences (bb) | |
6291 | int bb; | |
6292 | { | |
6293 | int b; | |
6294 | rtx x; | |
6295 | rtx head, tail; | |
6296 | int max_reg = max_reg_num (); | |
6297 | ||
6298 | b = BB_TO_BLOCK (bb); | |
6299 | ||
6300 | if (current_nr_blocks == 1) | |
6301 | { | |
6302 | reg_last_uses = (rtx *) alloca (max_reg * sizeof (rtx)); | |
6303 | reg_last_sets = (rtx *) alloca (max_reg * sizeof (rtx)); | |
28c95eff | 6304 | reg_last_clobbers = (rtx *) alloca (max_reg * sizeof (rtx)); |
8c660648 JL |
6305 | |
6306 | bzero ((char *) reg_last_uses, max_reg * sizeof (rtx)); | |
6307 | bzero ((char *) reg_last_sets, max_reg * sizeof (rtx)); | |
28c95eff | 6308 | bzero ((char *) reg_last_clobbers, max_reg * sizeof (rtx)); |
8c660648 JL |
6309 | |
6310 | pending_read_insns = 0; | |
6311 | pending_read_mems = 0; | |
6312 | pending_write_insns = 0; | |
6313 | pending_write_mems = 0; | |
6314 | pending_lists_length = 0; | |
6315 | last_function_call = 0; | |
6316 | last_pending_memory_flush = 0; | |
6317 | sched_before_next_call | |
38a448ca RH |
6318 | = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
6319 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
6320 | LOG_LINKS (sched_before_next_call) = 0; |
6321 | } | |
6322 | else | |
6323 | { | |
6324 | reg_last_uses = bb_reg_last_uses[bb]; | |
6325 | reg_last_sets = bb_reg_last_sets[bb]; | |
28c95eff | 6326 | reg_last_clobbers = bb_reg_last_clobbers[bb]; |
8c660648 JL |
6327 | |
6328 | pending_read_insns = bb_pending_read_insns[bb]; | |
6329 | pending_read_mems = bb_pending_read_mems[bb]; | |
6330 | pending_write_insns = bb_pending_write_insns[bb]; | |
6331 | pending_write_mems = bb_pending_write_mems[bb]; | |
6332 | pending_lists_length = bb_pending_lists_length[bb]; | |
6333 | last_function_call = bb_last_function_call[bb]; | |
6334 | last_pending_memory_flush = bb_last_pending_memory_flush[bb]; | |
6335 | ||
6336 | sched_before_next_call = bb_sched_before_next_call[bb]; | |
6337 | } | |
6338 | ||
63de6c74 | 6339 | /* Do the analysis for this block. */ |
8c660648 JL |
6340 | get_block_head_tail (bb, &head, &tail); |
6341 | sched_analyze (head, tail); | |
6342 | add_branch_dependences (head, tail); | |
6343 | ||
6344 | if (current_nr_blocks > 1) | |
6345 | { | |
6346 | int e, first_edge; | |
6347 | int b_succ, bb_succ; | |
6348 | int reg; | |
6349 | rtx link_insn, link_mem; | |
6350 | rtx u; | |
6351 | ||
63de6c74 MH |
6352 | /* These lists should point to the right place, for correct |
6353 | freeing later. */ | |
8c660648 JL |
6354 | bb_pending_read_insns[bb] = pending_read_insns; |
6355 | bb_pending_read_mems[bb] = pending_read_mems; | |
6356 | bb_pending_write_insns[bb] = pending_write_insns; | |
6357 | bb_pending_write_mems[bb] = pending_write_mems; | |
6358 | ||
63de6c74 | 6359 | /* bb's structures are inherited by it's successors. */ |
8c660648 JL |
6360 | first_edge = e = OUT_EDGES (b); |
6361 | if (e > 0) | |
6362 | do | |
6363 | { | |
6364 | b_succ = TO_BLOCK (e); | |
6365 | bb_succ = BLOCK_TO_BB (b_succ); | |
6366 | ||
63de6c74 | 6367 | /* Only bbs "below" bb, in the same region, are interesting. */ |
8c660648 JL |
6368 | if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ) |
6369 | || bb_succ <= bb) | |
6370 | { | |
6371 | e = NEXT_OUT (e); | |
6372 | continue; | |
6373 | } | |
6374 | ||
6375 | for (reg = 0; reg < max_reg; reg++) | |
6376 | { | |
6377 | ||
63de6c74 | 6378 | /* reg-last-uses lists are inherited by bb_succ. */ |
8c660648 JL |
6379 | for (u = reg_last_uses[reg]; u; u = XEXP (u, 1)) |
6380 | { | |
63de6c74 MH |
6381 | if (find_insn_list (XEXP (u, 0), |
6382 | (bb_reg_last_uses[bb_succ])[reg])) | |
8c660648 JL |
6383 | continue; |
6384 | ||
6385 | (bb_reg_last_uses[bb_succ])[reg] | |
ebb7b10b RH |
6386 | = alloc_INSN_LIST (XEXP (u, 0), |
6387 | (bb_reg_last_uses[bb_succ])[reg]); | |
8c660648 JL |
6388 | } |
6389 | ||
63de6c74 | 6390 | /* reg-last-defs lists are inherited by bb_succ. */ |
8c660648 JL |
6391 | for (u = reg_last_sets[reg]; u; u = XEXP (u, 1)) |
6392 | { | |
63de6c74 MH |
6393 | if (find_insn_list (XEXP (u, 0), |
6394 | (bb_reg_last_sets[bb_succ])[reg])) | |
8c660648 JL |
6395 | continue; |
6396 | ||
6397 | (bb_reg_last_sets[bb_succ])[reg] | |
ebb7b10b RH |
6398 | = alloc_INSN_LIST (XEXP (u, 0), |
6399 | (bb_reg_last_sets[bb_succ])[reg]); | |
8c660648 | 6400 | } |
28c95eff RH |
6401 | |
6402 | for (u = reg_last_clobbers[reg]; u; u = XEXP (u, 1)) | |
6403 | { | |
63de6c74 MH |
6404 | if (find_insn_list (XEXP (u, 0), |
6405 | (bb_reg_last_clobbers[bb_succ])[reg])) | |
28c95eff RH |
6406 | continue; |
6407 | ||
6408 | (bb_reg_last_clobbers[bb_succ])[reg] | |
6409 | = alloc_INSN_LIST (XEXP (u, 0), | |
6410 | (bb_reg_last_clobbers[bb_succ])[reg]); | |
6411 | } | |
8c660648 JL |
6412 | } |
6413 | ||
63de6c74 | 6414 | /* Mem read/write lists are inherited by bb_succ. */ |
8c660648 JL |
6415 | link_insn = pending_read_insns; |
6416 | link_mem = pending_read_mems; | |
6417 | while (link_insn) | |
6418 | { | |
63de6c74 MH |
6419 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
6420 | XEXP (link_mem, 0), | |
8c660648 JL |
6421 | bb_pending_read_insns[bb_succ], |
6422 | bb_pending_read_mems[bb_succ]))) | |
6423 | add_insn_mem_dependence (&bb_pending_read_insns[bb_succ], | |
6424 | &bb_pending_read_mems[bb_succ], | |
6425 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
6426 | link_insn = XEXP (link_insn, 1); | |
6427 | link_mem = XEXP (link_mem, 1); | |
6428 | } | |
6429 | ||
6430 | link_insn = pending_write_insns; | |
6431 | link_mem = pending_write_mems; | |
6432 | while (link_insn) | |
6433 | { | |
63de6c74 MH |
6434 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
6435 | XEXP (link_mem, 0), | |
8c660648 JL |
6436 | bb_pending_write_insns[bb_succ], |
6437 | bb_pending_write_mems[bb_succ]))) | |
6438 | add_insn_mem_dependence (&bb_pending_write_insns[bb_succ], | |
6439 | &bb_pending_write_mems[bb_succ], | |
6440 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
6441 | ||
6442 | link_insn = XEXP (link_insn, 1); | |
6443 | link_mem = XEXP (link_mem, 1); | |
6444 | } | |
6445 | ||
63de6c74 | 6446 | /* last_function_call is inherited by bb_succ. */ |
8c660648 JL |
6447 | for (u = last_function_call; u; u = XEXP (u, 1)) |
6448 | { | |
63de6c74 MH |
6449 | if (find_insn_list (XEXP (u, 0), |
6450 | bb_last_function_call[bb_succ])) | |
8c660648 JL |
6451 | continue; |
6452 | ||
6453 | bb_last_function_call[bb_succ] | |
ebb7b10b RH |
6454 | = alloc_INSN_LIST (XEXP (u, 0), |
6455 | bb_last_function_call[bb_succ]); | |
8c660648 JL |
6456 | } |
6457 | ||
63de6c74 | 6458 | /* last_pending_memory_flush is inherited by bb_succ. */ |
8c660648 JL |
6459 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
6460 | { | |
63de6c74 MH |
6461 | if (find_insn_list (XEXP (u, 0), |
6462 | bb_last_pending_memory_flush[bb_succ])) | |
8c660648 JL |
6463 | continue; |
6464 | ||
6465 | bb_last_pending_memory_flush[bb_succ] | |
ebb7b10b RH |
6466 | = alloc_INSN_LIST (XEXP (u, 0), |
6467 | bb_last_pending_memory_flush[bb_succ]); | |
8c660648 JL |
6468 | } |
6469 | ||
63de6c74 | 6470 | /* sched_before_next_call is inherited by bb_succ. */ |
8c660648 JL |
6471 | x = LOG_LINKS (sched_before_next_call); |
6472 | for (; x; x = XEXP (x, 1)) | |
6473 | add_dependence (bb_sched_before_next_call[bb_succ], | |
6474 | XEXP (x, 0), REG_DEP_ANTI); | |
6475 | ||
6476 | e = NEXT_OUT (e); | |
6477 | } | |
6478 | while (e != first_edge); | |
6479 | } | |
ebb7b10b | 6480 | |
63de6c74 | 6481 | /* Free up the INSN_LISTs. |
7eea6443 JL |
6482 | |
6483 | Note this loop is executed max_reg * nr_regions times. It's first | |
5a4f6418 AM |
6484 | implementation accounted for over 90% of the calls to free_INSN_LIST_list. |
6485 | The list was empty for the vast majority of those calls. On the PA, not | |
6486 | calling free_INSN_LIST_list in those cases improves -O2 compile times by | |
7eea6443 | 6487 | 3-5% on average. */ |
ebb7b10b RH |
6488 | for (b = 0; b < max_reg; ++b) |
6489 | { | |
28c95eff | 6490 | if (reg_last_clobbers[b]) |
5a4f6418 | 6491 | free_INSN_LIST_list (®_last_clobbers[b]); |
7eea6443 | 6492 | if (reg_last_sets[b]) |
5a4f6418 | 6493 | free_INSN_LIST_list (®_last_sets[b]); |
7eea6443 | 6494 | if (reg_last_uses[b]) |
5a4f6418 | 6495 | free_INSN_LIST_list (®_last_uses[b]); |
ebb7b10b RH |
6496 | } |
6497 | ||
6498 | /* Assert that we won't need bb_reg_last_* for this block anymore. */ | |
6499 | if (current_nr_blocks > 1) | |
6500 | { | |
6501 | bb_reg_last_uses[bb] = (rtx *) NULL_RTX; | |
6502 | bb_reg_last_sets[bb] = (rtx *) NULL_RTX; | |
28c95eff | 6503 | bb_reg_last_clobbers[bb] = (rtx *) NULL_RTX; |
ebb7b10b | 6504 | } |
8c660648 JL |
6505 | } |
6506 | ||
63de6c74 | 6507 | /* Print dependences for debugging, callable from debugger. */ |
8c660648 JL |
6508 | |
6509 | void | |
6510 | debug_dependencies () | |
6511 | { | |
6512 | int bb; | |
6513 | ||
6514 | fprintf (dump, ";; --------------- forward dependences: ------------ \n"); | |
6515 | for (bb = 0; bb < current_nr_blocks; bb++) | |
6516 | { | |
6517 | if (1) | |
6518 | { | |
6519 | rtx head, tail; | |
6520 | rtx next_tail; | |
6521 | rtx insn; | |
6522 | ||
6523 | get_block_head_tail (bb, &head, &tail); | |
6524 | next_tail = NEXT_INSN (tail); | |
6525 | fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n", | |
6526 | BB_TO_BLOCK (bb), bb); | |
6527 | ||
6528 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
6529 | "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units"); | |
6530 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
6531 | "----", "----", "--", "---", "----", "----", "--------", "-----"); | |
6532 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6533 | { | |
6534 | rtx link; | |
6535 | int unit, range; | |
6536 | ||
6537 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6538 | { | |
6539 | int n; | |
6540 | fprintf (dump, ";; %6d ", INSN_UID (insn)); | |
6541 | if (GET_CODE (insn) == NOTE) | |
ebc25a17 MM |
6542 | { |
6543 | n = NOTE_LINE_NUMBER (insn); | |
6544 | if (n < 0) | |
6545 | fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n)); | |
6546 | else | |
6547 | fprintf (dump, "line %d, file %s\n", n, | |
6548 | NOTE_SOURCE_FILE (insn)); | |
6549 | } | |
6550 | else | |
4f64eaca | 6551 | fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn))); |
8c660648 JL |
6552 | continue; |
6553 | } | |
6554 | ||
6555 | unit = insn_unit (insn); | |
6556 | range = (unit < 0 | |
6557 | || function_units[unit].blockage_range_function == 0) ? 0 : | |
6558 | function_units[unit].blockage_range_function (insn); | |
6559 | fprintf (dump, | |
6560 | ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ", | |
6561 | (SCHED_GROUP_P (insn) ? "+" : " "), | |
6562 | INSN_UID (insn), | |
6563 | INSN_CODE (insn), | |
6564 | INSN_BB (insn), | |
6565 | INSN_DEP_COUNT (insn), | |
6566 | INSN_PRIORITY (insn), | |
6567 | insn_cost (insn, 0, 0), | |
6568 | (int) MIN_BLOCKAGE_COST (range), | |
6569 | (int) MAX_BLOCKAGE_COST (range)); | |
6570 | insn_print_units (insn); | |
6571 | fprintf (dump, "\t: "); | |
6572 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
6573 | fprintf (dump, "%d ", INSN_UID (XEXP (link, 0))); | |
6574 | fprintf (dump, "\n"); | |
6575 | } | |
6576 | } | |
6577 | } | |
6578 | fprintf (dump, "\n"); | |
6579 | } | |
6580 | ||
63de6c74 | 6581 | /* Set_priorities: compute priority of each insn in the block. */ |
8c660648 JL |
6582 | |
6583 | static int | |
6584 | set_priorities (bb) | |
6585 | int bb; | |
6586 | { | |
6587 | rtx insn; | |
6588 | int n_insn; | |
6589 | ||
6590 | rtx tail; | |
6591 | rtx prev_head; | |
6592 | rtx head; | |
6593 | ||
6594 | get_block_head_tail (bb, &head, &tail); | |
6595 | prev_head = PREV_INSN (head); | |
6596 | ||
6597 | if (head == tail | |
6598 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6599 | return 0; | |
6600 | ||
6601 | n_insn = 0; | |
6602 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) | |
6603 | { | |
6604 | ||
6605 | if (GET_CODE (insn) == NOTE) | |
6606 | continue; | |
6607 | ||
6608 | if (!(SCHED_GROUP_P (insn))) | |
6609 | n_insn++; | |
6610 | (void) priority (insn); | |
6611 | } | |
6612 | ||
6613 | return n_insn; | |
6614 | } | |
6615 | ||
6616 | /* Make each element of VECTOR point at an rtx-vector, | |
6617 | taking the space for all those rtx-vectors from SPACE. | |
6618 | SPACE is of type (rtx *), but it is really as long as NELTS rtx-vectors. | |
6619 | BYTES_PER_ELT is the number of bytes in one rtx-vector. | |
63de6c74 | 6620 | (this is the same as init_regset_vector () in flow.c) */ |
8c660648 JL |
6621 | |
6622 | static void | |
6623 | init_rtx_vector (vector, space, nelts, bytes_per_elt) | |
6624 | rtx **vector; | |
6625 | rtx *space; | |
6626 | int nelts; | |
6627 | int bytes_per_elt; | |
6628 | { | |
6629 | register int i; | |
6630 | register rtx *p = space; | |
6631 | ||
6632 | for (i = 0; i < nelts; i++) | |
6633 | { | |
6634 | vector[i] = p; | |
6635 | p += bytes_per_elt / sizeof (*p); | |
6636 | } | |
6637 | } | |
6638 | ||
6639 | /* Schedule a region. A region is either an inner loop, a loop-free | |
6640 | subroutine, or a single basic block. Each bb in the region is | |
6641 | scheduled after its flow predecessors. */ | |
6642 | ||
6643 | static void | |
6644 | schedule_region (rgn) | |
6645 | int rgn; | |
6646 | { | |
6647 | int bb; | |
6648 | int rgn_n_insns = 0; | |
6649 | int sched_rgn_n_insns = 0; | |
c46a37c4 RH |
6650 | int initial_deaths; |
6651 | sbitmap blocks; | |
8c660648 | 6652 | |
63de6c74 | 6653 | /* Set variables for the current region. */ |
8c660648 JL |
6654 | current_nr_blocks = RGN_NR_BLOCKS (rgn); |
6655 | current_blocks = RGN_BLOCKS (rgn); | |
6656 | ||
6657 | reg_pending_sets = ALLOCA_REG_SET (); | |
28c95eff | 6658 | reg_pending_clobbers = ALLOCA_REG_SET (); |
8c660648 JL |
6659 | reg_pending_sets_all = 0; |
6660 | ||
c46a37c4 RH |
6661 | /* Create a bitmap of the blocks in this region. */ |
6662 | blocks = sbitmap_alloc (n_basic_blocks); | |
6663 | sbitmap_zero (blocks); | |
6664 | ||
6665 | for (bb = current_nr_blocks - 1; bb >= 0; --bb) | |
6666 | SET_BIT (blocks, BB_TO_BLOCK (bb)); | |
6667 | ||
63de6c74 | 6668 | /* Initializations for region data dependence analyisis. */ |
8c660648 JL |
6669 | if (current_nr_blocks > 1) |
6670 | { | |
6671 | rtx *space; | |
6672 | int maxreg = max_reg_num (); | |
6673 | ||
6674 | bb_reg_last_uses = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
6675 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
6676 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
28c95eff RH |
6677 | init_rtx_vector (bb_reg_last_uses, space, current_nr_blocks, |
6678 | maxreg * sizeof (rtx *)); | |
8c660648 JL |
6679 | |
6680 | bb_reg_last_sets = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
6681 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
6682 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
28c95eff RH |
6683 | init_rtx_vector (bb_reg_last_sets, space, current_nr_blocks, |
6684 | maxreg * sizeof (rtx *)); | |
6685 | ||
6686 | bb_reg_last_clobbers = | |
6687 | (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
6688 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
6689 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
6690 | init_rtx_vector (bb_reg_last_clobbers, space, current_nr_blocks, | |
6691 | maxreg * sizeof (rtx *)); | |
8c660648 JL |
6692 | |
6693 | bb_pending_read_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
6694 | bb_pending_read_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
28c95eff RH |
6695 | bb_pending_write_insns = |
6696 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 | 6697 | bb_pending_write_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); |
28c95eff RH |
6698 | bb_pending_lists_length = |
6699 | (int *) alloca (current_nr_blocks * sizeof (int)); | |
6700 | bb_last_pending_memory_flush = | |
6701 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 | 6702 | bb_last_function_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); |
28c95eff RH |
6703 | bb_sched_before_next_call = |
6704 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 JL |
6705 | |
6706 | init_rgn_data_dependences (current_nr_blocks); | |
6707 | } | |
6708 | ||
63de6c74 | 6709 | /* Compute LOG_LINKS. */ |
8c660648 JL |
6710 | for (bb = 0; bb < current_nr_blocks; bb++) |
6711 | compute_block_backward_dependences (bb); | |
6712 | ||
63de6c74 | 6713 | /* Compute INSN_DEPEND. */ |
8c660648 JL |
6714 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) |
6715 | compute_block_forward_dependences (bb); | |
6716 | ||
c46a37c4 RH |
6717 | /* Compute INSN_REG_WEIGHT. */ |
6718 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) | |
6719 | find_insn_reg_weight (bb); | |
6720 | ||
6721 | /* Remove death notes. */ | |
6722 | initial_deaths = count_or_remove_death_notes (blocks, 1); | |
6723 | ||
6724 | /* Delete line notes and set priorities. */ | |
8c660648 JL |
6725 | for (bb = 0; bb < current_nr_blocks; bb++) |
6726 | { | |
8c660648 JL |
6727 | if (write_symbols != NO_DEBUG) |
6728 | { | |
6729 | save_line_notes (bb); | |
6730 | rm_line_notes (bb); | |
6731 | } | |
6732 | ||
6733 | rgn_n_insns += set_priorities (bb); | |
6734 | } | |
6735 | ||
63de6c74 | 6736 | /* Compute interblock info: probabilities, split-edges, dominators, etc. */ |
8c660648 JL |
6737 | if (current_nr_blocks > 1) |
6738 | { | |
6739 | int i; | |
6740 | ||
6741 | prob = (float *) alloca ((current_nr_blocks) * sizeof (float)); | |
6742 | ||
6743 | bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1; | |
6744 | dom = (bbset *) alloca (current_nr_blocks * sizeof (bbset)); | |
6745 | for (i = 0; i < current_nr_blocks; i++) | |
6746 | { | |
6747 | dom[i] = (bbset) alloca (bbset_size * sizeof (HOST_WIDE_INT)); | |
6748 | bzero ((char *) dom[i], bbset_size * sizeof (HOST_WIDE_INT)); | |
6749 | } | |
6750 | ||
63de6c74 | 6751 | /* Edge to bit. */ |
8c660648 JL |
6752 | rgn_nr_edges = 0; |
6753 | edge_to_bit = (int *) alloca (nr_edges * sizeof (int)); | |
6754 | for (i = 1; i < nr_edges; i++) | |
6755 | if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn) | |
6756 | EDGE_TO_BIT (i) = rgn_nr_edges++; | |
6757 | rgn_edges = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
6758 | ||
6759 | rgn_nr_edges = 0; | |
6760 | for (i = 1; i < nr_edges; i++) | |
6761 | if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn)) | |
6762 | rgn_edges[rgn_nr_edges++] = i; | |
6763 | ||
63de6c74 | 6764 | /* Split edges. */ |
8c660648 JL |
6765 | edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1; |
6766 | pot_split = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset)); | |
63de6c74 MH |
6767 | ancestor_edges = (edgeset *) alloca (current_nr_blocks |
6768 | * sizeof (edgeset)); | |
8c660648 JL |
6769 | for (i = 0; i < current_nr_blocks; i++) |
6770 | { | |
6771 | pot_split[i] = | |
6772 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
6773 | bzero ((char *) pot_split[i], | |
6774 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
6775 | ancestor_edges[i] = | |
6776 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
6777 | bzero ((char *) ancestor_edges[i], | |
6778 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
6779 | } | |
6780 | ||
63de6c74 | 6781 | /* Compute probabilities, dominators, split_edges. */ |
8c660648 JL |
6782 | for (bb = 0; bb < current_nr_blocks; bb++) |
6783 | compute_dom_prob_ps (bb); | |
6784 | } | |
6785 | ||
63de6c74 | 6786 | /* Now we can schedule all blocks. */ |
8c660648 JL |
6787 | for (bb = 0; bb < current_nr_blocks; bb++) |
6788 | { | |
5835e573 | 6789 | sched_rgn_n_insns += schedule_block (bb, rgn_n_insns); |
8c660648 JL |
6790 | |
6791 | #ifdef USE_C_ALLOCA | |
6792 | alloca (0); | |
6793 | #endif | |
6794 | } | |
6795 | ||
63de6c74 | 6796 | /* Sanity check: verify that all region insns were scheduled. */ |
cc132865 JL |
6797 | if (sched_rgn_n_insns != rgn_n_insns) |
6798 | abort (); | |
8c660648 | 6799 | |
c46a37c4 RH |
6800 | /* Update register life and usage information. Scheduling a multi-block |
6801 | region requires a global update. */ | |
6802 | if (current_nr_blocks > 1) | |
6803 | update_life_info (blocks, UPDATE_LIFE_GLOBAL); | |
6804 | else | |
8c660648 | 6805 | { |
c46a37c4 RH |
6806 | update_life_info (blocks, UPDATE_LIFE_LOCAL); |
6807 | ||
6808 | /* In the single block case, the count of registers that died should | |
6809 | not have changed during the schedule. */ | |
6810 | if (count_or_remove_death_notes (blocks, 0) != initial_deaths) | |
6811 | abort (); | |
8c660648 JL |
6812 | } |
6813 | ||
63de6c74 | 6814 | /* Restore line notes. */ |
8c660648 JL |
6815 | if (write_symbols != NO_DEBUG) |
6816 | { | |
6817 | for (bb = 0; bb < current_nr_blocks; bb++) | |
6818 | restore_line_notes (bb); | |
6819 | } | |
6820 | ||
63de6c74 | 6821 | /* Done with this region. */ |
8c660648 | 6822 | free_pending_lists (); |
f187056f JL |
6823 | |
6824 | FREE_REG_SET (reg_pending_sets); | |
28c95eff | 6825 | FREE_REG_SET (reg_pending_clobbers); |
c46a37c4 | 6826 | sbitmap_free (blocks); |
8c660648 JL |
6827 | } |
6828 | ||
8c660648 JL |
6829 | /* The one entry point in this file. DUMP_FILE is the dump file for |
6830 | this pass. */ | |
6831 | ||
6832 | void | |
6833 | schedule_insns (dump_file) | |
6834 | FILE *dump_file; | |
6835 | { | |
6836 | ||
6837 | int max_uid; | |
6838 | int b; | |
8c660648 JL |
6839 | rtx insn; |
6840 | int rgn; | |
6841 | ||
6842 | int luid; | |
6843 | ||
63de6c74 | 6844 | /* Disable speculative loads in their presence if cc0 defined. */ |
8c660648 JL |
6845 | #ifdef HAVE_cc0 |
6846 | flag_schedule_speculative_load = 0; | |
6847 | #endif | |
6848 | ||
6849 | /* Taking care of this degenerate case makes the rest of | |
6850 | this code simpler. */ | |
6851 | if (n_basic_blocks == 0) | |
6852 | return; | |
6853 | ||
63de6c74 | 6854 | /* Set dump and sched_verbose for the desired debugging output. If no |
8c660648 JL |
6855 | dump-file was specified, but -fsched-verbose-N (any N), print to stderr. |
6856 | For -fsched-verbose-N, N>=10, print everything to stderr. */ | |
6857 | sched_verbose = sched_verbose_param; | |
6858 | if (sched_verbose_param == 0 && dump_file) | |
6859 | sched_verbose = 1; | |
6860 | dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file); | |
6861 | ||
6862 | nr_inter = 0; | |
6863 | nr_spec = 0; | |
6864 | ||
63de6c74 | 6865 | /* Initialize issue_rate. */ |
62d65906 | 6866 | issue_rate = ISSUE_RATE; |
8c660648 | 6867 | |
d3a923ee | 6868 | split_all_insns (1); |
8c660648 | 6869 | |
c88e8206 RH |
6870 | /* We use LUID 0 for the fake insn (UID 0) which holds dependencies for |
6871 | pseudos which do not cross calls. */ | |
6872 | max_uid = get_max_uid () + 1; | |
8c660648 | 6873 | |
ad85216e KG |
6874 | cant_move = xcalloc (max_uid, sizeof (char)); |
6875 | fed_by_spec_load = xcalloc (max_uid, sizeof (char)); | |
6876 | is_load_insn = xcalloc (max_uid, sizeof (char)); | |
8c660648 | 6877 | |
7c74b010 | 6878 | insn_luid = (int *) xmalloc (max_uid * sizeof (int)); |
8c660648 | 6879 | |
356edbd7 JL |
6880 | insn_luid[0] = 0; |
6881 | luid = 1; | |
8c660648 | 6882 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 6883 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 | 6884 | { |
8c660648 | 6885 | INSN_LUID (insn) = luid++; |
3b413743 | 6886 | if (insn == BLOCK_END (b)) |
8c660648 JL |
6887 | break; |
6888 | } | |
356edbd7 JL |
6889 | |
6890 | /* ?!? We could save some memory by computing a per-region luid mapping | |
6891 | which could reduce both the number of vectors in the cache and the size | |
aae0390e JL |
6892 | of each vector. Instead we just avoid the cache entirely unless the |
6893 | average number of instructions in a basic block is very high. See | |
6894 | the comment before the declaration of true_dependency_cache for | |
6895 | what we consider "very high". */ | |
6896 | if (luid / n_basic_blocks > 100 * 5) | |
6897 | { | |
6898 | true_dependency_cache = sbitmap_vector_alloc (luid, luid); | |
6899 | sbitmap_vector_zero (true_dependency_cache, luid); | |
6900 | } | |
8c660648 | 6901 | |
8c660648 JL |
6902 | nr_regions = 0; |
6903 | rgn_table = (region *) alloca ((n_basic_blocks) * sizeof (region)); | |
6904 | rgn_bb_table = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
6905 | block_to_bb = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
6906 | containing_rgn = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
6907 | ||
c88e8206 RH |
6908 | compute_bb_for_insn (max_uid); |
6909 | ||
63de6c74 | 6910 | /* Compute regions for scheduling. */ |
8c660648 JL |
6911 | if (reload_completed |
6912 | || n_basic_blocks == 1 | |
6913 | || !flag_schedule_interblock) | |
6914 | { | |
6915 | find_single_block_region (); | |
6916 | } | |
6917 | else | |
6918 | { | |
63de6c74 | 6919 | /* Verify that a 'good' control flow graph can be built. */ |
168cbdf9 | 6920 | if (is_cfg_nonregular ()) |
8c660648 JL |
6921 | { |
6922 | find_single_block_region (); | |
6923 | } | |
6924 | else | |
6925 | { | |
a2e68776 JL |
6926 | int_list_ptr *s_preds, *s_succs; |
6927 | int *num_preds, *num_succs; | |
6928 | sbitmap *dom, *pdom; | |
6929 | ||
6930 | s_preds = (int_list_ptr *) alloca (n_basic_blocks | |
6931 | * sizeof (int_list_ptr)); | |
6932 | s_succs = (int_list_ptr *) alloca (n_basic_blocks | |
6933 | * sizeof (int_list_ptr)); | |
6934 | num_preds = (int *) alloca (n_basic_blocks * sizeof (int)); | |
6935 | num_succs = (int *) alloca (n_basic_blocks * sizeof (int)); | |
6936 | dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
6937 | pdom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
6938 | ||
6939 | /* The scheduler runs after flow; therefore, we can't blindly call | |
6940 | back into find_basic_blocks since doing so could invalidate the | |
e881bb1b | 6941 | info in global_live_at_start. |
a2e68776 JL |
6942 | |
6943 | Consider a block consisting entirely of dead stores; after life | |
6944 | analysis it would be a block of NOTE_INSN_DELETED notes. If | |
6945 | we call find_basic_blocks again, then the block would be removed | |
6946 | entirely and invalidate our the register live information. | |
6947 | ||
6948 | We could (should?) recompute register live information. Doing | |
6949 | so may even be beneficial. */ | |
6950 | ||
5d27de7d | 6951 | compute_preds_succs (s_preds, s_succs, num_preds, num_succs); |
a2e68776 | 6952 | |
63de6c74 MH |
6953 | /* Compute the dominators and post dominators. We don't |
6954 | currently use post dominators, but we should for | |
6955 | speculative motion analysis. */ | |
a2e68776 JL |
6956 | compute_dominators (dom, pdom, s_preds, s_succs); |
6957 | ||
168cbdf9 JL |
6958 | /* build_control_flow will return nonzero if it detects unreachable |
6959 | blocks or any other irregularity with the cfg which prevents | |
6960 | cross block scheduling. */ | |
a2e68776 | 6961 | if (build_control_flow (s_preds, s_succs, num_preds, num_succs) != 0) |
168cbdf9 JL |
6962 | find_single_block_region (); |
6963 | else | |
a2e68776 | 6964 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom); |
8c660648 JL |
6965 | |
6966 | if (sched_verbose >= 3) | |
a2e68776 | 6967 | debug_regions (); |
8c660648 | 6968 | |
a2e68776 | 6969 | /* For now. This will move as more and more of haifa is converted |
63de6c74 | 6970 | to using the cfg code in flow.c. */ |
a2e68776 JL |
6971 | free_bb_mem (); |
6972 | free (dom); | |
6973 | free (pdom); | |
8c660648 JL |
6974 | } |
6975 | } | |
6976 | ||
6977 | /* Allocate data for this pass. See comments, above, | |
7c74b010 JW |
6978 | for what these vectors do. |
6979 | ||
6980 | We use xmalloc instead of alloca, because max_uid can be very large | |
6981 | when there is a lot of function inlining. If we used alloca, we could | |
6982 | exceed stack limits on some hosts for some inputs. */ | |
ad85216e KG |
6983 | insn_priority = (int *) xcalloc (max_uid, sizeof (int)); |
6984 | insn_reg_weight = (int *) xcalloc (max_uid, sizeof (int)); | |
6985 | insn_tick = (int *) xcalloc (max_uid, sizeof (int)); | |
6986 | insn_costs = (short *) xcalloc (max_uid, sizeof (short)); | |
6987 | insn_units = (short *) xcalloc (max_uid, sizeof (short)); | |
6988 | insn_blockage = (unsigned int *) xcalloc (max_uid, sizeof (unsigned int)); | |
6989 | insn_ref_count = (int *) xcalloc (max_uid, sizeof (int)); | |
8c660648 | 6990 | |
63de6c74 | 6991 | /* Allocate for forward dependencies. */ |
ad85216e KG |
6992 | insn_dep_count = (int *) xcalloc (max_uid, sizeof (int)); |
6993 | insn_depend = (rtx *) xcalloc (max_uid, sizeof (rtx)); | |
8c660648 | 6994 | |
8c660648 JL |
6995 | init_alias_analysis (); |
6996 | ||
6997 | if (write_symbols != NO_DEBUG) | |
6998 | { | |
6999 | rtx line; | |
7000 | ||
ad85216e | 7001 | line_note = (rtx *) xcalloc (max_uid, sizeof (rtx)); |
8c660648 JL |
7002 | line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx)); |
7003 | bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx)); | |
7004 | ||
7005 | /* Save-line-note-head: | |
7006 | Determine the line-number at the start of each basic block. | |
7007 | This must be computed and saved now, because after a basic block's | |
7008 | predecessor has been scheduled, it is impossible to accurately | |
7009 | determine the correct line number for the first insn of the block. */ | |
7010 | ||
7011 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7012 | for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line)) |
8c660648 JL |
7013 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) |
7014 | { | |
7015 | line_note_head[b] = line; | |
7016 | break; | |
7017 | } | |
7018 | } | |
7019 | ||
63de6c74 | 7020 | /* Find units used in this fuction, for visualization. */ |
8c660648 JL |
7021 | if (sched_verbose) |
7022 | init_target_units (); | |
7023 | ||
7024 | /* ??? Add a NOTE after the last insn of the last basic block. It is not | |
7025 | known why this is done. */ | |
7026 | ||
3b413743 | 7027 | insn = BLOCK_END (n_basic_blocks - 1); |
8c660648 JL |
7028 | if (NEXT_INSN (insn) == 0 |
7029 | || (GET_CODE (insn) != NOTE | |
7030 | && GET_CODE (insn) != CODE_LABEL | |
3b413743 RH |
7031 | /* Don't emit a NOTE if it would end up between an unconditional |
7032 | jump and a BARRIER. */ | |
8c660648 JL |
7033 | && !(GET_CODE (insn) == JUMP_INSN |
7034 | && GET_CODE (NEXT_INSN (insn)) == BARRIER))) | |
3b413743 | 7035 | emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1)); |
8c660648 | 7036 | |
63de6c74 | 7037 | /* Schedule every region in the subroutine. */ |
8c660648 JL |
7038 | for (rgn = 0; rgn < nr_regions; rgn++) |
7039 | { | |
7040 | schedule_region (rgn); | |
7041 | ||
7042 | #ifdef USE_C_ALLOCA | |
7043 | alloca (0); | |
7044 | #endif | |
7045 | } | |
7046 | ||
7047 | /* Reposition the prologue and epilogue notes in case we moved the | |
7048 | prologue/epilogue insns. */ | |
7049 | if (reload_completed) | |
7050 | reposition_prologue_and_epilogue_notes (get_insns ()); | |
7051 | ||
63de6c74 | 7052 | /* Delete redundant line notes. */ |
8c660648 JL |
7053 | if (write_symbols != NO_DEBUG) |
7054 | rm_redundant_line_notes (); | |
7055 | ||
8c660648 JL |
7056 | if (sched_verbose) |
7057 | { | |
7058 | if (reload_completed == 0 && flag_schedule_interblock) | |
7059 | { | |
7060 | fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n", | |
7061 | nr_inter, nr_spec); | |
7062 | } | |
7063 | else | |
7064 | { | |
7065 | if (nr_inter > 0) | |
7066 | abort (); | |
7067 | } | |
7068 | fprintf (dump, "\n\n"); | |
7069 | } | |
f187056f | 7070 | |
aae0390e JL |
7071 | if (true_dependency_cache) |
7072 | { | |
7073 | free (true_dependency_cache); | |
60588660 | 7074 | true_dependency_cache = NULL; |
aae0390e | 7075 | } |
7c74b010 JW |
7076 | free (cant_move); |
7077 | free (fed_by_spec_load); | |
7078 | free (is_load_insn); | |
7c74b010 JW |
7079 | free (insn_luid); |
7080 | ||
7081 | free (insn_priority); | |
7082 | free (insn_reg_weight); | |
7083 | free (insn_tick); | |
7084 | free (insn_costs); | |
7085 | free (insn_units); | |
7086 | free (insn_blockage); | |
7087 | free (insn_ref_count); | |
7088 | ||
7089 | free (insn_dep_count); | |
7090 | free (insn_depend); | |
7091 | ||
7092 | if (write_symbols != NO_DEBUG) | |
7093 | free (line_note); | |
7094 | ||
168cbdf9 JL |
7095 | if (edge_table) |
7096 | { | |
7097 | free (edge_table); | |
7098 | edge_table = NULL; | |
7099 | } | |
7100 | ||
7101 | if (in_edges) | |
7102 | { | |
7103 | free (in_edges); | |
7104 | in_edges = NULL; | |
7105 | } | |
7106 | if (out_edges) | |
7107 | { | |
7108 | free (out_edges); | |
7109 | out_edges = NULL; | |
7110 | } | |
8c660648 JL |
7111 | } |
7112 | #endif /* INSN_SCHEDULING */ |