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8c660648 | 1 | /* Instruction scheduling pass. |
a5cad800 | 2 | Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc. |
8c660648 JL |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
4 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, but | |
14 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to the Free | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | ||
24 | /* Instruction scheduling pass. | |
25 | ||
26 | This pass implements list scheduling within basic blocks. It is | |
27 | run twice: (1) after flow analysis, but before register allocation, | |
28 | and (2) after register allocation. | |
29 | ||
30 | The first run performs interblock scheduling, moving insns between | |
31 | different blocks in the same "region", and the second runs only | |
32 | basic block scheduling. | |
33 | ||
34 | Interblock motions performed are useful motions and speculative | |
35 | motions, including speculative loads. Motions requiring code | |
36 | duplication are not supported. The identification of motion type | |
37 | and the check for validity of speculative motions requires | |
38 | construction and analysis of the function's control flow graph. | |
39 | The scheduler works as follows: | |
40 | ||
41 | We compute insn priorities based on data dependencies. Flow | |
42 | analysis only creates a fraction of the data-dependencies we must | |
43 | observe: namely, only those dependencies which the combiner can be | |
44 | expected to use. For this pass, we must therefore create the | |
45 | remaining dependencies we need to observe: register dependencies, | |
46 | memory dependencies, dependencies to keep function calls in order, | |
47 | and the dependence between a conditional branch and the setting of | |
48 | condition codes are all dealt with here. | |
49 | ||
50 | The scheduler first traverses the data flow graph, starting with | |
51 | the last instruction, and proceeding to the first, assigning values | |
52 | to insn_priority as it goes. This sorts the instructions | |
53 | topologically by data dependence. | |
54 | ||
55 | Once priorities have been established, we order the insns using | |
56 | list scheduling. This works as follows: starting with a list of | |
57 | all the ready insns, and sorted according to priority number, we | |
58 | schedule the insn from the end of the list by placing its | |
59 | predecessors in the list according to their priority order. We | |
60 | consider this insn scheduled by setting the pointer to the "end" of | |
61 | the list to point to the previous insn. When an insn has no | |
62 | predecessors, we either queue it until sufficient time has elapsed | |
63 | or add it to the ready list. As the instructions are scheduled or | |
64 | when stalls are introduced, the queue advances and dumps insns into | |
65 | the ready list. When all insns down to the lowest priority have | |
66 | been scheduled, the critical path of the basic block has been made | |
67 | as short as possible. The remaining insns are then scheduled in | |
68 | remaining slots. | |
69 | ||
70 | Function unit conflicts are resolved during forward list scheduling | |
71 | by tracking the time when each insn is committed to the schedule | |
72 | and from that, the time the function units it uses must be free. | |
73 | As insns on the ready list are considered for scheduling, those | |
74 | that would result in a blockage of the already committed insns are | |
75 | queued until no blockage will result. | |
76 | ||
77 | The following list shows the order in which we want to break ties | |
78 | among insns in the ready list: | |
79 | ||
80 | 1. choose insn with the longest path to end of bb, ties | |
81 | broken by | |
82 | 2. choose insn with least contribution to register pressure, | |
83 | ties broken by | |
84 | 3. prefer in-block upon interblock motion, ties broken by | |
85 | 4. prefer useful upon speculative motion, ties broken by | |
86 | 5. choose insn with largest control flow probability, ties | |
87 | broken by | |
88 | 6. choose insn with the least dependences upon the previously | |
89 | scheduled insn, or finally | |
2db45993 JL |
90 | 7 choose the insn which has the most insns dependent on it. |
91 | 8. choose insn with lowest UID. | |
8c660648 JL |
92 | |
93 | Memory references complicate matters. Only if we can be certain | |
94 | that memory references are not part of the data dependency graph | |
95 | (via true, anti, or output dependence), can we move operations past | |
96 | memory references. To first approximation, reads can be done | |
97 | independently, while writes introduce dependencies. Better | |
98 | approximations will yield fewer dependencies. | |
99 | ||
100 | Before reload, an extended analysis of interblock data dependences | |
101 | is required for interblock scheduling. This is performed in | |
102 | compute_block_backward_dependences (). | |
103 | ||
104 | Dependencies set up by memory references are treated in exactly the | |
105 | same way as other dependencies, by using LOG_LINKS backward | |
106 | dependences. LOG_LINKS are translated into INSN_DEPEND forward | |
107 | dependences for the purpose of forward list scheduling. | |
108 | ||
109 | Having optimized the critical path, we may have also unduly | |
110 | extended the lifetimes of some registers. If an operation requires | |
111 | that constants be loaded into registers, it is certainly desirable | |
112 | to load those constants as early as necessary, but no earlier. | |
113 | I.e., it will not do to load up a bunch of registers at the | |
114 | beginning of a basic block only to use them at the end, if they | |
115 | could be loaded later, since this may result in excessive register | |
116 | utilization. | |
117 | ||
118 | Note that since branches are never in basic blocks, but only end | |
119 | basic blocks, this pass will not move branches. But that is ok, | |
120 | since we can use GNU's delayed branch scheduling pass to take care | |
121 | of this case. | |
122 | ||
123 | Also note that no further optimizations based on algebraic | |
124 | identities are performed, so this pass would be a good one to | |
125 | perform instruction splitting, such as breaking up a multiply | |
126 | instruction into shifts and adds where that is profitable. | |
127 | ||
128 | Given the memory aliasing analysis that this pass should perform, | |
129 | it should be possible to remove redundant stores to memory, and to | |
130 | load values from registers instead of hitting memory. | |
131 | ||
132 | Before reload, speculative insns are moved only if a 'proof' exists | |
133 | that no exception will be caused by this, and if no live registers | |
134 | exist that inhibit the motion (live registers constraints are not | |
135 | represented by data dependence edges). | |
136 | ||
137 | This pass must update information that subsequent passes expect to | |
138 | be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths, | |
3b413743 RH |
139 | reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD, |
140 | BLOCK_END. | |
8c660648 JL |
141 | |
142 | The information in the line number notes is carefully retained by | |
143 | this pass. Notes that refer to the starting and ending of | |
144 | exception regions are also carefully retained by this pass. All | |
145 | other NOTE insns are grouped in their same relative order at the | |
146 | beginning of basic blocks and regions that have been scheduled. | |
147 | ||
148 | The main entry point for this pass is schedule_insns(), called for | |
149 | each function. The work of the scheduler is organized in three | |
150 | levels: (1) function level: insns are subject to splitting, | |
151 | control-flow-graph is constructed, regions are computed (after | |
152 | reload, each region is of one block), (2) region level: control | |
153 | flow graph attributes required for interblock scheduling are | |
154 | computed (dominators, reachability, etc.), data dependences and | |
155 | priorities are computed, and (3) block level: insns in the block | |
156 | are actually scheduled. */ | |
157 | \f | |
8c660648 | 158 | #include "config.h" |
5835e573 | 159 | #include "system.h" |
01198c2f | 160 | #include "toplev.h" |
8c660648 | 161 | #include "rtl.h" |
6baf1cc8 | 162 | #include "tm_p.h" |
8c660648 JL |
163 | #include "basic-block.h" |
164 | #include "regs.h" | |
49ad7cfa | 165 | #include "function.h" |
8c660648 JL |
166 | #include "hard-reg-set.h" |
167 | #include "flags.h" | |
168 | #include "insn-config.h" | |
169 | #include "insn-attr.h" | |
170 | #include "except.h" | |
487a6e06 | 171 | #include "toplev.h" |
79c9824e | 172 | #include "recog.h" |
8c660648 JL |
173 | |
174 | extern char *reg_known_equiv_p; | |
175 | extern rtx *reg_known_value; | |
176 | ||
177 | #ifdef INSN_SCHEDULING | |
178 | ||
8c660648 JL |
179 | /* target_units bitmask has 1 for each unit in the cpu. It should be |
180 | possible to compute this variable from the machine description. | |
63de6c74 | 181 | But currently it is computed by examining the insn list. Since |
8c660648 JL |
182 | this is only needed for visualization, it seems an acceptable |
183 | solution. (For understanding the mapping of bits to units, see | |
63de6c74 | 184 | definition of function_units[] in "insn-attrtab.c".) */ |
8c660648 | 185 | |
61822835 | 186 | static int target_units = 0; |
8c660648 JL |
187 | |
188 | /* issue_rate is the number of insns that can be scheduled in the same | |
189 | machine cycle. It can be defined in the config/mach/mach.h file, | |
190 | otherwise we set it to 1. */ | |
191 | ||
192 | static int issue_rate; | |
193 | ||
62d65906 JL |
194 | #ifndef ISSUE_RATE |
195 | #define ISSUE_RATE 1 | |
8c660648 JL |
196 | #endif |
197 | ||
cc132865 | 198 | /* sched-verbose controls the amount of debugging output the |
8c660648 JL |
199 | scheduler prints. It is controlled by -fsched-verbose-N: |
200 | N>0 and no -DSR : the output is directed to stderr. | |
201 | N>=10 will direct the printouts to stderr (regardless of -dSR). | |
202 | N=1: same as -dSR. | |
203 | N=2: bb's probabilities, detailed ready list info, unit/insn info. | |
204 | N=3: rtl at abort point, control-flow, regions info. | |
cc132865 | 205 | N=5: dependences info. */ |
8c660648 JL |
206 | |
207 | #define MAX_RGN_BLOCKS 10 | |
208 | #define MAX_RGN_INSNS 100 | |
209 | ||
8c660648 JL |
210 | static int sched_verbose_param = 0; |
211 | static int sched_verbose = 0; | |
8c660648 | 212 | |
63de6c74 | 213 | /* nr_inter/spec counts interblock/speculative motion for the function. */ |
8c660648 JL |
214 | static int nr_inter, nr_spec; |
215 | ||
216 | ||
63de6c74 | 217 | /* Debugging file. All printouts are sent to dump, which is always set, |
8c660648 JL |
218 | either to stderr, or to the dump listing file (-dRS). */ |
219 | static FILE *dump = 0; | |
220 | ||
221 | /* fix_sched_param() is called from toplev.c upon detection | |
222 | of the -fsched-***-N options. */ | |
223 | ||
224 | void | |
225 | fix_sched_param (param, val) | |
5f06c983 | 226 | const char *param, *val; |
8c660648 | 227 | { |
cc132865 | 228 | if (!strcmp (param, "verbose")) |
8c660648 | 229 | sched_verbose_param = atoi (val); |
8c660648 JL |
230 | else |
231 | warning ("fix_sched_param: unknown param: %s", param); | |
232 | } | |
233 | ||
234 | ||
8c660648 JL |
235 | /* Element N is the next insn that sets (hard or pseudo) register |
236 | N within the current basic block; or zero, if there is no | |
237 | such insn. Needed for new registers which may be introduced | |
238 | by splitting insns. */ | |
239 | static rtx *reg_last_uses; | |
240 | static rtx *reg_last_sets; | |
28c95eff | 241 | static rtx *reg_last_clobbers; |
8c660648 | 242 | static regset reg_pending_sets; |
28c95eff | 243 | static regset reg_pending_clobbers; |
8c660648 JL |
244 | static int reg_pending_sets_all; |
245 | ||
356edbd7 | 246 | /* To speed up the test for duplicate dependency links we keep a record |
aae0390e JL |
247 | of true dependencies created by add_dependence when the average number |
248 | of instructions in a basic block is very large. | |
356edbd7 | 249 | |
aae0390e JL |
250 | Studies have shown that there is typically around 5 instructions between |
251 | branches for typical C code. So we can make a guess that the average | |
252 | basic block is approximately 5 instructions long; we will choose 100X | |
253 | the average size as a very large basic block. | |
254 | ||
356edbd7 JL |
255 | Each insn has an associated bitmap for its dependencies. Each bitmap |
256 | has enough entries to represent a dependency on any other insn in the | |
257 | insn chain. */ | |
258 | static sbitmap *true_dependency_cache; | |
259 | ||
f66d83e1 RH |
260 | /* Indexed by INSN_UID, the collection of all data associated with |
261 | a single instruction. */ | |
262 | ||
263 | struct haifa_insn_data | |
264 | { | |
265 | /* A list of insns which depend on the instruction. Unlike LOG_LINKS, | |
266 | it represents forward dependancies. */ | |
267 | rtx depend; | |
268 | ||
269 | /* The line number note in effect for each insn. For line number | |
270 | notes, this indicates whether the note may be reused. */ | |
271 | rtx line_note; | |
272 | ||
273 | /* Logical uid gives the original ordering of the insns. */ | |
274 | int luid; | |
275 | ||
276 | /* A priority for each insn. */ | |
277 | int priority; | |
278 | ||
279 | /* The number of incoming edges in the forward dependency graph. | |
280 | As scheduling proceds, counts are decreased. An insn moves to | |
281 | the ready queue when its counter reaches zero. */ | |
282 | int dep_count; | |
283 | ||
284 | /* An encoding of the blockage range function. Both unit and range | |
285 | are coded. */ | |
286 | unsigned int blockage; | |
287 | ||
288 | /* Number of instructions referring to this insn. */ | |
289 | int ref_count; | |
290 | ||
291 | /* The minimum clock tick at which the insn becomes ready. This is | |
292 | used to note timing constraints for the insns in the pending list. */ | |
293 | int tick; | |
294 | ||
295 | short cost; | |
296 | ||
297 | /* An encoding of the function units used. */ | |
298 | short units; | |
299 | ||
300 | /* This weight is an estimation of the insn's contribution to | |
301 | register pressure. */ | |
302 | short reg_weight; | |
303 | ||
304 | /* Some insns (e.g. call) are not allowed to move across blocks. */ | |
305 | unsigned int cant_move : 1; | |
306 | ||
307 | /* Set if there's DEF-USE dependance between some speculatively | |
308 | moved load insn and this one. */ | |
309 | unsigned int fed_by_spec_load : 1; | |
310 | unsigned int is_load_insn : 1; | |
311 | }; | |
312 | ||
313 | static struct haifa_insn_data *h_i_d; | |
314 | ||
315 | #define INSN_DEPEND(INSN) (h_i_d[INSN_UID (INSN)].depend) | |
316 | #define INSN_LUID(INSN) (h_i_d[INSN_UID (INSN)].luid) | |
317 | #define INSN_PRIORITY(INSN) (h_i_d[INSN_UID (INSN)].priority) | |
318 | #define INSN_DEP_COUNT(INSN) (h_i_d[INSN_UID (INSN)].dep_count) | |
319 | #define INSN_COST(INSN) (h_i_d[INSN_UID (INSN)].cost) | |
320 | #define INSN_UNIT(INSN) (h_i_d[INSN_UID (INSN)].units) | |
321 | #define INSN_REG_WEIGHT(INSN) (h_i_d[INSN_UID (INSN)].reg_weight) | |
322 | ||
323 | #define INSN_BLOCKAGE(INSN) (h_i_d[INSN_UID (INSN)].blockage) | |
324 | #define UNIT_BITS 5 | |
325 | #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1) | |
326 | #define ENCODE_BLOCKAGE(U, R) \ | |
327 | (((U) << BLOCKAGE_BITS \ | |
328 | | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \ | |
329 | | MAX_BLOCKAGE_COST (R)) | |
330 | #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS)) | |
8c660648 JL |
331 | #define BLOCKAGE_RANGE(B) \ |
332 | (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \ | |
5835e573 | 333 | | ((B) & BLOCKAGE_MASK)) |
8c660648 JL |
334 | |
335 | /* Encodings of the `<name>_unit_blockage_range' function. */ | |
336 | #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2)) | |
337 | #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1)) | |
338 | ||
339 | #define DONE_PRIORITY -1 | |
340 | #define MAX_PRIORITY 0x7fffffff | |
341 | #define TAIL_PRIORITY 0x7ffffffe | |
342 | #define LAUNCH_PRIORITY 0x7f000001 | |
343 | #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0) | |
344 | #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0) | |
345 | ||
f66d83e1 RH |
346 | #define INSN_REF_COUNT(INSN) (h_i_d[INSN_UID (INSN)].ref_count) |
347 | #define LINE_NOTE(INSN) (h_i_d[INSN_UID (INSN)].line_note) | |
348 | #define INSN_TICK(INSN) (h_i_d[INSN_UID (INSN)].tick) | |
349 | #define CANT_MOVE(insn) (h_i_d[INSN_UID (insn)].cant_move) | |
350 | #define FED_BY_SPEC_LOAD(insn) (h_i_d[INSN_UID (insn)].fed_by_spec_load) | |
351 | #define IS_LOAD_INSN(insn) (h_i_d[INSN_UID (insn)].is_load_insn) | |
8c660648 JL |
352 | |
353 | /* Vector indexed by basic block number giving the starting line-number | |
354 | for each basic block. */ | |
355 | static rtx *line_note_head; | |
356 | ||
357 | /* List of important notes we must keep around. This is a pointer to the | |
358 | last element in the list. */ | |
359 | static rtx note_list; | |
360 | ||
8c660648 JL |
361 | /* Queues, etc. */ |
362 | ||
363 | /* An instruction is ready to be scheduled when all insns preceding it | |
364 | have already been scheduled. It is important to ensure that all | |
365 | insns which use its result will not be executed until its result | |
366 | has been computed. An insn is maintained in one of four structures: | |
367 | ||
368 | (P) the "Pending" set of insns which cannot be scheduled until | |
369 | their dependencies have been satisfied. | |
370 | (Q) the "Queued" set of insns that can be scheduled when sufficient | |
371 | time has passed. | |
372 | (R) the "Ready" list of unscheduled, uncommitted insns. | |
373 | (S) the "Scheduled" list of insns. | |
374 | ||
375 | Initially, all insns are either "Pending" or "Ready" depending on | |
376 | whether their dependencies are satisfied. | |
377 | ||
378 | Insns move from the "Ready" list to the "Scheduled" list as they | |
379 | are committed to the schedule. As this occurs, the insns in the | |
380 | "Pending" list have their dependencies satisfied and move to either | |
381 | the "Ready" list or the "Queued" set depending on whether | |
382 | sufficient time has passed to make them ready. As time passes, | |
383 | insns move from the "Queued" set to the "Ready" list. Insns may | |
384 | move from the "Ready" list to the "Queued" set if they are blocked | |
385 | due to a function unit conflict. | |
386 | ||
387 | The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled | |
388 | insns, i.e., those that are ready, queued, and pending. | |
389 | The "Queued" set (Q) is implemented by the variable `insn_queue'. | |
390 | The "Ready" list (R) is implemented by the variables `ready' and | |
391 | `n_ready'. | |
392 | The "Scheduled" list (S) is the new insn chain built by this pass. | |
393 | ||
394 | The transition (R->S) is implemented in the scheduling loop in | |
395 | `schedule_block' when the best insn to schedule is chosen. | |
396 | The transition (R->Q) is implemented in `queue_insn' when an | |
38e01259 | 397 | insn is found to have a function unit conflict with the already |
8c660648 JL |
398 | committed insns. |
399 | The transitions (P->R and P->Q) are implemented in `schedule_insn' as | |
400 | insns move from the ready list to the scheduled list. | |
401 | The transition (Q->R) is implemented in 'queue_to_insn' as time | |
402 | passes or stalls are introduced. */ | |
403 | ||
404 | /* Implement a circular buffer to delay instructions until sufficient | |
405 | time has passed. INSN_QUEUE_SIZE is a power of two larger than | |
406 | MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the | |
407 | longest time an isnsn may be queued. */ | |
408 | static rtx insn_queue[INSN_QUEUE_SIZE]; | |
409 | static int q_ptr = 0; | |
410 | static int q_size = 0; | |
411 | #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1)) | |
412 | #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1)) | |
413 | ||
8c660648 JL |
414 | /* Forward declarations. */ |
415 | static void add_dependence PROTO ((rtx, rtx, enum reg_note)); | |
c88e8206 | 416 | #ifdef HAVE_cc0 |
8c660648 | 417 | static void remove_dependence PROTO ((rtx, rtx)); |
c88e8206 | 418 | #endif |
8c660648 JL |
419 | static rtx find_insn_list PROTO ((rtx, rtx)); |
420 | static int insn_unit PROTO ((rtx)); | |
421 | static unsigned int blockage_range PROTO ((int, rtx)); | |
422 | static void clear_units PROTO ((void)); | |
423 | static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int)); | |
424 | static void schedule_unit PROTO ((int, rtx, int)); | |
425 | static int actual_hazard PROTO ((int, rtx, int, int)); | |
426 | static int potential_hazard PROTO ((int, rtx, int)); | |
427 | static int insn_cost PROTO ((rtx, rtx, rtx)); | |
428 | static int priority PROTO ((rtx)); | |
429 | static void free_pending_lists PROTO ((void)); | |
430 | static void add_insn_mem_dependence PROTO ((rtx *, rtx *, rtx, rtx)); | |
431 | static void flush_pending_lists PROTO ((rtx, int)); | |
432 | static void sched_analyze_1 PROTO ((rtx, rtx)); | |
433 | static void sched_analyze_2 PROTO ((rtx, rtx)); | |
434 | static void sched_analyze_insn PROTO ((rtx, rtx, rtx)); | |
435 | static void sched_analyze PROTO ((rtx, rtx)); | |
e1b6684c | 436 | static int rank_for_schedule PROTO ((const PTR, const PTR)); |
8c660648 JL |
437 | static void swap_sort PROTO ((rtx *, int)); |
438 | static void queue_insn PROTO ((rtx, int)); | |
439 | static int schedule_insn PROTO ((rtx, rtx *, int, int)); | |
c46a37c4 | 440 | static void find_insn_reg_weight PROTO ((int)); |
5835e573 | 441 | static int schedule_block PROTO ((int, int)); |
5f06c983 | 442 | static char *safe_concat PROTO ((char *, char *, const char *)); |
cc4fe0e2 | 443 | static int insn_issue_delay PROTO ((rtx)); |
cc4fe0e2 | 444 | static void adjust_priority PROTO ((rtx)); |
8c660648 | 445 | |
8c660648 JL |
446 | /* Control flow graph edges are kept in circular lists. */ |
447 | typedef struct | |
448 | { | |
449 | int from_block; | |
450 | int to_block; | |
451 | int next_in; | |
452 | int next_out; | |
453 | } | |
e881bb1b RH |
454 | haifa_edge; |
455 | static haifa_edge *edge_table; | |
8c660648 JL |
456 | |
457 | #define NEXT_IN(edge) (edge_table[edge].next_in) | |
458 | #define NEXT_OUT(edge) (edge_table[edge].next_out) | |
459 | #define FROM_BLOCK(edge) (edge_table[edge].from_block) | |
460 | #define TO_BLOCK(edge) (edge_table[edge].to_block) | |
461 | ||
63de6c74 MH |
462 | /* Number of edges in the control flow graph. (In fact, larger than |
463 | that by 1, since edge 0 is unused.) */ | |
8c660648 JL |
464 | static int nr_edges; |
465 | ||
63de6c74 | 466 | /* Circular list of incoming/outgoing edges of a block. */ |
8c660648 JL |
467 | static int *in_edges; |
468 | static int *out_edges; | |
469 | ||
470 | #define IN_EDGES(block) (in_edges[block]) | |
471 | #define OUT_EDGES(block) (out_edges[block]) | |
472 | ||
8c660648 JL |
473 | |
474 | ||
168cbdf9 | 475 | static int is_cfg_nonregular PROTO ((void)); |
a2e68776 JL |
476 | static int build_control_flow PROTO ((int_list_ptr *, int_list_ptr *, |
477 | int *, int *)); | |
8c660648 JL |
478 | static void new_edge PROTO ((int, int)); |
479 | ||
480 | ||
481 | /* A region is the main entity for interblock scheduling: insns | |
482 | are allowed to move between blocks in the same region, along | |
483 | control flow graph edges, in the 'up' direction. */ | |
484 | typedef struct | |
485 | { | |
63de6c74 MH |
486 | int rgn_nr_blocks; /* Number of blocks in region. */ |
487 | int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */ | |
8c660648 JL |
488 | } |
489 | region; | |
490 | ||
63de6c74 | 491 | /* Number of regions in the procedure. */ |
8c660648 JL |
492 | static int nr_regions; |
493 | ||
63de6c74 | 494 | /* Table of region descriptions. */ |
8c660648 JL |
495 | static region *rgn_table; |
496 | ||
63de6c74 | 497 | /* Array of lists of regions' blocks. */ |
8c660648 JL |
498 | static int *rgn_bb_table; |
499 | ||
500 | /* Topological order of blocks in the region (if b2 is reachable from | |
63de6c74 MH |
501 | b1, block_to_bb[b2] > block_to_bb[b1]). Note: A basic block is |
502 | always referred to by either block or b, while its topological | |
503 | order name (in the region) is refered to by bb. */ | |
8c660648 JL |
504 | static int *block_to_bb; |
505 | ||
506 | /* The number of the region containing a block. */ | |
507 | static int *containing_rgn; | |
508 | ||
509 | #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks) | |
510 | #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks) | |
511 | #define BLOCK_TO_BB(block) (block_to_bb[block]) | |
512 | #define CONTAINING_RGN(block) (containing_rgn[block]) | |
513 | ||
514 | void debug_regions PROTO ((void)); | |
515 | static void find_single_block_region PROTO ((void)); | |
a2e68776 JL |
516 | static void find_rgns PROTO ((int_list_ptr *, int_list_ptr *, |
517 | int *, int *, sbitmap *)); | |
8c660648 JL |
518 | static int too_large PROTO ((int, int *, int *)); |
519 | ||
520 | extern void debug_live PROTO ((int, int)); | |
521 | ||
522 | /* Blocks of the current region being scheduled. */ | |
523 | static int current_nr_blocks; | |
524 | static int current_blocks; | |
525 | ||
63de6c74 | 526 | /* The mapping from bb to block. */ |
8c660648 JL |
527 | #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)]) |
528 | ||
529 | ||
530 | /* Bit vectors and bitset operations are needed for computations on | |
531 | the control flow graph. */ | |
532 | ||
533 | typedef unsigned HOST_WIDE_INT *bitset; | |
534 | typedef struct | |
535 | { | |
63de6c74 MH |
536 | int *first_member; /* Pointer to the list start in bitlst_table. */ |
537 | int nr_members; /* The number of members of the bit list. */ | |
8c660648 JL |
538 | } |
539 | bitlst; | |
540 | ||
61822835 JL |
541 | static int bitlst_table_last; |
542 | static int bitlst_table_size; | |
8c660648 JL |
543 | static int *bitlst_table; |
544 | ||
545 | static char bitset_member PROTO ((bitset, int, int)); | |
546 | static void extract_bitlst PROTO ((bitset, int, bitlst *)); | |
547 | ||
63de6c74 | 548 | /* Target info declarations. |
8c660648 JL |
549 | |
550 | The block currently being scheduled is referred to as the "target" block, | |
551 | while other blocks in the region from which insns can be moved to the | |
552 | target are called "source" blocks. The candidate structure holds info | |
553 | about such sources: are they valid? Speculative? Etc. */ | |
554 | typedef bitlst bblst; | |
555 | typedef struct | |
556 | { | |
557 | char is_valid; | |
558 | char is_speculative; | |
559 | int src_prob; | |
560 | bblst split_bbs; | |
561 | bblst update_bbs; | |
562 | } | |
563 | candidate; | |
564 | ||
565 | static candidate *candidate_table; | |
566 | ||
567 | /* A speculative motion requires checking live information on the path | |
568 | from 'source' to 'target'. The split blocks are those to be checked. | |
569 | After a speculative motion, live information should be modified in | |
570 | the 'update' blocks. | |
571 | ||
63de6c74 MH |
572 | Lists of split and update blocks for each candidate of the current |
573 | target are in array bblst_table. */ | |
61822835 | 574 | static int *bblst_table, bblst_size, bblst_last; |
8c660648 JL |
575 | |
576 | #define IS_VALID(src) ( candidate_table[src].is_valid ) | |
577 | #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative ) | |
578 | #define SRC_PROB(src) ( candidate_table[src].src_prob ) | |
579 | ||
580 | /* The bb being currently scheduled. */ | |
61822835 | 581 | static int target_bb; |
8c660648 JL |
582 | |
583 | /* List of edges. */ | |
584 | typedef bitlst edgelst; | |
585 | ||
63de6c74 | 586 | /* Target info functions. */ |
8c660648 JL |
587 | static void split_edges PROTO ((int, int, edgelst *)); |
588 | static void compute_trg_info PROTO ((int)); | |
589 | void debug_candidate PROTO ((int)); | |
590 | void debug_candidates PROTO ((int)); | |
591 | ||
592 | ||
593 | /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */ | |
594 | typedef bitset bbset; | |
595 | ||
596 | /* Number of words of the bbset. */ | |
61822835 | 597 | static int bbset_size; |
8c660648 JL |
598 | |
599 | /* Dominators array: dom[i] contains the bbset of dominators of | |
600 | bb i in the region. */ | |
61822835 | 601 | static bbset *dom; |
8c660648 | 602 | |
63de6c74 | 603 | /* bb 0 is the only region entry. */ |
8c660648 JL |
604 | #define IS_RGN_ENTRY(bb) (!bb) |
605 | ||
606 | /* Is bb_src dominated by bb_trg. */ | |
607 | #define IS_DOMINATED(bb_src, bb_trg) \ | |
608 | ( bitset_member (dom[bb_src], bb_trg, bbset_size) ) | |
609 | ||
610 | /* Probability: Prob[i] is a float in [0, 1] which is the probability | |
611 | of bb i relative to the region entry. */ | |
61822835 | 612 | static float *prob; |
8c660648 | 613 | |
63de6c74 | 614 | /* The probability of bb_src, relative to bb_trg. Note, that while the |
8c660648 JL |
615 | 'prob[bb]' is a float in [0, 1], this macro returns an integer |
616 | in [0, 100]. */ | |
617 | #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \ | |
618 | prob[bb_trg]))) | |
619 | ||
620 | /* Bit-set of edges, where bit i stands for edge i. */ | |
621 | typedef bitset edgeset; | |
622 | ||
623 | /* Number of edges in the region. */ | |
61822835 | 624 | static int rgn_nr_edges; |
8c660648 | 625 | |
63de6c74 | 626 | /* Array of size rgn_nr_edges. */ |
61822835 | 627 | static int *rgn_edges; |
8c660648 | 628 | |
63de6c74 | 629 | /* Number of words in an edgeset. */ |
61822835 | 630 | static int edgeset_size; |
8c660648 JL |
631 | |
632 | /* Mapping from each edge in the graph to its number in the rgn. */ | |
61822835 | 633 | static int *edge_to_bit; |
8c660648 JL |
634 | #define EDGE_TO_BIT(edge) (edge_to_bit[edge]) |
635 | ||
636 | /* The split edges of a source bb is different for each target | |
637 | bb. In order to compute this efficiently, the 'potential-split edges' | |
638 | are computed for each bb prior to scheduling a region. This is actually | |
639 | the split edges of each bb relative to the region entry. | |
640 | ||
641 | pot_split[bb] is the set of potential split edges of bb. */ | |
61822835 | 642 | static edgeset *pot_split; |
8c660648 JL |
643 | |
644 | /* For every bb, a set of its ancestor edges. */ | |
61822835 | 645 | static edgeset *ancestor_edges; |
8c660648 JL |
646 | |
647 | static void compute_dom_prob_ps PROTO ((int)); | |
648 | ||
649 | #define ABS_VALUE(x) (((x)<0)?(-(x)):(x)) | |
c88e8206 RH |
650 | #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (BLOCK_NUM (INSN)))) |
651 | #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (BLOCK_NUM (INSN)))) | |
652 | #define INSN_BB(INSN) (BLOCK_TO_BB (BLOCK_NUM (INSN))) | |
8c660648 | 653 | |
63de6c74 | 654 | /* Parameters affecting the decision of rank_for_schedule(). */ |
8c660648 JL |
655 | #define MIN_DIFF_PRIORITY 2 |
656 | #define MIN_PROBABILITY 40 | |
657 | #define MIN_PROB_DIFF 10 | |
658 | ||
63de6c74 | 659 | /* Speculative scheduling functions. */ |
8c660648 JL |
660 | static int check_live_1 PROTO ((int, rtx)); |
661 | static void update_live_1 PROTO ((int, rtx)); | |
5835e573 KG |
662 | static int check_live PROTO ((rtx, int)); |
663 | static void update_live PROTO ((rtx, int)); | |
8c660648 JL |
664 | static void set_spec_fed PROTO ((rtx)); |
665 | static int is_pfree PROTO ((rtx, int, int)); | |
666 | static int find_conditional_protection PROTO ((rtx, int)); | |
667 | static int is_conditionally_protected PROTO ((rtx, int, int)); | |
668 | static int may_trap_exp PROTO ((rtx, int)); | |
ac957f13 | 669 | static int haifa_classify_insn PROTO ((rtx)); |
e009aaf3 | 670 | static int is_prisky PROTO ((rtx, int, int)); |
8c660648 JL |
671 | static int is_exception_free PROTO ((rtx, int, int)); |
672 | ||
673 | static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx)); | |
674 | static void compute_block_forward_dependences PROTO ((int)); | |
675 | static void init_rgn_data_dependences PROTO ((int)); | |
676 | static void add_branch_dependences PROTO ((rtx, rtx)); | |
677 | static void compute_block_backward_dependences PROTO ((int)); | |
678 | void debug_dependencies PROTO ((void)); | |
679 | ||
680 | /* Notes handling mechanism: | |
681 | ========================= | |
682 | Generally, NOTES are saved before scheduling and restored after scheduling. | |
683 | The scheduler distinguishes between three types of notes: | |
684 | ||
685 | (1) LINE_NUMBER notes, generated and used for debugging. Here, | |
686 | before scheduling a region, a pointer to the LINE_NUMBER note is | |
687 | added to the insn following it (in save_line_notes()), and the note | |
688 | is removed (in rm_line_notes() and unlink_line_notes()). After | |
689 | scheduling the region, this pointer is used for regeneration of | |
690 | the LINE_NUMBER note (in restore_line_notes()). | |
691 | ||
692 | (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes: | |
693 | Before scheduling a region, a pointer to the note is added to the insn | |
694 | that follows or precedes it. (This happens as part of the data dependence | |
695 | computation). After scheduling an insn, the pointer contained in it is | |
696 | used for regenerating the corresponding note (in reemit_notes). | |
697 | ||
698 | (3) All other notes (e.g. INSN_DELETED): Before scheduling a block, | |
699 | these notes are put in a list (in rm_other_notes() and | |
700 | unlink_other_notes ()). After scheduling the block, these notes are | |
701 | inserted at the beginning of the block (in schedule_block()). */ | |
702 | ||
703 | static rtx unlink_other_notes PROTO ((rtx, rtx)); | |
704 | static rtx unlink_line_notes PROTO ((rtx, rtx)); | |
705 | static void rm_line_notes PROTO ((int)); | |
706 | static void save_line_notes PROTO ((int)); | |
707 | static void restore_line_notes PROTO ((int)); | |
708 | static void rm_redundant_line_notes PROTO ((void)); | |
709 | static void rm_other_notes PROTO ((rtx, rtx)); | |
710 | static rtx reemit_notes PROTO ((rtx, rtx)); | |
711 | ||
712 | static void get_block_head_tail PROTO ((int, rtx *, rtx *)); | |
49c3bb12 | 713 | static void get_bb_head_tail PROTO ((int, rtx *, rtx *)); |
8c660648 | 714 | |
c6a754f2 | 715 | static int queue_to_ready PROTO ((rtx [], int)); |
8c660648 | 716 | |
9a8b0889 | 717 | static void debug_ready_list PROTO ((rtx[], int)); |
cc4fe0e2 | 718 | static void init_target_units PROTO ((void)); |
8c660648 | 719 | static void insn_print_units PROTO ((rtx)); |
cc4fe0e2 L |
720 | static int get_visual_tbl_length PROTO ((void)); |
721 | static void init_block_visualization PROTO ((void)); | |
5f06c983 | 722 | static void print_block_visualization PROTO ((int, const char *)); |
8c660648 JL |
723 | static void visualize_scheduled_insns PROTO ((int, int)); |
724 | static void visualize_no_unit PROTO ((rtx)); | |
725 | static void visualize_stall_cycles PROTO ((int, int)); | |
726 | static void print_exp PROTO ((char *, rtx, int)); | |
727 | static void print_value PROTO ((char *, rtx, int)); | |
728 | static void print_pattern PROTO ((char *, rtx, int)); | |
729 | static void print_insn PROTO ((char *, rtx, int)); | |
730 | void debug_reg_vector PROTO ((regset)); | |
731 | ||
732 | static rtx move_insn1 PROTO ((rtx, rtx)); | |
733 | static rtx move_insn PROTO ((rtx, rtx)); | |
734 | static rtx group_leader PROTO ((rtx)); | |
735 | static int set_priorities PROTO ((int)); | |
736 | static void init_rtx_vector PROTO ((rtx **, rtx *, int, int)); | |
737 | static void schedule_region PROTO ((int)); | |
8c660648 JL |
738 | |
739 | #endif /* INSN_SCHEDULING */ | |
740 | \f | |
741 | #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X))) | |
742 | ||
8c660648 JL |
743 | /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the |
744 | LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type | |
745 | of dependence that this link represents. */ | |
746 | ||
747 | static void | |
748 | add_dependence (insn, elem, dep_type) | |
749 | rtx insn; | |
750 | rtx elem; | |
751 | enum reg_note dep_type; | |
752 | { | |
753 | rtx link, next; | |
754 | ||
755 | /* Don't depend an insn on itself. */ | |
756 | if (insn == elem) | |
757 | return; | |
758 | ||
342d9c89 JL |
759 | /* We can get a dependency on deleted insns due to optimizations in |
760 | the register allocation and reloading or due to splitting. Any | |
761 | such dependency is useless and can be ignored. */ | |
762 | if (GET_CODE (elem) == NOTE) | |
763 | return; | |
764 | ||
8c660648 JL |
765 | /* If elem is part of a sequence that must be scheduled together, then |
766 | make the dependence point to the last insn of the sequence. | |
767 | When HAVE_cc0, it is possible for NOTEs to exist between users and | |
768 | setters of the condition codes, so we must skip past notes here. | |
769 | Otherwise, NOTEs are impossible here. */ | |
770 | ||
771 | next = NEXT_INSN (elem); | |
772 | ||
773 | #ifdef HAVE_cc0 | |
774 | while (next && GET_CODE (next) == NOTE) | |
775 | next = NEXT_INSN (next); | |
776 | #endif | |
777 | ||
778 | if (next && SCHED_GROUP_P (next) | |
779 | && GET_CODE (next) != CODE_LABEL) | |
780 | { | |
781 | /* Notes will never intervene here though, so don't bother checking | |
782 | for them. */ | |
783 | /* We must reject CODE_LABELs, so that we don't get confused by one | |
784 | that has LABEL_PRESERVE_P set, which is represented by the same | |
785 | bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be | |
786 | SCHED_GROUP_P. */ | |
787 | while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next)) | |
788 | && GET_CODE (NEXT_INSN (next)) != CODE_LABEL) | |
789 | next = NEXT_INSN (next); | |
790 | ||
791 | /* Again, don't depend an insn on itself. */ | |
792 | if (insn == next) | |
793 | return; | |
794 | ||
795 | /* Make the dependence to NEXT, the last insn of the group, instead | |
796 | of the original ELEM. */ | |
797 | elem = next; | |
798 | } | |
799 | ||
800 | #ifdef INSN_SCHEDULING | |
801 | /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.) | |
802 | No need for interblock dependences with calls, since | |
803 | calls are not moved between blocks. Note: the edge where | |
804 | elem is a CALL is still required. */ | |
805 | if (GET_CODE (insn) == CALL_INSN | |
806 | && (INSN_BB (elem) != INSN_BB (insn))) | |
807 | return; | |
808 | ||
8c660648 | 809 | |
356edbd7 JL |
810 | /* If we already have a true dependency for ELEM, then we do not |
811 | need to do anything. Avoiding the list walk below can cut | |
812 | compile times dramatically for some code. */ | |
aae0390e JL |
813 | if (true_dependency_cache |
814 | && TEST_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem))) | |
356edbd7 | 815 | return; |
35c95c5a | 816 | #endif |
356edbd7 | 817 | |
8c660648 JL |
818 | /* Check that we don't already have this dependence. */ |
819 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
820 | if (XEXP (link, 0) == elem) | |
821 | { | |
822 | /* If this is a more restrictive type of dependence than the existing | |
823 | one, then change the existing dependence to this type. */ | |
824 | if ((int) dep_type < (int) REG_NOTE_KIND (link)) | |
825 | PUT_REG_NOTE_KIND (link, dep_type); | |
356edbd7 | 826 | |
35c95c5a | 827 | #ifdef INSN_SCHEDULING |
356edbd7 JL |
828 | /* If we are adding a true dependency to INSN's LOG_LINKs, then |
829 | note that in the bitmap cache of true dependency information. */ | |
aae0390e | 830 | if ((int)dep_type == 0 && true_dependency_cache) |
356edbd7 | 831 | SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)); |
35c95c5a | 832 | #endif |
8c660648 JL |
833 | return; |
834 | } | |
835 | /* Might want to check one level of transitivity to save conses. */ | |
836 | ||
ebb7b10b RH |
837 | link = alloc_INSN_LIST (elem, LOG_LINKS (insn)); |
838 | LOG_LINKS (insn) = link; | |
839 | ||
8c660648 JL |
840 | /* Insn dependency, not data dependency. */ |
841 | PUT_REG_NOTE_KIND (link, dep_type); | |
4525e228 JL |
842 | |
843 | #ifdef INSN_SCHEDULING | |
844 | /* If we are adding a true dependency to INSN's LOG_LINKs, then | |
845 | note that in the bitmap cache of true dependency information. */ | |
846 | if ((int)dep_type == 0 && true_dependency_cache) | |
847 | SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)); | |
848 | #endif | |
8c660648 JL |
849 | } |
850 | ||
c88e8206 | 851 | #ifdef HAVE_cc0 |
8c660648 JL |
852 | /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS |
853 | of INSN. Abort if not found. */ | |
854 | ||
855 | static void | |
856 | remove_dependence (insn, elem) | |
857 | rtx insn; | |
858 | rtx elem; | |
859 | { | |
ebb7b10b | 860 | rtx prev, link, next; |
8c660648 JL |
861 | int found = 0; |
862 | ||
ebb7b10b | 863 | for (prev = 0, link = LOG_LINKS (insn); link; link = next) |
8c660648 | 864 | { |
ebb7b10b | 865 | next = XEXP (link, 1); |
8c660648 JL |
866 | if (XEXP (link, 0) == elem) |
867 | { | |
868 | if (prev) | |
ebb7b10b | 869 | XEXP (prev, 1) = next; |
8c660648 | 870 | else |
ebb7b10b | 871 | LOG_LINKS (insn) = next; |
356edbd7 | 872 | |
35c95c5a | 873 | #ifdef INSN_SCHEDULING |
356edbd7 JL |
874 | /* If we are removing a true dependency from the LOG_LINKS list, |
875 | make sure to remove it from the cache too. */ | |
aae0390e | 876 | if (REG_NOTE_KIND (link) == 0 && true_dependency_cache) |
356edbd7 JL |
877 | RESET_BIT (true_dependency_cache[INSN_LUID (insn)], |
878 | INSN_LUID (elem)); | |
35c95c5a | 879 | #endif |
356edbd7 | 880 | |
5a4f6418 | 881 | free_INSN_LIST_node (link); |
ebb7b10b | 882 | |
8c660648 JL |
883 | found = 1; |
884 | } | |
6d8ccdbb JL |
885 | else |
886 | prev = link; | |
8c660648 JL |
887 | } |
888 | ||
889 | if (!found) | |
890 | abort (); | |
891 | return; | |
892 | } | |
c88e8206 | 893 | #endif /* HAVE_cc0 */ |
8c660648 JL |
894 | \f |
895 | #ifndef INSN_SCHEDULING | |
896 | void | |
897 | schedule_insns (dump_file) | |
898 | FILE *dump_file; | |
899 | { | |
900 | } | |
901 | #else | |
902 | #ifndef __GNUC__ | |
903 | #define __inline | |
904 | #endif | |
905 | ||
cbb13457 MM |
906 | #ifndef HAIFA_INLINE |
907 | #define HAIFA_INLINE __inline | |
908 | #endif | |
909 | ||
8c660648 JL |
910 | /* Computation of memory dependencies. */ |
911 | ||
912 | /* The *_insns and *_mems are paired lists. Each pending memory operation | |
913 | will have a pointer to the MEM rtx on one list and a pointer to the | |
914 | containing insn on the other list in the same place in the list. */ | |
915 | ||
916 | /* We can't use add_dependence like the old code did, because a single insn | |
917 | may have multiple memory accesses, and hence needs to be on the list | |
918 | once for each memory access. Add_dependence won't let you add an insn | |
919 | to a list more than once. */ | |
920 | ||
921 | /* An INSN_LIST containing all insns with pending read operations. */ | |
922 | static rtx pending_read_insns; | |
923 | ||
924 | /* An EXPR_LIST containing all MEM rtx's which are pending reads. */ | |
925 | static rtx pending_read_mems; | |
926 | ||
927 | /* An INSN_LIST containing all insns with pending write operations. */ | |
928 | static rtx pending_write_insns; | |
929 | ||
930 | /* An EXPR_LIST containing all MEM rtx's which are pending writes. */ | |
931 | static rtx pending_write_mems; | |
932 | ||
933 | /* Indicates the combined length of the two pending lists. We must prevent | |
934 | these lists from ever growing too large since the number of dependencies | |
935 | produced is at least O(N*N), and execution time is at least O(4*N*N), as | |
936 | a function of the length of these pending lists. */ | |
937 | ||
938 | static int pending_lists_length; | |
939 | ||
8c660648 JL |
940 | /* The last insn upon which all memory references must depend. |
941 | This is an insn which flushed the pending lists, creating a dependency | |
942 | between it and all previously pending memory references. This creates | |
943 | a barrier (or a checkpoint) which no memory reference is allowed to cross. | |
944 | ||
945 | This includes all non constant CALL_INSNs. When we do interprocedural | |
946 | alias analysis, this restriction can be relaxed. | |
947 | This may also be an INSN that writes memory if the pending lists grow | |
948 | too large. */ | |
949 | ||
950 | static rtx last_pending_memory_flush; | |
951 | ||
952 | /* The last function call we have seen. All hard regs, and, of course, | |
953 | the last function call, must depend on this. */ | |
954 | ||
955 | static rtx last_function_call; | |
956 | ||
957 | /* The LOG_LINKS field of this is a list of insns which use a pseudo register | |
958 | that does not already cross a call. We create dependencies between each | |
959 | of those insn and the next call insn, to ensure that they won't cross a call | |
960 | after scheduling is done. */ | |
961 | ||
962 | static rtx sched_before_next_call; | |
963 | ||
964 | /* Pointer to the last instruction scheduled. Used by rank_for_schedule, | |
965 | so that insns independent of the last scheduled insn will be preferred | |
966 | over dependent instructions. */ | |
967 | ||
968 | static rtx last_scheduled_insn; | |
969 | ||
970 | /* Data structures for the computation of data dependences in a regions. We | |
971 | keep one copy of each of the declared above variables for each bb in the | |
972 | region. Before analyzing the data dependences for a bb, its variables | |
973 | are initialized as a function of the variables of its predecessors. When | |
974 | the analysis for a bb completes, we save the contents of each variable X | |
975 | to a corresponding bb_X[bb] variable. For example, pending_read_insns is | |
976 | copied to bb_pending_read_insns[bb]. Another change is that few | |
977 | variables are now a list of insns rather than a single insn: | |
978 | last_pending_memory_flash, last_function_call, reg_last_sets. The | |
979 | manipulation of these variables was changed appropriately. */ | |
980 | ||
981 | static rtx **bb_reg_last_uses; | |
982 | static rtx **bb_reg_last_sets; | |
28c95eff | 983 | static rtx **bb_reg_last_clobbers; |
8c660648 JL |
984 | |
985 | static rtx *bb_pending_read_insns; | |
986 | static rtx *bb_pending_read_mems; | |
987 | static rtx *bb_pending_write_insns; | |
988 | static rtx *bb_pending_write_mems; | |
989 | static int *bb_pending_lists_length; | |
990 | ||
991 | static rtx *bb_last_pending_memory_flush; | |
992 | static rtx *bb_last_function_call; | |
993 | static rtx *bb_sched_before_next_call; | |
994 | ||
63de6c74 | 995 | /* Functions for construction of the control flow graph. */ |
8c660648 JL |
996 | |
997 | /* Return 1 if control flow graph should not be constructed, 0 otherwise. | |
168cbdf9 | 998 | |
8c660648 | 999 | We decide not to build the control flow graph if there is possibly more |
168cbdf9 JL |
1000 | than one entry to the function, if computed branches exist, of if we |
1001 | have nonlocal gotos. */ | |
8c660648 | 1002 | |
168cbdf9 | 1003 | static int |
8c660648 JL |
1004 | is_cfg_nonregular () |
1005 | { | |
1006 | int b; | |
1007 | rtx insn; | |
1008 | RTX_CODE code; | |
1009 | ||
168cbdf9 JL |
1010 | /* If we have a label that could be the target of a nonlocal goto, then |
1011 | the cfg is not well structured. */ | |
e881bb1b | 1012 | if (nonlocal_goto_handler_labels) |
168cbdf9 | 1013 | return 1; |
8c660648 | 1014 | |
168cbdf9 | 1015 | /* If we have any forced labels, then the cfg is not well structured. */ |
8c660648 | 1016 | if (forced_labels) |
168cbdf9 | 1017 | return 1; |
8c660648 | 1018 | |
4d1d8045 BS |
1019 | /* If this function has a computed jump, then we consider the cfg |
1020 | not well structured. */ | |
1021 | if (current_function_has_computed_jump) | |
1022 | return 1; | |
1023 | ||
168cbdf9 JL |
1024 | /* If we have exception handlers, then we consider the cfg not well |
1025 | structured. ?!? We should be able to handle this now that flow.c | |
1026 | computes an accurate cfg for EH. */ | |
8c660648 | 1027 | if (exception_handler_labels) |
168cbdf9 | 1028 | return 1; |
8c660648 | 1029 | |
168cbdf9 JL |
1030 | /* If we have non-jumping insns which refer to labels, then we consider |
1031 | the cfg not well structured. */ | |
63de6c74 | 1032 | /* Check for labels referred to other thn by jumps. */ |
8c660648 | 1033 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 1034 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
1035 | { |
1036 | code = GET_CODE (insn); | |
1037 | if (GET_RTX_CLASS (code) == 'i') | |
1038 | { | |
1039 | rtx note; | |
1040 | ||
1041 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1042 | if (REG_NOTE_KIND (note) == REG_LABEL) | |
168cbdf9 | 1043 | return 1; |
8c660648 JL |
1044 | } |
1045 | ||
3b413743 | 1046 | if (insn == BLOCK_END (b)) |
8c660648 JL |
1047 | break; |
1048 | } | |
1049 | ||
168cbdf9 | 1050 | /* All the tests passed. Consider the cfg well structured. */ |
8c660648 JL |
1051 | return 0; |
1052 | } | |
1053 | ||
5ece9746 JL |
1054 | /* Build the control flow graph and set nr_edges. |
1055 | ||
1056 | Instead of trying to build a cfg ourselves, we rely on flow to | |
168cbdf9 | 1057 | do it for us. Stamp out useless code (and bug) duplication. |
8c660648 | 1058 | |
168cbdf9 JL |
1059 | Return nonzero if an irregularity in the cfg is found which would |
1060 | prevent cross block scheduling. */ | |
1061 | ||
1062 | static int | |
a2e68776 JL |
1063 | build_control_flow (s_preds, s_succs, num_preds, num_succs) |
1064 | int_list_ptr *s_preds; | |
1065 | int_list_ptr *s_succs; | |
1066 | int *num_preds; | |
1067 | int *num_succs; | |
8c660648 | 1068 | { |
081f5e7e | 1069 | int i; |
5ece9746 | 1070 | int_list_ptr succ; |
168cbdf9 | 1071 | int unreachable; |
5ece9746 | 1072 | |
168cbdf9 JL |
1073 | /* Count the number of edges in the cfg. */ |
1074 | nr_edges = 0; | |
1075 | unreachable = 0; | |
1076 | for (i = 0; i < n_basic_blocks; i++) | |
1077 | { | |
1078 | nr_edges += num_succs[i]; | |
15ebe47d JL |
1079 | |
1080 | /* Unreachable loops with more than one basic block are detected | |
1081 | during the DFS traversal in find_rgns. | |
1082 | ||
1083 | Unreachable loops with a single block are detected here. This | |
1084 | test is redundant with the one in find_rgns, but it's much | |
1085 | cheaper to go ahead and catch the trivial case here. */ | |
a8afd67b JW |
1086 | if (num_preds[i] == 0 |
1087 | || (num_preds[i] == 1 && INT_LIST_VAL (s_preds[i]) == i)) | |
168cbdf9 JL |
1088 | unreachable = 1; |
1089 | } | |
1090 | ||
1091 | /* Account for entry/exit edges. */ | |
1092 | nr_edges += 2; | |
1093 | ||
3de90026 RH |
1094 | in_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); |
1095 | out_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); | |
1096 | edge_table = (haifa_edge *) xcalloc (nr_edges, sizeof (haifa_edge)); | |
168cbdf9 | 1097 | |
8c660648 JL |
1098 | nr_edges = 0; |
1099 | for (i = 0; i < n_basic_blocks; i++) | |
5ece9746 JL |
1100 | for (succ = s_succs[i]; succ; succ = succ->next) |
1101 | { | |
1102 | if (INT_LIST_VAL (succ) != EXIT_BLOCK) | |
1103 | new_edge (i, INT_LIST_VAL (succ)); | |
1104 | } | |
8c660648 | 1105 | |
63de6c74 | 1106 | /* Increment by 1, since edge 0 is unused. */ |
8c660648 JL |
1107 | nr_edges++; |
1108 | ||
168cbdf9 | 1109 | return unreachable; |
8c660648 JL |
1110 | } |
1111 | ||
1112 | ||
5ece9746 | 1113 | /* Record an edge in the control flow graph from SOURCE to TARGET. |
8c660648 | 1114 | |
5ece9746 JL |
1115 | In theory, this is redundant with the s_succs computed above, but |
1116 | we have not converted all of haifa to use information from the | |
1117 | integer lists. */ | |
8c660648 JL |
1118 | |
1119 | static void | |
1120 | new_edge (source, target) | |
1121 | int source, target; | |
1122 | { | |
1123 | int e, next_edge; | |
1124 | int curr_edge, fst_edge; | |
1125 | ||
63de6c74 | 1126 | /* Check for duplicates. */ |
8c660648 JL |
1127 | fst_edge = curr_edge = OUT_EDGES (source); |
1128 | while (curr_edge) | |
1129 | { | |
1130 | if (FROM_BLOCK (curr_edge) == source | |
1131 | && TO_BLOCK (curr_edge) == target) | |
1132 | { | |
1133 | return; | |
1134 | } | |
1135 | ||
1136 | curr_edge = NEXT_OUT (curr_edge); | |
1137 | ||
1138 | if (fst_edge == curr_edge) | |
1139 | break; | |
1140 | } | |
1141 | ||
1142 | e = ++nr_edges; | |
1143 | ||
1144 | FROM_BLOCK (e) = source; | |
1145 | TO_BLOCK (e) = target; | |
1146 | ||
1147 | if (OUT_EDGES (source)) | |
1148 | { | |
1149 | next_edge = NEXT_OUT (OUT_EDGES (source)); | |
1150 | NEXT_OUT (OUT_EDGES (source)) = e; | |
1151 | NEXT_OUT (e) = next_edge; | |
1152 | } | |
1153 | else | |
1154 | { | |
1155 | OUT_EDGES (source) = e; | |
1156 | NEXT_OUT (e) = e; | |
1157 | } | |
1158 | ||
1159 | if (IN_EDGES (target)) | |
1160 | { | |
1161 | next_edge = NEXT_IN (IN_EDGES (target)); | |
1162 | NEXT_IN (IN_EDGES (target)) = e; | |
1163 | NEXT_IN (e) = next_edge; | |
1164 | } | |
1165 | else | |
1166 | { | |
1167 | IN_EDGES (target) = e; | |
1168 | NEXT_IN (e) = e; | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | ||
1173 | /* BITSET macros for operations on the control flow graph. */ | |
1174 | ||
63de6c74 | 1175 | /* Compute bitwise union of two bitsets. */ |
8c660648 JL |
1176 | #define BITSET_UNION(set1, set2, len) \ |
1177 | do { register bitset tp = set1, sp = set2; \ | |
1178 | register int i; \ | |
1179 | for (i = 0; i < len; i++) \ | |
1180 | *(tp++) |= *(sp++); } while (0) | |
1181 | ||
63de6c74 | 1182 | /* Compute bitwise intersection of two bitsets. */ |
8c660648 JL |
1183 | #define BITSET_INTER(set1, set2, len) \ |
1184 | do { register bitset tp = set1, sp = set2; \ | |
1185 | register int i; \ | |
1186 | for (i = 0; i < len; i++) \ | |
1187 | *(tp++) &= *(sp++); } while (0) | |
1188 | ||
63de6c74 | 1189 | /* Compute bitwise difference of two bitsets. */ |
8c660648 JL |
1190 | #define BITSET_DIFFER(set1, set2, len) \ |
1191 | do { register bitset tp = set1, sp = set2; \ | |
1192 | register int i; \ | |
1193 | for (i = 0; i < len; i++) \ | |
1194 | *(tp++) &= ~*(sp++); } while (0) | |
1195 | ||
63de6c74 | 1196 | /* Inverts every bit of bitset 'set'. */ |
8c660648 JL |
1197 | #define BITSET_INVERT(set, len) \ |
1198 | do { register bitset tmpset = set; \ | |
1199 | register int i; \ | |
1200 | for (i = 0; i < len; i++, tmpset++) \ | |
1201 | *tmpset = ~*tmpset; } while (0) | |
1202 | ||
1203 | /* Turn on the index'th bit in bitset set. */ | |
1204 | #define BITSET_ADD(set, index, len) \ | |
1205 | { \ | |
1206 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1207 | abort (); \ | |
1208 | else \ | |
1209 | set[index/HOST_BITS_PER_WIDE_INT] |= \ | |
1210 | 1 << (index % HOST_BITS_PER_WIDE_INT); \ | |
1211 | } | |
1212 | ||
1213 | /* Turn off the index'th bit in set. */ | |
1214 | #define BITSET_REMOVE(set, index, len) \ | |
1215 | { \ | |
1216 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1217 | abort (); \ | |
1218 | else \ | |
1219 | set[index/HOST_BITS_PER_WIDE_INT] &= \ | |
1220 | ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \ | |
1221 | } | |
1222 | ||
1223 | ||
63de6c74 | 1224 | /* Check if the index'th bit in bitset set is on. */ |
8c660648 JL |
1225 | |
1226 | static char | |
1227 | bitset_member (set, index, len) | |
1228 | bitset set; | |
1229 | int index, len; | |
1230 | { | |
1231 | if (index >= HOST_BITS_PER_WIDE_INT * len) | |
1232 | abort (); | |
1233 | return (set[index / HOST_BITS_PER_WIDE_INT] & | |
1234 | 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0; | |
1235 | } | |
1236 | ||
1237 | ||
1238 | /* Translate a bit-set SET to a list BL of the bit-set members. */ | |
1239 | ||
1240 | static void | |
1241 | extract_bitlst (set, len, bl) | |
1242 | bitset set; | |
1243 | int len; | |
1244 | bitlst *bl; | |
1245 | { | |
1246 | int i, j, offset; | |
1247 | unsigned HOST_WIDE_INT word; | |
1248 | ||
63de6c74 | 1249 | /* bblst table space is reused in each call to extract_bitlst. */ |
8c660648 JL |
1250 | bitlst_table_last = 0; |
1251 | ||
1252 | bl->first_member = &bitlst_table[bitlst_table_last]; | |
1253 | bl->nr_members = 0; | |
1254 | ||
1255 | for (i = 0; i < len; i++) | |
1256 | { | |
1257 | word = set[i]; | |
1258 | offset = i * HOST_BITS_PER_WIDE_INT; | |
1259 | for (j = 0; word; j++) | |
1260 | { | |
1261 | if (word & 1) | |
1262 | { | |
1263 | bitlst_table[bitlst_table_last++] = offset; | |
1264 | (bl->nr_members)++; | |
1265 | } | |
1266 | word >>= 1; | |
1267 | ++offset; | |
1268 | } | |
1269 | } | |
1270 | ||
1271 | } | |
1272 | ||
1273 | ||
63de6c74 | 1274 | /* Functions for the construction of regions. */ |
8c660648 JL |
1275 | |
1276 | /* Print the regions, for debugging purposes. Callable from debugger. */ | |
1277 | ||
1278 | void | |
1279 | debug_regions () | |
1280 | { | |
1281 | int rgn, bb; | |
1282 | ||
1283 | fprintf (dump, "\n;; ------------ REGIONS ----------\n\n"); | |
1284 | for (rgn = 0; rgn < nr_regions; rgn++) | |
1285 | { | |
1286 | fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn, | |
1287 | rgn_table[rgn].rgn_nr_blocks); | |
1288 | fprintf (dump, ";;\tbb/block: "); | |
1289 | ||
1290 | for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++) | |
1291 | { | |
1292 | current_blocks = RGN_BLOCKS (rgn); | |
1293 | ||
1294 | if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb))) | |
1295 | abort (); | |
1296 | ||
1297 | fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb)); | |
1298 | } | |
1299 | ||
1300 | fprintf (dump, "\n\n"); | |
1301 | } | |
1302 | } | |
1303 | ||
1304 | ||
1305 | /* Build a single block region for each basic block in the function. | |
1306 | This allows for using the same code for interblock and basic block | |
1307 | scheduling. */ | |
1308 | ||
1309 | static void | |
1310 | find_single_block_region () | |
1311 | { | |
1312 | int i; | |
1313 | ||
1314 | for (i = 0; i < n_basic_blocks; i++) | |
1315 | { | |
1316 | rgn_bb_table[i] = i; | |
1317 | RGN_NR_BLOCKS (i) = 1; | |
1318 | RGN_BLOCKS (i) = i; | |
1319 | CONTAINING_RGN (i) = i; | |
1320 | BLOCK_TO_BB (i) = 0; | |
1321 | } | |
1322 | nr_regions = n_basic_blocks; | |
1323 | } | |
1324 | ||
1325 | ||
1326 | /* Update number of blocks and the estimate for number of insns | |
1327 | in the region. Return 1 if the region is "too large" for interblock | |
1328 | scheduling (compile time considerations), otherwise return 0. */ | |
1329 | ||
1330 | static int | |
1331 | too_large (block, num_bbs, num_insns) | |
1332 | int block, *num_bbs, *num_insns; | |
1333 | { | |
1334 | (*num_bbs)++; | |
3b413743 RH |
1335 | (*num_insns) += (INSN_LUID (BLOCK_END (block)) - |
1336 | INSN_LUID (BLOCK_HEAD (block))); | |
cc132865 | 1337 | if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS)) |
8c660648 JL |
1338 | return 1; |
1339 | else | |
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | ||
1344 | /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk] | |
1345 | is still an inner loop. Put in max_hdr[blk] the header of the most inner | |
1346 | loop containing blk. */ | |
1347 | #define UPDATE_LOOP_RELATIONS(blk, hdr) \ | |
1348 | { \ | |
1349 | if (max_hdr[blk] == -1) \ | |
1350 | max_hdr[blk] = hdr; \ | |
1351 | else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \ | |
a2e68776 | 1352 | RESET_BIT (inner, hdr); \ |
8c660648 JL |
1353 | else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \ |
1354 | { \ | |
a2e68776 | 1355 | RESET_BIT (inner,max_hdr[blk]); \ |
8c660648 JL |
1356 | max_hdr[blk] = hdr; \ |
1357 | } \ | |
1358 | } | |
1359 | ||
1360 | ||
a2e68776 JL |
1361 | /* Find regions for interblock scheduling. |
1362 | ||
1363 | A region for scheduling can be: | |
1364 | ||
1365 | * A loop-free procedure, or | |
1366 | ||
1367 | * A reducible inner loop, or | |
1368 | ||
1369 | * A basic block not contained in any other region. | |
1370 | ||
1371 | ||
1372 | ?!? In theory we could build other regions based on extended basic | |
1373 | blocks or reverse extended basic blocks. Is it worth the trouble? | |
1374 | ||
1375 | Loop blocks that form a region are put into the region's block list | |
1376 | in topological order. | |
1377 | ||
1378 | This procedure stores its results into the following global (ick) variables | |
1379 | ||
1380 | * rgn_nr | |
1381 | * rgn_table | |
1382 | * rgn_bb_table | |
1383 | * block_to_bb | |
1384 | * containing region | |
1385 | ||
1386 | ||
1387 | We use dominator relationships to avoid making regions out of non-reducible | |
1388 | loops. | |
8c660648 | 1389 | |
a2e68776 JL |
1390 | This procedure needs to be converted to work on pred/succ lists instead |
1391 | of edge tables. That would simplify it somewhat. */ | |
8c660648 JL |
1392 | |
1393 | static void | |
a2e68776 JL |
1394 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom) |
1395 | int_list_ptr *s_preds; | |
1396 | int_list_ptr *s_succs; | |
1397 | int *num_preds; | |
1398 | int *num_succs; | |
1399 | sbitmap *dom; | |
8c660648 | 1400 | { |
98903742 | 1401 | int *max_hdr, *dfs_nr, *stack, *degree; |
a2e68776 | 1402 | char no_loops = 1; |
487a6e06 | 1403 | int node, child, loop_head, i, head, tail; |
8c660648 | 1404 | int count = 0, sp, idx = 0, current_edge = out_edges[0]; |
15ebe47d | 1405 | int num_bbs, num_insns, unreachable; |
8c660648 | 1406 | int too_large_failure; |
8c660648 | 1407 | |
a2e68776 JL |
1408 | /* Note if an edge has been passed. */ |
1409 | sbitmap passed; | |
1410 | ||
1411 | /* Note if a block is a natural loop header. */ | |
1412 | sbitmap header; | |
1413 | ||
1414 | /* Note if a block is an natural inner loop header. */ | |
1415 | sbitmap inner; | |
1416 | ||
1417 | /* Note if a block is in the block queue. */ | |
1418 | sbitmap in_queue; | |
1419 | ||
cc132865 JL |
1420 | /* Note if a block is in the block queue. */ |
1421 | sbitmap in_stack; | |
1422 | ||
a2e68776 JL |
1423 | /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops |
1424 | and a mapping from block to its loop header (if the block is contained | |
1425 | in a loop, else -1). | |
1426 | ||
1427 | Store results in HEADER, INNER, and MAX_HDR respectively, these will | |
1428 | be used as inputs to the second traversal. | |
1429 | ||
1430 | STACK, SP and DFS_NR are only used during the first traversal. */ | |
1431 | ||
1432 | /* Allocate and initialize variables for the first traversal. */ | |
98903742 MM |
1433 | max_hdr = (int *) xmalloc (n_basic_blocks * sizeof (int)); |
1434 | dfs_nr = (int *) xcalloc (n_basic_blocks, sizeof (int)); | |
1435 | stack = (int *) xmalloc (nr_edges * sizeof (int)); | |
8c660648 | 1436 | |
a2e68776 JL |
1437 | inner = sbitmap_alloc (n_basic_blocks); |
1438 | sbitmap_ones (inner); | |
1439 | ||
1440 | header = sbitmap_alloc (n_basic_blocks); | |
1441 | sbitmap_zero (header); | |
8c660648 | 1442 | |
a2e68776 JL |
1443 | passed = sbitmap_alloc (nr_edges); |
1444 | sbitmap_zero (passed); | |
1445 | ||
1446 | in_queue = sbitmap_alloc (n_basic_blocks); | |
1447 | sbitmap_zero (in_queue); | |
8c660648 | 1448 | |
cc132865 JL |
1449 | in_stack = sbitmap_alloc (n_basic_blocks); |
1450 | sbitmap_zero (in_stack); | |
1451 | ||
8c660648 | 1452 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 | 1453 | max_hdr[i] = -1; |
8c660648 | 1454 | |
a2e68776 | 1455 | /* DFS traversal to find inner loops in the cfg. */ |
8c660648 | 1456 | |
8c660648 JL |
1457 | sp = -1; |
1458 | while (1) | |
1459 | { | |
a2e68776 | 1460 | if (current_edge == 0 || TEST_BIT (passed, current_edge)) |
8c660648 | 1461 | { |
a2e68776 | 1462 | /* We have reached a leaf node or a node that was already |
cc132865 | 1463 | processed. Pop edges off the stack until we find |
a2e68776 JL |
1464 | an edge that has not yet been processed. */ |
1465 | while (sp >= 0 | |
1466 | && (current_edge == 0 || TEST_BIT (passed, current_edge))) | |
8c660648 | 1467 | { |
a2e68776 | 1468 | /* Pop entry off the stack. */ |
8c660648 JL |
1469 | current_edge = stack[sp--]; |
1470 | node = FROM_BLOCK (current_edge); | |
1471 | child = TO_BLOCK (current_edge); | |
cc132865 JL |
1472 | RESET_BIT (in_stack, child); |
1473 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) | |
8c660648 JL |
1474 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
1475 | current_edge = NEXT_OUT (current_edge); | |
1476 | } | |
1477 | ||
a2e68776 JL |
1478 | /* See if have finished the DFS tree traversal. */ |
1479 | if (sp < 0 && TEST_BIT (passed, current_edge)) | |
8c660648 | 1480 | break; |
a2e68776 JL |
1481 | |
1482 | /* Nope, continue the traversal with the popped node. */ | |
8c660648 JL |
1483 | continue; |
1484 | } | |
1485 | ||
a2e68776 | 1486 | /* Process a node. */ |
8c660648 | 1487 | node = FROM_BLOCK (current_edge); |
8c660648 | 1488 | child = TO_BLOCK (current_edge); |
cc132865 | 1489 | SET_BIT (in_stack, node); |
a2e68776 | 1490 | dfs_nr[node] = ++count; |
8c660648 | 1491 | |
cc132865 JL |
1492 | /* If the successor is in the stack, then we've found a loop. |
1493 | Mark the loop, if it is not a natural loop, then it will | |
1494 | be rejected during the second traversal. */ | |
1495 | if (TEST_BIT (in_stack, child)) | |
8c660648 JL |
1496 | { |
1497 | no_loops = 0; | |
a2e68776 | 1498 | SET_BIT (header, child); |
8c660648 | 1499 | UPDATE_LOOP_RELATIONS (node, child); |
a2e68776 | 1500 | SET_BIT (passed, current_edge); |
8c660648 JL |
1501 | current_edge = NEXT_OUT (current_edge); |
1502 | continue; | |
1503 | } | |
1504 | ||
a2e68776 JL |
1505 | /* If the child was already visited, then there is no need to visit |
1506 | it again. Just update the loop relationships and restart | |
1507 | with a new edge. */ | |
8c660648 JL |
1508 | if (dfs_nr[child]) |
1509 | { | |
cc132865 | 1510 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) |
8c660648 | 1511 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
a2e68776 | 1512 | SET_BIT (passed, current_edge); |
8c660648 JL |
1513 | current_edge = NEXT_OUT (current_edge); |
1514 | continue; | |
1515 | } | |
1516 | ||
a2e68776 | 1517 | /* Push an entry on the stack and continue DFS traversal. */ |
8c660648 | 1518 | stack[++sp] = current_edge; |
a2e68776 | 1519 | SET_BIT (passed, current_edge); |
8c660648 | 1520 | current_edge = OUT_EDGES (child); |
50f71e6f JL |
1521 | |
1522 | /* This is temporary until haifa is converted to use rth's new | |
1523 | cfg routines which have true entry/exit blocks and the | |
1524 | appropriate edges from/to those blocks. | |
1525 | ||
1526 | Generally we update dfs_nr for a node when we process its | |
1527 | out edge. However, if the node has no out edge then we will | |
1528 | not set dfs_nr for that node. This can confuse the scheduler | |
1529 | into thinking that we have unreachable blocks, which in turn | |
1530 | disables cross block scheduling. | |
1531 | ||
1532 | So, if we have a node with no out edges, go ahead and mark it | |
1533 | as reachable now. */ | |
1534 | if (current_edge == 0) | |
1535 | dfs_nr[child] = ++count; | |
a2e68776 | 1536 | } |
8c660648 | 1537 | |
15ebe47d JL |
1538 | /* Another check for unreachable blocks. The earlier test in |
1539 | is_cfg_nonregular only finds unreachable blocks that do not | |
1540 | form a loop. | |
a2e68776 | 1541 | |
15ebe47d JL |
1542 | The DFS traversal will mark every block that is reachable from |
1543 | the entry node by placing a nonzero value in dfs_nr. Thus if | |
1544 | dfs_nr is zero for any block, then it must be unreachable. */ | |
1545 | unreachable = 0; | |
1546 | for (i = 0; i < n_basic_blocks; i++) | |
1547 | if (dfs_nr[i] == 0) | |
1548 | { | |
1549 | unreachable = 1; | |
1550 | break; | |
1551 | } | |
a2e68776 JL |
1552 | |
1553 | /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array | |
1554 | to hold degree counts. */ | |
1555 | degree = dfs_nr; | |
8c660648 | 1556 | |
63de6c74 | 1557 | /* Compute the in-degree of every block in the graph. */ |
8c660648 | 1558 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 JL |
1559 | degree[i] = num_preds[i]; |
1560 | ||
15ebe47d JL |
1561 | /* Do not perform region scheduling if there are any unreachable |
1562 | blocks. */ | |
1563 | if (!unreachable) | |
8c660648 | 1564 | { |
98903742 MM |
1565 | int *queue; |
1566 | ||
15ebe47d JL |
1567 | if (no_loops) |
1568 | SET_BIT (header, 0); | |
8c660648 | 1569 | |
15ebe47d JL |
1570 | /* Second travsersal:find reducible inner loops and topologically sort |
1571 | block of each region. */ | |
8c660648 | 1572 | |
98903742 | 1573 | queue = (int *) xmalloc (n_basic_blocks * sizeof (int)); |
8c660648 | 1574 | |
cc132865 JL |
1575 | /* Find blocks which are inner loop headers. We still have non-reducible |
1576 | loops to consider at this point. */ | |
15ebe47d JL |
1577 | for (i = 0; i < n_basic_blocks; i++) |
1578 | { | |
1579 | if (TEST_BIT (header, i) && TEST_BIT (inner, i)) | |
1580 | { | |
1581 | int_list_ptr ps; | |
cc132865 JL |
1582 | int j; |
1583 | ||
1584 | /* Now check that the loop is reducible. We do this separate | |
1585 | from finding inner loops so that we do not find a reducible | |
63de6c74 | 1586 | loop which contains an inner non-reducible loop. |
cc132865 | 1587 | |
63de6c74 | 1588 | A simple way to find reducible/natural loops is to verify |
cc132865 JL |
1589 | that each block in the loop is dominated by the loop |
1590 | header. | |
1591 | ||
1592 | If there exists a block that is not dominated by the loop | |
1593 | header, then the block is reachable from outside the loop | |
1594 | and thus the loop is not a natural loop. */ | |
1595 | for (j = 0; j < n_basic_blocks; j++) | |
1596 | { | |
1597 | /* First identify blocks in the loop, except for the loop | |
1598 | entry block. */ | |
1599 | if (i == max_hdr[j] && i != j) | |
1600 | { | |
1601 | /* Now verify that the block is dominated by the loop | |
1602 | header. */ | |
1603 | if (!TEST_BIT (dom[j], i)) | |
1604 | break; | |
1605 | } | |
1606 | } | |
1607 | ||
63de6c74 MH |
1608 | /* If we exited the loop early, then I is the header of |
1609 | a non-reducible loop and we should quit processing it | |
1610 | now. */ | |
cc132865 JL |
1611 | if (j != n_basic_blocks) |
1612 | continue; | |
8c660648 | 1613 | |
cc132865 JL |
1614 | /* I is a header of an inner loop, or block 0 in a subroutine |
1615 | with no loops at all. */ | |
15ebe47d JL |
1616 | head = tail = -1; |
1617 | too_large_failure = 0; | |
1618 | loop_head = max_hdr[i]; | |
8c660648 | 1619 | |
15ebe47d | 1620 | /* Decrease degree of all I's successors for topological |
a59bfd78 | 1621 | ordering. */ |
15ebe47d JL |
1622 | for (ps = s_succs[i]; ps; ps = ps->next) |
1623 | if (INT_LIST_VAL (ps) != EXIT_BLOCK | |
1624 | && INT_LIST_VAL (ps) != ENTRY_BLOCK) | |
cc132865 | 1625 | --degree[INT_LIST_VAL(ps)]; |
a2e68776 | 1626 | |
15ebe47d JL |
1627 | /* Estimate # insns, and count # blocks in the region. */ |
1628 | num_bbs = 1; | |
3b413743 RH |
1629 | num_insns = (INSN_LUID (BLOCK_END (i)) |
1630 | - INSN_LUID (BLOCK_HEAD (i))); | |
8c660648 | 1631 | |
15ebe47d | 1632 | |
63de6c74 | 1633 | /* Find all loop latches (blocks with back edges to the loop |
15ebe47d JL |
1634 | header) or all the leaf blocks in the cfg has no loops. |
1635 | ||
1636 | Place those blocks into the queue. */ | |
1637 | if (no_loops) | |
1638 | { | |
1639 | for (j = 0; j < n_basic_blocks; j++) | |
1640 | /* Leaf nodes have only a single successor which must | |
1641 | be EXIT_BLOCK. */ | |
1642 | if (num_succs[j] == 1 | |
1643 | && INT_LIST_VAL (s_succs[j]) == EXIT_BLOCK) | |
8c660648 | 1644 | { |
15ebe47d JL |
1645 | queue[++tail] = j; |
1646 | SET_BIT (in_queue, j); | |
1647 | ||
1648 | if (too_large (j, &num_bbs, &num_insns)) | |
1649 | { | |
1650 | too_large_failure = 1; | |
1651 | break; | |
1652 | } | |
8c660648 | 1653 | } |
15ebe47d JL |
1654 | } |
1655 | else | |
8c660648 | 1656 | { |
15ebe47d | 1657 | int_list_ptr ps; |
a2e68776 | 1658 | |
15ebe47d | 1659 | for (ps = s_preds[i]; ps; ps = ps->next) |
8c660648 | 1660 | { |
15ebe47d | 1661 | node = INT_LIST_VAL (ps); |
8c660648 | 1662 | |
15ebe47d JL |
1663 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK) |
1664 | continue; | |
1665 | ||
1666 | if (max_hdr[node] == loop_head && node != i) | |
8c660648 | 1667 | { |
15ebe47d JL |
1668 | /* This is a loop latch. */ |
1669 | queue[++tail] = node; | |
1670 | SET_BIT (in_queue, node); | |
1671 | ||
1672 | if (too_large (node, &num_bbs, &num_insns)) | |
1673 | { | |
1674 | too_large_failure = 1; | |
1675 | break; | |
1676 | } | |
8c660648 | 1677 | } |
15ebe47d | 1678 | |
8c660648 | 1679 | } |
8c660648 | 1680 | } |
8c660648 | 1681 | |
15ebe47d | 1682 | /* Now add all the blocks in the loop to the queue. |
a2e68776 JL |
1683 | |
1684 | We know the loop is a natural loop; however the algorithm | |
1685 | above will not always mark certain blocks as being in the | |
1686 | loop. Consider: | |
1687 | node children | |
1688 | a b,c | |
1689 | b c | |
1690 | c a,d | |
1691 | d b | |
1692 | ||
1693 | ||
1694 | The algorithm in the DFS traversal may not mark B & D as part | |
1695 | of the loop (ie they will not have max_hdr set to A). | |
1696 | ||
1697 | We know they can not be loop latches (else they would have | |
1698 | had max_hdr set since they'd have a backedge to a dominator | |
1699 | block). So we don't need them on the initial queue. | |
1700 | ||
1701 | We know they are part of the loop because they are dominated | |
1702 | by the loop header and can be reached by a backwards walk of | |
1703 | the edges starting with nodes on the initial queue. | |
1704 | ||
1705 | It is safe and desirable to include those nodes in the | |
1706 | loop/scheduling region. To do so we would need to decrease | |
1707 | the degree of a node if it is the target of a backedge | |
1708 | within the loop itself as the node is placed in the queue. | |
1709 | ||
1710 | We do not do this because I'm not sure that the actual | |
1711 | scheduling code will properly handle this case. ?!? */ | |
1712 | ||
15ebe47d | 1713 | while (head < tail && !too_large_failure) |
8c660648 | 1714 | { |
15ebe47d JL |
1715 | int_list_ptr ps; |
1716 | child = queue[++head]; | |
8c660648 | 1717 | |
15ebe47d | 1718 | for (ps = s_preds[child]; ps; ps = ps->next) |
8c660648 | 1719 | { |
15ebe47d | 1720 | node = INT_LIST_VAL (ps); |
8c660648 | 1721 | |
15ebe47d JL |
1722 | /* See discussion above about nodes not marked as in |
1723 | this loop during the initial DFS traversal. */ | |
1724 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK | |
1725 | || max_hdr[node] != loop_head) | |
8c660648 | 1726 | { |
15ebe47d | 1727 | tail = -1; |
8c660648 JL |
1728 | break; |
1729 | } | |
15ebe47d JL |
1730 | else if (!TEST_BIT (in_queue, node) && node != i) |
1731 | { | |
1732 | queue[++tail] = node; | |
1733 | SET_BIT (in_queue, node); | |
1734 | ||
1735 | if (too_large (node, &num_bbs, &num_insns)) | |
1736 | { | |
1737 | too_large_failure = 1; | |
1738 | break; | |
1739 | } | |
1740 | } | |
8c660648 | 1741 | } |
8c660648 | 1742 | } |
8c660648 | 1743 | |
15ebe47d JL |
1744 | if (tail >= 0 && !too_large_failure) |
1745 | { | |
1746 | /* Place the loop header into list of region blocks. */ | |
1747 | degree[i] = -1; | |
1748 | rgn_bb_table[idx] = i; | |
1749 | RGN_NR_BLOCKS (nr_regions) = num_bbs; | |
1750 | RGN_BLOCKS (nr_regions) = idx++; | |
1751 | CONTAINING_RGN (i) = nr_regions; | |
1752 | BLOCK_TO_BB (i) = count = 0; | |
1753 | ||
63de6c74 MH |
1754 | /* Remove blocks from queue[] when their in degree |
1755 | becomes zero. Repeat until no blocks are left on the | |
1756 | list. This produces a topological list of blocks in | |
1757 | the region. */ | |
15ebe47d | 1758 | while (tail >= 0) |
8c660648 | 1759 | { |
15ebe47d JL |
1760 | int_list_ptr ps; |
1761 | ||
1762 | if (head < 0) | |
1763 | head = tail; | |
1764 | child = queue[head]; | |
1765 | if (degree[child] == 0) | |
1766 | { | |
1767 | degree[child] = -1; | |
1768 | rgn_bb_table[idx++] = child; | |
1769 | BLOCK_TO_BB (child) = ++count; | |
1770 | CONTAINING_RGN (child) = nr_regions; | |
1771 | queue[head] = queue[tail--]; | |
1772 | ||
1773 | for (ps = s_succs[child]; ps; ps = ps->next) | |
1774 | if (INT_LIST_VAL (ps) != ENTRY_BLOCK | |
1775 | && INT_LIST_VAL (ps) != EXIT_BLOCK) | |
1776 | --degree[INT_LIST_VAL (ps)]; | |
1777 | } | |
1778 | else | |
1779 | --head; | |
8c660648 | 1780 | } |
15ebe47d | 1781 | ++nr_regions; |
8c660648 | 1782 | } |
8c660648 JL |
1783 | } |
1784 | } | |
98903742 | 1785 | free (queue); |
8c660648 JL |
1786 | } |
1787 | ||
a2e68776 JL |
1788 | /* Any block that did not end up in a region is placed into a region |
1789 | by itself. */ | |
8c660648 JL |
1790 | for (i = 0; i < n_basic_blocks; i++) |
1791 | if (degree[i] >= 0) | |
1792 | { | |
1793 | rgn_bb_table[idx] = i; | |
1794 | RGN_NR_BLOCKS (nr_regions) = 1; | |
1795 | RGN_BLOCKS (nr_regions) = idx++; | |
1796 | CONTAINING_RGN (i) = nr_regions++; | |
1797 | BLOCK_TO_BB (i) = 0; | |
1798 | } | |
1799 | ||
98903742 MM |
1800 | free (max_hdr); |
1801 | free (dfs_nr); | |
1802 | free (stack); | |
a2e68776 JL |
1803 | free (passed); |
1804 | free (header); | |
1805 | free (inner); | |
1806 | free (in_queue); | |
cc132865 | 1807 | free (in_stack); |
a2e68776 | 1808 | } |
8c660648 JL |
1809 | |
1810 | ||
63de6c74 | 1811 | /* Functions for regions scheduling information. */ |
8c660648 JL |
1812 | |
1813 | /* Compute dominators, probability, and potential-split-edges of bb. | |
1814 | Assume that these values were already computed for bb's predecessors. */ | |
1815 | ||
1816 | static void | |
1817 | compute_dom_prob_ps (bb) | |
1818 | int bb; | |
1819 | { | |
1820 | int nxt_in_edge, fst_in_edge, pred; | |
1821 | int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges; | |
1822 | ||
1823 | prob[bb] = 0.0; | |
1824 | if (IS_RGN_ENTRY (bb)) | |
1825 | { | |
1826 | BITSET_ADD (dom[bb], 0, bbset_size); | |
1827 | prob[bb] = 1.0; | |
1828 | return; | |
1829 | } | |
1830 | ||
1831 | fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb)); | |
1832 | ||
63de6c74 | 1833 | /* Intialize dom[bb] to '111..1'. */ |
8c660648 JL |
1834 | BITSET_INVERT (dom[bb], bbset_size); |
1835 | ||
1836 | do | |
1837 | { | |
1838 | pred = FROM_BLOCK (nxt_in_edge); | |
1839 | BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size); | |
1840 | ||
1841 | BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)], | |
1842 | edgeset_size); | |
1843 | ||
1844 | BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size); | |
1845 | ||
1846 | nr_out_edges = 1; | |
1847 | nr_rgn_out_edges = 0; | |
1848 | fst_out_edge = OUT_EDGES (pred); | |
1849 | nxt_out_edge = NEXT_OUT (fst_out_edge); | |
1850 | BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)], | |
1851 | edgeset_size); | |
1852 | ||
1853 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size); | |
1854 | ||
63de6c74 | 1855 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1856 | if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) != |
1857 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1858 | ++nr_rgn_out_edges; | |
1859 | ||
1860 | while (fst_out_edge != nxt_out_edge) | |
1861 | { | |
1862 | ++nr_out_edges; | |
63de6c74 | 1863 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1864 | if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) != |
1865 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1866 | ++nr_rgn_out_edges; | |
1867 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size); | |
1868 | nxt_out_edge = NEXT_OUT (nxt_out_edge); | |
1869 | ||
1870 | } | |
1871 | ||
63de6c74 MH |
1872 | /* Now nr_rgn_out_edges is the number of region-exit edges from |
1873 | pred, and nr_out_edges will be the number of pred out edges | |
1874 | not leaving the region. */ | |
8c660648 JL |
1875 | nr_out_edges -= nr_rgn_out_edges; |
1876 | if (nr_rgn_out_edges > 0) | |
1877 | prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1878 | else | |
1879 | prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1880 | nxt_in_edge = NEXT_IN (nxt_in_edge); | |
1881 | } | |
1882 | while (fst_in_edge != nxt_in_edge); | |
1883 | ||
1884 | BITSET_ADD (dom[bb], bb, bbset_size); | |
1885 | BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size); | |
1886 | ||
1887 | if (sched_verbose >= 2) | |
1888 | fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb])); | |
1889 | } /* compute_dom_prob_ps */ | |
1890 | ||
63de6c74 | 1891 | /* Functions for target info. */ |
8c660648 JL |
1892 | |
1893 | /* Compute in BL the list of split-edges of bb_src relatively to bb_trg. | |
1894 | Note that bb_trg dominates bb_src. */ | |
1895 | ||
1896 | static void | |
1897 | split_edges (bb_src, bb_trg, bl) | |
1898 | int bb_src; | |
1899 | int bb_trg; | |
1900 | edgelst *bl; | |
1901 | { | |
1902 | int es = edgeset_size; | |
98903742 | 1903 | edgeset src = (edgeset) xmalloc (es * sizeof (HOST_WIDE_INT)); |
8c660648 JL |
1904 | |
1905 | while (es--) | |
1906 | src[es] = (pot_split[bb_src])[es]; | |
1907 | BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size); | |
1908 | extract_bitlst (src, edgeset_size, bl); | |
98903742 | 1909 | free (src); |
8c660648 JL |
1910 | } |
1911 | ||
1912 | ||
1913 | /* Find the valid candidate-source-blocks for the target block TRG, compute | |
1914 | their probability, and check if they are speculative or not. | |
1915 | For speculative sources, compute their update-blocks and split-blocks. */ | |
1916 | ||
1917 | static void | |
1918 | compute_trg_info (trg) | |
1919 | int trg; | |
1920 | { | |
1921 | register candidate *sp; | |
1922 | edgelst el; | |
1923 | int check_block, update_idx; | |
1924 | int i, j, k, fst_edge, nxt_edge; | |
1925 | ||
63de6c74 | 1926 | /* Define some of the fields for the target bb as well. */ |
8c660648 JL |
1927 | sp = candidate_table + trg; |
1928 | sp->is_valid = 1; | |
1929 | sp->is_speculative = 0; | |
1930 | sp->src_prob = 100; | |
1931 | ||
1932 | for (i = trg + 1; i < current_nr_blocks; i++) | |
1933 | { | |
1934 | sp = candidate_table + i; | |
1935 | ||
1936 | sp->is_valid = IS_DOMINATED (i, trg); | |
1937 | if (sp->is_valid) | |
1938 | { | |
1939 | sp->src_prob = GET_SRC_PROB (i, trg); | |
1940 | sp->is_valid = (sp->src_prob >= MIN_PROBABILITY); | |
1941 | } | |
1942 | ||
1943 | if (sp->is_valid) | |
1944 | { | |
1945 | split_edges (i, trg, &el); | |
1946 | sp->is_speculative = (el.nr_members) ? 1 : 0; | |
1947 | if (sp->is_speculative && !flag_schedule_speculative) | |
1948 | sp->is_valid = 0; | |
1949 | } | |
1950 | ||
1951 | if (sp->is_valid) | |
1952 | { | |
1953 | sp->split_bbs.first_member = &bblst_table[bblst_last]; | |
1954 | sp->split_bbs.nr_members = el.nr_members; | |
1955 | for (j = 0; j < el.nr_members; bblst_last++, j++) | |
1956 | bblst_table[bblst_last] = | |
1957 | TO_BLOCK (rgn_edges[el.first_member[j]]); | |
1958 | sp->update_bbs.first_member = &bblst_table[bblst_last]; | |
1959 | update_idx = 0; | |
1960 | for (j = 0; j < el.nr_members; j++) | |
1961 | { | |
1962 | check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]); | |
1963 | fst_edge = nxt_edge = OUT_EDGES (check_block); | |
1964 | do | |
1965 | { | |
1966 | for (k = 0; k < el.nr_members; k++) | |
1967 | if (EDGE_TO_BIT (nxt_edge) == el.first_member[k]) | |
1968 | break; | |
1969 | ||
1970 | if (k >= el.nr_members) | |
1971 | { | |
1972 | bblst_table[bblst_last++] = TO_BLOCK (nxt_edge); | |
1973 | update_idx++; | |
1974 | } | |
1975 | ||
1976 | nxt_edge = NEXT_OUT (nxt_edge); | |
1977 | } | |
1978 | while (fst_edge != nxt_edge); | |
1979 | } | |
1980 | sp->update_bbs.nr_members = update_idx; | |
1981 | ||
1982 | } | |
1983 | else | |
1984 | { | |
1985 | sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0; | |
1986 | ||
1987 | sp->is_speculative = 0; | |
1988 | sp->src_prob = 0; | |
1989 | } | |
1990 | } | |
1991 | } /* compute_trg_info */ | |
1992 | ||
1993 | ||
1994 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
1995 | ||
1996 | void | |
1997 | debug_candidate (i) | |
1998 | int i; | |
1999 | { | |
2000 | if (!candidate_table[i].is_valid) | |
2001 | return; | |
2002 | ||
2003 | if (candidate_table[i].is_speculative) | |
2004 | { | |
2005 | int j; | |
2006 | fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i); | |
2007 | ||
2008 | fprintf (dump, "split path: "); | |
2009 | for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++) | |
2010 | { | |
2011 | int b = candidate_table[i].split_bbs.first_member[j]; | |
2012 | ||
2013 | fprintf (dump, " %d ", b); | |
2014 | } | |
2015 | fprintf (dump, "\n"); | |
2016 | ||
2017 | fprintf (dump, "update path: "); | |
2018 | for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++) | |
2019 | { | |
2020 | int b = candidate_table[i].update_bbs.first_member[j]; | |
2021 | ||
2022 | fprintf (dump, " %d ", b); | |
2023 | } | |
2024 | fprintf (dump, "\n"); | |
2025 | } | |
2026 | else | |
2027 | { | |
2028 | fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i)); | |
2029 | } | |
2030 | } | |
2031 | ||
2032 | ||
2033 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
2034 | ||
2035 | void | |
2036 | debug_candidates (trg) | |
2037 | int trg; | |
2038 | { | |
2039 | int i; | |
2040 | ||
2041 | fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n", | |
2042 | BB_TO_BLOCK (trg), trg); | |
2043 | for (i = trg + 1; i < current_nr_blocks; i++) | |
2044 | debug_candidate (i); | |
2045 | } | |
2046 | ||
2047 | ||
63de6c74 | 2048 | /* Functions for speculative scheduing. */ |
8c660648 JL |
2049 | |
2050 | /* Return 0 if x is a set of a register alive in the beginning of one | |
2051 | of the split-blocks of src, otherwise return 1. */ | |
2052 | ||
2053 | static int | |
2054 | check_live_1 (src, x) | |
2055 | int src; | |
2056 | rtx x; | |
2057 | { | |
5835e573 | 2058 | register int i; |
8c660648 JL |
2059 | register int regno; |
2060 | register rtx reg = SET_DEST (x); | |
2061 | ||
2062 | if (reg == 0) | |
2063 | return 1; | |
2064 | ||
2065 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2066 | || GET_CODE (reg) == SIGN_EXTRACT | |
2067 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2068 | reg = XEXP (reg, 0); | |
2069 | ||
c0222c21 DM |
2070 | if (GET_CODE (reg) == PARALLEL |
2071 | && GET_MODE (reg) == BLKmode) | |
2072 | { | |
2073 | register int i; | |
2074 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2075 | if (check_live_1 (src, XVECEXP (reg, 0, i))) | |
2076 | return 1; | |
2077 | return 0; | |
2078 | } | |
2079 | ||
8c660648 JL |
2080 | if (GET_CODE (reg) != REG) |
2081 | return 1; | |
2082 | ||
2083 | regno = REGNO (reg); | |
2084 | ||
2085 | if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno]) | |
2086 | { | |
63de6c74 | 2087 | /* Global registers are assumed live. */ |
8c660648 JL |
2088 | return 0; |
2089 | } | |
2090 | else | |
2091 | { | |
2092 | if (regno < FIRST_PSEUDO_REGISTER) | |
2093 | { | |
63de6c74 | 2094 | /* Check for hard registers. */ |
8c660648 JL |
2095 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); |
2096 | while (--j >= 0) | |
2097 | { | |
2098 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) | |
2099 | { | |
2100 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2101 | ||
e881bb1b RH |
2102 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, |
2103 | regno + j)) | |
8c660648 JL |
2104 | { |
2105 | return 0; | |
2106 | } | |
2107 | } | |
2108 | } | |
2109 | } | |
2110 | else | |
2111 | { | |
63de6c74 | 2112 | /* Check for psuedo registers. */ |
8c660648 JL |
2113 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) |
2114 | { | |
2115 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2116 | ||
e881bb1b | 2117 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, regno)) |
8c660648 JL |
2118 | { |
2119 | return 0; | |
2120 | } | |
2121 | } | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | return 1; | |
2126 | } | |
2127 | ||
2128 | ||
2129 | /* If x is a set of a register R, mark that R is alive in the beginning | |
2130 | of every update-block of src. */ | |
2131 | ||
2132 | static void | |
2133 | update_live_1 (src, x) | |
2134 | int src; | |
2135 | rtx x; | |
2136 | { | |
5835e573 | 2137 | register int i; |
8c660648 JL |
2138 | register int regno; |
2139 | register rtx reg = SET_DEST (x); | |
2140 | ||
2141 | if (reg == 0) | |
2142 | return; | |
2143 | ||
2144 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2145 | || GET_CODE (reg) == SIGN_EXTRACT | |
2146 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2147 | reg = XEXP (reg, 0); | |
2148 | ||
c0222c21 DM |
2149 | if (GET_CODE (reg) == PARALLEL |
2150 | && GET_MODE (reg) == BLKmode) | |
2151 | { | |
2152 | register int i; | |
2153 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2154 | update_live_1 (src, XVECEXP (reg, 0, i)); | |
2155 | return; | |
2156 | } | |
2157 | ||
8c660648 JL |
2158 | if (GET_CODE (reg) != REG) |
2159 | return; | |
2160 | ||
2161 | /* Global registers are always live, so the code below does not apply | |
2162 | to them. */ | |
2163 | ||
2164 | regno = REGNO (reg); | |
2165 | ||
2166 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
2167 | { | |
2168 | if (regno < FIRST_PSEUDO_REGISTER) | |
2169 | { | |
2170 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2171 | while (--j >= 0) | |
2172 | { | |
2173 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2174 | { | |
2175 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2176 | ||
e881bb1b RH |
2177 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, |
2178 | regno + j); | |
8c660648 JL |
2179 | } |
2180 | } | |
2181 | } | |
2182 | else | |
2183 | { | |
2184 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2185 | { | |
2186 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2187 | ||
e881bb1b | 2188 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, regno); |
8c660648 JL |
2189 | } |
2190 | } | |
2191 | } | |
2192 | } | |
2193 | ||
2194 | ||
2195 | /* Return 1 if insn can be speculatively moved from block src to trg, | |
2196 | otherwise return 0. Called before first insertion of insn to | |
2197 | ready-list or before the scheduling. */ | |
2198 | ||
2199 | static int | |
5835e573 | 2200 | check_live (insn, src) |
8c660648 JL |
2201 | rtx insn; |
2202 | int src; | |
8c660648 | 2203 | { |
63de6c74 | 2204 | /* Find the registers set by instruction. */ |
8c660648 JL |
2205 | if (GET_CODE (PATTERN (insn)) == SET |
2206 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2207 | return check_live_1 (src, PATTERN (insn)); | |
2208 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2209 | { | |
2210 | int j; | |
2211 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2212 | if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2213 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2214 | && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j))) | |
2215 | return 0; | |
2216 | ||
2217 | return 1; | |
2218 | } | |
2219 | ||
2220 | return 1; | |
2221 | } | |
2222 | ||
2223 | ||
2224 | /* Update the live registers info after insn was moved speculatively from | |
2225 | block src to trg. */ | |
2226 | ||
2227 | static void | |
5835e573 | 2228 | update_live (insn, src) |
8c660648 | 2229 | rtx insn; |
5835e573 | 2230 | int src; |
8c660648 | 2231 | { |
63de6c74 | 2232 | /* Find the registers set by instruction. */ |
8c660648 JL |
2233 | if (GET_CODE (PATTERN (insn)) == SET |
2234 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2235 | update_live_1 (src, PATTERN (insn)); | |
2236 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2237 | { | |
2238 | int j; | |
2239 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2240 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2241 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2242 | update_live_1 (src, XVECEXP (PATTERN (insn), 0, j)); | |
2243 | } | |
2244 | } | |
2245 | ||
2246 | /* Exception Free Loads: | |
2247 | ||
2248 | We define five classes of speculative loads: IFREE, IRISKY, | |
2249 | PFREE, PRISKY, and MFREE. | |
2250 | ||
2251 | IFREE loads are loads that are proved to be exception-free, just | |
2252 | by examining the load insn. Examples for such loads are loads | |
2253 | from TOC and loads of global data. | |
2254 | ||
2255 | IRISKY loads are loads that are proved to be exception-risky, | |
2256 | just by examining the load insn. Examples for such loads are | |
2257 | volatile loads and loads from shared memory. | |
2258 | ||
2259 | PFREE loads are loads for which we can prove, by examining other | |
2260 | insns, that they are exception-free. Currently, this class consists | |
2261 | of loads for which we are able to find a "similar load", either in | |
2262 | the target block, or, if only one split-block exists, in that split | |
2263 | block. Load2 is similar to load1 if both have same single base | |
2264 | register. We identify only part of the similar loads, by finding | |
2265 | an insn upon which both load1 and load2 have a DEF-USE dependence. | |
2266 | ||
2267 | PRISKY loads are loads for which we can prove, by examining other | |
2268 | insns, that they are exception-risky. Currently we have two proofs for | |
2269 | such loads. The first proof detects loads that are probably guarded by a | |
2270 | test on the memory address. This proof is based on the | |
2271 | backward and forward data dependence information for the region. | |
2272 | Let load-insn be the examined load. | |
2273 | Load-insn is PRISKY iff ALL the following hold: | |
2274 | ||
2275 | - insn1 is not in the same block as load-insn | |
2276 | - there is a DEF-USE dependence chain (insn1, ..., load-insn) | |
63de6c74 MH |
2277 | - test-insn is either a compare or a branch, not in the same block |
2278 | as load-insn | |
8c660648 JL |
2279 | - load-insn is reachable from test-insn |
2280 | - there is a DEF-USE dependence chain (insn1, ..., test-insn) | |
2281 | ||
2282 | This proof might fail when the compare and the load are fed | |
2283 | by an insn not in the region. To solve this, we will add to this | |
2284 | group all loads that have no input DEF-USE dependence. | |
2285 | ||
2286 | The second proof detects loads that are directly or indirectly | |
2287 | fed by a speculative load. This proof is affected by the | |
2288 | scheduling process. We will use the flag fed_by_spec_load. | |
2289 | Initially, all insns have this flag reset. After a speculative | |
2290 | motion of an insn, if insn is either a load, or marked as | |
2291 | fed_by_spec_load, we will also mark as fed_by_spec_load every | |
2292 | insn1 for which a DEF-USE dependence (insn, insn1) exists. A | |
2293 | load which is fed_by_spec_load is also PRISKY. | |
2294 | ||
2295 | MFREE (maybe-free) loads are all the remaining loads. They may be | |
2296 | exception-free, but we cannot prove it. | |
2297 | ||
2298 | Now, all loads in IFREE and PFREE classes are considered | |
2299 | exception-free, while all loads in IRISKY and PRISKY classes are | |
2300 | considered exception-risky. As for loads in the MFREE class, | |
2301 | these are considered either exception-free or exception-risky, | |
2302 | depending on whether we are pessimistic or optimistic. We have | |
2303 | to take the pessimistic approach to assure the safety of | |
2304 | speculative scheduling, but we can take the optimistic approach | |
2305 | by invoking the -fsched_spec_load_dangerous option. */ | |
2306 | ||
2307 | enum INSN_TRAP_CLASS | |
2308 | { | |
2309 | TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2, | |
2310 | PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5 | |
2311 | }; | |
2312 | ||
2313 | #define WORST_CLASS(class1, class2) \ | |
2314 | ((class1 > class2) ? class1 : class2) | |
2315 | ||
8c660648 JL |
2316 | /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */ |
2317 | #define IS_REACHABLE(bb_from, bb_to) \ | |
2318 | (bb_from == bb_to \ | |
2319 | || IS_RGN_ENTRY (bb_from) \ | |
2320 | || (bitset_member (ancestor_edges[bb_to], \ | |
2321 | EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \ | |
2322 | edgeset_size))) | |
8c660648 | 2323 | |
63de6c74 | 2324 | /* Non-zero iff the address is comprised from at most 1 register. */ |
8c660648 JL |
2325 | #define CONST_BASED_ADDRESS_P(x) \ |
2326 | (GET_CODE (x) == REG \ | |
2327 | || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \ | |
2328 | || (GET_CODE (x) == LO_SUM)) \ | |
2329 | && (GET_CODE (XEXP (x, 0)) == CONST_INT \ | |
2330 | || GET_CODE (XEXP (x, 1)) == CONST_INT))) | |
2331 | ||
2332 | /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */ | |
2333 | ||
2334 | static void | |
2335 | set_spec_fed (load_insn) | |
2336 | rtx load_insn; | |
2337 | { | |
2338 | rtx link; | |
2339 | ||
2340 | for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1)) | |
2341 | if (GET_MODE (link) == VOIDmode) | |
2342 | FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1; | |
2343 | } /* set_spec_fed */ | |
2344 | ||
63de6c74 MH |
2345 | /* On the path from the insn to load_insn_bb, find a conditional |
2346 | branch depending on insn, that guards the speculative load. */ | |
8c660648 JL |
2347 | |
2348 | static int | |
2349 | find_conditional_protection (insn, load_insn_bb) | |
2350 | rtx insn; | |
2351 | int load_insn_bb; | |
2352 | { | |
2353 | rtx link; | |
2354 | ||
63de6c74 | 2355 | /* Iterate through DEF-USE forward dependences. */ |
8c660648 JL |
2356 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) |
2357 | { | |
2358 | rtx next = XEXP (link, 0); | |
c88e8206 | 2359 | if ((CONTAINING_RGN (BLOCK_NUM (next)) == |
8c660648 JL |
2360 | CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb))) |
2361 | && IS_REACHABLE (INSN_BB (next), load_insn_bb) | |
2362 | && load_insn_bb != INSN_BB (next) | |
2363 | && GET_MODE (link) == VOIDmode | |
2364 | && (GET_CODE (next) == JUMP_INSN | |
2365 | || find_conditional_protection (next, load_insn_bb))) | |
2366 | return 1; | |
2367 | } | |
2368 | return 0; | |
2369 | } /* find_conditional_protection */ | |
2370 | ||
2371 | /* Returns 1 if the same insn1 that participates in the computation | |
2372 | of load_insn's address is feeding a conditional branch that is | |
2373 | guarding on load_insn. This is true if we find a the two DEF-USE | |
2374 | chains: | |
2375 | insn1 -> ... -> conditional-branch | |
2376 | insn1 -> ... -> load_insn, | |
2377 | and if a flow path exist: | |
2378 | insn1 -> ... -> conditional-branch -> ... -> load_insn, | |
2379 | and if insn1 is on the path | |
2380 | region-entry -> ... -> bb_trg -> ... load_insn. | |
2381 | ||
2382 | Locate insn1 by climbing on LOG_LINKS from load_insn. | |
2383 | Locate the branch by following INSN_DEPEND from insn1. */ | |
2384 | ||
2385 | static int | |
2386 | is_conditionally_protected (load_insn, bb_src, bb_trg) | |
2387 | rtx load_insn; | |
2388 | int bb_src, bb_trg; | |
2389 | { | |
2390 | rtx link; | |
2391 | ||
2392 | for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1)) | |
2393 | { | |
2394 | rtx insn1 = XEXP (link, 0); | |
2395 | ||
63de6c74 | 2396 | /* Must be a DEF-USE dependence upon non-branch. */ |
8c660648 JL |
2397 | if (GET_MODE (link) != VOIDmode |
2398 | || GET_CODE (insn1) == JUMP_INSN) | |
2399 | continue; | |
2400 | ||
63de6c74 | 2401 | /* Must exist a path: region-entry -> ... -> bb_trg -> ... load_insn. */ |
8c660648 | 2402 | if (INSN_BB (insn1) == bb_src |
c88e8206 | 2403 | || (CONTAINING_RGN (BLOCK_NUM (insn1)) |
8c660648 JL |
2404 | != CONTAINING_RGN (BB_TO_BLOCK (bb_src))) |
2405 | || (!IS_REACHABLE (bb_trg, INSN_BB (insn1)) | |
2406 | && !IS_REACHABLE (INSN_BB (insn1), bb_trg))) | |
2407 | continue; | |
2408 | ||
63de6c74 | 2409 | /* Now search for the conditional-branch. */ |
8c660648 JL |
2410 | if (find_conditional_protection (insn1, bb_src)) |
2411 | return 1; | |
2412 | ||
63de6c74 | 2413 | /* Recursive step: search another insn1, "above" current insn1. */ |
8c660648 JL |
2414 | return is_conditionally_protected (insn1, bb_src, bb_trg); |
2415 | } | |
2416 | ||
63de6c74 | 2417 | /* The chain does not exist. */ |
8c660648 JL |
2418 | return 0; |
2419 | } /* is_conditionally_protected */ | |
2420 | ||
2421 | /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence | |
2422 | load_insn can move speculatively from bb_src to bb_trg. All the | |
2423 | following must hold: | |
2424 | ||
2425 | (1) both loads have 1 base register (PFREE_CANDIDATEs). | |
2426 | (2) load_insn and load1 have a def-use dependence upon | |
2427 | the same insn 'insn1'. | |
2428 | (3) either load2 is in bb_trg, or: | |
2429 | - there's only one split-block, and | |
2430 | - load1 is on the escape path, and | |
2431 | ||
2432 | From all these we can conclude that the two loads access memory | |
2433 | addresses that differ at most by a constant, and hence if moving | |
2434 | load_insn would cause an exception, it would have been caused by | |
2435 | load2 anyhow. */ | |
2436 | ||
2437 | static int | |
2438 | is_pfree (load_insn, bb_src, bb_trg) | |
2439 | rtx load_insn; | |
2440 | int bb_src, bb_trg; | |
2441 | { | |
2442 | rtx back_link; | |
2443 | register candidate *candp = candidate_table + bb_src; | |
2444 | ||
2445 | if (candp->split_bbs.nr_members != 1) | |
63de6c74 | 2446 | /* Must have exactly one escape block. */ |
8c660648 JL |
2447 | return 0; |
2448 | ||
2449 | for (back_link = LOG_LINKS (load_insn); | |
2450 | back_link; back_link = XEXP (back_link, 1)) | |
2451 | { | |
2452 | rtx insn1 = XEXP (back_link, 0); | |
2453 | ||
2454 | if (GET_MODE (back_link) == VOIDmode) | |
2455 | { | |
63de6c74 | 2456 | /* Found a DEF-USE dependence (insn1, load_insn). */ |
8c660648 JL |
2457 | rtx fore_link; |
2458 | ||
2459 | for (fore_link = INSN_DEPEND (insn1); | |
2460 | fore_link; fore_link = XEXP (fore_link, 1)) | |
2461 | { | |
2462 | rtx insn2 = XEXP (fore_link, 0); | |
2463 | if (GET_MODE (fore_link) == VOIDmode) | |
2464 | { | |
63de6c74 | 2465 | /* Found a DEF-USE dependence (insn1, insn2). */ |
ac957f13 | 2466 | if (haifa_classify_insn (insn2) != PFREE_CANDIDATE) |
63de6c74 | 2467 | /* insn2 not guaranteed to be a 1 base reg load. */ |
8c660648 JL |
2468 | continue; |
2469 | ||
2470 | if (INSN_BB (insn2) == bb_trg) | |
63de6c74 | 2471 | /* insn2 is the similar load, in the target block. */ |
8c660648 JL |
2472 | return 1; |
2473 | ||
c88e8206 | 2474 | if (*(candp->split_bbs.first_member) == BLOCK_NUM (insn2)) |
63de6c74 | 2475 | /* insn2 is a similar load, in a split-block. */ |
8c660648 JL |
2476 | return 1; |
2477 | } | |
2478 | } | |
2479 | } | |
2480 | } | |
2481 | ||
63de6c74 | 2482 | /* Couldn't find a similar load. */ |
8c660648 JL |
2483 | return 0; |
2484 | } /* is_pfree */ | |
2485 | ||
2486 | /* Returns a class that insn with GET_DEST(insn)=x may belong to, | |
2487 | as found by analyzing insn's expression. */ | |
2488 | ||
2489 | static int | |
2490 | may_trap_exp (x, is_store) | |
2491 | rtx x; | |
2492 | int is_store; | |
2493 | { | |
2494 | enum rtx_code code; | |
2495 | ||
2496 | if (x == 0) | |
2497 | return TRAP_FREE; | |
2498 | code = GET_CODE (x); | |
2499 | if (is_store) | |
2500 | { | |
2501 | if (code == MEM) | |
2502 | return TRAP_RISKY; | |
2503 | else | |
2504 | return TRAP_FREE; | |
2505 | } | |
2506 | if (code == MEM) | |
2507 | { | |
63de6c74 | 2508 | /* The insn uses memory: a volatile load. */ |
8c660648 JL |
2509 | if (MEM_VOLATILE_P (x)) |
2510 | return IRISKY; | |
63de6c74 | 2511 | /* An exception-free load. */ |
8c660648 JL |
2512 | if (!may_trap_p (x)) |
2513 | return IFREE; | |
63de6c74 | 2514 | /* A load with 1 base register, to be further checked. */ |
8c660648 JL |
2515 | if (CONST_BASED_ADDRESS_P (XEXP (x, 0))) |
2516 | return PFREE_CANDIDATE; | |
63de6c74 | 2517 | /* No info on the load, to be further checked. */ |
8c660648 JL |
2518 | return PRISKY_CANDIDATE; |
2519 | } | |
2520 | else | |
2521 | { | |
6f7d635c | 2522 | const char *fmt; |
8c660648 JL |
2523 | int i, insn_class = TRAP_FREE; |
2524 | ||
63de6c74 | 2525 | /* Neither store nor load, check if it may cause a trap. */ |
8c660648 JL |
2526 | if (may_trap_p (x)) |
2527 | return TRAP_RISKY; | |
63de6c74 | 2528 | /* Recursive step: walk the insn... */ |
8c660648 JL |
2529 | fmt = GET_RTX_FORMAT (code); |
2530 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2531 | { | |
2532 | if (fmt[i] == 'e') | |
2533 | { | |
2534 | int tmp_class = may_trap_exp (XEXP (x, i), is_store); | |
2535 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2536 | } | |
2537 | else if (fmt[i] == 'E') | |
2538 | { | |
2539 | int j; | |
2540 | for (j = 0; j < XVECLEN (x, i); j++) | |
2541 | { | |
2542 | int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store); | |
2543 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2544 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2545 | break; | |
2546 | } | |
2547 | } | |
2548 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2549 | break; | |
2550 | } | |
2551 | return insn_class; | |
2552 | } | |
2553 | } /* may_trap_exp */ | |
2554 | ||
2555 | ||
2556 | /* Classifies insn for the purpose of verifying that it can be | |
2557 | moved speculatively, by examining it's patterns, returning: | |
2558 | TRAP_RISKY: store, or risky non-load insn (e.g. division by variable). | |
2559 | TRAP_FREE: non-load insn. | |
2560 | IFREE: load from a globaly safe location. | |
2561 | IRISKY: volatile load. | |
2562 | PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for | |
2563 | being either PFREE or PRISKY. */ | |
2564 | ||
2565 | static int | |
ac957f13 | 2566 | haifa_classify_insn (insn) |
8c660648 JL |
2567 | rtx insn; |
2568 | { | |
2569 | rtx pat = PATTERN (insn); | |
2570 | int tmp_class = TRAP_FREE; | |
2571 | int insn_class = TRAP_FREE; | |
2572 | enum rtx_code code; | |
2573 | ||
2574 | if (GET_CODE (pat) == PARALLEL) | |
2575 | { | |
2576 | int i, len = XVECLEN (pat, 0); | |
2577 | ||
2578 | for (i = len - 1; i >= 0; i--) | |
2579 | { | |
2580 | code = GET_CODE (XVECEXP (pat, 0, i)); | |
2581 | switch (code) | |
2582 | { | |
2583 | case CLOBBER: | |
63de6c74 | 2584 | /* Test if it is a 'store'. */ |
8c660648 JL |
2585 | tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1); |
2586 | break; | |
2587 | case SET: | |
63de6c74 | 2588 | /* Test if it is a store. */ |
8c660648 JL |
2589 | tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1); |
2590 | if (tmp_class == TRAP_RISKY) | |
2591 | break; | |
63de6c74 | 2592 | /* Test if it is a load. */ |
8c660648 JL |
2593 | tmp_class = |
2594 | WORST_CLASS (tmp_class, | |
2595 | may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0)); | |
e0cd0770 JC |
2596 | break; |
2597 | case TRAP_IF: | |
2598 | tmp_class = TRAP_RISKY; | |
2599 | break; | |
8c660648 JL |
2600 | default:; |
2601 | } | |
2602 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2603 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2604 | break; | |
2605 | } | |
2606 | } | |
2607 | else | |
2608 | { | |
2609 | code = GET_CODE (pat); | |
2610 | switch (code) | |
2611 | { | |
2612 | case CLOBBER: | |
63de6c74 | 2613 | /* Test if it is a 'store'. */ |
8c660648 JL |
2614 | tmp_class = may_trap_exp (XEXP (pat, 0), 1); |
2615 | break; | |
2616 | case SET: | |
63de6c74 | 2617 | /* Test if it is a store. */ |
8c660648 JL |
2618 | tmp_class = may_trap_exp (SET_DEST (pat), 1); |
2619 | if (tmp_class == TRAP_RISKY) | |
2620 | break; | |
63de6c74 | 2621 | /* Test if it is a load. */ |
8c660648 JL |
2622 | tmp_class = |
2623 | WORST_CLASS (tmp_class, | |
2624 | may_trap_exp (SET_SRC (pat), 0)); | |
e0cd0770 JC |
2625 | break; |
2626 | case TRAP_IF: | |
2627 | tmp_class = TRAP_RISKY; | |
2628 | break; | |
8c660648 JL |
2629 | default:; |
2630 | } | |
2631 | insn_class = tmp_class; | |
2632 | } | |
2633 | ||
2634 | return insn_class; | |
2635 | ||
ac957f13 | 2636 | } /* haifa_classify_insn */ |
8c660648 JL |
2637 | |
2638 | /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by | |
2639 | a load moved speculatively, or if load_insn is protected by | |
2640 | a compare on load_insn's address). */ | |
2641 | ||
2642 | static int | |
2643 | is_prisky (load_insn, bb_src, bb_trg) | |
2644 | rtx load_insn; | |
2645 | int bb_src, bb_trg; | |
2646 | { | |
2647 | if (FED_BY_SPEC_LOAD (load_insn)) | |
2648 | return 1; | |
2649 | ||
2650 | if (LOG_LINKS (load_insn) == NULL) | |
63de6c74 | 2651 | /* Dependence may 'hide' out of the region. */ |
8c660648 JL |
2652 | return 1; |
2653 | ||
2654 | if (is_conditionally_protected (load_insn, bb_src, bb_trg)) | |
2655 | return 1; | |
2656 | ||
2657 | return 0; | |
2658 | } /* is_prisky */ | |
2659 | ||
2660 | /* Insn is a candidate to be moved speculatively from bb_src to bb_trg. | |
2661 | Return 1 if insn is exception-free (and the motion is valid) | |
2662 | and 0 otherwise. */ | |
2663 | ||
2664 | static int | |
2665 | is_exception_free (insn, bb_src, bb_trg) | |
2666 | rtx insn; | |
2667 | int bb_src, bb_trg; | |
2668 | { | |
ac957f13 | 2669 | int insn_class = haifa_classify_insn (insn); |
8c660648 | 2670 | |
63de6c74 | 2671 | /* Handle non-load insns. */ |
8c660648 JL |
2672 | switch (insn_class) |
2673 | { | |
2674 | case TRAP_FREE: | |
2675 | return 1; | |
2676 | case TRAP_RISKY: | |
2677 | return 0; | |
2678 | default:; | |
2679 | } | |
2680 | ||
63de6c74 | 2681 | /* Handle loads. */ |
8c660648 JL |
2682 | if (!flag_schedule_speculative_load) |
2683 | return 0; | |
2684 | IS_LOAD_INSN (insn) = 1; | |
2685 | switch (insn_class) | |
2686 | { | |
2687 | case IFREE: | |
2688 | return (1); | |
2689 | case IRISKY: | |
2690 | return 0; | |
2691 | case PFREE_CANDIDATE: | |
2692 | if (is_pfree (insn, bb_src, bb_trg)) | |
2693 | return 1; | |
63de6c74 | 2694 | /* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */ |
8c660648 JL |
2695 | case PRISKY_CANDIDATE: |
2696 | if (!flag_schedule_speculative_load_dangerous | |
2697 | || is_prisky (insn, bb_src, bb_trg)) | |
2698 | return 0; | |
2699 | break; | |
2700 | default:; | |
2701 | } | |
2702 | ||
2703 | return flag_schedule_speculative_load_dangerous; | |
2704 | } /* is_exception_free */ | |
2705 | ||
2706 | ||
2707 | /* Process an insn's memory dependencies. There are four kinds of | |
2708 | dependencies: | |
2709 | ||
2710 | (0) read dependence: read follows read | |
2711 | (1) true dependence: read follows write | |
2712 | (2) anti dependence: write follows read | |
2713 | (3) output dependence: write follows write | |
2714 | ||
2715 | We are careful to build only dependencies which actually exist, and | |
2716 | use transitivity to avoid building too many links. */ | |
2717 | \f | |
2718 | /* Return the INSN_LIST containing INSN in LIST, or NULL | |
2719 | if LIST does not contain INSN. */ | |
2720 | ||
cbb13457 | 2721 | HAIFA_INLINE static rtx |
8c660648 JL |
2722 | find_insn_list (insn, list) |
2723 | rtx insn; | |
2724 | rtx list; | |
2725 | { | |
2726 | while (list) | |
2727 | { | |
2728 | if (XEXP (list, 0) == insn) | |
2729 | return list; | |
2730 | list = XEXP (list, 1); | |
2731 | } | |
2732 | return 0; | |
2733 | } | |
2734 | ||
2735 | ||
63de6c74 MH |
2736 | /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 |
2737 | otherwise. */ | |
8c660648 | 2738 | |
cbb13457 | 2739 | HAIFA_INLINE static char |
8c660648 JL |
2740 | find_insn_mem_list (insn, x, list, list1) |
2741 | rtx insn, x; | |
2742 | rtx list, list1; | |
2743 | { | |
2744 | while (list) | |
2745 | { | |
2746 | if (XEXP (list, 0) == insn | |
2747 | && XEXP (list1, 0) == x) | |
2748 | return 1; | |
2749 | list = XEXP (list, 1); | |
2750 | list1 = XEXP (list1, 1); | |
2751 | } | |
2752 | return 0; | |
2753 | } | |
2754 | ||
2755 | ||
2756 | /* Compute the function units used by INSN. This caches the value | |
2757 | returned by function_units_used. A function unit is encoded as the | |
2758 | unit number if the value is non-negative and the compliment of a | |
2759 | mask if the value is negative. A function unit index is the | |
2760 | non-negative encoding. */ | |
2761 | ||
cbb13457 | 2762 | HAIFA_INLINE static int |
8c660648 JL |
2763 | insn_unit (insn) |
2764 | rtx insn; | |
2765 | { | |
2766 | register int unit = INSN_UNIT (insn); | |
2767 | ||
2768 | if (unit == 0) | |
2769 | { | |
2770 | recog_memoized (insn); | |
2771 | ||
2772 | /* A USE insn, or something else we don't need to understand. | |
2773 | We can't pass these directly to function_units_used because it will | |
2774 | trigger a fatal error for unrecognizable insns. */ | |
2775 | if (INSN_CODE (insn) < 0) | |
2776 | unit = -1; | |
2777 | else | |
2778 | { | |
2779 | unit = function_units_used (insn); | |
2780 | /* Increment non-negative values so we can cache zero. */ | |
2781 | if (unit >= 0) | |
2782 | unit++; | |
2783 | } | |
2784 | /* We only cache 16 bits of the result, so if the value is out of | |
2785 | range, don't cache it. */ | |
2786 | if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT | |
2787 | || unit >= 0 | |
77f3d48a | 2788 | || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0) |
8c660648 JL |
2789 | INSN_UNIT (insn) = unit; |
2790 | } | |
2791 | return (unit > 0 ? unit - 1 : unit); | |
2792 | } | |
2793 | ||
2794 | /* Compute the blockage range for executing INSN on UNIT. This caches | |
2795 | the value returned by the blockage_range_function for the unit. | |
2796 | These values are encoded in an int where the upper half gives the | |
2797 | minimum value and the lower half gives the maximum value. */ | |
2798 | ||
cbb13457 | 2799 | HAIFA_INLINE static unsigned int |
8c660648 JL |
2800 | blockage_range (unit, insn) |
2801 | int unit; | |
2802 | rtx insn; | |
2803 | { | |
2804 | unsigned int blockage = INSN_BLOCKAGE (insn); | |
2805 | unsigned int range; | |
2806 | ||
79c9824e | 2807 | if ((int) UNIT_BLOCKED (blockage) != unit + 1) |
8c660648 JL |
2808 | { |
2809 | range = function_units[unit].blockage_range_function (insn); | |
2810 | /* We only cache the blockage range for one unit and then only if | |
2811 | the values fit. */ | |
2812 | if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS) | |
2813 | INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range); | |
2814 | } | |
2815 | else | |
2816 | range = BLOCKAGE_RANGE (blockage); | |
2817 | ||
2818 | return range; | |
2819 | } | |
2820 | ||
2821 | /* A vector indexed by function unit instance giving the last insn to use | |
2822 | the unit. The value of the function unit instance index for unit U | |
2823 | instance I is (U + I * FUNCTION_UNITS_SIZE). */ | |
2824 | static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2825 | ||
2826 | /* A vector indexed by function unit instance giving the minimum time when | |
2827 | the unit will unblock based on the maximum blockage cost. */ | |
2828 | static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2829 | ||
2830 | /* A vector indexed by function unit number giving the number of insns | |
2831 | that remain to use the unit. */ | |
2832 | static int unit_n_insns[FUNCTION_UNITS_SIZE]; | |
2833 | ||
2834 | /* Reset the function unit state to the null state. */ | |
2835 | ||
2836 | static void | |
2837 | clear_units () | |
2838 | { | |
2839 | bzero ((char *) unit_last_insn, sizeof (unit_last_insn)); | |
2840 | bzero ((char *) unit_tick, sizeof (unit_tick)); | |
2841 | bzero ((char *) unit_n_insns, sizeof (unit_n_insns)); | |
2842 | } | |
2843 | ||
63de6c74 | 2844 | /* Return the issue-delay of an insn. */ |
8c660648 | 2845 | |
cbb13457 | 2846 | HAIFA_INLINE static int |
8c660648 JL |
2847 | insn_issue_delay (insn) |
2848 | rtx insn; | |
2849 | { | |
8c660648 JL |
2850 | int i, delay = 0; |
2851 | int unit = insn_unit (insn); | |
2852 | ||
63de6c74 | 2853 | /* Efficiency note: in fact, we are working 'hard' to compute a |
8c660648 JL |
2854 | value that was available in md file, and is not available in |
2855 | function_units[] structure. It would be nice to have this | |
2856 | value there, too. */ | |
2857 | if (unit >= 0) | |
2858 | { | |
2859 | if (function_units[unit].blockage_range_function && | |
2860 | function_units[unit].blockage_function) | |
2861 | delay = function_units[unit].blockage_function (insn, insn); | |
2862 | } | |
2863 | else | |
2864 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2865 | if ((unit & 1) != 0 && function_units[i].blockage_range_function | |
2866 | && function_units[i].blockage_function) | |
2867 | delay = MAX (delay, function_units[i].blockage_function (insn, insn)); | |
2868 | ||
2869 | return delay; | |
2870 | } | |
2871 | ||
2872 | /* Return the actual hazard cost of executing INSN on the unit UNIT, | |
2873 | instance INSTANCE at time CLOCK if the previous actual hazard cost | |
2874 | was COST. */ | |
2875 | ||
cbb13457 | 2876 | HAIFA_INLINE static int |
8c660648 JL |
2877 | actual_hazard_this_instance (unit, instance, insn, clock, cost) |
2878 | int unit, instance, clock, cost; | |
2879 | rtx insn; | |
2880 | { | |
63de6c74 | 2881 | int tick = unit_tick[instance]; /* Issue time of the last issued insn. */ |
8c660648 JL |
2882 | |
2883 | if (tick - clock > cost) | |
2884 | { | |
2885 | /* The scheduler is operating forward, so unit's last insn is the | |
2886 | executing insn and INSN is the candidate insn. We want a | |
2887 | more exact measure of the blockage if we execute INSN at CLOCK | |
2888 | given when we committed the execution of the unit's last insn. | |
2889 | ||
2890 | The blockage value is given by either the unit's max blockage | |
2891 | constant, blockage range function, or blockage function. Use | |
2892 | the most exact form for the given unit. */ | |
2893 | ||
2894 | if (function_units[unit].blockage_range_function) | |
2895 | { | |
2896 | if (function_units[unit].blockage_function) | |
2897 | tick += (function_units[unit].blockage_function | |
2898 | (unit_last_insn[instance], insn) | |
2899 | - function_units[unit].max_blockage); | |
2900 | else | |
2901 | tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn)) | |
2902 | - function_units[unit].max_blockage); | |
2903 | } | |
2904 | if (tick - clock > cost) | |
2905 | cost = tick - clock; | |
2906 | } | |
2907 | return cost; | |
2908 | } | |
2909 | ||
2910 | /* Record INSN as having begun execution on the units encoded by UNIT at | |
2911 | time CLOCK. */ | |
2912 | ||
cbb13457 | 2913 | HAIFA_INLINE static void |
8c660648 JL |
2914 | schedule_unit (unit, insn, clock) |
2915 | int unit, clock; | |
2916 | rtx insn; | |
2917 | { | |
2918 | int i; | |
2919 | ||
2920 | if (unit >= 0) | |
2921 | { | |
2922 | int instance = unit; | |
2923 | #if MAX_MULTIPLICITY > 1 | |
2924 | /* Find the first free instance of the function unit and use that | |
2925 | one. We assume that one is free. */ | |
2926 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2927 | { | |
2928 | if (!actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
2929 | break; | |
2930 | instance += FUNCTION_UNITS_SIZE; | |
2931 | } | |
2932 | #endif | |
2933 | unit_last_insn[instance] = insn; | |
2934 | unit_tick[instance] = (clock + function_units[unit].max_blockage); | |
2935 | } | |
2936 | else | |
2937 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2938 | if ((unit & 1) != 0) | |
2939 | schedule_unit (i, insn, clock); | |
2940 | } | |
2941 | ||
2942 | /* Return the actual hazard cost of executing INSN on the units encoded by | |
2943 | UNIT at time CLOCK if the previous actual hazard cost was COST. */ | |
2944 | ||
cbb13457 | 2945 | HAIFA_INLINE static int |
8c660648 JL |
2946 | actual_hazard (unit, insn, clock, cost) |
2947 | int unit, clock, cost; | |
2948 | rtx insn; | |
2949 | { | |
2950 | int i; | |
2951 | ||
2952 | if (unit >= 0) | |
2953 | { | |
2954 | /* Find the instance of the function unit with the minimum hazard. */ | |
2955 | int instance = unit; | |
2956 | int best_cost = actual_hazard_this_instance (unit, instance, insn, | |
2957 | clock, cost); | |
1eda7a81 | 2958 | #if MAX_MULTIPLICITY > 1 |
8c660648 JL |
2959 | int this_cost; |
2960 | ||
8c660648 JL |
2961 | if (best_cost > cost) |
2962 | { | |
2963 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2964 | { | |
2965 | instance += FUNCTION_UNITS_SIZE; | |
2966 | this_cost = actual_hazard_this_instance (unit, instance, insn, | |
2967 | clock, cost); | |
2968 | if (this_cost < best_cost) | |
2969 | { | |
2970 | best_cost = this_cost; | |
2971 | if (this_cost <= cost) | |
2972 | break; | |
2973 | } | |
2974 | } | |
2975 | } | |
2976 | #endif | |
2977 | cost = MAX (cost, best_cost); | |
2978 | } | |
2979 | else | |
2980 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2981 | if ((unit & 1) != 0) | |
2982 | cost = actual_hazard (i, insn, clock, cost); | |
2983 | ||
2984 | return cost; | |
2985 | } | |
2986 | ||
2987 | /* Return the potential hazard cost of executing an instruction on the | |
2988 | units encoded by UNIT if the previous potential hazard cost was COST. | |
2989 | An insn with a large blockage time is chosen in preference to one | |
2990 | with a smaller time; an insn that uses a unit that is more likely | |
2991 | to be used is chosen in preference to one with a unit that is less | |
2992 | used. We are trying to minimize a subsequent actual hazard. */ | |
2993 | ||
cbb13457 | 2994 | HAIFA_INLINE static int |
8c660648 JL |
2995 | potential_hazard (unit, insn, cost) |
2996 | int unit, cost; | |
2997 | rtx insn; | |
2998 | { | |
2999 | int i, ncost; | |
3000 | unsigned int minb, maxb; | |
3001 | ||
3002 | if (unit >= 0) | |
3003 | { | |
3004 | minb = maxb = function_units[unit].max_blockage; | |
3005 | if (maxb > 1) | |
3006 | { | |
3007 | if (function_units[unit].blockage_range_function) | |
3008 | { | |
3009 | maxb = minb = blockage_range (unit, insn); | |
3010 | maxb = MAX_BLOCKAGE_COST (maxb); | |
3011 | minb = MIN_BLOCKAGE_COST (minb); | |
3012 | } | |
3013 | ||
3014 | if (maxb > 1) | |
3015 | { | |
3016 | /* Make the number of instructions left dominate. Make the | |
3017 | minimum delay dominate the maximum delay. If all these | |
3018 | are the same, use the unit number to add an arbitrary | |
3019 | ordering. Other terms can be added. */ | |
3020 | ncost = minb * 0x40 + maxb; | |
3021 | ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit; | |
3022 | if (ncost > cost) | |
3023 | cost = ncost; | |
3024 | } | |
3025 | } | |
3026 | } | |
3027 | else | |
3028 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3029 | if ((unit & 1) != 0) | |
3030 | cost = potential_hazard (i, insn, cost); | |
3031 | ||
3032 | return cost; | |
3033 | } | |
3034 | ||
3035 | /* Compute cost of executing INSN given the dependence LINK on the insn USED. | |
3036 | This is the number of cycles between instruction issue and | |
3037 | instruction results. */ | |
3038 | ||
cbb13457 | 3039 | HAIFA_INLINE static int |
8c660648 JL |
3040 | insn_cost (insn, link, used) |
3041 | rtx insn, link, used; | |
3042 | { | |
3043 | register int cost = INSN_COST (insn); | |
3044 | ||
3045 | if (cost == 0) | |
3046 | { | |
3047 | recog_memoized (insn); | |
3048 | ||
3049 | /* A USE insn, or something else we don't need to understand. | |
3050 | We can't pass these directly to result_ready_cost because it will | |
3051 | trigger a fatal error for unrecognizable insns. */ | |
3052 | if (INSN_CODE (insn) < 0) | |
3053 | { | |
3054 | INSN_COST (insn) = 1; | |
3055 | return 1; | |
3056 | } | |
3057 | else | |
3058 | { | |
3059 | cost = result_ready_cost (insn); | |
3060 | ||
3061 | if (cost < 1) | |
3062 | cost = 1; | |
3063 | ||
3064 | INSN_COST (insn) = cost; | |
3065 | } | |
3066 | } | |
3067 | ||
63de6c74 | 3068 | /* In this case estimate cost without caring how insn is used. */ |
8c660648 JL |
3069 | if (link == 0 && used == 0) |
3070 | return cost; | |
3071 | ||
3072 | /* A USE insn should never require the value used to be computed. This | |
3073 | allows the computation of a function's result and parameter values to | |
3074 | overlap the return and call. */ | |
3075 | recog_memoized (used); | |
3076 | if (INSN_CODE (used) < 0) | |
3077 | LINK_COST_FREE (link) = 1; | |
3078 | ||
3079 | /* If some dependencies vary the cost, compute the adjustment. Most | |
3080 | commonly, the adjustment is complete: either the cost is ignored | |
3081 | (in the case of an output- or anti-dependence), or the cost is | |
3082 | unchanged. These values are cached in the link as LINK_COST_FREE | |
3083 | and LINK_COST_ZERO. */ | |
3084 | ||
3085 | if (LINK_COST_FREE (link)) | |
197043f5 | 3086 | cost = 0; |
8c660648 JL |
3087 | #ifdef ADJUST_COST |
3088 | else if (!LINK_COST_ZERO (link)) | |
3089 | { | |
3090 | int ncost = cost; | |
3091 | ||
3092 | ADJUST_COST (used, link, insn, ncost); | |
197043f5 RH |
3093 | if (ncost < 1) |
3094 | { | |
3095 | LINK_COST_FREE (link) = 1; | |
3096 | ncost = 0; | |
3097 | } | |
8c660648 JL |
3098 | if (cost == ncost) |
3099 | LINK_COST_ZERO (link) = 1; | |
3100 | cost = ncost; | |
3101 | } | |
3102 | #endif | |
3103 | return cost; | |
3104 | } | |
3105 | ||
3106 | /* Compute the priority number for INSN. */ | |
3107 | ||
3108 | static int | |
3109 | priority (insn) | |
3110 | rtx insn; | |
3111 | { | |
3112 | int this_priority; | |
3113 | rtx link; | |
3114 | ||
3115 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
3116 | return 0; | |
3117 | ||
3118 | if ((this_priority = INSN_PRIORITY (insn)) == 0) | |
3119 | { | |
3120 | if (INSN_DEPEND (insn) == 0) | |
3121 | this_priority = insn_cost (insn, 0, 0); | |
3122 | else | |
3123 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
3124 | { | |
3125 | rtx next; | |
3126 | int next_priority; | |
3127 | ||
6d8ccdbb JL |
3128 | if (RTX_INTEGRATED_P (link)) |
3129 | continue; | |
3130 | ||
8c660648 JL |
3131 | next = XEXP (link, 0); |
3132 | ||
63de6c74 | 3133 | /* Critical path is meaningful in block boundaries only. */ |
c88e8206 | 3134 | if (BLOCK_NUM (next) != BLOCK_NUM (insn)) |
8c660648 JL |
3135 | continue; |
3136 | ||
3137 | next_priority = insn_cost (insn, link, next) + priority (next); | |
3138 | if (next_priority > this_priority) | |
3139 | this_priority = next_priority; | |
3140 | } | |
3141 | INSN_PRIORITY (insn) = this_priority; | |
3142 | } | |
3143 | return this_priority; | |
3144 | } | |
3145 | \f | |
3146 | ||
3147 | /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add | |
3148 | them to the unused_*_list variables, so that they can be reused. */ | |
3149 | ||
8c660648 JL |
3150 | static void |
3151 | free_pending_lists () | |
3152 | { | |
8c660648 JL |
3153 | if (current_nr_blocks <= 1) |
3154 | { | |
5a4f6418 AM |
3155 | free_INSN_LIST_list (&pending_read_insns); |
3156 | free_INSN_LIST_list (&pending_write_insns); | |
3157 | free_EXPR_LIST_list (&pending_read_mems); | |
3158 | free_EXPR_LIST_list (&pending_write_mems); | |
8c660648 JL |
3159 | } |
3160 | else | |
3161 | { | |
63de6c74 | 3162 | /* Interblock scheduling. */ |
8c660648 JL |
3163 | int bb; |
3164 | ||
3165 | for (bb = 0; bb < current_nr_blocks; bb++) | |
3166 | { | |
5a4f6418 AM |
3167 | free_INSN_LIST_list (&bb_pending_read_insns[bb]); |
3168 | free_INSN_LIST_list (&bb_pending_write_insns[bb]); | |
3169 | free_EXPR_LIST_list (&bb_pending_read_mems[bb]); | |
3170 | free_EXPR_LIST_list (&bb_pending_write_mems[bb]); | |
8c660648 JL |
3171 | } |
3172 | } | |
3173 | } | |
3174 | ||
3175 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
3176 | The MEM is a memory reference contained within INSN, which we are saving | |
3177 | so that we can do memory aliasing on it. */ | |
3178 | ||
3179 | static void | |
3180 | add_insn_mem_dependence (insn_list, mem_list, insn, mem) | |
3181 | rtx *insn_list, *mem_list, insn, mem; | |
3182 | { | |
3183 | register rtx link; | |
3184 | ||
ebb7b10b | 3185 | link = alloc_INSN_LIST (insn, *insn_list); |
8c660648 JL |
3186 | *insn_list = link; |
3187 | ||
ebb7b10b | 3188 | link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list); |
8c660648 JL |
3189 | *mem_list = link; |
3190 | ||
3191 | pending_lists_length++; | |
3192 | } | |
3193 | \f | |
3194 | ||
3195 | /* Make a dependency between every memory reference on the pending lists | |
3196 | and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush | |
3197 | the read list. */ | |
3198 | ||
3199 | static void | |
3200 | flush_pending_lists (insn, only_write) | |
3201 | rtx insn; | |
3202 | int only_write; | |
3203 | { | |
3204 | rtx u; | |
3205 | rtx link; | |
3206 | ||
3207 | while (pending_read_insns && ! only_write) | |
3208 | { | |
3209 | add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI); | |
3210 | ||
3211 | link = pending_read_insns; | |
3212 | pending_read_insns = XEXP (pending_read_insns, 1); | |
5a4f6418 | 3213 | free_INSN_LIST_node (link); |
8c660648 JL |
3214 | |
3215 | link = pending_read_mems; | |
3216 | pending_read_mems = XEXP (pending_read_mems, 1); | |
5a4f6418 | 3217 | free_EXPR_LIST_node (link); |
8c660648 JL |
3218 | } |
3219 | while (pending_write_insns) | |
3220 | { | |
3221 | add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI); | |
3222 | ||
3223 | link = pending_write_insns; | |
3224 | pending_write_insns = XEXP (pending_write_insns, 1); | |
5a4f6418 | 3225 | free_INSN_LIST_node (link); |
8c660648 JL |
3226 | |
3227 | link = pending_write_mems; | |
3228 | pending_write_mems = XEXP (pending_write_mems, 1); | |
5a4f6418 | 3229 | free_EXPR_LIST_node (link); |
8c660648 JL |
3230 | } |
3231 | pending_lists_length = 0; | |
3232 | ||
63de6c74 | 3233 | /* last_pending_memory_flush is now a list of insns. */ |
8c660648 JL |
3234 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
3235 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3236 | ||
5a4f6418 | 3237 | free_INSN_LIST_list (&last_pending_memory_flush); |
ebb7b10b | 3238 | last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3239 | } |
3240 | ||
355fca3e AB |
3241 | /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC |
3242 | rtx, X, creating all dependencies generated by the write to the | |
3243 | destination of X, and reads of everything mentioned. */ | |
8c660648 JL |
3244 | |
3245 | static void | |
3246 | sched_analyze_1 (x, insn) | |
3247 | rtx x; | |
3248 | rtx insn; | |
3249 | { | |
3250 | register int regno; | |
355fca3e | 3251 | register rtx dest = XEXP (x, 0); |
28c95eff | 3252 | enum rtx_code code = GET_CODE (x); |
8c660648 JL |
3253 | |
3254 | if (dest == 0) | |
3255 | return; | |
3256 | ||
c0222c21 DM |
3257 | if (GET_CODE (dest) == PARALLEL |
3258 | && GET_MODE (dest) == BLKmode) | |
3259 | { | |
3260 | register int i; | |
3261 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
3262 | sched_analyze_1 (XVECEXP (dest, 0, i), insn); | |
3263 | if (GET_CODE (x) == SET) | |
3264 | sched_analyze_2 (SET_SRC (x), insn); | |
3265 | return; | |
3266 | } | |
3267 | ||
8c660648 JL |
3268 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG |
3269 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3270 | { | |
3271 | if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3272 | { | |
3273 | /* The second and third arguments are values read by this insn. */ | |
3274 | sched_analyze_2 (XEXP (dest, 1), insn); | |
3275 | sched_analyze_2 (XEXP (dest, 2), insn); | |
3276 | } | |
355fca3e | 3277 | dest = XEXP (dest, 0); |
8c660648 JL |
3278 | } |
3279 | ||
3280 | if (GET_CODE (dest) == REG) | |
3281 | { | |
3282 | register int i; | |
3283 | ||
3284 | regno = REGNO (dest); | |
3285 | ||
3286 | /* A hard reg in a wide mode may really be multiple registers. | |
3287 | If so, mark all of them just like the first. */ | |
3288 | if (regno < FIRST_PSEUDO_REGISTER) | |
3289 | { | |
3290 | i = HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
3291 | while (--i >= 0) | |
3292 | { | |
3293 | rtx u; | |
3294 | ||
3295 | for (u = reg_last_uses[regno + i]; u; u = XEXP (u, 1)) | |
3296 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3297 | |
3298 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3299 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3300 | ||
63de6c74 MH |
3301 | /* Clobbers need not be ordered with respect to one |
3302 | another, but sets must be ordered with respect to a | |
3303 | pending clobber. */ | |
28c95eff RH |
3304 | if (code == SET) |
3305 | { | |
5a4f6418 | 3306 | free_INSN_LIST_list (®_last_uses[regno + i]); |
28c95eff RH |
3307 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) |
3308 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3309 | SET_REGNO_REG_SET (reg_pending_sets, regno + i); | |
3310 | } | |
3311 | else | |
3312 | SET_REGNO_REG_SET (reg_pending_clobbers, regno + i); | |
8c660648 | 3313 | |
28c95eff RH |
3314 | /* Function calls clobber all call_used regs. */ |
3315 | if (global_regs[regno + i] | |
3316 | || (code == SET && call_used_regs[regno + i])) | |
8c660648 JL |
3317 | for (u = last_function_call; u; u = XEXP (u, 1)) |
3318 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3319 | } | |
3320 | } | |
3321 | else | |
3322 | { | |
3323 | rtx u; | |
3324 | ||
3325 | for (u = reg_last_uses[regno]; u; u = XEXP (u, 1)) | |
3326 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3327 | |
3328 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3329 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3330 | ||
28c95eff | 3331 | if (code == SET) |
7399257b | 3332 | { |
5a4f6418 | 3333 | free_INSN_LIST_list (®_last_uses[regno]); |
7399257b RH |
3334 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) |
3335 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3336 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
3337 | } | |
28c95eff RH |
3338 | else |
3339 | SET_REGNO_REG_SET (reg_pending_clobbers, regno); | |
8c660648 JL |
3340 | |
3341 | /* Pseudos that are REG_EQUIV to something may be replaced | |
3342 | by that during reloading. We need only add dependencies for | |
3343 | the address in the REG_EQUIV note. */ | |
3344 | if (!reload_completed | |
3345 | && reg_known_equiv_p[regno] | |
3346 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3347 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3348 | ||
3349 | /* Don't let it cross a call after scheduling if it doesn't | |
3350 | already cross one. */ | |
3351 | ||
3352 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3353 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3354 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3355 | } | |
3356 | } | |
3357 | else if (GET_CODE (dest) == MEM) | |
3358 | { | |
3359 | /* Writing memory. */ | |
3360 | ||
3361 | if (pending_lists_length > 32) | |
3362 | { | |
3363 | /* Flush all pending reads and writes to prevent the pending lists | |
3364 | from getting any larger. Insn scheduling runs too slowly when | |
3365 | these lists get long. The number 32 was chosen because it | |
3366 | seems like a reasonable number. When compiling GCC with itself, | |
3367 | this flush occurs 8 times for sparc, and 10 times for m88k using | |
3368 | the number 32. */ | |
3369 | flush_pending_lists (insn, 0); | |
3370 | } | |
3371 | else | |
3372 | { | |
3373 | rtx u; | |
3374 | rtx pending, pending_mem; | |
3375 | ||
3376 | pending = pending_read_insns; | |
3377 | pending_mem = pending_read_mems; | |
3378 | while (pending) | |
3379 | { | |
87373fba RH |
3380 | if (anti_dependence (XEXP (pending_mem, 0), dest)) |
3381 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3382 | |
3383 | pending = XEXP (pending, 1); | |
3384 | pending_mem = XEXP (pending_mem, 1); | |
3385 | } | |
3386 | ||
3387 | pending = pending_write_insns; | |
3388 | pending_mem = pending_write_mems; | |
3389 | while (pending) | |
3390 | { | |
87373fba RH |
3391 | if (output_dependence (XEXP (pending_mem, 0), dest)) |
3392 | add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT); | |
8c660648 JL |
3393 | |
3394 | pending = XEXP (pending, 1); | |
3395 | pending_mem = XEXP (pending_mem, 1); | |
3396 | } | |
3397 | ||
3398 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3399 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3400 | ||
3401 | add_insn_mem_dependence (&pending_write_insns, &pending_write_mems, | |
3402 | insn, dest); | |
3403 | } | |
3404 | sched_analyze_2 (XEXP (dest, 0), insn); | |
3405 | } | |
3406 | ||
3407 | /* Analyze reads. */ | |
3408 | if (GET_CODE (x) == SET) | |
3409 | sched_analyze_2 (SET_SRC (x), insn); | |
3410 | } | |
3411 | ||
3412 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
3413 | ||
3414 | static void | |
3415 | sched_analyze_2 (x, insn) | |
3416 | rtx x; | |
3417 | rtx insn; | |
3418 | { | |
3419 | register int i; | |
3420 | register int j; | |
3421 | register enum rtx_code code; | |
6f7d635c | 3422 | register const char *fmt; |
8c660648 JL |
3423 | |
3424 | if (x == 0) | |
3425 | return; | |
3426 | ||
3427 | code = GET_CODE (x); | |
3428 | ||
3429 | switch (code) | |
3430 | { | |
3431 | case CONST_INT: | |
3432 | case CONST_DOUBLE: | |
3433 | case SYMBOL_REF: | |
3434 | case CONST: | |
3435 | case LABEL_REF: | |
3436 | /* Ignore constants. Note that we must handle CONST_DOUBLE here | |
3437 | because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but | |
3438 | this does not mean that this insn is using cc0. */ | |
3439 | return; | |
3440 | ||
3441 | #ifdef HAVE_cc0 | |
3442 | case CC0: | |
3443 | { | |
3444 | rtx link, prev; | |
3445 | ||
3446 | /* User of CC0 depends on immediately preceding insn. */ | |
3447 | SCHED_GROUP_P (insn) = 1; | |
3448 | ||
3449 | /* There may be a note before this insn now, but all notes will | |
3450 | be removed before we actually try to schedule the insns, so | |
3451 | it won't cause a problem later. We must avoid it here though. */ | |
3452 | prev = prev_nonnote_insn (insn); | |
3453 | ||
3454 | /* Make a copy of all dependencies on the immediately previous insn, | |
3455 | and add to this insn. This is so that all the dependencies will | |
3456 | apply to the group. Remove an explicit dependence on this insn | |
3457 | as SCHED_GROUP_P now represents it. */ | |
3458 | ||
3459 | if (find_insn_list (prev, LOG_LINKS (insn))) | |
3460 | remove_dependence (insn, prev); | |
3461 | ||
3462 | for (link = LOG_LINKS (prev); link; link = XEXP (link, 1)) | |
3463 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3464 | ||
3465 | return; | |
3466 | } | |
3467 | #endif | |
3468 | ||
3469 | case REG: | |
3470 | { | |
3471 | rtx u; | |
3472 | int regno = REGNO (x); | |
3473 | if (regno < FIRST_PSEUDO_REGISTER) | |
3474 | { | |
3475 | int i; | |
3476 | ||
3477 | i = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3478 | while (--i >= 0) | |
3479 | { | |
3480 | reg_last_uses[regno + i] | |
ebb7b10b | 3481 | = alloc_INSN_LIST (insn, reg_last_uses[regno + i]); |
8c660648 JL |
3482 | |
3483 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3484 | add_dependence (insn, XEXP (u, 0), 0); | |
3485 | ||
28c95eff RH |
3486 | /* ??? This should never happen. */ |
3487 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) | |
3488 | add_dependence (insn, XEXP (u, 0), 0); | |
3489 | ||
8c660648 JL |
3490 | if ((call_used_regs[regno + i] || global_regs[regno + i])) |
3491 | /* Function calls clobber all call_used regs. */ | |
3492 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3493 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3494 | } | |
3495 | } | |
3496 | else | |
3497 | { | |
63de6c74 MH |
3498 | reg_last_uses[regno] = alloc_INSN_LIST (insn, |
3499 | reg_last_uses[regno]); | |
8c660648 JL |
3500 | |
3501 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3502 | add_dependence (insn, XEXP (u, 0), 0); | |
3503 | ||
28c95eff RH |
3504 | /* ??? This should never happen. */ |
3505 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) | |
3506 | add_dependence (insn, XEXP (u, 0), 0); | |
3507 | ||
8c660648 JL |
3508 | /* Pseudos that are REG_EQUIV to something may be replaced |
3509 | by that during reloading. We need only add dependencies for | |
3510 | the address in the REG_EQUIV note. */ | |
3511 | if (!reload_completed | |
3512 | && reg_known_equiv_p[regno] | |
3513 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3514 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3515 | ||
3516 | /* If the register does not already cross any calls, then add this | |
3517 | insn to the sched_before_next_call list so that it will still | |
3518 | not cross calls after scheduling. */ | |
3519 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3520 | add_dependence (sched_before_next_call, insn, REG_DEP_ANTI); | |
3521 | } | |
3522 | return; | |
3523 | } | |
3524 | ||
3525 | case MEM: | |
3526 | { | |
3527 | /* Reading memory. */ | |
3528 | rtx u; | |
3529 | rtx pending, pending_mem; | |
3530 | ||
3531 | pending = pending_read_insns; | |
3532 | pending_mem = pending_read_mems; | |
3533 | while (pending) | |
3534 | { | |
87373fba RH |
3535 | if (read_dependence (XEXP (pending_mem, 0), x)) |
3536 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3537 | |
3538 | pending = XEXP (pending, 1); | |
3539 | pending_mem = XEXP (pending_mem, 1); | |
3540 | } | |
3541 | ||
3542 | pending = pending_write_insns; | |
3543 | pending_mem = pending_write_mems; | |
3544 | while (pending) | |
3545 | { | |
87373fba RH |
3546 | if (true_dependence (XEXP (pending_mem, 0), VOIDmode, |
3547 | x, rtx_varies_p)) | |
3548 | add_dependence (insn, XEXP (pending, 0), 0); | |
8c660648 JL |
3549 | |
3550 | pending = XEXP (pending, 1); | |
3551 | pending_mem = XEXP (pending_mem, 1); | |
3552 | } | |
3553 | ||
3554 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3555 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3556 | ||
3557 | /* Always add these dependencies to pending_reads, since | |
3558 | this insn may be followed by a write. */ | |
3559 | add_insn_mem_dependence (&pending_read_insns, &pending_read_mems, | |
3560 | insn, x); | |
3561 | ||
3562 | /* Take advantage of tail recursion here. */ | |
3563 | sched_analyze_2 (XEXP (x, 0), insn); | |
3564 | return; | |
3565 | } | |
3566 | ||
e0cd0770 JC |
3567 | /* Force pending stores to memory in case a trap handler needs them. */ |
3568 | case TRAP_IF: | |
3569 | flush_pending_lists (insn, 1); | |
3570 | break; | |
3571 | ||
8c660648 JL |
3572 | case ASM_OPERANDS: |
3573 | case ASM_INPUT: | |
3574 | case UNSPEC_VOLATILE: | |
8c660648 JL |
3575 | { |
3576 | rtx u; | |
3577 | ||
3578 | /* Traditional and volatile asm instructions must be considered to use | |
3579 | and clobber all hard registers, all pseudo-registers and all of | |
3580 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
3581 | ||
3582 | Consider for instance a volatile asm that changes the fpu rounding | |
3583 | mode. An insn should not be moved across this even if it only uses | |
3584 | pseudo-regs because it might give an incorrectly rounded result. */ | |
3585 | if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) | |
3586 | { | |
3587 | int max_reg = max_reg_num (); | |
3588 | for (i = 0; i < max_reg; i++) | |
3589 | { | |
3590 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3591 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3592 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3593 | |
8c660648 JL |
3594 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3595 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3596 | |
3597 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3598 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3599 | } |
3600 | reg_pending_sets_all = 1; | |
3601 | ||
3602 | flush_pending_lists (insn, 0); | |
3603 | } | |
3604 | ||
3605 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
3606 | We can not just fall through here since then we would be confused | |
3607 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
3608 | traditional asms unlike their normal usage. */ | |
3609 | ||
3610 | if (code == ASM_OPERANDS) | |
3611 | { | |
3612 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
3613 | sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn); | |
3614 | return; | |
3615 | } | |
3616 | break; | |
3617 | } | |
3618 | ||
3619 | case PRE_DEC: | |
3620 | case POST_DEC: | |
3621 | case PRE_INC: | |
3622 | case POST_INC: | |
3623 | /* These both read and modify the result. We must handle them as writes | |
3624 | to get proper dependencies for following instructions. We must handle | |
3625 | them as reads to get proper dependencies from this to previous | |
3626 | instructions. Thus we need to pass them to both sched_analyze_1 | |
3627 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
3628 | to get the proper antecedent for the read. */ | |
3629 | sched_analyze_2 (XEXP (x, 0), insn); | |
3630 | sched_analyze_1 (x, insn); | |
3631 | return; | |
5835e573 KG |
3632 | |
3633 | default: | |
3634 | break; | |
8c660648 JL |
3635 | } |
3636 | ||
3637 | /* Other cases: walk the insn. */ | |
3638 | fmt = GET_RTX_FORMAT (code); | |
3639 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3640 | { | |
3641 | if (fmt[i] == 'e') | |
3642 | sched_analyze_2 (XEXP (x, i), insn); | |
3643 | else if (fmt[i] == 'E') | |
3644 | for (j = 0; j < XVECLEN (x, i); j++) | |
3645 | sched_analyze_2 (XVECEXP (x, i, j), insn); | |
3646 | } | |
3647 | } | |
3648 | ||
3649 | /* Analyze an INSN with pattern X to find all dependencies. */ | |
3650 | ||
3651 | static void | |
3652 | sched_analyze_insn (x, insn, loop_notes) | |
3653 | rtx x, insn; | |
3654 | rtx loop_notes; | |
3655 | { | |
3656 | register RTX_CODE code = GET_CODE (x); | |
3657 | rtx link; | |
3658 | int maxreg = max_reg_num (); | |
3659 | int i; | |
3660 | ||
3661 | if (code == SET || code == CLOBBER) | |
3662 | sched_analyze_1 (x, insn); | |
3663 | else if (code == PARALLEL) | |
3664 | { | |
3665 | register int i; | |
3666 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
3667 | { | |
3668 | code = GET_CODE (XVECEXP (x, 0, i)); | |
3669 | if (code == SET || code == CLOBBER) | |
3670 | sched_analyze_1 (XVECEXP (x, 0, i), insn); | |
3671 | else | |
3672 | sched_analyze_2 (XVECEXP (x, 0, i), insn); | |
3673 | } | |
3674 | } | |
3675 | else | |
3676 | sched_analyze_2 (x, insn); | |
3677 | ||
3678 | /* Mark registers CLOBBERED or used by called function. */ | |
3679 | if (GET_CODE (insn) == CALL_INSN) | |
3680 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
3681 | { | |
3682 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
3683 | sched_analyze_1 (XEXP (link, 0), insn); | |
3684 | else | |
3685 | sched_analyze_2 (XEXP (link, 0), insn); | |
3686 | } | |
3687 | ||
1f1ed00c JL |
3688 | /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic |
3689 | block, then we must be sure that no instructions are scheduled across it. | |
8c660648 JL |
3690 | Otherwise, the reg_n_refs info (which depends on loop_depth) would |
3691 | become incorrect. */ | |
3692 | ||
3693 | if (loop_notes) | |
3694 | { | |
3695 | int max_reg = max_reg_num (); | |
1f1ed00c | 3696 | int schedule_barrier_found = 0; |
8c660648 JL |
3697 | rtx link; |
3698 | ||
1f1ed00c JL |
3699 | /* Update loop_notes with any notes from this insn. Also determine |
3700 | if any of the notes on the list correspond to instruction scheduling | |
3701 | barriers (loop, eh & setjmp notes, but not range notes. */ | |
8c660648 JL |
3702 | link = loop_notes; |
3703 | while (XEXP (link, 1)) | |
1f1ed00c | 3704 | { |
54c3cf4b JL |
3705 | if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG |
3706 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END | |
3707 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG | |
3708 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END | |
3709 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP) | |
1f1ed00c JL |
3710 | schedule_barrier_found = 1; |
3711 | ||
3712 | link = XEXP (link, 1); | |
3713 | } | |
8c660648 JL |
3714 | XEXP (link, 1) = REG_NOTES (insn); |
3715 | REG_NOTES (insn) = loop_notes; | |
1f1ed00c JL |
3716 | |
3717 | /* Add dependencies if a scheduling barrier was found. */ | |
3718 | if (schedule_barrier_found) | |
3719 | { | |
3720 | for (i = 0; i < max_reg; i++) | |
3721 | { | |
3722 | rtx u; | |
3723 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3724 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3725 | free_INSN_LIST_list (®_last_uses[i]); |
1f1ed00c | 3726 | |
1f1ed00c JL |
3727 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3728 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3729 | |
3730 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3731 | add_dependence (insn, XEXP (u, 0), 0); | |
1f1ed00c JL |
3732 | } |
3733 | reg_pending_sets_all = 1; | |
3734 | ||
3735 | flush_pending_lists (insn, 0); | |
3736 | } | |
3737 | ||
8c660648 JL |
3738 | } |
3739 | ||
63de6c74 | 3740 | /* Accumulate clobbers until the next set so that it will be output dependent |
28c95eff | 3741 | on all of them. At the next set we can clear the clobber list, since |
63de6c74 | 3742 | subsequent sets will be output dependent on it. */ |
8c660648 JL |
3743 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, |
3744 | { | |
5a4f6418 AM |
3745 | free_INSN_LIST_list (®_last_sets[i]); |
3746 | free_INSN_LIST_list (®_last_clobbers[i]); | |
8c660648 | 3747 | reg_last_sets[i] |
ebb7b10b | 3748 | = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 | 3749 | }); |
28c95eff RH |
3750 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, |
3751 | { | |
3752 | reg_last_clobbers[i] | |
63de6c74 MH |
3753 | = alloc_INSN_LIST (insn, |
3754 | reg_last_clobbers[i]); | |
28c95eff | 3755 | }); |
8c660648 | 3756 | CLEAR_REG_SET (reg_pending_sets); |
28c95eff | 3757 | CLEAR_REG_SET (reg_pending_clobbers); |
8c660648 JL |
3758 | |
3759 | if (reg_pending_sets_all) | |
3760 | { | |
3761 | for (i = 0; i < maxreg; i++) | |
ebb7b10b | 3762 | { |
5a4f6418 | 3763 | free_INSN_LIST_list (®_last_sets[i]); |
c88e8206 | 3764 | free_INSN_LIST_list (®_last_clobbers[i]); |
ebb7b10b RH |
3765 | reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX); |
3766 | } | |
8c660648 JL |
3767 | |
3768 | reg_pending_sets_all = 0; | |
3769 | } | |
3770 | ||
3771 | /* Handle function calls and function returns created by the epilogue | |
3772 | threading code. */ | |
3773 | if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
3774 | { | |
3775 | rtx dep_insn; | |
3776 | rtx prev_dep_insn; | |
3777 | ||
3778 | /* When scheduling instructions, we make sure calls don't lose their | |
3779 | accompanying USE insns by depending them one on another in order. | |
3780 | ||
3781 | Also, we must do the same thing for returns created by the epilogue | |
3782 | threading code. Note this code works only in this special case, | |
3783 | because other passes make no guarantee that they will never emit | |
3784 | an instruction between a USE and a RETURN. There is such a guarantee | |
3785 | for USE instructions immediately before a call. */ | |
3786 | ||
3787 | prev_dep_insn = insn; | |
3788 | dep_insn = PREV_INSN (insn); | |
3789 | while (GET_CODE (dep_insn) == INSN | |
3790 | && GET_CODE (PATTERN (dep_insn)) == USE | |
3791 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG) | |
3792 | { | |
3793 | SCHED_GROUP_P (prev_dep_insn) = 1; | |
3794 | ||
3795 | /* Make a copy of all dependencies on dep_insn, and add to insn. | |
3796 | This is so that all of the dependencies will apply to the | |
3797 | group. */ | |
3798 | ||
3799 | for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1)) | |
3800 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3801 | ||
3802 | prev_dep_insn = dep_insn; | |
3803 | dep_insn = PREV_INSN (dep_insn); | |
3804 | } | |
3805 | } | |
3806 | } | |
3807 | ||
3808 | /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS | |
3809 | for every dependency. */ | |
3810 | ||
3811 | static void | |
3812 | sched_analyze (head, tail) | |
3813 | rtx head, tail; | |
3814 | { | |
3815 | register rtx insn; | |
3816 | register rtx u; | |
3817 | rtx loop_notes = 0; | |
3818 | ||
3819 | for (insn = head;; insn = NEXT_INSN (insn)) | |
3820 | { | |
3821 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) | |
3822 | { | |
87373fba RH |
3823 | /* Clear out the stale LOG_LINKS from flow. */ |
3824 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3825 | ||
63de6c74 MH |
3826 | /* Make each JUMP_INSN a scheduling barrier for memory |
3827 | references. */ | |
062ae7ed JL |
3828 | if (GET_CODE (insn) == JUMP_INSN) |
3829 | last_pending_memory_flush | |
3830 | = alloc_INSN_LIST (insn, last_pending_memory_flush); | |
8c660648 JL |
3831 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); |
3832 | loop_notes = 0; | |
3833 | } | |
3834 | else if (GET_CODE (insn) == CALL_INSN) | |
3835 | { | |
3836 | rtx x; | |
3837 | register int i; | |
3838 | ||
3839 | CANT_MOVE (insn) = 1; | |
3840 | ||
87373fba RH |
3841 | /* Clear out the stale LOG_LINKS from flow. */ |
3842 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3843 | ||
8c660648 JL |
3844 | /* Any instruction using a hard register which may get clobbered |
3845 | by a call needs to be marked as dependent on this call. | |
3846 | This prevents a use of a hard return reg from being moved | |
3847 | past a void call (i.e. it does not explicitly set the hard | |
3848 | return reg). */ | |
3849 | ||
3850 | /* If this call is followed by a NOTE_INSN_SETJMP, then assume that | |
3851 | all registers, not just hard registers, may be clobbered by this | |
3852 | call. */ | |
3853 | ||
3854 | /* Insn, being a CALL_INSN, magically depends on | |
3855 | `last_function_call' already. */ | |
3856 | ||
3857 | if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE | |
3858 | && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP) | |
3859 | { | |
3860 | int max_reg = max_reg_num (); | |
3861 | for (i = 0; i < max_reg; i++) | |
3862 | { | |
3863 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3864 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3865 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3866 | |
8c660648 JL |
3867 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3868 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3869 | |
3870 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3871 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3872 | } |
3873 | reg_pending_sets_all = 1; | |
3874 | ||
c46a37c4 | 3875 | /* Add a pair of REG_SAVE_NOTEs which we will later |
8c660648 JL |
3876 | convert back into a NOTE_INSN_SETJMP note. See |
3877 | reemit_notes for why we use a pair of NOTEs. */ | |
c46a37c4 | 3878 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3879 | GEN_INT (0), |
3880 | REG_NOTES (insn)); | |
c46a37c4 | 3881 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3882 | GEN_INT (NOTE_INSN_SETJMP), |
3883 | REG_NOTES (insn)); | |
8c660648 JL |
3884 | } |
3885 | else | |
3886 | { | |
3887 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3888 | if (call_used_regs[i] || global_regs[i]) | |
3889 | { | |
3890 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3891 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 | 3892 | |
8c660648 JL |
3893 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3894 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3895 | ||
c1cb76e9 | 3896 | SET_REGNO_REG_SET (reg_pending_clobbers, i); |
8c660648 JL |
3897 | } |
3898 | } | |
3899 | ||
3900 | /* For each insn which shouldn't cross a call, add a dependence | |
3901 | between that insn and this call insn. */ | |
3902 | x = LOG_LINKS (sched_before_next_call); | |
3903 | while (x) | |
3904 | { | |
3905 | add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI); | |
3906 | x = XEXP (x, 1); | |
3907 | } | |
2a780534 | 3908 | free_INSN_LIST_list (&LOG_LINKS (sched_before_next_call)); |
8c660648 JL |
3909 | |
3910 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); | |
3911 | loop_notes = 0; | |
3912 | ||
3913 | /* In the absence of interprocedural alias analysis, we must flush | |
3914 | all pending reads and writes, and start new dependencies starting | |
3915 | from here. But only flush writes for constant calls (which may | |
3916 | be passed a pointer to something we haven't written yet). */ | |
3917 | flush_pending_lists (insn, CONST_CALL_P (insn)); | |
3918 | ||
3919 | /* Depend this function call (actually, the user of this | |
3920 | function call) on all hard register clobberage. */ | |
3921 | ||
63de6c74 | 3922 | /* last_function_call is now a list of insns. */ |
5a4f6418 | 3923 | free_INSN_LIST_list(&last_function_call); |
ebb7b10b | 3924 | last_function_call = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3925 | } |
3926 | ||
63de6c74 MH |
3927 | /* See comments on reemit_notes as to why we do this. |
3928 | ??? Actually, the reemit_notes just say what is done, not why. */ | |
6dfdecdb RH |
3929 | |
3930 | else if (GET_CODE (insn) == NOTE | |
3931 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START | |
3932 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END)) | |
3933 | { | |
c46a37c4 | 3934 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, NOTE_RANGE_INFO (insn), |
6dfdecdb | 3935 | loop_notes); |
c46a37c4 | 3936 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
6dfdecdb RH |
3937 | GEN_INT (NOTE_LINE_NUMBER (insn)), |
3938 | loop_notes); | |
3939 | } | |
8c660648 JL |
3940 | else if (GET_CODE (insn) == NOTE |
3941 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG | |
3942 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END | |
3943 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG | |
3944 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END | |
3945 | || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP | |
3946 | && GET_CODE (PREV_INSN (insn)) != CALL_INSN))) | |
3947 | { | |
f5db61ef | 3948 | rtx rtx_region; |
7bd41ea6 | 3949 | |
1a4450c7 MM |
3950 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG |
3951 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END) | |
f5db61ef | 3952 | rtx_region = GEN_INT (NOTE_EH_HANDLER (insn)); |
7bd41ea6 | 3953 | else |
f5db61ef | 3954 | rtx_region = GEN_INT (0); |
1a4450c7 | 3955 | |
c46a37c4 | 3956 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
f5db61ef | 3957 | rtx_region, |
7bd41ea6 | 3958 | loop_notes); |
c46a37c4 | 3959 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3960 | GEN_INT (NOTE_LINE_NUMBER (insn)), |
3961 | loop_notes); | |
8c660648 JL |
3962 | CONST_CALL_P (loop_notes) = CONST_CALL_P (insn); |
3963 | } | |
3964 | ||
3965 | if (insn == tail) | |
3966 | return; | |
3967 | } | |
3968 | abort (); | |
3969 | } | |
3970 | \f | |
8c660648 JL |
3971 | /* Macros and functions for keeping the priority queue sorted, and |
3972 | dealing with queueing and dequeueing of instructions. */ | |
3973 | ||
3974 | #define SCHED_SORT(READY, N_READY) \ | |
3975 | do { if ((N_READY) == 2) \ | |
3976 | swap_sort (READY, N_READY); \ | |
3977 | else if ((N_READY) > 2) \ | |
3978 | qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ | |
3979 | while (0) | |
3980 | ||
3981 | /* Returns a positive value if x is preferred; returns a negative value if | |
3982 | y is preferred. Should never return 0, since that will make the sort | |
3983 | unstable. */ | |
3984 | ||
3985 | static int | |
3986 | rank_for_schedule (x, y) | |
e1b6684c KG |
3987 | const PTR x; |
3988 | const PTR y; | |
8c660648 | 3989 | { |
01c7f350 MM |
3990 | rtx tmp = *(rtx *)y; |
3991 | rtx tmp2 = *(rtx *)x; | |
8c660648 | 3992 | rtx link; |
2db45993 | 3993 | int tmp_class, tmp2_class, depend_count1, depend_count2; |
8c660648 JL |
3994 | int val, priority_val, spec_val, prob_val, weight_val; |
3995 | ||
3996 | ||
63de6c74 | 3997 | /* Prefer insn with higher priority. */ |
8c660648 JL |
3998 | priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp); |
3999 | if (priority_val) | |
4000 | return priority_val; | |
4001 | ||
63de6c74 | 4002 | /* Prefer an insn with smaller contribution to registers-pressure. */ |
8c660648 JL |
4003 | if (!reload_completed && |
4004 | (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2))) | |
4005 | return (weight_val); | |
4006 | ||
63de6c74 | 4007 | /* Some comparison make sense in interblock scheduling only. */ |
8c660648 JL |
4008 | if (INSN_BB (tmp) != INSN_BB (tmp2)) |
4009 | { | |
63de6c74 | 4010 | /* Prefer an inblock motion on an interblock motion. */ |
8c660648 JL |
4011 | if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb)) |
4012 | return 1; | |
4013 | if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb)) | |
4014 | return -1; | |
4015 | ||
63de6c74 | 4016 | /* Prefer a useful motion on a speculative one. */ |
8c660648 JL |
4017 | if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2))) |
4018 | return (spec_val); | |
4019 | ||
63de6c74 | 4020 | /* Prefer a more probable (speculative) insn. */ |
8c660648 JL |
4021 | prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp); |
4022 | if (prob_val) | |
4023 | return (prob_val); | |
4024 | } | |
4025 | ||
63de6c74 | 4026 | /* Compare insns based on their relation to the last-scheduled-insn. */ |
8c660648 JL |
4027 | if (last_scheduled_insn) |
4028 | { | |
4029 | /* Classify the instructions into three classes: | |
4030 | 1) Data dependent on last schedule insn. | |
4031 | 2) Anti/Output dependent on last scheduled insn. | |
4032 | 3) Independent of last scheduled insn, or has latency of one. | |
4033 | Choose the insn from the highest numbered class if different. */ | |
4034 | link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn)); | |
4035 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1) | |
4036 | tmp_class = 3; | |
4037 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4038 | tmp_class = 1; | |
4039 | else | |
4040 | tmp_class = 2; | |
4041 | ||
4042 | link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn)); | |
4043 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1) | |
4044 | tmp2_class = 3; | |
4045 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4046 | tmp2_class = 1; | |
4047 | else | |
4048 | tmp2_class = 2; | |
4049 | ||
4050 | if ((val = tmp2_class - tmp_class)) | |
4051 | return val; | |
4052 | } | |
4053 | ||
2db45993 JL |
4054 | /* Prefer the insn which has more later insns that depend on it. |
4055 | This gives the scheduler more freedom when scheduling later | |
4056 | instructions at the expense of added register pressure. */ | |
4057 | depend_count1 = 0; | |
4058 | for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1)) | |
4059 | depend_count1++; | |
4060 | ||
4061 | depend_count2 = 0; | |
4062 | for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1)) | |
4063 | depend_count2++; | |
4064 | ||
4065 | val = depend_count2 - depend_count1; | |
4066 | if (val) | |
4067 | return val; | |
4068 | ||
8c660648 JL |
4069 | /* If insns are equally good, sort by INSN_LUID (original insn order), |
4070 | so that we make the sort stable. This minimizes instruction movement, | |
4071 | thus minimizing sched's effect on debugging and cross-jumping. */ | |
4072 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
4073 | } | |
4074 | ||
4075 | /* Resort the array A in which only element at index N may be out of order. */ | |
4076 | ||
cbb13457 | 4077 | HAIFA_INLINE static void |
8c660648 JL |
4078 | swap_sort (a, n) |
4079 | rtx *a; | |
4080 | int n; | |
4081 | { | |
4082 | rtx insn = a[n - 1]; | |
4083 | int i = n - 2; | |
4084 | ||
4085 | while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0) | |
4086 | { | |
4087 | a[i + 1] = a[i]; | |
4088 | i -= 1; | |
4089 | } | |
4090 | a[i + 1] = insn; | |
4091 | } | |
4092 | ||
4093 | static int max_priority; | |
4094 | ||
4095 | /* Add INSN to the insn queue so that it can be executed at least | |
4096 | N_CYCLES after the currently executing insn. Preserve insns | |
4097 | chain for debugging purposes. */ | |
4098 | ||
cbb13457 | 4099 | HAIFA_INLINE static void |
8c660648 JL |
4100 | queue_insn (insn, n_cycles) |
4101 | rtx insn; | |
4102 | int n_cycles; | |
4103 | { | |
4104 | int next_q = NEXT_Q_AFTER (q_ptr, n_cycles); | |
ebb7b10b | 4105 | rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]); |
8c660648 JL |
4106 | insn_queue[next_q] = link; |
4107 | q_size += 1; | |
4108 | ||
4109 | if (sched_verbose >= 2) | |
4110 | { | |
4111 | fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn)); | |
4112 | ||
4113 | if (INSN_BB (insn) != target_bb) | |
c88e8206 | 4114 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4115 | |
4116 | fprintf (dump, "queued for %d cycles.\n", n_cycles); | |
4117 | } | |
4118 | ||
4119 | } | |
4120 | ||
8c660648 | 4121 | /* PREV is an insn that is ready to execute. Adjust its priority if that |
c46a37c4 RH |
4122 | will help shorten or lengthen register lifetimes as appropriate. Also |
4123 | provide a hook for the target to tweek itself. */ | |
8c660648 | 4124 | |
cbb13457 | 4125 | HAIFA_INLINE static void |
8c660648 | 4126 | adjust_priority (prev) |
c46a37c4 | 4127 | rtx prev ATTRIBUTE_UNUSED; |
8c660648 | 4128 | { |
c46a37c4 RH |
4129 | /* ??? There used to be code here to try and estimate how an insn |
4130 | affected register lifetimes, but it did it by looking at REG_DEAD | |
4131 | notes, which we removed in schedule_region. Nor did it try to | |
4132 | take into account register pressure or anything useful like that. | |
8c660648 | 4133 | |
c46a37c4 | 4134 | Revisit when we have a machine model to work with and not before. */ |
197043f5 | 4135 | |
8c660648 | 4136 | #ifdef ADJUST_PRIORITY |
197043f5 | 4137 | ADJUST_PRIORITY (prev); |
8c660648 | 4138 | #endif |
8c660648 JL |
4139 | } |
4140 | ||
4bdc8810 RH |
4141 | /* Clock at which the previous instruction was issued. */ |
4142 | static int last_clock_var; | |
4143 | ||
8c660648 JL |
4144 | /* INSN is the "currently executing insn". Launch each insn which was |
4145 | waiting on INSN. READY is a vector of insns which are ready to fire. | |
4146 | N_READY is the number of elements in READY. CLOCK is the current | |
4147 | cycle. */ | |
4148 | ||
4149 | static int | |
4150 | schedule_insn (insn, ready, n_ready, clock) | |
4151 | rtx insn; | |
4152 | rtx *ready; | |
4153 | int n_ready; | |
4154 | int clock; | |
4155 | { | |
4156 | rtx link; | |
4157 | int unit; | |
4158 | ||
4159 | unit = insn_unit (insn); | |
4160 | ||
4161 | if (sched_verbose >= 2) | |
4162 | { | |
63de6c74 MH |
4163 | fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", |
4164 | INSN_UID (insn)); | |
8c660648 JL |
4165 | insn_print_units (insn); |
4166 | fprintf (dump, "\n"); | |
4167 | } | |
4168 | ||
4169 | if (sched_verbose && unit == -1) | |
4170 | visualize_no_unit (insn); | |
4171 | ||
4172 | if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose) | |
4173 | schedule_unit (unit, insn, clock); | |
4174 | ||
4175 | if (INSN_DEPEND (insn) == 0) | |
4176 | return n_ready; | |
4177 | ||
4178 | /* This is used by the function adjust_priority above. */ | |
4179 | if (n_ready > 0) | |
4180 | max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn)); | |
4181 | else | |
4182 | max_priority = INSN_PRIORITY (insn); | |
4183 | ||
4184 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
4185 | { | |
4186 | rtx next = XEXP (link, 0); | |
4187 | int cost = insn_cost (insn, link, next); | |
4188 | ||
4189 | INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost); | |
4190 | ||
4191 | if ((INSN_DEP_COUNT (next) -= 1) == 0) | |
4192 | { | |
4193 | int effective_cost = INSN_TICK (next) - clock; | |
4194 | ||
4195 | /* For speculative insns, before inserting to ready/queue, | |
63de6c74 | 4196 | check live, exception-free, and issue-delay. */ |
8c660648 JL |
4197 | if (INSN_BB (next) != target_bb |
4198 | && (!IS_VALID (INSN_BB (next)) | |
4199 | || CANT_MOVE (next) | |
4200 | || (IS_SPECULATIVE_INSN (next) | |
4201 | && (insn_issue_delay (next) > 3 | |
5835e573 | 4202 | || !check_live (next, INSN_BB (next)) |
8c660648 JL |
4203 | || !is_exception_free (next, INSN_BB (next), target_bb))))) |
4204 | continue; | |
4205 | ||
4206 | if (sched_verbose >= 2) | |
4207 | { | |
63de6c74 MH |
4208 | fprintf (dump, ";;\t\tdependences resolved: insn %d ", |
4209 | INSN_UID (next)); | |
8c660648 JL |
4210 | |
4211 | if (current_nr_blocks > 1 && INSN_BB (next) != target_bb) | |
c88e8206 | 4212 | fprintf (dump, "/b%d ", BLOCK_NUM (next)); |
8c660648 | 4213 | |
197043f5 | 4214 | if (effective_cost < 1) |
8c660648 JL |
4215 | fprintf (dump, "into ready\n"); |
4216 | else | |
4217 | fprintf (dump, "into queue with cost=%d\n", effective_cost); | |
4218 | } | |
4219 | ||
4220 | /* Adjust the priority of NEXT and either put it on the ready | |
4221 | list or queue it. */ | |
4222 | adjust_priority (next); | |
197043f5 | 4223 | if (effective_cost < 1) |
8c660648 JL |
4224 | ready[n_ready++] = next; |
4225 | else | |
4226 | queue_insn (next, effective_cost); | |
4227 | } | |
4228 | } | |
4229 | ||
4bdc8810 RH |
4230 | /* Annotate the instruction with issue information -- TImode |
4231 | indicates that the instruction is expected not to be able | |
4232 | to issue on the same cycle as the previous insn. A machine | |
4233 | may use this information to decide how the instruction should | |
4234 | be aligned. */ | |
4235 | if (reload_completed && issue_rate > 1) | |
4236 | { | |
4237 | PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode); | |
4238 | last_clock_var = clock; | |
4239 | } | |
4240 | ||
8c660648 JL |
4241 | return n_ready; |
4242 | } | |
4243 | ||
63de6c74 | 4244 | /* Functions for handling of notes. */ |
8c660648 JL |
4245 | |
4246 | /* Delete notes beginning with INSN and put them in the chain | |
4247 | of notes ended by NOTE_LIST. | |
4248 | Returns the insn following the notes. */ | |
4249 | ||
4250 | static rtx | |
4251 | unlink_other_notes (insn, tail) | |
4252 | rtx insn, tail; | |
4253 | { | |
4254 | rtx prev = PREV_INSN (insn); | |
4255 | ||
4256 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4257 | { | |
4258 | rtx next = NEXT_INSN (insn); | |
4259 | /* Delete the note from its current position. */ | |
4260 | if (prev) | |
4261 | NEXT_INSN (prev) = next; | |
4262 | if (next) | |
4263 | PREV_INSN (next) = prev; | |
4264 | ||
c46a37c4 | 4265 | /* See sched_analyze to see how these are handled. */ |
8c660648 JL |
4266 | if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP |
4267 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG | |
4268 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END | |
0dfa1860 MM |
4269 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START |
4270 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END | |
8c660648 JL |
4271 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG |
4272 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END) | |
4273 | { | |
4274 | /* Insert the note at the end of the notes list. */ | |
4275 | PREV_INSN (insn) = note_list; | |
4276 | if (note_list) | |
4277 | NEXT_INSN (note_list) = insn; | |
4278 | note_list = insn; | |
4279 | } | |
4280 | ||
4281 | insn = next; | |
4282 | } | |
4283 | return insn; | |
4284 | } | |
4285 | ||
4286 | /* Delete line notes beginning with INSN. Record line-number notes so | |
4287 | they can be reused. Returns the insn following the notes. */ | |
4288 | ||
4289 | static rtx | |
4290 | unlink_line_notes (insn, tail) | |
4291 | rtx insn, tail; | |
4292 | { | |
4293 | rtx prev = PREV_INSN (insn); | |
4294 | ||
4295 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4296 | { | |
4297 | rtx next = NEXT_INSN (insn); | |
4298 | ||
4299 | if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0) | |
4300 | { | |
4301 | /* Delete the note from its current position. */ | |
4302 | if (prev) | |
4303 | NEXT_INSN (prev) = next; | |
4304 | if (next) | |
4305 | PREV_INSN (next) = prev; | |
4306 | ||
4307 | /* Record line-number notes so they can be reused. */ | |
4308 | LINE_NOTE (insn) = insn; | |
4309 | } | |
4310 | else | |
4311 | prev = insn; | |
4312 | ||
4313 | insn = next; | |
4314 | } | |
4315 | return insn; | |
4316 | } | |
4317 | ||
4318 | /* Return the head and tail pointers of BB. */ | |
4319 | ||
cbb13457 | 4320 | HAIFA_INLINE static void |
49c3bb12 RH |
4321 | get_block_head_tail (b, headp, tailp) |
4322 | int b; | |
8c660648 JL |
4323 | rtx *headp; |
4324 | rtx *tailp; | |
4325 | { | |
4326 | ||
55d89719 TK |
4327 | rtx head; |
4328 | rtx tail; | |
8c660648 JL |
4329 | |
4330 | /* HEAD and TAIL delimit the basic block being scheduled. */ | |
3b413743 RH |
4331 | head = BLOCK_HEAD (b); |
4332 | tail = BLOCK_END (b); | |
8c660648 JL |
4333 | |
4334 | /* Don't include any notes or labels at the beginning of the | |
4335 | basic block, or notes at the ends of basic blocks. */ | |
4336 | while (head != tail) | |
4337 | { | |
4338 | if (GET_CODE (head) == NOTE) | |
4339 | head = NEXT_INSN (head); | |
4340 | else if (GET_CODE (tail) == NOTE) | |
4341 | tail = PREV_INSN (tail); | |
4342 | else if (GET_CODE (head) == CODE_LABEL) | |
4343 | head = NEXT_INSN (head); | |
4344 | else | |
4345 | break; | |
4346 | } | |
4347 | ||
4348 | *headp = head; | |
4349 | *tailp = tail; | |
4350 | } | |
4351 | ||
49c3bb12 RH |
4352 | HAIFA_INLINE static void |
4353 | get_bb_head_tail (bb, headp, tailp) | |
4354 | int bb; | |
4355 | rtx *headp; | |
4356 | rtx *tailp; | |
4357 | { | |
4358 | get_block_head_tail (BB_TO_BLOCK (bb), headp, tailp); | |
4359 | } | |
4360 | ||
8c660648 JL |
4361 | /* Delete line notes from bb. Save them so they can be later restored |
4362 | (in restore_line_notes ()). */ | |
4363 | ||
4364 | static void | |
4365 | rm_line_notes (bb) | |
4366 | int bb; | |
4367 | { | |
4368 | rtx next_tail; | |
4369 | rtx tail; | |
4370 | rtx head; | |
4371 | rtx insn; | |
4372 | ||
49c3bb12 | 4373 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
4374 | |
4375 | if (head == tail | |
4376 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
4377 | return; | |
4378 | ||
4379 | next_tail = NEXT_INSN (tail); | |
4380 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4381 | { | |
4382 | rtx prev; | |
4383 | ||
4384 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4385 | This is needed to keep the debugger from | |
4386 | getting completely deranged. */ | |
4387 | if (GET_CODE (insn) == NOTE) | |
4388 | { | |
4389 | prev = insn; | |
4390 | insn = unlink_line_notes (insn, next_tail); | |
4391 | ||
4392 | if (prev == tail) | |
4393 | abort (); | |
4394 | if (prev == head) | |
4395 | abort (); | |
4396 | if (insn == next_tail) | |
4397 | abort (); | |
4398 | } | |
4399 | } | |
4400 | } | |
4401 | ||
4402 | /* Save line number notes for each insn in bb. */ | |
4403 | ||
4404 | static void | |
4405 | save_line_notes (bb) | |
4406 | int bb; | |
4407 | { | |
4408 | rtx head, tail; | |
4409 | rtx next_tail; | |
4410 | ||
4411 | /* We must use the true line number for the first insn in the block | |
4412 | that was computed and saved at the start of this pass. We can't | |
4413 | use the current line number, because scheduling of the previous | |
4414 | block may have changed the current line number. */ | |
4415 | ||
4416 | rtx line = line_note_head[BB_TO_BLOCK (bb)]; | |
4417 | rtx insn; | |
4418 | ||
49c3bb12 | 4419 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
4420 | next_tail = NEXT_INSN (tail); |
4421 | ||
3b413743 | 4422 | for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb)); |
8c660648 JL |
4423 | insn != next_tail; |
4424 | insn = NEXT_INSN (insn)) | |
4425 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4426 | line = insn; | |
4427 | else | |
4428 | LINE_NOTE (insn) = line; | |
4429 | } | |
4430 | ||
4431 | ||
4432 | /* After bb was scheduled, insert line notes into the insns list. */ | |
4433 | ||
4434 | static void | |
4435 | restore_line_notes (bb) | |
4436 | int bb; | |
4437 | { | |
4438 | rtx line, note, prev, new; | |
4439 | int added_notes = 0; | |
4440 | int b; | |
4441 | rtx head, next_tail, insn; | |
4442 | ||
4443 | b = BB_TO_BLOCK (bb); | |
4444 | ||
3b413743 RH |
4445 | head = BLOCK_HEAD (b); |
4446 | next_tail = NEXT_INSN (BLOCK_END (b)); | |
8c660648 JL |
4447 | |
4448 | /* Determine the current line-number. We want to know the current | |
4449 | line number of the first insn of the block here, in case it is | |
4450 | different from the true line number that was saved earlier. If | |
4451 | different, then we need a line number note before the first insn | |
4452 | of this block. If it happens to be the same, then we don't want to | |
4453 | emit another line number note here. */ | |
4454 | for (line = head; line; line = PREV_INSN (line)) | |
4455 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) | |
4456 | break; | |
4457 | ||
4458 | /* Walk the insns keeping track of the current line-number and inserting | |
4459 | the line-number notes as needed. */ | |
4460 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4461 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4462 | line = insn; | |
4463 | /* This used to emit line number notes before every non-deleted note. | |
4464 | However, this confuses a debugger, because line notes not separated | |
4465 | by real instructions all end up at the same address. I can find no | |
4466 | use for line number notes before other notes, so none are emitted. */ | |
4467 | else if (GET_CODE (insn) != NOTE | |
4468 | && (note = LINE_NOTE (insn)) != 0 | |
4469 | && note != line | |
4470 | && (line == 0 | |
4471 | || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line) | |
4472 | || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line))) | |
4473 | { | |
4474 | line = note; | |
4475 | prev = PREV_INSN (insn); | |
4476 | if (LINE_NOTE (note)) | |
4477 | { | |
4478 | /* Re-use the original line-number note. */ | |
4479 | LINE_NOTE (note) = 0; | |
4480 | PREV_INSN (note) = prev; | |
4481 | NEXT_INSN (prev) = note; | |
4482 | PREV_INSN (insn) = note; | |
4483 | NEXT_INSN (note) = insn; | |
4484 | } | |
4485 | else | |
4486 | { | |
4487 | added_notes++; | |
4488 | new = emit_note_after (NOTE_LINE_NUMBER (note), prev); | |
4489 | NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note); | |
4490 | RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note); | |
4491 | } | |
4492 | } | |
4493 | if (sched_verbose && added_notes) | |
4494 | fprintf (dump, ";; added %d line-number notes\n", added_notes); | |
4495 | } | |
4496 | ||
4497 | /* After scheduling the function, delete redundant line notes from the | |
4498 | insns list. */ | |
4499 | ||
4500 | static void | |
4501 | rm_redundant_line_notes () | |
4502 | { | |
4503 | rtx line = 0; | |
4504 | rtx insn = get_insns (); | |
4505 | int active_insn = 0; | |
4506 | int notes = 0; | |
4507 | ||
4508 | /* Walk the insns deleting redundant line-number notes. Many of these | |
4509 | are already present. The remainder tend to occur at basic | |
4510 | block boundaries. */ | |
4511 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
4512 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4513 | { | |
4514 | /* If there are no active insns following, INSN is redundant. */ | |
4515 | if (active_insn == 0) | |
4516 | { | |
4517 | notes++; | |
4518 | NOTE_SOURCE_FILE (insn) = 0; | |
4519 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
4520 | } | |
4521 | /* If the line number is unchanged, LINE is redundant. */ | |
4522 | else if (line | |
4523 | && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn) | |
4524 | && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn)) | |
4525 | { | |
4526 | notes++; | |
4527 | NOTE_SOURCE_FILE (line) = 0; | |
4528 | NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED; | |
4529 | line = insn; | |
4530 | } | |
4531 | else | |
4532 | line = insn; | |
4533 | active_insn = 0; | |
4534 | } | |
4535 | else if (!((GET_CODE (insn) == NOTE | |
4536 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) | |
4537 | || (GET_CODE (insn) == INSN | |
4538 | && (GET_CODE (PATTERN (insn)) == USE | |
4539 | || GET_CODE (PATTERN (insn)) == CLOBBER)))) | |
4540 | active_insn++; | |
4541 | ||
4542 | if (sched_verbose && notes) | |
4543 | fprintf (dump, ";; deleted %d line-number notes\n", notes); | |
4544 | } | |
4545 | ||
4546 | /* Delete notes between head and tail and put them in the chain | |
4547 | of notes ended by NOTE_LIST. */ | |
4548 | ||
4549 | static void | |
4550 | rm_other_notes (head, tail) | |
4551 | rtx head; | |
4552 | rtx tail; | |
4553 | { | |
4554 | rtx next_tail; | |
4555 | rtx insn; | |
4556 | ||
4557 | if (head == tail | |
4558 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
4559 | return; | |
4560 | ||
4561 | next_tail = NEXT_INSN (tail); | |
4562 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4563 | { | |
4564 | rtx prev; | |
4565 | ||
4566 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4567 | This is needed to keep the debugger from | |
4568 | getting completely deranged. */ | |
4569 | if (GET_CODE (insn) == NOTE) | |
4570 | { | |
4571 | prev = insn; | |
4572 | ||
4573 | insn = unlink_other_notes (insn, next_tail); | |
4574 | ||
4575 | if (prev == tail) | |
4576 | abort (); | |
4577 | if (prev == head) | |
4578 | abort (); | |
4579 | if (insn == next_tail) | |
4580 | abort (); | |
4581 | } | |
4582 | } | |
4583 | } | |
4584 | ||
63de6c74 | 4585 | /* Functions for computation of registers live/usage info. */ |
8c660648 | 4586 | |
c46a37c4 | 4587 | /* Calculate INSN_REG_WEIGHT for all insns of a block. */ |
8c660648 JL |
4588 | |
4589 | static void | |
49c3bb12 RH |
4590 | find_insn_reg_weight (b) |
4591 | int b; | |
8c660648 JL |
4592 | { |
4593 | rtx insn, next_tail, head, tail; | |
8c660648 | 4594 | |
49c3bb12 | 4595 | get_block_head_tail (b, &head, &tail); |
8c660648 JL |
4596 | next_tail = NEXT_INSN (tail); |
4597 | ||
4598 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4599 | { | |
8c660648 | 4600 | int reg_weight = 0; |
c46a37c4 | 4601 | rtx x; |
8c660648 JL |
4602 | |
4603 | /* Handle register life information. */ | |
8c660648 JL |
4604 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') |
4605 | continue; | |
4606 | ||
c46a37c4 RH |
4607 | /* Increment weight for each register born here. */ |
4608 | x = PATTERN (insn); | |
4609 | if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
4610 | && register_operand (SET_DEST (x), VOIDmode)) | |
4611 | reg_weight++; | |
4612 | else if (GET_CODE (x) == PARALLEL) | |
8c660648 | 4613 | { |
c46a37c4 RH |
4614 | int j; |
4615 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
4616 | { | |
4617 | x = XVECEXP (PATTERN (insn), 0, j); | |
4618 | if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
4619 | && register_operand (SET_DEST (x), VOIDmode)) | |
4620 | reg_weight++; | |
4621 | } | |
8c660648 JL |
4622 | } |
4623 | ||
c46a37c4 RH |
4624 | /* Decrement weight for each register that dies here. */ |
4625 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
8c660648 | 4626 | { |
c46a37c4 RH |
4627 | if (REG_NOTE_KIND (x) == REG_DEAD |
4628 | || REG_NOTE_KIND (x) == REG_UNUSED) | |
4629 | reg_weight--; | |
8c660648 JL |
4630 | } |
4631 | ||
c46a37c4 | 4632 | INSN_REG_WEIGHT (insn) = reg_weight; |
8c660648 | 4633 | } |
8c660648 JL |
4634 | } |
4635 | ||
63de6c74 | 4636 | /* Scheduling clock, modified in schedule_block() and queue_to_ready (). */ |
8c660648 JL |
4637 | static int clock_var; |
4638 | ||
4639 | /* Move insns that became ready to fire from queue to ready list. */ | |
4640 | ||
4641 | static int | |
4642 | queue_to_ready (ready, n_ready) | |
4643 | rtx ready[]; | |
4644 | int n_ready; | |
4645 | { | |
4646 | rtx insn; | |
4647 | rtx link; | |
4648 | ||
4649 | q_ptr = NEXT_Q (q_ptr); | |
4650 | ||
4651 | /* Add all pending insns that can be scheduled without stalls to the | |
4652 | ready list. */ | |
4653 | for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1)) | |
4654 | { | |
4655 | ||
4656 | insn = XEXP (link, 0); | |
4657 | q_size -= 1; | |
4658 | ||
4659 | if (sched_verbose >= 2) | |
4660 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
4661 | ||
4662 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
c88e8206 | 4663 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4664 | |
4665 | ready[n_ready++] = insn; | |
4666 | if (sched_verbose >= 2) | |
4667 | fprintf (dump, "moving to ready without stalls\n"); | |
4668 | } | |
4669 | insn_queue[q_ptr] = 0; | |
4670 | ||
4671 | /* If there are no ready insns, stall until one is ready and add all | |
4672 | of the pending insns at that point to the ready list. */ | |
4673 | if (n_ready == 0) | |
4674 | { | |
4675 | register int stalls; | |
4676 | ||
4677 | for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++) | |
4678 | { | |
4679 | if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])) | |
4680 | { | |
4681 | for (; link; link = XEXP (link, 1)) | |
4682 | { | |
4683 | insn = XEXP (link, 0); | |
4684 | q_size -= 1; | |
4685 | ||
4686 | if (sched_verbose >= 2) | |
4687 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
4688 | ||
4689 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
c88e8206 | 4690 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4691 | |
4692 | ready[n_ready++] = insn; | |
4693 | if (sched_verbose >= 2) | |
4694 | fprintf (dump, "moving to ready with %d stalls\n", stalls); | |
4695 | } | |
4696 | insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0; | |
4697 | ||
4698 | if (n_ready) | |
4699 | break; | |
4700 | } | |
4701 | } | |
4702 | ||
4703 | if (sched_verbose && stalls) | |
4704 | visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls); | |
4705 | q_ptr = NEXT_Q_AFTER (q_ptr, stalls); | |
4706 | clock_var += stalls; | |
4707 | } | |
4708 | return n_ready; | |
4709 | } | |
4710 | ||
63de6c74 | 4711 | /* Print the ready list for debugging purposes. Callable from debugger. */ |
8c660648 | 4712 | |
9a8b0889 | 4713 | static void |
8c660648 JL |
4714 | debug_ready_list (ready, n_ready) |
4715 | rtx ready[]; | |
4716 | int n_ready; | |
4717 | { | |
4718 | int i; | |
4719 | ||
4720 | for (i = 0; i < n_ready; i++) | |
4721 | { | |
4722 | fprintf (dump, " %d", INSN_UID (ready[i])); | |
4723 | if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb) | |
c88e8206 | 4724 | fprintf (dump, "/b%d", BLOCK_NUM (ready[i])); |
8c660648 JL |
4725 | } |
4726 | fprintf (dump, "\n"); | |
4727 | } | |
4728 | ||
4729 | /* Print names of units on which insn can/should execute, for debugging. */ | |
4730 | ||
4731 | static void | |
4732 | insn_print_units (insn) | |
4733 | rtx insn; | |
4734 | { | |
4735 | int i; | |
4736 | int unit = insn_unit (insn); | |
4737 | ||
4738 | if (unit == -1) | |
4739 | fprintf (dump, "none"); | |
4740 | else if (unit >= 0) | |
4741 | fprintf (dump, "%s", function_units[unit].name); | |
4742 | else | |
4743 | { | |
4744 | fprintf (dump, "["); | |
4745 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
4746 | if (unit & 1) | |
4747 | { | |
4748 | fprintf (dump, "%s", function_units[i].name); | |
4749 | if (unit != 1) | |
4750 | fprintf (dump, " "); | |
4751 | } | |
4752 | fprintf (dump, "]"); | |
4753 | } | |
4754 | } | |
4755 | ||
4756 | /* MAX_VISUAL_LINES is the maximum number of lines in visualization table | |
4757 | of a basic block. If more lines are needed, table is splitted to two. | |
4758 | n_visual_lines is the number of lines printed so far for a block. | |
4759 | visual_tbl contains the block visualization info. | |
4760 | vis_no_unit holds insns in a cycle that are not mapped to any unit. */ | |
4761 | #define MAX_VISUAL_LINES 100 | |
4762 | #define INSN_LEN 30 | |
4763 | int n_visual_lines; | |
4764 | char *visual_tbl; | |
4765 | int n_vis_no_unit; | |
4766 | rtx vis_no_unit[10]; | |
4767 | ||
63de6c74 | 4768 | /* Finds units that are in use in this fuction. Required only |
8c660648 JL |
4769 | for visualization. */ |
4770 | ||
4771 | static void | |
4772 | init_target_units () | |
4773 | { | |
4774 | rtx insn; | |
4775 | int unit; | |
4776 | ||
4777 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
4778 | { | |
4779 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
4780 | continue; | |
4781 | ||
4782 | unit = insn_unit (insn); | |
4783 | ||
4784 | if (unit < 0) | |
4785 | target_units |= ~unit; | |
4786 | else | |
4787 | target_units |= (1 << unit); | |
4788 | } | |
4789 | } | |
4790 | ||
63de6c74 | 4791 | /* Return the length of the visualization table. */ |
8c660648 JL |
4792 | |
4793 | static int | |
4794 | get_visual_tbl_length () | |
4795 | { | |
4796 | int unit, i; | |
4797 | int n, n1; | |
4798 | char *s; | |
4799 | ||
63de6c74 | 4800 | /* Compute length of one field in line. */ |
8f04d345 | 4801 | s = (char *) alloca (INSN_LEN + 6); |
8c660648 JL |
4802 | sprintf (s, " %33s", "uname"); |
4803 | n1 = strlen (s); | |
4804 | ||
63de6c74 | 4805 | /* Compute length of one line. */ |
8c660648 JL |
4806 | n = strlen (";; "); |
4807 | n += n1; | |
4808 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
4809 | if (function_units[unit].bitmask & target_units) | |
4810 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
4811 | n += n1; | |
4812 | n += n1; | |
4813 | n += strlen ("\n") + 2; | |
4814 | ||
63de6c74 | 4815 | /* Compute length of visualization string. */ |
8c660648 JL |
4816 | return (MAX_VISUAL_LINES * n); |
4817 | } | |
4818 | ||
63de6c74 | 4819 | /* Init block visualization debugging info. */ |
8c660648 JL |
4820 | |
4821 | static void | |
4822 | init_block_visualization () | |
4823 | { | |
4824 | strcpy (visual_tbl, ""); | |
4825 | n_visual_lines = 0; | |
4826 | n_vis_no_unit = 0; | |
4827 | } | |
4828 | ||
4829 | #define BUF_LEN 256 | |
4830 | ||
459b3825 MM |
4831 | static char * |
4832 | safe_concat (buf, cur, str) | |
4833 | char *buf; | |
4834 | char *cur; | |
5f06c983 | 4835 | const char *str; |
459b3825 | 4836 | { |
63de6c74 | 4837 | char *end = buf + BUF_LEN - 2; /* Leave room for null. */ |
459b3825 MM |
4838 | int c; |
4839 | ||
4840 | if (cur > end) | |
4841 | { | |
4842 | *end = '\0'; | |
4843 | return end; | |
4844 | } | |
4845 | ||
4846 | while (cur < end && (c = *str++) != '\0') | |
4847 | *cur++ = c; | |
4848 | ||
4849 | *cur = '\0'; | |
4850 | return cur; | |
4851 | } | |
4852 | ||
63de6c74 MH |
4853 | /* This recognizes rtx, I classified as expressions. These are always |
4854 | represent some action on values or results of other expression, that | |
4855 | may be stored in objects representing values. */ | |
8c660648 JL |
4856 | |
4857 | static void | |
4858 | print_exp (buf, x, verbose) | |
4859 | char *buf; | |
4860 | rtx x; | |
4861 | int verbose; | |
4862 | { | |
459b3825 | 4863 | char tmp[BUF_LEN]; |
5f06c983 | 4864 | const char *st[4]; |
459b3825 | 4865 | char *cur = buf; |
5f06c983 KG |
4866 | const char *fun = (char *)0; |
4867 | const char *sep; | |
459b3825 MM |
4868 | rtx op[4]; |
4869 | int i; | |
4870 | ||
4871 | for (i = 0; i < 4; i++) | |
4872 | { | |
4873 | st[i] = (char *)0; | |
4874 | op[i] = NULL_RTX; | |
4875 | } | |
8c660648 JL |
4876 | |
4877 | switch (GET_CODE (x)) | |
4878 | { | |
4879 | case PLUS: | |
459b3825 | 4880 | op[0] = XEXP (x, 0); |
f4b94256 RH |
4881 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
4882 | && INTVAL (XEXP (x, 1)) < 0) | |
4883 | { | |
4884 | st[1] = "-"; | |
4885 | op[1] = GEN_INT (-INTVAL (XEXP (x, 1))); | |
4886 | } | |
4887 | else | |
4888 | { | |
4889 | st[1] = "+"; | |
4890 | op[1] = XEXP (x, 1); | |
4891 | } | |
8c660648 JL |
4892 | break; |
4893 | case LO_SUM: | |
459b3825 MM |
4894 | op[0] = XEXP (x, 0); |
4895 | st[1] = "+low("; | |
4896 | op[1] = XEXP (x, 1); | |
4897 | st[2] = ")"; | |
8c660648 JL |
4898 | break; |
4899 | case MINUS: | |
459b3825 MM |
4900 | op[0] = XEXP (x, 0); |
4901 | st[1] = "-"; | |
4902 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4903 | break; |
4904 | case COMPARE: | |
459b3825 MM |
4905 | fun = "cmp"; |
4906 | op[0] = XEXP (x, 0); | |
4907 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4908 | break; |
4909 | case NEG: | |
459b3825 MM |
4910 | st[0] = "-"; |
4911 | op[0] = XEXP (x, 0); | |
8c660648 JL |
4912 | break; |
4913 | case MULT: | |
459b3825 MM |
4914 | op[0] = XEXP (x, 0); |
4915 | st[1] = "*"; | |
4916 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4917 | break; |
4918 | case DIV: | |
459b3825 MM |
4919 | op[0] = XEXP (x, 0); |
4920 | st[1] = "/"; | |
4921 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4922 | break; |
4923 | case UDIV: | |
459b3825 MM |
4924 | fun = "udiv"; |
4925 | op[0] = XEXP (x, 0); | |
4926 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4927 | break; |
4928 | case MOD: | |
459b3825 MM |
4929 | op[0] = XEXP (x, 0); |
4930 | st[1] = "%"; | |
4931 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4932 | break; |
4933 | case UMOD: | |
459b3825 MM |
4934 | fun = "umod"; |
4935 | op[0] = XEXP (x, 0); | |
4936 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4937 | break; |
4938 | case SMIN: | |
459b3825 MM |
4939 | fun = "smin"; |
4940 | op[0] = XEXP (x, 0); | |
4941 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4942 | break; |
4943 | case SMAX: | |
459b3825 MM |
4944 | fun = "smax"; |
4945 | op[0] = XEXP (x, 0); | |
4946 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4947 | break; |
4948 | case UMIN: | |
459b3825 MM |
4949 | fun = "umin"; |
4950 | op[0] = XEXP (x, 0); | |
4951 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4952 | break; |
4953 | case UMAX: | |
459b3825 MM |
4954 | fun = "umax"; |
4955 | op[0] = XEXP (x, 0); | |
4956 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4957 | break; |
4958 | case NOT: | |
459b3825 MM |
4959 | st[0] = "!"; |
4960 | op[0] = XEXP (x, 0); | |
8c660648 JL |
4961 | break; |
4962 | case AND: | |
459b3825 MM |
4963 | op[0] = XEXP (x, 0); |
4964 | st[1] = "&"; | |
4965 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4966 | break; |
4967 | case IOR: | |
459b3825 MM |
4968 | op[0] = XEXP (x, 0); |
4969 | st[1] = "|"; | |
4970 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4971 | break; |
4972 | case XOR: | |
459b3825 MM |
4973 | op[0] = XEXP (x, 0); |
4974 | st[1] = "^"; | |
4975 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4976 | break; |
4977 | case ASHIFT: | |
459b3825 MM |
4978 | op[0] = XEXP (x, 0); |
4979 | st[1] = "<<"; | |
4980 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4981 | break; |
4982 | case LSHIFTRT: | |
459b3825 MM |
4983 | op[0] = XEXP (x, 0); |
4984 | st[1] = " 0>>"; | |
4985 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4986 | break; |
4987 | case ASHIFTRT: | |
459b3825 MM |
4988 | op[0] = XEXP (x, 0); |
4989 | st[1] = ">>"; | |
4990 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4991 | break; |
4992 | case ROTATE: | |
459b3825 MM |
4993 | op[0] = XEXP (x, 0); |
4994 | st[1] = "<-<"; | |
4995 | op[1] = XEXP (x, 1); | |
8c660648 JL |
4996 | break; |
4997 | case ROTATERT: | |
459b3825 MM |
4998 | op[0] = XEXP (x, 0); |
4999 | st[1] = ">->"; | |
5000 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5001 | break; |
5002 | case ABS: | |
459b3825 MM |
5003 | fun = "abs"; |
5004 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5005 | break; |
5006 | case SQRT: | |
459b3825 MM |
5007 | fun = "sqrt"; |
5008 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5009 | break; |
5010 | case FFS: | |
459b3825 MM |
5011 | fun = "ffs"; |
5012 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5013 | break; |
5014 | case EQ: | |
459b3825 MM |
5015 | op[0] = XEXP (x, 0); |
5016 | st[1] = "=="; | |
5017 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5018 | break; |
5019 | case NE: | |
459b3825 MM |
5020 | op[0] = XEXP (x, 0); |
5021 | st[1] = "!="; | |
5022 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5023 | break; |
5024 | case GT: | |
459b3825 MM |
5025 | op[0] = XEXP (x, 0); |
5026 | st[1] = ">"; | |
5027 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5028 | break; |
5029 | case GTU: | |
459b3825 MM |
5030 | fun = "gtu"; |
5031 | op[0] = XEXP (x, 0); | |
5032 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5033 | break; |
5034 | case LT: | |
459b3825 MM |
5035 | op[0] = XEXP (x, 0); |
5036 | st[1] = "<"; | |
5037 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5038 | break; |
5039 | case LTU: | |
459b3825 MM |
5040 | fun = "ltu"; |
5041 | op[0] = XEXP (x, 0); | |
5042 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5043 | break; |
5044 | case GE: | |
459b3825 MM |
5045 | op[0] = XEXP (x, 0); |
5046 | st[1] = ">="; | |
5047 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5048 | break; |
5049 | case GEU: | |
459b3825 MM |
5050 | fun = "geu"; |
5051 | op[0] = XEXP (x, 0); | |
5052 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5053 | break; |
5054 | case LE: | |
459b3825 MM |
5055 | op[0] = XEXP (x, 0); |
5056 | st[1] = "<="; | |
5057 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5058 | break; |
5059 | case LEU: | |
459b3825 MM |
5060 | fun = "leu"; |
5061 | op[0] = XEXP (x, 0); | |
5062 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5063 | break; |
5064 | case SIGN_EXTRACT: | |
459b3825 MM |
5065 | fun = (verbose) ? "sign_extract" : "sxt"; |
5066 | op[0] = XEXP (x, 0); | |
5067 | op[1] = XEXP (x, 1); | |
5068 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5069 | break; |
5070 | case ZERO_EXTRACT: | |
459b3825 MM |
5071 | fun = (verbose) ? "zero_extract" : "zxt"; |
5072 | op[0] = XEXP (x, 0); | |
5073 | op[1] = XEXP (x, 1); | |
5074 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5075 | break; |
5076 | case SIGN_EXTEND: | |
459b3825 MM |
5077 | fun = (verbose) ? "sign_extend" : "sxn"; |
5078 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5079 | break; |
5080 | case ZERO_EXTEND: | |
459b3825 MM |
5081 | fun = (verbose) ? "zero_extend" : "zxn"; |
5082 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5083 | break; |
5084 | case FLOAT_EXTEND: | |
459b3825 MM |
5085 | fun = (verbose) ? "float_extend" : "fxn"; |
5086 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5087 | break; |
5088 | case TRUNCATE: | |
459b3825 MM |
5089 | fun = (verbose) ? "trunc" : "trn"; |
5090 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5091 | break; |
5092 | case FLOAT_TRUNCATE: | |
459b3825 MM |
5093 | fun = (verbose) ? "float_trunc" : "ftr"; |
5094 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5095 | break; |
5096 | case FLOAT: | |
459b3825 MM |
5097 | fun = (verbose) ? "float" : "flt"; |
5098 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5099 | break; |
5100 | case UNSIGNED_FLOAT: | |
459b3825 MM |
5101 | fun = (verbose) ? "uns_float" : "ufl"; |
5102 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5103 | break; |
5104 | case FIX: | |
459b3825 MM |
5105 | fun = "fix"; |
5106 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5107 | break; |
5108 | case UNSIGNED_FIX: | |
459b3825 MM |
5109 | fun = (verbose) ? "uns_fix" : "ufx"; |
5110 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5111 | break; |
5112 | case PRE_DEC: | |
459b3825 MM |
5113 | st[0] = "--"; |
5114 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5115 | break; |
5116 | case PRE_INC: | |
459b3825 MM |
5117 | st[0] = "++"; |
5118 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5119 | break; |
5120 | case POST_DEC: | |
459b3825 MM |
5121 | op[0] = XEXP (x, 0); |
5122 | st[1] = "--"; | |
8c660648 JL |
5123 | break; |
5124 | case POST_INC: | |
459b3825 MM |
5125 | op[0] = XEXP (x, 0); |
5126 | st[1] = "++"; | |
8c660648 JL |
5127 | break; |
5128 | case CALL: | |
459b3825 MM |
5129 | st[0] = "call "; |
5130 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5131 | if (verbose) |
5132 | { | |
459b3825 MM |
5133 | st[1] = " argc:"; |
5134 | op[1] = XEXP (x, 1); | |
8c660648 | 5135 | } |
8c660648 JL |
5136 | break; |
5137 | case IF_THEN_ELSE: | |
459b3825 MM |
5138 | st[0] = "{("; |
5139 | op[0] = XEXP (x, 0); | |
5140 | st[1] = ")?"; | |
5141 | op[1] = XEXP (x, 1); | |
5142 | st[2] = ":"; | |
5143 | op[2] = XEXP (x, 2); | |
5144 | st[3] = "}"; | |
8c660648 JL |
5145 | break; |
5146 | case TRAP_IF: | |
459b3825 MM |
5147 | fun = "trap_if"; |
5148 | op[0] = TRAP_CONDITION (x); | |
8c660648 JL |
5149 | break; |
5150 | case UNSPEC: | |
8c660648 JL |
5151 | case UNSPEC_VOLATILE: |
5152 | { | |
459b3825 MM |
5153 | cur = safe_concat (buf, cur, "unspec"); |
5154 | if (GET_CODE (x) == UNSPEC_VOLATILE) | |
5155 | cur = safe_concat (buf, cur, "/v"); | |
5156 | cur = safe_concat (buf, cur, "["); | |
5157 | sep = ""; | |
8c660648 JL |
5158 | for (i = 0; i < XVECLEN (x, 0); i++) |
5159 | { | |
459b3825 MM |
5160 | print_pattern (tmp, XVECEXP (x, 0, i), verbose); |
5161 | cur = safe_concat (buf, cur, sep); | |
5162 | cur = safe_concat (buf, cur, tmp); | |
5163 | sep = ","; | |
8c660648 | 5164 | } |
459b3825 MM |
5165 | cur = safe_concat (buf, cur, "] "); |
5166 | sprintf (tmp, "%d", XINT (x, 1)); | |
5167 | cur = safe_concat (buf, cur, tmp); | |
8c660648 JL |
5168 | } |
5169 | break; | |
5170 | default: | |
63de6c74 | 5171 | /* If (verbose) debug_rtx (x); */ |
53c0919d | 5172 | st[0] = GET_RTX_NAME (GET_CODE (x)); |
459b3825 MM |
5173 | break; |
5174 | } | |
5175 | ||
63de6c74 | 5176 | /* Print this as a function? */ |
459b3825 MM |
5177 | if (fun) |
5178 | { | |
5179 | cur = safe_concat (buf, cur, fun); | |
5180 | cur = safe_concat (buf, cur, "("); | |
5181 | } | |
5182 | ||
5183 | for (i = 0; i < 4; i++) | |
5184 | { | |
5185 | if (st[i]) | |
5186 | cur = safe_concat (buf, cur, st[i]); | |
5187 | ||
5188 | if (op[i]) | |
5189 | { | |
5190 | if (fun && i != 0) | |
5191 | cur = safe_concat (buf, cur, ","); | |
5192 | ||
5193 | print_value (tmp, op[i], verbose); | |
5194 | cur = safe_concat (buf, cur, tmp); | |
5195 | } | |
8c660648 | 5196 | } |
459b3825 MM |
5197 | |
5198 | if (fun) | |
5199 | cur = safe_concat (buf, cur, ")"); | |
5200 | } /* print_exp */ | |
8c660648 | 5201 | |
63de6c74 MH |
5202 | /* Prints rtxes, I customly classified as values. They're constants, |
5203 | registers, labels, symbols and memory accesses. */ | |
8c660648 JL |
5204 | |
5205 | static void | |
5206 | print_value (buf, x, verbose) | |
5207 | char *buf; | |
5208 | rtx x; | |
5209 | int verbose; | |
5210 | { | |
5211 | char t[BUF_LEN]; | |
459b3825 | 5212 | char *cur = buf; |
8c660648 JL |
5213 | |
5214 | switch (GET_CODE (x)) | |
5215 | { | |
5216 | case CONST_INT: | |
f4b94256 | 5217 | sprintf (t, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); |
459b3825 | 5218 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
5219 | break; |
5220 | case CONST_DOUBLE: | |
459b3825 MM |
5221 | sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); |
5222 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
5223 | break; |
5224 | case CONST_STRING: | |
459b3825 MM |
5225 | cur = safe_concat (buf, cur, "\""); |
5226 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
5227 | cur = safe_concat (buf, cur, "\""); | |
8c660648 JL |
5228 | break; |
5229 | case SYMBOL_REF: | |
459b3825 MM |
5230 | cur = safe_concat (buf, cur, "`"); |
5231 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
5232 | cur = safe_concat (buf, cur, "'"); | |
8c660648 JL |
5233 | break; |
5234 | case LABEL_REF: | |
459b3825 MM |
5235 | sprintf (t, "L%d", INSN_UID (XEXP (x, 0))); |
5236 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
5237 | break; |
5238 | case CONST: | |
459b3825 MM |
5239 | print_value (t, XEXP (x, 0), verbose); |
5240 | cur = safe_concat (buf, cur, "const("); | |
5241 | cur = safe_concat (buf, cur, t); | |
5242 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
5243 | break; |
5244 | case HIGH: | |
459b3825 MM |
5245 | print_value (t, XEXP (x, 0), verbose); |
5246 | cur = safe_concat (buf, cur, "high("); | |
5247 | cur = safe_concat (buf, cur, t); | |
5248 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
5249 | break; |
5250 | case REG: | |
459b3825 MM |
5251 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) |
5252 | { | |
5253 | int c = reg_names[ REGNO (x) ][0]; | |
5254 | if (c >= '0' && c <= '9') | |
5255 | cur = safe_concat (buf, cur, "%"); | |
5256 | ||
5257 | cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]); | |
5258 | } | |
8c660648 | 5259 | else |
459b3825 MM |
5260 | { |
5261 | sprintf (t, "r%d", REGNO (x)); | |
5262 | cur = safe_concat (buf, cur, t); | |
5263 | } | |
8c660648 JL |
5264 | break; |
5265 | case SUBREG: | |
459b3825 MM |
5266 | print_value (t, SUBREG_REG (x), verbose); |
5267 | cur = safe_concat (buf, cur, t); | |
6b879bcc | 5268 | sprintf (t, "#%d", SUBREG_WORD (x)); |
459b3825 | 5269 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
5270 | break; |
5271 | case SCRATCH: | |
459b3825 | 5272 | cur = safe_concat (buf, cur, "scratch"); |
8c660648 JL |
5273 | break; |
5274 | case CC0: | |
459b3825 | 5275 | cur = safe_concat (buf, cur, "cc0"); |
8c660648 JL |
5276 | break; |
5277 | case PC: | |
459b3825 | 5278 | cur = safe_concat (buf, cur, "pc"); |
8c660648 JL |
5279 | break; |
5280 | case MEM: | |
5281 | print_value (t, XEXP (x, 0), verbose); | |
459b3825 MM |
5282 | cur = safe_concat (buf, cur, "["); |
5283 | cur = safe_concat (buf, cur, t); | |
5284 | cur = safe_concat (buf, cur, "]"); | |
8c660648 JL |
5285 | break; |
5286 | default: | |
459b3825 MM |
5287 | print_exp (t, x, verbose); |
5288 | cur = safe_concat (buf, cur, t); | |
5289 | break; | |
8c660648 JL |
5290 | } |
5291 | } /* print_value */ | |
5292 | ||
63de6c74 | 5293 | /* The next step in insn detalization, its pattern recognition. */ |
8c660648 JL |
5294 | |
5295 | static void | |
5296 | print_pattern (buf, x, verbose) | |
5297 | char *buf; | |
5298 | rtx x; | |
5299 | int verbose; | |
5300 | { | |
5301 | char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN]; | |
5302 | ||
5303 | switch (GET_CODE (x)) | |
5304 | { | |
5305 | case SET: | |
5306 | print_value (t1, SET_DEST (x), verbose); | |
5307 | print_value (t2, SET_SRC (x), verbose); | |
5308 | sprintf (buf, "%s=%s", t1, t2); | |
5309 | break; | |
5310 | case RETURN: | |
5311 | sprintf (buf, "return"); | |
5312 | break; | |
5313 | case CALL: | |
5314 | print_exp (buf, x, verbose); | |
5315 | break; | |
5316 | case CLOBBER: | |
5317 | print_value (t1, XEXP (x, 0), verbose); | |
5318 | sprintf (buf, "clobber %s", t1); | |
5319 | break; | |
5320 | case USE: | |
5321 | print_value (t1, XEXP (x, 0), verbose); | |
5322 | sprintf (buf, "use %s", t1); | |
5323 | break; | |
5324 | case PARALLEL: | |
5325 | { | |
5326 | int i; | |
5327 | ||
5328 | sprintf (t1, "{"); | |
5329 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5330 | { | |
5331 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5332 | sprintf (t3, "%s%s;", t1, t2); | |
5333 | strcpy (t1, t3); | |
5334 | } | |
5335 | sprintf (buf, "%s}", t1); | |
5336 | } | |
5337 | break; | |
5338 | case SEQUENCE: | |
5339 | { | |
5340 | int i; | |
5341 | ||
5342 | sprintf (t1, "%%{"); | |
5343 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5344 | { | |
5345 | print_insn (t2, XVECEXP (x, 0, i), verbose); | |
5346 | sprintf (t3, "%s%s;", t1, t2); | |
5347 | strcpy (t1, t3); | |
5348 | } | |
5349 | sprintf (buf, "%s%%}", t1); | |
5350 | } | |
5351 | break; | |
5352 | case ASM_INPUT: | |
c4fa3460 | 5353 | sprintf (buf, "asm {%s}", XSTR (x, 0)); |
8c660648 JL |
5354 | break; |
5355 | case ADDR_VEC: | |
5356 | break; | |
5357 | case ADDR_DIFF_VEC: | |
5358 | print_value (buf, XEXP (x, 0), verbose); | |
5359 | break; | |
5360 | case TRAP_IF: | |
5361 | print_value (t1, TRAP_CONDITION (x), verbose); | |
5362 | sprintf (buf, "trap_if %s", t1); | |
5363 | break; | |
5364 | case UNSPEC: | |
5365 | { | |
5366 | int i; | |
5367 | ||
5368 | sprintf (t1, "unspec{"); | |
5369 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5370 | { | |
5371 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5372 | sprintf (t3, "%s%s;", t1, t2); | |
5373 | strcpy (t1, t3); | |
5374 | } | |
5375 | sprintf (buf, "%s}", t1); | |
5376 | } | |
5377 | break; | |
5378 | case UNSPEC_VOLATILE: | |
5379 | { | |
5380 | int i; | |
5381 | ||
5382 | sprintf (t1, "unspec/v{"); | |
5383 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5384 | { | |
5385 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5386 | sprintf (t3, "%s%s;", t1, t2); | |
5387 | strcpy (t1, t3); | |
5388 | } | |
5389 | sprintf (buf, "%s}", t1); | |
5390 | } | |
5391 | break; | |
5392 | default: | |
5393 | print_value (buf, x, verbose); | |
5394 | } | |
5395 | } /* print_pattern */ | |
5396 | ||
5397 | /* This is the main function in rtl visualization mechanism. It | |
5398 | accepts an rtx and tries to recognize it as an insn, then prints it | |
63de6c74 MH |
5399 | properly in human readable form, resembling assembler mnemonics. |
5400 | For every insn it prints its UID and BB the insn belongs too. | |
5401 | (Probably the last "option" should be extended somehow, since it | |
5402 | depends now on sched.c inner variables ...) */ | |
8c660648 JL |
5403 | |
5404 | static void | |
5405 | print_insn (buf, x, verbose) | |
5406 | char *buf; | |
5407 | rtx x; | |
5408 | int verbose; | |
5409 | { | |
5410 | char t[BUF_LEN]; | |
5411 | rtx insn = x; | |
5412 | ||
5413 | switch (GET_CODE (x)) | |
5414 | { | |
5415 | case INSN: | |
5416 | print_pattern (t, PATTERN (x), verbose); | |
5417 | if (verbose) | |
5418 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x), | |
5419 | INSN_UID (x), t); | |
5420 | else | |
5421 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
5422 | break; | |
5423 | case JUMP_INSN: | |
5424 | print_pattern (t, PATTERN (x), verbose); | |
5425 | if (verbose) | |
5426 | sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x), | |
5427 | INSN_UID (x), t); | |
5428 | else | |
5429 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
5430 | break; | |
5431 | case CALL_INSN: | |
5432 | x = PATTERN (insn); | |
5433 | if (GET_CODE (x) == PARALLEL) | |
5434 | { | |
5435 | x = XVECEXP (x, 0, 0); | |
5436 | print_pattern (t, x, verbose); | |
5437 | } | |
5438 | else | |
5439 | strcpy (t, "call <...>"); | |
5440 | if (verbose) | |
5441 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn), | |
5442 | INSN_UID (insn), t); | |
5443 | else | |
5444 | sprintf (buf, "%-4d %s", INSN_UID (insn), t); | |
5445 | break; | |
5446 | case CODE_LABEL: | |
5447 | sprintf (buf, "L%d:", INSN_UID (x)); | |
5448 | break; | |
5449 | case BARRIER: | |
5450 | sprintf (buf, "i% 4d: barrier", INSN_UID (x)); | |
5451 | break; | |
5452 | case NOTE: | |
5453 | if (NOTE_LINE_NUMBER (x) > 0) | |
5454 | sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x), | |
5455 | NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x)); | |
5456 | else | |
5457 | sprintf (buf, "%4d %s", INSN_UID (x), | |
5458 | GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x))); | |
5459 | break; | |
5460 | default: | |
5461 | if (verbose) | |
5462 | { | |
5463 | sprintf (buf, "Not an INSN at all\n"); | |
5464 | debug_rtx (x); | |
5465 | } | |
5466 | else | |
5467 | sprintf (buf, "i%-4d <What?>", INSN_UID (x)); | |
5468 | } | |
5469 | } /* print_insn */ | |
5470 | ||
63de6c74 | 5471 | /* Print visualization debugging info. */ |
8c660648 JL |
5472 | |
5473 | static void | |
5474 | print_block_visualization (b, s) | |
5475 | int b; | |
5f06c983 | 5476 | const char *s; |
8c660648 JL |
5477 | { |
5478 | int unit, i; | |
8c660648 | 5479 | |
63de6c74 | 5480 | /* Print header. */ |
8c660648 JL |
5481 | fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s); |
5482 | ||
63de6c74 | 5483 | /* Print names of units. */ |
2f308fec | 5484 | fprintf (dump, ";; %-8s", "clock"); |
8c660648 JL |
5485 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) |
5486 | if (function_units[unit].bitmask & target_units) | |
5487 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
2f308fec RH |
5488 | fprintf (dump, " %-33s", function_units[unit].name); |
5489 | fprintf (dump, " %-8s\n", "no-unit"); | |
5490 | ||
5491 | fprintf (dump, ";; %-8s", "====="); | |
5492 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5493 | if (function_units[unit].bitmask & target_units) | |
5494 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5495 | fprintf (dump, " %-33s", "=============================="); | |
5496 | fprintf (dump, " %-8s\n", "======="); | |
8c660648 | 5497 | |
63de6c74 | 5498 | /* Print insns in each cycle. */ |
8c660648 JL |
5499 | fprintf (dump, "%s\n", visual_tbl); |
5500 | } | |
5501 | ||
63de6c74 | 5502 | /* Print insns in the 'no_unit' column of visualization. */ |
8c660648 JL |
5503 | |
5504 | static void | |
5505 | visualize_no_unit (insn) | |
5506 | rtx insn; | |
5507 | { | |
5508 | vis_no_unit[n_vis_no_unit] = insn; | |
5509 | n_vis_no_unit++; | |
5510 | } | |
5511 | ||
5512 | /* Print insns scheduled in clock, for visualization. */ | |
5513 | ||
5514 | static void | |
5515 | visualize_scheduled_insns (b, clock) | |
5516 | int b, clock; | |
5517 | { | |
5518 | int i, unit; | |
5519 | ||
63de6c74 | 5520 | /* If no more room, split table into two. */ |
8c660648 JL |
5521 | if (n_visual_lines >= MAX_VISUAL_LINES) |
5522 | { | |
5523 | print_block_visualization (b, "(incomplete)"); | |
5524 | init_block_visualization (); | |
5525 | } | |
5526 | ||
5527 | n_visual_lines++; | |
5528 | ||
5529 | sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock); | |
5530 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5531 | if (function_units[unit].bitmask & target_units) | |
5532 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5533 | { | |
5534 | int instance = unit + i * FUNCTION_UNITS_SIZE; | |
5535 | rtx insn = unit_last_insn[instance]; | |
5536 | ||
63de6c74 | 5537 | /* Print insns that still keep the unit busy. */ |
8c660648 JL |
5538 | if (insn && |
5539 | actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
5540 | { | |
5541 | char str[BUF_LEN]; | |
5542 | print_insn (str, insn, 0); | |
5543 | str[INSN_LEN] = '\0'; | |
5544 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str); | |
5545 | } | |
5546 | else | |
5547 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------"); | |
5548 | } | |
5549 | ||
63de6c74 | 5550 | /* Print insns that are not assigned to any unit. */ |
8c660648 JL |
5551 | for (i = 0; i < n_vis_no_unit; i++) |
5552 | sprintf (visual_tbl + strlen (visual_tbl), " %-8d", | |
5553 | INSN_UID (vis_no_unit[i])); | |
5554 | n_vis_no_unit = 0; | |
5555 | ||
5556 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
5557 | } | |
5558 | ||
63de6c74 | 5559 | /* Print stalled cycles. */ |
8c660648 JL |
5560 | |
5561 | static void | |
5562 | visualize_stall_cycles (b, stalls) | |
5563 | int b, stalls; | |
5564 | { | |
5565 | int i; | |
5566 | ||
63de6c74 | 5567 | /* If no more room, split table into two. */ |
8c660648 JL |
5568 | if (n_visual_lines >= MAX_VISUAL_LINES) |
5569 | { | |
5570 | print_block_visualization (b, "(incomplete)"); | |
5571 | init_block_visualization (); | |
5572 | } | |
5573 | ||
5574 | n_visual_lines++; | |
5575 | ||
5576 | sprintf (visual_tbl + strlen (visual_tbl), ";; "); | |
5577 | for (i = 0; i < stalls; i++) | |
5578 | sprintf (visual_tbl + strlen (visual_tbl), "."); | |
5579 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
5580 | } | |
5581 | ||
63de6c74 | 5582 | /* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */ |
8c660648 JL |
5583 | |
5584 | static rtx | |
5585 | move_insn1 (insn, last) | |
5586 | rtx insn, last; | |
5587 | { | |
5588 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
5589 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
5590 | ||
5591 | NEXT_INSN (insn) = NEXT_INSN (last); | |
5592 | PREV_INSN (NEXT_INSN (last)) = insn; | |
5593 | ||
5594 | NEXT_INSN (last) = insn; | |
5595 | PREV_INSN (insn) = last; | |
5596 | ||
5597 | return insn; | |
5598 | } | |
5599 | ||
c46a37c4 | 5600 | /* Search INSN for REG_SAVE_NOTE note pairs for NOTE_INSN_SETJMP, |
8c660648 | 5601 | NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into |
c46a37c4 RH |
5602 | NOTEs. The REG_SAVE_NOTE note following first one is contains the |
5603 | saved value for NOTE_BLOCK_NUMBER which is useful for | |
8c660648 JL |
5604 | NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction |
5605 | output by the instruction scheduler. Return the new value of LAST. */ | |
5606 | ||
5607 | static rtx | |
5608 | reemit_notes (insn, last) | |
5609 | rtx insn; | |
5610 | rtx last; | |
5611 | { | |
5612 | rtx note, retval; | |
5613 | ||
5614 | retval = last; | |
5615 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
5616 | { | |
c46a37c4 | 5617 | if (REG_NOTE_KIND (note) == REG_SAVE_NOTE) |
8c660648 | 5618 | { |
6dfdecdb RH |
5619 | int note_type = INTVAL (XEXP (note, 0)); |
5620 | if (note_type == NOTE_INSN_SETJMP) | |
8c660648 | 5621 | { |
6dfdecdb | 5622 | retval = emit_note_after (NOTE_INSN_SETJMP, insn); |
8c660648 | 5623 | CONST_CALL_P (retval) = CONST_CALL_P (note); |
7bd41ea6 MM |
5624 | remove_note (insn, note); |
5625 | note = XEXP (note, 1); | |
8c660648 | 5626 | } |
6dfdecdb RH |
5627 | else if (note_type == NOTE_INSN_RANGE_START |
5628 | || note_type == NOTE_INSN_RANGE_END) | |
5629 | { | |
5630 | last = emit_note_before (note_type, last); | |
5631 | remove_note (insn, note); | |
5632 | note = XEXP (note, 1); | |
5633 | NOTE_RANGE_INFO (last) = XEXP (note, 0); | |
5634 | } | |
8c660648 JL |
5635 | else |
5636 | { | |
19699da4 | 5637 | last = emit_note_before (note_type, last); |
7bd41ea6 MM |
5638 | remove_note (insn, note); |
5639 | note = XEXP (note, 1); | |
1a4450c7 MM |
5640 | if (note_type == NOTE_INSN_EH_REGION_BEG |
5641 | || note_type == NOTE_INSN_EH_REGION_END) | |
7bd41ea6 | 5642 | NOTE_EH_HANDLER (last) = INTVAL (XEXP (note, 0)); |
8c660648 JL |
5643 | } |
5644 | remove_note (insn, note); | |
5645 | } | |
5646 | } | |
5647 | return retval; | |
5648 | } | |
5649 | ||
5650 | /* Move INSN, and all insns which should be issued before it, | |
c9e03727 JL |
5651 | due to SCHED_GROUP_P flag. Reemit notes if needed. |
5652 | ||
5653 | Return the last insn emitted by the scheduler, which is the | |
5654 | return value from the first call to reemit_notes. */ | |
8c660648 JL |
5655 | |
5656 | static rtx | |
5657 | move_insn (insn, last) | |
5658 | rtx insn, last; | |
5659 | { | |
c9e03727 | 5660 | rtx retval = NULL; |
8c660648 | 5661 | |
c9e03727 JL |
5662 | /* If INSN has SCHED_GROUP_P set, then issue it and any other |
5663 | insns with SCHED_GROUP_P set first. */ | |
8c660648 JL |
5664 | while (SCHED_GROUP_P (insn)) |
5665 | { | |
5666 | rtx prev = PREV_INSN (insn); | |
c9e03727 JL |
5667 | |
5668 | /* Move a SCHED_GROUP_P insn. */ | |
8c660648 | 5669 | move_insn1 (insn, last); |
c9e03727 JL |
5670 | /* If this is the first call to reemit_notes, then record |
5671 | its return value. */ | |
5672 | if (retval == NULL_RTX) | |
5673 | retval = reemit_notes (insn, insn); | |
5674 | else | |
5675 | reemit_notes (insn, insn); | |
8c660648 JL |
5676 | insn = prev; |
5677 | } | |
5678 | ||
c9e03727 | 5679 | /* Now move the first non SCHED_GROUP_P insn. */ |
8c660648 | 5680 | move_insn1 (insn, last); |
c9e03727 JL |
5681 | |
5682 | /* If this is the first call to reemit_notes, then record | |
5683 | its return value. */ | |
5684 | if (retval == NULL_RTX) | |
5685 | retval = reemit_notes (insn, insn); | |
5686 | else | |
5687 | reemit_notes (insn, insn); | |
5688 | ||
5689 | return retval; | |
8c660648 JL |
5690 | } |
5691 | ||
5692 | /* Return an insn which represents a SCHED_GROUP, which is | |
5693 | the last insn in the group. */ | |
5694 | ||
5695 | static rtx | |
5696 | group_leader (insn) | |
5697 | rtx insn; | |
5698 | { | |
5699 | rtx prev; | |
5700 | ||
5701 | do | |
5702 | { | |
5703 | prev = insn; | |
5704 | insn = next_nonnote_insn (insn); | |
5705 | } | |
5706 | while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL)); | |
5707 | ||
5708 | return prev; | |
5709 | } | |
5710 | ||
5711 | /* Use forward list scheduling to rearrange insns of block BB in region RGN, | |
5712 | possibly bringing insns from subsequent blocks in the same region. | |
5713 | Return number of insns scheduled. */ | |
5714 | ||
5715 | static int | |
5835e573 | 5716 | schedule_block (bb, rgn_n_insns) |
8c660648 | 5717 | int bb; |
8c660648 JL |
5718 | int rgn_n_insns; |
5719 | { | |
5720 | /* Local variables. */ | |
5721 | rtx insn, last; | |
5722 | rtx *ready; | |
8c660648 JL |
5723 | int n_ready = 0; |
5724 | int can_issue_more; | |
5725 | ||
63de6c74 | 5726 | /* Flow block of this bb. */ |
8c660648 JL |
5727 | int b = BB_TO_BLOCK (bb); |
5728 | ||
5729 | /* target_n_insns == number of insns in b before scheduling starts. | |
5730 | sched_target_n_insns == how many of b's insns were scheduled. | |
63de6c74 | 5731 | sched_n_insns == how many insns were scheduled in b. */ |
8c660648 JL |
5732 | int target_n_insns = 0; |
5733 | int sched_target_n_insns = 0; | |
5734 | int sched_n_insns = 0; | |
5735 | ||
5736 | #define NEED_NOTHING 0 | |
5737 | #define NEED_HEAD 1 | |
5738 | #define NEED_TAIL 2 | |
5739 | int new_needs; | |
5740 | ||
63de6c74 | 5741 | /* Head/tail info for this block. */ |
8c660648 JL |
5742 | rtx prev_head; |
5743 | rtx next_tail; | |
5744 | rtx head; | |
5745 | rtx tail; | |
5746 | int bb_src; | |
5747 | ||
484df988 JL |
5748 | /* We used to have code to avoid getting parameters moved from hard |
5749 | argument registers into pseudos. | |
8c660648 | 5750 | |
484df988 JL |
5751 | However, it was removed when it proved to be of marginal benefit |
5752 | and caused problems because schedule_block and compute_forward_dependences | |
5753 | had different notions of what the "head" insn was. */ | |
49c3bb12 | 5754 | get_bb_head_tail (bb, &head, &tail); |
8c660648 | 5755 | |
1447b516 JL |
5756 | /* Interblock scheduling could have moved the original head insn from this |
5757 | block into a proceeding block. This may also cause schedule_block and | |
5758 | compute_forward_dependences to have different notions of what the | |
5759 | "head" insn was. | |
5760 | ||
5761 | If the interblock movement happened to make this block start with | |
5762 | some notes (LOOP, EH or SETJMP) before the first real insn, then | |
5763 | HEAD will have various special notes attached to it which must be | |
5764 | removed so that we don't end up with extra copies of the notes. */ | |
5765 | if (GET_RTX_CLASS (GET_CODE (head)) == 'i') | |
5766 | { | |
5767 | rtx note; | |
5768 | ||
5769 | for (note = REG_NOTES (head); note; note = XEXP (note, 1)) | |
c46a37c4 | 5770 | if (REG_NOTE_KIND (note) == REG_SAVE_NOTE) |
1447b516 JL |
5771 | remove_note (head, note); |
5772 | } | |
5773 | ||
8c660648 JL |
5774 | next_tail = NEXT_INSN (tail); |
5775 | prev_head = PREV_INSN (head); | |
5776 | ||
5777 | /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need | |
5778 | to schedule this block. */ | |
5779 | if (head == tail | |
5780 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
5781 | return (sched_n_insns); | |
5782 | ||
63de6c74 | 5783 | /* Debug info. */ |
8c660648 JL |
5784 | if (sched_verbose) |
5785 | { | |
5786 | fprintf (dump, ";; ======================================================\n"); | |
5787 | fprintf (dump, | |
5788 | ";; -- basic block %d from %d to %d -- %s reload\n", | |
3b413743 | 5789 | b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)), |
8c660648 JL |
5790 | (reload_completed ? "after" : "before")); |
5791 | fprintf (dump, ";; ======================================================\n"); | |
8c660648 JL |
5792 | fprintf (dump, "\n"); |
5793 | ||
5794 | visual_tbl = (char *) alloca (get_visual_tbl_length ()); | |
5795 | init_block_visualization (); | |
5796 | } | |
5797 | ||
63de6c74 | 5798 | /* Remove remaining note insns from the block, save them in |
8c660648 JL |
5799 | note_list. These notes are restored at the end of |
5800 | schedule_block (). */ | |
5801 | note_list = 0; | |
5802 | rm_other_notes (head, tail); | |
5803 | ||
5804 | target_bb = bb; | |
5805 | ||
63de6c74 | 5806 | /* Prepare current target block info. */ |
8c660648 JL |
5807 | if (current_nr_blocks > 1) |
5808 | { | |
98903742 MM |
5809 | candidate_table = (candidate *) xmalloc (current_nr_blocks |
5810 | * sizeof (candidate)); | |
8c660648 JL |
5811 | |
5812 | bblst_last = 0; | |
5813 | /* ??? It is not clear why bblst_size is computed this way. The original | |
5814 | number was clearly too small as it resulted in compiler failures. | |
5815 | Multiplying by the original number by 2 (to account for update_bbs | |
5816 | members) seems to be a reasonable solution. */ | |
5817 | /* ??? Or perhaps there is a bug somewhere else in this file? */ | |
5818 | bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2; | |
98903742 | 5819 | bblst_table = (int *) xmalloc (bblst_size * sizeof (int)); |
8c660648 JL |
5820 | |
5821 | bitlst_table_last = 0; | |
5822 | bitlst_table_size = rgn_nr_edges; | |
98903742 | 5823 | bitlst_table = (int *) xmalloc (rgn_nr_edges * sizeof (int)); |
8c660648 JL |
5824 | |
5825 | compute_trg_info (bb); | |
5826 | } | |
5827 | ||
5828 | clear_units (); | |
5829 | ||
63de6c74 | 5830 | /* Allocate the ready list. */ |
98903742 | 5831 | ready = (rtx *) xmalloc ((rgn_n_insns + 1) * sizeof (rtx)); |
8c660648 JL |
5832 | |
5833 | /* Print debugging information. */ | |
5834 | if (sched_verbose >= 5) | |
5835 | debug_dependencies (); | |
5836 | ||
5837 | ||
5838 | /* Initialize ready list with all 'ready' insns in target block. | |
5839 | Count number of insns in the target block being scheduled. */ | |
5840 | n_ready = 0; | |
5841 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5842 | { | |
5843 | rtx next; | |
5844 | ||
5845 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5846 | continue; | |
5847 | next = NEXT_INSN (insn); | |
5848 | ||
5849 | if (INSN_DEP_COUNT (insn) == 0 | |
5850 | && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
5851 | ready[n_ready++] = insn; | |
5852 | if (!(SCHED_GROUP_P (insn))) | |
5853 | target_n_insns++; | |
5854 | } | |
5855 | ||
5856 | /* Add to ready list all 'ready' insns in valid source blocks. | |
5857 | For speculative insns, check-live, exception-free, and | |
5858 | issue-delay. */ | |
5859 | for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++) | |
5860 | if (IS_VALID (bb_src)) | |
5861 | { | |
5862 | rtx src_head; | |
5863 | rtx src_next_tail; | |
5864 | rtx tail, head; | |
5865 | ||
49c3bb12 | 5866 | get_bb_head_tail (bb_src, &head, &tail); |
8c660648 JL |
5867 | src_next_tail = NEXT_INSN (tail); |
5868 | src_head = head; | |
5869 | ||
5870 | if (head == tail | |
5871 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
5872 | continue; | |
5873 | ||
5874 | for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn)) | |
5875 | { | |
5876 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5877 | continue; | |
5878 | ||
5879 | if (!CANT_MOVE (insn) | |
5880 | && (!IS_SPECULATIVE_INSN (insn) | |
5881 | || (insn_issue_delay (insn) <= 3 | |
5835e573 | 5882 | && check_live (insn, bb_src) |
8c660648 | 5883 | && is_exception_free (insn, bb_src, target_bb)))) |
8c660648 JL |
5884 | { |
5885 | rtx next; | |
5886 | ||
0d8b2ca1 RH |
5887 | /* Note that we havn't squirrled away the notes for |
5888 | blocks other than the current. So if this is a | |
5889 | speculative insn, NEXT might otherwise be a note. */ | |
5890 | next = next_nonnote_insn (insn); | |
8c660648 | 5891 | if (INSN_DEP_COUNT (insn) == 0 |
b182031e RH |
5892 | && (! next |
5893 | || SCHED_GROUP_P (next) == 0 | |
8c660648 JL |
5894 | || GET_RTX_CLASS (GET_CODE (next)) != 'i')) |
5895 | ready[n_ready++] = insn; | |
5896 | } | |
5897 | } | |
5898 | } | |
5899 | ||
e4da5f6d MM |
5900 | #ifdef MD_SCHED_INIT |
5901 | MD_SCHED_INIT (dump, sched_verbose); | |
5902 | #endif | |
5903 | ||
63de6c74 | 5904 | /* No insns scheduled in this block yet. */ |
8c660648 JL |
5905 | last_scheduled_insn = 0; |
5906 | ||
8c660648 JL |
5907 | /* Q_SIZE is the total number of insns in the queue. */ |
5908 | q_ptr = 0; | |
5909 | q_size = 0; | |
4bdc8810 | 5910 | last_clock_var = 0; |
8c660648 JL |
5911 | bzero ((char *) insn_queue, sizeof (insn_queue)); |
5912 | ||
197043f5 RH |
5913 | /* Start just before the beginning of time. */ |
5914 | clock_var = -1; | |
5915 | ||
8c660648 JL |
5916 | /* We start inserting insns after PREV_HEAD. */ |
5917 | last = prev_head; | |
5918 | ||
5919 | /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */ | |
3b413743 | 5920 | new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b) |
8c660648 | 5921 | ? NEED_HEAD : NEED_NOTHING); |
3b413743 | 5922 | if (PREV_INSN (next_tail) == BLOCK_END (b)) |
8c660648 JL |
5923 | new_needs |= NEED_TAIL; |
5924 | ||
63de6c74 | 5925 | /* Loop until all the insns in BB are scheduled. */ |
8c660648 JL |
5926 | while (sched_target_n_insns < target_n_insns) |
5927 | { | |
8c660648 JL |
5928 | clock_var++; |
5929 | ||
5930 | /* Add to the ready list all pending insns that can be issued now. | |
5931 | If there are no ready insns, increment clock until one | |
5932 | is ready and add all pending insns at that point to the ready | |
5933 | list. */ | |
5934 | n_ready = queue_to_ready (ready, n_ready); | |
5935 | ||
5936 | if (n_ready == 0) | |
5937 | abort (); | |
5938 | ||
5939 | if (sched_verbose >= 2) | |
5940 | { | |
5941 | fprintf (dump, ";;\t\tReady list after queue_to_ready: "); | |
5942 | debug_ready_list (ready, n_ready); | |
5943 | } | |
5944 | ||
197043f5 | 5945 | /* Sort the ready list based on priority. */ |
8c660648 | 5946 | SCHED_SORT (ready, n_ready); |
197043f5 RH |
5947 | |
5948 | /* Allow the target to reorder the list, typically for | |
5949 | better instruction bundling. */ | |
e4da5f6d | 5950 | #ifdef MD_SCHED_REORDER |
197043f5 RH |
5951 | MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var, |
5952 | can_issue_more); | |
5953 | #else | |
5954 | can_issue_more = issue_rate; | |
e4da5f6d | 5955 | #endif |
8c660648 JL |
5956 | |
5957 | if (sched_verbose) | |
5958 | { | |
47312d84 | 5959 | fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var); |
8c660648 JL |
5960 | debug_ready_list (ready, n_ready); |
5961 | } | |
5962 | ||
197043f5 RH |
5963 | /* Issue insns from ready list. */ |
5964 | while (n_ready != 0 && can_issue_more) | |
8c660648 | 5965 | { |
197043f5 RH |
5966 | /* Select and remove the insn from the ready list. */ |
5967 | rtx insn = ready[--n_ready]; | |
8c660648 JL |
5968 | int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0); |
5969 | ||
197043f5 | 5970 | if (cost >= 1) |
8c660648 JL |
5971 | { |
5972 | queue_insn (insn, cost); | |
197043f5 | 5973 | continue; |
8c660648 | 5974 | } |
4f64eaca | 5975 | |
197043f5 RH |
5976 | /* An interblock motion? */ |
5977 | if (INSN_BB (insn) != target_bb) | |
5978 | { | |
5979 | rtx temp; | |
c88e8206 | 5980 | basic_block b1; |
8c660648 | 5981 | |
197043f5 RH |
5982 | if (IS_SPECULATIVE_INSN (insn)) |
5983 | { | |
5984 | if (!check_live (insn, INSN_BB (insn))) | |
5985 | continue; | |
5986 | update_live (insn, INSN_BB (insn)); | |
8c660648 | 5987 | |
197043f5 RH |
5988 | /* For speculative load, mark insns fed by it. */ |
5989 | if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn)) | |
5990 | set_spec_fed (insn); | |
8c660648 | 5991 | |
197043f5 RH |
5992 | nr_spec++; |
5993 | } | |
5994 | nr_inter++; | |
8c660648 | 5995 | |
49c3bb12 RH |
5996 | /* Find the beginning of the scheduling group. */ |
5997 | /* ??? Ought to update basic block here, but later bits of | |
5998 | schedule_block assumes the original insn block is | |
5999 | still intact. */ | |
6000 | ||
197043f5 | 6001 | temp = insn; |
eae48b73 | 6002 | while (SCHED_GROUP_P (temp)) |
49c3bb12 | 6003 | temp = PREV_INSN (temp); |
4f64eaca | 6004 | |
197043f5 | 6005 | /* Update source block boundaries. */ |
c88e8206 RH |
6006 | b1 = BLOCK_FOR_INSN (temp); |
6007 | if (temp == b1->head && insn == b1->end) | |
197043f5 RH |
6008 | { |
6009 | /* We moved all the insns in the basic block. | |
6010 | Emit a note after the last insn and update the | |
6011 | begin/end boundaries to point to the note. */ | |
c88e8206 RH |
6012 | rtx note = emit_note_after (NOTE_INSN_DELETED, insn); |
6013 | b1->head = note; | |
6014 | b1->end = note; | |
8c660648 | 6015 | } |
c88e8206 | 6016 | else if (insn == b1->end) |
8c660648 | 6017 | { |
197043f5 RH |
6018 | /* We took insns from the end of the basic block, |
6019 | so update the end of block boundary so that it | |
6020 | points to the first insn we did not move. */ | |
c88e8206 | 6021 | b1->end = PREV_INSN (temp); |
8c660648 | 6022 | } |
c88e8206 | 6023 | else if (temp == b1->head) |
197043f5 RH |
6024 | { |
6025 | /* We took insns from the start of the basic block, | |
6026 | so update the start of block boundary so that | |
6027 | it points to the first insn we did not move. */ | |
c88e8206 | 6028 | b1->head = NEXT_INSN (insn); |
197043f5 RH |
6029 | } |
6030 | } | |
6031 | else | |
6032 | { | |
6033 | /* In block motion. */ | |
6034 | sched_target_n_insns++; | |
6035 | } | |
8c660648 | 6036 | |
197043f5 RH |
6037 | last_scheduled_insn = insn; |
6038 | last = move_insn (insn, last); | |
6039 | sched_n_insns++; | |
8c660648 | 6040 | |
e4da5f6d | 6041 | #ifdef MD_SCHED_VARIABLE_ISSUE |
197043f5 RH |
6042 | MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, |
6043 | can_issue_more); | |
e4da5f6d | 6044 | #else |
197043f5 | 6045 | can_issue_more--; |
e4da5f6d | 6046 | #endif |
8c660648 | 6047 | |
197043f5 | 6048 | n_ready = schedule_insn (insn, ready, n_ready, clock_var); |
8c660648 | 6049 | |
197043f5 RH |
6050 | /* Close this block after scheduling its jump. */ |
6051 | if (GET_CODE (last_scheduled_insn) == JUMP_INSN) | |
6052 | break; | |
8c660648 JL |
6053 | } |
6054 | ||
197043f5 | 6055 | /* Debug info. */ |
8c660648 | 6056 | if (sched_verbose) |
197043f5 | 6057 | visualize_scheduled_insns (b, clock_var); |
8c660648 JL |
6058 | } |
6059 | ||
63de6c74 | 6060 | /* Debug info. */ |
8c660648 JL |
6061 | if (sched_verbose) |
6062 | { | |
6063 | fprintf (dump, ";;\tReady list (final): "); | |
6064 | debug_ready_list (ready, n_ready); | |
6065 | print_block_visualization (b, ""); | |
6066 | } | |
6067 | ||
6068 | /* Sanity check -- queue must be empty now. Meaningless if region has | |
cc132865 | 6069 | multiple bbs. */ |
8c660648 | 6070 | if (current_nr_blocks > 1) |
cc132865 JL |
6071 | if (!flag_schedule_interblock && q_size != 0) |
6072 | abort (); | |
8c660648 | 6073 | |
63de6c74 | 6074 | /* Update head/tail boundaries. */ |
8c660648 JL |
6075 | head = NEXT_INSN (prev_head); |
6076 | tail = last; | |
6077 | ||
8c660648 JL |
6078 | /* Restore-other-notes: NOTE_LIST is the end of a chain of notes |
6079 | previously found among the insns. Insert them at the beginning | |
6080 | of the insns. */ | |
6081 | if (note_list != 0) | |
6082 | { | |
6083 | rtx note_head = note_list; | |
6084 | ||
6085 | while (PREV_INSN (note_head)) | |
6086 | { | |
6087 | note_head = PREV_INSN (note_head); | |
6088 | } | |
6089 | ||
6090 | PREV_INSN (note_head) = PREV_INSN (head); | |
6091 | NEXT_INSN (PREV_INSN (head)) = note_head; | |
6092 | PREV_INSN (head) = note_list; | |
6093 | NEXT_INSN (note_list) = head; | |
6094 | head = note_head; | |
6095 | } | |
6096 | ||
63de6c74 | 6097 | /* Update target block boundaries. */ |
8c660648 | 6098 | if (new_needs & NEED_HEAD) |
3b413743 | 6099 | BLOCK_HEAD (b) = head; |
8c660648 JL |
6100 | |
6101 | if (new_needs & NEED_TAIL) | |
3b413743 | 6102 | BLOCK_END (b) = tail; |
8c660648 | 6103 | |
63de6c74 | 6104 | /* Debugging. */ |
8c660648 JL |
6105 | if (sched_verbose) |
6106 | { | |
6107 | fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n", | |
3b413743 | 6108 | clock_var, INSN_UID (BLOCK_HEAD (b))); |
8c660648 | 6109 | fprintf (dump, ";; new basic block end = %d\n\n", |
3b413743 | 6110 | INSN_UID (BLOCK_END (b))); |
8c660648 JL |
6111 | } |
6112 | ||
98903742 MM |
6113 | /* Clean up. */ |
6114 | if (current_nr_blocks > 1) | |
6115 | { | |
6116 | free (candidate_table); | |
6117 | free (bblst_table); | |
6118 | free (bitlst_table); | |
6119 | } | |
6120 | free (ready); | |
6121 | ||
8c660648 JL |
6122 | return (sched_n_insns); |
6123 | } /* schedule_block () */ | |
6124 | \f | |
6125 | ||
63de6c74 | 6126 | /* Print the bit-set of registers, S, callable from debugger. */ |
8c660648 JL |
6127 | |
6128 | extern void | |
6129 | debug_reg_vector (s) | |
6130 | regset s; | |
6131 | { | |
6132 | int regno; | |
6133 | ||
6134 | EXECUTE_IF_SET_IN_REG_SET (s, 0, regno, | |
6135 | { | |
6136 | fprintf (dump, " %d", regno); | |
6137 | }); | |
6138 | ||
6139 | fprintf (dump, "\n"); | |
6140 | } | |
6141 | ||
6142 | /* Use the backward dependences from LOG_LINKS to build | |
6143 | forward dependences in INSN_DEPEND. */ | |
6144 | ||
6145 | static void | |
6146 | compute_block_forward_dependences (bb) | |
6147 | int bb; | |
6148 | { | |
6149 | rtx insn, link; | |
6150 | rtx tail, head; | |
6151 | rtx next_tail; | |
6152 | enum reg_note dep_type; | |
6153 | ||
49c3bb12 | 6154 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
6155 | next_tail = NEXT_INSN (tail); |
6156 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6157 | { | |
6158 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6159 | continue; | |
6160 | ||
6161 | insn = group_leader (insn); | |
6162 | ||
6163 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
6164 | { | |
6165 | rtx x = group_leader (XEXP (link, 0)); | |
6166 | rtx new_link; | |
6167 | ||
6168 | if (x != XEXP (link, 0)) | |
6169 | continue; | |
6170 | ||
706c5c2f JL |
6171 | #ifdef ENABLE_CHECKING |
6172 | /* If add_dependence is working properly there should never | |
6173 | be notes, deleted insns or duplicates in the backward | |
6174 | links. Thus we need not check for them here. | |
6175 | ||
6176 | However, if we have enabled checking we might as well go | |
6177 | ahead and verify that add_dependence worked properly. */ | |
6178 | if (GET_CODE (x) == NOTE | |
6179 | || INSN_DELETED_P (x) | |
6180 | || find_insn_list (insn, INSN_DEPEND (x))) | |
6181 | abort (); | |
6182 | #endif | |
8c660648 | 6183 | |
ebb7b10b | 6184 | new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x)); |
8c660648 JL |
6185 | |
6186 | dep_type = REG_NOTE_KIND (link); | |
6187 | PUT_REG_NOTE_KIND (new_link, dep_type); | |
6188 | ||
8c660648 JL |
6189 | INSN_DEPEND (x) = new_link; |
6190 | INSN_DEP_COUNT (insn) += 1; | |
6191 | } | |
6192 | } | |
6193 | } | |
6194 | ||
6195 | /* Initialize variables for region data dependence analysis. | |
63de6c74 | 6196 | n_bbs is the number of region blocks. */ |
8c660648 | 6197 | |
6d3352d9 | 6198 | __inline static void |
8c660648 JL |
6199 | init_rgn_data_dependences (n_bbs) |
6200 | int n_bbs; | |
6201 | { | |
6202 | int bb; | |
6203 | ||
63de6c74 | 6204 | /* Variables for which one copy exists for each block. */ |
8c660648 JL |
6205 | bzero ((char *) bb_pending_read_insns, n_bbs * sizeof (rtx)); |
6206 | bzero ((char *) bb_pending_read_mems, n_bbs * sizeof (rtx)); | |
6207 | bzero ((char *) bb_pending_write_insns, n_bbs * sizeof (rtx)); | |
6208 | bzero ((char *) bb_pending_write_mems, n_bbs * sizeof (rtx)); | |
920a303d | 6209 | bzero ((char *) bb_pending_lists_length, n_bbs * sizeof (int)); |
8c660648 JL |
6210 | bzero ((char *) bb_last_pending_memory_flush, n_bbs * sizeof (rtx)); |
6211 | bzero ((char *) bb_last_function_call, n_bbs * sizeof (rtx)); | |
6212 | bzero ((char *) bb_sched_before_next_call, n_bbs * sizeof (rtx)); | |
6213 | ||
6214 | /* Create an insn here so that we can hang dependencies off of it later. */ | |
6215 | for (bb = 0; bb < n_bbs; bb++) | |
6216 | { | |
6217 | bb_sched_before_next_call[bb] = | |
38a448ca RH |
6218 | gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
6219 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
6220 | LOG_LINKS (bb_sched_before_next_call[bb]) = 0; |
6221 | } | |
6222 | } | |
6223 | ||
63de6c74 MH |
6224 | /* Add dependences so that branches are scheduled to run last in their |
6225 | block. */ | |
8c660648 JL |
6226 | |
6227 | static void | |
6228 | add_branch_dependences (head, tail) | |
6229 | rtx head, tail; | |
6230 | { | |
6231 | ||
6232 | rtx insn, last; | |
6233 | ||
b182031e RH |
6234 | /* For all branches, calls, uses, clobbers, and cc0 setters, force them |
6235 | to remain in order at the end of the block by adding dependencies and | |
6236 | giving the last a high priority. There may be notes present, and | |
6237 | prev_head may also be a note. | |
8c660648 JL |
6238 | |
6239 | Branches must obviously remain at the end. Calls should remain at the | |
6240 | end since moving them results in worse register allocation. Uses remain | |
6241 | at the end to ensure proper register allocation. cc0 setters remaim | |
6242 | at the end because they can't be moved away from their cc0 user. */ | |
6243 | insn = tail; | |
6244 | last = 0; | |
b182031e RH |
6245 | while (GET_CODE (insn) == CALL_INSN |
6246 | || GET_CODE (insn) == JUMP_INSN | |
8c660648 JL |
6247 | || (GET_CODE (insn) == INSN |
6248 | && (GET_CODE (PATTERN (insn)) == USE | |
b182031e | 6249 | || GET_CODE (PATTERN (insn)) == CLOBBER |
8c660648 JL |
6250 | #ifdef HAVE_cc0 |
6251 | || sets_cc0_p (PATTERN (insn)) | |
6252 | #endif | |
6253 | )) | |
6254 | || GET_CODE (insn) == NOTE) | |
6255 | { | |
6256 | if (GET_CODE (insn) != NOTE) | |
6257 | { | |
6258 | if (last != 0 | |
6259 | && !find_insn_list (insn, LOG_LINKS (last))) | |
6260 | { | |
6261 | add_dependence (last, insn, REG_DEP_ANTI); | |
6262 | INSN_REF_COUNT (insn)++; | |
6263 | } | |
6264 | ||
6265 | CANT_MOVE (insn) = 1; | |
6266 | ||
6267 | last = insn; | |
326ee7a3 JL |
6268 | /* Skip over insns that are part of a group. |
6269 | Make each insn explicitly depend on the previous insn. | |
6270 | This ensures that only the group header will ever enter | |
6271 | the ready queue (and, when scheduled, will automatically | |
6272 | schedule the SCHED_GROUP_P block). */ | |
8c660648 | 6273 | while (SCHED_GROUP_P (insn)) |
326ee7a3 JL |
6274 | { |
6275 | rtx temp = prev_nonnote_insn (insn); | |
6276 | add_dependence (insn, temp, REG_DEP_ANTI); | |
6277 | insn = temp; | |
6278 | } | |
8c660648 JL |
6279 | } |
6280 | ||
6281 | /* Don't overrun the bounds of the basic block. */ | |
6282 | if (insn == head) | |
6283 | break; | |
6284 | ||
6285 | insn = PREV_INSN (insn); | |
6286 | } | |
6287 | ||
63de6c74 | 6288 | /* Make sure these insns are scheduled last in their block. */ |
8c660648 JL |
6289 | insn = last; |
6290 | if (insn != 0) | |
6291 | while (insn != head) | |
6292 | { | |
6293 | insn = prev_nonnote_insn (insn); | |
6294 | ||
6295 | if (INSN_REF_COUNT (insn) != 0) | |
6296 | continue; | |
6297 | ||
87373fba | 6298 | add_dependence (last, insn, REG_DEP_ANTI); |
8c660648 JL |
6299 | INSN_REF_COUNT (insn) = 1; |
6300 | ||
6301 | /* Skip over insns that are part of a group. */ | |
6302 | while (SCHED_GROUP_P (insn)) | |
6303 | insn = prev_nonnote_insn (insn); | |
6304 | } | |
6305 | } | |
6306 | ||
63de6c74 | 6307 | /* Compute backward dependences inside bb. In a multiple blocks region: |
8c660648 JL |
6308 | (1) a bb is analyzed after its predecessors, and (2) the lists in |
6309 | effect at the end of bb (after analyzing for bb) are inherited by | |
6310 | bb's successrs. | |
6311 | ||
6312 | Specifically for reg-reg data dependences, the block insns are | |
6313 | scanned by sched_analyze () top-to-bottom. Two lists are | |
63de6c74 | 6314 | maintained by sched_analyze (): reg_last_sets[] for register DEFs, |
8c660648 JL |
6315 | and reg_last_uses[] for register USEs. |
6316 | ||
6317 | When analysis is completed for bb, we update for its successors: | |
6318 | ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb]) | |
6319 | ; - USES[succ] = Union (USES [succ], DEFS [bb]) | |
6320 | ||
6321 | The mechanism for computing mem-mem data dependence is very | |
6322 | similar, and the result is interblock dependences in the region. */ | |
6323 | ||
6324 | static void | |
6325 | compute_block_backward_dependences (bb) | |
6326 | int bb; | |
6327 | { | |
6328 | int b; | |
6329 | rtx x; | |
6330 | rtx head, tail; | |
6331 | int max_reg = max_reg_num (); | |
6332 | ||
6333 | b = BB_TO_BLOCK (bb); | |
6334 | ||
6335 | if (current_nr_blocks == 1) | |
6336 | { | |
98903742 MM |
6337 | reg_last_uses = (rtx *) xcalloc (max_reg, sizeof (rtx)); |
6338 | reg_last_sets = (rtx *) xcalloc (max_reg, sizeof (rtx)); | |
6339 | reg_last_clobbers = (rtx *) xcalloc (max_reg, sizeof (rtx)); | |
8c660648 JL |
6340 | |
6341 | pending_read_insns = 0; | |
6342 | pending_read_mems = 0; | |
6343 | pending_write_insns = 0; | |
6344 | pending_write_mems = 0; | |
6345 | pending_lists_length = 0; | |
6346 | last_function_call = 0; | |
6347 | last_pending_memory_flush = 0; | |
6348 | sched_before_next_call | |
38a448ca RH |
6349 | = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
6350 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
6351 | LOG_LINKS (sched_before_next_call) = 0; |
6352 | } | |
6353 | else | |
6354 | { | |
6355 | reg_last_uses = bb_reg_last_uses[bb]; | |
6356 | reg_last_sets = bb_reg_last_sets[bb]; | |
28c95eff | 6357 | reg_last_clobbers = bb_reg_last_clobbers[bb]; |
8c660648 JL |
6358 | |
6359 | pending_read_insns = bb_pending_read_insns[bb]; | |
6360 | pending_read_mems = bb_pending_read_mems[bb]; | |
6361 | pending_write_insns = bb_pending_write_insns[bb]; | |
6362 | pending_write_mems = bb_pending_write_mems[bb]; | |
6363 | pending_lists_length = bb_pending_lists_length[bb]; | |
6364 | last_function_call = bb_last_function_call[bb]; | |
6365 | last_pending_memory_flush = bb_last_pending_memory_flush[bb]; | |
6366 | ||
6367 | sched_before_next_call = bb_sched_before_next_call[bb]; | |
6368 | } | |
6369 | ||
63de6c74 | 6370 | /* Do the analysis for this block. */ |
49c3bb12 | 6371 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
6372 | sched_analyze (head, tail); |
6373 | add_branch_dependences (head, tail); | |
6374 | ||
6375 | if (current_nr_blocks > 1) | |
6376 | { | |
6377 | int e, first_edge; | |
6378 | int b_succ, bb_succ; | |
6379 | int reg; | |
6380 | rtx link_insn, link_mem; | |
6381 | rtx u; | |
6382 | ||
63de6c74 MH |
6383 | /* These lists should point to the right place, for correct |
6384 | freeing later. */ | |
8c660648 JL |
6385 | bb_pending_read_insns[bb] = pending_read_insns; |
6386 | bb_pending_read_mems[bb] = pending_read_mems; | |
6387 | bb_pending_write_insns[bb] = pending_write_insns; | |
6388 | bb_pending_write_mems[bb] = pending_write_mems; | |
6389 | ||
63de6c74 | 6390 | /* bb's structures are inherited by it's successors. */ |
8c660648 JL |
6391 | first_edge = e = OUT_EDGES (b); |
6392 | if (e > 0) | |
6393 | do | |
6394 | { | |
6395 | b_succ = TO_BLOCK (e); | |
6396 | bb_succ = BLOCK_TO_BB (b_succ); | |
6397 | ||
63de6c74 | 6398 | /* Only bbs "below" bb, in the same region, are interesting. */ |
8c660648 JL |
6399 | if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ) |
6400 | || bb_succ <= bb) | |
6401 | { | |
6402 | e = NEXT_OUT (e); | |
6403 | continue; | |
6404 | } | |
6405 | ||
6406 | for (reg = 0; reg < max_reg; reg++) | |
6407 | { | |
6408 | ||
63de6c74 | 6409 | /* reg-last-uses lists are inherited by bb_succ. */ |
8c660648 JL |
6410 | for (u = reg_last_uses[reg]; u; u = XEXP (u, 1)) |
6411 | { | |
63de6c74 MH |
6412 | if (find_insn_list (XEXP (u, 0), |
6413 | (bb_reg_last_uses[bb_succ])[reg])) | |
8c660648 JL |
6414 | continue; |
6415 | ||
6416 | (bb_reg_last_uses[bb_succ])[reg] | |
ebb7b10b RH |
6417 | = alloc_INSN_LIST (XEXP (u, 0), |
6418 | (bb_reg_last_uses[bb_succ])[reg]); | |
8c660648 JL |
6419 | } |
6420 | ||
63de6c74 | 6421 | /* reg-last-defs lists are inherited by bb_succ. */ |
8c660648 JL |
6422 | for (u = reg_last_sets[reg]; u; u = XEXP (u, 1)) |
6423 | { | |
63de6c74 MH |
6424 | if (find_insn_list (XEXP (u, 0), |
6425 | (bb_reg_last_sets[bb_succ])[reg])) | |
8c660648 JL |
6426 | continue; |
6427 | ||
6428 | (bb_reg_last_sets[bb_succ])[reg] | |
ebb7b10b RH |
6429 | = alloc_INSN_LIST (XEXP (u, 0), |
6430 | (bb_reg_last_sets[bb_succ])[reg]); | |
8c660648 | 6431 | } |
28c95eff RH |
6432 | |
6433 | for (u = reg_last_clobbers[reg]; u; u = XEXP (u, 1)) | |
6434 | { | |
63de6c74 MH |
6435 | if (find_insn_list (XEXP (u, 0), |
6436 | (bb_reg_last_clobbers[bb_succ])[reg])) | |
28c95eff RH |
6437 | continue; |
6438 | ||
6439 | (bb_reg_last_clobbers[bb_succ])[reg] | |
6440 | = alloc_INSN_LIST (XEXP (u, 0), | |
6441 | (bb_reg_last_clobbers[bb_succ])[reg]); | |
6442 | } | |
8c660648 JL |
6443 | } |
6444 | ||
63de6c74 | 6445 | /* Mem read/write lists are inherited by bb_succ. */ |
8c660648 JL |
6446 | link_insn = pending_read_insns; |
6447 | link_mem = pending_read_mems; | |
6448 | while (link_insn) | |
6449 | { | |
63de6c74 MH |
6450 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
6451 | XEXP (link_mem, 0), | |
8c660648 JL |
6452 | bb_pending_read_insns[bb_succ], |
6453 | bb_pending_read_mems[bb_succ]))) | |
6454 | add_insn_mem_dependence (&bb_pending_read_insns[bb_succ], | |
6455 | &bb_pending_read_mems[bb_succ], | |
6456 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
6457 | link_insn = XEXP (link_insn, 1); | |
6458 | link_mem = XEXP (link_mem, 1); | |
6459 | } | |
6460 | ||
6461 | link_insn = pending_write_insns; | |
6462 | link_mem = pending_write_mems; | |
6463 | while (link_insn) | |
6464 | { | |
63de6c74 MH |
6465 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
6466 | XEXP (link_mem, 0), | |
8c660648 JL |
6467 | bb_pending_write_insns[bb_succ], |
6468 | bb_pending_write_mems[bb_succ]))) | |
6469 | add_insn_mem_dependence (&bb_pending_write_insns[bb_succ], | |
6470 | &bb_pending_write_mems[bb_succ], | |
6471 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
6472 | ||
6473 | link_insn = XEXP (link_insn, 1); | |
6474 | link_mem = XEXP (link_mem, 1); | |
6475 | } | |
6476 | ||
63de6c74 | 6477 | /* last_function_call is inherited by bb_succ. */ |
8c660648 JL |
6478 | for (u = last_function_call; u; u = XEXP (u, 1)) |
6479 | { | |
63de6c74 MH |
6480 | if (find_insn_list (XEXP (u, 0), |
6481 | bb_last_function_call[bb_succ])) | |
8c660648 JL |
6482 | continue; |
6483 | ||
6484 | bb_last_function_call[bb_succ] | |
ebb7b10b RH |
6485 | = alloc_INSN_LIST (XEXP (u, 0), |
6486 | bb_last_function_call[bb_succ]); | |
8c660648 JL |
6487 | } |
6488 | ||
63de6c74 | 6489 | /* last_pending_memory_flush is inherited by bb_succ. */ |
8c660648 JL |
6490 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
6491 | { | |
63de6c74 MH |
6492 | if (find_insn_list (XEXP (u, 0), |
6493 | bb_last_pending_memory_flush[bb_succ])) | |
8c660648 JL |
6494 | continue; |
6495 | ||
6496 | bb_last_pending_memory_flush[bb_succ] | |
ebb7b10b RH |
6497 | = alloc_INSN_LIST (XEXP (u, 0), |
6498 | bb_last_pending_memory_flush[bb_succ]); | |
8c660648 JL |
6499 | } |
6500 | ||
63de6c74 | 6501 | /* sched_before_next_call is inherited by bb_succ. */ |
8c660648 JL |
6502 | x = LOG_LINKS (sched_before_next_call); |
6503 | for (; x; x = XEXP (x, 1)) | |
6504 | add_dependence (bb_sched_before_next_call[bb_succ], | |
6505 | XEXP (x, 0), REG_DEP_ANTI); | |
6506 | ||
6507 | e = NEXT_OUT (e); | |
6508 | } | |
6509 | while (e != first_edge); | |
6510 | } | |
ebb7b10b | 6511 | |
63de6c74 | 6512 | /* Free up the INSN_LISTs. |
7eea6443 JL |
6513 | |
6514 | Note this loop is executed max_reg * nr_regions times. It's first | |
5a4f6418 AM |
6515 | implementation accounted for over 90% of the calls to free_INSN_LIST_list. |
6516 | The list was empty for the vast majority of those calls. On the PA, not | |
6517 | calling free_INSN_LIST_list in those cases improves -O2 compile times by | |
7eea6443 | 6518 | 3-5% on average. */ |
ebb7b10b RH |
6519 | for (b = 0; b < max_reg; ++b) |
6520 | { | |
28c95eff | 6521 | if (reg_last_clobbers[b]) |
5a4f6418 | 6522 | free_INSN_LIST_list (®_last_clobbers[b]); |
7eea6443 | 6523 | if (reg_last_sets[b]) |
5a4f6418 | 6524 | free_INSN_LIST_list (®_last_sets[b]); |
7eea6443 | 6525 | if (reg_last_uses[b]) |
5a4f6418 | 6526 | free_INSN_LIST_list (®_last_uses[b]); |
ebb7b10b RH |
6527 | } |
6528 | ||
6529 | /* Assert that we won't need bb_reg_last_* for this block anymore. */ | |
6530 | if (current_nr_blocks > 1) | |
6531 | { | |
6532 | bb_reg_last_uses[bb] = (rtx *) NULL_RTX; | |
6533 | bb_reg_last_sets[bb] = (rtx *) NULL_RTX; | |
28c95eff | 6534 | bb_reg_last_clobbers[bb] = (rtx *) NULL_RTX; |
ebb7b10b | 6535 | } |
98903742 MM |
6536 | else if (current_nr_blocks == 1) |
6537 | { | |
6538 | free (reg_last_uses); | |
6539 | free (reg_last_sets); | |
6540 | free (reg_last_clobbers); | |
6541 | } | |
8c660648 JL |
6542 | } |
6543 | ||
63de6c74 | 6544 | /* Print dependences for debugging, callable from debugger. */ |
8c660648 JL |
6545 | |
6546 | void | |
6547 | debug_dependencies () | |
6548 | { | |
6549 | int bb; | |
6550 | ||
6551 | fprintf (dump, ";; --------------- forward dependences: ------------ \n"); | |
6552 | for (bb = 0; bb < current_nr_blocks; bb++) | |
6553 | { | |
6554 | if (1) | |
6555 | { | |
6556 | rtx head, tail; | |
6557 | rtx next_tail; | |
6558 | rtx insn; | |
6559 | ||
49c3bb12 | 6560 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
6561 | next_tail = NEXT_INSN (tail); |
6562 | fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n", | |
6563 | BB_TO_BLOCK (bb), bb); | |
6564 | ||
6565 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
6566 | "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units"); | |
6567 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
6568 | "----", "----", "--", "---", "----", "----", "--------", "-----"); | |
6569 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6570 | { | |
6571 | rtx link; | |
6572 | int unit, range; | |
6573 | ||
6574 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6575 | { | |
6576 | int n; | |
6577 | fprintf (dump, ";; %6d ", INSN_UID (insn)); | |
6578 | if (GET_CODE (insn) == NOTE) | |
ebc25a17 MM |
6579 | { |
6580 | n = NOTE_LINE_NUMBER (insn); | |
6581 | if (n < 0) | |
6582 | fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n)); | |
6583 | else | |
6584 | fprintf (dump, "line %d, file %s\n", n, | |
6585 | NOTE_SOURCE_FILE (insn)); | |
6586 | } | |
6587 | else | |
4f64eaca | 6588 | fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn))); |
8c660648 JL |
6589 | continue; |
6590 | } | |
6591 | ||
6592 | unit = insn_unit (insn); | |
6593 | range = (unit < 0 | |
6594 | || function_units[unit].blockage_range_function == 0) ? 0 : | |
6595 | function_units[unit].blockage_range_function (insn); | |
6596 | fprintf (dump, | |
6597 | ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ", | |
6598 | (SCHED_GROUP_P (insn) ? "+" : " "), | |
6599 | INSN_UID (insn), | |
6600 | INSN_CODE (insn), | |
6601 | INSN_BB (insn), | |
6602 | INSN_DEP_COUNT (insn), | |
6603 | INSN_PRIORITY (insn), | |
6604 | insn_cost (insn, 0, 0), | |
6605 | (int) MIN_BLOCKAGE_COST (range), | |
6606 | (int) MAX_BLOCKAGE_COST (range)); | |
6607 | insn_print_units (insn); | |
6608 | fprintf (dump, "\t: "); | |
6609 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
6610 | fprintf (dump, "%d ", INSN_UID (XEXP (link, 0))); | |
6611 | fprintf (dump, "\n"); | |
6612 | } | |
6613 | } | |
6614 | } | |
6615 | fprintf (dump, "\n"); | |
6616 | } | |
6617 | ||
63de6c74 | 6618 | /* Set_priorities: compute priority of each insn in the block. */ |
8c660648 JL |
6619 | |
6620 | static int | |
6621 | set_priorities (bb) | |
6622 | int bb; | |
6623 | { | |
6624 | rtx insn; | |
6625 | int n_insn; | |
6626 | ||
6627 | rtx tail; | |
6628 | rtx prev_head; | |
6629 | rtx head; | |
6630 | ||
49c3bb12 | 6631 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
6632 | prev_head = PREV_INSN (head); |
6633 | ||
6634 | if (head == tail | |
6635 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6636 | return 0; | |
6637 | ||
6638 | n_insn = 0; | |
6639 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) | |
6640 | { | |
6641 | ||
6642 | if (GET_CODE (insn) == NOTE) | |
6643 | continue; | |
6644 | ||
6645 | if (!(SCHED_GROUP_P (insn))) | |
6646 | n_insn++; | |
6647 | (void) priority (insn); | |
6648 | } | |
6649 | ||
6650 | return n_insn; | |
6651 | } | |
6652 | ||
6653 | /* Make each element of VECTOR point at an rtx-vector, | |
6654 | taking the space for all those rtx-vectors from SPACE. | |
6655 | SPACE is of type (rtx *), but it is really as long as NELTS rtx-vectors. | |
6656 | BYTES_PER_ELT is the number of bytes in one rtx-vector. | |
63de6c74 | 6657 | (this is the same as init_regset_vector () in flow.c) */ |
8c660648 JL |
6658 | |
6659 | static void | |
6660 | init_rtx_vector (vector, space, nelts, bytes_per_elt) | |
6661 | rtx **vector; | |
6662 | rtx *space; | |
6663 | int nelts; | |
6664 | int bytes_per_elt; | |
6665 | { | |
6666 | register int i; | |
6667 | register rtx *p = space; | |
6668 | ||
6669 | for (i = 0; i < nelts; i++) | |
6670 | { | |
6671 | vector[i] = p; | |
6672 | p += bytes_per_elt / sizeof (*p); | |
6673 | } | |
6674 | } | |
6675 | ||
6676 | /* Schedule a region. A region is either an inner loop, a loop-free | |
6677 | subroutine, or a single basic block. Each bb in the region is | |
6678 | scheduled after its flow predecessors. */ | |
6679 | ||
6680 | static void | |
6681 | schedule_region (rgn) | |
6682 | int rgn; | |
6683 | { | |
6684 | int bb; | |
6685 | int rgn_n_insns = 0; | |
6686 | int sched_rgn_n_insns = 0; | |
98903742 MM |
6687 | rtx *bb_reg_last_uses_space = NULL; |
6688 | rtx *bb_reg_last_sets_space = NULL; | |
6689 | rtx *bb_reg_last_clobbers_space = NULL; | |
8c660648 | 6690 | |
63de6c74 | 6691 | /* Set variables for the current region. */ |
8c660648 JL |
6692 | current_nr_blocks = RGN_NR_BLOCKS (rgn); |
6693 | current_blocks = RGN_BLOCKS (rgn); | |
6694 | ||
6695 | reg_pending_sets = ALLOCA_REG_SET (); | |
28c95eff | 6696 | reg_pending_clobbers = ALLOCA_REG_SET (); |
8c660648 JL |
6697 | reg_pending_sets_all = 0; |
6698 | ||
63de6c74 | 6699 | /* Initializations for region data dependence analyisis. */ |
8c660648 JL |
6700 | if (current_nr_blocks > 1) |
6701 | { | |
8c660648 JL |
6702 | int maxreg = max_reg_num (); |
6703 | ||
98903742 MM |
6704 | bb_reg_last_uses = (rtx **) xmalloc (current_nr_blocks * sizeof (rtx *)); |
6705 | bb_reg_last_uses_space | |
6706 | = (rtx *) xcalloc (current_nr_blocks * maxreg, sizeof (rtx)); | |
6707 | init_rtx_vector (bb_reg_last_uses, bb_reg_last_uses_space, | |
6708 | current_nr_blocks, maxreg * sizeof (rtx *)); | |
8c660648 | 6709 | |
98903742 MM |
6710 | bb_reg_last_sets = (rtx **) xmalloc (current_nr_blocks * sizeof (rtx *)); |
6711 | bb_reg_last_sets_space | |
6712 | = (rtx *) xcalloc (current_nr_blocks * maxreg, sizeof (rtx)); | |
6713 | init_rtx_vector (bb_reg_last_sets, bb_reg_last_sets_space, | |
6714 | current_nr_blocks, maxreg * sizeof (rtx *)); | |
28c95eff RH |
6715 | |
6716 | bb_reg_last_clobbers = | |
98903742 MM |
6717 | (rtx **) xmalloc (current_nr_blocks * sizeof (rtx *)); |
6718 | bb_reg_last_clobbers_space | |
6719 | = (rtx *) xcalloc (current_nr_blocks * maxreg, sizeof (rtx)); | |
6720 | init_rtx_vector (bb_reg_last_clobbers, bb_reg_last_clobbers_space, | |
6721 | current_nr_blocks, maxreg * sizeof (rtx *)); | |
6722 | ||
6723 | bb_pending_read_insns | |
6724 | = (rtx *) xmalloc (current_nr_blocks * sizeof (rtx)); | |
6725 | bb_pending_read_mems | |
6726 | = (rtx *) xmalloc (current_nr_blocks * sizeof (rtx)); | |
28c95eff | 6727 | bb_pending_write_insns = |
98903742 MM |
6728 | (rtx *) xmalloc (current_nr_blocks * sizeof (rtx)); |
6729 | bb_pending_write_mems | |
6730 | = (rtx *) xmalloc (current_nr_blocks * sizeof (rtx)); | |
28c95eff | 6731 | bb_pending_lists_length = |
98903742 | 6732 | (int *) xmalloc (current_nr_blocks * sizeof (int)); |
28c95eff | 6733 | bb_last_pending_memory_flush = |
98903742 MM |
6734 | (rtx *) xmalloc (current_nr_blocks * sizeof (rtx)); |
6735 | bb_last_function_call | |
6736 | = (rtx *) xmalloc (current_nr_blocks * sizeof (rtx)); | |
28c95eff | 6737 | bb_sched_before_next_call = |
98903742 | 6738 | (rtx *) xmalloc (current_nr_blocks * sizeof (rtx)); |
8c660648 JL |
6739 | |
6740 | init_rgn_data_dependences (current_nr_blocks); | |
6741 | } | |
6742 | ||
63de6c74 | 6743 | /* Compute LOG_LINKS. */ |
8c660648 JL |
6744 | for (bb = 0; bb < current_nr_blocks; bb++) |
6745 | compute_block_backward_dependences (bb); | |
6746 | ||
63de6c74 | 6747 | /* Compute INSN_DEPEND. */ |
8c660648 JL |
6748 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) |
6749 | compute_block_forward_dependences (bb); | |
6750 | ||
c46a37c4 | 6751 | /* Delete line notes and set priorities. */ |
8c660648 JL |
6752 | for (bb = 0; bb < current_nr_blocks; bb++) |
6753 | { | |
8c660648 JL |
6754 | if (write_symbols != NO_DEBUG) |
6755 | { | |
6756 | save_line_notes (bb); | |
6757 | rm_line_notes (bb); | |
6758 | } | |
6759 | ||
6760 | rgn_n_insns += set_priorities (bb); | |
6761 | } | |
6762 | ||
63de6c74 | 6763 | /* Compute interblock info: probabilities, split-edges, dominators, etc. */ |
8c660648 JL |
6764 | if (current_nr_blocks > 1) |
6765 | { | |
6766 | int i; | |
6767 | ||
98903742 | 6768 | prob = (float *) xmalloc ((current_nr_blocks) * sizeof (float)); |
8c660648 JL |
6769 | |
6770 | bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1; | |
98903742 | 6771 | dom = (bbset *) xmalloc (current_nr_blocks * sizeof (bbset)); |
8c660648 | 6772 | for (i = 0; i < current_nr_blocks; i++) |
98903742 | 6773 | dom[i] = (bbset) xcalloc (bbset_size, sizeof (HOST_WIDE_INT)); |
8c660648 | 6774 | |
63de6c74 | 6775 | /* Edge to bit. */ |
8c660648 | 6776 | rgn_nr_edges = 0; |
98903742 | 6777 | edge_to_bit = (int *) xmalloc (nr_edges * sizeof (int)); |
8c660648 JL |
6778 | for (i = 1; i < nr_edges; i++) |
6779 | if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn) | |
6780 | EDGE_TO_BIT (i) = rgn_nr_edges++; | |
98903742 | 6781 | rgn_edges = (int *) xmalloc (rgn_nr_edges * sizeof (int)); |
8c660648 JL |
6782 | |
6783 | rgn_nr_edges = 0; | |
6784 | for (i = 1; i < nr_edges; i++) | |
6785 | if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn)) | |
6786 | rgn_edges[rgn_nr_edges++] = i; | |
6787 | ||
63de6c74 | 6788 | /* Split edges. */ |
8c660648 | 6789 | edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1; |
98903742 MM |
6790 | pot_split = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset)); |
6791 | ancestor_edges | |
6792 | = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset)); | |
8c660648 JL |
6793 | for (i = 0; i < current_nr_blocks; i++) |
6794 | { | |
6795 | pot_split[i] = | |
98903742 | 6796 | (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT)); |
8c660648 | 6797 | ancestor_edges[i] = |
98903742 | 6798 | (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT)); |
8c660648 JL |
6799 | } |
6800 | ||
63de6c74 | 6801 | /* Compute probabilities, dominators, split_edges. */ |
8c660648 JL |
6802 | for (bb = 0; bb < current_nr_blocks; bb++) |
6803 | compute_dom_prob_ps (bb); | |
6804 | } | |
6805 | ||
63de6c74 | 6806 | /* Now we can schedule all blocks. */ |
8c660648 | 6807 | for (bb = 0; bb < current_nr_blocks; bb++) |
98903742 | 6808 | sched_rgn_n_insns += schedule_block (bb, rgn_n_insns); |
8c660648 | 6809 | |
63de6c74 | 6810 | /* Sanity check: verify that all region insns were scheduled. */ |
cc132865 JL |
6811 | if (sched_rgn_n_insns != rgn_n_insns) |
6812 | abort (); | |
8c660648 | 6813 | |
63de6c74 | 6814 | /* Restore line notes. */ |
8c660648 JL |
6815 | if (write_symbols != NO_DEBUG) |
6816 | { | |
6817 | for (bb = 0; bb < current_nr_blocks; bb++) | |
6818 | restore_line_notes (bb); | |
6819 | } | |
6820 | ||
63de6c74 | 6821 | /* Done with this region. */ |
8c660648 | 6822 | free_pending_lists (); |
f187056f JL |
6823 | |
6824 | FREE_REG_SET (reg_pending_sets); | |
28c95eff | 6825 | FREE_REG_SET (reg_pending_clobbers); |
98903742 MM |
6826 | |
6827 | if (current_nr_blocks > 1) | |
6828 | { | |
6829 | int i; | |
6830 | ||
6831 | free (bb_reg_last_uses_space); | |
6832 | free (bb_reg_last_uses); | |
6833 | free (bb_reg_last_sets_space); | |
6834 | free (bb_reg_last_sets); | |
6835 | free (bb_reg_last_clobbers_space); | |
6836 | free (bb_reg_last_clobbers); | |
6837 | free (bb_pending_read_insns); | |
6838 | free (bb_pending_read_mems); | |
6839 | free (bb_pending_write_insns); | |
6840 | free (bb_pending_write_mems); | |
6841 | free (bb_pending_lists_length); | |
6842 | free (bb_last_pending_memory_flush); | |
6843 | free (bb_last_function_call); | |
6844 | free (bb_sched_before_next_call); | |
6845 | free (prob); | |
6846 | for (i = 0; i < current_nr_blocks; ++i) | |
6847 | { | |
6848 | free (dom[i]); | |
6849 | free (pot_split[i]); | |
6850 | free (ancestor_edges[i]); | |
6851 | } | |
6852 | free (dom); | |
6853 | free (edge_to_bit); | |
6854 | free (rgn_edges); | |
6855 | free (pot_split); | |
6856 | free (ancestor_edges); | |
6857 | } | |
8c660648 JL |
6858 | } |
6859 | ||
8c660648 JL |
6860 | /* The one entry point in this file. DUMP_FILE is the dump file for |
6861 | this pass. */ | |
6862 | ||
6863 | void | |
6864 | schedule_insns (dump_file) | |
6865 | FILE *dump_file; | |
6866 | { | |
49c3bb12 RH |
6867 | int *deaths_in_region; |
6868 | sbitmap blocks, large_region_blocks; | |
8c660648 JL |
6869 | int max_uid; |
6870 | int b; | |
8c660648 JL |
6871 | rtx insn; |
6872 | int rgn; | |
8c660648 | 6873 | int luid; |
49c3bb12 | 6874 | int any_large_regions; |
8c660648 | 6875 | |
63de6c74 | 6876 | /* Disable speculative loads in their presence if cc0 defined. */ |
8c660648 JL |
6877 | #ifdef HAVE_cc0 |
6878 | flag_schedule_speculative_load = 0; | |
6879 | #endif | |
6880 | ||
6881 | /* Taking care of this degenerate case makes the rest of | |
6882 | this code simpler. */ | |
6883 | if (n_basic_blocks == 0) | |
6884 | return; | |
6885 | ||
63de6c74 | 6886 | /* Set dump and sched_verbose for the desired debugging output. If no |
8c660648 JL |
6887 | dump-file was specified, but -fsched-verbose-N (any N), print to stderr. |
6888 | For -fsched-verbose-N, N>=10, print everything to stderr. */ | |
6889 | sched_verbose = sched_verbose_param; | |
6890 | if (sched_verbose_param == 0 && dump_file) | |
6891 | sched_verbose = 1; | |
6892 | dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file); | |
6893 | ||
6894 | nr_inter = 0; | |
6895 | nr_spec = 0; | |
6896 | ||
63de6c74 | 6897 | /* Initialize issue_rate. */ |
62d65906 | 6898 | issue_rate = ISSUE_RATE; |
8c660648 | 6899 | |
d3a923ee | 6900 | split_all_insns (1); |
8c660648 | 6901 | |
c88e8206 RH |
6902 | /* We use LUID 0 for the fake insn (UID 0) which holds dependencies for |
6903 | pseudos which do not cross calls. */ | |
6904 | max_uid = get_max_uid () + 1; | |
8c660648 | 6905 | |
f66d83e1 | 6906 | h_i_d = (struct haifa_insn_data *) xcalloc (max_uid, sizeof (*h_i_d)); |
8c660648 | 6907 | |
f66d83e1 | 6908 | h_i_d[0].luid = 0; |
356edbd7 | 6909 | luid = 1; |
8c660648 | 6910 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 6911 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 | 6912 | { |
f77e39fc MM |
6913 | INSN_LUID (insn) = luid; |
6914 | ||
6915 | /* Increment the next luid, unless this is a note. We don't | |
6916 | really need separate IDs for notes and we don't want to | |
6917 | schedule differently depending on whether or not there are | |
6918 | line-number notes, i.e., depending on whether or not we're | |
6919 | generating debugging information. */ | |
6920 | if (GET_CODE (insn) != NOTE) | |
6921 | ++luid; | |
6922 | ||
3b413743 | 6923 | if (insn == BLOCK_END (b)) |
8c660648 JL |
6924 | break; |
6925 | } | |
356edbd7 JL |
6926 | |
6927 | /* ?!? We could save some memory by computing a per-region luid mapping | |
6928 | which could reduce both the number of vectors in the cache and the size | |
aae0390e JL |
6929 | of each vector. Instead we just avoid the cache entirely unless the |
6930 | average number of instructions in a basic block is very high. See | |
6931 | the comment before the declaration of true_dependency_cache for | |
6932 | what we consider "very high". */ | |
6933 | if (luid / n_basic_blocks > 100 * 5) | |
6934 | { | |
6935 | true_dependency_cache = sbitmap_vector_alloc (luid, luid); | |
6936 | sbitmap_vector_zero (true_dependency_cache, luid); | |
6937 | } | |
8c660648 | 6938 | |
8c660648 | 6939 | nr_regions = 0; |
98903742 MM |
6940 | rgn_table = (region *) xmalloc ((n_basic_blocks) * sizeof (region)); |
6941 | rgn_bb_table = (int *) xmalloc ((n_basic_blocks) * sizeof (int)); | |
6942 | block_to_bb = (int *) xmalloc ((n_basic_blocks) * sizeof (int)); | |
6943 | containing_rgn = (int *) xmalloc ((n_basic_blocks) * sizeof (int)); | |
8c660648 | 6944 | |
49c3bb12 RH |
6945 | blocks = sbitmap_alloc (n_basic_blocks); |
6946 | large_region_blocks = sbitmap_alloc (n_basic_blocks); | |
6947 | ||
c88e8206 RH |
6948 | compute_bb_for_insn (max_uid); |
6949 | ||
63de6c74 | 6950 | /* Compute regions for scheduling. */ |
8c660648 JL |
6951 | if (reload_completed |
6952 | || n_basic_blocks == 1 | |
6953 | || !flag_schedule_interblock) | |
6954 | { | |
6955 | find_single_block_region (); | |
6956 | } | |
6957 | else | |
6958 | { | |
63de6c74 | 6959 | /* Verify that a 'good' control flow graph can be built. */ |
168cbdf9 | 6960 | if (is_cfg_nonregular ()) |
8c660648 JL |
6961 | { |
6962 | find_single_block_region (); | |
6963 | } | |
6964 | else | |
6965 | { | |
a2e68776 JL |
6966 | int_list_ptr *s_preds, *s_succs; |
6967 | int *num_preds, *num_succs; | |
092ae4ba | 6968 | sbitmap *dom; |
a2e68776 | 6969 | |
98903742 MM |
6970 | s_preds = (int_list_ptr *) xmalloc (n_basic_blocks |
6971 | * sizeof (int_list_ptr)); | |
6972 | s_succs = (int_list_ptr *) xmalloc (n_basic_blocks | |
6973 | * sizeof (int_list_ptr)); | |
6974 | num_preds = (int *) xmalloc (n_basic_blocks * sizeof (int)); | |
6975 | num_succs = (int *) xmalloc (n_basic_blocks * sizeof (int)); | |
a2e68776 | 6976 | dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); |
a2e68776 JL |
6977 | |
6978 | /* The scheduler runs after flow; therefore, we can't blindly call | |
6979 | back into find_basic_blocks since doing so could invalidate the | |
e881bb1b | 6980 | info in global_live_at_start. |
a2e68776 JL |
6981 | |
6982 | Consider a block consisting entirely of dead stores; after life | |
6983 | analysis it would be a block of NOTE_INSN_DELETED notes. If | |
6984 | we call find_basic_blocks again, then the block would be removed | |
6985 | entirely and invalidate our the register live information. | |
6986 | ||
6987 | We could (should?) recompute register live information. Doing | |
6988 | so may even be beneficial. */ | |
6989 | ||
5d27de7d | 6990 | compute_preds_succs (s_preds, s_succs, num_preds, num_succs); |
a2e68776 | 6991 | |
63de6c74 MH |
6992 | /* Compute the dominators and post dominators. We don't |
6993 | currently use post dominators, but we should for | |
6994 | speculative motion analysis. */ | |
092ae4ba | 6995 | compute_flow_dominators (dom, NULL); |
a2e68776 | 6996 | |
168cbdf9 JL |
6997 | /* build_control_flow will return nonzero if it detects unreachable |
6998 | blocks or any other irregularity with the cfg which prevents | |
6999 | cross block scheduling. */ | |
a2e68776 | 7000 | if (build_control_flow (s_preds, s_succs, num_preds, num_succs) != 0) |
168cbdf9 JL |
7001 | find_single_block_region (); |
7002 | else | |
a2e68776 | 7003 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom); |
8c660648 JL |
7004 | |
7005 | if (sched_verbose >= 3) | |
a2e68776 | 7006 | debug_regions (); |
8c660648 | 7007 | |
a2e68776 | 7008 | /* For now. This will move as more and more of haifa is converted |
63de6c74 | 7009 | to using the cfg code in flow.c. */ |
a2e68776 JL |
7010 | free_bb_mem (); |
7011 | free (dom); | |
98903742 MM |
7012 | free (s_preds); |
7013 | free (s_succs); | |
7014 | free (num_preds); | |
7015 | free (num_succs); | |
8c660648 JL |
7016 | } |
7017 | } | |
7018 | ||
98903742 | 7019 | deaths_in_region = (int *) xmalloc (sizeof(int) * nr_regions); |
49c3bb12 | 7020 | |
8c660648 JL |
7021 | init_alias_analysis (); |
7022 | ||
7023 | if (write_symbols != NO_DEBUG) | |
7024 | { | |
7025 | rtx line; | |
7026 | ||
98903742 | 7027 | line_note_head = (rtx *) xcalloc (n_basic_blocks, sizeof (rtx)); |
8c660648 JL |
7028 | |
7029 | /* Save-line-note-head: | |
7030 | Determine the line-number at the start of each basic block. | |
7031 | This must be computed and saved now, because after a basic block's | |
7032 | predecessor has been scheduled, it is impossible to accurately | |
7033 | determine the correct line number for the first insn of the block. */ | |
7034 | ||
7035 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7036 | for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line)) |
8c660648 JL |
7037 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) |
7038 | { | |
7039 | line_note_head[b] = line; | |
7040 | break; | |
7041 | } | |
7042 | } | |
7043 | ||
63de6c74 | 7044 | /* Find units used in this fuction, for visualization. */ |
8c660648 JL |
7045 | if (sched_verbose) |
7046 | init_target_units (); | |
7047 | ||
7048 | /* ??? Add a NOTE after the last insn of the last basic block. It is not | |
7049 | known why this is done. */ | |
7050 | ||
3b413743 | 7051 | insn = BLOCK_END (n_basic_blocks - 1); |
8c660648 JL |
7052 | if (NEXT_INSN (insn) == 0 |
7053 | || (GET_CODE (insn) != NOTE | |
7054 | && GET_CODE (insn) != CODE_LABEL | |
3b413743 RH |
7055 | /* Don't emit a NOTE if it would end up between an unconditional |
7056 | jump and a BARRIER. */ | |
8c660648 JL |
7057 | && !(GET_CODE (insn) == JUMP_INSN |
7058 | && GET_CODE (NEXT_INSN (insn)) == BARRIER))) | |
3b413743 | 7059 | emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1)); |
8c660648 | 7060 | |
49c3bb12 RH |
7061 | /* Compute INSN_REG_WEIGHT for all blocks. We must do this before |
7062 | removing death notes. */ | |
7063 | for (b = n_basic_blocks - 1; b >= 0; b--) | |
7064 | find_insn_reg_weight (b); | |
7065 | ||
7066 | /* Remove all death notes from the subroutine. */ | |
7067 | for (rgn = 0; rgn < nr_regions; rgn++) | |
7068 | { | |
7069 | sbitmap_zero (blocks); | |
7070 | for (b = RGN_NR_BLOCKS (rgn) - 1; b >= 0; --b) | |
7071 | SET_BIT (blocks, rgn_bb_table [RGN_BLOCKS (rgn) + b]); | |
7072 | ||
7073 | deaths_in_region[rgn] = count_or_remove_death_notes (blocks, 1); | |
7074 | } | |
7075 | ||
63de6c74 | 7076 | /* Schedule every region in the subroutine. */ |
8c660648 | 7077 | for (rgn = 0; rgn < nr_regions; rgn++) |
98903742 | 7078 | schedule_region (rgn); |
8c660648 | 7079 | |
49c3bb12 RH |
7080 | /* Update life analysis for the subroutine. Do single block regions |
7081 | first so that we can verify that live_at_start didn't change. Then | |
7082 | do all other blocks. */ | |
7083 | /* ??? There is an outside possibility that update_life_info, or more | |
7084 | to the point propagate_block, could get called with non-zero flags | |
7085 | more than once for one basic block. This would be kinda bad if it | |
7086 | were to happen, since REG_INFO would be accumulated twice for the | |
7087 | block, and we'd have twice the REG_DEAD notes. | |
7088 | ||
7089 | I'm fairly certain that this _shouldn't_ happen, since I don't think | |
7090 | that live_at_start should change at region heads. Not sure what the | |
7091 | best way to test for this kind of thing... */ | |
7092 | ||
7093 | allocate_reg_life_data (); | |
7094 | compute_bb_for_insn (max_uid); | |
7095 | ||
7096 | any_large_regions = 0; | |
7097 | sbitmap_ones (large_region_blocks); | |
7098 | ||
7099 | for (rgn = 0; rgn < nr_regions; rgn++) | |
7100 | if (RGN_NR_BLOCKS (rgn) > 1) | |
7101 | any_large_regions = 1; | |
7102 | else | |
7103 | { | |
7104 | sbitmap_zero (blocks); | |
7105 | SET_BIT (blocks, rgn_bb_table[RGN_BLOCKS (rgn)]); | |
7106 | RESET_BIT (large_region_blocks, rgn_bb_table[RGN_BLOCKS (rgn)]); | |
7107 | ||
7108 | update_life_info (blocks, UPDATE_LIFE_LOCAL, | |
7109 | PROP_DEATH_NOTES | PROP_REG_INFO); | |
7110 | ||
7111 | /* In the single block case, the count of registers that died should | |
7112 | not have changed during the schedule. */ | |
7113 | if (count_or_remove_death_notes (blocks, 0) != deaths_in_region[rgn]) | |
7114 | abort (); | |
7115 | } | |
7116 | ||
7117 | if (any_large_regions) | |
7118 | { | |
7119 | update_life_info (large_region_blocks, UPDATE_LIFE_GLOBAL, | |
7120 | PROP_DEATH_NOTES | PROP_REG_INFO); | |
7121 | } | |
7122 | ||
8c660648 JL |
7123 | /* Reposition the prologue and epilogue notes in case we moved the |
7124 | prologue/epilogue insns. */ | |
7125 | if (reload_completed) | |
7126 | reposition_prologue_and_epilogue_notes (get_insns ()); | |
7127 | ||
63de6c74 | 7128 | /* Delete redundant line notes. */ |
8c660648 JL |
7129 | if (write_symbols != NO_DEBUG) |
7130 | rm_redundant_line_notes (); | |
7131 | ||
8c660648 JL |
7132 | if (sched_verbose) |
7133 | { | |
7134 | if (reload_completed == 0 && flag_schedule_interblock) | |
7135 | { | |
7136 | fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n", | |
7137 | nr_inter, nr_spec); | |
7138 | } | |
7139 | else | |
7140 | { | |
7141 | if (nr_inter > 0) | |
7142 | abort (); | |
7143 | } | |
7144 | fprintf (dump, "\n\n"); | |
7145 | } | |
f187056f | 7146 | |
e05e2395 MM |
7147 | /* Clean up. */ |
7148 | end_alias_analysis (); | |
7149 | ||
aae0390e JL |
7150 | if (true_dependency_cache) |
7151 | { | |
7152 | free (true_dependency_cache); | |
60588660 | 7153 | true_dependency_cache = NULL; |
aae0390e | 7154 | } |
98903742 MM |
7155 | free (rgn_table); |
7156 | free (rgn_bb_table); | |
7157 | free (block_to_bb); | |
7158 | free (containing_rgn); | |
f66d83e1 RH |
7159 | |
7160 | free (h_i_d); | |
7c74b010 JW |
7161 | |
7162 | if (write_symbols != NO_DEBUG) | |
f66d83e1 | 7163 | free (line_note_head); |
7c74b010 | 7164 | |
168cbdf9 JL |
7165 | if (edge_table) |
7166 | { | |
7167 | free (edge_table); | |
7168 | edge_table = NULL; | |
7169 | } | |
7170 | ||
7171 | if (in_edges) | |
7172 | { | |
7173 | free (in_edges); | |
7174 | in_edges = NULL; | |
7175 | } | |
7176 | if (out_edges) | |
7177 | { | |
7178 | free (out_edges); | |
7179 | out_edges = NULL; | |
7180 | } | |
49c3bb12 RH |
7181 | |
7182 | sbitmap_free (blocks); | |
7183 | sbitmap_free (large_region_blocks); | |
98903742 MM |
7184 | |
7185 | free (deaths_in_region); | |
8c660648 | 7186 | } |
98903742 | 7187 | |
8c660648 | 7188 | #endif /* INSN_SCHEDULING */ |